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rtl-llm
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chisel-verilog-pairs

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Generate the Verilog code corresponding to this FIRRTL code module RoundRawFNToRecFN_e11_s53_1 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} inst roundAnyRawFNToRecFN of RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_1 connect roundAnyRawFNToRecFN.io.invalidExc, io.invalidExc connect roundAnyRawFNToRecFN.io.infiniteExc, io.infiniteExc connect roundAnyRawFNToRecFN.io.in.sig, io.in.sig connect roundAnyRawFNToRecFN.io.in.sExp, io.in.sExp connect roundAnyRawFNToRecFN.io.in.sign, io.in.sign connect roundAnyRawFNToRecFN.io.in.isZero, io.in.isZero connect roundAnyRawFNToRecFN.io.in.isInf, io.in.isInf connect roundAnyRawFNToRecFN.io.in.isNaN, io.in.isNaN connect roundAnyRawFNToRecFN.io.roundingMode, io.roundingMode connect roundAnyRawFNToRecFN.io.detectTininess, io.detectTininess connect io.out, roundAnyRawFNToRecFN.io.out connect io.exceptionFlags, roundAnyRawFNToRecFN.io.exceptionFlags
module RoundRawFNToRecFN_e11_s53_1( // @[RoundAnyRawFNToRecFN.scala:295:5] input io_invalidExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_infiniteExc, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isNaN, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isInf, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:299:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:299:16] input [12:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:299:16] input [55:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:299:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:299:16] output [64:0] io_out, // @[RoundAnyRawFNToRecFN.scala:299:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:299:16] ); wire io_invalidExc_0 = io_invalidExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_infiniteExc_0 = io_infiniteExc; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isNaN_0 = io_in_isNaN; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isInf_0 = io_in_isInf; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [12:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [55:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:295:5] wire io_detectTininess = 1'h0; // @[RoundAnyRawFNToRecFN.scala:295:5, :299:16, :310:15] wire [64:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] RoundAnyRawFNToRecFN_ie11_is55_oe11_os53_1 roundAnyRawFNToRecFN ( // @[RoundAnyRawFNToRecFN.scala:310:15] .io_invalidExc (io_invalidExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_infiniteExc (io_infiniteExc_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isNaN (io_in_isNaN_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isInf (io_in_isInf_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_isZero (io_in_isZero_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sign (io_in_sign_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sExp (io_in_sExp_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_in_sig (io_in_sig_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_roundingMode (io_roundingMode_0), // @[RoundAnyRawFNToRecFN.scala:295:5] .io_out (io_out_0), .io_exceptionFlags (io_exceptionFlags_0) ); // @[RoundAnyRawFNToRecFN.scala:310:15] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:295:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:295:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module IssueSlot_83 : input clock : Clock input reset : Reset output io : { valid : UInt<1>, will_be_valid : UInt<1>, request : UInt<1>, request_hp : UInt<1>, flip grant : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip kill : UInt<1>, flip clear : UInt<1>, flip ldspec_miss : UInt<1>, flip wakeup_ports : { valid : UInt<1>, bits : { pdst : UInt<7>, poisoned : UInt<1>}}[2], flip pred_wakeup_port : { valid : UInt<1>, bits : UInt<5>}, flip spec_ld_wakeup : { valid : UInt<1>, bits : UInt<7>}[1], flip in_uop : { valid : UInt<1>, bits : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}}, out_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, debug : { p1 : UInt<1>, p2 : UInt<1>, p3 : UInt<1>, ppred : UInt<1>, state : UInt<2>}} wire next_state : UInt wire next_uopc : UInt wire next_lrs1_rtype : UInt wire next_lrs2_rtype : UInt regreset state : UInt<2>, clock, reset, UInt<2>(0h0) regreset p1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2 : UInt<1>, clock, reset, UInt<1>(0h0) regreset p3 : UInt<1>, clock, reset, UInt<1>(0h0) regreset ppred : UInt<1>, clock, reset, UInt<1>(0h0) regreset p1_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) regreset p2_poisoned : UInt<1>, clock, reset, UInt<1>(0h0) connect p1_poisoned, UInt<1>(0h0) connect p2_poisoned, UInt<1>(0h0) node next_p1_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p1_poisoned, p1_poisoned) node next_p2_poisoned = mux(io.in_uop.valid, io.in_uop.bits.iw_p2_poisoned, p2_poisoned) wire slot_uop_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>} invalidate slot_uop_uop.debug_tsrc invalidate slot_uop_uop.debug_fsrc invalidate slot_uop_uop.bp_xcpt_if invalidate slot_uop_uop.bp_debug_if invalidate slot_uop_uop.xcpt_ma_if invalidate slot_uop_uop.xcpt_ae_if invalidate slot_uop_uop.xcpt_pf_if invalidate slot_uop_uop.fp_single invalidate slot_uop_uop.fp_val invalidate slot_uop_uop.frs3_en invalidate slot_uop_uop.lrs2_rtype invalidate slot_uop_uop.lrs1_rtype invalidate slot_uop_uop.dst_rtype invalidate slot_uop_uop.ldst_val invalidate slot_uop_uop.lrs3 invalidate slot_uop_uop.lrs2 invalidate slot_uop_uop.lrs1 invalidate slot_uop_uop.ldst invalidate slot_uop_uop.ldst_is_rs1 invalidate slot_uop_uop.flush_on_commit invalidate slot_uop_uop.is_unique invalidate slot_uop_uop.is_sys_pc2epc invalidate slot_uop_uop.uses_stq invalidate slot_uop_uop.uses_ldq invalidate slot_uop_uop.is_amo invalidate slot_uop_uop.is_fencei invalidate slot_uop_uop.is_fence invalidate slot_uop_uop.mem_signed invalidate slot_uop_uop.mem_size invalidate slot_uop_uop.mem_cmd invalidate slot_uop_uop.bypassable invalidate slot_uop_uop.exc_cause invalidate slot_uop_uop.exception invalidate slot_uop_uop.stale_pdst invalidate slot_uop_uop.ppred_busy invalidate slot_uop_uop.prs3_busy invalidate slot_uop_uop.prs2_busy invalidate slot_uop_uop.prs1_busy invalidate slot_uop_uop.ppred invalidate slot_uop_uop.prs3 invalidate slot_uop_uop.prs2 invalidate slot_uop_uop.prs1 invalidate slot_uop_uop.pdst invalidate slot_uop_uop.rxq_idx invalidate slot_uop_uop.stq_idx invalidate slot_uop_uop.ldq_idx invalidate slot_uop_uop.rob_idx invalidate slot_uop_uop.csr_addr invalidate slot_uop_uop.imm_packed invalidate slot_uop_uop.taken invalidate slot_uop_uop.pc_lob invalidate slot_uop_uop.edge_inst invalidate slot_uop_uop.ftq_idx invalidate slot_uop_uop.br_tag invalidate slot_uop_uop.br_mask invalidate slot_uop_uop.is_sfb invalidate slot_uop_uop.is_jal invalidate slot_uop_uop.is_jalr invalidate slot_uop_uop.is_br invalidate slot_uop_uop.iw_p2_poisoned invalidate slot_uop_uop.iw_p1_poisoned invalidate slot_uop_uop.iw_state invalidate slot_uop_uop.ctrl.is_std invalidate slot_uop_uop.ctrl.is_sta invalidate slot_uop_uop.ctrl.is_load invalidate slot_uop_uop.ctrl.csr_cmd invalidate slot_uop_uop.ctrl.fcn_dw invalidate slot_uop_uop.ctrl.op_fcn invalidate slot_uop_uop.ctrl.imm_sel invalidate slot_uop_uop.ctrl.op2_sel invalidate slot_uop_uop.ctrl.op1_sel invalidate slot_uop_uop.ctrl.br_type invalidate slot_uop_uop.fu_code invalidate slot_uop_uop.iq_type invalidate slot_uop_uop.debug_pc invalidate slot_uop_uop.is_rvc invalidate slot_uop_uop.debug_inst invalidate slot_uop_uop.inst invalidate slot_uop_uop.uopc connect slot_uop_uop.uopc, UInt<7>(0h0) connect slot_uop_uop.bypassable, UInt<1>(0h0) connect slot_uop_uop.fp_val, UInt<1>(0h0) connect slot_uop_uop.uses_stq, UInt<1>(0h0) connect slot_uop_uop.uses_ldq, UInt<1>(0h0) connect slot_uop_uop.pdst, UInt<1>(0h0) connect slot_uop_uop.dst_rtype, UInt<2>(0h2) wire slot_uop_cs : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>} invalidate slot_uop_cs.is_std invalidate slot_uop_cs.is_sta invalidate slot_uop_cs.is_load invalidate slot_uop_cs.csr_cmd invalidate slot_uop_cs.fcn_dw invalidate slot_uop_cs.op_fcn invalidate slot_uop_cs.imm_sel invalidate slot_uop_cs.op2_sel invalidate slot_uop_cs.op1_sel invalidate slot_uop_cs.br_type connect slot_uop_cs.br_type, UInt<4>(0h0) connect slot_uop_cs.csr_cmd, UInt<3>(0h0) connect slot_uop_cs.is_load, UInt<1>(0h0) connect slot_uop_cs.is_sta, UInt<1>(0h0) connect slot_uop_cs.is_std, UInt<1>(0h0) connect slot_uop_uop.ctrl, slot_uop_cs regreset slot_uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, clock, reset, slot_uop_uop node next_uop = mux(io.in_uop.valid, io.in_uop.bits, slot_uop) when io.kill : connect state, UInt<2>(0h0) else : when io.in_uop.valid : connect state, io.in_uop.bits.iw_state else : when io.clear : connect state, UInt<2>(0h0) else : connect state, next_state connect next_state, state connect next_uopc, slot_uop.uopc connect next_lrs1_rtype, slot_uop.lrs1_rtype connect next_lrs2_rtype, slot_uop.lrs2_rtype when io.kill : connect next_state, UInt<2>(0h0) else : node _T = eq(state, UInt<2>(0h1)) node _T_1 = and(io.grant, _T) node _T_2 = eq(state, UInt<2>(0h2)) node _T_3 = and(io.grant, _T_2) node _T_4 = and(_T_3, p1) node _T_5 = and(_T_4, p2) node _T_6 = and(_T_5, ppred) node _T_7 = or(_T_1, _T_6) when _T_7 : node _T_8 = or(p1_poisoned, p2_poisoned) node _T_9 = and(io.ldspec_miss, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : connect next_state, UInt<2>(0h0) else : node _T_11 = eq(state, UInt<2>(0h2)) node _T_12 = and(io.grant, _T_11) when _T_12 : node _T_13 = or(p1_poisoned, p2_poisoned) node _T_14 = and(io.ldspec_miss, _T_13) node _T_15 = eq(_T_14, UInt<1>(0h0)) when _T_15 : connect next_state, UInt<2>(0h1) when p1 : connect slot_uop.uopc, UInt<7>(0h3) connect next_uopc, UInt<7>(0h3) connect slot_uop.lrs1_rtype, UInt<2>(0h2) connect next_lrs1_rtype, UInt<2>(0h2) else : connect slot_uop.lrs2_rtype, UInt<2>(0h2) connect next_lrs2_rtype, UInt<2>(0h2) when io.in_uop.valid : connect slot_uop, io.in_uop.bits node _T_16 = eq(state, UInt<2>(0h0)) node _T_17 = or(_T_16, io.clear) node _T_18 = or(_T_17, io.kill) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed: trying to overwrite a valid issue slot.\n at issue-slot.scala:156 assert (is_invalid || io.clear || io.kill, \"trying to overwrite a valid issue slot.\")\n") : printf assert(clock, _T_18, UInt<1>(0h1), "") : assert wire next_p1 : UInt<1> connect next_p1, p1 wire next_p2 : UInt<1> connect next_p2, p2 wire next_p3 : UInt<1> connect next_p3, p3 wire next_ppred : UInt<1> connect next_ppred, ppred when io.in_uop.valid : node _p1_T = eq(io.in_uop.bits.prs1_busy, UInt<1>(0h0)) connect p1, _p1_T node _p2_T = eq(io.in_uop.bits.prs2_busy, UInt<1>(0h0)) connect p2, _p2_T node _p3_T = eq(io.in_uop.bits.prs3_busy, UInt<1>(0h0)) connect p3, _p3_T node _ppred_T = eq(io.in_uop.bits.ppred_busy, UInt<1>(0h0)) connect ppred, _ppred_T node _T_22 = and(io.ldspec_miss, next_p1_poisoned) when _T_22 : node _T_23 = neq(next_uop.prs1, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs1=x0!\n at issue-slot.scala:176 assert(next_uop.prs1 =/= 0.U, \"Poison bit can't be set for prs1=x0!\")\n") : printf_1 assert(clock, _T_23, UInt<1>(0h1), "") : assert_1 connect p1, UInt<1>(0h0) node _T_27 = and(io.ldspec_miss, next_p2_poisoned) when _T_27 : node _T_28 = neq(next_uop.prs2, UInt<1>(0h0)) node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : node _T_31 = eq(_T_28, UInt<1>(0h0)) when _T_31 : printf(clock, UInt<1>(0h1), "Assertion failed: Poison bit can't be set for prs2=x0!\n at issue-slot.scala:180 assert(next_uop.prs2 =/= 0.U, \"Poison bit can't be set for prs2=x0!\")\n") : printf_2 assert(clock, _T_28, UInt<1>(0h1), "") : assert_2 connect p2, UInt<1>(0h0) node _T_32 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs1) node _T_33 = and(io.wakeup_ports[0].valid, _T_32) when _T_33 : connect p1, UInt<1>(0h1) node _T_34 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs2) node _T_35 = and(io.wakeup_ports[0].valid, _T_34) when _T_35 : connect p2, UInt<1>(0h1) node _T_36 = eq(io.wakeup_ports[0].bits.pdst, next_uop.prs3) node _T_37 = and(io.wakeup_ports[0].valid, _T_36) when _T_37 : connect p3, UInt<1>(0h1) node _T_38 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs1) node _T_39 = and(io.wakeup_ports[1].valid, _T_38) when _T_39 : connect p1, UInt<1>(0h1) node _T_40 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs2) node _T_41 = and(io.wakeup_ports[1].valid, _T_40) when _T_41 : connect p2, UInt<1>(0h1) node _T_42 = eq(io.wakeup_ports[1].bits.pdst, next_uop.prs3) node _T_43 = and(io.wakeup_ports[1].valid, _T_42) when _T_43 : connect p3, UInt<1>(0h1) node _T_44 = eq(io.pred_wakeup_port.bits, next_uop.ppred) node _T_45 = and(io.pred_wakeup_port.valid, _T_44) when _T_45 : connect ppred, UInt<1>(0h1) node _T_46 = eq(io.spec_ld_wakeup[0].bits, UInt<1>(0h0)) node _T_47 = and(io.spec_ld_wakeup[0].valid, _T_46) node _T_48 = eq(_T_47, UInt<1>(0h0)) node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_T_48, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: Loads to x0 should never speculatively wakeup other instructions\n at issue-slot.scala:203 assert (!(io.spec_ld_wakeup(w).valid && io.spec_ld_wakeup(w).bits === 0.U),\n") : printf_3 assert(clock, _T_48, UInt<1>(0h1), "") : assert_3 node _T_52 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs1) node _T_53 = and(io.spec_ld_wakeup[0].valid, _T_52) node _T_54 = eq(next_uop.lrs1_rtype, UInt<2>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect p1, UInt<1>(0h1) connect p1_poisoned, UInt<1>(0h1) node _T_56 = eq(next_p1_poisoned, UInt<1>(0h0)) node _T_57 = asUInt(reset) node _T_58 = eq(_T_57, UInt<1>(0h0)) when _T_58 : node _T_59 = eq(_T_56, UInt<1>(0h0)) when _T_59 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:214 assert (!next_p1_poisoned)\n") : printf_4 assert(clock, _T_56, UInt<1>(0h1), "") : assert_4 node _T_60 = eq(io.spec_ld_wakeup[0].bits, next_uop.prs2) node _T_61 = and(io.spec_ld_wakeup[0].valid, _T_60) node _T_62 = eq(next_uop.lrs2_rtype, UInt<2>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect p2, UInt<1>(0h1) connect p2_poisoned, UInt<1>(0h1) node _T_64 = eq(next_p2_poisoned, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at issue-slot.scala:221 assert (!next_p2_poisoned)\n") : printf_5 assert(clock, _T_64, UInt<1>(0h1), "") : assert_5 node _next_br_mask_T = not(io.brupdate.b1.resolve_mask) node next_br_mask = and(slot_uop.br_mask, _next_br_mask_T) node _T_68 = and(io.brupdate.b1.mispredict_mask, slot_uop.br_mask) node _T_69 = neq(_T_68, UInt<1>(0h0)) when _T_69 : connect next_state, UInt<2>(0h0) node _T_70 = eq(io.in_uop.valid, UInt<1>(0h0)) when _T_70 : connect slot_uop.br_mask, next_br_mask node _io_request_T = neq(state, UInt<2>(0h0)) node _io_request_T_1 = and(_io_request_T, p1) node _io_request_T_2 = and(_io_request_T_1, p2) node _io_request_T_3 = and(_io_request_T_2, p3) node _io_request_T_4 = and(_io_request_T_3, ppred) node _io_request_T_5 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_6 = and(_io_request_T_4, _io_request_T_5) connect io.request, _io_request_T_6 node _high_priority_T = or(slot_uop.is_br, slot_uop.is_jal) node high_priority = or(_high_priority_T, slot_uop.is_jalr) node _io_request_hp_T = and(io.request, high_priority) connect io.request_hp, _io_request_hp_T node _T_71 = eq(state, UInt<2>(0h1)) when _T_71 : node _io_request_T_7 = and(p1, p2) node _io_request_T_8 = and(_io_request_T_7, p3) node _io_request_T_9 = and(_io_request_T_8, ppred) node _io_request_T_10 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_11 = and(_io_request_T_9, _io_request_T_10) connect io.request, _io_request_T_11 else : node _T_72 = eq(state, UInt<2>(0h2)) when _T_72 : node _io_request_T_12 = or(p1, p2) node _io_request_T_13 = and(_io_request_T_12, ppred) node _io_request_T_14 = eq(io.kill, UInt<1>(0h0)) node _io_request_T_15 = and(_io_request_T_13, _io_request_T_14) connect io.request, _io_request_T_15 else : connect io.request, UInt<1>(0h0) node _io_valid_T = neq(state, UInt<2>(0h0)) connect io.valid, _io_valid_T connect io.uop, slot_uop connect io.uop.iw_p1_poisoned, p1_poisoned connect io.uop.iw_p2_poisoned, p2_poisoned node _may_vacate_T = eq(state, UInt<2>(0h1)) node _may_vacate_T_1 = eq(state, UInt<2>(0h2)) node _may_vacate_T_2 = and(_may_vacate_T_1, p1) node _may_vacate_T_3 = and(_may_vacate_T_2, p2) node _may_vacate_T_4 = and(_may_vacate_T_3, ppred) node _may_vacate_T_5 = or(_may_vacate_T, _may_vacate_T_4) node may_vacate = and(io.grant, _may_vacate_T_5) node _squash_grant_T = or(p1_poisoned, p2_poisoned) node squash_grant = and(io.ldspec_miss, _squash_grant_T) node _io_will_be_valid_T = neq(state, UInt<2>(0h0)) node _io_will_be_valid_T_1 = eq(squash_grant, UInt<1>(0h0)) node _io_will_be_valid_T_2 = and(may_vacate, _io_will_be_valid_T_1) node _io_will_be_valid_T_3 = eq(_io_will_be_valid_T_2, UInt<1>(0h0)) node _io_will_be_valid_T_4 = and(_io_will_be_valid_T, _io_will_be_valid_T_3) connect io.will_be_valid, _io_will_be_valid_T_4 connect io.out_uop, slot_uop connect io.out_uop.iw_state, next_state connect io.out_uop.uopc, next_uopc connect io.out_uop.lrs1_rtype, next_lrs1_rtype connect io.out_uop.lrs2_rtype, next_lrs2_rtype connect io.out_uop.br_mask, next_br_mask node _io_out_uop_prs1_busy_T = eq(p1, UInt<1>(0h0)) connect io.out_uop.prs1_busy, _io_out_uop_prs1_busy_T node _io_out_uop_prs2_busy_T = eq(p2, UInt<1>(0h0)) connect io.out_uop.prs2_busy, _io_out_uop_prs2_busy_T node _io_out_uop_prs3_busy_T = eq(p3, UInt<1>(0h0)) connect io.out_uop.prs3_busy, _io_out_uop_prs3_busy_T node _io_out_uop_ppred_busy_T = eq(ppred, UInt<1>(0h0)) connect io.out_uop.ppred_busy, _io_out_uop_ppred_busy_T connect io.out_uop.iw_p1_poisoned, p1_poisoned connect io.out_uop.iw_p2_poisoned, p2_poisoned node _T_73 = eq(state, UInt<2>(0h2)) when _T_73 : node _T_74 = and(p1, p2) node _T_75 = and(_T_74, ppred) when _T_75 : skip else : node _T_76 = and(p1, ppred) when _T_76 : connect io.uop.uopc, slot_uop.uopc connect io.uop.lrs2_rtype, UInt<2>(0h2) else : node _T_77 = and(p2, ppred) when _T_77 : connect io.uop.uopc, UInt<7>(0h3) connect io.uop.lrs1_rtype, UInt<2>(0h2) connect io.debug.p1, p1 connect io.debug.p2, p2 connect io.debug.p3, p3 connect io.debug.ppred, ppred connect io.debug.state, state
module IssueSlot_83( // @[issue-slot.scala:69:7] input clock, // @[issue-slot.scala:69:7] input reset, // @[issue-slot.scala:69:7] output io_valid, // @[issue-slot.scala:73:14] output io_will_be_valid, // @[issue-slot.scala:73:14] output io_request, // @[issue-slot.scala:73:14] output io_request_hp, // @[issue-slot.scala:73:14] input io_grant, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_resolve_mask, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_uopc, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_inst, // @[issue-slot.scala:73:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_load, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_br, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jalr, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_jal, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_taken, // @[issue-slot.scala:73:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_pdst, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs1, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs2, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_prs3, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_ppred, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs1_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs2_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_prs3_busy, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_exception, // @[issue-slot.scala:73:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_mem_signed, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fence, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_fencei, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_amo, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_ldq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_uses_stq, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_is_unique, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_flush_on_commit, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_ldst, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_frs3_en, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_val, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_fp_single, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_debug_if, // @[issue-slot.scala:73:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[issue-slot.scala:73:14] input io_brupdate_b2_valid, // @[issue-slot.scala:73:14] input io_brupdate_b2_mispredict, // @[issue-slot.scala:73:14] input io_brupdate_b2_taken, // @[issue-slot.scala:73:14] input [2:0] io_brupdate_b2_cfi_type, // @[issue-slot.scala:73:14] input [1:0] io_brupdate_b2_pc_sel, // @[issue-slot.scala:73:14] input [39:0] io_brupdate_b2_jalr_target, // @[issue-slot.scala:73:14] input [20:0] io_brupdate_b2_target_offset, // @[issue-slot.scala:73:14] input io_kill, // @[issue-slot.scala:73:14] input io_clear, // @[issue-slot.scala:73:14] input io_wakeup_ports_0_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_0_bits_pdst, // @[issue-slot.scala:73:14] input io_wakeup_ports_1_valid, // @[issue-slot.scala:73:14] input [6:0] io_wakeup_ports_1_bits_pdst, // @[issue-slot.scala:73:14] input io_in_uop_valid, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_uopc, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_inst, // @[issue-slot.scala:73:14] input [31:0] io_in_uop_bits_debug_inst, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_rvc, // @[issue-slot.scala:73:14] input [39:0] io_in_uop_bits_debug_pc, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_iq_type, // @[issue-slot.scala:73:14] input [9:0] io_in_uop_bits_fu_code, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_ctrl_br_type, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_ctrl_op1_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_op2_sel, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_imm_sel, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ctrl_op_fcn, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_fcn_dw, // @[issue-slot.scala:73:14] input [2:0] io_in_uop_bits_ctrl_csr_cmd, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_load, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_sta, // @[issue-slot.scala:73:14] input io_in_uop_bits_ctrl_is_std, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_iw_state, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_br, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jalr, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_jal, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sfb, // @[issue-slot.scala:73:14] input [15:0] io_in_uop_bits_br_mask, // @[issue-slot.scala:73:14] input [3:0] io_in_uop_bits_br_tag, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ftq_idx, // @[issue-slot.scala:73:14] input io_in_uop_bits_edge_inst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_pc_lob, // @[issue-slot.scala:73:14] input io_in_uop_bits_taken, // @[issue-slot.scala:73:14] input [19:0] io_in_uop_bits_imm_packed, // @[issue-slot.scala:73:14] input [11:0] io_in_uop_bits_csr_addr, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_rob_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ldq_idx, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_stq_idx, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_rxq_idx, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_pdst, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs1, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs2, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_prs3, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_ppred, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs1_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs2_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_prs3_busy, // @[issue-slot.scala:73:14] input io_in_uop_bits_ppred_busy, // @[issue-slot.scala:73:14] input [6:0] io_in_uop_bits_stale_pdst, // @[issue-slot.scala:73:14] input io_in_uop_bits_exception, // @[issue-slot.scala:73:14] input [63:0] io_in_uop_bits_exc_cause, // @[issue-slot.scala:73:14] input io_in_uop_bits_bypassable, // @[issue-slot.scala:73:14] input [4:0] io_in_uop_bits_mem_cmd, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_mem_size, // @[issue-slot.scala:73:14] input io_in_uop_bits_mem_signed, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fence, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_fencei, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_amo, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_ldq, // @[issue-slot.scala:73:14] input io_in_uop_bits_uses_stq, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_sys_pc2epc, // @[issue-slot.scala:73:14] input io_in_uop_bits_is_unique, // @[issue-slot.scala:73:14] input io_in_uop_bits_flush_on_commit, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_is_rs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_ldst, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs1, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs2, // @[issue-slot.scala:73:14] input [5:0] io_in_uop_bits_lrs3, // @[issue-slot.scala:73:14] input io_in_uop_bits_ldst_val, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_dst_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs1_rtype, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_lrs2_rtype, // @[issue-slot.scala:73:14] input io_in_uop_bits_frs3_en, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_val, // @[issue-slot.scala:73:14] input io_in_uop_bits_fp_single, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_pf_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ae_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_xcpt_ma_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_debug_if, // @[issue-slot.scala:73:14] input io_in_uop_bits_bp_xcpt_if, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_fsrc, // @[issue-slot.scala:73:14] input [1:0] io_in_uop_bits_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_out_uop_debug_inst, // @[issue-slot.scala:73:14] output io_out_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_out_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_out_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_out_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_out_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_iw_state, // @[issue-slot.scala:73:14] output io_out_uop_is_br, // @[issue-slot.scala:73:14] output io_out_uop_is_jalr, // @[issue-slot.scala:73:14] output io_out_uop_is_jal, // @[issue-slot.scala:73:14] output io_out_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_out_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_out_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_out_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_pc_lob, // @[issue-slot.scala:73:14] output io_out_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_out_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_out_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_ppred, // @[issue-slot.scala:73:14] output io_out_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_out_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_out_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_out_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_out_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_out_uop_exc_cause, // @[issue-slot.scala:73:14] output io_out_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_out_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_mem_size, // @[issue-slot.scala:73:14] output io_out_uop_mem_signed, // @[issue-slot.scala:73:14] output io_out_uop_is_fence, // @[issue-slot.scala:73:14] output io_out_uop_is_fencei, // @[issue-slot.scala:73:14] output io_out_uop_is_amo, // @[issue-slot.scala:73:14] output io_out_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_out_uop_uses_stq, // @[issue-slot.scala:73:14] output io_out_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_out_uop_is_unique, // @[issue-slot.scala:73:14] output io_out_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_out_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_out_uop_lrs3, // @[issue-slot.scala:73:14] output io_out_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_out_uop_frs3_en, // @[issue-slot.scala:73:14] output io_out_uop_fp_val, // @[issue-slot.scala:73:14] output io_out_uop_fp_single, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_out_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_out_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_out_uop_debug_tsrc, // @[issue-slot.scala:73:14] output [6:0] io_uop_uopc, // @[issue-slot.scala:73:14] output [31:0] io_uop_inst, // @[issue-slot.scala:73:14] output [31:0] io_uop_debug_inst, // @[issue-slot.scala:73:14] output io_uop_is_rvc, // @[issue-slot.scala:73:14] output [39:0] io_uop_debug_pc, // @[issue-slot.scala:73:14] output [2:0] io_uop_iq_type, // @[issue-slot.scala:73:14] output [9:0] io_uop_fu_code, // @[issue-slot.scala:73:14] output [3:0] io_uop_ctrl_br_type, // @[issue-slot.scala:73:14] output [1:0] io_uop_ctrl_op1_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_op2_sel, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_imm_sel, // @[issue-slot.scala:73:14] output [4:0] io_uop_ctrl_op_fcn, // @[issue-slot.scala:73:14] output io_uop_ctrl_fcn_dw, // @[issue-slot.scala:73:14] output [2:0] io_uop_ctrl_csr_cmd, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_load, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_sta, // @[issue-slot.scala:73:14] output io_uop_ctrl_is_std, // @[issue-slot.scala:73:14] output [1:0] io_uop_iw_state, // @[issue-slot.scala:73:14] output io_uop_is_br, // @[issue-slot.scala:73:14] output io_uop_is_jalr, // @[issue-slot.scala:73:14] output io_uop_is_jal, // @[issue-slot.scala:73:14] output io_uop_is_sfb, // @[issue-slot.scala:73:14] output [15:0] io_uop_br_mask, // @[issue-slot.scala:73:14] output [3:0] io_uop_br_tag, // @[issue-slot.scala:73:14] output [4:0] io_uop_ftq_idx, // @[issue-slot.scala:73:14] output io_uop_edge_inst, // @[issue-slot.scala:73:14] output [5:0] io_uop_pc_lob, // @[issue-slot.scala:73:14] output io_uop_taken, // @[issue-slot.scala:73:14] output [19:0] io_uop_imm_packed, // @[issue-slot.scala:73:14] output [11:0] io_uop_csr_addr, // @[issue-slot.scala:73:14] output [6:0] io_uop_rob_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_ldq_idx, // @[issue-slot.scala:73:14] output [4:0] io_uop_stq_idx, // @[issue-slot.scala:73:14] output [1:0] io_uop_rxq_idx, // @[issue-slot.scala:73:14] output [6:0] io_uop_pdst, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs1, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs2, // @[issue-slot.scala:73:14] output [6:0] io_uop_prs3, // @[issue-slot.scala:73:14] output [4:0] io_uop_ppred, // @[issue-slot.scala:73:14] output io_uop_prs1_busy, // @[issue-slot.scala:73:14] output io_uop_prs2_busy, // @[issue-slot.scala:73:14] output io_uop_prs3_busy, // @[issue-slot.scala:73:14] output io_uop_ppred_busy, // @[issue-slot.scala:73:14] output [6:0] io_uop_stale_pdst, // @[issue-slot.scala:73:14] output io_uop_exception, // @[issue-slot.scala:73:14] output [63:0] io_uop_exc_cause, // @[issue-slot.scala:73:14] output io_uop_bypassable, // @[issue-slot.scala:73:14] output [4:0] io_uop_mem_cmd, // @[issue-slot.scala:73:14] output [1:0] io_uop_mem_size, // @[issue-slot.scala:73:14] output io_uop_mem_signed, // @[issue-slot.scala:73:14] output io_uop_is_fence, // @[issue-slot.scala:73:14] output io_uop_is_fencei, // @[issue-slot.scala:73:14] output io_uop_is_amo, // @[issue-slot.scala:73:14] output io_uop_uses_ldq, // @[issue-slot.scala:73:14] output io_uop_uses_stq, // @[issue-slot.scala:73:14] output io_uop_is_sys_pc2epc, // @[issue-slot.scala:73:14] output io_uop_is_unique, // @[issue-slot.scala:73:14] output io_uop_flush_on_commit, // @[issue-slot.scala:73:14] output io_uop_ldst_is_rs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_ldst, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs1, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs2, // @[issue-slot.scala:73:14] output [5:0] io_uop_lrs3, // @[issue-slot.scala:73:14] output io_uop_ldst_val, // @[issue-slot.scala:73:14] output [1:0] io_uop_dst_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs1_rtype, // @[issue-slot.scala:73:14] output [1:0] io_uop_lrs2_rtype, // @[issue-slot.scala:73:14] output io_uop_frs3_en, // @[issue-slot.scala:73:14] output io_uop_fp_val, // @[issue-slot.scala:73:14] output io_uop_fp_single, // @[issue-slot.scala:73:14] output io_uop_xcpt_pf_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ae_if, // @[issue-slot.scala:73:14] output io_uop_xcpt_ma_if, // @[issue-slot.scala:73:14] output io_uop_bp_debug_if, // @[issue-slot.scala:73:14] output io_uop_bp_xcpt_if, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_fsrc, // @[issue-slot.scala:73:14] output [1:0] io_uop_debug_tsrc, // @[issue-slot.scala:73:14] output io_debug_p1, // @[issue-slot.scala:73:14] output io_debug_p2, // @[issue-slot.scala:73:14] output io_debug_p3, // @[issue-slot.scala:73:14] output io_debug_ppred, // @[issue-slot.scala:73:14] output [1:0] io_debug_state // @[issue-slot.scala:73:14] ); wire io_grant_0 = io_grant; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[issue-slot.scala:69:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[issue-slot.scala:69:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[issue-slot.scala:69:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[issue-slot.scala:69:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[issue-slot.scala:69:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[issue-slot.scala:69:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[issue-slot.scala:69:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[issue-slot.scala:69:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[issue-slot.scala:69:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[issue-slot.scala:69:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[issue-slot.scala:69:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[issue-slot.scala:69:7] wire io_kill_0 = io_kill; // @[issue-slot.scala:69:7] wire io_clear_0 = io_clear; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_valid_0 = io_wakeup_ports_0_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_0_bits_pdst_0 = io_wakeup_ports_0_bits_pdst; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_valid_0 = io_wakeup_ports_1_valid; // @[issue-slot.scala:69:7] wire [6:0] io_wakeup_ports_1_bits_pdst_0 = io_wakeup_ports_1_bits_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_valid_0 = io_in_uop_valid; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_uopc_0 = io_in_uop_bits_uopc; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_inst_0 = io_in_uop_bits_inst; // @[issue-slot.scala:69:7] wire [31:0] io_in_uop_bits_debug_inst_0 = io_in_uop_bits_debug_inst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_rvc_0 = io_in_uop_bits_is_rvc; // @[issue-slot.scala:69:7] wire [39:0] io_in_uop_bits_debug_pc_0 = io_in_uop_bits_debug_pc; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_iq_type_0 = io_in_uop_bits_iq_type; // @[issue-slot.scala:69:7] wire [9:0] io_in_uop_bits_fu_code_0 = io_in_uop_bits_fu_code; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_ctrl_br_type_0 = io_in_uop_bits_ctrl_br_type; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_ctrl_op1_sel_0 = io_in_uop_bits_ctrl_op1_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_op2_sel_0 = io_in_uop_bits_ctrl_op2_sel; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_imm_sel_0 = io_in_uop_bits_ctrl_imm_sel; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ctrl_op_fcn_0 = io_in_uop_bits_ctrl_op_fcn; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_fcn_dw_0 = io_in_uop_bits_ctrl_fcn_dw; // @[issue-slot.scala:69:7] wire [2:0] io_in_uop_bits_ctrl_csr_cmd_0 = io_in_uop_bits_ctrl_csr_cmd; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_load_0 = io_in_uop_bits_ctrl_is_load; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_sta_0 = io_in_uop_bits_ctrl_is_sta; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ctrl_is_std_0 = io_in_uop_bits_ctrl_is_std; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_iw_state_0 = io_in_uop_bits_iw_state; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_br_0 = io_in_uop_bits_is_br; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jalr_0 = io_in_uop_bits_is_jalr; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_jal_0 = io_in_uop_bits_is_jal; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sfb_0 = io_in_uop_bits_is_sfb; // @[issue-slot.scala:69:7] wire [15:0] io_in_uop_bits_br_mask_0 = io_in_uop_bits_br_mask; // @[issue-slot.scala:69:7] wire [3:0] io_in_uop_bits_br_tag_0 = io_in_uop_bits_br_tag; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ftq_idx_0 = io_in_uop_bits_ftq_idx; // @[issue-slot.scala:69:7] wire io_in_uop_bits_edge_inst_0 = io_in_uop_bits_edge_inst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_pc_lob_0 = io_in_uop_bits_pc_lob; // @[issue-slot.scala:69:7] wire io_in_uop_bits_taken_0 = io_in_uop_bits_taken; // @[issue-slot.scala:69:7] wire [19:0] io_in_uop_bits_imm_packed_0 = io_in_uop_bits_imm_packed; // @[issue-slot.scala:69:7] wire [11:0] io_in_uop_bits_csr_addr_0 = io_in_uop_bits_csr_addr; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_rob_idx_0 = io_in_uop_bits_rob_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ldq_idx_0 = io_in_uop_bits_ldq_idx; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_stq_idx_0 = io_in_uop_bits_stq_idx; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_rxq_idx_0 = io_in_uop_bits_rxq_idx; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_pdst_0 = io_in_uop_bits_pdst; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs1_0 = io_in_uop_bits_prs1; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs2_0 = io_in_uop_bits_prs2; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_prs3_0 = io_in_uop_bits_prs3; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_ppred_0 = io_in_uop_bits_ppred; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs1_busy_0 = io_in_uop_bits_prs1_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs2_busy_0 = io_in_uop_bits_prs2_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_prs3_busy_0 = io_in_uop_bits_prs3_busy; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ppred_busy_0 = io_in_uop_bits_ppred_busy; // @[issue-slot.scala:69:7] wire [6:0] io_in_uop_bits_stale_pdst_0 = io_in_uop_bits_stale_pdst; // @[issue-slot.scala:69:7] wire io_in_uop_bits_exception_0 = io_in_uop_bits_exception; // @[issue-slot.scala:69:7] wire [63:0] io_in_uop_bits_exc_cause_0 = io_in_uop_bits_exc_cause; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bypassable_0 = io_in_uop_bits_bypassable; // @[issue-slot.scala:69:7] wire [4:0] io_in_uop_bits_mem_cmd_0 = io_in_uop_bits_mem_cmd; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_mem_size_0 = io_in_uop_bits_mem_size; // @[issue-slot.scala:69:7] wire io_in_uop_bits_mem_signed_0 = io_in_uop_bits_mem_signed; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fence_0 = io_in_uop_bits_is_fence; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_fencei_0 = io_in_uop_bits_is_fencei; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_amo_0 = io_in_uop_bits_is_amo; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_ldq_0 = io_in_uop_bits_uses_ldq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_uses_stq_0 = io_in_uop_bits_uses_stq; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_sys_pc2epc_0 = io_in_uop_bits_is_sys_pc2epc; // @[issue-slot.scala:69:7] wire io_in_uop_bits_is_unique_0 = io_in_uop_bits_is_unique; // @[issue-slot.scala:69:7] wire io_in_uop_bits_flush_on_commit_0 = io_in_uop_bits_flush_on_commit; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_is_rs1_0 = io_in_uop_bits_ldst_is_rs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_ldst_0 = io_in_uop_bits_ldst; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs1_0 = io_in_uop_bits_lrs1; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs2_0 = io_in_uop_bits_lrs2; // @[issue-slot.scala:69:7] wire [5:0] io_in_uop_bits_lrs3_0 = io_in_uop_bits_lrs3; // @[issue-slot.scala:69:7] wire io_in_uop_bits_ldst_val_0 = io_in_uop_bits_ldst_val; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_dst_rtype_0 = io_in_uop_bits_dst_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs1_rtype_0 = io_in_uop_bits_lrs1_rtype; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_lrs2_rtype_0 = io_in_uop_bits_lrs2_rtype; // @[issue-slot.scala:69:7] wire io_in_uop_bits_frs3_en_0 = io_in_uop_bits_frs3_en; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_val_0 = io_in_uop_bits_fp_val; // @[issue-slot.scala:69:7] wire io_in_uop_bits_fp_single_0 = io_in_uop_bits_fp_single; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_pf_if_0 = io_in_uop_bits_xcpt_pf_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ae_if_0 = io_in_uop_bits_xcpt_ae_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_xcpt_ma_if_0 = io_in_uop_bits_xcpt_ma_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_debug_if_0 = io_in_uop_bits_bp_debug_if; // @[issue-slot.scala:69:7] wire io_in_uop_bits_bp_xcpt_if_0 = io_in_uop_bits_bp_xcpt_if; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_fsrc_0 = io_in_uop_bits_debug_fsrc; // @[issue-slot.scala:69:7] wire [1:0] io_in_uop_bits_debug_tsrc_0 = io_in_uop_bits_debug_tsrc; // @[issue-slot.scala:69:7] wire io_ldspec_miss = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_0_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_wakeup_ports_1_bits_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_pred_wakeup_port_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_spec_ld_wakeup_0_valid = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_in_uop_bits_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_out_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p1_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire io_uop_iw_p2_poisoned = 1'h0; // @[issue-slot.scala:69:7] wire next_p1_poisoned = 1'h0; // @[issue-slot.scala:99:29] wire next_p2_poisoned = 1'h0; // @[issue-slot.scala:100:29] wire slot_uop_uop_is_rvc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_fcn_dw = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_load = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_sta = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ctrl_is_std = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p1_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_iw_p2_poisoned = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_br = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jalr = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_jal = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sfb = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_edge_inst = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_taken = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs1_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs2_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_prs3_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ppred_busy = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_exception = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bypassable = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_mem_signed = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fence = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_fencei = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_amo = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_ldq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_uses_stq = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_sys_pc2epc = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_is_unique = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_flush_on_commit = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_is_rs1 = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_ldst_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_frs3_en = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_val = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_fp_single = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_pf_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ae_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_xcpt_ma_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_debug_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_uop_bp_xcpt_if = 1'h0; // @[consts.scala:269:19] wire slot_uop_cs_fcn_dw = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_load = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_sta = 1'h0; // @[consts.scala:279:18] wire slot_uop_cs_is_std = 1'h0; // @[consts.scala:279:18] wire _squash_grant_T = 1'h0; // @[issue-slot.scala:261:53] wire squash_grant = 1'h0; // @[issue-slot.scala:261:37] wire [4:0] io_pred_wakeup_port_bits = 5'h0; // @[issue-slot.scala:69:7] wire [4:0] slot_uop_uop_ctrl_op_fcn = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ftq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ldq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_stq_idx = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_ppred = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_uop_mem_cmd = 5'h0; // @[consts.scala:269:19] wire [4:0] slot_uop_cs_op_fcn = 5'h0; // @[consts.scala:279:18] wire [6:0] io_spec_ld_wakeup_0_bits = 7'h0; // @[issue-slot.scala:69:7] wire [6:0] slot_uop_uop_uopc = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_rob_idx = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_pdst = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs1 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs2 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_prs3 = 7'h0; // @[consts.scala:269:19] wire [6:0] slot_uop_uop_stale_pdst = 7'h0; // @[consts.scala:269:19] wire _io_will_be_valid_T_1 = 1'h1; // @[issue-slot.scala:262:51] wire [1:0] slot_uop_uop_ctrl_op1_sel = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_iw_state = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_rxq_idx = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_mem_size = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs1_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_lrs2_rtype = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_fsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_uop_debug_tsrc = 2'h0; // @[consts.scala:269:19] wire [1:0] slot_uop_cs_op1_sel = 2'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_uop_iq_type = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_op2_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_imm_sel = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_uop_ctrl_csr_cmd = 3'h0; // @[consts.scala:269:19] wire [2:0] slot_uop_cs_op2_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_imm_sel = 3'h0; // @[consts.scala:279:18] wire [2:0] slot_uop_cs_csr_cmd = 3'h0; // @[consts.scala:279:18] wire [3:0] slot_uop_uop_ctrl_br_type = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_uop_br_tag = 4'h0; // @[consts.scala:269:19] wire [3:0] slot_uop_cs_br_type = 4'h0; // @[consts.scala:279:18] wire [1:0] slot_uop_uop_dst_rtype = 2'h2; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_pc_lob = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_ldst = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs1 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs2 = 6'h0; // @[consts.scala:269:19] wire [5:0] slot_uop_uop_lrs3 = 6'h0; // @[consts.scala:269:19] wire [63:0] slot_uop_uop_exc_cause = 64'h0; // @[consts.scala:269:19] wire [11:0] slot_uop_uop_csr_addr = 12'h0; // @[consts.scala:269:19] wire [19:0] slot_uop_uop_imm_packed = 20'h0; // @[consts.scala:269:19] wire [15:0] slot_uop_uop_br_mask = 16'h0; // @[consts.scala:269:19] wire [9:0] slot_uop_uop_fu_code = 10'h0; // @[consts.scala:269:19] wire [39:0] slot_uop_uop_debug_pc = 40'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_inst = 32'h0; // @[consts.scala:269:19] wire [31:0] slot_uop_uop_debug_inst = 32'h0; // @[consts.scala:269:19] wire _io_valid_T; // @[issue-slot.scala:79:24] wire _io_will_be_valid_T_4; // @[issue-slot.scala:262:32] wire _io_request_hp_T; // @[issue-slot.scala:243:31] wire [6:0] next_uopc; // @[issue-slot.scala:82:29] wire [1:0] next_state; // @[issue-slot.scala:81:29] wire [15:0] next_br_mask; // @[util.scala:85:25] wire _io_out_uop_prs1_busy_T; // @[issue-slot.scala:270:28] wire _io_out_uop_prs2_busy_T; // @[issue-slot.scala:271:28] wire _io_out_uop_prs3_busy_T; // @[issue-slot.scala:272:28] wire _io_out_uop_ppred_busy_T; // @[issue-slot.scala:273:28] wire [1:0] next_lrs1_rtype; // @[issue-slot.scala:83:29] wire [1:0] next_lrs2_rtype; // @[issue-slot.scala:84:29] wire [3:0] io_out_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_out_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_out_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_out_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_out_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_out_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_out_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_out_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_out_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_out_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_out_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_out_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_out_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_out_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_out_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_out_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_out_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_out_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_out_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_out_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_out_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_out_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_out_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_out_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_out_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_out_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_out_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_out_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_ctrl_br_type_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_ctrl_op1_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_op2_sel_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_imm_sel_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ctrl_op_fcn_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_fcn_dw_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_ctrl_csr_cmd_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_load_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_sta_0; // @[issue-slot.scala:69:7] wire io_uop_ctrl_is_std_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_uopc_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_inst_0; // @[issue-slot.scala:69:7] wire [31:0] io_uop_debug_inst_0; // @[issue-slot.scala:69:7] wire io_uop_is_rvc_0; // @[issue-slot.scala:69:7] wire [39:0] io_uop_debug_pc_0; // @[issue-slot.scala:69:7] wire [2:0] io_uop_iq_type_0; // @[issue-slot.scala:69:7] wire [9:0] io_uop_fu_code_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_iw_state_0; // @[issue-slot.scala:69:7] wire io_uop_is_br_0; // @[issue-slot.scala:69:7] wire io_uop_is_jalr_0; // @[issue-slot.scala:69:7] wire io_uop_is_jal_0; // @[issue-slot.scala:69:7] wire io_uop_is_sfb_0; // @[issue-slot.scala:69:7] wire [15:0] io_uop_br_mask_0; // @[issue-slot.scala:69:7] wire [3:0] io_uop_br_tag_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ftq_idx_0; // @[issue-slot.scala:69:7] wire io_uop_edge_inst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_pc_lob_0; // @[issue-slot.scala:69:7] wire io_uop_taken_0; // @[issue-slot.scala:69:7] wire [19:0] io_uop_imm_packed_0; // @[issue-slot.scala:69:7] wire [11:0] io_uop_csr_addr_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_rob_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ldq_idx_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_stq_idx_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_rxq_idx_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_pdst_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs1_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs2_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_prs3_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_ppred_0; // @[issue-slot.scala:69:7] wire io_uop_prs1_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs2_busy_0; // @[issue-slot.scala:69:7] wire io_uop_prs3_busy_0; // @[issue-slot.scala:69:7] wire io_uop_ppred_busy_0; // @[issue-slot.scala:69:7] wire [6:0] io_uop_stale_pdst_0; // @[issue-slot.scala:69:7] wire io_uop_exception_0; // @[issue-slot.scala:69:7] wire [63:0] io_uop_exc_cause_0; // @[issue-slot.scala:69:7] wire io_uop_bypassable_0; // @[issue-slot.scala:69:7] wire [4:0] io_uop_mem_cmd_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_mem_size_0; // @[issue-slot.scala:69:7] wire io_uop_mem_signed_0; // @[issue-slot.scala:69:7] wire io_uop_is_fence_0; // @[issue-slot.scala:69:7] wire io_uop_is_fencei_0; // @[issue-slot.scala:69:7] wire io_uop_is_amo_0; // @[issue-slot.scala:69:7] wire io_uop_uses_ldq_0; // @[issue-slot.scala:69:7] wire io_uop_uses_stq_0; // @[issue-slot.scala:69:7] wire io_uop_is_sys_pc2epc_0; // @[issue-slot.scala:69:7] wire io_uop_is_unique_0; // @[issue-slot.scala:69:7] wire io_uop_flush_on_commit_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_is_rs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_ldst_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs1_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs2_0; // @[issue-slot.scala:69:7] wire [5:0] io_uop_lrs3_0; // @[issue-slot.scala:69:7] wire io_uop_ldst_val_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_dst_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs1_rtype_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_lrs2_rtype_0; // @[issue-slot.scala:69:7] wire io_uop_frs3_en_0; // @[issue-slot.scala:69:7] wire io_uop_fp_val_0; // @[issue-slot.scala:69:7] wire io_uop_fp_single_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_pf_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ae_if_0; // @[issue-slot.scala:69:7] wire io_uop_xcpt_ma_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_debug_if_0; // @[issue-slot.scala:69:7] wire io_uop_bp_xcpt_if_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_fsrc_0; // @[issue-slot.scala:69:7] wire [1:0] io_uop_debug_tsrc_0; // @[issue-slot.scala:69:7] wire io_debug_p1_0; // @[issue-slot.scala:69:7] wire io_debug_p2_0; // @[issue-slot.scala:69:7] wire io_debug_p3_0; // @[issue-slot.scala:69:7] wire io_debug_ppred_0; // @[issue-slot.scala:69:7] wire [1:0] io_debug_state_0; // @[issue-slot.scala:69:7] wire io_valid_0; // @[issue-slot.scala:69:7] wire io_will_be_valid_0; // @[issue-slot.scala:69:7] wire io_request_0; // @[issue-slot.scala:69:7] wire io_request_hp_0; // @[issue-slot.scala:69:7] assign io_out_uop_iw_state_0 = next_state; // @[issue-slot.scala:69:7, :81:29] assign io_out_uop_uopc_0 = next_uopc; // @[issue-slot.scala:69:7, :82:29] assign io_out_uop_lrs1_rtype_0 = next_lrs1_rtype; // @[issue-slot.scala:69:7, :83:29] assign io_out_uop_lrs2_rtype_0 = next_lrs2_rtype; // @[issue-slot.scala:69:7, :84:29] reg [1:0] state; // @[issue-slot.scala:86:22] assign io_debug_state_0 = state; // @[issue-slot.scala:69:7, :86:22] reg p1; // @[issue-slot.scala:87:22] assign io_debug_p1_0 = p1; // @[issue-slot.scala:69:7, :87:22] wire next_p1 = p1; // @[issue-slot.scala:87:22, :163:25] reg p2; // @[issue-slot.scala:88:22] assign io_debug_p2_0 = p2; // @[issue-slot.scala:69:7, :88:22] wire next_p2 = p2; // @[issue-slot.scala:88:22, :164:25] reg p3; // @[issue-slot.scala:89:22] assign io_debug_p3_0 = p3; // @[issue-slot.scala:69:7, :89:22] wire next_p3 = p3; // @[issue-slot.scala:89:22, :165:25] reg ppred; // @[issue-slot.scala:90:22] assign io_debug_ppred_0 = ppred; // @[issue-slot.scala:69:7, :90:22] wire next_ppred = ppred; // @[issue-slot.scala:90:22, :166:28] reg [6:0] slot_uop_uopc; // @[issue-slot.scala:102:25] reg [31:0] slot_uop_inst; // @[issue-slot.scala:102:25] assign io_out_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_inst_0 = slot_uop_inst; // @[issue-slot.scala:69:7, :102:25] reg [31:0] slot_uop_debug_inst; // @[issue-slot.scala:102:25] assign io_out_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_inst_0 = slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_rvc; // @[issue-slot.scala:102:25] assign io_out_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_rvc_0 = slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25] reg [39:0] slot_uop_debug_pc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_pc_0 = slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_iq_type; // @[issue-slot.scala:102:25] assign io_out_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_iq_type_0 = slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25] reg [9:0] slot_uop_fu_code; // @[issue-slot.scala:102:25] assign io_out_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fu_code_0 = slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_ctrl_br_type; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_br_type_0 = slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_ctrl_op1_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op1_sel_0 = slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_op2_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op2_sel_0 = slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_imm_sel; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_imm_sel_0 = slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ctrl_op_fcn; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_op_fcn_0 = slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_fcn_dw_0 = slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25] reg [2:0] slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_csr_cmd_0 = slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_load; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_load_0 = slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_sta; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_sta_0 = slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ctrl_is_std; // @[issue-slot.scala:102:25] assign io_out_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ctrl_is_std_0 = slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_iw_state; // @[issue-slot.scala:102:25] assign io_uop_iw_state_0 = slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_iw_p1_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_iw_p2_poisoned; // @[issue-slot.scala:102:25] reg slot_uop_is_br; // @[issue-slot.scala:102:25] assign io_out_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_br_0 = slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jalr; // @[issue-slot.scala:102:25] assign io_out_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jalr_0 = slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_jal; // @[issue-slot.scala:102:25] assign io_out_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_jal_0 = slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sfb; // @[issue-slot.scala:102:25] assign io_out_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sfb_0 = slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25] reg [15:0] slot_uop_br_mask; // @[issue-slot.scala:102:25] assign io_uop_br_mask_0 = slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25] reg [3:0] slot_uop_br_tag; // @[issue-slot.scala:102:25] assign io_out_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] assign io_uop_br_tag_0 = slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ftq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ftq_idx_0 = slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_edge_inst; // @[issue-slot.scala:102:25] assign io_out_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_edge_inst_0 = slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_pc_lob; // @[issue-slot.scala:102:25] assign io_out_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pc_lob_0 = slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_taken; // @[issue-slot.scala:102:25] assign io_out_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] assign io_uop_taken_0 = slot_uop_taken; // @[issue-slot.scala:69:7, :102:25] reg [19:0] slot_uop_imm_packed; // @[issue-slot.scala:102:25] assign io_out_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_imm_packed_0 = slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25] reg [11:0] slot_uop_csr_addr; // @[issue-slot.scala:102:25] assign io_out_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] assign io_uop_csr_addr_0 = slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_rob_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rob_idx_0 = slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ldq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldq_idx_0 = slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_stq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stq_idx_0 = slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_rxq_idx; // @[issue-slot.scala:102:25] assign io_out_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] assign io_uop_rxq_idx_0 = slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_pdst_0 = slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs1; // @[issue-slot.scala:102:25] assign io_out_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs1_0 = slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs2; // @[issue-slot.scala:102:25] assign io_out_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs2_0 = slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_prs3; // @[issue-slot.scala:102:25] assign io_out_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_prs3_0 = slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_ppred; // @[issue-slot.scala:102:25] assign io_out_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ppred_0 = slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs1_busy; // @[issue-slot.scala:102:25] assign io_uop_prs1_busy_0 = slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs2_busy; // @[issue-slot.scala:102:25] assign io_uop_prs2_busy_0 = slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_prs3_busy; // @[issue-slot.scala:102:25] assign io_uop_prs3_busy_0 = slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ppred_busy; // @[issue-slot.scala:102:25] assign io_uop_ppred_busy_0 = slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25] reg [6:0] slot_uop_stale_pdst; // @[issue-slot.scala:102:25] assign io_out_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_stale_pdst_0 = slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_exception; // @[issue-slot.scala:102:25] assign io_out_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exception_0 = slot_uop_exception; // @[issue-slot.scala:69:7, :102:25] reg [63:0] slot_uop_exc_cause; // @[issue-slot.scala:102:25] assign io_out_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] assign io_uop_exc_cause_0 = slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bypassable; // @[issue-slot.scala:102:25] assign io_out_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bypassable_0 = slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25] reg [4:0] slot_uop_mem_cmd; // @[issue-slot.scala:102:25] assign io_out_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_cmd_0 = slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_mem_size; // @[issue-slot.scala:102:25] assign io_out_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_size_0 = slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_mem_signed; // @[issue-slot.scala:102:25] assign io_out_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] assign io_uop_mem_signed_0 = slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fence; // @[issue-slot.scala:102:25] assign io_out_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fence_0 = slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_fencei; // @[issue-slot.scala:102:25] assign io_out_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_fencei_0 = slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_amo; // @[issue-slot.scala:102:25] assign io_out_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_amo_0 = slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_ldq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_ldq_0 = slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_uses_stq; // @[issue-slot.scala:102:25] assign io_out_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] assign io_uop_uses_stq_0 = slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_sys_pc2epc; // @[issue-slot.scala:102:25] assign io_out_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_sys_pc2epc_0 = slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_is_unique; // @[issue-slot.scala:102:25] assign io_out_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] assign io_uop_is_unique_0 = slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_flush_on_commit; // @[issue-slot.scala:102:25] assign io_out_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] assign io_uop_flush_on_commit_0 = slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_is_rs1; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_is_rs1_0 = slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_ldst; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_0 = slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs1; // @[issue-slot.scala:102:25] assign io_out_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs1_0 = slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs2; // @[issue-slot.scala:102:25] assign io_out_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs2_0 = slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25] reg [5:0] slot_uop_lrs3; // @[issue-slot.scala:102:25] assign io_out_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] assign io_uop_lrs3_0 = slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_ldst_val; // @[issue-slot.scala:102:25] assign io_out_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_ldst_val_0 = slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_dst_rtype; // @[issue-slot.scala:102:25] assign io_out_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] assign io_uop_dst_rtype_0 = slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_lrs1_rtype; // @[issue-slot.scala:102:25] reg [1:0] slot_uop_lrs2_rtype; // @[issue-slot.scala:102:25] reg slot_uop_frs3_en; // @[issue-slot.scala:102:25] assign io_out_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] assign io_uop_frs3_en_0 = slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_val; // @[issue-slot.scala:102:25] assign io_out_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_val_0 = slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_fp_single; // @[issue-slot.scala:102:25] assign io_out_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] assign io_uop_fp_single_0 = slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_pf_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_pf_if_0 = slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ae_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ae_if_0 = slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_xcpt_ma_if; // @[issue-slot.scala:102:25] assign io_out_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_xcpt_ma_if_0 = slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_debug_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_debug_if_0 = slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25] reg slot_uop_bp_xcpt_if; // @[issue-slot.scala:102:25] assign io_out_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] assign io_uop_bp_xcpt_if_0 = slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_fsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_fsrc_0 = slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25] reg [1:0] slot_uop_debug_tsrc; // @[issue-slot.scala:102:25] assign io_out_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] assign io_uop_debug_tsrc_0 = slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25] wire [6:0] next_uop_uopc = io_in_uop_valid_0 ? io_in_uop_bits_uopc_0 : slot_uop_uopc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_inst = io_in_uop_valid_0 ? io_in_uop_bits_inst_0 : slot_uop_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [31:0] next_uop_debug_inst = io_in_uop_valid_0 ? io_in_uop_bits_debug_inst_0 : slot_uop_debug_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_rvc = io_in_uop_valid_0 ? io_in_uop_bits_is_rvc_0 : slot_uop_is_rvc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [39:0] next_uop_debug_pc = io_in_uop_valid_0 ? io_in_uop_bits_debug_pc_0 : slot_uop_debug_pc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_iq_type = io_in_uop_valid_0 ? io_in_uop_bits_iq_type_0 : slot_uop_iq_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [9:0] next_uop_fu_code = io_in_uop_valid_0 ? io_in_uop_bits_fu_code_0 : slot_uop_fu_code; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_ctrl_br_type = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_br_type_0 : slot_uop_ctrl_br_type; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_ctrl_op1_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op1_sel_0 : slot_uop_ctrl_op1_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_op2_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op2_sel_0 : slot_uop_ctrl_op2_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_imm_sel = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_imm_sel_0 : slot_uop_ctrl_imm_sel; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ctrl_op_fcn = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_op_fcn_0 : slot_uop_ctrl_op_fcn; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_fcn_dw = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_fcn_dw_0 : slot_uop_ctrl_fcn_dw; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [2:0] next_uop_ctrl_csr_cmd = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_csr_cmd_0 : slot_uop_ctrl_csr_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_load = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_load_0 : slot_uop_ctrl_is_load; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_sta = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_sta_0 : slot_uop_ctrl_is_sta; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ctrl_is_std = io_in_uop_valid_0 ? io_in_uop_bits_ctrl_is_std_0 : slot_uop_ctrl_is_std; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_iw_state = io_in_uop_valid_0 ? io_in_uop_bits_iw_state_0 : slot_uop_iw_state; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p1_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p1_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_iw_p2_poisoned = ~io_in_uop_valid_0 & slot_uop_iw_p2_poisoned; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_br = io_in_uop_valid_0 ? io_in_uop_bits_is_br_0 : slot_uop_is_br; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jalr = io_in_uop_valid_0 ? io_in_uop_bits_is_jalr_0 : slot_uop_is_jalr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_jal = io_in_uop_valid_0 ? io_in_uop_bits_is_jal_0 : slot_uop_is_jal; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sfb = io_in_uop_valid_0 ? io_in_uop_bits_is_sfb_0 : slot_uop_is_sfb; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [15:0] next_uop_br_mask = io_in_uop_valid_0 ? io_in_uop_bits_br_mask_0 : slot_uop_br_mask; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [3:0] next_uop_br_tag = io_in_uop_valid_0 ? io_in_uop_bits_br_tag_0 : slot_uop_br_tag; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ftq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ftq_idx_0 : slot_uop_ftq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_edge_inst = io_in_uop_valid_0 ? io_in_uop_bits_edge_inst_0 : slot_uop_edge_inst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_pc_lob = io_in_uop_valid_0 ? io_in_uop_bits_pc_lob_0 : slot_uop_pc_lob; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_taken = io_in_uop_valid_0 ? io_in_uop_bits_taken_0 : slot_uop_taken; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [19:0] next_uop_imm_packed = io_in_uop_valid_0 ? io_in_uop_bits_imm_packed_0 : slot_uop_imm_packed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [11:0] next_uop_csr_addr = io_in_uop_valid_0 ? io_in_uop_bits_csr_addr_0 : slot_uop_csr_addr; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_rob_idx = io_in_uop_valid_0 ? io_in_uop_bits_rob_idx_0 : slot_uop_rob_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ldq_idx = io_in_uop_valid_0 ? io_in_uop_bits_ldq_idx_0 : slot_uop_ldq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_stq_idx = io_in_uop_valid_0 ? io_in_uop_bits_stq_idx_0 : slot_uop_stq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_rxq_idx = io_in_uop_valid_0 ? io_in_uop_bits_rxq_idx_0 : slot_uop_rxq_idx; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_pdst = io_in_uop_valid_0 ? io_in_uop_bits_pdst_0 : slot_uop_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs1 = io_in_uop_valid_0 ? io_in_uop_bits_prs1_0 : slot_uop_prs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs2 = io_in_uop_valid_0 ? io_in_uop_bits_prs2_0 : slot_uop_prs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_prs3 = io_in_uop_valid_0 ? io_in_uop_bits_prs3_0 : slot_uop_prs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_ppred = io_in_uop_valid_0 ? io_in_uop_bits_ppred_0 : slot_uop_ppred; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs1_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs1_busy_0 : slot_uop_prs1_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs2_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs2_busy_0 : slot_uop_prs2_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_prs3_busy = io_in_uop_valid_0 ? io_in_uop_bits_prs3_busy_0 : slot_uop_prs3_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ppred_busy = io_in_uop_valid_0 ? io_in_uop_bits_ppred_busy_0 : slot_uop_ppred_busy; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [6:0] next_uop_stale_pdst = io_in_uop_valid_0 ? io_in_uop_bits_stale_pdst_0 : slot_uop_stale_pdst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_exception = io_in_uop_valid_0 ? io_in_uop_bits_exception_0 : slot_uop_exception; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [63:0] next_uop_exc_cause = io_in_uop_valid_0 ? io_in_uop_bits_exc_cause_0 : slot_uop_exc_cause; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bypassable = io_in_uop_valid_0 ? io_in_uop_bits_bypassable_0 : slot_uop_bypassable; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [4:0] next_uop_mem_cmd = io_in_uop_valid_0 ? io_in_uop_bits_mem_cmd_0 : slot_uop_mem_cmd; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_mem_size = io_in_uop_valid_0 ? io_in_uop_bits_mem_size_0 : slot_uop_mem_size; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_mem_signed = io_in_uop_valid_0 ? io_in_uop_bits_mem_signed_0 : slot_uop_mem_signed; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fence = io_in_uop_valid_0 ? io_in_uop_bits_is_fence_0 : slot_uop_is_fence; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_fencei = io_in_uop_valid_0 ? io_in_uop_bits_is_fencei_0 : slot_uop_is_fencei; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_amo = io_in_uop_valid_0 ? io_in_uop_bits_is_amo_0 : slot_uop_is_amo; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_ldq = io_in_uop_valid_0 ? io_in_uop_bits_uses_ldq_0 : slot_uop_uses_ldq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_uses_stq = io_in_uop_valid_0 ? io_in_uop_bits_uses_stq_0 : slot_uop_uses_stq; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_sys_pc2epc = io_in_uop_valid_0 ? io_in_uop_bits_is_sys_pc2epc_0 : slot_uop_is_sys_pc2epc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_is_unique = io_in_uop_valid_0 ? io_in_uop_bits_is_unique_0 : slot_uop_is_unique; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_flush_on_commit = io_in_uop_valid_0 ? io_in_uop_bits_flush_on_commit_0 : slot_uop_flush_on_commit; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_is_rs1 = io_in_uop_valid_0 ? io_in_uop_bits_ldst_is_rs1_0 : slot_uop_ldst_is_rs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_ldst = io_in_uop_valid_0 ? io_in_uop_bits_ldst_0 : slot_uop_ldst; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs1 = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_0 : slot_uop_lrs1; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs2 = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_0 : slot_uop_lrs2; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [5:0] next_uop_lrs3 = io_in_uop_valid_0 ? io_in_uop_bits_lrs3_0 : slot_uop_lrs3; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_ldst_val = io_in_uop_valid_0 ? io_in_uop_bits_ldst_val_0 : slot_uop_ldst_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_dst_rtype = io_in_uop_valid_0 ? io_in_uop_bits_dst_rtype_0 : slot_uop_dst_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs1_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs1_rtype_0 : slot_uop_lrs1_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_lrs2_rtype = io_in_uop_valid_0 ? io_in_uop_bits_lrs2_rtype_0 : slot_uop_lrs2_rtype; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_frs3_en = io_in_uop_valid_0 ? io_in_uop_bits_frs3_en_0 : slot_uop_frs3_en; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_val = io_in_uop_valid_0 ? io_in_uop_bits_fp_val_0 : slot_uop_fp_val; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_fp_single = io_in_uop_valid_0 ? io_in_uop_bits_fp_single_0 : slot_uop_fp_single; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_pf_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_pf_if_0 : slot_uop_xcpt_pf_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ae_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ae_if_0 : slot_uop_xcpt_ae_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_xcpt_ma_if = io_in_uop_valid_0 ? io_in_uop_bits_xcpt_ma_if_0 : slot_uop_xcpt_ma_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_debug_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_debug_if_0 : slot_uop_bp_debug_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire next_uop_bp_xcpt_if = io_in_uop_valid_0 ? io_in_uop_bits_bp_xcpt_if_0 : slot_uop_bp_xcpt_if; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_fsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_fsrc_0 : slot_uop_debug_fsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire [1:0] next_uop_debug_tsrc = io_in_uop_valid_0 ? io_in_uop_bits_debug_tsrc_0 : slot_uop_debug_tsrc; // @[issue-slot.scala:69:7, :102:25, :103:21] wire _T_11 = state == 2'h2; // @[issue-slot.scala:86:22, :134:25] wire _T_7 = io_grant_0 & state == 2'h1 | io_grant_0 & _T_11 & p1 & p2 & ppred; // @[issue-slot.scala:69:7, :86:22, :87:22, :88:22, :90:22, :133:{26,36,52}, :134:{15,25,40,46,52}] wire _T_12 = io_grant_0 & _T_11; // @[issue-slot.scala:69:7, :134:25, :139:25] wire _GEN = io_kill_0 | _T_7; // @[issue-slot.scala:69:7, :102:25, :131:18, :133:52, :134:63, :139:51] wire _GEN_0 = _GEN | ~(_T_12 & p1); // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17, :143:23] assign next_uopc = _GEN_0 ? slot_uop_uopc : 7'h3; // @[issue-slot.scala:82:29, :102:25, :131:18, :134:63, :139:51] assign next_lrs1_rtype = _GEN_0 ? slot_uop_lrs1_rtype : 2'h2; // @[issue-slot.scala:83:29, :102:25, :131:18, :134:63, :139:51] wire _GEN_1 = _GEN | ~_T_12 | p1; // @[issue-slot.scala:87:22, :102:25, :131:18, :134:63, :139:{25,51}, :140:62, :142:17] assign next_lrs2_rtype = _GEN_1 ? slot_uop_lrs2_rtype : 2'h2; // @[issue-slot.scala:84:29, :102:25, :131:18, :134:63, :139:51, :140:62, :142:17]
Generate the Verilog code corresponding to this FIRRTL code module XactTracker : input clock : Clock input reset : Reset output io : { flip alloc : { valid : UInt<1>, flip ready : UInt<1>, flip xactid : UInt<4>, entry : { shift : UInt<6>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<8>, len : UInt<16>, block_stride : UInt<16>, spad_row_offset : UInt<9>, lg_len_req : UInt<3>, bytes_to_read : UInt<7>, cmd_id : UInt<1>}}, peek : { flip xactid : UInt<4>, flip pop : UInt<1>, entry : { shift : UInt<6>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<8>, len : UInt<16>, block_stride : UInt<16>, spad_row_offset : UInt<9>, lg_len_req : UInt<3>, bytes_to_read : UInt<7>, cmd_id : UInt<1>}}, busy : UInt<1>, counter : { event_signal : UInt<1>[45], external_values : UInt<32>[8], flip external_reset : UInt<1>}} reg entries : { valid : UInt<1>, bits : { shift : UInt<6>, addr : UInt<14>, is_acc : UInt<1>, accumulate : UInt<1>, has_acc_bitwidth : UInt<1>, scale : UInt<32>, repeats : UInt<16>, pixel_repeats : UInt<8>, len : UInt<16>, block_stride : UInt<16>, spad_row_offset : UInt<9>, lg_len_req : UInt<3>, bytes_to_read : UInt<7>, cmd_id : UInt<1>}}[16], clock node _free_entry_T = eq(entries[0].valid, UInt<1>(0h0)) node _free_entry_T_1 = eq(entries[1].valid, UInt<1>(0h0)) node _free_entry_T_2 = eq(entries[2].valid, UInt<1>(0h0)) node _free_entry_T_3 = eq(entries[3].valid, UInt<1>(0h0)) node _free_entry_T_4 = eq(entries[4].valid, UInt<1>(0h0)) node _free_entry_T_5 = eq(entries[5].valid, UInt<1>(0h0)) node _free_entry_T_6 = eq(entries[6].valid, UInt<1>(0h0)) node _free_entry_T_7 = eq(entries[7].valid, UInt<1>(0h0)) node _free_entry_T_8 = eq(entries[8].valid, UInt<1>(0h0)) node _free_entry_T_9 = eq(entries[9].valid, UInt<1>(0h0)) node _free_entry_T_10 = eq(entries[10].valid, UInt<1>(0h0)) node _free_entry_T_11 = eq(entries[11].valid, UInt<1>(0h0)) node _free_entry_T_12 = eq(entries[12].valid, UInt<1>(0h0)) node _free_entry_T_13 = eq(entries[13].valid, UInt<1>(0h0)) node _free_entry_T_14 = eq(entries[14].valid, UInt<1>(0h0)) node _free_entry_T_15 = eq(entries[15].valid, UInt<1>(0h0)) node _free_entry_T_16 = mux(_free_entry_T_15, UInt<4>(0hf), UInt<4>(0hf)) node _free_entry_T_17 = mux(_free_entry_T_14, UInt<4>(0he), _free_entry_T_16) node _free_entry_T_18 = mux(_free_entry_T_13, UInt<4>(0hd), _free_entry_T_17) node _free_entry_T_19 = mux(_free_entry_T_12, UInt<4>(0hc), _free_entry_T_18) node _free_entry_T_20 = mux(_free_entry_T_11, UInt<4>(0hb), _free_entry_T_19) node _free_entry_T_21 = mux(_free_entry_T_10, UInt<4>(0ha), _free_entry_T_20) node _free_entry_T_22 = mux(_free_entry_T_9, UInt<4>(0h9), _free_entry_T_21) node _free_entry_T_23 = mux(_free_entry_T_8, UInt<4>(0h8), _free_entry_T_22) node _free_entry_T_24 = mux(_free_entry_T_7, UInt<3>(0h7), _free_entry_T_23) node _free_entry_T_25 = mux(_free_entry_T_6, UInt<3>(0h6), _free_entry_T_24) node _free_entry_T_26 = mux(_free_entry_T_5, UInt<3>(0h5), _free_entry_T_25) node _free_entry_T_27 = mux(_free_entry_T_4, UInt<3>(0h4), _free_entry_T_26) node _free_entry_T_28 = mux(_free_entry_T_3, UInt<2>(0h3), _free_entry_T_27) node _free_entry_T_29 = mux(_free_entry_T_2, UInt<2>(0h2), _free_entry_T_28) node _free_entry_T_30 = mux(_free_entry_T_1, UInt<1>(0h1), _free_entry_T_29) node free_entry = mux(_free_entry_T, UInt<1>(0h0), _free_entry_T_30) node _io_alloc_ready_T = and(entries[0].valid, entries[1].valid) node _io_alloc_ready_T_1 = and(_io_alloc_ready_T, entries[2].valid) node _io_alloc_ready_T_2 = and(_io_alloc_ready_T_1, entries[3].valid) node _io_alloc_ready_T_3 = and(_io_alloc_ready_T_2, entries[4].valid) node _io_alloc_ready_T_4 = and(_io_alloc_ready_T_3, entries[5].valid) node _io_alloc_ready_T_5 = and(_io_alloc_ready_T_4, entries[6].valid) node _io_alloc_ready_T_6 = and(_io_alloc_ready_T_5, entries[7].valid) node _io_alloc_ready_T_7 = and(_io_alloc_ready_T_6, entries[8].valid) node _io_alloc_ready_T_8 = and(_io_alloc_ready_T_7, entries[9].valid) node _io_alloc_ready_T_9 = and(_io_alloc_ready_T_8, entries[10].valid) node _io_alloc_ready_T_10 = and(_io_alloc_ready_T_9, entries[11].valid) node _io_alloc_ready_T_11 = and(_io_alloc_ready_T_10, entries[12].valid) node _io_alloc_ready_T_12 = and(_io_alloc_ready_T_11, entries[13].valid) node _io_alloc_ready_T_13 = and(_io_alloc_ready_T_12, entries[14].valid) node _io_alloc_ready_T_14 = and(_io_alloc_ready_T_13, entries[15].valid) node _io_alloc_ready_T_15 = eq(_io_alloc_ready_T_14, UInt<1>(0h0)) connect io.alloc.ready, _io_alloc_ready_T_15 connect io.alloc.xactid, free_entry connect io.peek.entry, entries[io.peek.xactid].bits node _io_busy_T = or(entries[0].valid, entries[1].valid) node _io_busy_T_1 = or(_io_busy_T, entries[2].valid) node _io_busy_T_2 = or(_io_busy_T_1, entries[3].valid) node _io_busy_T_3 = or(_io_busy_T_2, entries[4].valid) node _io_busy_T_4 = or(_io_busy_T_3, entries[5].valid) node _io_busy_T_5 = or(_io_busy_T_4, entries[6].valid) node _io_busy_T_6 = or(_io_busy_T_5, entries[7].valid) node _io_busy_T_7 = or(_io_busy_T_6, entries[8].valid) node _io_busy_T_8 = or(_io_busy_T_7, entries[9].valid) node _io_busy_T_9 = or(_io_busy_T_8, entries[10].valid) node _io_busy_T_10 = or(_io_busy_T_9, entries[11].valid) node _io_busy_T_11 = or(_io_busy_T_10, entries[12].valid) node _io_busy_T_12 = or(_io_busy_T_11, entries[13].valid) node _io_busy_T_13 = or(_io_busy_T_12, entries[14].valid) node _io_busy_T_14 = or(_io_busy_T_13, entries[15].valid) connect io.busy, _io_busy_T_14 node _T = and(io.alloc.valid, io.alloc.ready) when _T : connect entries[free_entry].valid, UInt<1>(0h1) connect entries[free_entry].bits, io.alloc.entry when io.peek.pop : connect entries[io.peek.xactid].valid, UInt<1>(0h0) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(entries[io.peek.xactid].valid, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed\n at XactTracker.scala:84 assert(entries(io.peek.xactid).valid)\n") : printf assert(clock, entries[io.peek.xactid].valid, UInt<1>(0h1), "") : assert node _T_4 = asUInt(reset) when _T_4 : connect entries[0].valid, UInt<1>(0h0) connect entries[1].valid, UInt<1>(0h0) connect entries[2].valid, UInt<1>(0h0) connect entries[3].valid, UInt<1>(0h0) connect entries[4].valid, UInt<1>(0h0) connect entries[5].valid, UInt<1>(0h0) connect entries[6].valid, UInt<1>(0h0) connect entries[7].valid, UInt<1>(0h0) connect entries[8].valid, UInt<1>(0h0) connect entries[9].valid, UInt<1>(0h0) connect entries[10].valid, UInt<1>(0h0) connect entries[11].valid, UInt<1>(0h0) connect entries[12].valid, UInt<1>(0h0) connect entries[13].valid, UInt<1>(0h0) connect entries[14].valid, UInt<1>(0h0) connect entries[15].valid, UInt<1>(0h0) wire _WIRE : UInt<1>[45] connect _WIRE[0], UInt<1>(0h0) connect _WIRE[1], UInt<1>(0h0) connect _WIRE[2], UInt<1>(0h0) connect _WIRE[3], UInt<1>(0h0) connect _WIRE[4], UInt<1>(0h0) connect _WIRE[5], UInt<1>(0h0) connect _WIRE[6], UInt<1>(0h0) connect _WIRE[7], UInt<1>(0h0) connect _WIRE[8], UInt<1>(0h0) connect _WIRE[9], UInt<1>(0h0) connect _WIRE[10], UInt<1>(0h0) connect _WIRE[11], UInt<1>(0h0) connect _WIRE[12], UInt<1>(0h0) connect _WIRE[13], UInt<1>(0h0) connect _WIRE[14], UInt<1>(0h0) connect _WIRE[15], UInt<1>(0h0) connect _WIRE[16], UInt<1>(0h0) connect _WIRE[17], UInt<1>(0h0) connect _WIRE[18], UInt<1>(0h0) connect _WIRE[19], UInt<1>(0h0) connect _WIRE[20], UInt<1>(0h0) connect _WIRE[21], UInt<1>(0h0) connect _WIRE[22], UInt<1>(0h0) connect _WIRE[23], UInt<1>(0h0) connect _WIRE[24], UInt<1>(0h0) connect _WIRE[25], UInt<1>(0h0) connect _WIRE[26], UInt<1>(0h0) connect _WIRE[27], UInt<1>(0h0) connect _WIRE[28], UInt<1>(0h0) connect _WIRE[29], UInt<1>(0h0) connect _WIRE[30], UInt<1>(0h0) connect _WIRE[31], UInt<1>(0h0) connect _WIRE[32], UInt<1>(0h0) connect _WIRE[33], UInt<1>(0h0) connect _WIRE[34], UInt<1>(0h0) connect _WIRE[35], UInt<1>(0h0) connect _WIRE[36], UInt<1>(0h0) connect _WIRE[37], UInt<1>(0h0) connect _WIRE[38], UInt<1>(0h0) connect _WIRE[39], UInt<1>(0h0) connect _WIRE[40], UInt<1>(0h0) connect _WIRE[41], UInt<1>(0h0) connect _WIRE[42], UInt<1>(0h0) connect _WIRE[43], UInt<1>(0h0) connect _WIRE[44], UInt<1>(0h0) connect io.counter.event_signal, _WIRE wire _WIRE_1 : UInt<32>[8] connect _WIRE_1[0], UInt<32>(0h0) connect _WIRE_1[1], UInt<32>(0h0) connect _WIRE_1[2], UInt<32>(0h0) connect _WIRE_1[3], UInt<32>(0h0) connect _WIRE_1[4], UInt<32>(0h0) connect _WIRE_1[5], UInt<32>(0h0) connect _WIRE_1[6], UInt<32>(0h0) connect _WIRE_1[7], UInt<32>(0h0) connect io.counter.external_values, _WIRE_1 regreset total_latency : UInt<32>, clock, reset, UInt<32>(0h0) when io.counter.external_reset : connect total_latency, UInt<1>(0h0) else : node _total_latency_T = add(entries[0].valid, entries[1].valid) node _total_latency_T_1 = bits(_total_latency_T, 1, 0) node _total_latency_T_2 = add(entries[2].valid, entries[3].valid) node _total_latency_T_3 = bits(_total_latency_T_2, 1, 0) node _total_latency_T_4 = add(_total_latency_T_1, _total_latency_T_3) node _total_latency_T_5 = bits(_total_latency_T_4, 2, 0) node _total_latency_T_6 = add(entries[4].valid, entries[5].valid) node _total_latency_T_7 = bits(_total_latency_T_6, 1, 0) node _total_latency_T_8 = add(entries[6].valid, entries[7].valid) node _total_latency_T_9 = bits(_total_latency_T_8, 1, 0) node _total_latency_T_10 = add(_total_latency_T_7, _total_latency_T_9) node _total_latency_T_11 = bits(_total_latency_T_10, 2, 0) node _total_latency_T_12 = add(_total_latency_T_5, _total_latency_T_11) node _total_latency_T_13 = bits(_total_latency_T_12, 3, 0) node _total_latency_T_14 = add(entries[8].valid, entries[9].valid) node _total_latency_T_15 = bits(_total_latency_T_14, 1, 0) node _total_latency_T_16 = add(entries[10].valid, entries[11].valid) node _total_latency_T_17 = bits(_total_latency_T_16, 1, 0) node _total_latency_T_18 = add(_total_latency_T_15, _total_latency_T_17) node _total_latency_T_19 = bits(_total_latency_T_18, 2, 0) node _total_latency_T_20 = add(entries[12].valid, entries[13].valid) node _total_latency_T_21 = bits(_total_latency_T_20, 1, 0) node _total_latency_T_22 = add(entries[14].valid, entries[15].valid) node _total_latency_T_23 = bits(_total_latency_T_22, 1, 0) node _total_latency_T_24 = add(_total_latency_T_21, _total_latency_T_23) node _total_latency_T_25 = bits(_total_latency_T_24, 2, 0) node _total_latency_T_26 = add(_total_latency_T_19, _total_latency_T_25) node _total_latency_T_27 = bits(_total_latency_T_26, 3, 0) node _total_latency_T_28 = add(_total_latency_T_13, _total_latency_T_27) node _total_latency_T_29 = bits(_total_latency_T_28, 4, 0) node _total_latency_T_30 = add(total_latency, _total_latency_T_29) node _total_latency_T_31 = tail(_total_latency_T_30, 1) connect total_latency, _total_latency_T_31 connect io.counter.external_values[6], total_latency
module XactTracker( // @[XactTracker.scala:56:7] input clock, // @[XactTracker.scala:56:7] input reset, // @[XactTracker.scala:56:7] input io_alloc_valid, // @[XactTracker.scala:59:14] output io_alloc_ready, // @[XactTracker.scala:59:14] output [3:0] io_alloc_xactid, // @[XactTracker.scala:59:14] input [5:0] io_alloc_entry_shift, // @[XactTracker.scala:59:14] input [13:0] io_alloc_entry_addr, // @[XactTracker.scala:59:14] input io_alloc_entry_is_acc, // @[XactTracker.scala:59:14] input io_alloc_entry_accumulate, // @[XactTracker.scala:59:14] input io_alloc_entry_has_acc_bitwidth, // @[XactTracker.scala:59:14] input [31:0] io_alloc_entry_scale, // @[XactTracker.scala:59:14] input [15:0] io_alloc_entry_repeats, // @[XactTracker.scala:59:14] input [7:0] io_alloc_entry_pixel_repeats, // @[XactTracker.scala:59:14] input [15:0] io_alloc_entry_len, // @[XactTracker.scala:59:14] input [15:0] io_alloc_entry_block_stride, // @[XactTracker.scala:59:14] input [8:0] io_alloc_entry_spad_row_offset, // @[XactTracker.scala:59:14] input [6:0] io_alloc_entry_bytes_to_read, // @[XactTracker.scala:59:14] input io_alloc_entry_cmd_id, // @[XactTracker.scala:59:14] input [3:0] io_peek_xactid, // @[XactTracker.scala:59:14] input io_peek_pop, // @[XactTracker.scala:59:14] output [5:0] io_peek_entry_shift, // @[XactTracker.scala:59:14] output [13:0] io_peek_entry_addr, // @[XactTracker.scala:59:14] output io_peek_entry_is_acc, // @[XactTracker.scala:59:14] output io_peek_entry_accumulate, // @[XactTracker.scala:59:14] output io_peek_entry_has_acc_bitwidth, // @[XactTracker.scala:59:14] output [31:0] io_peek_entry_scale, // @[XactTracker.scala:59:14] output [15:0] io_peek_entry_repeats, // @[XactTracker.scala:59:14] output [7:0] io_peek_entry_pixel_repeats, // @[XactTracker.scala:59:14] output [15:0] io_peek_entry_len, // @[XactTracker.scala:59:14] output [15:0] io_peek_entry_block_stride, // @[XactTracker.scala:59:14] output [8:0] io_peek_entry_spad_row_offset, // @[XactTracker.scala:59:14] output [6:0] io_peek_entry_bytes_to_read, // @[XactTracker.scala:59:14] output io_peek_entry_cmd_id, // @[XactTracker.scala:59:14] output io_busy, // @[XactTracker.scala:59:14] output [31:0] io_counter_external_values_6, // @[XactTracker.scala:59:14] input io_counter_external_reset // @[XactTracker.scala:59:14] ); wire io_alloc_valid_0 = io_alloc_valid; // @[XactTracker.scala:56:7] wire [5:0] io_alloc_entry_shift_0 = io_alloc_entry_shift; // @[XactTracker.scala:56:7] wire [13:0] io_alloc_entry_addr_0 = io_alloc_entry_addr; // @[XactTracker.scala:56:7] wire io_alloc_entry_is_acc_0 = io_alloc_entry_is_acc; // @[XactTracker.scala:56:7] wire io_alloc_entry_accumulate_0 = io_alloc_entry_accumulate; // @[XactTracker.scala:56:7] wire io_alloc_entry_has_acc_bitwidth_0 = io_alloc_entry_has_acc_bitwidth; // @[XactTracker.scala:56:7] wire [31:0] io_alloc_entry_scale_0 = io_alloc_entry_scale; // @[XactTracker.scala:56:7] wire [15:0] io_alloc_entry_repeats_0 = io_alloc_entry_repeats; // @[XactTracker.scala:56:7] wire [7:0] io_alloc_entry_pixel_repeats_0 = io_alloc_entry_pixel_repeats; // @[XactTracker.scala:56:7] wire [15:0] io_alloc_entry_len_0 = io_alloc_entry_len; // @[XactTracker.scala:56:7] wire [15:0] io_alloc_entry_block_stride_0 = io_alloc_entry_block_stride; // @[XactTracker.scala:56:7] wire [8:0] io_alloc_entry_spad_row_offset_0 = io_alloc_entry_spad_row_offset; // @[XactTracker.scala:56:7] wire [6:0] io_alloc_entry_bytes_to_read_0 = io_alloc_entry_bytes_to_read; // @[XactTracker.scala:56:7] wire io_alloc_entry_cmd_id_0 = io_alloc_entry_cmd_id; // @[XactTracker.scala:56:7] wire [3:0] io_peek_xactid_0 = io_peek_xactid; // @[XactTracker.scala:56:7] wire io_peek_pop_0 = io_peek_pop; // @[XactTracker.scala:56:7] wire io_counter_external_reset_0 = io_counter_external_reset; // @[XactTracker.scala:56:7] wire [2:0] io_alloc_entry_lg_len_req = 3'h0; // @[XactTracker.scala:56:7] wire [2:0] io_peek_entry_lg_len_req = 3'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_0 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_1 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_2 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_3 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_4 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_5 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_6 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_7 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_8 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_9 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_10 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_11 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_12 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_13 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_14 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_15 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_16 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_17 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_18 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_19 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_20 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_21 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_22 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_23 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_24 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_25 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_26 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_27 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_28 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_29 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_30 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_31 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_32 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_33 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_34 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_35 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_36 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_37 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_38 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_39 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_40 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_41 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_42 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_43 = 1'h0; // @[XactTracker.scala:56:7] wire io_counter_event_signal_44 = 1'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_0 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_1 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_2 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_3 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_4 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_5 = 32'h0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_7 = 32'h0; // @[XactTracker.scala:56:7] wire [3:0] _free_entry_T_16 = 4'hF; // @[Mux.scala:126:16] wire _io_alloc_ready_T_15; // @[XactTracker.scala:70:21] wire [3:0] free_entry; // @[Mux.scala:126:16] wire _io_busy_T_14; // @[XactTracker.scala:75:44] wire io_alloc_ready_0; // @[XactTracker.scala:56:7] wire [3:0] io_alloc_xactid_0; // @[XactTracker.scala:56:7] wire [5:0] io_peek_entry_shift_0; // @[XactTracker.scala:56:7] wire [13:0] io_peek_entry_addr_0; // @[XactTracker.scala:56:7] wire io_peek_entry_is_acc_0; // @[XactTracker.scala:56:7] wire io_peek_entry_accumulate_0; // @[XactTracker.scala:56:7] wire io_peek_entry_has_acc_bitwidth_0; // @[XactTracker.scala:56:7] wire [31:0] io_peek_entry_scale_0; // @[XactTracker.scala:56:7] wire [15:0] io_peek_entry_repeats_0; // @[XactTracker.scala:56:7] wire [7:0] io_peek_entry_pixel_repeats_0; // @[XactTracker.scala:56:7] wire [15:0] io_peek_entry_len_0; // @[XactTracker.scala:56:7] wire [15:0] io_peek_entry_block_stride_0; // @[XactTracker.scala:56:7] wire [8:0] io_peek_entry_spad_row_offset_0; // @[XactTracker.scala:56:7] wire [6:0] io_peek_entry_bytes_to_read_0; // @[XactTracker.scala:56:7] wire io_peek_entry_cmd_id_0; // @[XactTracker.scala:56:7] wire [31:0] io_counter_external_values_6_0; // @[XactTracker.scala:56:7] wire io_busy_0; // @[XactTracker.scala:56:7] reg entries_0_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_0_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_0_bits_addr; // @[XactTracker.scala:67:20] reg entries_0_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_0_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_0_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_0_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_0_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_0_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_0_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_0_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_0_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_0_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_0_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_1_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_1_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_1_bits_addr; // @[XactTracker.scala:67:20] reg entries_1_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_1_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_1_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_1_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_1_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_1_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_1_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_1_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_1_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_1_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_1_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_2_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_2_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_2_bits_addr; // @[XactTracker.scala:67:20] reg entries_2_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_2_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_2_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_2_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_2_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_2_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_2_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_2_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_2_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_2_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_2_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_3_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_3_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_3_bits_addr; // @[XactTracker.scala:67:20] reg entries_3_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_3_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_3_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_3_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_3_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_3_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_3_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_3_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_3_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_3_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_3_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_4_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_4_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_4_bits_addr; // @[XactTracker.scala:67:20] reg entries_4_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_4_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_4_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_4_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_4_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_4_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_4_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_4_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_4_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_4_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_4_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_5_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_5_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_5_bits_addr; // @[XactTracker.scala:67:20] reg entries_5_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_5_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_5_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_5_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_5_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_5_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_5_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_5_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_5_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_5_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_5_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_6_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_6_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_6_bits_addr; // @[XactTracker.scala:67:20] reg entries_6_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_6_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_6_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_6_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_6_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_6_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_6_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_6_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_6_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_6_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_6_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_7_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_7_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_7_bits_addr; // @[XactTracker.scala:67:20] reg entries_7_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_7_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_7_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_7_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_7_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_7_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_7_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_7_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_7_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_7_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_7_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_8_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_8_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_8_bits_addr; // @[XactTracker.scala:67:20] reg entries_8_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_8_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_8_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_8_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_8_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_8_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_8_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_8_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_8_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_8_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_8_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_9_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_9_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_9_bits_addr; // @[XactTracker.scala:67:20] reg entries_9_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_9_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_9_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_9_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_9_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_9_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_9_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_9_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_9_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_9_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_9_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_10_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_10_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_10_bits_addr; // @[XactTracker.scala:67:20] reg entries_10_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_10_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_10_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_10_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_10_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_10_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_10_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_10_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_10_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_10_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_10_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_11_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_11_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_11_bits_addr; // @[XactTracker.scala:67:20] reg entries_11_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_11_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_11_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_11_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_11_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_11_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_11_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_11_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_11_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_11_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_11_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_12_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_12_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_12_bits_addr; // @[XactTracker.scala:67:20] reg entries_12_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_12_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_12_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_12_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_12_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_12_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_12_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_12_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_12_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_12_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_12_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_13_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_13_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_13_bits_addr; // @[XactTracker.scala:67:20] reg entries_13_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_13_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_13_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_13_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_13_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_13_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_13_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_13_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_13_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_13_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_13_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_14_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_14_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_14_bits_addr; // @[XactTracker.scala:67:20] reg entries_14_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_14_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_14_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_14_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_14_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_14_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_14_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_14_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_14_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_14_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_14_bits_cmd_id; // @[XactTracker.scala:67:20] reg entries_15_valid; // @[XactTracker.scala:67:20] reg [5:0] entries_15_bits_shift; // @[XactTracker.scala:67:20] reg [13:0] entries_15_bits_addr; // @[XactTracker.scala:67:20] reg entries_15_bits_is_acc; // @[XactTracker.scala:67:20] reg entries_15_bits_accumulate; // @[XactTracker.scala:67:20] reg entries_15_bits_has_acc_bitwidth; // @[XactTracker.scala:67:20] reg [31:0] entries_15_bits_scale; // @[XactTracker.scala:67:20] reg [15:0] entries_15_bits_repeats; // @[XactTracker.scala:67:20] reg [7:0] entries_15_bits_pixel_repeats; // @[XactTracker.scala:67:20] reg [15:0] entries_15_bits_len; // @[XactTracker.scala:67:20] reg [15:0] entries_15_bits_block_stride; // @[XactTracker.scala:67:20] reg [8:0] entries_15_bits_spad_row_offset; // @[XactTracker.scala:67:20] reg [6:0] entries_15_bits_bytes_to_read; // @[XactTracker.scala:67:20] reg entries_15_bits_cmd_id; // @[XactTracker.scala:67:20] wire _free_entry_T = ~entries_0_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_1 = ~entries_1_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_2 = ~entries_2_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_3 = ~entries_3_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_4 = ~entries_4_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_5 = ~entries_5_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_6 = ~entries_6_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_7 = ~entries_7_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_8 = ~entries_8_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_9 = ~entries_9_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_10 = ~entries_10_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_11 = ~entries_11_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_12 = ~entries_12_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_13 = ~entries_13_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_14 = ~entries_14_valid; // @[XactTracker.scala:67:20, :69:84] wire _free_entry_T_15 = ~entries_15_valid; // @[XactTracker.scala:67:20, :69:84] wire [3:0] _free_entry_T_17 = {3'h7, ~_free_entry_T_14}; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_18 = _free_entry_T_13 ? 4'hD : _free_entry_T_17; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_19 = _free_entry_T_12 ? 4'hC : _free_entry_T_18; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_20 = _free_entry_T_11 ? 4'hB : _free_entry_T_19; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_21 = _free_entry_T_10 ? 4'hA : _free_entry_T_20; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_22 = _free_entry_T_9 ? 4'h9 : _free_entry_T_21; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_23 = _free_entry_T_8 ? 4'h8 : _free_entry_T_22; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_24 = _free_entry_T_7 ? 4'h7 : _free_entry_T_23; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_25 = _free_entry_T_6 ? 4'h6 : _free_entry_T_24; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_26 = _free_entry_T_5 ? 4'h5 : _free_entry_T_25; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_27 = _free_entry_T_4 ? 4'h4 : _free_entry_T_26; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_28 = _free_entry_T_3 ? 4'h3 : _free_entry_T_27; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_29 = _free_entry_T_2 ? 4'h2 : _free_entry_T_28; // @[Mux.scala:126:16] wire [3:0] _free_entry_T_30 = _free_entry_T_1 ? 4'h1 : _free_entry_T_29; // @[Mux.scala:126:16] assign free_entry = _free_entry_T ? 4'h0 : _free_entry_T_30; // @[Mux.scala:126:16] assign io_alloc_xactid_0 = free_entry; // @[Mux.scala:126:16] wire _io_alloc_ready_T = entries_0_valid & entries_1_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_1 = _io_alloc_ready_T & entries_2_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_2 = _io_alloc_ready_T_1 & entries_3_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_3 = _io_alloc_ready_T_2 & entries_4_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_4 = _io_alloc_ready_T_3 & entries_5_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_5 = _io_alloc_ready_T_4 & entries_6_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_6 = _io_alloc_ready_T_5 & entries_7_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_7 = _io_alloc_ready_T_6 & entries_8_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_8 = _io_alloc_ready_T_7 & entries_9_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_9 = _io_alloc_ready_T_8 & entries_10_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_10 = _io_alloc_ready_T_9 & entries_11_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_11 = _io_alloc_ready_T_10 & entries_12_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_12 = _io_alloc_ready_T_11 & entries_13_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_13 = _io_alloc_ready_T_12 & entries_14_valid; // @[XactTracker.scala:67:20, :70:52] wire _io_alloc_ready_T_14 = _io_alloc_ready_T_13 & entries_15_valid; // @[XactTracker.scala:67:20, :70:52] assign _io_alloc_ready_T_15 = ~_io_alloc_ready_T_14; // @[XactTracker.scala:70:{21,52}] assign io_alloc_ready_0 = _io_alloc_ready_T_15; // @[XactTracker.scala:56:7, :70:21] wire [15:0] _GEN = {{entries_15_valid}, {entries_14_valid}, {entries_13_valid}, {entries_12_valid}, {entries_11_valid}, {entries_10_valid}, {entries_9_valid}, {entries_8_valid}, {entries_7_valid}, {entries_6_valid}, {entries_5_valid}, {entries_4_valid}, {entries_3_valid}, {entries_2_valid}, {entries_1_valid}, {entries_0_valid}}; // @[XactTracker.scala:67:20, :73:17] wire [15:0][5:0] _GEN_0 = {{entries_15_bits_shift}, {entries_14_bits_shift}, {entries_13_bits_shift}, {entries_12_bits_shift}, {entries_11_bits_shift}, {entries_10_bits_shift}, {entries_9_bits_shift}, {entries_8_bits_shift}, {entries_7_bits_shift}, {entries_6_bits_shift}, {entries_5_bits_shift}, {entries_4_bits_shift}, {entries_3_bits_shift}, {entries_2_bits_shift}, {entries_1_bits_shift}, {entries_0_bits_shift}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_shift_0 = _GEN_0[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0][13:0] _GEN_1 = {{entries_15_bits_addr}, {entries_14_bits_addr}, {entries_13_bits_addr}, {entries_12_bits_addr}, {entries_11_bits_addr}, {entries_10_bits_addr}, {entries_9_bits_addr}, {entries_8_bits_addr}, {entries_7_bits_addr}, {entries_6_bits_addr}, {entries_5_bits_addr}, {entries_4_bits_addr}, {entries_3_bits_addr}, {entries_2_bits_addr}, {entries_1_bits_addr}, {entries_0_bits_addr}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_addr_0 = _GEN_1[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0] _GEN_2 = {{entries_15_bits_is_acc}, {entries_14_bits_is_acc}, {entries_13_bits_is_acc}, {entries_12_bits_is_acc}, {entries_11_bits_is_acc}, {entries_10_bits_is_acc}, {entries_9_bits_is_acc}, {entries_8_bits_is_acc}, {entries_7_bits_is_acc}, {entries_6_bits_is_acc}, {entries_5_bits_is_acc}, {entries_4_bits_is_acc}, {entries_3_bits_is_acc}, {entries_2_bits_is_acc}, {entries_1_bits_is_acc}, {entries_0_bits_is_acc}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_is_acc_0 = _GEN_2[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0] _GEN_3 = {{entries_15_bits_accumulate}, {entries_14_bits_accumulate}, {entries_13_bits_accumulate}, {entries_12_bits_accumulate}, {entries_11_bits_accumulate}, {entries_10_bits_accumulate}, {entries_9_bits_accumulate}, {entries_8_bits_accumulate}, {entries_7_bits_accumulate}, {entries_6_bits_accumulate}, {entries_5_bits_accumulate}, {entries_4_bits_accumulate}, {entries_3_bits_accumulate}, {entries_2_bits_accumulate}, {entries_1_bits_accumulate}, {entries_0_bits_accumulate}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_accumulate_0 = _GEN_3[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0] _GEN_4 = {{entries_15_bits_has_acc_bitwidth}, {entries_14_bits_has_acc_bitwidth}, {entries_13_bits_has_acc_bitwidth}, {entries_12_bits_has_acc_bitwidth}, {entries_11_bits_has_acc_bitwidth}, {entries_10_bits_has_acc_bitwidth}, {entries_9_bits_has_acc_bitwidth}, {entries_8_bits_has_acc_bitwidth}, {entries_7_bits_has_acc_bitwidth}, {entries_6_bits_has_acc_bitwidth}, {entries_5_bits_has_acc_bitwidth}, {entries_4_bits_has_acc_bitwidth}, {entries_3_bits_has_acc_bitwidth}, {entries_2_bits_has_acc_bitwidth}, {entries_1_bits_has_acc_bitwidth}, {entries_0_bits_has_acc_bitwidth}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_has_acc_bitwidth_0 = _GEN_4[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0][31:0] _GEN_5 = {{entries_15_bits_scale}, {entries_14_bits_scale}, {entries_13_bits_scale}, {entries_12_bits_scale}, {entries_11_bits_scale}, {entries_10_bits_scale}, {entries_9_bits_scale}, {entries_8_bits_scale}, {entries_7_bits_scale}, {entries_6_bits_scale}, {entries_5_bits_scale}, {entries_4_bits_scale}, {entries_3_bits_scale}, {entries_2_bits_scale}, {entries_1_bits_scale}, {entries_0_bits_scale}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_scale_0 = _GEN_5[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0][15:0] _GEN_6 = {{entries_15_bits_repeats}, {entries_14_bits_repeats}, {entries_13_bits_repeats}, {entries_12_bits_repeats}, {entries_11_bits_repeats}, {entries_10_bits_repeats}, {entries_9_bits_repeats}, {entries_8_bits_repeats}, {entries_7_bits_repeats}, {entries_6_bits_repeats}, {entries_5_bits_repeats}, {entries_4_bits_repeats}, {entries_3_bits_repeats}, {entries_2_bits_repeats}, {entries_1_bits_repeats}, {entries_0_bits_repeats}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_repeats_0 = _GEN_6[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0][7:0] _GEN_7 = {{entries_15_bits_pixel_repeats}, {entries_14_bits_pixel_repeats}, {entries_13_bits_pixel_repeats}, {entries_12_bits_pixel_repeats}, {entries_11_bits_pixel_repeats}, {entries_10_bits_pixel_repeats}, {entries_9_bits_pixel_repeats}, {entries_8_bits_pixel_repeats}, {entries_7_bits_pixel_repeats}, {entries_6_bits_pixel_repeats}, {entries_5_bits_pixel_repeats}, {entries_4_bits_pixel_repeats}, {entries_3_bits_pixel_repeats}, {entries_2_bits_pixel_repeats}, {entries_1_bits_pixel_repeats}, {entries_0_bits_pixel_repeats}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_pixel_repeats_0 = _GEN_7[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0][15:0] _GEN_8 = {{entries_15_bits_len}, {entries_14_bits_len}, {entries_13_bits_len}, {entries_12_bits_len}, {entries_11_bits_len}, {entries_10_bits_len}, {entries_9_bits_len}, {entries_8_bits_len}, {entries_7_bits_len}, {entries_6_bits_len}, {entries_5_bits_len}, {entries_4_bits_len}, {entries_3_bits_len}, {entries_2_bits_len}, {entries_1_bits_len}, {entries_0_bits_len}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_len_0 = _GEN_8[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0][15:0] _GEN_9 = {{entries_15_bits_block_stride}, {entries_14_bits_block_stride}, {entries_13_bits_block_stride}, {entries_12_bits_block_stride}, {entries_11_bits_block_stride}, {entries_10_bits_block_stride}, {entries_9_bits_block_stride}, {entries_8_bits_block_stride}, {entries_7_bits_block_stride}, {entries_6_bits_block_stride}, {entries_5_bits_block_stride}, {entries_4_bits_block_stride}, {entries_3_bits_block_stride}, {entries_2_bits_block_stride}, {entries_1_bits_block_stride}, {entries_0_bits_block_stride}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_block_stride_0 = _GEN_9[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0][8:0] _GEN_10 = {{entries_15_bits_spad_row_offset}, {entries_14_bits_spad_row_offset}, {entries_13_bits_spad_row_offset}, {entries_12_bits_spad_row_offset}, {entries_11_bits_spad_row_offset}, {entries_10_bits_spad_row_offset}, {entries_9_bits_spad_row_offset}, {entries_8_bits_spad_row_offset}, {entries_7_bits_spad_row_offset}, {entries_6_bits_spad_row_offset}, {entries_5_bits_spad_row_offset}, {entries_4_bits_spad_row_offset}, {entries_3_bits_spad_row_offset}, {entries_2_bits_spad_row_offset}, {entries_1_bits_spad_row_offset}, {entries_0_bits_spad_row_offset}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_spad_row_offset_0 = _GEN_10[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0][6:0] _GEN_11 = {{entries_15_bits_bytes_to_read}, {entries_14_bits_bytes_to_read}, {entries_13_bits_bytes_to_read}, {entries_12_bits_bytes_to_read}, {entries_11_bits_bytes_to_read}, {entries_10_bits_bytes_to_read}, {entries_9_bits_bytes_to_read}, {entries_8_bits_bytes_to_read}, {entries_7_bits_bytes_to_read}, {entries_6_bits_bytes_to_read}, {entries_5_bits_bytes_to_read}, {entries_4_bits_bytes_to_read}, {entries_3_bits_bytes_to_read}, {entries_2_bits_bytes_to_read}, {entries_1_bits_bytes_to_read}, {entries_0_bits_bytes_to_read}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_bytes_to_read_0 = _GEN_11[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire [15:0] _GEN_12 = {{entries_15_bits_cmd_id}, {entries_14_bits_cmd_id}, {entries_13_bits_cmd_id}, {entries_12_bits_cmd_id}, {entries_11_bits_cmd_id}, {entries_10_bits_cmd_id}, {entries_9_bits_cmd_id}, {entries_8_bits_cmd_id}, {entries_7_bits_cmd_id}, {entries_6_bits_cmd_id}, {entries_5_bits_cmd_id}, {entries_4_bits_cmd_id}, {entries_3_bits_cmd_id}, {entries_2_bits_cmd_id}, {entries_1_bits_cmd_id}, {entries_0_bits_cmd_id}}; // @[XactTracker.scala:67:20, :73:17] assign io_peek_entry_cmd_id_0 = _GEN_12[io_peek_xactid_0]; // @[XactTracker.scala:56:7, :73:17] wire _io_busy_T = entries_0_valid | entries_1_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_1 = _io_busy_T | entries_2_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_2 = _io_busy_T_1 | entries_3_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_3 = _io_busy_T_2 | entries_4_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_4 = _io_busy_T_3 | entries_5_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_5 = _io_busy_T_4 | entries_6_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_6 = _io_busy_T_5 | entries_7_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_7 = _io_busy_T_6 | entries_8_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_8 = _io_busy_T_7 | entries_9_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_9 = _io_busy_T_8 | entries_10_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_10 = _io_busy_T_9 | entries_11_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_11 = _io_busy_T_10 | entries_12_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_12 = _io_busy_T_11 | entries_13_valid; // @[XactTracker.scala:67:20, :75:44] wire _io_busy_T_13 = _io_busy_T_12 | entries_14_valid; // @[XactTracker.scala:67:20, :75:44] assign _io_busy_T_14 = _io_busy_T_13 | entries_15_valid; // @[XactTracker.scala:67:20, :75:44] assign io_busy_0 = _io_busy_T_14; // @[XactTracker.scala:56:7, :75:44] wire _GEN_13 = io_peek_pop_0 & ~reset; // @[XactTracker.scala:56:7, :84:11]
Generate the Verilog code corresponding to this FIRRTL code module FPToInt : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock when io.in.valid : connect in, io.in.bits reg valid : UInt<1>, clock connect valid, io.in.valid inst dcmp of CompareRecFN connect dcmp.io.a, in.in1 connect dcmp.io.b, in.in2 node _dcmp_io_signaling_T = bits(in.rm, 1, 1) node _dcmp_io_signaling_T_1 = eq(_dcmp_io_signaling_T, UInt<1>(0h0)) connect dcmp.io.signaling, _dcmp_io_signaling_T_1 node toint_ieee_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 9) node toint_ieee_unrecoded_rawIn_isZero = eq(_toint_ieee_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_unrecoded_rawIn_exp, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_unrecoded_rawIn.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_unrecoded_rawIn_exp, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_unrecoded_rawIn_isSpecial, _toint_ieee_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_unrecoded_rawIn.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_unrecoded_rawIn.isZero, toint_ieee_unrecoded_rawIn_isZero node _toint_ieee_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn.sign, _toint_ieee_unrecoded_rawIn_out_sign_T node _toint_ieee_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_unrecoded_rawIn_exp) connect toint_ieee_unrecoded_rawIn.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T node _toint_ieee_unrecoded_rawIn_out_sig_T = eq(toint_ieee_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T) node _toint_ieee_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_unrecoded_rawIn.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_3 node toint_ieee_unrecoded_isSubnormal = lt(toint_ieee_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T = bits(toint_ieee_unrecoded_rawIn.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T) node toint_ieee_unrecoded_denormShiftDist = tail(_toint_ieee_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_unrecoded_denormFract_T = shr(toint_ieee_unrecoded_rawIn.sig, 1) node _toint_ieee_unrecoded_denormFract_T_1 = dshr(_toint_ieee_unrecoded_denormFract_T, toint_ieee_unrecoded_denormShiftDist) node toint_ieee_unrecoded_denormFract = bits(_toint_ieee_unrecoded_denormFract_T_1, 51, 0) node _toint_ieee_unrecoded_expOut_T = bits(toint_ieee_unrecoded_rawIn.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_1 = sub(_toint_ieee_unrecoded_expOut_T, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_2 = tail(_toint_ieee_unrecoded_expOut_T_1, 1) node _toint_ieee_unrecoded_expOut_T_3 = mux(toint_ieee_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_2) node _toint_ieee_unrecoded_expOut_T_4 = or(toint_ieee_unrecoded_rawIn.isNaN, toint_ieee_unrecoded_rawIn.isInf) node _toint_ieee_unrecoded_expOut_T_5 = mux(_toint_ieee_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut = or(_toint_ieee_unrecoded_expOut_T_3, _toint_ieee_unrecoded_expOut_T_5) node _toint_ieee_unrecoded_fractOut_T = bits(toint_ieee_unrecoded_rawIn.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_1 = mux(toint_ieee_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T) node toint_ieee_unrecoded_fractOut = mux(toint_ieee_unrecoded_isSubnormal, toint_ieee_unrecoded_denormFract, _toint_ieee_unrecoded_fractOut_T_1) node toint_ieee_unrecoded_hi = cat(toint_ieee_unrecoded_rawIn.sign, toint_ieee_unrecoded_expOut) node toint_ieee_unrecoded = cat(toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut) node _toint_ieee_prevRecoded_T = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_1 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_2 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi = cat(_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1) node toint_ieee_prevRecoded = cat(toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = bits(toint_ieee_prevRecoded, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_unrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(toint_ieee_prevRecoded, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevRecoded, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_unrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T) node toint_ieee_prevUnrecoded_unrecoded_fractOut = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal, toint_ieee_prevUnrecoded_unrecoded_denormFract, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_unrecoded_hi = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn.sign, toint_ieee_prevUnrecoded_unrecoded_expOut) node toint_ieee_prevUnrecoded_unrecoded = cat(toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut) node _toint_ieee_prevUnrecoded_prevRecoded_T = bits(toint_ieee_prevRecoded, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_1 = bits(toint_ieee_prevRecoded, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_2 = bits(toint_ieee_prevRecoded, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi = cat(_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1) node toint_ieee_prevUnrecoded_prevRecoded = cat(toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(toint_ieee_prevUnrecoded_prevRecoded, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(toint_ieee_prevUnrecoded_prevRecoded, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1) node toint_ieee_prevUnrecoded_prevUnrecoded_hi = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut) node toint_ieee_prevUnrecoded_prevUnrecoded = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut) node _toint_ieee_prevUnrecoded_T = shr(toint_ieee_prevUnrecoded_unrecoded, 16) node _toint_ieee_prevUnrecoded_T_1 = bits(toint_ieee_prevRecoded, 31, 29) node _toint_ieee_prevUnrecoded_T_2 = andr(_toint_ieee_prevUnrecoded_T_1) node _toint_ieee_prevUnrecoded_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded, 15, 0) node _toint_ieee_prevUnrecoded_T_4 = mux(_toint_ieee_prevUnrecoded_T_2, toint_ieee_prevUnrecoded_prevUnrecoded, _toint_ieee_prevUnrecoded_T_3) node toint_ieee_prevUnrecoded = cat(_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4) node _toint_ieee_T = shr(toint_ieee_unrecoded, 32) node _toint_ieee_T_1 = bits(in.in1, 63, 61) node _toint_ieee_T_2 = andr(_toint_ieee_T_1) node _toint_ieee_T_3 = bits(toint_ieee_unrecoded, 31, 0) node _toint_ieee_T_4 = mux(_toint_ieee_T_2, toint_ieee_prevUnrecoded, _toint_ieee_T_3) node _toint_ieee_T_5 = cat(_toint_ieee_T, _toint_ieee_T_4) node _toint_ieee_T_6 = bits(_toint_ieee_T_5, 15, 0) node _toint_ieee_T_7 = bits(_toint_ieee_T_6, 15, 15) node _toint_ieee_T_8 = mux(_toint_ieee_T_7, UInt<16>(0hffff), UInt<16>(0h0)) node _toint_ieee_T_9 = cat(_toint_ieee_T_8, _toint_ieee_T_6) node _toint_ieee_T_10 = cat(_toint_ieee_T_9, _toint_ieee_T_9) node toint_ieee_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_unrecoded_rawIn_exp_1, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_unrecoded_rawIn_1.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_unrecoded_rawIn_exp_1, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_1, _toint_ieee_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_unrecoded_rawIn_1.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_unrecoded_rawIn_1.isZero, toint_ieee_unrecoded_rawIn_isZero_1 node _toint_ieee_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_1.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_unrecoded_rawIn_exp_1) connect toint_ieee_unrecoded_rawIn_1.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_unrecoded_rawIn_1.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_7 node toint_ieee_unrecoded_isSubnormal_1 = lt(toint_ieee_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_2) node toint_ieee_unrecoded_denormShiftDist_1 = tail(_toint_ieee_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_unrecoded_denormFract_T_2 = shr(toint_ieee_unrecoded_rawIn_1.sig, 1) node _toint_ieee_unrecoded_denormFract_T_3 = dshr(_toint_ieee_unrecoded_denormFract_T_2, toint_ieee_unrecoded_denormShiftDist_1) node toint_ieee_unrecoded_denormFract_1 = bits(_toint_ieee_unrecoded_denormFract_T_3, 51, 0) node _toint_ieee_unrecoded_expOut_T_6 = bits(toint_ieee_unrecoded_rawIn_1.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_7 = sub(_toint_ieee_unrecoded_expOut_T_6, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_8 = tail(_toint_ieee_unrecoded_expOut_T_7, 1) node _toint_ieee_unrecoded_expOut_T_9 = mux(toint_ieee_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_8) node _toint_ieee_unrecoded_expOut_T_10 = or(toint_ieee_unrecoded_rawIn_1.isNaN, toint_ieee_unrecoded_rawIn_1.isInf) node _toint_ieee_unrecoded_expOut_T_11 = mux(_toint_ieee_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_1 = or(_toint_ieee_unrecoded_expOut_T_9, _toint_ieee_unrecoded_expOut_T_11) node _toint_ieee_unrecoded_fractOut_T_2 = bits(toint_ieee_unrecoded_rawIn_1.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_3 = mux(toint_ieee_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_2) node toint_ieee_unrecoded_fractOut_1 = mux(toint_ieee_unrecoded_isSubnormal_1, toint_ieee_unrecoded_denormFract_1, _toint_ieee_unrecoded_fractOut_T_3) node toint_ieee_unrecoded_hi_1 = cat(toint_ieee_unrecoded_rawIn_1.sign, toint_ieee_unrecoded_expOut_1) node toint_ieee_unrecoded_1 = cat(toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1) node _toint_ieee_prevRecoded_T_3 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_4 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_5 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_1 = cat(_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4) node toint_ieee_prevRecoded_1 = cat(toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(toint_ieee_prevRecoded_1, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevRecoded_1, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevRecoded_1, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_unrecoded_denormFract_1, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_unrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1) node toint_ieee_prevUnrecoded_unrecoded_1 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_prevRecoded_T_3 = bits(toint_ieee_prevRecoded_1, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_4 = bits(toint_ieee_prevRecoded_1, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_5 = bits(toint_ieee_prevRecoded_1, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_1 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4) node toint_ieee_prevUnrecoded_prevRecoded_1 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(toint_ieee_prevUnrecoded_prevRecoded_1, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1) node toint_ieee_prevUnrecoded_prevUnrecoded_1 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1) node _toint_ieee_prevUnrecoded_T_5 = shr(toint_ieee_prevUnrecoded_unrecoded_1, 16) node _toint_ieee_prevUnrecoded_T_6 = bits(toint_ieee_prevRecoded_1, 31, 29) node _toint_ieee_prevUnrecoded_T_7 = andr(_toint_ieee_prevUnrecoded_T_6) node _toint_ieee_prevUnrecoded_T_8 = bits(toint_ieee_prevUnrecoded_unrecoded_1, 15, 0) node _toint_ieee_prevUnrecoded_T_9 = mux(_toint_ieee_prevUnrecoded_T_7, toint_ieee_prevUnrecoded_prevUnrecoded_1, _toint_ieee_prevUnrecoded_T_8) node toint_ieee_prevUnrecoded_1 = cat(_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9) node _toint_ieee_T_11 = shr(toint_ieee_unrecoded_1, 32) node _toint_ieee_T_12 = bits(in.in1, 63, 61) node _toint_ieee_T_13 = andr(_toint_ieee_T_12) node _toint_ieee_T_14 = bits(toint_ieee_unrecoded_1, 31, 0) node _toint_ieee_T_15 = mux(_toint_ieee_T_13, toint_ieee_prevUnrecoded_1, _toint_ieee_T_14) node _toint_ieee_T_16 = cat(_toint_ieee_T_11, _toint_ieee_T_15) node _toint_ieee_T_17 = bits(_toint_ieee_T_16, 31, 0) node _toint_ieee_T_18 = cat(_toint_ieee_T_17, _toint_ieee_T_17) node toint_ieee_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _toint_ieee_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 9) node toint_ieee_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_unrecoded_rawIn_exp_2, 11, 10) node toint_ieee_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_unrecoded_rawIn_2.isNaN, _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_unrecoded_rawIn_exp_2, 9, 9) node _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_unrecoded_rawIn_isSpecial_2, _toint_ieee_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_unrecoded_rawIn_2.isInf, _toint_ieee_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_unrecoded_rawIn_2.isZero, toint_ieee_unrecoded_rawIn_isZero_2 node _toint_ieee_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect toint_ieee_unrecoded_rawIn_2.sign, _toint_ieee_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_unrecoded_rawIn_exp_2) connect toint_ieee_unrecoded_rawIn_2.sExp, _toint_ieee_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _toint_ieee_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_unrecoded_rawIn_2.sig, _toint_ieee_unrecoded_rawIn_out_sig_T_11 node toint_ieee_unrecoded_isSubnormal_2 = lt(toint_ieee_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _toint_ieee_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 5, 0) node _toint_ieee_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_unrecoded_denormShiftDist_T_4) node toint_ieee_unrecoded_denormShiftDist_2 = tail(_toint_ieee_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_unrecoded_denormFract_T_4 = shr(toint_ieee_unrecoded_rawIn_2.sig, 1) node _toint_ieee_unrecoded_denormFract_T_5 = dshr(_toint_ieee_unrecoded_denormFract_T_4, toint_ieee_unrecoded_denormShiftDist_2) node toint_ieee_unrecoded_denormFract_2 = bits(_toint_ieee_unrecoded_denormFract_T_5, 51, 0) node _toint_ieee_unrecoded_expOut_T_12 = bits(toint_ieee_unrecoded_rawIn_2.sExp, 10, 0) node _toint_ieee_unrecoded_expOut_T_13 = sub(_toint_ieee_unrecoded_expOut_T_12, UInt<11>(0h401)) node _toint_ieee_unrecoded_expOut_T_14 = tail(_toint_ieee_unrecoded_expOut_T_13, 1) node _toint_ieee_unrecoded_expOut_T_15 = mux(toint_ieee_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_unrecoded_expOut_T_14) node _toint_ieee_unrecoded_expOut_T_16 = or(toint_ieee_unrecoded_rawIn_2.isNaN, toint_ieee_unrecoded_rawIn_2.isInf) node _toint_ieee_unrecoded_expOut_T_17 = mux(_toint_ieee_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node toint_ieee_unrecoded_expOut_2 = or(_toint_ieee_unrecoded_expOut_T_15, _toint_ieee_unrecoded_expOut_T_17) node _toint_ieee_unrecoded_fractOut_T_4 = bits(toint_ieee_unrecoded_rawIn_2.sig, 51, 0) node _toint_ieee_unrecoded_fractOut_T_5 = mux(toint_ieee_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_unrecoded_fractOut_T_4) node toint_ieee_unrecoded_fractOut_2 = mux(toint_ieee_unrecoded_isSubnormal_2, toint_ieee_unrecoded_denormFract_2, _toint_ieee_unrecoded_fractOut_T_5) node toint_ieee_unrecoded_hi_2 = cat(toint_ieee_unrecoded_rawIn_2.sign, toint_ieee_unrecoded_expOut_2) node toint_ieee_unrecoded_2 = cat(toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2) node _toint_ieee_prevRecoded_T_6 = bits(in.in1, 31, 31) node _toint_ieee_prevRecoded_T_7 = bits(in.in1, 52, 52) node _toint_ieee_prevRecoded_T_8 = bits(in.in1, 30, 0) node toint_ieee_prevRecoded_hi_2 = cat(_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7) node toint_ieee_prevRecoded_2 = cat(toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8) node toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(toint_ieee_prevRecoded_2, 31, 23) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevRecoded_2, 32, 32) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevRecoded_2, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node toint_ieee_prevUnrecoded_unrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_unrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_unrecoded_denormFract_2, _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_unrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_unrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2) node toint_ieee_prevUnrecoded_unrecoded_2 = cat(toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_prevRecoded_T_6 = bits(toint_ieee_prevRecoded_2, 15, 15) node _toint_ieee_prevUnrecoded_prevRecoded_T_7 = bits(toint_ieee_prevRecoded_2, 23, 23) node _toint_ieee_prevUnrecoded_prevRecoded_T_8 = bits(toint_ieee_prevRecoded_2, 14, 0) node toint_ieee_prevUnrecoded_prevRecoded_hi_2 = cat(_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7) node toint_ieee_prevUnrecoded_prevRecoded_2 = cat(toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 15, 10) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 16, 16) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(toint_ieee_prevUnrecoded_prevRecoded_2, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4, toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = or(_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4) node toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2, toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2, _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5) node toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2.sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2) node toint_ieee_prevUnrecoded_prevUnrecoded_2 = cat(toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2) node _toint_ieee_prevUnrecoded_T_10 = shr(toint_ieee_prevUnrecoded_unrecoded_2, 16) node _toint_ieee_prevUnrecoded_T_11 = bits(toint_ieee_prevRecoded_2, 31, 29) node _toint_ieee_prevUnrecoded_T_12 = andr(_toint_ieee_prevUnrecoded_T_11) node _toint_ieee_prevUnrecoded_T_13 = bits(toint_ieee_prevUnrecoded_unrecoded_2, 15, 0) node _toint_ieee_prevUnrecoded_T_14 = mux(_toint_ieee_prevUnrecoded_T_12, toint_ieee_prevUnrecoded_prevUnrecoded_2, _toint_ieee_prevUnrecoded_T_13) node toint_ieee_prevUnrecoded_2 = cat(_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14) node _toint_ieee_T_19 = shr(toint_ieee_unrecoded_2, 32) node _toint_ieee_T_20 = bits(in.in1, 63, 61) node _toint_ieee_T_21 = andr(_toint_ieee_T_20) node _toint_ieee_T_22 = bits(toint_ieee_unrecoded_2, 31, 0) node _toint_ieee_T_23 = mux(_toint_ieee_T_21, toint_ieee_prevUnrecoded_2, _toint_ieee_T_22) node _toint_ieee_T_24 = cat(_toint_ieee_T_19, _toint_ieee_T_23) node _toint_ieee_T_25 = bits(_toint_ieee_T_24, 63, 0) node _toint_ieee_T_26 = eq(in.typeTagOut, UInt<1>(0h1)) node _toint_ieee_T_27 = mux(_toint_ieee_T_26, _toint_ieee_T_18, _toint_ieee_T_10) node _toint_ieee_T_28 = eq(in.typeTagOut, UInt<2>(0h2)) node _toint_ieee_T_29 = mux(_toint_ieee_T_28, _toint_ieee_T_25, _toint_ieee_T_27) node _toint_ieee_T_30 = eq(in.typeTagOut, UInt<2>(0h3)) node toint_ieee = mux(_toint_ieee_T_30, _toint_ieee_T_25, _toint_ieee_T_29) wire toint : UInt connect toint, toint_ieee node _intType_T = bits(in.fmt, 0, 0) wire intType : UInt<1> connect intType, _intType_T node io_out_bits_store_unrecoded_rawIn_exp = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_unrecoded_rawIn.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_unrecoded_rawIn_exp, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_unrecoded_rawIn_isSpecial, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_unrecoded_rawIn.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_unrecoded_rawIn.isZero, io_out_bits_store_unrecoded_rawIn_isZero node _io_out_bits_store_unrecoded_rawIn_out_sign_T = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T node _io_out_bits_store_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_unrecoded_rawIn_exp) connect io_out_bits_store_unrecoded_rawIn.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_unrecoded_rawIn.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_unrecoded_isSubnormal = lt(io_out_bits_store_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T) node io_out_bits_store_unrecoded_denormShiftDist = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_unrecoded_denormFract_T = shr(io_out_bits_store_unrecoded_rawIn.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_unrecoded_denormFract_T, io_out_bits_store_unrecoded_denormShiftDist) node io_out_bits_store_unrecoded_denormFract = bits(_io_out_bits_store_unrecoded_denormFract_T_1, 51, 0) node _io_out_bits_store_unrecoded_expOut_T = bits(io_out_bits_store_unrecoded_rawIn.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_1 = sub(_io_out_bits_store_unrecoded_expOut_T, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_2 = tail(_io_out_bits_store_unrecoded_expOut_T_1, 1) node _io_out_bits_store_unrecoded_expOut_T_3 = mux(io_out_bits_store_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_2) node _io_out_bits_store_unrecoded_expOut_T_4 = or(io_out_bits_store_unrecoded_rawIn.isNaN, io_out_bits_store_unrecoded_rawIn.isInf) node _io_out_bits_store_unrecoded_expOut_T_5 = mux(_io_out_bits_store_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut = or(_io_out_bits_store_unrecoded_expOut_T_3, _io_out_bits_store_unrecoded_expOut_T_5) node _io_out_bits_store_unrecoded_fractOut_T = bits(io_out_bits_store_unrecoded_rawIn.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_1 = mux(io_out_bits_store_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T) node io_out_bits_store_unrecoded_fractOut = mux(io_out_bits_store_unrecoded_isSubnormal, io_out_bits_store_unrecoded_denormFract, _io_out_bits_store_unrecoded_fractOut_T_1) node io_out_bits_store_unrecoded_hi = cat(io_out_bits_store_unrecoded_rawIn.sign, io_out_bits_store_unrecoded_expOut) node io_out_bits_store_unrecoded = cat(io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut) node _io_out_bits_store_prevRecoded_T = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_1 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_2 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi = cat(_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1) node io_out_bits_store_prevRecoded = cat(io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = bits(io_out_bits_store_prevRecoded, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevRecoded, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevRecoded, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_unrecoded_denormFract, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_unrecoded_hi = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut) node io_out_bits_store_prevUnrecoded_unrecoded = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_prevRecoded_T = bits(io_out_bits_store_prevRecoded, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = bits(io_out_bits_store_prevRecoded, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = bits(io_out_bits_store_prevRecoded, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1) node io_out_bits_store_prevUnrecoded_prevRecoded = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut) node io_out_bits_store_prevUnrecoded_prevUnrecoded = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut) node _io_out_bits_store_prevUnrecoded_T = shr(io_out_bits_store_prevUnrecoded_unrecoded, 16) node _io_out_bits_store_prevUnrecoded_T_1 = bits(io_out_bits_store_prevRecoded, 31, 29) node _io_out_bits_store_prevUnrecoded_T_2 = andr(_io_out_bits_store_prevUnrecoded_T_1) node _io_out_bits_store_prevUnrecoded_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded, 15, 0) node _io_out_bits_store_prevUnrecoded_T_4 = mux(_io_out_bits_store_prevUnrecoded_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded, _io_out_bits_store_prevUnrecoded_T_3) node io_out_bits_store_prevUnrecoded = cat(_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4) node _io_out_bits_store_T = shr(io_out_bits_store_unrecoded, 32) node _io_out_bits_store_T_1 = bits(in.in1, 63, 61) node _io_out_bits_store_T_2 = andr(_io_out_bits_store_T_1) node _io_out_bits_store_T_3 = bits(io_out_bits_store_unrecoded, 31, 0) node _io_out_bits_store_T_4 = mux(_io_out_bits_store_T_2, io_out_bits_store_prevUnrecoded, _io_out_bits_store_T_3) node _io_out_bits_store_T_5 = cat(_io_out_bits_store_T, _io_out_bits_store_T_4) node _io_out_bits_store_T_6 = bits(_io_out_bits_store_T_5, 15, 0) node _io_out_bits_store_T_7 = cat(_io_out_bits_store_T_6, _io_out_bits_store_T_6) node _io_out_bits_store_T_8 = cat(_io_out_bits_store_T_7, _io_out_bits_store_T_7) node io_out_bits_store_unrecoded_rawIn_exp_1 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_unrecoded_rawIn_1.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_unrecoded_rawIn_exp_1, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_unrecoded_rawIn_1.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_unrecoded_rawIn_1.isZero, io_out_bits_store_unrecoded_rawIn_isZero_1 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_1.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_unrecoded_rawIn_exp_1) connect io_out_bits_store_unrecoded_rawIn_1.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_unrecoded_rawIn_1.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_unrecoded_isSubnormal_1 = lt(io_out_bits_store_unrecoded_rawIn_1.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_2) node io_out_bits_store_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_unrecoded_denormFract_T_2 = shr(io_out_bits_store_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_unrecoded_denormFract_T_2, io_out_bits_store_unrecoded_denormShiftDist_1) node io_out_bits_store_unrecoded_denormFract_1 = bits(_io_out_bits_store_unrecoded_denormFract_T_3, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_6 = bits(io_out_bits_store_unrecoded_rawIn_1.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_7 = sub(_io_out_bits_store_unrecoded_expOut_T_6, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_8 = tail(_io_out_bits_store_unrecoded_expOut_T_7, 1) node _io_out_bits_store_unrecoded_expOut_T_9 = mux(io_out_bits_store_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_8) node _io_out_bits_store_unrecoded_expOut_T_10 = or(io_out_bits_store_unrecoded_rawIn_1.isNaN, io_out_bits_store_unrecoded_rawIn_1.isInf) node _io_out_bits_store_unrecoded_expOut_T_11 = mux(_io_out_bits_store_unrecoded_expOut_T_10, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_1 = or(_io_out_bits_store_unrecoded_expOut_T_9, _io_out_bits_store_unrecoded_expOut_T_11) node _io_out_bits_store_unrecoded_fractOut_T_2 = bits(io_out_bits_store_unrecoded_rawIn_1.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_3 = mux(io_out_bits_store_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_2) node io_out_bits_store_unrecoded_fractOut_1 = mux(io_out_bits_store_unrecoded_isSubnormal_1, io_out_bits_store_unrecoded_denormFract_1, _io_out_bits_store_unrecoded_fractOut_T_3) node io_out_bits_store_unrecoded_hi_1 = cat(io_out_bits_store_unrecoded_rawIn_1.sign, io_out_bits_store_unrecoded_expOut_1) node io_out_bits_store_unrecoded_1 = cat(io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1) node _io_out_bits_store_prevRecoded_T_3 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_4 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_5 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_1 = cat(_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4) node io_out_bits_store_prevRecoded_1 = cat(io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevRecoded_1, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevRecoded_1, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevRecoded_1, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_unrecoded_1 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = bits(io_out_bits_store_prevRecoded_1, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = bits(io_out_bits_store_prevRecoded_1, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = bits(io_out_bits_store_prevRecoded_1, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4) node io_out_bits_store_prevUnrecoded_prevRecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_1, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1) node io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1) node _io_out_bits_store_prevUnrecoded_T_5 = shr(io_out_bits_store_prevUnrecoded_unrecoded_1, 16) node _io_out_bits_store_prevUnrecoded_T_6 = bits(io_out_bits_store_prevRecoded_1, 31, 29) node _io_out_bits_store_prevUnrecoded_T_7 = andr(_io_out_bits_store_prevUnrecoded_T_6) node _io_out_bits_store_prevUnrecoded_T_8 = bits(io_out_bits_store_prevUnrecoded_unrecoded_1, 15, 0) node _io_out_bits_store_prevUnrecoded_T_9 = mux(_io_out_bits_store_prevUnrecoded_T_7, io_out_bits_store_prevUnrecoded_prevUnrecoded_1, _io_out_bits_store_prevUnrecoded_T_8) node io_out_bits_store_prevUnrecoded_1 = cat(_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9) node _io_out_bits_store_T_9 = shr(io_out_bits_store_unrecoded_1, 32) node _io_out_bits_store_T_10 = bits(in.in1, 63, 61) node _io_out_bits_store_T_11 = andr(_io_out_bits_store_T_10) node _io_out_bits_store_T_12 = bits(io_out_bits_store_unrecoded_1, 31, 0) node _io_out_bits_store_T_13 = mux(_io_out_bits_store_T_11, io_out_bits_store_prevUnrecoded_1, _io_out_bits_store_T_12) node _io_out_bits_store_T_14 = cat(_io_out_bits_store_T_9, _io_out_bits_store_T_13) node _io_out_bits_store_T_15 = bits(_io_out_bits_store_T_14, 31, 0) node _io_out_bits_store_T_16 = cat(_io_out_bits_store_T_15, _io_out_bits_store_T_15) node io_out_bits_store_unrecoded_rawIn_exp_2 = bits(in.in1, 63, 52) node _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 9) node io_out_bits_store_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 11, 10) node io_out_bits_store_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_unrecoded_rawIn_2.isNaN, _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_unrecoded_rawIn_exp_2, 9, 9) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_unrecoded_rawIn_2.isInf, _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_unrecoded_rawIn_2.isZero, io_out_bits_store_unrecoded_rawIn_isZero_2 node _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = bits(in.in1, 64, 64) connect io_out_bits_store_unrecoded_rawIn_2.sign, _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_unrecoded_rawIn_exp_2) connect io_out_bits_store_unrecoded_rawIn_2.sExp, _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = bits(in.in1, 51, 0) node _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_unrecoded_rawIn_2.sig, _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_unrecoded_isSubnormal_2 = lt(io_out_bits_store_unrecoded_rawIn_2.sExp, asSInt(UInt<12>(0h402))) node _io_out_bits_store_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 5, 0) node _io_out_bits_store_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_unrecoded_denormShiftDist_T_4) node io_out_bits_store_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_unrecoded_denormFract_T_4 = shr(io_out_bits_store_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_unrecoded_denormFract_T_4, io_out_bits_store_unrecoded_denormShiftDist_2) node io_out_bits_store_unrecoded_denormFract_2 = bits(_io_out_bits_store_unrecoded_denormFract_T_5, 51, 0) node _io_out_bits_store_unrecoded_expOut_T_12 = bits(io_out_bits_store_unrecoded_rawIn_2.sExp, 10, 0) node _io_out_bits_store_unrecoded_expOut_T_13 = sub(_io_out_bits_store_unrecoded_expOut_T_12, UInt<11>(0h401)) node _io_out_bits_store_unrecoded_expOut_T_14 = tail(_io_out_bits_store_unrecoded_expOut_T_13, 1) node _io_out_bits_store_unrecoded_expOut_T_15 = mux(io_out_bits_store_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_unrecoded_expOut_T_14) node _io_out_bits_store_unrecoded_expOut_T_16 = or(io_out_bits_store_unrecoded_rawIn_2.isNaN, io_out_bits_store_unrecoded_rawIn_2.isInf) node _io_out_bits_store_unrecoded_expOut_T_17 = mux(_io_out_bits_store_unrecoded_expOut_T_16, UInt<11>(0h7ff), UInt<11>(0h0)) node io_out_bits_store_unrecoded_expOut_2 = or(_io_out_bits_store_unrecoded_expOut_T_15, _io_out_bits_store_unrecoded_expOut_T_17) node _io_out_bits_store_unrecoded_fractOut_T_4 = bits(io_out_bits_store_unrecoded_rawIn_2.sig, 51, 0) node _io_out_bits_store_unrecoded_fractOut_T_5 = mux(io_out_bits_store_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_unrecoded_fractOut_T_4) node io_out_bits_store_unrecoded_fractOut_2 = mux(io_out_bits_store_unrecoded_isSubnormal_2, io_out_bits_store_unrecoded_denormFract_2, _io_out_bits_store_unrecoded_fractOut_T_5) node io_out_bits_store_unrecoded_hi_2 = cat(io_out_bits_store_unrecoded_rawIn_2.sign, io_out_bits_store_unrecoded_expOut_2) node io_out_bits_store_unrecoded_2 = cat(io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2) node _io_out_bits_store_prevRecoded_T_6 = bits(in.in1, 31, 31) node _io_out_bits_store_prevRecoded_T_7 = bits(in.in1, 52, 52) node _io_out_bits_store_prevRecoded_T_8 = bits(in.in1, 30, 0) node io_out_bits_store_prevRecoded_hi_2 = cat(_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7) node io_out_bits_store_prevRecoded_2 = cat(io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevRecoded_2, 31, 23) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 6) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 8, 7) node io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2, 6, 6) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevRecoded_2, 32, 32) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevRecoded_2, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, asSInt(UInt<9>(0h82))) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sExp, 7, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12, UInt<8>(0h81)) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16, UInt<8>(0hff), UInt<8>(0h0)) node io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sig, 22, 0) node _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_unrecoded_2 = cat(io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = bits(io_out_bits_store_prevRecoded_2, 15, 15) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = bits(io_out_bits_store_prevRecoded_2, 23, 23) node _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = bits(io_out_bits_store_prevRecoded_2, 14, 0) node io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = cat(_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7) node io_out_bits_store_prevUnrecoded_prevRecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 15, 10) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 3) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 5, 4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2, UInt<2>(0h3)) wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2 : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>} node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2, 3, 3) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = eq(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = and(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isZero, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 16, 16) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = cvt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = eq(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2, UInt<1>(0h0)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = cat(UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = bits(io_out_bits_store_prevUnrecoded_prevRecoded_2, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = cat(_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10) connect io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 node io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = lt(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, asSInt(UInt<6>(0h12))) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 3, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = sub(UInt<1>(0h1), _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = shr(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = dshr(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = bits(_io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sExp, 4, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = sub(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12, UInt<5>(0h11)) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = tail(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13, 1) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = or(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isNaN, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = mux(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16, UInt<5>(0h1f), UInt<5>(0h0)) node io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = or(_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = bits(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sig, 9, 0) node _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.isInf, UInt<1>(0h0), _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4) node io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = mux(io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2, _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5) node io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2.sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2) node io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = cat(io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2) node _io_out_bits_store_prevUnrecoded_T_10 = shr(io_out_bits_store_prevUnrecoded_unrecoded_2, 16) node _io_out_bits_store_prevUnrecoded_T_11 = bits(io_out_bits_store_prevRecoded_2, 31, 29) node _io_out_bits_store_prevUnrecoded_T_12 = andr(_io_out_bits_store_prevUnrecoded_T_11) node _io_out_bits_store_prevUnrecoded_T_13 = bits(io_out_bits_store_prevUnrecoded_unrecoded_2, 15, 0) node _io_out_bits_store_prevUnrecoded_T_14 = mux(_io_out_bits_store_prevUnrecoded_T_12, io_out_bits_store_prevUnrecoded_prevUnrecoded_2, _io_out_bits_store_prevUnrecoded_T_13) node io_out_bits_store_prevUnrecoded_2 = cat(_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14) node _io_out_bits_store_T_17 = shr(io_out_bits_store_unrecoded_2, 32) node _io_out_bits_store_T_18 = bits(in.in1, 63, 61) node _io_out_bits_store_T_19 = andr(_io_out_bits_store_T_18) node _io_out_bits_store_T_20 = bits(io_out_bits_store_unrecoded_2, 31, 0) node _io_out_bits_store_T_21 = mux(_io_out_bits_store_T_19, io_out_bits_store_prevUnrecoded_2, _io_out_bits_store_T_20) node _io_out_bits_store_T_22 = cat(_io_out_bits_store_T_17, _io_out_bits_store_T_21) node _io_out_bits_store_T_23 = bits(_io_out_bits_store_T_22, 63, 0) node _io_out_bits_store_T_24 = eq(in.typeTagOut, UInt<1>(0h1)) node _io_out_bits_store_T_25 = mux(_io_out_bits_store_T_24, _io_out_bits_store_T_16, _io_out_bits_store_T_8) node _io_out_bits_store_T_26 = eq(in.typeTagOut, UInt<2>(0h2)) node _io_out_bits_store_T_27 = mux(_io_out_bits_store_T_26, _io_out_bits_store_T_23, _io_out_bits_store_T_25) node _io_out_bits_store_T_28 = eq(in.typeTagOut, UInt<2>(0h3)) node _io_out_bits_store_T_29 = mux(_io_out_bits_store_T_28, _io_out_bits_store_T_23, _io_out_bits_store_T_27) connect io.out.bits.store, _io_out_bits_store_T_29 node _io_out_bits_toint_T = bits(toint, 31, 0) node _io_out_bits_toint_T_1 = bits(_io_out_bits_toint_T, 31, 31) node _io_out_bits_toint_T_2 = mux(_io_out_bits_toint_T_1, UInt<32>(0hffffffff), UInt<32>(0h0)) node _io_out_bits_toint_T_3 = cat(_io_out_bits_toint_T_2, _io_out_bits_toint_T) node _io_out_bits_toint_T_4 = bits(toint, 63, 0) node _io_out_bits_toint_T_5 = eq(intType, UInt<1>(0h1)) node _io_out_bits_toint_T_6 = mux(_io_out_bits_toint_T_5, _io_out_bits_toint_T_4, _io_out_bits_toint_T_3) connect io.out.bits.toint, _io_out_bits_toint_T_6 connect io.out.bits.exc, UInt<1>(0h0) node _T = bits(in.rm, 0, 0) when _T : node classify_out_sign = bits(in.in1, 64, 64) node classify_out_fractIn = bits(in.in1, 51, 0) node classify_out_expIn = bits(in.in1, 63, 52) node _classify_out_fractOut_T = shl(classify_out_fractIn, 11) node classify_out_fractOut = shr(_classify_out_fractOut_T, 53) node classify_out_expOut_expCode = bits(classify_out_expIn, 11, 9) node _classify_out_expOut_commonCase_T = add(classify_out_expIn, UInt<6>(0h20)) node _classify_out_expOut_commonCase_T_1 = tail(_classify_out_expOut_commonCase_T, 1) node _classify_out_expOut_commonCase_T_2 = sub(_classify_out_expOut_commonCase_T_1, UInt<12>(0h800)) node classify_out_expOut_commonCase = tail(_classify_out_expOut_commonCase_T_2, 1) node _classify_out_expOut_T = eq(classify_out_expOut_expCode, UInt<1>(0h0)) node _classify_out_expOut_T_1 = geq(classify_out_expOut_expCode, UInt<3>(0h6)) node _classify_out_expOut_T_2 = or(_classify_out_expOut_T, _classify_out_expOut_T_1) node _classify_out_expOut_T_3 = bits(classify_out_expOut_commonCase, 2, 0) node _classify_out_expOut_T_4 = cat(classify_out_expOut_expCode, _classify_out_expOut_T_3) node _classify_out_expOut_T_5 = bits(classify_out_expOut_commonCase, 5, 0) node classify_out_expOut = mux(_classify_out_expOut_T_2, _classify_out_expOut_T_4, _classify_out_expOut_T_5) node classify_out_hi = cat(classify_out_sign, classify_out_expOut) node _classify_out_T = cat(classify_out_hi, classify_out_fractOut) node classify_out_sign_1 = bits(_classify_out_T, 16, 16) node classify_out_code = bits(_classify_out_T, 15, 13) node classify_out_codeHi = bits(classify_out_code, 2, 1) node classify_out_isSpecial = eq(classify_out_codeHi, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T = bits(_classify_out_T, 13, 10) node classify_out_isHighSubnormalIn = lt(_classify_out_isHighSubnormalIn_T, UInt<2>(0h2)) node _classify_out_isSubnormal_T = eq(classify_out_code, UInt<1>(0h1)) node _classify_out_isSubnormal_T_1 = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isSubnormal_T_2 = and(_classify_out_isSubnormal_T_1, classify_out_isHighSubnormalIn) node classify_out_isSubnormal = or(_classify_out_isSubnormal_T, _classify_out_isSubnormal_T_2) node _classify_out_isNormal_T = eq(classify_out_codeHi, UInt<1>(0h1)) node _classify_out_isNormal_T_1 = eq(classify_out_isHighSubnormalIn, UInt<1>(0h0)) node _classify_out_isNormal_T_2 = and(_classify_out_isNormal_T, _classify_out_isNormal_T_1) node _classify_out_isNormal_T_3 = eq(classify_out_codeHi, UInt<2>(0h2)) node classify_out_isNormal = or(_classify_out_isNormal_T_2, _classify_out_isNormal_T_3) node classify_out_isZero = eq(classify_out_code, UInt<1>(0h0)) node _classify_out_isInf_T = bits(classify_out_code, 0, 0) node _classify_out_isInf_T_1 = eq(_classify_out_isInf_T, UInt<1>(0h0)) node classify_out_isInf = and(classify_out_isSpecial, _classify_out_isInf_T_1) node classify_out_isNaN = andr(classify_out_code) node _classify_out_isSNaN_T = bits(_classify_out_T, 9, 9) node _classify_out_isSNaN_T_1 = eq(_classify_out_isSNaN_T, UInt<1>(0h0)) node classify_out_isSNaN = and(classify_out_isNaN, _classify_out_isSNaN_T_1) node _classify_out_isQNaN_T = bits(_classify_out_T, 9, 9) node classify_out_isQNaN = and(classify_out_isNaN, _classify_out_isQNaN_T) node _classify_out_T_1 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_2 = and(classify_out_isInf, _classify_out_T_1) node _classify_out_T_3 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_4 = and(classify_out_isNormal, _classify_out_T_3) node _classify_out_T_5 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_6 = and(classify_out_isSubnormal, _classify_out_T_5) node _classify_out_T_7 = eq(classify_out_sign_1, UInt<1>(0h0)) node _classify_out_T_8 = and(classify_out_isZero, _classify_out_T_7) node _classify_out_T_9 = and(classify_out_isZero, classify_out_sign_1) node _classify_out_T_10 = and(classify_out_isSubnormal, classify_out_sign_1) node _classify_out_T_11 = and(classify_out_isNormal, classify_out_sign_1) node _classify_out_T_12 = and(classify_out_isInf, classify_out_sign_1) node classify_out_lo_lo = cat(_classify_out_T_11, _classify_out_T_12) node classify_out_lo_hi_hi = cat(_classify_out_T_8, _classify_out_T_9) node classify_out_lo_hi = cat(classify_out_lo_hi_hi, _classify_out_T_10) node classify_out_lo = cat(classify_out_lo_hi, classify_out_lo_lo) node classify_out_hi_lo = cat(_classify_out_T_4, _classify_out_T_6) node classify_out_hi_hi_hi = cat(classify_out_isQNaN, classify_out_isSNaN) node classify_out_hi_hi = cat(classify_out_hi_hi_hi, _classify_out_T_2) node classify_out_hi_1 = cat(classify_out_hi_hi, classify_out_hi_lo) node _classify_out_T_13 = cat(classify_out_hi_1, classify_out_lo) node classify_out_sign_2 = bits(in.in1, 64, 64) node classify_out_fractIn_1 = bits(in.in1, 51, 0) node classify_out_expIn_1 = bits(in.in1, 63, 52) node _classify_out_fractOut_T_1 = shl(classify_out_fractIn_1, 24) node classify_out_fractOut_1 = shr(_classify_out_fractOut_T_1, 53) node classify_out_expOut_expCode_1 = bits(classify_out_expIn_1, 11, 9) node _classify_out_expOut_commonCase_T_3 = add(classify_out_expIn_1, UInt<9>(0h100)) node _classify_out_expOut_commonCase_T_4 = tail(_classify_out_expOut_commonCase_T_3, 1) node _classify_out_expOut_commonCase_T_5 = sub(_classify_out_expOut_commonCase_T_4, UInt<12>(0h800)) node classify_out_expOut_commonCase_1 = tail(_classify_out_expOut_commonCase_T_5, 1) node _classify_out_expOut_T_6 = eq(classify_out_expOut_expCode_1, UInt<1>(0h0)) node _classify_out_expOut_T_7 = geq(classify_out_expOut_expCode_1, UInt<3>(0h6)) node _classify_out_expOut_T_8 = or(_classify_out_expOut_T_6, _classify_out_expOut_T_7) node _classify_out_expOut_T_9 = bits(classify_out_expOut_commonCase_1, 5, 0) node _classify_out_expOut_T_10 = cat(classify_out_expOut_expCode_1, _classify_out_expOut_T_9) node _classify_out_expOut_T_11 = bits(classify_out_expOut_commonCase_1, 8, 0) node classify_out_expOut_1 = mux(_classify_out_expOut_T_8, _classify_out_expOut_T_10, _classify_out_expOut_T_11) node classify_out_hi_2 = cat(classify_out_sign_2, classify_out_expOut_1) node _classify_out_T_14 = cat(classify_out_hi_2, classify_out_fractOut_1) node classify_out_sign_3 = bits(_classify_out_T_14, 32, 32) node classify_out_code_1 = bits(_classify_out_T_14, 31, 29) node classify_out_codeHi_1 = bits(classify_out_code_1, 2, 1) node classify_out_isSpecial_1 = eq(classify_out_codeHi_1, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_1 = bits(_classify_out_T_14, 29, 23) node classify_out_isHighSubnormalIn_1 = lt(_classify_out_isHighSubnormalIn_T_1, UInt<2>(0h2)) node _classify_out_isSubnormal_T_3 = eq(classify_out_code_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isSubnormal_T_5 = and(_classify_out_isSubnormal_T_4, classify_out_isHighSubnormalIn_1) node classify_out_isSubnormal_1 = or(_classify_out_isSubnormal_T_3, _classify_out_isSubnormal_T_5) node _classify_out_isNormal_T_4 = eq(classify_out_codeHi_1, UInt<1>(0h1)) node _classify_out_isNormal_T_5 = eq(classify_out_isHighSubnormalIn_1, UInt<1>(0h0)) node _classify_out_isNormal_T_6 = and(_classify_out_isNormal_T_4, _classify_out_isNormal_T_5) node _classify_out_isNormal_T_7 = eq(classify_out_codeHi_1, UInt<2>(0h2)) node classify_out_isNormal_1 = or(_classify_out_isNormal_T_6, _classify_out_isNormal_T_7) node classify_out_isZero_1 = eq(classify_out_code_1, UInt<1>(0h0)) node _classify_out_isInf_T_2 = bits(classify_out_code_1, 0, 0) node _classify_out_isInf_T_3 = eq(_classify_out_isInf_T_2, UInt<1>(0h0)) node classify_out_isInf_1 = and(classify_out_isSpecial_1, _classify_out_isInf_T_3) node classify_out_isNaN_1 = andr(classify_out_code_1) node _classify_out_isSNaN_T_2 = bits(_classify_out_T_14, 22, 22) node _classify_out_isSNaN_T_3 = eq(_classify_out_isSNaN_T_2, UInt<1>(0h0)) node classify_out_isSNaN_1 = and(classify_out_isNaN_1, _classify_out_isSNaN_T_3) node _classify_out_isQNaN_T_1 = bits(_classify_out_T_14, 22, 22) node classify_out_isQNaN_1 = and(classify_out_isNaN_1, _classify_out_isQNaN_T_1) node _classify_out_T_15 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_16 = and(classify_out_isInf_1, _classify_out_T_15) node _classify_out_T_17 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_18 = and(classify_out_isNormal_1, _classify_out_T_17) node _classify_out_T_19 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_20 = and(classify_out_isSubnormal_1, _classify_out_T_19) node _classify_out_T_21 = eq(classify_out_sign_3, UInt<1>(0h0)) node _classify_out_T_22 = and(classify_out_isZero_1, _classify_out_T_21) node _classify_out_T_23 = and(classify_out_isZero_1, classify_out_sign_3) node _classify_out_T_24 = and(classify_out_isSubnormal_1, classify_out_sign_3) node _classify_out_T_25 = and(classify_out_isNormal_1, classify_out_sign_3) node _classify_out_T_26 = and(classify_out_isInf_1, classify_out_sign_3) node classify_out_lo_lo_1 = cat(_classify_out_T_25, _classify_out_T_26) node classify_out_lo_hi_hi_1 = cat(_classify_out_T_22, _classify_out_T_23) node classify_out_lo_hi_1 = cat(classify_out_lo_hi_hi_1, _classify_out_T_24) node classify_out_lo_1 = cat(classify_out_lo_hi_1, classify_out_lo_lo_1) node classify_out_hi_lo_1 = cat(_classify_out_T_18, _classify_out_T_20) node classify_out_hi_hi_hi_1 = cat(classify_out_isQNaN_1, classify_out_isSNaN_1) node classify_out_hi_hi_1 = cat(classify_out_hi_hi_hi_1, _classify_out_T_16) node classify_out_hi_3 = cat(classify_out_hi_hi_1, classify_out_hi_lo_1) node _classify_out_T_27 = cat(classify_out_hi_3, classify_out_lo_1) node classify_out_sign_4 = bits(in.in1, 64, 64) node classify_out_code_2 = bits(in.in1, 63, 61) node classify_out_codeHi_2 = bits(classify_out_code_2, 2, 1) node classify_out_isSpecial_2 = eq(classify_out_codeHi_2, UInt<2>(0h3)) node _classify_out_isHighSubnormalIn_T_2 = bits(in.in1, 61, 52) node classify_out_isHighSubnormalIn_2 = lt(_classify_out_isHighSubnormalIn_T_2, UInt<2>(0h2)) node _classify_out_isSubnormal_T_6 = eq(classify_out_code_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_7 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isSubnormal_T_8 = and(_classify_out_isSubnormal_T_7, classify_out_isHighSubnormalIn_2) node classify_out_isSubnormal_2 = or(_classify_out_isSubnormal_T_6, _classify_out_isSubnormal_T_8) node _classify_out_isNormal_T_8 = eq(classify_out_codeHi_2, UInt<1>(0h1)) node _classify_out_isNormal_T_9 = eq(classify_out_isHighSubnormalIn_2, UInt<1>(0h0)) node _classify_out_isNormal_T_10 = and(_classify_out_isNormal_T_8, _classify_out_isNormal_T_9) node _classify_out_isNormal_T_11 = eq(classify_out_codeHi_2, UInt<2>(0h2)) node classify_out_isNormal_2 = or(_classify_out_isNormal_T_10, _classify_out_isNormal_T_11) node classify_out_isZero_2 = eq(classify_out_code_2, UInt<1>(0h0)) node _classify_out_isInf_T_4 = bits(classify_out_code_2, 0, 0) node _classify_out_isInf_T_5 = eq(_classify_out_isInf_T_4, UInt<1>(0h0)) node classify_out_isInf_2 = and(classify_out_isSpecial_2, _classify_out_isInf_T_5) node classify_out_isNaN_2 = andr(classify_out_code_2) node _classify_out_isSNaN_T_4 = bits(in.in1, 51, 51) node _classify_out_isSNaN_T_5 = eq(_classify_out_isSNaN_T_4, UInt<1>(0h0)) node classify_out_isSNaN_2 = and(classify_out_isNaN_2, _classify_out_isSNaN_T_5) node _classify_out_isQNaN_T_2 = bits(in.in1, 51, 51) node classify_out_isQNaN_2 = and(classify_out_isNaN_2, _classify_out_isQNaN_T_2) node _classify_out_T_28 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_29 = and(classify_out_isInf_2, _classify_out_T_28) node _classify_out_T_30 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_31 = and(classify_out_isNormal_2, _classify_out_T_30) node _classify_out_T_32 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_33 = and(classify_out_isSubnormal_2, _classify_out_T_32) node _classify_out_T_34 = eq(classify_out_sign_4, UInt<1>(0h0)) node _classify_out_T_35 = and(classify_out_isZero_2, _classify_out_T_34) node _classify_out_T_36 = and(classify_out_isZero_2, classify_out_sign_4) node _classify_out_T_37 = and(classify_out_isSubnormal_2, classify_out_sign_4) node _classify_out_T_38 = and(classify_out_isNormal_2, classify_out_sign_4) node _classify_out_T_39 = and(classify_out_isInf_2, classify_out_sign_4) node classify_out_lo_lo_2 = cat(_classify_out_T_38, _classify_out_T_39) node classify_out_lo_hi_hi_2 = cat(_classify_out_T_35, _classify_out_T_36) node classify_out_lo_hi_2 = cat(classify_out_lo_hi_hi_2, _classify_out_T_37) node classify_out_lo_2 = cat(classify_out_lo_hi_2, classify_out_lo_lo_2) node classify_out_hi_lo_2 = cat(_classify_out_T_31, _classify_out_T_33) node classify_out_hi_hi_hi_2 = cat(classify_out_isQNaN_2, classify_out_isSNaN_2) node classify_out_hi_hi_2 = cat(classify_out_hi_hi_hi_2, _classify_out_T_29) node classify_out_hi_4 = cat(classify_out_hi_hi_2, classify_out_hi_lo_2) node _classify_out_T_40 = cat(classify_out_hi_4, classify_out_lo_2) node _classify_out_T_41 = eq(in.typeTagOut, UInt<1>(0h1)) node _classify_out_T_42 = mux(_classify_out_T_41, _classify_out_T_27, _classify_out_T_13) node _classify_out_T_43 = eq(in.typeTagOut, UInt<2>(0h2)) node _classify_out_T_44 = mux(_classify_out_T_43, _classify_out_T_40, _classify_out_T_42) node _classify_out_T_45 = eq(in.typeTagOut, UInt<2>(0h3)) node classify_out = mux(_classify_out_T_45, _classify_out_T_40, _classify_out_T_44) node _toint_T = shr(toint_ieee, 32) node _toint_T_1 = shl(_toint_T, 32) node _toint_T_2 = or(classify_out, _toint_T_1) connect toint, _toint_T_2 connect intType, UInt<1>(0h0) when in.wflags : node _toint_T_3 = not(in.rm) node _toint_T_4 = cat(dcmp.io.lt, dcmp.io.eq) node _toint_T_5 = and(_toint_T_3, _toint_T_4) node _toint_T_6 = orr(_toint_T_5) node _toint_T_7 = shr(toint_ieee, 32) node _toint_T_8 = shl(_toint_T_7, 32) node _toint_T_9 = or(_toint_T_6, _toint_T_8) connect toint, _toint_T_9 connect io.out.bits.exc, dcmp.io.exceptionFlags connect intType, UInt<1>(0h0) node _T_1 = eq(in.ren2, UInt<1>(0h0)) when _T_1 : node cvtType = bits(in.typ, 1, 1) connect intType, cvtType inst conv of RecFNToIN_e11_s53_i64 connect conv.clock, clock connect conv.reset, reset connect conv.io.in, in.in1 connect conv.io.roundingMode, in.rm node _conv_io_signedOut_T = bits(in.typ, 0, 0) node _conv_io_signedOut_T_1 = not(_conv_io_signedOut_T) connect conv.io.signedOut, _conv_io_signedOut_T_1 connect toint, conv.io.out node _io_out_bits_exc_T = bits(conv.io.intExceptionFlags, 2, 1) node _io_out_bits_exc_T_1 = orr(_io_out_bits_exc_T) node _io_out_bits_exc_T_2 = bits(conv.io.intExceptionFlags, 0, 0) node io_out_bits_exc_hi = cat(_io_out_bits_exc_T_1, UInt<3>(0h0)) node _io_out_bits_exc_T_3 = cat(io_out_bits_exc_hi, _io_out_bits_exc_T_2) connect io.out.bits.exc, _io_out_bits_exc_T_3 node _T_2 = eq(cvtType, UInt<1>(0h0)) when _T_2 : inst narrow of RecFNToIN_e11_s53_i32 connect narrow.clock, clock connect narrow.reset, reset connect narrow.io.in, in.in1 connect narrow.io.roundingMode, in.rm node _narrow_io_signedOut_T = bits(in.typ, 0, 0) node _narrow_io_signedOut_T_1 = not(_narrow_io_signedOut_T) connect narrow.io.signedOut, _narrow_io_signedOut_T_1 node _excSign_T = bits(in.in1, 64, 64) node _excSign_T_1 = bits(in.in1, 63, 61) node _excSign_T_2 = andr(_excSign_T_1) node _excSign_T_3 = eq(_excSign_T_2, UInt<1>(0h0)) node excSign = and(_excSign_T, _excSign_T_3) node _excOut_T = eq(conv.io.signedOut, excSign) node _excOut_T_1 = eq(excSign, UInt<1>(0h0)) node _excOut_T_2 = mux(_excOut_T_1, UInt<31>(0h7fffffff), UInt<31>(0h0)) node excOut = cat(_excOut_T, _excOut_T_2) node _invalid_T = bits(conv.io.intExceptionFlags, 2, 2) node _invalid_T_1 = bits(narrow.io.intExceptionFlags, 1, 1) node invalid = or(_invalid_T, _invalid_T_1) when invalid : node _toint_T_10 = shr(conv.io.out, 32) node _toint_T_11 = cat(_toint_T_10, excOut) connect toint, _toint_T_11 node _io_out_bits_exc_T_4 = eq(invalid, UInt<1>(0h0)) node _io_out_bits_exc_T_5 = bits(conv.io.intExceptionFlags, 0, 0) node _io_out_bits_exc_T_6 = and(_io_out_bits_exc_T_4, _io_out_bits_exc_T_5) node io_out_bits_exc_hi_1 = cat(invalid, UInt<3>(0h0)) node _io_out_bits_exc_T_7 = cat(io_out_bits_exc_hi_1, _io_out_bits_exc_T_6) connect io.out.bits.exc, _io_out_bits_exc_T_7 connect io.out.valid, valid node _io_out_bits_lt_T = asSInt(dcmp.io.a) node _io_out_bits_lt_T_1 = lt(_io_out_bits_lt_T, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_2 = asSInt(dcmp.io.b) node _io_out_bits_lt_T_3 = geq(_io_out_bits_lt_T_2, asSInt(UInt<1>(0h0))) node _io_out_bits_lt_T_4 = and(_io_out_bits_lt_T_1, _io_out_bits_lt_T_3) node _io_out_bits_lt_T_5 = or(dcmp.io.lt, _io_out_bits_lt_T_4) connect io.out.bits.lt, _io_out_bits_lt_T_5 connect io.out.bits.in, in
module FPToInt( // @[FPU.scala:453:7] input clock, // @[FPU.scala:453:7] input reset, // @[FPU.scala:453:7] input io_in_valid, // @[FPU.scala:461:14] input io_in_bits_ldst, // @[FPU.scala:461:14] input io_in_bits_wen, // @[FPU.scala:461:14] input io_in_bits_ren1, // @[FPU.scala:461:14] input io_in_bits_ren2, // @[FPU.scala:461:14] input io_in_bits_ren3, // @[FPU.scala:461:14] input io_in_bits_swap12, // @[FPU.scala:461:14] input io_in_bits_swap23, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:461:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:461:14] input io_in_bits_fromint, // @[FPU.scala:461:14] input io_in_bits_toint, // @[FPU.scala:461:14] input io_in_bits_fastpipe, // @[FPU.scala:461:14] input io_in_bits_fma, // @[FPU.scala:461:14] input io_in_bits_div, // @[FPU.scala:461:14] input io_in_bits_sqrt, // @[FPU.scala:461:14] input io_in_bits_wflags, // @[FPU.scala:461:14] input [2:0] io_in_bits_rm, // @[FPU.scala:461:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:461:14] input [1:0] io_in_bits_typ, // @[FPU.scala:461:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:461:14] input [64:0] io_in_bits_in1, // @[FPU.scala:461:14] input [64:0] io_in_bits_in2, // @[FPU.scala:461:14] input [64:0] io_in_bits_in3, // @[FPU.scala:461:14] output io_out_bits_in_ldst, // @[FPU.scala:461:14] output io_out_bits_in_wen, // @[FPU.scala:461:14] output io_out_bits_in_ren1, // @[FPU.scala:461:14] output io_out_bits_in_ren2, // @[FPU.scala:461:14] output io_out_bits_in_ren3, // @[FPU.scala:461:14] output io_out_bits_in_swap12, // @[FPU.scala:461:14] output io_out_bits_in_swap23, // @[FPU.scala:461:14] output [1:0] io_out_bits_in_typeTagIn, // @[FPU.scala:461:14] output [1:0] io_out_bits_in_typeTagOut, // @[FPU.scala:461:14] output io_out_bits_in_fromint, // @[FPU.scala:461:14] output io_out_bits_in_toint, // @[FPU.scala:461:14] output io_out_bits_in_fastpipe, // @[FPU.scala:461:14] output io_out_bits_in_fma, // @[FPU.scala:461:14] output io_out_bits_in_div, // @[FPU.scala:461:14] output io_out_bits_in_sqrt, // @[FPU.scala:461:14] output io_out_bits_in_wflags, // @[FPU.scala:461:14] output [2:0] io_out_bits_in_rm, // @[FPU.scala:461:14] output [1:0] io_out_bits_in_fmaCmd, // @[FPU.scala:461:14] output [1:0] io_out_bits_in_typ, // @[FPU.scala:461:14] output [1:0] io_out_bits_in_fmt, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in1, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in2, // @[FPU.scala:461:14] output [64:0] io_out_bits_in_in3, // @[FPU.scala:461:14] output io_out_bits_lt, // @[FPU.scala:461:14] output [63:0] io_out_bits_store, // @[FPU.scala:461:14] output [63:0] io_out_bits_toint, // @[FPU.scala:461:14] output [4:0] io_out_bits_exc // @[FPU.scala:461:14] ); wire [2:0] _narrow_io_intExceptionFlags; // @[FPU.scala:508:30] wire [63:0] _conv_io_out; // @[FPU.scala:498:24] wire [2:0] _conv_io_intExceptionFlags; // @[FPU.scala:498:24] wire _dcmp_io_lt; // @[FPU.scala:469:20] wire _dcmp_io_eq; // @[FPU.scala:469:20] wire [4:0] _dcmp_io_exceptionFlags; // @[FPU.scala:469:20] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:453:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:453:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:453:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:453:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:453:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:453:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:453:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:453:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:453:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:453:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:453:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:453:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:453:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:453:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:453:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:453:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:453:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:453:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:453:7] wire io_in_bits_vec = 1'h0; // @[FPU.scala:453:7] wire io_out_bits_in_vec = 1'h0; // @[FPU.scala:453:7] wire _io_out_bits_lt_T_5; // @[FPU.scala:524:32] wire [63:0] _io_out_bits_store_T_29; // @[package.scala:39:76] wire [63:0] _io_out_bits_toint_T_6; // @[package.scala:39:76] wire io_out_bits_in_ldst_0; // @[FPU.scala:453:7] wire io_out_bits_in_wen_0; // @[FPU.scala:453:7] wire io_out_bits_in_ren1_0; // @[FPU.scala:453:7] wire io_out_bits_in_ren2_0; // @[FPU.scala:453:7] wire io_out_bits_in_ren3_0; // @[FPU.scala:453:7] wire io_out_bits_in_swap12_0; // @[FPU.scala:453:7] wire io_out_bits_in_swap23_0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagIn_0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typeTagOut_0; // @[FPU.scala:453:7] wire io_out_bits_in_fromint_0; // @[FPU.scala:453:7] wire io_out_bits_in_toint_0; // @[FPU.scala:453:7] wire io_out_bits_in_fastpipe_0; // @[FPU.scala:453:7] wire io_out_bits_in_fma_0; // @[FPU.scala:453:7] wire io_out_bits_in_div_0; // @[FPU.scala:453:7] wire io_out_bits_in_sqrt_0; // @[FPU.scala:453:7] wire io_out_bits_in_wflags_0; // @[FPU.scala:453:7] wire [2:0] io_out_bits_in_rm_0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmaCmd_0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_typ_0; // @[FPU.scala:453:7] wire [1:0] io_out_bits_in_fmt_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in1_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in2_0; // @[FPU.scala:453:7] wire [64:0] io_out_bits_in_in3_0; // @[FPU.scala:453:7] wire io_out_bits_lt_0; // @[FPU.scala:453:7] wire [63:0] io_out_bits_store_0; // @[FPU.scala:453:7] wire [63:0] io_out_bits_toint_0; // @[FPU.scala:453:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:453:7] wire io_out_valid; // @[FPU.scala:453:7] reg in_ldst; // @[FPU.scala:466:21] assign io_out_bits_in_ldst_0 = in_ldst; // @[FPU.scala:453:7, :466:21] reg in_wen; // @[FPU.scala:466:21] assign io_out_bits_in_wen_0 = in_wen; // @[FPU.scala:453:7, :466:21] reg in_ren1; // @[FPU.scala:466:21] assign io_out_bits_in_ren1_0 = in_ren1; // @[FPU.scala:453:7, :466:21] reg in_ren2; // @[FPU.scala:466:21] assign io_out_bits_in_ren2_0 = in_ren2; // @[FPU.scala:453:7, :466:21] reg in_ren3; // @[FPU.scala:466:21] assign io_out_bits_in_ren3_0 = in_ren3; // @[FPU.scala:453:7, :466:21] reg in_swap12; // @[FPU.scala:466:21] assign io_out_bits_in_swap12_0 = in_swap12; // @[FPU.scala:453:7, :466:21] reg in_swap23; // @[FPU.scala:466:21] assign io_out_bits_in_swap23_0 = in_swap23; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagIn; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagIn_0 = in_typeTagIn; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typeTagOut; // @[FPU.scala:466:21] assign io_out_bits_in_typeTagOut_0 = in_typeTagOut; // @[FPU.scala:453:7, :466:21] reg in_fromint; // @[FPU.scala:466:21] assign io_out_bits_in_fromint_0 = in_fromint; // @[FPU.scala:453:7, :466:21] reg in_toint; // @[FPU.scala:466:21] assign io_out_bits_in_toint_0 = in_toint; // @[FPU.scala:453:7, :466:21] reg in_fastpipe; // @[FPU.scala:466:21] assign io_out_bits_in_fastpipe_0 = in_fastpipe; // @[FPU.scala:453:7, :466:21] reg in_fma; // @[FPU.scala:466:21] assign io_out_bits_in_fma_0 = in_fma; // @[FPU.scala:453:7, :466:21] reg in_div; // @[FPU.scala:466:21] assign io_out_bits_in_div_0 = in_div; // @[FPU.scala:453:7, :466:21] reg in_sqrt; // @[FPU.scala:466:21] assign io_out_bits_in_sqrt_0 = in_sqrt; // @[FPU.scala:453:7, :466:21] reg in_wflags; // @[FPU.scala:466:21] assign io_out_bits_in_wflags_0 = in_wflags; // @[FPU.scala:453:7, :466:21] reg [2:0] in_rm; // @[FPU.scala:466:21] assign io_out_bits_in_rm_0 = in_rm; // @[FPU.scala:453:7, :466:21] reg [1:0] in_fmaCmd; // @[FPU.scala:466:21] assign io_out_bits_in_fmaCmd_0 = in_fmaCmd; // @[FPU.scala:453:7, :466:21] reg [1:0] in_typ; // @[FPU.scala:466:21] assign io_out_bits_in_typ_0 = in_typ; // @[FPU.scala:453:7, :466:21] reg [1:0] in_fmt; // @[FPU.scala:466:21] assign io_out_bits_in_fmt_0 = in_fmt; // @[FPU.scala:453:7, :466:21] reg [64:0] in_in1; // @[FPU.scala:466:21] assign io_out_bits_in_in1_0 = in_in1; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T = in_in1; // @[FPU.scala:466:21, :524:46] reg [64:0] in_in2; // @[FPU.scala:466:21] assign io_out_bits_in_in2_0 = in_in2; // @[FPU.scala:453:7, :466:21] wire [64:0] _io_out_bits_lt_T_2 = in_in2; // @[FPU.scala:466:21, :524:72] reg [64:0] in_in3; // @[FPU.scala:466:21] assign io_out_bits_in_in3_0 = in_in3; // @[FPU.scala:453:7, :466:21] reg valid; // @[FPU.scala:467:22] assign io_out_valid = valid; // @[FPU.scala:453:7, :467:22] wire _dcmp_io_signaling_T = in_rm[1]; // @[FPU.scala:466:21, :472:30] wire _dcmp_io_signaling_T_1 = ~_dcmp_io_signaling_T; // @[FPU.scala:472:{24,30}] wire [11:0] toint_ieee_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] toint_ieee_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_1 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] io_out_bits_store_unrecoded_rawIn_exp_2 = in_in1[63:52]; // @[FPU.scala:466:21] wire [11:0] classify_out_expIn = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [11:0] classify_out_expIn_1 = in_in1[63:52]; // @[FPU.scala:276:18, :466:21] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T = toint_ieee_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero = _toint_ieee_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_isZero_0 = toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T = toint_ieee_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial = &_toint_ieee_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T = toint_ieee_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_unrecoded_rawIn_isSpecial & _toint_ieee_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _toint_ieee_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_1 = in_in1[64]; // @[FPU.scala:466:21] wire _io_out_bits_store_unrecoded_rawIn_out_sign_T_2 = in_in1[64]; // @[FPU.scala:466:21] wire classify_out_sign = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_2 = in_in1[64]; // @[FPU.scala:274:17, :466:21] wire classify_out_sign_4 = in_in1[64]; // @[FPU.scala:253:17, :466:21] wire _excSign_T = in_in1[64]; // @[FPU.scala:466:21, :513:31] assign toint_ieee_unrecoded_rawIn_sign = _toint_ieee_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T = ~toint_ieee_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _toint_ieee_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_2 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_6 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_10 = in_in1[51:0]; // @[FPU.scala:466:21] wire [51:0] classify_out_fractIn = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] wire [51:0] classify_out_fractIn_1 = in_in1[51:0]; // @[FPU.scala:275:20, :466:21] assign _toint_ieee_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_unrecoded_rawIn_out_sig_T_1, _toint_ieee_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal = $signed(toint_ieee_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T = toint_ieee_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist = _toint_ieee_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T = toint_ieee_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_1 = _toint_ieee_unrecoded_denormFract_T >> toint_ieee_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract = _toint_ieee_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T = toint_ieee_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_2 = _toint_ieee_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_3 = toint_ieee_unrecoded_isSubnormal ? 11'h0 : _toint_ieee_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_4 = toint_ieee_unrecoded_rawIn_isNaN | toint_ieee_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_5 = {11{_toint_ieee_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut = _toint_ieee_unrecoded_expOut_T_3 | _toint_ieee_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T = toint_ieee_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_1 = toint_ieee_unrecoded_rawIn_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut = toint_ieee_unrecoded_isSubnormal ? toint_ieee_unrecoded_denormFract : _toint_ieee_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi = {toint_ieee_unrecoded_rawIn_sign, toint_ieee_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded = {toint_ieee_unrecoded_hi, toint_ieee_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_3 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _io_out_bits_store_prevRecoded_T_6 = in_in1[31]; // @[FPU.scala:442:10, :466:21] wire _toint_ieee_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _toint_ieee_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_1 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_4 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire _io_out_bits_store_prevRecoded_T_7 = in_in1[52]; // @[FPU.scala:443:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _toint_ieee_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_2 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_5 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [30:0] _io_out_bits_store_prevRecoded_T_8 = in_in1[30:0]; // @[FPU.scala:444:10, :466:21] wire [1:0] toint_ieee_prevRecoded_hi = {_toint_ieee_prevRecoded_T, _toint_ieee_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded = {toint_ieee_prevRecoded_hi, _toint_ieee_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp = toint_ieee_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T = toint_ieee_prevRecoded[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = toint_ieee_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_3 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T = toint_ieee_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut = toint_ieee_prevUnrecoded_unrecoded_isSubnormal ? toint_ieee_prevUnrecoded_unrecoded_denormFract : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi = {toint_ieee_prevUnrecoded_unrecoded_rawIn_sign, toint_ieee_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded = {toint_ieee_prevUnrecoded_unrecoded_hi, toint_ieee_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T = toint_ieee_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_1 = toint_ieee_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_2 = toint_ieee_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi = {_toint_ieee_prevUnrecoded_prevRecoded_T, _toint_ieee_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded = {toint_ieee_prevUnrecoded_prevRecoded_hi, _toint_ieee_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp = toint_ieee_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = toint_ieee_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = toint_ieee_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_3 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded = {toint_ieee_prevUnrecoded_prevUnrecoded_hi, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T = toint_ieee_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_1 = toint_ieee_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_2 = &_toint_ieee_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_3 = toint_ieee_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_4 = _toint_ieee_prevUnrecoded_T_2 ? toint_ieee_prevUnrecoded_prevUnrecoded : _toint_ieee_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded = {_toint_ieee_prevUnrecoded_T, _toint_ieee_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T = toint_ieee_unrecoded[63:32]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_12 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _toint_ieee_T_20 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_10 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] _io_out_bits_store_T_18 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire [2:0] classify_out_code_2 = in_in1[63:61]; // @[FPU.scala:249:25, :254:17, :466:21] wire [2:0] _excSign_T_1 = in_in1[63:61]; // @[FPU.scala:249:25, :466:21] wire _toint_ieee_T_2 = &_toint_ieee_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_3 = toint_ieee_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_4 = _toint_ieee_T_2 ? toint_ieee_prevUnrecoded : _toint_ieee_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_5 = {_toint_ieee_T, _toint_ieee_T_4}; // @[FPU.scala:446:{10,21,44}] wire [15:0] _toint_ieee_T_6 = _toint_ieee_T_5[15:0]; // @[FPU.scala:446:10, :475:107] wire _toint_ieee_T_7 = _toint_ieee_T_6[15]; // @[package.scala:132:38] wire [15:0] _toint_ieee_T_8 = {16{_toint_ieee_T_7}}; // @[package.scala:132:{20,38}] wire [31:0] _toint_ieee_T_9 = {_toint_ieee_T_8, _toint_ieee_T_6}; // @[package.scala:132:{15,20}] wire [63:0] _toint_ieee_T_10 = {2{_toint_ieee_T_9}}; // @[package.scala:132:15] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_1 = _toint_ieee_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_1_isZero = toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_1_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_1 & _toint_ieee_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_1_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_1_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_1_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_unrecoded_rawIn_out_sig_T_5, _toint_ieee_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_1_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_1 = $signed(toint_ieee_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_2 = toint_ieee_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_1 = _toint_ieee_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_2 = toint_ieee_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_3 = _toint_ieee_unrecoded_denormFract_T_2 >> toint_ieee_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_1 = _toint_ieee_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_6 = toint_ieee_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_8 = _toint_ieee_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_9 = toint_ieee_unrecoded_isSubnormal_1 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_10 = toint_ieee_unrecoded_rawIn_1_isNaN | toint_ieee_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_11 = {11{_toint_ieee_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_1 = _toint_ieee_unrecoded_expOut_T_9 | _toint_ieee_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_2 = toint_ieee_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_3 = toint_ieee_unrecoded_rawIn_1_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_1 = toint_ieee_unrecoded_isSubnormal_1 ? toint_ieee_unrecoded_denormFract_1 : _toint_ieee_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_1 = {toint_ieee_unrecoded_rawIn_1_sign, toint_ieee_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_1 = {toint_ieee_unrecoded_hi_1, toint_ieee_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_1 = {_toint_ieee_prevRecoded_T_3, _toint_ieee_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_1 = {toint_ieee_prevRecoded_hi_1, _toint_ieee_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1 = toint_ieee_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = toint_ieee_prevRecoded_1[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = toint_ieee_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_1 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_9 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_1 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_1 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded_1 = {toint_ieee_prevUnrecoded_unrecoded_hi_1, toint_ieee_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T_3 = toint_ieee_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_4 = toint_ieee_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_5 = toint_ieee_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_1 = {_toint_ieee_prevUnrecoded_prevRecoded_T_3, _toint_ieee_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_1 = {toint_ieee_prevUnrecoded_prevRecoded_hi_1, _toint_ieee_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = toint_ieee_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = toint_ieee_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = toint_ieee_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_9 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_1 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_1_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_1 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_1, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T_5 = toint_ieee_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_6 = toint_ieee_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_7 = &_toint_ieee_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_8 = toint_ieee_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_9 = _toint_ieee_prevUnrecoded_T_7 ? toint_ieee_prevUnrecoded_prevUnrecoded_1 : _toint_ieee_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded_1 = {_toint_ieee_prevUnrecoded_T_5, _toint_ieee_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_11 = toint_ieee_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_13 = &_toint_ieee_T_12; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_14 = toint_ieee_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_15 = _toint_ieee_T_13 ? toint_ieee_prevUnrecoded_1 : _toint_ieee_T_14; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_16 = {_toint_ieee_T_11, _toint_ieee_T_15}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_17 = _toint_ieee_T_16[31:0]; // @[FPU.scala:446:10, :476:109] wire [63:0] _toint_ieee_T_18 = {2{_toint_ieee_T_17}}; // @[FPU.scala:476:{63,109}] wire [2:0] _toint_ieee_unrecoded_rawIn_isZero_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_unrecoded_rawIn_isZero_2 = _toint_ieee_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_unrecoded_rawIn_2_isZero = toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] toint_ieee_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] toint_ieee_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_unrecoded_rawIn_2_isNaN = _toint_ieee_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_unrecoded_rawIn_isSpecial_2 & _toint_ieee_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_unrecoded_rawIn_2_isInf = _toint_ieee_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign toint_ieee_unrecoded_rawIn_2_sign = _toint_ieee_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_unrecoded_rawIn_2_sExp = _toint_ieee_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _toint_ieee_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_unrecoded_rawIn_out_sig_T_9, _toint_ieee_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_unrecoded_rawIn_2_sig = _toint_ieee_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_unrecoded_isSubnormal_2 = $signed(toint_ieee_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_unrecoded_denormShiftDist_T_4 = toint_ieee_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _toint_ieee_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _toint_ieee_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] toint_ieee_unrecoded_denormShiftDist_2 = _toint_ieee_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _toint_ieee_unrecoded_denormFract_T_4 = toint_ieee_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _toint_ieee_unrecoded_denormFract_T_5 = _toint_ieee_unrecoded_denormFract_T_4 >> toint_ieee_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] toint_ieee_unrecoded_denormFract_2 = _toint_ieee_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _toint_ieee_unrecoded_expOut_T_12 = toint_ieee_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _toint_ieee_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _toint_ieee_unrecoded_expOut_T_14 = _toint_ieee_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _toint_ieee_unrecoded_expOut_T_15 = toint_ieee_unrecoded_isSubnormal_2 ? 11'h0 : _toint_ieee_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_unrecoded_expOut_T_16 = toint_ieee_unrecoded_rawIn_2_isNaN | toint_ieee_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_unrecoded_expOut_T_17 = {11{_toint_ieee_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] toint_ieee_unrecoded_expOut_2 = _toint_ieee_unrecoded_expOut_T_15 | _toint_ieee_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _toint_ieee_unrecoded_fractOut_T_4 = toint_ieee_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _toint_ieee_unrecoded_fractOut_T_5 = toint_ieee_unrecoded_rawIn_2_isInf ? 52'h0 : _toint_ieee_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] toint_ieee_unrecoded_fractOut_2 = toint_ieee_unrecoded_isSubnormal_2 ? toint_ieee_unrecoded_denormFract_2 : _toint_ieee_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] toint_ieee_unrecoded_hi_2 = {toint_ieee_unrecoded_rawIn_2_sign, toint_ieee_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] toint_ieee_unrecoded_2 = {toint_ieee_unrecoded_hi_2, toint_ieee_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] toint_ieee_prevRecoded_hi_2 = {_toint_ieee_prevRecoded_T_6, _toint_ieee_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] toint_ieee_prevRecoded_2 = {toint_ieee_prevRecoded_hi_2, _toint_ieee_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2 = toint_ieee_prevRecoded_2[31:23]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = toint_ieee_prevRecoded_2[32]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = toint_ieee_prevRecoded_2[22:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _toint_ieee_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_unrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isNaN | toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17 = {8{_toint_ieee_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] toint_ieee_prevUnrecoded_unrecoded_expOut_2 = _toint_ieee_prevUnrecoded_unrecoded_expOut_T_15 | _toint_ieee_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] toint_ieee_prevUnrecoded_unrecoded_fractOut_2 = toint_ieee_prevUnrecoded_unrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_unrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] toint_ieee_prevUnrecoded_unrecoded_hi_2 = {toint_ieee_prevUnrecoded_unrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] toint_ieee_prevUnrecoded_unrecoded_2 = {toint_ieee_prevUnrecoded_unrecoded_hi_2, toint_ieee_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire _toint_ieee_prevUnrecoded_prevRecoded_T_6 = toint_ieee_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10] wire _toint_ieee_prevUnrecoded_prevRecoded_T_7 = toint_ieee_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _toint_ieee_prevUnrecoded_prevRecoded_T_8 = toint_ieee_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] toint_ieee_prevUnrecoded_prevRecoded_hi_2 = {_toint_ieee_prevUnrecoded_prevRecoded_T_6, _toint_ieee_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] toint_ieee_prevUnrecoded_prevRecoded_2 = {toint_ieee_prevUnrecoded_prevRecoded_hi_2, _toint_ieee_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = toint_ieee_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28] wire [2:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = toint_ieee_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = toint_ieee_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28] assign _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> toint_ieee_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN | toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2 = _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_15 | _toint_ieee_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5 = toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2 = toint_ieee_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? toint_ieee_prevUnrecoded_prevUnrecoded_denormFract_2 : _toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] toint_ieee_prevUnrecoded_prevUnrecoded_hi_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_rawIn_2_sign, toint_ieee_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] toint_ieee_prevUnrecoded_prevUnrecoded_2 = {toint_ieee_prevUnrecoded_prevUnrecoded_hi_2, toint_ieee_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _toint_ieee_prevUnrecoded_T_10 = toint_ieee_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21] wire [2:0] _toint_ieee_prevUnrecoded_T_11 = toint_ieee_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28] wire _toint_ieee_prevUnrecoded_T_12 = &_toint_ieee_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}] wire [15:0] _toint_ieee_prevUnrecoded_T_13 = toint_ieee_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81] wire [15:0] _toint_ieee_prevUnrecoded_T_14 = _toint_ieee_prevUnrecoded_T_12 ? toint_ieee_prevUnrecoded_prevUnrecoded_2 : _toint_ieee_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] toint_ieee_prevUnrecoded_2 = {_toint_ieee_prevUnrecoded_T_10, _toint_ieee_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _toint_ieee_T_19 = toint_ieee_unrecoded_2[63:32]; // @[FPU.scala:446:21] wire _toint_ieee_T_21 = &_toint_ieee_T_20; // @[FPU.scala:249:{25,56}] wire [31:0] _toint_ieee_T_22 = toint_ieee_unrecoded_2[31:0]; // @[FPU.scala:446:81] wire [31:0] _toint_ieee_T_23 = _toint_ieee_T_21 ? toint_ieee_prevUnrecoded_2 : _toint_ieee_T_22; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _toint_ieee_T_24 = {_toint_ieee_T_19, _toint_ieee_T_23}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _toint_ieee_T_25 = _toint_ieee_T_24; // @[FPU.scala:446:10, :476:109] wire _GEN = in_typeTagOut == 2'h1; // @[package.scala:39:86] wire _toint_ieee_T_26; // @[package.scala:39:86] assign _toint_ieee_T_26 = _GEN; // @[package.scala:39:86] wire _io_out_bits_store_T_24; // @[package.scala:39:86] assign _io_out_bits_store_T_24 = _GEN; // @[package.scala:39:86] wire _classify_out_T_41; // @[package.scala:39:86] assign _classify_out_T_41 = _GEN; // @[package.scala:39:86] wire [63:0] _toint_ieee_T_27 = _toint_ieee_T_26 ? _toint_ieee_T_18 : _toint_ieee_T_10; // @[package.scala:39:{76,86}] wire _GEN_0 = in_typeTagOut == 2'h2; // @[package.scala:39:86] wire _toint_ieee_T_28; // @[package.scala:39:86] assign _toint_ieee_T_28 = _GEN_0; // @[package.scala:39:86] wire _io_out_bits_store_T_26; // @[package.scala:39:86] assign _io_out_bits_store_T_26 = _GEN_0; // @[package.scala:39:86] wire _classify_out_T_43; // @[package.scala:39:86] assign _classify_out_T_43 = _GEN_0; // @[package.scala:39:86] wire [63:0] _toint_ieee_T_29 = _toint_ieee_T_28 ? _toint_ieee_T_25 : _toint_ieee_T_27; // @[package.scala:39:{76,86}] wire _toint_ieee_T_30 = &in_typeTagOut; // @[package.scala:39:86] wire [63:0] toint_ieee = _toint_ieee_T_30 ? _toint_ieee_T_25 : _toint_ieee_T_29; // @[package.scala:39:{76,86}] wire [63:0] toint; // @[FPU.scala:478:26] wire [63:0] _io_out_bits_toint_T_4 = toint; // @[FPU.scala:478:26, :481:59] wire _intType_T = in_fmt[0]; // @[FPU.scala:466:21, :479:35] wire intType; // @[FPU.scala:479:28] wire _io_out_bits_toint_T_5 = intType; // @[package.scala:39:86] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T = io_out_bits_store_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero = _io_out_bits_store_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_isZero_0 = io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T = io_out_bits_store_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T = io_out_bits_store_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_unrecoded_rawIn_isSpecial & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal = $signed(io_out_bits_store_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T = io_out_bits_store_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist = _io_out_bits_store_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T = io_out_bits_store_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_1 = _io_out_bits_store_unrecoded_denormFract_T >> io_out_bits_store_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract = _io_out_bits_store_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T = io_out_bits_store_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_2 = _io_out_bits_store_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_3 = io_out_bits_store_unrecoded_isSubnormal ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_4 = io_out_bits_store_unrecoded_rawIn_isNaN | io_out_bits_store_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_5 = {11{_io_out_bits_store_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut = _io_out_bits_store_unrecoded_expOut_T_3 | _io_out_bits_store_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T = io_out_bits_store_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_1 = io_out_bits_store_unrecoded_rawIn_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut = io_out_bits_store_unrecoded_isSubnormal ? io_out_bits_store_unrecoded_denormFract : _io_out_bits_store_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi = {io_out_bits_store_unrecoded_rawIn_sign, io_out_bits_store_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded = {io_out_bits_store_unrecoded_hi, io_out_bits_store_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi = {_io_out_bits_store_prevRecoded_T, _io_out_bits_store_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded = {io_out_bits_store_prevRecoded_hi, _io_out_bits_store_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp = io_out_bits_store_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T = io_out_bits_store_prevRecoded[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_3 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded = {io_out_bits_store_prevUnrecoded_unrecoded_hi, io_out_bits_store_prevUnrecoded_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T = io_out_bits_store_prevRecoded[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_1 = io_out_bits_store_prevRecoded[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_2 = io_out_bits_store_prevRecoded[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi = {_io_out_bits_store_prevUnrecoded_prevRecoded_T, _io_out_bits_store_prevUnrecoded_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded = {io_out_bits_store_prevUnrecoded_prevRecoded_hi, _io_out_bits_store_prevUnrecoded_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp = io_out_bits_store_prevUnrecoded_prevRecoded[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_0 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T = io_out_bits_store_prevUnrecoded_prevRecoded[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_1, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_1[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_1[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_1[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_3 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T = io_out_bits_store_prevUnrecoded_unrecoded[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_1 = io_out_bits_store_prevRecoded[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_2 = &_io_out_bits_store_prevUnrecoded_T_1; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_3 = io_out_bits_store_prevUnrecoded_unrecoded[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_4 = _io_out_bits_store_prevUnrecoded_T_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded : _io_out_bits_store_prevUnrecoded_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded = {_io_out_bits_store_prevUnrecoded_T, _io_out_bits_store_prevUnrecoded_T_4}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T = io_out_bits_store_unrecoded[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_2 = &_io_out_bits_store_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_3 = io_out_bits_store_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_4 = _io_out_bits_store_T_2 ? io_out_bits_store_prevUnrecoded : _io_out_bits_store_T_3; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_5 = {_io_out_bits_store_T, _io_out_bits_store_T_4}; // @[FPU.scala:446:{10,21,44}] wire [15:0] _io_out_bits_store_T_6 = _io_out_bits_store_T_5[15:0]; // @[FPU.scala:446:10, :480:82] wire [31:0] _io_out_bits_store_T_7 = {2{_io_out_bits_store_T_6}}; // @[FPU.scala:480:{49,82}] wire [63:0] _io_out_bits_store_T_8 = {2{_io_out_bits_store_T_7}}; // @[FPU.scala:480:49] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_1 = _io_out_bits_store_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_1_isZero = io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_unrecoded_rawIn_exp_1[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_unrecoded_rawIn_exp_1[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_1_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_1_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_1_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_1_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_1_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_unrecoded_rawIn_1_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_2 = io_out_bits_store_unrecoded_rawIn_1_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_3 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_1 = _io_out_bits_store_unrecoded_denormShiftDist_T_3[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_3 = _io_out_bits_store_unrecoded_denormFract_T_2 >> io_out_bits_store_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_1 = _io_out_bits_store_unrecoded_denormFract_T_3[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_6 = io_out_bits_store_unrecoded_rawIn_1_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_6} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_8 = _io_out_bits_store_unrecoded_expOut_T_7[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_9 = io_out_bits_store_unrecoded_isSubnormal_1 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_10 = io_out_bits_store_unrecoded_rawIn_1_isNaN | io_out_bits_store_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_11 = {11{_io_out_bits_store_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_1 = _io_out_bits_store_unrecoded_expOut_T_9 | _io_out_bits_store_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_2 = io_out_bits_store_unrecoded_rawIn_1_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_3 = io_out_bits_store_unrecoded_rawIn_1_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_1 = io_out_bits_store_unrecoded_isSubnormal_1 ? io_out_bits_store_unrecoded_denormFract_1 : _io_out_bits_store_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_1 = {io_out_bits_store_unrecoded_rawIn_1_sign, io_out_bits_store_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_1 = {io_out_bits_store_unrecoded_hi_1, io_out_bits_store_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_1 = {_io_out_bits_store_prevRecoded_T_3, _io_out_bits_store_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_1 = {io_out_bits_store_prevRecoded_hi_1, _io_out_bits_store_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1 = io_out_bits_store_prevRecoded_1[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevRecoded_1[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevRecoded_1[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_3[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_3[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_6} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_7[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_9 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_1 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_1, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_3 = io_out_bits_store_prevRecoded_1[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_4 = io_out_bits_store_prevRecoded_1[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_5 = io_out_bits_store_prevRecoded_1[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_1 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_3, _io_out_bits_store_prevUnrecoded_prevRecoded_T_4}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_1 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_1, _io_out_bits_store_prevUnrecoded_prevRecoded_T_5}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_1 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_1; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_2; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_3; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_3; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_1 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_4; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_5; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1 = io_out_bits_store_prevUnrecoded_prevRecoded_1[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_1; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_1}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_1; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_1; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_4}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6 = io_out_bits_store_prevUnrecoded_prevRecoded_1[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_5, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_6}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_7; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_2}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_3[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_2 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_1; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_3[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_6} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_7[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_8; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_10}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_9 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_11; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_2; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_1 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_1 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_3; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_1_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_1}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_1 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_1, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_1}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_1[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_6 = io_out_bits_store_prevRecoded_1[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_7 = &_io_out_bits_store_prevUnrecoded_T_6; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_1[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_9 = _io_out_bits_store_prevUnrecoded_T_7 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_1 : _io_out_bits_store_prevUnrecoded_T_8; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded_1 = {_io_out_bits_store_prevUnrecoded_T_5, _io_out_bits_store_prevUnrecoded_T_9}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_9 = io_out_bits_store_unrecoded_1[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_11 = &_io_out_bits_store_T_10; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_12 = io_out_bits_store_unrecoded_1[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_13 = _io_out_bits_store_T_11 ? io_out_bits_store_prevUnrecoded_1 : _io_out_bits_store_T_12; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_14 = {_io_out_bits_store_T_9, _io_out_bits_store_T_13}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_15 = _io_out_bits_store_T_14[31:0]; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_16 = {2{_io_out_bits_store_T_15}}; // @[FPU.scala:480:{49,82}] wire [2:0] _io_out_bits_store_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_unrecoded_rawIn_isZero_2 = _io_out_bits_store_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_unrecoded_rawIn_2_isZero = io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_unrecoded_rawIn_exp_2[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire [12:0] _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] io_out_bits_store_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] io_out_bits_store_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_unrecoded_rawIn_exp_2[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_unrecoded_rawIn_2_isNaN = _io_out_bits_store_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_unrecoded_rawIn_2_isInf = _io_out_bits_store_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign io_out_bits_store_unrecoded_rawIn_2_sign = _io_out_bits_store_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_unrecoded_rawIn_2_sExp = _io_out_bits_store_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] assign _io_out_bits_store_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_unrecoded_rawIn_2_sig = _io_out_bits_store_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_unrecoded_rawIn_2_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_unrecoded_denormShiftDist_T_4 = io_out_bits_store_unrecoded_rawIn_2_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _io_out_bits_store_unrecoded_denormShiftDist_T_5 = 7'h1 - {1'h0, _io_out_bits_store_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] io_out_bits_store_unrecoded_denormShiftDist_2 = _io_out_bits_store_unrecoded_denormShiftDist_T_5[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _io_out_bits_store_unrecoded_denormFract_T_5 = _io_out_bits_store_unrecoded_denormFract_T_4 >> io_out_bits_store_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] io_out_bits_store_unrecoded_denormFract_2 = _io_out_bits_store_unrecoded_denormFract_T_5[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_12 = io_out_bits_store_unrecoded_rawIn_2_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _io_out_bits_store_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_unrecoded_expOut_T_12} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_14 = _io_out_bits_store_unrecoded_expOut_T_13[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_15 = io_out_bits_store_unrecoded_isSubnormal_2 ? 11'h0 : _io_out_bits_store_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_unrecoded_expOut_T_16 = io_out_bits_store_unrecoded_rawIn_2_isNaN | io_out_bits_store_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_unrecoded_expOut_T_17 = {11{_io_out_bits_store_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] io_out_bits_store_unrecoded_expOut_2 = _io_out_bits_store_unrecoded_expOut_T_15 | _io_out_bits_store_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_4 = io_out_bits_store_unrecoded_rawIn_2_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _io_out_bits_store_unrecoded_fractOut_T_5 = io_out_bits_store_unrecoded_rawIn_2_isInf ? 52'h0 : _io_out_bits_store_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] io_out_bits_store_unrecoded_fractOut_2 = io_out_bits_store_unrecoded_isSubnormal_2 ? io_out_bits_store_unrecoded_denormFract_2 : _io_out_bits_store_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] io_out_bits_store_unrecoded_hi_2 = {io_out_bits_store_unrecoded_rawIn_2_sign, io_out_bits_store_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] io_out_bits_store_unrecoded_2 = {io_out_bits_store_unrecoded_hi_2, io_out_bits_store_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [1:0] io_out_bits_store_prevRecoded_hi_2 = {_io_out_bits_store_prevRecoded_T_6, _io_out_bits_store_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] io_out_bits_store_prevRecoded_2 = {io_out_bits_store_prevRecoded_hi_2, _io_out_bits_store_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2 = io_out_bits_store_prevRecoded_2[31:23]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevRecoded_2[32]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_unrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_unrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevRecoded_2[22:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_unrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5 = 6'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_T_5[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_unrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_unrecoded_denormFract_T_5[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_12} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_13[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? 8'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isNaN | io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17 = {8{_io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] io_out_bits_store_prevUnrecoded_unrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_15 | _io_out_bits_store_prevUnrecoded_unrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_isInf ? 23'h0 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_unrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_unrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_unrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] io_out_bits_store_prevUnrecoded_unrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_unrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_unrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] io_out_bits_store_prevUnrecoded_unrecoded_2 = {io_out_bits_store_prevUnrecoded_unrecoded_hi_2, io_out_bits_store_prevUnrecoded_unrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_6 = io_out_bits_store_prevRecoded_2[15]; // @[FPU.scala:441:28, :442:10] wire _io_out_bits_store_prevUnrecoded_prevRecoded_T_7 = io_out_bits_store_prevRecoded_2[23]; // @[FPU.scala:441:28, :443:10] wire [14:0] _io_out_bits_store_prevUnrecoded_prevRecoded_T_8 = io_out_bits_store_prevRecoded_2[14:0]; // @[FPU.scala:441:28, :444:10] wire [1:0] io_out_bits_store_prevUnrecoded_prevRecoded_hi_2 = {_io_out_bits_store_prevUnrecoded_prevRecoded_T_6, _io_out_bits_store_prevUnrecoded_prevRecoded_T_7}; // @[FPU.scala:441:28, :442:10, :443:10] wire [16:0] io_out_bits_store_prevUnrecoded_prevRecoded_2 = {io_out_bits_store_prevUnrecoded_prevRecoded_hi_2, _io_out_bits_store_prevUnrecoded_prevRecoded_T_8}; // @[FPU.scala:441:28, :444:10] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[15:10]; // @[FPU.scala:441:28] wire [2:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:3]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_T_2 == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isZero = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[5:4]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 = &_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_T_2; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:57:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:59:25] wire [6:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:60:27] wire [11:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig; // @[rawFloatFromRecFN.scala:55:23] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2[3]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_4; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isNaN_T_5; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7 = ~_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_6; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isSpecial_2 & _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_7; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_isInf_T_8; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2 = io_out_bits_store_prevUnrecoded_prevRecoded_2[16]; // @[FPU.scala:441:28] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sign_T_2; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2 = {1'h0, io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_exp_2}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sExp_T_2; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8 = ~io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_isZero_2; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_8}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10 = io_out_bits_store_prevUnrecoded_prevRecoded_2[9:0]; // @[FPU.scala:441:28] assign _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11 = {_io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_9, _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_10}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig = _io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_out_sig_T_11; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 = $signed(io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp) < 7'sh12; // @[rawFloatFromRecFN.scala:55:23] wire [3:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[3:0]; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5 = 5'h1 - {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_4}; // @[fNFromRecFN.scala:52:{35,47}] wire [3:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_T_5[3:0]; // @[fNFromRecFN.scala:52:35] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[11:1]; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_4 >> io_out_bits_store_prevUnrecoded_prevUnrecoded_denormShiftDist_2; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_T_5[9:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13 = {1'h0, _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_12} - 6'h11; // @[fNFromRecFN.scala:58:{27,45}] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_13[4:0]; // @[fNFromRecFN.scala:58:45] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? 5'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_14; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isNaN | io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17 = {5{_io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_16}}; // @[fNFromRecFN.scala:60:{21,44}] wire [4:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2 = _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_15 | _io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_T_17; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sig[9:0]; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5 = io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_isInf ? 10'h0 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_4; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2 = io_out_bits_store_prevUnrecoded_prevUnrecoded_isSubnormal_2 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_denormFract_2 : _io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_T_5; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [5:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_rawIn_2_sign, io_out_bits_store_prevUnrecoded_prevUnrecoded_expOut_2}; // @[rawFloatFromRecFN.scala:55:23] wire [15:0] io_out_bits_store_prevUnrecoded_prevUnrecoded_2 = {io_out_bits_store_prevUnrecoded_prevUnrecoded_hi_2, io_out_bits_store_prevUnrecoded_prevUnrecoded_fractOut_2}; // @[fNFromRecFN.scala:62:16, :66:12] wire [15:0] _io_out_bits_store_prevUnrecoded_T_10 = io_out_bits_store_prevUnrecoded_unrecoded_2[31:16]; // @[FPU.scala:446:21] wire [2:0] _io_out_bits_store_prevUnrecoded_T_11 = io_out_bits_store_prevRecoded_2[31:29]; // @[FPU.scala:249:25, :441:28] wire _io_out_bits_store_prevUnrecoded_T_12 = &_io_out_bits_store_prevUnrecoded_T_11; // @[FPU.scala:249:{25,56}] wire [15:0] _io_out_bits_store_prevUnrecoded_T_13 = io_out_bits_store_prevUnrecoded_unrecoded_2[15:0]; // @[FPU.scala:446:81] wire [15:0] _io_out_bits_store_prevUnrecoded_T_14 = _io_out_bits_store_prevUnrecoded_T_12 ? io_out_bits_store_prevUnrecoded_prevUnrecoded_2 : _io_out_bits_store_prevUnrecoded_T_13; // @[FPU.scala:249:56, :446:{44,81}] wire [31:0] io_out_bits_store_prevUnrecoded_2 = {_io_out_bits_store_prevUnrecoded_T_10, _io_out_bits_store_prevUnrecoded_T_14}; // @[FPU.scala:446:{10,21,44}] wire [31:0] _io_out_bits_store_T_17 = io_out_bits_store_unrecoded_2[63:32]; // @[FPU.scala:446:21] wire _io_out_bits_store_T_19 = &_io_out_bits_store_T_18; // @[FPU.scala:249:{25,56}] wire [31:0] _io_out_bits_store_T_20 = io_out_bits_store_unrecoded_2[31:0]; // @[FPU.scala:446:81] wire [31:0] _io_out_bits_store_T_21 = _io_out_bits_store_T_19 ? io_out_bits_store_prevUnrecoded_2 : _io_out_bits_store_T_20; // @[FPU.scala:249:56, :446:{10,44,81}] wire [63:0] _io_out_bits_store_T_22 = {_io_out_bits_store_T_17, _io_out_bits_store_T_21}; // @[FPU.scala:446:{10,21,44}] wire [63:0] _io_out_bits_store_T_23 = _io_out_bits_store_T_22; // @[FPU.scala:446:10, :480:82] wire [63:0] _io_out_bits_store_T_25 = _io_out_bits_store_T_24 ? _io_out_bits_store_T_16 : _io_out_bits_store_T_8; // @[package.scala:39:{76,86}] wire [63:0] _io_out_bits_store_T_27 = _io_out_bits_store_T_26 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_25; // @[package.scala:39:{76,86}] wire _io_out_bits_store_T_28 = &in_typeTagOut; // @[package.scala:39:86] assign _io_out_bits_store_T_29 = _io_out_bits_store_T_28 ? _io_out_bits_store_T_23 : _io_out_bits_store_T_27; // @[package.scala:39:{76,86}] assign io_out_bits_store_0 = _io_out_bits_store_T_29; // @[package.scala:39:76] wire [31:0] _io_out_bits_toint_T = toint[31:0]; // @[FPU.scala:478:26, :481:59] wire _io_out_bits_toint_T_1 = _io_out_bits_toint_T[31]; // @[package.scala:132:38] wire [31:0] _io_out_bits_toint_T_2 = {32{_io_out_bits_toint_T_1}}; // @[package.scala:132:{20,38}] wire [63:0] _io_out_bits_toint_T_3 = {_io_out_bits_toint_T_2, _io_out_bits_toint_T}; // @[package.scala:132:{15,20}] assign _io_out_bits_toint_T_6 = _io_out_bits_toint_T_5 ? _io_out_bits_toint_T_4 : _io_out_bits_toint_T_3; // @[package.scala:39:{76,86}, :132:15] assign io_out_bits_toint_0 = _io_out_bits_toint_T_6; // @[package.scala:39:76] wire [62:0] _classify_out_fractOut_T = {classify_out_fractIn, 11'h0}; // @[FPU.scala:275:20, :277:28] wire [9:0] classify_out_fractOut = _classify_out_fractOut_T[62:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode = classify_out_expIn[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T = {1'h0, classify_out_expIn} + 13'h20; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_1 = _classify_out_expOut_commonCase_T[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_2 = {1'h0, _classify_out_expOut_commonCase_T_1} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase = _classify_out_expOut_commonCase_T_2[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T = classify_out_expOut_expCode == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_1 = classify_out_expOut_expCode > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_2 = _classify_out_expOut_T | _classify_out_expOut_T_1; // @[FPU.scala:281:{19,27,38}] wire [2:0] _classify_out_expOut_T_3 = classify_out_expOut_commonCase[2:0]; // @[FPU.scala:280:50, :281:69] wire [5:0] _classify_out_expOut_T_4 = {classify_out_expOut_expCode, _classify_out_expOut_T_3}; // @[FPU.scala:279:26, :281:{49,69}] wire [5:0] _classify_out_expOut_T_5 = classify_out_expOut_commonCase[5:0]; // @[FPU.scala:280:50, :281:97] wire [5:0] classify_out_expOut = _classify_out_expOut_T_2 ? _classify_out_expOut_T_4 : _classify_out_expOut_T_5; // @[FPU.scala:281:{10,27,49,97}] wire [6:0] classify_out_hi = {classify_out_sign, classify_out_expOut}; // @[FPU.scala:274:17, :281:10, :283:8] wire [16:0] _classify_out_T = {classify_out_hi, classify_out_fractOut}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_1 = _classify_out_T[16]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code = _classify_out_T[15:13]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi = classify_out_code[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial = &classify_out_codeHi; // @[FPU.scala:255:22, :256:28] wire [3:0] _classify_out_isHighSubnormalIn_T = _classify_out_T[13:10]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn = _classify_out_isHighSubnormalIn_T < 4'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T = classify_out_code == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_1 = classify_out_codeHi == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_1; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_1 = _GEN_1; // @[FPU.scala:259:46] wire _classify_out_isNormal_T; // @[FPU.scala:260:27] assign _classify_out_isNormal_T = _GEN_1; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_2 = _classify_out_isSubnormal_T_1 & classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal = _classify_out_isSubnormal_T | _classify_out_isSubnormal_T_2; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_1 = ~classify_out_isHighSubnormalIn; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_2 = _classify_out_isNormal_T & _classify_out_isNormal_T_1; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_3 = classify_out_codeHi == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal = _classify_out_isNormal_T_2 | _classify_out_isNormal_T_3; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero = classify_out_code == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T = classify_out_code[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_1 = ~_classify_out_isInf_T; // @[FPU.scala:262:{30,35}] wire classify_out_isInf = classify_out_isSpecial & _classify_out_isInf_T_1; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN = &classify_out_code; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T = _classify_out_T[9]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_1 = ~_classify_out_isSNaN_T; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN = classify_out_isNaN & _classify_out_isSNaN_T_1; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN = classify_out_isNaN & _classify_out_isQNaN_T; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_1 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_2 = classify_out_isInf & _classify_out_T_1; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_3 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_4 = classify_out_isNormal & _classify_out_T_3; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_5 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_6 = classify_out_isSubnormal & _classify_out_T_5; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_7 = ~classify_out_sign_1; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_8 = classify_out_isZero & _classify_out_T_7; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_9 = classify_out_isZero & classify_out_sign_1; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_10 = classify_out_isSubnormal & classify_out_sign_1; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_11 = classify_out_isNormal & classify_out_sign_1; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_12 = classify_out_isInf & classify_out_sign_1; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo = {_classify_out_T_11, _classify_out_T_12}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi = {_classify_out_T_8, _classify_out_T_9}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi = {classify_out_lo_hi_hi, _classify_out_T_10}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo = {classify_out_lo_hi, classify_out_lo_lo}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo = {_classify_out_T_4, _classify_out_T_6}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi = {classify_out_isQNaN, classify_out_isSNaN}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi = {classify_out_hi_hi_hi, _classify_out_T_2}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_1 = {classify_out_hi_hi, classify_out_hi_lo}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_13 = {classify_out_hi_1, classify_out_lo}; // @[FPU.scala:267:8] wire [75:0] _classify_out_fractOut_T_1 = {classify_out_fractIn_1, 24'h0}; // @[FPU.scala:275:20, :277:28] wire [22:0] classify_out_fractOut_1 = _classify_out_fractOut_T_1[75:53]; // @[FPU.scala:277:{28,38}] wire [2:0] classify_out_expOut_expCode_1 = classify_out_expIn_1[11:9]; // @[FPU.scala:276:18, :279:26] wire [12:0] _classify_out_expOut_commonCase_T_3 = {1'h0, classify_out_expIn_1} + 13'h100; // @[FPU.scala:276:18, :280:31] wire [11:0] _classify_out_expOut_commonCase_T_4 = _classify_out_expOut_commonCase_T_3[11:0]; // @[FPU.scala:280:31] wire [12:0] _classify_out_expOut_commonCase_T_5 = {1'h0, _classify_out_expOut_commonCase_T_4} - 13'h800; // @[FPU.scala:280:{31,50}] wire [11:0] classify_out_expOut_commonCase_1 = _classify_out_expOut_commonCase_T_5[11:0]; // @[FPU.scala:280:50] wire _classify_out_expOut_T_6 = classify_out_expOut_expCode_1 == 3'h0; // @[FPU.scala:279:26, :281:19] wire _classify_out_expOut_T_7 = classify_out_expOut_expCode_1 > 3'h5; // @[FPU.scala:279:26, :281:38] wire _classify_out_expOut_T_8 = _classify_out_expOut_T_6 | _classify_out_expOut_T_7; // @[FPU.scala:281:{19,27,38}] wire [5:0] _classify_out_expOut_T_9 = classify_out_expOut_commonCase_1[5:0]; // @[FPU.scala:280:50, :281:69] wire [8:0] _classify_out_expOut_T_10 = {classify_out_expOut_expCode_1, _classify_out_expOut_T_9}; // @[FPU.scala:279:26, :281:{49,69}] wire [8:0] _classify_out_expOut_T_11 = classify_out_expOut_commonCase_1[8:0]; // @[FPU.scala:280:50, :281:97] wire [8:0] classify_out_expOut_1 = _classify_out_expOut_T_8 ? _classify_out_expOut_T_10 : _classify_out_expOut_T_11; // @[FPU.scala:281:{10,27,49,97}] wire [9:0] classify_out_hi_2 = {classify_out_sign_2, classify_out_expOut_1}; // @[FPU.scala:274:17, :281:10, :283:8] wire [32:0] _classify_out_T_14 = {classify_out_hi_2, classify_out_fractOut_1}; // @[FPU.scala:277:38, :283:8] wire classify_out_sign_3 = _classify_out_T_14[32]; // @[FPU.scala:253:17, :283:8] wire [2:0] classify_out_code_1 = _classify_out_T_14[31:29]; // @[FPU.scala:254:17, :283:8] wire [1:0] classify_out_codeHi_1 = classify_out_code_1[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_1 = &classify_out_codeHi_1; // @[FPU.scala:255:22, :256:28] wire [6:0] _classify_out_isHighSubnormalIn_T_1 = _classify_out_T_14[29:23]; // @[FPU.scala:258:30, :283:8] wire classify_out_isHighSubnormalIn_1 = _classify_out_isHighSubnormalIn_T_1 < 7'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_3 = classify_out_code_1 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_2 = classify_out_codeHi_1 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_4; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_4 = _GEN_2; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_4; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_4 = _GEN_2; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_5 = _classify_out_isSubnormal_T_4 & classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_1 = _classify_out_isSubnormal_T_3 | _classify_out_isSubnormal_T_5; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_5 = ~classify_out_isHighSubnormalIn_1; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_6 = _classify_out_isNormal_T_4 & _classify_out_isNormal_T_5; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_7 = classify_out_codeHi_1 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_1 = _classify_out_isNormal_T_6 | _classify_out_isNormal_T_7; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_1 = classify_out_code_1 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_2 = classify_out_code_1[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_3 = ~_classify_out_isInf_T_2; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_1 = classify_out_isSpecial_1 & _classify_out_isInf_T_3; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_1 = &classify_out_code_1; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_2 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :283:8] wire _classify_out_isQNaN_T_1 = _classify_out_T_14[22]; // @[FPU.scala:264:29, :265:28, :283:8] wire _classify_out_isSNaN_T_3 = ~_classify_out_isSNaN_T_2; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_1 = classify_out_isNaN_1 & _classify_out_isSNaN_T_3; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_1 = classify_out_isNaN_1 & _classify_out_isQNaN_T_1; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_15 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_16 = classify_out_isInf_1 & _classify_out_T_15; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_17 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_18 = classify_out_isNormal_1 & _classify_out_T_17; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_19 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_20 = classify_out_isSubnormal_1 & _classify_out_T_19; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_21 = ~classify_out_sign_3; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_22 = classify_out_isZero_1 & _classify_out_T_21; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_23 = classify_out_isZero_1 & classify_out_sign_3; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_24 = classify_out_isSubnormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_25 = classify_out_isNormal_1 & classify_out_sign_3; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_26 = classify_out_isInf_1 & classify_out_sign_3; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_1 = {_classify_out_T_25, _classify_out_T_26}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_1 = {_classify_out_T_22, _classify_out_T_23}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_1 = {classify_out_lo_hi_hi_1, _classify_out_T_24}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_1 = {classify_out_lo_hi_1, classify_out_lo_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_1 = {_classify_out_T_18, _classify_out_T_20}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_1 = {classify_out_isQNaN_1, classify_out_isSNaN_1}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_1 = {classify_out_hi_hi_hi_1, _classify_out_T_16}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_3 = {classify_out_hi_hi_1, classify_out_hi_lo_1}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_27 = {classify_out_hi_3, classify_out_lo_1}; // @[FPU.scala:267:8] wire [1:0] classify_out_codeHi_2 = classify_out_code_2[2:1]; // @[FPU.scala:254:17, :255:22] wire classify_out_isSpecial_2 = &classify_out_codeHi_2; // @[FPU.scala:255:22, :256:28] wire [9:0] _classify_out_isHighSubnormalIn_T_2 = in_in1[61:52]; // @[FPU.scala:258:30, :466:21] wire classify_out_isHighSubnormalIn_2 = _classify_out_isHighSubnormalIn_T_2 < 10'h2; // @[FPU.scala:258:{30,55}] wire _classify_out_isSubnormal_T_6 = classify_out_code_2 == 3'h1; // @[FPU.scala:254:17, :259:28] wire _GEN_3 = classify_out_codeHi_2 == 2'h1; // @[FPU.scala:255:22, :259:46] wire _classify_out_isSubnormal_T_7; // @[FPU.scala:259:46] assign _classify_out_isSubnormal_T_7 = _GEN_3; // @[FPU.scala:259:46] wire _classify_out_isNormal_T_8; // @[FPU.scala:260:27] assign _classify_out_isNormal_T_8 = _GEN_3; // @[FPU.scala:259:46, :260:27] wire _classify_out_isSubnormal_T_8 = _classify_out_isSubnormal_T_7 & classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :259:{46,54}] wire classify_out_isSubnormal_2 = _classify_out_isSubnormal_T_6 | _classify_out_isSubnormal_T_8; // @[FPU.scala:259:{28,36,54}] wire _classify_out_isNormal_T_9 = ~classify_out_isHighSubnormalIn_2; // @[FPU.scala:258:55, :260:38] wire _classify_out_isNormal_T_10 = _classify_out_isNormal_T_8 & _classify_out_isNormal_T_9; // @[FPU.scala:260:{27,35,38}] wire _classify_out_isNormal_T_11 = classify_out_codeHi_2 == 2'h2; // @[FPU.scala:255:22, :260:67] wire classify_out_isNormal_2 = _classify_out_isNormal_T_10 | _classify_out_isNormal_T_11; // @[FPU.scala:260:{35,57,67}] wire classify_out_isZero_2 = classify_out_code_2 == 3'h0; // @[FPU.scala:254:17, :261:23] wire _classify_out_isInf_T_4 = classify_out_code_2[0]; // @[FPU.scala:254:17, :262:35] wire _classify_out_isInf_T_5 = ~_classify_out_isInf_T_4; // @[FPU.scala:262:{30,35}] wire classify_out_isInf_2 = classify_out_isSpecial_2 & _classify_out_isInf_T_5; // @[FPU.scala:256:28, :262:{27,30}] wire classify_out_isNaN_2 = &classify_out_code_2; // @[FPU.scala:254:17, :263:22] wire _classify_out_isSNaN_T_4 = in_in1[51]; // @[FPU.scala:264:29, :466:21] wire _classify_out_isQNaN_T_2 = in_in1[51]; // @[FPU.scala:264:29, :265:28, :466:21] wire _classify_out_isSNaN_T_5 = ~_classify_out_isSNaN_T_4; // @[FPU.scala:264:{27,29}] wire classify_out_isSNaN_2 = classify_out_isNaN_2 & _classify_out_isSNaN_T_5; // @[FPU.scala:263:22, :264:{24,27}] wire classify_out_isQNaN_2 = classify_out_isNaN_2 & _classify_out_isQNaN_T_2; // @[FPU.scala:263:22, :265:{24,28}] wire _classify_out_T_28 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34] wire _classify_out_T_29 = classify_out_isInf_2 & _classify_out_T_28; // @[FPU.scala:262:27, :267:{31,34}] wire _classify_out_T_30 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:{34,53}] wire _classify_out_T_31 = classify_out_isNormal_2 & _classify_out_T_30; // @[FPU.scala:260:57, :267:{50,53}] wire _classify_out_T_32 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:24] wire _classify_out_T_33 = classify_out_isSubnormal_2 & _classify_out_T_32; // @[FPU.scala:259:36, :268:{21,24}] wire _classify_out_T_34 = ~classify_out_sign_4; // @[FPU.scala:253:17, :267:34, :268:41] wire _classify_out_T_35 = classify_out_isZero_2 & _classify_out_T_34; // @[FPU.scala:261:23, :268:{38,41}] wire _classify_out_T_36 = classify_out_isZero_2 & classify_out_sign_4; // @[FPU.scala:253:17, :261:23, :268:55] wire _classify_out_T_37 = classify_out_isSubnormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :259:36, :269:21] wire _classify_out_T_38 = classify_out_isNormal_2 & classify_out_sign_4; // @[FPU.scala:253:17, :260:57, :269:39] wire _classify_out_T_39 = classify_out_isInf_2 & classify_out_sign_4; // @[FPU.scala:253:17, :262:27, :269:54] wire [1:0] classify_out_lo_lo_2 = {_classify_out_T_38, _classify_out_T_39}; // @[FPU.scala:267:8, :269:{39,54}] wire [1:0] classify_out_lo_hi_hi_2 = {_classify_out_T_35, _classify_out_T_36}; // @[FPU.scala:267:8, :268:{38,55}] wire [2:0] classify_out_lo_hi_2 = {classify_out_lo_hi_hi_2, _classify_out_T_37}; // @[FPU.scala:267:8, :269:21] wire [4:0] classify_out_lo_2 = {classify_out_lo_hi_2, classify_out_lo_lo_2}; // @[FPU.scala:267:8] wire [1:0] classify_out_hi_lo_2 = {_classify_out_T_31, _classify_out_T_33}; // @[FPU.scala:267:{8,50}, :268:21] wire [1:0] classify_out_hi_hi_hi_2 = {classify_out_isQNaN_2, classify_out_isSNaN_2}; // @[FPU.scala:264:24, :265:24, :267:8] wire [2:0] classify_out_hi_hi_2 = {classify_out_hi_hi_hi_2, _classify_out_T_29}; // @[FPU.scala:267:{8,31}] wire [4:0] classify_out_hi_4 = {classify_out_hi_hi_2, classify_out_hi_lo_2}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_40 = {classify_out_hi_4, classify_out_lo_2}; // @[FPU.scala:267:8] wire [9:0] _classify_out_T_42 = _classify_out_T_41 ? _classify_out_T_27 : _classify_out_T_13; // @[package.scala:39:{76,86}] wire [9:0] _classify_out_T_44 = _classify_out_T_43 ? _classify_out_T_40 : _classify_out_T_42; // @[package.scala:39:{76,86}] wire _classify_out_T_45 = &in_typeTagOut; // @[package.scala:39:86] wire [9:0] classify_out = _classify_out_T_45 ? _classify_out_T_40 : _classify_out_T_44; // @[package.scala:39:{76,86}] wire [31:0] _toint_T = toint_ieee[63:32]; // @[package.scala:39:76] wire [31:0] _toint_T_7 = toint_ieee[63:32]; // @[package.scala:39:76] wire [63:0] _toint_T_1 = {_toint_T, 32'h0}; // @[FPU.scala:486:{41,52}] wire [63:0] _toint_T_2 = {54'h0, classify_out} | _toint_T_1; // @[package.scala:39:76] wire [2:0] _toint_T_3 = ~in_rm; // @[FPU.scala:466:21, :491:15] wire [1:0] _toint_T_4 = {_dcmp_io_lt, _dcmp_io_eq}; // @[FPU.scala:469:20, :491:27] wire [2:0] _toint_T_5 = {1'h0, _toint_T_3[1:0] & _toint_T_4}; // @[FPU.scala:491:{15,22,27}] wire _toint_T_6 = |_toint_T_5; // @[FPU.scala:491:{22,53}] wire [63:0] _toint_T_8 = {_toint_T_7, 32'h0}; // @[FPU.scala:491:{71,82}] wire [63:0] _toint_T_9 = {63'h0, _toint_T_6} | _toint_T_8; // @[FPU.scala:491:{53,57,82}] wire cvtType = in_typ[1]; // @[package.scala:163:13] assign intType = in_wflags ? ~in_ren2 & cvtType : ~(in_rm[0]) & _intType_T; // @[package.scala:163:13] wire _conv_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35] wire _narrow_io_signedOut_T = in_typ[0]; // @[FPU.scala:466:21, :501:35, :511:41] wire _conv_io_signedOut_T_1 = ~_conv_io_signedOut_T; // @[FPU.scala:501:{28,35}] wire [1:0] _io_out_bits_exc_T = _conv_io_intExceptionFlags[2:1]; // @[FPU.scala:498:24, :503:55] wire _io_out_bits_exc_T_1 = |_io_out_bits_exc_T; // @[FPU.scala:503:{55,62}] wire _io_out_bits_exc_T_2 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102] wire _io_out_bits_exc_T_5 = _conv_io_intExceptionFlags[0]; // @[FPU.scala:498:24, :503:102, :517:90] wire [3:0] io_out_bits_exc_hi = {_io_out_bits_exc_T_1, 3'h0}; // @[FPU.scala:503:{29,62}] wire [4:0] _io_out_bits_exc_T_3 = {io_out_bits_exc_hi, _io_out_bits_exc_T_2}; // @[FPU.scala:503:{29,102}] wire _narrow_io_signedOut_T_1 = ~_narrow_io_signedOut_T; // @[FPU.scala:511:{34,41}] wire _excSign_T_2 = &_excSign_T_1; // @[FPU.scala:249:{25,56}] wire _excSign_T_3 = ~_excSign_T_2; // @[FPU.scala:249:56, :513:62] wire excSign = _excSign_T & _excSign_T_3; // @[FPU.scala:513:{31,59,62}] wire _excOut_T = _conv_io_signedOut_T_1 == excSign; // @[FPU.scala:501:28, :513:59, :514:46] wire _excOut_T_1 = ~excSign; // @[FPU.scala:513:59, :514:69] wire [30:0] _excOut_T_2 = {31{_excOut_T_1}}; // @[FPU.scala:514:{63,69}] wire [31:0] excOut = {_excOut_T, _excOut_T_2}; // @[FPU.scala:514:{27,46,63}] wire _invalid_T = _conv_io_intExceptionFlags[2]; // @[FPU.scala:498:24, :515:50] wire _invalid_T_1 = _narrow_io_intExceptionFlags[1]; // @[FPU.scala:508:30, :515:84] wire invalid = _invalid_T | _invalid_T_1; // @[FPU.scala:515:{50,54,84}] wire [31:0] _toint_T_10 = _conv_io_out[63:32]; // @[FPU.scala:498:24, :516:53] wire [63:0] _toint_T_11 = {_toint_T_10, excOut}; // @[FPU.scala:514:27, :516:{40,53}] assign toint = in_wflags ? (in_ren2 ? _toint_T_9 : ~cvtType & invalid ? _toint_T_11 : _conv_io_out) : in_rm[0] ? _toint_T_2 : toint_ieee; // @[package.scala:39:76, :163:13] wire _io_out_bits_exc_T_4 = ~invalid; // @[FPU.scala:515:54, :517:53] wire _io_out_bits_exc_T_6 = _io_out_bits_exc_T_4 & _io_out_bits_exc_T_5; // @[FPU.scala:517:{53,62,90}] wire [3:0] io_out_bits_exc_hi_1 = {invalid, 3'h0}; // @[FPU.scala:515:54, :517:33] wire [4:0] _io_out_bits_exc_T_7 = {io_out_bits_exc_hi_1, _io_out_bits_exc_T_6}; // @[FPU.scala:517:{33,62}] assign io_out_bits_exc_0 = in_wflags ? (in_ren2 ? _dcmp_io_exceptionFlags : cvtType ? _io_out_bits_exc_T_3 : _io_out_bits_exc_T_7) : 5'h0; // @[package.scala:163:13] wire _io_out_bits_lt_T_1 = $signed(_io_out_bits_lt_T) < 65'sh0; // @[FPU.scala:524:{46,53}] wire _io_out_bits_lt_T_3 = $signed(_io_out_bits_lt_T_2) > -65'sh1; // @[FPU.scala:524:{72,79}] wire _io_out_bits_lt_T_4 = _io_out_bits_lt_T_1 & _io_out_bits_lt_T_3; // @[FPU.scala:524:{53,59,79}] assign _io_out_bits_lt_T_5 = _dcmp_io_lt | _io_out_bits_lt_T_4; // @[FPU.scala:469:20, :524:{32,59}] assign io_out_bits_lt_0 = _io_out_bits_lt_T_5; // @[FPU.scala:453:7, :524:32] always @(posedge clock) begin // @[FPU.scala:453:7] if (io_in_valid_0) begin // @[FPU.scala:453:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:453:7, :466:21] in_wen <= io_in_bits_wen_0; // @[FPU.scala:453:7, :466:21] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:453:7, :466:21] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:453:7, :466:21] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:453:7, :466:21] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:453:7, :466:21] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:453:7, :466:21] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:453:7, :466:21] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:453:7, :466:21] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:453:7, :466:21] in_toint <= io_in_bits_toint_0; // @[FPU.scala:453:7, :466:21] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:453:7, :466:21] in_fma <= io_in_bits_fma_0; // @[FPU.scala:453:7, :466:21] in_div <= io_in_bits_div_0; // @[FPU.scala:453:7, :466:21] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:453:7, :466:21] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:453:7, :466:21] in_rm <= io_in_bits_rm_0; // @[FPU.scala:453:7, :466:21] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:453:7, :466:21] in_typ <= io_in_bits_typ_0; // @[FPU.scala:453:7, :466:21] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:453:7, :466:21] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:453:7, :466:21] in_in2 <= io_in_bits_in2_0; // @[FPU.scala:453:7, :466:21] in_in3 <= io_in_bits_in3_0; // @[FPU.scala:453:7, :466:21] end valid <= io_in_valid_0; // @[FPU.scala:453:7, :467:22] always @(posedge) CompareRecFN dcmp ( // @[FPU.scala:469:20] .io_a (in_in1), // @[FPU.scala:466:21] .io_b (in_in2), // @[FPU.scala:466:21] .io_signaling (_dcmp_io_signaling_T_1), // @[FPU.scala:472:24] .io_lt (_dcmp_io_lt), .io_eq (_dcmp_io_eq), .io_exceptionFlags (_dcmp_io_exceptionFlags) ); // @[FPU.scala:469:20] RecFNToIN_e11_s53_i64 conv ( // @[FPU.scala:498:24] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_conv_io_signedOut_T_1), // @[FPU.scala:501:28] .io_out (_conv_io_out), .io_intExceptionFlags (_conv_io_intExceptionFlags) ); // @[FPU.scala:498:24] RecFNToIN_e11_s53_i32 narrow ( // @[FPU.scala:508:30] .clock (clock), .reset (reset), .io_in (in_in1), // @[FPU.scala:466:21] .io_roundingMode (in_rm), // @[FPU.scala:466:21] .io_signedOut (_narrow_io_signedOut_T_1), // @[FPU.scala:511:34] .io_intExceptionFlags (_narrow_io_intExceptionFlags) ); // @[FPU.scala:508:30] assign io_out_bits_in_ldst = io_out_bits_in_ldst_0; // @[FPU.scala:453:7] assign io_out_bits_in_wen = io_out_bits_in_wen_0; // @[FPU.scala:453:7] assign io_out_bits_in_ren1 = io_out_bits_in_ren1_0; // @[FPU.scala:453:7] assign io_out_bits_in_ren2 = io_out_bits_in_ren2_0; // @[FPU.scala:453:7] assign io_out_bits_in_ren3 = io_out_bits_in_ren3_0; // @[FPU.scala:453:7] assign io_out_bits_in_swap12 = io_out_bits_in_swap12_0; // @[FPU.scala:453:7] assign io_out_bits_in_swap23 = io_out_bits_in_swap23_0; // @[FPU.scala:453:7] assign io_out_bits_in_typeTagIn = io_out_bits_in_typeTagIn_0; // @[FPU.scala:453:7] assign io_out_bits_in_typeTagOut = io_out_bits_in_typeTagOut_0; // @[FPU.scala:453:7] assign io_out_bits_in_fromint = io_out_bits_in_fromint_0; // @[FPU.scala:453:7] assign io_out_bits_in_toint = io_out_bits_in_toint_0; // @[FPU.scala:453:7] assign io_out_bits_in_fastpipe = io_out_bits_in_fastpipe_0; // @[FPU.scala:453:7] assign io_out_bits_in_fma = io_out_bits_in_fma_0; // @[FPU.scala:453:7] assign io_out_bits_in_div = io_out_bits_in_div_0; // @[FPU.scala:453:7] assign io_out_bits_in_sqrt = io_out_bits_in_sqrt_0; // @[FPU.scala:453:7] assign io_out_bits_in_wflags = io_out_bits_in_wflags_0; // @[FPU.scala:453:7] assign io_out_bits_in_rm = io_out_bits_in_rm_0; // @[FPU.scala:453:7] assign io_out_bits_in_fmaCmd = io_out_bits_in_fmaCmd_0; // @[FPU.scala:453:7] assign io_out_bits_in_typ = io_out_bits_in_typ_0; // @[FPU.scala:453:7] assign io_out_bits_in_fmt = io_out_bits_in_fmt_0; // @[FPU.scala:453:7] assign io_out_bits_in_in1 = io_out_bits_in_in1_0; // @[FPU.scala:453:7] assign io_out_bits_in_in2 = io_out_bits_in_in2_0; // @[FPU.scala:453:7] assign io_out_bits_in_in3 = io_out_bits_in_in3_0; // @[FPU.scala:453:7] assign io_out_bits_lt = io_out_bits_lt_0; // @[FPU.scala:453:7] assign io_out_bits_store = io_out_bits_store_0; // @[FPU.scala:453:7] assign io_out_bits_toint = io_out_bits_toint_0; // @[FPU.scala:453:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:453:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_261 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_261( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module TLSerdesser_serial_tl_0 : input clock : Clock input reset : Reset output auto : { client_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} output io : { ser : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}}[5], debug : { ser_busy : UInt<1>, des_busy : UInt<1>}} wire clientNodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clientNodeOut.d.bits.corrupt invalidate clientNodeOut.d.bits.data invalidate clientNodeOut.d.bits.denied invalidate clientNodeOut.d.bits.sink invalidate clientNodeOut.d.bits.source invalidate clientNodeOut.d.bits.size invalidate clientNodeOut.d.bits.param invalidate clientNodeOut.d.bits.opcode invalidate clientNodeOut.d.valid invalidate clientNodeOut.d.ready invalidate clientNodeOut.a.bits.corrupt invalidate clientNodeOut.a.bits.data invalidate clientNodeOut.a.bits.mask invalidate clientNodeOut.a.bits.address invalidate clientNodeOut.a.bits.source invalidate clientNodeOut.a.bits.size invalidate clientNodeOut.a.bits.param invalidate clientNodeOut.a.bits.opcode invalidate clientNodeOut.a.valid invalidate clientNodeOut.a.ready connect auto.client_out, clientNodeOut wire manager_tl : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, address : UInt<64>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<8>, source : UInt<8>, address : UInt<64>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<8>, source : UInt<8>, sink : UInt<8>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<8>}}} connect manager_tl.e.bits.sink, UInt<8>(0h0) connect manager_tl.e.valid, UInt<1>(0h0) connect manager_tl.e.ready, UInt<1>(0h0) connect manager_tl.d.bits.corrupt, UInt<1>(0h0) connect manager_tl.d.bits.data, UInt<64>(0h0) connect manager_tl.d.bits.denied, UInt<1>(0h0) connect manager_tl.d.bits.sink, UInt<8>(0h0) connect manager_tl.d.bits.source, UInt<8>(0h0) connect manager_tl.d.bits.size, UInt<8>(0h0) connect manager_tl.d.bits.param, UInt<2>(0h0) connect manager_tl.d.bits.opcode, UInt<3>(0h0) connect manager_tl.d.valid, UInt<1>(0h0) connect manager_tl.d.ready, UInt<1>(0h0) connect manager_tl.c.bits.corrupt, UInt<1>(0h0) connect manager_tl.c.bits.data, UInt<64>(0h0) connect manager_tl.c.bits.address, UInt<64>(0h0) connect manager_tl.c.bits.source, UInt<8>(0h0) connect manager_tl.c.bits.size, UInt<8>(0h0) connect manager_tl.c.bits.param, UInt<3>(0h0) connect manager_tl.c.bits.opcode, UInt<3>(0h0) connect manager_tl.c.valid, UInt<1>(0h0) connect manager_tl.c.ready, UInt<1>(0h0) connect manager_tl.b.bits.corrupt, UInt<1>(0h0) connect manager_tl.b.bits.data, UInt<64>(0h0) connect manager_tl.b.bits.mask, UInt<8>(0h0) connect manager_tl.b.bits.address, UInt<64>(0h0) connect manager_tl.b.bits.source, UInt<8>(0h0) connect manager_tl.b.bits.size, UInt<8>(0h0) connect manager_tl.b.bits.param, UInt<2>(0h0) connect manager_tl.b.bits.opcode, UInt<3>(0h0) connect manager_tl.b.valid, UInt<1>(0h0) connect manager_tl.b.ready, UInt<1>(0h0) connect manager_tl.a.bits.corrupt, UInt<1>(0h0) connect manager_tl.a.bits.data, UInt<64>(0h0) connect manager_tl.a.bits.mask, UInt<8>(0h0) connect manager_tl.a.bits.address, UInt<64>(0h0) connect manager_tl.a.bits.source, UInt<8>(0h0) connect manager_tl.a.bits.size, UInt<8>(0h0) connect manager_tl.a.bits.param, UInt<3>(0h0) connect manager_tl.a.bits.opcode, UInt<3>(0h0) connect manager_tl.a.valid, UInt<1>(0h0) connect manager_tl.a.ready, UInt<1>(0h0) inst out_channels_1_2 of TLDToBeat_serial_tl_0_a64d64s8k8z8c connect out_channels_1_2.clock, clock connect out_channels_1_2.reset, reset wire _out_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _out_channels_WIRE.bits.corrupt, UInt<1>(0h0) connect _out_channels_WIRE.bits.data, UInt<64>(0h0) connect _out_channels_WIRE.bits.mask, UInt<8>(0h0) connect _out_channels_WIRE.bits.address, UInt<32>(0h0) connect _out_channels_WIRE.bits.source, UInt<4>(0h0) connect _out_channels_WIRE.bits.size, UInt<4>(0h0) connect _out_channels_WIRE.bits.param, UInt<2>(0h0) connect _out_channels_WIRE.bits.opcode, UInt<3>(0h0) connect _out_channels_WIRE.valid, UInt<1>(0h0) connect _out_channels_WIRE.ready, UInt<1>(0h0) wire out_channels_3_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect out_channels_3_1.bits, _out_channels_WIRE.bits connect out_channels_3_1.valid, _out_channels_WIRE.valid connect out_channels_3_1.ready, _out_channels_WIRE.ready inst out_channels_3_2 of TLBToBeat_serial_tl_0_a64d64s8k8z8c connect out_channels_3_2.clock, clock connect out_channels_3_2.reset, reset connect io.ser[0].out.valid, UInt<1>(0h0) connect io.ser[1].out.valid, UInt<1>(0h0) connect io.ser[2].out.valid, UInt<1>(0h0) connect io.ser[3].out.valid, UInt<1>(0h0) connect io.ser[4].out.valid, UInt<1>(0h0) invalidate io.ser[0].out.bits.flit invalidate io.ser[1].out.bits.flit invalidate io.ser[2].out.bits.flit invalidate io.ser[3].out.bits.flit invalidate io.ser[4].out.bits.flit connect out_channels_1_2.io.protocol, clientNodeOut.d inst ser_1 of GenericSerializer_TLBeatw67_f32 connect ser_1.clock, clock connect ser_1.reset, reset connect ser_1.io.in, out_channels_1_2.io.beat connect io.ser[1].out.bits, ser_1.io.out.bits connect io.ser[1].out.valid, ser_1.io.out.valid connect ser_1.io.out.ready, io.ser[1].out.ready connect out_channels_3_2.io.protocol, out_channels_3_1 inst ser_3 of GenericSerializer_TLBeatw87_f32 connect ser_3.clock, clock connect ser_3.reset, reset connect ser_3.io.in, out_channels_3_2.io.beat connect io.ser[3].out.bits, ser_3.io.out.bits connect io.ser[3].out.valid, ser_3.io.out.valid connect ser_3.io.out.ready, io.ser[3].out.ready node _io_debug_ser_busy_T = or(ser_1.io.busy, ser_3.io.busy) connect io.debug.ser_busy, _io_debug_ser_busy_T wire _in_channels_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _in_channels_WIRE.bits.sink, UInt<4>(0h0) connect _in_channels_WIRE.valid, UInt<1>(0h0) connect _in_channels_WIRE.ready, UInt<1>(0h0) wire in_channels_0_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect in_channels_0_1.bits, _in_channels_WIRE.bits connect in_channels_0_1.valid, _in_channels_WIRE.valid connect in_channels_0_1.ready, _in_channels_WIRE.ready inst in_channels_0_2 of TLEFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_0_2.clock, clock connect in_channels_0_2.reset, reset inst in_channels_1_2 of TLDFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_1_2.clock, clock connect in_channels_1_2.reset, reset wire _in_channels_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _in_channels_WIRE_1.bits.corrupt, UInt<1>(0h0) connect _in_channels_WIRE_1.bits.data, UInt<64>(0h0) connect _in_channels_WIRE_1.bits.address, UInt<32>(0h0) connect _in_channels_WIRE_1.bits.source, UInt<4>(0h0) connect _in_channels_WIRE_1.bits.size, UInt<4>(0h0) connect _in_channels_WIRE_1.bits.param, UInt<3>(0h0) connect _in_channels_WIRE_1.bits.opcode, UInt<3>(0h0) connect _in_channels_WIRE_1.valid, UInt<1>(0h0) connect _in_channels_WIRE_1.ready, UInt<1>(0h0) wire in_channels_2_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect in_channels_2_1.bits, _in_channels_WIRE_1.bits connect in_channels_2_1.valid, _in_channels_WIRE_1.valid connect in_channels_2_1.ready, _in_channels_WIRE_1.ready inst in_channels_2_2 of TLCFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_2_2.clock, clock connect in_channels_2_2.reset, reset inst in_channels_3_2 of TLBFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_3_2.clock, clock connect in_channels_3_2.reset, reset inst in_channels_4_2 of TLAFromBeat_serial_tl_0_a64d64s8k8z8c connect in_channels_4_2.clock, clock connect in_channels_4_2.reset, reset connect in_channels_0_1.bits, in_channels_0_2.io.protocol.bits connect in_channels_0_1.valid, in_channels_0_2.io.protocol.valid connect in_channels_0_2.io.protocol.ready, in_channels_0_1.ready inst des_0 of GenericDeserializer_TLBeatw10_f32 connect des_0.clock, clock connect des_0.reset, reset connect des_0.io.in, io.ser[0].in connect in_channels_0_2.io.beat, des_0.io.out connect manager_tl.d.bits.corrupt, in_channels_1_2.io.protocol.bits.corrupt connect manager_tl.d.bits.data, in_channels_1_2.io.protocol.bits.data connect manager_tl.d.bits.denied, in_channels_1_2.io.protocol.bits.denied connect manager_tl.d.bits.sink, in_channels_1_2.io.protocol.bits.sink connect manager_tl.d.bits.source, in_channels_1_2.io.protocol.bits.source connect manager_tl.d.bits.size, in_channels_1_2.io.protocol.bits.size connect manager_tl.d.bits.param, in_channels_1_2.io.protocol.bits.param connect manager_tl.d.bits.opcode, in_channels_1_2.io.protocol.bits.opcode connect manager_tl.d.valid, in_channels_1_2.io.protocol.valid connect in_channels_1_2.io.protocol.ready, manager_tl.d.ready inst des_1 of GenericDeserializer_TLBeatw67_f32 connect des_1.clock, clock connect des_1.reset, reset connect des_1.io.in, io.ser[1].in connect in_channels_1_2.io.beat, des_1.io.out connect in_channels_2_1.bits, in_channels_2_2.io.protocol.bits connect in_channels_2_1.valid, in_channels_2_2.io.protocol.valid connect in_channels_2_2.io.protocol.ready, in_channels_2_1.ready inst des_2 of GenericDeserializer_TLBeatw88_f32 connect des_2.clock, clock connect des_2.reset, reset connect des_2.io.in, io.ser[2].in connect in_channels_2_2.io.beat, des_2.io.out connect manager_tl.b.bits.corrupt, in_channels_3_2.io.protocol.bits.corrupt connect manager_tl.b.bits.data, in_channels_3_2.io.protocol.bits.data connect manager_tl.b.bits.mask, in_channels_3_2.io.protocol.bits.mask connect manager_tl.b.bits.address, in_channels_3_2.io.protocol.bits.address connect manager_tl.b.bits.source, in_channels_3_2.io.protocol.bits.source connect manager_tl.b.bits.size, in_channels_3_2.io.protocol.bits.size connect manager_tl.b.bits.param, in_channels_3_2.io.protocol.bits.param connect manager_tl.b.bits.opcode, in_channels_3_2.io.protocol.bits.opcode connect manager_tl.b.valid, in_channels_3_2.io.protocol.valid connect in_channels_3_2.io.protocol.ready, manager_tl.b.ready inst des_3 of GenericDeserializer_TLBeatw87_f32 connect des_3.clock, clock connect des_3.reset, reset connect des_3.io.in, io.ser[3].in connect in_channels_3_2.io.beat, des_3.io.out connect clientNodeOut.a.bits, in_channels_4_2.io.protocol.bits connect clientNodeOut.a.valid, in_channels_4_2.io.protocol.valid connect in_channels_4_2.io.protocol.ready, clientNodeOut.a.ready inst des_4 of GenericDeserializer_TLBeatw88_f32_1 connect des_4.clock, clock connect des_4.reset, reset connect des_4.io.in, io.ser[4].in connect in_channels_4_2.io.beat, des_4.io.out node _io_debug_des_busy_T = or(des_0.io.busy, des_1.io.busy) node _io_debug_des_busy_T_1 = or(_io_debug_des_busy_T, des_2.io.busy) node _io_debug_des_busy_T_2 = or(_io_debug_des_busy_T_1, des_3.io.busy) node _io_debug_des_busy_T_3 = or(_io_debug_des_busy_T_2, des_4.io.busy) connect io.debug.des_busy, _io_debug_des_busy_T_3
module TLSerdesser_serial_tl_0( // @[TLSerdes.scala:39:9] input clock, // @[TLSerdes.scala:39:9] input reset, // @[TLSerdes.scala:39:9] input auto_client_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_client_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_client_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_client_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_client_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_client_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_client_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_client_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_client_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_client_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_client_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_client_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_client_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_client_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_client_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_client_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_client_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_client_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] output io_ser_0_in_ready, // @[TLSerdes.scala:40:16] input io_ser_0_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_0_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_1_in_ready, // @[TLSerdes.scala:40:16] input io_ser_1_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_1_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_1_out_ready, // @[TLSerdes.scala:40:16] output io_ser_1_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_1_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_2_in_ready, // @[TLSerdes.scala:40:16] input io_ser_2_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_2_in_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_3_in_ready, // @[TLSerdes.scala:40:16] input io_ser_3_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_3_in_bits_flit, // @[TLSerdes.scala:40:16] input io_ser_3_out_ready, // @[TLSerdes.scala:40:16] output io_ser_3_out_valid, // @[TLSerdes.scala:40:16] output [31:0] io_ser_3_out_bits_flit, // @[TLSerdes.scala:40:16] output io_ser_4_in_ready, // @[TLSerdes.scala:40:16] input io_ser_4_in_valid, // @[TLSerdes.scala:40:16] input [31:0] io_ser_4_in_bits_flit, // @[TLSerdes.scala:40:16] output io_debug_ser_busy, // @[TLSerdes.scala:40:16] output io_debug_des_busy // @[TLSerdes.scala:40:16] ); wire _des_4_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_4_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_4_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_4_io_busy; // @[TLSerdes.scala:86:23] wire _des_3_io_out_valid; // @[TLSerdes.scala:86:23] wire [84:0] _des_3_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_3_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_3_io_busy; // @[TLSerdes.scala:86:23] wire _des_2_io_out_valid; // @[TLSerdes.scala:86:23] wire [85:0] _des_2_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_2_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _des_1_io_out_valid; // @[TLSerdes.scala:86:23] wire [64:0] _des_1_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_1_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire _des_0_io_out_valid; // @[TLSerdes.scala:86:23] wire [7:0] _des_0_io_out_bits_payload; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_head; // @[TLSerdes.scala:86:23] wire _des_0_io_out_bits_tail; // @[TLSerdes.scala:86:23] wire [7:0] _in_channels_4_2_io_protocol_bits_size; // @[TLSerdes.scala:82:28] wire [7:0] _in_channels_4_2_io_protocol_bits_source; // @[TLSerdes.scala:82:28] wire [63:0] _in_channels_4_2_io_protocol_bits_address; // @[TLSerdes.scala:82:28] wire _in_channels_4_2_io_beat_ready; // @[TLSerdes.scala:82:28] wire _in_channels_3_2_io_beat_ready; // @[TLSerdes.scala:81:28] wire [7:0] _in_channels_2_2_io_protocol_bits_size; // @[TLSerdes.scala:80:28] wire [7:0] _in_channels_2_2_io_protocol_bits_source; // @[TLSerdes.scala:80:28] wire [63:0] _in_channels_2_2_io_protocol_bits_address; // @[TLSerdes.scala:80:28] wire _in_channels_2_2_io_beat_ready; // @[TLSerdes.scala:80:28] wire _in_channels_1_2_io_beat_ready; // @[TLSerdes.scala:79:28] wire [7:0] _in_channels_0_2_io_protocol_bits_sink; // @[TLSerdes.scala:78:28] wire _in_channels_0_2_io_beat_ready; // @[TLSerdes.scala:78:28] wire _ser_3_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_3_io_busy; // @[TLSerdes.scala:69:23] wire _ser_1_io_in_ready; // @[TLSerdes.scala:69:23] wire _ser_1_io_busy; // @[TLSerdes.scala:69:23] wire _out_channels_3_2_io_beat_bits_head; // @[TLSerdes.scala:62:50] wire _out_channels_3_2_io_beat_bits_tail; // @[TLSerdes.scala:62:50] wire _out_channels_1_2_io_beat_valid; // @[TLSerdes.scala:60:50] wire [64:0] _out_channels_1_2_io_beat_bits_payload; // @[TLSerdes.scala:60:50] wire _out_channels_1_2_io_beat_bits_head; // @[TLSerdes.scala:60:50] wire _out_channels_1_2_io_beat_bits_tail; // @[TLSerdes.scala:60:50] wire auto_client_out_a_ready_0 = auto_client_out_a_ready; // @[TLSerdes.scala:39:9] wire auto_client_out_d_valid_0 = auto_client_out_d_valid; // @[TLSerdes.scala:39:9] wire [2:0] auto_client_out_d_bits_opcode_0 = auto_client_out_d_bits_opcode; // @[TLSerdes.scala:39:9] wire [1:0] auto_client_out_d_bits_param_0 = auto_client_out_d_bits_param; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_d_bits_size_0 = auto_client_out_d_bits_size; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_d_bits_source_0 = auto_client_out_d_bits_source; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_d_bits_sink_0 = auto_client_out_d_bits_sink; // @[TLSerdes.scala:39:9] wire auto_client_out_d_bits_denied_0 = auto_client_out_d_bits_denied; // @[TLSerdes.scala:39:9] wire [63:0] auto_client_out_d_bits_data_0 = auto_client_out_d_bits_data; // @[TLSerdes.scala:39:9] wire auto_client_out_d_bits_corrupt_0 = auto_client_out_d_bits_corrupt; // @[TLSerdes.scala:39:9] wire io_ser_0_in_valid_0 = io_ser_0_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_0_in_bits_flit_0 = io_ser_0_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_1_in_valid_0 = io_ser_1_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_in_bits_flit_0 = io_ser_1_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_1_out_ready_0 = io_ser_1_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_2_in_valid_0 = io_ser_2_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_in_bits_flit_0 = io_ser_2_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_3_in_valid_0 = io_ser_3_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_in_bits_flit_0 = io_ser_3_in_bits_flit; // @[TLSerdes.scala:39:9] wire io_ser_3_out_ready_0 = io_ser_3_out_ready; // @[TLSerdes.scala:39:9] wire io_ser_4_in_valid_0 = io_ser_4_in_valid; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_in_bits_flit_0 = io_ser_4_in_bits_flit; // @[TLSerdes.scala:39:9] wire [1:0] _out_channels_WIRE_bits_param = 2'h0; // @[Bundles.scala:264:74] wire [1:0] out_channels_3_1_bits_param = 2'h0; // @[Bundles.scala:264:61] wire [7:0] manager_tl_a_bits_size = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_a_bits_source = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_a_bits_mask = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_c_bits_size = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_c_bits_source = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_e_bits_sink = 8'h0; // @[TLSerdes.scala:47:72] wire [7:0] _out_channels_WIRE_bits_mask = 8'h0; // @[Bundles.scala:264:74] wire [7:0] out_channels_3_1_bits_mask = 8'h0; // @[Bundles.scala:264:61] wire [2:0] manager_tl_a_bits_opcode = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_a_bits_param = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_c_bits_opcode = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_c_bits_param = 3'h0; // @[TLSerdes.scala:47:72] wire [2:0] _out_channels_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:264:74] wire [2:0] out_channels_3_1_bits_opcode = 3'h0; // @[Bundles.scala:264:61] wire [2:0] _in_channels_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _in_channels_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [3:0] _out_channels_WIRE_bits_size = 4'h0; // @[Bundles.scala:264:74] wire [3:0] _out_channels_WIRE_bits_source = 4'h0; // @[Bundles.scala:264:74] wire [3:0] out_channels_3_1_bits_size = 4'h0; // @[Bundles.scala:264:61] wire [3:0] out_channels_3_1_bits_source = 4'h0; // @[Bundles.scala:264:61] wire [3:0] _in_channels_WIRE_bits_sink = 4'h0; // @[Bundles.scala:267:74] wire [3:0] _in_channels_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _in_channels_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [63:0] manager_tl_a_bits_address = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_a_bits_data = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_c_bits_address = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_c_bits_data = 64'h0; // @[TLSerdes.scala:47:72] wire [63:0] _out_channels_WIRE_bits_data = 64'h0; // @[Bundles.scala:264:74] wire [63:0] out_channels_3_1_bits_data = 64'h0; // @[Bundles.scala:264:61] wire [63:0] _in_channels_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [31:0] io_ser_0_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_2_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_4_out_bits_flit = 32'h0; // @[TLSerdes.scala:39:9] wire [31:0] _out_channels_WIRE_bits_address = 32'h0; // @[Bundles.scala:264:74] wire [31:0] out_channels_3_1_bits_address = 32'h0; // @[Bundles.scala:264:61] wire [31:0] _in_channels_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:74] wire io_ser_0_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_2_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire io_ser_4_out_valid = 1'h0; // @[TLSerdes.scala:39:9] wire manager_tl_a_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_a_valid = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_a_bits_corrupt = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_b_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_c_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_c_valid = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_c_bits_corrupt = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_d_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_e_ready = 1'h0; // @[TLSerdes.scala:47:72] wire manager_tl_e_valid = 1'h0; // @[TLSerdes.scala:47:72] wire _out_channels_WIRE_ready = 1'h0; // @[Bundles.scala:264:74] wire _out_channels_WIRE_valid = 1'h0; // @[Bundles.scala:264:74] wire _out_channels_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:264:74] wire out_channels_3_1_valid = 1'h0; // @[Bundles.scala:264:61] wire out_channels_3_1_bits_corrupt = 1'h0; // @[Bundles.scala:264:61] wire _in_channels_WIRE_ready = 1'h0; // @[Bundles.scala:267:74] wire _in_channels_WIRE_valid = 1'h0; // @[Bundles.scala:267:74] wire in_channels_0_1_ready = 1'h0; // @[Bundles.scala:267:61] wire _in_channels_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:74] wire _in_channels_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:74] wire _in_channels_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire in_channels_2_1_ready = 1'h0; // @[Bundles.scala:265:61] wire io_ser_0_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire io_ser_2_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire io_ser_4_out_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire out_channels_3_1_ready = 1'h1; // @[TLSerdes.scala:39:9, :40:16, :62:50] wire clientNodeOut_a_ready = auto_client_out_a_ready_0; // @[TLSerdes.scala:39:9] wire clientNodeOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] clientNodeOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] clientNodeOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] clientNodeOut_a_bits_size; // @[MixedNode.scala:542:17] wire [3:0] clientNodeOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] clientNodeOut_a_bits_address; // @[MixedNode.scala:542:17] wire [7:0] clientNodeOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [63:0] clientNodeOut_a_bits_data; // @[MixedNode.scala:542:17] wire clientNodeOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire clientNodeOut_d_ready; // @[MixedNode.scala:542:17] wire clientNodeOut_d_valid = auto_client_out_d_valid_0; // @[TLSerdes.scala:39:9] wire [2:0] clientNodeOut_d_bits_opcode = auto_client_out_d_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [1:0] clientNodeOut_d_bits_param = auto_client_out_d_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] clientNodeOut_d_bits_size = auto_client_out_d_bits_size_0; // @[TLSerdes.scala:39:9] wire [3:0] clientNodeOut_d_bits_source = auto_client_out_d_bits_source_0; // @[TLSerdes.scala:39:9] wire [3:0] clientNodeOut_d_bits_sink = auto_client_out_d_bits_sink_0; // @[TLSerdes.scala:39:9] wire clientNodeOut_d_bits_denied = auto_client_out_d_bits_denied_0; // @[TLSerdes.scala:39:9] wire [63:0] clientNodeOut_d_bits_data = auto_client_out_d_bits_data_0; // @[TLSerdes.scala:39:9] wire clientNodeOut_d_bits_corrupt = auto_client_out_d_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire _io_debug_ser_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_3; // @[package.scala:81:59] wire [2:0] auto_client_out_a_bits_opcode_0; // @[TLSerdes.scala:39:9] wire [2:0] auto_client_out_a_bits_param_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_a_bits_size_0; // @[TLSerdes.scala:39:9] wire [3:0] auto_client_out_a_bits_source_0; // @[TLSerdes.scala:39:9] wire [31:0] auto_client_out_a_bits_address_0; // @[TLSerdes.scala:39:9] wire [7:0] auto_client_out_a_bits_mask_0; // @[TLSerdes.scala:39:9] wire [63:0] auto_client_out_a_bits_data_0; // @[TLSerdes.scala:39:9] wire auto_client_out_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] wire auto_client_out_a_valid_0; // @[TLSerdes.scala:39:9] wire auto_client_out_d_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_1_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_1_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] wire io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] wire [31:0] io_ser_3_out_bits_flit_0; // @[TLSerdes.scala:39:9] wire io_ser_3_out_valid_0; // @[TLSerdes.scala:39:9] wire io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] wire io_debug_ser_busy_0; // @[TLSerdes.scala:39:9] wire io_debug_des_busy_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_valid_0 = clientNodeOut_a_valid; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_opcode_0 = clientNodeOut_a_bits_opcode; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_param_0 = clientNodeOut_a_bits_param; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_size_0 = clientNodeOut_a_bits_size; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_source_0 = clientNodeOut_a_bits_source; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_address_0 = clientNodeOut_a_bits_address; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_mask_0 = clientNodeOut_a_bits_mask; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_data_0 = clientNodeOut_a_bits_data; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_corrupt_0 = clientNodeOut_a_bits_corrupt; // @[TLSerdes.scala:39:9] assign auto_client_out_d_ready_0 = clientNodeOut_d_ready; // @[TLSerdes.scala:39:9] wire [2:0] manager_tl_b_bits_opcode; // @[TLSerdes.scala:47:72] wire [1:0] manager_tl_b_bits_param; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_b_bits_size; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_b_bits_source; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_b_bits_address; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_b_bits_mask; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_b_bits_data; // @[TLSerdes.scala:47:72] wire manager_tl_b_bits_corrupt; // @[TLSerdes.scala:47:72] wire manager_tl_b_valid; // @[TLSerdes.scala:47:72] wire [2:0] manager_tl_d_bits_opcode; // @[TLSerdes.scala:47:72] wire [1:0] manager_tl_d_bits_param; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_d_bits_size; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_d_bits_source; // @[TLSerdes.scala:47:72] wire [7:0] manager_tl_d_bits_sink; // @[TLSerdes.scala:47:72] wire manager_tl_d_bits_denied; // @[TLSerdes.scala:47:72] wire [63:0] manager_tl_d_bits_data; // @[TLSerdes.scala:47:72] wire manager_tl_d_bits_corrupt; // @[TLSerdes.scala:47:72] wire manager_tl_d_valid; // @[TLSerdes.scala:47:72] assign _io_debug_ser_busy_T = _ser_1_io_busy | _ser_3_io_busy; // @[TLSerdes.scala:69:23] assign io_debug_ser_busy_0 = _io_debug_ser_busy_T; // @[TLSerdes.scala:39:9] wire [3:0] in_channels_0_1_bits_sink; // @[Bundles.scala:267:61] wire in_channels_0_1_valid; // @[Bundles.scala:267:61] wire [2:0] in_channels_2_1_bits_opcode; // @[Bundles.scala:265:61] wire [2:0] in_channels_2_1_bits_param; // @[Bundles.scala:265:61] wire [3:0] in_channels_2_1_bits_size; // @[Bundles.scala:265:61] wire [3:0] in_channels_2_1_bits_source; // @[Bundles.scala:265:61] wire [31:0] in_channels_2_1_bits_address; // @[Bundles.scala:265:61] wire [63:0] in_channels_2_1_bits_data; // @[Bundles.scala:265:61] wire in_channels_2_1_bits_corrupt; // @[Bundles.scala:265:61] wire in_channels_2_1_valid; // @[Bundles.scala:265:61] assign in_channels_0_1_bits_sink = _in_channels_0_2_io_protocol_bits_sink[3:0]; // @[TLSerdes.scala:78:28, :85:9] assign in_channels_2_1_bits_size = _in_channels_2_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:80:28, :85:9] assign in_channels_2_1_bits_source = _in_channels_2_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:80:28, :85:9] assign in_channels_2_1_bits_address = _in_channels_2_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:80:28, :85:9] assign clientNodeOut_a_bits_size = _in_channels_4_2_io_protocol_bits_size[3:0]; // @[TLSerdes.scala:82:28, :85:9] assign clientNodeOut_a_bits_source = _in_channels_4_2_io_protocol_bits_source[3:0]; // @[TLSerdes.scala:82:28, :85:9] assign clientNodeOut_a_bits_address = _in_channels_4_2_io_protocol_bits_address[31:0]; // @[TLSerdes.scala:82:28, :85:9] wire _io_debug_des_busy_T; // @[package.scala:81:59] wire _io_debug_des_busy_T_1 = _io_debug_des_busy_T | _des_2_io_busy; // @[TLSerdes.scala:86:23] wire _io_debug_des_busy_T_2 = _io_debug_des_busy_T_1 | _des_3_io_busy; // @[TLSerdes.scala:86:23] assign _io_debug_des_busy_T_3 = _io_debug_des_busy_T_2 | _des_4_io_busy; // @[TLSerdes.scala:86:23] assign io_debug_des_busy_0 = _io_debug_des_busy_T_3; // @[TLSerdes.scala:39:9] TLDToBeat_serial_tl_0_a64d64s8k8z8c out_channels_1_2 ( // @[TLSerdes.scala:60:50] .clock (clock), .reset (reset), .io_protocol_ready (clientNodeOut_d_ready), .io_protocol_valid (clientNodeOut_d_valid), // @[MixedNode.scala:542:17] .io_protocol_bits_opcode (clientNodeOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_protocol_bits_param (clientNodeOut_d_bits_param), // @[MixedNode.scala:542:17] .io_protocol_bits_size ({4'h0, clientNodeOut_d_bits_size}), // @[TLSerdes.scala:68:21] .io_protocol_bits_source ({4'h0, clientNodeOut_d_bits_source}), // @[TLSerdes.scala:68:21] .io_protocol_bits_sink ({4'h0, clientNodeOut_d_bits_sink}), // @[TLSerdes.scala:68:21] .io_protocol_bits_denied (clientNodeOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_protocol_bits_data (clientNodeOut_d_bits_data), // @[MixedNode.scala:542:17] .io_protocol_bits_corrupt (clientNodeOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_beat_ready (_ser_1_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_valid (_out_channels_1_2_io_beat_valid), .io_beat_bits_payload (_out_channels_1_2_io_beat_bits_payload), .io_beat_bits_head (_out_channels_1_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_1_2_io_beat_bits_tail) ); // @[TLSerdes.scala:60:50] TLBToBeat_serial_tl_0_a64d64s8k8z8c out_channels_3_2 ( // @[TLSerdes.scala:62:50] .clock (clock), .reset (reset), .io_beat_ready (_ser_3_io_in_ready), // @[TLSerdes.scala:69:23] .io_beat_bits_head (_out_channels_3_2_io_beat_bits_head), .io_beat_bits_tail (_out_channels_3_2_io_beat_bits_tail) ); // @[TLSerdes.scala:62:50] GenericSerializer_TLBeatw67_f32 ser_1 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_1_io_in_ready), .io_in_valid (_out_channels_1_2_io_beat_valid), // @[TLSerdes.scala:60:50] .io_in_bits_payload (_out_channels_1_2_io_beat_bits_payload), // @[TLSerdes.scala:60:50] .io_in_bits_head (_out_channels_1_2_io_beat_bits_head), // @[TLSerdes.scala:60:50] .io_in_bits_tail (_out_channels_1_2_io_beat_bits_tail), // @[TLSerdes.scala:60:50] .io_out_ready (io_ser_1_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_1_out_valid_0), .io_out_bits_flit (io_ser_1_out_bits_flit_0), .io_busy (_ser_1_io_busy) ); // @[TLSerdes.scala:69:23] GenericSerializer_TLBeatw87_f32 ser_3 ( // @[TLSerdes.scala:69:23] .clock (clock), .reset (reset), .io_in_ready (_ser_3_io_in_ready), .io_in_bits_head (_out_channels_3_2_io_beat_bits_head), // @[TLSerdes.scala:62:50] .io_in_bits_tail (_out_channels_3_2_io_beat_bits_tail), // @[TLSerdes.scala:62:50] .io_out_ready (io_ser_3_out_ready_0), // @[TLSerdes.scala:39:9] .io_out_valid (io_ser_3_out_valid_0), .io_out_bits_flit (io_ser_3_out_bits_flit_0), .io_busy (_ser_3_io_busy) ); // @[TLSerdes.scala:69:23] TLEFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_0_2 ( // @[TLSerdes.scala:78:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_0_1_valid), .io_protocol_bits_sink (_in_channels_0_2_io_protocol_bits_sink), .io_beat_ready (_in_channels_0_2_io_beat_ready), .io_beat_valid (_des_0_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_0_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_0_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_0_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:78:28] TLDFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_1_2 ( // @[TLSerdes.scala:79:28] .clock (clock), .reset (reset), .io_protocol_valid (manager_tl_d_valid), .io_protocol_bits_opcode (manager_tl_d_bits_opcode), .io_protocol_bits_param (manager_tl_d_bits_param), .io_protocol_bits_size (manager_tl_d_bits_size), .io_protocol_bits_source (manager_tl_d_bits_source), .io_protocol_bits_sink (manager_tl_d_bits_sink), .io_protocol_bits_denied (manager_tl_d_bits_denied), .io_protocol_bits_data (manager_tl_d_bits_data), .io_protocol_bits_corrupt (manager_tl_d_bits_corrupt), .io_beat_ready (_in_channels_1_2_io_beat_ready), .io_beat_valid (_des_1_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_1_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_1_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_1_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:79:28] TLCFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_2_2 ( // @[TLSerdes.scala:80:28] .clock (clock), .reset (reset), .io_protocol_valid (in_channels_2_1_valid), .io_protocol_bits_opcode (in_channels_2_1_bits_opcode), .io_protocol_bits_param (in_channels_2_1_bits_param), .io_protocol_bits_size (_in_channels_2_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_2_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_2_2_io_protocol_bits_address), .io_protocol_bits_data (in_channels_2_1_bits_data), .io_protocol_bits_corrupt (in_channels_2_1_bits_corrupt), .io_beat_ready (_in_channels_2_2_io_beat_ready), .io_beat_valid (_des_2_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_2_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_2_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_2_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:80:28] TLBFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_3_2 ( // @[TLSerdes.scala:81:28] .clock (clock), .reset (reset), .io_protocol_valid (manager_tl_b_valid), .io_protocol_bits_opcode (manager_tl_b_bits_opcode), .io_protocol_bits_param (manager_tl_b_bits_param), .io_protocol_bits_size (manager_tl_b_bits_size), .io_protocol_bits_source (manager_tl_b_bits_source), .io_protocol_bits_address (manager_tl_b_bits_address), .io_protocol_bits_mask (manager_tl_b_bits_mask), .io_protocol_bits_data (manager_tl_b_bits_data), .io_protocol_bits_corrupt (manager_tl_b_bits_corrupt), .io_beat_ready (_in_channels_3_2_io_beat_ready), .io_beat_valid (_des_3_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_3_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_3_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_3_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:81:28] TLAFromBeat_serial_tl_0_a64d64s8k8z8c in_channels_4_2 ( // @[TLSerdes.scala:82:28] .clock (clock), .reset (reset), .io_protocol_ready (clientNodeOut_a_ready), // @[MixedNode.scala:542:17] .io_protocol_valid (clientNodeOut_a_valid), .io_protocol_bits_opcode (clientNodeOut_a_bits_opcode), .io_protocol_bits_param (clientNodeOut_a_bits_param), .io_protocol_bits_size (_in_channels_4_2_io_protocol_bits_size), .io_protocol_bits_source (_in_channels_4_2_io_protocol_bits_source), .io_protocol_bits_address (_in_channels_4_2_io_protocol_bits_address), .io_protocol_bits_mask (clientNodeOut_a_bits_mask), .io_protocol_bits_data (clientNodeOut_a_bits_data), .io_protocol_bits_corrupt (clientNodeOut_a_bits_corrupt), .io_beat_ready (_in_channels_4_2_io_beat_ready), .io_beat_valid (_des_4_io_out_valid), // @[TLSerdes.scala:86:23] .io_beat_bits_payload (_des_4_io_out_bits_payload), // @[TLSerdes.scala:86:23] .io_beat_bits_head (_des_4_io_out_bits_head), // @[TLSerdes.scala:86:23] .io_beat_bits_tail (_des_4_io_out_bits_tail) // @[TLSerdes.scala:86:23] ); // @[TLSerdes.scala:82:28] GenericDeserializer_TLBeatw10_f32 des_0 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_0_in_ready_0), .io_in_valid (io_ser_0_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_0_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_0_2_io_beat_ready), // @[TLSerdes.scala:78:28] .io_out_valid (_des_0_io_out_valid), .io_out_bits_payload (_des_0_io_out_bits_payload), .io_out_bits_head (_des_0_io_out_bits_head), .io_out_bits_tail (_des_0_io_out_bits_tail) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw67_f32 des_1 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_1_in_ready_0), .io_in_valid (io_ser_1_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_1_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_1_2_io_beat_ready), // @[TLSerdes.scala:79:28] .io_out_valid (_des_1_io_out_valid), .io_out_bits_payload (_des_1_io_out_bits_payload), .io_out_bits_head (_des_1_io_out_bits_head), .io_out_bits_tail (_des_1_io_out_bits_tail), .io_busy (_io_debug_des_busy_T) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32 des_2 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_2_in_ready_0), .io_in_valid (io_ser_2_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_2_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_2_2_io_beat_ready), // @[TLSerdes.scala:80:28] .io_out_valid (_des_2_io_out_valid), .io_out_bits_payload (_des_2_io_out_bits_payload), .io_out_bits_head (_des_2_io_out_bits_head), .io_out_bits_tail (_des_2_io_out_bits_tail), .io_busy (_des_2_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw87_f32 des_3 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_3_in_ready_0), .io_in_valid (io_ser_3_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_3_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_3_2_io_beat_ready), // @[TLSerdes.scala:81:28] .io_out_valid (_des_3_io_out_valid), .io_out_bits_payload (_des_3_io_out_bits_payload), .io_out_bits_head (_des_3_io_out_bits_head), .io_out_bits_tail (_des_3_io_out_bits_tail), .io_busy (_des_3_io_busy) ); // @[TLSerdes.scala:86:23] GenericDeserializer_TLBeatw88_f32_1 des_4 ( // @[TLSerdes.scala:86:23] .clock (clock), .reset (reset), .io_in_ready (io_ser_4_in_ready_0), .io_in_valid (io_ser_4_in_valid_0), // @[TLSerdes.scala:39:9] .io_in_bits_flit (io_ser_4_in_bits_flit_0), // @[TLSerdes.scala:39:9] .io_out_ready (_in_channels_4_2_io_beat_ready), // @[TLSerdes.scala:82:28] .io_out_valid (_des_4_io_out_valid), .io_out_bits_payload (_des_4_io_out_bits_payload), .io_out_bits_head (_des_4_io_out_bits_head), .io_out_bits_tail (_des_4_io_out_bits_tail), .io_busy (_des_4_io_busy) ); // @[TLSerdes.scala:86:23] assign auto_client_out_a_valid = auto_client_out_a_valid_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_opcode = auto_client_out_a_bits_opcode_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_param = auto_client_out_a_bits_param_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_size = auto_client_out_a_bits_size_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_source = auto_client_out_a_bits_source_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_address = auto_client_out_a_bits_address_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_mask = auto_client_out_a_bits_mask_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_data = auto_client_out_a_bits_data_0; // @[TLSerdes.scala:39:9] assign auto_client_out_a_bits_corrupt = auto_client_out_a_bits_corrupt_0; // @[TLSerdes.scala:39:9] assign auto_client_out_d_ready = auto_client_out_d_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_0_in_ready = io_ser_0_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_1_in_ready = io_ser_1_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_1_out_valid = io_ser_1_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_1_out_bits_flit = io_ser_1_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_2_in_ready = io_ser_2_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_3_in_ready = io_ser_3_in_ready_0; // @[TLSerdes.scala:39:9] assign io_ser_3_out_valid = io_ser_3_out_valid_0; // @[TLSerdes.scala:39:9] assign io_ser_3_out_bits_flit = io_ser_3_out_bits_flit_0; // @[TLSerdes.scala:39:9] assign io_ser_4_in_ready = io_ser_4_in_ready_0; // @[TLSerdes.scala:39:9] assign io_debug_ser_busy = io_debug_ser_busy_0; // @[TLSerdes.scala:39:9] assign io_debug_des_busy = io_debug_des_busy_0; // @[TLSerdes.scala:39:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLWidthWidget8 : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_6 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in node _hasData_opdata_T = bits(anonIn.a.bits.opcode, 2, 2) node hasData = eq(_hasData_opdata_T, UInt<1>(0h0)) node _limit_T = dshl(UInt<4>(0hf), anonIn.a.bits.size) node _limit_T_1 = bits(_limit_T, 3, 0) node _limit_T_2 = not(_limit_T_1) node limit = shr(_limit_T_2, 3) regreset count : UInt<1>, clock, reset, UInt<1>(0h0) node first = eq(count, UInt<1>(0h0)) node _last_T = eq(count, limit) node _last_T_1 = eq(hasData, UInt<1>(0h0)) node last = or(_last_T, _last_T_1) node _enable_T = xor(count, UInt<1>(0h0)) node _enable_T_1 = and(_enable_T, limit) node _enable_T_2 = orr(_enable_T_1) node enable_0 = eq(_enable_T_2, UInt<1>(0h0)) node _enable_T_3 = xor(count, UInt<1>(0h1)) node _enable_T_4 = and(_enable_T_3, limit) node _enable_T_5 = orr(_enable_T_4) node enable_1 = eq(_enable_T_5, UInt<1>(0h0)) regreset corrupt_reg : UInt<1>, clock, reset, UInt<1>(0h0) node corrupt_out = or(anonIn.a.bits.corrupt, corrupt_reg) node _T = and(anonIn.a.ready, anonIn.a.valid) when _T : node _count_T = add(count, UInt<1>(0h1)) node _count_T_1 = tail(_count_T, 1) connect count, _count_T_1 connect corrupt_reg, corrupt_out when last : connect count, UInt<1>(0h0) connect corrupt_reg, UInt<1>(0h0) node _anonIn_a_ready_T = eq(last, UInt<1>(0h0)) node _anonIn_a_ready_T_1 = or(anonOut.a.ready, _anonIn_a_ready_T) connect anonIn.a.ready, _anonIn_a_ready_T_1 node _anonOut_a_valid_T = and(anonIn.a.valid, last) connect anonOut.a.valid, _anonOut_a_valid_T connect anonOut.a.bits, anonIn.a.bits regreset anonOut_a_bits_data_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonOut_a_bits_data_masked_enable_T = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_0 = or(enable_0, _anonOut_a_bits_data_masked_enable_T) node _anonOut_a_bits_data_masked_enable_T_1 = eq(anonOut_a_bits_data_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_data_masked_enable_1 = or(enable_1, _anonOut_a_bits_data_masked_enable_T_1) wire anonOut_a_bits_data_odata_0 : UInt connect anonOut_a_bits_data_odata_0, anonIn.a.bits.data wire anonOut_a_bits_data_odata_1 : UInt connect anonOut_a_bits_data_odata_1, anonIn.a.bits.data reg anonOut_a_bits_data_rdata : UInt<64>[1], clock node anonOut_a_bits_data_mdata_0 = mux(anonOut_a_bits_data_masked_enable_0, anonOut_a_bits_data_odata_0, anonOut_a_bits_data_rdata[0]) node anonOut_a_bits_data_mdata_1 = mux(anonOut_a_bits_data_masked_enable_1, anonOut_a_bits_data_odata_1, anonIn.a.bits.data) node _anonOut_a_bits_data_T = and(anonIn.a.ready, anonIn.a.valid) node _anonOut_a_bits_data_T_1 = eq(last, UInt<1>(0h0)) node _anonOut_a_bits_data_T_2 = and(_anonOut_a_bits_data_T, _anonOut_a_bits_data_T_1) when _anonOut_a_bits_data_T_2 : connect anonOut_a_bits_data_rdata_written_once, UInt<1>(0h1) connect anonOut_a_bits_data_rdata[0], anonOut_a_bits_data_mdata_0 node _anonOut_a_bits_data_T_3 = cat(anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0) connect anonOut.a.bits.data, _anonOut_a_bits_data_T_3 connect anonOut.a.bits.corrupt, corrupt_out node _anonOut_a_bits_mask_sizeOH_T = or(anonOut.a.bits.size, UInt<4>(0h0)) node anonOut_a_bits_mask_sizeOH_shiftAmount = bits(_anonOut_a_bits_mask_sizeOH_T, 1, 0) node _anonOut_a_bits_mask_sizeOH_T_1 = dshl(UInt<1>(0h1), anonOut_a_bits_mask_sizeOH_shiftAmount) node _anonOut_a_bits_mask_sizeOH_T_2 = bits(_anonOut_a_bits_mask_sizeOH_T_1, 3, 0) node anonOut_a_bits_mask_sizeOH = or(_anonOut_a_bits_mask_sizeOH_T_2, UInt<1>(0h1)) node anonOut_a_bits_mask_sub_sub_sub_sub_0_1 = geq(anonOut.a.bits.size, UInt<3>(0h4)) node anonOut_a_bits_mask_sub_sub_sub_size = bits(anonOut_a_bits_mask_sizeOH, 3, 3) node anonOut_a_bits_mask_sub_sub_sub_bit = bits(anonOut.a.bits.address, 3, 3) node anonOut_a_bits_mask_sub_sub_sub_nbit = eq(anonOut_a_bits_mask_sub_sub_sub_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_sub_nbit) node _anonOut_a_bits_mask_sub_sub_sub_acc_T = and(anonOut_a_bits_mask_sub_sub_sub_size, anonOut_a_bits_mask_sub_sub_sub_0_2) node anonOut_a_bits_mask_sub_sub_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_sub_acc_T) node anonOut_a_bits_mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), anonOut_a_bits_mask_sub_sub_sub_bit) node _anonOut_a_bits_mask_sub_sub_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_sub_sub_size, anonOut_a_bits_mask_sub_sub_sub_1_2) node anonOut_a_bits_mask_sub_sub_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_sub_acc_T_1) node anonOut_a_bits_mask_sub_sub_size = bits(anonOut_a_bits_mask_sizeOH, 2, 2) node anonOut_a_bits_mask_sub_sub_bit = bits(anonOut.a.bits.address, 2, 2) node anonOut_a_bits_mask_sub_sub_nbit = eq(anonOut_a_bits_mask_sub_sub_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_sub_sub_0_2 = and(anonOut_a_bits_mask_sub_sub_sub_0_2, anonOut_a_bits_mask_sub_sub_nbit) node _anonOut_a_bits_mask_sub_sub_acc_T = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_0_2) node anonOut_a_bits_mask_sub_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T) node anonOut_a_bits_mask_sub_sub_1_2 = and(anonOut_a_bits_mask_sub_sub_sub_0_2, anonOut_a_bits_mask_sub_sub_bit) node _anonOut_a_bits_mask_sub_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_1_2) node anonOut_a_bits_mask_sub_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_sub_0_1, _anonOut_a_bits_mask_sub_sub_acc_T_1) node anonOut_a_bits_mask_sub_sub_2_2 = and(anonOut_a_bits_mask_sub_sub_sub_1_2, anonOut_a_bits_mask_sub_sub_nbit) node _anonOut_a_bits_mask_sub_sub_acc_T_2 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_2_2) node anonOut_a_bits_mask_sub_sub_2_1 = or(anonOut_a_bits_mask_sub_sub_sub_1_1, _anonOut_a_bits_mask_sub_sub_acc_T_2) node anonOut_a_bits_mask_sub_sub_3_2 = and(anonOut_a_bits_mask_sub_sub_sub_1_2, anonOut_a_bits_mask_sub_sub_bit) node _anonOut_a_bits_mask_sub_sub_acc_T_3 = and(anonOut_a_bits_mask_sub_sub_size, anonOut_a_bits_mask_sub_sub_3_2) node anonOut_a_bits_mask_sub_sub_3_1 = or(anonOut_a_bits_mask_sub_sub_sub_1_1, _anonOut_a_bits_mask_sub_sub_acc_T_3) node anonOut_a_bits_mask_sub_size = bits(anonOut_a_bits_mask_sizeOH, 1, 1) node anonOut_a_bits_mask_sub_bit = bits(anonOut.a.bits.address, 1, 1) node anonOut_a_bits_mask_sub_nbit = eq(anonOut_a_bits_mask_sub_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_sub_0_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_nbit) node _anonOut_a_bits_mask_sub_acc_T = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_0_2) node anonOut_a_bits_mask_sub_0_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T) node anonOut_a_bits_mask_sub_1_2 = and(anonOut_a_bits_mask_sub_sub_0_2, anonOut_a_bits_mask_sub_bit) node _anonOut_a_bits_mask_sub_acc_T_1 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_1_2) node anonOut_a_bits_mask_sub_1_1 = or(anonOut_a_bits_mask_sub_sub_0_1, _anonOut_a_bits_mask_sub_acc_T_1) node anonOut_a_bits_mask_sub_2_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_nbit) node _anonOut_a_bits_mask_sub_acc_T_2 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_2_2) node anonOut_a_bits_mask_sub_2_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_2) node anonOut_a_bits_mask_sub_3_2 = and(anonOut_a_bits_mask_sub_sub_1_2, anonOut_a_bits_mask_sub_bit) node _anonOut_a_bits_mask_sub_acc_T_3 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_3_2) node anonOut_a_bits_mask_sub_3_1 = or(anonOut_a_bits_mask_sub_sub_1_1, _anonOut_a_bits_mask_sub_acc_T_3) node anonOut_a_bits_mask_sub_4_2 = and(anonOut_a_bits_mask_sub_sub_2_2, anonOut_a_bits_mask_sub_nbit) node _anonOut_a_bits_mask_sub_acc_T_4 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_4_2) node anonOut_a_bits_mask_sub_4_1 = or(anonOut_a_bits_mask_sub_sub_2_1, _anonOut_a_bits_mask_sub_acc_T_4) node anonOut_a_bits_mask_sub_5_2 = and(anonOut_a_bits_mask_sub_sub_2_2, anonOut_a_bits_mask_sub_bit) node _anonOut_a_bits_mask_sub_acc_T_5 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_5_2) node anonOut_a_bits_mask_sub_5_1 = or(anonOut_a_bits_mask_sub_sub_2_1, _anonOut_a_bits_mask_sub_acc_T_5) node anonOut_a_bits_mask_sub_6_2 = and(anonOut_a_bits_mask_sub_sub_3_2, anonOut_a_bits_mask_sub_nbit) node _anonOut_a_bits_mask_sub_acc_T_6 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_6_2) node anonOut_a_bits_mask_sub_6_1 = or(anonOut_a_bits_mask_sub_sub_3_1, _anonOut_a_bits_mask_sub_acc_T_6) node anonOut_a_bits_mask_sub_7_2 = and(anonOut_a_bits_mask_sub_sub_3_2, anonOut_a_bits_mask_sub_bit) node _anonOut_a_bits_mask_sub_acc_T_7 = and(anonOut_a_bits_mask_sub_size, anonOut_a_bits_mask_sub_7_2) node anonOut_a_bits_mask_sub_7_1 = or(anonOut_a_bits_mask_sub_sub_3_1, _anonOut_a_bits_mask_sub_acc_T_7) node anonOut_a_bits_mask_size = bits(anonOut_a_bits_mask_sizeOH, 0, 0) node anonOut_a_bits_mask_bit = bits(anonOut.a.bits.address, 0, 0) node anonOut_a_bits_mask_nbit = eq(anonOut_a_bits_mask_bit, UInt<1>(0h0)) node anonOut_a_bits_mask_eq = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq) node anonOut_a_bits_mask_acc = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T) node anonOut_a_bits_mask_eq_1 = and(anonOut_a_bits_mask_sub_0_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_1 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_1) node anonOut_a_bits_mask_acc_1 = or(anonOut_a_bits_mask_sub_0_1, _anonOut_a_bits_mask_acc_T_1) node anonOut_a_bits_mask_eq_2 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_2 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_2) node anonOut_a_bits_mask_acc_2 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_2) node anonOut_a_bits_mask_eq_3 = and(anonOut_a_bits_mask_sub_1_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_3 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_3) node anonOut_a_bits_mask_acc_3 = or(anonOut_a_bits_mask_sub_1_1, _anonOut_a_bits_mask_acc_T_3) node anonOut_a_bits_mask_eq_4 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_4 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_4) node anonOut_a_bits_mask_acc_4 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_4) node anonOut_a_bits_mask_eq_5 = and(anonOut_a_bits_mask_sub_2_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_5 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_5) node anonOut_a_bits_mask_acc_5 = or(anonOut_a_bits_mask_sub_2_1, _anonOut_a_bits_mask_acc_T_5) node anonOut_a_bits_mask_eq_6 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_6 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_6) node anonOut_a_bits_mask_acc_6 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_6) node anonOut_a_bits_mask_eq_7 = and(anonOut_a_bits_mask_sub_3_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_7 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_7) node anonOut_a_bits_mask_acc_7 = or(anonOut_a_bits_mask_sub_3_1, _anonOut_a_bits_mask_acc_T_7) node anonOut_a_bits_mask_eq_8 = and(anonOut_a_bits_mask_sub_4_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_8 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_8) node anonOut_a_bits_mask_acc_8 = or(anonOut_a_bits_mask_sub_4_1, _anonOut_a_bits_mask_acc_T_8) node anonOut_a_bits_mask_eq_9 = and(anonOut_a_bits_mask_sub_4_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_9 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_9) node anonOut_a_bits_mask_acc_9 = or(anonOut_a_bits_mask_sub_4_1, _anonOut_a_bits_mask_acc_T_9) node anonOut_a_bits_mask_eq_10 = and(anonOut_a_bits_mask_sub_5_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_10 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_10) node anonOut_a_bits_mask_acc_10 = or(anonOut_a_bits_mask_sub_5_1, _anonOut_a_bits_mask_acc_T_10) node anonOut_a_bits_mask_eq_11 = and(anonOut_a_bits_mask_sub_5_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_11 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_11) node anonOut_a_bits_mask_acc_11 = or(anonOut_a_bits_mask_sub_5_1, _anonOut_a_bits_mask_acc_T_11) node anonOut_a_bits_mask_eq_12 = and(anonOut_a_bits_mask_sub_6_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_12 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_12) node anonOut_a_bits_mask_acc_12 = or(anonOut_a_bits_mask_sub_6_1, _anonOut_a_bits_mask_acc_T_12) node anonOut_a_bits_mask_eq_13 = and(anonOut_a_bits_mask_sub_6_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_13 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_13) node anonOut_a_bits_mask_acc_13 = or(anonOut_a_bits_mask_sub_6_1, _anonOut_a_bits_mask_acc_T_13) node anonOut_a_bits_mask_eq_14 = and(anonOut_a_bits_mask_sub_7_2, anonOut_a_bits_mask_nbit) node _anonOut_a_bits_mask_acc_T_14 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_14) node anonOut_a_bits_mask_acc_14 = or(anonOut_a_bits_mask_sub_7_1, _anonOut_a_bits_mask_acc_T_14) node anonOut_a_bits_mask_eq_15 = and(anonOut_a_bits_mask_sub_7_2, anonOut_a_bits_mask_bit) node _anonOut_a_bits_mask_acc_T_15 = and(anonOut_a_bits_mask_size, anonOut_a_bits_mask_eq_15) node anonOut_a_bits_mask_acc_15 = or(anonOut_a_bits_mask_sub_7_1, _anonOut_a_bits_mask_acc_T_15) node anonOut_a_bits_mask_lo_lo_lo = cat(anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc) node anonOut_a_bits_mask_lo_lo_hi = cat(anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2) node anonOut_a_bits_mask_lo_lo = cat(anonOut_a_bits_mask_lo_lo_hi, anonOut_a_bits_mask_lo_lo_lo) node anonOut_a_bits_mask_lo_hi_lo = cat(anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4) node anonOut_a_bits_mask_lo_hi_hi = cat(anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6) node anonOut_a_bits_mask_lo_hi = cat(anonOut_a_bits_mask_lo_hi_hi, anonOut_a_bits_mask_lo_hi_lo) node anonOut_a_bits_mask_lo = cat(anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo) node anonOut_a_bits_mask_hi_lo_lo = cat(anonOut_a_bits_mask_acc_9, anonOut_a_bits_mask_acc_8) node anonOut_a_bits_mask_hi_lo_hi = cat(anonOut_a_bits_mask_acc_11, anonOut_a_bits_mask_acc_10) node anonOut_a_bits_mask_hi_lo = cat(anonOut_a_bits_mask_hi_lo_hi, anonOut_a_bits_mask_hi_lo_lo) node anonOut_a_bits_mask_hi_hi_lo = cat(anonOut_a_bits_mask_acc_13, anonOut_a_bits_mask_acc_12) node anonOut_a_bits_mask_hi_hi_hi = cat(anonOut_a_bits_mask_acc_15, anonOut_a_bits_mask_acc_14) node anonOut_a_bits_mask_hi_hi = cat(anonOut_a_bits_mask_hi_hi_hi, anonOut_a_bits_mask_hi_hi_lo) node anonOut_a_bits_mask_hi = cat(anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo) node _anonOut_a_bits_mask_T = cat(anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo) regreset anonOut_a_bits_mask_rdata_written_once : UInt<1>, clock, reset, UInt<1>(0h0) node _anonOut_a_bits_mask_masked_enable_T = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_0 = or(enable_0, _anonOut_a_bits_mask_masked_enable_T) node _anonOut_a_bits_mask_masked_enable_T_1 = eq(anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h0)) node anonOut_a_bits_mask_masked_enable_1 = or(enable_1, _anonOut_a_bits_mask_masked_enable_T_1) wire anonOut_a_bits_mask_odata_0 : UInt connect anonOut_a_bits_mask_odata_0, anonIn.a.bits.mask wire anonOut_a_bits_mask_odata_1 : UInt connect anonOut_a_bits_mask_odata_1, anonIn.a.bits.mask reg anonOut_a_bits_mask_rdata : UInt<8>[1], clock node anonOut_a_bits_mask_mdata_0 = mux(anonOut_a_bits_mask_masked_enable_0, anonOut_a_bits_mask_odata_0, anonOut_a_bits_mask_rdata[0]) node anonOut_a_bits_mask_mdata_1 = mux(anonOut_a_bits_mask_masked_enable_1, anonOut_a_bits_mask_odata_1, anonIn.a.bits.mask) node _anonOut_a_bits_mask_T_1 = and(anonIn.a.ready, anonIn.a.valid) node _anonOut_a_bits_mask_T_2 = eq(last, UInt<1>(0h0)) node _anonOut_a_bits_mask_T_3 = and(_anonOut_a_bits_mask_T_1, _anonOut_a_bits_mask_T_2) when _anonOut_a_bits_mask_T_3 : connect anonOut_a_bits_mask_rdata_written_once, UInt<1>(0h1) connect anonOut_a_bits_mask_rdata[0], anonOut_a_bits_mask_mdata_0 node _anonOut_a_bits_mask_T_4 = cat(anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0) node _anonOut_a_bits_mask_T_5 = not(UInt<16>(0h0)) node _anonOut_a_bits_mask_T_6 = mux(hasData, _anonOut_a_bits_mask_T_4, _anonOut_a_bits_mask_T_5) node _anonOut_a_bits_mask_T_7 = and(_anonOut_a_bits_mask_T, _anonOut_a_bits_mask_T_6) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T_7 wire repeat : UInt<1> inst repeated_repeater of Repeater_TLBundleD_a32d128s5k4z4u connect repeated_repeater.clock, clock connect repeated_repeater.reset, reset connect repeated_repeater.io.repeat, repeat connect repeated_repeater.io.enq, anonOut.d wire cated : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect cated.bits, repeated_repeater.io.deq.bits connect cated.valid, repeated_repeater.io.deq.valid connect repeated_repeater.io.deq.ready, cated.ready node _cated_bits_data_T = bits(repeated_repeater.io.deq.bits.data, 127, 64) node _cated_bits_data_T_1 = bits(anonOut.d.bits.data, 63, 0) node _cated_bits_data_T_2 = cat(_cated_bits_data_T, _cated_bits_data_T_1) connect cated.bits.data, _cated_bits_data_T_2 node repeat_hasData = bits(cated.bits.opcode, 0, 0) node _repeat_limit_T = dshl(UInt<4>(0hf), cated.bits.size) node _repeat_limit_T_1 = bits(_repeat_limit_T, 3, 0) node _repeat_limit_T_2 = not(_repeat_limit_T_1) node repeat_limit = shr(_repeat_limit_T_2, 3) regreset repeat_count : UInt<1>, clock, reset, UInt<1>(0h0) node repeat_first = eq(repeat_count, UInt<1>(0h0)) node _repeat_last_T = eq(repeat_count, repeat_limit) node _repeat_last_T_1 = eq(repeat_hasData, UInt<1>(0h0)) node repeat_last = or(_repeat_last_T, _repeat_last_T_1) node _repeat_T = and(anonIn.d.ready, anonIn.d.valid) when _repeat_T : node _repeat_count_T = add(repeat_count, UInt<1>(0h1)) node _repeat_count_T_1 = tail(_repeat_count_T, 1) connect repeat_count, _repeat_count_T_1 when repeat_last : connect repeat_count, UInt<1>(0h0) reg repeat_sel_sel_sources : UInt<1>[17], clock node repeat_sel_sel_a_sel = bits(anonIn.a.bits.address, 3, 3) node _repeat_sel_sel_T = and(anonIn.a.ready, anonIn.a.valid) when _repeat_sel_sel_T : connect repeat_sel_sel_sources[anonIn.a.bits.source], repeat_sel_sel_a_sel node _repeat_sel_sel_bypass_T = eq(anonIn.a.bits.source, cated.bits.source) node repeat_sel_sel_bypass = and(anonIn.a.valid, _repeat_sel_sel_bypass_T) reg repeat_sel_hold_r : UInt<1>, clock when repeat_first : connect repeat_sel_hold_r, repeat_sel_sel_sources[cated.bits.source] node repeat_sel_hold = mux(repeat_first, repeat_sel_sel_sources[cated.bits.source], repeat_sel_hold_r) node _repeat_sel_T = not(repeat_limit) node repeat_sel = and(repeat_sel_hold, _repeat_sel_T) node repeat_index = or(repeat_sel, repeat_count) connect anonIn.d.bits.corrupt, cated.bits.corrupt connect anonIn.d.bits.data, cated.bits.data connect anonIn.d.bits.denied, cated.bits.denied connect anonIn.d.bits.sink, cated.bits.sink connect anonIn.d.bits.source, cated.bits.source connect anonIn.d.bits.size, cated.bits.size connect anonIn.d.bits.param, cated.bits.param connect anonIn.d.bits.opcode, cated.bits.opcode connect anonIn.d.valid, cated.valid connect cated.ready, anonIn.d.ready node _repeat_anonIn_d_bits_data_mux_T = bits(cated.bits.data, 63, 0) node _repeat_anonIn_d_bits_data_mux_T_1 = bits(cated.bits.data, 127, 64) wire repeat_anonIn_d_bits_data_mux : UInt<64>[2] connect repeat_anonIn_d_bits_data_mux[0], _repeat_anonIn_d_bits_data_mux_T connect repeat_anonIn_d_bits_data_mux[1], _repeat_anonIn_d_bits_data_mux_T_1 connect anonIn.d.bits.data, repeat_anonIn_d_bits_data_mux[repeat_index] node _repeat_T_1 = eq(repeat_last, UInt<1>(0h0)) connect repeat, _repeat_T_1 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.mask, UInt<16>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_10.bits.sink, UInt<4>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLWidthWidget8( // @[WidthWidget.scala:27:9] input clock, // @[WidthWidget.scala:27:9] input reset, // @[WidthWidget.scala:27:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [4:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [15:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [127:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [4:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [3:0] auto_anon_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [127:0] auto_anon_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire [127:0] _repeated_repeater_io_deq_bits_data; // @[Repeater.scala:36:26] wire auto_anon_in_a_valid_0 = auto_anon_in_a_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_opcode_0 = auto_anon_in_a_bits_opcode; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_a_bits_param_0 = auto_anon_in_a_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_a_bits_size_0 = auto_anon_in_a_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_in_a_bits_source_0 = auto_anon_in_a_bits_source; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_in_a_bits_address_0 = auto_anon_in_a_bits_address; // @[WidthWidget.scala:27:9] wire [7:0] auto_anon_in_a_bits_mask_0 = auto_anon_in_a_bits_mask; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_in_a_bits_data_0 = auto_anon_in_a_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_bits_corrupt_0 = auto_anon_in_a_bits_corrupt; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_ready_0 = auto_anon_in_d_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_ready_0 = auto_anon_out_a_ready; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_valid_0 = auto_anon_out_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_d_bits_opcode_0 = auto_anon_out_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_out_d_bits_param_0 = auto_anon_out_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_size_0 = auto_anon_out_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_out_d_bits_source_0 = auto_anon_out_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_d_bits_sink_0 = auto_anon_out_d_bits_sink; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_denied_0 = auto_anon_out_d_bits_denied; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_out_d_bits_data_0 = auto_anon_out_d_bits_data; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_bits_corrupt_0 = auto_anon_out_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire anonIn_a_ready; // @[MixedNode.scala:551:17] wire [15:0] _anonOut_a_bits_mask_T_5 = 16'hFFFF; // @[WidthWidget.scala:85:119] wire anonIn_a_valid = auto_anon_in_a_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_opcode = auto_anon_in_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] anonIn_a_bits_param = auto_anon_in_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonIn_a_bits_size = auto_anon_in_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] anonIn_a_bits_source = auto_anon_in_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] anonIn_a_bits_address = auto_anon_in_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [7:0] anonIn_a_bits_mask = auto_anon_in_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [63:0] anonIn_a_bits_data = auto_anon_in_a_bits_data_0; // @[WidthWidget.scala:27:9] wire anonIn_a_bits_corrupt = auto_anon_in_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire anonIn_d_ready = auto_anon_in_d_ready_0; // @[WidthWidget.scala:27:9] wire anonIn_d_valid; // @[MixedNode.scala:551:17] wire [2:0] anonIn_d_bits_opcode; // @[MixedNode.scala:551:17] wire [1:0] anonIn_d_bits_param; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_size; // @[MixedNode.scala:551:17] wire [4:0] anonIn_d_bits_source; // @[MixedNode.scala:551:17] wire [3:0] anonIn_d_bits_sink; // @[MixedNode.scala:551:17] wire anonIn_d_bits_denied; // @[MixedNode.scala:551:17] wire [63:0] anonIn_d_bits_data; // @[MixedNode.scala:551:17] wire anonIn_d_bits_corrupt; // @[MixedNode.scala:551:17] wire anonOut_a_ready = auto_anon_out_a_ready_0; // @[WidthWidget.scala:27:9] wire anonOut_a_valid; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_opcode; // @[MixedNode.scala:542:17] wire [2:0] anonOut_a_bits_param; // @[MixedNode.scala:542:17] wire [3:0] anonOut_a_bits_size; // @[MixedNode.scala:542:17] wire [4:0] anonOut_a_bits_source; // @[MixedNode.scala:542:17] wire [31:0] anonOut_a_bits_address; // @[MixedNode.scala:542:17] wire [15:0] anonOut_a_bits_mask; // @[MixedNode.scala:542:17] wire [127:0] anonOut_a_bits_data; // @[MixedNode.scala:542:17] wire anonOut_a_bits_corrupt; // @[MixedNode.scala:542:17] wire anonOut_d_ready; // @[MixedNode.scala:542:17] wire anonOut_d_valid = auto_anon_out_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] anonOut_d_bits_opcode = auto_anon_out_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] anonOut_d_bits_param = auto_anon_out_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_size = auto_anon_out_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] anonOut_d_bits_source = auto_anon_out_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [3:0] anonOut_d_bits_sink = auto_anon_out_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_denied = auto_anon_out_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [127:0] anonOut_d_bits_data = auto_anon_out_d_bits_data_0; // @[WidthWidget.scala:27:9] wire anonOut_d_bits_corrupt = auto_anon_out_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [1:0] auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] wire [63:0] auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] wire [2:0] auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] wire [3:0] auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] wire [4:0] auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] wire [31:0] auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] wire [15:0] auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] wire [127:0] auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] wire auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] wire _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign auto_anon_in_a_ready_0 = anonIn_a_ready; // @[WidthWidget.scala:27:9] assign anonOut_a_bits_opcode = anonIn_a_bits_opcode; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_param = anonIn_a_bits_param; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_size = anonIn_a_bits_size; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_source = anonIn_a_bits_source; // @[MixedNode.scala:542:17, :551:17] assign anonOut_a_bits_address = anonIn_a_bits_address; // @[MixedNode.scala:542:17, :551:17] wire [7:0] anonOut_a_bits_mask_odata_0 = anonIn_a_bits_mask; // @[WidthWidget.scala:65:47] wire [7:0] anonOut_a_bits_mask_odata_1 = anonIn_a_bits_mask; // @[WidthWidget.scala:65:47] wire [63:0] anonOut_a_bits_data_odata_0 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire [63:0] anonOut_a_bits_data_odata_1 = anonIn_a_bits_data; // @[WidthWidget.scala:65:47] wire cated_ready = anonIn_d_ready; // @[WidthWidget.scala:161:25] wire cated_valid; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_valid_0 = anonIn_d_valid; // @[WidthWidget.scala:27:9] wire [2:0] cated_bits_opcode; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_opcode_0 = anonIn_d_bits_opcode; // @[WidthWidget.scala:27:9] wire [1:0] cated_bits_param; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_param_0 = anonIn_d_bits_param; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_size; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_size_0 = anonIn_d_bits_size; // @[WidthWidget.scala:27:9] wire [4:0] cated_bits_source; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_source_0 = anonIn_d_bits_source; // @[WidthWidget.scala:27:9] wire [3:0] cated_bits_sink; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_sink_0 = anonIn_d_bits_sink; // @[WidthWidget.scala:27:9] wire cated_bits_denied; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_denied_0 = anonIn_d_bits_denied; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data_0 = anonIn_d_bits_data; // @[WidthWidget.scala:27:9] wire cated_bits_corrupt; // @[WidthWidget.scala:161:25] assign auto_anon_in_d_bits_corrupt_0 = anonIn_d_bits_corrupt; // @[WidthWidget.scala:27:9] wire _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] assign auto_anon_out_a_valid_0 = anonOut_a_valid; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode_0 = anonOut_a_bits_opcode; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param_0 = anonOut_a_bits_param; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size_0 = anonOut_a_bits_size; // @[WidthWidget.scala:27:9] wire [3:0] _anonOut_a_bits_mask_sizeOH_T = anonOut_a_bits_size; // @[Misc.scala:202:34] assign auto_anon_out_a_bits_source_0 = anonOut_a_bits_source; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address_0 = anonOut_a_bits_address; // @[WidthWidget.scala:27:9] wire [15:0] _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] assign auto_anon_out_a_bits_mask_0 = anonOut_a_bits_mask; // @[WidthWidget.scala:27:9] wire [127:0] _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] assign auto_anon_out_a_bits_data_0 = anonOut_a_bits_data; // @[WidthWidget.scala:27:9] wire corrupt_out; // @[WidthWidget.scala:47:36] assign auto_anon_out_a_bits_corrupt_0 = anonOut_a_bits_corrupt; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready_0 = anonOut_d_ready; // @[WidthWidget.scala:27:9] wire _hasData_opdata_T = anonIn_a_bits_opcode[2]; // @[Edges.scala:92:37] wire hasData = ~_hasData_opdata_T; // @[Edges.scala:92:{28,37}] wire [18:0] _limit_T = 19'hF << anonIn_a_bits_size; // @[package.scala:243:71] wire [3:0] _limit_T_1 = _limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _limit_T_2 = ~_limit_T_1; // @[package.scala:243:{46,76}] wire limit = _limit_T_2[3]; // @[package.scala:243:46] reg count; // @[WidthWidget.scala:40:27] wire _enable_T = count; // @[WidthWidget.scala:40:27, :43:56] wire first = ~count; // @[WidthWidget.scala:40:27, :41:26] wire _last_T = count == limit; // @[WidthWidget.scala:38:47, :40:27, :42:26] wire _last_T_1 = ~hasData; // @[WidthWidget.scala:42:39] wire last = _last_T | _last_T_1; // @[WidthWidget.scala:42:{26,36,39}] wire _enable_T_1 = _enable_T & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_2 = _enable_T_1; // @[WidthWidget.scala:43:{63,72}] wire enable_0 = ~_enable_T_2; // @[WidthWidget.scala:43:{47,72}] wire _enable_T_3 = ~count; // @[WidthWidget.scala:40:27, :41:26, :43:56] wire _enable_T_4 = _enable_T_3 & limit; // @[WidthWidget.scala:38:47, :43:{56,63}] wire _enable_T_5 = _enable_T_4; // @[WidthWidget.scala:43:{63,72}] wire enable_1 = ~_enable_T_5; // @[WidthWidget.scala:43:{47,72}] reg corrupt_reg; // @[WidthWidget.scala:45:32] assign corrupt_out = anonIn_a_bits_corrupt | corrupt_reg; // @[WidthWidget.scala:45:32, :47:36] assign anonOut_a_bits_corrupt = corrupt_out; // @[WidthWidget.scala:47:36] wire _T = anonIn_a_ready & anonIn_a_valid; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_data_T; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_data_T = _T; // @[Decoupled.scala:51:35] wire _anonOut_a_bits_mask_T_1; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_mask_T_1 = _T; // @[Decoupled.scala:51:35] wire _repeat_sel_sel_T; // @[Decoupled.scala:51:35] assign _repeat_sel_sel_T = _T; // @[Decoupled.scala:51:35] wire [1:0] _count_T = {1'h0, count} + 2'h1; // @[WidthWidget.scala:40:27, :50:24] wire _count_T_1 = _count_T[0]; // @[WidthWidget.scala:50:24] wire _anonIn_a_ready_T = ~last; // @[WidthWidget.scala:42:36, :76:32] assign _anonIn_a_ready_T_1 = anonOut_a_ready | _anonIn_a_ready_T; // @[WidthWidget.scala:76:{29,32}] assign anonIn_a_ready = _anonIn_a_ready_T_1; // @[WidthWidget.scala:76:29] assign _anonOut_a_valid_T = anonIn_a_valid & last; // @[WidthWidget.scala:42:36, :77:29] assign anonOut_a_valid = _anonOut_a_valid_T; // @[WidthWidget.scala:77:29] reg anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_data_masked_enable_T = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_0 = enable_0 | _anonOut_a_bits_data_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_data_masked_enable_T_1 = ~anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_data_masked_enable_1 = enable_1 | _anonOut_a_bits_data_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [63:0] anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:66:24] wire [63:0] anonOut_a_bits_data_mdata_0 = anonOut_a_bits_data_masked_enable_0 ? anonOut_a_bits_data_odata_0 : anonOut_a_bits_data_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [63:0] anonOut_a_bits_data_mdata_1 = anonOut_a_bits_data_masked_enable_1 ? anonOut_a_bits_data_odata_1 : anonIn_a_bits_data; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonOut_a_bits_data_T_1 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_data_T_2 = _anonOut_a_bits_data_T & _anonOut_a_bits_data_T_1; // @[Decoupled.scala:51:35] assign _anonOut_a_bits_data_T_3 = {anonOut_a_bits_data_mdata_1, anonOut_a_bits_data_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] assign anonOut_a_bits_data = _anonOut_a_bits_data_T_3; // @[WidthWidget.scala:73:12] wire [1:0] anonOut_a_bits_mask_sizeOH_shiftAmount = _anonOut_a_bits_mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _anonOut_a_bits_mask_sizeOH_T_1 = 4'h1 << anonOut_a_bits_mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _anonOut_a_bits_mask_sizeOH_T_2 = _anonOut_a_bits_mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] anonOut_a_bits_mask_sizeOH = {_anonOut_a_bits_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire anonOut_a_bits_mask_sub_sub_sub_sub_0_1 = |(anonOut_a_bits_size[3:2]); // @[Misc.scala:206:21] wire anonOut_a_bits_mask_sub_sub_sub_size = anonOut_a_bits_mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_sub_sub_bit = anonOut_a_bits_address[3]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_sub_sub_1_2 = anonOut_a_bits_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire anonOut_a_bits_mask_sub_sub_sub_nbit = ~anonOut_a_bits_mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_sub_sub_0_2 = anonOut_a_bits_mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_sub_sub_acc_T = anonOut_a_bits_mask_sub_sub_sub_size & anonOut_a_bits_mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _anonOut_a_bits_mask_sub_sub_sub_acc_T_1 = anonOut_a_bits_mask_sub_sub_sub_size & anonOut_a_bits_mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire anonOut_a_bits_mask_sub_sub_size = anonOut_a_bits_mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_sub_bit = anonOut_a_bits_address[2]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_sub_nbit = ~anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_sub_0_2 = anonOut_a_bits_mask_sub_sub_sub_0_2 & anonOut_a_bits_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_sub_acc_T = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_0_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_sub_1_2 = anonOut_a_bits_mask_sub_sub_sub_0_2 & anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_sub_acc_T_1 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_1_1 = anonOut_a_bits_mask_sub_sub_sub_0_1 | _anonOut_a_bits_mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_sub_2_2 = anonOut_a_bits_mask_sub_sub_sub_1_2 & anonOut_a_bits_mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_sub_acc_T_2 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_2_1 = anonOut_a_bits_mask_sub_sub_sub_1_1 | _anonOut_a_bits_mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_sub_3_2 = anonOut_a_bits_mask_sub_sub_sub_1_2 & anonOut_a_bits_mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_sub_acc_T_3 = anonOut_a_bits_mask_sub_sub_size & anonOut_a_bits_mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_sub_3_1 = anonOut_a_bits_mask_sub_sub_sub_1_1 | _anonOut_a_bits_mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_size = anonOut_a_bits_mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_sub_bit = anonOut_a_bits_address[1]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_sub_nbit = ~anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_sub_0_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_0_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_1_2 = anonOut_a_bits_mask_sub_sub_0_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_1 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_1_1 = anonOut_a_bits_mask_sub_sub_0_1 | _anonOut_a_bits_mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_2_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_2 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_2_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_3_2 = anonOut_a_bits_mask_sub_sub_1_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_3 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_3_1 = anonOut_a_bits_mask_sub_sub_1_1 | _anonOut_a_bits_mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_4_2 = anonOut_a_bits_mask_sub_sub_2_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_4 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_4_1 = anonOut_a_bits_mask_sub_sub_2_1 | _anonOut_a_bits_mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_5_2 = anonOut_a_bits_mask_sub_sub_2_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_5 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_5_1 = anonOut_a_bits_mask_sub_sub_2_1 | _anonOut_a_bits_mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_6_2 = anonOut_a_bits_mask_sub_sub_3_2 & anonOut_a_bits_mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_6 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_6_1 = anonOut_a_bits_mask_sub_sub_3_1 | _anonOut_a_bits_mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_sub_7_2 = anonOut_a_bits_mask_sub_sub_3_2 & anonOut_a_bits_mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_sub_acc_T_7 = anonOut_a_bits_mask_sub_size & anonOut_a_bits_mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_sub_7_1 = anonOut_a_bits_mask_sub_sub_3_1 | _anonOut_a_bits_mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_size = anonOut_a_bits_mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire anonOut_a_bits_mask_bit = anonOut_a_bits_address[0]; // @[Misc.scala:210:26] wire anonOut_a_bits_mask_nbit = ~anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :211:20] wire anonOut_a_bits_mask_eq = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_1 = anonOut_a_bits_mask_sub_0_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_1 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_1 = anonOut_a_bits_mask_sub_0_1 | _anonOut_a_bits_mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_2 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_2 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_2 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_3 = anonOut_a_bits_mask_sub_1_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_3 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_3 = anonOut_a_bits_mask_sub_1_1 | _anonOut_a_bits_mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_4 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_4 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_4 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_5 = anonOut_a_bits_mask_sub_2_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_5 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_5 = anonOut_a_bits_mask_sub_2_1 | _anonOut_a_bits_mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_6 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_6 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_6 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_7 = anonOut_a_bits_mask_sub_3_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_7 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_7 = anonOut_a_bits_mask_sub_3_1 | _anonOut_a_bits_mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_8 = anonOut_a_bits_mask_sub_4_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_8 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_8 = anonOut_a_bits_mask_sub_4_1 | _anonOut_a_bits_mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_9 = anonOut_a_bits_mask_sub_4_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_9 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_9 = anonOut_a_bits_mask_sub_4_1 | _anonOut_a_bits_mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_10 = anonOut_a_bits_mask_sub_5_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_10 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_10 = anonOut_a_bits_mask_sub_5_1 | _anonOut_a_bits_mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_11 = anonOut_a_bits_mask_sub_5_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_11 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_11 = anonOut_a_bits_mask_sub_5_1 | _anonOut_a_bits_mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_12 = anonOut_a_bits_mask_sub_6_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_12 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_12 = anonOut_a_bits_mask_sub_6_1 | _anonOut_a_bits_mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_13 = anonOut_a_bits_mask_sub_6_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_13 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_13 = anonOut_a_bits_mask_sub_6_1 | _anonOut_a_bits_mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_14 = anonOut_a_bits_mask_sub_7_2 & anonOut_a_bits_mask_nbit; // @[Misc.scala:211:20, :214:27] wire _anonOut_a_bits_mask_acc_T_14 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_14 = anonOut_a_bits_mask_sub_7_1 | _anonOut_a_bits_mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire anonOut_a_bits_mask_eq_15 = anonOut_a_bits_mask_sub_7_2 & anonOut_a_bits_mask_bit; // @[Misc.scala:210:26, :214:27] wire _anonOut_a_bits_mask_acc_T_15 = anonOut_a_bits_mask_size & anonOut_a_bits_mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire anonOut_a_bits_mask_acc_15 = anonOut_a_bits_mask_sub_7_1 | _anonOut_a_bits_mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] anonOut_a_bits_mask_lo_lo_lo = {anonOut_a_bits_mask_acc_1, anonOut_a_bits_mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_lo_lo_hi = {anonOut_a_bits_mask_acc_3, anonOut_a_bits_mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_lo_lo = {anonOut_a_bits_mask_lo_lo_hi, anonOut_a_bits_mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] anonOut_a_bits_mask_lo_hi_lo = {anonOut_a_bits_mask_acc_5, anonOut_a_bits_mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_lo_hi_hi = {anonOut_a_bits_mask_acc_7, anonOut_a_bits_mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_lo_hi = {anonOut_a_bits_mask_lo_hi_hi, anonOut_a_bits_mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] anonOut_a_bits_mask_lo = {anonOut_a_bits_mask_lo_hi, anonOut_a_bits_mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] anonOut_a_bits_mask_hi_lo_lo = {anonOut_a_bits_mask_acc_9, anonOut_a_bits_mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_hi_lo_hi = {anonOut_a_bits_mask_acc_11, anonOut_a_bits_mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_hi_lo = {anonOut_a_bits_mask_hi_lo_hi, anonOut_a_bits_mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] anonOut_a_bits_mask_hi_hi_lo = {anonOut_a_bits_mask_acc_13, anonOut_a_bits_mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] anonOut_a_bits_mask_hi_hi_hi = {anonOut_a_bits_mask_acc_15, anonOut_a_bits_mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] anonOut_a_bits_mask_hi_hi = {anonOut_a_bits_mask_hi_hi_hi, anonOut_a_bits_mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] anonOut_a_bits_mask_hi = {anonOut_a_bits_mask_hi_hi, anonOut_a_bits_mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] _anonOut_a_bits_mask_T = {anonOut_a_bits_mask_hi, anonOut_a_bits_mask_lo}; // @[Misc.scala:222:10] reg anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41] wire _anonOut_a_bits_mask_masked_enable_T = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_0 = enable_0 | _anonOut_a_bits_mask_masked_enable_T; // @[WidthWidget.scala:43:47, :63:{42,45}] wire _anonOut_a_bits_mask_masked_enable_T_1 = ~anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :63:45] wire anonOut_a_bits_mask_masked_enable_1 = enable_1 | _anonOut_a_bits_mask_masked_enable_T_1; // @[WidthWidget.scala:43:47, :63:{42,45}] reg [7:0] anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:66:24] wire [7:0] anonOut_a_bits_mask_mdata_0 = anonOut_a_bits_mask_masked_enable_0 ? anonOut_a_bits_mask_odata_0 : anonOut_a_bits_mask_rdata_0; // @[WidthWidget.scala:63:42, :65:47, :66:24, :68:88] wire [7:0] anonOut_a_bits_mask_mdata_1 = anonOut_a_bits_mask_masked_enable_1 ? anonOut_a_bits_mask_odata_1 : anonIn_a_bits_mask; // @[WidthWidget.scala:63:42, :65:47, :68:88] wire _anonOut_a_bits_mask_T_2 = ~last; // @[WidthWidget.scala:42:36, :69:26, :76:32] wire _anonOut_a_bits_mask_T_3 = _anonOut_a_bits_mask_T_1 & _anonOut_a_bits_mask_T_2; // @[Decoupled.scala:51:35] wire [15:0] _anonOut_a_bits_mask_T_4 = {anonOut_a_bits_mask_mdata_1, anonOut_a_bits_mask_mdata_0}; // @[WidthWidget.scala:68:88, :73:12] wire [15:0] _anonOut_a_bits_mask_T_6 = hasData ? _anonOut_a_bits_mask_T_4 : 16'hFFFF; // @[WidthWidget.scala:73:12, :85:93] assign _anonOut_a_bits_mask_T_7 = _anonOut_a_bits_mask_T & _anonOut_a_bits_mask_T_6; // @[Misc.scala:222:10] assign anonOut_a_bits_mask = _anonOut_a_bits_mask_T_7; // @[WidthWidget.scala:85:88] wire _repeat_T_1; // @[WidthWidget.scala:148:7] wire repeat_0; // @[WidthWidget.scala:159:26] assign anonIn_d_valid = cated_valid; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_opcode = cated_bits_opcode; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_param = cated_bits_param; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_size = cated_bits_size; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_source = cated_bits_source; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_sink = cated_bits_sink; // @[WidthWidget.scala:161:25] assign anonIn_d_bits_denied = cated_bits_denied; // @[WidthWidget.scala:161:25] wire [127:0] _cated_bits_data_T_2; // @[WidthWidget.scala:163:39] assign anonIn_d_bits_corrupt = cated_bits_corrupt; // @[WidthWidget.scala:161:25] wire [127:0] cated_bits_data; // @[WidthWidget.scala:161:25] wire [63:0] _cated_bits_data_T = _repeated_repeater_io_deq_bits_data[127:64]; // @[Repeater.scala:36:26] wire [63:0] _cated_bits_data_T_1 = anonOut_d_bits_data[63:0]; // @[WidthWidget.scala:165:31] assign _cated_bits_data_T_2 = {_cated_bits_data_T, _cated_bits_data_T_1}; // @[WidthWidget.scala:163:39, :164:37, :165:31] assign cated_bits_data = _cated_bits_data_T_2; // @[WidthWidget.scala:161:25, :163:39] wire repeat_hasData = cated_bits_opcode[0]; // @[WidthWidget.scala:161:25] wire [18:0] _repeat_limit_T = 19'hF << cated_bits_size; // @[package.scala:243:71] wire [3:0] _repeat_limit_T_1 = _repeat_limit_T[3:0]; // @[package.scala:243:{71,76}] wire [3:0] _repeat_limit_T_2 = ~_repeat_limit_T_1; // @[package.scala:243:{46,76}] wire repeat_limit = _repeat_limit_T_2[3]; // @[package.scala:243:46] reg repeat_count; // @[WidthWidget.scala:105:26] wire repeat_first = ~repeat_count; // @[WidthWidget.scala:105:26, :106:25] wire _repeat_last_T = repeat_count == repeat_limit; // @[WidthWidget.scala:103:47, :105:26, :107:25] wire _repeat_last_T_1 = ~repeat_hasData; // @[WidthWidget.scala:107:38] wire repeat_last = _repeat_last_T | _repeat_last_T_1; // @[WidthWidget.scala:107:{25,35,38}] wire _repeat_T = anonIn_d_ready & anonIn_d_valid; // @[Decoupled.scala:51:35] wire [1:0] _repeat_count_T = {1'h0, repeat_count} + 2'h1; // @[WidthWidget.scala:105:26, :110:24] wire _repeat_count_T_1 = _repeat_count_T[0]; // @[WidthWidget.scala:110:24] reg repeat_sel_sel_sources_0; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_1; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_2; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_3; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_4; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_5; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_6; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_7; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_8; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_9; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_10; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_11; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_12; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_13; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_14; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_15; // @[WidthWidget.scala:187:27] reg repeat_sel_sel_sources_16; // @[WidthWidget.scala:187:27] wire repeat_sel_sel_a_sel = anonIn_a_bits_address[3]; // @[WidthWidget.scala:188:38] wire _repeat_sel_sel_bypass_T = anonIn_a_bits_source == cated_bits_source; // @[WidthWidget.scala:161:25, :200:53] wire repeat_sel_sel_bypass = anonIn_a_valid & _repeat_sel_sel_bypass_T; // @[WidthWidget.scala:200:{33,53}] reg repeat_sel_hold_r; // @[WidthWidget.scala:121:47] wire [31:0] _GEN = {{repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_0}, {repeat_sel_sel_sources_16}, {repeat_sel_sel_sources_15}, {repeat_sel_sel_sources_14}, {repeat_sel_sel_sources_13}, {repeat_sel_sel_sources_12}, {repeat_sel_sel_sources_11}, {repeat_sel_sel_sources_10}, {repeat_sel_sel_sources_9}, {repeat_sel_sel_sources_8}, {repeat_sel_sel_sources_7}, {repeat_sel_sel_sources_6}, {repeat_sel_sel_sources_5}, {repeat_sel_sel_sources_4}, {repeat_sel_sel_sources_3}, {repeat_sel_sel_sources_2}, {repeat_sel_sel_sources_1}, {repeat_sel_sel_sources_0}}; // @[WidthWidget.scala:121:47, :187:27] wire repeat_sel_hold = repeat_first ? _GEN[cated_bits_source] : repeat_sel_hold_r; // @[WidthWidget.scala:106:25, :121:{25,47}, :161:25] wire _repeat_sel_T = ~repeat_limit; // @[WidthWidget.scala:103:47, :122:18] wire repeat_sel = repeat_sel_hold & _repeat_sel_T; // @[WidthWidget.scala:121:25, :122:{16,18}] wire repeat_index = repeat_sel | repeat_count; // @[WidthWidget.scala:105:26, :122:16, :126:24] wire [63:0] _repeat_anonIn_d_bits_data_mux_T = cated_bits_data[63:0]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonIn_d_bits_data_mux_0 = _repeat_anonIn_d_bits_data_mux_T; // @[WidthWidget.scala:128:{43,55}] wire [63:0] _repeat_anonIn_d_bits_data_mux_T_1 = cated_bits_data[127:64]; // @[WidthWidget.scala:128:55, :161:25] wire [63:0] repeat_anonIn_d_bits_data_mux_1 = _repeat_anonIn_d_bits_data_mux_T_1; // @[WidthWidget.scala:128:{43,55}] assign anonIn_d_bits_data = repeat_index ? repeat_anonIn_d_bits_data_mux_1 : repeat_anonIn_d_bits_data_mux_0; // @[WidthWidget.scala:126:24, :128:43, :137:30] assign _repeat_T_1 = ~repeat_last; // @[WidthWidget.scala:107:35, :148:7] assign repeat_0 = _repeat_T_1; // @[WidthWidget.scala:148:7, :159:26] always @(posedge clock) begin // @[WidthWidget.scala:27:9] if (reset) begin // @[WidthWidget.scala:27:9] count <= 1'h0; // @[WidthWidget.scala:40:27] corrupt_reg <= 1'h0; // @[WidthWidget.scala:45:32] anonOut_a_bits_data_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] anonOut_a_bits_mask_rdata_written_once <= 1'h0; // @[WidthWidget.scala:62:41] repeat_count <= 1'h0; // @[WidthWidget.scala:105:26] end else begin // @[WidthWidget.scala:27:9] if (_T) begin // @[Decoupled.scala:51:35] count <= ~last & _count_T_1; // @[WidthWidget.scala:40:27, :42:36, :50:{15,24}, :52:21, :53:17] corrupt_reg <= ~last & corrupt_out; // @[WidthWidget.scala:42:36, :45:32, :47:36, :50:15, :51:21, :52:21, :53:17, :54:23] end anonOut_a_bits_data_rdata_written_once <= _anonOut_a_bits_data_T_2 | anonOut_a_bits_data_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] anonOut_a_bits_mask_rdata_written_once <= _anonOut_a_bits_mask_T_3 | anonOut_a_bits_mask_rdata_written_once; // @[WidthWidget.scala:62:41, :69:{23,33}, :70:30] if (_repeat_T) // @[Decoupled.scala:51:35] repeat_count <= ~repeat_last & _repeat_count_T_1; // @[WidthWidget.scala:105:26, :107:35, :110:{15,24}, :111:{21,29}] end if (_anonOut_a_bits_data_T_2) // @[WidthWidget.scala:69:23] anonOut_a_bits_data_rdata_0 <= anonOut_a_bits_data_mdata_0; // @[WidthWidget.scala:66:24, :68:88] if (_anonOut_a_bits_mask_T_3) // @[WidthWidget.scala:69:23] anonOut_a_bits_mask_rdata_0 <= anonOut_a_bits_mask_mdata_0; // @[WidthWidget.scala:66:24, :68:88] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h0) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_0 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h1) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_1 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h2) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_2 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h3) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_3 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h4) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_4 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h5) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_5 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h6) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_6 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h7) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_7 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h8) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_8 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h9) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_9 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hA) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_10 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hB) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_11 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hC) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_12 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hD) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_13 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hE) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_14 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'hF) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_15 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (_repeat_sel_sel_T & anonIn_a_bits_source == 5'h10) // @[Decoupled.scala:51:35] repeat_sel_sel_sources_16 <= repeat_sel_sel_a_sel; // @[WidthWidget.scala:187:27, :188:38] if (repeat_first) // @[WidthWidget.scala:106:25] repeat_sel_hold_r <= _GEN[cated_bits_source]; // @[WidthWidget.scala:121:47, :161:25] always @(posedge) TLMonitor_6 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (anonIn_a_ready), // @[MixedNode.scala:551:17] .io_in_a_valid (anonIn_a_valid), // @[MixedNode.scala:551:17] .io_in_a_bits_opcode (anonIn_a_bits_opcode), // @[MixedNode.scala:551:17] .io_in_a_bits_param (anonIn_a_bits_param), // @[MixedNode.scala:551:17] .io_in_a_bits_size (anonIn_a_bits_size), // @[MixedNode.scala:551:17] .io_in_a_bits_source (anonIn_a_bits_source), // @[MixedNode.scala:551:17] .io_in_a_bits_address (anonIn_a_bits_address), // @[MixedNode.scala:551:17] .io_in_a_bits_mask (anonIn_a_bits_mask), // @[MixedNode.scala:551:17] .io_in_a_bits_data (anonIn_a_bits_data), // @[MixedNode.scala:551:17] .io_in_a_bits_corrupt (anonIn_a_bits_corrupt), // @[MixedNode.scala:551:17] .io_in_d_ready (anonIn_d_ready), // @[MixedNode.scala:551:17] .io_in_d_valid (anonIn_d_valid), // @[MixedNode.scala:551:17] .io_in_d_bits_opcode (anonIn_d_bits_opcode), // @[MixedNode.scala:551:17] .io_in_d_bits_param (anonIn_d_bits_param), // @[MixedNode.scala:551:17] .io_in_d_bits_size (anonIn_d_bits_size), // @[MixedNode.scala:551:17] .io_in_d_bits_source (anonIn_d_bits_source), // @[MixedNode.scala:551:17] .io_in_d_bits_sink (anonIn_d_bits_sink), // @[MixedNode.scala:551:17] .io_in_d_bits_denied (anonIn_d_bits_denied), // @[MixedNode.scala:551:17] .io_in_d_bits_data (anonIn_d_bits_data), // @[MixedNode.scala:551:17] .io_in_d_bits_corrupt (anonIn_d_bits_corrupt) // @[MixedNode.scala:551:17] ); // @[Nodes.scala:27:25] Repeater_TLBundleD_a32d128s5k4z4u repeated_repeater ( // @[Repeater.scala:36:26] .clock (clock), .reset (reset), .io_repeat (repeat_0), // @[WidthWidget.scala:159:26] .io_enq_ready (anonOut_d_ready), .io_enq_valid (anonOut_d_valid), // @[MixedNode.scala:542:17] .io_enq_bits_opcode (anonOut_d_bits_opcode), // @[MixedNode.scala:542:17] .io_enq_bits_param (anonOut_d_bits_param), // @[MixedNode.scala:542:17] .io_enq_bits_size (anonOut_d_bits_size), // @[MixedNode.scala:542:17] .io_enq_bits_source (anonOut_d_bits_source), // @[MixedNode.scala:542:17] .io_enq_bits_sink (anonOut_d_bits_sink), // @[MixedNode.scala:542:17] .io_enq_bits_denied (anonOut_d_bits_denied), // @[MixedNode.scala:542:17] .io_enq_bits_data (anonOut_d_bits_data), // @[MixedNode.scala:542:17] .io_enq_bits_corrupt (anonOut_d_bits_corrupt), // @[MixedNode.scala:542:17] .io_deq_ready (cated_ready), // @[WidthWidget.scala:161:25] .io_deq_valid (cated_valid), .io_deq_bits_opcode (cated_bits_opcode), .io_deq_bits_param (cated_bits_param), .io_deq_bits_size (cated_bits_size), .io_deq_bits_source (cated_bits_source), .io_deq_bits_sink (cated_bits_sink), .io_deq_bits_denied (cated_bits_denied), .io_deq_bits_data (_repeated_repeater_io_deq_bits_data), .io_deq_bits_corrupt (cated_bits_corrupt) ); // @[Repeater.scala:36:26] assign auto_anon_in_a_ready = auto_anon_in_a_ready_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_valid = auto_anon_in_d_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_opcode = auto_anon_in_d_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_param = auto_anon_in_d_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_size = auto_anon_in_d_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_source = auto_anon_in_d_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_sink = auto_anon_in_d_bits_sink_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_denied = auto_anon_in_d_bits_denied_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_data = auto_anon_in_d_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_in_d_bits_corrupt = auto_anon_in_d_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_valid = auto_anon_out_a_valid_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_opcode = auto_anon_out_a_bits_opcode_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_param = auto_anon_out_a_bits_param_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_size = auto_anon_out_a_bits_size_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_source = auto_anon_out_a_bits_source_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_address = auto_anon_out_a_bits_address_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_mask = auto_anon_out_a_bits_mask_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_data = auto_anon_out_a_bits_data_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_a_bits_corrupt = auto_anon_out_a_bits_corrupt_0; // @[WidthWidget.scala:27:9] assign auto_anon_out_d_ready = auto_anon_out_d_ready_0; // @[WidthWidget.scala:27:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_462 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_206 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<32>, clock reg c2 : SInt<32>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h1), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node c1_sign = bits(io.in_d, 19, 19) node c1_lo_lo_hi = cat(c1_sign, c1_sign) node c1_lo_lo = cat(c1_lo_lo_hi, c1_sign) node c1_lo_hi_hi = cat(c1_sign, c1_sign) node c1_lo_hi = cat(c1_lo_hi_hi, c1_sign) node c1_lo = cat(c1_lo_hi, c1_lo_lo) node c1_hi_lo_hi = cat(c1_sign, c1_sign) node c1_hi_lo = cat(c1_hi_lo_hi, c1_sign) node c1_hi_hi_hi = cat(c1_sign, c1_sign) node c1_hi_hi = cat(c1_hi_hi_hi, c1_sign) node c1_hi = cat(c1_hi_hi, c1_hi_lo) node _c1_T = cat(c1_hi, c1_lo) node c1_lo_1 = asUInt(io.in_d) node _c1_T_1 = cat(_c1_T, c1_lo_1) wire _c1_WIRE : SInt<32> node _c1_T_2 = asSInt(_c1_T_1) connect _c1_WIRE, _c1_T_2 connect c1, _c1_WIRE else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node c2_sign = bits(io.in_d, 19, 19) node c2_lo_lo_hi = cat(c2_sign, c2_sign) node c2_lo_lo = cat(c2_lo_lo_hi, c2_sign) node c2_lo_hi_hi = cat(c2_sign, c2_sign) node c2_lo_hi = cat(c2_lo_hi_hi, c2_sign) node c2_lo = cat(c2_lo_hi, c2_lo_lo) node c2_hi_lo_hi = cat(c2_sign, c2_sign) node c2_hi_lo = cat(c2_hi_lo_hi, c2_sign) node c2_hi_hi_hi = cat(c2_sign, c2_sign) node c2_hi_hi = cat(c2_hi_hi_hi, c2_sign) node c2_hi = cat(c2_hi_hi, c2_hi_lo) node _c2_T = cat(c2_hi, c2_lo) node c2_lo_1 = asUInt(io.in_d) node _c2_T_1 = cat(_c2_T, c2_lo_1) wire _c2_WIRE : SInt<32> node _c2_T_2 = asSInt(_c2_T_1) connect _c2_WIRE, _c2_T_2 connect c2, _c2_WIRE else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h1), _T_4) node _T_6 = or(UInt<1>(0h0), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_462( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid, // @[PE.scala:35:14] output io_bad_dataflow // @[PE.scala:35:14] ); wire [19:0] _mac_unit_io_out_d; // @[PE.scala:64:24] wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow_0 = 1'h0; // @[PE.scala:31:7] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire [19:0] c1_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire [19:0] c2_lo_1 = io_in_d_0; // @[PE.scala:31:7] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [31:0] c1; // @[PE.scala:70:15] wire [31:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [31:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [31:0] c2; // @[PE.scala:71:15] wire [31:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [31:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = _io_out_c_zeros_T_1 & _io_out_c_zeros_T_6; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_2 = {27'h0, shift_offset}; // @[PE.scala:91:25] wire [31:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [31:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_2 = {_io_out_c_T[31], _io_out_c_T} + {{31{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_3 = _io_out_c_T_2[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire _io_out_c_T_5 = $signed(_io_out_c_T_4) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_6 = $signed(_io_out_c_T_4) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_7 = _io_out_c_T_6 ? 32'hFFF80000 : _io_out_c_T_4; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_8 = _io_out_c_T_5 ? 32'h7FFFF : _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire c1_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire c2_sign = io_in_d_0[19]; // @[PE.scala:31:7] wire [1:0] _GEN_4 = {2{c1_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c1_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c1_lo_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c1_lo_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c1_hi_lo_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [1:0] c1_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c1_hi_hi_hi = _GEN_4; // @[Arithmetic.scala:118:18] wire [2:0] c1_lo_lo = {c1_lo_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_lo_hi = {c1_lo_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_lo = {c1_lo_hi, c1_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c1_hi_lo = {c1_hi_lo_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c1_hi_hi = {c1_hi_hi_hi, c1_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c1_hi = {c1_hi_hi, c1_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c1_T = {c1_hi, c1_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c1_T_1 = {_c1_T, c1_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c1_T_2 = _c1_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c1_WIRE = _c1_T_2; // @[Arithmetic.scala:118:61] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [31:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = _io_out_c_zeros_T_10 & _io_out_c_zeros_T_15; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [31:0] _GEN_5 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [31:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_5; // @[Arithmetic.scala:103:30] wire [31:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_5; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [32:0] _io_out_c_T_13 = {_io_out_c_T_11[31], _io_out_c_T_11} + {{31{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [31:0] _io_out_c_T_14 = _io_out_c_T_13[31:0]; // @[Arithmetic.scala:107:28] wire [31:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire _io_out_c_T_16 = $signed(_io_out_c_T_15) > 32'sh7FFFF; // @[Arithmetic.scala:107:28, :125:33] wire _io_out_c_T_17 = $signed(_io_out_c_T_15) < -32'sh80000; // @[Arithmetic.scala:107:28, :125:60] wire [31:0] _io_out_c_T_18 = _io_out_c_T_17 ? 32'hFFF80000 : _io_out_c_T_15; // @[Mux.scala:126:16] wire [31:0] _io_out_c_T_19 = _io_out_c_T_16 ? 32'h7FFFF : _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19[19:0]; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [1:0] _GEN_6 = {2{c2_sign}}; // @[Arithmetic.scala:117:26, :118:18] wire [1:0] c2_lo_lo_hi; // @[Arithmetic.scala:118:18] assign c2_lo_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_lo_hi_hi; // @[Arithmetic.scala:118:18] assign c2_lo_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_lo_hi; // @[Arithmetic.scala:118:18] assign c2_hi_lo_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [1:0] c2_hi_hi_hi; // @[Arithmetic.scala:118:18] assign c2_hi_hi_hi = _GEN_6; // @[Arithmetic.scala:118:18] wire [2:0] c2_lo_lo = {c2_lo_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_lo_hi = {c2_lo_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_lo = {c2_lo_hi, c2_lo_lo}; // @[Arithmetic.scala:118:18] wire [2:0] c2_hi_lo = {c2_hi_lo_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [2:0] c2_hi_hi = {c2_hi_hi_hi, c2_sign}; // @[Arithmetic.scala:117:26, :118:18] wire [5:0] c2_hi = {c2_hi_hi, c2_hi_lo}; // @[Arithmetic.scala:118:18] wire [11:0] _c2_T = {c2_hi, c2_lo}; // @[Arithmetic.scala:118:18] wire [31:0] _c2_T_1 = {_c2_T, c2_lo_1}; // @[Arithmetic.scala:118:{14,18}] wire [31:0] _c2_T_2 = _c2_T_1; // @[Arithmetic.scala:118:{14,61}] wire [31:0] _c2_WIRE = _c2_T_2; // @[Arithmetic.scala:118:61] wire [31:0] _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5[7:0]; // @[PE.scala:121:38] wire [31:0] _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7[7:0]; // @[PE.scala:127:38] assign io_out_c_0 = io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? c1[19:0] : c2[19:0]) : io_in_control_propagate_0 ? _io_out_c_T_10 : _io_out_c_T_21; // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :104:16, :111:16, :118:101, :119:30, :120:16, :126:16] assign io_out_b_0 = io_in_control_dataflow_0 ? _mac_unit_io_out_d : io_in_b_0; // @[PE.scala:31:7, :64:24, :102:95, :103:30, :118:101] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] wire [31:0] _GEN_7 = {{12{io_in_d_0[19]}}, io_in_d_0}; // @[PE.scala:31:7, :124:10] wire [31:0] _GEN_8 = {{12{_mac_unit_io_out_d[19]}}, _mac_unit_io_out_d}; // @[PE.scala:64:24, :108:10] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0) begin // @[PE.scala:31:7] if (io_in_control_dataflow_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :70:15, :118:101, :119:30, :124:10] c1 <= _GEN_7; // @[PE.scala:70:15, :124:10] if (~io_in_control_dataflow_0 | io_in_control_propagate_0) begin // @[PE.scala:31:7, :71:15, :118:101, :119:30] end else // @[PE.scala:71:15, :118:101, :119:30] c2 <= _GEN_7; // @[PE.scala:71:15, :124:10] end else begin // @[PE.scala:31:7] c1 <= io_in_control_propagate_0 ? _c1_WIRE : _GEN_8; // @[PE.scala:31:7, :70:15, :103:30, :108:10, :109:10, :115:10] c2 <= io_in_control_propagate_0 ? _GEN_8 : _c2_WIRE; // @[PE.scala:31:7, :71:15, :103:30, :108:10, :116:10] end last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] end always @(posedge) MacUnit_206 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_dataflow_0 ? (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3) : io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE : _mac_unit_io_in_b_WIRE_1), // @[PE.scala:31:7, :102:95, :103:30, :106:{24,37}, :113:{24,37}, :118:101, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_control_dataflow_0 ? {{12{io_in_b_0[19]}}, io_in_b_0} : io_in_control_propagate_0 ? c2 : c1), // @[PE.scala:31:7, :70:15, :71:15, :102:95, :103:30, :107:24, :114:24, :118:101, :122:24] .io_out_d (_mac_unit_io_out_d) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLFragmenter_PLIC : input clock : Clock input reset : Reset output auto : { flip anon_in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, anon_out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire anonIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonIn.d.bits.corrupt invalidate anonIn.d.bits.data invalidate anonIn.d.bits.denied invalidate anonIn.d.bits.sink invalidate anonIn.d.bits.source invalidate anonIn.d.bits.size invalidate anonIn.d.bits.param invalidate anonIn.d.bits.opcode invalidate anonIn.d.valid invalidate anonIn.d.ready invalidate anonIn.a.bits.corrupt invalidate anonIn.a.bits.data invalidate anonIn.a.bits.mask invalidate anonIn.a.bits.address invalidate anonIn.a.bits.source invalidate anonIn.a.bits.size invalidate anonIn.a.bits.param invalidate anonIn.a.bits.opcode invalidate anonIn.a.valid invalidate anonIn.a.ready inst monitor of TLMonitor_37 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, anonIn.d.bits.corrupt connect monitor.io.in.d.bits.data, anonIn.d.bits.data connect monitor.io.in.d.bits.denied, anonIn.d.bits.denied connect monitor.io.in.d.bits.sink, anonIn.d.bits.sink connect monitor.io.in.d.bits.source, anonIn.d.bits.source connect monitor.io.in.d.bits.size, anonIn.d.bits.size connect monitor.io.in.d.bits.param, anonIn.d.bits.param connect monitor.io.in.d.bits.opcode, anonIn.d.bits.opcode connect monitor.io.in.d.valid, anonIn.d.valid connect monitor.io.in.d.ready, anonIn.d.ready connect monitor.io.in.a.bits.corrupt, anonIn.a.bits.corrupt connect monitor.io.in.a.bits.data, anonIn.a.bits.data connect monitor.io.in.a.bits.mask, anonIn.a.bits.mask connect monitor.io.in.a.bits.address, anonIn.a.bits.address connect monitor.io.in.a.bits.source, anonIn.a.bits.source connect monitor.io.in.a.bits.size, anonIn.a.bits.size connect monitor.io.in.a.bits.param, anonIn.a.bits.param connect monitor.io.in.a.bits.opcode, anonIn.a.bits.opcode connect monitor.io.in.a.valid, anonIn.a.valid connect monitor.io.in.a.ready, anonIn.a.ready wire anonOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate anonOut.d.bits.corrupt invalidate anonOut.d.bits.data invalidate anonOut.d.bits.denied invalidate anonOut.d.bits.sink invalidate anonOut.d.bits.source invalidate anonOut.d.bits.size invalidate anonOut.d.bits.param invalidate anonOut.d.bits.opcode invalidate anonOut.d.valid invalidate anonOut.d.ready invalidate anonOut.a.bits.corrupt invalidate anonOut.a.bits.data invalidate anonOut.a.bits.mask invalidate anonOut.a.bits.address invalidate anonOut.a.bits.source invalidate anonOut.a.bits.size invalidate anonOut.a.bits.param invalidate anonOut.a.bits.opcode invalidate anonOut.a.valid invalidate anonOut.a.ready connect auto.anon_out, anonOut connect anonIn, auto.anon_in regreset acknum : UInt<3>, clock, reset, UInt<3>(0h0) reg dOrig : UInt, clock regreset dToggle : UInt<1>, clock, reset, UInt<1>(0h0) node dFragnum = bits(anonOut.d.bits.source, 2, 0) node dFirst = eq(acknum, UInt<1>(0h0)) node dLast = eq(dFragnum, UInt<1>(0h0)) node dsizeOH_shiftAmount = bits(anonOut.d.bits.size, 1, 0) node _dsizeOH_T = dshl(UInt<1>(0h1), dsizeOH_shiftAmount) node dsizeOH = bits(_dsizeOH_T, 3, 0) node _dsizeOH1_T = dshl(UInt<3>(0h7), anonOut.d.bits.size) node _dsizeOH1_T_1 = bits(_dsizeOH1_T, 2, 0) node dsizeOH1 = not(_dsizeOH1_T_1) node dHasData = bits(anonOut.d.bits.opcode, 0, 0) node acknum_fragment = shl(dFragnum, 0) node acknum_size = shr(dsizeOH1, 3) node _T = eq(anonOut.d.valid, UInt<1>(0h0)) node _T_1 = and(acknum_fragment, acknum_size) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = or(_T, _T_2) node _T_4 = asUInt(reset) node _T_5 = eq(_T_4, UInt<1>(0h0)) when _T_5 : node _T_6 = eq(_T_3, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:214 assert (!out.d.valid || (acknum_fragment & acknum_size) === 0.U)\n") : printf assert(clock, _T_3, UInt<1>(0h1), "") : assert node _dFirst_acknum_T = mux(dHasData, acknum_size, UInt<1>(0h0)) node dFirst_acknum = or(acknum_fragment, _dFirst_acknum_T) node _ack_decrement_T = shr(dsizeOH, 3) node ack_decrement = mux(dHasData, UInt<1>(0h1), _ack_decrement_T) node _dFirst_size_T = shl(dFragnum, 3) node _dFirst_size_T_1 = or(_dFirst_size_T, dsizeOH1) node _dFirst_size_T_2 = shl(_dFirst_size_T_1, 1) node _dFirst_size_T_3 = or(_dFirst_size_T_2, UInt<1>(0h1)) node _dFirst_size_T_4 = cat(UInt<1>(0h0), _dFirst_size_T_1) node _dFirst_size_T_5 = not(_dFirst_size_T_4) node _dFirst_size_T_6 = and(_dFirst_size_T_3, _dFirst_size_T_5) node dFirst_size_hi = bits(_dFirst_size_T_6, 6, 4) node dFirst_size_lo = bits(_dFirst_size_T_6, 3, 0) node _dFirst_size_T_7 = orr(dFirst_size_hi) node _dFirst_size_T_8 = or(dFirst_size_hi, dFirst_size_lo) node dFirst_size_hi_1 = bits(_dFirst_size_T_8, 3, 2) node dFirst_size_lo_1 = bits(_dFirst_size_T_8, 1, 0) node _dFirst_size_T_9 = orr(dFirst_size_hi_1) node _dFirst_size_T_10 = or(dFirst_size_hi_1, dFirst_size_lo_1) node _dFirst_size_T_11 = bits(_dFirst_size_T_10, 1, 1) node _dFirst_size_T_12 = cat(_dFirst_size_T_9, _dFirst_size_T_11) node dFirst_size = cat(_dFirst_size_T_7, _dFirst_size_T_12) node _T_7 = and(anonOut.d.ready, anonOut.d.valid) when _T_7 : node _acknum_T = sub(acknum, ack_decrement) node _acknum_T_1 = tail(_acknum_T, 1) node _acknum_T_2 = mux(dFirst, dFirst_acknum, _acknum_T_1) connect acknum, _acknum_T_2 when dFirst : connect dOrig, dFirst_size node _dToggle_T = bits(anonOut.d.bits.source, 3, 3) connect dToggle, _dToggle_T node _drop_T = eq(dHasData, UInt<1>(0h0)) node _drop_T_1 = mux(UInt<1>(0h0), dFirst, dLast) node _drop_T_2 = eq(_drop_T_1, UInt<1>(0h0)) node drop = and(_drop_T, _drop_T_2) node _anonOut_d_ready_T = or(anonIn.d.ready, drop) connect anonOut.d.ready, _anonOut_d_ready_T node _anonIn_d_valid_T = eq(drop, UInt<1>(0h0)) node _anonIn_d_valid_T_1 = and(anonOut.d.valid, _anonIn_d_valid_T) connect anonIn.d.valid, _anonIn_d_valid_T_1 connect anonIn.d.bits.corrupt, anonOut.d.bits.corrupt connect anonIn.d.bits.data, anonOut.d.bits.data connect anonIn.d.bits.denied, anonOut.d.bits.denied connect anonIn.d.bits.sink, anonOut.d.bits.sink connect anonIn.d.bits.source, anonOut.d.bits.source connect anonIn.d.bits.size, anonOut.d.bits.size connect anonIn.d.bits.param, anonOut.d.bits.param connect anonIn.d.bits.opcode, anonOut.d.bits.opcode node _anonIn_d_bits_source_T = shr(anonOut.d.bits.source, 4) connect anonIn.d.bits.source, _anonIn_d_bits_source_T node _anonIn_d_bits_size_T = mux(dFirst, dFirst_size, dOrig) connect anonIn.d.bits.size, _anonIn_d_bits_size_T inst repeater of Repeater_TLBundleA_a28d64s8k1z3u connect repeater.clock, clock connect repeater.reset, reset connect repeater.io.enq, anonIn.a node _find_T = xor(repeater.io.deq.bits.address, UInt<1>(0h0)) node _find_T_1 = cvt(_find_T) node _find_T_2 = and(_find_T_1, asSInt(UInt<1>(0h0))) node _find_T_3 = asSInt(_find_T_2) node _find_T_4 = eq(_find_T_3, asSInt(UInt<1>(0h0))) wire find : UInt<1>[1] connect find[0], _find_T_4 node _limit_T = eq(UInt<1>(0h0), repeater.io.deq.bits.opcode) node _limit_T_1 = mux(_limit_T, UInt<2>(0h3), UInt<2>(0h3)) node _limit_T_2 = eq(UInt<1>(0h1), repeater.io.deq.bits.opcode) node _limit_T_3 = mux(_limit_T_2, UInt<2>(0h3), _limit_T_1) node _limit_T_4 = eq(UInt<2>(0h2), repeater.io.deq.bits.opcode) node _limit_T_5 = mux(_limit_T_4, UInt<2>(0h3), _limit_T_3) node _limit_T_6 = eq(UInt<2>(0h3), repeater.io.deq.bits.opcode) node _limit_T_7 = mux(_limit_T_6, UInt<2>(0h3), _limit_T_5) node _limit_T_8 = eq(UInt<3>(0h4), repeater.io.deq.bits.opcode) node _limit_T_9 = mux(_limit_T_8, UInt<2>(0h3), _limit_T_7) node _limit_T_10 = eq(UInt<3>(0h5), repeater.io.deq.bits.opcode) node limit = mux(_limit_T_10, UInt<2>(0h3), _limit_T_9) node _aFrag_T = gt(repeater.io.deq.bits.size, limit) node aFrag = mux(_aFrag_T, limit, repeater.io.deq.bits.size) node _aOrigOH1_T = dshl(UInt<6>(0h3f), repeater.io.deq.bits.size) node _aOrigOH1_T_1 = bits(_aOrigOH1_T, 5, 0) node aOrigOH1 = not(_aOrigOH1_T_1) node _aFragOH1_T = dshl(UInt<3>(0h7), aFrag) node _aFragOH1_T_1 = bits(_aFragOH1_T, 2, 0) node aFragOH1 = not(_aFragOH1_T_1) node _aHasData_opdata_T = bits(repeater.io.deq.bits.opcode, 2, 2) node aHasData = eq(_aHasData_opdata_T, UInt<1>(0h0)) node aMask = mux(aHasData, UInt<1>(0h0), aFragOH1) regreset gennum : UInt<3>, clock, reset, UInt<3>(0h0) node aFirst = eq(gennum, UInt<1>(0h0)) node _old_gennum1_T = shr(aOrigOH1, 3) node _old_gennum1_T_1 = sub(gennum, UInt<1>(0h1)) node _old_gennum1_T_2 = tail(_old_gennum1_T_1, 1) node old_gennum1 = mux(aFirst, _old_gennum1_T, _old_gennum1_T_2) node _new_gennum_T = not(old_gennum1) node _new_gennum_T_1 = shr(aMask, 3) node _new_gennum_T_2 = or(_new_gennum_T, _new_gennum_T_1) node new_gennum = not(_new_gennum_T_2) node _aFragnum_T = shr(old_gennum1, 0) node _aFragnum_T_1 = not(_aFragnum_T) node _aFragnum_T_2 = shr(aFragOH1, 3) node _aFragnum_T_3 = or(_aFragnum_T_1, _aFragnum_T_2) node aFragnum = not(_aFragnum_T_3) node aLast = eq(aFragnum, UInt<1>(0h0)) reg aToggle_r : UInt<1>, clock when aFirst : connect aToggle_r, dToggle node _aToggle_T = mux(aFirst, dToggle, aToggle_r) node aToggle = eq(_aToggle_T, UInt<1>(0h0)) node _T_8 = and(anonOut.a.ready, anonOut.a.valid) when _T_8 : connect gennum, new_gennum node _repeater_io_repeat_T = eq(aHasData, UInt<1>(0h0)) node _repeater_io_repeat_T_1 = neq(aFragnum, UInt<1>(0h0)) node _repeater_io_repeat_T_2 = and(_repeater_io_repeat_T, _repeater_io_repeat_T_1) connect repeater.io.repeat, _repeater_io_repeat_T_2 connect anonOut.a.bits, repeater.io.deq.bits connect anonOut.a.valid, repeater.io.deq.valid connect repeater.io.deq.ready, anonOut.a.ready node _anonOut_a_bits_address_T = shl(old_gennum1, 3) node _anonOut_a_bits_address_T_1 = not(aOrigOH1) node _anonOut_a_bits_address_T_2 = or(_anonOut_a_bits_address_T, _anonOut_a_bits_address_T_1) node _anonOut_a_bits_address_T_3 = or(_anonOut_a_bits_address_T_2, aFragOH1) node _anonOut_a_bits_address_T_4 = or(_anonOut_a_bits_address_T_3, UInt<3>(0h7)) node _anonOut_a_bits_address_T_5 = not(_anonOut_a_bits_address_T_4) node _anonOut_a_bits_address_T_6 = or(repeater.io.deq.bits.address, _anonOut_a_bits_address_T_5) connect anonOut.a.bits.address, _anonOut_a_bits_address_T_6 node anonOut_a_bits_source_hi = cat(repeater.io.deq.bits.source, aToggle) node _anonOut_a_bits_source_T = cat(anonOut_a_bits_source_hi, aFragnum) connect anonOut.a.bits.source, _anonOut_a_bits_source_T connect anonOut.a.bits.size, aFrag node _T_9 = eq(repeater.io.full, UInt<1>(0h0)) node _T_10 = eq(aHasData, UInt<1>(0h0)) node _T_11 = or(_T_9, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:321 assert (!repeater.io.full || !aHasData)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 connect anonOut.a.bits.data, anonIn.a.bits.data node _T_15 = eq(repeater.io.full, UInt<1>(0h0)) node _T_16 = eq(repeater.io.deq.bits.mask, UInt<8>(0hff)) node _T_17 = or(_T_15, _T_16) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Fragmenter.scala:324 assert (!repeater.io.full || in_a.bits.mask === fullMask)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 node _anonOut_a_bits_mask_T = mux(repeater.io.full, UInt<8>(0hff), anonIn.a.bits.mask) connect anonOut.a.bits.mask, _anonOut_a_bits_mask_T wire anonOut_a_bits_user_out : { } wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<28>(0h0) connect _WIRE.bits.source, UInt<8>(0h0) connect _WIRE.bits.size, UInt<3>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<8>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<28>(0h0) connect _WIRE_2.bits.source, UInt<8>(0h0) connect _WIRE_2.bits.size, UInt<3>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<8>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<28>(0h0) connect _WIRE_6.bits.source, UInt<12>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<12>, address : UInt<28>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<28>(0h0) connect _WIRE_8.bits.source, UInt<12>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<12>, address : UInt<28>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_10.bits.sink, UInt<1>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLFragmenter_PLIC( // @[Fragmenter.scala:92:9] input clock, // @[Fragmenter.scala:92:9] input reset, // @[Fragmenter.scala:92:9] output auto_anon_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [27:0] auto_anon_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_anon_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_anon_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_in_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_anon_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_anon_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [1:0] auto_anon_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [11:0] auto_anon_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [27:0] auto_anon_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_anon_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_anon_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_anon_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_anon_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_anon_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_anon_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_anon_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [11:0] auto_anon_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [63:0] auto_anon_out_d_bits_data // @[LazyModuleImp.scala:107:25] ); wire _repeater_io_full; // @[Fragmenter.scala:274:30] wire _repeater_io_enq_ready; // @[Fragmenter.scala:274:30] wire _repeater_io_deq_valid; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_opcode; // @[Fragmenter.scala:274:30] wire [2:0] _repeater_io_deq_bits_size; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_source; // @[Fragmenter.scala:274:30] wire [27:0] _repeater_io_deq_bits_address; // @[Fragmenter.scala:274:30] wire [7:0] _repeater_io_deq_bits_mask; // @[Fragmenter.scala:274:30] reg [2:0] acknum; // @[Fragmenter.scala:201:29] reg [2:0] dOrig; // @[Fragmenter.scala:202:24] reg dToggle; // @[Fragmenter.scala:203:30] wire dFirst = acknum == 3'h0; // @[Fragmenter.scala:201:29, :205:29] wire [5:0] _dsizeOH1_T = 6'h7 << auto_anon_out_d_bits_size; // @[package.scala:243:71] wire [2:0] _GEN = ~(auto_anon_out_d_bits_source[2:0]); // @[package.scala:241:49] wire [2:0] dFirst_size_hi = auto_anon_out_d_bits_source[2:0] & {1'h1, _GEN[2:1]}; // @[OneHot.scala:30:18] wire [2:0] _dFirst_size_T_8 = {1'h0, dFirst_size_hi[2:1]} | ~(_dsizeOH1_T[2:0]) & {_GEN[0], _dsizeOH1_T[2:1]}; // @[OneHot.scala:30:18, :31:18, :32:28] wire [2:0] dFirst_size = {|dFirst_size_hi, |(_dFirst_size_T_8[2:1]), _dFirst_size_T_8[2] | _dFirst_size_T_8[0]}; // @[OneHot.scala:30:18, :31:18, :32:{10,14,28}] wire drop = ~(auto_anon_out_d_bits_opcode[0]) & (|(auto_anon_out_d_bits_source[2:0])); // @[Fragmenter.scala:204:41, :206:30, :234:{20,30}] wire anonOut_d_ready = auto_anon_in_d_ready | drop; // @[Fragmenter.scala:234:30, :235:35] wire anonIn_d_valid = auto_anon_out_d_valid & ~drop; // @[Fragmenter.scala:234:30, :236:{36,39}] wire [2:0] anonIn_d_bits_size = dFirst ? dFirst_size : dOrig; // @[OneHot.scala:32:10] wire [12:0] _aOrigOH1_T = 13'h3F << _repeater_io_deq_bits_size; // @[package.scala:243:71] reg [2:0] gennum; // @[Fragmenter.scala:303:29] wire aFirst = gennum == 3'h0; // @[Fragmenter.scala:303:29, :304:29] wire [2:0] aFragnum = aFirst ? ~(_aOrigOH1_T[5:3]) : gennum - 3'h1; // @[package.scala:243:{46,71,76}] reg aToggle_r; // @[Fragmenter.scala:309:54]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_20 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<5>(0h10)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<5>(0h11)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<5>(0h12)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<5>(0h13)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 3, 0) node _source_ok_T_27 = shr(io.in.a.bits.source, 4) node _source_ok_T_28 = eq(_source_ok_T_27, UInt<1>(0h1)) node _source_ok_T_29 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = leq(source_ok_uncommonBits_4, UInt<4>(0hf)) node _source_ok_T_32 = and(_source_ok_T_30, _source_ok_T_31) node _source_ok_uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 3, 0) node _source_ok_T_33 = shr(io.in.a.bits.source, 4) node _source_ok_T_34 = eq(_source_ok_T_33, UInt<1>(0h0)) node _source_ok_T_35 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_36 = and(_source_ok_T_34, _source_ok_T_35) node _source_ok_T_37 = leq(source_ok_uncommonBits_5, UInt<4>(0hf)) node _source_ok_T_38 = and(_source_ok_T_36, _source_ok_T_37) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE : UInt<1>[11] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_38 connect _source_ok_WIRE[9], _source_ok_T_39 connect _source_ok_WIRE[10], _source_ok_T_40 node _source_ok_T_41 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[2]) node _source_ok_T_43 = or(_source_ok_T_42, _source_ok_WIRE[3]) node _source_ok_T_44 = or(_source_ok_T_43, _source_ok_WIRE[4]) node _source_ok_T_45 = or(_source_ok_T_44, _source_ok_WIRE[5]) node _source_ok_T_46 = or(_source_ok_T_45, _source_ok_WIRE[6]) node _source_ok_T_47 = or(_source_ok_T_46, _source_ok_WIRE[7]) node _source_ok_T_48 = or(_source_ok_T_47, _source_ok_WIRE[8]) node _source_ok_T_49 = or(_source_ok_T_48, _source_ok_WIRE[9]) node source_ok = or(_source_ok_T_49, _source_ok_WIRE[10]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<5>(0h10)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<5>(0h11)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<5>(0h12)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<5>(0h13)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_80 = shr(io.in.a.bits.source, 4) node _T_81 = eq(_T_80, UInt<1>(0h1)) node _T_82 = leq(UInt<1>(0h0), uncommonBits_4) node _T_83 = and(_T_81, _T_82) node _T_84 = leq(uncommonBits_4, UInt<4>(0hf)) node _T_85 = and(_T_83, _T_84) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_93 = shr(io.in.a.bits.source, 4) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = leq(UInt<1>(0h0), uncommonBits_5) node _T_96 = and(_T_94, _T_95) node _T_97 = leq(uncommonBits_5, UInt<4>(0hf)) node _T_98 = and(_T_96, _T_97) node _T_99 = eq(_T_98, UInt<1>(0h0)) node _T_100 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_101 = cvt(_T_100) node _T_102 = and(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = asSInt(_T_102) node _T_104 = eq(_T_103, asSInt(UInt<1>(0h0))) node _T_105 = or(_T_99, _T_104) node _T_106 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_107 = eq(_T_106, UInt<1>(0h0)) node _T_108 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_109 = cvt(_T_108) node _T_110 = and(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = asSInt(_T_110) node _T_112 = eq(_T_111, asSInt(UInt<1>(0h0))) node _T_113 = or(_T_107, _T_112) node _T_114 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_115 = eq(_T_114, UInt<1>(0h0)) node _T_116 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = or(_T_115, _T_120) node _T_122 = and(_T_11, _T_24) node _T_123 = and(_T_122, _T_37) node _T_124 = and(_T_123, _T_50) node _T_125 = and(_T_124, _T_63) node _T_126 = and(_T_125, _T_71) node _T_127 = and(_T_126, _T_79) node _T_128 = and(_T_127, _T_92) node _T_129 = and(_T_128, _T_105) node _T_130 = and(_T_129, _T_113) node _T_131 = and(_T_130, _T_121) node _T_132 = asUInt(reset) node _T_133 = eq(_T_132, UInt<1>(0h0)) when _T_133 : node _T_134 = eq(_T_131, UInt<1>(0h0)) when _T_134 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_131, UInt<1>(0h1), "") : assert_1 node _T_135 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_135 : node _T_136 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_137 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_138 = and(_T_136, _T_137) node _T_139 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_140 = shr(io.in.a.bits.source, 2) node _T_141 = eq(_T_140, UInt<5>(0h10)) node _T_142 = leq(UInt<1>(0h0), uncommonBits_6) node _T_143 = and(_T_141, _T_142) node _T_144 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_145 = and(_T_143, _T_144) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_146 = shr(io.in.a.bits.source, 2) node _T_147 = eq(_T_146, UInt<5>(0h11)) node _T_148 = leq(UInt<1>(0h0), uncommonBits_7) node _T_149 = and(_T_147, _T_148) node _T_150 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_151 = and(_T_149, _T_150) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_152 = shr(io.in.a.bits.source, 2) node _T_153 = eq(_T_152, UInt<5>(0h12)) node _T_154 = leq(UInt<1>(0h0), uncommonBits_8) node _T_155 = and(_T_153, _T_154) node _T_156 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_157 = and(_T_155, _T_156) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_158 = shr(io.in.a.bits.source, 2) node _T_159 = eq(_T_158, UInt<5>(0h13)) node _T_160 = leq(UInt<1>(0h0), uncommonBits_9) node _T_161 = and(_T_159, _T_160) node _T_162 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_163 = and(_T_161, _T_162) node _T_164 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_165 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_166 = shr(io.in.a.bits.source, 4) node _T_167 = eq(_T_166, UInt<1>(0h1)) node _T_168 = leq(UInt<1>(0h0), uncommonBits_10) node _T_169 = and(_T_167, _T_168) node _T_170 = leq(uncommonBits_10, UInt<4>(0hf)) node _T_171 = and(_T_169, _T_170) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_172 = shr(io.in.a.bits.source, 4) node _T_173 = eq(_T_172, UInt<1>(0h0)) node _T_174 = leq(UInt<1>(0h0), uncommonBits_11) node _T_175 = and(_T_173, _T_174) node _T_176 = leq(uncommonBits_11, UInt<4>(0hf)) node _T_177 = and(_T_175, _T_176) node _T_178 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_179 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_180 = or(_T_139, _T_145) node _T_181 = or(_T_180, _T_151) node _T_182 = or(_T_181, _T_157) node _T_183 = or(_T_182, _T_163) node _T_184 = or(_T_183, _T_164) node _T_185 = or(_T_184, _T_165) node _T_186 = or(_T_185, _T_171) node _T_187 = or(_T_186, _T_177) node _T_188 = or(_T_187, _T_178) node _T_189 = or(_T_188, _T_179) node _T_190 = and(_T_138, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_193 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_194 = cvt(_T_193) node _T_195 = and(_T_194, asSInt(UInt<14>(0h2000))) node _T_196 = asSInt(_T_195) node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0))) node _T_198 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_199 = cvt(_T_198) node _T_200 = and(_T_199, asSInt(UInt<13>(0h1000))) node _T_201 = asSInt(_T_200) node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0))) node _T_203 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<17>(0h10000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<18>(0h2f000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<17>(0h10000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<13>(0h1000))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_224 = cvt(_T_223) node _T_225 = and(_T_224, asSInt(UInt<27>(0h4000000))) node _T_226 = asSInt(_T_225) node _T_227 = eq(_T_226, asSInt(UInt<1>(0h0))) node _T_228 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_229 = cvt(_T_228) node _T_230 = and(_T_229, asSInt(UInt<13>(0h1000))) node _T_231 = asSInt(_T_230) node _T_232 = eq(_T_231, asSInt(UInt<1>(0h0))) node _T_233 = or(_T_197, _T_202) node _T_234 = or(_T_233, _T_207) node _T_235 = or(_T_234, _T_212) node _T_236 = or(_T_235, _T_217) node _T_237 = or(_T_236, _T_222) node _T_238 = or(_T_237, _T_227) node _T_239 = or(_T_238, _T_232) node _T_240 = and(_T_192, _T_239) node _T_241 = or(UInt<1>(0h0), _T_240) node _T_242 = and(_T_191, _T_241) node _T_243 = asUInt(reset) node _T_244 = eq(_T_243, UInt<1>(0h0)) when _T_244 : node _T_245 = eq(_T_242, UInt<1>(0h0)) when _T_245 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_242, UInt<1>(0h1), "") : assert_2 node _T_246 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_247 = shr(io.in.a.bits.source, 2) node _T_248 = eq(_T_247, UInt<5>(0h10)) node _T_249 = leq(UInt<1>(0h0), uncommonBits_12) node _T_250 = and(_T_248, _T_249) node _T_251 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_252 = and(_T_250, _T_251) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_253 = shr(io.in.a.bits.source, 2) node _T_254 = eq(_T_253, UInt<5>(0h11)) node _T_255 = leq(UInt<1>(0h0), uncommonBits_13) node _T_256 = and(_T_254, _T_255) node _T_257 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_258 = and(_T_256, _T_257) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_259 = shr(io.in.a.bits.source, 2) node _T_260 = eq(_T_259, UInt<5>(0h12)) node _T_261 = leq(UInt<1>(0h0), uncommonBits_14) node _T_262 = and(_T_260, _T_261) node _T_263 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_264 = and(_T_262, _T_263) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_265 = shr(io.in.a.bits.source, 2) node _T_266 = eq(_T_265, UInt<5>(0h13)) node _T_267 = leq(UInt<1>(0h0), uncommonBits_15) node _T_268 = and(_T_266, _T_267) node _T_269 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_270 = and(_T_268, _T_269) node _T_271 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_272 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_273 = shr(io.in.a.bits.source, 4) node _T_274 = eq(_T_273, UInt<1>(0h1)) node _T_275 = leq(UInt<1>(0h0), uncommonBits_16) node _T_276 = and(_T_274, _T_275) node _T_277 = leq(uncommonBits_16, UInt<4>(0hf)) node _T_278 = and(_T_276, _T_277) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_279 = shr(io.in.a.bits.source, 4) node _T_280 = eq(_T_279, UInt<1>(0h0)) node _T_281 = leq(UInt<1>(0h0), uncommonBits_17) node _T_282 = and(_T_280, _T_281) node _T_283 = leq(uncommonBits_17, UInt<4>(0hf)) node _T_284 = and(_T_282, _T_283) node _T_285 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_286 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE : UInt<1>[11] connect _WIRE[0], _T_246 connect _WIRE[1], _T_252 connect _WIRE[2], _T_258 connect _WIRE[3], _T_264 connect _WIRE[4], _T_270 connect _WIRE[5], _T_271 connect _WIRE[6], _T_272 connect _WIRE[7], _T_278 connect _WIRE[8], _T_284 connect _WIRE[9], _T_285 connect _WIRE[10], _T_286 node _T_287 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_288 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_289 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_290 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_291 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_292 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_293 = mux(_WIRE[5], _T_287, UInt<1>(0h0)) node _T_294 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_295 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_296 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_297 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_298 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_299 = or(_T_288, _T_289) node _T_300 = or(_T_299, _T_290) node _T_301 = or(_T_300, _T_291) node _T_302 = or(_T_301, _T_292) node _T_303 = or(_T_302, _T_293) node _T_304 = or(_T_303, _T_294) node _T_305 = or(_T_304, _T_295) node _T_306 = or(_T_305, _T_296) node _T_307 = or(_T_306, _T_297) node _T_308 = or(_T_307, _T_298) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_308 node _T_309 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_310 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_311 = and(_T_309, _T_310) node _T_312 = or(UInt<1>(0h0), _T_311) node _T_313 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_314 = cvt(_T_313) node _T_315 = and(_T_314, asSInt(UInt<14>(0h2000))) node _T_316 = asSInt(_T_315) node _T_317 = eq(_T_316, asSInt(UInt<1>(0h0))) node _T_318 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_319 = cvt(_T_318) node _T_320 = and(_T_319, asSInt(UInt<13>(0h1000))) node _T_321 = asSInt(_T_320) node _T_322 = eq(_T_321, asSInt(UInt<1>(0h0))) node _T_323 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_324 = cvt(_T_323) node _T_325 = and(_T_324, asSInt(UInt<17>(0h10000))) node _T_326 = asSInt(_T_325) node _T_327 = eq(_T_326, asSInt(UInt<1>(0h0))) node _T_328 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_329 = cvt(_T_328) node _T_330 = and(_T_329, asSInt(UInt<18>(0h2f000))) node _T_331 = asSInt(_T_330) node _T_332 = eq(_T_331, asSInt(UInt<1>(0h0))) node _T_333 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_334 = cvt(_T_333) node _T_335 = and(_T_334, asSInt(UInt<17>(0h10000))) node _T_336 = asSInt(_T_335) node _T_337 = eq(_T_336, asSInt(UInt<1>(0h0))) node _T_338 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_339 = cvt(_T_338) node _T_340 = and(_T_339, asSInt(UInt<13>(0h1000))) node _T_341 = asSInt(_T_340) node _T_342 = eq(_T_341, asSInt(UInt<1>(0h0))) node _T_343 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_344 = cvt(_T_343) node _T_345 = and(_T_344, asSInt(UInt<27>(0h4000000))) node _T_346 = asSInt(_T_345) node _T_347 = eq(_T_346, asSInt(UInt<1>(0h0))) node _T_348 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_349 = cvt(_T_348) node _T_350 = and(_T_349, asSInt(UInt<13>(0h1000))) node _T_351 = asSInt(_T_350) node _T_352 = eq(_T_351, asSInt(UInt<1>(0h0))) node _T_353 = or(_T_317, _T_322) node _T_354 = or(_T_353, _T_327) node _T_355 = or(_T_354, _T_332) node _T_356 = or(_T_355, _T_337) node _T_357 = or(_T_356, _T_342) node _T_358 = or(_T_357, _T_347) node _T_359 = or(_T_358, _T_352) node _T_360 = and(_T_312, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = and(_WIRE_1, _T_361) node _T_363 = asUInt(reset) node _T_364 = eq(_T_363, UInt<1>(0h0)) when _T_364 : node _T_365 = eq(_T_362, UInt<1>(0h0)) when _T_365 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_362, UInt<1>(0h1), "") : assert_3 node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(source_ok, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_369 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_369, UInt<1>(0h1), "") : assert_5 node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(is_aligned, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_376 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_377 = asUInt(reset) node _T_378 = eq(_T_377, UInt<1>(0h0)) when _T_378 : node _T_379 = eq(_T_376, UInt<1>(0h0)) when _T_379 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_376, UInt<1>(0h1), "") : assert_7 node _T_380 = not(io.in.a.bits.mask) node _T_381 = eq(_T_380, UInt<1>(0h0)) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_381, UInt<1>(0h1), "") : assert_8 node _T_385 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_385, UInt<1>(0h1), "") : assert_9 node _T_389 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_389 : node _T_390 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_391 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_392 = and(_T_390, _T_391) node _T_393 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_394 = shr(io.in.a.bits.source, 2) node _T_395 = eq(_T_394, UInt<5>(0h10)) node _T_396 = leq(UInt<1>(0h0), uncommonBits_18) node _T_397 = and(_T_395, _T_396) node _T_398 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_399 = and(_T_397, _T_398) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_400 = shr(io.in.a.bits.source, 2) node _T_401 = eq(_T_400, UInt<5>(0h11)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_19) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_406 = shr(io.in.a.bits.source, 2) node _T_407 = eq(_T_406, UInt<5>(0h12)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_20) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_412 = shr(io.in.a.bits.source, 2) node _T_413 = eq(_T_412, UInt<5>(0h13)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_21) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_419 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 3, 0) node _T_420 = shr(io.in.a.bits.source, 4) node _T_421 = eq(_T_420, UInt<1>(0h1)) node _T_422 = leq(UInt<1>(0h0), uncommonBits_22) node _T_423 = and(_T_421, _T_422) node _T_424 = leq(uncommonBits_22, UInt<4>(0hf)) node _T_425 = and(_T_423, _T_424) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 3, 0) node _T_426 = shr(io.in.a.bits.source, 4) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = leq(UInt<1>(0h0), uncommonBits_23) node _T_429 = and(_T_427, _T_428) node _T_430 = leq(uncommonBits_23, UInt<4>(0hf)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_433 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_434 = or(_T_393, _T_399) node _T_435 = or(_T_434, _T_405) node _T_436 = or(_T_435, _T_411) node _T_437 = or(_T_436, _T_417) node _T_438 = or(_T_437, _T_418) node _T_439 = or(_T_438, _T_419) node _T_440 = or(_T_439, _T_425) node _T_441 = or(_T_440, _T_431) node _T_442 = or(_T_441, _T_432) node _T_443 = or(_T_442, _T_433) node _T_444 = and(_T_392, _T_443) node _T_445 = or(UInt<1>(0h0), _T_444) node _T_446 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_447 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<14>(0h2000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<13>(0h1000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<17>(0h10000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<18>(0h2f000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<17>(0h10000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<27>(0h4000000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_483 = cvt(_T_482) node _T_484 = and(_T_483, asSInt(UInt<13>(0h1000))) node _T_485 = asSInt(_T_484) node _T_486 = eq(_T_485, asSInt(UInt<1>(0h0))) node _T_487 = or(_T_451, _T_456) node _T_488 = or(_T_487, _T_461) node _T_489 = or(_T_488, _T_466) node _T_490 = or(_T_489, _T_471) node _T_491 = or(_T_490, _T_476) node _T_492 = or(_T_491, _T_481) node _T_493 = or(_T_492, _T_486) node _T_494 = and(_T_446, _T_493) node _T_495 = or(UInt<1>(0h0), _T_494) node _T_496 = and(_T_445, _T_495) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_496, UInt<1>(0h1), "") : assert_10 node _T_500 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_501 = shr(io.in.a.bits.source, 2) node _T_502 = eq(_T_501, UInt<5>(0h10)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_24) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_507 = shr(io.in.a.bits.source, 2) node _T_508 = eq(_T_507, UInt<5>(0h11)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_25) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_512 = and(_T_510, _T_511) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_513 = shr(io.in.a.bits.source, 2) node _T_514 = eq(_T_513, UInt<5>(0h12)) node _T_515 = leq(UInt<1>(0h0), uncommonBits_26) node _T_516 = and(_T_514, _T_515) node _T_517 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_518 = and(_T_516, _T_517) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_519 = shr(io.in.a.bits.source, 2) node _T_520 = eq(_T_519, UInt<5>(0h13)) node _T_521 = leq(UInt<1>(0h0), uncommonBits_27) node _T_522 = and(_T_520, _T_521) node _T_523 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_524 = and(_T_522, _T_523) node _T_525 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_526 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 3, 0) node _T_527 = shr(io.in.a.bits.source, 4) node _T_528 = eq(_T_527, UInt<1>(0h1)) node _T_529 = leq(UInt<1>(0h0), uncommonBits_28) node _T_530 = and(_T_528, _T_529) node _T_531 = leq(uncommonBits_28, UInt<4>(0hf)) node _T_532 = and(_T_530, _T_531) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 3, 0) node _T_533 = shr(io.in.a.bits.source, 4) node _T_534 = eq(_T_533, UInt<1>(0h0)) node _T_535 = leq(UInt<1>(0h0), uncommonBits_29) node _T_536 = and(_T_534, _T_535) node _T_537 = leq(uncommonBits_29, UInt<4>(0hf)) node _T_538 = and(_T_536, _T_537) node _T_539 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_540 = eq(io.in.a.bits.source, UInt<8>(0h80)) wire _WIRE_2 : UInt<1>[11] connect _WIRE_2[0], _T_500 connect _WIRE_2[1], _T_506 connect _WIRE_2[2], _T_512 connect _WIRE_2[3], _T_518 connect _WIRE_2[4], _T_524 connect _WIRE_2[5], _T_525 connect _WIRE_2[6], _T_526 connect _WIRE_2[7], _T_532 connect _WIRE_2[8], _T_538 connect _WIRE_2[9], _T_539 connect _WIRE_2[10], _T_540 node _T_541 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_542 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_543 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_544 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_545 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_546 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_547 = mux(_WIRE_2[5], _T_541, UInt<1>(0h0)) node _T_548 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_549 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_550 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_551 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_552 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_553 = or(_T_542, _T_543) node _T_554 = or(_T_553, _T_544) node _T_555 = or(_T_554, _T_545) node _T_556 = or(_T_555, _T_546) node _T_557 = or(_T_556, _T_547) node _T_558 = or(_T_557, _T_548) node _T_559 = or(_T_558, _T_549) node _T_560 = or(_T_559, _T_550) node _T_561 = or(_T_560, _T_551) node _T_562 = or(_T_561, _T_552) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_562 node _T_563 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_564 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_565 = and(_T_563, _T_564) node _T_566 = or(UInt<1>(0h0), _T_565) node _T_567 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_568 = cvt(_T_567) node _T_569 = and(_T_568, asSInt(UInt<14>(0h2000))) node _T_570 = asSInt(_T_569) node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0))) node _T_572 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_573 = cvt(_T_572) node _T_574 = and(_T_573, asSInt(UInt<13>(0h1000))) node _T_575 = asSInt(_T_574) node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) node _T_577 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_578 = cvt(_T_577) node _T_579 = and(_T_578, asSInt(UInt<17>(0h10000))) node _T_580 = asSInt(_T_579) node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0))) node _T_582 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_583 = cvt(_T_582) node _T_584 = and(_T_583, asSInt(UInt<18>(0h2f000))) node _T_585 = asSInt(_T_584) node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0))) node _T_587 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_588 = cvt(_T_587) node _T_589 = and(_T_588, asSInt(UInt<17>(0h10000))) node _T_590 = asSInt(_T_589) node _T_591 = eq(_T_590, asSInt(UInt<1>(0h0))) node _T_592 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_593 = cvt(_T_592) node _T_594 = and(_T_593, asSInt(UInt<13>(0h1000))) node _T_595 = asSInt(_T_594) node _T_596 = eq(_T_595, asSInt(UInt<1>(0h0))) node _T_597 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_598 = cvt(_T_597) node _T_599 = and(_T_598, asSInt(UInt<27>(0h4000000))) node _T_600 = asSInt(_T_599) node _T_601 = eq(_T_600, asSInt(UInt<1>(0h0))) node _T_602 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_603 = cvt(_T_602) node _T_604 = and(_T_603, asSInt(UInt<13>(0h1000))) node _T_605 = asSInt(_T_604) node _T_606 = eq(_T_605, asSInt(UInt<1>(0h0))) node _T_607 = or(_T_571, _T_576) node _T_608 = or(_T_607, _T_581) node _T_609 = or(_T_608, _T_586) node _T_610 = or(_T_609, _T_591) node _T_611 = or(_T_610, _T_596) node _T_612 = or(_T_611, _T_601) node _T_613 = or(_T_612, _T_606) node _T_614 = and(_T_566, _T_613) node _T_615 = or(UInt<1>(0h0), _T_614) node _T_616 = and(_WIRE_3, _T_615) node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(_T_616, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_616, UInt<1>(0h1), "") : assert_11 node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(source_ok, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_623 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_623, UInt<1>(0h1), "") : assert_13 node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(is_aligned, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_630 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_630, UInt<1>(0h1), "") : assert_15 node _T_634 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_635 = asUInt(reset) node _T_636 = eq(_T_635, UInt<1>(0h0)) when _T_636 : node _T_637 = eq(_T_634, UInt<1>(0h0)) when _T_637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_634, UInt<1>(0h1), "") : assert_16 node _T_638 = not(io.in.a.bits.mask) node _T_639 = eq(_T_638, UInt<1>(0h0)) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_639, UInt<1>(0h1), "") : assert_17 node _T_643 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(_T_643, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_643, UInt<1>(0h1), "") : assert_18 node _T_647 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_647 : node _T_648 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_649 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_650 = and(_T_648, _T_649) node _T_651 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_652 = shr(io.in.a.bits.source, 2) node _T_653 = eq(_T_652, UInt<5>(0h10)) node _T_654 = leq(UInt<1>(0h0), uncommonBits_30) node _T_655 = and(_T_653, _T_654) node _T_656 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_657 = and(_T_655, _T_656) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_658 = shr(io.in.a.bits.source, 2) node _T_659 = eq(_T_658, UInt<5>(0h11)) node _T_660 = leq(UInt<1>(0h0), uncommonBits_31) node _T_661 = and(_T_659, _T_660) node _T_662 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_663 = and(_T_661, _T_662) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_664 = shr(io.in.a.bits.source, 2) node _T_665 = eq(_T_664, UInt<5>(0h12)) node _T_666 = leq(UInt<1>(0h0), uncommonBits_32) node _T_667 = and(_T_665, _T_666) node _T_668 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_669 = and(_T_667, _T_668) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_670 = shr(io.in.a.bits.source, 2) node _T_671 = eq(_T_670, UInt<5>(0h13)) node _T_672 = leq(UInt<1>(0h0), uncommonBits_33) node _T_673 = and(_T_671, _T_672) node _T_674 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_675 = and(_T_673, _T_674) node _T_676 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_677 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 3, 0) node _T_678 = shr(io.in.a.bits.source, 4) node _T_679 = eq(_T_678, UInt<1>(0h1)) node _T_680 = leq(UInt<1>(0h0), uncommonBits_34) node _T_681 = and(_T_679, _T_680) node _T_682 = leq(uncommonBits_34, UInt<4>(0hf)) node _T_683 = and(_T_681, _T_682) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 3, 0) node _T_684 = shr(io.in.a.bits.source, 4) node _T_685 = eq(_T_684, UInt<1>(0h0)) node _T_686 = leq(UInt<1>(0h0), uncommonBits_35) node _T_687 = and(_T_685, _T_686) node _T_688 = leq(uncommonBits_35, UInt<4>(0hf)) node _T_689 = and(_T_687, _T_688) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_691 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_692 = or(_T_651, _T_657) node _T_693 = or(_T_692, _T_663) node _T_694 = or(_T_693, _T_669) node _T_695 = or(_T_694, _T_675) node _T_696 = or(_T_695, _T_676) node _T_697 = or(_T_696, _T_677) node _T_698 = or(_T_697, _T_683) node _T_699 = or(_T_698, _T_689) node _T_700 = or(_T_699, _T_690) node _T_701 = or(_T_700, _T_691) node _T_702 = and(_T_650, _T_701) node _T_703 = or(UInt<1>(0h0), _T_702) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_703, UInt<1>(0h1), "") : assert_19 node _T_707 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_708 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_709 = and(_T_707, _T_708) node _T_710 = or(UInt<1>(0h0), _T_709) node _T_711 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_712 = cvt(_T_711) node _T_713 = and(_T_712, asSInt(UInt<13>(0h1000))) node _T_714 = asSInt(_T_713) node _T_715 = eq(_T_714, asSInt(UInt<1>(0h0))) node _T_716 = and(_T_710, _T_715) node _T_717 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_718 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_719 = and(_T_717, _T_718) node _T_720 = or(UInt<1>(0h0), _T_719) node _T_721 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_722 = cvt(_T_721) node _T_723 = and(_T_722, asSInt(UInt<14>(0h2000))) node _T_724 = asSInt(_T_723) node _T_725 = eq(_T_724, asSInt(UInt<1>(0h0))) node _T_726 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_727 = cvt(_T_726) node _T_728 = and(_T_727, asSInt(UInt<17>(0h10000))) node _T_729 = asSInt(_T_728) node _T_730 = eq(_T_729, asSInt(UInt<1>(0h0))) node _T_731 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<18>(0h2f000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_737 = cvt(_T_736) node _T_738 = and(_T_737, asSInt(UInt<17>(0h10000))) node _T_739 = asSInt(_T_738) node _T_740 = eq(_T_739, asSInt(UInt<1>(0h0))) node _T_741 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_747 = cvt(_T_746) node _T_748 = and(_T_747, asSInt(UInt<27>(0h4000000))) node _T_749 = asSInt(_T_748) node _T_750 = eq(_T_749, asSInt(UInt<1>(0h0))) node _T_751 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<13>(0h1000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = or(_T_725, _T_730) node _T_757 = or(_T_756, _T_735) node _T_758 = or(_T_757, _T_740) node _T_759 = or(_T_758, _T_745) node _T_760 = or(_T_759, _T_750) node _T_761 = or(_T_760, _T_755) node _T_762 = and(_T_720, _T_761) node _T_763 = or(UInt<1>(0h0), _T_716) node _T_764 = or(_T_763, _T_762) node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_T_764, UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_764, UInt<1>(0h1), "") : assert_20 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(source_ok, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(is_aligned, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_774 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(_T_774, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_774, UInt<1>(0h1), "") : assert_23 node _T_778 = eq(io.in.a.bits.mask, mask) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_778, UInt<1>(0h1), "") : assert_24 node _T_782 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_783 = asUInt(reset) node _T_784 = eq(_T_783, UInt<1>(0h0)) when _T_784 : node _T_785 = eq(_T_782, UInt<1>(0h0)) when _T_785 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_782, UInt<1>(0h1), "") : assert_25 node _T_786 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_786 : node _T_787 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_788 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_789 = and(_T_787, _T_788) node _T_790 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_791 = shr(io.in.a.bits.source, 2) node _T_792 = eq(_T_791, UInt<5>(0h10)) node _T_793 = leq(UInt<1>(0h0), uncommonBits_36) node _T_794 = and(_T_792, _T_793) node _T_795 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_796 = and(_T_794, _T_795) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_797 = shr(io.in.a.bits.source, 2) node _T_798 = eq(_T_797, UInt<5>(0h11)) node _T_799 = leq(UInt<1>(0h0), uncommonBits_37) node _T_800 = and(_T_798, _T_799) node _T_801 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_802 = and(_T_800, _T_801) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_803 = shr(io.in.a.bits.source, 2) node _T_804 = eq(_T_803, UInt<5>(0h12)) node _T_805 = leq(UInt<1>(0h0), uncommonBits_38) node _T_806 = and(_T_804, _T_805) node _T_807 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_808 = and(_T_806, _T_807) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_809 = shr(io.in.a.bits.source, 2) node _T_810 = eq(_T_809, UInt<5>(0h13)) node _T_811 = leq(UInt<1>(0h0), uncommonBits_39) node _T_812 = and(_T_810, _T_811) node _T_813 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_814 = and(_T_812, _T_813) node _T_815 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_816 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 3, 0) node _T_817 = shr(io.in.a.bits.source, 4) node _T_818 = eq(_T_817, UInt<1>(0h1)) node _T_819 = leq(UInt<1>(0h0), uncommonBits_40) node _T_820 = and(_T_818, _T_819) node _T_821 = leq(uncommonBits_40, UInt<4>(0hf)) node _T_822 = and(_T_820, _T_821) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 3, 0) node _T_823 = shr(io.in.a.bits.source, 4) node _T_824 = eq(_T_823, UInt<1>(0h0)) node _T_825 = leq(UInt<1>(0h0), uncommonBits_41) node _T_826 = and(_T_824, _T_825) node _T_827 = leq(uncommonBits_41, UInt<4>(0hf)) node _T_828 = and(_T_826, _T_827) node _T_829 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_830 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_831 = or(_T_790, _T_796) node _T_832 = or(_T_831, _T_802) node _T_833 = or(_T_832, _T_808) node _T_834 = or(_T_833, _T_814) node _T_835 = or(_T_834, _T_815) node _T_836 = or(_T_835, _T_816) node _T_837 = or(_T_836, _T_822) node _T_838 = or(_T_837, _T_828) node _T_839 = or(_T_838, _T_829) node _T_840 = or(_T_839, _T_830) node _T_841 = and(_T_789, _T_840) node _T_842 = or(UInt<1>(0h0), _T_841) node _T_843 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_844 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_848 = cvt(_T_847) node _T_849 = and(_T_848, asSInt(UInt<13>(0h1000))) node _T_850 = asSInt(_T_849) node _T_851 = eq(_T_850, asSInt(UInt<1>(0h0))) node _T_852 = and(_T_846, _T_851) node _T_853 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_854 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(UInt<1>(0h0), _T_855) node _T_857 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_858 = cvt(_T_857) node _T_859 = and(_T_858, asSInt(UInt<14>(0h2000))) node _T_860 = asSInt(_T_859) node _T_861 = eq(_T_860, asSInt(UInt<1>(0h0))) node _T_862 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_863 = cvt(_T_862) node _T_864 = and(_T_863, asSInt(UInt<18>(0h2f000))) node _T_865 = asSInt(_T_864) node _T_866 = eq(_T_865, asSInt(UInt<1>(0h0))) node _T_867 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_868 = cvt(_T_867) node _T_869 = and(_T_868, asSInt(UInt<17>(0h10000))) node _T_870 = asSInt(_T_869) node _T_871 = eq(_T_870, asSInt(UInt<1>(0h0))) node _T_872 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_873 = cvt(_T_872) node _T_874 = and(_T_873, asSInt(UInt<13>(0h1000))) node _T_875 = asSInt(_T_874) node _T_876 = eq(_T_875, asSInt(UInt<1>(0h0))) node _T_877 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_878 = cvt(_T_877) node _T_879 = and(_T_878, asSInt(UInt<27>(0h4000000))) node _T_880 = asSInt(_T_879) node _T_881 = eq(_T_880, asSInt(UInt<1>(0h0))) node _T_882 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_883 = cvt(_T_882) node _T_884 = and(_T_883, asSInt(UInt<13>(0h1000))) node _T_885 = asSInt(_T_884) node _T_886 = eq(_T_885, asSInt(UInt<1>(0h0))) node _T_887 = or(_T_861, _T_866) node _T_888 = or(_T_887, _T_871) node _T_889 = or(_T_888, _T_876) node _T_890 = or(_T_889, _T_881) node _T_891 = or(_T_890, _T_886) node _T_892 = and(_T_856, _T_891) node _T_893 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_894 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_895 = cvt(_T_894) node _T_896 = and(_T_895, asSInt(UInt<17>(0h10000))) node _T_897 = asSInt(_T_896) node _T_898 = eq(_T_897, asSInt(UInt<1>(0h0))) node _T_899 = and(_T_893, _T_898) node _T_900 = or(UInt<1>(0h0), _T_852) node _T_901 = or(_T_900, _T_892) node _T_902 = or(_T_901, _T_899) node _T_903 = and(_T_842, _T_902) node _T_904 = asUInt(reset) node _T_905 = eq(_T_904, UInt<1>(0h0)) when _T_905 : node _T_906 = eq(_T_903, UInt<1>(0h0)) when _T_906 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_903, UInt<1>(0h1), "") : assert_26 node _T_907 = asUInt(reset) node _T_908 = eq(_T_907, UInt<1>(0h0)) when _T_908 : node _T_909 = eq(source_ok, UInt<1>(0h0)) when _T_909 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(is_aligned, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_913 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_914 = asUInt(reset) node _T_915 = eq(_T_914, UInt<1>(0h0)) when _T_915 : node _T_916 = eq(_T_913, UInt<1>(0h0)) when _T_916 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_913, UInt<1>(0h1), "") : assert_29 node _T_917 = eq(io.in.a.bits.mask, mask) node _T_918 = asUInt(reset) node _T_919 = eq(_T_918, UInt<1>(0h0)) when _T_919 : node _T_920 = eq(_T_917, UInt<1>(0h0)) when _T_920 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_917, UInt<1>(0h1), "") : assert_30 node _T_921 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_921 : node _T_922 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_923 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_924 = and(_T_922, _T_923) node _T_925 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_926 = shr(io.in.a.bits.source, 2) node _T_927 = eq(_T_926, UInt<5>(0h10)) node _T_928 = leq(UInt<1>(0h0), uncommonBits_42) node _T_929 = and(_T_927, _T_928) node _T_930 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_931 = and(_T_929, _T_930) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_932 = shr(io.in.a.bits.source, 2) node _T_933 = eq(_T_932, UInt<5>(0h11)) node _T_934 = leq(UInt<1>(0h0), uncommonBits_43) node _T_935 = and(_T_933, _T_934) node _T_936 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_937 = and(_T_935, _T_936) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 1, 0) node _T_938 = shr(io.in.a.bits.source, 2) node _T_939 = eq(_T_938, UInt<5>(0h12)) node _T_940 = leq(UInt<1>(0h0), uncommonBits_44) node _T_941 = and(_T_939, _T_940) node _T_942 = leq(uncommonBits_44, UInt<2>(0h3)) node _T_943 = and(_T_941, _T_942) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_944 = shr(io.in.a.bits.source, 2) node _T_945 = eq(_T_944, UInt<5>(0h13)) node _T_946 = leq(UInt<1>(0h0), uncommonBits_45) node _T_947 = and(_T_945, _T_946) node _T_948 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_949 = and(_T_947, _T_948) node _T_950 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_951 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 3, 0) node _T_952 = shr(io.in.a.bits.source, 4) node _T_953 = eq(_T_952, UInt<1>(0h1)) node _T_954 = leq(UInt<1>(0h0), uncommonBits_46) node _T_955 = and(_T_953, _T_954) node _T_956 = leq(uncommonBits_46, UInt<4>(0hf)) node _T_957 = and(_T_955, _T_956) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 3, 0) node _T_958 = shr(io.in.a.bits.source, 4) node _T_959 = eq(_T_958, UInt<1>(0h0)) node _T_960 = leq(UInt<1>(0h0), uncommonBits_47) node _T_961 = and(_T_959, _T_960) node _T_962 = leq(uncommonBits_47, UInt<4>(0hf)) node _T_963 = and(_T_961, _T_962) node _T_964 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_965 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_966 = or(_T_925, _T_931) node _T_967 = or(_T_966, _T_937) node _T_968 = or(_T_967, _T_943) node _T_969 = or(_T_968, _T_949) node _T_970 = or(_T_969, _T_950) node _T_971 = or(_T_970, _T_951) node _T_972 = or(_T_971, _T_957) node _T_973 = or(_T_972, _T_963) node _T_974 = or(_T_973, _T_964) node _T_975 = or(_T_974, _T_965) node _T_976 = and(_T_924, _T_975) node _T_977 = or(UInt<1>(0h0), _T_976) node _T_978 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_979 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_980 = and(_T_978, _T_979) node _T_981 = or(UInt<1>(0h0), _T_980) node _T_982 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<13>(0h1000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = and(_T_981, _T_986) node _T_988 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_989 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_990 = and(_T_988, _T_989) node _T_991 = or(UInt<1>(0h0), _T_990) node _T_992 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<14>(0h2000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<18>(0h2f000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<17>(0h10000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1008 = cvt(_T_1007) node _T_1009 = and(_T_1008, asSInt(UInt<13>(0h1000))) node _T_1010 = asSInt(_T_1009) node _T_1011 = eq(_T_1010, asSInt(UInt<1>(0h0))) node _T_1012 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1013 = cvt(_T_1012) node _T_1014 = and(_T_1013, asSInt(UInt<27>(0h4000000))) node _T_1015 = asSInt(_T_1014) node _T_1016 = eq(_T_1015, asSInt(UInt<1>(0h0))) node _T_1017 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1018 = cvt(_T_1017) node _T_1019 = and(_T_1018, asSInt(UInt<13>(0h1000))) node _T_1020 = asSInt(_T_1019) node _T_1021 = eq(_T_1020, asSInt(UInt<1>(0h0))) node _T_1022 = or(_T_996, _T_1001) node _T_1023 = or(_T_1022, _T_1006) node _T_1024 = or(_T_1023, _T_1011) node _T_1025 = or(_T_1024, _T_1016) node _T_1026 = or(_T_1025, _T_1021) node _T_1027 = and(_T_991, _T_1026) node _T_1028 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1029 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1030 = cvt(_T_1029) node _T_1031 = and(_T_1030, asSInt(UInt<17>(0h10000))) node _T_1032 = asSInt(_T_1031) node _T_1033 = eq(_T_1032, asSInt(UInt<1>(0h0))) node _T_1034 = and(_T_1028, _T_1033) node _T_1035 = or(UInt<1>(0h0), _T_987) node _T_1036 = or(_T_1035, _T_1027) node _T_1037 = or(_T_1036, _T_1034) node _T_1038 = and(_T_977, _T_1037) node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_T_1038, UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1038, UInt<1>(0h1), "") : assert_31 node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(source_ok, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(is_aligned, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1048 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_34 node _T_1052 = not(mask) node _T_1053 = and(io.in.a.bits.mask, _T_1052) node _T_1054 = eq(_T_1053, UInt<1>(0h0)) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_35 node _T_1058 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1058 : node _T_1059 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1060 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1061 = and(_T_1059, _T_1060) node _T_1062 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_1063 = shr(io.in.a.bits.source, 2) node _T_1064 = eq(_T_1063, UInt<5>(0h10)) node _T_1065 = leq(UInt<1>(0h0), uncommonBits_48) node _T_1066 = and(_T_1064, _T_1065) node _T_1067 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_1068 = and(_T_1066, _T_1067) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 1, 0) node _T_1069 = shr(io.in.a.bits.source, 2) node _T_1070 = eq(_T_1069, UInt<5>(0h11)) node _T_1071 = leq(UInt<1>(0h0), uncommonBits_49) node _T_1072 = and(_T_1070, _T_1071) node _T_1073 = leq(uncommonBits_49, UInt<2>(0h3)) node _T_1074 = and(_T_1072, _T_1073) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_1075 = shr(io.in.a.bits.source, 2) node _T_1076 = eq(_T_1075, UInt<5>(0h12)) node _T_1077 = leq(UInt<1>(0h0), uncommonBits_50) node _T_1078 = and(_T_1076, _T_1077) node _T_1079 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_1080 = and(_T_1078, _T_1079) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_1081 = shr(io.in.a.bits.source, 2) node _T_1082 = eq(_T_1081, UInt<5>(0h13)) node _T_1083 = leq(UInt<1>(0h0), uncommonBits_51) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_1086 = and(_T_1084, _T_1085) node _T_1087 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1088 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 3, 0) node _T_1089 = shr(io.in.a.bits.source, 4) node _T_1090 = eq(_T_1089, UInt<1>(0h1)) node _T_1091 = leq(UInt<1>(0h0), uncommonBits_52) node _T_1092 = and(_T_1090, _T_1091) node _T_1093 = leq(uncommonBits_52, UInt<4>(0hf)) node _T_1094 = and(_T_1092, _T_1093) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 3, 0) node _T_1095 = shr(io.in.a.bits.source, 4) node _T_1096 = eq(_T_1095, UInt<1>(0h0)) node _T_1097 = leq(UInt<1>(0h0), uncommonBits_53) node _T_1098 = and(_T_1096, _T_1097) node _T_1099 = leq(uncommonBits_53, UInt<4>(0hf)) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1102 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1103 = or(_T_1062, _T_1068) node _T_1104 = or(_T_1103, _T_1074) node _T_1105 = or(_T_1104, _T_1080) node _T_1106 = or(_T_1105, _T_1086) node _T_1107 = or(_T_1106, _T_1087) node _T_1108 = or(_T_1107, _T_1088) node _T_1109 = or(_T_1108, _T_1094) node _T_1110 = or(_T_1109, _T_1100) node _T_1111 = or(_T_1110, _T_1101) node _T_1112 = or(_T_1111, _T_1102) node _T_1113 = and(_T_1061, _T_1112) node _T_1114 = or(UInt<1>(0h0), _T_1113) node _T_1115 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1116 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1117 = and(_T_1115, _T_1116) node _T_1118 = or(UInt<1>(0h0), _T_1117) node _T_1119 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1120 = cvt(_T_1119) node _T_1121 = and(_T_1120, asSInt(UInt<14>(0h2000))) node _T_1122 = asSInt(_T_1121) node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1125 = cvt(_T_1124) node _T_1126 = and(_T_1125, asSInt(UInt<13>(0h1000))) node _T_1127 = asSInt(_T_1126) node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0))) node _T_1129 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1130 = cvt(_T_1129) node _T_1131 = and(_T_1130, asSInt(UInt<18>(0h2f000))) node _T_1132 = asSInt(_T_1131) node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0))) node _T_1134 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1135 = cvt(_T_1134) node _T_1136 = and(_T_1135, asSInt(UInt<17>(0h10000))) node _T_1137 = asSInt(_T_1136) node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0))) node _T_1139 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1140 = cvt(_T_1139) node _T_1141 = and(_T_1140, asSInt(UInt<13>(0h1000))) node _T_1142 = asSInt(_T_1141) node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<27>(0h4000000))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1150 = cvt(_T_1149) node _T_1151 = and(_T_1150, asSInt(UInt<13>(0h1000))) node _T_1152 = asSInt(_T_1151) node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0))) node _T_1154 = or(_T_1123, _T_1128) node _T_1155 = or(_T_1154, _T_1133) node _T_1156 = or(_T_1155, _T_1138) node _T_1157 = or(_T_1156, _T_1143) node _T_1158 = or(_T_1157, _T_1148) node _T_1159 = or(_T_1158, _T_1153) node _T_1160 = and(_T_1118, _T_1159) node _T_1161 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1162 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1163 = cvt(_T_1162) node _T_1164 = and(_T_1163, asSInt(UInt<17>(0h10000))) node _T_1165 = asSInt(_T_1164) node _T_1166 = eq(_T_1165, asSInt(UInt<1>(0h0))) node _T_1167 = and(_T_1161, _T_1166) node _T_1168 = or(UInt<1>(0h0), _T_1160) node _T_1169 = or(_T_1168, _T_1167) node _T_1170 = and(_T_1114, _T_1169) node _T_1171 = asUInt(reset) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) when _T_1172 : node _T_1173 = eq(_T_1170, UInt<1>(0h0)) when _T_1173 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1170, UInt<1>(0h1), "") : assert_36 node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(source_ok, UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(is_aligned, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1180 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_39 node _T_1184 = eq(io.in.a.bits.mask, mask) node _T_1185 = asUInt(reset) node _T_1186 = eq(_T_1185, UInt<1>(0h0)) when _T_1186 : node _T_1187 = eq(_T_1184, UInt<1>(0h0)) when _T_1187 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1184, UInt<1>(0h1), "") : assert_40 node _T_1188 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1188 : node _T_1189 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1190 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1191 = and(_T_1189, _T_1190) node _T_1192 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 1, 0) node _T_1193 = shr(io.in.a.bits.source, 2) node _T_1194 = eq(_T_1193, UInt<5>(0h10)) node _T_1195 = leq(UInt<1>(0h0), uncommonBits_54) node _T_1196 = and(_T_1194, _T_1195) node _T_1197 = leq(uncommonBits_54, UInt<2>(0h3)) node _T_1198 = and(_T_1196, _T_1197) node _uncommonBits_T_55 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_55 = bits(_uncommonBits_T_55, 1, 0) node _T_1199 = shr(io.in.a.bits.source, 2) node _T_1200 = eq(_T_1199, UInt<5>(0h11)) node _T_1201 = leq(UInt<1>(0h0), uncommonBits_55) node _T_1202 = and(_T_1200, _T_1201) node _T_1203 = leq(uncommonBits_55, UInt<2>(0h3)) node _T_1204 = and(_T_1202, _T_1203) node _uncommonBits_T_56 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_56 = bits(_uncommonBits_T_56, 1, 0) node _T_1205 = shr(io.in.a.bits.source, 2) node _T_1206 = eq(_T_1205, UInt<5>(0h12)) node _T_1207 = leq(UInt<1>(0h0), uncommonBits_56) node _T_1208 = and(_T_1206, _T_1207) node _T_1209 = leq(uncommonBits_56, UInt<2>(0h3)) node _T_1210 = and(_T_1208, _T_1209) node _uncommonBits_T_57 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_57 = bits(_uncommonBits_T_57, 1, 0) node _T_1211 = shr(io.in.a.bits.source, 2) node _T_1212 = eq(_T_1211, UInt<5>(0h13)) node _T_1213 = leq(UInt<1>(0h0), uncommonBits_57) node _T_1214 = and(_T_1212, _T_1213) node _T_1215 = leq(uncommonBits_57, UInt<2>(0h3)) node _T_1216 = and(_T_1214, _T_1215) node _T_1217 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1218 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_58 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_58 = bits(_uncommonBits_T_58, 3, 0) node _T_1219 = shr(io.in.a.bits.source, 4) node _T_1220 = eq(_T_1219, UInt<1>(0h1)) node _T_1221 = leq(UInt<1>(0h0), uncommonBits_58) node _T_1222 = and(_T_1220, _T_1221) node _T_1223 = leq(uncommonBits_58, UInt<4>(0hf)) node _T_1224 = and(_T_1222, _T_1223) node _uncommonBits_T_59 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_59 = bits(_uncommonBits_T_59, 3, 0) node _T_1225 = shr(io.in.a.bits.source, 4) node _T_1226 = eq(_T_1225, UInt<1>(0h0)) node _T_1227 = leq(UInt<1>(0h0), uncommonBits_59) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = leq(uncommonBits_59, UInt<4>(0hf)) node _T_1230 = and(_T_1228, _T_1229) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1232 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1233 = or(_T_1192, _T_1198) node _T_1234 = or(_T_1233, _T_1204) node _T_1235 = or(_T_1234, _T_1210) node _T_1236 = or(_T_1235, _T_1216) node _T_1237 = or(_T_1236, _T_1217) node _T_1238 = or(_T_1237, _T_1218) node _T_1239 = or(_T_1238, _T_1224) node _T_1240 = or(_T_1239, _T_1230) node _T_1241 = or(_T_1240, _T_1231) node _T_1242 = or(_T_1241, _T_1232) node _T_1243 = and(_T_1191, _T_1242) node _T_1244 = or(UInt<1>(0h0), _T_1243) node _T_1245 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1246 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1247 = and(_T_1245, _T_1246) node _T_1248 = or(UInt<1>(0h0), _T_1247) node _T_1249 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1250 = cvt(_T_1249) node _T_1251 = and(_T_1250, asSInt(UInt<14>(0h2000))) node _T_1252 = asSInt(_T_1251) node _T_1253 = eq(_T_1252, asSInt(UInt<1>(0h0))) node _T_1254 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1255 = cvt(_T_1254) node _T_1256 = and(_T_1255, asSInt(UInt<13>(0h1000))) node _T_1257 = asSInt(_T_1256) node _T_1258 = eq(_T_1257, asSInt(UInt<1>(0h0))) node _T_1259 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1260 = cvt(_T_1259) node _T_1261 = and(_T_1260, asSInt(UInt<18>(0h2f000))) node _T_1262 = asSInt(_T_1261) node _T_1263 = eq(_T_1262, asSInt(UInt<1>(0h0))) node _T_1264 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1265 = cvt(_T_1264) node _T_1266 = and(_T_1265, asSInt(UInt<17>(0h10000))) node _T_1267 = asSInt(_T_1266) node _T_1268 = eq(_T_1267, asSInt(UInt<1>(0h0))) node _T_1269 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1270 = cvt(_T_1269) node _T_1271 = and(_T_1270, asSInt(UInt<13>(0h1000))) node _T_1272 = asSInt(_T_1271) node _T_1273 = eq(_T_1272, asSInt(UInt<1>(0h0))) node _T_1274 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1275 = cvt(_T_1274) node _T_1276 = and(_T_1275, asSInt(UInt<27>(0h4000000))) node _T_1277 = asSInt(_T_1276) node _T_1278 = eq(_T_1277, asSInt(UInt<1>(0h0))) node _T_1279 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1280 = cvt(_T_1279) node _T_1281 = and(_T_1280, asSInt(UInt<13>(0h1000))) node _T_1282 = asSInt(_T_1281) node _T_1283 = eq(_T_1282, asSInt(UInt<1>(0h0))) node _T_1284 = or(_T_1253, _T_1258) node _T_1285 = or(_T_1284, _T_1263) node _T_1286 = or(_T_1285, _T_1268) node _T_1287 = or(_T_1286, _T_1273) node _T_1288 = or(_T_1287, _T_1278) node _T_1289 = or(_T_1288, _T_1283) node _T_1290 = and(_T_1248, _T_1289) node _T_1291 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1292 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1293 = cvt(_T_1292) node _T_1294 = and(_T_1293, asSInt(UInt<17>(0h10000))) node _T_1295 = asSInt(_T_1294) node _T_1296 = eq(_T_1295, asSInt(UInt<1>(0h0))) node _T_1297 = and(_T_1291, _T_1296) node _T_1298 = or(UInt<1>(0h0), _T_1290) node _T_1299 = or(_T_1298, _T_1297) node _T_1300 = and(_T_1244, _T_1299) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_41 node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(source_ok, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1307 = asUInt(reset) node _T_1308 = eq(_T_1307, UInt<1>(0h0)) when _T_1308 : node _T_1309 = eq(is_aligned, UInt<1>(0h0)) when _T_1309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1310 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1311 = asUInt(reset) node _T_1312 = eq(_T_1311, UInt<1>(0h0)) when _T_1312 : node _T_1313 = eq(_T_1310, UInt<1>(0h0)) when _T_1313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1310, UInt<1>(0h1), "") : assert_44 node _T_1314 = eq(io.in.a.bits.mask, mask) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_45 node _T_1318 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1318 : node _T_1319 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1320 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1321 = and(_T_1319, _T_1320) node _T_1322 = eq(io.in.a.bits.source, UInt<7>(0h50)) node _uncommonBits_T_60 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_60 = bits(_uncommonBits_T_60, 1, 0) node _T_1323 = shr(io.in.a.bits.source, 2) node _T_1324 = eq(_T_1323, UInt<5>(0h10)) node _T_1325 = leq(UInt<1>(0h0), uncommonBits_60) node _T_1326 = and(_T_1324, _T_1325) node _T_1327 = leq(uncommonBits_60, UInt<2>(0h3)) node _T_1328 = and(_T_1326, _T_1327) node _uncommonBits_T_61 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_61 = bits(_uncommonBits_T_61, 1, 0) node _T_1329 = shr(io.in.a.bits.source, 2) node _T_1330 = eq(_T_1329, UInt<5>(0h11)) node _T_1331 = leq(UInt<1>(0h0), uncommonBits_61) node _T_1332 = and(_T_1330, _T_1331) node _T_1333 = leq(uncommonBits_61, UInt<2>(0h3)) node _T_1334 = and(_T_1332, _T_1333) node _uncommonBits_T_62 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_62 = bits(_uncommonBits_T_62, 1, 0) node _T_1335 = shr(io.in.a.bits.source, 2) node _T_1336 = eq(_T_1335, UInt<5>(0h12)) node _T_1337 = leq(UInt<1>(0h0), uncommonBits_62) node _T_1338 = and(_T_1336, _T_1337) node _T_1339 = leq(uncommonBits_62, UInt<2>(0h3)) node _T_1340 = and(_T_1338, _T_1339) node _uncommonBits_T_63 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_63 = bits(_uncommonBits_T_63, 1, 0) node _T_1341 = shr(io.in.a.bits.source, 2) node _T_1342 = eq(_T_1341, UInt<5>(0h13)) node _T_1343 = leq(UInt<1>(0h0), uncommonBits_63) node _T_1344 = and(_T_1342, _T_1343) node _T_1345 = leq(uncommonBits_63, UInt<2>(0h3)) node _T_1346 = and(_T_1344, _T_1345) node _T_1347 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1348 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _uncommonBits_T_64 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_64 = bits(_uncommonBits_T_64, 3, 0) node _T_1349 = shr(io.in.a.bits.source, 4) node _T_1350 = eq(_T_1349, UInt<1>(0h1)) node _T_1351 = leq(UInt<1>(0h0), uncommonBits_64) node _T_1352 = and(_T_1350, _T_1351) node _T_1353 = leq(uncommonBits_64, UInt<4>(0hf)) node _T_1354 = and(_T_1352, _T_1353) node _uncommonBits_T_65 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_65 = bits(_uncommonBits_T_65, 3, 0) node _T_1355 = shr(io.in.a.bits.source, 4) node _T_1356 = eq(_T_1355, UInt<1>(0h0)) node _T_1357 = leq(UInt<1>(0h0), uncommonBits_65) node _T_1358 = and(_T_1356, _T_1357) node _T_1359 = leq(uncommonBits_65, UInt<4>(0hf)) node _T_1360 = and(_T_1358, _T_1359) node _T_1361 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1362 = eq(io.in.a.bits.source, UInt<8>(0h80)) node _T_1363 = or(_T_1322, _T_1328) node _T_1364 = or(_T_1363, _T_1334) node _T_1365 = or(_T_1364, _T_1340) node _T_1366 = or(_T_1365, _T_1346) node _T_1367 = or(_T_1366, _T_1347) node _T_1368 = or(_T_1367, _T_1348) node _T_1369 = or(_T_1368, _T_1354) node _T_1370 = or(_T_1369, _T_1360) node _T_1371 = or(_T_1370, _T_1361) node _T_1372 = or(_T_1371, _T_1362) node _T_1373 = and(_T_1321, _T_1372) node _T_1374 = or(UInt<1>(0h0), _T_1373) node _T_1375 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1376 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1377 = and(_T_1375, _T_1376) node _T_1378 = or(UInt<1>(0h0), _T_1377) node _T_1379 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1380 = cvt(_T_1379) node _T_1381 = and(_T_1380, asSInt(UInt<13>(0h1000))) node _T_1382 = asSInt(_T_1381) node _T_1383 = eq(_T_1382, asSInt(UInt<1>(0h0))) node _T_1384 = and(_T_1378, _T_1383) node _T_1385 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1386 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1387 = cvt(_T_1386) node _T_1388 = and(_T_1387, asSInt(UInt<14>(0h2000))) node _T_1389 = asSInt(_T_1388) node _T_1390 = eq(_T_1389, asSInt(UInt<1>(0h0))) node _T_1391 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1392 = cvt(_T_1391) node _T_1393 = and(_T_1392, asSInt(UInt<17>(0h10000))) node _T_1394 = asSInt(_T_1393) node _T_1395 = eq(_T_1394, asSInt(UInt<1>(0h0))) node _T_1396 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1397 = cvt(_T_1396) node _T_1398 = and(_T_1397, asSInt(UInt<18>(0h2f000))) node _T_1399 = asSInt(_T_1398) node _T_1400 = eq(_T_1399, asSInt(UInt<1>(0h0))) node _T_1401 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1402 = cvt(_T_1401) node _T_1403 = and(_T_1402, asSInt(UInt<17>(0h10000))) node _T_1404 = asSInt(_T_1403) node _T_1405 = eq(_T_1404, asSInt(UInt<1>(0h0))) node _T_1406 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1407 = cvt(_T_1406) node _T_1408 = and(_T_1407, asSInt(UInt<13>(0h1000))) node _T_1409 = asSInt(_T_1408) node _T_1410 = eq(_T_1409, asSInt(UInt<1>(0h0))) node _T_1411 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1412 = cvt(_T_1411) node _T_1413 = and(_T_1412, asSInt(UInt<27>(0h4000000))) node _T_1414 = asSInt(_T_1413) node _T_1415 = eq(_T_1414, asSInt(UInt<1>(0h0))) node _T_1416 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1417 = cvt(_T_1416) node _T_1418 = and(_T_1417, asSInt(UInt<13>(0h1000))) node _T_1419 = asSInt(_T_1418) node _T_1420 = eq(_T_1419, asSInt(UInt<1>(0h0))) node _T_1421 = or(_T_1390, _T_1395) node _T_1422 = or(_T_1421, _T_1400) node _T_1423 = or(_T_1422, _T_1405) node _T_1424 = or(_T_1423, _T_1410) node _T_1425 = or(_T_1424, _T_1415) node _T_1426 = or(_T_1425, _T_1420) node _T_1427 = and(_T_1385, _T_1426) node _T_1428 = or(UInt<1>(0h0), _T_1384) node _T_1429 = or(_T_1428, _T_1427) node _T_1430 = and(_T_1374, _T_1429) node _T_1431 = asUInt(reset) node _T_1432 = eq(_T_1431, UInt<1>(0h0)) when _T_1432 : node _T_1433 = eq(_T_1430, UInt<1>(0h0)) when _T_1433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1430, UInt<1>(0h1), "") : assert_46 node _T_1434 = asUInt(reset) node _T_1435 = eq(_T_1434, UInt<1>(0h0)) when _T_1435 : node _T_1436 = eq(source_ok, UInt<1>(0h0)) when _T_1436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1437 = asUInt(reset) node _T_1438 = eq(_T_1437, UInt<1>(0h0)) when _T_1438 : node _T_1439 = eq(is_aligned, UInt<1>(0h0)) when _T_1439 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1440 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1441 = asUInt(reset) node _T_1442 = eq(_T_1441, UInt<1>(0h0)) when _T_1442 : node _T_1443 = eq(_T_1440, UInt<1>(0h0)) when _T_1443 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1440, UInt<1>(0h1), "") : assert_49 node _T_1444 = eq(io.in.a.bits.mask, mask) node _T_1445 = asUInt(reset) node _T_1446 = eq(_T_1445, UInt<1>(0h0)) when _T_1446 : node _T_1447 = eq(_T_1444, UInt<1>(0h0)) when _T_1447 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1444, UInt<1>(0h1), "") : assert_50 node _T_1448 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1449 = asUInt(reset) node _T_1450 = eq(_T_1449, UInt<1>(0h0)) when _T_1450 : node _T_1451 = eq(_T_1448, UInt<1>(0h0)) when _T_1451 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1448, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1452 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1453 = asUInt(reset) node _T_1454 = eq(_T_1453, UInt<1>(0h0)) when _T_1454 : node _T_1455 = eq(_T_1452, UInt<1>(0h0)) when _T_1455 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1452, UInt<1>(0h1), "") : assert_52 node _source_ok_T_50 = eq(io.in.d.bits.source, UInt<7>(0h50)) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<5>(0h10)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<5>(0h11)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_63 = shr(io.in.d.bits.source, 2) node _source_ok_T_64 = eq(_source_ok_T_63, UInt<5>(0h12)) node _source_ok_T_65 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_66 = and(_source_ok_T_64, _source_ok_T_65) node _source_ok_T_67 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_68 = and(_source_ok_T_66, _source_ok_T_67) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 1, 0) node _source_ok_T_69 = shr(io.in.d.bits.source, 2) node _source_ok_T_70 = eq(_source_ok_T_69, UInt<5>(0h13)) node _source_ok_T_71 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_72 = and(_source_ok_T_70, _source_ok_T_71) node _source_ok_T_73 = leq(source_ok_uncommonBits_9, UInt<2>(0h3)) node _source_ok_T_74 = and(_source_ok_T_72, _source_ok_T_73) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_uncommonBits_T_10 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_10 = bits(_source_ok_uncommonBits_T_10, 3, 0) node _source_ok_T_77 = shr(io.in.d.bits.source, 4) node _source_ok_T_78 = eq(_source_ok_T_77, UInt<1>(0h1)) node _source_ok_T_79 = leq(UInt<1>(0h0), source_ok_uncommonBits_10) node _source_ok_T_80 = and(_source_ok_T_78, _source_ok_T_79) node _source_ok_T_81 = leq(source_ok_uncommonBits_10, UInt<4>(0hf)) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_uncommonBits_T_11 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_11 = bits(_source_ok_uncommonBits_T_11, 3, 0) node _source_ok_T_83 = shr(io.in.d.bits.source, 4) node _source_ok_T_84 = eq(_source_ok_T_83, UInt<1>(0h0)) node _source_ok_T_85 = leq(UInt<1>(0h0), source_ok_uncommonBits_11) node _source_ok_T_86 = and(_source_ok_T_84, _source_ok_T_85) node _source_ok_T_87 = leq(source_ok_uncommonBits_11, UInt<4>(0hf)) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_90 = eq(io.in.d.bits.source, UInt<8>(0h80)) wire _source_ok_WIRE_1 : UInt<1>[11] connect _source_ok_WIRE_1[0], _source_ok_T_50 connect _source_ok_WIRE_1[1], _source_ok_T_56 connect _source_ok_WIRE_1[2], _source_ok_T_62 connect _source_ok_WIRE_1[3], _source_ok_T_68 connect _source_ok_WIRE_1[4], _source_ok_T_74 connect _source_ok_WIRE_1[5], _source_ok_T_75 connect _source_ok_WIRE_1[6], _source_ok_T_76 connect _source_ok_WIRE_1[7], _source_ok_T_82 connect _source_ok_WIRE_1[8], _source_ok_T_88 connect _source_ok_WIRE_1[9], _source_ok_T_89 connect _source_ok_WIRE_1[10], _source_ok_T_90 node _source_ok_T_91 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_92 = or(_source_ok_T_91, _source_ok_WIRE_1[2]) node _source_ok_T_93 = or(_source_ok_T_92, _source_ok_WIRE_1[3]) node _source_ok_T_94 = or(_source_ok_T_93, _source_ok_WIRE_1[4]) node _source_ok_T_95 = or(_source_ok_T_94, _source_ok_WIRE_1[5]) node _source_ok_T_96 = or(_source_ok_T_95, _source_ok_WIRE_1[6]) node _source_ok_T_97 = or(_source_ok_T_96, _source_ok_WIRE_1[7]) node _source_ok_T_98 = or(_source_ok_T_97, _source_ok_WIRE_1[8]) node _source_ok_T_99 = or(_source_ok_T_98, _source_ok_WIRE_1[9]) node source_ok_1 = or(_source_ok_T_99, _source_ok_WIRE_1[10]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1456 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1456 : node _T_1457 = asUInt(reset) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(source_ok_1, UInt<1>(0h0)) when _T_1459 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1460 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1461 = asUInt(reset) node _T_1462 = eq(_T_1461, UInt<1>(0h0)) when _T_1462 : node _T_1463 = eq(_T_1460, UInt<1>(0h0)) when _T_1463 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1460, UInt<1>(0h1), "") : assert_54 node _T_1464 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_55 node _T_1468 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1469 = asUInt(reset) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(_T_1468, UInt<1>(0h0)) when _T_1471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1468, UInt<1>(0h1), "") : assert_56 node _T_1472 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1473 = asUInt(reset) node _T_1474 = eq(_T_1473, UInt<1>(0h0)) when _T_1474 : node _T_1475 = eq(_T_1472, UInt<1>(0h0)) when _T_1475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1472, UInt<1>(0h1), "") : assert_57 node _T_1476 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1476 : node _T_1477 = asUInt(reset) node _T_1478 = eq(_T_1477, UInt<1>(0h0)) when _T_1478 : node _T_1479 = eq(source_ok_1, UInt<1>(0h0)) when _T_1479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1480 = asUInt(reset) node _T_1481 = eq(_T_1480, UInt<1>(0h0)) when _T_1481 : node _T_1482 = eq(sink_ok, UInt<1>(0h0)) when _T_1482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1483 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1484 = asUInt(reset) node _T_1485 = eq(_T_1484, UInt<1>(0h0)) when _T_1485 : node _T_1486 = eq(_T_1483, UInt<1>(0h0)) when _T_1486 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1483, UInt<1>(0h1), "") : assert_60 node _T_1487 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1488 = asUInt(reset) node _T_1489 = eq(_T_1488, UInt<1>(0h0)) when _T_1489 : node _T_1490 = eq(_T_1487, UInt<1>(0h0)) when _T_1490 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1487, UInt<1>(0h1), "") : assert_61 node _T_1491 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1492 = asUInt(reset) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) when _T_1493 : node _T_1494 = eq(_T_1491, UInt<1>(0h0)) when _T_1494 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1491, UInt<1>(0h1), "") : assert_62 node _T_1495 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1496 = asUInt(reset) node _T_1497 = eq(_T_1496, UInt<1>(0h0)) when _T_1497 : node _T_1498 = eq(_T_1495, UInt<1>(0h0)) when _T_1498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1495, UInt<1>(0h1), "") : assert_63 node _T_1499 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1500 = or(UInt<1>(0h1), _T_1499) node _T_1501 = asUInt(reset) node _T_1502 = eq(_T_1501, UInt<1>(0h0)) when _T_1502 : node _T_1503 = eq(_T_1500, UInt<1>(0h0)) when _T_1503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1500, UInt<1>(0h1), "") : assert_64 node _T_1504 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1504 : node _T_1505 = asUInt(reset) node _T_1506 = eq(_T_1505, UInt<1>(0h0)) when _T_1506 : node _T_1507 = eq(source_ok_1, UInt<1>(0h0)) when _T_1507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1508 = asUInt(reset) node _T_1509 = eq(_T_1508, UInt<1>(0h0)) when _T_1509 : node _T_1510 = eq(sink_ok, UInt<1>(0h0)) when _T_1510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1511 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1512 = asUInt(reset) node _T_1513 = eq(_T_1512, UInt<1>(0h0)) when _T_1513 : node _T_1514 = eq(_T_1511, UInt<1>(0h0)) when _T_1514 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1511, UInt<1>(0h1), "") : assert_67 node _T_1515 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1516 = asUInt(reset) node _T_1517 = eq(_T_1516, UInt<1>(0h0)) when _T_1517 : node _T_1518 = eq(_T_1515, UInt<1>(0h0)) when _T_1518 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1515, UInt<1>(0h1), "") : assert_68 node _T_1519 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1520 = asUInt(reset) node _T_1521 = eq(_T_1520, UInt<1>(0h0)) when _T_1521 : node _T_1522 = eq(_T_1519, UInt<1>(0h0)) when _T_1522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1519, UInt<1>(0h1), "") : assert_69 node _T_1523 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1524 = or(_T_1523, io.in.d.bits.corrupt) node _T_1525 = asUInt(reset) node _T_1526 = eq(_T_1525, UInt<1>(0h0)) when _T_1526 : node _T_1527 = eq(_T_1524, UInt<1>(0h0)) when _T_1527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1524, UInt<1>(0h1), "") : assert_70 node _T_1528 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1529 = or(UInt<1>(0h1), _T_1528) node _T_1530 = asUInt(reset) node _T_1531 = eq(_T_1530, UInt<1>(0h0)) when _T_1531 : node _T_1532 = eq(_T_1529, UInt<1>(0h0)) when _T_1532 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1529, UInt<1>(0h1), "") : assert_71 node _T_1533 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1533 : node _T_1534 = asUInt(reset) node _T_1535 = eq(_T_1534, UInt<1>(0h0)) when _T_1535 : node _T_1536 = eq(source_ok_1, UInt<1>(0h0)) when _T_1536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1537 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1538 = asUInt(reset) node _T_1539 = eq(_T_1538, UInt<1>(0h0)) when _T_1539 : node _T_1540 = eq(_T_1537, UInt<1>(0h0)) when _T_1540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1537, UInt<1>(0h1), "") : assert_73 node _T_1541 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1542 = asUInt(reset) node _T_1543 = eq(_T_1542, UInt<1>(0h0)) when _T_1543 : node _T_1544 = eq(_T_1541, UInt<1>(0h0)) when _T_1544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1541, UInt<1>(0h1), "") : assert_74 node _T_1545 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1546 = or(UInt<1>(0h1), _T_1545) node _T_1547 = asUInt(reset) node _T_1548 = eq(_T_1547, UInt<1>(0h0)) when _T_1548 : node _T_1549 = eq(_T_1546, UInt<1>(0h0)) when _T_1549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1546, UInt<1>(0h1), "") : assert_75 node _T_1550 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1550 : node _T_1551 = asUInt(reset) node _T_1552 = eq(_T_1551, UInt<1>(0h0)) when _T_1552 : node _T_1553 = eq(source_ok_1, UInt<1>(0h0)) when _T_1553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1554 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1555 = asUInt(reset) node _T_1556 = eq(_T_1555, UInt<1>(0h0)) when _T_1556 : node _T_1557 = eq(_T_1554, UInt<1>(0h0)) when _T_1557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1554, UInt<1>(0h1), "") : assert_77 node _T_1558 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1559 = or(_T_1558, io.in.d.bits.corrupt) node _T_1560 = asUInt(reset) node _T_1561 = eq(_T_1560, UInt<1>(0h0)) when _T_1561 : node _T_1562 = eq(_T_1559, UInt<1>(0h0)) when _T_1562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1559, UInt<1>(0h1), "") : assert_78 node _T_1563 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1564 = or(UInt<1>(0h1), _T_1563) node _T_1565 = asUInt(reset) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(_T_1564, UInt<1>(0h0)) when _T_1567 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1564, UInt<1>(0h1), "") : assert_79 node _T_1568 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1568 : node _T_1569 = asUInt(reset) node _T_1570 = eq(_T_1569, UInt<1>(0h0)) when _T_1570 : node _T_1571 = eq(source_ok_1, UInt<1>(0h0)) when _T_1571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1572 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1573 = asUInt(reset) node _T_1574 = eq(_T_1573, UInt<1>(0h0)) when _T_1574 : node _T_1575 = eq(_T_1572, UInt<1>(0h0)) when _T_1575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1572, UInt<1>(0h1), "") : assert_81 node _T_1576 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1577 = asUInt(reset) node _T_1578 = eq(_T_1577, UInt<1>(0h0)) when _T_1578 : node _T_1579 = eq(_T_1576, UInt<1>(0h0)) when _T_1579 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1576, UInt<1>(0h1), "") : assert_82 node _T_1580 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1581 = or(UInt<1>(0h1), _T_1580) node _T_1582 = asUInt(reset) node _T_1583 = eq(_T_1582, UInt<1>(0h0)) when _T_1583 : node _T_1584 = eq(_T_1581, UInt<1>(0h0)) when _T_1584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1581, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<8>(0h0) connect _WIRE_4.bits.size, UInt<4>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<8>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1585 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1586 = asUInt(reset) node _T_1587 = eq(_T_1586, UInt<1>(0h0)) when _T_1587 : node _T_1588 = eq(_T_1585, UInt<1>(0h0)) when _T_1588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1585, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<8>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1589 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1590 = asUInt(reset) node _T_1591 = eq(_T_1590, UInt<1>(0h0)) when _T_1591 : node _T_1592 = eq(_T_1589, UInt<1>(0h0)) when _T_1592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1589, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1593 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1594 = asUInt(reset) node _T_1595 = eq(_T_1594, UInt<1>(0h0)) when _T_1595 : node _T_1596 = eq(_T_1593, UInt<1>(0h0)) when _T_1596 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1593, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1597 = eq(a_first, UInt<1>(0h0)) node _T_1598 = and(io.in.a.valid, _T_1597) when _T_1598 : node _T_1599 = eq(io.in.a.bits.opcode, opcode) node _T_1600 = asUInt(reset) node _T_1601 = eq(_T_1600, UInt<1>(0h0)) when _T_1601 : node _T_1602 = eq(_T_1599, UInt<1>(0h0)) when _T_1602 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1599, UInt<1>(0h1), "") : assert_87 node _T_1603 = eq(io.in.a.bits.param, param) node _T_1604 = asUInt(reset) node _T_1605 = eq(_T_1604, UInt<1>(0h0)) when _T_1605 : node _T_1606 = eq(_T_1603, UInt<1>(0h0)) when _T_1606 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1603, UInt<1>(0h1), "") : assert_88 node _T_1607 = eq(io.in.a.bits.size, size) node _T_1608 = asUInt(reset) node _T_1609 = eq(_T_1608, UInt<1>(0h0)) when _T_1609 : node _T_1610 = eq(_T_1607, UInt<1>(0h0)) when _T_1610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1607, UInt<1>(0h1), "") : assert_89 node _T_1611 = eq(io.in.a.bits.source, source) node _T_1612 = asUInt(reset) node _T_1613 = eq(_T_1612, UInt<1>(0h0)) when _T_1613 : node _T_1614 = eq(_T_1611, UInt<1>(0h0)) when _T_1614 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1611, UInt<1>(0h1), "") : assert_90 node _T_1615 = eq(io.in.a.bits.address, address) node _T_1616 = asUInt(reset) node _T_1617 = eq(_T_1616, UInt<1>(0h0)) when _T_1617 : node _T_1618 = eq(_T_1615, UInt<1>(0h0)) when _T_1618 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1615, UInt<1>(0h1), "") : assert_91 node _T_1619 = and(io.in.a.ready, io.in.a.valid) node _T_1620 = and(_T_1619, a_first) when _T_1620 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1621 = eq(d_first, UInt<1>(0h0)) node _T_1622 = and(io.in.d.valid, _T_1621) when _T_1622 : node _T_1623 = eq(io.in.d.bits.opcode, opcode_1) node _T_1624 = asUInt(reset) node _T_1625 = eq(_T_1624, UInt<1>(0h0)) when _T_1625 : node _T_1626 = eq(_T_1623, UInt<1>(0h0)) when _T_1626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1623, UInt<1>(0h1), "") : assert_92 node _T_1627 = eq(io.in.d.bits.param, param_1) node _T_1628 = asUInt(reset) node _T_1629 = eq(_T_1628, UInt<1>(0h0)) when _T_1629 : node _T_1630 = eq(_T_1627, UInt<1>(0h0)) when _T_1630 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1627, UInt<1>(0h1), "") : assert_93 node _T_1631 = eq(io.in.d.bits.size, size_1) node _T_1632 = asUInt(reset) node _T_1633 = eq(_T_1632, UInt<1>(0h0)) when _T_1633 : node _T_1634 = eq(_T_1631, UInt<1>(0h0)) when _T_1634 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1631, UInt<1>(0h1), "") : assert_94 node _T_1635 = eq(io.in.d.bits.source, source_1) node _T_1636 = asUInt(reset) node _T_1637 = eq(_T_1636, UInt<1>(0h0)) when _T_1637 : node _T_1638 = eq(_T_1635, UInt<1>(0h0)) when _T_1638 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1635, UInt<1>(0h1), "") : assert_95 node _T_1639 = eq(io.in.d.bits.sink, sink) node _T_1640 = asUInt(reset) node _T_1641 = eq(_T_1640, UInt<1>(0h0)) when _T_1641 : node _T_1642 = eq(_T_1639, UInt<1>(0h0)) when _T_1642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1639, UInt<1>(0h1), "") : assert_96 node _T_1643 = eq(io.in.d.bits.denied, denied) node _T_1644 = asUInt(reset) node _T_1645 = eq(_T_1644, UInt<1>(0h0)) when _T_1645 : node _T_1646 = eq(_T_1643, UInt<1>(0h0)) when _T_1646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1643, UInt<1>(0h1), "") : assert_97 node _T_1647 = and(io.in.d.ready, io.in.d.valid) node _T_1648 = and(_T_1647, d_first) when _T_1648 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes : UInt<1032>, clock, reset, UInt<1032>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<129> connect a_set, UInt<129>(0h0) wire a_set_wo_ready : UInt<129> connect a_set_wo_ready, UInt<129>(0h0) wire a_opcodes_set : UInt<516> connect a_opcodes_set, UInt<516>(0h0) wire a_sizes_set : UInt<1032> connect a_sizes_set, UInt<1032>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1649 = and(io.in.a.valid, a_first_1) node _T_1650 = and(_T_1649, UInt<1>(0h1)) when _T_1650 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1651 = and(io.in.a.ready, io.in.a.valid) node _T_1652 = and(_T_1651, a_first_1) node _T_1653 = and(_T_1652, UInt<1>(0h1)) when _T_1653 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1654 = dshr(inflight, io.in.a.bits.source) node _T_1655 = bits(_T_1654, 0, 0) node _T_1656 = eq(_T_1655, UInt<1>(0h0)) node _T_1657 = asUInt(reset) node _T_1658 = eq(_T_1657, UInt<1>(0h0)) when _T_1658 : node _T_1659 = eq(_T_1656, UInt<1>(0h0)) when _T_1659 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1656, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<129> connect d_clr, UInt<129>(0h0) wire d_clr_wo_ready : UInt<129> connect d_clr_wo_ready, UInt<129>(0h0) wire d_opcodes_clr : UInt<516> connect d_opcodes_clr, UInt<516>(0h0) wire d_sizes_clr : UInt<1032> connect d_sizes_clr, UInt<1032>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1660 = and(io.in.d.valid, d_first_1) node _T_1661 = and(_T_1660, UInt<1>(0h1)) node _T_1662 = eq(d_release_ack, UInt<1>(0h0)) node _T_1663 = and(_T_1661, _T_1662) when _T_1663 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1664 = and(io.in.d.ready, io.in.d.valid) node _T_1665 = and(_T_1664, d_first_1) node _T_1666 = and(_T_1665, UInt<1>(0h1)) node _T_1667 = eq(d_release_ack, UInt<1>(0h0)) node _T_1668 = and(_T_1666, _T_1667) when _T_1668 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1669 = and(io.in.d.valid, d_first_1) node _T_1670 = and(_T_1669, UInt<1>(0h1)) node _T_1671 = eq(d_release_ack, UInt<1>(0h0)) node _T_1672 = and(_T_1670, _T_1671) when _T_1672 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1673 = dshr(inflight, io.in.d.bits.source) node _T_1674 = bits(_T_1673, 0, 0) node _T_1675 = or(_T_1674, same_cycle_resp) node _T_1676 = asUInt(reset) node _T_1677 = eq(_T_1676, UInt<1>(0h0)) when _T_1677 : node _T_1678 = eq(_T_1675, UInt<1>(0h0)) when _T_1678 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1675, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1679 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1680 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1681 = or(_T_1679, _T_1680) node _T_1682 = asUInt(reset) node _T_1683 = eq(_T_1682, UInt<1>(0h0)) when _T_1683 : node _T_1684 = eq(_T_1681, UInt<1>(0h0)) when _T_1684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1681, UInt<1>(0h1), "") : assert_100 node _T_1685 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1686 = asUInt(reset) node _T_1687 = eq(_T_1686, UInt<1>(0h0)) when _T_1687 : node _T_1688 = eq(_T_1685, UInt<1>(0h0)) when _T_1688 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1685, UInt<1>(0h1), "") : assert_101 else : node _T_1689 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1690 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1691 = or(_T_1689, _T_1690) node _T_1692 = asUInt(reset) node _T_1693 = eq(_T_1692, UInt<1>(0h0)) when _T_1693 : node _T_1694 = eq(_T_1691, UInt<1>(0h0)) when _T_1694 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1691, UInt<1>(0h1), "") : assert_102 node _T_1695 = eq(io.in.d.bits.size, a_size_lookup) node _T_1696 = asUInt(reset) node _T_1697 = eq(_T_1696, UInt<1>(0h0)) when _T_1697 : node _T_1698 = eq(_T_1695, UInt<1>(0h0)) when _T_1698 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1695, UInt<1>(0h1), "") : assert_103 node _T_1699 = and(io.in.d.valid, d_first_1) node _T_1700 = and(_T_1699, a_first_1) node _T_1701 = and(_T_1700, io.in.a.valid) node _T_1702 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1703 = and(_T_1701, _T_1702) node _T_1704 = eq(d_release_ack, UInt<1>(0h0)) node _T_1705 = and(_T_1703, _T_1704) when _T_1705 : node _T_1706 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1707 = or(_T_1706, io.in.a.ready) node _T_1708 = asUInt(reset) node _T_1709 = eq(_T_1708, UInt<1>(0h0)) when _T_1709 : node _T_1710 = eq(_T_1707, UInt<1>(0h0)) when _T_1710 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1707, UInt<1>(0h1), "") : assert_104 node _T_1711 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1712 = orr(a_set_wo_ready) node _T_1713 = eq(_T_1712, UInt<1>(0h0)) node _T_1714 = or(_T_1711, _T_1713) node _T_1715 = asUInt(reset) node _T_1716 = eq(_T_1715, UInt<1>(0h0)) when _T_1716 : node _T_1717 = eq(_T_1714, UInt<1>(0h0)) when _T_1717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1714, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_40 node _T_1718 = orr(inflight) node _T_1719 = eq(_T_1718, UInt<1>(0h0)) node _T_1720 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1721 = or(_T_1719, _T_1720) node _T_1722 = lt(watchdog, plusarg_reader.out) node _T_1723 = or(_T_1721, _T_1722) node _T_1724 = asUInt(reset) node _T_1725 = eq(_T_1724, UInt<1>(0h0)) when _T_1725 : node _T_1726 = eq(_T_1723, UInt<1>(0h0)) when _T_1726 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1723, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1727 = and(io.in.a.ready, io.in.a.valid) node _T_1728 = and(io.in.d.ready, io.in.d.valid) node _T_1729 = or(_T_1727, _T_1728) when _T_1729 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<129>, clock, reset, UInt<129>(0h0) regreset inflight_opcodes_1 : UInt<516>, clock, reset, UInt<516>(0h0) regreset inflight_sizes_1 : UInt<1032>, clock, reset, UInt<1032>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<8>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<8>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<129> connect c_set, UInt<129>(0h0) wire c_set_wo_ready : UInt<129> connect c_set_wo_ready, UInt<129>(0h0) wire c_opcodes_set : UInt<516> connect c_opcodes_set, UInt<516>(0h0) wire c_sizes_set : UInt<1032> connect c_sizes_set, UInt<1032>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<8>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1730 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<8>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1731 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1732 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1733 = and(_T_1731, _T_1732) node _T_1734 = and(_T_1730, _T_1733) when _T_1734 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<8>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<8>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1735 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1736 = and(_T_1735, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<8>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1737 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1738 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1739 = and(_T_1737, _T_1738) node _T_1740 = and(_T_1736, _T_1739) when _T_1740 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<8>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<8>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<8>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1741 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1742 = bits(_T_1741, 0, 0) node _T_1743 = eq(_T_1742, UInt<1>(0h0)) node _T_1744 = asUInt(reset) node _T_1745 = eq(_T_1744, UInt<1>(0h0)) when _T_1745 : node _T_1746 = eq(_T_1743, UInt<1>(0h0)) when _T_1746 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1743, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<8>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<129> connect d_clr_1, UInt<129>(0h0) wire d_clr_wo_ready_1 : UInt<129> connect d_clr_wo_ready_1, UInt<129>(0h0) wire d_opcodes_clr_1 : UInt<516> connect d_opcodes_clr_1, UInt<516>(0h0) wire d_sizes_clr_1 : UInt<1032> connect d_sizes_clr_1, UInt<1032>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1747 = and(io.in.d.valid, d_first_2) node _T_1748 = and(_T_1747, UInt<1>(0h1)) node _T_1749 = and(_T_1748, d_release_ack_1) when _T_1749 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1750 = and(io.in.d.ready, io.in.d.valid) node _T_1751 = and(_T_1750, d_first_2) node _T_1752 = and(_T_1751, UInt<1>(0h1)) node _T_1753 = and(_T_1752, d_release_ack_1) when _T_1753 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1754 = and(io.in.d.valid, d_first_2) node _T_1755 = and(_T_1754, UInt<1>(0h1)) node _T_1756 = and(_T_1755, d_release_ack_1) when _T_1756 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<8>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1757 = dshr(inflight_1, io.in.d.bits.source) node _T_1758 = bits(_T_1757, 0, 0) node _T_1759 = or(_T_1758, same_cycle_resp_1) node _T_1760 = asUInt(reset) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) when _T_1761 : node _T_1762 = eq(_T_1759, UInt<1>(0h0)) when _T_1762 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1759, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<8>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1763 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1764 = asUInt(reset) node _T_1765 = eq(_T_1764, UInt<1>(0h0)) when _T_1765 : node _T_1766 = eq(_T_1763, UInt<1>(0h0)) when _T_1766 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1763, UInt<1>(0h1), "") : assert_109 else : node _T_1767 = eq(io.in.d.bits.size, c_size_lookup) node _T_1768 = asUInt(reset) node _T_1769 = eq(_T_1768, UInt<1>(0h0)) when _T_1769 : node _T_1770 = eq(_T_1767, UInt<1>(0h0)) when _T_1770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1767, UInt<1>(0h1), "") : assert_110 node _T_1771 = and(io.in.d.valid, d_first_2) node _T_1772 = and(_T_1771, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<8>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1773 = and(_T_1772, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<8>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1774 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1775 = and(_T_1773, _T_1774) node _T_1776 = and(_T_1775, d_release_ack_1) node _T_1777 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1778 = and(_T_1776, _T_1777) when _T_1778 : node _T_1779 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<8>(0h0) connect _WIRE_26.bits.size, UInt<4>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1780 = or(_T_1779, _WIRE_27.ready) node _T_1781 = asUInt(reset) node _T_1782 = eq(_T_1781, UInt<1>(0h0)) when _T_1782 : node _T_1783 = eq(_T_1780, UInt<1>(0h0)) when _T_1783 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1780, UInt<1>(0h1), "") : assert_111 node _T_1784 = orr(c_set_wo_ready) when _T_1784 : node _T_1785 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1786 = asUInt(reset) node _T_1787 = eq(_T_1786, UInt<1>(0h0)) when _T_1787 : node _T_1788 = eq(_T_1785, UInt<1>(0h0)) when _T_1788 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1785, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_41 node _T_1789 = orr(inflight_1) node _T_1790 = eq(_T_1789, UInt<1>(0h0)) node _T_1791 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1792 = or(_T_1790, _T_1791) node _T_1793 = lt(watchdog_1, plusarg_reader_1.out) node _T_1794 = or(_T_1792, _T_1793) node _T_1795 = asUInt(reset) node _T_1796 = eq(_T_1795, UInt<1>(0h0)) when _T_1796 : node _T_1797 = eq(_T_1794, UInt<1>(0h0)) when _T_1797 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1794, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<8>(0h0) connect _WIRE_28.bits.size, UInt<4>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<8>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1798 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1799 = and(io.in.d.ready, io.in.d.valid) node _T_1800 = or(_T_1798, _T_1799) when _T_1800 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_20( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [7:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [7:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_31 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_35 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_37 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_53 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_55 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_59 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_61 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_65 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_67 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_71 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_73 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_79 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_85 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_first_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_first_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_wo_ready_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_wo_ready_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_interm_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_interm_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_opcodes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_opcodes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_sizes_set_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_sizes_set_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _c_probe_ack_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _c_probe_ack_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_1_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_2_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_3_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [7:0] _same_cycle_resp_WIRE_4_bits_source = 8'h0; // @[Bundles.scala:265:74] wire [7:0] _same_cycle_resp_WIRE_5_bits_source = 8'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2051:0] _c_sizes_set_T_1 = 2052'h0; // @[Monitor.scala:768:52] wire [10:0] _c_opcodes_set_T = 11'h0; // @[Monitor.scala:767:79] wire [10:0] _c_sizes_set_T = 11'h0; // @[Monitor.scala:768:77] wire [2050:0] _c_opcodes_set_T_1 = 2051'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [255:0] _c_set_wo_ready_T = 256'h1; // @[OneHot.scala:58:35] wire [255:0] _c_set_T = 256'h1; // @[OneHot.scala:58:35] wire [1031:0] c_sizes_set = 1032'h0; // @[Monitor.scala:741:34] wire [515:0] c_opcodes_set = 516'h0; // @[Monitor.scala:740:34] wire [128:0] c_set = 129'h0; // @[Monitor.scala:738:34] wire [128:0] c_set_wo_ready = 129'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [7:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_55 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_56 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_57 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_58 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_59 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_60 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_61 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_62 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_63 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_64 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _uncommonBits_T_65 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_10 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [7:0] _source_ok_uncommonBits_T_11 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_1 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_7 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_13 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_19 = io_in_a_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_27 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_33 = io_in_a_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_28 = _source_ok_T_27 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_32 = _source_ok_T_30; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_34 = _source_ok_T_33 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_36 = _source_ok_T_34; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_38 = _source_ok_T_36; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_8 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_43 = _source_ok_T_42 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_44 = _source_ok_T_43 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_45 = _source_ok_T_44 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_46 = _source_ok_T_45 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_47 = _source_ok_T_46 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_48 = _source_ok_T_47 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_49 = _source_ok_T_48 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_49 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {17'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_22 = _uncommonBits_T_22[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_23 = _uncommonBits_T_23[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_28 = _uncommonBits_T_28[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_29 = _uncommonBits_T_29[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_34 = _uncommonBits_T_34[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_35 = _uncommonBits_T_35[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_40 = _uncommonBits_T_40[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_41 = _uncommonBits_T_41[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_44 = _uncommonBits_T_44[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_46 = _uncommonBits_T_46[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_47 = _uncommonBits_T_47[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_49 = _uncommonBits_T_49[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_52 = _uncommonBits_T_52[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_53 = _uncommonBits_T_53[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_54 = _uncommonBits_T_54[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_55 = _uncommonBits_T_55[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_56 = _uncommonBits_T_56[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_57 = _uncommonBits_T_57[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_58 = _uncommonBits_T_58[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_59 = _uncommonBits_T_59[3:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_60 = _uncommonBits_T_60[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_61 = _uncommonBits_T_61[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_62 = _uncommonBits_T_62[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_63 = _uncommonBits_T_63[1:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_64 = _uncommonBits_T_64[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_65 = _uncommonBits_T_65[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_50 = io_in_d_bits_source_0 == 8'h50; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_50; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [5:0] _source_ok_T_51 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_57 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_63 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire [5:0] _source_ok_T_69 = io_in_d_bits_source_0[7:2]; // @[Monitor.scala:36:7] wire _source_ok_T_52 = _source_ok_T_51 == 6'h10; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_54 = _source_ok_T_52; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_56 = _source_ok_T_54; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_56; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_58 = _source_ok_T_57 == 6'h11; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_60 = _source_ok_T_58; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_62 = _source_ok_T_60; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_62; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_64 = _source_ok_T_63 == 6'h12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_66 = _source_ok_T_64; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_68 = _source_ok_T_66; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_68; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_70 = _source_ok_T_69 == 6'h13; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_72 = _source_ok_T_70; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_74 = _source_ok_T_72; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 8'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 8'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_10 = _source_ok_uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_77 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire [3:0] _source_ok_T_83 = io_in_d_bits_source_0[7:4]; // @[Monitor.scala:36:7] wire _source_ok_T_78 = _source_ok_T_77 == 4'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_80 = _source_ok_T_78; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_7 = _source_ok_T_82; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_11 = _source_ok_uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_84 = _source_ok_T_83 == 4'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_86 = _source_ok_T_84; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_8 = _source_ok_T_88; // @[Parameters.scala:1138:31] wire _source_ok_T_89 = io_in_d_bits_source_0 == 8'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_89; // @[Parameters.scala:1138:31] wire _source_ok_T_90 = io_in_d_bits_source_0 == 8'h80; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire _source_ok_T_91 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_92 = _source_ok_T_91 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_93 = _source_ok_T_92 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_94 = _source_ok_T_93 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_95 = _source_ok_T_94 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_96 = _source_ok_T_95 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_97 = _source_ok_T_96 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_98 = _source_ok_T_97 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_99 = _source_ok_T_98 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_99 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _T_1727 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1727; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1727; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [7:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1800 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1800; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1800; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1800; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [7:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [128:0] inflight; // @[Monitor.scala:614:27] reg [515:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [1031:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [128:0] a_set; // @[Monitor.scala:626:34] wire [128:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [515:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [1031:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [10:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [10:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [10:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [10:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [10:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [515:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [515:0] _a_opcode_lookup_T_6 = {512'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [515:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [10:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [10:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [10:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [10:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [10:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [1031:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [1031:0] _a_size_lookup_T_6 = {1024'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [1031:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[1031:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [255:0] _GEN_3 = 256'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_3; // @[OneHot.scala:58:35] wire [255:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_3; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1653 = _T_1727 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1653 ? _a_set_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1653 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1653 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [10:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [2050:0] _a_opcodes_set_T_1 = {2047'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1653 ? _a_opcodes_set_T_1[515:0] : 516'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [10:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [2051:0] _a_sizes_set_T_1 = {2047'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1653 ? _a_sizes_set_T_1[1031:0] : 1032'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [128:0] d_clr; // @[Monitor.scala:664:34] wire [128:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [515:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [1031:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1699 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [255:0] _GEN_5 = 256'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [255:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1699 & ~d_release_ack ? _d_clr_wo_ready_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1668 = _T_1800 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1668 ? _d_clr_T[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_5 = 2063'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1668 ? _d_opcodes_clr_T_5[515:0] : 516'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [2062:0] _d_sizes_clr_T_5 = 2063'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1668 ? _d_sizes_clr_T_5[1031:0] : 1032'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [128:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [128:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [128:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [515:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [515:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [515:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [1031:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [1031:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [1031:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [128:0] inflight_1; // @[Monitor.scala:726:35] wire [128:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [515:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [515:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [1031:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [1031:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [515:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [515:0] _c_opcode_lookup_T_6 = {512'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [515:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[515:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [1031:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [1031:0] _c_size_lookup_T_6 = {1024'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [1031:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[1031:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [128:0] d_clr_1; // @[Monitor.scala:774:34] wire [128:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [515:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [1031:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1771 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1771 & d_release_ack_1 ? _d_clr_wo_ready_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire _T_1753 = _T_1800 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1753 ? _d_clr_T_1[128:0] : 129'h0; // @[OneHot.scala:58:35] wire [2062:0] _d_opcodes_clr_T_11 = 2063'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1753 ? _d_opcodes_clr_T_11[515:0] : 516'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [2062:0] _d_sizes_clr_T_11 = 2063'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1753 ? _d_sizes_clr_T_11[1031:0] : 1032'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 8'h0; // @[Monitor.scala:36:7, :795:113] wire [128:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [128:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [515:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [515:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [1031:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [1031:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_238 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RecFNToRecFN_238( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_191 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_447 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_191( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_447 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_184 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_336 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_184( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_336 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_5 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _source_ok_T_30 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _source_ok_T_35 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _source_ok_T_36 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _source_ok_T_37 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _source_ok_T_38 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _source_ok_T_39 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _source_ok_T_40 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_41 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_42 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_43 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _source_ok_T_44 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _source_ok_T_45 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _source_ok_T_46 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_47 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_48 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_49 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[30] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 connect _source_ok_WIRE[10], _source_ok_T_30 connect _source_ok_WIRE[11], _source_ok_T_31 connect _source_ok_WIRE[12], _source_ok_T_32 connect _source_ok_WIRE[13], _source_ok_T_33 connect _source_ok_WIRE[14], _source_ok_T_34 connect _source_ok_WIRE[15], _source_ok_T_35 connect _source_ok_WIRE[16], _source_ok_T_36 connect _source_ok_WIRE[17], _source_ok_T_37 connect _source_ok_WIRE[18], _source_ok_T_38 connect _source_ok_WIRE[19], _source_ok_T_39 connect _source_ok_WIRE[20], _source_ok_T_40 connect _source_ok_WIRE[21], _source_ok_T_41 connect _source_ok_WIRE[22], _source_ok_T_42 connect _source_ok_WIRE[23], _source_ok_T_43 connect _source_ok_WIRE[24], _source_ok_T_44 connect _source_ok_WIRE[25], _source_ok_T_45 connect _source_ok_WIRE[26], _source_ok_T_46 connect _source_ok_WIRE[27], _source_ok_T_47 connect _source_ok_WIRE[28], _source_ok_T_48 connect _source_ok_WIRE[29], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE[2]) node _source_ok_T_52 = or(_source_ok_T_51, _source_ok_WIRE[3]) node _source_ok_T_53 = or(_source_ok_T_52, _source_ok_WIRE[4]) node _source_ok_T_54 = or(_source_ok_T_53, _source_ok_WIRE[5]) node _source_ok_T_55 = or(_source_ok_T_54, _source_ok_WIRE[6]) node _source_ok_T_56 = or(_source_ok_T_55, _source_ok_WIRE[7]) node _source_ok_T_57 = or(_source_ok_T_56, _source_ok_WIRE[8]) node _source_ok_T_58 = or(_source_ok_T_57, _source_ok_WIRE[9]) node _source_ok_T_59 = or(_source_ok_T_58, _source_ok_WIRE[10]) node _source_ok_T_60 = or(_source_ok_T_59, _source_ok_WIRE[11]) node _source_ok_T_61 = or(_source_ok_T_60, _source_ok_WIRE[12]) node _source_ok_T_62 = or(_source_ok_T_61, _source_ok_WIRE[13]) node _source_ok_T_63 = or(_source_ok_T_62, _source_ok_WIRE[14]) node _source_ok_T_64 = or(_source_ok_T_63, _source_ok_WIRE[15]) node _source_ok_T_65 = or(_source_ok_T_64, _source_ok_WIRE[16]) node _source_ok_T_66 = or(_source_ok_T_65, _source_ok_WIRE[17]) node _source_ok_T_67 = or(_source_ok_T_66, _source_ok_WIRE[18]) node _source_ok_T_68 = or(_source_ok_T_67, _source_ok_WIRE[19]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE[20]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE[21]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE[22]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE[23]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE[24]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE[25]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE[26]) node _source_ok_T_76 = or(_source_ok_T_75, _source_ok_WIRE[27]) node _source_ok_T_77 = or(_source_ok_T_76, _source_ok_WIRE[28]) node source_ok = or(_source_ok_T_77, _source_ok_WIRE[29]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_105 = eq(_T_104, UInt<1>(0h0)) node _T_106 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = or(_T_105, _T_110) node _T_112 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_113 = eq(_T_112, UInt<1>(0h0)) node _T_114 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = or(_T_113, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<1>(0h0))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = or(_T_121, _T_126) node _T_128 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_129 = eq(_T_128, UInt<1>(0h0)) node _T_130 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_131 = cvt(_T_130) node _T_132 = and(_T_131, asSInt(UInt<1>(0h0))) node _T_133 = asSInt(_T_132) node _T_134 = eq(_T_133, asSInt(UInt<1>(0h0))) node _T_135 = or(_T_129, _T_134) node _T_136 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_137 = eq(_T_136, UInt<1>(0h0)) node _T_138 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_139 = cvt(_T_138) node _T_140 = and(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = asSInt(_T_140) node _T_142 = eq(_T_141, asSInt(UInt<1>(0h0))) node _T_143 = or(_T_137, _T_142) node _T_144 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_145 = eq(_T_144, UInt<1>(0h0)) node _T_146 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<1>(0h0))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = or(_T_145, _T_150) node _T_152 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_153 = eq(_T_152, UInt<1>(0h0)) node _T_154 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_155 = cvt(_T_154) node _T_156 = and(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = asSInt(_T_156) node _T_158 = eq(_T_157, asSInt(UInt<1>(0h0))) node _T_159 = or(_T_153, _T_158) node _T_160 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_161 = eq(_T_160, UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<1>(0h0))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_161, _T_166) node _T_168 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_171 = cvt(_T_170) node _T_172 = and(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = asSInt(_T_172) node _T_174 = eq(_T_173, asSInt(UInt<1>(0h0))) node _T_175 = or(_T_169, _T_174) node _T_176 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_177 = eq(_T_176, UInt<1>(0h0)) node _T_178 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<1>(0h0))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = or(_T_177, _T_182) node _T_184 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_187 = cvt(_T_186) node _T_188 = and(_T_187, asSInt(UInt<1>(0h0))) node _T_189 = asSInt(_T_188) node _T_190 = eq(_T_189, asSInt(UInt<1>(0h0))) node _T_191 = or(_T_185, _T_190) node _T_192 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_193 = eq(_T_192, UInt<1>(0h0)) node _T_194 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_195 = cvt(_T_194) node _T_196 = and(_T_195, asSInt(UInt<1>(0h0))) node _T_197 = asSInt(_T_196) node _T_198 = eq(_T_197, asSInt(UInt<1>(0h0))) node _T_199 = or(_T_193, _T_198) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_201 = eq(_T_200, UInt<1>(0h0)) node _T_202 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_203 = cvt(_T_202) node _T_204 = and(_T_203, asSInt(UInt<1>(0h0))) node _T_205 = asSInt(_T_204) node _T_206 = eq(_T_205, asSInt(UInt<1>(0h0))) node _T_207 = or(_T_201, _T_206) node _T_208 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_209 = eq(_T_208, UInt<1>(0h0)) node _T_210 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_211 = cvt(_T_210) node _T_212 = and(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = asSInt(_T_212) node _T_214 = eq(_T_213, asSInt(UInt<1>(0h0))) node _T_215 = or(_T_209, _T_214) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_217 = eq(_T_216, UInt<1>(0h0)) node _T_218 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_219 = cvt(_T_218) node _T_220 = and(_T_219, asSInt(UInt<1>(0h0))) node _T_221 = asSInt(_T_220) node _T_222 = eq(_T_221, asSInt(UInt<1>(0h0))) node _T_223 = or(_T_217, _T_222) node _T_224 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_227 = cvt(_T_226) node _T_228 = and(_T_227, asSInt(UInt<1>(0h0))) node _T_229 = asSInt(_T_228) node _T_230 = eq(_T_229, asSInt(UInt<1>(0h0))) node _T_231 = or(_T_225, _T_230) node _T_232 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_233 = eq(_T_232, UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<1>(0h0))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = or(_T_233, _T_238) node _T_240 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_241 = eq(_T_240, UInt<1>(0h0)) node _T_242 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = or(_T_241, _T_246) node _T_248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_249 = eq(_T_248, UInt<1>(0h0)) node _T_250 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<1>(0h0))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_257 = eq(_T_256, UInt<1>(0h0)) node _T_258 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_259 = cvt(_T_258) node _T_260 = and(_T_259, asSInt(UInt<1>(0h0))) node _T_261 = asSInt(_T_260) node _T_262 = eq(_T_261, asSInt(UInt<1>(0h0))) node _T_263 = or(_T_257, _T_262) node _T_264 = and(_T_11, _T_24) node _T_265 = and(_T_264, _T_37) node _T_266 = and(_T_265, _T_50) node _T_267 = and(_T_266, _T_63) node _T_268 = and(_T_267, _T_71) node _T_269 = and(_T_268, _T_79) node _T_270 = and(_T_269, _T_87) node _T_271 = and(_T_270, _T_95) node _T_272 = and(_T_271, _T_103) node _T_273 = and(_T_272, _T_111) node _T_274 = and(_T_273, _T_119) node _T_275 = and(_T_274, _T_127) node _T_276 = and(_T_275, _T_135) node _T_277 = and(_T_276, _T_143) node _T_278 = and(_T_277, _T_151) node _T_279 = and(_T_278, _T_159) node _T_280 = and(_T_279, _T_167) node _T_281 = and(_T_280, _T_175) node _T_282 = and(_T_281, _T_183) node _T_283 = and(_T_282, _T_191) node _T_284 = and(_T_283, _T_199) node _T_285 = and(_T_284, _T_207) node _T_286 = and(_T_285, _T_215) node _T_287 = and(_T_286, _T_223) node _T_288 = and(_T_287, _T_231) node _T_289 = and(_T_288, _T_239) node _T_290 = and(_T_289, _T_247) node _T_291 = and(_T_290, _T_255) node _T_292 = and(_T_291, _T_263) node _T_293 = asUInt(reset) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(_T_292, UInt<1>(0h0)) when _T_295 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_292, UInt<1>(0h1), "") : assert_1 node _T_296 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_296 : node _T_297 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_298 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_299 = and(_T_297, _T_298) node _T_300 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_301 = shr(io.in.a.bits.source, 2) node _T_302 = eq(_T_301, UInt<1>(0h0)) node _T_303 = leq(UInt<1>(0h0), uncommonBits_4) node _T_304 = and(_T_302, _T_303) node _T_305 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_306 = and(_T_304, _T_305) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_307 = shr(io.in.a.bits.source, 2) node _T_308 = eq(_T_307, UInt<1>(0h1)) node _T_309 = leq(UInt<1>(0h0), uncommonBits_5) node _T_310 = and(_T_308, _T_309) node _T_311 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_312 = and(_T_310, _T_311) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_313 = shr(io.in.a.bits.source, 2) node _T_314 = eq(_T_313, UInt<2>(0h2)) node _T_315 = leq(UInt<1>(0h0), uncommonBits_6) node _T_316 = and(_T_314, _T_315) node _T_317 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_318 = and(_T_316, _T_317) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<2>(0h3)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_7) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_326 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_327 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_328 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_329 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_330 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_331 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_332 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_333 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_334 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_335 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_336 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_337 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_338 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_339 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_340 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_341 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_342 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_343 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_347 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_348 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_349 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_350 = or(_T_300, _T_306) node _T_351 = or(_T_350, _T_312) node _T_352 = or(_T_351, _T_318) node _T_353 = or(_T_352, _T_324) node _T_354 = or(_T_353, _T_325) node _T_355 = or(_T_354, _T_326) node _T_356 = or(_T_355, _T_327) node _T_357 = or(_T_356, _T_328) node _T_358 = or(_T_357, _T_329) node _T_359 = or(_T_358, _T_330) node _T_360 = or(_T_359, _T_331) node _T_361 = or(_T_360, _T_332) node _T_362 = or(_T_361, _T_333) node _T_363 = or(_T_362, _T_334) node _T_364 = or(_T_363, _T_335) node _T_365 = or(_T_364, _T_336) node _T_366 = or(_T_365, _T_337) node _T_367 = or(_T_366, _T_338) node _T_368 = or(_T_367, _T_339) node _T_369 = or(_T_368, _T_340) node _T_370 = or(_T_369, _T_341) node _T_371 = or(_T_370, _T_342) node _T_372 = or(_T_371, _T_343) node _T_373 = or(_T_372, _T_344) node _T_374 = or(_T_373, _T_345) node _T_375 = or(_T_374, _T_346) node _T_376 = or(_T_375, _T_347) node _T_377 = or(_T_376, _T_348) node _T_378 = or(_T_377, _T_349) node _T_379 = and(_T_299, _T_378) node _T_380 = or(UInt<1>(0h0), _T_379) node _T_381 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<13>(0h1000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = or(_T_386, _T_391) node _T_393 = and(_T_381, _T_392) node _T_394 = or(UInt<1>(0h0), _T_393) node _T_395 = and(_T_380, _T_394) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_395, UInt<1>(0h1), "") : assert_2 node _T_399 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_400 = shr(io.in.a.bits.source, 2) node _T_401 = eq(_T_400, UInt<1>(0h0)) node _T_402 = leq(UInt<1>(0h0), uncommonBits_8) node _T_403 = and(_T_401, _T_402) node _T_404 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_405 = and(_T_403, _T_404) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_406 = shr(io.in.a.bits.source, 2) node _T_407 = eq(_T_406, UInt<1>(0h1)) node _T_408 = leq(UInt<1>(0h0), uncommonBits_9) node _T_409 = and(_T_407, _T_408) node _T_410 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_411 = and(_T_409, _T_410) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_412 = shr(io.in.a.bits.source, 2) node _T_413 = eq(_T_412, UInt<2>(0h2)) node _T_414 = leq(UInt<1>(0h0), uncommonBits_10) node _T_415 = and(_T_413, _T_414) node _T_416 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_417 = and(_T_415, _T_416) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_418 = shr(io.in.a.bits.source, 2) node _T_419 = eq(_T_418, UInt<2>(0h3)) node _T_420 = leq(UInt<1>(0h0), uncommonBits_11) node _T_421 = and(_T_419, _T_420) node _T_422 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_423 = and(_T_421, _T_422) node _T_424 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_425 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_426 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_427 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_428 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_429 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_430 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_431 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_432 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_433 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_434 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_435 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_436 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_437 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_438 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_439 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_443 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_444 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_445 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_446 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_447 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_448 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[30] connect _WIRE[0], _T_399 connect _WIRE[1], _T_405 connect _WIRE[2], _T_411 connect _WIRE[3], _T_417 connect _WIRE[4], _T_423 connect _WIRE[5], _T_424 connect _WIRE[6], _T_425 connect _WIRE[7], _T_426 connect _WIRE[8], _T_427 connect _WIRE[9], _T_428 connect _WIRE[10], _T_429 connect _WIRE[11], _T_430 connect _WIRE[12], _T_431 connect _WIRE[13], _T_432 connect _WIRE[14], _T_433 connect _WIRE[15], _T_434 connect _WIRE[16], _T_435 connect _WIRE[17], _T_436 connect _WIRE[18], _T_437 connect _WIRE[19], _T_438 connect _WIRE[20], _T_439 connect _WIRE[21], _T_440 connect _WIRE[22], _T_441 connect _WIRE[23], _T_442 connect _WIRE[24], _T_443 connect _WIRE[25], _T_444 connect _WIRE[26], _T_445 connect _WIRE[27], _T_446 connect _WIRE[28], _T_447 connect _WIRE[29], _T_448 node _T_449 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_450 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_451 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_452 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_453 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_454 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_455 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_456 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_457 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_458 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_459 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_460 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_461 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_462 = mux(_WIRE[5], _T_449, UInt<1>(0h0)) node _T_463 = mux(_WIRE[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_464 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_465 = mux(_WIRE[8], _T_450, UInt<1>(0h0)) node _T_466 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_467 = mux(_WIRE[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_468 = mux(_WIRE[11], _T_451, UInt<1>(0h0)) node _T_469 = mux(_WIRE[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_470 = mux(_WIRE[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_471 = mux(_WIRE[14], _T_452, UInt<1>(0h0)) node _T_472 = mux(_WIRE[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_473 = mux(_WIRE[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_474 = mux(_WIRE[17], _T_453, UInt<1>(0h0)) node _T_475 = mux(_WIRE[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_476 = mux(_WIRE[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_477 = mux(_WIRE[20], _T_454, UInt<1>(0h0)) node _T_478 = mux(_WIRE[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_479 = mux(_WIRE[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_480 = mux(_WIRE[23], _T_455, UInt<1>(0h0)) node _T_481 = mux(_WIRE[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_482 = mux(_WIRE[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_483 = mux(_WIRE[26], _T_456, UInt<1>(0h0)) node _T_484 = mux(_WIRE[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_485 = mux(_WIRE[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_486 = mux(_WIRE[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_487 = or(_T_457, _T_458) node _T_488 = or(_T_487, _T_459) node _T_489 = or(_T_488, _T_460) node _T_490 = or(_T_489, _T_461) node _T_491 = or(_T_490, _T_462) node _T_492 = or(_T_491, _T_463) node _T_493 = or(_T_492, _T_464) node _T_494 = or(_T_493, _T_465) node _T_495 = or(_T_494, _T_466) node _T_496 = or(_T_495, _T_467) node _T_497 = or(_T_496, _T_468) node _T_498 = or(_T_497, _T_469) node _T_499 = or(_T_498, _T_470) node _T_500 = or(_T_499, _T_471) node _T_501 = or(_T_500, _T_472) node _T_502 = or(_T_501, _T_473) node _T_503 = or(_T_502, _T_474) node _T_504 = or(_T_503, _T_475) node _T_505 = or(_T_504, _T_476) node _T_506 = or(_T_505, _T_477) node _T_507 = or(_T_506, _T_478) node _T_508 = or(_T_507, _T_479) node _T_509 = or(_T_508, _T_480) node _T_510 = or(_T_509, _T_481) node _T_511 = or(_T_510, _T_482) node _T_512 = or(_T_511, _T_483) node _T_513 = or(_T_512, _T_484) node _T_514 = or(_T_513, _T_485) node _T_515 = or(_T_514, _T_486) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_515 node _T_516 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_517 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_518 = and(_T_516, _T_517) node _T_519 = or(UInt<1>(0h0), _T_518) node _T_520 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_521 = cvt(_T_520) node _T_522 = and(_T_521, asSInt(UInt<13>(0h1000))) node _T_523 = asSInt(_T_522) node _T_524 = eq(_T_523, asSInt(UInt<1>(0h0))) node _T_525 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_526 = cvt(_T_525) node _T_527 = and(_T_526, asSInt(UInt<13>(0h1000))) node _T_528 = asSInt(_T_527) node _T_529 = eq(_T_528, asSInt(UInt<1>(0h0))) node _T_530 = or(_T_524, _T_529) node _T_531 = and(_T_519, _T_530) node _T_532 = or(UInt<1>(0h0), _T_531) node _T_533 = and(_WIRE_1, _T_532) node _T_534 = asUInt(reset) node _T_535 = eq(_T_534, UInt<1>(0h0)) when _T_535 : node _T_536 = eq(_T_533, UInt<1>(0h0)) when _T_536 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_533, UInt<1>(0h1), "") : assert_3 node _T_537 = asUInt(reset) node _T_538 = eq(_T_537, UInt<1>(0h0)) when _T_538 : node _T_539 = eq(source_ok, UInt<1>(0h0)) when _T_539 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_540 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_541 = asUInt(reset) node _T_542 = eq(_T_541, UInt<1>(0h0)) when _T_542 : node _T_543 = eq(_T_540, UInt<1>(0h0)) when _T_543 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_540, UInt<1>(0h1), "") : assert_5 node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(is_aligned, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_547 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_548 = asUInt(reset) node _T_549 = eq(_T_548, UInt<1>(0h0)) when _T_549 : node _T_550 = eq(_T_547, UInt<1>(0h0)) when _T_550 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_547, UInt<1>(0h1), "") : assert_7 node _T_551 = not(io.in.a.bits.mask) node _T_552 = eq(_T_551, UInt<1>(0h0)) node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(_T_552, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_552, UInt<1>(0h1), "") : assert_8 node _T_556 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_556, UInt<1>(0h1), "") : assert_9 node _T_560 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_560 : node _T_561 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_562 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_563 = and(_T_561, _T_562) node _T_564 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_565 = shr(io.in.a.bits.source, 2) node _T_566 = eq(_T_565, UInt<1>(0h0)) node _T_567 = leq(UInt<1>(0h0), uncommonBits_12) node _T_568 = and(_T_566, _T_567) node _T_569 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_570 = and(_T_568, _T_569) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_571 = shr(io.in.a.bits.source, 2) node _T_572 = eq(_T_571, UInt<1>(0h1)) node _T_573 = leq(UInt<1>(0h0), uncommonBits_13) node _T_574 = and(_T_572, _T_573) node _T_575 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_576 = and(_T_574, _T_575) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_577 = shr(io.in.a.bits.source, 2) node _T_578 = eq(_T_577, UInt<2>(0h2)) node _T_579 = leq(UInt<1>(0h0), uncommonBits_14) node _T_580 = and(_T_578, _T_579) node _T_581 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_582 = and(_T_580, _T_581) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_583 = shr(io.in.a.bits.source, 2) node _T_584 = eq(_T_583, UInt<2>(0h3)) node _T_585 = leq(UInt<1>(0h0), uncommonBits_15) node _T_586 = and(_T_584, _T_585) node _T_587 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_588 = and(_T_586, _T_587) node _T_589 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_590 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_591 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_592 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_593 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_597 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_598 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_599 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_600 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_601 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_602 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_603 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_604 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_605 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_606 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_607 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_608 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_609 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_610 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_611 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_612 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_613 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_614 = or(_T_564, _T_570) node _T_615 = or(_T_614, _T_576) node _T_616 = or(_T_615, _T_582) node _T_617 = or(_T_616, _T_588) node _T_618 = or(_T_617, _T_589) node _T_619 = or(_T_618, _T_590) node _T_620 = or(_T_619, _T_591) node _T_621 = or(_T_620, _T_592) node _T_622 = or(_T_621, _T_593) node _T_623 = or(_T_622, _T_594) node _T_624 = or(_T_623, _T_595) node _T_625 = or(_T_624, _T_596) node _T_626 = or(_T_625, _T_597) node _T_627 = or(_T_626, _T_598) node _T_628 = or(_T_627, _T_599) node _T_629 = or(_T_628, _T_600) node _T_630 = or(_T_629, _T_601) node _T_631 = or(_T_630, _T_602) node _T_632 = or(_T_631, _T_603) node _T_633 = or(_T_632, _T_604) node _T_634 = or(_T_633, _T_605) node _T_635 = or(_T_634, _T_606) node _T_636 = or(_T_635, _T_607) node _T_637 = or(_T_636, _T_608) node _T_638 = or(_T_637, _T_609) node _T_639 = or(_T_638, _T_610) node _T_640 = or(_T_639, _T_611) node _T_641 = or(_T_640, _T_612) node _T_642 = or(_T_641, _T_613) node _T_643 = and(_T_563, _T_642) node _T_644 = or(UInt<1>(0h0), _T_643) node _T_645 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_646 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<13>(0h1000))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_652 = cvt(_T_651) node _T_653 = and(_T_652, asSInt(UInt<13>(0h1000))) node _T_654 = asSInt(_T_653) node _T_655 = eq(_T_654, asSInt(UInt<1>(0h0))) node _T_656 = or(_T_650, _T_655) node _T_657 = and(_T_645, _T_656) node _T_658 = or(UInt<1>(0h0), _T_657) node _T_659 = and(_T_644, _T_658) node _T_660 = asUInt(reset) node _T_661 = eq(_T_660, UInt<1>(0h0)) when _T_661 : node _T_662 = eq(_T_659, UInt<1>(0h0)) when _T_662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_659, UInt<1>(0h1), "") : assert_10 node _T_663 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_664 = shr(io.in.a.bits.source, 2) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = leq(UInt<1>(0h0), uncommonBits_16) node _T_667 = and(_T_665, _T_666) node _T_668 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_669 = and(_T_667, _T_668) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_670 = shr(io.in.a.bits.source, 2) node _T_671 = eq(_T_670, UInt<1>(0h1)) node _T_672 = leq(UInt<1>(0h0), uncommonBits_17) node _T_673 = and(_T_671, _T_672) node _T_674 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_675 = and(_T_673, _T_674) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_676 = shr(io.in.a.bits.source, 2) node _T_677 = eq(_T_676, UInt<2>(0h2)) node _T_678 = leq(UInt<1>(0h0), uncommonBits_18) node _T_679 = and(_T_677, _T_678) node _T_680 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_681 = and(_T_679, _T_680) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_682 = shr(io.in.a.bits.source, 2) node _T_683 = eq(_T_682, UInt<2>(0h3)) node _T_684 = leq(UInt<1>(0h0), uncommonBits_19) node _T_685 = and(_T_683, _T_684) node _T_686 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_687 = and(_T_685, _T_686) node _T_688 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_689 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_690 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_691 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_692 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_693 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_694 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_695 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_696 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_697 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_698 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_699 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_700 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_701 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_702 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_703 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_704 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_705 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_706 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_707 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_708 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_709 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_710 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_711 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_712 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[30] connect _WIRE_2[0], _T_663 connect _WIRE_2[1], _T_669 connect _WIRE_2[2], _T_675 connect _WIRE_2[3], _T_681 connect _WIRE_2[4], _T_687 connect _WIRE_2[5], _T_688 connect _WIRE_2[6], _T_689 connect _WIRE_2[7], _T_690 connect _WIRE_2[8], _T_691 connect _WIRE_2[9], _T_692 connect _WIRE_2[10], _T_693 connect _WIRE_2[11], _T_694 connect _WIRE_2[12], _T_695 connect _WIRE_2[13], _T_696 connect _WIRE_2[14], _T_697 connect _WIRE_2[15], _T_698 connect _WIRE_2[16], _T_699 connect _WIRE_2[17], _T_700 connect _WIRE_2[18], _T_701 connect _WIRE_2[19], _T_702 connect _WIRE_2[20], _T_703 connect _WIRE_2[21], _T_704 connect _WIRE_2[22], _T_705 connect _WIRE_2[23], _T_706 connect _WIRE_2[24], _T_707 connect _WIRE_2[25], _T_708 connect _WIRE_2[26], _T_709 connect _WIRE_2[27], _T_710 connect _WIRE_2[28], _T_711 connect _WIRE_2[29], _T_712 node _T_713 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_714 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_715 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_716 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_717 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_718 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_719 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_720 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_721 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_722 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_723 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_724 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_725 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_726 = mux(_WIRE_2[5], _T_713, UInt<1>(0h0)) node _T_727 = mux(_WIRE_2[6], UInt<1>(0h0), UInt<1>(0h0)) node _T_728 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_729 = mux(_WIRE_2[8], _T_714, UInt<1>(0h0)) node _T_730 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_731 = mux(_WIRE_2[10], UInt<1>(0h0), UInt<1>(0h0)) node _T_732 = mux(_WIRE_2[11], _T_715, UInt<1>(0h0)) node _T_733 = mux(_WIRE_2[12], UInt<1>(0h0), UInt<1>(0h0)) node _T_734 = mux(_WIRE_2[13], UInt<1>(0h0), UInt<1>(0h0)) node _T_735 = mux(_WIRE_2[14], _T_716, UInt<1>(0h0)) node _T_736 = mux(_WIRE_2[15], UInt<1>(0h0), UInt<1>(0h0)) node _T_737 = mux(_WIRE_2[16], UInt<1>(0h0), UInt<1>(0h0)) node _T_738 = mux(_WIRE_2[17], _T_717, UInt<1>(0h0)) node _T_739 = mux(_WIRE_2[18], UInt<1>(0h0), UInt<1>(0h0)) node _T_740 = mux(_WIRE_2[19], UInt<1>(0h0), UInt<1>(0h0)) node _T_741 = mux(_WIRE_2[20], _T_718, UInt<1>(0h0)) node _T_742 = mux(_WIRE_2[21], UInt<1>(0h0), UInt<1>(0h0)) node _T_743 = mux(_WIRE_2[22], UInt<1>(0h0), UInt<1>(0h0)) node _T_744 = mux(_WIRE_2[23], _T_719, UInt<1>(0h0)) node _T_745 = mux(_WIRE_2[24], UInt<1>(0h0), UInt<1>(0h0)) node _T_746 = mux(_WIRE_2[25], UInt<1>(0h0), UInt<1>(0h0)) node _T_747 = mux(_WIRE_2[26], _T_720, UInt<1>(0h0)) node _T_748 = mux(_WIRE_2[27], UInt<1>(0h0), UInt<1>(0h0)) node _T_749 = mux(_WIRE_2[28], UInt<1>(0h0), UInt<1>(0h0)) node _T_750 = mux(_WIRE_2[29], UInt<1>(0h0), UInt<1>(0h0)) node _T_751 = or(_T_721, _T_722) node _T_752 = or(_T_751, _T_723) node _T_753 = or(_T_752, _T_724) node _T_754 = or(_T_753, _T_725) node _T_755 = or(_T_754, _T_726) node _T_756 = or(_T_755, _T_727) node _T_757 = or(_T_756, _T_728) node _T_758 = or(_T_757, _T_729) node _T_759 = or(_T_758, _T_730) node _T_760 = or(_T_759, _T_731) node _T_761 = or(_T_760, _T_732) node _T_762 = or(_T_761, _T_733) node _T_763 = or(_T_762, _T_734) node _T_764 = or(_T_763, _T_735) node _T_765 = or(_T_764, _T_736) node _T_766 = or(_T_765, _T_737) node _T_767 = or(_T_766, _T_738) node _T_768 = or(_T_767, _T_739) node _T_769 = or(_T_768, _T_740) node _T_770 = or(_T_769, _T_741) node _T_771 = or(_T_770, _T_742) node _T_772 = or(_T_771, _T_743) node _T_773 = or(_T_772, _T_744) node _T_774 = or(_T_773, _T_745) node _T_775 = or(_T_774, _T_746) node _T_776 = or(_T_775, _T_747) node _T_777 = or(_T_776, _T_748) node _T_778 = or(_T_777, _T_749) node _T_779 = or(_T_778, _T_750) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_779 node _T_780 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_781 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_782 = and(_T_780, _T_781) node _T_783 = or(UInt<1>(0h0), _T_782) node _T_784 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_785 = cvt(_T_784) node _T_786 = and(_T_785, asSInt(UInt<13>(0h1000))) node _T_787 = asSInt(_T_786) node _T_788 = eq(_T_787, asSInt(UInt<1>(0h0))) node _T_789 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_790 = cvt(_T_789) node _T_791 = and(_T_790, asSInt(UInt<13>(0h1000))) node _T_792 = asSInt(_T_791) node _T_793 = eq(_T_792, asSInt(UInt<1>(0h0))) node _T_794 = or(_T_788, _T_793) node _T_795 = and(_T_783, _T_794) node _T_796 = or(UInt<1>(0h0), _T_795) node _T_797 = and(_WIRE_3, _T_796) node _T_798 = asUInt(reset) node _T_799 = eq(_T_798, UInt<1>(0h0)) when _T_799 : node _T_800 = eq(_T_797, UInt<1>(0h0)) when _T_800 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_797, UInt<1>(0h1), "") : assert_11 node _T_801 = asUInt(reset) node _T_802 = eq(_T_801, UInt<1>(0h0)) when _T_802 : node _T_803 = eq(source_ok, UInt<1>(0h0)) when _T_803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_804 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_805 = asUInt(reset) node _T_806 = eq(_T_805, UInt<1>(0h0)) when _T_806 : node _T_807 = eq(_T_804, UInt<1>(0h0)) when _T_807 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_804, UInt<1>(0h1), "") : assert_13 node _T_808 = asUInt(reset) node _T_809 = eq(_T_808, UInt<1>(0h0)) when _T_809 : node _T_810 = eq(is_aligned, UInt<1>(0h0)) when _T_810 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_811 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_812 = asUInt(reset) node _T_813 = eq(_T_812, UInt<1>(0h0)) when _T_813 : node _T_814 = eq(_T_811, UInt<1>(0h0)) when _T_814 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_811, UInt<1>(0h1), "") : assert_15 node _T_815 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_816 = asUInt(reset) node _T_817 = eq(_T_816, UInt<1>(0h0)) when _T_817 : node _T_818 = eq(_T_815, UInt<1>(0h0)) when _T_818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_815, UInt<1>(0h1), "") : assert_16 node _T_819 = not(io.in.a.bits.mask) node _T_820 = eq(_T_819, UInt<1>(0h0)) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_820, UInt<1>(0h1), "") : assert_17 node _T_824 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(_T_824, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_824, UInt<1>(0h1), "") : assert_18 node _T_828 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_828 : node _T_829 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_830 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_831 = and(_T_829, _T_830) node _T_832 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_833 = shr(io.in.a.bits.source, 2) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = leq(UInt<1>(0h0), uncommonBits_20) node _T_836 = and(_T_834, _T_835) node _T_837 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_839 = shr(io.in.a.bits.source, 2) node _T_840 = eq(_T_839, UInt<1>(0h1)) node _T_841 = leq(UInt<1>(0h0), uncommonBits_21) node _T_842 = and(_T_840, _T_841) node _T_843 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_844 = and(_T_842, _T_843) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_845 = shr(io.in.a.bits.source, 2) node _T_846 = eq(_T_845, UInt<2>(0h2)) node _T_847 = leq(UInt<1>(0h0), uncommonBits_22) node _T_848 = and(_T_846, _T_847) node _T_849 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_850 = and(_T_848, _T_849) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_851 = shr(io.in.a.bits.source, 2) node _T_852 = eq(_T_851, UInt<2>(0h3)) node _T_853 = leq(UInt<1>(0h0), uncommonBits_23) node _T_854 = and(_T_852, _T_853) node _T_855 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_856 = and(_T_854, _T_855) node _T_857 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_858 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_859 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_860 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_861 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_862 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_863 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_864 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_865 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_866 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_867 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_868 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_869 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_870 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_871 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_872 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_873 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_874 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_875 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_876 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_877 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_878 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_879 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_880 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_881 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_882 = or(_T_832, _T_838) node _T_883 = or(_T_882, _T_844) node _T_884 = or(_T_883, _T_850) node _T_885 = or(_T_884, _T_856) node _T_886 = or(_T_885, _T_857) node _T_887 = or(_T_886, _T_858) node _T_888 = or(_T_887, _T_859) node _T_889 = or(_T_888, _T_860) node _T_890 = or(_T_889, _T_861) node _T_891 = or(_T_890, _T_862) node _T_892 = or(_T_891, _T_863) node _T_893 = or(_T_892, _T_864) node _T_894 = or(_T_893, _T_865) node _T_895 = or(_T_894, _T_866) node _T_896 = or(_T_895, _T_867) node _T_897 = or(_T_896, _T_868) node _T_898 = or(_T_897, _T_869) node _T_899 = or(_T_898, _T_870) node _T_900 = or(_T_899, _T_871) node _T_901 = or(_T_900, _T_872) node _T_902 = or(_T_901, _T_873) node _T_903 = or(_T_902, _T_874) node _T_904 = or(_T_903, _T_875) node _T_905 = or(_T_904, _T_876) node _T_906 = or(_T_905, _T_877) node _T_907 = or(_T_906, _T_878) node _T_908 = or(_T_907, _T_879) node _T_909 = or(_T_908, _T_880) node _T_910 = or(_T_909, _T_881) node _T_911 = and(_T_831, _T_910) node _T_912 = or(UInt<1>(0h0), _T_911) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_912, UInt<1>(0h1), "") : assert_19 node _T_916 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_917 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_918 = and(_T_916, _T_917) node _T_919 = or(UInt<1>(0h0), _T_918) node _T_920 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_921 = cvt(_T_920) node _T_922 = and(_T_921, asSInt(UInt<13>(0h1000))) node _T_923 = asSInt(_T_922) node _T_924 = eq(_T_923, asSInt(UInt<1>(0h0))) node _T_925 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_926 = cvt(_T_925) node _T_927 = and(_T_926, asSInt(UInt<13>(0h1000))) node _T_928 = asSInt(_T_927) node _T_929 = eq(_T_928, asSInt(UInt<1>(0h0))) node _T_930 = or(_T_924, _T_929) node _T_931 = and(_T_919, _T_930) node _T_932 = or(UInt<1>(0h0), _T_931) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_932, UInt<1>(0h1), "") : assert_20 node _T_936 = asUInt(reset) node _T_937 = eq(_T_936, UInt<1>(0h0)) when _T_937 : node _T_938 = eq(source_ok, UInt<1>(0h0)) when _T_938 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(is_aligned, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_942 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_942, UInt<1>(0h1), "") : assert_23 node _T_946 = eq(io.in.a.bits.mask, mask) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_946, UInt<1>(0h1), "") : assert_24 node _T_950 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_951 = asUInt(reset) node _T_952 = eq(_T_951, UInt<1>(0h0)) when _T_952 : node _T_953 = eq(_T_950, UInt<1>(0h0)) when _T_953 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_950, UInt<1>(0h1), "") : assert_25 node _T_954 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_954 : node _T_955 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_956 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_957 = and(_T_955, _T_956) node _T_958 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_959 = shr(io.in.a.bits.source, 2) node _T_960 = eq(_T_959, UInt<1>(0h0)) node _T_961 = leq(UInt<1>(0h0), uncommonBits_24) node _T_962 = and(_T_960, _T_961) node _T_963 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_964 = and(_T_962, _T_963) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_965 = shr(io.in.a.bits.source, 2) node _T_966 = eq(_T_965, UInt<1>(0h1)) node _T_967 = leq(UInt<1>(0h0), uncommonBits_25) node _T_968 = and(_T_966, _T_967) node _T_969 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_970 = and(_T_968, _T_969) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_971 = shr(io.in.a.bits.source, 2) node _T_972 = eq(_T_971, UInt<2>(0h2)) node _T_973 = leq(UInt<1>(0h0), uncommonBits_26) node _T_974 = and(_T_972, _T_973) node _T_975 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_976 = and(_T_974, _T_975) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_977 = shr(io.in.a.bits.source, 2) node _T_978 = eq(_T_977, UInt<2>(0h3)) node _T_979 = leq(UInt<1>(0h0), uncommonBits_27) node _T_980 = and(_T_978, _T_979) node _T_981 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_982 = and(_T_980, _T_981) node _T_983 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_984 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_985 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_986 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_987 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_988 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_989 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_990 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_991 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_992 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_993 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_994 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_995 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_996 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_997 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_998 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_999 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1000 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1001 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1002 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1003 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1004 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1005 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1006 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1007 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1008 = or(_T_958, _T_964) node _T_1009 = or(_T_1008, _T_970) node _T_1010 = or(_T_1009, _T_976) node _T_1011 = or(_T_1010, _T_982) node _T_1012 = or(_T_1011, _T_983) node _T_1013 = or(_T_1012, _T_984) node _T_1014 = or(_T_1013, _T_985) node _T_1015 = or(_T_1014, _T_986) node _T_1016 = or(_T_1015, _T_987) node _T_1017 = or(_T_1016, _T_988) node _T_1018 = or(_T_1017, _T_989) node _T_1019 = or(_T_1018, _T_990) node _T_1020 = or(_T_1019, _T_991) node _T_1021 = or(_T_1020, _T_992) node _T_1022 = or(_T_1021, _T_993) node _T_1023 = or(_T_1022, _T_994) node _T_1024 = or(_T_1023, _T_995) node _T_1025 = or(_T_1024, _T_996) node _T_1026 = or(_T_1025, _T_997) node _T_1027 = or(_T_1026, _T_998) node _T_1028 = or(_T_1027, _T_999) node _T_1029 = or(_T_1028, _T_1000) node _T_1030 = or(_T_1029, _T_1001) node _T_1031 = or(_T_1030, _T_1002) node _T_1032 = or(_T_1031, _T_1003) node _T_1033 = or(_T_1032, _T_1004) node _T_1034 = or(_T_1033, _T_1005) node _T_1035 = or(_T_1034, _T_1006) node _T_1036 = or(_T_1035, _T_1007) node _T_1037 = and(_T_957, _T_1036) node _T_1038 = or(UInt<1>(0h0), _T_1037) node _T_1039 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1040 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1041 = and(_T_1039, _T_1040) node _T_1042 = or(UInt<1>(0h0), _T_1041) node _T_1043 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1044 = cvt(_T_1043) node _T_1045 = and(_T_1044, asSInt(UInt<13>(0h1000))) node _T_1046 = asSInt(_T_1045) node _T_1047 = eq(_T_1046, asSInt(UInt<1>(0h0))) node _T_1048 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1049 = cvt(_T_1048) node _T_1050 = and(_T_1049, asSInt(UInt<13>(0h1000))) node _T_1051 = asSInt(_T_1050) node _T_1052 = eq(_T_1051, asSInt(UInt<1>(0h0))) node _T_1053 = or(_T_1047, _T_1052) node _T_1054 = and(_T_1042, _T_1053) node _T_1055 = or(UInt<1>(0h0), _T_1054) node _T_1056 = and(_T_1038, _T_1055) node _T_1057 = asUInt(reset) node _T_1058 = eq(_T_1057, UInt<1>(0h0)) when _T_1058 : node _T_1059 = eq(_T_1056, UInt<1>(0h0)) when _T_1059 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_1056, UInt<1>(0h1), "") : assert_26 node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(source_ok, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(is_aligned, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_1066 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(_T_1066, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_1066, UInt<1>(0h1), "") : assert_29 node _T_1070 = eq(io.in.a.bits.mask, mask) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_30 node _T_1074 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_1074 : node _T_1075 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1076 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1077 = and(_T_1075, _T_1076) node _T_1078 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_1079 = shr(io.in.a.bits.source, 2) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_28) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_1085 = shr(io.in.a.bits.source, 2) node _T_1086 = eq(_T_1085, UInt<1>(0h1)) node _T_1087 = leq(UInt<1>(0h0), uncommonBits_29) node _T_1088 = and(_T_1086, _T_1087) node _T_1089 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_1090 = and(_T_1088, _T_1089) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_1091 = shr(io.in.a.bits.source, 2) node _T_1092 = eq(_T_1091, UInt<2>(0h2)) node _T_1093 = leq(UInt<1>(0h0), uncommonBits_30) node _T_1094 = and(_T_1092, _T_1093) node _T_1095 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_1096 = and(_T_1094, _T_1095) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_1097 = shr(io.in.a.bits.source, 2) node _T_1098 = eq(_T_1097, UInt<2>(0h3)) node _T_1099 = leq(UInt<1>(0h0), uncommonBits_31) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1104 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1105 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1106 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1107 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1108 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1109 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1110 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1111 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1112 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1113 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1114 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1115 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1116 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1117 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1118 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1119 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1120 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1121 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1122 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1123 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1124 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1125 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1126 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1127 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1128 = or(_T_1078, _T_1084) node _T_1129 = or(_T_1128, _T_1090) node _T_1130 = or(_T_1129, _T_1096) node _T_1131 = or(_T_1130, _T_1102) node _T_1132 = or(_T_1131, _T_1103) node _T_1133 = or(_T_1132, _T_1104) node _T_1134 = or(_T_1133, _T_1105) node _T_1135 = or(_T_1134, _T_1106) node _T_1136 = or(_T_1135, _T_1107) node _T_1137 = or(_T_1136, _T_1108) node _T_1138 = or(_T_1137, _T_1109) node _T_1139 = or(_T_1138, _T_1110) node _T_1140 = or(_T_1139, _T_1111) node _T_1141 = or(_T_1140, _T_1112) node _T_1142 = or(_T_1141, _T_1113) node _T_1143 = or(_T_1142, _T_1114) node _T_1144 = or(_T_1143, _T_1115) node _T_1145 = or(_T_1144, _T_1116) node _T_1146 = or(_T_1145, _T_1117) node _T_1147 = or(_T_1146, _T_1118) node _T_1148 = or(_T_1147, _T_1119) node _T_1149 = or(_T_1148, _T_1120) node _T_1150 = or(_T_1149, _T_1121) node _T_1151 = or(_T_1150, _T_1122) node _T_1152 = or(_T_1151, _T_1123) node _T_1153 = or(_T_1152, _T_1124) node _T_1154 = or(_T_1153, _T_1125) node _T_1155 = or(_T_1154, _T_1126) node _T_1156 = or(_T_1155, _T_1127) node _T_1157 = and(_T_1077, _T_1156) node _T_1158 = or(UInt<1>(0h0), _T_1157) node _T_1159 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1160 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1161 = and(_T_1159, _T_1160) node _T_1162 = or(UInt<1>(0h0), _T_1161) node _T_1163 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1164 = cvt(_T_1163) node _T_1165 = and(_T_1164, asSInt(UInt<13>(0h1000))) node _T_1166 = asSInt(_T_1165) node _T_1167 = eq(_T_1166, asSInt(UInt<1>(0h0))) node _T_1168 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1169 = cvt(_T_1168) node _T_1170 = and(_T_1169, asSInt(UInt<13>(0h1000))) node _T_1171 = asSInt(_T_1170) node _T_1172 = eq(_T_1171, asSInt(UInt<1>(0h0))) node _T_1173 = or(_T_1167, _T_1172) node _T_1174 = and(_T_1162, _T_1173) node _T_1175 = or(UInt<1>(0h0), _T_1174) node _T_1176 = and(_T_1158, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_31 node _T_1180 = asUInt(reset) node _T_1181 = eq(_T_1180, UInt<1>(0h0)) when _T_1181 : node _T_1182 = eq(source_ok, UInt<1>(0h0)) when _T_1182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(is_aligned, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_1186 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_34 node _T_1190 = not(mask) node _T_1191 = and(io.in.a.bits.mask, _T_1190) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) node _T_1193 = asUInt(reset) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(_T_1192, UInt<1>(0h0)) when _T_1195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_1192, UInt<1>(0h1), "") : assert_35 node _T_1196 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_1196 : node _T_1197 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1198 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1199 = and(_T_1197, _T_1198) node _T_1200 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1201 = shr(io.in.a.bits.source, 2) node _T_1202 = eq(_T_1201, UInt<1>(0h0)) node _T_1203 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1206 = and(_T_1204, _T_1205) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1207 = shr(io.in.a.bits.source, 2) node _T_1208 = eq(_T_1207, UInt<1>(0h1)) node _T_1209 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1210 = and(_T_1208, _T_1209) node _T_1211 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1212 = and(_T_1210, _T_1211) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1213 = shr(io.in.a.bits.source, 2) node _T_1214 = eq(_T_1213, UInt<2>(0h2)) node _T_1215 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1216 = and(_T_1214, _T_1215) node _T_1217 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1218 = and(_T_1216, _T_1217) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1219 = shr(io.in.a.bits.source, 2) node _T_1220 = eq(_T_1219, UInt<2>(0h3)) node _T_1221 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1222 = and(_T_1220, _T_1221) node _T_1223 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1224 = and(_T_1222, _T_1223) node _T_1225 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1226 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1227 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1228 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1229 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1230 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1231 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1232 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1233 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1234 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1235 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1236 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1237 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1238 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1239 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1240 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1241 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1242 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1243 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1244 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1245 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1246 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1247 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1248 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1249 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1250 = or(_T_1200, _T_1206) node _T_1251 = or(_T_1250, _T_1212) node _T_1252 = or(_T_1251, _T_1218) node _T_1253 = or(_T_1252, _T_1224) node _T_1254 = or(_T_1253, _T_1225) node _T_1255 = or(_T_1254, _T_1226) node _T_1256 = or(_T_1255, _T_1227) node _T_1257 = or(_T_1256, _T_1228) node _T_1258 = or(_T_1257, _T_1229) node _T_1259 = or(_T_1258, _T_1230) node _T_1260 = or(_T_1259, _T_1231) node _T_1261 = or(_T_1260, _T_1232) node _T_1262 = or(_T_1261, _T_1233) node _T_1263 = or(_T_1262, _T_1234) node _T_1264 = or(_T_1263, _T_1235) node _T_1265 = or(_T_1264, _T_1236) node _T_1266 = or(_T_1265, _T_1237) node _T_1267 = or(_T_1266, _T_1238) node _T_1268 = or(_T_1267, _T_1239) node _T_1269 = or(_T_1268, _T_1240) node _T_1270 = or(_T_1269, _T_1241) node _T_1271 = or(_T_1270, _T_1242) node _T_1272 = or(_T_1271, _T_1243) node _T_1273 = or(_T_1272, _T_1244) node _T_1274 = or(_T_1273, _T_1245) node _T_1275 = or(_T_1274, _T_1246) node _T_1276 = or(_T_1275, _T_1247) node _T_1277 = or(_T_1276, _T_1248) node _T_1278 = or(_T_1277, _T_1249) node _T_1279 = and(_T_1199, _T_1278) node _T_1280 = or(UInt<1>(0h0), _T_1279) node _T_1281 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1282 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1283 = and(_T_1281, _T_1282) node _T_1284 = or(UInt<1>(0h0), _T_1283) node _T_1285 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1286 = cvt(_T_1285) node _T_1287 = and(_T_1286, asSInt(UInt<13>(0h1000))) node _T_1288 = asSInt(_T_1287) node _T_1289 = eq(_T_1288, asSInt(UInt<1>(0h0))) node _T_1290 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1291 = cvt(_T_1290) node _T_1292 = and(_T_1291, asSInt(UInt<13>(0h1000))) node _T_1293 = asSInt(_T_1292) node _T_1294 = eq(_T_1293, asSInt(UInt<1>(0h0))) node _T_1295 = or(_T_1289, _T_1294) node _T_1296 = and(_T_1284, _T_1295) node _T_1297 = or(UInt<1>(0h0), _T_1296) node _T_1298 = and(_T_1280, _T_1297) node _T_1299 = asUInt(reset) node _T_1300 = eq(_T_1299, UInt<1>(0h0)) when _T_1300 : node _T_1301 = eq(_T_1298, UInt<1>(0h0)) when _T_1301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_1298, UInt<1>(0h1), "") : assert_36 node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(source_ok, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(is_aligned, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_1308 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_1309 = asUInt(reset) node _T_1310 = eq(_T_1309, UInt<1>(0h0)) when _T_1310 : node _T_1311 = eq(_T_1308, UInt<1>(0h0)) when _T_1311 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_1308, UInt<1>(0h1), "") : assert_39 node _T_1312 = eq(io.in.a.bits.mask, mask) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_40 node _T_1316 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_1316 : node _T_1317 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1318 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1319 = and(_T_1317, _T_1318) node _T_1320 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_1321 = shr(io.in.a.bits.source, 2) node _T_1322 = eq(_T_1321, UInt<1>(0h0)) node _T_1323 = leq(UInt<1>(0h0), uncommonBits_36) node _T_1324 = and(_T_1322, _T_1323) node _T_1325 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_1326 = and(_T_1324, _T_1325) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_1327 = shr(io.in.a.bits.source, 2) node _T_1328 = eq(_T_1327, UInt<1>(0h1)) node _T_1329 = leq(UInt<1>(0h0), uncommonBits_37) node _T_1330 = and(_T_1328, _T_1329) node _T_1331 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_1332 = and(_T_1330, _T_1331) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_1333 = shr(io.in.a.bits.source, 2) node _T_1334 = eq(_T_1333, UInt<2>(0h2)) node _T_1335 = leq(UInt<1>(0h0), uncommonBits_38) node _T_1336 = and(_T_1334, _T_1335) node _T_1337 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_1338 = and(_T_1336, _T_1337) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_1339 = shr(io.in.a.bits.source, 2) node _T_1340 = eq(_T_1339, UInt<2>(0h3)) node _T_1341 = leq(UInt<1>(0h0), uncommonBits_39) node _T_1342 = and(_T_1340, _T_1341) node _T_1343 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_1344 = and(_T_1342, _T_1343) node _T_1345 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1346 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1347 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1348 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1349 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1350 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1351 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1352 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1353 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1354 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1355 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1356 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1357 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1358 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1359 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1360 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1361 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1362 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1363 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1364 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1365 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1366 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1367 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1368 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1369 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1370 = or(_T_1320, _T_1326) node _T_1371 = or(_T_1370, _T_1332) node _T_1372 = or(_T_1371, _T_1338) node _T_1373 = or(_T_1372, _T_1344) node _T_1374 = or(_T_1373, _T_1345) node _T_1375 = or(_T_1374, _T_1346) node _T_1376 = or(_T_1375, _T_1347) node _T_1377 = or(_T_1376, _T_1348) node _T_1378 = or(_T_1377, _T_1349) node _T_1379 = or(_T_1378, _T_1350) node _T_1380 = or(_T_1379, _T_1351) node _T_1381 = or(_T_1380, _T_1352) node _T_1382 = or(_T_1381, _T_1353) node _T_1383 = or(_T_1382, _T_1354) node _T_1384 = or(_T_1383, _T_1355) node _T_1385 = or(_T_1384, _T_1356) node _T_1386 = or(_T_1385, _T_1357) node _T_1387 = or(_T_1386, _T_1358) node _T_1388 = or(_T_1387, _T_1359) node _T_1389 = or(_T_1388, _T_1360) node _T_1390 = or(_T_1389, _T_1361) node _T_1391 = or(_T_1390, _T_1362) node _T_1392 = or(_T_1391, _T_1363) node _T_1393 = or(_T_1392, _T_1364) node _T_1394 = or(_T_1393, _T_1365) node _T_1395 = or(_T_1394, _T_1366) node _T_1396 = or(_T_1395, _T_1367) node _T_1397 = or(_T_1396, _T_1368) node _T_1398 = or(_T_1397, _T_1369) node _T_1399 = and(_T_1319, _T_1398) node _T_1400 = or(UInt<1>(0h0), _T_1399) node _T_1401 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1402 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_1403 = and(_T_1401, _T_1402) node _T_1404 = or(UInt<1>(0h0), _T_1403) node _T_1405 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1406 = cvt(_T_1405) node _T_1407 = and(_T_1406, asSInt(UInt<13>(0h1000))) node _T_1408 = asSInt(_T_1407) node _T_1409 = eq(_T_1408, asSInt(UInt<1>(0h0))) node _T_1410 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1411 = cvt(_T_1410) node _T_1412 = and(_T_1411, asSInt(UInt<13>(0h1000))) node _T_1413 = asSInt(_T_1412) node _T_1414 = eq(_T_1413, asSInt(UInt<1>(0h0))) node _T_1415 = or(_T_1409, _T_1414) node _T_1416 = and(_T_1404, _T_1415) node _T_1417 = or(UInt<1>(0h0), _T_1416) node _T_1418 = and(_T_1400, _T_1417) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_41 node _T_1422 = asUInt(reset) node _T_1423 = eq(_T_1422, UInt<1>(0h0)) when _T_1423 : node _T_1424 = eq(source_ok, UInt<1>(0h0)) when _T_1424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1425 = asUInt(reset) node _T_1426 = eq(_T_1425, UInt<1>(0h0)) when _T_1426 : node _T_1427 = eq(is_aligned, UInt<1>(0h0)) when _T_1427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1428 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1429 = asUInt(reset) node _T_1430 = eq(_T_1429, UInt<1>(0h0)) when _T_1430 : node _T_1431 = eq(_T_1428, UInt<1>(0h0)) when _T_1431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1428, UInt<1>(0h1), "") : assert_44 node _T_1432 = eq(io.in.a.bits.mask, mask) node _T_1433 = asUInt(reset) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(_T_1432, UInt<1>(0h0)) when _T_1435 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1432, UInt<1>(0h1), "") : assert_45 node _T_1436 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1436 : node _T_1437 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1438 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1439 = and(_T_1437, _T_1438) node _T_1440 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_1441 = shr(io.in.a.bits.source, 2) node _T_1442 = eq(_T_1441, UInt<1>(0h0)) node _T_1443 = leq(UInt<1>(0h0), uncommonBits_40) node _T_1444 = and(_T_1442, _T_1443) node _T_1445 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_1446 = and(_T_1444, _T_1445) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_1447 = shr(io.in.a.bits.source, 2) node _T_1448 = eq(_T_1447, UInt<1>(0h1)) node _T_1449 = leq(UInt<1>(0h0), uncommonBits_41) node _T_1450 = and(_T_1448, _T_1449) node _T_1451 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_1452 = and(_T_1450, _T_1451) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_1453 = shr(io.in.a.bits.source, 2) node _T_1454 = eq(_T_1453, UInt<2>(0h2)) node _T_1455 = leq(UInt<1>(0h0), uncommonBits_42) node _T_1456 = and(_T_1454, _T_1455) node _T_1457 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_1458 = and(_T_1456, _T_1457) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_1459 = shr(io.in.a.bits.source, 2) node _T_1460 = eq(_T_1459, UInt<2>(0h3)) node _T_1461 = leq(UInt<1>(0h0), uncommonBits_43) node _T_1462 = and(_T_1460, _T_1461) node _T_1463 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_1464 = and(_T_1462, _T_1463) node _T_1465 = eq(io.in.a.bits.source, UInt<6>(0h3c)) node _T_1466 = eq(io.in.a.bits.source, UInt<6>(0h3d)) node _T_1467 = eq(io.in.a.bits.source, UInt<6>(0h3e)) node _T_1468 = eq(io.in.a.bits.source, UInt<6>(0h38)) node _T_1469 = eq(io.in.a.bits.source, UInt<6>(0h39)) node _T_1470 = eq(io.in.a.bits.source, UInt<6>(0h3a)) node _T_1471 = eq(io.in.a.bits.source, UInt<6>(0h34)) node _T_1472 = eq(io.in.a.bits.source, UInt<6>(0h35)) node _T_1473 = eq(io.in.a.bits.source, UInt<6>(0h36)) node _T_1474 = eq(io.in.a.bits.source, UInt<6>(0h30)) node _T_1475 = eq(io.in.a.bits.source, UInt<6>(0h31)) node _T_1476 = eq(io.in.a.bits.source, UInt<6>(0h32)) node _T_1477 = eq(io.in.a.bits.source, UInt<6>(0h2c)) node _T_1478 = eq(io.in.a.bits.source, UInt<6>(0h2d)) node _T_1479 = eq(io.in.a.bits.source, UInt<6>(0h2e)) node _T_1480 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_1481 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_1482 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_1483 = eq(io.in.a.bits.source, UInt<6>(0h24)) node _T_1484 = eq(io.in.a.bits.source, UInt<6>(0h25)) node _T_1485 = eq(io.in.a.bits.source, UInt<6>(0h26)) node _T_1486 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_1487 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_1488 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_1489 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_1490 = or(_T_1440, _T_1446) node _T_1491 = or(_T_1490, _T_1452) node _T_1492 = or(_T_1491, _T_1458) node _T_1493 = or(_T_1492, _T_1464) node _T_1494 = or(_T_1493, _T_1465) node _T_1495 = or(_T_1494, _T_1466) node _T_1496 = or(_T_1495, _T_1467) node _T_1497 = or(_T_1496, _T_1468) node _T_1498 = or(_T_1497, _T_1469) node _T_1499 = or(_T_1498, _T_1470) node _T_1500 = or(_T_1499, _T_1471) node _T_1501 = or(_T_1500, _T_1472) node _T_1502 = or(_T_1501, _T_1473) node _T_1503 = or(_T_1502, _T_1474) node _T_1504 = or(_T_1503, _T_1475) node _T_1505 = or(_T_1504, _T_1476) node _T_1506 = or(_T_1505, _T_1477) node _T_1507 = or(_T_1506, _T_1478) node _T_1508 = or(_T_1507, _T_1479) node _T_1509 = or(_T_1508, _T_1480) node _T_1510 = or(_T_1509, _T_1481) node _T_1511 = or(_T_1510, _T_1482) node _T_1512 = or(_T_1511, _T_1483) node _T_1513 = or(_T_1512, _T_1484) node _T_1514 = or(_T_1513, _T_1485) node _T_1515 = or(_T_1514, _T_1486) node _T_1516 = or(_T_1515, _T_1487) node _T_1517 = or(_T_1516, _T_1488) node _T_1518 = or(_T_1517, _T_1489) node _T_1519 = and(_T_1439, _T_1518) node _T_1520 = or(UInt<1>(0h0), _T_1519) node _T_1521 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1522 = xor(io.in.a.bits.address, UInt<13>(0h1000)) node _T_1523 = cvt(_T_1522) node _T_1524 = and(_T_1523, asSInt(UInt<13>(0h1000))) node _T_1525 = asSInt(_T_1524) node _T_1526 = eq(_T_1525, asSInt(UInt<1>(0h0))) node _T_1527 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1528 = cvt(_T_1527) node _T_1529 = and(_T_1528, asSInt(UInt<13>(0h1000))) node _T_1530 = asSInt(_T_1529) node _T_1531 = eq(_T_1530, asSInt(UInt<1>(0h0))) node _T_1532 = or(_T_1526, _T_1531) node _T_1533 = and(_T_1521, _T_1532) node _T_1534 = or(UInt<1>(0h0), _T_1533) node _T_1535 = and(_T_1520, _T_1534) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_46 node _T_1539 = asUInt(reset) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) when _T_1540 : node _T_1541 = eq(source_ok, UInt<1>(0h0)) when _T_1541 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1542 = asUInt(reset) node _T_1543 = eq(_T_1542, UInt<1>(0h0)) when _T_1543 : node _T_1544 = eq(is_aligned, UInt<1>(0h0)) when _T_1544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1545 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1546 = asUInt(reset) node _T_1547 = eq(_T_1546, UInt<1>(0h0)) when _T_1547 : node _T_1548 = eq(_T_1545, UInt<1>(0h0)) when _T_1548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1545, UInt<1>(0h1), "") : assert_49 node _T_1549 = eq(io.in.a.bits.mask, mask) node _T_1550 = asUInt(reset) node _T_1551 = eq(_T_1550, UInt<1>(0h0)) when _T_1551 : node _T_1552 = eq(_T_1549, UInt<1>(0h0)) when _T_1552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1549, UInt<1>(0h1), "") : assert_50 node _T_1553 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1554 = asUInt(reset) node _T_1555 = eq(_T_1554, UInt<1>(0h0)) when _T_1555 : node _T_1556 = eq(_T_1553, UInt<1>(0h0)) when _T_1556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1553, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1557 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1558 = asUInt(reset) node _T_1559 = eq(_T_1558, UInt<1>(0h0)) when _T_1559 : node _T_1560 = eq(_T_1557, UInt<1>(0h0)) when _T_1560 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1557, UInt<1>(0h1), "") : assert_52 node _source_ok_T_78 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_79 = shr(io.in.d.bits.source, 2) node _source_ok_T_80 = eq(_source_ok_T_79, UInt<1>(0h0)) node _source_ok_T_81 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_82 = and(_source_ok_T_80, _source_ok_T_81) node _source_ok_T_83 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_84 = and(_source_ok_T_82, _source_ok_T_83) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_85 = shr(io.in.d.bits.source, 2) node _source_ok_T_86 = eq(_source_ok_T_85, UInt<1>(0h1)) node _source_ok_T_87 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_88 = and(_source_ok_T_86, _source_ok_T_87) node _source_ok_T_89 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_90 = and(_source_ok_T_88, _source_ok_T_89) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_91 = shr(io.in.d.bits.source, 2) node _source_ok_T_92 = eq(_source_ok_T_91, UInt<2>(0h2)) node _source_ok_T_93 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_94 = and(_source_ok_T_92, _source_ok_T_93) node _source_ok_T_95 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_96 = and(_source_ok_T_94, _source_ok_T_95) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_97 = shr(io.in.d.bits.source, 2) node _source_ok_T_98 = eq(_source_ok_T_97, UInt<2>(0h3)) node _source_ok_T_99 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_100 = and(_source_ok_T_98, _source_ok_T_99) node _source_ok_T_101 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_102 = and(_source_ok_T_100, _source_ok_T_101) node _source_ok_T_103 = eq(io.in.d.bits.source, UInt<6>(0h3c)) node _source_ok_T_104 = eq(io.in.d.bits.source, UInt<6>(0h3d)) node _source_ok_T_105 = eq(io.in.d.bits.source, UInt<6>(0h3e)) node _source_ok_T_106 = eq(io.in.d.bits.source, UInt<6>(0h38)) node _source_ok_T_107 = eq(io.in.d.bits.source, UInt<6>(0h39)) node _source_ok_T_108 = eq(io.in.d.bits.source, UInt<6>(0h3a)) node _source_ok_T_109 = eq(io.in.d.bits.source, UInt<6>(0h34)) node _source_ok_T_110 = eq(io.in.d.bits.source, UInt<6>(0h35)) node _source_ok_T_111 = eq(io.in.d.bits.source, UInt<6>(0h36)) node _source_ok_T_112 = eq(io.in.d.bits.source, UInt<6>(0h30)) node _source_ok_T_113 = eq(io.in.d.bits.source, UInt<6>(0h31)) node _source_ok_T_114 = eq(io.in.d.bits.source, UInt<6>(0h32)) node _source_ok_T_115 = eq(io.in.d.bits.source, UInt<6>(0h2c)) node _source_ok_T_116 = eq(io.in.d.bits.source, UInt<6>(0h2d)) node _source_ok_T_117 = eq(io.in.d.bits.source, UInt<6>(0h2e)) node _source_ok_T_118 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_119 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_120 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_121 = eq(io.in.d.bits.source, UInt<6>(0h24)) node _source_ok_T_122 = eq(io.in.d.bits.source, UInt<6>(0h25)) node _source_ok_T_123 = eq(io.in.d.bits.source, UInt<6>(0h26)) node _source_ok_T_124 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_125 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_126 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_127 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[30] connect _source_ok_WIRE_1[0], _source_ok_T_78 connect _source_ok_WIRE_1[1], _source_ok_T_84 connect _source_ok_WIRE_1[2], _source_ok_T_90 connect _source_ok_WIRE_1[3], _source_ok_T_96 connect _source_ok_WIRE_1[4], _source_ok_T_102 connect _source_ok_WIRE_1[5], _source_ok_T_103 connect _source_ok_WIRE_1[6], _source_ok_T_104 connect _source_ok_WIRE_1[7], _source_ok_T_105 connect _source_ok_WIRE_1[8], _source_ok_T_106 connect _source_ok_WIRE_1[9], _source_ok_T_107 connect _source_ok_WIRE_1[10], _source_ok_T_108 connect _source_ok_WIRE_1[11], _source_ok_T_109 connect _source_ok_WIRE_1[12], _source_ok_T_110 connect _source_ok_WIRE_1[13], _source_ok_T_111 connect _source_ok_WIRE_1[14], _source_ok_T_112 connect _source_ok_WIRE_1[15], _source_ok_T_113 connect _source_ok_WIRE_1[16], _source_ok_T_114 connect _source_ok_WIRE_1[17], _source_ok_T_115 connect _source_ok_WIRE_1[18], _source_ok_T_116 connect _source_ok_WIRE_1[19], _source_ok_T_117 connect _source_ok_WIRE_1[20], _source_ok_T_118 connect _source_ok_WIRE_1[21], _source_ok_T_119 connect _source_ok_WIRE_1[22], _source_ok_T_120 connect _source_ok_WIRE_1[23], _source_ok_T_121 connect _source_ok_WIRE_1[24], _source_ok_T_122 connect _source_ok_WIRE_1[25], _source_ok_T_123 connect _source_ok_WIRE_1[26], _source_ok_T_124 connect _source_ok_WIRE_1[27], _source_ok_T_125 connect _source_ok_WIRE_1[28], _source_ok_T_126 connect _source_ok_WIRE_1[29], _source_ok_T_127 node _source_ok_T_128 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_129 = or(_source_ok_T_128, _source_ok_WIRE_1[2]) node _source_ok_T_130 = or(_source_ok_T_129, _source_ok_WIRE_1[3]) node _source_ok_T_131 = or(_source_ok_T_130, _source_ok_WIRE_1[4]) node _source_ok_T_132 = or(_source_ok_T_131, _source_ok_WIRE_1[5]) node _source_ok_T_133 = or(_source_ok_T_132, _source_ok_WIRE_1[6]) node _source_ok_T_134 = or(_source_ok_T_133, _source_ok_WIRE_1[7]) node _source_ok_T_135 = or(_source_ok_T_134, _source_ok_WIRE_1[8]) node _source_ok_T_136 = or(_source_ok_T_135, _source_ok_WIRE_1[9]) node _source_ok_T_137 = or(_source_ok_T_136, _source_ok_WIRE_1[10]) node _source_ok_T_138 = or(_source_ok_T_137, _source_ok_WIRE_1[11]) node _source_ok_T_139 = or(_source_ok_T_138, _source_ok_WIRE_1[12]) node _source_ok_T_140 = or(_source_ok_T_139, _source_ok_WIRE_1[13]) node _source_ok_T_141 = or(_source_ok_T_140, _source_ok_WIRE_1[14]) node _source_ok_T_142 = or(_source_ok_T_141, _source_ok_WIRE_1[15]) node _source_ok_T_143 = or(_source_ok_T_142, _source_ok_WIRE_1[16]) node _source_ok_T_144 = or(_source_ok_T_143, _source_ok_WIRE_1[17]) node _source_ok_T_145 = or(_source_ok_T_144, _source_ok_WIRE_1[18]) node _source_ok_T_146 = or(_source_ok_T_145, _source_ok_WIRE_1[19]) node _source_ok_T_147 = or(_source_ok_T_146, _source_ok_WIRE_1[20]) node _source_ok_T_148 = or(_source_ok_T_147, _source_ok_WIRE_1[21]) node _source_ok_T_149 = or(_source_ok_T_148, _source_ok_WIRE_1[22]) node _source_ok_T_150 = or(_source_ok_T_149, _source_ok_WIRE_1[23]) node _source_ok_T_151 = or(_source_ok_T_150, _source_ok_WIRE_1[24]) node _source_ok_T_152 = or(_source_ok_T_151, _source_ok_WIRE_1[25]) node _source_ok_T_153 = or(_source_ok_T_152, _source_ok_WIRE_1[26]) node _source_ok_T_154 = or(_source_ok_T_153, _source_ok_WIRE_1[27]) node _source_ok_T_155 = or(_source_ok_T_154, _source_ok_WIRE_1[28]) node source_ok_1 = or(_source_ok_T_155, _source_ok_WIRE_1[29]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_1561 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1561 : node _T_1562 = asUInt(reset) node _T_1563 = eq(_T_1562, UInt<1>(0h0)) when _T_1563 : node _T_1564 = eq(source_ok_1, UInt<1>(0h0)) when _T_1564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1565 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1566 = asUInt(reset) node _T_1567 = eq(_T_1566, UInt<1>(0h0)) when _T_1567 : node _T_1568 = eq(_T_1565, UInt<1>(0h0)) when _T_1568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1565, UInt<1>(0h1), "") : assert_54 node _T_1569 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1570 = asUInt(reset) node _T_1571 = eq(_T_1570, UInt<1>(0h0)) when _T_1571 : node _T_1572 = eq(_T_1569, UInt<1>(0h0)) when _T_1572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1569, UInt<1>(0h1), "") : assert_55 node _T_1573 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1574 = asUInt(reset) node _T_1575 = eq(_T_1574, UInt<1>(0h0)) when _T_1575 : node _T_1576 = eq(_T_1573, UInt<1>(0h0)) when _T_1576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1573, UInt<1>(0h1), "") : assert_56 node _T_1577 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1578 = asUInt(reset) node _T_1579 = eq(_T_1578, UInt<1>(0h0)) when _T_1579 : node _T_1580 = eq(_T_1577, UInt<1>(0h0)) when _T_1580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1577, UInt<1>(0h1), "") : assert_57 node _T_1581 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1581 : node _T_1582 = asUInt(reset) node _T_1583 = eq(_T_1582, UInt<1>(0h0)) when _T_1583 : node _T_1584 = eq(source_ok_1, UInt<1>(0h0)) when _T_1584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1585 = asUInt(reset) node _T_1586 = eq(_T_1585, UInt<1>(0h0)) when _T_1586 : node _T_1587 = eq(sink_ok, UInt<1>(0h0)) when _T_1587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1588 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1589 = asUInt(reset) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(_T_1588, UInt<1>(0h0)) when _T_1591 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1588, UInt<1>(0h1), "") : assert_60 node _T_1592 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1593 = asUInt(reset) node _T_1594 = eq(_T_1593, UInt<1>(0h0)) when _T_1594 : node _T_1595 = eq(_T_1592, UInt<1>(0h0)) when _T_1595 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1592, UInt<1>(0h1), "") : assert_61 node _T_1596 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1597 = asUInt(reset) node _T_1598 = eq(_T_1597, UInt<1>(0h0)) when _T_1598 : node _T_1599 = eq(_T_1596, UInt<1>(0h0)) when _T_1599 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1596, UInt<1>(0h1), "") : assert_62 node _T_1600 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1601 = asUInt(reset) node _T_1602 = eq(_T_1601, UInt<1>(0h0)) when _T_1602 : node _T_1603 = eq(_T_1600, UInt<1>(0h0)) when _T_1603 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1600, UInt<1>(0h1), "") : assert_63 node _T_1604 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1605 = or(UInt<1>(0h0), _T_1604) node _T_1606 = asUInt(reset) node _T_1607 = eq(_T_1606, UInt<1>(0h0)) when _T_1607 : node _T_1608 = eq(_T_1605, UInt<1>(0h0)) when _T_1608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1605, UInt<1>(0h1), "") : assert_64 node _T_1609 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1609 : node _T_1610 = asUInt(reset) node _T_1611 = eq(_T_1610, UInt<1>(0h0)) when _T_1611 : node _T_1612 = eq(source_ok_1, UInt<1>(0h0)) when _T_1612 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1613 = asUInt(reset) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(sink_ok, UInt<1>(0h0)) when _T_1615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1616 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1617 = asUInt(reset) node _T_1618 = eq(_T_1617, UInt<1>(0h0)) when _T_1618 : node _T_1619 = eq(_T_1616, UInt<1>(0h0)) when _T_1619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1616, UInt<1>(0h1), "") : assert_67 node _T_1620 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1621 = asUInt(reset) node _T_1622 = eq(_T_1621, UInt<1>(0h0)) when _T_1622 : node _T_1623 = eq(_T_1620, UInt<1>(0h0)) when _T_1623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1620, UInt<1>(0h1), "") : assert_68 node _T_1624 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1625 = asUInt(reset) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(_T_1624, UInt<1>(0h0)) when _T_1627 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1624, UInt<1>(0h1), "") : assert_69 node _T_1628 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1629 = or(_T_1628, io.in.d.bits.corrupt) node _T_1630 = asUInt(reset) node _T_1631 = eq(_T_1630, UInt<1>(0h0)) when _T_1631 : node _T_1632 = eq(_T_1629, UInt<1>(0h0)) when _T_1632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1629, UInt<1>(0h1), "") : assert_70 node _T_1633 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1634 = or(UInt<1>(0h0), _T_1633) node _T_1635 = asUInt(reset) node _T_1636 = eq(_T_1635, UInt<1>(0h0)) when _T_1636 : node _T_1637 = eq(_T_1634, UInt<1>(0h0)) when _T_1637 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1634, UInt<1>(0h1), "") : assert_71 node _T_1638 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1638 : node _T_1639 = asUInt(reset) node _T_1640 = eq(_T_1639, UInt<1>(0h0)) when _T_1640 : node _T_1641 = eq(source_ok_1, UInt<1>(0h0)) when _T_1641 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1642 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1643 = asUInt(reset) node _T_1644 = eq(_T_1643, UInt<1>(0h0)) when _T_1644 : node _T_1645 = eq(_T_1642, UInt<1>(0h0)) when _T_1645 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1642, UInt<1>(0h1), "") : assert_73 node _T_1646 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1647 = asUInt(reset) node _T_1648 = eq(_T_1647, UInt<1>(0h0)) when _T_1648 : node _T_1649 = eq(_T_1646, UInt<1>(0h0)) when _T_1649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1646, UInt<1>(0h1), "") : assert_74 node _T_1650 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1651 = or(UInt<1>(0h0), _T_1650) node _T_1652 = asUInt(reset) node _T_1653 = eq(_T_1652, UInt<1>(0h0)) when _T_1653 : node _T_1654 = eq(_T_1651, UInt<1>(0h0)) when _T_1654 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1651, UInt<1>(0h1), "") : assert_75 node _T_1655 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1655 : node _T_1656 = asUInt(reset) node _T_1657 = eq(_T_1656, UInt<1>(0h0)) when _T_1657 : node _T_1658 = eq(source_ok_1, UInt<1>(0h0)) when _T_1658 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1659 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1660 = asUInt(reset) node _T_1661 = eq(_T_1660, UInt<1>(0h0)) when _T_1661 : node _T_1662 = eq(_T_1659, UInt<1>(0h0)) when _T_1662 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1659, UInt<1>(0h1), "") : assert_77 node _T_1663 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1664 = or(_T_1663, io.in.d.bits.corrupt) node _T_1665 = asUInt(reset) node _T_1666 = eq(_T_1665, UInt<1>(0h0)) when _T_1666 : node _T_1667 = eq(_T_1664, UInt<1>(0h0)) when _T_1667 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1664, UInt<1>(0h1), "") : assert_78 node _T_1668 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1669 = or(UInt<1>(0h0), _T_1668) node _T_1670 = asUInt(reset) node _T_1671 = eq(_T_1670, UInt<1>(0h0)) when _T_1671 : node _T_1672 = eq(_T_1669, UInt<1>(0h0)) when _T_1672 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1669, UInt<1>(0h1), "") : assert_79 node _T_1673 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1673 : node _T_1674 = asUInt(reset) node _T_1675 = eq(_T_1674, UInt<1>(0h0)) when _T_1675 : node _T_1676 = eq(source_ok_1, UInt<1>(0h0)) when _T_1676 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1677 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1678 = asUInt(reset) node _T_1679 = eq(_T_1678, UInt<1>(0h0)) when _T_1679 : node _T_1680 = eq(_T_1677, UInt<1>(0h0)) when _T_1680 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1677, UInt<1>(0h1), "") : assert_81 node _T_1681 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1682 = asUInt(reset) node _T_1683 = eq(_T_1682, UInt<1>(0h0)) when _T_1683 : node _T_1684 = eq(_T_1681, UInt<1>(0h0)) when _T_1684 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1681, UInt<1>(0h1), "") : assert_82 node _T_1685 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1686 = or(UInt<1>(0h0), _T_1685) node _T_1687 = asUInt(reset) node _T_1688 = eq(_T_1687, UInt<1>(0h0)) when _T_1688 : node _T_1689 = eq(_T_1686, UInt<1>(0h0)) when _T_1689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1686, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<29>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<29>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1690 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1691 = asUInt(reset) node _T_1692 = eq(_T_1691, UInt<1>(0h0)) when _T_1692 : node _T_1693 = eq(_T_1690, UInt<1>(0h0)) when _T_1693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1690, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<29>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1694 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1695 = asUInt(reset) node _T_1696 = eq(_T_1695, UInt<1>(0h0)) when _T_1696 : node _T_1697 = eq(_T_1694, UInt<1>(0h0)) when _T_1697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1694, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1698 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1699 = asUInt(reset) node _T_1700 = eq(_T_1699, UInt<1>(0h0)) when _T_1700 : node _T_1701 = eq(_T_1698, UInt<1>(0h0)) when _T_1701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1698, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1702 = eq(a_first, UInt<1>(0h0)) node _T_1703 = and(io.in.a.valid, _T_1702) when _T_1703 : node _T_1704 = eq(io.in.a.bits.opcode, opcode) node _T_1705 = asUInt(reset) node _T_1706 = eq(_T_1705, UInt<1>(0h0)) when _T_1706 : node _T_1707 = eq(_T_1704, UInt<1>(0h0)) when _T_1707 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1704, UInt<1>(0h1), "") : assert_87 node _T_1708 = eq(io.in.a.bits.param, param) node _T_1709 = asUInt(reset) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(_T_1708, UInt<1>(0h0)) when _T_1711 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1708, UInt<1>(0h1), "") : assert_88 node _T_1712 = eq(io.in.a.bits.size, size) node _T_1713 = asUInt(reset) node _T_1714 = eq(_T_1713, UInt<1>(0h0)) when _T_1714 : node _T_1715 = eq(_T_1712, UInt<1>(0h0)) when _T_1715 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1712, UInt<1>(0h1), "") : assert_89 node _T_1716 = eq(io.in.a.bits.source, source) node _T_1717 = asUInt(reset) node _T_1718 = eq(_T_1717, UInt<1>(0h0)) when _T_1718 : node _T_1719 = eq(_T_1716, UInt<1>(0h0)) when _T_1719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1716, UInt<1>(0h1), "") : assert_90 node _T_1720 = eq(io.in.a.bits.address, address) node _T_1721 = asUInt(reset) node _T_1722 = eq(_T_1721, UInt<1>(0h0)) when _T_1722 : node _T_1723 = eq(_T_1720, UInt<1>(0h0)) when _T_1723 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1720, UInt<1>(0h1), "") : assert_91 node _T_1724 = and(io.in.a.ready, io.in.a.valid) node _T_1725 = and(_T_1724, a_first) when _T_1725 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1726 = eq(d_first, UInt<1>(0h0)) node _T_1727 = and(io.in.d.valid, _T_1726) when _T_1727 : node _T_1728 = eq(io.in.d.bits.opcode, opcode_1) node _T_1729 = asUInt(reset) node _T_1730 = eq(_T_1729, UInt<1>(0h0)) when _T_1730 : node _T_1731 = eq(_T_1728, UInt<1>(0h0)) when _T_1731 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1728, UInt<1>(0h1), "") : assert_92 node _T_1732 = eq(io.in.d.bits.param, param_1) node _T_1733 = asUInt(reset) node _T_1734 = eq(_T_1733, UInt<1>(0h0)) when _T_1734 : node _T_1735 = eq(_T_1732, UInt<1>(0h0)) when _T_1735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1732, UInt<1>(0h1), "") : assert_93 node _T_1736 = eq(io.in.d.bits.size, size_1) node _T_1737 = asUInt(reset) node _T_1738 = eq(_T_1737, UInt<1>(0h0)) when _T_1738 : node _T_1739 = eq(_T_1736, UInt<1>(0h0)) when _T_1739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1736, UInt<1>(0h1), "") : assert_94 node _T_1740 = eq(io.in.d.bits.source, source_1) node _T_1741 = asUInt(reset) node _T_1742 = eq(_T_1741, UInt<1>(0h0)) when _T_1742 : node _T_1743 = eq(_T_1740, UInt<1>(0h0)) when _T_1743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1740, UInt<1>(0h1), "") : assert_95 node _T_1744 = eq(io.in.d.bits.sink, sink) node _T_1745 = asUInt(reset) node _T_1746 = eq(_T_1745, UInt<1>(0h0)) when _T_1746 : node _T_1747 = eq(_T_1744, UInt<1>(0h0)) when _T_1747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1744, UInt<1>(0h1), "") : assert_96 node _T_1748 = eq(io.in.d.bits.denied, denied) node _T_1749 = asUInt(reset) node _T_1750 = eq(_T_1749, UInt<1>(0h0)) when _T_1750 : node _T_1751 = eq(_T_1748, UInt<1>(0h0)) when _T_1751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1748, UInt<1>(0h1), "") : assert_97 node _T_1752 = and(io.in.d.ready, io.in.d.valid) node _T_1753 = and(_T_1752, d_first) when _T_1753 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1754 = and(io.in.a.valid, a_first_1) node _T_1755 = and(_T_1754, UInt<1>(0h1)) when _T_1755 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1756 = and(io.in.a.ready, io.in.a.valid) node _T_1757 = and(_T_1756, a_first_1) node _T_1758 = and(_T_1757, UInt<1>(0h1)) when _T_1758 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1759 = dshr(inflight, io.in.a.bits.source) node _T_1760 = bits(_T_1759, 0, 0) node _T_1761 = eq(_T_1760, UInt<1>(0h0)) node _T_1762 = asUInt(reset) node _T_1763 = eq(_T_1762, UInt<1>(0h0)) when _T_1763 : node _T_1764 = eq(_T_1761, UInt<1>(0h0)) when _T_1764 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1761, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1765 = and(io.in.d.valid, d_first_1) node _T_1766 = and(_T_1765, UInt<1>(0h1)) node _T_1767 = eq(d_release_ack, UInt<1>(0h0)) node _T_1768 = and(_T_1766, _T_1767) when _T_1768 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1769 = and(io.in.d.ready, io.in.d.valid) node _T_1770 = and(_T_1769, d_first_1) node _T_1771 = and(_T_1770, UInt<1>(0h1)) node _T_1772 = eq(d_release_ack, UInt<1>(0h0)) node _T_1773 = and(_T_1771, _T_1772) when _T_1773 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1774 = and(io.in.d.valid, d_first_1) node _T_1775 = and(_T_1774, UInt<1>(0h1)) node _T_1776 = eq(d_release_ack, UInt<1>(0h0)) node _T_1777 = and(_T_1775, _T_1776) when _T_1777 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1778 = dshr(inflight, io.in.d.bits.source) node _T_1779 = bits(_T_1778, 0, 0) node _T_1780 = or(_T_1779, same_cycle_resp) node _T_1781 = asUInt(reset) node _T_1782 = eq(_T_1781, UInt<1>(0h0)) when _T_1782 : node _T_1783 = eq(_T_1780, UInt<1>(0h0)) when _T_1783 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1780, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1784 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1785 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1786 = or(_T_1784, _T_1785) node _T_1787 = asUInt(reset) node _T_1788 = eq(_T_1787, UInt<1>(0h0)) when _T_1788 : node _T_1789 = eq(_T_1786, UInt<1>(0h0)) when _T_1789 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1786, UInt<1>(0h1), "") : assert_100 node _T_1790 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1791 = asUInt(reset) node _T_1792 = eq(_T_1791, UInt<1>(0h0)) when _T_1792 : node _T_1793 = eq(_T_1790, UInt<1>(0h0)) when _T_1793 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1790, UInt<1>(0h1), "") : assert_101 else : node _T_1794 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1795 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1796 = or(_T_1794, _T_1795) node _T_1797 = asUInt(reset) node _T_1798 = eq(_T_1797, UInt<1>(0h0)) when _T_1798 : node _T_1799 = eq(_T_1796, UInt<1>(0h0)) when _T_1799 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1796, UInt<1>(0h1), "") : assert_102 node _T_1800 = eq(io.in.d.bits.size, a_size_lookup) node _T_1801 = asUInt(reset) node _T_1802 = eq(_T_1801, UInt<1>(0h0)) when _T_1802 : node _T_1803 = eq(_T_1800, UInt<1>(0h0)) when _T_1803 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1800, UInt<1>(0h1), "") : assert_103 node _T_1804 = and(io.in.d.valid, d_first_1) node _T_1805 = and(_T_1804, a_first_1) node _T_1806 = and(_T_1805, io.in.a.valid) node _T_1807 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1808 = and(_T_1806, _T_1807) node _T_1809 = eq(d_release_ack, UInt<1>(0h0)) node _T_1810 = and(_T_1808, _T_1809) when _T_1810 : node _T_1811 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1812 = or(_T_1811, io.in.a.ready) node _T_1813 = asUInt(reset) node _T_1814 = eq(_T_1813, UInt<1>(0h0)) when _T_1814 : node _T_1815 = eq(_T_1812, UInt<1>(0h0)) when _T_1815 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1812, UInt<1>(0h1), "") : assert_104 node _T_1816 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1817 = orr(a_set_wo_ready) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) node _T_1819 = or(_T_1816, _T_1818) node _T_1820 = asUInt(reset) node _T_1821 = eq(_T_1820, UInt<1>(0h0)) when _T_1821 : node _T_1822 = eq(_T_1819, UInt<1>(0h0)) when _T_1822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1819, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_10 node _T_1823 = orr(inflight) node _T_1824 = eq(_T_1823, UInt<1>(0h0)) node _T_1825 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1826 = or(_T_1824, _T_1825) node _T_1827 = lt(watchdog, plusarg_reader.out) node _T_1828 = or(_T_1826, _T_1827) node _T_1829 = asUInt(reset) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(_T_1828, UInt<1>(0h0)) when _T_1831 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1828, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1832 = and(io.in.a.ready, io.in.a.valid) node _T_1833 = and(io.in.d.ready, io.in.d.valid) node _T_1834 = or(_T_1832, _T_1833) when _T_1834 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<29>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<29>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<29>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1835 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<29>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1836 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1837 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1838 = and(_T_1836, _T_1837) node _T_1839 = and(_T_1835, _T_1838) when _T_1839 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<29>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<29>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1840 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1841 = and(_T_1840, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<29>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1842 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1843 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1844 = and(_T_1842, _T_1843) node _T_1845 = and(_T_1841, _T_1844) when _T_1845 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<29>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<29>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<29>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1846 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1847 = bits(_T_1846, 0, 0) node _T_1848 = eq(_T_1847, UInt<1>(0h0)) node _T_1849 = asUInt(reset) node _T_1850 = eq(_T_1849, UInt<1>(0h0)) when _T_1850 : node _T_1851 = eq(_T_1848, UInt<1>(0h0)) when _T_1851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1848, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<29>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1852 = and(io.in.d.valid, d_first_2) node _T_1853 = and(_T_1852, UInt<1>(0h1)) node _T_1854 = and(_T_1853, d_release_ack_1) when _T_1854 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1855 = and(io.in.d.ready, io.in.d.valid) node _T_1856 = and(_T_1855, d_first_2) node _T_1857 = and(_T_1856, UInt<1>(0h1)) node _T_1858 = and(_T_1857, d_release_ack_1) when _T_1858 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1859 = and(io.in.d.valid, d_first_2) node _T_1860 = and(_T_1859, UInt<1>(0h1)) node _T_1861 = and(_T_1860, d_release_ack_1) when _T_1861 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<29>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1862 = dshr(inflight_1, io.in.d.bits.source) node _T_1863 = bits(_T_1862, 0, 0) node _T_1864 = or(_T_1863, same_cycle_resp_1) node _T_1865 = asUInt(reset) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(_T_1864, UInt<1>(0h0)) when _T_1867 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1864, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<29>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1868 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1869 = asUInt(reset) node _T_1870 = eq(_T_1869, UInt<1>(0h0)) when _T_1870 : node _T_1871 = eq(_T_1868, UInt<1>(0h0)) when _T_1871 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1868, UInt<1>(0h1), "") : assert_109 else : node _T_1872 = eq(io.in.d.bits.size, c_size_lookup) node _T_1873 = asUInt(reset) node _T_1874 = eq(_T_1873, UInt<1>(0h0)) when _T_1874 : node _T_1875 = eq(_T_1872, UInt<1>(0h0)) when _T_1875 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1872, UInt<1>(0h1), "") : assert_110 node _T_1876 = and(io.in.d.valid, d_first_2) node _T_1877 = and(_T_1876, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<29>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1878 = and(_T_1877, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<29>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1879 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1880 = and(_T_1878, _T_1879) node _T_1881 = and(_T_1880, d_release_ack_1) node _T_1882 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1883 = and(_T_1881, _T_1882) when _T_1883 : node _T_1884 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<29>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1885 = or(_T_1884, _WIRE_27.ready) node _T_1886 = asUInt(reset) node _T_1887 = eq(_T_1886, UInt<1>(0h0)) when _T_1887 : node _T_1888 = eq(_T_1885, UInt<1>(0h0)) when _T_1888 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1885, UInt<1>(0h1), "") : assert_111 node _T_1889 = orr(c_set_wo_ready) when _T_1889 : node _T_1890 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1891 = asUInt(reset) node _T_1892 = eq(_T_1891, UInt<1>(0h0)) when _T_1892 : node _T_1893 = eq(_T_1890, UInt<1>(0h0)) when _T_1893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1890, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_11 node _T_1894 = orr(inflight_1) node _T_1895 = eq(_T_1894, UInt<1>(0h0)) node _T_1896 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1897 = or(_T_1895, _T_1896) node _T_1898 = lt(watchdog_1, plusarg_reader_1.out) node _T_1899 = or(_T_1897, _T_1898) node _T_1900 = asUInt(reset) node _T_1901 = eq(_T_1900, UInt<1>(0h0)) when _T_1901 : node _T_1902 = eq(_T_1899, UInt<1>(0h0)) when _T_1902 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/subsystem/PeripheryBus.scala:65:7)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1899, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<29>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1903 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1904 = and(io.in.d.ready, io.in.d.valid) node _T_1905 = or(_T_1903, _T_1904) when _T_1905 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_5( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [28:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [28:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_81 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_83 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_87 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_89 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_93 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_95 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_99 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_101 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_first_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_first_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_wo_ready_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_wo_ready_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_interm_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_interm_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_opcodes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_opcodes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_sizes_set_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_sizes_set_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _c_probe_ack_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _c_probe_ack_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_1_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_2_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_3_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [28:0] _same_cycle_resp_WIRE_4_bits_address = 29'h0; // @[Bundles.scala:265:74] wire [28:0] _same_cycle_resp_WIRE_5_bits_address = 29'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire _source_ok_T_25 = io_in_a_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_5 = _source_ok_T_25; // @[Parameters.scala:1138:31] wire _source_ok_T_26 = io_in_a_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_26; // @[Parameters.scala:1138:31] wire _source_ok_T_27 = io_in_a_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_27; // @[Parameters.scala:1138:31] wire _source_ok_T_28 = io_in_a_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_28; // @[Parameters.scala:1138:31] wire _source_ok_T_29 = io_in_a_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_29; // @[Parameters.scala:1138:31] wire _source_ok_T_30 = io_in_a_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_10 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_11 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_12 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_13 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_14 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = io_in_a_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_15 = _source_ok_T_35; // @[Parameters.scala:1138:31] wire _source_ok_T_36 = io_in_a_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_16 = _source_ok_T_36; // @[Parameters.scala:1138:31] wire _source_ok_T_37 = io_in_a_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_17 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire _source_ok_T_38 = io_in_a_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_18 = _source_ok_T_38; // @[Parameters.scala:1138:31] wire _source_ok_T_39 = io_in_a_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_19 = _source_ok_T_39; // @[Parameters.scala:1138:31] wire _source_ok_T_40 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_20 = _source_ok_T_40; // @[Parameters.scala:1138:31] wire _source_ok_T_41 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_21 = _source_ok_T_41; // @[Parameters.scala:1138:31] wire _source_ok_T_42 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_22 = _source_ok_T_42; // @[Parameters.scala:1138:31] wire _source_ok_T_43 = io_in_a_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_23 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire _source_ok_T_44 = io_in_a_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_24 = _source_ok_T_44; // @[Parameters.scala:1138:31] wire _source_ok_T_45 = io_in_a_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_25 = _source_ok_T_45; // @[Parameters.scala:1138:31] wire _source_ok_T_46 = io_in_a_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_26 = _source_ok_T_46; // @[Parameters.scala:1138:31] wire _source_ok_T_47 = io_in_a_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_27 = _source_ok_T_47; // @[Parameters.scala:1138:31] wire _source_ok_T_48 = io_in_a_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_28 = _source_ok_T_48; // @[Parameters.scala:1138:31] wire _source_ok_T_49 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_29 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_52 = _source_ok_T_51 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_53 = _source_ok_T_52 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_54 = _source_ok_T_53 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_55 = _source_ok_T_54 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_56 = _source_ok_T_55 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_57 = _source_ok_T_56 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_58 = _source_ok_T_57 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_59 = _source_ok_T_58 | _source_ok_WIRE_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_60 = _source_ok_T_59 | _source_ok_WIRE_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_61 = _source_ok_T_60 | _source_ok_WIRE_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_62 = _source_ok_T_61 | _source_ok_WIRE_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_63 = _source_ok_T_62 | _source_ok_WIRE_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_64 = _source_ok_T_63 | _source_ok_WIRE_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_65 = _source_ok_T_64 | _source_ok_WIRE_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_66 = _source_ok_T_65 | _source_ok_WIRE_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_67 = _source_ok_T_66 | _source_ok_WIRE_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_68 = _source_ok_T_67 | _source_ok_WIRE_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_69 = _source_ok_T_68 | _source_ok_WIRE_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_70 = _source_ok_T_69 | _source_ok_WIRE_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_71 = _source_ok_T_70 | _source_ok_WIRE_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_72 = _source_ok_T_71 | _source_ok_WIRE_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_73 = _source_ok_T_72 | _source_ok_WIRE_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_74 = _source_ok_T_73 | _source_ok_WIRE_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_75 = _source_ok_T_74 | _source_ok_WIRE_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_76 = _source_ok_T_75 | _source_ok_WIRE_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_77 = _source_ok_T_76 | _source_ok_WIRE_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_77 | _source_ok_WIRE_29; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [28:0] _is_aligned_T = {23'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 29'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_39 = _uncommonBits_T_39[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_78 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_78; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_79 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_85 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_91 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_97 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_80 = _source_ok_T_79 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_82 = _source_ok_T_80; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_84 = _source_ok_T_82; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_84; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_86 = _source_ok_T_85 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_88 = _source_ok_T_86; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_90 = _source_ok_T_88; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_90; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_92 = _source_ok_T_91 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_94 = _source_ok_T_92; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_96 = _source_ok_T_94; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_96; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_98 = _source_ok_T_97 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_100 = _source_ok_T_98; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_102 = _source_ok_T_100; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_102; // @[Parameters.scala:1138:31] wire _source_ok_T_103 = io_in_d_bits_source_0 == 7'h3C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_5 = _source_ok_T_103; // @[Parameters.scala:1138:31] wire _source_ok_T_104 = io_in_d_bits_source_0 == 7'h3D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_104; // @[Parameters.scala:1138:31] wire _source_ok_T_105 = io_in_d_bits_source_0 == 7'h3E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_105; // @[Parameters.scala:1138:31] wire _source_ok_T_106 = io_in_d_bits_source_0 == 7'h38; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_106; // @[Parameters.scala:1138:31] wire _source_ok_T_107 = io_in_d_bits_source_0 == 7'h39; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_107; // @[Parameters.scala:1138:31] wire _source_ok_T_108 = io_in_d_bits_source_0 == 7'h3A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_10 = _source_ok_T_108; // @[Parameters.scala:1138:31] wire _source_ok_T_109 = io_in_d_bits_source_0 == 7'h34; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_11 = _source_ok_T_109; // @[Parameters.scala:1138:31] wire _source_ok_T_110 = io_in_d_bits_source_0 == 7'h35; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_12 = _source_ok_T_110; // @[Parameters.scala:1138:31] wire _source_ok_T_111 = io_in_d_bits_source_0 == 7'h36; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_13 = _source_ok_T_111; // @[Parameters.scala:1138:31] wire _source_ok_T_112 = io_in_d_bits_source_0 == 7'h30; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_14 = _source_ok_T_112; // @[Parameters.scala:1138:31] wire _source_ok_T_113 = io_in_d_bits_source_0 == 7'h31; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_15 = _source_ok_T_113; // @[Parameters.scala:1138:31] wire _source_ok_T_114 = io_in_d_bits_source_0 == 7'h32; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_16 = _source_ok_T_114; // @[Parameters.scala:1138:31] wire _source_ok_T_115 = io_in_d_bits_source_0 == 7'h2C; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_17 = _source_ok_T_115; // @[Parameters.scala:1138:31] wire _source_ok_T_116 = io_in_d_bits_source_0 == 7'h2D; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_18 = _source_ok_T_116; // @[Parameters.scala:1138:31] wire _source_ok_T_117 = io_in_d_bits_source_0 == 7'h2E; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_19 = _source_ok_T_117; // @[Parameters.scala:1138:31] wire _source_ok_T_118 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_20 = _source_ok_T_118; // @[Parameters.scala:1138:31] wire _source_ok_T_119 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_21 = _source_ok_T_119; // @[Parameters.scala:1138:31] wire _source_ok_T_120 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_22 = _source_ok_T_120; // @[Parameters.scala:1138:31] wire _source_ok_T_121 = io_in_d_bits_source_0 == 7'h24; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_23 = _source_ok_T_121; // @[Parameters.scala:1138:31] wire _source_ok_T_122 = io_in_d_bits_source_0 == 7'h25; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_24 = _source_ok_T_122; // @[Parameters.scala:1138:31] wire _source_ok_T_123 = io_in_d_bits_source_0 == 7'h26; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_25 = _source_ok_T_123; // @[Parameters.scala:1138:31] wire _source_ok_T_124 = io_in_d_bits_source_0 == 7'h20; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_26 = _source_ok_T_124; // @[Parameters.scala:1138:31] wire _source_ok_T_125 = io_in_d_bits_source_0 == 7'h21; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_27 = _source_ok_T_125; // @[Parameters.scala:1138:31] wire _source_ok_T_126 = io_in_d_bits_source_0 == 7'h22; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_28 = _source_ok_T_126; // @[Parameters.scala:1138:31] wire _source_ok_T_127 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_29 = _source_ok_T_127; // @[Parameters.scala:1138:31] wire _source_ok_T_128 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_129 = _source_ok_T_128 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_130 = _source_ok_T_129 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_131 = _source_ok_T_130 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_132 = _source_ok_T_131 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_133 = _source_ok_T_132 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_134 = _source_ok_T_133 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_135 = _source_ok_T_134 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_136 = _source_ok_T_135 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_137 = _source_ok_T_136 | _source_ok_WIRE_1_10; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_138 = _source_ok_T_137 | _source_ok_WIRE_1_11; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_139 = _source_ok_T_138 | _source_ok_WIRE_1_12; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_140 = _source_ok_T_139 | _source_ok_WIRE_1_13; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_141 = _source_ok_T_140 | _source_ok_WIRE_1_14; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_142 = _source_ok_T_141 | _source_ok_WIRE_1_15; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_143 = _source_ok_T_142 | _source_ok_WIRE_1_16; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_144 = _source_ok_T_143 | _source_ok_WIRE_1_17; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_145 = _source_ok_T_144 | _source_ok_WIRE_1_18; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_146 = _source_ok_T_145 | _source_ok_WIRE_1_19; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_147 = _source_ok_T_146 | _source_ok_WIRE_1_20; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_148 = _source_ok_T_147 | _source_ok_WIRE_1_21; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_149 = _source_ok_T_148 | _source_ok_WIRE_1_22; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_150 = _source_ok_T_149 | _source_ok_WIRE_1_23; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_151 = _source_ok_T_150 | _source_ok_WIRE_1_24; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_152 = _source_ok_T_151 | _source_ok_WIRE_1_25; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_153 = _source_ok_T_152 | _source_ok_WIRE_1_26; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_154 = _source_ok_T_153 | _source_ok_WIRE_1_27; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_155 = _source_ok_T_154 | _source_ok_WIRE_1_28; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_155 | _source_ok_WIRE_1_29; // @[Parameters.scala:1138:31, :1139:46] wire _T_1832 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1832; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1832; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [28:0] address; // @[Monitor.scala:391:22] wire _T_1905 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1905; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1905; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1905; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1758 = _T_1832 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1758 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1758 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1758 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1758 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1758 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1804 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1804 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1773 = _T_1905 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1773 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1773 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1773 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1876 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1876 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1858 = _T_1905 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1858 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1858 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1858 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module DivSqrtRawFN_small_e5_s11 : input clock : Clock input reset : Reset output io : { inReady : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<12>}, flip roundingMode : UInt<3>, rawOutValid_div : UInt<1>, rawOutValid_sqrt : UInt<1>, roundingModeOut : UInt<3>, invalidExc : UInt<1>, infiniteExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<7>, sig : UInt<14>}} regreset cycleNum : UInt<4>, clock, reset, UInt<4>(0h0) regreset inReady : UInt<1>, clock, reset, UInt<1>(0h1) regreset rawOutValid : UInt<1>, clock, reset, UInt<1>(0h0) reg sqrtOp_Z : UInt<1>, clock reg majorExc_Z : UInt<1>, clock reg isNaN_Z : UInt<1>, clock reg isInf_Z : UInt<1>, clock reg isZero_Z : UInt<1>, clock reg sign_Z : UInt<1>, clock reg sExp_Z : SInt<7>, clock reg fractB_Z : UInt<11>, clock reg roundingMode_Z : UInt<3>, clock reg rem_Z : UInt<13>, clock reg notZeroRem_Z : UInt<1>, clock reg sigX_Z : UInt<13>, clock node _notSigNaNIn_invalidExc_S_div_T = and(io.a.isZero, io.b.isZero) node _notSigNaNIn_invalidExc_S_div_T_1 = and(io.a.isInf, io.b.isInf) node notSigNaNIn_invalidExc_S_div = or(_notSigNaNIn_invalidExc_S_div_T, _notSigNaNIn_invalidExc_S_div_T_1) node _notSigNaNIn_invalidExc_S_sqrt_T = eq(io.a.isNaN, UInt<1>(0h0)) node _notSigNaNIn_invalidExc_S_sqrt_T_1 = eq(io.a.isZero, UInt<1>(0h0)) node _notSigNaNIn_invalidExc_S_sqrt_T_2 = and(_notSigNaNIn_invalidExc_S_sqrt_T, _notSigNaNIn_invalidExc_S_sqrt_T_1) node notSigNaNIn_invalidExc_S_sqrt = and(_notSigNaNIn_invalidExc_S_sqrt_T_2, io.a.sign) node _majorExc_S_T = bits(io.a.sig, 9, 9) node _majorExc_S_T_1 = eq(_majorExc_S_T, UInt<1>(0h0)) node _majorExc_S_T_2 = and(io.a.isNaN, _majorExc_S_T_1) node _majorExc_S_T_3 = or(_majorExc_S_T_2, notSigNaNIn_invalidExc_S_sqrt) node _majorExc_S_T_4 = bits(io.a.sig, 9, 9) node _majorExc_S_T_5 = eq(_majorExc_S_T_4, UInt<1>(0h0)) node _majorExc_S_T_6 = and(io.a.isNaN, _majorExc_S_T_5) node _majorExc_S_T_7 = bits(io.b.sig, 9, 9) node _majorExc_S_T_8 = eq(_majorExc_S_T_7, UInt<1>(0h0)) node _majorExc_S_T_9 = and(io.b.isNaN, _majorExc_S_T_8) node _majorExc_S_T_10 = or(_majorExc_S_T_6, _majorExc_S_T_9) node _majorExc_S_T_11 = or(_majorExc_S_T_10, notSigNaNIn_invalidExc_S_div) node _majorExc_S_T_12 = eq(io.a.isNaN, UInt<1>(0h0)) node _majorExc_S_T_13 = eq(io.a.isInf, UInt<1>(0h0)) node _majorExc_S_T_14 = and(_majorExc_S_T_12, _majorExc_S_T_13) node _majorExc_S_T_15 = and(_majorExc_S_T_14, io.b.isZero) node _majorExc_S_T_16 = or(_majorExc_S_T_11, _majorExc_S_T_15) node majorExc_S = mux(io.sqrtOp, _majorExc_S_T_3, _majorExc_S_T_16) node _isNaN_S_T = or(io.a.isNaN, notSigNaNIn_invalidExc_S_sqrt) node _isNaN_S_T_1 = or(io.a.isNaN, io.b.isNaN) node _isNaN_S_T_2 = or(_isNaN_S_T_1, notSigNaNIn_invalidExc_S_div) node isNaN_S = mux(io.sqrtOp, _isNaN_S_T, _isNaN_S_T_2) node _isInf_S_T = or(io.a.isInf, io.b.isZero) node isInf_S = mux(io.sqrtOp, io.a.isInf, _isInf_S_T) node _isZero_S_T = or(io.a.isZero, io.b.isInf) node isZero_S = mux(io.sqrtOp, io.a.isZero, _isZero_S_T) node _sign_S_T = eq(io.sqrtOp, UInt<1>(0h0)) node _sign_S_T_1 = and(_sign_S_T, io.b.sign) node sign_S = xor(io.a.sign, _sign_S_T_1) node _specialCaseA_S_T = or(io.a.isNaN, io.a.isInf) node specialCaseA_S = or(_specialCaseA_S_T, io.a.isZero) node _specialCaseB_S_T = or(io.b.isNaN, io.b.isInf) node specialCaseB_S = or(_specialCaseB_S_T, io.b.isZero) node _normalCase_S_div_T = eq(specialCaseA_S, UInt<1>(0h0)) node _normalCase_S_div_T_1 = eq(specialCaseB_S, UInt<1>(0h0)) node normalCase_S_div = and(_normalCase_S_div_T, _normalCase_S_div_T_1) node _normalCase_S_sqrt_T = eq(specialCaseA_S, UInt<1>(0h0)) node _normalCase_S_sqrt_T_1 = eq(io.a.sign, UInt<1>(0h0)) node normalCase_S_sqrt = and(_normalCase_S_sqrt_T, _normalCase_S_sqrt_T_1) node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) node _sExpQuot_S_div_T = bits(io.b.sExp, 5, 5) node _sExpQuot_S_div_T_1 = bits(io.b.sExp, 4, 0) node _sExpQuot_S_div_T_2 = not(_sExpQuot_S_div_T_1) node _sExpQuot_S_div_T_3 = cat(_sExpQuot_S_div_T, _sExpQuot_S_div_T_2) node _sExpQuot_S_div_T_4 = asSInt(_sExpQuot_S_div_T_3) node sExpQuot_S_div = add(io.a.sExp, _sExpQuot_S_div_T_4) node _sSatExpQuot_S_div_T = leq(asSInt(UInt<7>(0h38)), sExpQuot_S_div) node _sSatExpQuot_S_div_T_1 = bits(sExpQuot_S_div, 6, 3) node _sSatExpQuot_S_div_T_2 = mux(_sSatExpQuot_S_div_T, UInt<3>(0h6), _sSatExpQuot_S_div_T_1) node _sSatExpQuot_S_div_T_3 = bits(sExpQuot_S_div, 2, 0) node _sSatExpQuot_S_div_T_4 = cat(_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3) node sSatExpQuot_S_div = asSInt(_sSatExpQuot_S_div_T_4) node _evenSqrt_S_T = bits(io.a.sExp, 0, 0) node _evenSqrt_S_T_1 = eq(_evenSqrt_S_T, UInt<1>(0h0)) node evenSqrt_S = and(io.sqrtOp, _evenSqrt_S_T_1) node _oddSqrt_S_T = bits(io.a.sExp, 0, 0) node oddSqrt_S = and(io.sqrtOp, _oddSqrt_S_T) node idle = eq(cycleNum, UInt<1>(0h0)) node entering = and(inReady, io.inValid) node entering_normalCase = and(entering, normalCase_S) node _processTwoBits_T = geq(cycleNum, UInt<2>(0h3)) node processTwoBits = and(_processTwoBits_T, UInt<1>(0h0)) node _skipCycle2_T = eq(cycleNum, UInt<2>(0h3)) node _skipCycle2_T_1 = bits(sigX_Z, 12, 12) node _skipCycle2_T_2 = and(_skipCycle2_T, _skipCycle2_T_1) node skipCycle2 = and(_skipCycle2_T_2, UInt<1>(0h1)) node _T = eq(idle, UInt<1>(0h0)) node _T_1 = or(_T, entering) when _T_1 : node _inReady_T = eq(normalCase_S, UInt<1>(0h0)) node _inReady_T_1 = and(entering, _inReady_T) node _inReady_T_2 = leq(UInt<1>(0h1), UInt<1>(0h1)) node _inReady_T_3 = mux(_inReady_T_1, _inReady_T_2, UInt<1>(0h0)) node _inReady_T_4 = bits(io.a.sExp, 0, 0) node _inReady_T_5 = leq(UInt<4>(0hb), UInt<1>(0h1)) node _inReady_T_6 = leq(UInt<4>(0hc), UInt<1>(0h1)) node _inReady_T_7 = mux(_inReady_T_4, _inReady_T_5, _inReady_T_6) node _inReady_T_8 = leq(UInt<4>(0hd), UInt<1>(0h1)) node _inReady_T_9 = mux(io.sqrtOp, _inReady_T_7, _inReady_T_8) node _inReady_T_10 = mux(entering_normalCase, _inReady_T_9, UInt<1>(0h0)) node _inReady_T_11 = or(_inReady_T_3, _inReady_T_10) node _inReady_T_12 = eq(entering, UInt<1>(0h0)) node _inReady_T_13 = eq(skipCycle2, UInt<1>(0h0)) node _inReady_T_14 = and(_inReady_T_12, _inReady_T_13) node _inReady_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) node _inReady_T_16 = sub(cycleNum, _inReady_T_15) node _inReady_T_17 = tail(_inReady_T_16, 1) node _inReady_T_18 = leq(_inReady_T_17, UInt<1>(0h1)) node _inReady_T_19 = mux(_inReady_T_14, _inReady_T_18, UInt<1>(0h0)) node _inReady_T_20 = or(_inReady_T_11, _inReady_T_19) node _inReady_T_21 = leq(UInt<1>(0h1), UInt<1>(0h1)) node _inReady_T_22 = mux(skipCycle2, _inReady_T_21, UInt<1>(0h0)) node _inReady_T_23 = or(_inReady_T_20, _inReady_T_22) node _inReady_T_24 = bits(_inReady_T_23, 0, 0) connect inReady, _inReady_T_24 node _rawOutValid_T = eq(normalCase_S, UInt<1>(0h0)) node _rawOutValid_T_1 = and(entering, _rawOutValid_T) node _rawOutValid_T_2 = eq(UInt<1>(0h1), UInt<1>(0h1)) node _rawOutValid_T_3 = mux(_rawOutValid_T_1, _rawOutValid_T_2, UInt<1>(0h0)) node _rawOutValid_T_4 = bits(io.a.sExp, 0, 0) node _rawOutValid_T_5 = eq(UInt<4>(0hb), UInt<1>(0h1)) node _rawOutValid_T_6 = eq(UInt<4>(0hc), UInt<1>(0h1)) node _rawOutValid_T_7 = mux(_rawOutValid_T_4, _rawOutValid_T_5, _rawOutValid_T_6) node _rawOutValid_T_8 = eq(UInt<4>(0hd), UInt<1>(0h1)) node _rawOutValid_T_9 = mux(io.sqrtOp, _rawOutValid_T_7, _rawOutValid_T_8) node _rawOutValid_T_10 = mux(entering_normalCase, _rawOutValid_T_9, UInt<1>(0h0)) node _rawOutValid_T_11 = or(_rawOutValid_T_3, _rawOutValid_T_10) node _rawOutValid_T_12 = eq(entering, UInt<1>(0h0)) node _rawOutValid_T_13 = eq(skipCycle2, UInt<1>(0h0)) node _rawOutValid_T_14 = and(_rawOutValid_T_12, _rawOutValid_T_13) node _rawOutValid_T_15 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) node _rawOutValid_T_16 = sub(cycleNum, _rawOutValid_T_15) node _rawOutValid_T_17 = tail(_rawOutValid_T_16, 1) node _rawOutValid_T_18 = eq(_rawOutValid_T_17, UInt<1>(0h1)) node _rawOutValid_T_19 = mux(_rawOutValid_T_14, _rawOutValid_T_18, UInt<1>(0h0)) node _rawOutValid_T_20 = or(_rawOutValid_T_11, _rawOutValid_T_19) node _rawOutValid_T_21 = eq(UInt<1>(0h1), UInt<1>(0h1)) node _rawOutValid_T_22 = mux(skipCycle2, _rawOutValid_T_21, UInt<1>(0h0)) node _rawOutValid_T_23 = or(_rawOutValid_T_20, _rawOutValid_T_22) node _rawOutValid_T_24 = bits(_rawOutValid_T_23, 0, 0) connect rawOutValid, _rawOutValid_T_24 node _cycleNum_T = eq(normalCase_S, UInt<1>(0h0)) node _cycleNum_T_1 = and(entering, _cycleNum_T) node _cycleNum_T_2 = mux(_cycleNum_T_1, UInt<1>(0h1), UInt<1>(0h0)) node _cycleNum_T_3 = bits(io.a.sExp, 0, 0) node _cycleNum_T_4 = mux(_cycleNum_T_3, UInt<4>(0hb), UInt<4>(0hc)) node _cycleNum_T_5 = mux(io.sqrtOp, _cycleNum_T_4, UInt<4>(0hd)) node _cycleNum_T_6 = mux(entering_normalCase, _cycleNum_T_5, UInt<1>(0h0)) node _cycleNum_T_7 = or(_cycleNum_T_2, _cycleNum_T_6) node _cycleNum_T_8 = eq(entering, UInt<1>(0h0)) node _cycleNum_T_9 = eq(skipCycle2, UInt<1>(0h0)) node _cycleNum_T_10 = and(_cycleNum_T_8, _cycleNum_T_9) node _cycleNum_T_11 = mux(processTwoBits, UInt<2>(0h2), UInt<1>(0h1)) node _cycleNum_T_12 = sub(cycleNum, _cycleNum_T_11) node _cycleNum_T_13 = tail(_cycleNum_T_12, 1) node _cycleNum_T_14 = mux(_cycleNum_T_10, _cycleNum_T_13, UInt<1>(0h0)) node _cycleNum_T_15 = or(_cycleNum_T_7, _cycleNum_T_14) node _cycleNum_T_16 = mux(skipCycle2, UInt<1>(0h1), UInt<1>(0h0)) node _cycleNum_T_17 = or(_cycleNum_T_15, _cycleNum_T_16) connect cycleNum, _cycleNum_T_17 connect io.inReady, inReady when entering : connect sqrtOp_Z, io.sqrtOp connect majorExc_Z, majorExc_S connect isNaN_Z, isNaN_S connect isInf_Z, isInf_S connect isZero_Z, isZero_S connect sign_Z, sign_S node _sExp_Z_T = shr(io.a.sExp, 1) node _sExp_Z_T_1 = add(_sExp_Z_T, asSInt(UInt<6>(0h10))) node _sExp_Z_T_2 = mux(io.sqrtOp, _sExp_Z_T_1, sSatExpQuot_S_div) connect sExp_Z, _sExp_Z_T_2 connect roundingMode_Z, io.roundingMode node _T_2 = eq(inReady, UInt<1>(0h0)) node _T_3 = and(_T_2, sqrtOp_Z) node _T_4 = or(entering, _T_3) when _T_4 : node _fractB_Z_T = eq(io.sqrtOp, UInt<1>(0h0)) node _fractB_Z_T_1 = and(inReady, _fractB_Z_T) node _fractB_Z_T_2 = bits(io.b.sig, 9, 0) node _fractB_Z_T_3 = shl(_fractB_Z_T_2, 1) node _fractB_Z_T_4 = mux(_fractB_Z_T_1, _fractB_Z_T_3, UInt<1>(0h0)) node _fractB_Z_T_5 = and(inReady, io.sqrtOp) node _fractB_Z_T_6 = bits(io.a.sExp, 0, 0) node _fractB_Z_T_7 = and(_fractB_Z_T_5, _fractB_Z_T_6) node _fractB_Z_T_8 = mux(_fractB_Z_T_7, UInt<10>(0h200), UInt<1>(0h0)) node _fractB_Z_T_9 = or(_fractB_Z_T_4, _fractB_Z_T_8) node _fractB_Z_T_10 = and(inReady, io.sqrtOp) node _fractB_Z_T_11 = bits(io.a.sExp, 0, 0) node _fractB_Z_T_12 = eq(_fractB_Z_T_11, UInt<1>(0h0)) node _fractB_Z_T_13 = and(_fractB_Z_T_10, _fractB_Z_T_12) node _fractB_Z_T_14 = mux(_fractB_Z_T_13, UInt<11>(0h400), UInt<1>(0h0)) node _fractB_Z_T_15 = or(_fractB_Z_T_9, _fractB_Z_T_14) node _fractB_Z_T_16 = eq(inReady, UInt<1>(0h0)) node _fractB_Z_T_17 = and(_fractB_Z_T_16, processTwoBits) node _fractB_Z_T_18 = shr(fractB_Z, 2) node _fractB_Z_T_19 = mux(_fractB_Z_T_17, _fractB_Z_T_18, UInt<1>(0h0)) node _fractB_Z_T_20 = or(_fractB_Z_T_15, _fractB_Z_T_19) node _fractB_Z_T_21 = eq(inReady, UInt<1>(0h0)) node _fractB_Z_T_22 = eq(processTwoBits, UInt<1>(0h0)) node _fractB_Z_T_23 = and(_fractB_Z_T_21, _fractB_Z_T_22) node _fractB_Z_T_24 = shr(fractB_Z, 1) node _fractB_Z_T_25 = mux(_fractB_Z_T_23, _fractB_Z_T_24, UInt<1>(0h0)) node _fractB_Z_T_26 = or(_fractB_Z_T_20, _fractB_Z_T_25) connect fractB_Z, _fractB_Z_T_26 node _rem_T = eq(oddSqrt_S, UInt<1>(0h0)) node _rem_T_1 = and(inReady, _rem_T) node _rem_T_2 = shl(io.a.sig, 1) node _rem_T_3 = mux(_rem_T_1, _rem_T_2, UInt<1>(0h0)) node _rem_T_4 = and(inReady, oddSqrt_S) node _rem_T_5 = bits(io.a.sig, 10, 9) node _rem_T_6 = sub(_rem_T_5, UInt<1>(0h1)) node _rem_T_7 = tail(_rem_T_6, 1) node _rem_T_8 = bits(io.a.sig, 8, 0) node _rem_T_9 = shl(_rem_T_8, 3) node _rem_T_10 = cat(_rem_T_7, _rem_T_9) node _rem_T_11 = mux(_rem_T_4, _rem_T_10, UInt<1>(0h0)) node _rem_T_12 = or(_rem_T_3, _rem_T_11) node _rem_T_13 = eq(inReady, UInt<1>(0h0)) node _rem_T_14 = shl(rem_Z, 1) node _rem_T_15 = mux(_rem_T_13, _rem_T_14, UInt<1>(0h0)) node rem = or(_rem_T_12, _rem_T_15) node _bitMask_T = dshl(UInt<1>(0h1), cycleNum) node bitMask = shr(_bitMask_T, 2) node _trialTerm_T = eq(io.sqrtOp, UInt<1>(0h0)) node _trialTerm_T_1 = and(inReady, _trialTerm_T) node _trialTerm_T_2 = shl(io.b.sig, 1) node _trialTerm_T_3 = mux(_trialTerm_T_1, _trialTerm_T_2, UInt<1>(0h0)) node _trialTerm_T_4 = and(inReady, evenSqrt_S) node _trialTerm_T_5 = mux(_trialTerm_T_4, UInt<12>(0h800), UInt<1>(0h0)) node _trialTerm_T_6 = or(_trialTerm_T_3, _trialTerm_T_5) node _trialTerm_T_7 = and(inReady, oddSqrt_S) node _trialTerm_T_8 = mux(_trialTerm_T_7, UInt<13>(0h1400), UInt<1>(0h0)) node _trialTerm_T_9 = or(_trialTerm_T_6, _trialTerm_T_8) node _trialTerm_T_10 = eq(inReady, UInt<1>(0h0)) node _trialTerm_T_11 = mux(_trialTerm_T_10, fractB_Z, UInt<1>(0h0)) node _trialTerm_T_12 = or(_trialTerm_T_9, _trialTerm_T_11) node _trialTerm_T_13 = eq(inReady, UInt<1>(0h0)) node _trialTerm_T_14 = eq(sqrtOp_Z, UInt<1>(0h0)) node _trialTerm_T_15 = and(_trialTerm_T_13, _trialTerm_T_14) node _trialTerm_T_16 = shl(UInt<1>(0h1), 11) node _trialTerm_T_17 = mux(_trialTerm_T_15, _trialTerm_T_16, UInt<1>(0h0)) node _trialTerm_T_18 = or(_trialTerm_T_12, _trialTerm_T_17) node _trialTerm_T_19 = eq(inReady, UInt<1>(0h0)) node _trialTerm_T_20 = and(_trialTerm_T_19, sqrtOp_Z) node _trialTerm_T_21 = shl(sigX_Z, 1) node _trialTerm_T_22 = mux(_trialTerm_T_20, _trialTerm_T_21, UInt<1>(0h0)) node trialTerm = or(_trialTerm_T_18, _trialTerm_T_22) node _trialRem_T = cvt(rem) node _trialRem_T_1 = cvt(trialTerm) node trialRem = sub(_trialRem_T, _trialRem_T_1) node newBit = leq(asSInt(UInt<1>(0h0)), trialRem) node _nextRem_Z_T = asUInt(trialRem) node _nextRem_Z_T_1 = mux(newBit, _nextRem_Z_T, rem) node nextRem_Z = bits(_nextRem_Z_T_1, 12, 0) node rem2 = shl(nextRem_Z, 1) node _trialTerm2_newBit0_T = shr(fractB_Z, 1) node _trialTerm2_newBit0_T_1 = shl(sigX_Z, 1) node _trialTerm2_newBit0_T_2 = or(_trialTerm2_newBit0_T, _trialTerm2_newBit0_T_1) node _trialTerm2_newBit0_T_3 = shl(UInt<1>(0h1), 11) node _trialTerm2_newBit0_T_4 = or(fractB_Z, _trialTerm2_newBit0_T_3) node trialTerm2_newBit0 = mux(sqrtOp_Z, _trialTerm2_newBit0_T_2, _trialTerm2_newBit0_T_4) node _trialTerm2_newBit1_T = shl(fractB_Z, 1) node _trialTerm2_newBit1_T_1 = mux(sqrtOp_Z, _trialTerm2_newBit1_T, UInt<1>(0h0)) node trialTerm2_newBit1 = or(trialTerm2_newBit0, _trialTerm2_newBit1_T_1) node _trialRem2_T = shl(trialRem, 1) node _trialRem2_T_1 = cvt(trialTerm2_newBit1) node _trialRem2_T_2 = sub(_trialRem2_T, _trialRem2_T_1) node _trialRem2_T_3 = tail(_trialRem2_T_2, 1) node _trialRem2_T_4 = asSInt(_trialRem2_T_3) node _trialRem2_T_5 = shl(rem_Z, 2) node _trialRem2_T_6 = bits(_trialRem2_T_5, 13, 0) node _trialRem2_T_7 = cvt(_trialRem2_T_6) node _trialRem2_T_8 = cvt(trialTerm2_newBit0) node _trialRem2_T_9 = sub(_trialRem2_T_7, _trialRem2_T_8) node _trialRem2_T_10 = tail(_trialRem2_T_9, 1) node _trialRem2_T_11 = asSInt(_trialRem2_T_10) node trialRem2 = mux(newBit, _trialRem2_T_4, _trialRem2_T_11) node newBit2 = leq(asSInt(UInt<1>(0h0)), trialRem2) node _nextNotZeroRem_Z_T = or(inReady, newBit) node _nextNotZeroRem_Z_T_1 = neq(trialRem, asSInt(UInt<1>(0h0))) node nextNotZeroRem_Z = mux(_nextNotZeroRem_Z_T, _nextNotZeroRem_Z_T_1, notZeroRem_Z) node _nextNotZeroRem_Z_2_T = and(processTwoBits, newBit) node _nextNotZeroRem_Z_2_T_1 = shl(trialRem, 1) node _nextNotZeroRem_Z_2_T_2 = cvt(trialTerm2_newBit1) node _nextNotZeroRem_Z_2_T_3 = sub(_nextNotZeroRem_Z_2_T_1, _nextNotZeroRem_Z_2_T_2) node _nextNotZeroRem_Z_2_T_4 = tail(_nextNotZeroRem_Z_2_T_3, 1) node _nextNotZeroRem_Z_2_T_5 = asSInt(_nextNotZeroRem_Z_2_T_4) node _nextNotZeroRem_Z_2_T_6 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_5) node _nextNotZeroRem_Z_2_T_7 = and(_nextNotZeroRem_Z_2_T, _nextNotZeroRem_Z_2_T_6) node _nextNotZeroRem_Z_2_T_8 = eq(newBit, UInt<1>(0h0)) node _nextNotZeroRem_Z_2_T_9 = and(processTwoBits, _nextNotZeroRem_Z_2_T_8) node _nextNotZeroRem_Z_2_T_10 = shl(rem_Z, 2) node _nextNotZeroRem_Z_2_T_11 = bits(_nextNotZeroRem_Z_2_T_10, 13, 0) node _nextNotZeroRem_Z_2_T_12 = cvt(_nextNotZeroRem_Z_2_T_11) node _nextNotZeroRem_Z_2_T_13 = cvt(trialTerm2_newBit0) node _nextNotZeroRem_Z_2_T_14 = sub(_nextNotZeroRem_Z_2_T_12, _nextNotZeroRem_Z_2_T_13) node _nextNotZeroRem_Z_2_T_15 = tail(_nextNotZeroRem_Z_2_T_14, 1) node _nextNotZeroRem_Z_2_T_16 = asSInt(_nextNotZeroRem_Z_2_T_15) node _nextNotZeroRem_Z_2_T_17 = lt(asSInt(UInt<1>(0h0)), _nextNotZeroRem_Z_2_T_16) node _nextNotZeroRem_Z_2_T_18 = and(_nextNotZeroRem_Z_2_T_9, _nextNotZeroRem_Z_2_T_17) node _nextNotZeroRem_Z_2_T_19 = or(_nextNotZeroRem_Z_2_T_7, _nextNotZeroRem_Z_2_T_18) node _nextNotZeroRem_Z_2_T_20 = and(processTwoBits, newBit2) node _nextNotZeroRem_Z_2_T_21 = eq(_nextNotZeroRem_Z_2_T_20, UInt<1>(0h0)) node _nextNotZeroRem_Z_2_T_22 = and(_nextNotZeroRem_Z_2_T_21, nextNotZeroRem_Z) node nextNotZeroRem_Z_2 = or(_nextNotZeroRem_Z_2_T_19, _nextNotZeroRem_Z_2_T_22) node _nextRem_Z_2_T = and(processTwoBits, newBit2) node _nextRem_Z_2_T_1 = asUInt(trialRem2) node _nextRem_Z_2_T_2 = bits(_nextRem_Z_2_T_1, 12, 0) node _nextRem_Z_2_T_3 = mux(_nextRem_Z_2_T, _nextRem_Z_2_T_2, UInt<1>(0h0)) node _nextRem_Z_2_T_4 = eq(newBit2, UInt<1>(0h0)) node _nextRem_Z_2_T_5 = and(processTwoBits, _nextRem_Z_2_T_4) node _nextRem_Z_2_T_6 = bits(rem2, 12, 0) node _nextRem_Z_2_T_7 = mux(_nextRem_Z_2_T_5, _nextRem_Z_2_T_6, UInt<1>(0h0)) node _nextRem_Z_2_T_8 = or(_nextRem_Z_2_T_3, _nextRem_Z_2_T_7) node _nextRem_Z_2_T_9 = eq(processTwoBits, UInt<1>(0h0)) node _nextRem_Z_2_T_10 = mux(_nextRem_Z_2_T_9, nextRem_Z, UInt<1>(0h0)) node nextRem_Z_2 = or(_nextRem_Z_2_T_8, _nextRem_Z_2_T_10) node _T_5 = eq(inReady, UInt<1>(0h0)) node _T_6 = or(entering, _T_5) when _T_6 : connect notZeroRem_Z, nextNotZeroRem_Z_2 connect rem_Z, nextRem_Z_2 node _sigX_Z_T = eq(io.sqrtOp, UInt<1>(0h0)) node _sigX_Z_T_1 = and(inReady, _sigX_Z_T) node _sigX_Z_T_2 = shl(newBit, 12) node _sigX_Z_T_3 = mux(_sigX_Z_T_1, _sigX_Z_T_2, UInt<1>(0h0)) node _sigX_Z_T_4 = and(inReady, io.sqrtOp) node _sigX_Z_T_5 = mux(_sigX_Z_T_4, UInt<12>(0h800), UInt<1>(0h0)) node _sigX_Z_T_6 = or(_sigX_Z_T_3, _sigX_Z_T_5) node _sigX_Z_T_7 = and(inReady, oddSqrt_S) node _sigX_Z_T_8 = shl(newBit, 10) node _sigX_Z_T_9 = mux(_sigX_Z_T_7, _sigX_Z_T_8, UInt<1>(0h0)) node _sigX_Z_T_10 = or(_sigX_Z_T_6, _sigX_Z_T_9) node _sigX_Z_T_11 = eq(inReady, UInt<1>(0h0)) node _sigX_Z_T_12 = mux(_sigX_Z_T_11, sigX_Z, UInt<1>(0h0)) node _sigX_Z_T_13 = or(_sigX_Z_T_10, _sigX_Z_T_12) node _sigX_Z_T_14 = eq(inReady, UInt<1>(0h0)) node _sigX_Z_T_15 = and(_sigX_Z_T_14, newBit) node _sigX_Z_T_16 = mux(_sigX_Z_T_15, bitMask, UInt<1>(0h0)) node _sigX_Z_T_17 = or(_sigX_Z_T_13, _sigX_Z_T_16) node _sigX_Z_T_18 = and(processTwoBits, newBit2) node _sigX_Z_T_19 = shr(bitMask, 1) node _sigX_Z_T_20 = mux(_sigX_Z_T_18, _sigX_Z_T_19, UInt<1>(0h0)) node _sigX_Z_T_21 = or(_sigX_Z_T_17, _sigX_Z_T_20) connect sigX_Z, _sigX_Z_T_21 node _io_rawOutValid_div_T = eq(sqrtOp_Z, UInt<1>(0h0)) node _io_rawOutValid_div_T_1 = and(rawOutValid, _io_rawOutValid_div_T) connect io.rawOutValid_div, _io_rawOutValid_div_T_1 node _io_rawOutValid_sqrt_T = and(rawOutValid, sqrtOp_Z) connect io.rawOutValid_sqrt, _io_rawOutValid_sqrt_T connect io.roundingModeOut, roundingMode_Z node _io_invalidExc_T = and(majorExc_Z, isNaN_Z) connect io.invalidExc, _io_invalidExc_T node _io_infiniteExc_T = eq(isNaN_Z, UInt<1>(0h0)) node _io_infiniteExc_T_1 = and(majorExc_Z, _io_infiniteExc_T) connect io.infiniteExc, _io_infiniteExc_T_1 connect io.rawOut.isNaN, isNaN_Z connect io.rawOut.isInf, isInf_Z connect io.rawOut.isZero, isZero_Z connect io.rawOut.sign, sign_Z connect io.rawOut.sExp, sExp_Z node _io_rawOut_sig_T = shl(sigX_Z, 1) node _io_rawOut_sig_T_1 = or(_io_rawOut_sig_T, notZeroRem_Z) connect io.rawOut.sig, _io_rawOut_sig_T_1
module DivSqrtRawFN_small_e5_s11( // @[DivSqrtRecFN_small.scala:199:5] input clock, // @[DivSqrtRecFN_small.scala:199:5] input reset, // @[DivSqrtRecFN_small.scala:199:5] output io_inReady, // @[DivSqrtRecFN_small.scala:203:16] input io_inValid, // @[DivSqrtRecFN_small.scala:203:16] input io_sqrtOp, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isNaN, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isInf, // @[DivSqrtRecFN_small.scala:203:16] input io_a_isZero, // @[DivSqrtRecFN_small.scala:203:16] input io_a_sign, // @[DivSqrtRecFN_small.scala:203:16] input [6:0] io_a_sExp, // @[DivSqrtRecFN_small.scala:203:16] input [11:0] io_a_sig, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isNaN, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isInf, // @[DivSqrtRecFN_small.scala:203:16] input io_b_isZero, // @[DivSqrtRecFN_small.scala:203:16] input io_b_sign, // @[DivSqrtRecFN_small.scala:203:16] input [6:0] io_b_sExp, // @[DivSqrtRecFN_small.scala:203:16] input [11:0] io_b_sig, // @[DivSqrtRecFN_small.scala:203:16] input [2:0] io_roundingMode, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOutValid_div, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOutValid_sqrt, // @[DivSqrtRecFN_small.scala:203:16] output [2:0] io_roundingModeOut, // @[DivSqrtRecFN_small.scala:203:16] output io_invalidExc, // @[DivSqrtRecFN_small.scala:203:16] output io_infiniteExc, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isNaN, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isInf, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_isZero, // @[DivSqrtRecFN_small.scala:203:16] output io_rawOut_sign, // @[DivSqrtRecFN_small.scala:203:16] output [6:0] io_rawOut_sExp, // @[DivSqrtRecFN_small.scala:203:16] output [13:0] io_rawOut_sig // @[DivSqrtRecFN_small.scala:203:16] ); wire io_inValid_0 = io_inValid; // @[DivSqrtRecFN_small.scala:199:5] wire io_sqrtOp_0 = io_sqrtOp; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isNaN_0 = io_a_isNaN; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isInf_0 = io_a_isInf; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_isZero_0 = io_a_isZero; // @[DivSqrtRecFN_small.scala:199:5] wire io_a_sign_0 = io_a_sign; // @[DivSqrtRecFN_small.scala:199:5] wire [6:0] io_a_sExp_0 = io_a_sExp; // @[DivSqrtRecFN_small.scala:199:5] wire [11:0] io_a_sig_0 = io_a_sig; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isNaN_0 = io_b_isNaN; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isInf_0 = io_b_isInf; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_isZero_0 = io_b_isZero; // @[DivSqrtRecFN_small.scala:199:5] wire io_b_sign_0 = io_b_sign; // @[DivSqrtRecFN_small.scala:199:5] wire [6:0] io_b_sExp_0 = io_b_sExp; // @[DivSqrtRecFN_small.scala:199:5] wire [11:0] io_b_sig_0 = io_b_sig; // @[DivSqrtRecFN_small.scala:199:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[DivSqrtRecFN_small.scala:199:5] wire [1:0] _inReady_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [1:0] _rawOutValid_T_15 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [1:0] _cycleNum_T_11 = 2'h1; // @[DivSqrtRecFN_small.scala:313:61] wire [8:0] _fractB_Z_T_19 = 9'h0; // @[DivSqrtRecFN_small.scala:345:16] wire [11:0] _trialTerm_T_16 = 12'h800; // @[DivSqrtRecFN_small.scala:366:42] wire [11:0] _trialTerm2_newBit0_T_3 = 12'h800; // @[DivSqrtRecFN_small.scala:373:85] wire _inReady_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:317:38] wire _rawOutValid_T_2 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:318:42] wire _fractB_Z_T_22 = 1'h1; // @[DivSqrtRecFN_small.scala:346:45] wire _nextNotZeroRem_Z_2_T_21 = 1'h1; // @[DivSqrtRecFN_small.scala:384:9] wire _nextRem_Z_2_T_9 = 1'h1; // @[DivSqrtRecFN_small.scala:388:13] wire processTwoBits = 1'h0; // @[DivSqrtRecFN_small.scala:300:42] wire _inReady_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24] wire _inReady_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:317:38] wire _inReady_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20] wire _inReady_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16] wire _rawOutValid_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_6 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:308:24] wire _rawOutValid_T_8 = 1'h0; // @[DivSqrtRecFN_small.scala:318:42] wire _rawOutValid_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:307:20] wire _rawOutValid_T_10 = 1'h0; // @[DivSqrtRecFN_small.scala:306:16] wire _fractB_Z_T_17 = 1'h0; // @[DivSqrtRecFN_small.scala:345:42] wire _nextNotZeroRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:382:24] wire _nextNotZeroRem_Z_2_T_7 = 1'h0; // @[DivSqrtRecFN_small.scala:382:34] wire _nextNotZeroRem_Z_2_T_9 = 1'h0; // @[DivSqrtRecFN_small.scala:383:24] wire _nextNotZeroRem_Z_2_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:383:35] wire _nextNotZeroRem_Z_2_T_19 = 1'h0; // @[DivSqrtRecFN_small.scala:382:85] wire _nextNotZeroRem_Z_2_T_20 = 1'h0; // @[DivSqrtRecFN_small.scala:384:26] wire _nextRem_Z_2_T = 1'h0; // @[DivSqrtRecFN_small.scala:386:28] wire _nextRem_Z_2_T_5 = 1'h0; // @[DivSqrtRecFN_small.scala:387:28] wire _sigX_Z_T_18 = 1'h0; // @[DivSqrtRecFN_small.scala:399:32] wire [12:0] _nextRem_Z_2_T_3 = 13'h0; // @[DivSqrtRecFN_small.scala:386:12] wire [12:0] _nextRem_Z_2_T_7 = 13'h0; // @[DivSqrtRecFN_small.scala:387:12] wire [12:0] _nextRem_Z_2_T_8 = 13'h0; // @[DivSqrtRecFN_small.scala:386:81] wire [12:0] _sigX_Z_T_20 = 13'h0; // @[DivSqrtRecFN_small.scala:399:16] wire _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:404:40] wire _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:405:40] wire _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:407:36] wire _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:408:36] wire [13:0] _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:414:35] wire io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5] wire [6:0] io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5] wire [13:0] io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5] wire [2:0] io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5] wire io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5] reg [3:0] cycleNum; // @[DivSqrtRecFN_small.scala:224:33] reg inReady; // @[DivSqrtRecFN_small.scala:225:33] assign io_inReady_0 = inReady; // @[DivSqrtRecFN_small.scala:199:5, :225:33] reg rawOutValid; // @[DivSqrtRecFN_small.scala:226:33] reg sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29] reg majorExc_Z; // @[DivSqrtRecFN_small.scala:229:29] reg isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29] assign io_rawOut_isNaN_0 = isNaN_Z; // @[DivSqrtRecFN_small.scala:199:5, :231:29] reg isInf_Z; // @[DivSqrtRecFN_small.scala:232:29] assign io_rawOut_isInf_0 = isInf_Z; // @[DivSqrtRecFN_small.scala:199:5, :232:29] reg isZero_Z; // @[DivSqrtRecFN_small.scala:233:29] assign io_rawOut_isZero_0 = isZero_Z; // @[DivSqrtRecFN_small.scala:199:5, :233:29] reg sign_Z; // @[DivSqrtRecFN_small.scala:234:29] assign io_rawOut_sign_0 = sign_Z; // @[DivSqrtRecFN_small.scala:199:5, :234:29] reg [6:0] sExp_Z; // @[DivSqrtRecFN_small.scala:235:29] assign io_rawOut_sExp_0 = sExp_Z; // @[DivSqrtRecFN_small.scala:199:5, :235:29] reg [10:0] fractB_Z; // @[DivSqrtRecFN_small.scala:236:29] reg [2:0] roundingMode_Z; // @[DivSqrtRecFN_small.scala:237:29] assign io_roundingModeOut_0 = roundingMode_Z; // @[DivSqrtRecFN_small.scala:199:5, :237:29] reg [12:0] rem_Z; // @[DivSqrtRecFN_small.scala:243:29] reg notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29] reg [12:0] sigX_Z; // @[DivSqrtRecFN_small.scala:245:29] wire _notSigNaNIn_invalidExc_S_div_T = io_a_isZero_0 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :254:24] wire _notSigNaNIn_invalidExc_S_div_T_1 = io_a_isInf_0 & io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :254:59] wire notSigNaNIn_invalidExc_S_div = _notSigNaNIn_invalidExc_S_div_T | _notSigNaNIn_invalidExc_S_div_T_1; // @[DivSqrtRecFN_small.scala:254:{24,42,59}] wire _notSigNaNIn_invalidExc_S_sqrt_T = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9] wire _notSigNaNIn_invalidExc_S_sqrt_T_1 = ~io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :256:27] wire _notSigNaNIn_invalidExc_S_sqrt_T_2 = _notSigNaNIn_invalidExc_S_sqrt_T & _notSigNaNIn_invalidExc_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:256:{9,24,27}] wire notSigNaNIn_invalidExc_S_sqrt = _notSigNaNIn_invalidExc_S_sqrt_T_2 & io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :256:{24,43}] wire _majorExc_S_T = io_a_sig_0[9]; // @[common.scala:82:56] wire _majorExc_S_T_4 = io_a_sig_0[9]; // @[common.scala:82:56] wire _majorExc_S_T_1 = ~_majorExc_S_T; // @[common.scala:82:{49,56}] wire _majorExc_S_T_2 = io_a_isNaN_0 & _majorExc_S_T_1; // @[common.scala:82:{46,49}] wire _majorExc_S_T_3 = _majorExc_S_T_2 | notSigNaNIn_invalidExc_S_sqrt; // @[common.scala:82:46] wire _majorExc_S_T_5 = ~_majorExc_S_T_4; // @[common.scala:82:{49,56}] wire _majorExc_S_T_6 = io_a_isNaN_0 & _majorExc_S_T_5; // @[common.scala:82:{46,49}] wire _majorExc_S_T_7 = io_b_sig_0[9]; // @[common.scala:82:56] wire _majorExc_S_T_8 = ~_majorExc_S_T_7; // @[common.scala:82:{49,56}] wire _majorExc_S_T_9 = io_b_isNaN_0 & _majorExc_S_T_8; // @[common.scala:82:{46,49}] wire _majorExc_S_T_10 = _majorExc_S_T_6 | _majorExc_S_T_9; // @[common.scala:82:46] wire _majorExc_S_T_11 = _majorExc_S_T_10 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :260:{38,66}] wire _majorExc_S_T_12 = ~io_a_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :256:9, :262:18] wire _majorExc_S_T_13 = ~io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :262:36] wire _majorExc_S_T_14 = _majorExc_S_T_12 & _majorExc_S_T_13; // @[DivSqrtRecFN_small.scala:262:{18,33,36}] wire _majorExc_S_T_15 = _majorExc_S_T_14 & io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :262:{33,51}] wire _majorExc_S_T_16 = _majorExc_S_T_11 | _majorExc_S_T_15; // @[DivSqrtRecFN_small.scala:260:66, :261:46, :262:51] wire majorExc_S = io_sqrtOp_0 ? _majorExc_S_T_3 : _majorExc_S_T_16; // @[DivSqrtRecFN_small.scala:199:5, :258:12, :259:38, :261:46] wire _isNaN_S_T = io_a_isNaN_0 | notSigNaNIn_invalidExc_S_sqrt; // @[DivSqrtRecFN_small.scala:199:5, :256:43, :266:26] wire _isNaN_S_T_1 = io_a_isNaN_0 | io_b_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5, :267:26] wire _isNaN_S_T_2 = _isNaN_S_T_1 | notSigNaNIn_invalidExc_S_div; // @[DivSqrtRecFN_small.scala:254:42, :267:{26,42}] wire isNaN_S = io_sqrtOp_0 ? _isNaN_S_T : _isNaN_S_T_2; // @[DivSqrtRecFN_small.scala:199:5, :265:12, :266:26, :267:42] wire _isInf_S_T = io_a_isInf_0 | io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :269:63] wire isInf_S = io_sqrtOp_0 ? io_a_isInf_0 : _isInf_S_T; // @[DivSqrtRecFN_small.scala:199:5, :269:{23,63}] wire _isZero_S_T = io_a_isZero_0 | io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :270:64] wire isZero_S = io_sqrtOp_0 ? io_a_isZero_0 : _isZero_S_T; // @[DivSqrtRecFN_small.scala:199:5, :270:{23,64}] wire _sign_S_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33] wire _sign_S_T_1 = _sign_S_T & io_b_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :271:{33,45}] wire sign_S = io_a_sign_0 ^ _sign_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :271:{30,45}] wire _specialCaseA_S_T = io_a_isNaN_0 | io_a_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :273:39] wire specialCaseA_S = _specialCaseA_S_T | io_a_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :273:{39,55}] wire _specialCaseB_S_T = io_b_isNaN_0 | io_b_isInf_0; // @[DivSqrtRecFN_small.scala:199:5, :274:39] wire specialCaseB_S = _specialCaseB_S_T | io_b_isZero_0; // @[DivSqrtRecFN_small.scala:199:5, :274:{39,55}] wire _normalCase_S_div_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28] wire _normalCase_S_div_T_1 = ~specialCaseB_S; // @[DivSqrtRecFN_small.scala:274:55, :275:48] wire normalCase_S_div = _normalCase_S_div_T & _normalCase_S_div_T_1; // @[DivSqrtRecFN_small.scala:275:{28,45,48}] wire _normalCase_S_sqrt_T = ~specialCaseA_S; // @[DivSqrtRecFN_small.scala:273:55, :275:28, :276:29] wire _normalCase_S_sqrt_T_1 = ~io_a_sign_0; // @[DivSqrtRecFN_small.scala:199:5, :276:49] wire normalCase_S_sqrt = _normalCase_S_sqrt_T & _normalCase_S_sqrt_T_1; // @[DivSqrtRecFN_small.scala:276:{29,46,49}] wire normalCase_S = io_sqrtOp_0 ? normalCase_S_sqrt : normalCase_S_div; // @[DivSqrtRecFN_small.scala:199:5, :275:45, :276:46, :277:27] wire _sExpQuot_S_div_T = io_b_sExp_0[5]; // @[DivSqrtRecFN_small.scala:199:5, :281:28] wire [4:0] _sExpQuot_S_div_T_1 = io_b_sExp_0[4:0]; // @[DivSqrtRecFN_small.scala:199:5, :281:52] wire [4:0] _sExpQuot_S_div_T_2 = ~_sExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:281:{40,52}] wire [5:0] _sExpQuot_S_div_T_3 = {_sExpQuot_S_div_T, _sExpQuot_S_div_T_2}; // @[DivSqrtRecFN_small.scala:281:{16,28,40}] wire [5:0] _sExpQuot_S_div_T_4 = _sExpQuot_S_div_T_3; // @[DivSqrtRecFN_small.scala:281:{16,71}] wire [7:0] sExpQuot_S_div = {io_a_sExp_0[6], io_a_sExp_0} + {{2{_sExpQuot_S_div_T_4[5]}}, _sExpQuot_S_div_T_4}; // @[DivSqrtRecFN_small.scala:199:5, :280:21, :281:71] wire _sSatExpQuot_S_div_T = $signed(sExpQuot_S_div) > 8'sh37; // @[DivSqrtRecFN_small.scala:280:21, :284:48] wire [3:0] _sSatExpQuot_S_div_T_1 = sExpQuot_S_div[6:3]; // @[DivSqrtRecFN_small.scala:280:21, :286:31] wire [3:0] _sSatExpQuot_S_div_T_2 = _sSatExpQuot_S_div_T ? 4'h6 : _sSatExpQuot_S_div_T_1; // @[DivSqrtRecFN_small.scala:284:{16,48}, :286:31] wire [2:0] _sSatExpQuot_S_div_T_3 = sExpQuot_S_div[2:0]; // @[DivSqrtRecFN_small.scala:280:21, :288:27] wire [6:0] _sSatExpQuot_S_div_T_4 = {_sSatExpQuot_S_div_T_2, _sSatExpQuot_S_div_T_3}; // @[DivSqrtRecFN_small.scala:284:{12,16}, :288:27] wire [6:0] sSatExpQuot_S_div = _sSatExpQuot_S_div_T_4; // @[DivSqrtRecFN_small.scala:284:12, :289:11] wire _evenSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48] wire _oddSqrt_S_T = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :292:48] wire _inReady_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _rawOutValid_T_4 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _cycleNum_T_3 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :308:36] wire _fractB_Z_T_6 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :343:52] wire _fractB_Z_T_11 = io_a_sExp_0[0]; // @[DivSqrtRecFN_small.scala:199:5, :291:48, :344:54] wire _evenSqrt_S_T_1 = ~_evenSqrt_S_T; // @[DivSqrtRecFN_small.scala:291:{35,48}] wire evenSqrt_S = io_sqrtOp_0 & _evenSqrt_S_T_1; // @[DivSqrtRecFN_small.scala:199:5, :291:{32,35}] wire oddSqrt_S = io_sqrtOp_0 & _oddSqrt_S_T; // @[DivSqrtRecFN_small.scala:199:5, :292:{32,48}] wire idle = cycleNum == 4'h0; // @[DivSqrtRecFN_small.scala:224:33, :296:25] wire entering = inReady & io_inValid_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :297:28] wire entering_normalCase = entering & normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :297:28, :298:40] wire _processTwoBits_T = cycleNum > 4'h2; // @[DivSqrtRecFN_small.scala:224:33, :300:35] wire _skipCycle2_T = cycleNum == 4'h3; // @[DivSqrtRecFN_small.scala:224:33, :301:31] wire _skipCycle2_T_1 = sigX_Z[12]; // @[DivSqrtRecFN_small.scala:245:29, :301:48] wire _skipCycle2_T_2 = _skipCycle2_T & _skipCycle2_T_1; // @[DivSqrtRecFN_small.scala:301:{31,39,48}] wire skipCycle2 = _skipCycle2_T_2; // @[DivSqrtRecFN_small.scala:301:{39,63}] wire _inReady_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _rawOutValid_T_22 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _cycleNum_T_16 = skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :314:16] wire _inReady_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _inReady_T_1 = entering & _inReady_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _inReady_T_3 = _inReady_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire _inReady_T_11 = _inReady_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}] wire _inReady_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _inReady_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _inReady_T_14 = _inReady_T_12 & _inReady_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [4:0] _GEN = {1'h0, cycleNum} - 5'h1; // @[DivSqrtRecFN_small.scala:224:33, :313:56] wire [4:0] _inReady_T_16; // @[DivSqrtRecFN_small.scala:313:56] assign _inReady_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [4:0] _rawOutValid_T_16; // @[DivSqrtRecFN_small.scala:313:56] assign _rawOutValid_T_16 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [4:0] _cycleNum_T_12; // @[DivSqrtRecFN_small.scala:313:56] assign _cycleNum_T_12 = _GEN; // @[DivSqrtRecFN_small.scala:313:56] wire [3:0] _inReady_T_17 = _inReady_T_16[3:0]; // @[DivSqrtRecFN_small.scala:313:56] wire _inReady_T_18 = _inReady_T_17 < 4'h2; // @[DivSqrtRecFN_small.scala:313:56, :317:38] wire _inReady_T_19 = _inReady_T_14 & _inReady_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :317:38] wire _inReady_T_20 = _inReady_T_11 | _inReady_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire _inReady_T_23 = _inReady_T_20 | _inReady_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire _inReady_T_24 = _inReady_T_23; // @[DivSqrtRecFN_small.scala:313:95, :317:46] wire _rawOutValid_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _rawOutValid_T_1 = entering & _rawOutValid_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _rawOutValid_T_3 = _rawOutValid_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire _rawOutValid_T_11 = _rawOutValid_T_3; // @[DivSqrtRecFN_small.scala:305:{16,57}] wire _rawOutValid_T_12 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _rawOutValid_T_13 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _rawOutValid_T_14 = _rawOutValid_T_12 & _rawOutValid_T_13; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [3:0] _rawOutValid_T_17 = _rawOutValid_T_16[3:0]; // @[DivSqrtRecFN_small.scala:313:56] wire _rawOutValid_T_18 = _rawOutValid_T_17 == 4'h1; // @[DivSqrtRecFN_small.scala:313:56, :318:42] wire _rawOutValid_T_19 = _rawOutValid_T_14 & _rawOutValid_T_18; // @[DivSqrtRecFN_small.scala:313:{16,28}, :318:42] wire _rawOutValid_T_20 = _rawOutValid_T_11 | _rawOutValid_T_19; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire _rawOutValid_T_23 = _rawOutValid_T_20 | _rawOutValid_T_22; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire _rawOutValid_T_24 = _rawOutValid_T_23; // @[DivSqrtRecFN_small.scala:313:95, :318:51] wire _cycleNum_T = ~normalCase_S; // @[DivSqrtRecFN_small.scala:277:27, :305:28] wire _cycleNum_T_1 = entering & _cycleNum_T; // @[DivSqrtRecFN_small.scala:297:28, :305:{26,28}] wire _cycleNum_T_2 = _cycleNum_T_1; // @[DivSqrtRecFN_small.scala:305:{16,26}] wire [3:0] _cycleNum_T_4 = _cycleNum_T_3 ? 4'hB : 4'hC; // @[DivSqrtRecFN_small.scala:308:{24,36}] wire [3:0] _cycleNum_T_5 = io_sqrtOp_0 ? _cycleNum_T_4 : 4'hD; // @[DivSqrtRecFN_small.scala:199:5, :307:20, :308:24] wire [3:0] _cycleNum_T_6 = entering_normalCase ? _cycleNum_T_5 : 4'h0; // @[DivSqrtRecFN_small.scala:298:40, :306:16, :307:20] wire [3:0] _cycleNum_T_7 = {3'h0, _cycleNum_T_2} | _cycleNum_T_6; // @[DivSqrtRecFN_small.scala:305:{16,57}, :306:16, :313:56] wire _cycleNum_T_8 = ~entering; // @[DivSqrtRecFN_small.scala:297:28, :313:17] wire _cycleNum_T_9 = ~skipCycle2; // @[DivSqrtRecFN_small.scala:301:63, :313:31] wire _cycleNum_T_10 = _cycleNum_T_8 & _cycleNum_T_9; // @[DivSqrtRecFN_small.scala:313:{17,28,31}] wire [3:0] _cycleNum_T_13 = _cycleNum_T_12[3:0]; // @[DivSqrtRecFN_small.scala:313:56] wire [3:0] _cycleNum_T_14 = _cycleNum_T_10 ? _cycleNum_T_13 : 4'h0; // @[DivSqrtRecFN_small.scala:313:{16,28,56}] wire [3:0] _cycleNum_T_15 = _cycleNum_T_7 | _cycleNum_T_14; // @[DivSqrtRecFN_small.scala:305:57, :312:15, :313:16] wire [3:0] _cycleNum_T_17 = {_cycleNum_T_15[3:1], _cycleNum_T_15[0] | _cycleNum_T_16}; // @[DivSqrtRecFN_small.scala:312:15, :313:95, :314:16] wire [5:0] _sExp_Z_T = io_a_sExp_0[6:1]; // @[DivSqrtRecFN_small.scala:199:5, :335:29] wire [6:0] _sExp_Z_T_1 = {_sExp_Z_T[5], _sExp_Z_T} + 7'h10; // @[DivSqrtRecFN_small.scala:335:{29,34}] wire [6:0] _sExp_Z_T_2 = io_sqrtOp_0 ? _sExp_Z_T_1 : sSatExpQuot_S_div; // @[DivSqrtRecFN_small.scala:199:5, :289:11, :334:16, :335:34] wire _fractB_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :342:28] wire _fractB_Z_T_1 = inReady & _fractB_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :342:{25,28}] wire [9:0] _fractB_Z_T_2 = io_b_sig_0[9:0]; // @[DivSqrtRecFN_small.scala:199:5, :342:73] wire [10:0] _fractB_Z_T_3 = {_fractB_Z_T_2, 1'h0}; // @[DivSqrtRecFN_small.scala:342:{73,90}] wire [10:0] _fractB_Z_T_4 = _fractB_Z_T_1 ? _fractB_Z_T_3 : 11'h0; // @[DivSqrtRecFN_small.scala:342:{16,25,90}] wire _GEN_0 = inReady & io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :225:33, :343:25] wire _fractB_Z_T_5; // @[DivSqrtRecFN_small.scala:343:25] assign _fractB_Z_T_5 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25] wire _fractB_Z_T_10; // @[DivSqrtRecFN_small.scala:344:25] assign _fractB_Z_T_10 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :344:25] wire _sigX_Z_T_4; // @[DivSqrtRecFN_small.scala:395:25] assign _sigX_Z_T_4 = _GEN_0; // @[DivSqrtRecFN_small.scala:343:25, :395:25] wire _fractB_Z_T_7 = _fractB_Z_T_5 & _fractB_Z_T_6; // @[DivSqrtRecFN_small.scala:343:{25,38,52}] wire [9:0] _fractB_Z_T_8 = {_fractB_Z_T_7, 9'h0}; // @[DivSqrtRecFN_small.scala:343:{16,38}] wire [10:0] _fractB_Z_T_9 = {_fractB_Z_T_4[10], _fractB_Z_T_4[9:0] | _fractB_Z_T_8}; // @[DivSqrtRecFN_small.scala:342:{16,100}, :343:16] wire _fractB_Z_T_12 = ~_fractB_Z_T_11; // @[DivSqrtRecFN_small.scala:344:{41,54}] wire _fractB_Z_T_13 = _fractB_Z_T_10 & _fractB_Z_T_12; // @[DivSqrtRecFN_small.scala:344:{25,38,41}] wire [10:0] _fractB_Z_T_14 = {_fractB_Z_T_13, 10'h0}; // @[DivSqrtRecFN_small.scala:344:{16,38}] wire [10:0] _fractB_Z_T_15 = _fractB_Z_T_9 | _fractB_Z_T_14; // @[DivSqrtRecFN_small.scala:342:100, :343:100, :344:16] wire [10:0] _fractB_Z_T_20 = _fractB_Z_T_15; // @[DivSqrtRecFN_small.scala:343:100, :344:100] wire _fractB_Z_T_16 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :345:17] wire [8:0] _fractB_Z_T_18 = fractB_Z[10:2]; // @[DivSqrtRecFN_small.scala:236:29, :345:71] wire _fractB_Z_T_21 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :346:17] wire _fractB_Z_T_23 = _fractB_Z_T_21; // @[DivSqrtRecFN_small.scala:346:{17,42}] wire [9:0] _fractB_Z_T_24 = fractB_Z[10:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71] wire [9:0] _trialTerm2_newBit0_T = fractB_Z[10:1]; // @[DivSqrtRecFN_small.scala:236:29, :346:71, :373:52] wire [9:0] _fractB_Z_T_25 = _fractB_Z_T_23 ? _fractB_Z_T_24 : 10'h0; // @[DivSqrtRecFN_small.scala:346:{16,42,71}] wire [10:0] _fractB_Z_T_26 = {_fractB_Z_T_20[10], _fractB_Z_T_20[9:0] | _fractB_Z_T_25}; // @[DivSqrtRecFN_small.scala:344:100, :345:100, :346:16] wire _rem_T = ~oddSqrt_S; // @[DivSqrtRecFN_small.scala:292:32, :352:24] wire _rem_T_1 = inReady & _rem_T; // @[DivSqrtRecFN_small.scala:225:33, :352:{21,24}] wire [12:0] _rem_T_2 = {io_a_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :352:47] wire [12:0] _rem_T_3 = _rem_T_1 ? _rem_T_2 : 13'h0; // @[DivSqrtRecFN_small.scala:352:{12,21,47}] wire _GEN_1 = inReady & oddSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :292:32, :353:21] wire _rem_T_4; // @[DivSqrtRecFN_small.scala:353:21] assign _rem_T_4 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21] wire _trialTerm_T_7; // @[DivSqrtRecFN_small.scala:364:21] assign _trialTerm_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :364:21] wire _sigX_Z_T_7; // @[DivSqrtRecFN_small.scala:396:25] assign _sigX_Z_T_7 = _GEN_1; // @[DivSqrtRecFN_small.scala:353:21, :396:25] wire [1:0] _rem_T_5 = io_a_sig_0[10:9]; // @[DivSqrtRecFN_small.scala:199:5, :354:27] wire [2:0] _rem_T_6 = {1'h0, _rem_T_5} - 3'h1; // @[DivSqrtRecFN_small.scala:354:{27,56}] wire [1:0] _rem_T_7 = _rem_T_6[1:0]; // @[DivSqrtRecFN_small.scala:354:56] wire [8:0] _rem_T_8 = io_a_sig_0[8:0]; // @[DivSqrtRecFN_small.scala:199:5, :355:27] wire [11:0] _rem_T_9 = {_rem_T_8, 3'h0}; // @[DivSqrtRecFN_small.scala:313:56, :355:{27,44}] wire [13:0] _rem_T_10 = {_rem_T_7, _rem_T_9}; // @[DivSqrtRecFN_small.scala:354:{16,56}, :355:44] wire [13:0] _rem_T_11 = _rem_T_4 ? _rem_T_10 : 14'h0; // @[DivSqrtRecFN_small.scala:353:{12,21}, :354:16] wire [13:0] _rem_T_12 = {1'h0, _rem_T_3} | _rem_T_11; // @[DivSqrtRecFN_small.scala:352:{12,57}, :353:12] wire _rem_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :359:13] wire [13:0] _rem_T_14 = {rem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:243:29, :359:29] wire [13:0] _rem_T_15 = _rem_T_13 ? _rem_T_14 : 14'h0; // @[DivSqrtRecFN_small.scala:359:{12,13,29}] wire [13:0] rem = _rem_T_12 | _rem_T_15; // @[DivSqrtRecFN_small.scala:352:57, :358:11, :359:12] wire [15:0] _bitMask_T = 16'h1 << cycleNum; // @[DivSqrtRecFN_small.scala:224:33, :360:23] wire [13:0] bitMask = _bitMask_T[15:2]; // @[DivSqrtRecFN_small.scala:360:{23,34}] wire _trialTerm_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :362:24] wire _trialTerm_T_1 = inReady & _trialTerm_T; // @[DivSqrtRecFN_small.scala:225:33, :362:{21,24}] wire [12:0] _trialTerm_T_2 = {io_b_sig_0, 1'h0}; // @[DivSqrtRecFN_small.scala:199:5, :362:48] wire [12:0] _trialTerm_T_3 = _trialTerm_T_1 ? _trialTerm_T_2 : 13'h0; // @[DivSqrtRecFN_small.scala:362:{12,21,48}] wire _trialTerm_T_4 = inReady & evenSqrt_S; // @[DivSqrtRecFN_small.scala:225:33, :291:32, :363:21] wire [11:0] _trialTerm_T_5 = {_trialTerm_T_4, 11'h0}; // @[DivSqrtRecFN_small.scala:363:{12,21}] wire [12:0] _trialTerm_T_6 = {_trialTerm_T_3[12], _trialTerm_T_3[11:0] | _trialTerm_T_5}; // @[DivSqrtRecFN_small.scala:362:{12,74}, :363:12] wire [12:0] _trialTerm_T_8 = _trialTerm_T_7 ? 13'h1400 : 13'h0; // @[DivSqrtRecFN_small.scala:364:{12,21}] wire [12:0] _trialTerm_T_9 = _trialTerm_T_6 | _trialTerm_T_8; // @[DivSqrtRecFN_small.scala:362:74, :363:74, :364:12] wire _trialTerm_T_10 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :365:13] wire [10:0] _trialTerm_T_11 = _trialTerm_T_10 ? fractB_Z : 11'h0; // @[DivSqrtRecFN_small.scala:236:29, :365:{12,13}] wire [12:0] _trialTerm_T_12 = {_trialTerm_T_9[12:11], _trialTerm_T_9[10:0] | _trialTerm_T_11}; // @[DivSqrtRecFN_small.scala:363:74, :364:74, :365:12] wire _trialTerm_T_13 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :366:13] wire _trialTerm_T_14 = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26] wire _trialTerm_T_15 = _trialTerm_T_13 & _trialTerm_T_14; // @[DivSqrtRecFN_small.scala:366:{13,23,26}] wire [11:0] _trialTerm_T_17 = {_trialTerm_T_15, 11'h0}; // @[DivSqrtRecFN_small.scala:366:{12,23}] wire [12:0] _trialTerm_T_18 = {_trialTerm_T_12[12], _trialTerm_T_12[11:0] | _trialTerm_T_17}; // @[DivSqrtRecFN_small.scala:364:74, :365:74, :366:12] wire _trialTerm_T_19 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :367:13] wire _trialTerm_T_20 = _trialTerm_T_19 & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :367:{13,23}] wire [13:0] _GEN_2 = {sigX_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:245:29, :367:44] wire [13:0] _trialTerm_T_21; // @[DivSqrtRecFN_small.scala:367:44] assign _trialTerm_T_21 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44] wire [13:0] _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:373:64] assign _trialTerm2_newBit0_T_1 = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :373:64] wire [13:0] _io_rawOut_sig_T; // @[DivSqrtRecFN_small.scala:414:31] assign _io_rawOut_sig_T = _GEN_2; // @[DivSqrtRecFN_small.scala:367:44, :414:31] wire [13:0] _trialTerm_T_22 = _trialTerm_T_20 ? _trialTerm_T_21 : 14'h0; // @[DivSqrtRecFN_small.scala:367:{12,23,44}] wire [13:0] trialTerm = {1'h0, _trialTerm_T_18} | _trialTerm_T_22; // @[DivSqrtRecFN_small.scala:365:74, :366:74, :367:12] wire [14:0] _trialRem_T = {1'h0, rem}; // @[DivSqrtRecFN_small.scala:358:11, :368:24] wire [14:0] _trialRem_T_1 = {1'h0, trialTerm}; // @[DivSqrtRecFN_small.scala:366:74, :368:42] wire [15:0] trialRem = {_trialRem_T[14], _trialRem_T} - {_trialRem_T_1[14], _trialRem_T_1}; // @[DivSqrtRecFN_small.scala:368:{24,29,42}] wire [15:0] _nextRem_Z_T = trialRem; // @[DivSqrtRecFN_small.scala:368:29, :371:42] wire newBit = $signed(trialRem) > -16'sh1; // @[DivSqrtRecFN_small.scala:368:29, :369:23] wire [15:0] _nextRem_Z_T_1 = newBit ? _nextRem_Z_T : {2'h0, rem}; // @[DivSqrtRecFN_small.scala:300:35, :358:11, :369:23, :371:{24,42}] wire [12:0] nextRem_Z = _nextRem_Z_T_1[12:0]; // @[DivSqrtRecFN_small.scala:371:{24,54}] wire [12:0] _nextRem_Z_2_T_10 = nextRem_Z; // @[DivSqrtRecFN_small.scala:371:54, :388:12] wire [13:0] rem2 = {nextRem_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:371:54, :372:25] wire [13:0] _trialTerm2_newBit0_T_2 = {4'h0, _trialTerm2_newBit0_T} | _trialTerm2_newBit0_T_1; // @[DivSqrtRecFN_small.scala:373:{52,56,64}] wire [11:0] _trialTerm2_newBit0_T_4 = {1'h1, fractB_Z}; // @[DivSqrtRecFN_small.scala:236:29, :373:78] wire [13:0] trialTerm2_newBit0 = sqrtOp_Z ? _trialTerm2_newBit0_T_2 : {2'h0, _trialTerm2_newBit0_T_4}; // @[DivSqrtRecFN_small.scala:228:29, :300:35, :373:{33,56,78}] wire [11:0] _trialTerm2_newBit1_T = {fractB_Z, 1'h0}; // @[DivSqrtRecFN_small.scala:236:29, :374:73] wire [11:0] _trialTerm2_newBit1_T_1 = sqrtOp_Z ? _trialTerm2_newBit1_T : 12'h0; // @[DivSqrtRecFN_small.scala:228:29, :374:{54,73}] wire [13:0] trialTerm2_newBit1 = {trialTerm2_newBit0[13:12], trialTerm2_newBit0[11:0] | _trialTerm2_newBit1_T_1}; // @[DivSqrtRecFN_small.scala:373:33, :374:{49,54}] wire [16:0] _GEN_3 = {trialRem, 1'h0}; // @[DivSqrtRecFN_small.scala:368:29, :377:22] wire [16:0] _trialRem2_T; // @[DivSqrtRecFN_small.scala:377:22] assign _trialRem2_T = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22] wire [16:0] _nextNotZeroRem_Z_2_T_1; // @[DivSqrtRecFN_small.scala:382:53] assign _nextNotZeroRem_Z_2_T_1 = _GEN_3; // @[DivSqrtRecFN_small.scala:377:22, :382:53] wire [14:0] _GEN_4 = {1'h0, trialTerm2_newBit1}; // @[DivSqrtRecFN_small.scala:374:49, :377:48] wire [14:0] _trialRem2_T_1; // @[DivSqrtRecFN_small.scala:377:48] assign _trialRem2_T_1 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48] wire [14:0] _nextNotZeroRem_Z_2_T_2; // @[DivSqrtRecFN_small.scala:382:79] assign _nextNotZeroRem_Z_2_T_2 = _GEN_4; // @[DivSqrtRecFN_small.scala:377:48, :382:79] wire [17:0] _trialRem2_T_2 = {_trialRem2_T[16], _trialRem2_T} - {{3{_trialRem2_T_1[14]}}, _trialRem2_T_1}; // @[DivSqrtRecFN_small.scala:377:{22,27,48}] wire [16:0] _trialRem2_T_3 = _trialRem2_T_2[16:0]; // @[DivSqrtRecFN_small.scala:377:27] wire [16:0] _trialRem2_T_4 = _trialRem2_T_3; // @[DivSqrtRecFN_small.scala:377:27] wire [14:0] _GEN_5 = {rem_Z, 2'h0}; // @[DivSqrtRecFN_small.scala:243:29, :300:35, :378:19] wire [14:0] _trialRem2_T_5; // @[DivSqrtRecFN_small.scala:378:19] assign _trialRem2_T_5 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19] wire [14:0] _nextNotZeroRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:383:51] assign _nextNotZeroRem_Z_2_T_10 = _GEN_5; // @[DivSqrtRecFN_small.scala:378:19, :383:51] wire [13:0] _trialRem2_T_6 = _trialRem2_T_5[13:0]; // @[DivSqrtRecFN_small.scala:378:{19,23}] wire [14:0] _trialRem2_T_7 = {1'h0, _trialRem2_T_6}; // @[DivSqrtRecFN_small.scala:378:{23,39}] wire [14:0] _GEN_6 = {1'h0, trialTerm2_newBit0}; // @[DivSqrtRecFN_small.scala:373:33, :378:65] wire [14:0] _trialRem2_T_8; // @[DivSqrtRecFN_small.scala:378:65] assign _trialRem2_T_8 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65] wire [14:0] _nextNotZeroRem_Z_2_T_13; // @[DivSqrtRecFN_small.scala:383:97] assign _nextNotZeroRem_Z_2_T_13 = _GEN_6; // @[DivSqrtRecFN_small.scala:378:65, :383:97] wire [15:0] _trialRem2_T_9 = {_trialRem2_T_7[14], _trialRem2_T_7} - {_trialRem2_T_8[14], _trialRem2_T_8}; // @[DivSqrtRecFN_small.scala:378:{39,44,65}] wire [14:0] _trialRem2_T_10 = _trialRem2_T_9[14:0]; // @[DivSqrtRecFN_small.scala:378:44] wire [14:0] _trialRem2_T_11 = _trialRem2_T_10; // @[DivSqrtRecFN_small.scala:378:44] wire [16:0] trialRem2 = newBit ? _trialRem2_T_4 : {{2{_trialRem2_T_11[14]}}, _trialRem2_T_11}; // @[DivSqrtRecFN_small.scala:369:23, :376:12, :377:27, :378:44] wire [16:0] _nextRem_Z_2_T_1 = trialRem2; // @[DivSqrtRecFN_small.scala:376:12, :386:51] wire newBit2 = $signed(trialRem2) > -17'sh1; // @[DivSqrtRecFN_small.scala:376:12, :379:24] wire _nextNotZeroRem_Z_T = inReady | newBit; // @[DivSqrtRecFN_small.scala:225:33, :369:23, :380:40] wire _nextNotZeroRem_Z_T_1 = |trialRem; // @[DivSqrtRecFN_small.scala:368:29, :380:60] wire nextNotZeroRem_Z = _nextNotZeroRem_Z_T ? _nextNotZeroRem_Z_T_1 : notZeroRem_Z; // @[DivSqrtRecFN_small.scala:244:29, :380:{31,40,60}] wire _nextNotZeroRem_Z_2_T_22 = nextNotZeroRem_Z; // @[DivSqrtRecFN_small.scala:380:31, :384:38] wire [17:0] _nextNotZeroRem_Z_2_T_3 = {_nextNotZeroRem_Z_2_T_1[16], _nextNotZeroRem_Z_2_T_1} - {{3{_nextNotZeroRem_Z_2_T_2[14]}}, _nextNotZeroRem_Z_2_T_2}; // @[DivSqrtRecFN_small.scala:382:{53,58,79}] wire [16:0] _nextNotZeroRem_Z_2_T_4 = _nextNotZeroRem_Z_2_T_3[16:0]; // @[DivSqrtRecFN_small.scala:382:58] wire [16:0] _nextNotZeroRem_Z_2_T_5 = _nextNotZeroRem_Z_2_T_4; // @[DivSqrtRecFN_small.scala:382:58] wire _nextNotZeroRem_Z_2_T_6 = $signed(_nextNotZeroRem_Z_2_T_5) > 17'sh0; // @[DivSqrtRecFN_small.scala:382:{42,58}] wire _nextNotZeroRem_Z_2_T_8 = ~newBit; // @[DivSqrtRecFN_small.scala:369:23, :383:27] wire [13:0] _nextNotZeroRem_Z_2_T_11 = _nextNotZeroRem_Z_2_T_10[13:0]; // @[DivSqrtRecFN_small.scala:383:{51,55}] wire [14:0] _nextNotZeroRem_Z_2_T_12 = {1'h0, _nextNotZeroRem_Z_2_T_11}; // @[DivSqrtRecFN_small.scala:383:{55,71}] wire [15:0] _nextNotZeroRem_Z_2_T_14 = {_nextNotZeroRem_Z_2_T_12[14], _nextNotZeroRem_Z_2_T_12} - {_nextNotZeroRem_Z_2_T_13[14], _nextNotZeroRem_Z_2_T_13}; // @[DivSqrtRecFN_small.scala:383:{71,76,97}] wire [14:0] _nextNotZeroRem_Z_2_T_15 = _nextNotZeroRem_Z_2_T_14[14:0]; // @[DivSqrtRecFN_small.scala:383:76] wire [14:0] _nextNotZeroRem_Z_2_T_16 = _nextNotZeroRem_Z_2_T_15; // @[DivSqrtRecFN_small.scala:383:76] wire _nextNotZeroRem_Z_2_T_17 = $signed(_nextNotZeroRem_Z_2_T_16) > 15'sh0; // @[DivSqrtRecFN_small.scala:383:{43,76}] wire nextNotZeroRem_Z_2 = _nextNotZeroRem_Z_2_T_22; // @[DivSqrtRecFN_small.scala:383:103, :384:38] wire [12:0] _nextRem_Z_2_T_2 = _nextRem_Z_2_T_1[12:0]; // @[DivSqrtRecFN_small.scala:386:{51,57}] wire _nextRem_Z_2_T_4 = ~newBit2; // @[DivSqrtRecFN_small.scala:379:24, :387:31] wire [12:0] _nextRem_Z_2_T_6 = rem2[12:0]; // @[DivSqrtRecFN_small.scala:372:25, :387:45] wire [12:0] nextRem_Z_2 = _nextRem_Z_2_T_10; // @[DivSqrtRecFN_small.scala:387:83, :388:12] wire _sigX_Z_T = ~io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :271:33, :394:28] wire _sigX_Z_T_1 = inReady & _sigX_Z_T; // @[DivSqrtRecFN_small.scala:225:33, :394:{25,28}] wire [12:0] _sigX_Z_T_2 = {newBit, 12'h0}; // @[DivSqrtRecFN_small.scala:369:23, :394:50] wire [12:0] _sigX_Z_T_3 = _sigX_Z_T_1 ? _sigX_Z_T_2 : 13'h0; // @[DivSqrtRecFN_small.scala:394:{16,25,50}] wire [11:0] _sigX_Z_T_5 = {_sigX_Z_T_4, 11'h0}; // @[DivSqrtRecFN_small.scala:395:{16,25}] wire [12:0] _sigX_Z_T_6 = {_sigX_Z_T_3[12], _sigX_Z_T_3[11:0] | _sigX_Z_T_5}; // @[DivSqrtRecFN_small.scala:394:{16,74}, :395:16] wire [10:0] _sigX_Z_T_8 = {newBit, 10'h0}; // @[DivSqrtRecFN_small.scala:369:23, :396:50] wire [10:0] _sigX_Z_T_9 = _sigX_Z_T_7 ? _sigX_Z_T_8 : 11'h0; // @[DivSqrtRecFN_small.scala:396:{16,25,50}] wire [12:0] _sigX_Z_T_10 = {_sigX_Z_T_6[12:11], _sigX_Z_T_6[10:0] | _sigX_Z_T_9}; // @[DivSqrtRecFN_small.scala:394:74, :395:74, :396:16] wire _sigX_Z_T_11 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :397:17] wire [12:0] _sigX_Z_T_12 = _sigX_Z_T_11 ? sigX_Z : 13'h0; // @[DivSqrtRecFN_small.scala:245:29, :397:{16,17}] wire [12:0] _sigX_Z_T_13 = _sigX_Z_T_10 | _sigX_Z_T_12; // @[DivSqrtRecFN_small.scala:395:74, :396:74, :397:16] wire _sigX_Z_T_14 = ~inReady; // @[DivSqrtRecFN_small.scala:225:33, :340:23, :398:17] wire _sigX_Z_T_15 = _sigX_Z_T_14 & newBit; // @[DivSqrtRecFN_small.scala:369:23, :398:{17,27}] wire [13:0] _sigX_Z_T_16 = _sigX_Z_T_15 ? bitMask : 14'h0; // @[DivSqrtRecFN_small.scala:360:34, :398:{16,27}] wire [13:0] _sigX_Z_T_17 = {1'h0, _sigX_Z_T_13} | _sigX_Z_T_16; // @[DivSqrtRecFN_small.scala:396:74, :397:74, :398:16] wire [13:0] _sigX_Z_T_21 = _sigX_Z_T_17; // @[DivSqrtRecFN_small.scala:397:74, :398:74] wire [12:0] _sigX_Z_T_19 = bitMask[13:1]; // @[DivSqrtRecFN_small.scala:360:34, :399:51] wire _io_rawOutValid_div_T = ~sqrtOp_Z; // @[DivSqrtRecFN_small.scala:228:29, :366:26, :404:43] assign _io_rawOutValid_div_T_1 = rawOutValid & _io_rawOutValid_div_T; // @[DivSqrtRecFN_small.scala:226:33, :404:{40,43}] assign io_rawOutValid_div_0 = _io_rawOutValid_div_T_1; // @[DivSqrtRecFN_small.scala:199:5, :404:40] assign _io_rawOutValid_sqrt_T = rawOutValid & sqrtOp_Z; // @[DivSqrtRecFN_small.scala:226:33, :228:29, :405:40] assign io_rawOutValid_sqrt_0 = _io_rawOutValid_sqrt_T; // @[DivSqrtRecFN_small.scala:199:5, :405:40] assign _io_invalidExc_T = majorExc_Z & isNaN_Z; // @[DivSqrtRecFN_small.scala:229:29, :231:29, :407:36] assign io_invalidExc_0 = _io_invalidExc_T; // @[DivSqrtRecFN_small.scala:199:5, :407:36] wire _io_infiniteExc_T = ~isNaN_Z; // @[DivSqrtRecFN_small.scala:231:29, :408:39] assign _io_infiniteExc_T_1 = majorExc_Z & _io_infiniteExc_T; // @[DivSqrtRecFN_small.scala:229:29, :408:{36,39}] assign io_infiniteExc_0 = _io_infiniteExc_T_1; // @[DivSqrtRecFN_small.scala:199:5, :408:36] assign _io_rawOut_sig_T_1 = {_io_rawOut_sig_T[13:1], _io_rawOut_sig_T[0] | notZeroRem_Z}; // @[DivSqrtRecFN_small.scala:244:29, :414:{31,35}] assign io_rawOut_sig_0 = _io_rawOut_sig_T_1; // @[DivSqrtRecFN_small.scala:199:5, :414:35] always @(posedge clock) begin // @[DivSqrtRecFN_small.scala:199:5] if (reset) begin // @[DivSqrtRecFN_small.scala:199:5] cycleNum <= 4'h0; // @[DivSqrtRecFN_small.scala:224:33] inReady <= 1'h1; // @[DivSqrtRecFN_small.scala:225:33] rawOutValid <= 1'h0; // @[DivSqrtRecFN_small.scala:226:33] end else if (~idle | entering) begin // @[DivSqrtRecFN_small.scala:296:25, :297:28, :303:{11,18}] cycleNum <= _cycleNum_T_17; // @[DivSqrtRecFN_small.scala:224:33, :313:95] inReady <= _inReady_T_24; // @[DivSqrtRecFN_small.scala:225:33, :317:46] rawOutValid <= _rawOutValid_T_24; // @[DivSqrtRecFN_small.scala:226:33, :318:51] end if (entering) begin // @[DivSqrtRecFN_small.scala:297:28] sqrtOp_Z <= io_sqrtOp_0; // @[DivSqrtRecFN_small.scala:199:5, :228:29] majorExc_Z <= majorExc_S; // @[DivSqrtRecFN_small.scala:229:29, :258:12] isNaN_Z <= isNaN_S; // @[DivSqrtRecFN_small.scala:231:29, :265:12] isInf_Z <= isInf_S; // @[DivSqrtRecFN_small.scala:232:29, :269:23] isZero_Z <= isZero_S; // @[DivSqrtRecFN_small.scala:233:29, :270:23] sign_Z <= sign_S; // @[DivSqrtRecFN_small.scala:234:29, :271:30] sExp_Z <= _sExp_Z_T_2; // @[DivSqrtRecFN_small.scala:235:29, :334:16] roundingMode_Z <= io_roundingMode_0; // @[DivSqrtRecFN_small.scala:199:5, :237:29] end if (entering | ~inReady & sqrtOp_Z) // @[DivSqrtRecFN_small.scala:225:33, :228:29, :297:28, :340:{20,23,33}] fractB_Z <= _fractB_Z_T_26; // @[DivSqrtRecFN_small.scala:236:29, :345:100] if (entering | ~inReady) begin // @[DivSqrtRecFN_small.scala:225:33, :297:28, :340:23, :390:20] rem_Z <= nextRem_Z_2; // @[DivSqrtRecFN_small.scala:243:29, :387:83] notZeroRem_Z <= nextNotZeroRem_Z_2; // @[DivSqrtRecFN_small.scala:244:29, :383:103] sigX_Z <= _sigX_Z_T_21[12:0]; // @[DivSqrtRecFN_small.scala:245:29, :393:16, :398:74] end always @(posedge) assign io_inReady = io_inReady_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOutValid_div = io_rawOutValid_div_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOutValid_sqrt = io_rawOutValid_sqrt_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_roundingModeOut = io_roundingModeOut_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_invalidExc = io_invalidExc_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_infiniteExc = io_infiniteExc_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sign = io_rawOut_sign_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[DivSqrtRecFN_small.scala:199:5] assign io_rawOut_sig = io_rawOut_sig_0; // @[DivSqrtRecFN_small.scala:199:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w4_d3_i0_18 : input clock : Clock input reset : Reset output io : { flip d : UInt<4>, q : UInt<4>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_144 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q node _output_T_2 = asAsyncReset(reset) node _output_T_3 = bits(io.d, 1, 1) inst output_chain_1 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_145 connect output_chain_1.clock, clock connect output_chain_1.reset, _output_T_2 connect output_chain_1.io.d, _output_T_3 wire output_1 : UInt<1> connect output_1, output_chain_1.io.q node _output_T_4 = asAsyncReset(reset) node _output_T_5 = bits(io.d, 2, 2) inst output_chain_2 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_146 connect output_chain_2.clock, clock connect output_chain_2.reset, _output_T_4 connect output_chain_2.io.d, _output_T_5 wire output_2 : UInt<1> connect output_2, output_chain_2.io.q node _output_T_6 = asAsyncReset(reset) node _output_T_7 = bits(io.d, 3, 3) inst output_chain_3 of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_147 connect output_chain_3.clock, clock connect output_chain_3.reset, _output_T_6 connect output_chain_3.io.d, _output_T_7 wire output_3 : UInt<1> connect output_3, output_chain_3.io.q node io_q_lo = cat(output_1, output_0) node io_q_hi = cat(output_3, output_2) node _io_q_T = cat(io_q_hi, io_q_lo) connect io.q, _io_q_T
module AsyncResetSynchronizerShiftReg_w4_d3_i0_18( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input [3:0] io_d, // @[ShiftReg.scala:36:14] output [3:0] io_q // @[ShiftReg.scala:36:14] ); wire [3:0] io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_2 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_4 = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_6 = reset; // @[SynchronizerReg.scala:86:21] wire [3:0] _io_q_T; // @[SynchronizerReg.scala:90:14] wire [3:0] io_q_0; // @[SynchronizerReg.scala:80:7] wire _output_T_1 = io_d_0[0]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire _output_T_3 = io_d_0[1]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_1; // @[ShiftReg.scala:48:24] wire _output_T_5 = io_d_0[2]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_2; // @[ShiftReg.scala:48:24] wire _output_T_7 = io_d_0[3]; // @[SynchronizerReg.scala:80:7, :87:41] wire output_3; // @[ShiftReg.scala:48:24] wire [1:0] io_q_lo = {output_1, output_0}; // @[SynchronizerReg.scala:90:14] wire [1:0] io_q_hi = {output_3, output_2}; // @[SynchronizerReg.scala:90:14] assign _io_q_T = {io_q_hi, io_q_lo}; // @[SynchronizerReg.scala:90:14] assign io_q_0 = _io_q_T; // @[SynchronizerReg.scala:80:7, :90:14] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_144 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_145 output_chain_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_2), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_3), // @[SynchronizerReg.scala:87:41] .io_q (output_1) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_146 output_chain_2 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_4), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_5), // @[SynchronizerReg.scala:87:41] .io_q (output_2) ); // @[ShiftReg.scala:45:23] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_147 output_chain_3 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T_6), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_7), // @[SynchronizerReg.scala:87:41] .io_q (output_3) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_15 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_15( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_180 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RecFNToRecFN_180( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BoomCore : input clock : Clock input reset : Reset output io : { flip hartid : UInt<1>, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, seip : UInt<1>, lip : UInt<1>[0]}, ifu : { flip fetchpacket : { flip ready : UInt<1>, valid : UInt<1>, bits : { uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[2]}}, arb_ftq_reqs : UInt<5>[3], flip rrd_ftq_resps : { valid : UInt<1>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<4>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>}[3], flip com_pc : UInt<40>, debug_ftq_idx : UInt<5>[2], flip debug_fetch_pc : UInt<40>[2], status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], mcontext : UInt<0>, scontext : UInt<0>, sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, redirect_flush : UInt<1>, redirect_val : UInt<1>, redirect_pc : UInt, redirect_ftq_idx : UInt, redirect_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, commit : { valid : UInt<1>, bits : UInt<32>}, flush_icache : UInt<1>, enable_bpd : UInt<1>, flip perf : { acquire : UInt<1>, tlbMiss : UInt<1>}}, flip ptw : { flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], perf : { l2miss : UInt<1>, l2hit : UInt<1>, pte_miss : UInt<1>, pte_hit : UInt<1>}, flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}, clock_enabled : UInt<1>}, flip rocc : { flip cmd : { flip ready : UInt<1>, valid : UInt<1>, bits : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { rd : UInt<5>, data : UInt<64>}}, mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, phys : UInt<1>, no_resp : UInt<1>, no_alloc : UInt<1>, no_xcpt : UInt<1>, data : UInt<64>, mask : UInt<8>}}, s1_kill : UInt<1>, s1_data : { data : UInt<64>, mask : UInt<8>}, flip s2_nack : UInt<1>, flip s2_nack_cause_raw : UInt<1>, s2_kill : UInt<1>, flip s2_uncached : UInt<1>, flip s2_paddr : UInt<32>, flip resp : { valid : UInt<1>, bits : { addr : UInt<40>, tag : UInt<7>, cmd : UInt<5>, size : UInt<2>, signed : UInt<1>, dprv : UInt<2>, dv : UInt<1>, data : UInt<64>, mask : UInt<8>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, data_raw : UInt<64>, store_data : UInt<64>}}, flip replay_next : UInt<1>, flip s2_xcpt : { ma : { ld : UInt<1>, st : UInt<1>}, pf : { ld : UInt<1>, st : UInt<1>}, gf : { ld : UInt<1>, st : UInt<1>}, ae : { ld : UInt<1>, st : UInt<1>}}, flip s2_gpa : UInt<40>, flip s2_gpa_is_pte : UInt<1>, flip ordered : UInt<1>, flip store_pending : UInt<1>, flip perf : { acquire : UInt<1>, release : UInt<1>, grant : UInt<1>, tlbMiss : UInt<1>, blocked : UInt<1>, canAcceptStoreThenLoad : UInt<1>, canAcceptStoreThenRMW : UInt<1>, canAcceptLoadThenLoad : UInt<1>, storeBufferEmptyAfterLoad : UInt<1>, storeBufferEmptyAfterStore : UInt<1>}, keep_clock_enabled : UInt<1>, flip clock_enabled : UInt<1>}, busy : UInt<1>, interrupt : UInt<1>, flip exception : UInt<1>, flip csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[0]}, flip lsu : { flip agen : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}}[1], flip dgen : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>}}[3], iwakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[1], iresp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1], fresp : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[1], flip sfence : { valid : UInt<1>, bits : { rs1 : UInt<1>, rs2 : UInt<1>, addr : UInt<39>, asid : UInt<1>, hv : UInt<1>, hg : UInt<1>}}, flip dis_uops : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}[2], dis_ldq_idx : UInt<4>[2], dis_stq_idx : UInt<4>[2], ldq_full : UInt<1>[2], stq_full : UInt<1>[2], flip commit : { valids : UInt<1>[2], arch_valids : UInt<1>[2], uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[2], fflags : { valid : UInt<1>, bits : UInt<5>}, debug_insts : UInt<32>[2], debug_wdata : UInt<64>[2]}, flip commit_load_at_rob_head : UInt<1>, clr_bsy : { valid : UInt<1>, bits : UInt<6>}[2], clr_unsafe : { valid : UInt<1>, bits : UInt<6>}[1], flip fence_dmem : UInt<1>, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}, flip rob_pnr_idx : UInt<6>, flip rob_head_idx : UInt<6>, flip exception : UInt<1>, fencei_rdy : UInt<1>, lxcpt : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, cause : UInt<5>, badvaddr : UInt<40>}}, flip tsc_reg : UInt, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<40>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<39>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<48>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[0], flip mcontext : UInt, flip scontext : UInt, perf : { acquire : UInt<1>, release : UInt<1>, tlbMiss : UInt<1>}}, ptw_tlb : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { valid : UInt<1>, bits : { addr : UInt<27>, need_gpa : UInt<1>, vstage1 : UInt<1>, stage2 : UInt<1>}}}, flip resp : { valid : UInt<1>, bits : { ae_ptw : UInt<1>, ae_final : UInt<1>, pf : UInt<1>, gf : UInt<1>, hr : UInt<1>, hw : UInt<1>, hx : UInt<1>, pte : { reserved_for_future : UInt<10>, ppn : UInt<44>, reserved_for_software : UInt<2>, d : UInt<1>, a : UInt<1>, g : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>, v : UInt<1>}, level : UInt<2>, fragmented_superpage : UInt<1>, homogeneous : UInt<1>, gpa : { valid : UInt<1>, bits : UInt<39>}, gpa_is_pte : UInt<1>}}, flip ptbr : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip hgatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip vsatp : { mode : UInt<4>, asid : UInt<16>, ppn : UInt<44>}, flip status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, flip gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip customCSRs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]}}, trace : { insns : { valid : UInt<1>, iaddr : UInt<40>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<64>, tval : UInt<40>}[2], time : UInt<64>, custom : { rob_empty : UInt<1>}}, fcsr_rm : UInt<3>} invalidate io.ptw_tlb.customCSRs.csrs[0].sdata invalidate io.ptw_tlb.customCSRs.csrs[0].set invalidate io.ptw_tlb.customCSRs.csrs[0].stall invalidate io.ptw_tlb.customCSRs.csrs[0].value invalidate io.ptw_tlb.customCSRs.csrs[0].wdata invalidate io.ptw_tlb.customCSRs.csrs[0].wen invalidate io.ptw_tlb.customCSRs.csrs[0].ren invalidate io.ptw_tlb.customCSRs.csrs[1].sdata invalidate io.ptw_tlb.customCSRs.csrs[1].set invalidate io.ptw_tlb.customCSRs.csrs[1].stall invalidate io.ptw_tlb.customCSRs.csrs[1].value invalidate io.ptw_tlb.customCSRs.csrs[1].wdata invalidate io.ptw_tlb.customCSRs.csrs[1].wen invalidate io.ptw_tlb.customCSRs.csrs[1].ren invalidate io.ptw_tlb.customCSRs.csrs[2].sdata invalidate io.ptw_tlb.customCSRs.csrs[2].set invalidate io.ptw_tlb.customCSRs.csrs[2].stall invalidate io.ptw_tlb.customCSRs.csrs[2].value invalidate io.ptw_tlb.customCSRs.csrs[2].wdata invalidate io.ptw_tlb.customCSRs.csrs[2].wen invalidate io.ptw_tlb.customCSRs.csrs[2].ren invalidate io.ptw_tlb.customCSRs.csrs[3].sdata invalidate io.ptw_tlb.customCSRs.csrs[3].set invalidate io.ptw_tlb.customCSRs.csrs[3].stall invalidate io.ptw_tlb.customCSRs.csrs[3].value invalidate io.ptw_tlb.customCSRs.csrs[3].wdata invalidate io.ptw_tlb.customCSRs.csrs[3].wen invalidate io.ptw_tlb.customCSRs.csrs[3].ren invalidate io.ptw_tlb.pmp[0].mask invalidate io.ptw_tlb.pmp[0].addr invalidate io.ptw_tlb.pmp[0].cfg.r invalidate io.ptw_tlb.pmp[0].cfg.w invalidate io.ptw_tlb.pmp[0].cfg.x invalidate io.ptw_tlb.pmp[0].cfg.a invalidate io.ptw_tlb.pmp[0].cfg.res invalidate io.ptw_tlb.pmp[0].cfg.l invalidate io.ptw_tlb.pmp[1].mask invalidate io.ptw_tlb.pmp[1].addr invalidate io.ptw_tlb.pmp[1].cfg.r invalidate io.ptw_tlb.pmp[1].cfg.w invalidate io.ptw_tlb.pmp[1].cfg.x invalidate io.ptw_tlb.pmp[1].cfg.a invalidate io.ptw_tlb.pmp[1].cfg.res invalidate io.ptw_tlb.pmp[1].cfg.l invalidate io.ptw_tlb.pmp[2].mask invalidate io.ptw_tlb.pmp[2].addr invalidate io.ptw_tlb.pmp[2].cfg.r invalidate io.ptw_tlb.pmp[2].cfg.w invalidate io.ptw_tlb.pmp[2].cfg.x invalidate io.ptw_tlb.pmp[2].cfg.a invalidate io.ptw_tlb.pmp[2].cfg.res invalidate io.ptw_tlb.pmp[2].cfg.l invalidate io.ptw_tlb.pmp[3].mask invalidate io.ptw_tlb.pmp[3].addr invalidate io.ptw_tlb.pmp[3].cfg.r invalidate io.ptw_tlb.pmp[3].cfg.w invalidate io.ptw_tlb.pmp[3].cfg.x invalidate io.ptw_tlb.pmp[3].cfg.a invalidate io.ptw_tlb.pmp[3].cfg.res invalidate io.ptw_tlb.pmp[3].cfg.l invalidate io.ptw_tlb.pmp[4].mask invalidate io.ptw_tlb.pmp[4].addr invalidate io.ptw_tlb.pmp[4].cfg.r invalidate io.ptw_tlb.pmp[4].cfg.w invalidate io.ptw_tlb.pmp[4].cfg.x invalidate io.ptw_tlb.pmp[4].cfg.a invalidate io.ptw_tlb.pmp[4].cfg.res invalidate io.ptw_tlb.pmp[4].cfg.l invalidate io.ptw_tlb.pmp[5].mask invalidate io.ptw_tlb.pmp[5].addr invalidate io.ptw_tlb.pmp[5].cfg.r invalidate io.ptw_tlb.pmp[5].cfg.w invalidate io.ptw_tlb.pmp[5].cfg.x invalidate io.ptw_tlb.pmp[5].cfg.a invalidate io.ptw_tlb.pmp[5].cfg.res invalidate io.ptw_tlb.pmp[5].cfg.l invalidate io.ptw_tlb.pmp[6].mask invalidate io.ptw_tlb.pmp[6].addr invalidate io.ptw_tlb.pmp[6].cfg.r invalidate io.ptw_tlb.pmp[6].cfg.w invalidate io.ptw_tlb.pmp[6].cfg.x invalidate io.ptw_tlb.pmp[6].cfg.a invalidate io.ptw_tlb.pmp[6].cfg.res invalidate io.ptw_tlb.pmp[6].cfg.l invalidate io.ptw_tlb.pmp[7].mask invalidate io.ptw_tlb.pmp[7].addr invalidate io.ptw_tlb.pmp[7].cfg.r invalidate io.ptw_tlb.pmp[7].cfg.w invalidate io.ptw_tlb.pmp[7].cfg.x invalidate io.ptw_tlb.pmp[7].cfg.a invalidate io.ptw_tlb.pmp[7].cfg.res invalidate io.ptw_tlb.pmp[7].cfg.l invalidate io.ptw_tlb.gstatus.uie invalidate io.ptw_tlb.gstatus.sie invalidate io.ptw_tlb.gstatus.hie invalidate io.ptw_tlb.gstatus.mie invalidate io.ptw_tlb.gstatus.upie invalidate io.ptw_tlb.gstatus.spie invalidate io.ptw_tlb.gstatus.ube invalidate io.ptw_tlb.gstatus.mpie invalidate io.ptw_tlb.gstatus.spp invalidate io.ptw_tlb.gstatus.vs invalidate io.ptw_tlb.gstatus.mpp invalidate io.ptw_tlb.gstatus.fs invalidate io.ptw_tlb.gstatus.xs invalidate io.ptw_tlb.gstatus.mprv invalidate io.ptw_tlb.gstatus.sum invalidate io.ptw_tlb.gstatus.mxr invalidate io.ptw_tlb.gstatus.tvm invalidate io.ptw_tlb.gstatus.tw invalidate io.ptw_tlb.gstatus.tsr invalidate io.ptw_tlb.gstatus.zero1 invalidate io.ptw_tlb.gstatus.sd_rv32 invalidate io.ptw_tlb.gstatus.uxl invalidate io.ptw_tlb.gstatus.sxl invalidate io.ptw_tlb.gstatus.sbe invalidate io.ptw_tlb.gstatus.mbe invalidate io.ptw_tlb.gstatus.gva invalidate io.ptw_tlb.gstatus.mpv invalidate io.ptw_tlb.gstatus.zero2 invalidate io.ptw_tlb.gstatus.sd invalidate io.ptw_tlb.gstatus.v invalidate io.ptw_tlb.gstatus.prv invalidate io.ptw_tlb.gstatus.dv invalidate io.ptw_tlb.gstatus.dprv invalidate io.ptw_tlb.gstatus.isa invalidate io.ptw_tlb.gstatus.wfi invalidate io.ptw_tlb.gstatus.cease invalidate io.ptw_tlb.gstatus.debug invalidate io.ptw_tlb.hstatus.zero1 invalidate io.ptw_tlb.hstatus.vsbe invalidate io.ptw_tlb.hstatus.gva invalidate io.ptw_tlb.hstatus.spv invalidate io.ptw_tlb.hstatus.spvp invalidate io.ptw_tlb.hstatus.hu invalidate io.ptw_tlb.hstatus.zero2 invalidate io.ptw_tlb.hstatus.vgein invalidate io.ptw_tlb.hstatus.zero3 invalidate io.ptw_tlb.hstatus.vtvm invalidate io.ptw_tlb.hstatus.vtw invalidate io.ptw_tlb.hstatus.vtsr invalidate io.ptw_tlb.hstatus.zero5 invalidate io.ptw_tlb.hstatus.vsxl invalidate io.ptw_tlb.hstatus.zero6 invalidate io.ptw_tlb.status.uie invalidate io.ptw_tlb.status.sie invalidate io.ptw_tlb.status.hie invalidate io.ptw_tlb.status.mie invalidate io.ptw_tlb.status.upie invalidate io.ptw_tlb.status.spie invalidate io.ptw_tlb.status.ube invalidate io.ptw_tlb.status.mpie invalidate io.ptw_tlb.status.spp invalidate io.ptw_tlb.status.vs invalidate io.ptw_tlb.status.mpp invalidate io.ptw_tlb.status.fs invalidate io.ptw_tlb.status.xs invalidate io.ptw_tlb.status.mprv invalidate io.ptw_tlb.status.sum invalidate io.ptw_tlb.status.mxr invalidate io.ptw_tlb.status.tvm invalidate io.ptw_tlb.status.tw invalidate io.ptw_tlb.status.tsr invalidate io.ptw_tlb.status.zero1 invalidate io.ptw_tlb.status.sd_rv32 invalidate io.ptw_tlb.status.uxl invalidate io.ptw_tlb.status.sxl invalidate io.ptw_tlb.status.sbe invalidate io.ptw_tlb.status.mbe invalidate io.ptw_tlb.status.gva invalidate io.ptw_tlb.status.mpv invalidate io.ptw_tlb.status.zero2 invalidate io.ptw_tlb.status.sd invalidate io.ptw_tlb.status.v invalidate io.ptw_tlb.status.prv invalidate io.ptw_tlb.status.dv invalidate io.ptw_tlb.status.dprv invalidate io.ptw_tlb.status.isa invalidate io.ptw_tlb.status.wfi invalidate io.ptw_tlb.status.cease invalidate io.ptw_tlb.status.debug invalidate io.ptw_tlb.vsatp.ppn invalidate io.ptw_tlb.vsatp.asid invalidate io.ptw_tlb.vsatp.mode invalidate io.ptw_tlb.hgatp.ppn invalidate io.ptw_tlb.hgatp.asid invalidate io.ptw_tlb.hgatp.mode invalidate io.ptw_tlb.ptbr.ppn invalidate io.ptw_tlb.ptbr.asid invalidate io.ptw_tlb.ptbr.mode invalidate io.ptw_tlb.resp.bits.gpa_is_pte invalidate io.ptw_tlb.resp.bits.gpa.bits invalidate io.ptw_tlb.resp.bits.gpa.valid invalidate io.ptw_tlb.resp.bits.homogeneous invalidate io.ptw_tlb.resp.bits.fragmented_superpage invalidate io.ptw_tlb.resp.bits.level invalidate io.ptw_tlb.resp.bits.pte.v invalidate io.ptw_tlb.resp.bits.pte.r invalidate io.ptw_tlb.resp.bits.pte.w invalidate io.ptw_tlb.resp.bits.pte.x invalidate io.ptw_tlb.resp.bits.pte.u invalidate io.ptw_tlb.resp.bits.pte.g invalidate io.ptw_tlb.resp.bits.pte.a invalidate io.ptw_tlb.resp.bits.pte.d invalidate io.ptw_tlb.resp.bits.pte.reserved_for_software invalidate io.ptw_tlb.resp.bits.pte.ppn invalidate io.ptw_tlb.resp.bits.pte.reserved_for_future invalidate io.ptw_tlb.resp.bits.hx invalidate io.ptw_tlb.resp.bits.hw invalidate io.ptw_tlb.resp.bits.hr invalidate io.ptw_tlb.resp.bits.gf invalidate io.ptw_tlb.resp.bits.pf invalidate io.ptw_tlb.resp.bits.ae_final invalidate io.ptw_tlb.resp.bits.ae_ptw invalidate io.ptw_tlb.resp.valid invalidate io.ptw_tlb.req.bits.bits.stage2 invalidate io.ptw_tlb.req.bits.bits.vstage1 invalidate io.ptw_tlb.req.bits.bits.need_gpa invalidate io.ptw_tlb.req.bits.bits.addr invalidate io.ptw_tlb.req.bits.valid invalidate io.ptw_tlb.req.valid invalidate io.ptw_tlb.req.ready invalidate io.ptw.clock_enabled invalidate io.ptw.customCSRs.csrs[0].sdata invalidate io.ptw.customCSRs.csrs[0].set invalidate io.ptw.customCSRs.csrs[0].stall invalidate io.ptw.customCSRs.csrs[0].value invalidate io.ptw.customCSRs.csrs[0].wdata invalidate io.ptw.customCSRs.csrs[0].wen invalidate io.ptw.customCSRs.csrs[0].ren invalidate io.ptw.customCSRs.csrs[1].sdata invalidate io.ptw.customCSRs.csrs[1].set invalidate io.ptw.customCSRs.csrs[1].stall invalidate io.ptw.customCSRs.csrs[1].value invalidate io.ptw.customCSRs.csrs[1].wdata invalidate io.ptw.customCSRs.csrs[1].wen invalidate io.ptw.customCSRs.csrs[1].ren invalidate io.ptw.customCSRs.csrs[2].sdata invalidate io.ptw.customCSRs.csrs[2].set invalidate io.ptw.customCSRs.csrs[2].stall invalidate io.ptw.customCSRs.csrs[2].value invalidate io.ptw.customCSRs.csrs[2].wdata invalidate io.ptw.customCSRs.csrs[2].wen invalidate io.ptw.customCSRs.csrs[2].ren invalidate io.ptw.customCSRs.csrs[3].sdata invalidate io.ptw.customCSRs.csrs[3].set invalidate io.ptw.customCSRs.csrs[3].stall invalidate io.ptw.customCSRs.csrs[3].value invalidate io.ptw.customCSRs.csrs[3].wdata invalidate io.ptw.customCSRs.csrs[3].wen invalidate io.ptw.customCSRs.csrs[3].ren invalidate io.ptw.perf.pte_hit invalidate io.ptw.perf.pte_miss invalidate io.ptw.perf.l2hit invalidate io.ptw.perf.l2miss invalidate io.ptw.pmp[0].mask invalidate io.ptw.pmp[0].addr invalidate io.ptw.pmp[0].cfg.r invalidate io.ptw.pmp[0].cfg.w invalidate io.ptw.pmp[0].cfg.x invalidate io.ptw.pmp[0].cfg.a invalidate io.ptw.pmp[0].cfg.res invalidate io.ptw.pmp[0].cfg.l invalidate io.ptw.pmp[1].mask invalidate io.ptw.pmp[1].addr invalidate io.ptw.pmp[1].cfg.r invalidate io.ptw.pmp[1].cfg.w invalidate io.ptw.pmp[1].cfg.x invalidate io.ptw.pmp[1].cfg.a invalidate io.ptw.pmp[1].cfg.res invalidate io.ptw.pmp[1].cfg.l invalidate io.ptw.pmp[2].mask invalidate io.ptw.pmp[2].addr invalidate io.ptw.pmp[2].cfg.r invalidate io.ptw.pmp[2].cfg.w invalidate io.ptw.pmp[2].cfg.x invalidate io.ptw.pmp[2].cfg.a invalidate io.ptw.pmp[2].cfg.res invalidate io.ptw.pmp[2].cfg.l invalidate io.ptw.pmp[3].mask invalidate io.ptw.pmp[3].addr invalidate io.ptw.pmp[3].cfg.r invalidate io.ptw.pmp[3].cfg.w invalidate io.ptw.pmp[3].cfg.x invalidate io.ptw.pmp[3].cfg.a invalidate io.ptw.pmp[3].cfg.res invalidate io.ptw.pmp[3].cfg.l invalidate io.ptw.pmp[4].mask invalidate io.ptw.pmp[4].addr invalidate io.ptw.pmp[4].cfg.r invalidate io.ptw.pmp[4].cfg.w invalidate io.ptw.pmp[4].cfg.x invalidate io.ptw.pmp[4].cfg.a invalidate io.ptw.pmp[4].cfg.res invalidate io.ptw.pmp[4].cfg.l invalidate io.ptw.pmp[5].mask invalidate io.ptw.pmp[5].addr invalidate io.ptw.pmp[5].cfg.r invalidate io.ptw.pmp[5].cfg.w invalidate io.ptw.pmp[5].cfg.x invalidate io.ptw.pmp[5].cfg.a invalidate io.ptw.pmp[5].cfg.res invalidate io.ptw.pmp[5].cfg.l invalidate io.ptw.pmp[6].mask invalidate io.ptw.pmp[6].addr invalidate io.ptw.pmp[6].cfg.r invalidate io.ptw.pmp[6].cfg.w invalidate io.ptw.pmp[6].cfg.x invalidate io.ptw.pmp[6].cfg.a invalidate io.ptw.pmp[6].cfg.res invalidate io.ptw.pmp[6].cfg.l invalidate io.ptw.pmp[7].mask invalidate io.ptw.pmp[7].addr invalidate io.ptw.pmp[7].cfg.r invalidate io.ptw.pmp[7].cfg.w invalidate io.ptw.pmp[7].cfg.x invalidate io.ptw.pmp[7].cfg.a invalidate io.ptw.pmp[7].cfg.res invalidate io.ptw.pmp[7].cfg.l invalidate io.ptw.gstatus.uie invalidate io.ptw.gstatus.sie invalidate io.ptw.gstatus.hie invalidate io.ptw.gstatus.mie invalidate io.ptw.gstatus.upie invalidate io.ptw.gstatus.spie invalidate io.ptw.gstatus.ube invalidate io.ptw.gstatus.mpie invalidate io.ptw.gstatus.spp invalidate io.ptw.gstatus.vs invalidate io.ptw.gstatus.mpp invalidate io.ptw.gstatus.fs invalidate io.ptw.gstatus.xs invalidate io.ptw.gstatus.mprv invalidate io.ptw.gstatus.sum invalidate io.ptw.gstatus.mxr invalidate io.ptw.gstatus.tvm invalidate io.ptw.gstatus.tw invalidate io.ptw.gstatus.tsr invalidate io.ptw.gstatus.zero1 invalidate io.ptw.gstatus.sd_rv32 invalidate io.ptw.gstatus.uxl invalidate io.ptw.gstatus.sxl invalidate io.ptw.gstatus.sbe invalidate io.ptw.gstatus.mbe invalidate io.ptw.gstatus.gva invalidate io.ptw.gstatus.mpv invalidate io.ptw.gstatus.zero2 invalidate io.ptw.gstatus.sd invalidate io.ptw.gstatus.v invalidate io.ptw.gstatus.prv invalidate io.ptw.gstatus.dv invalidate io.ptw.gstatus.dprv invalidate io.ptw.gstatus.isa invalidate io.ptw.gstatus.wfi invalidate io.ptw.gstatus.cease invalidate io.ptw.gstatus.debug invalidate io.ptw.hstatus.zero1 invalidate io.ptw.hstatus.vsbe invalidate io.ptw.hstatus.gva invalidate io.ptw.hstatus.spv invalidate io.ptw.hstatus.spvp invalidate io.ptw.hstatus.hu invalidate io.ptw.hstatus.zero2 invalidate io.ptw.hstatus.vgein invalidate io.ptw.hstatus.zero3 invalidate io.ptw.hstatus.vtvm invalidate io.ptw.hstatus.vtw invalidate io.ptw.hstatus.vtsr invalidate io.ptw.hstatus.zero5 invalidate io.ptw.hstatus.vsxl invalidate io.ptw.hstatus.zero6 invalidate io.ptw.status.uie invalidate io.ptw.status.sie invalidate io.ptw.status.hie invalidate io.ptw.status.mie invalidate io.ptw.status.upie invalidate io.ptw.status.spie invalidate io.ptw.status.ube invalidate io.ptw.status.mpie invalidate io.ptw.status.spp invalidate io.ptw.status.vs invalidate io.ptw.status.mpp invalidate io.ptw.status.fs invalidate io.ptw.status.xs invalidate io.ptw.status.mprv invalidate io.ptw.status.sum invalidate io.ptw.status.mxr invalidate io.ptw.status.tvm invalidate io.ptw.status.tw invalidate io.ptw.status.tsr invalidate io.ptw.status.zero1 invalidate io.ptw.status.sd_rv32 invalidate io.ptw.status.uxl invalidate io.ptw.status.sxl invalidate io.ptw.status.sbe invalidate io.ptw.status.mbe invalidate io.ptw.status.gva invalidate io.ptw.status.mpv invalidate io.ptw.status.zero2 invalidate io.ptw.status.sd invalidate io.ptw.status.v invalidate io.ptw.status.prv invalidate io.ptw.status.dv invalidate io.ptw.status.dprv invalidate io.ptw.status.isa invalidate io.ptw.status.wfi invalidate io.ptw.status.cease invalidate io.ptw.status.debug invalidate io.ptw.sfence.bits.hg invalidate io.ptw.sfence.bits.hv invalidate io.ptw.sfence.bits.asid invalidate io.ptw.sfence.bits.addr invalidate io.ptw.sfence.bits.rs2 invalidate io.ptw.sfence.bits.rs1 invalidate io.ptw.sfence.valid invalidate io.ptw.vsatp.ppn invalidate io.ptw.vsatp.asid invalidate io.ptw.vsatp.mode invalidate io.ptw.hgatp.ppn invalidate io.ptw.hgatp.asid invalidate io.ptw.hgatp.mode invalidate io.ptw.ptbr.ppn invalidate io.ptw.ptbr.asid invalidate io.ptw.ptbr.mode invalidate io.ifu.perf.tlbMiss invalidate io.ifu.perf.acquire invalidate io.ifu.enable_bpd invalidate io.ifu.flush_icache invalidate io.ifu.commit.bits invalidate io.ifu.commit.valid invalidate io.ifu.redirect_ghist.ras_idx invalidate io.ifu.redirect_ghist.new_saw_branch_taken invalidate io.ifu.redirect_ghist.new_saw_branch_not_taken invalidate io.ifu.redirect_ghist.current_saw_branch_not_taken invalidate io.ifu.redirect_ghist.old_history invalidate io.ifu.redirect_ftq_idx invalidate io.ifu.redirect_pc invalidate io.ifu.redirect_val invalidate io.ifu.redirect_flush invalidate io.ifu.brupdate.b2.target_offset invalidate io.ifu.brupdate.b2.jalr_target invalidate io.ifu.brupdate.b2.pc_sel invalidate io.ifu.brupdate.b2.cfi_type invalidate io.ifu.brupdate.b2.taken invalidate io.ifu.brupdate.b2.mispredict invalidate io.ifu.brupdate.b2.uop.debug_tsrc invalidate io.ifu.brupdate.b2.uop.debug_fsrc invalidate io.ifu.brupdate.b2.uop.bp_xcpt_if invalidate io.ifu.brupdate.b2.uop.bp_debug_if invalidate io.ifu.brupdate.b2.uop.xcpt_ma_if invalidate io.ifu.brupdate.b2.uop.xcpt_ae_if invalidate io.ifu.brupdate.b2.uop.xcpt_pf_if invalidate io.ifu.brupdate.b2.uop.fp_typ invalidate io.ifu.brupdate.b2.uop.fp_rm invalidate io.ifu.brupdate.b2.uop.fp_val invalidate io.ifu.brupdate.b2.uop.fcn_op invalidate io.ifu.brupdate.b2.uop.fcn_dw invalidate io.ifu.brupdate.b2.uop.frs3_en invalidate io.ifu.brupdate.b2.uop.lrs2_rtype invalidate io.ifu.brupdate.b2.uop.lrs1_rtype invalidate io.ifu.brupdate.b2.uop.dst_rtype invalidate io.ifu.brupdate.b2.uop.lrs3 invalidate io.ifu.brupdate.b2.uop.lrs2 invalidate io.ifu.brupdate.b2.uop.lrs1 invalidate io.ifu.brupdate.b2.uop.ldst invalidate io.ifu.brupdate.b2.uop.ldst_is_rs1 invalidate io.ifu.brupdate.b2.uop.csr_cmd invalidate io.ifu.brupdate.b2.uop.flush_on_commit invalidate io.ifu.brupdate.b2.uop.is_unique invalidate io.ifu.brupdate.b2.uop.uses_stq invalidate io.ifu.brupdate.b2.uop.uses_ldq invalidate io.ifu.brupdate.b2.uop.mem_signed invalidate io.ifu.brupdate.b2.uop.mem_size invalidate io.ifu.brupdate.b2.uop.mem_cmd invalidate io.ifu.brupdate.b2.uop.exc_cause invalidate io.ifu.brupdate.b2.uop.exception invalidate io.ifu.brupdate.b2.uop.stale_pdst invalidate io.ifu.brupdate.b2.uop.ppred_busy invalidate io.ifu.brupdate.b2.uop.prs3_busy invalidate io.ifu.brupdate.b2.uop.prs2_busy invalidate io.ifu.brupdate.b2.uop.prs1_busy invalidate io.ifu.brupdate.b2.uop.ppred invalidate io.ifu.brupdate.b2.uop.prs3 invalidate io.ifu.brupdate.b2.uop.prs2 invalidate io.ifu.brupdate.b2.uop.prs1 invalidate io.ifu.brupdate.b2.uop.pdst invalidate io.ifu.brupdate.b2.uop.rxq_idx invalidate io.ifu.brupdate.b2.uop.stq_idx invalidate io.ifu.brupdate.b2.uop.ldq_idx invalidate io.ifu.brupdate.b2.uop.rob_idx invalidate io.ifu.brupdate.b2.uop.fp_ctrl.vec invalidate io.ifu.brupdate.b2.uop.fp_ctrl.wflags invalidate io.ifu.brupdate.b2.uop.fp_ctrl.sqrt invalidate io.ifu.brupdate.b2.uop.fp_ctrl.div invalidate io.ifu.brupdate.b2.uop.fp_ctrl.fma invalidate io.ifu.brupdate.b2.uop.fp_ctrl.fastpipe invalidate io.ifu.brupdate.b2.uop.fp_ctrl.toint invalidate io.ifu.brupdate.b2.uop.fp_ctrl.fromint invalidate io.ifu.brupdate.b2.uop.fp_ctrl.typeTagOut invalidate io.ifu.brupdate.b2.uop.fp_ctrl.typeTagIn invalidate io.ifu.brupdate.b2.uop.fp_ctrl.swap23 invalidate io.ifu.brupdate.b2.uop.fp_ctrl.swap12 invalidate io.ifu.brupdate.b2.uop.fp_ctrl.ren3 invalidate io.ifu.brupdate.b2.uop.fp_ctrl.ren2 invalidate io.ifu.brupdate.b2.uop.fp_ctrl.ren1 invalidate io.ifu.brupdate.b2.uop.fp_ctrl.wen invalidate io.ifu.brupdate.b2.uop.fp_ctrl.ldst invalidate io.ifu.brupdate.b2.uop.op2_sel invalidate io.ifu.brupdate.b2.uop.op1_sel invalidate io.ifu.brupdate.b2.uop.imm_packed invalidate io.ifu.brupdate.b2.uop.pimm invalidate io.ifu.brupdate.b2.uop.imm_sel invalidate io.ifu.brupdate.b2.uop.imm_rename invalidate io.ifu.brupdate.b2.uop.taken invalidate io.ifu.brupdate.b2.uop.pc_lob invalidate io.ifu.brupdate.b2.uop.edge_inst invalidate io.ifu.brupdate.b2.uop.ftq_idx invalidate io.ifu.brupdate.b2.uop.is_mov invalidate io.ifu.brupdate.b2.uop.is_rocc invalidate io.ifu.brupdate.b2.uop.is_sys_pc2epc invalidate io.ifu.brupdate.b2.uop.is_eret invalidate io.ifu.brupdate.b2.uop.is_amo invalidate io.ifu.brupdate.b2.uop.is_sfence invalidate io.ifu.brupdate.b2.uop.is_fencei invalidate io.ifu.brupdate.b2.uop.is_fence invalidate io.ifu.brupdate.b2.uop.is_sfb invalidate io.ifu.brupdate.b2.uop.br_type invalidate io.ifu.brupdate.b2.uop.br_tag invalidate io.ifu.brupdate.b2.uop.br_mask invalidate io.ifu.brupdate.b2.uop.dis_col_sel invalidate io.ifu.brupdate.b2.uop.iw_p3_bypass_hint invalidate io.ifu.brupdate.b2.uop.iw_p2_bypass_hint invalidate io.ifu.brupdate.b2.uop.iw_p1_bypass_hint invalidate io.ifu.brupdate.b2.uop.iw_p2_speculative_child invalidate io.ifu.brupdate.b2.uop.iw_p1_speculative_child invalidate io.ifu.brupdate.b2.uop.iw_issued_partial_dgen invalidate io.ifu.brupdate.b2.uop.iw_issued_partial_agen invalidate io.ifu.brupdate.b2.uop.iw_issued invalidate io.ifu.brupdate.b2.uop.fu_code[0] invalidate io.ifu.brupdate.b2.uop.fu_code[1] invalidate io.ifu.brupdate.b2.uop.fu_code[2] invalidate io.ifu.brupdate.b2.uop.fu_code[3] invalidate io.ifu.brupdate.b2.uop.fu_code[4] invalidate io.ifu.brupdate.b2.uop.fu_code[5] invalidate io.ifu.brupdate.b2.uop.fu_code[6] invalidate io.ifu.brupdate.b2.uop.fu_code[7] invalidate io.ifu.brupdate.b2.uop.fu_code[8] invalidate io.ifu.brupdate.b2.uop.fu_code[9] invalidate io.ifu.brupdate.b2.uop.iq_type[0] invalidate io.ifu.brupdate.b2.uop.iq_type[1] invalidate io.ifu.brupdate.b2.uop.iq_type[2] invalidate io.ifu.brupdate.b2.uop.iq_type[3] invalidate io.ifu.brupdate.b2.uop.debug_pc invalidate io.ifu.brupdate.b2.uop.is_rvc invalidate io.ifu.brupdate.b2.uop.debug_inst invalidate io.ifu.brupdate.b2.uop.inst invalidate io.ifu.brupdate.b1.mispredict_mask invalidate io.ifu.brupdate.b1.resolve_mask invalidate io.ifu.sfence.bits.hg invalidate io.ifu.sfence.bits.hv invalidate io.ifu.sfence.bits.asid invalidate io.ifu.sfence.bits.addr invalidate io.ifu.sfence.bits.rs2 invalidate io.ifu.sfence.bits.rs1 invalidate io.ifu.sfence.valid invalidate io.ifu.scontext invalidate io.ifu.mcontext invalidate io.ifu.status.uie invalidate io.ifu.status.sie invalidate io.ifu.status.hie invalidate io.ifu.status.mie invalidate io.ifu.status.upie invalidate io.ifu.status.spie invalidate io.ifu.status.ube invalidate io.ifu.status.mpie invalidate io.ifu.status.spp invalidate io.ifu.status.vs invalidate io.ifu.status.mpp invalidate io.ifu.status.fs invalidate io.ifu.status.xs invalidate io.ifu.status.mprv invalidate io.ifu.status.sum invalidate io.ifu.status.mxr invalidate io.ifu.status.tvm invalidate io.ifu.status.tw invalidate io.ifu.status.tsr invalidate io.ifu.status.zero1 invalidate io.ifu.status.sd_rv32 invalidate io.ifu.status.uxl invalidate io.ifu.status.sxl invalidate io.ifu.status.sbe invalidate io.ifu.status.mbe invalidate io.ifu.status.gva invalidate io.ifu.status.mpv invalidate io.ifu.status.zero2 invalidate io.ifu.status.sd invalidate io.ifu.status.v invalidate io.ifu.status.prv invalidate io.ifu.status.dv invalidate io.ifu.status.dprv invalidate io.ifu.status.isa invalidate io.ifu.status.wfi invalidate io.ifu.status.cease invalidate io.ifu.status.debug invalidate io.ifu.debug_fetch_pc[0] invalidate io.ifu.debug_fetch_pc[1] invalidate io.ifu.debug_ftq_idx[0] invalidate io.ifu.debug_ftq_idx[1] invalidate io.ifu.com_pc invalidate io.ifu.rrd_ftq_resps[0].pc invalidate io.ifu.rrd_ftq_resps[0].ghist.ras_idx invalidate io.ifu.rrd_ftq_resps[0].ghist.new_saw_branch_taken invalidate io.ifu.rrd_ftq_resps[0].ghist.new_saw_branch_not_taken invalidate io.ifu.rrd_ftq_resps[0].ghist.current_saw_branch_not_taken invalidate io.ifu.rrd_ftq_resps[0].ghist.old_history invalidate io.ifu.rrd_ftq_resps[0].entry.start_bank invalidate io.ifu.rrd_ftq_resps[0].entry.ras_idx invalidate io.ifu.rrd_ftq_resps[0].entry.ras_top invalidate io.ifu.rrd_ftq_resps[0].entry.cfi_npc_plus4 invalidate io.ifu.rrd_ftq_resps[0].entry.cfi_is_ret invalidate io.ifu.rrd_ftq_resps[0].entry.cfi_is_call invalidate io.ifu.rrd_ftq_resps[0].entry.br_mask invalidate io.ifu.rrd_ftq_resps[0].entry.cfi_type invalidate io.ifu.rrd_ftq_resps[0].entry.cfi_mispredicted invalidate io.ifu.rrd_ftq_resps[0].entry.cfi_taken invalidate io.ifu.rrd_ftq_resps[0].entry.cfi_idx.bits invalidate io.ifu.rrd_ftq_resps[0].entry.cfi_idx.valid invalidate io.ifu.rrd_ftq_resps[0].valid invalidate io.ifu.rrd_ftq_resps[1].pc invalidate io.ifu.rrd_ftq_resps[1].ghist.ras_idx invalidate io.ifu.rrd_ftq_resps[1].ghist.new_saw_branch_taken invalidate io.ifu.rrd_ftq_resps[1].ghist.new_saw_branch_not_taken invalidate io.ifu.rrd_ftq_resps[1].ghist.current_saw_branch_not_taken invalidate io.ifu.rrd_ftq_resps[1].ghist.old_history invalidate io.ifu.rrd_ftq_resps[1].entry.start_bank invalidate io.ifu.rrd_ftq_resps[1].entry.ras_idx invalidate io.ifu.rrd_ftq_resps[1].entry.ras_top invalidate io.ifu.rrd_ftq_resps[1].entry.cfi_npc_plus4 invalidate io.ifu.rrd_ftq_resps[1].entry.cfi_is_ret invalidate io.ifu.rrd_ftq_resps[1].entry.cfi_is_call invalidate io.ifu.rrd_ftq_resps[1].entry.br_mask invalidate io.ifu.rrd_ftq_resps[1].entry.cfi_type invalidate io.ifu.rrd_ftq_resps[1].entry.cfi_mispredicted invalidate io.ifu.rrd_ftq_resps[1].entry.cfi_taken invalidate io.ifu.rrd_ftq_resps[1].entry.cfi_idx.bits invalidate io.ifu.rrd_ftq_resps[1].entry.cfi_idx.valid invalidate io.ifu.rrd_ftq_resps[1].valid invalidate io.ifu.rrd_ftq_resps[2].pc invalidate io.ifu.rrd_ftq_resps[2].ghist.ras_idx invalidate io.ifu.rrd_ftq_resps[2].ghist.new_saw_branch_taken invalidate io.ifu.rrd_ftq_resps[2].ghist.new_saw_branch_not_taken invalidate io.ifu.rrd_ftq_resps[2].ghist.current_saw_branch_not_taken invalidate io.ifu.rrd_ftq_resps[2].ghist.old_history invalidate io.ifu.rrd_ftq_resps[2].entry.start_bank invalidate io.ifu.rrd_ftq_resps[2].entry.ras_idx invalidate io.ifu.rrd_ftq_resps[2].entry.ras_top invalidate io.ifu.rrd_ftq_resps[2].entry.cfi_npc_plus4 invalidate io.ifu.rrd_ftq_resps[2].entry.cfi_is_ret invalidate io.ifu.rrd_ftq_resps[2].entry.cfi_is_call invalidate io.ifu.rrd_ftq_resps[2].entry.br_mask invalidate io.ifu.rrd_ftq_resps[2].entry.cfi_type invalidate io.ifu.rrd_ftq_resps[2].entry.cfi_mispredicted invalidate io.ifu.rrd_ftq_resps[2].entry.cfi_taken invalidate io.ifu.rrd_ftq_resps[2].entry.cfi_idx.bits invalidate io.ifu.rrd_ftq_resps[2].entry.cfi_idx.valid invalidate io.ifu.rrd_ftq_resps[2].valid invalidate io.ifu.arb_ftq_reqs[0] invalidate io.ifu.arb_ftq_reqs[1] invalidate io.ifu.arb_ftq_reqs[2] invalidate io.ifu.fetchpacket.bits.uops[0].bits.debug_tsrc invalidate io.ifu.fetchpacket.bits.uops[0].bits.debug_fsrc invalidate io.ifu.fetchpacket.bits.uops[0].bits.bp_xcpt_if invalidate io.ifu.fetchpacket.bits.uops[0].bits.bp_debug_if invalidate io.ifu.fetchpacket.bits.uops[0].bits.xcpt_ma_if invalidate io.ifu.fetchpacket.bits.uops[0].bits.xcpt_ae_if invalidate io.ifu.fetchpacket.bits.uops[0].bits.xcpt_pf_if invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_typ invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_rm invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_val invalidate io.ifu.fetchpacket.bits.uops[0].bits.fcn_op invalidate io.ifu.fetchpacket.bits.uops[0].bits.fcn_dw invalidate io.ifu.fetchpacket.bits.uops[0].bits.frs3_en invalidate io.ifu.fetchpacket.bits.uops[0].bits.lrs2_rtype invalidate io.ifu.fetchpacket.bits.uops[0].bits.lrs1_rtype invalidate io.ifu.fetchpacket.bits.uops[0].bits.dst_rtype invalidate io.ifu.fetchpacket.bits.uops[0].bits.lrs3 invalidate io.ifu.fetchpacket.bits.uops[0].bits.lrs2 invalidate io.ifu.fetchpacket.bits.uops[0].bits.lrs1 invalidate io.ifu.fetchpacket.bits.uops[0].bits.ldst invalidate io.ifu.fetchpacket.bits.uops[0].bits.ldst_is_rs1 invalidate io.ifu.fetchpacket.bits.uops[0].bits.csr_cmd invalidate io.ifu.fetchpacket.bits.uops[0].bits.flush_on_commit invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_unique invalidate io.ifu.fetchpacket.bits.uops[0].bits.uses_stq invalidate io.ifu.fetchpacket.bits.uops[0].bits.uses_ldq invalidate io.ifu.fetchpacket.bits.uops[0].bits.mem_signed invalidate io.ifu.fetchpacket.bits.uops[0].bits.mem_size invalidate io.ifu.fetchpacket.bits.uops[0].bits.mem_cmd invalidate io.ifu.fetchpacket.bits.uops[0].bits.exc_cause invalidate io.ifu.fetchpacket.bits.uops[0].bits.exception invalidate io.ifu.fetchpacket.bits.uops[0].bits.stale_pdst invalidate io.ifu.fetchpacket.bits.uops[0].bits.ppred_busy invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs3_busy invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs2_busy invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs1_busy invalidate io.ifu.fetchpacket.bits.uops[0].bits.ppred invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs3 invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs2 invalidate io.ifu.fetchpacket.bits.uops[0].bits.prs1 invalidate io.ifu.fetchpacket.bits.uops[0].bits.pdst invalidate io.ifu.fetchpacket.bits.uops[0].bits.rxq_idx invalidate io.ifu.fetchpacket.bits.uops[0].bits.stq_idx invalidate io.ifu.fetchpacket.bits.uops[0].bits.ldq_idx invalidate io.ifu.fetchpacket.bits.uops[0].bits.rob_idx invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.vec invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.wflags invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.sqrt invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.div invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.fma invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.fastpipe invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.toint invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.fromint invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.typeTagOut invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.typeTagIn invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.swap23 invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.swap12 invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.ren3 invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.ren2 invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.ren1 invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.wen invalidate io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.ldst invalidate io.ifu.fetchpacket.bits.uops[0].bits.op2_sel invalidate io.ifu.fetchpacket.bits.uops[0].bits.op1_sel invalidate io.ifu.fetchpacket.bits.uops[0].bits.imm_packed invalidate io.ifu.fetchpacket.bits.uops[0].bits.pimm invalidate io.ifu.fetchpacket.bits.uops[0].bits.imm_sel invalidate io.ifu.fetchpacket.bits.uops[0].bits.imm_rename invalidate io.ifu.fetchpacket.bits.uops[0].bits.taken invalidate io.ifu.fetchpacket.bits.uops[0].bits.pc_lob invalidate io.ifu.fetchpacket.bits.uops[0].bits.edge_inst invalidate io.ifu.fetchpacket.bits.uops[0].bits.ftq_idx invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_mov invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_rocc invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_sys_pc2epc invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_eret invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_amo invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_sfence invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_fencei invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_fence invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_sfb invalidate io.ifu.fetchpacket.bits.uops[0].bits.br_type invalidate io.ifu.fetchpacket.bits.uops[0].bits.br_tag invalidate io.ifu.fetchpacket.bits.uops[0].bits.br_mask invalidate io.ifu.fetchpacket.bits.uops[0].bits.dis_col_sel invalidate io.ifu.fetchpacket.bits.uops[0].bits.iw_p3_bypass_hint invalidate io.ifu.fetchpacket.bits.uops[0].bits.iw_p2_bypass_hint invalidate io.ifu.fetchpacket.bits.uops[0].bits.iw_p1_bypass_hint invalidate io.ifu.fetchpacket.bits.uops[0].bits.iw_p2_speculative_child invalidate io.ifu.fetchpacket.bits.uops[0].bits.iw_p1_speculative_child invalidate io.ifu.fetchpacket.bits.uops[0].bits.iw_issued_partial_dgen invalidate io.ifu.fetchpacket.bits.uops[0].bits.iw_issued_partial_agen invalidate io.ifu.fetchpacket.bits.uops[0].bits.iw_issued invalidate io.ifu.fetchpacket.bits.uops[0].bits.fu_code[0] invalidate io.ifu.fetchpacket.bits.uops[0].bits.fu_code[1] invalidate io.ifu.fetchpacket.bits.uops[0].bits.fu_code[2] invalidate io.ifu.fetchpacket.bits.uops[0].bits.fu_code[3] invalidate io.ifu.fetchpacket.bits.uops[0].bits.fu_code[4] invalidate io.ifu.fetchpacket.bits.uops[0].bits.fu_code[5] invalidate io.ifu.fetchpacket.bits.uops[0].bits.fu_code[6] invalidate io.ifu.fetchpacket.bits.uops[0].bits.fu_code[7] invalidate io.ifu.fetchpacket.bits.uops[0].bits.fu_code[8] invalidate io.ifu.fetchpacket.bits.uops[0].bits.fu_code[9] invalidate io.ifu.fetchpacket.bits.uops[0].bits.iq_type[0] invalidate io.ifu.fetchpacket.bits.uops[0].bits.iq_type[1] invalidate io.ifu.fetchpacket.bits.uops[0].bits.iq_type[2] invalidate io.ifu.fetchpacket.bits.uops[0].bits.iq_type[3] invalidate io.ifu.fetchpacket.bits.uops[0].bits.debug_pc invalidate io.ifu.fetchpacket.bits.uops[0].bits.is_rvc invalidate io.ifu.fetchpacket.bits.uops[0].bits.debug_inst invalidate io.ifu.fetchpacket.bits.uops[0].bits.inst invalidate io.ifu.fetchpacket.bits.uops[0].valid invalidate io.ifu.fetchpacket.bits.uops[1].bits.debug_tsrc invalidate io.ifu.fetchpacket.bits.uops[1].bits.debug_fsrc invalidate io.ifu.fetchpacket.bits.uops[1].bits.bp_xcpt_if invalidate io.ifu.fetchpacket.bits.uops[1].bits.bp_debug_if invalidate io.ifu.fetchpacket.bits.uops[1].bits.xcpt_ma_if invalidate io.ifu.fetchpacket.bits.uops[1].bits.xcpt_ae_if invalidate io.ifu.fetchpacket.bits.uops[1].bits.xcpt_pf_if invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_typ invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_rm invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_val invalidate io.ifu.fetchpacket.bits.uops[1].bits.fcn_op invalidate io.ifu.fetchpacket.bits.uops[1].bits.fcn_dw invalidate io.ifu.fetchpacket.bits.uops[1].bits.frs3_en invalidate io.ifu.fetchpacket.bits.uops[1].bits.lrs2_rtype invalidate io.ifu.fetchpacket.bits.uops[1].bits.lrs1_rtype invalidate io.ifu.fetchpacket.bits.uops[1].bits.dst_rtype invalidate io.ifu.fetchpacket.bits.uops[1].bits.lrs3 invalidate io.ifu.fetchpacket.bits.uops[1].bits.lrs2 invalidate io.ifu.fetchpacket.bits.uops[1].bits.lrs1 invalidate io.ifu.fetchpacket.bits.uops[1].bits.ldst invalidate io.ifu.fetchpacket.bits.uops[1].bits.ldst_is_rs1 invalidate io.ifu.fetchpacket.bits.uops[1].bits.csr_cmd invalidate io.ifu.fetchpacket.bits.uops[1].bits.flush_on_commit invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_unique invalidate io.ifu.fetchpacket.bits.uops[1].bits.uses_stq invalidate io.ifu.fetchpacket.bits.uops[1].bits.uses_ldq invalidate io.ifu.fetchpacket.bits.uops[1].bits.mem_signed invalidate io.ifu.fetchpacket.bits.uops[1].bits.mem_size invalidate io.ifu.fetchpacket.bits.uops[1].bits.mem_cmd invalidate io.ifu.fetchpacket.bits.uops[1].bits.exc_cause invalidate io.ifu.fetchpacket.bits.uops[1].bits.exception invalidate io.ifu.fetchpacket.bits.uops[1].bits.stale_pdst invalidate io.ifu.fetchpacket.bits.uops[1].bits.ppred_busy invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs3_busy invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs2_busy invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs1_busy invalidate io.ifu.fetchpacket.bits.uops[1].bits.ppred invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs3 invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs2 invalidate io.ifu.fetchpacket.bits.uops[1].bits.prs1 invalidate io.ifu.fetchpacket.bits.uops[1].bits.pdst invalidate io.ifu.fetchpacket.bits.uops[1].bits.rxq_idx invalidate io.ifu.fetchpacket.bits.uops[1].bits.stq_idx invalidate io.ifu.fetchpacket.bits.uops[1].bits.ldq_idx invalidate io.ifu.fetchpacket.bits.uops[1].bits.rob_idx invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.vec invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.wflags invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.sqrt invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.div invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.fma invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.fastpipe invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.toint invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.fromint invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.typeTagOut invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.typeTagIn invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.swap23 invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.swap12 invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.ren3 invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.ren2 invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.ren1 invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.wen invalidate io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.ldst invalidate io.ifu.fetchpacket.bits.uops[1].bits.op2_sel invalidate io.ifu.fetchpacket.bits.uops[1].bits.op1_sel invalidate io.ifu.fetchpacket.bits.uops[1].bits.imm_packed invalidate io.ifu.fetchpacket.bits.uops[1].bits.pimm invalidate io.ifu.fetchpacket.bits.uops[1].bits.imm_sel invalidate io.ifu.fetchpacket.bits.uops[1].bits.imm_rename invalidate io.ifu.fetchpacket.bits.uops[1].bits.taken invalidate io.ifu.fetchpacket.bits.uops[1].bits.pc_lob invalidate io.ifu.fetchpacket.bits.uops[1].bits.edge_inst invalidate io.ifu.fetchpacket.bits.uops[1].bits.ftq_idx invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_mov invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_rocc invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_sys_pc2epc invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_eret invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_amo invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_sfence invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_fencei invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_fence invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_sfb invalidate io.ifu.fetchpacket.bits.uops[1].bits.br_type invalidate io.ifu.fetchpacket.bits.uops[1].bits.br_tag invalidate io.ifu.fetchpacket.bits.uops[1].bits.br_mask invalidate io.ifu.fetchpacket.bits.uops[1].bits.dis_col_sel invalidate io.ifu.fetchpacket.bits.uops[1].bits.iw_p3_bypass_hint invalidate io.ifu.fetchpacket.bits.uops[1].bits.iw_p2_bypass_hint invalidate io.ifu.fetchpacket.bits.uops[1].bits.iw_p1_bypass_hint invalidate io.ifu.fetchpacket.bits.uops[1].bits.iw_p2_speculative_child invalidate io.ifu.fetchpacket.bits.uops[1].bits.iw_p1_speculative_child invalidate io.ifu.fetchpacket.bits.uops[1].bits.iw_issued_partial_dgen invalidate io.ifu.fetchpacket.bits.uops[1].bits.iw_issued_partial_agen invalidate io.ifu.fetchpacket.bits.uops[1].bits.iw_issued invalidate io.ifu.fetchpacket.bits.uops[1].bits.fu_code[0] invalidate io.ifu.fetchpacket.bits.uops[1].bits.fu_code[1] invalidate io.ifu.fetchpacket.bits.uops[1].bits.fu_code[2] invalidate io.ifu.fetchpacket.bits.uops[1].bits.fu_code[3] invalidate io.ifu.fetchpacket.bits.uops[1].bits.fu_code[4] invalidate io.ifu.fetchpacket.bits.uops[1].bits.fu_code[5] invalidate io.ifu.fetchpacket.bits.uops[1].bits.fu_code[6] invalidate io.ifu.fetchpacket.bits.uops[1].bits.fu_code[7] invalidate io.ifu.fetchpacket.bits.uops[1].bits.fu_code[8] invalidate io.ifu.fetchpacket.bits.uops[1].bits.fu_code[9] invalidate io.ifu.fetchpacket.bits.uops[1].bits.iq_type[0] invalidate io.ifu.fetchpacket.bits.uops[1].bits.iq_type[1] invalidate io.ifu.fetchpacket.bits.uops[1].bits.iq_type[2] invalidate io.ifu.fetchpacket.bits.uops[1].bits.iq_type[3] invalidate io.ifu.fetchpacket.bits.uops[1].bits.debug_pc invalidate io.ifu.fetchpacket.bits.uops[1].bits.is_rvc invalidate io.ifu.fetchpacket.bits.uops[1].bits.debug_inst invalidate io.ifu.fetchpacket.bits.uops[1].bits.inst invalidate io.ifu.fetchpacket.bits.uops[1].valid invalidate io.ifu.fetchpacket.valid invalidate io.ifu.fetchpacket.ready inst mem_exe_unit_0 of MemExeUnit connect mem_exe_unit_0.clock, clock connect mem_exe_unit_0.reset, reset inst mem_exe_unit_1 of MemExeUnit_1 connect mem_exe_unit_1.clock, clock connect mem_exe_unit_1.reset, reset inst unique_exe_unit_0 of UniqueExeUnit connect unique_exe_unit_0.clock, clock connect unique_exe_unit_0.reset, reset inst alu_exe_unit_0 of ALUExeUnit connect alu_exe_unit_0.clock, clock connect alu_exe_unit_0.reset, reset inst alu_exe_unit_1 of ALUExeUnit_1 connect alu_exe_unit_1.clock, clock connect alu_exe_unit_1.reset, reset inst fp_pipeline of FpPipeline connect fp_pipeline.clock, clock connect fp_pipeline.reset, reset invalidate fp_pipeline.io.ll_wports[0].bits.fflags.bits invalidate fp_pipeline.io.ll_wports[0].bits.fflags.valid invalidate fp_pipeline.io.ll_wports[0].bits.predicated invalidate fp_pipeline.io.ll_wports[0].bits.data invalidate fp_pipeline.io.ll_wports[0].bits.uop.debug_tsrc invalidate fp_pipeline.io.ll_wports[0].bits.uop.debug_fsrc invalidate fp_pipeline.io.ll_wports[0].bits.uop.bp_xcpt_if invalidate fp_pipeline.io.ll_wports[0].bits.uop.bp_debug_if invalidate fp_pipeline.io.ll_wports[0].bits.uop.xcpt_ma_if invalidate fp_pipeline.io.ll_wports[0].bits.uop.xcpt_ae_if invalidate fp_pipeline.io.ll_wports[0].bits.uop.xcpt_pf_if invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_typ invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_rm invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_val invalidate fp_pipeline.io.ll_wports[0].bits.uop.fcn_op invalidate fp_pipeline.io.ll_wports[0].bits.uop.fcn_dw invalidate fp_pipeline.io.ll_wports[0].bits.uop.frs3_en invalidate fp_pipeline.io.ll_wports[0].bits.uop.lrs2_rtype invalidate fp_pipeline.io.ll_wports[0].bits.uop.lrs1_rtype invalidate fp_pipeline.io.ll_wports[0].bits.uop.dst_rtype invalidate fp_pipeline.io.ll_wports[0].bits.uop.lrs3 invalidate fp_pipeline.io.ll_wports[0].bits.uop.lrs2 invalidate fp_pipeline.io.ll_wports[0].bits.uop.lrs1 invalidate fp_pipeline.io.ll_wports[0].bits.uop.ldst invalidate fp_pipeline.io.ll_wports[0].bits.uop.ldst_is_rs1 invalidate fp_pipeline.io.ll_wports[0].bits.uop.csr_cmd invalidate fp_pipeline.io.ll_wports[0].bits.uop.flush_on_commit invalidate fp_pipeline.io.ll_wports[0].bits.uop.is_unique invalidate fp_pipeline.io.ll_wports[0].bits.uop.uses_stq invalidate fp_pipeline.io.ll_wports[0].bits.uop.uses_ldq invalidate fp_pipeline.io.ll_wports[0].bits.uop.mem_signed invalidate fp_pipeline.io.ll_wports[0].bits.uop.mem_size invalidate fp_pipeline.io.ll_wports[0].bits.uop.mem_cmd invalidate fp_pipeline.io.ll_wports[0].bits.uop.exc_cause invalidate fp_pipeline.io.ll_wports[0].bits.uop.exception invalidate fp_pipeline.io.ll_wports[0].bits.uop.stale_pdst invalidate fp_pipeline.io.ll_wports[0].bits.uop.ppred_busy invalidate fp_pipeline.io.ll_wports[0].bits.uop.prs3_busy invalidate fp_pipeline.io.ll_wports[0].bits.uop.prs2_busy invalidate fp_pipeline.io.ll_wports[0].bits.uop.prs1_busy invalidate fp_pipeline.io.ll_wports[0].bits.uop.ppred invalidate fp_pipeline.io.ll_wports[0].bits.uop.prs3 invalidate fp_pipeline.io.ll_wports[0].bits.uop.prs2 invalidate fp_pipeline.io.ll_wports[0].bits.uop.prs1 invalidate fp_pipeline.io.ll_wports[0].bits.uop.pdst invalidate fp_pipeline.io.ll_wports[0].bits.uop.rxq_idx invalidate fp_pipeline.io.ll_wports[0].bits.uop.stq_idx invalidate fp_pipeline.io.ll_wports[0].bits.uop.ldq_idx invalidate fp_pipeline.io.ll_wports[0].bits.uop.rob_idx invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.vec invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.wflags invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.sqrt invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.div invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.fma invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.fastpipe invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.toint invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.fromint invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.typeTagOut invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.typeTagIn invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.swap23 invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.swap12 invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.ren3 invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.ren2 invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.ren1 invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.wen invalidate fp_pipeline.io.ll_wports[0].bits.uop.fp_ctrl.ldst invalidate fp_pipeline.io.ll_wports[0].bits.uop.op2_sel invalidate fp_pipeline.io.ll_wports[0].bits.uop.op1_sel invalidate fp_pipeline.io.ll_wports[0].bits.uop.imm_packed invalidate fp_pipeline.io.ll_wports[0].bits.uop.pimm invalidate fp_pipeline.io.ll_wports[0].bits.uop.imm_sel invalidate fp_pipeline.io.ll_wports[0].bits.uop.imm_rename invalidate fp_pipeline.io.ll_wports[0].bits.uop.taken invalidate fp_pipeline.io.ll_wports[0].bits.uop.pc_lob invalidate fp_pipeline.io.ll_wports[0].bits.uop.edge_inst invalidate fp_pipeline.io.ll_wports[0].bits.uop.ftq_idx invalidate fp_pipeline.io.ll_wports[0].bits.uop.is_mov invalidate fp_pipeline.io.ll_wports[0].bits.uop.is_rocc invalidate fp_pipeline.io.ll_wports[0].bits.uop.is_sys_pc2epc invalidate fp_pipeline.io.ll_wports[0].bits.uop.is_eret invalidate fp_pipeline.io.ll_wports[0].bits.uop.is_amo invalidate fp_pipeline.io.ll_wports[0].bits.uop.is_sfence invalidate fp_pipeline.io.ll_wports[0].bits.uop.is_fencei invalidate fp_pipeline.io.ll_wports[0].bits.uop.is_fence invalidate fp_pipeline.io.ll_wports[0].bits.uop.is_sfb invalidate fp_pipeline.io.ll_wports[0].bits.uop.br_type invalidate fp_pipeline.io.ll_wports[0].bits.uop.br_tag invalidate fp_pipeline.io.ll_wports[0].bits.uop.br_mask invalidate fp_pipeline.io.ll_wports[0].bits.uop.dis_col_sel invalidate fp_pipeline.io.ll_wports[0].bits.uop.iw_p3_bypass_hint invalidate fp_pipeline.io.ll_wports[0].bits.uop.iw_p2_bypass_hint invalidate fp_pipeline.io.ll_wports[0].bits.uop.iw_p1_bypass_hint invalidate fp_pipeline.io.ll_wports[0].bits.uop.iw_p2_speculative_child invalidate fp_pipeline.io.ll_wports[0].bits.uop.iw_p1_speculative_child invalidate fp_pipeline.io.ll_wports[0].bits.uop.iw_issued_partial_dgen invalidate fp_pipeline.io.ll_wports[0].bits.uop.iw_issued_partial_agen invalidate fp_pipeline.io.ll_wports[0].bits.uop.iw_issued invalidate fp_pipeline.io.ll_wports[0].bits.uop.fu_code[0] invalidate fp_pipeline.io.ll_wports[0].bits.uop.fu_code[1] invalidate fp_pipeline.io.ll_wports[0].bits.uop.fu_code[2] invalidate fp_pipeline.io.ll_wports[0].bits.uop.fu_code[3] invalidate fp_pipeline.io.ll_wports[0].bits.uop.fu_code[4] invalidate fp_pipeline.io.ll_wports[0].bits.uop.fu_code[5] invalidate fp_pipeline.io.ll_wports[0].bits.uop.fu_code[6] invalidate fp_pipeline.io.ll_wports[0].bits.uop.fu_code[7] invalidate fp_pipeline.io.ll_wports[0].bits.uop.fu_code[8] invalidate fp_pipeline.io.ll_wports[0].bits.uop.fu_code[9] invalidate fp_pipeline.io.ll_wports[0].bits.uop.iq_type[0] invalidate fp_pipeline.io.ll_wports[0].bits.uop.iq_type[1] invalidate fp_pipeline.io.ll_wports[0].bits.uop.iq_type[2] invalidate fp_pipeline.io.ll_wports[0].bits.uop.iq_type[3] invalidate fp_pipeline.io.ll_wports[0].bits.uop.debug_pc invalidate fp_pipeline.io.ll_wports[0].bits.uop.is_rvc invalidate fp_pipeline.io.ll_wports[0].bits.uop.debug_inst invalidate fp_pipeline.io.ll_wports[0].bits.uop.inst invalidate fp_pipeline.io.ll_wports[0].valid inst decode_0 of DecodeUnit connect decode_0.clock, clock connect decode_0.reset, reset inst decode_1 of DecodeUnit_1 connect decode_1.clock, clock connect decode_1.reset, reset inst dec_brmask_logic of BranchMaskGenerationLogic connect dec_brmask_logic.clock, clock connect dec_brmask_logic.reset, reset inst rename_stage of RenameStage connect rename_stage.clock, clock connect rename_stage.reset, reset inst fp_rename_stage of RenameStage_1 connect fp_rename_stage.clock, clock connect fp_rename_stage.reset, reset inst pred_rename_stage of PredRenameStage connect pred_rename_stage.clock, clock connect pred_rename_stage.reset, reset inst imm_rename_stage of ImmRenameStage connect imm_rename_stage.clock, clock connect imm_rename_stage.reset, reset inst mem_iss_unit of IssueUnitCollapsing_1 connect mem_iss_unit.clock, clock connect mem_iss_unit.reset, reset inst unq_iss_unit of IssueUnitCollapsing_2 connect unq_iss_unit.clock, clock connect unq_iss_unit.reset, reset inst alu_iss_unit of IssueUnitCollapsing_3 connect alu_iss_unit.clock, clock connect alu_iss_unit.reset, reset inst dispatcher of BasicDispatcher connect dispatcher.clock, clock connect dispatcher.reset, reset inst iregfile of BankedRF_1 connect iregfile.clock, clock connect iregfile.reset, reset inst pregfile of FullyPortedRF_3 connect pregfile.clock, clock connect pregfile.reset, reset inst immregfile of FullyPortedRF_4 connect immregfile.clock, clock connect immregfile.reset, reset inst bregfile of FullyPortedRF_5 connect bregfile.clock, clock connect bregfile.reset, reset inst rob of Rob connect rob.clock, clock connect rob.reset, reset wire int_wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[4] wire pred_wakeups : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}}[2] node _T = add(pred_wakeups[0].valid, pred_wakeups[1].valid) node _T_1 = bits(_T, 1, 0) node _T_2 = leq(_T_1, UInt<1>(0h1)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at core.scala:168 assert(PopCount(pred_wakeups.map(_.valid)) <= 1.U)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert wire pred_wakeup : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, bypassable : UInt<1>, speculative_mask : UInt<2>, rebusy : UInt<1>}} node _pred_wakeup_valid_T = or(pred_wakeups[0].valid, pred_wakeups[1].valid) connect pred_wakeup.valid, _pred_wakeup_valid_T invalidate pred_wakeup.bits.rebusy invalidate pred_wakeup.bits.speculative_mask invalidate pred_wakeup.bits.bypassable invalidate pred_wakeup.bits.uop.debug_tsrc invalidate pred_wakeup.bits.uop.debug_fsrc invalidate pred_wakeup.bits.uop.bp_xcpt_if invalidate pred_wakeup.bits.uop.bp_debug_if invalidate pred_wakeup.bits.uop.xcpt_ma_if invalidate pred_wakeup.bits.uop.xcpt_ae_if invalidate pred_wakeup.bits.uop.xcpt_pf_if invalidate pred_wakeup.bits.uop.fp_typ invalidate pred_wakeup.bits.uop.fp_rm invalidate pred_wakeup.bits.uop.fp_val invalidate pred_wakeup.bits.uop.fcn_op invalidate pred_wakeup.bits.uop.fcn_dw invalidate pred_wakeup.bits.uop.frs3_en invalidate pred_wakeup.bits.uop.lrs2_rtype invalidate pred_wakeup.bits.uop.lrs1_rtype invalidate pred_wakeup.bits.uop.dst_rtype invalidate pred_wakeup.bits.uop.lrs3 invalidate pred_wakeup.bits.uop.lrs2 invalidate pred_wakeup.bits.uop.lrs1 invalidate pred_wakeup.bits.uop.ldst invalidate pred_wakeup.bits.uop.ldst_is_rs1 invalidate pred_wakeup.bits.uop.csr_cmd invalidate pred_wakeup.bits.uop.flush_on_commit invalidate pred_wakeup.bits.uop.is_unique invalidate pred_wakeup.bits.uop.uses_stq invalidate pred_wakeup.bits.uop.uses_ldq invalidate pred_wakeup.bits.uop.mem_signed invalidate pred_wakeup.bits.uop.mem_size invalidate pred_wakeup.bits.uop.mem_cmd invalidate pred_wakeup.bits.uop.exc_cause invalidate pred_wakeup.bits.uop.exception invalidate pred_wakeup.bits.uop.stale_pdst invalidate pred_wakeup.bits.uop.ppred_busy invalidate pred_wakeup.bits.uop.prs3_busy invalidate pred_wakeup.bits.uop.prs2_busy invalidate pred_wakeup.bits.uop.prs1_busy invalidate pred_wakeup.bits.uop.ppred invalidate pred_wakeup.bits.uop.prs3 invalidate pred_wakeup.bits.uop.prs2 invalidate pred_wakeup.bits.uop.prs1 invalidate pred_wakeup.bits.uop.pdst invalidate pred_wakeup.bits.uop.rxq_idx invalidate pred_wakeup.bits.uop.stq_idx invalidate pred_wakeup.bits.uop.ldq_idx invalidate pred_wakeup.bits.uop.rob_idx invalidate pred_wakeup.bits.uop.fp_ctrl.vec invalidate pred_wakeup.bits.uop.fp_ctrl.wflags invalidate pred_wakeup.bits.uop.fp_ctrl.sqrt invalidate pred_wakeup.bits.uop.fp_ctrl.div invalidate pred_wakeup.bits.uop.fp_ctrl.fma invalidate pred_wakeup.bits.uop.fp_ctrl.fastpipe invalidate pred_wakeup.bits.uop.fp_ctrl.toint invalidate pred_wakeup.bits.uop.fp_ctrl.fromint invalidate pred_wakeup.bits.uop.fp_ctrl.typeTagOut invalidate pred_wakeup.bits.uop.fp_ctrl.typeTagIn invalidate pred_wakeup.bits.uop.fp_ctrl.swap23 invalidate pred_wakeup.bits.uop.fp_ctrl.swap12 invalidate pred_wakeup.bits.uop.fp_ctrl.ren3 invalidate pred_wakeup.bits.uop.fp_ctrl.ren2 invalidate pred_wakeup.bits.uop.fp_ctrl.ren1 invalidate pred_wakeup.bits.uop.fp_ctrl.wen invalidate pred_wakeup.bits.uop.fp_ctrl.ldst invalidate pred_wakeup.bits.uop.op2_sel invalidate pred_wakeup.bits.uop.op1_sel invalidate pred_wakeup.bits.uop.imm_packed invalidate pred_wakeup.bits.uop.pimm invalidate pred_wakeup.bits.uop.imm_sel invalidate pred_wakeup.bits.uop.imm_rename invalidate pred_wakeup.bits.uop.taken invalidate pred_wakeup.bits.uop.pc_lob invalidate pred_wakeup.bits.uop.edge_inst invalidate pred_wakeup.bits.uop.ftq_idx invalidate pred_wakeup.bits.uop.is_mov invalidate pred_wakeup.bits.uop.is_rocc invalidate pred_wakeup.bits.uop.is_sys_pc2epc invalidate pred_wakeup.bits.uop.is_eret invalidate pred_wakeup.bits.uop.is_amo invalidate pred_wakeup.bits.uop.is_sfence invalidate pred_wakeup.bits.uop.is_fencei invalidate pred_wakeup.bits.uop.is_fence invalidate pred_wakeup.bits.uop.is_sfb invalidate pred_wakeup.bits.uop.br_type invalidate pred_wakeup.bits.uop.br_tag invalidate pred_wakeup.bits.uop.br_mask invalidate pred_wakeup.bits.uop.dis_col_sel invalidate pred_wakeup.bits.uop.iw_p3_bypass_hint invalidate pred_wakeup.bits.uop.iw_p2_bypass_hint invalidate pred_wakeup.bits.uop.iw_p1_bypass_hint invalidate pred_wakeup.bits.uop.iw_p2_speculative_child invalidate pred_wakeup.bits.uop.iw_p1_speculative_child invalidate pred_wakeup.bits.uop.iw_issued_partial_dgen invalidate pred_wakeup.bits.uop.iw_issued_partial_agen invalidate pred_wakeup.bits.uop.iw_issued invalidate pred_wakeup.bits.uop.fu_code[0] invalidate pred_wakeup.bits.uop.fu_code[1] invalidate pred_wakeup.bits.uop.fu_code[2] invalidate pred_wakeup.bits.uop.fu_code[3] invalidate pred_wakeup.bits.uop.fu_code[4] invalidate pred_wakeup.bits.uop.fu_code[5] invalidate pred_wakeup.bits.uop.fu_code[6] invalidate pred_wakeup.bits.uop.fu_code[7] invalidate pred_wakeup.bits.uop.fu_code[8] invalidate pred_wakeup.bits.uop.fu_code[9] invalidate pred_wakeup.bits.uop.iq_type[0] invalidate pred_wakeup.bits.uop.iq_type[1] invalidate pred_wakeup.bits.uop.iq_type[2] invalidate pred_wakeup.bits.uop.iq_type[3] invalidate pred_wakeup.bits.uop.debug_pc invalidate pred_wakeup.bits.uop.is_rvc invalidate pred_wakeup.bits.uop.debug_inst invalidate pred_wakeup.bits.uop.inst node _pred_wakeup_bits_uop_pdst_T = mux(pred_wakeups[0].valid, pred_wakeups[0].bits.uop.pdst, UInt<1>(0h0)) node _pred_wakeup_bits_uop_pdst_T_1 = mux(pred_wakeups[1].valid, pred_wakeups[1].bits.uop.pdst, UInt<1>(0h0)) node _pred_wakeup_bits_uop_pdst_T_2 = or(_pred_wakeup_bits_uop_pdst_T, _pred_wakeup_bits_uop_pdst_T_1) wire _pred_wakeup_bits_uop_pdst_WIRE : UInt<7> connect _pred_wakeup_bits_uop_pdst_WIRE, _pred_wakeup_bits_uop_pdst_T_2 connect pred_wakeup.bits.uop.pdst, _pred_wakeup_bits_uop_pdst_WIRE wire int_bypasses : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}[3] wire dec_valids : UInt<1>[2] wire dec_uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[2] wire dec_fire : UInt<1>[2] wire dec_ready : UInt<1> wire dec_xcpts : UInt<1>[2] wire ren_stalls : UInt<1>[2] wire dis_valids : UInt<1>[2] wire dis_uops : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}[2] wire dis_fire : UInt<1>[2] wire dis_ready : UInt<1> reg brinfos : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}[2], clock wire brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}} wire b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>} reg b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}, clock connect brupdate.b1, b1 connect brupdate.b2, b2 wire brinfos_0_bits_out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>} connect brinfos_0_bits_out, alu_exe_unit_0.io_brinfo.bits node _brinfos_0_bits_out_uop_br_mask_T = not(brupdate.b1.resolve_mask) node _brinfos_0_bits_out_uop_br_mask_T_1 = and(alu_exe_unit_0.io_brinfo.bits.uop.br_mask, _brinfos_0_bits_out_uop_br_mask_T) connect brinfos_0_bits_out.uop.br_mask, _brinfos_0_bits_out_uop_br_mask_T_1 connect brinfos[0].bits, brinfos_0_bits_out node _brinfos_0_valid_T = eq(rob.io.flush.valid, UInt<1>(0h0)) node _brinfos_0_valid_T_1 = and(alu_exe_unit_0.io_brinfo.valid, _brinfos_0_valid_T) reg brinfos_0_valid_REG : UInt<1>, clock connect brinfos_0_valid_REG, rob.io.flush.valid node _brinfos_0_valid_T_2 = and(brupdate.b1.mispredict_mask, alu_exe_unit_0.io_brinfo.bits.uop.br_mask) node _brinfos_0_valid_T_3 = neq(_brinfos_0_valid_T_2, UInt<1>(0h0)) node _brinfos_0_valid_T_4 = or(_brinfos_0_valid_T_3, brinfos_0_valid_REG) node _brinfos_0_valid_T_5 = eq(_brinfos_0_valid_T_4, UInt<1>(0h0)) node _brinfos_0_valid_T_6 = and(_brinfos_0_valid_T_1, _brinfos_0_valid_T_5) connect brinfos[0].valid, _brinfos_0_valid_T_6 wire brinfos_1_bits_out : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>} connect brinfos_1_bits_out, alu_exe_unit_1.io_brinfo.bits node _brinfos_1_bits_out_uop_br_mask_T = not(brupdate.b1.resolve_mask) node _brinfos_1_bits_out_uop_br_mask_T_1 = and(alu_exe_unit_1.io_brinfo.bits.uop.br_mask, _brinfos_1_bits_out_uop_br_mask_T) connect brinfos_1_bits_out.uop.br_mask, _brinfos_1_bits_out_uop_br_mask_T_1 connect brinfos[1].bits, brinfos_1_bits_out node _brinfos_1_valid_T = eq(rob.io.flush.valid, UInt<1>(0h0)) node _brinfos_1_valid_T_1 = and(alu_exe_unit_1.io_brinfo.valid, _brinfos_1_valid_T) reg brinfos_1_valid_REG : UInt<1>, clock connect brinfos_1_valid_REG, rob.io.flush.valid node _brinfos_1_valid_T_2 = and(brupdate.b1.mispredict_mask, alu_exe_unit_1.io_brinfo.bits.uop.br_mask) node _brinfos_1_valid_T_3 = neq(_brinfos_1_valid_T_2, UInt<1>(0h0)) node _brinfos_1_valid_T_4 = or(_brinfos_1_valid_T_3, brinfos_1_valid_REG) node _brinfos_1_valid_T_5 = eq(_brinfos_1_valid_T_4, UInt<1>(0h0)) node _brinfos_1_valid_T_6 = and(_brinfos_1_valid_T_1, _brinfos_1_valid_T_5) connect brinfos[1].valid, _brinfos_1_valid_T_6 node _b1_resolve_mask_T = dshl(brinfos[0].valid, brinfos[0].bits.uop.br_tag) node _b1_resolve_mask_T_1 = dshl(brinfos[1].valid, brinfos[1].bits.uop.br_tag) node _b1_resolve_mask_T_2 = or(_b1_resolve_mask_T, _b1_resolve_mask_T_1) connect b1.resolve_mask, _b1_resolve_mask_T_2 node _b1_mispredict_mask_T = and(brinfos[0].valid, brinfos[0].bits.mispredict) node _b1_mispredict_mask_T_1 = dshl(_b1_mispredict_mask_T, brinfos[0].bits.uop.br_tag) node _b1_mispredict_mask_T_2 = and(brinfos[1].valid, brinfos[1].bits.mispredict) node _b1_mispredict_mask_T_3 = dshl(_b1_mispredict_mask_T_2, brinfos[1].bits.uop.br_tag) node _b1_mispredict_mask_T_4 = or(_b1_mispredict_mask_T_1, _b1_mispredict_mask_T_3) connect b1.mispredict_mask, _b1_mispredict_mask_T_4 node _live_brinfos_T = and(brinfos[0].valid, brinfos[0].bits.mispredict) reg live_brinfos_REG : UInt<1>, clock connect live_brinfos_REG, rob.io.flush.valid node _live_brinfos_T_1 = and(brupdate.b1.mispredict_mask, brinfos[0].bits.uop.br_mask) node _live_brinfos_T_2 = neq(_live_brinfos_T_1, UInt<1>(0h0)) node _live_brinfos_T_3 = or(_live_brinfos_T_2, live_brinfos_REG) node _live_brinfos_T_4 = eq(_live_brinfos_T_3, UInt<1>(0h0)) node live_brinfos_0 = and(_live_brinfos_T, _live_brinfos_T_4) node _live_brinfos_T_5 = and(brinfos[1].valid, brinfos[1].bits.mispredict) reg live_brinfos_REG_1 : UInt<1>, clock connect live_brinfos_REG_1, rob.io.flush.valid node _live_brinfos_T_6 = and(brupdate.b1.mispredict_mask, brinfos[1].bits.uop.br_mask) node _live_brinfos_T_7 = neq(_live_brinfos_T_6, UInt<1>(0h0)) node _live_brinfos_T_8 = or(_live_brinfos_T_7, live_brinfos_REG_1) node _live_brinfos_T_9 = eq(_live_brinfos_T_8, UInt<1>(0h0)) node live_brinfos_1 = and(_live_brinfos_T_5, _live_brinfos_T_9) node mispredict_val = or(live_brinfos_0, live_brinfos_1) connect b2.mispredict, mispredict_val node _b2_cfi_type_T = mux(live_brinfos_0, brinfos[0].bits.cfi_type, UInt<1>(0h0)) node _b2_cfi_type_T_1 = mux(live_brinfos_1, brinfos[1].bits.cfi_type, UInt<1>(0h0)) node _b2_cfi_type_T_2 = or(_b2_cfi_type_T, _b2_cfi_type_T_1) wire _b2_cfi_type_WIRE : UInt<3> connect _b2_cfi_type_WIRE, _b2_cfi_type_T_2 connect b2.cfi_type, _b2_cfi_type_WIRE node _b2_taken_T = mux(live_brinfos_0, brinfos[0].bits.taken, UInt<1>(0h0)) node _b2_taken_T_1 = mux(live_brinfos_1, brinfos[1].bits.taken, UInt<1>(0h0)) node _b2_taken_T_2 = or(_b2_taken_T, _b2_taken_T_1) wire _b2_taken_WIRE : UInt<1> connect _b2_taken_WIRE, _b2_taken_T_2 connect b2.taken, _b2_taken_WIRE node _b2_pc_sel_T = mux(live_brinfos_0, brinfos[0].bits.pc_sel, UInt<1>(0h0)) node _b2_pc_sel_T_1 = mux(live_brinfos_1, brinfos[1].bits.pc_sel, UInt<1>(0h0)) node _b2_pc_sel_T_2 = or(_b2_pc_sel_T, _b2_pc_sel_T_1) wire _b2_pc_sel_WIRE : UInt<2> connect _b2_pc_sel_WIRE, _b2_pc_sel_T_2 connect b2.pc_sel, _b2_pc_sel_WIRE node _b2_uop_T = mux(live_brinfos_0, brinfos[0].bits.uop, brinfos[1].bits.uop) wire b2_uop_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect b2_uop_out, _b2_uop_T node _b2_uop_out_br_mask_T = not(brupdate.b1.resolve_mask) node _b2_uop_out_br_mask_T_1 = and(_b2_uop_T.br_mask, _b2_uop_out_br_mask_T) connect b2_uop_out.br_mask, _b2_uop_out_br_mask_T_1 connect b2.uop, b2_uop_out node _b2_jalr_target_T = mux(live_brinfos_0, brinfos[0].bits.jalr_target, UInt<1>(0h0)) node _b2_jalr_target_T_1 = mux(live_brinfos_1, brinfos[1].bits.jalr_target, UInt<1>(0h0)) node _b2_jalr_target_T_2 = or(_b2_jalr_target_T, _b2_jalr_target_T_1) wire _b2_jalr_target_WIRE : UInt<40> connect _b2_jalr_target_WIRE, _b2_jalr_target_T_2 connect b2.jalr_target, _b2_jalr_target_WIRE wire _b2_target_offset_WIRE : SInt<21> node _b2_target_offset_T = asUInt(brinfos[0].bits.target_offset) node _b2_target_offset_T_1 = asSInt(_b2_target_offset_T) connect _b2_target_offset_WIRE, _b2_target_offset_T_1 wire _b2_target_offset_WIRE_1 : SInt<21> node _b2_target_offset_T_2 = asUInt(brinfos[1].bits.target_offset) node _b2_target_offset_T_3 = asSInt(_b2_target_offset_T_2) connect _b2_target_offset_WIRE_1, _b2_target_offset_T_3 node _b2_target_offset_T_4 = mux(live_brinfos_0, _b2_target_offset_WIRE, asSInt(UInt<1>(0h0))) node _b2_target_offset_T_5 = mux(live_brinfos_1, _b2_target_offset_WIRE_1, asSInt(UInt<1>(0h0))) node _b2_target_offset_T_6 = or(_b2_target_offset_T_4, _b2_target_offset_T_5) node _b2_target_offset_T_7 = asSInt(_b2_target_offset_T_6) wire _b2_target_offset_WIRE_2 : SInt<21> node _b2_target_offset_T_8 = asUInt(_b2_target_offset_T_7) node _b2_target_offset_T_9 = asSInt(_b2_target_offset_T_8) connect _b2_target_offset_WIRE_2, _b2_target_offset_T_9 connect b2.target_offset, _b2_target_offset_WIRE_2 node _oldest_mispredict_ftq_idx_T = mux(live_brinfos_0, brinfos[0].bits.uop.ftq_idx, UInt<1>(0h0)) node _oldest_mispredict_ftq_idx_T_1 = mux(live_brinfos_1, brinfos[1].bits.uop.ftq_idx, UInt<1>(0h0)) node _oldest_mispredict_ftq_idx_T_2 = or(_oldest_mispredict_ftq_idx_T, _oldest_mispredict_ftq_idx_T_1) wire oldest_mispredict_ftq_idx : UInt<5> connect oldest_mispredict_ftq_idx, _oldest_mispredict_ftq_idx_T_2 node _T_6 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _T_7 = or(_T_6, brupdate.b2.mispredict) node _T_8 = and(_T_7, rob.io.rollback) node _T_9 = eq(_T_8, UInt<1>(0h0)) node _T_10 = asUInt(reset) node _T_11 = eq(_T_10, UInt<1>(0h0)) when _T_11 : node _T_12 = eq(_T_9, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "Assertion failed: Can't have a mispredict during rollback.\n at core.scala:238 assert (!((brupdate.b1.mispredict_mask =/= 0.U || brupdate.b2.mispredict)\n") : printf_1 assert(clock, _T_9, UInt<1>(0h1), "") : assert_1 connect io.ifu.brupdate, brupdate connect alu_exe_unit_0.io_brupdate.b2.target_offset, brupdate.b2.target_offset connect alu_exe_unit_0.io_brupdate.b2.jalr_target, brupdate.b2.jalr_target connect alu_exe_unit_0.io_brupdate.b2.pc_sel, brupdate.b2.pc_sel connect alu_exe_unit_0.io_brupdate.b2.cfi_type, brupdate.b2.cfi_type connect alu_exe_unit_0.io_brupdate.b2.taken, brupdate.b2.taken connect alu_exe_unit_0.io_brupdate.b2.mispredict, brupdate.b2.mispredict connect alu_exe_unit_0.io_brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect alu_exe_unit_0.io_brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect alu_exe_unit_0.io_brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect alu_exe_unit_0.io_brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect alu_exe_unit_0.io_brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect alu_exe_unit_0.io_brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect alu_exe_unit_0.io_brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect alu_exe_unit_0.io_brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect alu_exe_unit_0.io_brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect alu_exe_unit_0.io_brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect alu_exe_unit_0.io_brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect alu_exe_unit_0.io_brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect alu_exe_unit_0.io_brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect alu_exe_unit_0.io_brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect alu_exe_unit_0.io_brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect alu_exe_unit_0.io_brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect alu_exe_unit_0.io_brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect alu_exe_unit_0.io_brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect alu_exe_unit_0.io_brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect alu_exe_unit_0.io_brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect alu_exe_unit_0.io_brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect alu_exe_unit_0.io_brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect alu_exe_unit_0.io_brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect alu_exe_unit_0.io_brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect alu_exe_unit_0.io_brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect alu_exe_unit_0.io_brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect alu_exe_unit_0.io_brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect alu_exe_unit_0.io_brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect alu_exe_unit_0.io_brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect alu_exe_unit_0.io_brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect alu_exe_unit_0.io_brupdate.b2.uop.exception, brupdate.b2.uop.exception connect alu_exe_unit_0.io_brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect alu_exe_unit_0.io_brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect alu_exe_unit_0.io_brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect alu_exe_unit_0.io_brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect alu_exe_unit_0.io_brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect alu_exe_unit_0.io_brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect alu_exe_unit_0.io_brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect alu_exe_unit_0.io_brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect alu_exe_unit_0.io_brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect alu_exe_unit_0.io_brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect alu_exe_unit_0.io_brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect alu_exe_unit_0.io_brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect alu_exe_unit_0.io_brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect alu_exe_unit_0.io_brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect alu_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect alu_exe_unit_0.io_brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect alu_exe_unit_0.io_brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect alu_exe_unit_0.io_brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect alu_exe_unit_0.io_brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect alu_exe_unit_0.io_brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect alu_exe_unit_0.io_brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect alu_exe_unit_0.io_brupdate.b2.uop.taken, brupdate.b2.uop.taken connect alu_exe_unit_0.io_brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect alu_exe_unit_0.io_brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect alu_exe_unit_0.io_brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect alu_exe_unit_0.io_brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect alu_exe_unit_0.io_brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect alu_exe_unit_0.io_brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect alu_exe_unit_0.io_brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect alu_exe_unit_0.io_brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect alu_exe_unit_0.io_brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect alu_exe_unit_0.io_brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect alu_exe_unit_0.io_brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect alu_exe_unit_0.io_brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect alu_exe_unit_0.io_brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect alu_exe_unit_0.io_brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect alu_exe_unit_0.io_brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect alu_exe_unit_0.io_brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect alu_exe_unit_0.io_brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect alu_exe_unit_0.io_brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect alu_exe_unit_0.io_brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect alu_exe_unit_0.io_brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect alu_exe_unit_0.io_brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect alu_exe_unit_0.io_brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect alu_exe_unit_0.io_brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect alu_exe_unit_0.io_brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect alu_exe_unit_0.io_brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect alu_exe_unit_0.io_brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect alu_exe_unit_0.io_brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect alu_exe_unit_0.io_brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect alu_exe_unit_0.io_brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect alu_exe_unit_0.io_brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect alu_exe_unit_0.io_brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect alu_exe_unit_0.io_brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect alu_exe_unit_0.io_brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect alu_exe_unit_0.io_brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect alu_exe_unit_0.io_brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect alu_exe_unit_0.io_brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect alu_exe_unit_0.io_brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect alu_exe_unit_0.io_brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect alu_exe_unit_0.io_brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect alu_exe_unit_0.io_brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect alu_exe_unit_0.io_brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect alu_exe_unit_0.io_brupdate.b2.uop.inst, brupdate.b2.uop.inst connect alu_exe_unit_0.io_brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect alu_exe_unit_0.io_brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect alu_exe_unit_1.io_brupdate.b2.target_offset, brupdate.b2.target_offset connect alu_exe_unit_1.io_brupdate.b2.jalr_target, brupdate.b2.jalr_target connect alu_exe_unit_1.io_brupdate.b2.pc_sel, brupdate.b2.pc_sel connect alu_exe_unit_1.io_brupdate.b2.cfi_type, brupdate.b2.cfi_type connect alu_exe_unit_1.io_brupdate.b2.taken, brupdate.b2.taken connect alu_exe_unit_1.io_brupdate.b2.mispredict, brupdate.b2.mispredict connect alu_exe_unit_1.io_brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect alu_exe_unit_1.io_brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect alu_exe_unit_1.io_brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect alu_exe_unit_1.io_brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect alu_exe_unit_1.io_brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect alu_exe_unit_1.io_brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect alu_exe_unit_1.io_brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect alu_exe_unit_1.io_brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect alu_exe_unit_1.io_brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect alu_exe_unit_1.io_brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect alu_exe_unit_1.io_brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect alu_exe_unit_1.io_brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect alu_exe_unit_1.io_brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect alu_exe_unit_1.io_brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect alu_exe_unit_1.io_brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect alu_exe_unit_1.io_brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect alu_exe_unit_1.io_brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect alu_exe_unit_1.io_brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect alu_exe_unit_1.io_brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect alu_exe_unit_1.io_brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect alu_exe_unit_1.io_brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect alu_exe_unit_1.io_brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect alu_exe_unit_1.io_brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect alu_exe_unit_1.io_brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect alu_exe_unit_1.io_brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect alu_exe_unit_1.io_brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect alu_exe_unit_1.io_brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect alu_exe_unit_1.io_brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect alu_exe_unit_1.io_brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect alu_exe_unit_1.io_brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect alu_exe_unit_1.io_brupdate.b2.uop.exception, brupdate.b2.uop.exception connect alu_exe_unit_1.io_brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect alu_exe_unit_1.io_brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect alu_exe_unit_1.io_brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect alu_exe_unit_1.io_brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect alu_exe_unit_1.io_brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect alu_exe_unit_1.io_brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect alu_exe_unit_1.io_brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect alu_exe_unit_1.io_brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect alu_exe_unit_1.io_brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect alu_exe_unit_1.io_brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect alu_exe_unit_1.io_brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect alu_exe_unit_1.io_brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect alu_exe_unit_1.io_brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect alu_exe_unit_1.io_brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect alu_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect alu_exe_unit_1.io_brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect alu_exe_unit_1.io_brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect alu_exe_unit_1.io_brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect alu_exe_unit_1.io_brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect alu_exe_unit_1.io_brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect alu_exe_unit_1.io_brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect alu_exe_unit_1.io_brupdate.b2.uop.taken, brupdate.b2.uop.taken connect alu_exe_unit_1.io_brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect alu_exe_unit_1.io_brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect alu_exe_unit_1.io_brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect alu_exe_unit_1.io_brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect alu_exe_unit_1.io_brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect alu_exe_unit_1.io_brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect alu_exe_unit_1.io_brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect alu_exe_unit_1.io_brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect alu_exe_unit_1.io_brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect alu_exe_unit_1.io_brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect alu_exe_unit_1.io_brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect alu_exe_unit_1.io_brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect alu_exe_unit_1.io_brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect alu_exe_unit_1.io_brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect alu_exe_unit_1.io_brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect alu_exe_unit_1.io_brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect alu_exe_unit_1.io_brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect alu_exe_unit_1.io_brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect alu_exe_unit_1.io_brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect alu_exe_unit_1.io_brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect alu_exe_unit_1.io_brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect alu_exe_unit_1.io_brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect alu_exe_unit_1.io_brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect alu_exe_unit_1.io_brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect alu_exe_unit_1.io_brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect alu_exe_unit_1.io_brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect alu_exe_unit_1.io_brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect alu_exe_unit_1.io_brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect alu_exe_unit_1.io_brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect alu_exe_unit_1.io_brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect alu_exe_unit_1.io_brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect alu_exe_unit_1.io_brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect alu_exe_unit_1.io_brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect alu_exe_unit_1.io_brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect alu_exe_unit_1.io_brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect alu_exe_unit_1.io_brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect alu_exe_unit_1.io_brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect alu_exe_unit_1.io_brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect alu_exe_unit_1.io_brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect alu_exe_unit_1.io_brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect alu_exe_unit_1.io_brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect alu_exe_unit_1.io_brupdate.b2.uop.inst, brupdate.b2.uop.inst connect alu_exe_unit_1.io_brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect alu_exe_unit_1.io_brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect mem_exe_unit_0.io_brupdate.b2.target_offset, brupdate.b2.target_offset connect mem_exe_unit_0.io_brupdate.b2.jalr_target, brupdate.b2.jalr_target connect mem_exe_unit_0.io_brupdate.b2.pc_sel, brupdate.b2.pc_sel connect mem_exe_unit_0.io_brupdate.b2.cfi_type, brupdate.b2.cfi_type connect mem_exe_unit_0.io_brupdate.b2.taken, brupdate.b2.taken connect mem_exe_unit_0.io_brupdate.b2.mispredict, brupdate.b2.mispredict connect mem_exe_unit_0.io_brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect mem_exe_unit_0.io_brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect mem_exe_unit_0.io_brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect mem_exe_unit_0.io_brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect mem_exe_unit_0.io_brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect mem_exe_unit_0.io_brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect mem_exe_unit_0.io_brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect mem_exe_unit_0.io_brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect mem_exe_unit_0.io_brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect mem_exe_unit_0.io_brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect mem_exe_unit_0.io_brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect mem_exe_unit_0.io_brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect mem_exe_unit_0.io_brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect mem_exe_unit_0.io_brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect mem_exe_unit_0.io_brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect mem_exe_unit_0.io_brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect mem_exe_unit_0.io_brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect mem_exe_unit_0.io_brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect mem_exe_unit_0.io_brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect mem_exe_unit_0.io_brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect mem_exe_unit_0.io_brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect mem_exe_unit_0.io_brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect mem_exe_unit_0.io_brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect mem_exe_unit_0.io_brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect mem_exe_unit_0.io_brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect mem_exe_unit_0.io_brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect mem_exe_unit_0.io_brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect mem_exe_unit_0.io_brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect mem_exe_unit_0.io_brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect mem_exe_unit_0.io_brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect mem_exe_unit_0.io_brupdate.b2.uop.exception, brupdate.b2.uop.exception connect mem_exe_unit_0.io_brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect mem_exe_unit_0.io_brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect mem_exe_unit_0.io_brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect mem_exe_unit_0.io_brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect mem_exe_unit_0.io_brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect mem_exe_unit_0.io_brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect mem_exe_unit_0.io_brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect mem_exe_unit_0.io_brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect mem_exe_unit_0.io_brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect mem_exe_unit_0.io_brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect mem_exe_unit_0.io_brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect mem_exe_unit_0.io_brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect mem_exe_unit_0.io_brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect mem_exe_unit_0.io_brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect mem_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect mem_exe_unit_0.io_brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect mem_exe_unit_0.io_brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect mem_exe_unit_0.io_brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect mem_exe_unit_0.io_brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect mem_exe_unit_0.io_brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect mem_exe_unit_0.io_brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect mem_exe_unit_0.io_brupdate.b2.uop.taken, brupdate.b2.uop.taken connect mem_exe_unit_0.io_brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect mem_exe_unit_0.io_brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect mem_exe_unit_0.io_brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect mem_exe_unit_0.io_brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect mem_exe_unit_0.io_brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect mem_exe_unit_0.io_brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect mem_exe_unit_0.io_brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect mem_exe_unit_0.io_brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect mem_exe_unit_0.io_brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect mem_exe_unit_0.io_brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect mem_exe_unit_0.io_brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect mem_exe_unit_0.io_brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect mem_exe_unit_0.io_brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect mem_exe_unit_0.io_brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect mem_exe_unit_0.io_brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect mem_exe_unit_0.io_brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect mem_exe_unit_0.io_brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect mem_exe_unit_0.io_brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect mem_exe_unit_0.io_brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect mem_exe_unit_0.io_brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect mem_exe_unit_0.io_brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect mem_exe_unit_0.io_brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect mem_exe_unit_0.io_brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect mem_exe_unit_0.io_brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect mem_exe_unit_0.io_brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect mem_exe_unit_0.io_brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect mem_exe_unit_0.io_brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect mem_exe_unit_0.io_brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect mem_exe_unit_0.io_brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect mem_exe_unit_0.io_brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect mem_exe_unit_0.io_brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect mem_exe_unit_0.io_brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect mem_exe_unit_0.io_brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect mem_exe_unit_0.io_brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect mem_exe_unit_0.io_brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect mem_exe_unit_0.io_brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect mem_exe_unit_0.io_brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect mem_exe_unit_0.io_brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect mem_exe_unit_0.io_brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect mem_exe_unit_0.io_brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect mem_exe_unit_0.io_brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect mem_exe_unit_0.io_brupdate.b2.uop.inst, brupdate.b2.uop.inst connect mem_exe_unit_0.io_brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect mem_exe_unit_0.io_brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect mem_exe_unit_1.io_brupdate.b2.target_offset, brupdate.b2.target_offset connect mem_exe_unit_1.io_brupdate.b2.jalr_target, brupdate.b2.jalr_target connect mem_exe_unit_1.io_brupdate.b2.pc_sel, brupdate.b2.pc_sel connect mem_exe_unit_1.io_brupdate.b2.cfi_type, brupdate.b2.cfi_type connect mem_exe_unit_1.io_brupdate.b2.taken, brupdate.b2.taken connect mem_exe_unit_1.io_brupdate.b2.mispredict, brupdate.b2.mispredict connect mem_exe_unit_1.io_brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect mem_exe_unit_1.io_brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect mem_exe_unit_1.io_brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect mem_exe_unit_1.io_brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect mem_exe_unit_1.io_brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect mem_exe_unit_1.io_brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect mem_exe_unit_1.io_brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect mem_exe_unit_1.io_brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect mem_exe_unit_1.io_brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect mem_exe_unit_1.io_brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect mem_exe_unit_1.io_brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect mem_exe_unit_1.io_brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect mem_exe_unit_1.io_brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect mem_exe_unit_1.io_brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect mem_exe_unit_1.io_brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect mem_exe_unit_1.io_brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect mem_exe_unit_1.io_brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect mem_exe_unit_1.io_brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect mem_exe_unit_1.io_brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect mem_exe_unit_1.io_brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect mem_exe_unit_1.io_brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect mem_exe_unit_1.io_brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect mem_exe_unit_1.io_brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect mem_exe_unit_1.io_brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect mem_exe_unit_1.io_brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect mem_exe_unit_1.io_brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect mem_exe_unit_1.io_brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect mem_exe_unit_1.io_brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect mem_exe_unit_1.io_brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect mem_exe_unit_1.io_brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect mem_exe_unit_1.io_brupdate.b2.uop.exception, brupdate.b2.uop.exception connect mem_exe_unit_1.io_brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect mem_exe_unit_1.io_brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect mem_exe_unit_1.io_brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect mem_exe_unit_1.io_brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect mem_exe_unit_1.io_brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect mem_exe_unit_1.io_brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect mem_exe_unit_1.io_brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect mem_exe_unit_1.io_brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect mem_exe_unit_1.io_brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect mem_exe_unit_1.io_brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect mem_exe_unit_1.io_brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect mem_exe_unit_1.io_brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect mem_exe_unit_1.io_brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect mem_exe_unit_1.io_brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect mem_exe_unit_1.io_brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect mem_exe_unit_1.io_brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect mem_exe_unit_1.io_brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect mem_exe_unit_1.io_brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect mem_exe_unit_1.io_brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect mem_exe_unit_1.io_brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect mem_exe_unit_1.io_brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect mem_exe_unit_1.io_brupdate.b2.uop.taken, brupdate.b2.uop.taken connect mem_exe_unit_1.io_brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect mem_exe_unit_1.io_brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect mem_exe_unit_1.io_brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect mem_exe_unit_1.io_brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect mem_exe_unit_1.io_brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect mem_exe_unit_1.io_brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect mem_exe_unit_1.io_brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect mem_exe_unit_1.io_brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect mem_exe_unit_1.io_brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect mem_exe_unit_1.io_brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect mem_exe_unit_1.io_brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect mem_exe_unit_1.io_brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect mem_exe_unit_1.io_brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect mem_exe_unit_1.io_brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect mem_exe_unit_1.io_brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect mem_exe_unit_1.io_brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect mem_exe_unit_1.io_brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect mem_exe_unit_1.io_brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect mem_exe_unit_1.io_brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect mem_exe_unit_1.io_brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect mem_exe_unit_1.io_brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect mem_exe_unit_1.io_brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect mem_exe_unit_1.io_brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect mem_exe_unit_1.io_brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect mem_exe_unit_1.io_brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect mem_exe_unit_1.io_brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect mem_exe_unit_1.io_brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect mem_exe_unit_1.io_brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect mem_exe_unit_1.io_brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect mem_exe_unit_1.io_brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect mem_exe_unit_1.io_brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect mem_exe_unit_1.io_brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect mem_exe_unit_1.io_brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect mem_exe_unit_1.io_brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect mem_exe_unit_1.io_brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect mem_exe_unit_1.io_brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect mem_exe_unit_1.io_brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect mem_exe_unit_1.io_brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect mem_exe_unit_1.io_brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect mem_exe_unit_1.io_brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect mem_exe_unit_1.io_brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect mem_exe_unit_1.io_brupdate.b2.uop.inst, brupdate.b2.uop.inst connect mem_exe_unit_1.io_brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect mem_exe_unit_1.io_brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect unique_exe_unit_0.io_brupdate.b2.target_offset, brupdate.b2.target_offset connect unique_exe_unit_0.io_brupdate.b2.jalr_target, brupdate.b2.jalr_target connect unique_exe_unit_0.io_brupdate.b2.pc_sel, brupdate.b2.pc_sel connect unique_exe_unit_0.io_brupdate.b2.cfi_type, brupdate.b2.cfi_type connect unique_exe_unit_0.io_brupdate.b2.taken, brupdate.b2.taken connect unique_exe_unit_0.io_brupdate.b2.mispredict, brupdate.b2.mispredict connect unique_exe_unit_0.io_brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect unique_exe_unit_0.io_brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect unique_exe_unit_0.io_brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect unique_exe_unit_0.io_brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect unique_exe_unit_0.io_brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect unique_exe_unit_0.io_brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect unique_exe_unit_0.io_brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect unique_exe_unit_0.io_brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect unique_exe_unit_0.io_brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect unique_exe_unit_0.io_brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect unique_exe_unit_0.io_brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect unique_exe_unit_0.io_brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect unique_exe_unit_0.io_brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect unique_exe_unit_0.io_brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect unique_exe_unit_0.io_brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect unique_exe_unit_0.io_brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect unique_exe_unit_0.io_brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect unique_exe_unit_0.io_brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect unique_exe_unit_0.io_brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect unique_exe_unit_0.io_brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect unique_exe_unit_0.io_brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect unique_exe_unit_0.io_brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect unique_exe_unit_0.io_brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect unique_exe_unit_0.io_brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect unique_exe_unit_0.io_brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect unique_exe_unit_0.io_brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect unique_exe_unit_0.io_brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect unique_exe_unit_0.io_brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect unique_exe_unit_0.io_brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect unique_exe_unit_0.io_brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect unique_exe_unit_0.io_brupdate.b2.uop.exception, brupdate.b2.uop.exception connect unique_exe_unit_0.io_brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect unique_exe_unit_0.io_brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect unique_exe_unit_0.io_brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect unique_exe_unit_0.io_brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect unique_exe_unit_0.io_brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect unique_exe_unit_0.io_brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect unique_exe_unit_0.io_brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect unique_exe_unit_0.io_brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect unique_exe_unit_0.io_brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect unique_exe_unit_0.io_brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect unique_exe_unit_0.io_brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect unique_exe_unit_0.io_brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect unique_exe_unit_0.io_brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect unique_exe_unit_0.io_brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect unique_exe_unit_0.io_brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect unique_exe_unit_0.io_brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect unique_exe_unit_0.io_brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect unique_exe_unit_0.io_brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect unique_exe_unit_0.io_brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect unique_exe_unit_0.io_brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect unique_exe_unit_0.io_brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect unique_exe_unit_0.io_brupdate.b2.uop.taken, brupdate.b2.uop.taken connect unique_exe_unit_0.io_brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect unique_exe_unit_0.io_brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect unique_exe_unit_0.io_brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect unique_exe_unit_0.io_brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect unique_exe_unit_0.io_brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect unique_exe_unit_0.io_brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect unique_exe_unit_0.io_brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect unique_exe_unit_0.io_brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect unique_exe_unit_0.io_brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect unique_exe_unit_0.io_brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect unique_exe_unit_0.io_brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect unique_exe_unit_0.io_brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect unique_exe_unit_0.io_brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect unique_exe_unit_0.io_brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect unique_exe_unit_0.io_brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect unique_exe_unit_0.io_brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect unique_exe_unit_0.io_brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect unique_exe_unit_0.io_brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect unique_exe_unit_0.io_brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect unique_exe_unit_0.io_brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect unique_exe_unit_0.io_brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect unique_exe_unit_0.io_brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect unique_exe_unit_0.io_brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect unique_exe_unit_0.io_brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect unique_exe_unit_0.io_brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect unique_exe_unit_0.io_brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect unique_exe_unit_0.io_brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect unique_exe_unit_0.io_brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect unique_exe_unit_0.io_brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect unique_exe_unit_0.io_brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect unique_exe_unit_0.io_brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect unique_exe_unit_0.io_brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect unique_exe_unit_0.io_brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect unique_exe_unit_0.io_brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect unique_exe_unit_0.io_brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect unique_exe_unit_0.io_brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect unique_exe_unit_0.io_brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect unique_exe_unit_0.io_brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect unique_exe_unit_0.io_brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect unique_exe_unit_0.io_brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect unique_exe_unit_0.io_brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect unique_exe_unit_0.io_brupdate.b2.uop.inst, brupdate.b2.uop.inst connect unique_exe_unit_0.io_brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect unique_exe_unit_0.io_brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect fp_pipeline.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect fp_pipeline.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect fp_pipeline.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect fp_pipeline.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect fp_pipeline.io.brupdate.b2.taken, brupdate.b2.taken connect fp_pipeline.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect fp_pipeline.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect fp_pipeline.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect fp_pipeline.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect fp_pipeline.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect fp_pipeline.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect fp_pipeline.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect fp_pipeline.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect fp_pipeline.io.brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect fp_pipeline.io.brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect fp_pipeline.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect fp_pipeline.io.brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect fp_pipeline.io.brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect fp_pipeline.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect fp_pipeline.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect fp_pipeline.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect fp_pipeline.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect fp_pipeline.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect fp_pipeline.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect fp_pipeline.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect fp_pipeline.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect fp_pipeline.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect fp_pipeline.io.brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect fp_pipeline.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect fp_pipeline.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect fp_pipeline.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect fp_pipeline.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect fp_pipeline.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect fp_pipeline.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect fp_pipeline.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect fp_pipeline.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect fp_pipeline.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect fp_pipeline.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect fp_pipeline.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect fp_pipeline.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect fp_pipeline.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect fp_pipeline.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect fp_pipeline.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect fp_pipeline.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect fp_pipeline.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect fp_pipeline.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect fp_pipeline.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect fp_pipeline.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect fp_pipeline.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect fp_pipeline.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect fp_pipeline.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect fp_pipeline.io.brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect fp_pipeline.io.brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect fp_pipeline.io.brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect fp_pipeline.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect fp_pipeline.io.brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect fp_pipeline.io.brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect fp_pipeline.io.brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect fp_pipeline.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect fp_pipeline.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect fp_pipeline.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect fp_pipeline.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect fp_pipeline.io.brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect fp_pipeline.io.brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect fp_pipeline.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect fp_pipeline.io.brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect fp_pipeline.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect fp_pipeline.io.brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect fp_pipeline.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect fp_pipeline.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect fp_pipeline.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect fp_pipeline.io.brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect fp_pipeline.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect fp_pipeline.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect fp_pipeline.io.brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect fp_pipeline.io.brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect fp_pipeline.io.brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect fp_pipeline.io.brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect fp_pipeline.io.brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect fp_pipeline.io.brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect fp_pipeline.io.brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect fp_pipeline.io.brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect fp_pipeline.io.brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect fp_pipeline.io.brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect fp_pipeline.io.brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect fp_pipeline.io.brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect fp_pipeline.io.brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect fp_pipeline.io.brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect fp_pipeline.io.brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect fp_pipeline.io.brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect fp_pipeline.io.brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect fp_pipeline.io.brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect fp_pipeline.io.brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect fp_pipeline.io.brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect fp_pipeline.io.brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect fp_pipeline.io.brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect fp_pipeline.io.brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect fp_pipeline.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect fp_pipeline.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect fp_pipeline.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect fp_pipeline.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect fp_pipeline.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect fp_pipeline.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect io.lsu.dgen[0], mem_exe_unit_0.io_dgen connect io.lsu.agen[0], mem_exe_unit_1.io_agen connect io.lsu.dgen[1], mem_exe_unit_1.io_dgen connect io.lsu.dgen[2], fp_pipeline.io.dgen wire _hits_WIRE : UInt<1>[4] connect _hits_WIRE[0], UInt<1>(0h0) connect _hits_WIRE[1], UInt<1>(0h0) connect _hits_WIRE[2], UInt<1>(0h0) connect _hits_WIRE[3], UInt<1>(0h0) wire hits : UInt<1>[4] connect hits, _hits_WIRE wire _hits_WIRE_1 : UInt<1>[4] connect _hits_WIRE_1[0], UInt<1>(0h0) connect _hits_WIRE_1[1], UInt<1>(0h0) connect _hits_WIRE_1[2], UInt<1>(0h0) connect _hits_WIRE_1[3], UInt<1>(0h0) wire hits_1 : UInt<1>[4] connect hits_1, _hits_WIRE_1 wire _hits_WIRE_2 : UInt<1>[6] connect _hits_WIRE_2[0], UInt<1>(0h0) connect _hits_WIRE_2[1], UInt<1>(0h0) connect _hits_WIRE_2[2], UInt<1>(0h0) connect _hits_WIRE_2[3], UInt<1>(0h0) connect _hits_WIRE_2[4], UInt<1>(0h0) connect _hits_WIRE_2[5], UInt<1>(0h0) wire hits_2 : UInt<1>[6] connect hits_2, _hits_WIRE_2 inst csr of CSRFile connect csr.clock, clock connect csr.reset, reset invalidate csr.io.inst[0] invalidate csr.io.inst[1] connect csr.io.rocc_interrupt, io.rocc.interrupt invalidate csr.io.gva invalidate csr.io.htval connect csr.io.mhtinst_read_pseudo, UInt<1>(0h0) wire custom_csrs : { csrs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<64>, value : UInt<64>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<64>}[4]} connect custom_csrs.csrs[0].stall, UInt<1>(0h0) connect custom_csrs.csrs[0].set, UInt<1>(0h0) invalidate custom_csrs.csrs[0].sdata connect custom_csrs.csrs[1].stall, UInt<1>(0h0) connect custom_csrs.csrs[1].set, UInt<1>(0h0) invalidate custom_csrs.csrs[1].sdata connect custom_csrs.csrs[2].stall, UInt<1>(0h0) connect custom_csrs.csrs[2].set, UInt<1>(0h0) invalidate custom_csrs.csrs[2].sdata connect custom_csrs.csrs[3].stall, UInt<1>(0h0) connect custom_csrs.csrs[3].set, UInt<1>(0h0) invalidate custom_csrs.csrs[3].sdata connect csr.io.customCSRs[0].sdata, custom_csrs.csrs[0].sdata connect csr.io.customCSRs[0].set, custom_csrs.csrs[0].set connect csr.io.customCSRs[0].stall, custom_csrs.csrs[0].stall connect custom_csrs.csrs[0].value, csr.io.customCSRs[0].value connect custom_csrs.csrs[0].wdata, csr.io.customCSRs[0].wdata connect custom_csrs.csrs[0].wen, csr.io.customCSRs[0].wen connect custom_csrs.csrs[0].ren, csr.io.customCSRs[0].ren connect csr.io.customCSRs[1].sdata, custom_csrs.csrs[1].sdata connect csr.io.customCSRs[1].set, custom_csrs.csrs[1].set connect csr.io.customCSRs[1].stall, custom_csrs.csrs[1].stall connect custom_csrs.csrs[1].value, csr.io.customCSRs[1].value connect custom_csrs.csrs[1].wdata, csr.io.customCSRs[1].wdata connect custom_csrs.csrs[1].wen, csr.io.customCSRs[1].wen connect custom_csrs.csrs[1].ren, csr.io.customCSRs[1].ren connect csr.io.customCSRs[2].sdata, custom_csrs.csrs[2].sdata connect csr.io.customCSRs[2].set, custom_csrs.csrs[2].set connect csr.io.customCSRs[2].stall, custom_csrs.csrs[2].stall connect custom_csrs.csrs[2].value, csr.io.customCSRs[2].value connect custom_csrs.csrs[2].wdata, csr.io.customCSRs[2].wdata connect custom_csrs.csrs[2].wen, csr.io.customCSRs[2].wen connect custom_csrs.csrs[2].ren, csr.io.customCSRs[2].ren connect csr.io.customCSRs[3].sdata, custom_csrs.csrs[3].sdata connect csr.io.customCSRs[3].set, custom_csrs.csrs[3].set connect csr.io.customCSRs[3].stall, custom_csrs.csrs[3].stall connect custom_csrs.csrs[3].value, csr.io.customCSRs[3].value connect custom_csrs.csrs[3].wdata, csr.io.customCSRs[3].wdata connect custom_csrs.csrs[3].wen, csr.io.customCSRs[3].wen connect custom_csrs.csrs[3].ren, csr.io.customCSRs[3].ren node _io_ifu_enable_bpd_T = bits(custom_csrs.csrs[1].value, 0, 0) connect io.ifu.enable_bpd, _io_ifu_enable_bpd_T node csr_io_counters_0_inc_set = bits(csr.io.counters[0].eventSel, 1, 0) node csr_io_counters_0_inc_mask = shr(csr.io.counters[0].eventSel, 8) connect hits[0], rob.io.com_xcpt.valid connect hits[1], UInt<1>(0h0) connect hits[2], UInt<1>(0h0) connect hits[3], UInt<1>(0h0) node csr_io_counters_0_inc_sets_lo = cat(hits[1], hits[0]) node csr_io_counters_0_inc_sets_hi = cat(hits[3], hits[2]) node _csr_io_counters_0_inc_sets_T = cat(csr_io_counters_0_inc_sets_hi, csr_io_counters_0_inc_sets_lo) node _csr_io_counters_0_inc_sets_T_1 = and(csr_io_counters_0_inc_mask, _csr_io_counters_0_inc_sets_T) node csr_io_counters_0_inc_sets_0 = orr(_csr_io_counters_0_inc_sets_T_1) node _csr_io_counters_0_inc_sets_T_2 = eq(b2.cfi_type, UInt<3>(0h3)) node _csr_io_counters_0_inc_sets_T_3 = and(b2.mispredict, _csr_io_counters_0_inc_sets_T_2) connect hits_1[0], UInt<1>(0h0) connect hits_1[1], b2.mispredict connect hits_1[2], _csr_io_counters_0_inc_sets_T_3 connect hits_1[3], rob.io.flush.valid node csr_io_counters_0_inc_sets_lo_1 = cat(hits_1[1], hits_1[0]) node csr_io_counters_0_inc_sets_hi_1 = cat(hits_1[3], hits_1[2]) node _csr_io_counters_0_inc_sets_T_4 = cat(csr_io_counters_0_inc_sets_hi_1, csr_io_counters_0_inc_sets_lo_1) node _csr_io_counters_0_inc_sets_T_5 = and(csr_io_counters_0_inc_mask, _csr_io_counters_0_inc_sets_T_4) node csr_io_counters_0_inc_sets_1 = orr(_csr_io_counters_0_inc_sets_T_5) connect hits_2[0], io.ifu.perf.acquire connect hits_2[1], io.lsu.perf.acquire connect hits_2[2], io.lsu.perf.release connect hits_2[3], io.ifu.perf.tlbMiss connect hits_2[4], io.lsu.perf.tlbMiss connect hits_2[5], io.ptw.perf.l2miss node csr_io_counters_0_inc_sets_lo_hi = cat(hits_2[2], hits_2[1]) node csr_io_counters_0_inc_sets_lo_2 = cat(csr_io_counters_0_inc_sets_lo_hi, hits_2[0]) node csr_io_counters_0_inc_sets_hi_hi = cat(hits_2[5], hits_2[4]) node csr_io_counters_0_inc_sets_hi_2 = cat(csr_io_counters_0_inc_sets_hi_hi, hits_2[3]) node _csr_io_counters_0_inc_sets_T_6 = cat(csr_io_counters_0_inc_sets_hi_2, csr_io_counters_0_inc_sets_lo_2) node _csr_io_counters_0_inc_sets_T_7 = and(csr_io_counters_0_inc_mask, _csr_io_counters_0_inc_sets_T_6) node csr_io_counters_0_inc_sets_2 = orr(_csr_io_counters_0_inc_sets_T_7) node _csr_io_counters_0_inc_T = eq(csr_io_counters_0_inc_set, UInt<1>(0h1)) node _csr_io_counters_0_inc_T_1 = mux(_csr_io_counters_0_inc_T, csr_io_counters_0_inc_sets_1, csr_io_counters_0_inc_sets_0) node _csr_io_counters_0_inc_T_2 = eq(csr_io_counters_0_inc_set, UInt<2>(0h2)) node _csr_io_counters_0_inc_T_3 = mux(_csr_io_counters_0_inc_T_2, csr_io_counters_0_inc_sets_2, _csr_io_counters_0_inc_T_1) node _csr_io_counters_0_inc_T_4 = eq(csr_io_counters_0_inc_set, UInt<2>(0h3)) node _csr_io_counters_0_inc_T_5 = mux(_csr_io_counters_0_inc_T_4, csr_io_counters_0_inc_sets_2, _csr_io_counters_0_inc_T_3) reg csr_io_counters_0_inc_REG : UInt<1>, clock connect csr_io_counters_0_inc_REG, _csr_io_counters_0_inc_T_5 connect csr.io.counters[0].inc, csr_io_counters_0_inc_REG node csr_io_counters_1_inc_set = bits(csr.io.counters[1].eventSel, 1, 0) node csr_io_counters_1_inc_mask = shr(csr.io.counters[1].eventSel, 8) connect hits[0], rob.io.com_xcpt.valid connect hits[1], UInt<1>(0h0) connect hits[2], UInt<1>(0h0) connect hits[3], UInt<1>(0h0) node csr_io_counters_1_inc_sets_lo = cat(hits[1], hits[0]) node csr_io_counters_1_inc_sets_hi = cat(hits[3], hits[2]) node _csr_io_counters_1_inc_sets_T = cat(csr_io_counters_1_inc_sets_hi, csr_io_counters_1_inc_sets_lo) node _csr_io_counters_1_inc_sets_T_1 = and(csr_io_counters_1_inc_mask, _csr_io_counters_1_inc_sets_T) node csr_io_counters_1_inc_sets_0 = orr(_csr_io_counters_1_inc_sets_T_1) node _csr_io_counters_1_inc_sets_T_2 = eq(b2.cfi_type, UInt<3>(0h3)) node _csr_io_counters_1_inc_sets_T_3 = and(b2.mispredict, _csr_io_counters_1_inc_sets_T_2) connect hits_1[0], UInt<1>(0h0) connect hits_1[1], b2.mispredict connect hits_1[2], _csr_io_counters_1_inc_sets_T_3 connect hits_1[3], rob.io.flush.valid node csr_io_counters_1_inc_sets_lo_1 = cat(hits_1[1], hits_1[0]) node csr_io_counters_1_inc_sets_hi_1 = cat(hits_1[3], hits_1[2]) node _csr_io_counters_1_inc_sets_T_4 = cat(csr_io_counters_1_inc_sets_hi_1, csr_io_counters_1_inc_sets_lo_1) node _csr_io_counters_1_inc_sets_T_5 = and(csr_io_counters_1_inc_mask, _csr_io_counters_1_inc_sets_T_4) node csr_io_counters_1_inc_sets_1 = orr(_csr_io_counters_1_inc_sets_T_5) connect hits_2[0], io.ifu.perf.acquire connect hits_2[1], io.lsu.perf.acquire connect hits_2[2], io.lsu.perf.release connect hits_2[3], io.ifu.perf.tlbMiss connect hits_2[4], io.lsu.perf.tlbMiss connect hits_2[5], io.ptw.perf.l2miss node csr_io_counters_1_inc_sets_lo_hi = cat(hits_2[2], hits_2[1]) node csr_io_counters_1_inc_sets_lo_2 = cat(csr_io_counters_1_inc_sets_lo_hi, hits_2[0]) node csr_io_counters_1_inc_sets_hi_hi = cat(hits_2[5], hits_2[4]) node csr_io_counters_1_inc_sets_hi_2 = cat(csr_io_counters_1_inc_sets_hi_hi, hits_2[3]) node _csr_io_counters_1_inc_sets_T_6 = cat(csr_io_counters_1_inc_sets_hi_2, csr_io_counters_1_inc_sets_lo_2) node _csr_io_counters_1_inc_sets_T_7 = and(csr_io_counters_1_inc_mask, _csr_io_counters_1_inc_sets_T_6) node csr_io_counters_1_inc_sets_2 = orr(_csr_io_counters_1_inc_sets_T_7) node _csr_io_counters_1_inc_T = eq(csr_io_counters_1_inc_set, UInt<1>(0h1)) node _csr_io_counters_1_inc_T_1 = mux(_csr_io_counters_1_inc_T, csr_io_counters_1_inc_sets_1, csr_io_counters_1_inc_sets_0) node _csr_io_counters_1_inc_T_2 = eq(csr_io_counters_1_inc_set, UInt<2>(0h2)) node _csr_io_counters_1_inc_T_3 = mux(_csr_io_counters_1_inc_T_2, csr_io_counters_1_inc_sets_2, _csr_io_counters_1_inc_T_1) node _csr_io_counters_1_inc_T_4 = eq(csr_io_counters_1_inc_set, UInt<2>(0h3)) node _csr_io_counters_1_inc_T_5 = mux(_csr_io_counters_1_inc_T_4, csr_io_counters_1_inc_sets_2, _csr_io_counters_1_inc_T_3) reg csr_io_counters_1_inc_REG : UInt<1>, clock connect csr_io_counters_1_inc_REG, _csr_io_counters_1_inc_T_5 connect csr.io.counters[1].inc, csr_io_counters_1_inc_REG node csr_io_counters_2_inc_set = bits(csr.io.counters[2].eventSel, 1, 0) node csr_io_counters_2_inc_mask = shr(csr.io.counters[2].eventSel, 8) connect hits[0], rob.io.com_xcpt.valid connect hits[1], UInt<1>(0h0) connect hits[2], UInt<1>(0h0) connect hits[3], UInt<1>(0h0) node csr_io_counters_2_inc_sets_lo = cat(hits[1], hits[0]) node csr_io_counters_2_inc_sets_hi = cat(hits[3], hits[2]) node _csr_io_counters_2_inc_sets_T = cat(csr_io_counters_2_inc_sets_hi, csr_io_counters_2_inc_sets_lo) node _csr_io_counters_2_inc_sets_T_1 = and(csr_io_counters_2_inc_mask, _csr_io_counters_2_inc_sets_T) node csr_io_counters_2_inc_sets_0 = orr(_csr_io_counters_2_inc_sets_T_1) node _csr_io_counters_2_inc_sets_T_2 = eq(b2.cfi_type, UInt<3>(0h3)) node _csr_io_counters_2_inc_sets_T_3 = and(b2.mispredict, _csr_io_counters_2_inc_sets_T_2) connect hits_1[0], UInt<1>(0h0) connect hits_1[1], b2.mispredict connect hits_1[2], _csr_io_counters_2_inc_sets_T_3 connect hits_1[3], rob.io.flush.valid node csr_io_counters_2_inc_sets_lo_1 = cat(hits_1[1], hits_1[0]) node csr_io_counters_2_inc_sets_hi_1 = cat(hits_1[3], hits_1[2]) node _csr_io_counters_2_inc_sets_T_4 = cat(csr_io_counters_2_inc_sets_hi_1, csr_io_counters_2_inc_sets_lo_1) node _csr_io_counters_2_inc_sets_T_5 = and(csr_io_counters_2_inc_mask, _csr_io_counters_2_inc_sets_T_4) node csr_io_counters_2_inc_sets_1 = orr(_csr_io_counters_2_inc_sets_T_5) connect hits_2[0], io.ifu.perf.acquire connect hits_2[1], io.lsu.perf.acquire connect hits_2[2], io.lsu.perf.release connect hits_2[3], io.ifu.perf.tlbMiss connect hits_2[4], io.lsu.perf.tlbMiss connect hits_2[5], io.ptw.perf.l2miss node csr_io_counters_2_inc_sets_lo_hi = cat(hits_2[2], hits_2[1]) node csr_io_counters_2_inc_sets_lo_2 = cat(csr_io_counters_2_inc_sets_lo_hi, hits_2[0]) node csr_io_counters_2_inc_sets_hi_hi = cat(hits_2[5], hits_2[4]) node csr_io_counters_2_inc_sets_hi_2 = cat(csr_io_counters_2_inc_sets_hi_hi, hits_2[3]) node _csr_io_counters_2_inc_sets_T_6 = cat(csr_io_counters_2_inc_sets_hi_2, csr_io_counters_2_inc_sets_lo_2) node _csr_io_counters_2_inc_sets_T_7 = and(csr_io_counters_2_inc_mask, _csr_io_counters_2_inc_sets_T_6) node csr_io_counters_2_inc_sets_2 = orr(_csr_io_counters_2_inc_sets_T_7) node _csr_io_counters_2_inc_T = eq(csr_io_counters_2_inc_set, UInt<1>(0h1)) node _csr_io_counters_2_inc_T_1 = mux(_csr_io_counters_2_inc_T, csr_io_counters_2_inc_sets_1, csr_io_counters_2_inc_sets_0) node _csr_io_counters_2_inc_T_2 = eq(csr_io_counters_2_inc_set, UInt<2>(0h2)) node _csr_io_counters_2_inc_T_3 = mux(_csr_io_counters_2_inc_T_2, csr_io_counters_2_inc_sets_2, _csr_io_counters_2_inc_T_1) node _csr_io_counters_2_inc_T_4 = eq(csr_io_counters_2_inc_set, UInt<2>(0h3)) node _csr_io_counters_2_inc_T_5 = mux(_csr_io_counters_2_inc_T_4, csr_io_counters_2_inc_sets_2, _csr_io_counters_2_inc_T_3) reg csr_io_counters_2_inc_REG : UInt<1>, clock connect csr_io_counters_2_inc_REG, _csr_io_counters_2_inc_T_5 connect csr.io.counters[2].inc, csr_io_counters_2_inc_REG node csr_io_counters_3_inc_set = bits(csr.io.counters[3].eventSel, 1, 0) node csr_io_counters_3_inc_mask = shr(csr.io.counters[3].eventSel, 8) connect hits[0], rob.io.com_xcpt.valid connect hits[1], UInt<1>(0h0) connect hits[2], UInt<1>(0h0) connect hits[3], UInt<1>(0h0) node csr_io_counters_3_inc_sets_lo = cat(hits[1], hits[0]) node csr_io_counters_3_inc_sets_hi = cat(hits[3], hits[2]) node _csr_io_counters_3_inc_sets_T = cat(csr_io_counters_3_inc_sets_hi, csr_io_counters_3_inc_sets_lo) node _csr_io_counters_3_inc_sets_T_1 = and(csr_io_counters_3_inc_mask, _csr_io_counters_3_inc_sets_T) node csr_io_counters_3_inc_sets_0 = orr(_csr_io_counters_3_inc_sets_T_1) node _csr_io_counters_3_inc_sets_T_2 = eq(b2.cfi_type, UInt<3>(0h3)) node _csr_io_counters_3_inc_sets_T_3 = and(b2.mispredict, _csr_io_counters_3_inc_sets_T_2) connect hits_1[0], UInt<1>(0h0) connect hits_1[1], b2.mispredict connect hits_1[2], _csr_io_counters_3_inc_sets_T_3 connect hits_1[3], rob.io.flush.valid node csr_io_counters_3_inc_sets_lo_1 = cat(hits_1[1], hits_1[0]) node csr_io_counters_3_inc_sets_hi_1 = cat(hits_1[3], hits_1[2]) node _csr_io_counters_3_inc_sets_T_4 = cat(csr_io_counters_3_inc_sets_hi_1, csr_io_counters_3_inc_sets_lo_1) node _csr_io_counters_3_inc_sets_T_5 = and(csr_io_counters_3_inc_mask, _csr_io_counters_3_inc_sets_T_4) node csr_io_counters_3_inc_sets_1 = orr(_csr_io_counters_3_inc_sets_T_5) connect hits_2[0], io.ifu.perf.acquire connect hits_2[1], io.lsu.perf.acquire connect hits_2[2], io.lsu.perf.release connect hits_2[3], io.ifu.perf.tlbMiss connect hits_2[4], io.lsu.perf.tlbMiss connect hits_2[5], io.ptw.perf.l2miss node csr_io_counters_3_inc_sets_lo_hi = cat(hits_2[2], hits_2[1]) node csr_io_counters_3_inc_sets_lo_2 = cat(csr_io_counters_3_inc_sets_lo_hi, hits_2[0]) node csr_io_counters_3_inc_sets_hi_hi = cat(hits_2[5], hits_2[4]) node csr_io_counters_3_inc_sets_hi_2 = cat(csr_io_counters_3_inc_sets_hi_hi, hits_2[3]) node _csr_io_counters_3_inc_sets_T_6 = cat(csr_io_counters_3_inc_sets_hi_2, csr_io_counters_3_inc_sets_lo_2) node _csr_io_counters_3_inc_sets_T_7 = and(csr_io_counters_3_inc_mask, _csr_io_counters_3_inc_sets_T_6) node csr_io_counters_3_inc_sets_2 = orr(_csr_io_counters_3_inc_sets_T_7) node _csr_io_counters_3_inc_T = eq(csr_io_counters_3_inc_set, UInt<1>(0h1)) node _csr_io_counters_3_inc_T_1 = mux(_csr_io_counters_3_inc_T, csr_io_counters_3_inc_sets_1, csr_io_counters_3_inc_sets_0) node _csr_io_counters_3_inc_T_2 = eq(csr_io_counters_3_inc_set, UInt<2>(0h2)) node _csr_io_counters_3_inc_T_3 = mux(_csr_io_counters_3_inc_T_2, csr_io_counters_3_inc_sets_2, _csr_io_counters_3_inc_T_1) node _csr_io_counters_3_inc_T_4 = eq(csr_io_counters_3_inc_set, UInt<2>(0h3)) node _csr_io_counters_3_inc_T_5 = mux(_csr_io_counters_3_inc_T_4, csr_io_counters_3_inc_sets_2, _csr_io_counters_3_inc_T_3) reg csr_io_counters_3_inc_REG : UInt<1>, clock connect csr_io_counters_3_inc_REG, _csr_io_counters_3_inc_T_5 connect csr.io.counters[3].inc, csr_io_counters_3_inc_REG node csr_io_counters_4_inc_set = bits(csr.io.counters[4].eventSel, 1, 0) node csr_io_counters_4_inc_mask = shr(csr.io.counters[4].eventSel, 8) connect hits[0], rob.io.com_xcpt.valid connect hits[1], UInt<1>(0h0) connect hits[2], UInt<1>(0h0) connect hits[3], UInt<1>(0h0) node csr_io_counters_4_inc_sets_lo = cat(hits[1], hits[0]) node csr_io_counters_4_inc_sets_hi = cat(hits[3], hits[2]) node _csr_io_counters_4_inc_sets_T = cat(csr_io_counters_4_inc_sets_hi, csr_io_counters_4_inc_sets_lo) node _csr_io_counters_4_inc_sets_T_1 = and(csr_io_counters_4_inc_mask, _csr_io_counters_4_inc_sets_T) node csr_io_counters_4_inc_sets_0 = orr(_csr_io_counters_4_inc_sets_T_1) node _csr_io_counters_4_inc_sets_T_2 = eq(b2.cfi_type, UInt<3>(0h3)) node _csr_io_counters_4_inc_sets_T_3 = and(b2.mispredict, _csr_io_counters_4_inc_sets_T_2) connect hits_1[0], UInt<1>(0h0) connect hits_1[1], b2.mispredict connect hits_1[2], _csr_io_counters_4_inc_sets_T_3 connect hits_1[3], rob.io.flush.valid node csr_io_counters_4_inc_sets_lo_1 = cat(hits_1[1], hits_1[0]) node csr_io_counters_4_inc_sets_hi_1 = cat(hits_1[3], hits_1[2]) node _csr_io_counters_4_inc_sets_T_4 = cat(csr_io_counters_4_inc_sets_hi_1, csr_io_counters_4_inc_sets_lo_1) node _csr_io_counters_4_inc_sets_T_5 = and(csr_io_counters_4_inc_mask, _csr_io_counters_4_inc_sets_T_4) node csr_io_counters_4_inc_sets_1 = orr(_csr_io_counters_4_inc_sets_T_5) connect hits_2[0], io.ifu.perf.acquire connect hits_2[1], io.lsu.perf.acquire connect hits_2[2], io.lsu.perf.release connect hits_2[3], io.ifu.perf.tlbMiss connect hits_2[4], io.lsu.perf.tlbMiss connect hits_2[5], io.ptw.perf.l2miss node csr_io_counters_4_inc_sets_lo_hi = cat(hits_2[2], hits_2[1]) node csr_io_counters_4_inc_sets_lo_2 = cat(csr_io_counters_4_inc_sets_lo_hi, hits_2[0]) node csr_io_counters_4_inc_sets_hi_hi = cat(hits_2[5], hits_2[4]) node csr_io_counters_4_inc_sets_hi_2 = cat(csr_io_counters_4_inc_sets_hi_hi, hits_2[3]) node _csr_io_counters_4_inc_sets_T_6 = cat(csr_io_counters_4_inc_sets_hi_2, csr_io_counters_4_inc_sets_lo_2) node _csr_io_counters_4_inc_sets_T_7 = and(csr_io_counters_4_inc_mask, _csr_io_counters_4_inc_sets_T_6) node csr_io_counters_4_inc_sets_2 = orr(_csr_io_counters_4_inc_sets_T_7) node _csr_io_counters_4_inc_T = eq(csr_io_counters_4_inc_set, UInt<1>(0h1)) node _csr_io_counters_4_inc_T_1 = mux(_csr_io_counters_4_inc_T, csr_io_counters_4_inc_sets_1, csr_io_counters_4_inc_sets_0) node _csr_io_counters_4_inc_T_2 = eq(csr_io_counters_4_inc_set, UInt<2>(0h2)) node _csr_io_counters_4_inc_T_3 = mux(_csr_io_counters_4_inc_T_2, csr_io_counters_4_inc_sets_2, _csr_io_counters_4_inc_T_1) node _csr_io_counters_4_inc_T_4 = eq(csr_io_counters_4_inc_set, UInt<2>(0h3)) node _csr_io_counters_4_inc_T_5 = mux(_csr_io_counters_4_inc_T_4, csr_io_counters_4_inc_sets_2, _csr_io_counters_4_inc_T_3) reg csr_io_counters_4_inc_REG : UInt<1>, clock connect csr_io_counters_4_inc_REG, _csr_io_counters_4_inc_T_5 connect csr.io.counters[4].inc, csr_io_counters_4_inc_REG node csr_io_counters_5_inc_set = bits(csr.io.counters[5].eventSel, 1, 0) node csr_io_counters_5_inc_mask = shr(csr.io.counters[5].eventSel, 8) connect hits[0], rob.io.com_xcpt.valid connect hits[1], UInt<1>(0h0) connect hits[2], UInt<1>(0h0) connect hits[3], UInt<1>(0h0) node csr_io_counters_5_inc_sets_lo = cat(hits[1], hits[0]) node csr_io_counters_5_inc_sets_hi = cat(hits[3], hits[2]) node _csr_io_counters_5_inc_sets_T = cat(csr_io_counters_5_inc_sets_hi, csr_io_counters_5_inc_sets_lo) node _csr_io_counters_5_inc_sets_T_1 = and(csr_io_counters_5_inc_mask, _csr_io_counters_5_inc_sets_T) node csr_io_counters_5_inc_sets_0 = orr(_csr_io_counters_5_inc_sets_T_1) node _csr_io_counters_5_inc_sets_T_2 = eq(b2.cfi_type, UInt<3>(0h3)) node _csr_io_counters_5_inc_sets_T_3 = and(b2.mispredict, _csr_io_counters_5_inc_sets_T_2) connect hits_1[0], UInt<1>(0h0) connect hits_1[1], b2.mispredict connect hits_1[2], _csr_io_counters_5_inc_sets_T_3 connect hits_1[3], rob.io.flush.valid node csr_io_counters_5_inc_sets_lo_1 = cat(hits_1[1], hits_1[0]) node csr_io_counters_5_inc_sets_hi_1 = cat(hits_1[3], hits_1[2]) node _csr_io_counters_5_inc_sets_T_4 = cat(csr_io_counters_5_inc_sets_hi_1, csr_io_counters_5_inc_sets_lo_1) node _csr_io_counters_5_inc_sets_T_5 = and(csr_io_counters_5_inc_mask, _csr_io_counters_5_inc_sets_T_4) node csr_io_counters_5_inc_sets_1 = orr(_csr_io_counters_5_inc_sets_T_5) connect hits_2[0], io.ifu.perf.acquire connect hits_2[1], io.lsu.perf.acquire connect hits_2[2], io.lsu.perf.release connect hits_2[3], io.ifu.perf.tlbMiss connect hits_2[4], io.lsu.perf.tlbMiss connect hits_2[5], io.ptw.perf.l2miss node csr_io_counters_5_inc_sets_lo_hi = cat(hits_2[2], hits_2[1]) node csr_io_counters_5_inc_sets_lo_2 = cat(csr_io_counters_5_inc_sets_lo_hi, hits_2[0]) node csr_io_counters_5_inc_sets_hi_hi = cat(hits_2[5], hits_2[4]) node csr_io_counters_5_inc_sets_hi_2 = cat(csr_io_counters_5_inc_sets_hi_hi, hits_2[3]) node _csr_io_counters_5_inc_sets_T_6 = cat(csr_io_counters_5_inc_sets_hi_2, csr_io_counters_5_inc_sets_lo_2) node _csr_io_counters_5_inc_sets_T_7 = and(csr_io_counters_5_inc_mask, _csr_io_counters_5_inc_sets_T_6) node csr_io_counters_5_inc_sets_2 = orr(_csr_io_counters_5_inc_sets_T_7) node _csr_io_counters_5_inc_T = eq(csr_io_counters_5_inc_set, UInt<1>(0h1)) node _csr_io_counters_5_inc_T_1 = mux(_csr_io_counters_5_inc_T, csr_io_counters_5_inc_sets_1, csr_io_counters_5_inc_sets_0) node _csr_io_counters_5_inc_T_2 = eq(csr_io_counters_5_inc_set, UInt<2>(0h2)) node _csr_io_counters_5_inc_T_3 = mux(_csr_io_counters_5_inc_T_2, csr_io_counters_5_inc_sets_2, _csr_io_counters_5_inc_T_1) node _csr_io_counters_5_inc_T_4 = eq(csr_io_counters_5_inc_set, UInt<2>(0h3)) node _csr_io_counters_5_inc_T_5 = mux(_csr_io_counters_5_inc_T_4, csr_io_counters_5_inc_sets_2, _csr_io_counters_5_inc_T_3) reg csr_io_counters_5_inc_REG : UInt<1>, clock connect csr_io_counters_5_inc_REG, _csr_io_counters_5_inc_T_5 connect csr.io.counters[5].inc, csr_io_counters_5_inc_REG regreset debug_tsc_reg : UInt<64>, clock, reset, UInt<64>(0h0) regreset debug_irt_reg : UInt<64>, clock, reset, UInt<64>(0h0) wire _debug_brs_WIRE : UInt<64>[5] connect _debug_brs_WIRE[0], UInt<64>(0h0) connect _debug_brs_WIRE[1], UInt<64>(0h0) connect _debug_brs_WIRE[2], UInt<64>(0h0) connect _debug_brs_WIRE[3], UInt<64>(0h0) connect _debug_brs_WIRE[4], UInt<64>(0h0) regreset debug_brs : UInt<64>[5], clock, reset, _debug_brs_WIRE wire _debug_jals_WIRE : UInt<64>[5] connect _debug_jals_WIRE[0], UInt<64>(0h0) connect _debug_jals_WIRE[1], UInt<64>(0h0) connect _debug_jals_WIRE[2], UInt<64>(0h0) connect _debug_jals_WIRE[3], UInt<64>(0h0) connect _debug_jals_WIRE[4], UInt<64>(0h0) regreset debug_jals : UInt<64>[5], clock, reset, _debug_jals_WIRE wire _debug_jalrs_WIRE : UInt<64>[5] connect _debug_jalrs_WIRE[0], UInt<64>(0h0) connect _debug_jalrs_WIRE[1], UInt<64>(0h0) connect _debug_jalrs_WIRE[2], UInt<64>(0h0) connect _debug_jalrs_WIRE[3], UInt<64>(0h0) connect _debug_jalrs_WIRE[4], UInt<64>(0h0) regreset debug_jalrs : UInt<64>[5], clock, reset, _debug_jalrs_WIRE node _debug_brs_0_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h0)) node _debug_brs_0_T_1 = and(rob.io.commit.arch_valids[0], _debug_brs_0_T) node _debug_brs_0_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h1)) node _debug_brs_0_T_3 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h2)) node _debug_brs_0_T_4 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h3)) node _debug_brs_0_T_5 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h4)) node _debug_brs_0_T_6 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h5)) node _debug_brs_0_T_7 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h6)) node _debug_brs_0_T_8 = or(_debug_brs_0_T_2, _debug_brs_0_T_3) node _debug_brs_0_T_9 = or(_debug_brs_0_T_8, _debug_brs_0_T_4) node _debug_brs_0_T_10 = or(_debug_brs_0_T_9, _debug_brs_0_T_5) node _debug_brs_0_T_11 = or(_debug_brs_0_T_10, _debug_brs_0_T_6) node _debug_brs_0_T_12 = or(_debug_brs_0_T_11, _debug_brs_0_T_7) node _debug_brs_0_T_13 = and(_debug_brs_0_T_1, _debug_brs_0_T_12) node _debug_brs_0_T_14 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h0)) node _debug_brs_0_T_15 = and(rob.io.commit.arch_valids[1], _debug_brs_0_T_14) node _debug_brs_0_T_16 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h1)) node _debug_brs_0_T_17 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h2)) node _debug_brs_0_T_18 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h3)) node _debug_brs_0_T_19 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h4)) node _debug_brs_0_T_20 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h5)) node _debug_brs_0_T_21 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h6)) node _debug_brs_0_T_22 = or(_debug_brs_0_T_16, _debug_brs_0_T_17) node _debug_brs_0_T_23 = or(_debug_brs_0_T_22, _debug_brs_0_T_18) node _debug_brs_0_T_24 = or(_debug_brs_0_T_23, _debug_brs_0_T_19) node _debug_brs_0_T_25 = or(_debug_brs_0_T_24, _debug_brs_0_T_20) node _debug_brs_0_T_26 = or(_debug_brs_0_T_25, _debug_brs_0_T_21) node _debug_brs_0_T_27 = and(_debug_brs_0_T_15, _debug_brs_0_T_26) wire _debug_brs_0_WIRE : UInt<1>[2] connect _debug_brs_0_WIRE[0], _debug_brs_0_T_13 connect _debug_brs_0_WIRE[1], _debug_brs_0_T_27 node _debug_brs_0_T_28 = add(_debug_brs_0_WIRE[0], _debug_brs_0_WIRE[1]) node _debug_brs_0_T_29 = bits(_debug_brs_0_T_28, 1, 0) node _debug_brs_0_T_30 = add(debug_brs[0], _debug_brs_0_T_29) node _debug_brs_0_T_31 = tail(_debug_brs_0_T_30, 1) connect debug_brs[0], _debug_brs_0_T_31 node _debug_jals_0_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h0)) node _debug_jals_0_T_1 = and(rob.io.commit.arch_valids[0], _debug_jals_0_T) node _debug_jals_0_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h7)) node _debug_jals_0_T_3 = and(_debug_jals_0_T_1, _debug_jals_0_T_2) node _debug_jals_0_T_4 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h0)) node _debug_jals_0_T_5 = and(rob.io.commit.arch_valids[1], _debug_jals_0_T_4) node _debug_jals_0_T_6 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h7)) node _debug_jals_0_T_7 = and(_debug_jals_0_T_5, _debug_jals_0_T_6) wire _debug_jals_0_WIRE : UInt<1>[2] connect _debug_jals_0_WIRE[0], _debug_jals_0_T_3 connect _debug_jals_0_WIRE[1], _debug_jals_0_T_7 node _debug_jals_0_T_8 = add(_debug_jals_0_WIRE[0], _debug_jals_0_WIRE[1]) node _debug_jals_0_T_9 = bits(_debug_jals_0_T_8, 1, 0) node _debug_jals_0_T_10 = add(debug_jals[0], _debug_jals_0_T_9) node _debug_jals_0_T_11 = tail(_debug_jals_0_T_10, 1) connect debug_jals[0], _debug_jals_0_T_11 node _debug_jalrs_0_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h0)) node _debug_jalrs_0_T_1 = and(rob.io.commit.arch_valids[0], _debug_jalrs_0_T) node _debug_jalrs_0_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h8)) node _debug_jalrs_0_T_3 = and(_debug_jalrs_0_T_1, _debug_jalrs_0_T_2) node _debug_jalrs_0_T_4 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h0)) node _debug_jalrs_0_T_5 = and(rob.io.commit.arch_valids[1], _debug_jalrs_0_T_4) node _debug_jalrs_0_T_6 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h8)) node _debug_jalrs_0_T_7 = and(_debug_jalrs_0_T_5, _debug_jalrs_0_T_6) wire _debug_jalrs_0_WIRE : UInt<1>[2] connect _debug_jalrs_0_WIRE[0], _debug_jalrs_0_T_3 connect _debug_jalrs_0_WIRE[1], _debug_jalrs_0_T_7 node _debug_jalrs_0_T_8 = add(_debug_jalrs_0_WIRE[0], _debug_jalrs_0_WIRE[1]) node _debug_jalrs_0_T_9 = bits(_debug_jalrs_0_T_8, 1, 0) node _debug_jalrs_0_T_10 = add(debug_jalrs[0], _debug_jalrs_0_T_9) node _debug_jalrs_0_T_11 = tail(_debug_jalrs_0_T_10, 1) connect debug_jalrs[0], _debug_jalrs_0_T_11 node _debug_brs_1_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h1)) node _debug_brs_1_T_1 = and(rob.io.commit.arch_valids[0], _debug_brs_1_T) node _debug_brs_1_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h1)) node _debug_brs_1_T_3 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h2)) node _debug_brs_1_T_4 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h3)) node _debug_brs_1_T_5 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h4)) node _debug_brs_1_T_6 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h5)) node _debug_brs_1_T_7 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h6)) node _debug_brs_1_T_8 = or(_debug_brs_1_T_2, _debug_brs_1_T_3) node _debug_brs_1_T_9 = or(_debug_brs_1_T_8, _debug_brs_1_T_4) node _debug_brs_1_T_10 = or(_debug_brs_1_T_9, _debug_brs_1_T_5) node _debug_brs_1_T_11 = or(_debug_brs_1_T_10, _debug_brs_1_T_6) node _debug_brs_1_T_12 = or(_debug_brs_1_T_11, _debug_brs_1_T_7) node _debug_brs_1_T_13 = and(_debug_brs_1_T_1, _debug_brs_1_T_12) node _debug_brs_1_T_14 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h1)) node _debug_brs_1_T_15 = and(rob.io.commit.arch_valids[1], _debug_brs_1_T_14) node _debug_brs_1_T_16 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h1)) node _debug_brs_1_T_17 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h2)) node _debug_brs_1_T_18 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h3)) node _debug_brs_1_T_19 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h4)) node _debug_brs_1_T_20 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h5)) node _debug_brs_1_T_21 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h6)) node _debug_brs_1_T_22 = or(_debug_brs_1_T_16, _debug_brs_1_T_17) node _debug_brs_1_T_23 = or(_debug_brs_1_T_22, _debug_brs_1_T_18) node _debug_brs_1_T_24 = or(_debug_brs_1_T_23, _debug_brs_1_T_19) node _debug_brs_1_T_25 = or(_debug_brs_1_T_24, _debug_brs_1_T_20) node _debug_brs_1_T_26 = or(_debug_brs_1_T_25, _debug_brs_1_T_21) node _debug_brs_1_T_27 = and(_debug_brs_1_T_15, _debug_brs_1_T_26) wire _debug_brs_1_WIRE : UInt<1>[2] connect _debug_brs_1_WIRE[0], _debug_brs_1_T_13 connect _debug_brs_1_WIRE[1], _debug_brs_1_T_27 node _debug_brs_1_T_28 = add(_debug_brs_1_WIRE[0], _debug_brs_1_WIRE[1]) node _debug_brs_1_T_29 = bits(_debug_brs_1_T_28, 1, 0) node _debug_brs_1_T_30 = add(debug_brs[1], _debug_brs_1_T_29) node _debug_brs_1_T_31 = tail(_debug_brs_1_T_30, 1) connect debug_brs[1], _debug_brs_1_T_31 node _debug_jals_1_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h1)) node _debug_jals_1_T_1 = and(rob.io.commit.arch_valids[0], _debug_jals_1_T) node _debug_jals_1_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h7)) node _debug_jals_1_T_3 = and(_debug_jals_1_T_1, _debug_jals_1_T_2) node _debug_jals_1_T_4 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h1)) node _debug_jals_1_T_5 = and(rob.io.commit.arch_valids[1], _debug_jals_1_T_4) node _debug_jals_1_T_6 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h7)) node _debug_jals_1_T_7 = and(_debug_jals_1_T_5, _debug_jals_1_T_6) wire _debug_jals_1_WIRE : UInt<1>[2] connect _debug_jals_1_WIRE[0], _debug_jals_1_T_3 connect _debug_jals_1_WIRE[1], _debug_jals_1_T_7 node _debug_jals_1_T_8 = add(_debug_jals_1_WIRE[0], _debug_jals_1_WIRE[1]) node _debug_jals_1_T_9 = bits(_debug_jals_1_T_8, 1, 0) node _debug_jals_1_T_10 = add(debug_jals[1], _debug_jals_1_T_9) node _debug_jals_1_T_11 = tail(_debug_jals_1_T_10, 1) connect debug_jals[1], _debug_jals_1_T_11 node _debug_jalrs_1_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<1>(0h1)) node _debug_jalrs_1_T_1 = and(rob.io.commit.arch_valids[0], _debug_jalrs_1_T) node _debug_jalrs_1_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h8)) node _debug_jalrs_1_T_3 = and(_debug_jalrs_1_T_1, _debug_jalrs_1_T_2) node _debug_jalrs_1_T_4 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<1>(0h1)) node _debug_jalrs_1_T_5 = and(rob.io.commit.arch_valids[1], _debug_jalrs_1_T_4) node _debug_jalrs_1_T_6 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h8)) node _debug_jalrs_1_T_7 = and(_debug_jalrs_1_T_5, _debug_jalrs_1_T_6) wire _debug_jalrs_1_WIRE : UInt<1>[2] connect _debug_jalrs_1_WIRE[0], _debug_jalrs_1_T_3 connect _debug_jalrs_1_WIRE[1], _debug_jalrs_1_T_7 node _debug_jalrs_1_T_8 = add(_debug_jalrs_1_WIRE[0], _debug_jalrs_1_WIRE[1]) node _debug_jalrs_1_T_9 = bits(_debug_jalrs_1_T_8, 1, 0) node _debug_jalrs_1_T_10 = add(debug_jalrs[1], _debug_jalrs_1_T_9) node _debug_jalrs_1_T_11 = tail(_debug_jalrs_1_T_10, 1) connect debug_jalrs[1], _debug_jalrs_1_T_11 node _debug_brs_2_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h2)) node _debug_brs_2_T_1 = and(rob.io.commit.arch_valids[0], _debug_brs_2_T) node _debug_brs_2_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h1)) node _debug_brs_2_T_3 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h2)) node _debug_brs_2_T_4 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h3)) node _debug_brs_2_T_5 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h4)) node _debug_brs_2_T_6 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h5)) node _debug_brs_2_T_7 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h6)) node _debug_brs_2_T_8 = or(_debug_brs_2_T_2, _debug_brs_2_T_3) node _debug_brs_2_T_9 = or(_debug_brs_2_T_8, _debug_brs_2_T_4) node _debug_brs_2_T_10 = or(_debug_brs_2_T_9, _debug_brs_2_T_5) node _debug_brs_2_T_11 = or(_debug_brs_2_T_10, _debug_brs_2_T_6) node _debug_brs_2_T_12 = or(_debug_brs_2_T_11, _debug_brs_2_T_7) node _debug_brs_2_T_13 = and(_debug_brs_2_T_1, _debug_brs_2_T_12) node _debug_brs_2_T_14 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h2)) node _debug_brs_2_T_15 = and(rob.io.commit.arch_valids[1], _debug_brs_2_T_14) node _debug_brs_2_T_16 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h1)) node _debug_brs_2_T_17 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h2)) node _debug_brs_2_T_18 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h3)) node _debug_brs_2_T_19 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h4)) node _debug_brs_2_T_20 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h5)) node _debug_brs_2_T_21 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h6)) node _debug_brs_2_T_22 = or(_debug_brs_2_T_16, _debug_brs_2_T_17) node _debug_brs_2_T_23 = or(_debug_brs_2_T_22, _debug_brs_2_T_18) node _debug_brs_2_T_24 = or(_debug_brs_2_T_23, _debug_brs_2_T_19) node _debug_brs_2_T_25 = or(_debug_brs_2_T_24, _debug_brs_2_T_20) node _debug_brs_2_T_26 = or(_debug_brs_2_T_25, _debug_brs_2_T_21) node _debug_brs_2_T_27 = and(_debug_brs_2_T_15, _debug_brs_2_T_26) wire _debug_brs_2_WIRE : UInt<1>[2] connect _debug_brs_2_WIRE[0], _debug_brs_2_T_13 connect _debug_brs_2_WIRE[1], _debug_brs_2_T_27 node _debug_brs_2_T_28 = add(_debug_brs_2_WIRE[0], _debug_brs_2_WIRE[1]) node _debug_brs_2_T_29 = bits(_debug_brs_2_T_28, 1, 0) node _debug_brs_2_T_30 = add(debug_brs[2], _debug_brs_2_T_29) node _debug_brs_2_T_31 = tail(_debug_brs_2_T_30, 1) connect debug_brs[2], _debug_brs_2_T_31 node _debug_jals_2_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h2)) node _debug_jals_2_T_1 = and(rob.io.commit.arch_valids[0], _debug_jals_2_T) node _debug_jals_2_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h7)) node _debug_jals_2_T_3 = and(_debug_jals_2_T_1, _debug_jals_2_T_2) node _debug_jals_2_T_4 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h2)) node _debug_jals_2_T_5 = and(rob.io.commit.arch_valids[1], _debug_jals_2_T_4) node _debug_jals_2_T_6 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h7)) node _debug_jals_2_T_7 = and(_debug_jals_2_T_5, _debug_jals_2_T_6) wire _debug_jals_2_WIRE : UInt<1>[2] connect _debug_jals_2_WIRE[0], _debug_jals_2_T_3 connect _debug_jals_2_WIRE[1], _debug_jals_2_T_7 node _debug_jals_2_T_8 = add(_debug_jals_2_WIRE[0], _debug_jals_2_WIRE[1]) node _debug_jals_2_T_9 = bits(_debug_jals_2_T_8, 1, 0) node _debug_jals_2_T_10 = add(debug_jals[2], _debug_jals_2_T_9) node _debug_jals_2_T_11 = tail(_debug_jals_2_T_10, 1) connect debug_jals[2], _debug_jals_2_T_11 node _debug_jalrs_2_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h2)) node _debug_jalrs_2_T_1 = and(rob.io.commit.arch_valids[0], _debug_jalrs_2_T) node _debug_jalrs_2_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h8)) node _debug_jalrs_2_T_3 = and(_debug_jalrs_2_T_1, _debug_jalrs_2_T_2) node _debug_jalrs_2_T_4 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h2)) node _debug_jalrs_2_T_5 = and(rob.io.commit.arch_valids[1], _debug_jalrs_2_T_4) node _debug_jalrs_2_T_6 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h8)) node _debug_jalrs_2_T_7 = and(_debug_jalrs_2_T_5, _debug_jalrs_2_T_6) wire _debug_jalrs_2_WIRE : UInt<1>[2] connect _debug_jalrs_2_WIRE[0], _debug_jalrs_2_T_3 connect _debug_jalrs_2_WIRE[1], _debug_jalrs_2_T_7 node _debug_jalrs_2_T_8 = add(_debug_jalrs_2_WIRE[0], _debug_jalrs_2_WIRE[1]) node _debug_jalrs_2_T_9 = bits(_debug_jalrs_2_T_8, 1, 0) node _debug_jalrs_2_T_10 = add(debug_jalrs[2], _debug_jalrs_2_T_9) node _debug_jalrs_2_T_11 = tail(_debug_jalrs_2_T_10, 1) connect debug_jalrs[2], _debug_jalrs_2_T_11 node _debug_brs_3_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h3)) node _debug_brs_3_T_1 = and(rob.io.commit.arch_valids[0], _debug_brs_3_T) node _debug_brs_3_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h1)) node _debug_brs_3_T_3 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h2)) node _debug_brs_3_T_4 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h3)) node _debug_brs_3_T_5 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h4)) node _debug_brs_3_T_6 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h5)) node _debug_brs_3_T_7 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h6)) node _debug_brs_3_T_8 = or(_debug_brs_3_T_2, _debug_brs_3_T_3) node _debug_brs_3_T_9 = or(_debug_brs_3_T_8, _debug_brs_3_T_4) node _debug_brs_3_T_10 = or(_debug_brs_3_T_9, _debug_brs_3_T_5) node _debug_brs_3_T_11 = or(_debug_brs_3_T_10, _debug_brs_3_T_6) node _debug_brs_3_T_12 = or(_debug_brs_3_T_11, _debug_brs_3_T_7) node _debug_brs_3_T_13 = and(_debug_brs_3_T_1, _debug_brs_3_T_12) node _debug_brs_3_T_14 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h3)) node _debug_brs_3_T_15 = and(rob.io.commit.arch_valids[1], _debug_brs_3_T_14) node _debug_brs_3_T_16 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h1)) node _debug_brs_3_T_17 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h2)) node _debug_brs_3_T_18 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h3)) node _debug_brs_3_T_19 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h4)) node _debug_brs_3_T_20 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h5)) node _debug_brs_3_T_21 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h6)) node _debug_brs_3_T_22 = or(_debug_brs_3_T_16, _debug_brs_3_T_17) node _debug_brs_3_T_23 = or(_debug_brs_3_T_22, _debug_brs_3_T_18) node _debug_brs_3_T_24 = or(_debug_brs_3_T_23, _debug_brs_3_T_19) node _debug_brs_3_T_25 = or(_debug_brs_3_T_24, _debug_brs_3_T_20) node _debug_brs_3_T_26 = or(_debug_brs_3_T_25, _debug_brs_3_T_21) node _debug_brs_3_T_27 = and(_debug_brs_3_T_15, _debug_brs_3_T_26) wire _debug_brs_3_WIRE : UInt<1>[2] connect _debug_brs_3_WIRE[0], _debug_brs_3_T_13 connect _debug_brs_3_WIRE[1], _debug_brs_3_T_27 node _debug_brs_3_T_28 = add(_debug_brs_3_WIRE[0], _debug_brs_3_WIRE[1]) node _debug_brs_3_T_29 = bits(_debug_brs_3_T_28, 1, 0) node _debug_brs_3_T_30 = add(debug_brs[3], _debug_brs_3_T_29) node _debug_brs_3_T_31 = tail(_debug_brs_3_T_30, 1) connect debug_brs[3], _debug_brs_3_T_31 node _debug_jals_3_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h3)) node _debug_jals_3_T_1 = and(rob.io.commit.arch_valids[0], _debug_jals_3_T) node _debug_jals_3_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h7)) node _debug_jals_3_T_3 = and(_debug_jals_3_T_1, _debug_jals_3_T_2) node _debug_jals_3_T_4 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h3)) node _debug_jals_3_T_5 = and(rob.io.commit.arch_valids[1], _debug_jals_3_T_4) node _debug_jals_3_T_6 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h7)) node _debug_jals_3_T_7 = and(_debug_jals_3_T_5, _debug_jals_3_T_6) wire _debug_jals_3_WIRE : UInt<1>[2] connect _debug_jals_3_WIRE[0], _debug_jals_3_T_3 connect _debug_jals_3_WIRE[1], _debug_jals_3_T_7 node _debug_jals_3_T_8 = add(_debug_jals_3_WIRE[0], _debug_jals_3_WIRE[1]) node _debug_jals_3_T_9 = bits(_debug_jals_3_T_8, 1, 0) node _debug_jals_3_T_10 = add(debug_jals[3], _debug_jals_3_T_9) node _debug_jals_3_T_11 = tail(_debug_jals_3_T_10, 1) connect debug_jals[3], _debug_jals_3_T_11 node _debug_jalrs_3_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<2>(0h3)) node _debug_jalrs_3_T_1 = and(rob.io.commit.arch_valids[0], _debug_jalrs_3_T) node _debug_jalrs_3_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h8)) node _debug_jalrs_3_T_3 = and(_debug_jalrs_3_T_1, _debug_jalrs_3_T_2) node _debug_jalrs_3_T_4 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<2>(0h3)) node _debug_jalrs_3_T_5 = and(rob.io.commit.arch_valids[1], _debug_jalrs_3_T_4) node _debug_jalrs_3_T_6 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h8)) node _debug_jalrs_3_T_7 = and(_debug_jalrs_3_T_5, _debug_jalrs_3_T_6) wire _debug_jalrs_3_WIRE : UInt<1>[2] connect _debug_jalrs_3_WIRE[0], _debug_jalrs_3_T_3 connect _debug_jalrs_3_WIRE[1], _debug_jalrs_3_T_7 node _debug_jalrs_3_T_8 = add(_debug_jalrs_3_WIRE[0], _debug_jalrs_3_WIRE[1]) node _debug_jalrs_3_T_9 = bits(_debug_jalrs_3_T_8, 1, 0) node _debug_jalrs_3_T_10 = add(debug_jalrs[3], _debug_jalrs_3_T_9) node _debug_jalrs_3_T_11 = tail(_debug_jalrs_3_T_10, 1) connect debug_jalrs[3], _debug_jalrs_3_T_11 node _debug_brs_4_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<3>(0h4)) node _debug_brs_4_T_1 = and(rob.io.commit.arch_valids[0], _debug_brs_4_T) node _debug_brs_4_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h1)) node _debug_brs_4_T_3 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h2)) node _debug_brs_4_T_4 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h3)) node _debug_brs_4_T_5 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h4)) node _debug_brs_4_T_6 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h5)) node _debug_brs_4_T_7 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h6)) node _debug_brs_4_T_8 = or(_debug_brs_4_T_2, _debug_brs_4_T_3) node _debug_brs_4_T_9 = or(_debug_brs_4_T_8, _debug_brs_4_T_4) node _debug_brs_4_T_10 = or(_debug_brs_4_T_9, _debug_brs_4_T_5) node _debug_brs_4_T_11 = or(_debug_brs_4_T_10, _debug_brs_4_T_6) node _debug_brs_4_T_12 = or(_debug_brs_4_T_11, _debug_brs_4_T_7) node _debug_brs_4_T_13 = and(_debug_brs_4_T_1, _debug_brs_4_T_12) node _debug_brs_4_T_14 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<3>(0h4)) node _debug_brs_4_T_15 = and(rob.io.commit.arch_valids[1], _debug_brs_4_T_14) node _debug_brs_4_T_16 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h1)) node _debug_brs_4_T_17 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h2)) node _debug_brs_4_T_18 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h3)) node _debug_brs_4_T_19 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h4)) node _debug_brs_4_T_20 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h5)) node _debug_brs_4_T_21 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h6)) node _debug_brs_4_T_22 = or(_debug_brs_4_T_16, _debug_brs_4_T_17) node _debug_brs_4_T_23 = or(_debug_brs_4_T_22, _debug_brs_4_T_18) node _debug_brs_4_T_24 = or(_debug_brs_4_T_23, _debug_brs_4_T_19) node _debug_brs_4_T_25 = or(_debug_brs_4_T_24, _debug_brs_4_T_20) node _debug_brs_4_T_26 = or(_debug_brs_4_T_25, _debug_brs_4_T_21) node _debug_brs_4_T_27 = and(_debug_brs_4_T_15, _debug_brs_4_T_26) wire _debug_brs_4_WIRE : UInt<1>[2] connect _debug_brs_4_WIRE[0], _debug_brs_4_T_13 connect _debug_brs_4_WIRE[1], _debug_brs_4_T_27 node _debug_brs_4_T_28 = add(_debug_brs_4_WIRE[0], _debug_brs_4_WIRE[1]) node _debug_brs_4_T_29 = bits(_debug_brs_4_T_28, 1, 0) node _debug_brs_4_T_30 = add(debug_brs[4], _debug_brs_4_T_29) node _debug_brs_4_T_31 = tail(_debug_brs_4_T_30, 1) connect debug_brs[4], _debug_brs_4_T_31 node _debug_jals_4_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<3>(0h4)) node _debug_jals_4_T_1 = and(rob.io.commit.arch_valids[0], _debug_jals_4_T) node _debug_jals_4_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h7)) node _debug_jals_4_T_3 = and(_debug_jals_4_T_1, _debug_jals_4_T_2) node _debug_jals_4_T_4 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<3>(0h4)) node _debug_jals_4_T_5 = and(rob.io.commit.arch_valids[1], _debug_jals_4_T_4) node _debug_jals_4_T_6 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h7)) node _debug_jals_4_T_7 = and(_debug_jals_4_T_5, _debug_jals_4_T_6) wire _debug_jals_4_WIRE : UInt<1>[2] connect _debug_jals_4_WIRE[0], _debug_jals_4_T_3 connect _debug_jals_4_WIRE[1], _debug_jals_4_T_7 node _debug_jals_4_T_8 = add(_debug_jals_4_WIRE[0], _debug_jals_4_WIRE[1]) node _debug_jals_4_T_9 = bits(_debug_jals_4_T_8, 1, 0) node _debug_jals_4_T_10 = add(debug_jals[4], _debug_jals_4_T_9) node _debug_jals_4_T_11 = tail(_debug_jals_4_T_10, 1) connect debug_jals[4], _debug_jals_4_T_11 node _debug_jalrs_4_T = eq(rob.io.commit.uops[0].debug_fsrc, UInt<3>(0h4)) node _debug_jalrs_4_T_1 = and(rob.io.commit.arch_valids[0], _debug_jalrs_4_T) node _debug_jalrs_4_T_2 = eq(rob.io.commit.uops[0].br_type, UInt<4>(0h8)) node _debug_jalrs_4_T_3 = and(_debug_jalrs_4_T_1, _debug_jalrs_4_T_2) node _debug_jalrs_4_T_4 = eq(rob.io.commit.uops[1].debug_fsrc, UInt<3>(0h4)) node _debug_jalrs_4_T_5 = and(rob.io.commit.arch_valids[1], _debug_jalrs_4_T_4) node _debug_jalrs_4_T_6 = eq(rob.io.commit.uops[1].br_type, UInt<4>(0h8)) node _debug_jalrs_4_T_7 = and(_debug_jalrs_4_T_5, _debug_jalrs_4_T_6) wire _debug_jalrs_4_WIRE : UInt<1>[2] connect _debug_jalrs_4_WIRE[0], _debug_jalrs_4_T_3 connect _debug_jalrs_4_WIRE[1], _debug_jalrs_4_T_7 node _debug_jalrs_4_T_8 = add(_debug_jalrs_4_WIRE[0], _debug_jalrs_4_WIRE[1]) node _debug_jalrs_4_T_9 = bits(_debug_jalrs_4_T_8, 1, 0) node _debug_jalrs_4_T_10 = add(debug_jalrs[4], _debug_jalrs_4_T_9) node _debug_jalrs_4_T_11 = tail(_debug_jalrs_4_T_10, 1) connect debug_jalrs[4], _debug_jalrs_4_T_11 node _debug_tsc_reg_T = add(debug_tsc_reg, UInt<1>(0h1)) node _debug_tsc_reg_T_1 = tail(_debug_tsc_reg_T, 1) connect debug_tsc_reg, _debug_tsc_reg_T_1 node _debug_irt_reg_T = cat(rob.io.commit.arch_valids[1], rob.io.commit.arch_valids[0]) node _debug_irt_reg_T_1 = bits(_debug_irt_reg_T, 0, 0) node _debug_irt_reg_T_2 = bits(_debug_irt_reg_T, 1, 1) node _debug_irt_reg_T_3 = add(_debug_irt_reg_T_1, _debug_irt_reg_T_2) node _debug_irt_reg_T_4 = bits(_debug_irt_reg_T_3, 1, 0) node _debug_irt_reg_T_5 = add(debug_irt_reg, _debug_irt_reg_T_4) node _debug_irt_reg_T_6 = tail(_debug_irt_reg_T_5, 1) connect debug_irt_reg, _debug_irt_reg_T_6 connect io.ifu.redirect_val, UInt<1>(0h0) connect io.ifu.redirect_flush, UInt<1>(0h0) connect io.ifu.status, csr.io.status connect io.ifu.bp, csr.io.bp connect io.ifu.mcontext, csr.io.mcontext connect io.ifu.scontext, csr.io.scontext node _io_ifu_flush_icache_T = and(rob.io.commit.arch_valids[0], rob.io.commit.uops[0].is_fencei) node _io_ifu_flush_icache_T_1 = eq(dec_uops[0].br_type, UInt<4>(0h8)) node _io_ifu_flush_icache_T_2 = and(dec_valids[0], _io_ifu_flush_icache_T_1) node _io_ifu_flush_icache_T_3 = and(_io_ifu_flush_icache_T_2, csr.io.status.debug) reg io_ifu_flush_icache_REG : UInt<1>, clock connect io_ifu_flush_icache_REG, _io_ifu_flush_icache_T_3 node _io_ifu_flush_icache_T_4 = or(_io_ifu_flush_icache_T, io_ifu_flush_icache_REG) node _io_ifu_flush_icache_T_5 = and(rob.io.commit.arch_valids[1], rob.io.commit.uops[1].is_fencei) node _io_ifu_flush_icache_T_6 = eq(dec_uops[1].br_type, UInt<4>(0h8)) node _io_ifu_flush_icache_T_7 = and(dec_valids[1], _io_ifu_flush_icache_T_6) node _io_ifu_flush_icache_T_8 = and(_io_ifu_flush_icache_T_7, csr.io.status.debug) reg io_ifu_flush_icache_REG_1 : UInt<1>, clock connect io_ifu_flush_icache_REG_1, _io_ifu_flush_icache_T_8 node _io_ifu_flush_icache_T_9 = or(_io_ifu_flush_icache_T_5, io_ifu_flush_icache_REG_1) node _io_ifu_flush_icache_T_10 = or(_io_ifu_flush_icache_T_4, _io_ifu_flush_icache_T_9) connect io.ifu.flush_icache, _io_ifu_flush_icache_T_10 reg REG : UInt<1>, clock connect REG, rob.io.flush.valid when REG : connect io.ifu.redirect_val, UInt<1>(0h1) connect io.ifu.redirect_flush, UInt<1>(0h1) reg flush_typ : UInt, clock connect flush_typ, rob.io.flush.bits.flush_typ wire _new_ghist_WIRE : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect _new_ghist_WIRE.ras_idx, UInt<5>(0h0) connect _new_ghist_WIRE.new_saw_branch_taken, UInt<1>(0h0) connect _new_ghist_WIRE.new_saw_branch_not_taken, UInt<1>(0h0) connect _new_ghist_WIRE.current_saw_branch_not_taken, UInt<1>(0h0) connect _new_ghist_WIRE.old_history, UInt<64>(0h0) wire new_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} connect new_ghist, _new_ghist_WIRE connect new_ghist.current_saw_branch_not_taken, UInt<1>(0h1) connect new_ghist.ras_idx, io.ifu.rrd_ftq_resps[0].entry.ras_idx connect io.ifu.redirect_ghist, new_ghist node _T_13 = bits(flush_typ, 0, 0) when _T_13 : node _io_ifu_redirect_pc_T = eq(flush_typ, UInt<2>(0h3)) reg io_ifu_redirect_pc_r : UInt<40>, clock when UInt<1>(0h1) : connect io_ifu_redirect_pc_r, csr.io.evec reg io_ifu_redirect_pc_r_1 : UInt<40>, clock when UInt<1>(0h1) : connect io_ifu_redirect_pc_r_1, io_ifu_redirect_pc_r reg io_ifu_redirect_pc_r_2 : UInt<40>, clock when UInt<1>(0h1) : connect io_ifu_redirect_pc_r_2, io_ifu_redirect_pc_r_1 node _io_ifu_redirect_pc_T_1 = mux(_io_ifu_redirect_pc_T, io_ifu_redirect_pc_r_2, csr.io.evec) connect io.ifu.redirect_pc, _io_ifu_redirect_pc_T_1 else : node _flush_pc_T = not(io.ifu.rrd_ftq_resps[0].pc) node _flush_pc_T_1 = or(_flush_pc_T, UInt<6>(0h3f)) node _flush_pc_T_2 = not(_flush_pc_T_1) reg flush_pc_REG : UInt, clock connect flush_pc_REG, rob.io.flush.bits.pc_lob node _flush_pc_T_3 = add(_flush_pc_T_2, flush_pc_REG) node _flush_pc_T_4 = tail(_flush_pc_T_3, 1) reg flush_pc_REG_1 : UInt<1>, clock connect flush_pc_REG_1, rob.io.flush.bits.edge_inst node _flush_pc_T_5 = mux(flush_pc_REG_1, UInt<2>(0h2), UInt<1>(0h0)) node _flush_pc_T_6 = sub(_flush_pc_T_4, _flush_pc_T_5) node flush_pc = tail(_flush_pc_T_6, 1) reg flush_pc_next_REG : UInt<1>, clock connect flush_pc_next_REG, rob.io.flush.bits.is_rvc node _flush_pc_next_T = mux(flush_pc_next_REG, UInt<2>(0h2), UInt<3>(0h4)) node _flush_pc_next_T_1 = add(flush_pc, _flush_pc_next_T) node flush_pc_next = tail(_flush_pc_next_T_1, 1) node _io_ifu_redirect_pc_T_2 = eq(flush_typ, UInt<2>(0h2)) node _io_ifu_redirect_pc_T_3 = mux(_io_ifu_redirect_pc_T_2, flush_pc, flush_pc_next) connect io.ifu.redirect_pc, _io_ifu_redirect_pc_T_3 reg io_ifu_redirect_ftq_idx_REG : UInt, clock connect io_ifu_redirect_ftq_idx_REG, rob.io.flush.bits.ftq_idx connect io.ifu.redirect_ftq_idx, io_ifu_redirect_ftq_idx_REG else : reg REG_1 : UInt<1>, clock connect REG_1, rob.io.flush.valid node _T_14 = eq(REG_1, UInt<1>(0h0)) node _T_15 = and(brupdate.b2.mispredict, _T_14) when _T_15 : node _block_pc_T = not(io.ifu.rrd_ftq_resps[0].pc) node _block_pc_T_1 = or(_block_pc_T, UInt<6>(0h3f)) node block_pc = not(_block_pc_T_1) node uop_maybe_pc = or(block_pc, brupdate.b2.uop.pc_lob) node _npc_T = or(brupdate.b2.uop.is_rvc, brupdate.b2.uop.edge_inst) node _npc_T_1 = mux(_npc_T, UInt<2>(0h2), UInt<3>(0h4)) node _npc_T_2 = add(uop_maybe_pc, _npc_T_1) node npc = tail(_npc_T_2, 1) wire jal_br_target : UInt<40> node _jal_br_target_T = asSInt(uop_maybe_pc) node _jal_br_target_T_1 = add(_jal_br_target_T, brupdate.b2.target_offset) node _jal_br_target_T_2 = tail(_jal_br_target_T_1, 1) node _jal_br_target_T_3 = asSInt(_jal_br_target_T_2) node _jal_br_target_T_4 = mux(brupdate.b2.uop.edge_inst, UInt<39>(0h7fffffffff), UInt<39>(0h0)) node _jal_br_target_T_5 = shl(_jal_br_target_T_4, 1) node _jal_br_target_T_6 = asSInt(_jal_br_target_T_5) node _jal_br_target_T_7 = add(_jal_br_target_T_3, _jal_br_target_T_6) node _jal_br_target_T_8 = tail(_jal_br_target_T_7, 1) node _jal_br_target_T_9 = asSInt(_jal_br_target_T_8) node _jal_br_target_T_10 = asUInt(_jal_br_target_T_9) connect jal_br_target, _jal_br_target_T_10 node _bj_addr_T = eq(brupdate.b2.cfi_type, UInt<3>(0h3)) node bj_addr = mux(_bj_addr_T, brupdate.b2.jalr_target, jal_br_target) node _mispredict_target_T = eq(brupdate.b2.pc_sel, UInt<2>(0h0)) node mispredict_target = mux(_mispredict_target_T, npc, bj_addr) connect io.ifu.redirect_val, UInt<1>(0h1) connect io.ifu.redirect_pc, mispredict_target connect io.ifu.redirect_flush, UInt<1>(0h1) connect io.ifu.redirect_ftq_idx, brupdate.b2.uop.ftq_idx node _use_same_ghist_T = eq(brupdate.b2.cfi_type, UInt<3>(0h1)) node _use_same_ghist_T_1 = eq(brupdate.b2.taken, UInt<1>(0h0)) node _use_same_ghist_T_2 = and(_use_same_ghist_T, _use_same_ghist_T_1) node _use_same_ghist_T_3 = not(block_pc) node _use_same_ghist_T_4 = or(_use_same_ghist_T_3, UInt<3>(0h7)) node _use_same_ghist_T_5 = not(_use_same_ghist_T_4) node _use_same_ghist_T_6 = not(npc) node _use_same_ghist_T_7 = or(_use_same_ghist_T_6, UInt<3>(0h7)) node _use_same_ghist_T_8 = not(_use_same_ghist_T_7) node _use_same_ghist_T_9 = eq(_use_same_ghist_T_5, _use_same_ghist_T_8) node use_same_ghist = and(_use_same_ghist_T_2, _use_same_ghist_T_9) node _cfi_idx_T = eq(io.ifu.rrd_ftq_resps[0].entry.start_bank, UInt<1>(0h1)) node _cfi_idx_T_1 = shl(UInt<1>(0h1), 3) node _cfi_idx_T_2 = mux(_cfi_idx_T, _cfi_idx_T_1, UInt<1>(0h0)) node _cfi_idx_T_3 = xor(brupdate.b2.uop.pc_lob, _cfi_idx_T_2) node cfi_idx = bits(_cfi_idx_T_3, 2, 1) node _next_ghist_T = eq(brupdate.b2.cfi_type, UInt<3>(0h1)) node _next_ghist_T_1 = eq(io.ifu.rrd_ftq_resps[0].entry.cfi_idx.bits, cfi_idx) node _next_ghist_T_2 = and(io.ifu.rrd_ftq_resps[0].entry.cfi_is_call, _next_ghist_T_1) node _next_ghist_T_3 = eq(io.ifu.rrd_ftq_resps[0].entry.cfi_idx.bits, cfi_idx) node _next_ghist_T_4 = and(io.ifu.rrd_ftq_resps[0].entry.cfi_is_ret, _next_ghist_T_3) node next_ghist_cfi_idx_fixed = bits(cfi_idx, 1, 0) node next_ghist_cfi_idx_oh = dshl(UInt<1>(0h1), next_ghist_cfi_idx_fixed) wire next_ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>} node _next_ghist_not_taken_branches_T = dshr(next_ghist_cfi_idx_oh, UInt<1>(0h0)) node _next_ghist_not_taken_branches_T_1 = dshr(next_ghist_cfi_idx_oh, UInt<1>(0h1)) node _next_ghist_not_taken_branches_T_2 = dshr(next_ghist_cfi_idx_oh, UInt<2>(0h2)) node _next_ghist_not_taken_branches_T_3 = dshr(next_ghist_cfi_idx_oh, UInt<2>(0h3)) node _next_ghist_not_taken_branches_T_4 = or(_next_ghist_not_taken_branches_T, _next_ghist_not_taken_branches_T_1) node _next_ghist_not_taken_branches_T_5 = or(_next_ghist_not_taken_branches_T_4, _next_ghist_not_taken_branches_T_2) node _next_ghist_not_taken_branches_T_6 = or(_next_ghist_not_taken_branches_T_5, _next_ghist_not_taken_branches_T_3) node _next_ghist_not_taken_branches_T_7 = and(_next_ghist_T, brupdate.b2.taken) node _next_ghist_not_taken_branches_T_8 = mux(_next_ghist_not_taken_branches_T_7, next_ghist_cfi_idx_oh, UInt<4>(0h0)) node _next_ghist_not_taken_branches_T_9 = not(_next_ghist_not_taken_branches_T_8) node _next_ghist_not_taken_branches_T_10 = and(_next_ghist_not_taken_branches_T_6, _next_ghist_not_taken_branches_T_9) node _next_ghist_not_taken_branches_T_11 = not(UInt<4>(0h0)) node _next_ghist_not_taken_branches_T_12 = mux(UInt<1>(0h1), _next_ghist_not_taken_branches_T_10, _next_ghist_not_taken_branches_T_11) node next_ghist_not_taken_branches = and(io.ifu.rrd_ftq_resps[0].entry.br_mask, _next_ghist_not_taken_branches_T_12) invalidate next_ghist.ras_idx invalidate next_ghist.new_saw_branch_taken invalidate next_ghist.new_saw_branch_not_taken invalidate next_ghist.current_saw_branch_not_taken invalidate next_ghist.old_history connect next_ghist.current_saw_branch_not_taken, UInt<1>(0h0) node _next_ghist_saw_not_taken_branch_T = neq(next_ghist_not_taken_branches, UInt<1>(0h0)) node next_ghist_saw_not_taken_branch = or(_next_ghist_saw_not_taken_branch_T, io.ifu.rrd_ftq_resps[0].ghist.current_saw_branch_not_taken) node _next_ghist_new_history_old_history_T = and(_next_ghist_T, brupdate.b2.taken) node _next_ghist_new_history_old_history_T_1 = and(_next_ghist_new_history_old_history_T, UInt<1>(0h1)) node _next_ghist_new_history_old_history_T_2 = shl(io.ifu.rrd_ftq_resps[0].ghist.old_history, 1) node _next_ghist_new_history_old_history_T_3 = or(_next_ghist_new_history_old_history_T_2, UInt<1>(0h1)) node _next_ghist_new_history_old_history_T_4 = shl(io.ifu.rrd_ftq_resps[0].ghist.old_history, 1) node _next_ghist_new_history_old_history_T_5 = mux(next_ghist_saw_not_taken_branch, _next_ghist_new_history_old_history_T_4, io.ifu.rrd_ftq_resps[0].ghist.old_history) node _next_ghist_new_history_old_history_T_6 = mux(_next_ghist_new_history_old_history_T_1, _next_ghist_new_history_old_history_T_3, _next_ghist_new_history_old_history_T_5) connect next_ghist.old_history, _next_ghist_new_history_old_history_T_6 node _next_ghist_new_history_ras_idx_T = and(UInt<1>(0h1), _next_ghist_T_2) node _next_ghist_new_history_ras_idx_T_1 = add(io.ifu.rrd_ftq_resps[0].ghist.ras_idx, UInt<1>(0h1)) node _next_ghist_new_history_ras_idx_T_2 = tail(_next_ghist_new_history_ras_idx_T_1, 1) node _next_ghist_new_history_ras_idx_T_3 = bits(_next_ghist_new_history_ras_idx_T_2, 4, 0) node _next_ghist_new_history_ras_idx_T_4 = and(UInt<1>(0h1), _next_ghist_T_4) node _next_ghist_new_history_ras_idx_T_5 = sub(io.ifu.rrd_ftq_resps[0].ghist.ras_idx, UInt<1>(0h1)) node _next_ghist_new_history_ras_idx_T_6 = tail(_next_ghist_new_history_ras_idx_T_5, 1) node _next_ghist_new_history_ras_idx_T_7 = bits(_next_ghist_new_history_ras_idx_T_6, 4, 0) node _next_ghist_new_history_ras_idx_T_8 = mux(_next_ghist_new_history_ras_idx_T_4, _next_ghist_new_history_ras_idx_T_7, io.ifu.rrd_ftq_resps[0].ghist.ras_idx) node _next_ghist_new_history_ras_idx_T_9 = mux(_next_ghist_new_history_ras_idx_T, _next_ghist_new_history_ras_idx_T_3, _next_ghist_new_history_ras_idx_T_8) connect next_ghist.ras_idx, _next_ghist_new_history_ras_idx_T_9 node _io_ifu_redirect_ghist_T = mux(use_same_ghist, io.ifu.rrd_ftq_resps[0].ghist, next_ghist) connect io.ifu.redirect_ghist, _io_ifu_redirect_ghist_T connect io.ifu.redirect_ghist.current_saw_branch_not_taken, use_same_ghist else : node _T_16 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _T_17 = or(rob.io.flush_frontend, _T_16) when _T_17 : connect io.ifu.redirect_flush, UInt<1>(0h1) node _youngest_com_idx_T = mux(rob.io.commit.valids[1], UInt<1>(0h0), UInt<1>(0h1)) node _youngest_com_idx_T_1 = sub(UInt<1>(0h1), _youngest_com_idx_T) node youngest_com_idx = tail(_youngest_com_idx_T_1, 1) node _io_ifu_commit_valid_T = or(rob.io.commit.valids[0], rob.io.commit.valids[1]) node _io_ifu_commit_valid_T_1 = or(_io_ifu_commit_valid_T, rob.io.com_xcpt.valid) connect io.ifu.commit.valid, _io_ifu_commit_valid_T_1 node _io_ifu_commit_bits_T = mux(rob.io.com_xcpt.valid, rob.io.com_xcpt.bits.ftq_idx, rob.io.commit.uops[youngest_com_idx].ftq_idx) connect io.ifu.commit.bits, _io_ifu_commit_bits_T node _T_18 = or(rob.io.commit.valids[0], rob.io.commit.valids[1]) node _T_19 = and(_T_18, rob.io.com_xcpt.valid) node _T_20 = eq(_T_19, UInt<1>(0h0)) node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : node _T_23 = eq(_T_20, UInt<1>(0h0)) when _T_23 : printf(clock, UInt<1>(0h1), "Assertion failed: ROB can't commit and except in same cycle!\n at core.scala:491 assert(!(rob.io.commit.valids.reduce(_|_) && rob.io.com_xcpt.valid),\n") : printf_2 assert(clock, _T_20, UInt<1>(0h1), "") : assert_2 regreset dec_finished_mask : UInt<2>, clock, reset, UInt<2>(0h0) connect io.ifu.fetchpacket.ready, dec_ready node _dec_valids_0_T = and(io.ifu.fetchpacket.valid, io.ifu.fetchpacket.bits.uops[0].valid) node _dec_valids_0_T_1 = bits(dec_finished_mask, 0, 0) node _dec_valids_0_T_2 = eq(_dec_valids_0_T_1, UInt<1>(0h0)) node _dec_valids_0_T_3 = and(_dec_valids_0_T, _dec_valids_0_T_2) connect dec_valids[0], _dec_valids_0_T_3 connect decode_0.io.enq.uop.debug_tsrc, io.ifu.fetchpacket.bits.uops[0].bits.debug_tsrc connect decode_0.io.enq.uop.debug_fsrc, io.ifu.fetchpacket.bits.uops[0].bits.debug_fsrc connect decode_0.io.enq.uop.bp_xcpt_if, io.ifu.fetchpacket.bits.uops[0].bits.bp_xcpt_if connect decode_0.io.enq.uop.bp_debug_if, io.ifu.fetchpacket.bits.uops[0].bits.bp_debug_if connect decode_0.io.enq.uop.xcpt_ma_if, io.ifu.fetchpacket.bits.uops[0].bits.xcpt_ma_if connect decode_0.io.enq.uop.xcpt_ae_if, io.ifu.fetchpacket.bits.uops[0].bits.xcpt_ae_if connect decode_0.io.enq.uop.xcpt_pf_if, io.ifu.fetchpacket.bits.uops[0].bits.xcpt_pf_if connect decode_0.io.enq.uop.fp_typ, io.ifu.fetchpacket.bits.uops[0].bits.fp_typ connect decode_0.io.enq.uop.fp_rm, io.ifu.fetchpacket.bits.uops[0].bits.fp_rm connect decode_0.io.enq.uop.fp_val, io.ifu.fetchpacket.bits.uops[0].bits.fp_val connect decode_0.io.enq.uop.fcn_op, io.ifu.fetchpacket.bits.uops[0].bits.fcn_op connect decode_0.io.enq.uop.fcn_dw, io.ifu.fetchpacket.bits.uops[0].bits.fcn_dw connect decode_0.io.enq.uop.frs3_en, io.ifu.fetchpacket.bits.uops[0].bits.frs3_en connect decode_0.io.enq.uop.lrs2_rtype, io.ifu.fetchpacket.bits.uops[0].bits.lrs2_rtype connect decode_0.io.enq.uop.lrs1_rtype, io.ifu.fetchpacket.bits.uops[0].bits.lrs1_rtype connect decode_0.io.enq.uop.dst_rtype, io.ifu.fetchpacket.bits.uops[0].bits.dst_rtype connect decode_0.io.enq.uop.lrs3, io.ifu.fetchpacket.bits.uops[0].bits.lrs3 connect decode_0.io.enq.uop.lrs2, io.ifu.fetchpacket.bits.uops[0].bits.lrs2 connect decode_0.io.enq.uop.lrs1, io.ifu.fetchpacket.bits.uops[0].bits.lrs1 connect decode_0.io.enq.uop.ldst, io.ifu.fetchpacket.bits.uops[0].bits.ldst connect decode_0.io.enq.uop.ldst_is_rs1, io.ifu.fetchpacket.bits.uops[0].bits.ldst_is_rs1 connect decode_0.io.enq.uop.csr_cmd, io.ifu.fetchpacket.bits.uops[0].bits.csr_cmd connect decode_0.io.enq.uop.flush_on_commit, io.ifu.fetchpacket.bits.uops[0].bits.flush_on_commit connect decode_0.io.enq.uop.is_unique, io.ifu.fetchpacket.bits.uops[0].bits.is_unique connect decode_0.io.enq.uop.uses_stq, io.ifu.fetchpacket.bits.uops[0].bits.uses_stq connect decode_0.io.enq.uop.uses_ldq, io.ifu.fetchpacket.bits.uops[0].bits.uses_ldq connect decode_0.io.enq.uop.mem_signed, io.ifu.fetchpacket.bits.uops[0].bits.mem_signed connect decode_0.io.enq.uop.mem_size, io.ifu.fetchpacket.bits.uops[0].bits.mem_size connect decode_0.io.enq.uop.mem_cmd, io.ifu.fetchpacket.bits.uops[0].bits.mem_cmd connect decode_0.io.enq.uop.exc_cause, io.ifu.fetchpacket.bits.uops[0].bits.exc_cause connect decode_0.io.enq.uop.exception, io.ifu.fetchpacket.bits.uops[0].bits.exception connect decode_0.io.enq.uop.stale_pdst, io.ifu.fetchpacket.bits.uops[0].bits.stale_pdst connect decode_0.io.enq.uop.ppred_busy, io.ifu.fetchpacket.bits.uops[0].bits.ppred_busy connect decode_0.io.enq.uop.prs3_busy, io.ifu.fetchpacket.bits.uops[0].bits.prs3_busy connect decode_0.io.enq.uop.prs2_busy, io.ifu.fetchpacket.bits.uops[0].bits.prs2_busy connect decode_0.io.enq.uop.prs1_busy, io.ifu.fetchpacket.bits.uops[0].bits.prs1_busy connect decode_0.io.enq.uop.ppred, io.ifu.fetchpacket.bits.uops[0].bits.ppred connect decode_0.io.enq.uop.prs3, io.ifu.fetchpacket.bits.uops[0].bits.prs3 connect decode_0.io.enq.uop.prs2, io.ifu.fetchpacket.bits.uops[0].bits.prs2 connect decode_0.io.enq.uop.prs1, io.ifu.fetchpacket.bits.uops[0].bits.prs1 connect decode_0.io.enq.uop.pdst, io.ifu.fetchpacket.bits.uops[0].bits.pdst connect decode_0.io.enq.uop.rxq_idx, io.ifu.fetchpacket.bits.uops[0].bits.rxq_idx connect decode_0.io.enq.uop.stq_idx, io.ifu.fetchpacket.bits.uops[0].bits.stq_idx connect decode_0.io.enq.uop.ldq_idx, io.ifu.fetchpacket.bits.uops[0].bits.ldq_idx connect decode_0.io.enq.uop.rob_idx, io.ifu.fetchpacket.bits.uops[0].bits.rob_idx connect decode_0.io.enq.uop.fp_ctrl.vec, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.vec connect decode_0.io.enq.uop.fp_ctrl.wflags, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.wflags connect decode_0.io.enq.uop.fp_ctrl.sqrt, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.sqrt connect decode_0.io.enq.uop.fp_ctrl.div, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.div connect decode_0.io.enq.uop.fp_ctrl.fma, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.fma connect decode_0.io.enq.uop.fp_ctrl.fastpipe, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.fastpipe connect decode_0.io.enq.uop.fp_ctrl.toint, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.toint connect decode_0.io.enq.uop.fp_ctrl.fromint, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.fromint connect decode_0.io.enq.uop.fp_ctrl.typeTagOut, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.typeTagOut connect decode_0.io.enq.uop.fp_ctrl.typeTagIn, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.typeTagIn connect decode_0.io.enq.uop.fp_ctrl.swap23, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.swap23 connect decode_0.io.enq.uop.fp_ctrl.swap12, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.swap12 connect decode_0.io.enq.uop.fp_ctrl.ren3, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.ren3 connect decode_0.io.enq.uop.fp_ctrl.ren2, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.ren2 connect decode_0.io.enq.uop.fp_ctrl.ren1, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.ren1 connect decode_0.io.enq.uop.fp_ctrl.wen, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.wen connect decode_0.io.enq.uop.fp_ctrl.ldst, io.ifu.fetchpacket.bits.uops[0].bits.fp_ctrl.ldst connect decode_0.io.enq.uop.op2_sel, io.ifu.fetchpacket.bits.uops[0].bits.op2_sel connect decode_0.io.enq.uop.op1_sel, io.ifu.fetchpacket.bits.uops[0].bits.op1_sel connect decode_0.io.enq.uop.imm_packed, io.ifu.fetchpacket.bits.uops[0].bits.imm_packed connect decode_0.io.enq.uop.pimm, io.ifu.fetchpacket.bits.uops[0].bits.pimm connect decode_0.io.enq.uop.imm_sel, io.ifu.fetchpacket.bits.uops[0].bits.imm_sel connect decode_0.io.enq.uop.imm_rename, io.ifu.fetchpacket.bits.uops[0].bits.imm_rename connect decode_0.io.enq.uop.taken, io.ifu.fetchpacket.bits.uops[0].bits.taken connect decode_0.io.enq.uop.pc_lob, io.ifu.fetchpacket.bits.uops[0].bits.pc_lob connect decode_0.io.enq.uop.edge_inst, io.ifu.fetchpacket.bits.uops[0].bits.edge_inst connect decode_0.io.enq.uop.ftq_idx, io.ifu.fetchpacket.bits.uops[0].bits.ftq_idx connect decode_0.io.enq.uop.is_mov, io.ifu.fetchpacket.bits.uops[0].bits.is_mov connect decode_0.io.enq.uop.is_rocc, io.ifu.fetchpacket.bits.uops[0].bits.is_rocc connect decode_0.io.enq.uop.is_sys_pc2epc, io.ifu.fetchpacket.bits.uops[0].bits.is_sys_pc2epc connect decode_0.io.enq.uop.is_eret, io.ifu.fetchpacket.bits.uops[0].bits.is_eret connect decode_0.io.enq.uop.is_amo, io.ifu.fetchpacket.bits.uops[0].bits.is_amo connect decode_0.io.enq.uop.is_sfence, io.ifu.fetchpacket.bits.uops[0].bits.is_sfence connect decode_0.io.enq.uop.is_fencei, io.ifu.fetchpacket.bits.uops[0].bits.is_fencei connect decode_0.io.enq.uop.is_fence, io.ifu.fetchpacket.bits.uops[0].bits.is_fence connect decode_0.io.enq.uop.is_sfb, io.ifu.fetchpacket.bits.uops[0].bits.is_sfb connect decode_0.io.enq.uop.br_type, io.ifu.fetchpacket.bits.uops[0].bits.br_type connect decode_0.io.enq.uop.br_tag, io.ifu.fetchpacket.bits.uops[0].bits.br_tag connect decode_0.io.enq.uop.br_mask, io.ifu.fetchpacket.bits.uops[0].bits.br_mask connect decode_0.io.enq.uop.dis_col_sel, io.ifu.fetchpacket.bits.uops[0].bits.dis_col_sel connect decode_0.io.enq.uop.iw_p3_bypass_hint, io.ifu.fetchpacket.bits.uops[0].bits.iw_p3_bypass_hint connect decode_0.io.enq.uop.iw_p2_bypass_hint, io.ifu.fetchpacket.bits.uops[0].bits.iw_p2_bypass_hint connect decode_0.io.enq.uop.iw_p1_bypass_hint, io.ifu.fetchpacket.bits.uops[0].bits.iw_p1_bypass_hint connect decode_0.io.enq.uop.iw_p2_speculative_child, io.ifu.fetchpacket.bits.uops[0].bits.iw_p2_speculative_child connect decode_0.io.enq.uop.iw_p1_speculative_child, io.ifu.fetchpacket.bits.uops[0].bits.iw_p1_speculative_child connect decode_0.io.enq.uop.iw_issued_partial_dgen, io.ifu.fetchpacket.bits.uops[0].bits.iw_issued_partial_dgen connect decode_0.io.enq.uop.iw_issued_partial_agen, io.ifu.fetchpacket.bits.uops[0].bits.iw_issued_partial_agen connect decode_0.io.enq.uop.iw_issued, io.ifu.fetchpacket.bits.uops[0].bits.iw_issued connect decode_0.io.enq.uop.fu_code[0], io.ifu.fetchpacket.bits.uops[0].bits.fu_code[0] connect decode_0.io.enq.uop.fu_code[1], io.ifu.fetchpacket.bits.uops[0].bits.fu_code[1] connect decode_0.io.enq.uop.fu_code[2], io.ifu.fetchpacket.bits.uops[0].bits.fu_code[2] connect decode_0.io.enq.uop.fu_code[3], io.ifu.fetchpacket.bits.uops[0].bits.fu_code[3] connect decode_0.io.enq.uop.fu_code[4], io.ifu.fetchpacket.bits.uops[0].bits.fu_code[4] connect decode_0.io.enq.uop.fu_code[5], io.ifu.fetchpacket.bits.uops[0].bits.fu_code[5] connect decode_0.io.enq.uop.fu_code[6], io.ifu.fetchpacket.bits.uops[0].bits.fu_code[6] connect decode_0.io.enq.uop.fu_code[7], io.ifu.fetchpacket.bits.uops[0].bits.fu_code[7] connect decode_0.io.enq.uop.fu_code[8], io.ifu.fetchpacket.bits.uops[0].bits.fu_code[8] connect decode_0.io.enq.uop.fu_code[9], io.ifu.fetchpacket.bits.uops[0].bits.fu_code[9] connect decode_0.io.enq.uop.iq_type[0], io.ifu.fetchpacket.bits.uops[0].bits.iq_type[0] connect decode_0.io.enq.uop.iq_type[1], io.ifu.fetchpacket.bits.uops[0].bits.iq_type[1] connect decode_0.io.enq.uop.iq_type[2], io.ifu.fetchpacket.bits.uops[0].bits.iq_type[2] connect decode_0.io.enq.uop.iq_type[3], io.ifu.fetchpacket.bits.uops[0].bits.iq_type[3] connect decode_0.io.enq.uop.debug_pc, io.ifu.fetchpacket.bits.uops[0].bits.debug_pc connect decode_0.io.enq.uop.is_rvc, io.ifu.fetchpacket.bits.uops[0].bits.is_rvc connect decode_0.io.enq.uop.debug_inst, io.ifu.fetchpacket.bits.uops[0].bits.debug_inst connect decode_0.io.enq.uop.inst, io.ifu.fetchpacket.bits.uops[0].bits.inst connect decode_0.io.status.uie, csr.io.status.uie connect decode_0.io.status.sie, csr.io.status.sie connect decode_0.io.status.hie, csr.io.status.hie connect decode_0.io.status.mie, csr.io.status.mie connect decode_0.io.status.upie, csr.io.status.upie connect decode_0.io.status.spie, csr.io.status.spie connect decode_0.io.status.ube, csr.io.status.ube connect decode_0.io.status.mpie, csr.io.status.mpie connect decode_0.io.status.spp, csr.io.status.spp connect decode_0.io.status.vs, csr.io.status.vs connect decode_0.io.status.mpp, csr.io.status.mpp connect decode_0.io.status.fs, csr.io.status.fs connect decode_0.io.status.xs, csr.io.status.xs connect decode_0.io.status.mprv, csr.io.status.mprv connect decode_0.io.status.sum, csr.io.status.sum connect decode_0.io.status.mxr, csr.io.status.mxr connect decode_0.io.status.tvm, csr.io.status.tvm connect decode_0.io.status.tw, csr.io.status.tw connect decode_0.io.status.tsr, csr.io.status.tsr connect decode_0.io.status.zero1, csr.io.status.zero1 connect decode_0.io.status.sd_rv32, csr.io.status.sd_rv32 connect decode_0.io.status.uxl, csr.io.status.uxl connect decode_0.io.status.sxl, csr.io.status.sxl connect decode_0.io.status.sbe, csr.io.status.sbe connect decode_0.io.status.mbe, csr.io.status.mbe connect decode_0.io.status.gva, csr.io.status.gva connect decode_0.io.status.mpv, csr.io.status.mpv connect decode_0.io.status.zero2, csr.io.status.zero2 connect decode_0.io.status.sd, csr.io.status.sd connect decode_0.io.status.v, csr.io.status.v connect decode_0.io.status.prv, csr.io.status.prv connect decode_0.io.status.dv, csr.io.status.dv connect decode_0.io.status.dprv, csr.io.status.dprv connect decode_0.io.status.isa, csr.io.status.isa connect decode_0.io.status.wfi, csr.io.status.wfi connect decode_0.io.status.cease, csr.io.status.cease connect decode_0.io.status.debug, csr.io.status.debug connect decode_0.io.csr_decode, csr.io.decode[0] reg decode_0_io_interrupt_REG : UInt<1>, clock connect decode_0_io_interrupt_REG, csr.io.interrupt connect decode_0.io.interrupt, decode_0_io_interrupt_REG reg decode_0_io_interrupt_cause_REG : UInt, clock connect decode_0_io_interrupt_cause_REG, csr.io.interrupt_cause connect decode_0.io.interrupt_cause, decode_0_io_interrupt_cause_REG connect decode_0.io.fcsr_rm, csr.io.fcsr_rm connect dec_uops[0], decode_0.io.deq.uop node _dec_valids_1_T = and(io.ifu.fetchpacket.valid, io.ifu.fetchpacket.bits.uops[1].valid) node _dec_valids_1_T_1 = bits(dec_finished_mask, 1, 1) node _dec_valids_1_T_2 = eq(_dec_valids_1_T_1, UInt<1>(0h0)) node _dec_valids_1_T_3 = and(_dec_valids_1_T, _dec_valids_1_T_2) connect dec_valids[1], _dec_valids_1_T_3 connect decode_1.io.enq.uop.debug_tsrc, io.ifu.fetchpacket.bits.uops[1].bits.debug_tsrc connect decode_1.io.enq.uop.debug_fsrc, io.ifu.fetchpacket.bits.uops[1].bits.debug_fsrc connect decode_1.io.enq.uop.bp_xcpt_if, io.ifu.fetchpacket.bits.uops[1].bits.bp_xcpt_if connect decode_1.io.enq.uop.bp_debug_if, io.ifu.fetchpacket.bits.uops[1].bits.bp_debug_if connect decode_1.io.enq.uop.xcpt_ma_if, io.ifu.fetchpacket.bits.uops[1].bits.xcpt_ma_if connect decode_1.io.enq.uop.xcpt_ae_if, io.ifu.fetchpacket.bits.uops[1].bits.xcpt_ae_if connect decode_1.io.enq.uop.xcpt_pf_if, io.ifu.fetchpacket.bits.uops[1].bits.xcpt_pf_if connect decode_1.io.enq.uop.fp_typ, io.ifu.fetchpacket.bits.uops[1].bits.fp_typ connect decode_1.io.enq.uop.fp_rm, io.ifu.fetchpacket.bits.uops[1].bits.fp_rm connect decode_1.io.enq.uop.fp_val, io.ifu.fetchpacket.bits.uops[1].bits.fp_val connect decode_1.io.enq.uop.fcn_op, io.ifu.fetchpacket.bits.uops[1].bits.fcn_op connect decode_1.io.enq.uop.fcn_dw, io.ifu.fetchpacket.bits.uops[1].bits.fcn_dw connect decode_1.io.enq.uop.frs3_en, io.ifu.fetchpacket.bits.uops[1].bits.frs3_en connect decode_1.io.enq.uop.lrs2_rtype, io.ifu.fetchpacket.bits.uops[1].bits.lrs2_rtype connect decode_1.io.enq.uop.lrs1_rtype, io.ifu.fetchpacket.bits.uops[1].bits.lrs1_rtype connect decode_1.io.enq.uop.dst_rtype, io.ifu.fetchpacket.bits.uops[1].bits.dst_rtype connect decode_1.io.enq.uop.lrs3, io.ifu.fetchpacket.bits.uops[1].bits.lrs3 connect decode_1.io.enq.uop.lrs2, io.ifu.fetchpacket.bits.uops[1].bits.lrs2 connect decode_1.io.enq.uop.lrs1, io.ifu.fetchpacket.bits.uops[1].bits.lrs1 connect decode_1.io.enq.uop.ldst, io.ifu.fetchpacket.bits.uops[1].bits.ldst connect decode_1.io.enq.uop.ldst_is_rs1, io.ifu.fetchpacket.bits.uops[1].bits.ldst_is_rs1 connect decode_1.io.enq.uop.csr_cmd, io.ifu.fetchpacket.bits.uops[1].bits.csr_cmd connect decode_1.io.enq.uop.flush_on_commit, io.ifu.fetchpacket.bits.uops[1].bits.flush_on_commit connect decode_1.io.enq.uop.is_unique, io.ifu.fetchpacket.bits.uops[1].bits.is_unique connect decode_1.io.enq.uop.uses_stq, io.ifu.fetchpacket.bits.uops[1].bits.uses_stq connect decode_1.io.enq.uop.uses_ldq, io.ifu.fetchpacket.bits.uops[1].bits.uses_ldq connect decode_1.io.enq.uop.mem_signed, io.ifu.fetchpacket.bits.uops[1].bits.mem_signed connect decode_1.io.enq.uop.mem_size, io.ifu.fetchpacket.bits.uops[1].bits.mem_size connect decode_1.io.enq.uop.mem_cmd, io.ifu.fetchpacket.bits.uops[1].bits.mem_cmd connect decode_1.io.enq.uop.exc_cause, io.ifu.fetchpacket.bits.uops[1].bits.exc_cause connect decode_1.io.enq.uop.exception, io.ifu.fetchpacket.bits.uops[1].bits.exception connect decode_1.io.enq.uop.stale_pdst, io.ifu.fetchpacket.bits.uops[1].bits.stale_pdst connect decode_1.io.enq.uop.ppred_busy, io.ifu.fetchpacket.bits.uops[1].bits.ppred_busy connect decode_1.io.enq.uop.prs3_busy, io.ifu.fetchpacket.bits.uops[1].bits.prs3_busy connect decode_1.io.enq.uop.prs2_busy, io.ifu.fetchpacket.bits.uops[1].bits.prs2_busy connect decode_1.io.enq.uop.prs1_busy, io.ifu.fetchpacket.bits.uops[1].bits.prs1_busy connect decode_1.io.enq.uop.ppred, io.ifu.fetchpacket.bits.uops[1].bits.ppred connect decode_1.io.enq.uop.prs3, io.ifu.fetchpacket.bits.uops[1].bits.prs3 connect decode_1.io.enq.uop.prs2, io.ifu.fetchpacket.bits.uops[1].bits.prs2 connect decode_1.io.enq.uop.prs1, io.ifu.fetchpacket.bits.uops[1].bits.prs1 connect decode_1.io.enq.uop.pdst, io.ifu.fetchpacket.bits.uops[1].bits.pdst connect decode_1.io.enq.uop.rxq_idx, io.ifu.fetchpacket.bits.uops[1].bits.rxq_idx connect decode_1.io.enq.uop.stq_idx, io.ifu.fetchpacket.bits.uops[1].bits.stq_idx connect decode_1.io.enq.uop.ldq_idx, io.ifu.fetchpacket.bits.uops[1].bits.ldq_idx connect decode_1.io.enq.uop.rob_idx, io.ifu.fetchpacket.bits.uops[1].bits.rob_idx connect decode_1.io.enq.uop.fp_ctrl.vec, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.vec connect decode_1.io.enq.uop.fp_ctrl.wflags, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.wflags connect decode_1.io.enq.uop.fp_ctrl.sqrt, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.sqrt connect decode_1.io.enq.uop.fp_ctrl.div, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.div connect decode_1.io.enq.uop.fp_ctrl.fma, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.fma connect decode_1.io.enq.uop.fp_ctrl.fastpipe, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.fastpipe connect decode_1.io.enq.uop.fp_ctrl.toint, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.toint connect decode_1.io.enq.uop.fp_ctrl.fromint, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.fromint connect decode_1.io.enq.uop.fp_ctrl.typeTagOut, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.typeTagOut connect decode_1.io.enq.uop.fp_ctrl.typeTagIn, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.typeTagIn connect decode_1.io.enq.uop.fp_ctrl.swap23, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.swap23 connect decode_1.io.enq.uop.fp_ctrl.swap12, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.swap12 connect decode_1.io.enq.uop.fp_ctrl.ren3, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.ren3 connect decode_1.io.enq.uop.fp_ctrl.ren2, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.ren2 connect decode_1.io.enq.uop.fp_ctrl.ren1, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.ren1 connect decode_1.io.enq.uop.fp_ctrl.wen, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.wen connect decode_1.io.enq.uop.fp_ctrl.ldst, io.ifu.fetchpacket.bits.uops[1].bits.fp_ctrl.ldst connect decode_1.io.enq.uop.op2_sel, io.ifu.fetchpacket.bits.uops[1].bits.op2_sel connect decode_1.io.enq.uop.op1_sel, io.ifu.fetchpacket.bits.uops[1].bits.op1_sel connect decode_1.io.enq.uop.imm_packed, io.ifu.fetchpacket.bits.uops[1].bits.imm_packed connect decode_1.io.enq.uop.pimm, io.ifu.fetchpacket.bits.uops[1].bits.pimm connect decode_1.io.enq.uop.imm_sel, io.ifu.fetchpacket.bits.uops[1].bits.imm_sel connect decode_1.io.enq.uop.imm_rename, io.ifu.fetchpacket.bits.uops[1].bits.imm_rename connect decode_1.io.enq.uop.taken, io.ifu.fetchpacket.bits.uops[1].bits.taken connect decode_1.io.enq.uop.pc_lob, io.ifu.fetchpacket.bits.uops[1].bits.pc_lob connect decode_1.io.enq.uop.edge_inst, io.ifu.fetchpacket.bits.uops[1].bits.edge_inst connect decode_1.io.enq.uop.ftq_idx, io.ifu.fetchpacket.bits.uops[1].bits.ftq_idx connect decode_1.io.enq.uop.is_mov, io.ifu.fetchpacket.bits.uops[1].bits.is_mov connect decode_1.io.enq.uop.is_rocc, io.ifu.fetchpacket.bits.uops[1].bits.is_rocc connect decode_1.io.enq.uop.is_sys_pc2epc, io.ifu.fetchpacket.bits.uops[1].bits.is_sys_pc2epc connect decode_1.io.enq.uop.is_eret, io.ifu.fetchpacket.bits.uops[1].bits.is_eret connect decode_1.io.enq.uop.is_amo, io.ifu.fetchpacket.bits.uops[1].bits.is_amo connect decode_1.io.enq.uop.is_sfence, io.ifu.fetchpacket.bits.uops[1].bits.is_sfence connect decode_1.io.enq.uop.is_fencei, io.ifu.fetchpacket.bits.uops[1].bits.is_fencei connect decode_1.io.enq.uop.is_fence, io.ifu.fetchpacket.bits.uops[1].bits.is_fence connect decode_1.io.enq.uop.is_sfb, io.ifu.fetchpacket.bits.uops[1].bits.is_sfb connect decode_1.io.enq.uop.br_type, io.ifu.fetchpacket.bits.uops[1].bits.br_type connect decode_1.io.enq.uop.br_tag, io.ifu.fetchpacket.bits.uops[1].bits.br_tag connect decode_1.io.enq.uop.br_mask, io.ifu.fetchpacket.bits.uops[1].bits.br_mask connect decode_1.io.enq.uop.dis_col_sel, io.ifu.fetchpacket.bits.uops[1].bits.dis_col_sel connect decode_1.io.enq.uop.iw_p3_bypass_hint, io.ifu.fetchpacket.bits.uops[1].bits.iw_p3_bypass_hint connect decode_1.io.enq.uop.iw_p2_bypass_hint, io.ifu.fetchpacket.bits.uops[1].bits.iw_p2_bypass_hint connect decode_1.io.enq.uop.iw_p1_bypass_hint, io.ifu.fetchpacket.bits.uops[1].bits.iw_p1_bypass_hint connect decode_1.io.enq.uop.iw_p2_speculative_child, io.ifu.fetchpacket.bits.uops[1].bits.iw_p2_speculative_child connect decode_1.io.enq.uop.iw_p1_speculative_child, io.ifu.fetchpacket.bits.uops[1].bits.iw_p1_speculative_child connect decode_1.io.enq.uop.iw_issued_partial_dgen, io.ifu.fetchpacket.bits.uops[1].bits.iw_issued_partial_dgen connect decode_1.io.enq.uop.iw_issued_partial_agen, io.ifu.fetchpacket.bits.uops[1].bits.iw_issued_partial_agen connect decode_1.io.enq.uop.iw_issued, io.ifu.fetchpacket.bits.uops[1].bits.iw_issued connect decode_1.io.enq.uop.fu_code[0], io.ifu.fetchpacket.bits.uops[1].bits.fu_code[0] connect decode_1.io.enq.uop.fu_code[1], io.ifu.fetchpacket.bits.uops[1].bits.fu_code[1] connect decode_1.io.enq.uop.fu_code[2], io.ifu.fetchpacket.bits.uops[1].bits.fu_code[2] connect decode_1.io.enq.uop.fu_code[3], io.ifu.fetchpacket.bits.uops[1].bits.fu_code[3] connect decode_1.io.enq.uop.fu_code[4], io.ifu.fetchpacket.bits.uops[1].bits.fu_code[4] connect decode_1.io.enq.uop.fu_code[5], io.ifu.fetchpacket.bits.uops[1].bits.fu_code[5] connect decode_1.io.enq.uop.fu_code[6], io.ifu.fetchpacket.bits.uops[1].bits.fu_code[6] connect decode_1.io.enq.uop.fu_code[7], io.ifu.fetchpacket.bits.uops[1].bits.fu_code[7] connect decode_1.io.enq.uop.fu_code[8], io.ifu.fetchpacket.bits.uops[1].bits.fu_code[8] connect decode_1.io.enq.uop.fu_code[9], io.ifu.fetchpacket.bits.uops[1].bits.fu_code[9] connect decode_1.io.enq.uop.iq_type[0], io.ifu.fetchpacket.bits.uops[1].bits.iq_type[0] connect decode_1.io.enq.uop.iq_type[1], io.ifu.fetchpacket.bits.uops[1].bits.iq_type[1] connect decode_1.io.enq.uop.iq_type[2], io.ifu.fetchpacket.bits.uops[1].bits.iq_type[2] connect decode_1.io.enq.uop.iq_type[3], io.ifu.fetchpacket.bits.uops[1].bits.iq_type[3] connect decode_1.io.enq.uop.debug_pc, io.ifu.fetchpacket.bits.uops[1].bits.debug_pc connect decode_1.io.enq.uop.is_rvc, io.ifu.fetchpacket.bits.uops[1].bits.is_rvc connect decode_1.io.enq.uop.debug_inst, io.ifu.fetchpacket.bits.uops[1].bits.debug_inst connect decode_1.io.enq.uop.inst, io.ifu.fetchpacket.bits.uops[1].bits.inst connect decode_1.io.status.uie, csr.io.status.uie connect decode_1.io.status.sie, csr.io.status.sie connect decode_1.io.status.hie, csr.io.status.hie connect decode_1.io.status.mie, csr.io.status.mie connect decode_1.io.status.upie, csr.io.status.upie connect decode_1.io.status.spie, csr.io.status.spie connect decode_1.io.status.ube, csr.io.status.ube connect decode_1.io.status.mpie, csr.io.status.mpie connect decode_1.io.status.spp, csr.io.status.spp connect decode_1.io.status.vs, csr.io.status.vs connect decode_1.io.status.mpp, csr.io.status.mpp connect decode_1.io.status.fs, csr.io.status.fs connect decode_1.io.status.xs, csr.io.status.xs connect decode_1.io.status.mprv, csr.io.status.mprv connect decode_1.io.status.sum, csr.io.status.sum connect decode_1.io.status.mxr, csr.io.status.mxr connect decode_1.io.status.tvm, csr.io.status.tvm connect decode_1.io.status.tw, csr.io.status.tw connect decode_1.io.status.tsr, csr.io.status.tsr connect decode_1.io.status.zero1, csr.io.status.zero1 connect decode_1.io.status.sd_rv32, csr.io.status.sd_rv32 connect decode_1.io.status.uxl, csr.io.status.uxl connect decode_1.io.status.sxl, csr.io.status.sxl connect decode_1.io.status.sbe, csr.io.status.sbe connect decode_1.io.status.mbe, csr.io.status.mbe connect decode_1.io.status.gva, csr.io.status.gva connect decode_1.io.status.mpv, csr.io.status.mpv connect decode_1.io.status.zero2, csr.io.status.zero2 connect decode_1.io.status.sd, csr.io.status.sd connect decode_1.io.status.v, csr.io.status.v connect decode_1.io.status.prv, csr.io.status.prv connect decode_1.io.status.dv, csr.io.status.dv connect decode_1.io.status.dprv, csr.io.status.dprv connect decode_1.io.status.isa, csr.io.status.isa connect decode_1.io.status.wfi, csr.io.status.wfi connect decode_1.io.status.cease, csr.io.status.cease connect decode_1.io.status.debug, csr.io.status.debug connect decode_1.io.csr_decode, csr.io.decode[1] reg decode_1_io_interrupt_REG : UInt<1>, clock connect decode_1_io_interrupt_REG, csr.io.interrupt connect decode_1.io.interrupt, decode_1_io_interrupt_REG reg decode_1_io_interrupt_cause_REG : UInt, clock connect decode_1_io_interrupt_cause_REG, csr.io.interrupt_cause connect decode_1.io.interrupt_cause, decode_1_io_interrupt_cause_REG connect decode_1.io.fcsr_rm, csr.io.fcsr_rm connect dec_uops[1], decode_1.io.deq.uop wire xcpt_pc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>} wire mispredict_pc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>} wire flush_pc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>} inst ftq_arb of Arbiter3_UInt5 connect ftq_arb.clock, clock connect ftq_arb.reset, reset connect ftq_arb.io.in[0], flush_pc_req connect ftq_arb.io.in[1], mispredict_pc_req connect ftq_arb.io.in[2], xcpt_pc_req connect io.ifu.arb_ftq_reqs[0], ftq_arb.io.out.bits connect ftq_arb.io.out.ready, UInt<1>(0h1) wire data_sel : UInt<2> connect data_sel, UInt<2>(0h0) wire issue_read : UInt<1> connect issue_read, UInt<1>(0h0) wire use_port : UInt<1> connect use_port, UInt<1>(0h0) node _T_24 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_25 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_26 = and(_T_24, _T_25) node _T_27 = and(_T_26, alu_exe_unit_0.io_arb_ftq_reqs[0].valid) when _T_27 : connect issue_read, UInt<1>(0h1) connect use_port, UInt<1>(0h1) node _data_sel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) connect data_sel, _data_sel_T node _T_28 = or(use_port, UInt<1>(0h0)) node _T_29 = eq(use_port, UInt<1>(0h0)) node _T_30 = or(UInt<1>(0h0), _T_29) node _T_31 = mux(_T_30, UInt<1>(0h0), alu_exe_unit_0.io_arb_ftq_reqs[0].bits) node _T_32 = or(UInt<5>(0h0), _T_31) node _T_33 = or(issue_read, UInt<1>(0h0)) wire issue_read_1 : UInt<1> connect issue_read_1, UInt<1>(0h0) wire use_port_1 : UInt<1> connect use_port_1, UInt<1>(0h0) node _T_34 = eq(_T_33, UInt<1>(0h0)) node _T_35 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_36 = and(_T_34, _T_35) node _T_37 = and(_T_36, alu_exe_unit_0.io_arb_ftq_reqs[0].valid) when _T_37 : connect issue_read_1, UInt<1>(0h1) connect use_port_1, UInt<1>(0h1) node _data_sel_T_1 = dshl(UInt<1>(0h1), UInt<1>(0h1)) connect data_sel, _data_sel_T_1 node _T_38 = or(use_port_1, UInt<1>(0h0)) node _T_39 = eq(use_port_1, UInt<1>(0h0)) node _T_40 = or(UInt<1>(0h0), _T_39) node _T_41 = mux(_T_40, UInt<1>(0h0), alu_exe_unit_0.io_arb_ftq_reqs[0].bits) node _T_42 = or(UInt<5>(0h0), _T_41) node _T_43 = or(issue_read_1, _T_33) connect alu_exe_unit_0.io_arb_ftq_reqs[0].ready, _T_43 node _alu_exe_unit_0_io_rrd_ftq_resps_0_T = bits(data_sel, 0, 0) reg alu_exe_unit_0_io_rrd_ftq_resps_0_REG : UInt<1>, clock connect alu_exe_unit_0_io_rrd_ftq_resps_0_REG, _alu_exe_unit_0_io_rrd_ftq_resps_0_T node _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1 = mux(alu_exe_unit_0_io_rrd_ftq_resps_0_REG, io.ifu.rrd_ftq_resps[1], io.ifu.rrd_ftq_resps[2]) connect alu_exe_unit_0.io_rrd_ftq_resps[0].pc, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.pc connect alu_exe_unit_0.io_rrd_ftq_resps[0].ghist.ras_idx, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.ghist.ras_idx connect alu_exe_unit_0.io_rrd_ftq_resps[0].ghist.new_saw_branch_taken, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.ghist.new_saw_branch_taken connect alu_exe_unit_0.io_rrd_ftq_resps[0].ghist.new_saw_branch_not_taken, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.ghist.new_saw_branch_not_taken connect alu_exe_unit_0.io_rrd_ftq_resps[0].ghist.current_saw_branch_not_taken, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.ghist.current_saw_branch_not_taken connect alu_exe_unit_0.io_rrd_ftq_resps[0].ghist.old_history, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.ghist.old_history connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.start_bank, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.start_bank connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.ras_idx, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.ras_idx connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.ras_top, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.ras_top connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.cfi_npc_plus4, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.cfi_npc_plus4 connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.cfi_is_ret, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.cfi_is_ret connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.cfi_is_call, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.cfi_is_call connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.br_mask, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.br_mask connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.cfi_type, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.cfi_type connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.cfi_mispredicted, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.cfi_mispredicted connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.cfi_taken, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.cfi_taken connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.cfi_idx.bits, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.cfi_idx.bits connect alu_exe_unit_0.io_rrd_ftq_resps[0].entry.cfi_idx.valid, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.entry.cfi_idx.valid connect alu_exe_unit_0.io_rrd_ftq_resps[0].valid, _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1.valid wire data_sel_1 : UInt<2> connect data_sel_1, UInt<2>(0h0) wire issue_read_2 : UInt<1> connect issue_read_2, UInt<1>(0h0) wire use_port_2 : UInt<1> connect use_port_2, UInt<1>(0h0) node _T_44 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_45 = eq(_T_28, UInt<1>(0h0)) node _T_46 = and(_T_44, _T_45) node _T_47 = and(_T_46, alu_exe_unit_0.io_arb_ftq_reqs[1].valid) when _T_47 : connect issue_read_2, UInt<1>(0h1) connect use_port_2, UInt<1>(0h1) node _data_sel_T_2 = dshl(UInt<1>(0h1), UInt<1>(0h0)) connect data_sel_1, _data_sel_T_2 node _T_48 = or(use_port_2, _T_28) node _T_49 = eq(use_port_2, UInt<1>(0h0)) node _T_50 = or(_T_28, _T_49) node _T_51 = mux(_T_50, UInt<1>(0h0), alu_exe_unit_0.io_arb_ftq_reqs[1].bits) node _T_52 = or(_T_32, _T_51) node _T_53 = or(issue_read_2, UInt<1>(0h0)) wire issue_read_3 : UInt<1> connect issue_read_3, UInt<1>(0h0) wire use_port_3 : UInt<1> connect use_port_3, UInt<1>(0h0) node _T_54 = eq(_T_53, UInt<1>(0h0)) node _T_55 = eq(_T_38, UInt<1>(0h0)) node _T_56 = and(_T_54, _T_55) node _T_57 = and(_T_56, alu_exe_unit_0.io_arb_ftq_reqs[1].valid) when _T_57 : connect issue_read_3, UInt<1>(0h1) connect use_port_3, UInt<1>(0h1) node _data_sel_T_3 = dshl(UInt<1>(0h1), UInt<1>(0h1)) connect data_sel_1, _data_sel_T_3 node _T_58 = or(use_port_3, _T_38) node _T_59 = eq(use_port_3, UInt<1>(0h0)) node _T_60 = or(_T_38, _T_59) node _T_61 = mux(_T_60, UInt<1>(0h0), alu_exe_unit_0.io_arb_ftq_reqs[1].bits) node _T_62 = or(_T_42, _T_61) node _T_63 = or(issue_read_3, _T_53) connect alu_exe_unit_0.io_arb_ftq_reqs[1].ready, _T_63 node _alu_exe_unit_0_io_rrd_ftq_resps_1_T = bits(data_sel_1, 0, 0) reg alu_exe_unit_0_io_rrd_ftq_resps_1_REG : UInt<1>, clock connect alu_exe_unit_0_io_rrd_ftq_resps_1_REG, _alu_exe_unit_0_io_rrd_ftq_resps_1_T node _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1 = mux(alu_exe_unit_0_io_rrd_ftq_resps_1_REG, io.ifu.rrd_ftq_resps[1], io.ifu.rrd_ftq_resps[2]) connect alu_exe_unit_0.io_rrd_ftq_resps[1].pc, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.pc connect alu_exe_unit_0.io_rrd_ftq_resps[1].ghist.ras_idx, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.ghist.ras_idx connect alu_exe_unit_0.io_rrd_ftq_resps[1].ghist.new_saw_branch_taken, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.ghist.new_saw_branch_taken connect alu_exe_unit_0.io_rrd_ftq_resps[1].ghist.new_saw_branch_not_taken, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.ghist.new_saw_branch_not_taken connect alu_exe_unit_0.io_rrd_ftq_resps[1].ghist.current_saw_branch_not_taken, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.ghist.current_saw_branch_not_taken connect alu_exe_unit_0.io_rrd_ftq_resps[1].ghist.old_history, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.ghist.old_history connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.start_bank, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.start_bank connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.ras_idx, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.ras_idx connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.ras_top, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.ras_top connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.cfi_npc_plus4, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.cfi_npc_plus4 connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.cfi_is_ret, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.cfi_is_ret connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.cfi_is_call, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.cfi_is_call connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.br_mask, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.br_mask connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.cfi_type, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.cfi_type connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.cfi_mispredicted, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.cfi_mispredicted connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.cfi_taken, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.cfi_taken connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.cfi_idx.bits, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.cfi_idx.bits connect alu_exe_unit_0.io_rrd_ftq_resps[1].entry.cfi_idx.valid, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.entry.cfi_idx.valid connect alu_exe_unit_0.io_rrd_ftq_resps[1].valid, _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1.valid wire data_sel_2 : UInt<2> connect data_sel_2, UInt<2>(0h0) wire issue_read_4 : UInt<1> connect issue_read_4, UInt<1>(0h0) wire use_port_4 : UInt<1> connect use_port_4, UInt<1>(0h0) node _T_64 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_65 = eq(_T_48, UInt<1>(0h0)) node _T_66 = and(_T_64, _T_65) node _T_67 = and(_T_66, alu_exe_unit_1.io_arb_ftq_reqs[0].valid) when _T_67 : connect issue_read_4, UInt<1>(0h1) connect use_port_4, UInt<1>(0h1) node _data_sel_T_4 = dshl(UInt<1>(0h1), UInt<1>(0h0)) connect data_sel_2, _data_sel_T_4 node _T_68 = or(use_port_4, _T_48) node _T_69 = eq(use_port_4, UInt<1>(0h0)) node _T_70 = or(_T_48, _T_69) node _T_71 = mux(_T_70, UInt<1>(0h0), alu_exe_unit_1.io_arb_ftq_reqs[0].bits) node _T_72 = or(_T_52, _T_71) node _T_73 = or(issue_read_4, UInt<1>(0h0)) wire issue_read_5 : UInt<1> connect issue_read_5, UInt<1>(0h0) wire use_port_5 : UInt<1> connect use_port_5, UInt<1>(0h0) node _T_74 = eq(_T_73, UInt<1>(0h0)) node _T_75 = eq(_T_58, UInt<1>(0h0)) node _T_76 = and(_T_74, _T_75) node _T_77 = and(_T_76, alu_exe_unit_1.io_arb_ftq_reqs[0].valid) when _T_77 : connect issue_read_5, UInt<1>(0h1) connect use_port_5, UInt<1>(0h1) node _data_sel_T_5 = dshl(UInt<1>(0h1), UInt<1>(0h1)) connect data_sel_2, _data_sel_T_5 node _T_78 = or(use_port_5, _T_58) node _T_79 = eq(use_port_5, UInt<1>(0h0)) node _T_80 = or(_T_58, _T_79) node _T_81 = mux(_T_80, UInt<1>(0h0), alu_exe_unit_1.io_arb_ftq_reqs[0].bits) node _T_82 = or(_T_62, _T_81) node _T_83 = or(issue_read_5, _T_73) connect alu_exe_unit_1.io_arb_ftq_reqs[0].ready, _T_83 node _alu_exe_unit_1_io_rrd_ftq_resps_0_T = bits(data_sel_2, 0, 0) reg alu_exe_unit_1_io_rrd_ftq_resps_0_REG : UInt<1>, clock connect alu_exe_unit_1_io_rrd_ftq_resps_0_REG, _alu_exe_unit_1_io_rrd_ftq_resps_0_T node _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1 = mux(alu_exe_unit_1_io_rrd_ftq_resps_0_REG, io.ifu.rrd_ftq_resps[1], io.ifu.rrd_ftq_resps[2]) connect alu_exe_unit_1.io_rrd_ftq_resps[0].pc, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.pc connect alu_exe_unit_1.io_rrd_ftq_resps[0].ghist.ras_idx, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.ghist.ras_idx connect alu_exe_unit_1.io_rrd_ftq_resps[0].ghist.new_saw_branch_taken, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.ghist.new_saw_branch_taken connect alu_exe_unit_1.io_rrd_ftq_resps[0].ghist.new_saw_branch_not_taken, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.ghist.new_saw_branch_not_taken connect alu_exe_unit_1.io_rrd_ftq_resps[0].ghist.current_saw_branch_not_taken, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.ghist.current_saw_branch_not_taken connect alu_exe_unit_1.io_rrd_ftq_resps[0].ghist.old_history, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.ghist.old_history connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.start_bank, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.start_bank connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.ras_idx, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.ras_idx connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.ras_top, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.ras_top connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.cfi_npc_plus4, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.cfi_npc_plus4 connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.cfi_is_ret, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.cfi_is_ret connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.cfi_is_call, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.cfi_is_call connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.br_mask, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.br_mask connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.cfi_type, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.cfi_type connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.cfi_mispredicted, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.cfi_mispredicted connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.cfi_taken, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.cfi_taken connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.cfi_idx.bits, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.cfi_idx.bits connect alu_exe_unit_1.io_rrd_ftq_resps[0].entry.cfi_idx.valid, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.entry.cfi_idx.valid connect alu_exe_unit_1.io_rrd_ftq_resps[0].valid, _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1.valid wire data_sel_3 : UInt<2> connect data_sel_3, UInt<2>(0h0) wire issue_read_6 : UInt<1> connect issue_read_6, UInt<1>(0h0) wire use_port_6 : UInt<1> connect use_port_6, UInt<1>(0h0) node _T_84 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _T_85 = eq(_T_68, UInt<1>(0h0)) node _T_86 = and(_T_84, _T_85) node _T_87 = and(_T_86, alu_exe_unit_1.io_arb_ftq_reqs[1].valid) when _T_87 : connect issue_read_6, UInt<1>(0h1) connect use_port_6, UInt<1>(0h1) node _data_sel_T_6 = dshl(UInt<1>(0h1), UInt<1>(0h0)) connect data_sel_3, _data_sel_T_6 node _T_88 = or(use_port_6, _T_68) node _T_89 = eq(use_port_6, UInt<1>(0h0)) node _T_90 = or(_T_68, _T_89) node _T_91 = mux(_T_90, UInt<1>(0h0), alu_exe_unit_1.io_arb_ftq_reqs[1].bits) node _T_92 = or(_T_72, _T_91) node _T_93 = or(issue_read_6, UInt<1>(0h0)) wire issue_read_7 : UInt<1> connect issue_read_7, UInt<1>(0h0) wire use_port_7 : UInt<1> connect use_port_7, UInt<1>(0h0) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = eq(_T_78, UInt<1>(0h0)) node _T_96 = and(_T_94, _T_95) node _T_97 = and(_T_96, alu_exe_unit_1.io_arb_ftq_reqs[1].valid) when _T_97 : connect issue_read_7, UInt<1>(0h1) connect use_port_7, UInt<1>(0h1) node _data_sel_T_7 = dshl(UInt<1>(0h1), UInt<1>(0h1)) connect data_sel_3, _data_sel_T_7 node _T_98 = or(use_port_7, _T_78) node _T_99 = eq(use_port_7, UInt<1>(0h0)) node _T_100 = or(_T_78, _T_99) node _T_101 = mux(_T_100, UInt<1>(0h0), alu_exe_unit_1.io_arb_ftq_reqs[1].bits) node _T_102 = or(_T_82, _T_101) node _T_103 = or(issue_read_7, _T_93) connect alu_exe_unit_1.io_arb_ftq_reqs[1].ready, _T_103 node _alu_exe_unit_1_io_rrd_ftq_resps_1_T = bits(data_sel_3, 0, 0) reg alu_exe_unit_1_io_rrd_ftq_resps_1_REG : UInt<1>, clock connect alu_exe_unit_1_io_rrd_ftq_resps_1_REG, _alu_exe_unit_1_io_rrd_ftq_resps_1_T node _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1 = mux(alu_exe_unit_1_io_rrd_ftq_resps_1_REG, io.ifu.rrd_ftq_resps[1], io.ifu.rrd_ftq_resps[2]) connect alu_exe_unit_1.io_rrd_ftq_resps[1].pc, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.pc connect alu_exe_unit_1.io_rrd_ftq_resps[1].ghist.ras_idx, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.ghist.ras_idx connect alu_exe_unit_1.io_rrd_ftq_resps[1].ghist.new_saw_branch_taken, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.ghist.new_saw_branch_taken connect alu_exe_unit_1.io_rrd_ftq_resps[1].ghist.new_saw_branch_not_taken, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.ghist.new_saw_branch_not_taken connect alu_exe_unit_1.io_rrd_ftq_resps[1].ghist.current_saw_branch_not_taken, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.ghist.current_saw_branch_not_taken connect alu_exe_unit_1.io_rrd_ftq_resps[1].ghist.old_history, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.ghist.old_history connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.start_bank, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.start_bank connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.ras_idx, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.ras_idx connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.ras_top, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.ras_top connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.cfi_npc_plus4, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.cfi_npc_plus4 connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.cfi_is_ret, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.cfi_is_ret connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.cfi_is_call, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.cfi_is_call connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.br_mask, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.br_mask connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.cfi_type, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.cfi_type connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.cfi_mispredicted, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.cfi_mispredicted connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.cfi_taken, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.cfi_taken connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.cfi_idx.bits, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.cfi_idx.bits connect alu_exe_unit_1.io_rrd_ftq_resps[1].entry.cfi_idx.valid, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.entry.cfi_idx.valid connect alu_exe_unit_1.io_rrd_ftq_resps[1].valid, _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1.valid connect io.ifu.arb_ftq_reqs[1], _T_92 connect io.ifu.arb_ftq_reqs[2], _T_102 node xcpt_idx = mux(dec_xcpts[0], UInt<1>(0h0), UInt<1>(0h1)) node _xcpt_pc_req_valid_T = or(dec_xcpts[0], dec_xcpts[1]) connect xcpt_pc_req.valid, _xcpt_pc_req_valid_T connect xcpt_pc_req.bits, dec_uops[xcpt_idx].ftq_idx connect rob.io.xcpt_fetch_pc, io.ifu.rrd_ftq_resps[0].pc connect flush_pc_req.valid, rob.io.flush.valid connect flush_pc_req.bits, rob.io.flush.bits.ftq_idx connect mispredict_pc_req.valid, mispredict_val connect mispredict_pc_req.bits, oldest_mispredict_ftq_idx node _T_104 = and(dec_uops[0].exception, dec_valids[0]) node _T_105 = and(dec_uops[1].exception, dec_valids[1]) connect dec_xcpts[0], _T_104 connect dec_xcpts[1], _T_105 node dec_prior_slot_valid_1 = or(UInt<1>(0h0), dec_valids[0]) node dec_prior_slot_valid_2 = or(dec_prior_slot_valid_1, dec_valids[1]) node _dec_xcpt_stall_T = eq(rob.io.empty, UInt<1>(0h0)) node _dec_xcpt_stall_T_1 = eq(io.lsu.fencei_rdy, UInt<1>(0h0)) node _dec_xcpt_stall_T_2 = or(_dec_xcpt_stall_T, _dec_xcpt_stall_T_1) node _dec_xcpt_stall_T_3 = or(_dec_xcpt_stall_T_2, UInt<1>(0h0)) node _dec_xcpt_stall_T_4 = or(dis_valids[0], dis_valids[1]) node _dec_xcpt_stall_T_5 = or(_dec_xcpt_stall_T_3, _dec_xcpt_stall_T_4) node _dec_xcpt_stall_T_6 = eq(xcpt_pc_req.ready, UInt<1>(0h0)) node _dec_xcpt_stall_T_7 = or(_dec_xcpt_stall_T_5, _dec_xcpt_stall_T_6) node dec_xcpt_stall_0 = and(dec_xcpts[0], _dec_xcpt_stall_T_7) node _dec_xcpt_stall_T_8 = eq(rob.io.empty, UInt<1>(0h0)) node _dec_xcpt_stall_T_9 = eq(io.lsu.fencei_rdy, UInt<1>(0h0)) node _dec_xcpt_stall_T_10 = or(_dec_xcpt_stall_T_8, _dec_xcpt_stall_T_9) node _dec_xcpt_stall_T_11 = or(_dec_xcpt_stall_T_10, dec_prior_slot_valid_1) node _dec_xcpt_stall_T_12 = or(dis_valids[0], dis_valids[1]) node _dec_xcpt_stall_T_13 = or(_dec_xcpt_stall_T_11, _dec_xcpt_stall_T_12) node _dec_xcpt_stall_T_14 = eq(xcpt_pc_req.ready, UInt<1>(0h0)) node _dec_xcpt_stall_T_15 = or(_dec_xcpt_stall_T_13, _dec_xcpt_stall_T_14) node dec_xcpt_stall_1 = and(dec_xcpts[1], _dec_xcpt_stall_T_15) wire branch_mask_full : UInt<1>[2] node _dec_hazards_T = eq(dis_ready, UInt<1>(0h0)) node _dec_hazards_T_1 = or(_dec_hazards_T, rob.io.rollback) node _dec_hazards_T_2 = or(_dec_hazards_T_1, dec_xcpt_stall_0) node _dec_hazards_T_3 = or(_dec_hazards_T_2, branch_mask_full[0]) node _dec_hazards_T_4 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _dec_hazards_T_5 = or(_dec_hazards_T_3, _dec_hazards_T_4) node _dec_hazards_T_6 = or(_dec_hazards_T_5, brupdate.b2.mispredict) node _dec_hazards_T_7 = or(_dec_hazards_T_6, io.ifu.redirect_flush) node dec_hazards_0 = and(dec_valids[0], _dec_hazards_T_7) node _dec_hazards_T_8 = eq(dis_ready, UInt<1>(0h0)) node _dec_hazards_T_9 = or(_dec_hazards_T_8, rob.io.rollback) node _dec_hazards_T_10 = or(_dec_hazards_T_9, dec_xcpt_stall_1) node _dec_hazards_T_11 = or(_dec_hazards_T_10, branch_mask_full[1]) node _dec_hazards_T_12 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _dec_hazards_T_13 = or(_dec_hazards_T_11, _dec_hazards_T_12) node _dec_hazards_T_14 = or(_dec_hazards_T_13, brupdate.b2.mispredict) node _dec_hazards_T_15 = or(_dec_hazards_T_14, io.ifu.redirect_flush) node dec_hazards_1 = and(dec_valids[1], _dec_hazards_T_15) node dec_stalls_0 = or(UInt<1>(0h0), dec_hazards_0) node dec_stalls_1 = or(dec_stalls_0, dec_hazards_1) node _T_106 = eq(dec_stalls_0, UInt<1>(0h0)) node _T_107 = and(dec_valids[0], _T_106) node _T_108 = eq(dec_stalls_1, UInt<1>(0h0)) node _T_109 = and(dec_valids[1], _T_108) connect dec_fire[0], _T_107 connect dec_fire[1], _T_109 connect dec_ready, dec_fire[1] node _T_110 = or(dec_ready, io.ifu.redirect_flush) when _T_110 : connect dec_finished_mask, UInt<1>(0h0) else : node _dec_finished_mask_T = cat(dec_fire[1], dec_fire[0]) node _dec_finished_mask_T_1 = or(_dec_finished_mask_T, dec_finished_mask) connect dec_finished_mask, _dec_finished_mask_T_1 connect dec_brmask_logic.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect dec_brmask_logic.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect dec_brmask_logic.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect dec_brmask_logic.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect dec_brmask_logic.io.brupdate.b2.taken, brupdate.b2.taken connect dec_brmask_logic.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect dec_brmask_logic.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect dec_brmask_logic.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect dec_brmask_logic.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect dec_brmask_logic.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect dec_brmask_logic.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect dec_brmask_logic.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect dec_brmask_logic.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect dec_brmask_logic.io.brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect dec_brmask_logic.io.brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect dec_brmask_logic.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect dec_brmask_logic.io.brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect dec_brmask_logic.io.brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect dec_brmask_logic.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect dec_brmask_logic.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect dec_brmask_logic.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect dec_brmask_logic.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect dec_brmask_logic.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect dec_brmask_logic.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect dec_brmask_logic.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect dec_brmask_logic.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect dec_brmask_logic.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect dec_brmask_logic.io.brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect dec_brmask_logic.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect dec_brmask_logic.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect dec_brmask_logic.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect dec_brmask_logic.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect dec_brmask_logic.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect dec_brmask_logic.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect dec_brmask_logic.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect dec_brmask_logic.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect dec_brmask_logic.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect dec_brmask_logic.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect dec_brmask_logic.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect dec_brmask_logic.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect dec_brmask_logic.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect dec_brmask_logic.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect dec_brmask_logic.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect dec_brmask_logic.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect dec_brmask_logic.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect dec_brmask_logic.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect dec_brmask_logic.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect dec_brmask_logic.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect dec_brmask_logic.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect dec_brmask_logic.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect dec_brmask_logic.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect dec_brmask_logic.io.brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect dec_brmask_logic.io.brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect dec_brmask_logic.io.brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect dec_brmask_logic.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect dec_brmask_logic.io.brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect dec_brmask_logic.io.brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect dec_brmask_logic.io.brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect dec_brmask_logic.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect dec_brmask_logic.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect dec_brmask_logic.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect dec_brmask_logic.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect dec_brmask_logic.io.brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect dec_brmask_logic.io.brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect dec_brmask_logic.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect dec_brmask_logic.io.brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect dec_brmask_logic.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect dec_brmask_logic.io.brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect dec_brmask_logic.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect dec_brmask_logic.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect dec_brmask_logic.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect dec_brmask_logic.io.brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect dec_brmask_logic.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect dec_brmask_logic.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect dec_brmask_logic.io.brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect dec_brmask_logic.io.brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect dec_brmask_logic.io.brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect dec_brmask_logic.io.brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect dec_brmask_logic.io.brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect dec_brmask_logic.io.brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect dec_brmask_logic.io.brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect dec_brmask_logic.io.brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect dec_brmask_logic.io.brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect dec_brmask_logic.io.brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect dec_brmask_logic.io.brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect dec_brmask_logic.io.brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect dec_brmask_logic.io.brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect dec_brmask_logic.io.brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect dec_brmask_logic.io.brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect dec_brmask_logic.io.brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect dec_brmask_logic.io.brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect dec_brmask_logic.io.brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect dec_brmask_logic.io.brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect dec_brmask_logic.io.brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect dec_brmask_logic.io.brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect dec_brmask_logic.io.brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect dec_brmask_logic.io.brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect dec_brmask_logic.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect dec_brmask_logic.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect dec_brmask_logic.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect dec_brmask_logic.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect dec_brmask_logic.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect dec_brmask_logic.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask reg dec_brmask_logic_io_flush_pipeline_REG : UInt<1>, clock connect dec_brmask_logic_io_flush_pipeline_REG, rob.io.flush.valid connect dec_brmask_logic.io.flush_pipeline, dec_brmask_logic_io_flush_pipeline_REG node _dec_brmask_logic_io_is_branch_0_T = bits(dec_finished_mask, 0, 0) node _dec_brmask_logic_io_is_branch_0_T_1 = eq(_dec_brmask_logic_io_is_branch_0_T, UInt<1>(0h0)) node _dec_brmask_logic_io_is_branch_0_T_2 = eq(dec_uops[0].br_type, UInt<4>(0h1)) node _dec_brmask_logic_io_is_branch_0_T_3 = eq(dec_uops[0].br_type, UInt<4>(0h2)) node _dec_brmask_logic_io_is_branch_0_T_4 = eq(dec_uops[0].br_type, UInt<4>(0h3)) node _dec_brmask_logic_io_is_branch_0_T_5 = eq(dec_uops[0].br_type, UInt<4>(0h4)) node _dec_brmask_logic_io_is_branch_0_T_6 = eq(dec_uops[0].br_type, UInt<4>(0h5)) node _dec_brmask_logic_io_is_branch_0_T_7 = eq(dec_uops[0].br_type, UInt<4>(0h6)) node _dec_brmask_logic_io_is_branch_0_T_8 = or(_dec_brmask_logic_io_is_branch_0_T_2, _dec_brmask_logic_io_is_branch_0_T_3) node _dec_brmask_logic_io_is_branch_0_T_9 = or(_dec_brmask_logic_io_is_branch_0_T_8, _dec_brmask_logic_io_is_branch_0_T_4) node _dec_brmask_logic_io_is_branch_0_T_10 = or(_dec_brmask_logic_io_is_branch_0_T_9, _dec_brmask_logic_io_is_branch_0_T_5) node _dec_brmask_logic_io_is_branch_0_T_11 = or(_dec_brmask_logic_io_is_branch_0_T_10, _dec_brmask_logic_io_is_branch_0_T_6) node _dec_brmask_logic_io_is_branch_0_T_12 = or(_dec_brmask_logic_io_is_branch_0_T_11, _dec_brmask_logic_io_is_branch_0_T_7) node _dec_brmask_logic_io_is_branch_0_T_13 = eq(dec_uops[0].is_sfb, UInt<1>(0h0)) node _dec_brmask_logic_io_is_branch_0_T_14 = and(_dec_brmask_logic_io_is_branch_0_T_12, _dec_brmask_logic_io_is_branch_0_T_13) node _dec_brmask_logic_io_is_branch_0_T_15 = eq(dec_uops[0].br_type, UInt<4>(0h8)) node _dec_brmask_logic_io_is_branch_0_T_16 = or(_dec_brmask_logic_io_is_branch_0_T_14, _dec_brmask_logic_io_is_branch_0_T_15) node _dec_brmask_logic_io_is_branch_0_T_17 = and(_dec_brmask_logic_io_is_branch_0_T_1, _dec_brmask_logic_io_is_branch_0_T_16) connect dec_brmask_logic.io.is_branch[0], _dec_brmask_logic_io_is_branch_0_T_17 node _dec_brmask_logic_io_will_fire_0_T = eq(dec_uops[0].br_type, UInt<4>(0h1)) node _dec_brmask_logic_io_will_fire_0_T_1 = eq(dec_uops[0].br_type, UInt<4>(0h2)) node _dec_brmask_logic_io_will_fire_0_T_2 = eq(dec_uops[0].br_type, UInt<4>(0h3)) node _dec_brmask_logic_io_will_fire_0_T_3 = eq(dec_uops[0].br_type, UInt<4>(0h4)) node _dec_brmask_logic_io_will_fire_0_T_4 = eq(dec_uops[0].br_type, UInt<4>(0h5)) node _dec_brmask_logic_io_will_fire_0_T_5 = eq(dec_uops[0].br_type, UInt<4>(0h6)) node _dec_brmask_logic_io_will_fire_0_T_6 = or(_dec_brmask_logic_io_will_fire_0_T, _dec_brmask_logic_io_will_fire_0_T_1) node _dec_brmask_logic_io_will_fire_0_T_7 = or(_dec_brmask_logic_io_will_fire_0_T_6, _dec_brmask_logic_io_will_fire_0_T_2) node _dec_brmask_logic_io_will_fire_0_T_8 = or(_dec_brmask_logic_io_will_fire_0_T_7, _dec_brmask_logic_io_will_fire_0_T_3) node _dec_brmask_logic_io_will_fire_0_T_9 = or(_dec_brmask_logic_io_will_fire_0_T_8, _dec_brmask_logic_io_will_fire_0_T_4) node _dec_brmask_logic_io_will_fire_0_T_10 = or(_dec_brmask_logic_io_will_fire_0_T_9, _dec_brmask_logic_io_will_fire_0_T_5) node _dec_brmask_logic_io_will_fire_0_T_11 = eq(dec_uops[0].is_sfb, UInt<1>(0h0)) node _dec_brmask_logic_io_will_fire_0_T_12 = and(_dec_brmask_logic_io_will_fire_0_T_10, _dec_brmask_logic_io_will_fire_0_T_11) node _dec_brmask_logic_io_will_fire_0_T_13 = eq(dec_uops[0].br_type, UInt<4>(0h8)) node _dec_brmask_logic_io_will_fire_0_T_14 = or(_dec_brmask_logic_io_will_fire_0_T_12, _dec_brmask_logic_io_will_fire_0_T_13) node _dec_brmask_logic_io_will_fire_0_T_15 = and(dec_fire[0], _dec_brmask_logic_io_will_fire_0_T_14) connect dec_brmask_logic.io.will_fire[0], _dec_brmask_logic_io_will_fire_0_T_15 connect dec_uops[0].br_tag, dec_brmask_logic.io.br_tag[0] connect dec_uops[0].br_mask, dec_brmask_logic.io.br_mask[0] node _dec_brmask_logic_io_is_branch_1_T = bits(dec_finished_mask, 1, 1) node _dec_brmask_logic_io_is_branch_1_T_1 = eq(_dec_brmask_logic_io_is_branch_1_T, UInt<1>(0h0)) node _dec_brmask_logic_io_is_branch_1_T_2 = eq(dec_uops[1].br_type, UInt<4>(0h1)) node _dec_brmask_logic_io_is_branch_1_T_3 = eq(dec_uops[1].br_type, UInt<4>(0h2)) node _dec_brmask_logic_io_is_branch_1_T_4 = eq(dec_uops[1].br_type, UInt<4>(0h3)) node _dec_brmask_logic_io_is_branch_1_T_5 = eq(dec_uops[1].br_type, UInt<4>(0h4)) node _dec_brmask_logic_io_is_branch_1_T_6 = eq(dec_uops[1].br_type, UInt<4>(0h5)) node _dec_brmask_logic_io_is_branch_1_T_7 = eq(dec_uops[1].br_type, UInt<4>(0h6)) node _dec_brmask_logic_io_is_branch_1_T_8 = or(_dec_brmask_logic_io_is_branch_1_T_2, _dec_brmask_logic_io_is_branch_1_T_3) node _dec_brmask_logic_io_is_branch_1_T_9 = or(_dec_brmask_logic_io_is_branch_1_T_8, _dec_brmask_logic_io_is_branch_1_T_4) node _dec_brmask_logic_io_is_branch_1_T_10 = or(_dec_brmask_logic_io_is_branch_1_T_9, _dec_brmask_logic_io_is_branch_1_T_5) node _dec_brmask_logic_io_is_branch_1_T_11 = or(_dec_brmask_logic_io_is_branch_1_T_10, _dec_brmask_logic_io_is_branch_1_T_6) node _dec_brmask_logic_io_is_branch_1_T_12 = or(_dec_brmask_logic_io_is_branch_1_T_11, _dec_brmask_logic_io_is_branch_1_T_7) node _dec_brmask_logic_io_is_branch_1_T_13 = eq(dec_uops[1].is_sfb, UInt<1>(0h0)) node _dec_brmask_logic_io_is_branch_1_T_14 = and(_dec_brmask_logic_io_is_branch_1_T_12, _dec_brmask_logic_io_is_branch_1_T_13) node _dec_brmask_logic_io_is_branch_1_T_15 = eq(dec_uops[1].br_type, UInt<4>(0h8)) node _dec_brmask_logic_io_is_branch_1_T_16 = or(_dec_brmask_logic_io_is_branch_1_T_14, _dec_brmask_logic_io_is_branch_1_T_15) node _dec_brmask_logic_io_is_branch_1_T_17 = and(_dec_brmask_logic_io_is_branch_1_T_1, _dec_brmask_logic_io_is_branch_1_T_16) connect dec_brmask_logic.io.is_branch[1], _dec_brmask_logic_io_is_branch_1_T_17 node _dec_brmask_logic_io_will_fire_1_T = eq(dec_uops[1].br_type, UInt<4>(0h1)) node _dec_brmask_logic_io_will_fire_1_T_1 = eq(dec_uops[1].br_type, UInt<4>(0h2)) node _dec_brmask_logic_io_will_fire_1_T_2 = eq(dec_uops[1].br_type, UInt<4>(0h3)) node _dec_brmask_logic_io_will_fire_1_T_3 = eq(dec_uops[1].br_type, UInt<4>(0h4)) node _dec_brmask_logic_io_will_fire_1_T_4 = eq(dec_uops[1].br_type, UInt<4>(0h5)) node _dec_brmask_logic_io_will_fire_1_T_5 = eq(dec_uops[1].br_type, UInt<4>(0h6)) node _dec_brmask_logic_io_will_fire_1_T_6 = or(_dec_brmask_logic_io_will_fire_1_T, _dec_brmask_logic_io_will_fire_1_T_1) node _dec_brmask_logic_io_will_fire_1_T_7 = or(_dec_brmask_logic_io_will_fire_1_T_6, _dec_brmask_logic_io_will_fire_1_T_2) node _dec_brmask_logic_io_will_fire_1_T_8 = or(_dec_brmask_logic_io_will_fire_1_T_7, _dec_brmask_logic_io_will_fire_1_T_3) node _dec_brmask_logic_io_will_fire_1_T_9 = or(_dec_brmask_logic_io_will_fire_1_T_8, _dec_brmask_logic_io_will_fire_1_T_4) node _dec_brmask_logic_io_will_fire_1_T_10 = or(_dec_brmask_logic_io_will_fire_1_T_9, _dec_brmask_logic_io_will_fire_1_T_5) node _dec_brmask_logic_io_will_fire_1_T_11 = eq(dec_uops[1].is_sfb, UInt<1>(0h0)) node _dec_brmask_logic_io_will_fire_1_T_12 = and(_dec_brmask_logic_io_will_fire_1_T_10, _dec_brmask_logic_io_will_fire_1_T_11) node _dec_brmask_logic_io_will_fire_1_T_13 = eq(dec_uops[1].br_type, UInt<4>(0h8)) node _dec_brmask_logic_io_will_fire_1_T_14 = or(_dec_brmask_logic_io_will_fire_1_T_12, _dec_brmask_logic_io_will_fire_1_T_13) node _dec_brmask_logic_io_will_fire_1_T_15 = and(dec_fire[1], _dec_brmask_logic_io_will_fire_1_T_14) connect dec_brmask_logic.io.will_fire[1], _dec_brmask_logic_io_will_fire_1_T_15 connect dec_uops[1].br_tag, dec_brmask_logic.io.br_tag[1] connect dec_uops[1].br_mask, dec_brmask_logic.io.br_mask[1] connect branch_mask_full, dec_brmask_logic.io.is_full connect rename_stage.io.kill, io.ifu.redirect_flush connect rename_stage.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect rename_stage.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect rename_stage.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect rename_stage.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect rename_stage.io.brupdate.b2.taken, brupdate.b2.taken connect rename_stage.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect rename_stage.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect rename_stage.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect rename_stage.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect rename_stage.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect rename_stage.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect rename_stage.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect rename_stage.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect rename_stage.io.brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect rename_stage.io.brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect rename_stage.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect rename_stage.io.brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect rename_stage.io.brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect rename_stage.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect rename_stage.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect rename_stage.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect rename_stage.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect rename_stage.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect rename_stage.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect rename_stage.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect rename_stage.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect rename_stage.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect rename_stage.io.brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect rename_stage.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect rename_stage.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect rename_stage.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect rename_stage.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect rename_stage.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect rename_stage.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect rename_stage.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect rename_stage.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect rename_stage.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect rename_stage.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect rename_stage.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect rename_stage.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect rename_stage.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect rename_stage.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect rename_stage.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect rename_stage.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect rename_stage.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect rename_stage.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect rename_stage.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect rename_stage.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect rename_stage.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect rename_stage.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect rename_stage.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect rename_stage.io.brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect rename_stage.io.brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect rename_stage.io.brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect rename_stage.io.brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect rename_stage.io.brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect rename_stage.io.brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect rename_stage.io.brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect rename_stage.io.brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect rename_stage.io.brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect rename_stage.io.brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect rename_stage.io.brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect rename_stage.io.brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect rename_stage.io.brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect rename_stage.io.brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect rename_stage.io.brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect rename_stage.io.brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect rename_stage.io.brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect rename_stage.io.brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect rename_stage.io.brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect rename_stage.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect rename_stage.io.brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect rename_stage.io.brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect rename_stage.io.brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect rename_stage.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect rename_stage.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect rename_stage.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect rename_stage.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect rename_stage.io.brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect rename_stage.io.brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect rename_stage.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect rename_stage.io.brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect rename_stage.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect rename_stage.io.brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect rename_stage.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect rename_stage.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect rename_stage.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect rename_stage.io.brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect rename_stage.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect rename_stage.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect rename_stage.io.brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect rename_stage.io.brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect rename_stage.io.brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect rename_stage.io.brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect rename_stage.io.brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect rename_stage.io.brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect rename_stage.io.brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect rename_stage.io.brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect rename_stage.io.brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect rename_stage.io.brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect rename_stage.io.brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect rename_stage.io.brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect rename_stage.io.brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect rename_stage.io.brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect rename_stage.io.brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect rename_stage.io.brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect rename_stage.io.brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect rename_stage.io.brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect rename_stage.io.brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect rename_stage.io.brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect rename_stage.io.brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect rename_stage.io.brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect rename_stage.io.brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect rename_stage.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect rename_stage.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect rename_stage.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect rename_stage.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect rename_stage.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect rename_stage.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect rename_stage.io.debug_rob_empty, rob.io.empty connect rename_stage.io.dec_fire[0], dec_fire[0] connect rename_stage.io.dec_fire[1], dec_fire[1] connect rename_stage.io.dec_uops[0].debug_tsrc, dec_uops[0].debug_tsrc connect rename_stage.io.dec_uops[0].debug_fsrc, dec_uops[0].debug_fsrc connect rename_stage.io.dec_uops[0].bp_xcpt_if, dec_uops[0].bp_xcpt_if connect rename_stage.io.dec_uops[0].bp_debug_if, dec_uops[0].bp_debug_if connect rename_stage.io.dec_uops[0].xcpt_ma_if, dec_uops[0].xcpt_ma_if connect rename_stage.io.dec_uops[0].xcpt_ae_if, dec_uops[0].xcpt_ae_if connect rename_stage.io.dec_uops[0].xcpt_pf_if, dec_uops[0].xcpt_pf_if connect rename_stage.io.dec_uops[0].fp_typ, dec_uops[0].fp_typ connect rename_stage.io.dec_uops[0].fp_rm, dec_uops[0].fp_rm connect rename_stage.io.dec_uops[0].fp_val, dec_uops[0].fp_val connect rename_stage.io.dec_uops[0].fcn_op, dec_uops[0].fcn_op connect rename_stage.io.dec_uops[0].fcn_dw, dec_uops[0].fcn_dw connect rename_stage.io.dec_uops[0].frs3_en, dec_uops[0].frs3_en connect rename_stage.io.dec_uops[0].lrs2_rtype, dec_uops[0].lrs2_rtype connect rename_stage.io.dec_uops[0].lrs1_rtype, dec_uops[0].lrs1_rtype connect rename_stage.io.dec_uops[0].dst_rtype, dec_uops[0].dst_rtype connect rename_stage.io.dec_uops[0].lrs3, dec_uops[0].lrs3 connect rename_stage.io.dec_uops[0].lrs2, dec_uops[0].lrs2 connect rename_stage.io.dec_uops[0].lrs1, dec_uops[0].lrs1 connect rename_stage.io.dec_uops[0].ldst, dec_uops[0].ldst connect rename_stage.io.dec_uops[0].ldst_is_rs1, dec_uops[0].ldst_is_rs1 connect rename_stage.io.dec_uops[0].csr_cmd, dec_uops[0].csr_cmd connect rename_stage.io.dec_uops[0].flush_on_commit, dec_uops[0].flush_on_commit connect rename_stage.io.dec_uops[0].is_unique, dec_uops[0].is_unique connect rename_stage.io.dec_uops[0].uses_stq, dec_uops[0].uses_stq connect rename_stage.io.dec_uops[0].uses_ldq, dec_uops[0].uses_ldq connect rename_stage.io.dec_uops[0].mem_signed, dec_uops[0].mem_signed connect rename_stage.io.dec_uops[0].mem_size, dec_uops[0].mem_size connect rename_stage.io.dec_uops[0].mem_cmd, dec_uops[0].mem_cmd connect rename_stage.io.dec_uops[0].exc_cause, dec_uops[0].exc_cause connect rename_stage.io.dec_uops[0].exception, dec_uops[0].exception connect rename_stage.io.dec_uops[0].stale_pdst, dec_uops[0].stale_pdst connect rename_stage.io.dec_uops[0].ppred_busy, dec_uops[0].ppred_busy connect rename_stage.io.dec_uops[0].prs3_busy, dec_uops[0].prs3_busy connect rename_stage.io.dec_uops[0].prs2_busy, dec_uops[0].prs2_busy connect rename_stage.io.dec_uops[0].prs1_busy, dec_uops[0].prs1_busy connect rename_stage.io.dec_uops[0].ppred, dec_uops[0].ppred connect rename_stage.io.dec_uops[0].prs3, dec_uops[0].prs3 connect rename_stage.io.dec_uops[0].prs2, dec_uops[0].prs2 connect rename_stage.io.dec_uops[0].prs1, dec_uops[0].prs1 connect rename_stage.io.dec_uops[0].pdst, dec_uops[0].pdst connect rename_stage.io.dec_uops[0].rxq_idx, dec_uops[0].rxq_idx connect rename_stage.io.dec_uops[0].stq_idx, dec_uops[0].stq_idx connect rename_stage.io.dec_uops[0].ldq_idx, dec_uops[0].ldq_idx connect rename_stage.io.dec_uops[0].rob_idx, dec_uops[0].rob_idx connect rename_stage.io.dec_uops[0].fp_ctrl.vec, dec_uops[0].fp_ctrl.vec connect rename_stage.io.dec_uops[0].fp_ctrl.wflags, dec_uops[0].fp_ctrl.wflags connect rename_stage.io.dec_uops[0].fp_ctrl.sqrt, dec_uops[0].fp_ctrl.sqrt connect rename_stage.io.dec_uops[0].fp_ctrl.div, dec_uops[0].fp_ctrl.div connect rename_stage.io.dec_uops[0].fp_ctrl.fma, dec_uops[0].fp_ctrl.fma connect rename_stage.io.dec_uops[0].fp_ctrl.fastpipe, dec_uops[0].fp_ctrl.fastpipe connect rename_stage.io.dec_uops[0].fp_ctrl.toint, dec_uops[0].fp_ctrl.toint connect rename_stage.io.dec_uops[0].fp_ctrl.fromint, dec_uops[0].fp_ctrl.fromint connect rename_stage.io.dec_uops[0].fp_ctrl.typeTagOut, dec_uops[0].fp_ctrl.typeTagOut connect rename_stage.io.dec_uops[0].fp_ctrl.typeTagIn, dec_uops[0].fp_ctrl.typeTagIn connect rename_stage.io.dec_uops[0].fp_ctrl.swap23, dec_uops[0].fp_ctrl.swap23 connect rename_stage.io.dec_uops[0].fp_ctrl.swap12, dec_uops[0].fp_ctrl.swap12 connect rename_stage.io.dec_uops[0].fp_ctrl.ren3, dec_uops[0].fp_ctrl.ren3 connect rename_stage.io.dec_uops[0].fp_ctrl.ren2, dec_uops[0].fp_ctrl.ren2 connect rename_stage.io.dec_uops[0].fp_ctrl.ren1, dec_uops[0].fp_ctrl.ren1 connect rename_stage.io.dec_uops[0].fp_ctrl.wen, dec_uops[0].fp_ctrl.wen connect rename_stage.io.dec_uops[0].fp_ctrl.ldst, dec_uops[0].fp_ctrl.ldst connect rename_stage.io.dec_uops[0].op2_sel, dec_uops[0].op2_sel connect rename_stage.io.dec_uops[0].op1_sel, dec_uops[0].op1_sel connect rename_stage.io.dec_uops[0].imm_packed, dec_uops[0].imm_packed connect rename_stage.io.dec_uops[0].pimm, dec_uops[0].pimm connect rename_stage.io.dec_uops[0].imm_sel, dec_uops[0].imm_sel connect rename_stage.io.dec_uops[0].imm_rename, dec_uops[0].imm_rename connect rename_stage.io.dec_uops[0].taken, dec_uops[0].taken connect rename_stage.io.dec_uops[0].pc_lob, dec_uops[0].pc_lob connect rename_stage.io.dec_uops[0].edge_inst, dec_uops[0].edge_inst connect rename_stage.io.dec_uops[0].ftq_idx, dec_uops[0].ftq_idx connect rename_stage.io.dec_uops[0].is_mov, dec_uops[0].is_mov connect rename_stage.io.dec_uops[0].is_rocc, dec_uops[0].is_rocc connect rename_stage.io.dec_uops[0].is_sys_pc2epc, dec_uops[0].is_sys_pc2epc connect rename_stage.io.dec_uops[0].is_eret, dec_uops[0].is_eret connect rename_stage.io.dec_uops[0].is_amo, dec_uops[0].is_amo connect rename_stage.io.dec_uops[0].is_sfence, dec_uops[0].is_sfence connect rename_stage.io.dec_uops[0].is_fencei, dec_uops[0].is_fencei connect rename_stage.io.dec_uops[0].is_fence, dec_uops[0].is_fence connect rename_stage.io.dec_uops[0].is_sfb, dec_uops[0].is_sfb connect rename_stage.io.dec_uops[0].br_type, dec_uops[0].br_type connect rename_stage.io.dec_uops[0].br_tag, dec_uops[0].br_tag connect rename_stage.io.dec_uops[0].br_mask, dec_uops[0].br_mask connect rename_stage.io.dec_uops[0].dis_col_sel, dec_uops[0].dis_col_sel connect rename_stage.io.dec_uops[0].iw_p3_bypass_hint, dec_uops[0].iw_p3_bypass_hint connect rename_stage.io.dec_uops[0].iw_p2_bypass_hint, dec_uops[0].iw_p2_bypass_hint connect rename_stage.io.dec_uops[0].iw_p1_bypass_hint, dec_uops[0].iw_p1_bypass_hint connect rename_stage.io.dec_uops[0].iw_p2_speculative_child, dec_uops[0].iw_p2_speculative_child connect rename_stage.io.dec_uops[0].iw_p1_speculative_child, dec_uops[0].iw_p1_speculative_child connect rename_stage.io.dec_uops[0].iw_issued_partial_dgen, dec_uops[0].iw_issued_partial_dgen connect rename_stage.io.dec_uops[0].iw_issued_partial_agen, dec_uops[0].iw_issued_partial_agen connect rename_stage.io.dec_uops[0].iw_issued, dec_uops[0].iw_issued connect rename_stage.io.dec_uops[0].fu_code[0], dec_uops[0].fu_code[0] connect rename_stage.io.dec_uops[0].fu_code[1], dec_uops[0].fu_code[1] connect rename_stage.io.dec_uops[0].fu_code[2], dec_uops[0].fu_code[2] connect rename_stage.io.dec_uops[0].fu_code[3], dec_uops[0].fu_code[3] connect rename_stage.io.dec_uops[0].fu_code[4], dec_uops[0].fu_code[4] connect rename_stage.io.dec_uops[0].fu_code[5], dec_uops[0].fu_code[5] connect rename_stage.io.dec_uops[0].fu_code[6], dec_uops[0].fu_code[6] connect rename_stage.io.dec_uops[0].fu_code[7], dec_uops[0].fu_code[7] connect rename_stage.io.dec_uops[0].fu_code[8], dec_uops[0].fu_code[8] connect rename_stage.io.dec_uops[0].fu_code[9], dec_uops[0].fu_code[9] connect rename_stage.io.dec_uops[0].iq_type[0], dec_uops[0].iq_type[0] connect rename_stage.io.dec_uops[0].iq_type[1], dec_uops[0].iq_type[1] connect rename_stage.io.dec_uops[0].iq_type[2], dec_uops[0].iq_type[2] connect rename_stage.io.dec_uops[0].iq_type[3], dec_uops[0].iq_type[3] connect rename_stage.io.dec_uops[0].debug_pc, dec_uops[0].debug_pc connect rename_stage.io.dec_uops[0].is_rvc, dec_uops[0].is_rvc connect rename_stage.io.dec_uops[0].debug_inst, dec_uops[0].debug_inst connect rename_stage.io.dec_uops[0].inst, dec_uops[0].inst connect rename_stage.io.dec_uops[1].debug_tsrc, dec_uops[1].debug_tsrc connect rename_stage.io.dec_uops[1].debug_fsrc, dec_uops[1].debug_fsrc connect rename_stage.io.dec_uops[1].bp_xcpt_if, dec_uops[1].bp_xcpt_if connect rename_stage.io.dec_uops[1].bp_debug_if, dec_uops[1].bp_debug_if connect rename_stage.io.dec_uops[1].xcpt_ma_if, dec_uops[1].xcpt_ma_if connect rename_stage.io.dec_uops[1].xcpt_ae_if, dec_uops[1].xcpt_ae_if connect rename_stage.io.dec_uops[1].xcpt_pf_if, dec_uops[1].xcpt_pf_if connect rename_stage.io.dec_uops[1].fp_typ, dec_uops[1].fp_typ connect rename_stage.io.dec_uops[1].fp_rm, dec_uops[1].fp_rm connect rename_stage.io.dec_uops[1].fp_val, dec_uops[1].fp_val connect rename_stage.io.dec_uops[1].fcn_op, dec_uops[1].fcn_op connect rename_stage.io.dec_uops[1].fcn_dw, dec_uops[1].fcn_dw connect rename_stage.io.dec_uops[1].frs3_en, dec_uops[1].frs3_en connect rename_stage.io.dec_uops[1].lrs2_rtype, dec_uops[1].lrs2_rtype connect rename_stage.io.dec_uops[1].lrs1_rtype, dec_uops[1].lrs1_rtype connect rename_stage.io.dec_uops[1].dst_rtype, dec_uops[1].dst_rtype connect rename_stage.io.dec_uops[1].lrs3, dec_uops[1].lrs3 connect rename_stage.io.dec_uops[1].lrs2, dec_uops[1].lrs2 connect rename_stage.io.dec_uops[1].lrs1, dec_uops[1].lrs1 connect rename_stage.io.dec_uops[1].ldst, dec_uops[1].ldst connect rename_stage.io.dec_uops[1].ldst_is_rs1, dec_uops[1].ldst_is_rs1 connect rename_stage.io.dec_uops[1].csr_cmd, dec_uops[1].csr_cmd connect rename_stage.io.dec_uops[1].flush_on_commit, dec_uops[1].flush_on_commit connect rename_stage.io.dec_uops[1].is_unique, dec_uops[1].is_unique connect rename_stage.io.dec_uops[1].uses_stq, dec_uops[1].uses_stq connect rename_stage.io.dec_uops[1].uses_ldq, dec_uops[1].uses_ldq connect rename_stage.io.dec_uops[1].mem_signed, dec_uops[1].mem_signed connect rename_stage.io.dec_uops[1].mem_size, dec_uops[1].mem_size connect rename_stage.io.dec_uops[1].mem_cmd, dec_uops[1].mem_cmd connect rename_stage.io.dec_uops[1].exc_cause, dec_uops[1].exc_cause connect rename_stage.io.dec_uops[1].exception, dec_uops[1].exception connect rename_stage.io.dec_uops[1].stale_pdst, dec_uops[1].stale_pdst connect rename_stage.io.dec_uops[1].ppred_busy, dec_uops[1].ppred_busy connect rename_stage.io.dec_uops[1].prs3_busy, dec_uops[1].prs3_busy connect rename_stage.io.dec_uops[1].prs2_busy, dec_uops[1].prs2_busy connect rename_stage.io.dec_uops[1].prs1_busy, dec_uops[1].prs1_busy connect rename_stage.io.dec_uops[1].ppred, dec_uops[1].ppred connect rename_stage.io.dec_uops[1].prs3, dec_uops[1].prs3 connect rename_stage.io.dec_uops[1].prs2, dec_uops[1].prs2 connect rename_stage.io.dec_uops[1].prs1, dec_uops[1].prs1 connect rename_stage.io.dec_uops[1].pdst, dec_uops[1].pdst connect rename_stage.io.dec_uops[1].rxq_idx, dec_uops[1].rxq_idx connect rename_stage.io.dec_uops[1].stq_idx, dec_uops[1].stq_idx connect rename_stage.io.dec_uops[1].ldq_idx, dec_uops[1].ldq_idx connect rename_stage.io.dec_uops[1].rob_idx, dec_uops[1].rob_idx connect rename_stage.io.dec_uops[1].fp_ctrl.vec, dec_uops[1].fp_ctrl.vec connect rename_stage.io.dec_uops[1].fp_ctrl.wflags, dec_uops[1].fp_ctrl.wflags connect rename_stage.io.dec_uops[1].fp_ctrl.sqrt, dec_uops[1].fp_ctrl.sqrt connect rename_stage.io.dec_uops[1].fp_ctrl.div, dec_uops[1].fp_ctrl.div connect rename_stage.io.dec_uops[1].fp_ctrl.fma, dec_uops[1].fp_ctrl.fma connect rename_stage.io.dec_uops[1].fp_ctrl.fastpipe, dec_uops[1].fp_ctrl.fastpipe connect rename_stage.io.dec_uops[1].fp_ctrl.toint, dec_uops[1].fp_ctrl.toint connect rename_stage.io.dec_uops[1].fp_ctrl.fromint, dec_uops[1].fp_ctrl.fromint connect rename_stage.io.dec_uops[1].fp_ctrl.typeTagOut, dec_uops[1].fp_ctrl.typeTagOut connect rename_stage.io.dec_uops[1].fp_ctrl.typeTagIn, dec_uops[1].fp_ctrl.typeTagIn connect rename_stage.io.dec_uops[1].fp_ctrl.swap23, dec_uops[1].fp_ctrl.swap23 connect rename_stage.io.dec_uops[1].fp_ctrl.swap12, dec_uops[1].fp_ctrl.swap12 connect rename_stage.io.dec_uops[1].fp_ctrl.ren3, dec_uops[1].fp_ctrl.ren3 connect rename_stage.io.dec_uops[1].fp_ctrl.ren2, dec_uops[1].fp_ctrl.ren2 connect rename_stage.io.dec_uops[1].fp_ctrl.ren1, dec_uops[1].fp_ctrl.ren1 connect rename_stage.io.dec_uops[1].fp_ctrl.wen, dec_uops[1].fp_ctrl.wen connect rename_stage.io.dec_uops[1].fp_ctrl.ldst, dec_uops[1].fp_ctrl.ldst connect rename_stage.io.dec_uops[1].op2_sel, dec_uops[1].op2_sel connect rename_stage.io.dec_uops[1].op1_sel, dec_uops[1].op1_sel connect rename_stage.io.dec_uops[1].imm_packed, dec_uops[1].imm_packed connect rename_stage.io.dec_uops[1].pimm, dec_uops[1].pimm connect rename_stage.io.dec_uops[1].imm_sel, dec_uops[1].imm_sel connect rename_stage.io.dec_uops[1].imm_rename, dec_uops[1].imm_rename connect rename_stage.io.dec_uops[1].taken, dec_uops[1].taken connect rename_stage.io.dec_uops[1].pc_lob, dec_uops[1].pc_lob connect rename_stage.io.dec_uops[1].edge_inst, dec_uops[1].edge_inst connect rename_stage.io.dec_uops[1].ftq_idx, dec_uops[1].ftq_idx connect rename_stage.io.dec_uops[1].is_mov, dec_uops[1].is_mov connect rename_stage.io.dec_uops[1].is_rocc, dec_uops[1].is_rocc connect rename_stage.io.dec_uops[1].is_sys_pc2epc, dec_uops[1].is_sys_pc2epc connect rename_stage.io.dec_uops[1].is_eret, dec_uops[1].is_eret connect rename_stage.io.dec_uops[1].is_amo, dec_uops[1].is_amo connect rename_stage.io.dec_uops[1].is_sfence, dec_uops[1].is_sfence connect rename_stage.io.dec_uops[1].is_fencei, dec_uops[1].is_fencei connect rename_stage.io.dec_uops[1].is_fence, dec_uops[1].is_fence connect rename_stage.io.dec_uops[1].is_sfb, dec_uops[1].is_sfb connect rename_stage.io.dec_uops[1].br_type, dec_uops[1].br_type connect rename_stage.io.dec_uops[1].br_tag, dec_uops[1].br_tag connect rename_stage.io.dec_uops[1].br_mask, dec_uops[1].br_mask connect rename_stage.io.dec_uops[1].dis_col_sel, dec_uops[1].dis_col_sel connect rename_stage.io.dec_uops[1].iw_p3_bypass_hint, dec_uops[1].iw_p3_bypass_hint connect rename_stage.io.dec_uops[1].iw_p2_bypass_hint, dec_uops[1].iw_p2_bypass_hint connect rename_stage.io.dec_uops[1].iw_p1_bypass_hint, dec_uops[1].iw_p1_bypass_hint connect rename_stage.io.dec_uops[1].iw_p2_speculative_child, dec_uops[1].iw_p2_speculative_child connect rename_stage.io.dec_uops[1].iw_p1_speculative_child, dec_uops[1].iw_p1_speculative_child connect rename_stage.io.dec_uops[1].iw_issued_partial_dgen, dec_uops[1].iw_issued_partial_dgen connect rename_stage.io.dec_uops[1].iw_issued_partial_agen, dec_uops[1].iw_issued_partial_agen connect rename_stage.io.dec_uops[1].iw_issued, dec_uops[1].iw_issued connect rename_stage.io.dec_uops[1].fu_code[0], dec_uops[1].fu_code[0] connect rename_stage.io.dec_uops[1].fu_code[1], dec_uops[1].fu_code[1] connect rename_stage.io.dec_uops[1].fu_code[2], dec_uops[1].fu_code[2] connect rename_stage.io.dec_uops[1].fu_code[3], dec_uops[1].fu_code[3] connect rename_stage.io.dec_uops[1].fu_code[4], dec_uops[1].fu_code[4] connect rename_stage.io.dec_uops[1].fu_code[5], dec_uops[1].fu_code[5] connect rename_stage.io.dec_uops[1].fu_code[6], dec_uops[1].fu_code[6] connect rename_stage.io.dec_uops[1].fu_code[7], dec_uops[1].fu_code[7] connect rename_stage.io.dec_uops[1].fu_code[8], dec_uops[1].fu_code[8] connect rename_stage.io.dec_uops[1].fu_code[9], dec_uops[1].fu_code[9] connect rename_stage.io.dec_uops[1].iq_type[0], dec_uops[1].iq_type[0] connect rename_stage.io.dec_uops[1].iq_type[1], dec_uops[1].iq_type[1] connect rename_stage.io.dec_uops[1].iq_type[2], dec_uops[1].iq_type[2] connect rename_stage.io.dec_uops[1].iq_type[3], dec_uops[1].iq_type[3] connect rename_stage.io.dec_uops[1].debug_pc, dec_uops[1].debug_pc connect rename_stage.io.dec_uops[1].is_rvc, dec_uops[1].is_rvc connect rename_stage.io.dec_uops[1].debug_inst, dec_uops[1].debug_inst connect rename_stage.io.dec_uops[1].inst, dec_uops[1].inst connect rename_stage.io.dis_fire[0], dis_fire[0] connect rename_stage.io.dis_fire[1], dis_fire[1] connect rename_stage.io.dis_ready, dis_ready connect rename_stage.io.com_valids[0], rob.io.commit.valids[0] connect rename_stage.io.com_valids[1], rob.io.commit.valids[1] connect rename_stage.io.com_uops[0].debug_tsrc, rob.io.commit.uops[0].debug_tsrc connect rename_stage.io.com_uops[0].debug_fsrc, rob.io.commit.uops[0].debug_fsrc connect rename_stage.io.com_uops[0].bp_xcpt_if, rob.io.commit.uops[0].bp_xcpt_if connect rename_stage.io.com_uops[0].bp_debug_if, rob.io.commit.uops[0].bp_debug_if connect rename_stage.io.com_uops[0].xcpt_ma_if, rob.io.commit.uops[0].xcpt_ma_if connect rename_stage.io.com_uops[0].xcpt_ae_if, rob.io.commit.uops[0].xcpt_ae_if connect rename_stage.io.com_uops[0].xcpt_pf_if, rob.io.commit.uops[0].xcpt_pf_if connect rename_stage.io.com_uops[0].fp_typ, rob.io.commit.uops[0].fp_typ connect rename_stage.io.com_uops[0].fp_rm, rob.io.commit.uops[0].fp_rm connect rename_stage.io.com_uops[0].fp_val, rob.io.commit.uops[0].fp_val connect rename_stage.io.com_uops[0].fcn_op, rob.io.commit.uops[0].fcn_op connect rename_stage.io.com_uops[0].fcn_dw, rob.io.commit.uops[0].fcn_dw connect rename_stage.io.com_uops[0].frs3_en, rob.io.commit.uops[0].frs3_en connect rename_stage.io.com_uops[0].lrs2_rtype, rob.io.commit.uops[0].lrs2_rtype connect rename_stage.io.com_uops[0].lrs1_rtype, rob.io.commit.uops[0].lrs1_rtype connect rename_stage.io.com_uops[0].dst_rtype, rob.io.commit.uops[0].dst_rtype connect rename_stage.io.com_uops[0].lrs3, rob.io.commit.uops[0].lrs3 connect rename_stage.io.com_uops[0].lrs2, rob.io.commit.uops[0].lrs2 connect rename_stage.io.com_uops[0].lrs1, rob.io.commit.uops[0].lrs1 connect rename_stage.io.com_uops[0].ldst, rob.io.commit.uops[0].ldst connect rename_stage.io.com_uops[0].ldst_is_rs1, rob.io.commit.uops[0].ldst_is_rs1 connect rename_stage.io.com_uops[0].csr_cmd, rob.io.commit.uops[0].csr_cmd connect rename_stage.io.com_uops[0].flush_on_commit, rob.io.commit.uops[0].flush_on_commit connect rename_stage.io.com_uops[0].is_unique, rob.io.commit.uops[0].is_unique connect rename_stage.io.com_uops[0].uses_stq, rob.io.commit.uops[0].uses_stq connect rename_stage.io.com_uops[0].uses_ldq, rob.io.commit.uops[0].uses_ldq connect rename_stage.io.com_uops[0].mem_signed, rob.io.commit.uops[0].mem_signed connect rename_stage.io.com_uops[0].mem_size, rob.io.commit.uops[0].mem_size connect rename_stage.io.com_uops[0].mem_cmd, rob.io.commit.uops[0].mem_cmd connect rename_stage.io.com_uops[0].exc_cause, rob.io.commit.uops[0].exc_cause connect rename_stage.io.com_uops[0].exception, rob.io.commit.uops[0].exception connect rename_stage.io.com_uops[0].stale_pdst, rob.io.commit.uops[0].stale_pdst connect rename_stage.io.com_uops[0].ppred_busy, rob.io.commit.uops[0].ppred_busy connect rename_stage.io.com_uops[0].prs3_busy, rob.io.commit.uops[0].prs3_busy connect rename_stage.io.com_uops[0].prs2_busy, rob.io.commit.uops[0].prs2_busy connect rename_stage.io.com_uops[0].prs1_busy, rob.io.commit.uops[0].prs1_busy connect rename_stage.io.com_uops[0].ppred, rob.io.commit.uops[0].ppred connect rename_stage.io.com_uops[0].prs3, rob.io.commit.uops[0].prs3 connect rename_stage.io.com_uops[0].prs2, rob.io.commit.uops[0].prs2 connect rename_stage.io.com_uops[0].prs1, rob.io.commit.uops[0].prs1 connect rename_stage.io.com_uops[0].pdst, rob.io.commit.uops[0].pdst connect rename_stage.io.com_uops[0].rxq_idx, rob.io.commit.uops[0].rxq_idx connect rename_stage.io.com_uops[0].stq_idx, rob.io.commit.uops[0].stq_idx connect rename_stage.io.com_uops[0].ldq_idx, rob.io.commit.uops[0].ldq_idx connect rename_stage.io.com_uops[0].rob_idx, rob.io.commit.uops[0].rob_idx connect rename_stage.io.com_uops[0].fp_ctrl.vec, rob.io.commit.uops[0].fp_ctrl.vec connect rename_stage.io.com_uops[0].fp_ctrl.wflags, rob.io.commit.uops[0].fp_ctrl.wflags connect rename_stage.io.com_uops[0].fp_ctrl.sqrt, rob.io.commit.uops[0].fp_ctrl.sqrt connect rename_stage.io.com_uops[0].fp_ctrl.div, rob.io.commit.uops[0].fp_ctrl.div connect rename_stage.io.com_uops[0].fp_ctrl.fma, rob.io.commit.uops[0].fp_ctrl.fma connect rename_stage.io.com_uops[0].fp_ctrl.fastpipe, rob.io.commit.uops[0].fp_ctrl.fastpipe connect rename_stage.io.com_uops[0].fp_ctrl.toint, rob.io.commit.uops[0].fp_ctrl.toint connect rename_stage.io.com_uops[0].fp_ctrl.fromint, rob.io.commit.uops[0].fp_ctrl.fromint connect rename_stage.io.com_uops[0].fp_ctrl.typeTagOut, rob.io.commit.uops[0].fp_ctrl.typeTagOut connect rename_stage.io.com_uops[0].fp_ctrl.typeTagIn, rob.io.commit.uops[0].fp_ctrl.typeTagIn connect rename_stage.io.com_uops[0].fp_ctrl.swap23, rob.io.commit.uops[0].fp_ctrl.swap23 connect rename_stage.io.com_uops[0].fp_ctrl.swap12, rob.io.commit.uops[0].fp_ctrl.swap12 connect rename_stage.io.com_uops[0].fp_ctrl.ren3, rob.io.commit.uops[0].fp_ctrl.ren3 connect rename_stage.io.com_uops[0].fp_ctrl.ren2, rob.io.commit.uops[0].fp_ctrl.ren2 connect rename_stage.io.com_uops[0].fp_ctrl.ren1, rob.io.commit.uops[0].fp_ctrl.ren1 connect rename_stage.io.com_uops[0].fp_ctrl.wen, rob.io.commit.uops[0].fp_ctrl.wen connect rename_stage.io.com_uops[0].fp_ctrl.ldst, rob.io.commit.uops[0].fp_ctrl.ldst connect rename_stage.io.com_uops[0].op2_sel, rob.io.commit.uops[0].op2_sel connect rename_stage.io.com_uops[0].op1_sel, rob.io.commit.uops[0].op1_sel connect rename_stage.io.com_uops[0].imm_packed, rob.io.commit.uops[0].imm_packed connect rename_stage.io.com_uops[0].pimm, rob.io.commit.uops[0].pimm connect rename_stage.io.com_uops[0].imm_sel, rob.io.commit.uops[0].imm_sel connect rename_stage.io.com_uops[0].imm_rename, rob.io.commit.uops[0].imm_rename connect rename_stage.io.com_uops[0].taken, rob.io.commit.uops[0].taken connect rename_stage.io.com_uops[0].pc_lob, rob.io.commit.uops[0].pc_lob connect rename_stage.io.com_uops[0].edge_inst, rob.io.commit.uops[0].edge_inst connect rename_stage.io.com_uops[0].ftq_idx, rob.io.commit.uops[0].ftq_idx connect rename_stage.io.com_uops[0].is_mov, rob.io.commit.uops[0].is_mov connect rename_stage.io.com_uops[0].is_rocc, rob.io.commit.uops[0].is_rocc connect rename_stage.io.com_uops[0].is_sys_pc2epc, rob.io.commit.uops[0].is_sys_pc2epc connect rename_stage.io.com_uops[0].is_eret, rob.io.commit.uops[0].is_eret connect rename_stage.io.com_uops[0].is_amo, rob.io.commit.uops[0].is_amo connect rename_stage.io.com_uops[0].is_sfence, rob.io.commit.uops[0].is_sfence connect rename_stage.io.com_uops[0].is_fencei, rob.io.commit.uops[0].is_fencei connect rename_stage.io.com_uops[0].is_fence, rob.io.commit.uops[0].is_fence connect rename_stage.io.com_uops[0].is_sfb, rob.io.commit.uops[0].is_sfb connect rename_stage.io.com_uops[0].br_type, rob.io.commit.uops[0].br_type connect rename_stage.io.com_uops[0].br_tag, rob.io.commit.uops[0].br_tag connect rename_stage.io.com_uops[0].br_mask, rob.io.commit.uops[0].br_mask connect rename_stage.io.com_uops[0].dis_col_sel, rob.io.commit.uops[0].dis_col_sel connect rename_stage.io.com_uops[0].iw_p3_bypass_hint, rob.io.commit.uops[0].iw_p3_bypass_hint connect rename_stage.io.com_uops[0].iw_p2_bypass_hint, rob.io.commit.uops[0].iw_p2_bypass_hint connect rename_stage.io.com_uops[0].iw_p1_bypass_hint, rob.io.commit.uops[0].iw_p1_bypass_hint connect rename_stage.io.com_uops[0].iw_p2_speculative_child, rob.io.commit.uops[0].iw_p2_speculative_child connect rename_stage.io.com_uops[0].iw_p1_speculative_child, rob.io.commit.uops[0].iw_p1_speculative_child connect rename_stage.io.com_uops[0].iw_issued_partial_dgen, rob.io.commit.uops[0].iw_issued_partial_dgen connect rename_stage.io.com_uops[0].iw_issued_partial_agen, rob.io.commit.uops[0].iw_issued_partial_agen connect rename_stage.io.com_uops[0].iw_issued, rob.io.commit.uops[0].iw_issued connect rename_stage.io.com_uops[0].fu_code[0], rob.io.commit.uops[0].fu_code[0] connect rename_stage.io.com_uops[0].fu_code[1], rob.io.commit.uops[0].fu_code[1] connect rename_stage.io.com_uops[0].fu_code[2], rob.io.commit.uops[0].fu_code[2] connect rename_stage.io.com_uops[0].fu_code[3], rob.io.commit.uops[0].fu_code[3] connect rename_stage.io.com_uops[0].fu_code[4], rob.io.commit.uops[0].fu_code[4] connect rename_stage.io.com_uops[0].fu_code[5], rob.io.commit.uops[0].fu_code[5] connect rename_stage.io.com_uops[0].fu_code[6], rob.io.commit.uops[0].fu_code[6] connect rename_stage.io.com_uops[0].fu_code[7], rob.io.commit.uops[0].fu_code[7] connect rename_stage.io.com_uops[0].fu_code[8], rob.io.commit.uops[0].fu_code[8] connect rename_stage.io.com_uops[0].fu_code[9], rob.io.commit.uops[0].fu_code[9] connect rename_stage.io.com_uops[0].iq_type[0], rob.io.commit.uops[0].iq_type[0] connect rename_stage.io.com_uops[0].iq_type[1], rob.io.commit.uops[0].iq_type[1] connect rename_stage.io.com_uops[0].iq_type[2], rob.io.commit.uops[0].iq_type[2] connect rename_stage.io.com_uops[0].iq_type[3], rob.io.commit.uops[0].iq_type[3] connect rename_stage.io.com_uops[0].debug_pc, rob.io.commit.uops[0].debug_pc connect rename_stage.io.com_uops[0].is_rvc, rob.io.commit.uops[0].is_rvc connect rename_stage.io.com_uops[0].debug_inst, rob.io.commit.uops[0].debug_inst connect rename_stage.io.com_uops[0].inst, rob.io.commit.uops[0].inst connect rename_stage.io.com_uops[1].debug_tsrc, rob.io.commit.uops[1].debug_tsrc connect rename_stage.io.com_uops[1].debug_fsrc, rob.io.commit.uops[1].debug_fsrc connect rename_stage.io.com_uops[1].bp_xcpt_if, rob.io.commit.uops[1].bp_xcpt_if connect rename_stage.io.com_uops[1].bp_debug_if, rob.io.commit.uops[1].bp_debug_if connect rename_stage.io.com_uops[1].xcpt_ma_if, rob.io.commit.uops[1].xcpt_ma_if connect rename_stage.io.com_uops[1].xcpt_ae_if, rob.io.commit.uops[1].xcpt_ae_if connect rename_stage.io.com_uops[1].xcpt_pf_if, rob.io.commit.uops[1].xcpt_pf_if connect rename_stage.io.com_uops[1].fp_typ, rob.io.commit.uops[1].fp_typ connect rename_stage.io.com_uops[1].fp_rm, rob.io.commit.uops[1].fp_rm connect rename_stage.io.com_uops[1].fp_val, rob.io.commit.uops[1].fp_val connect rename_stage.io.com_uops[1].fcn_op, rob.io.commit.uops[1].fcn_op connect rename_stage.io.com_uops[1].fcn_dw, rob.io.commit.uops[1].fcn_dw connect rename_stage.io.com_uops[1].frs3_en, rob.io.commit.uops[1].frs3_en connect rename_stage.io.com_uops[1].lrs2_rtype, rob.io.commit.uops[1].lrs2_rtype connect rename_stage.io.com_uops[1].lrs1_rtype, rob.io.commit.uops[1].lrs1_rtype connect rename_stage.io.com_uops[1].dst_rtype, rob.io.commit.uops[1].dst_rtype connect rename_stage.io.com_uops[1].lrs3, rob.io.commit.uops[1].lrs3 connect rename_stage.io.com_uops[1].lrs2, rob.io.commit.uops[1].lrs2 connect rename_stage.io.com_uops[1].lrs1, rob.io.commit.uops[1].lrs1 connect rename_stage.io.com_uops[1].ldst, rob.io.commit.uops[1].ldst connect rename_stage.io.com_uops[1].ldst_is_rs1, rob.io.commit.uops[1].ldst_is_rs1 connect rename_stage.io.com_uops[1].csr_cmd, rob.io.commit.uops[1].csr_cmd connect rename_stage.io.com_uops[1].flush_on_commit, rob.io.commit.uops[1].flush_on_commit connect rename_stage.io.com_uops[1].is_unique, rob.io.commit.uops[1].is_unique connect rename_stage.io.com_uops[1].uses_stq, rob.io.commit.uops[1].uses_stq connect rename_stage.io.com_uops[1].uses_ldq, rob.io.commit.uops[1].uses_ldq connect rename_stage.io.com_uops[1].mem_signed, rob.io.commit.uops[1].mem_signed connect rename_stage.io.com_uops[1].mem_size, rob.io.commit.uops[1].mem_size connect rename_stage.io.com_uops[1].mem_cmd, rob.io.commit.uops[1].mem_cmd connect rename_stage.io.com_uops[1].exc_cause, rob.io.commit.uops[1].exc_cause connect rename_stage.io.com_uops[1].exception, rob.io.commit.uops[1].exception connect rename_stage.io.com_uops[1].stale_pdst, rob.io.commit.uops[1].stale_pdst connect rename_stage.io.com_uops[1].ppred_busy, rob.io.commit.uops[1].ppred_busy connect rename_stage.io.com_uops[1].prs3_busy, rob.io.commit.uops[1].prs3_busy connect rename_stage.io.com_uops[1].prs2_busy, rob.io.commit.uops[1].prs2_busy connect rename_stage.io.com_uops[1].prs1_busy, rob.io.commit.uops[1].prs1_busy connect rename_stage.io.com_uops[1].ppred, rob.io.commit.uops[1].ppred connect rename_stage.io.com_uops[1].prs3, rob.io.commit.uops[1].prs3 connect rename_stage.io.com_uops[1].prs2, rob.io.commit.uops[1].prs2 connect rename_stage.io.com_uops[1].prs1, rob.io.commit.uops[1].prs1 connect rename_stage.io.com_uops[1].pdst, rob.io.commit.uops[1].pdst connect rename_stage.io.com_uops[1].rxq_idx, rob.io.commit.uops[1].rxq_idx connect rename_stage.io.com_uops[1].stq_idx, rob.io.commit.uops[1].stq_idx connect rename_stage.io.com_uops[1].ldq_idx, rob.io.commit.uops[1].ldq_idx connect rename_stage.io.com_uops[1].rob_idx, rob.io.commit.uops[1].rob_idx connect rename_stage.io.com_uops[1].fp_ctrl.vec, rob.io.commit.uops[1].fp_ctrl.vec connect rename_stage.io.com_uops[1].fp_ctrl.wflags, rob.io.commit.uops[1].fp_ctrl.wflags connect rename_stage.io.com_uops[1].fp_ctrl.sqrt, rob.io.commit.uops[1].fp_ctrl.sqrt connect rename_stage.io.com_uops[1].fp_ctrl.div, rob.io.commit.uops[1].fp_ctrl.div connect rename_stage.io.com_uops[1].fp_ctrl.fma, rob.io.commit.uops[1].fp_ctrl.fma connect rename_stage.io.com_uops[1].fp_ctrl.fastpipe, rob.io.commit.uops[1].fp_ctrl.fastpipe connect rename_stage.io.com_uops[1].fp_ctrl.toint, rob.io.commit.uops[1].fp_ctrl.toint connect rename_stage.io.com_uops[1].fp_ctrl.fromint, rob.io.commit.uops[1].fp_ctrl.fromint connect rename_stage.io.com_uops[1].fp_ctrl.typeTagOut, rob.io.commit.uops[1].fp_ctrl.typeTagOut connect rename_stage.io.com_uops[1].fp_ctrl.typeTagIn, rob.io.commit.uops[1].fp_ctrl.typeTagIn connect rename_stage.io.com_uops[1].fp_ctrl.swap23, rob.io.commit.uops[1].fp_ctrl.swap23 connect rename_stage.io.com_uops[1].fp_ctrl.swap12, rob.io.commit.uops[1].fp_ctrl.swap12 connect rename_stage.io.com_uops[1].fp_ctrl.ren3, rob.io.commit.uops[1].fp_ctrl.ren3 connect rename_stage.io.com_uops[1].fp_ctrl.ren2, rob.io.commit.uops[1].fp_ctrl.ren2 connect rename_stage.io.com_uops[1].fp_ctrl.ren1, rob.io.commit.uops[1].fp_ctrl.ren1 connect rename_stage.io.com_uops[1].fp_ctrl.wen, rob.io.commit.uops[1].fp_ctrl.wen connect rename_stage.io.com_uops[1].fp_ctrl.ldst, rob.io.commit.uops[1].fp_ctrl.ldst connect rename_stage.io.com_uops[1].op2_sel, rob.io.commit.uops[1].op2_sel connect rename_stage.io.com_uops[1].op1_sel, rob.io.commit.uops[1].op1_sel connect rename_stage.io.com_uops[1].imm_packed, rob.io.commit.uops[1].imm_packed connect rename_stage.io.com_uops[1].pimm, rob.io.commit.uops[1].pimm connect rename_stage.io.com_uops[1].imm_sel, rob.io.commit.uops[1].imm_sel connect rename_stage.io.com_uops[1].imm_rename, rob.io.commit.uops[1].imm_rename connect rename_stage.io.com_uops[1].taken, rob.io.commit.uops[1].taken connect rename_stage.io.com_uops[1].pc_lob, rob.io.commit.uops[1].pc_lob connect rename_stage.io.com_uops[1].edge_inst, rob.io.commit.uops[1].edge_inst connect rename_stage.io.com_uops[1].ftq_idx, rob.io.commit.uops[1].ftq_idx connect rename_stage.io.com_uops[1].is_mov, rob.io.commit.uops[1].is_mov connect rename_stage.io.com_uops[1].is_rocc, rob.io.commit.uops[1].is_rocc connect rename_stage.io.com_uops[1].is_sys_pc2epc, rob.io.commit.uops[1].is_sys_pc2epc connect rename_stage.io.com_uops[1].is_eret, rob.io.commit.uops[1].is_eret connect rename_stage.io.com_uops[1].is_amo, rob.io.commit.uops[1].is_amo connect rename_stage.io.com_uops[1].is_sfence, rob.io.commit.uops[1].is_sfence connect rename_stage.io.com_uops[1].is_fencei, rob.io.commit.uops[1].is_fencei connect rename_stage.io.com_uops[1].is_fence, rob.io.commit.uops[1].is_fence connect rename_stage.io.com_uops[1].is_sfb, rob.io.commit.uops[1].is_sfb connect rename_stage.io.com_uops[1].br_type, rob.io.commit.uops[1].br_type connect rename_stage.io.com_uops[1].br_tag, rob.io.commit.uops[1].br_tag connect rename_stage.io.com_uops[1].br_mask, rob.io.commit.uops[1].br_mask connect rename_stage.io.com_uops[1].dis_col_sel, rob.io.commit.uops[1].dis_col_sel connect rename_stage.io.com_uops[1].iw_p3_bypass_hint, rob.io.commit.uops[1].iw_p3_bypass_hint connect rename_stage.io.com_uops[1].iw_p2_bypass_hint, rob.io.commit.uops[1].iw_p2_bypass_hint connect rename_stage.io.com_uops[1].iw_p1_bypass_hint, rob.io.commit.uops[1].iw_p1_bypass_hint connect rename_stage.io.com_uops[1].iw_p2_speculative_child, rob.io.commit.uops[1].iw_p2_speculative_child connect rename_stage.io.com_uops[1].iw_p1_speculative_child, rob.io.commit.uops[1].iw_p1_speculative_child connect rename_stage.io.com_uops[1].iw_issued_partial_dgen, rob.io.commit.uops[1].iw_issued_partial_dgen connect rename_stage.io.com_uops[1].iw_issued_partial_agen, rob.io.commit.uops[1].iw_issued_partial_agen connect rename_stage.io.com_uops[1].iw_issued, rob.io.commit.uops[1].iw_issued connect rename_stage.io.com_uops[1].fu_code[0], rob.io.commit.uops[1].fu_code[0] connect rename_stage.io.com_uops[1].fu_code[1], rob.io.commit.uops[1].fu_code[1] connect rename_stage.io.com_uops[1].fu_code[2], rob.io.commit.uops[1].fu_code[2] connect rename_stage.io.com_uops[1].fu_code[3], rob.io.commit.uops[1].fu_code[3] connect rename_stage.io.com_uops[1].fu_code[4], rob.io.commit.uops[1].fu_code[4] connect rename_stage.io.com_uops[1].fu_code[5], rob.io.commit.uops[1].fu_code[5] connect rename_stage.io.com_uops[1].fu_code[6], rob.io.commit.uops[1].fu_code[6] connect rename_stage.io.com_uops[1].fu_code[7], rob.io.commit.uops[1].fu_code[7] connect rename_stage.io.com_uops[1].fu_code[8], rob.io.commit.uops[1].fu_code[8] connect rename_stage.io.com_uops[1].fu_code[9], rob.io.commit.uops[1].fu_code[9] connect rename_stage.io.com_uops[1].iq_type[0], rob.io.commit.uops[1].iq_type[0] connect rename_stage.io.com_uops[1].iq_type[1], rob.io.commit.uops[1].iq_type[1] connect rename_stage.io.com_uops[1].iq_type[2], rob.io.commit.uops[1].iq_type[2] connect rename_stage.io.com_uops[1].iq_type[3], rob.io.commit.uops[1].iq_type[3] connect rename_stage.io.com_uops[1].debug_pc, rob.io.commit.uops[1].debug_pc connect rename_stage.io.com_uops[1].is_rvc, rob.io.commit.uops[1].is_rvc connect rename_stage.io.com_uops[1].debug_inst, rob.io.commit.uops[1].debug_inst connect rename_stage.io.com_uops[1].inst, rob.io.commit.uops[1].inst connect rename_stage.io.rollback, rob.io.rollback connect pred_rename_stage.io.kill, io.ifu.redirect_flush connect pred_rename_stage.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect pred_rename_stage.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect pred_rename_stage.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect pred_rename_stage.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect pred_rename_stage.io.brupdate.b2.taken, brupdate.b2.taken connect pred_rename_stage.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect pred_rename_stage.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect pred_rename_stage.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect pred_rename_stage.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect pred_rename_stage.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect pred_rename_stage.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect pred_rename_stage.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect pred_rename_stage.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect pred_rename_stage.io.brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect pred_rename_stage.io.brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect pred_rename_stage.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect pred_rename_stage.io.brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect pred_rename_stage.io.brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect pred_rename_stage.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect pred_rename_stage.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect pred_rename_stage.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect pred_rename_stage.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect pred_rename_stage.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect pred_rename_stage.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect pred_rename_stage.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect pred_rename_stage.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect pred_rename_stage.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect pred_rename_stage.io.brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect pred_rename_stage.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect pred_rename_stage.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect pred_rename_stage.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect pred_rename_stage.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect pred_rename_stage.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect pred_rename_stage.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect pred_rename_stage.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect pred_rename_stage.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect pred_rename_stage.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect pred_rename_stage.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect pred_rename_stage.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect pred_rename_stage.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect pred_rename_stage.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect pred_rename_stage.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect pred_rename_stage.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect pred_rename_stage.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect pred_rename_stage.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect pred_rename_stage.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect pred_rename_stage.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect pred_rename_stage.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect pred_rename_stage.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect pred_rename_stage.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect pred_rename_stage.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect pred_rename_stage.io.brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect pred_rename_stage.io.brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect pred_rename_stage.io.brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect pred_rename_stage.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect pred_rename_stage.io.brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect pred_rename_stage.io.brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect pred_rename_stage.io.brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect pred_rename_stage.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect pred_rename_stage.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect pred_rename_stage.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect pred_rename_stage.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect pred_rename_stage.io.brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect pred_rename_stage.io.brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect pred_rename_stage.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect pred_rename_stage.io.brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect pred_rename_stage.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect pred_rename_stage.io.brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect pred_rename_stage.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect pred_rename_stage.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect pred_rename_stage.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect pred_rename_stage.io.brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect pred_rename_stage.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect pred_rename_stage.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect pred_rename_stage.io.brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect pred_rename_stage.io.brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect pred_rename_stage.io.brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect pred_rename_stage.io.brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect pred_rename_stage.io.brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect pred_rename_stage.io.brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect pred_rename_stage.io.brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect pred_rename_stage.io.brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect pred_rename_stage.io.brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect pred_rename_stage.io.brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect pred_rename_stage.io.brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect pred_rename_stage.io.brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect pred_rename_stage.io.brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect pred_rename_stage.io.brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect pred_rename_stage.io.brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect pred_rename_stage.io.brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect pred_rename_stage.io.brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect pred_rename_stage.io.brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect pred_rename_stage.io.brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect pred_rename_stage.io.brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect pred_rename_stage.io.brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect pred_rename_stage.io.brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect pred_rename_stage.io.brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect pred_rename_stage.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect pred_rename_stage.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect pred_rename_stage.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect pred_rename_stage.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect pred_rename_stage.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect pred_rename_stage.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect pred_rename_stage.io.debug_rob_empty, rob.io.empty connect pred_rename_stage.io.dec_fire[0], dec_fire[0] connect pred_rename_stage.io.dec_fire[1], dec_fire[1] connect pred_rename_stage.io.dec_uops[0].debug_tsrc, dec_uops[0].debug_tsrc connect pred_rename_stage.io.dec_uops[0].debug_fsrc, dec_uops[0].debug_fsrc connect pred_rename_stage.io.dec_uops[0].bp_xcpt_if, dec_uops[0].bp_xcpt_if connect pred_rename_stage.io.dec_uops[0].bp_debug_if, dec_uops[0].bp_debug_if connect pred_rename_stage.io.dec_uops[0].xcpt_ma_if, dec_uops[0].xcpt_ma_if connect pred_rename_stage.io.dec_uops[0].xcpt_ae_if, dec_uops[0].xcpt_ae_if connect pred_rename_stage.io.dec_uops[0].xcpt_pf_if, dec_uops[0].xcpt_pf_if connect pred_rename_stage.io.dec_uops[0].fp_typ, dec_uops[0].fp_typ connect pred_rename_stage.io.dec_uops[0].fp_rm, dec_uops[0].fp_rm connect pred_rename_stage.io.dec_uops[0].fp_val, dec_uops[0].fp_val connect pred_rename_stage.io.dec_uops[0].fcn_op, dec_uops[0].fcn_op connect pred_rename_stage.io.dec_uops[0].fcn_dw, dec_uops[0].fcn_dw connect pred_rename_stage.io.dec_uops[0].frs3_en, dec_uops[0].frs3_en connect pred_rename_stage.io.dec_uops[0].lrs2_rtype, dec_uops[0].lrs2_rtype connect pred_rename_stage.io.dec_uops[0].lrs1_rtype, dec_uops[0].lrs1_rtype connect pred_rename_stage.io.dec_uops[0].dst_rtype, dec_uops[0].dst_rtype connect pred_rename_stage.io.dec_uops[0].lrs3, dec_uops[0].lrs3 connect pred_rename_stage.io.dec_uops[0].lrs2, dec_uops[0].lrs2 connect pred_rename_stage.io.dec_uops[0].lrs1, dec_uops[0].lrs1 connect pred_rename_stage.io.dec_uops[0].ldst, dec_uops[0].ldst connect pred_rename_stage.io.dec_uops[0].ldst_is_rs1, dec_uops[0].ldst_is_rs1 connect pred_rename_stage.io.dec_uops[0].csr_cmd, dec_uops[0].csr_cmd connect pred_rename_stage.io.dec_uops[0].flush_on_commit, dec_uops[0].flush_on_commit connect pred_rename_stage.io.dec_uops[0].is_unique, dec_uops[0].is_unique connect pred_rename_stage.io.dec_uops[0].uses_stq, dec_uops[0].uses_stq connect pred_rename_stage.io.dec_uops[0].uses_ldq, dec_uops[0].uses_ldq connect pred_rename_stage.io.dec_uops[0].mem_signed, dec_uops[0].mem_signed connect pred_rename_stage.io.dec_uops[0].mem_size, dec_uops[0].mem_size connect pred_rename_stage.io.dec_uops[0].mem_cmd, dec_uops[0].mem_cmd connect pred_rename_stage.io.dec_uops[0].exc_cause, dec_uops[0].exc_cause connect pred_rename_stage.io.dec_uops[0].exception, dec_uops[0].exception connect pred_rename_stage.io.dec_uops[0].stale_pdst, dec_uops[0].stale_pdst connect pred_rename_stage.io.dec_uops[0].ppred_busy, dec_uops[0].ppred_busy connect pred_rename_stage.io.dec_uops[0].prs3_busy, dec_uops[0].prs3_busy connect pred_rename_stage.io.dec_uops[0].prs2_busy, dec_uops[0].prs2_busy connect pred_rename_stage.io.dec_uops[0].prs1_busy, dec_uops[0].prs1_busy connect pred_rename_stage.io.dec_uops[0].ppred, dec_uops[0].ppred connect pred_rename_stage.io.dec_uops[0].prs3, dec_uops[0].prs3 connect pred_rename_stage.io.dec_uops[0].prs2, dec_uops[0].prs2 connect pred_rename_stage.io.dec_uops[0].prs1, dec_uops[0].prs1 connect pred_rename_stage.io.dec_uops[0].pdst, dec_uops[0].pdst connect pred_rename_stage.io.dec_uops[0].rxq_idx, dec_uops[0].rxq_idx connect pred_rename_stage.io.dec_uops[0].stq_idx, dec_uops[0].stq_idx connect pred_rename_stage.io.dec_uops[0].ldq_idx, dec_uops[0].ldq_idx connect pred_rename_stage.io.dec_uops[0].rob_idx, dec_uops[0].rob_idx connect pred_rename_stage.io.dec_uops[0].fp_ctrl.vec, dec_uops[0].fp_ctrl.vec connect pred_rename_stage.io.dec_uops[0].fp_ctrl.wflags, dec_uops[0].fp_ctrl.wflags connect pred_rename_stage.io.dec_uops[0].fp_ctrl.sqrt, dec_uops[0].fp_ctrl.sqrt connect pred_rename_stage.io.dec_uops[0].fp_ctrl.div, dec_uops[0].fp_ctrl.div connect pred_rename_stage.io.dec_uops[0].fp_ctrl.fma, dec_uops[0].fp_ctrl.fma connect pred_rename_stage.io.dec_uops[0].fp_ctrl.fastpipe, dec_uops[0].fp_ctrl.fastpipe connect pred_rename_stage.io.dec_uops[0].fp_ctrl.toint, dec_uops[0].fp_ctrl.toint connect pred_rename_stage.io.dec_uops[0].fp_ctrl.fromint, dec_uops[0].fp_ctrl.fromint connect pred_rename_stage.io.dec_uops[0].fp_ctrl.typeTagOut, dec_uops[0].fp_ctrl.typeTagOut connect pred_rename_stage.io.dec_uops[0].fp_ctrl.typeTagIn, dec_uops[0].fp_ctrl.typeTagIn connect pred_rename_stage.io.dec_uops[0].fp_ctrl.swap23, dec_uops[0].fp_ctrl.swap23 connect pred_rename_stage.io.dec_uops[0].fp_ctrl.swap12, dec_uops[0].fp_ctrl.swap12 connect pred_rename_stage.io.dec_uops[0].fp_ctrl.ren3, dec_uops[0].fp_ctrl.ren3 connect pred_rename_stage.io.dec_uops[0].fp_ctrl.ren2, dec_uops[0].fp_ctrl.ren2 connect pred_rename_stage.io.dec_uops[0].fp_ctrl.ren1, dec_uops[0].fp_ctrl.ren1 connect pred_rename_stage.io.dec_uops[0].fp_ctrl.wen, dec_uops[0].fp_ctrl.wen connect pred_rename_stage.io.dec_uops[0].fp_ctrl.ldst, dec_uops[0].fp_ctrl.ldst connect pred_rename_stage.io.dec_uops[0].op2_sel, dec_uops[0].op2_sel connect pred_rename_stage.io.dec_uops[0].op1_sel, dec_uops[0].op1_sel connect pred_rename_stage.io.dec_uops[0].imm_packed, dec_uops[0].imm_packed connect pred_rename_stage.io.dec_uops[0].pimm, dec_uops[0].pimm connect pred_rename_stage.io.dec_uops[0].imm_sel, dec_uops[0].imm_sel connect pred_rename_stage.io.dec_uops[0].imm_rename, dec_uops[0].imm_rename connect pred_rename_stage.io.dec_uops[0].taken, dec_uops[0].taken connect pred_rename_stage.io.dec_uops[0].pc_lob, dec_uops[0].pc_lob connect pred_rename_stage.io.dec_uops[0].edge_inst, dec_uops[0].edge_inst connect pred_rename_stage.io.dec_uops[0].ftq_idx, dec_uops[0].ftq_idx connect pred_rename_stage.io.dec_uops[0].is_mov, dec_uops[0].is_mov connect pred_rename_stage.io.dec_uops[0].is_rocc, dec_uops[0].is_rocc connect pred_rename_stage.io.dec_uops[0].is_sys_pc2epc, dec_uops[0].is_sys_pc2epc connect pred_rename_stage.io.dec_uops[0].is_eret, dec_uops[0].is_eret connect pred_rename_stage.io.dec_uops[0].is_amo, dec_uops[0].is_amo connect pred_rename_stage.io.dec_uops[0].is_sfence, dec_uops[0].is_sfence connect pred_rename_stage.io.dec_uops[0].is_fencei, dec_uops[0].is_fencei connect pred_rename_stage.io.dec_uops[0].is_fence, dec_uops[0].is_fence connect pred_rename_stage.io.dec_uops[0].is_sfb, dec_uops[0].is_sfb connect pred_rename_stage.io.dec_uops[0].br_type, dec_uops[0].br_type connect pred_rename_stage.io.dec_uops[0].br_tag, dec_uops[0].br_tag connect pred_rename_stage.io.dec_uops[0].br_mask, dec_uops[0].br_mask connect pred_rename_stage.io.dec_uops[0].dis_col_sel, dec_uops[0].dis_col_sel connect pred_rename_stage.io.dec_uops[0].iw_p3_bypass_hint, dec_uops[0].iw_p3_bypass_hint connect pred_rename_stage.io.dec_uops[0].iw_p2_bypass_hint, dec_uops[0].iw_p2_bypass_hint connect pred_rename_stage.io.dec_uops[0].iw_p1_bypass_hint, dec_uops[0].iw_p1_bypass_hint connect pred_rename_stage.io.dec_uops[0].iw_p2_speculative_child, dec_uops[0].iw_p2_speculative_child connect pred_rename_stage.io.dec_uops[0].iw_p1_speculative_child, dec_uops[0].iw_p1_speculative_child connect pred_rename_stage.io.dec_uops[0].iw_issued_partial_dgen, dec_uops[0].iw_issued_partial_dgen connect pred_rename_stage.io.dec_uops[0].iw_issued_partial_agen, dec_uops[0].iw_issued_partial_agen connect pred_rename_stage.io.dec_uops[0].iw_issued, dec_uops[0].iw_issued connect pred_rename_stage.io.dec_uops[0].fu_code[0], dec_uops[0].fu_code[0] connect pred_rename_stage.io.dec_uops[0].fu_code[1], dec_uops[0].fu_code[1] connect pred_rename_stage.io.dec_uops[0].fu_code[2], dec_uops[0].fu_code[2] connect pred_rename_stage.io.dec_uops[0].fu_code[3], dec_uops[0].fu_code[3] connect pred_rename_stage.io.dec_uops[0].fu_code[4], dec_uops[0].fu_code[4] connect pred_rename_stage.io.dec_uops[0].fu_code[5], dec_uops[0].fu_code[5] connect pred_rename_stage.io.dec_uops[0].fu_code[6], dec_uops[0].fu_code[6] connect pred_rename_stage.io.dec_uops[0].fu_code[7], dec_uops[0].fu_code[7] connect pred_rename_stage.io.dec_uops[0].fu_code[8], dec_uops[0].fu_code[8] connect pred_rename_stage.io.dec_uops[0].fu_code[9], dec_uops[0].fu_code[9] connect pred_rename_stage.io.dec_uops[0].iq_type[0], dec_uops[0].iq_type[0] connect pred_rename_stage.io.dec_uops[0].iq_type[1], dec_uops[0].iq_type[1] connect pred_rename_stage.io.dec_uops[0].iq_type[2], dec_uops[0].iq_type[2] connect pred_rename_stage.io.dec_uops[0].iq_type[3], dec_uops[0].iq_type[3] connect pred_rename_stage.io.dec_uops[0].debug_pc, dec_uops[0].debug_pc connect pred_rename_stage.io.dec_uops[0].is_rvc, dec_uops[0].is_rvc connect pred_rename_stage.io.dec_uops[0].debug_inst, dec_uops[0].debug_inst connect pred_rename_stage.io.dec_uops[0].inst, dec_uops[0].inst connect pred_rename_stage.io.dec_uops[1].debug_tsrc, dec_uops[1].debug_tsrc connect pred_rename_stage.io.dec_uops[1].debug_fsrc, dec_uops[1].debug_fsrc connect pred_rename_stage.io.dec_uops[1].bp_xcpt_if, dec_uops[1].bp_xcpt_if connect pred_rename_stage.io.dec_uops[1].bp_debug_if, dec_uops[1].bp_debug_if connect pred_rename_stage.io.dec_uops[1].xcpt_ma_if, dec_uops[1].xcpt_ma_if connect pred_rename_stage.io.dec_uops[1].xcpt_ae_if, dec_uops[1].xcpt_ae_if connect pred_rename_stage.io.dec_uops[1].xcpt_pf_if, dec_uops[1].xcpt_pf_if connect pred_rename_stage.io.dec_uops[1].fp_typ, dec_uops[1].fp_typ connect pred_rename_stage.io.dec_uops[1].fp_rm, dec_uops[1].fp_rm connect pred_rename_stage.io.dec_uops[1].fp_val, dec_uops[1].fp_val connect pred_rename_stage.io.dec_uops[1].fcn_op, dec_uops[1].fcn_op connect pred_rename_stage.io.dec_uops[1].fcn_dw, dec_uops[1].fcn_dw connect pred_rename_stage.io.dec_uops[1].frs3_en, dec_uops[1].frs3_en connect pred_rename_stage.io.dec_uops[1].lrs2_rtype, dec_uops[1].lrs2_rtype connect pred_rename_stage.io.dec_uops[1].lrs1_rtype, dec_uops[1].lrs1_rtype connect pred_rename_stage.io.dec_uops[1].dst_rtype, dec_uops[1].dst_rtype connect pred_rename_stage.io.dec_uops[1].lrs3, dec_uops[1].lrs3 connect pred_rename_stage.io.dec_uops[1].lrs2, dec_uops[1].lrs2 connect pred_rename_stage.io.dec_uops[1].lrs1, dec_uops[1].lrs1 connect pred_rename_stage.io.dec_uops[1].ldst, dec_uops[1].ldst connect pred_rename_stage.io.dec_uops[1].ldst_is_rs1, dec_uops[1].ldst_is_rs1 connect pred_rename_stage.io.dec_uops[1].csr_cmd, dec_uops[1].csr_cmd connect pred_rename_stage.io.dec_uops[1].flush_on_commit, dec_uops[1].flush_on_commit connect pred_rename_stage.io.dec_uops[1].is_unique, dec_uops[1].is_unique connect pred_rename_stage.io.dec_uops[1].uses_stq, dec_uops[1].uses_stq connect pred_rename_stage.io.dec_uops[1].uses_ldq, dec_uops[1].uses_ldq connect pred_rename_stage.io.dec_uops[1].mem_signed, dec_uops[1].mem_signed connect pred_rename_stage.io.dec_uops[1].mem_size, dec_uops[1].mem_size connect pred_rename_stage.io.dec_uops[1].mem_cmd, dec_uops[1].mem_cmd connect pred_rename_stage.io.dec_uops[1].exc_cause, dec_uops[1].exc_cause connect pred_rename_stage.io.dec_uops[1].exception, dec_uops[1].exception connect pred_rename_stage.io.dec_uops[1].stale_pdst, dec_uops[1].stale_pdst connect pred_rename_stage.io.dec_uops[1].ppred_busy, dec_uops[1].ppred_busy connect pred_rename_stage.io.dec_uops[1].prs3_busy, dec_uops[1].prs3_busy connect pred_rename_stage.io.dec_uops[1].prs2_busy, dec_uops[1].prs2_busy connect pred_rename_stage.io.dec_uops[1].prs1_busy, dec_uops[1].prs1_busy connect pred_rename_stage.io.dec_uops[1].ppred, dec_uops[1].ppred connect pred_rename_stage.io.dec_uops[1].prs3, dec_uops[1].prs3 connect pred_rename_stage.io.dec_uops[1].prs2, dec_uops[1].prs2 connect pred_rename_stage.io.dec_uops[1].prs1, dec_uops[1].prs1 connect pred_rename_stage.io.dec_uops[1].pdst, dec_uops[1].pdst connect pred_rename_stage.io.dec_uops[1].rxq_idx, dec_uops[1].rxq_idx connect pred_rename_stage.io.dec_uops[1].stq_idx, dec_uops[1].stq_idx connect pred_rename_stage.io.dec_uops[1].ldq_idx, dec_uops[1].ldq_idx connect pred_rename_stage.io.dec_uops[1].rob_idx, dec_uops[1].rob_idx connect pred_rename_stage.io.dec_uops[1].fp_ctrl.vec, dec_uops[1].fp_ctrl.vec connect pred_rename_stage.io.dec_uops[1].fp_ctrl.wflags, dec_uops[1].fp_ctrl.wflags connect pred_rename_stage.io.dec_uops[1].fp_ctrl.sqrt, dec_uops[1].fp_ctrl.sqrt connect pred_rename_stage.io.dec_uops[1].fp_ctrl.div, dec_uops[1].fp_ctrl.div connect pred_rename_stage.io.dec_uops[1].fp_ctrl.fma, dec_uops[1].fp_ctrl.fma connect pred_rename_stage.io.dec_uops[1].fp_ctrl.fastpipe, dec_uops[1].fp_ctrl.fastpipe connect pred_rename_stage.io.dec_uops[1].fp_ctrl.toint, dec_uops[1].fp_ctrl.toint connect pred_rename_stage.io.dec_uops[1].fp_ctrl.fromint, dec_uops[1].fp_ctrl.fromint connect pred_rename_stage.io.dec_uops[1].fp_ctrl.typeTagOut, dec_uops[1].fp_ctrl.typeTagOut connect pred_rename_stage.io.dec_uops[1].fp_ctrl.typeTagIn, dec_uops[1].fp_ctrl.typeTagIn connect pred_rename_stage.io.dec_uops[1].fp_ctrl.swap23, dec_uops[1].fp_ctrl.swap23 connect pred_rename_stage.io.dec_uops[1].fp_ctrl.swap12, dec_uops[1].fp_ctrl.swap12 connect pred_rename_stage.io.dec_uops[1].fp_ctrl.ren3, dec_uops[1].fp_ctrl.ren3 connect pred_rename_stage.io.dec_uops[1].fp_ctrl.ren2, dec_uops[1].fp_ctrl.ren2 connect pred_rename_stage.io.dec_uops[1].fp_ctrl.ren1, dec_uops[1].fp_ctrl.ren1 connect pred_rename_stage.io.dec_uops[1].fp_ctrl.wen, dec_uops[1].fp_ctrl.wen connect pred_rename_stage.io.dec_uops[1].fp_ctrl.ldst, dec_uops[1].fp_ctrl.ldst connect pred_rename_stage.io.dec_uops[1].op2_sel, dec_uops[1].op2_sel connect pred_rename_stage.io.dec_uops[1].op1_sel, dec_uops[1].op1_sel connect pred_rename_stage.io.dec_uops[1].imm_packed, dec_uops[1].imm_packed connect pred_rename_stage.io.dec_uops[1].pimm, dec_uops[1].pimm connect pred_rename_stage.io.dec_uops[1].imm_sel, dec_uops[1].imm_sel connect pred_rename_stage.io.dec_uops[1].imm_rename, dec_uops[1].imm_rename connect pred_rename_stage.io.dec_uops[1].taken, dec_uops[1].taken connect pred_rename_stage.io.dec_uops[1].pc_lob, dec_uops[1].pc_lob connect pred_rename_stage.io.dec_uops[1].edge_inst, dec_uops[1].edge_inst connect pred_rename_stage.io.dec_uops[1].ftq_idx, dec_uops[1].ftq_idx connect pred_rename_stage.io.dec_uops[1].is_mov, dec_uops[1].is_mov connect pred_rename_stage.io.dec_uops[1].is_rocc, dec_uops[1].is_rocc connect pred_rename_stage.io.dec_uops[1].is_sys_pc2epc, dec_uops[1].is_sys_pc2epc connect pred_rename_stage.io.dec_uops[1].is_eret, dec_uops[1].is_eret connect pred_rename_stage.io.dec_uops[1].is_amo, dec_uops[1].is_amo connect pred_rename_stage.io.dec_uops[1].is_sfence, dec_uops[1].is_sfence connect pred_rename_stage.io.dec_uops[1].is_fencei, dec_uops[1].is_fencei connect pred_rename_stage.io.dec_uops[1].is_fence, dec_uops[1].is_fence connect pred_rename_stage.io.dec_uops[1].is_sfb, dec_uops[1].is_sfb connect pred_rename_stage.io.dec_uops[1].br_type, dec_uops[1].br_type connect pred_rename_stage.io.dec_uops[1].br_tag, dec_uops[1].br_tag connect pred_rename_stage.io.dec_uops[1].br_mask, dec_uops[1].br_mask connect pred_rename_stage.io.dec_uops[1].dis_col_sel, dec_uops[1].dis_col_sel connect pred_rename_stage.io.dec_uops[1].iw_p3_bypass_hint, dec_uops[1].iw_p3_bypass_hint connect pred_rename_stage.io.dec_uops[1].iw_p2_bypass_hint, dec_uops[1].iw_p2_bypass_hint connect pred_rename_stage.io.dec_uops[1].iw_p1_bypass_hint, dec_uops[1].iw_p1_bypass_hint connect pred_rename_stage.io.dec_uops[1].iw_p2_speculative_child, dec_uops[1].iw_p2_speculative_child connect pred_rename_stage.io.dec_uops[1].iw_p1_speculative_child, dec_uops[1].iw_p1_speculative_child connect pred_rename_stage.io.dec_uops[1].iw_issued_partial_dgen, dec_uops[1].iw_issued_partial_dgen connect pred_rename_stage.io.dec_uops[1].iw_issued_partial_agen, dec_uops[1].iw_issued_partial_agen connect pred_rename_stage.io.dec_uops[1].iw_issued, dec_uops[1].iw_issued connect pred_rename_stage.io.dec_uops[1].fu_code[0], dec_uops[1].fu_code[0] connect pred_rename_stage.io.dec_uops[1].fu_code[1], dec_uops[1].fu_code[1] connect pred_rename_stage.io.dec_uops[1].fu_code[2], dec_uops[1].fu_code[2] connect pred_rename_stage.io.dec_uops[1].fu_code[3], dec_uops[1].fu_code[3] connect pred_rename_stage.io.dec_uops[1].fu_code[4], dec_uops[1].fu_code[4] connect pred_rename_stage.io.dec_uops[1].fu_code[5], dec_uops[1].fu_code[5] connect pred_rename_stage.io.dec_uops[1].fu_code[6], dec_uops[1].fu_code[6] connect pred_rename_stage.io.dec_uops[1].fu_code[7], dec_uops[1].fu_code[7] connect pred_rename_stage.io.dec_uops[1].fu_code[8], dec_uops[1].fu_code[8] connect pred_rename_stage.io.dec_uops[1].fu_code[9], dec_uops[1].fu_code[9] connect pred_rename_stage.io.dec_uops[1].iq_type[0], dec_uops[1].iq_type[0] connect pred_rename_stage.io.dec_uops[1].iq_type[1], dec_uops[1].iq_type[1] connect pred_rename_stage.io.dec_uops[1].iq_type[2], dec_uops[1].iq_type[2] connect pred_rename_stage.io.dec_uops[1].iq_type[3], dec_uops[1].iq_type[3] connect pred_rename_stage.io.dec_uops[1].debug_pc, dec_uops[1].debug_pc connect pred_rename_stage.io.dec_uops[1].is_rvc, dec_uops[1].is_rvc connect pred_rename_stage.io.dec_uops[1].debug_inst, dec_uops[1].debug_inst connect pred_rename_stage.io.dec_uops[1].inst, dec_uops[1].inst connect pred_rename_stage.io.dis_fire[0], dis_fire[0] connect pred_rename_stage.io.dis_fire[1], dis_fire[1] connect pred_rename_stage.io.dis_ready, dis_ready connect pred_rename_stage.io.com_valids[0], rob.io.commit.valids[0] connect pred_rename_stage.io.com_valids[1], rob.io.commit.valids[1] connect pred_rename_stage.io.com_uops[0].debug_tsrc, rob.io.commit.uops[0].debug_tsrc connect pred_rename_stage.io.com_uops[0].debug_fsrc, rob.io.commit.uops[0].debug_fsrc connect pred_rename_stage.io.com_uops[0].bp_xcpt_if, rob.io.commit.uops[0].bp_xcpt_if connect pred_rename_stage.io.com_uops[0].bp_debug_if, rob.io.commit.uops[0].bp_debug_if connect pred_rename_stage.io.com_uops[0].xcpt_ma_if, rob.io.commit.uops[0].xcpt_ma_if connect pred_rename_stage.io.com_uops[0].xcpt_ae_if, rob.io.commit.uops[0].xcpt_ae_if connect pred_rename_stage.io.com_uops[0].xcpt_pf_if, rob.io.commit.uops[0].xcpt_pf_if connect pred_rename_stage.io.com_uops[0].fp_typ, rob.io.commit.uops[0].fp_typ connect pred_rename_stage.io.com_uops[0].fp_rm, rob.io.commit.uops[0].fp_rm connect pred_rename_stage.io.com_uops[0].fp_val, rob.io.commit.uops[0].fp_val connect pred_rename_stage.io.com_uops[0].fcn_op, rob.io.commit.uops[0].fcn_op connect pred_rename_stage.io.com_uops[0].fcn_dw, rob.io.commit.uops[0].fcn_dw connect pred_rename_stage.io.com_uops[0].frs3_en, rob.io.commit.uops[0].frs3_en connect pred_rename_stage.io.com_uops[0].lrs2_rtype, rob.io.commit.uops[0].lrs2_rtype connect pred_rename_stage.io.com_uops[0].lrs1_rtype, rob.io.commit.uops[0].lrs1_rtype connect pred_rename_stage.io.com_uops[0].dst_rtype, rob.io.commit.uops[0].dst_rtype connect pred_rename_stage.io.com_uops[0].lrs3, rob.io.commit.uops[0].lrs3 connect pred_rename_stage.io.com_uops[0].lrs2, rob.io.commit.uops[0].lrs2 connect pred_rename_stage.io.com_uops[0].lrs1, rob.io.commit.uops[0].lrs1 connect pred_rename_stage.io.com_uops[0].ldst, rob.io.commit.uops[0].ldst connect pred_rename_stage.io.com_uops[0].ldst_is_rs1, rob.io.commit.uops[0].ldst_is_rs1 connect pred_rename_stage.io.com_uops[0].csr_cmd, rob.io.commit.uops[0].csr_cmd connect pred_rename_stage.io.com_uops[0].flush_on_commit, rob.io.commit.uops[0].flush_on_commit connect pred_rename_stage.io.com_uops[0].is_unique, rob.io.commit.uops[0].is_unique connect pred_rename_stage.io.com_uops[0].uses_stq, rob.io.commit.uops[0].uses_stq connect pred_rename_stage.io.com_uops[0].uses_ldq, rob.io.commit.uops[0].uses_ldq connect pred_rename_stage.io.com_uops[0].mem_signed, rob.io.commit.uops[0].mem_signed connect pred_rename_stage.io.com_uops[0].mem_size, rob.io.commit.uops[0].mem_size connect pred_rename_stage.io.com_uops[0].mem_cmd, rob.io.commit.uops[0].mem_cmd connect pred_rename_stage.io.com_uops[0].exc_cause, rob.io.commit.uops[0].exc_cause connect pred_rename_stage.io.com_uops[0].exception, rob.io.commit.uops[0].exception connect pred_rename_stage.io.com_uops[0].stale_pdst, rob.io.commit.uops[0].stale_pdst connect pred_rename_stage.io.com_uops[0].ppred_busy, rob.io.commit.uops[0].ppred_busy connect pred_rename_stage.io.com_uops[0].prs3_busy, rob.io.commit.uops[0].prs3_busy connect pred_rename_stage.io.com_uops[0].prs2_busy, rob.io.commit.uops[0].prs2_busy connect pred_rename_stage.io.com_uops[0].prs1_busy, rob.io.commit.uops[0].prs1_busy connect pred_rename_stage.io.com_uops[0].ppred, rob.io.commit.uops[0].ppred connect pred_rename_stage.io.com_uops[0].prs3, rob.io.commit.uops[0].prs3 connect pred_rename_stage.io.com_uops[0].prs2, rob.io.commit.uops[0].prs2 connect pred_rename_stage.io.com_uops[0].prs1, rob.io.commit.uops[0].prs1 connect pred_rename_stage.io.com_uops[0].pdst, rob.io.commit.uops[0].pdst connect pred_rename_stage.io.com_uops[0].rxq_idx, rob.io.commit.uops[0].rxq_idx connect pred_rename_stage.io.com_uops[0].stq_idx, rob.io.commit.uops[0].stq_idx connect pred_rename_stage.io.com_uops[0].ldq_idx, rob.io.commit.uops[0].ldq_idx connect pred_rename_stage.io.com_uops[0].rob_idx, rob.io.commit.uops[0].rob_idx connect pred_rename_stage.io.com_uops[0].fp_ctrl.vec, rob.io.commit.uops[0].fp_ctrl.vec connect pred_rename_stage.io.com_uops[0].fp_ctrl.wflags, rob.io.commit.uops[0].fp_ctrl.wflags connect pred_rename_stage.io.com_uops[0].fp_ctrl.sqrt, rob.io.commit.uops[0].fp_ctrl.sqrt connect pred_rename_stage.io.com_uops[0].fp_ctrl.div, rob.io.commit.uops[0].fp_ctrl.div connect pred_rename_stage.io.com_uops[0].fp_ctrl.fma, rob.io.commit.uops[0].fp_ctrl.fma connect pred_rename_stage.io.com_uops[0].fp_ctrl.fastpipe, rob.io.commit.uops[0].fp_ctrl.fastpipe connect pred_rename_stage.io.com_uops[0].fp_ctrl.toint, rob.io.commit.uops[0].fp_ctrl.toint connect pred_rename_stage.io.com_uops[0].fp_ctrl.fromint, rob.io.commit.uops[0].fp_ctrl.fromint connect pred_rename_stage.io.com_uops[0].fp_ctrl.typeTagOut, rob.io.commit.uops[0].fp_ctrl.typeTagOut connect pred_rename_stage.io.com_uops[0].fp_ctrl.typeTagIn, rob.io.commit.uops[0].fp_ctrl.typeTagIn connect pred_rename_stage.io.com_uops[0].fp_ctrl.swap23, rob.io.commit.uops[0].fp_ctrl.swap23 connect pred_rename_stage.io.com_uops[0].fp_ctrl.swap12, rob.io.commit.uops[0].fp_ctrl.swap12 connect pred_rename_stage.io.com_uops[0].fp_ctrl.ren3, rob.io.commit.uops[0].fp_ctrl.ren3 connect pred_rename_stage.io.com_uops[0].fp_ctrl.ren2, rob.io.commit.uops[0].fp_ctrl.ren2 connect pred_rename_stage.io.com_uops[0].fp_ctrl.ren1, rob.io.commit.uops[0].fp_ctrl.ren1 connect pred_rename_stage.io.com_uops[0].fp_ctrl.wen, rob.io.commit.uops[0].fp_ctrl.wen connect pred_rename_stage.io.com_uops[0].fp_ctrl.ldst, rob.io.commit.uops[0].fp_ctrl.ldst connect pred_rename_stage.io.com_uops[0].op2_sel, rob.io.commit.uops[0].op2_sel connect pred_rename_stage.io.com_uops[0].op1_sel, rob.io.commit.uops[0].op1_sel connect pred_rename_stage.io.com_uops[0].imm_packed, rob.io.commit.uops[0].imm_packed connect pred_rename_stage.io.com_uops[0].pimm, rob.io.commit.uops[0].pimm connect pred_rename_stage.io.com_uops[0].imm_sel, rob.io.commit.uops[0].imm_sel connect pred_rename_stage.io.com_uops[0].imm_rename, rob.io.commit.uops[0].imm_rename connect pred_rename_stage.io.com_uops[0].taken, rob.io.commit.uops[0].taken connect pred_rename_stage.io.com_uops[0].pc_lob, rob.io.commit.uops[0].pc_lob connect pred_rename_stage.io.com_uops[0].edge_inst, rob.io.commit.uops[0].edge_inst connect pred_rename_stage.io.com_uops[0].ftq_idx, rob.io.commit.uops[0].ftq_idx connect pred_rename_stage.io.com_uops[0].is_mov, rob.io.commit.uops[0].is_mov connect pred_rename_stage.io.com_uops[0].is_rocc, rob.io.commit.uops[0].is_rocc connect pred_rename_stage.io.com_uops[0].is_sys_pc2epc, rob.io.commit.uops[0].is_sys_pc2epc connect pred_rename_stage.io.com_uops[0].is_eret, rob.io.commit.uops[0].is_eret connect pred_rename_stage.io.com_uops[0].is_amo, rob.io.commit.uops[0].is_amo connect pred_rename_stage.io.com_uops[0].is_sfence, rob.io.commit.uops[0].is_sfence connect pred_rename_stage.io.com_uops[0].is_fencei, rob.io.commit.uops[0].is_fencei connect pred_rename_stage.io.com_uops[0].is_fence, rob.io.commit.uops[0].is_fence connect pred_rename_stage.io.com_uops[0].is_sfb, rob.io.commit.uops[0].is_sfb connect pred_rename_stage.io.com_uops[0].br_type, rob.io.commit.uops[0].br_type connect pred_rename_stage.io.com_uops[0].br_tag, rob.io.commit.uops[0].br_tag connect pred_rename_stage.io.com_uops[0].br_mask, rob.io.commit.uops[0].br_mask connect pred_rename_stage.io.com_uops[0].dis_col_sel, rob.io.commit.uops[0].dis_col_sel connect pred_rename_stage.io.com_uops[0].iw_p3_bypass_hint, rob.io.commit.uops[0].iw_p3_bypass_hint connect pred_rename_stage.io.com_uops[0].iw_p2_bypass_hint, rob.io.commit.uops[0].iw_p2_bypass_hint connect pred_rename_stage.io.com_uops[0].iw_p1_bypass_hint, rob.io.commit.uops[0].iw_p1_bypass_hint connect pred_rename_stage.io.com_uops[0].iw_p2_speculative_child, rob.io.commit.uops[0].iw_p2_speculative_child connect pred_rename_stage.io.com_uops[0].iw_p1_speculative_child, rob.io.commit.uops[0].iw_p1_speculative_child connect pred_rename_stage.io.com_uops[0].iw_issued_partial_dgen, rob.io.commit.uops[0].iw_issued_partial_dgen connect pred_rename_stage.io.com_uops[0].iw_issued_partial_agen, rob.io.commit.uops[0].iw_issued_partial_agen connect pred_rename_stage.io.com_uops[0].iw_issued, rob.io.commit.uops[0].iw_issued connect pred_rename_stage.io.com_uops[0].fu_code[0], rob.io.commit.uops[0].fu_code[0] connect pred_rename_stage.io.com_uops[0].fu_code[1], rob.io.commit.uops[0].fu_code[1] connect pred_rename_stage.io.com_uops[0].fu_code[2], rob.io.commit.uops[0].fu_code[2] connect pred_rename_stage.io.com_uops[0].fu_code[3], rob.io.commit.uops[0].fu_code[3] connect pred_rename_stage.io.com_uops[0].fu_code[4], rob.io.commit.uops[0].fu_code[4] connect pred_rename_stage.io.com_uops[0].fu_code[5], rob.io.commit.uops[0].fu_code[5] connect pred_rename_stage.io.com_uops[0].fu_code[6], rob.io.commit.uops[0].fu_code[6] connect pred_rename_stage.io.com_uops[0].fu_code[7], rob.io.commit.uops[0].fu_code[7] connect pred_rename_stage.io.com_uops[0].fu_code[8], rob.io.commit.uops[0].fu_code[8] connect pred_rename_stage.io.com_uops[0].fu_code[9], rob.io.commit.uops[0].fu_code[9] connect pred_rename_stage.io.com_uops[0].iq_type[0], rob.io.commit.uops[0].iq_type[0] connect pred_rename_stage.io.com_uops[0].iq_type[1], rob.io.commit.uops[0].iq_type[1] connect pred_rename_stage.io.com_uops[0].iq_type[2], rob.io.commit.uops[0].iq_type[2] connect pred_rename_stage.io.com_uops[0].iq_type[3], rob.io.commit.uops[0].iq_type[3] connect pred_rename_stage.io.com_uops[0].debug_pc, rob.io.commit.uops[0].debug_pc connect pred_rename_stage.io.com_uops[0].is_rvc, rob.io.commit.uops[0].is_rvc connect pred_rename_stage.io.com_uops[0].debug_inst, rob.io.commit.uops[0].debug_inst connect pred_rename_stage.io.com_uops[0].inst, rob.io.commit.uops[0].inst connect pred_rename_stage.io.com_uops[1].debug_tsrc, rob.io.commit.uops[1].debug_tsrc connect pred_rename_stage.io.com_uops[1].debug_fsrc, rob.io.commit.uops[1].debug_fsrc connect pred_rename_stage.io.com_uops[1].bp_xcpt_if, rob.io.commit.uops[1].bp_xcpt_if connect pred_rename_stage.io.com_uops[1].bp_debug_if, rob.io.commit.uops[1].bp_debug_if connect pred_rename_stage.io.com_uops[1].xcpt_ma_if, rob.io.commit.uops[1].xcpt_ma_if connect pred_rename_stage.io.com_uops[1].xcpt_ae_if, rob.io.commit.uops[1].xcpt_ae_if connect pred_rename_stage.io.com_uops[1].xcpt_pf_if, rob.io.commit.uops[1].xcpt_pf_if connect pred_rename_stage.io.com_uops[1].fp_typ, rob.io.commit.uops[1].fp_typ connect pred_rename_stage.io.com_uops[1].fp_rm, rob.io.commit.uops[1].fp_rm connect pred_rename_stage.io.com_uops[1].fp_val, rob.io.commit.uops[1].fp_val connect pred_rename_stage.io.com_uops[1].fcn_op, rob.io.commit.uops[1].fcn_op connect pred_rename_stage.io.com_uops[1].fcn_dw, rob.io.commit.uops[1].fcn_dw connect pred_rename_stage.io.com_uops[1].frs3_en, rob.io.commit.uops[1].frs3_en connect pred_rename_stage.io.com_uops[1].lrs2_rtype, rob.io.commit.uops[1].lrs2_rtype connect pred_rename_stage.io.com_uops[1].lrs1_rtype, rob.io.commit.uops[1].lrs1_rtype connect pred_rename_stage.io.com_uops[1].dst_rtype, rob.io.commit.uops[1].dst_rtype connect pred_rename_stage.io.com_uops[1].lrs3, rob.io.commit.uops[1].lrs3 connect pred_rename_stage.io.com_uops[1].lrs2, rob.io.commit.uops[1].lrs2 connect pred_rename_stage.io.com_uops[1].lrs1, rob.io.commit.uops[1].lrs1 connect pred_rename_stage.io.com_uops[1].ldst, rob.io.commit.uops[1].ldst connect pred_rename_stage.io.com_uops[1].ldst_is_rs1, rob.io.commit.uops[1].ldst_is_rs1 connect pred_rename_stage.io.com_uops[1].csr_cmd, rob.io.commit.uops[1].csr_cmd connect pred_rename_stage.io.com_uops[1].flush_on_commit, rob.io.commit.uops[1].flush_on_commit connect pred_rename_stage.io.com_uops[1].is_unique, rob.io.commit.uops[1].is_unique connect pred_rename_stage.io.com_uops[1].uses_stq, rob.io.commit.uops[1].uses_stq connect pred_rename_stage.io.com_uops[1].uses_ldq, rob.io.commit.uops[1].uses_ldq connect pred_rename_stage.io.com_uops[1].mem_signed, rob.io.commit.uops[1].mem_signed connect pred_rename_stage.io.com_uops[1].mem_size, rob.io.commit.uops[1].mem_size connect pred_rename_stage.io.com_uops[1].mem_cmd, rob.io.commit.uops[1].mem_cmd connect pred_rename_stage.io.com_uops[1].exc_cause, rob.io.commit.uops[1].exc_cause connect pred_rename_stage.io.com_uops[1].exception, rob.io.commit.uops[1].exception connect pred_rename_stage.io.com_uops[1].stale_pdst, rob.io.commit.uops[1].stale_pdst connect pred_rename_stage.io.com_uops[1].ppred_busy, rob.io.commit.uops[1].ppred_busy connect pred_rename_stage.io.com_uops[1].prs3_busy, rob.io.commit.uops[1].prs3_busy connect pred_rename_stage.io.com_uops[1].prs2_busy, rob.io.commit.uops[1].prs2_busy connect pred_rename_stage.io.com_uops[1].prs1_busy, rob.io.commit.uops[1].prs1_busy connect pred_rename_stage.io.com_uops[1].ppred, rob.io.commit.uops[1].ppred connect pred_rename_stage.io.com_uops[1].prs3, rob.io.commit.uops[1].prs3 connect pred_rename_stage.io.com_uops[1].prs2, rob.io.commit.uops[1].prs2 connect pred_rename_stage.io.com_uops[1].prs1, rob.io.commit.uops[1].prs1 connect pred_rename_stage.io.com_uops[1].pdst, rob.io.commit.uops[1].pdst connect pred_rename_stage.io.com_uops[1].rxq_idx, rob.io.commit.uops[1].rxq_idx connect pred_rename_stage.io.com_uops[1].stq_idx, rob.io.commit.uops[1].stq_idx connect pred_rename_stage.io.com_uops[1].ldq_idx, rob.io.commit.uops[1].ldq_idx connect pred_rename_stage.io.com_uops[1].rob_idx, rob.io.commit.uops[1].rob_idx connect pred_rename_stage.io.com_uops[1].fp_ctrl.vec, rob.io.commit.uops[1].fp_ctrl.vec connect pred_rename_stage.io.com_uops[1].fp_ctrl.wflags, rob.io.commit.uops[1].fp_ctrl.wflags connect pred_rename_stage.io.com_uops[1].fp_ctrl.sqrt, rob.io.commit.uops[1].fp_ctrl.sqrt connect pred_rename_stage.io.com_uops[1].fp_ctrl.div, rob.io.commit.uops[1].fp_ctrl.div connect pred_rename_stage.io.com_uops[1].fp_ctrl.fma, rob.io.commit.uops[1].fp_ctrl.fma connect pred_rename_stage.io.com_uops[1].fp_ctrl.fastpipe, rob.io.commit.uops[1].fp_ctrl.fastpipe connect pred_rename_stage.io.com_uops[1].fp_ctrl.toint, rob.io.commit.uops[1].fp_ctrl.toint connect pred_rename_stage.io.com_uops[1].fp_ctrl.fromint, rob.io.commit.uops[1].fp_ctrl.fromint connect pred_rename_stage.io.com_uops[1].fp_ctrl.typeTagOut, rob.io.commit.uops[1].fp_ctrl.typeTagOut connect pred_rename_stage.io.com_uops[1].fp_ctrl.typeTagIn, rob.io.commit.uops[1].fp_ctrl.typeTagIn connect pred_rename_stage.io.com_uops[1].fp_ctrl.swap23, rob.io.commit.uops[1].fp_ctrl.swap23 connect pred_rename_stage.io.com_uops[1].fp_ctrl.swap12, rob.io.commit.uops[1].fp_ctrl.swap12 connect pred_rename_stage.io.com_uops[1].fp_ctrl.ren3, rob.io.commit.uops[1].fp_ctrl.ren3 connect pred_rename_stage.io.com_uops[1].fp_ctrl.ren2, rob.io.commit.uops[1].fp_ctrl.ren2 connect pred_rename_stage.io.com_uops[1].fp_ctrl.ren1, rob.io.commit.uops[1].fp_ctrl.ren1 connect pred_rename_stage.io.com_uops[1].fp_ctrl.wen, rob.io.commit.uops[1].fp_ctrl.wen connect pred_rename_stage.io.com_uops[1].fp_ctrl.ldst, rob.io.commit.uops[1].fp_ctrl.ldst connect pred_rename_stage.io.com_uops[1].op2_sel, rob.io.commit.uops[1].op2_sel connect pred_rename_stage.io.com_uops[1].op1_sel, rob.io.commit.uops[1].op1_sel connect pred_rename_stage.io.com_uops[1].imm_packed, rob.io.commit.uops[1].imm_packed connect pred_rename_stage.io.com_uops[1].pimm, rob.io.commit.uops[1].pimm connect pred_rename_stage.io.com_uops[1].imm_sel, rob.io.commit.uops[1].imm_sel connect pred_rename_stage.io.com_uops[1].imm_rename, rob.io.commit.uops[1].imm_rename connect pred_rename_stage.io.com_uops[1].taken, rob.io.commit.uops[1].taken connect pred_rename_stage.io.com_uops[1].pc_lob, rob.io.commit.uops[1].pc_lob connect pred_rename_stage.io.com_uops[1].edge_inst, rob.io.commit.uops[1].edge_inst connect pred_rename_stage.io.com_uops[1].ftq_idx, rob.io.commit.uops[1].ftq_idx connect pred_rename_stage.io.com_uops[1].is_mov, rob.io.commit.uops[1].is_mov connect pred_rename_stage.io.com_uops[1].is_rocc, rob.io.commit.uops[1].is_rocc connect pred_rename_stage.io.com_uops[1].is_sys_pc2epc, rob.io.commit.uops[1].is_sys_pc2epc connect pred_rename_stage.io.com_uops[1].is_eret, rob.io.commit.uops[1].is_eret connect pred_rename_stage.io.com_uops[1].is_amo, rob.io.commit.uops[1].is_amo connect pred_rename_stage.io.com_uops[1].is_sfence, rob.io.commit.uops[1].is_sfence connect pred_rename_stage.io.com_uops[1].is_fencei, rob.io.commit.uops[1].is_fencei connect pred_rename_stage.io.com_uops[1].is_fence, rob.io.commit.uops[1].is_fence connect pred_rename_stage.io.com_uops[1].is_sfb, rob.io.commit.uops[1].is_sfb connect pred_rename_stage.io.com_uops[1].br_type, rob.io.commit.uops[1].br_type connect pred_rename_stage.io.com_uops[1].br_tag, rob.io.commit.uops[1].br_tag connect pred_rename_stage.io.com_uops[1].br_mask, rob.io.commit.uops[1].br_mask connect pred_rename_stage.io.com_uops[1].dis_col_sel, rob.io.commit.uops[1].dis_col_sel connect pred_rename_stage.io.com_uops[1].iw_p3_bypass_hint, rob.io.commit.uops[1].iw_p3_bypass_hint connect pred_rename_stage.io.com_uops[1].iw_p2_bypass_hint, rob.io.commit.uops[1].iw_p2_bypass_hint connect pred_rename_stage.io.com_uops[1].iw_p1_bypass_hint, rob.io.commit.uops[1].iw_p1_bypass_hint connect pred_rename_stage.io.com_uops[1].iw_p2_speculative_child, rob.io.commit.uops[1].iw_p2_speculative_child connect pred_rename_stage.io.com_uops[1].iw_p1_speculative_child, rob.io.commit.uops[1].iw_p1_speculative_child connect pred_rename_stage.io.com_uops[1].iw_issued_partial_dgen, rob.io.commit.uops[1].iw_issued_partial_dgen connect pred_rename_stage.io.com_uops[1].iw_issued_partial_agen, rob.io.commit.uops[1].iw_issued_partial_agen connect pred_rename_stage.io.com_uops[1].iw_issued, rob.io.commit.uops[1].iw_issued connect pred_rename_stage.io.com_uops[1].fu_code[0], rob.io.commit.uops[1].fu_code[0] connect pred_rename_stage.io.com_uops[1].fu_code[1], rob.io.commit.uops[1].fu_code[1] connect pred_rename_stage.io.com_uops[1].fu_code[2], rob.io.commit.uops[1].fu_code[2] connect pred_rename_stage.io.com_uops[1].fu_code[3], rob.io.commit.uops[1].fu_code[3] connect pred_rename_stage.io.com_uops[1].fu_code[4], rob.io.commit.uops[1].fu_code[4] connect pred_rename_stage.io.com_uops[1].fu_code[5], rob.io.commit.uops[1].fu_code[5] connect pred_rename_stage.io.com_uops[1].fu_code[6], rob.io.commit.uops[1].fu_code[6] connect pred_rename_stage.io.com_uops[1].fu_code[7], rob.io.commit.uops[1].fu_code[7] connect pred_rename_stage.io.com_uops[1].fu_code[8], rob.io.commit.uops[1].fu_code[8] connect pred_rename_stage.io.com_uops[1].fu_code[9], rob.io.commit.uops[1].fu_code[9] connect pred_rename_stage.io.com_uops[1].iq_type[0], rob.io.commit.uops[1].iq_type[0] connect pred_rename_stage.io.com_uops[1].iq_type[1], rob.io.commit.uops[1].iq_type[1] connect pred_rename_stage.io.com_uops[1].iq_type[2], rob.io.commit.uops[1].iq_type[2] connect pred_rename_stage.io.com_uops[1].iq_type[3], rob.io.commit.uops[1].iq_type[3] connect pred_rename_stage.io.com_uops[1].debug_pc, rob.io.commit.uops[1].debug_pc connect pred_rename_stage.io.com_uops[1].is_rvc, rob.io.commit.uops[1].is_rvc connect pred_rename_stage.io.com_uops[1].debug_inst, rob.io.commit.uops[1].debug_inst connect pred_rename_stage.io.com_uops[1].inst, rob.io.commit.uops[1].inst connect pred_rename_stage.io.rollback, rob.io.rollback connect imm_rename_stage.io.kill, io.ifu.redirect_flush connect imm_rename_stage.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect imm_rename_stage.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect imm_rename_stage.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect imm_rename_stage.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect imm_rename_stage.io.brupdate.b2.taken, brupdate.b2.taken connect imm_rename_stage.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect imm_rename_stage.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect imm_rename_stage.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect imm_rename_stage.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect imm_rename_stage.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect imm_rename_stage.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect imm_rename_stage.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect imm_rename_stage.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect imm_rename_stage.io.brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect imm_rename_stage.io.brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect imm_rename_stage.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect imm_rename_stage.io.brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect imm_rename_stage.io.brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect imm_rename_stage.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect imm_rename_stage.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect imm_rename_stage.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect imm_rename_stage.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect imm_rename_stage.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect imm_rename_stage.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect imm_rename_stage.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect imm_rename_stage.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect imm_rename_stage.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect imm_rename_stage.io.brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect imm_rename_stage.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect imm_rename_stage.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect imm_rename_stage.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect imm_rename_stage.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect imm_rename_stage.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect imm_rename_stage.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect imm_rename_stage.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect imm_rename_stage.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect imm_rename_stage.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect imm_rename_stage.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect imm_rename_stage.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect imm_rename_stage.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect imm_rename_stage.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect imm_rename_stage.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect imm_rename_stage.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect imm_rename_stage.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect imm_rename_stage.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect imm_rename_stage.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect imm_rename_stage.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect imm_rename_stage.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect imm_rename_stage.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect imm_rename_stage.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect imm_rename_stage.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect imm_rename_stage.io.brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect imm_rename_stage.io.brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect imm_rename_stage.io.brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect imm_rename_stage.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect imm_rename_stage.io.brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect imm_rename_stage.io.brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect imm_rename_stage.io.brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect imm_rename_stage.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect imm_rename_stage.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect imm_rename_stage.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect imm_rename_stage.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect imm_rename_stage.io.brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect imm_rename_stage.io.brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect imm_rename_stage.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect imm_rename_stage.io.brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect imm_rename_stage.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect imm_rename_stage.io.brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect imm_rename_stage.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect imm_rename_stage.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect imm_rename_stage.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect imm_rename_stage.io.brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect imm_rename_stage.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect imm_rename_stage.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect imm_rename_stage.io.brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect imm_rename_stage.io.brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect imm_rename_stage.io.brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect imm_rename_stage.io.brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect imm_rename_stage.io.brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect imm_rename_stage.io.brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect imm_rename_stage.io.brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect imm_rename_stage.io.brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect imm_rename_stage.io.brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect imm_rename_stage.io.brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect imm_rename_stage.io.brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect imm_rename_stage.io.brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect imm_rename_stage.io.brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect imm_rename_stage.io.brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect imm_rename_stage.io.brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect imm_rename_stage.io.brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect imm_rename_stage.io.brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect imm_rename_stage.io.brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect imm_rename_stage.io.brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect imm_rename_stage.io.brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect imm_rename_stage.io.brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect imm_rename_stage.io.brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect imm_rename_stage.io.brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect imm_rename_stage.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect imm_rename_stage.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect imm_rename_stage.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect imm_rename_stage.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect imm_rename_stage.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect imm_rename_stage.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect imm_rename_stage.io.debug_rob_empty, rob.io.empty connect imm_rename_stage.io.dec_fire[0], dec_fire[0] connect imm_rename_stage.io.dec_fire[1], dec_fire[1] connect imm_rename_stage.io.dec_uops[0].debug_tsrc, dec_uops[0].debug_tsrc connect imm_rename_stage.io.dec_uops[0].debug_fsrc, dec_uops[0].debug_fsrc connect imm_rename_stage.io.dec_uops[0].bp_xcpt_if, dec_uops[0].bp_xcpt_if connect imm_rename_stage.io.dec_uops[0].bp_debug_if, dec_uops[0].bp_debug_if connect imm_rename_stage.io.dec_uops[0].xcpt_ma_if, dec_uops[0].xcpt_ma_if connect imm_rename_stage.io.dec_uops[0].xcpt_ae_if, dec_uops[0].xcpt_ae_if connect imm_rename_stage.io.dec_uops[0].xcpt_pf_if, dec_uops[0].xcpt_pf_if connect imm_rename_stage.io.dec_uops[0].fp_typ, dec_uops[0].fp_typ connect imm_rename_stage.io.dec_uops[0].fp_rm, dec_uops[0].fp_rm connect imm_rename_stage.io.dec_uops[0].fp_val, dec_uops[0].fp_val connect imm_rename_stage.io.dec_uops[0].fcn_op, dec_uops[0].fcn_op connect imm_rename_stage.io.dec_uops[0].fcn_dw, dec_uops[0].fcn_dw connect imm_rename_stage.io.dec_uops[0].frs3_en, dec_uops[0].frs3_en connect imm_rename_stage.io.dec_uops[0].lrs2_rtype, dec_uops[0].lrs2_rtype connect imm_rename_stage.io.dec_uops[0].lrs1_rtype, dec_uops[0].lrs1_rtype connect imm_rename_stage.io.dec_uops[0].dst_rtype, dec_uops[0].dst_rtype connect imm_rename_stage.io.dec_uops[0].lrs3, dec_uops[0].lrs3 connect imm_rename_stage.io.dec_uops[0].lrs2, dec_uops[0].lrs2 connect imm_rename_stage.io.dec_uops[0].lrs1, dec_uops[0].lrs1 connect imm_rename_stage.io.dec_uops[0].ldst, dec_uops[0].ldst connect imm_rename_stage.io.dec_uops[0].ldst_is_rs1, dec_uops[0].ldst_is_rs1 connect imm_rename_stage.io.dec_uops[0].csr_cmd, dec_uops[0].csr_cmd connect imm_rename_stage.io.dec_uops[0].flush_on_commit, dec_uops[0].flush_on_commit connect imm_rename_stage.io.dec_uops[0].is_unique, dec_uops[0].is_unique connect imm_rename_stage.io.dec_uops[0].uses_stq, dec_uops[0].uses_stq connect imm_rename_stage.io.dec_uops[0].uses_ldq, dec_uops[0].uses_ldq connect imm_rename_stage.io.dec_uops[0].mem_signed, dec_uops[0].mem_signed connect imm_rename_stage.io.dec_uops[0].mem_size, dec_uops[0].mem_size connect imm_rename_stage.io.dec_uops[0].mem_cmd, dec_uops[0].mem_cmd connect imm_rename_stage.io.dec_uops[0].exc_cause, dec_uops[0].exc_cause connect imm_rename_stage.io.dec_uops[0].exception, dec_uops[0].exception connect imm_rename_stage.io.dec_uops[0].stale_pdst, dec_uops[0].stale_pdst connect imm_rename_stage.io.dec_uops[0].ppred_busy, dec_uops[0].ppred_busy connect imm_rename_stage.io.dec_uops[0].prs3_busy, dec_uops[0].prs3_busy connect imm_rename_stage.io.dec_uops[0].prs2_busy, dec_uops[0].prs2_busy connect imm_rename_stage.io.dec_uops[0].prs1_busy, dec_uops[0].prs1_busy connect imm_rename_stage.io.dec_uops[0].ppred, dec_uops[0].ppred connect imm_rename_stage.io.dec_uops[0].prs3, dec_uops[0].prs3 connect imm_rename_stage.io.dec_uops[0].prs2, dec_uops[0].prs2 connect imm_rename_stage.io.dec_uops[0].prs1, dec_uops[0].prs1 connect imm_rename_stage.io.dec_uops[0].pdst, dec_uops[0].pdst connect imm_rename_stage.io.dec_uops[0].rxq_idx, dec_uops[0].rxq_idx connect imm_rename_stage.io.dec_uops[0].stq_idx, dec_uops[0].stq_idx connect imm_rename_stage.io.dec_uops[0].ldq_idx, dec_uops[0].ldq_idx connect imm_rename_stage.io.dec_uops[0].rob_idx, dec_uops[0].rob_idx connect imm_rename_stage.io.dec_uops[0].fp_ctrl.vec, dec_uops[0].fp_ctrl.vec connect imm_rename_stage.io.dec_uops[0].fp_ctrl.wflags, dec_uops[0].fp_ctrl.wflags connect imm_rename_stage.io.dec_uops[0].fp_ctrl.sqrt, dec_uops[0].fp_ctrl.sqrt connect imm_rename_stage.io.dec_uops[0].fp_ctrl.div, dec_uops[0].fp_ctrl.div connect imm_rename_stage.io.dec_uops[0].fp_ctrl.fma, dec_uops[0].fp_ctrl.fma connect imm_rename_stage.io.dec_uops[0].fp_ctrl.fastpipe, dec_uops[0].fp_ctrl.fastpipe connect imm_rename_stage.io.dec_uops[0].fp_ctrl.toint, dec_uops[0].fp_ctrl.toint connect imm_rename_stage.io.dec_uops[0].fp_ctrl.fromint, dec_uops[0].fp_ctrl.fromint connect imm_rename_stage.io.dec_uops[0].fp_ctrl.typeTagOut, dec_uops[0].fp_ctrl.typeTagOut connect imm_rename_stage.io.dec_uops[0].fp_ctrl.typeTagIn, dec_uops[0].fp_ctrl.typeTagIn connect imm_rename_stage.io.dec_uops[0].fp_ctrl.swap23, dec_uops[0].fp_ctrl.swap23 connect imm_rename_stage.io.dec_uops[0].fp_ctrl.swap12, dec_uops[0].fp_ctrl.swap12 connect imm_rename_stage.io.dec_uops[0].fp_ctrl.ren3, dec_uops[0].fp_ctrl.ren3 connect imm_rename_stage.io.dec_uops[0].fp_ctrl.ren2, dec_uops[0].fp_ctrl.ren2 connect imm_rename_stage.io.dec_uops[0].fp_ctrl.ren1, dec_uops[0].fp_ctrl.ren1 connect imm_rename_stage.io.dec_uops[0].fp_ctrl.wen, dec_uops[0].fp_ctrl.wen connect imm_rename_stage.io.dec_uops[0].fp_ctrl.ldst, dec_uops[0].fp_ctrl.ldst connect imm_rename_stage.io.dec_uops[0].op2_sel, dec_uops[0].op2_sel connect imm_rename_stage.io.dec_uops[0].op1_sel, dec_uops[0].op1_sel connect imm_rename_stage.io.dec_uops[0].imm_packed, dec_uops[0].imm_packed connect imm_rename_stage.io.dec_uops[0].pimm, dec_uops[0].pimm connect imm_rename_stage.io.dec_uops[0].imm_sel, dec_uops[0].imm_sel connect imm_rename_stage.io.dec_uops[0].imm_rename, dec_uops[0].imm_rename connect imm_rename_stage.io.dec_uops[0].taken, dec_uops[0].taken connect imm_rename_stage.io.dec_uops[0].pc_lob, dec_uops[0].pc_lob connect imm_rename_stage.io.dec_uops[0].edge_inst, dec_uops[0].edge_inst connect imm_rename_stage.io.dec_uops[0].ftq_idx, dec_uops[0].ftq_idx connect imm_rename_stage.io.dec_uops[0].is_mov, dec_uops[0].is_mov connect imm_rename_stage.io.dec_uops[0].is_rocc, dec_uops[0].is_rocc connect imm_rename_stage.io.dec_uops[0].is_sys_pc2epc, dec_uops[0].is_sys_pc2epc connect imm_rename_stage.io.dec_uops[0].is_eret, dec_uops[0].is_eret connect imm_rename_stage.io.dec_uops[0].is_amo, dec_uops[0].is_amo connect imm_rename_stage.io.dec_uops[0].is_sfence, dec_uops[0].is_sfence connect imm_rename_stage.io.dec_uops[0].is_fencei, dec_uops[0].is_fencei connect imm_rename_stage.io.dec_uops[0].is_fence, dec_uops[0].is_fence connect imm_rename_stage.io.dec_uops[0].is_sfb, dec_uops[0].is_sfb connect imm_rename_stage.io.dec_uops[0].br_type, dec_uops[0].br_type connect imm_rename_stage.io.dec_uops[0].br_tag, dec_uops[0].br_tag connect imm_rename_stage.io.dec_uops[0].br_mask, dec_uops[0].br_mask connect imm_rename_stage.io.dec_uops[0].dis_col_sel, dec_uops[0].dis_col_sel connect imm_rename_stage.io.dec_uops[0].iw_p3_bypass_hint, dec_uops[0].iw_p3_bypass_hint connect imm_rename_stage.io.dec_uops[0].iw_p2_bypass_hint, dec_uops[0].iw_p2_bypass_hint connect imm_rename_stage.io.dec_uops[0].iw_p1_bypass_hint, dec_uops[0].iw_p1_bypass_hint connect imm_rename_stage.io.dec_uops[0].iw_p2_speculative_child, dec_uops[0].iw_p2_speculative_child connect imm_rename_stage.io.dec_uops[0].iw_p1_speculative_child, dec_uops[0].iw_p1_speculative_child connect imm_rename_stage.io.dec_uops[0].iw_issued_partial_dgen, dec_uops[0].iw_issued_partial_dgen connect imm_rename_stage.io.dec_uops[0].iw_issued_partial_agen, dec_uops[0].iw_issued_partial_agen connect imm_rename_stage.io.dec_uops[0].iw_issued, dec_uops[0].iw_issued connect imm_rename_stage.io.dec_uops[0].fu_code[0], dec_uops[0].fu_code[0] connect imm_rename_stage.io.dec_uops[0].fu_code[1], dec_uops[0].fu_code[1] connect imm_rename_stage.io.dec_uops[0].fu_code[2], dec_uops[0].fu_code[2] connect imm_rename_stage.io.dec_uops[0].fu_code[3], dec_uops[0].fu_code[3] connect imm_rename_stage.io.dec_uops[0].fu_code[4], dec_uops[0].fu_code[4] connect imm_rename_stage.io.dec_uops[0].fu_code[5], dec_uops[0].fu_code[5] connect imm_rename_stage.io.dec_uops[0].fu_code[6], dec_uops[0].fu_code[6] connect imm_rename_stage.io.dec_uops[0].fu_code[7], dec_uops[0].fu_code[7] connect imm_rename_stage.io.dec_uops[0].fu_code[8], dec_uops[0].fu_code[8] connect imm_rename_stage.io.dec_uops[0].fu_code[9], dec_uops[0].fu_code[9] connect imm_rename_stage.io.dec_uops[0].iq_type[0], dec_uops[0].iq_type[0] connect imm_rename_stage.io.dec_uops[0].iq_type[1], dec_uops[0].iq_type[1] connect imm_rename_stage.io.dec_uops[0].iq_type[2], dec_uops[0].iq_type[2] connect imm_rename_stage.io.dec_uops[0].iq_type[3], dec_uops[0].iq_type[3] connect imm_rename_stage.io.dec_uops[0].debug_pc, dec_uops[0].debug_pc connect imm_rename_stage.io.dec_uops[0].is_rvc, dec_uops[0].is_rvc connect imm_rename_stage.io.dec_uops[0].debug_inst, dec_uops[0].debug_inst connect imm_rename_stage.io.dec_uops[0].inst, dec_uops[0].inst connect imm_rename_stage.io.dec_uops[1].debug_tsrc, dec_uops[1].debug_tsrc connect imm_rename_stage.io.dec_uops[1].debug_fsrc, dec_uops[1].debug_fsrc connect imm_rename_stage.io.dec_uops[1].bp_xcpt_if, dec_uops[1].bp_xcpt_if connect imm_rename_stage.io.dec_uops[1].bp_debug_if, dec_uops[1].bp_debug_if connect imm_rename_stage.io.dec_uops[1].xcpt_ma_if, dec_uops[1].xcpt_ma_if connect imm_rename_stage.io.dec_uops[1].xcpt_ae_if, dec_uops[1].xcpt_ae_if connect imm_rename_stage.io.dec_uops[1].xcpt_pf_if, dec_uops[1].xcpt_pf_if connect imm_rename_stage.io.dec_uops[1].fp_typ, dec_uops[1].fp_typ connect imm_rename_stage.io.dec_uops[1].fp_rm, dec_uops[1].fp_rm connect imm_rename_stage.io.dec_uops[1].fp_val, dec_uops[1].fp_val connect imm_rename_stage.io.dec_uops[1].fcn_op, dec_uops[1].fcn_op connect imm_rename_stage.io.dec_uops[1].fcn_dw, dec_uops[1].fcn_dw connect imm_rename_stage.io.dec_uops[1].frs3_en, dec_uops[1].frs3_en connect imm_rename_stage.io.dec_uops[1].lrs2_rtype, dec_uops[1].lrs2_rtype connect imm_rename_stage.io.dec_uops[1].lrs1_rtype, dec_uops[1].lrs1_rtype connect imm_rename_stage.io.dec_uops[1].dst_rtype, dec_uops[1].dst_rtype connect imm_rename_stage.io.dec_uops[1].lrs3, dec_uops[1].lrs3 connect imm_rename_stage.io.dec_uops[1].lrs2, dec_uops[1].lrs2 connect imm_rename_stage.io.dec_uops[1].lrs1, dec_uops[1].lrs1 connect imm_rename_stage.io.dec_uops[1].ldst, dec_uops[1].ldst connect imm_rename_stage.io.dec_uops[1].ldst_is_rs1, dec_uops[1].ldst_is_rs1 connect imm_rename_stage.io.dec_uops[1].csr_cmd, dec_uops[1].csr_cmd connect imm_rename_stage.io.dec_uops[1].flush_on_commit, dec_uops[1].flush_on_commit connect imm_rename_stage.io.dec_uops[1].is_unique, dec_uops[1].is_unique connect imm_rename_stage.io.dec_uops[1].uses_stq, dec_uops[1].uses_stq connect imm_rename_stage.io.dec_uops[1].uses_ldq, dec_uops[1].uses_ldq connect imm_rename_stage.io.dec_uops[1].mem_signed, dec_uops[1].mem_signed connect imm_rename_stage.io.dec_uops[1].mem_size, dec_uops[1].mem_size connect imm_rename_stage.io.dec_uops[1].mem_cmd, dec_uops[1].mem_cmd connect imm_rename_stage.io.dec_uops[1].exc_cause, dec_uops[1].exc_cause connect imm_rename_stage.io.dec_uops[1].exception, dec_uops[1].exception connect imm_rename_stage.io.dec_uops[1].stale_pdst, dec_uops[1].stale_pdst connect imm_rename_stage.io.dec_uops[1].ppred_busy, dec_uops[1].ppred_busy connect imm_rename_stage.io.dec_uops[1].prs3_busy, dec_uops[1].prs3_busy connect imm_rename_stage.io.dec_uops[1].prs2_busy, dec_uops[1].prs2_busy connect imm_rename_stage.io.dec_uops[1].prs1_busy, dec_uops[1].prs1_busy connect imm_rename_stage.io.dec_uops[1].ppred, dec_uops[1].ppred connect imm_rename_stage.io.dec_uops[1].prs3, dec_uops[1].prs3 connect imm_rename_stage.io.dec_uops[1].prs2, dec_uops[1].prs2 connect imm_rename_stage.io.dec_uops[1].prs1, dec_uops[1].prs1 connect imm_rename_stage.io.dec_uops[1].pdst, dec_uops[1].pdst connect imm_rename_stage.io.dec_uops[1].rxq_idx, dec_uops[1].rxq_idx connect imm_rename_stage.io.dec_uops[1].stq_idx, dec_uops[1].stq_idx connect imm_rename_stage.io.dec_uops[1].ldq_idx, dec_uops[1].ldq_idx connect imm_rename_stage.io.dec_uops[1].rob_idx, dec_uops[1].rob_idx connect imm_rename_stage.io.dec_uops[1].fp_ctrl.vec, dec_uops[1].fp_ctrl.vec connect imm_rename_stage.io.dec_uops[1].fp_ctrl.wflags, dec_uops[1].fp_ctrl.wflags connect imm_rename_stage.io.dec_uops[1].fp_ctrl.sqrt, dec_uops[1].fp_ctrl.sqrt connect imm_rename_stage.io.dec_uops[1].fp_ctrl.div, dec_uops[1].fp_ctrl.div connect imm_rename_stage.io.dec_uops[1].fp_ctrl.fma, dec_uops[1].fp_ctrl.fma connect imm_rename_stage.io.dec_uops[1].fp_ctrl.fastpipe, dec_uops[1].fp_ctrl.fastpipe connect imm_rename_stage.io.dec_uops[1].fp_ctrl.toint, dec_uops[1].fp_ctrl.toint connect imm_rename_stage.io.dec_uops[1].fp_ctrl.fromint, dec_uops[1].fp_ctrl.fromint connect imm_rename_stage.io.dec_uops[1].fp_ctrl.typeTagOut, dec_uops[1].fp_ctrl.typeTagOut connect imm_rename_stage.io.dec_uops[1].fp_ctrl.typeTagIn, dec_uops[1].fp_ctrl.typeTagIn connect imm_rename_stage.io.dec_uops[1].fp_ctrl.swap23, dec_uops[1].fp_ctrl.swap23 connect imm_rename_stage.io.dec_uops[1].fp_ctrl.swap12, dec_uops[1].fp_ctrl.swap12 connect imm_rename_stage.io.dec_uops[1].fp_ctrl.ren3, dec_uops[1].fp_ctrl.ren3 connect imm_rename_stage.io.dec_uops[1].fp_ctrl.ren2, dec_uops[1].fp_ctrl.ren2 connect imm_rename_stage.io.dec_uops[1].fp_ctrl.ren1, dec_uops[1].fp_ctrl.ren1 connect imm_rename_stage.io.dec_uops[1].fp_ctrl.wen, dec_uops[1].fp_ctrl.wen connect imm_rename_stage.io.dec_uops[1].fp_ctrl.ldst, dec_uops[1].fp_ctrl.ldst connect imm_rename_stage.io.dec_uops[1].op2_sel, dec_uops[1].op2_sel connect imm_rename_stage.io.dec_uops[1].op1_sel, dec_uops[1].op1_sel connect imm_rename_stage.io.dec_uops[1].imm_packed, dec_uops[1].imm_packed connect imm_rename_stage.io.dec_uops[1].pimm, dec_uops[1].pimm connect imm_rename_stage.io.dec_uops[1].imm_sel, dec_uops[1].imm_sel connect imm_rename_stage.io.dec_uops[1].imm_rename, dec_uops[1].imm_rename connect imm_rename_stage.io.dec_uops[1].taken, dec_uops[1].taken connect imm_rename_stage.io.dec_uops[1].pc_lob, dec_uops[1].pc_lob connect imm_rename_stage.io.dec_uops[1].edge_inst, dec_uops[1].edge_inst connect imm_rename_stage.io.dec_uops[1].ftq_idx, dec_uops[1].ftq_idx connect imm_rename_stage.io.dec_uops[1].is_mov, dec_uops[1].is_mov connect imm_rename_stage.io.dec_uops[1].is_rocc, dec_uops[1].is_rocc connect imm_rename_stage.io.dec_uops[1].is_sys_pc2epc, dec_uops[1].is_sys_pc2epc connect imm_rename_stage.io.dec_uops[1].is_eret, dec_uops[1].is_eret connect imm_rename_stage.io.dec_uops[1].is_amo, dec_uops[1].is_amo connect imm_rename_stage.io.dec_uops[1].is_sfence, dec_uops[1].is_sfence connect imm_rename_stage.io.dec_uops[1].is_fencei, dec_uops[1].is_fencei connect imm_rename_stage.io.dec_uops[1].is_fence, dec_uops[1].is_fence connect imm_rename_stage.io.dec_uops[1].is_sfb, dec_uops[1].is_sfb connect imm_rename_stage.io.dec_uops[1].br_type, dec_uops[1].br_type connect imm_rename_stage.io.dec_uops[1].br_tag, dec_uops[1].br_tag connect imm_rename_stage.io.dec_uops[1].br_mask, dec_uops[1].br_mask connect imm_rename_stage.io.dec_uops[1].dis_col_sel, dec_uops[1].dis_col_sel connect imm_rename_stage.io.dec_uops[1].iw_p3_bypass_hint, dec_uops[1].iw_p3_bypass_hint connect imm_rename_stage.io.dec_uops[1].iw_p2_bypass_hint, dec_uops[1].iw_p2_bypass_hint connect imm_rename_stage.io.dec_uops[1].iw_p1_bypass_hint, dec_uops[1].iw_p1_bypass_hint connect imm_rename_stage.io.dec_uops[1].iw_p2_speculative_child, dec_uops[1].iw_p2_speculative_child connect imm_rename_stage.io.dec_uops[1].iw_p1_speculative_child, dec_uops[1].iw_p1_speculative_child connect imm_rename_stage.io.dec_uops[1].iw_issued_partial_dgen, dec_uops[1].iw_issued_partial_dgen connect imm_rename_stage.io.dec_uops[1].iw_issued_partial_agen, dec_uops[1].iw_issued_partial_agen connect imm_rename_stage.io.dec_uops[1].iw_issued, dec_uops[1].iw_issued connect imm_rename_stage.io.dec_uops[1].fu_code[0], dec_uops[1].fu_code[0] connect imm_rename_stage.io.dec_uops[1].fu_code[1], dec_uops[1].fu_code[1] connect imm_rename_stage.io.dec_uops[1].fu_code[2], dec_uops[1].fu_code[2] connect imm_rename_stage.io.dec_uops[1].fu_code[3], dec_uops[1].fu_code[3] connect imm_rename_stage.io.dec_uops[1].fu_code[4], dec_uops[1].fu_code[4] connect imm_rename_stage.io.dec_uops[1].fu_code[5], dec_uops[1].fu_code[5] connect imm_rename_stage.io.dec_uops[1].fu_code[6], dec_uops[1].fu_code[6] connect imm_rename_stage.io.dec_uops[1].fu_code[7], dec_uops[1].fu_code[7] connect imm_rename_stage.io.dec_uops[1].fu_code[8], dec_uops[1].fu_code[8] connect imm_rename_stage.io.dec_uops[1].fu_code[9], dec_uops[1].fu_code[9] connect imm_rename_stage.io.dec_uops[1].iq_type[0], dec_uops[1].iq_type[0] connect imm_rename_stage.io.dec_uops[1].iq_type[1], dec_uops[1].iq_type[1] connect imm_rename_stage.io.dec_uops[1].iq_type[2], dec_uops[1].iq_type[2] connect imm_rename_stage.io.dec_uops[1].iq_type[3], dec_uops[1].iq_type[3] connect imm_rename_stage.io.dec_uops[1].debug_pc, dec_uops[1].debug_pc connect imm_rename_stage.io.dec_uops[1].is_rvc, dec_uops[1].is_rvc connect imm_rename_stage.io.dec_uops[1].debug_inst, dec_uops[1].debug_inst connect imm_rename_stage.io.dec_uops[1].inst, dec_uops[1].inst connect imm_rename_stage.io.dis_fire[0], dis_fire[0] connect imm_rename_stage.io.dis_fire[1], dis_fire[1] connect imm_rename_stage.io.dis_ready, dis_ready connect imm_rename_stage.io.com_valids[0], rob.io.commit.valids[0] connect imm_rename_stage.io.com_valids[1], rob.io.commit.valids[1] connect imm_rename_stage.io.com_uops[0].debug_tsrc, rob.io.commit.uops[0].debug_tsrc connect imm_rename_stage.io.com_uops[0].debug_fsrc, rob.io.commit.uops[0].debug_fsrc connect imm_rename_stage.io.com_uops[0].bp_xcpt_if, rob.io.commit.uops[0].bp_xcpt_if connect imm_rename_stage.io.com_uops[0].bp_debug_if, rob.io.commit.uops[0].bp_debug_if connect imm_rename_stage.io.com_uops[0].xcpt_ma_if, rob.io.commit.uops[0].xcpt_ma_if connect imm_rename_stage.io.com_uops[0].xcpt_ae_if, rob.io.commit.uops[0].xcpt_ae_if connect imm_rename_stage.io.com_uops[0].xcpt_pf_if, rob.io.commit.uops[0].xcpt_pf_if connect imm_rename_stage.io.com_uops[0].fp_typ, rob.io.commit.uops[0].fp_typ connect imm_rename_stage.io.com_uops[0].fp_rm, rob.io.commit.uops[0].fp_rm connect imm_rename_stage.io.com_uops[0].fp_val, rob.io.commit.uops[0].fp_val connect imm_rename_stage.io.com_uops[0].fcn_op, rob.io.commit.uops[0].fcn_op connect imm_rename_stage.io.com_uops[0].fcn_dw, rob.io.commit.uops[0].fcn_dw connect imm_rename_stage.io.com_uops[0].frs3_en, rob.io.commit.uops[0].frs3_en connect imm_rename_stage.io.com_uops[0].lrs2_rtype, rob.io.commit.uops[0].lrs2_rtype connect imm_rename_stage.io.com_uops[0].lrs1_rtype, rob.io.commit.uops[0].lrs1_rtype connect imm_rename_stage.io.com_uops[0].dst_rtype, rob.io.commit.uops[0].dst_rtype connect imm_rename_stage.io.com_uops[0].lrs3, rob.io.commit.uops[0].lrs3 connect imm_rename_stage.io.com_uops[0].lrs2, rob.io.commit.uops[0].lrs2 connect imm_rename_stage.io.com_uops[0].lrs1, rob.io.commit.uops[0].lrs1 connect imm_rename_stage.io.com_uops[0].ldst, rob.io.commit.uops[0].ldst connect imm_rename_stage.io.com_uops[0].ldst_is_rs1, rob.io.commit.uops[0].ldst_is_rs1 connect imm_rename_stage.io.com_uops[0].csr_cmd, rob.io.commit.uops[0].csr_cmd connect imm_rename_stage.io.com_uops[0].flush_on_commit, rob.io.commit.uops[0].flush_on_commit connect imm_rename_stage.io.com_uops[0].is_unique, rob.io.commit.uops[0].is_unique connect imm_rename_stage.io.com_uops[0].uses_stq, rob.io.commit.uops[0].uses_stq connect imm_rename_stage.io.com_uops[0].uses_ldq, rob.io.commit.uops[0].uses_ldq connect imm_rename_stage.io.com_uops[0].mem_signed, rob.io.commit.uops[0].mem_signed connect imm_rename_stage.io.com_uops[0].mem_size, rob.io.commit.uops[0].mem_size connect imm_rename_stage.io.com_uops[0].mem_cmd, rob.io.commit.uops[0].mem_cmd connect imm_rename_stage.io.com_uops[0].exc_cause, rob.io.commit.uops[0].exc_cause connect imm_rename_stage.io.com_uops[0].exception, rob.io.commit.uops[0].exception connect imm_rename_stage.io.com_uops[0].stale_pdst, rob.io.commit.uops[0].stale_pdst connect imm_rename_stage.io.com_uops[0].ppred_busy, rob.io.commit.uops[0].ppred_busy connect imm_rename_stage.io.com_uops[0].prs3_busy, rob.io.commit.uops[0].prs3_busy connect imm_rename_stage.io.com_uops[0].prs2_busy, rob.io.commit.uops[0].prs2_busy connect imm_rename_stage.io.com_uops[0].prs1_busy, rob.io.commit.uops[0].prs1_busy connect imm_rename_stage.io.com_uops[0].ppred, rob.io.commit.uops[0].ppred connect imm_rename_stage.io.com_uops[0].prs3, rob.io.commit.uops[0].prs3 connect imm_rename_stage.io.com_uops[0].prs2, rob.io.commit.uops[0].prs2 connect imm_rename_stage.io.com_uops[0].prs1, rob.io.commit.uops[0].prs1 connect imm_rename_stage.io.com_uops[0].pdst, rob.io.commit.uops[0].pdst connect imm_rename_stage.io.com_uops[0].rxq_idx, rob.io.commit.uops[0].rxq_idx connect imm_rename_stage.io.com_uops[0].stq_idx, rob.io.commit.uops[0].stq_idx connect imm_rename_stage.io.com_uops[0].ldq_idx, rob.io.commit.uops[0].ldq_idx connect imm_rename_stage.io.com_uops[0].rob_idx, rob.io.commit.uops[0].rob_idx connect imm_rename_stage.io.com_uops[0].fp_ctrl.vec, rob.io.commit.uops[0].fp_ctrl.vec connect imm_rename_stage.io.com_uops[0].fp_ctrl.wflags, rob.io.commit.uops[0].fp_ctrl.wflags connect imm_rename_stage.io.com_uops[0].fp_ctrl.sqrt, rob.io.commit.uops[0].fp_ctrl.sqrt connect imm_rename_stage.io.com_uops[0].fp_ctrl.div, rob.io.commit.uops[0].fp_ctrl.div connect imm_rename_stage.io.com_uops[0].fp_ctrl.fma, rob.io.commit.uops[0].fp_ctrl.fma connect imm_rename_stage.io.com_uops[0].fp_ctrl.fastpipe, rob.io.commit.uops[0].fp_ctrl.fastpipe connect imm_rename_stage.io.com_uops[0].fp_ctrl.toint, rob.io.commit.uops[0].fp_ctrl.toint connect imm_rename_stage.io.com_uops[0].fp_ctrl.fromint, rob.io.commit.uops[0].fp_ctrl.fromint connect imm_rename_stage.io.com_uops[0].fp_ctrl.typeTagOut, rob.io.commit.uops[0].fp_ctrl.typeTagOut connect imm_rename_stage.io.com_uops[0].fp_ctrl.typeTagIn, rob.io.commit.uops[0].fp_ctrl.typeTagIn connect imm_rename_stage.io.com_uops[0].fp_ctrl.swap23, rob.io.commit.uops[0].fp_ctrl.swap23 connect imm_rename_stage.io.com_uops[0].fp_ctrl.swap12, rob.io.commit.uops[0].fp_ctrl.swap12 connect imm_rename_stage.io.com_uops[0].fp_ctrl.ren3, rob.io.commit.uops[0].fp_ctrl.ren3 connect imm_rename_stage.io.com_uops[0].fp_ctrl.ren2, rob.io.commit.uops[0].fp_ctrl.ren2 connect imm_rename_stage.io.com_uops[0].fp_ctrl.ren1, rob.io.commit.uops[0].fp_ctrl.ren1 connect imm_rename_stage.io.com_uops[0].fp_ctrl.wen, rob.io.commit.uops[0].fp_ctrl.wen connect imm_rename_stage.io.com_uops[0].fp_ctrl.ldst, rob.io.commit.uops[0].fp_ctrl.ldst connect imm_rename_stage.io.com_uops[0].op2_sel, rob.io.commit.uops[0].op2_sel connect imm_rename_stage.io.com_uops[0].op1_sel, rob.io.commit.uops[0].op1_sel connect imm_rename_stage.io.com_uops[0].imm_packed, rob.io.commit.uops[0].imm_packed connect imm_rename_stage.io.com_uops[0].pimm, rob.io.commit.uops[0].pimm connect imm_rename_stage.io.com_uops[0].imm_sel, rob.io.commit.uops[0].imm_sel connect imm_rename_stage.io.com_uops[0].imm_rename, rob.io.commit.uops[0].imm_rename connect imm_rename_stage.io.com_uops[0].taken, rob.io.commit.uops[0].taken connect imm_rename_stage.io.com_uops[0].pc_lob, rob.io.commit.uops[0].pc_lob connect imm_rename_stage.io.com_uops[0].edge_inst, rob.io.commit.uops[0].edge_inst connect imm_rename_stage.io.com_uops[0].ftq_idx, rob.io.commit.uops[0].ftq_idx connect imm_rename_stage.io.com_uops[0].is_mov, rob.io.commit.uops[0].is_mov connect imm_rename_stage.io.com_uops[0].is_rocc, rob.io.commit.uops[0].is_rocc connect imm_rename_stage.io.com_uops[0].is_sys_pc2epc, rob.io.commit.uops[0].is_sys_pc2epc connect imm_rename_stage.io.com_uops[0].is_eret, rob.io.commit.uops[0].is_eret connect imm_rename_stage.io.com_uops[0].is_amo, rob.io.commit.uops[0].is_amo connect imm_rename_stage.io.com_uops[0].is_sfence, rob.io.commit.uops[0].is_sfence connect imm_rename_stage.io.com_uops[0].is_fencei, rob.io.commit.uops[0].is_fencei connect imm_rename_stage.io.com_uops[0].is_fence, rob.io.commit.uops[0].is_fence connect imm_rename_stage.io.com_uops[0].is_sfb, rob.io.commit.uops[0].is_sfb connect imm_rename_stage.io.com_uops[0].br_type, rob.io.commit.uops[0].br_type connect imm_rename_stage.io.com_uops[0].br_tag, rob.io.commit.uops[0].br_tag connect imm_rename_stage.io.com_uops[0].br_mask, rob.io.commit.uops[0].br_mask connect imm_rename_stage.io.com_uops[0].dis_col_sel, rob.io.commit.uops[0].dis_col_sel connect imm_rename_stage.io.com_uops[0].iw_p3_bypass_hint, rob.io.commit.uops[0].iw_p3_bypass_hint connect imm_rename_stage.io.com_uops[0].iw_p2_bypass_hint, rob.io.commit.uops[0].iw_p2_bypass_hint connect imm_rename_stage.io.com_uops[0].iw_p1_bypass_hint, rob.io.commit.uops[0].iw_p1_bypass_hint connect imm_rename_stage.io.com_uops[0].iw_p2_speculative_child, rob.io.commit.uops[0].iw_p2_speculative_child connect imm_rename_stage.io.com_uops[0].iw_p1_speculative_child, rob.io.commit.uops[0].iw_p1_speculative_child connect imm_rename_stage.io.com_uops[0].iw_issued_partial_dgen, rob.io.commit.uops[0].iw_issued_partial_dgen connect imm_rename_stage.io.com_uops[0].iw_issued_partial_agen, rob.io.commit.uops[0].iw_issued_partial_agen connect imm_rename_stage.io.com_uops[0].iw_issued, rob.io.commit.uops[0].iw_issued connect imm_rename_stage.io.com_uops[0].fu_code[0], rob.io.commit.uops[0].fu_code[0] connect imm_rename_stage.io.com_uops[0].fu_code[1], rob.io.commit.uops[0].fu_code[1] connect imm_rename_stage.io.com_uops[0].fu_code[2], rob.io.commit.uops[0].fu_code[2] connect imm_rename_stage.io.com_uops[0].fu_code[3], rob.io.commit.uops[0].fu_code[3] connect imm_rename_stage.io.com_uops[0].fu_code[4], rob.io.commit.uops[0].fu_code[4] connect imm_rename_stage.io.com_uops[0].fu_code[5], rob.io.commit.uops[0].fu_code[5] connect imm_rename_stage.io.com_uops[0].fu_code[6], rob.io.commit.uops[0].fu_code[6] connect imm_rename_stage.io.com_uops[0].fu_code[7], rob.io.commit.uops[0].fu_code[7] connect imm_rename_stage.io.com_uops[0].fu_code[8], rob.io.commit.uops[0].fu_code[8] connect imm_rename_stage.io.com_uops[0].fu_code[9], rob.io.commit.uops[0].fu_code[9] connect imm_rename_stage.io.com_uops[0].iq_type[0], rob.io.commit.uops[0].iq_type[0] connect imm_rename_stage.io.com_uops[0].iq_type[1], rob.io.commit.uops[0].iq_type[1] connect imm_rename_stage.io.com_uops[0].iq_type[2], rob.io.commit.uops[0].iq_type[2] connect imm_rename_stage.io.com_uops[0].iq_type[3], rob.io.commit.uops[0].iq_type[3] connect imm_rename_stage.io.com_uops[0].debug_pc, rob.io.commit.uops[0].debug_pc connect imm_rename_stage.io.com_uops[0].is_rvc, rob.io.commit.uops[0].is_rvc connect imm_rename_stage.io.com_uops[0].debug_inst, rob.io.commit.uops[0].debug_inst connect imm_rename_stage.io.com_uops[0].inst, rob.io.commit.uops[0].inst connect imm_rename_stage.io.com_uops[1].debug_tsrc, rob.io.commit.uops[1].debug_tsrc connect imm_rename_stage.io.com_uops[1].debug_fsrc, rob.io.commit.uops[1].debug_fsrc connect imm_rename_stage.io.com_uops[1].bp_xcpt_if, rob.io.commit.uops[1].bp_xcpt_if connect imm_rename_stage.io.com_uops[1].bp_debug_if, rob.io.commit.uops[1].bp_debug_if connect imm_rename_stage.io.com_uops[1].xcpt_ma_if, rob.io.commit.uops[1].xcpt_ma_if connect imm_rename_stage.io.com_uops[1].xcpt_ae_if, rob.io.commit.uops[1].xcpt_ae_if connect imm_rename_stage.io.com_uops[1].xcpt_pf_if, rob.io.commit.uops[1].xcpt_pf_if connect imm_rename_stage.io.com_uops[1].fp_typ, rob.io.commit.uops[1].fp_typ connect imm_rename_stage.io.com_uops[1].fp_rm, rob.io.commit.uops[1].fp_rm connect imm_rename_stage.io.com_uops[1].fp_val, rob.io.commit.uops[1].fp_val connect imm_rename_stage.io.com_uops[1].fcn_op, rob.io.commit.uops[1].fcn_op connect imm_rename_stage.io.com_uops[1].fcn_dw, rob.io.commit.uops[1].fcn_dw connect imm_rename_stage.io.com_uops[1].frs3_en, rob.io.commit.uops[1].frs3_en connect imm_rename_stage.io.com_uops[1].lrs2_rtype, rob.io.commit.uops[1].lrs2_rtype connect imm_rename_stage.io.com_uops[1].lrs1_rtype, rob.io.commit.uops[1].lrs1_rtype connect imm_rename_stage.io.com_uops[1].dst_rtype, rob.io.commit.uops[1].dst_rtype connect imm_rename_stage.io.com_uops[1].lrs3, rob.io.commit.uops[1].lrs3 connect imm_rename_stage.io.com_uops[1].lrs2, rob.io.commit.uops[1].lrs2 connect imm_rename_stage.io.com_uops[1].lrs1, rob.io.commit.uops[1].lrs1 connect imm_rename_stage.io.com_uops[1].ldst, rob.io.commit.uops[1].ldst connect imm_rename_stage.io.com_uops[1].ldst_is_rs1, rob.io.commit.uops[1].ldst_is_rs1 connect imm_rename_stage.io.com_uops[1].csr_cmd, rob.io.commit.uops[1].csr_cmd connect imm_rename_stage.io.com_uops[1].flush_on_commit, rob.io.commit.uops[1].flush_on_commit connect imm_rename_stage.io.com_uops[1].is_unique, rob.io.commit.uops[1].is_unique connect imm_rename_stage.io.com_uops[1].uses_stq, rob.io.commit.uops[1].uses_stq connect imm_rename_stage.io.com_uops[1].uses_ldq, rob.io.commit.uops[1].uses_ldq connect imm_rename_stage.io.com_uops[1].mem_signed, rob.io.commit.uops[1].mem_signed connect imm_rename_stage.io.com_uops[1].mem_size, rob.io.commit.uops[1].mem_size connect imm_rename_stage.io.com_uops[1].mem_cmd, rob.io.commit.uops[1].mem_cmd connect imm_rename_stage.io.com_uops[1].exc_cause, rob.io.commit.uops[1].exc_cause connect imm_rename_stage.io.com_uops[1].exception, rob.io.commit.uops[1].exception connect imm_rename_stage.io.com_uops[1].stale_pdst, rob.io.commit.uops[1].stale_pdst connect imm_rename_stage.io.com_uops[1].ppred_busy, rob.io.commit.uops[1].ppred_busy connect imm_rename_stage.io.com_uops[1].prs3_busy, rob.io.commit.uops[1].prs3_busy connect imm_rename_stage.io.com_uops[1].prs2_busy, rob.io.commit.uops[1].prs2_busy connect imm_rename_stage.io.com_uops[1].prs1_busy, rob.io.commit.uops[1].prs1_busy connect imm_rename_stage.io.com_uops[1].ppred, rob.io.commit.uops[1].ppred connect imm_rename_stage.io.com_uops[1].prs3, rob.io.commit.uops[1].prs3 connect imm_rename_stage.io.com_uops[1].prs2, rob.io.commit.uops[1].prs2 connect imm_rename_stage.io.com_uops[1].prs1, rob.io.commit.uops[1].prs1 connect imm_rename_stage.io.com_uops[1].pdst, rob.io.commit.uops[1].pdst connect imm_rename_stage.io.com_uops[1].rxq_idx, rob.io.commit.uops[1].rxq_idx connect imm_rename_stage.io.com_uops[1].stq_idx, rob.io.commit.uops[1].stq_idx connect imm_rename_stage.io.com_uops[1].ldq_idx, rob.io.commit.uops[1].ldq_idx connect imm_rename_stage.io.com_uops[1].rob_idx, rob.io.commit.uops[1].rob_idx connect imm_rename_stage.io.com_uops[1].fp_ctrl.vec, rob.io.commit.uops[1].fp_ctrl.vec connect imm_rename_stage.io.com_uops[1].fp_ctrl.wflags, rob.io.commit.uops[1].fp_ctrl.wflags connect imm_rename_stage.io.com_uops[1].fp_ctrl.sqrt, rob.io.commit.uops[1].fp_ctrl.sqrt connect imm_rename_stage.io.com_uops[1].fp_ctrl.div, rob.io.commit.uops[1].fp_ctrl.div connect imm_rename_stage.io.com_uops[1].fp_ctrl.fma, rob.io.commit.uops[1].fp_ctrl.fma connect imm_rename_stage.io.com_uops[1].fp_ctrl.fastpipe, rob.io.commit.uops[1].fp_ctrl.fastpipe connect imm_rename_stage.io.com_uops[1].fp_ctrl.toint, rob.io.commit.uops[1].fp_ctrl.toint connect imm_rename_stage.io.com_uops[1].fp_ctrl.fromint, rob.io.commit.uops[1].fp_ctrl.fromint connect imm_rename_stage.io.com_uops[1].fp_ctrl.typeTagOut, rob.io.commit.uops[1].fp_ctrl.typeTagOut connect imm_rename_stage.io.com_uops[1].fp_ctrl.typeTagIn, rob.io.commit.uops[1].fp_ctrl.typeTagIn connect imm_rename_stage.io.com_uops[1].fp_ctrl.swap23, rob.io.commit.uops[1].fp_ctrl.swap23 connect imm_rename_stage.io.com_uops[1].fp_ctrl.swap12, rob.io.commit.uops[1].fp_ctrl.swap12 connect imm_rename_stage.io.com_uops[1].fp_ctrl.ren3, rob.io.commit.uops[1].fp_ctrl.ren3 connect imm_rename_stage.io.com_uops[1].fp_ctrl.ren2, rob.io.commit.uops[1].fp_ctrl.ren2 connect imm_rename_stage.io.com_uops[1].fp_ctrl.ren1, rob.io.commit.uops[1].fp_ctrl.ren1 connect imm_rename_stage.io.com_uops[1].fp_ctrl.wen, rob.io.commit.uops[1].fp_ctrl.wen connect imm_rename_stage.io.com_uops[1].fp_ctrl.ldst, rob.io.commit.uops[1].fp_ctrl.ldst connect imm_rename_stage.io.com_uops[1].op2_sel, rob.io.commit.uops[1].op2_sel connect imm_rename_stage.io.com_uops[1].op1_sel, rob.io.commit.uops[1].op1_sel connect imm_rename_stage.io.com_uops[1].imm_packed, rob.io.commit.uops[1].imm_packed connect imm_rename_stage.io.com_uops[1].pimm, rob.io.commit.uops[1].pimm connect imm_rename_stage.io.com_uops[1].imm_sel, rob.io.commit.uops[1].imm_sel connect imm_rename_stage.io.com_uops[1].imm_rename, rob.io.commit.uops[1].imm_rename connect imm_rename_stage.io.com_uops[1].taken, rob.io.commit.uops[1].taken connect imm_rename_stage.io.com_uops[1].pc_lob, rob.io.commit.uops[1].pc_lob connect imm_rename_stage.io.com_uops[1].edge_inst, rob.io.commit.uops[1].edge_inst connect imm_rename_stage.io.com_uops[1].ftq_idx, rob.io.commit.uops[1].ftq_idx connect imm_rename_stage.io.com_uops[1].is_mov, rob.io.commit.uops[1].is_mov connect imm_rename_stage.io.com_uops[1].is_rocc, rob.io.commit.uops[1].is_rocc connect imm_rename_stage.io.com_uops[1].is_sys_pc2epc, rob.io.commit.uops[1].is_sys_pc2epc connect imm_rename_stage.io.com_uops[1].is_eret, rob.io.commit.uops[1].is_eret connect imm_rename_stage.io.com_uops[1].is_amo, rob.io.commit.uops[1].is_amo connect imm_rename_stage.io.com_uops[1].is_sfence, rob.io.commit.uops[1].is_sfence connect imm_rename_stage.io.com_uops[1].is_fencei, rob.io.commit.uops[1].is_fencei connect imm_rename_stage.io.com_uops[1].is_fence, rob.io.commit.uops[1].is_fence connect imm_rename_stage.io.com_uops[1].is_sfb, rob.io.commit.uops[1].is_sfb connect imm_rename_stage.io.com_uops[1].br_type, rob.io.commit.uops[1].br_type connect imm_rename_stage.io.com_uops[1].br_tag, rob.io.commit.uops[1].br_tag connect imm_rename_stage.io.com_uops[1].br_mask, rob.io.commit.uops[1].br_mask connect imm_rename_stage.io.com_uops[1].dis_col_sel, rob.io.commit.uops[1].dis_col_sel connect imm_rename_stage.io.com_uops[1].iw_p3_bypass_hint, rob.io.commit.uops[1].iw_p3_bypass_hint connect imm_rename_stage.io.com_uops[1].iw_p2_bypass_hint, rob.io.commit.uops[1].iw_p2_bypass_hint connect imm_rename_stage.io.com_uops[1].iw_p1_bypass_hint, rob.io.commit.uops[1].iw_p1_bypass_hint connect imm_rename_stage.io.com_uops[1].iw_p2_speculative_child, rob.io.commit.uops[1].iw_p2_speculative_child connect imm_rename_stage.io.com_uops[1].iw_p1_speculative_child, rob.io.commit.uops[1].iw_p1_speculative_child connect imm_rename_stage.io.com_uops[1].iw_issued_partial_dgen, rob.io.commit.uops[1].iw_issued_partial_dgen connect imm_rename_stage.io.com_uops[1].iw_issued_partial_agen, rob.io.commit.uops[1].iw_issued_partial_agen connect imm_rename_stage.io.com_uops[1].iw_issued, rob.io.commit.uops[1].iw_issued connect imm_rename_stage.io.com_uops[1].fu_code[0], rob.io.commit.uops[1].fu_code[0] connect imm_rename_stage.io.com_uops[1].fu_code[1], rob.io.commit.uops[1].fu_code[1] connect imm_rename_stage.io.com_uops[1].fu_code[2], rob.io.commit.uops[1].fu_code[2] connect imm_rename_stage.io.com_uops[1].fu_code[3], rob.io.commit.uops[1].fu_code[3] connect imm_rename_stage.io.com_uops[1].fu_code[4], rob.io.commit.uops[1].fu_code[4] connect imm_rename_stage.io.com_uops[1].fu_code[5], rob.io.commit.uops[1].fu_code[5] connect imm_rename_stage.io.com_uops[1].fu_code[6], rob.io.commit.uops[1].fu_code[6] connect imm_rename_stage.io.com_uops[1].fu_code[7], rob.io.commit.uops[1].fu_code[7] connect imm_rename_stage.io.com_uops[1].fu_code[8], rob.io.commit.uops[1].fu_code[8] connect imm_rename_stage.io.com_uops[1].fu_code[9], rob.io.commit.uops[1].fu_code[9] connect imm_rename_stage.io.com_uops[1].iq_type[0], rob.io.commit.uops[1].iq_type[0] connect imm_rename_stage.io.com_uops[1].iq_type[1], rob.io.commit.uops[1].iq_type[1] connect imm_rename_stage.io.com_uops[1].iq_type[2], rob.io.commit.uops[1].iq_type[2] connect imm_rename_stage.io.com_uops[1].iq_type[3], rob.io.commit.uops[1].iq_type[3] connect imm_rename_stage.io.com_uops[1].debug_pc, rob.io.commit.uops[1].debug_pc connect imm_rename_stage.io.com_uops[1].is_rvc, rob.io.commit.uops[1].is_rvc connect imm_rename_stage.io.com_uops[1].debug_inst, rob.io.commit.uops[1].debug_inst connect imm_rename_stage.io.com_uops[1].inst, rob.io.commit.uops[1].inst connect imm_rename_stage.io.rollback, rob.io.rollback connect fp_rename_stage.io.kill, io.ifu.redirect_flush connect fp_rename_stage.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect fp_rename_stage.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect fp_rename_stage.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect fp_rename_stage.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect fp_rename_stage.io.brupdate.b2.taken, brupdate.b2.taken connect fp_rename_stage.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect fp_rename_stage.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect fp_rename_stage.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect fp_rename_stage.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect fp_rename_stage.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect fp_rename_stage.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect fp_rename_stage.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect fp_rename_stage.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect fp_rename_stage.io.brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect fp_rename_stage.io.brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect fp_rename_stage.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect fp_rename_stage.io.brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect fp_rename_stage.io.brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect fp_rename_stage.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect fp_rename_stage.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect fp_rename_stage.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect fp_rename_stage.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect fp_rename_stage.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect fp_rename_stage.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect fp_rename_stage.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect fp_rename_stage.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect fp_rename_stage.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect fp_rename_stage.io.brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect fp_rename_stage.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect fp_rename_stage.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect fp_rename_stage.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect fp_rename_stage.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect fp_rename_stage.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect fp_rename_stage.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect fp_rename_stage.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect fp_rename_stage.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect fp_rename_stage.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect fp_rename_stage.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect fp_rename_stage.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect fp_rename_stage.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect fp_rename_stage.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect fp_rename_stage.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect fp_rename_stage.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect fp_rename_stage.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect fp_rename_stage.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect fp_rename_stage.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect fp_rename_stage.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect fp_rename_stage.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect fp_rename_stage.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect fp_rename_stage.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect fp_rename_stage.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect fp_rename_stage.io.brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect fp_rename_stage.io.brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect fp_rename_stage.io.brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect fp_rename_stage.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect fp_rename_stage.io.brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect fp_rename_stage.io.brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect fp_rename_stage.io.brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect fp_rename_stage.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect fp_rename_stage.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect fp_rename_stage.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect fp_rename_stage.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect fp_rename_stage.io.brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect fp_rename_stage.io.brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect fp_rename_stage.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect fp_rename_stage.io.brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect fp_rename_stage.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect fp_rename_stage.io.brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect fp_rename_stage.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect fp_rename_stage.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect fp_rename_stage.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect fp_rename_stage.io.brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect fp_rename_stage.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect fp_rename_stage.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect fp_rename_stage.io.brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect fp_rename_stage.io.brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect fp_rename_stage.io.brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect fp_rename_stage.io.brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect fp_rename_stage.io.brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect fp_rename_stage.io.brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect fp_rename_stage.io.brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect fp_rename_stage.io.brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect fp_rename_stage.io.brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect fp_rename_stage.io.brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect fp_rename_stage.io.brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect fp_rename_stage.io.brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect fp_rename_stage.io.brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect fp_rename_stage.io.brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect fp_rename_stage.io.brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect fp_rename_stage.io.brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect fp_rename_stage.io.brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect fp_rename_stage.io.brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect fp_rename_stage.io.brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect fp_rename_stage.io.brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect fp_rename_stage.io.brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect fp_rename_stage.io.brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect fp_rename_stage.io.brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect fp_rename_stage.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect fp_rename_stage.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect fp_rename_stage.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect fp_rename_stage.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect fp_rename_stage.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect fp_rename_stage.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask connect fp_rename_stage.io.debug_rob_empty, rob.io.empty connect fp_rename_stage.io.dec_fire[0], dec_fire[0] connect fp_rename_stage.io.dec_fire[1], dec_fire[1] connect fp_rename_stage.io.dec_uops[0].debug_tsrc, dec_uops[0].debug_tsrc connect fp_rename_stage.io.dec_uops[0].debug_fsrc, dec_uops[0].debug_fsrc connect fp_rename_stage.io.dec_uops[0].bp_xcpt_if, dec_uops[0].bp_xcpt_if connect fp_rename_stage.io.dec_uops[0].bp_debug_if, dec_uops[0].bp_debug_if connect fp_rename_stage.io.dec_uops[0].xcpt_ma_if, dec_uops[0].xcpt_ma_if connect fp_rename_stage.io.dec_uops[0].xcpt_ae_if, dec_uops[0].xcpt_ae_if connect fp_rename_stage.io.dec_uops[0].xcpt_pf_if, dec_uops[0].xcpt_pf_if connect fp_rename_stage.io.dec_uops[0].fp_typ, dec_uops[0].fp_typ connect fp_rename_stage.io.dec_uops[0].fp_rm, dec_uops[0].fp_rm connect fp_rename_stage.io.dec_uops[0].fp_val, dec_uops[0].fp_val connect fp_rename_stage.io.dec_uops[0].fcn_op, dec_uops[0].fcn_op connect fp_rename_stage.io.dec_uops[0].fcn_dw, dec_uops[0].fcn_dw connect fp_rename_stage.io.dec_uops[0].frs3_en, dec_uops[0].frs3_en connect fp_rename_stage.io.dec_uops[0].lrs2_rtype, dec_uops[0].lrs2_rtype connect fp_rename_stage.io.dec_uops[0].lrs1_rtype, dec_uops[0].lrs1_rtype connect fp_rename_stage.io.dec_uops[0].dst_rtype, dec_uops[0].dst_rtype connect fp_rename_stage.io.dec_uops[0].lrs3, dec_uops[0].lrs3 connect fp_rename_stage.io.dec_uops[0].lrs2, dec_uops[0].lrs2 connect fp_rename_stage.io.dec_uops[0].lrs1, dec_uops[0].lrs1 connect fp_rename_stage.io.dec_uops[0].ldst, dec_uops[0].ldst connect fp_rename_stage.io.dec_uops[0].ldst_is_rs1, dec_uops[0].ldst_is_rs1 connect fp_rename_stage.io.dec_uops[0].csr_cmd, dec_uops[0].csr_cmd connect fp_rename_stage.io.dec_uops[0].flush_on_commit, dec_uops[0].flush_on_commit connect fp_rename_stage.io.dec_uops[0].is_unique, dec_uops[0].is_unique connect fp_rename_stage.io.dec_uops[0].uses_stq, dec_uops[0].uses_stq connect fp_rename_stage.io.dec_uops[0].uses_ldq, dec_uops[0].uses_ldq connect fp_rename_stage.io.dec_uops[0].mem_signed, dec_uops[0].mem_signed connect fp_rename_stage.io.dec_uops[0].mem_size, dec_uops[0].mem_size connect fp_rename_stage.io.dec_uops[0].mem_cmd, dec_uops[0].mem_cmd connect fp_rename_stage.io.dec_uops[0].exc_cause, dec_uops[0].exc_cause connect fp_rename_stage.io.dec_uops[0].exception, dec_uops[0].exception connect fp_rename_stage.io.dec_uops[0].stale_pdst, dec_uops[0].stale_pdst connect fp_rename_stage.io.dec_uops[0].ppred_busy, dec_uops[0].ppred_busy connect fp_rename_stage.io.dec_uops[0].prs3_busy, dec_uops[0].prs3_busy connect fp_rename_stage.io.dec_uops[0].prs2_busy, dec_uops[0].prs2_busy connect fp_rename_stage.io.dec_uops[0].prs1_busy, dec_uops[0].prs1_busy connect fp_rename_stage.io.dec_uops[0].ppred, dec_uops[0].ppred connect fp_rename_stage.io.dec_uops[0].prs3, dec_uops[0].prs3 connect fp_rename_stage.io.dec_uops[0].prs2, dec_uops[0].prs2 connect fp_rename_stage.io.dec_uops[0].prs1, dec_uops[0].prs1 connect fp_rename_stage.io.dec_uops[0].pdst, dec_uops[0].pdst connect fp_rename_stage.io.dec_uops[0].rxq_idx, dec_uops[0].rxq_idx connect fp_rename_stage.io.dec_uops[0].stq_idx, dec_uops[0].stq_idx connect fp_rename_stage.io.dec_uops[0].ldq_idx, dec_uops[0].ldq_idx connect fp_rename_stage.io.dec_uops[0].rob_idx, dec_uops[0].rob_idx connect fp_rename_stage.io.dec_uops[0].fp_ctrl.vec, dec_uops[0].fp_ctrl.vec connect fp_rename_stage.io.dec_uops[0].fp_ctrl.wflags, dec_uops[0].fp_ctrl.wflags connect fp_rename_stage.io.dec_uops[0].fp_ctrl.sqrt, dec_uops[0].fp_ctrl.sqrt connect fp_rename_stage.io.dec_uops[0].fp_ctrl.div, dec_uops[0].fp_ctrl.div connect fp_rename_stage.io.dec_uops[0].fp_ctrl.fma, dec_uops[0].fp_ctrl.fma connect fp_rename_stage.io.dec_uops[0].fp_ctrl.fastpipe, dec_uops[0].fp_ctrl.fastpipe connect fp_rename_stage.io.dec_uops[0].fp_ctrl.toint, dec_uops[0].fp_ctrl.toint connect fp_rename_stage.io.dec_uops[0].fp_ctrl.fromint, dec_uops[0].fp_ctrl.fromint connect fp_rename_stage.io.dec_uops[0].fp_ctrl.typeTagOut, dec_uops[0].fp_ctrl.typeTagOut connect fp_rename_stage.io.dec_uops[0].fp_ctrl.typeTagIn, dec_uops[0].fp_ctrl.typeTagIn connect fp_rename_stage.io.dec_uops[0].fp_ctrl.swap23, dec_uops[0].fp_ctrl.swap23 connect fp_rename_stage.io.dec_uops[0].fp_ctrl.swap12, dec_uops[0].fp_ctrl.swap12 connect fp_rename_stage.io.dec_uops[0].fp_ctrl.ren3, dec_uops[0].fp_ctrl.ren3 connect fp_rename_stage.io.dec_uops[0].fp_ctrl.ren2, dec_uops[0].fp_ctrl.ren2 connect fp_rename_stage.io.dec_uops[0].fp_ctrl.ren1, dec_uops[0].fp_ctrl.ren1 connect fp_rename_stage.io.dec_uops[0].fp_ctrl.wen, dec_uops[0].fp_ctrl.wen connect fp_rename_stage.io.dec_uops[0].fp_ctrl.ldst, dec_uops[0].fp_ctrl.ldst connect fp_rename_stage.io.dec_uops[0].op2_sel, dec_uops[0].op2_sel connect fp_rename_stage.io.dec_uops[0].op1_sel, dec_uops[0].op1_sel connect fp_rename_stage.io.dec_uops[0].imm_packed, dec_uops[0].imm_packed connect fp_rename_stage.io.dec_uops[0].pimm, dec_uops[0].pimm connect fp_rename_stage.io.dec_uops[0].imm_sel, dec_uops[0].imm_sel connect fp_rename_stage.io.dec_uops[0].imm_rename, dec_uops[0].imm_rename connect fp_rename_stage.io.dec_uops[0].taken, dec_uops[0].taken connect fp_rename_stage.io.dec_uops[0].pc_lob, dec_uops[0].pc_lob connect fp_rename_stage.io.dec_uops[0].edge_inst, dec_uops[0].edge_inst connect fp_rename_stage.io.dec_uops[0].ftq_idx, dec_uops[0].ftq_idx connect fp_rename_stage.io.dec_uops[0].is_mov, dec_uops[0].is_mov connect fp_rename_stage.io.dec_uops[0].is_rocc, dec_uops[0].is_rocc connect fp_rename_stage.io.dec_uops[0].is_sys_pc2epc, dec_uops[0].is_sys_pc2epc connect fp_rename_stage.io.dec_uops[0].is_eret, dec_uops[0].is_eret connect fp_rename_stage.io.dec_uops[0].is_amo, dec_uops[0].is_amo connect fp_rename_stage.io.dec_uops[0].is_sfence, dec_uops[0].is_sfence connect fp_rename_stage.io.dec_uops[0].is_fencei, dec_uops[0].is_fencei connect fp_rename_stage.io.dec_uops[0].is_fence, dec_uops[0].is_fence connect fp_rename_stage.io.dec_uops[0].is_sfb, dec_uops[0].is_sfb connect fp_rename_stage.io.dec_uops[0].br_type, dec_uops[0].br_type connect fp_rename_stage.io.dec_uops[0].br_tag, dec_uops[0].br_tag connect fp_rename_stage.io.dec_uops[0].br_mask, dec_uops[0].br_mask connect fp_rename_stage.io.dec_uops[0].dis_col_sel, dec_uops[0].dis_col_sel connect fp_rename_stage.io.dec_uops[0].iw_p3_bypass_hint, dec_uops[0].iw_p3_bypass_hint connect fp_rename_stage.io.dec_uops[0].iw_p2_bypass_hint, dec_uops[0].iw_p2_bypass_hint connect fp_rename_stage.io.dec_uops[0].iw_p1_bypass_hint, dec_uops[0].iw_p1_bypass_hint connect fp_rename_stage.io.dec_uops[0].iw_p2_speculative_child, dec_uops[0].iw_p2_speculative_child connect fp_rename_stage.io.dec_uops[0].iw_p1_speculative_child, dec_uops[0].iw_p1_speculative_child connect fp_rename_stage.io.dec_uops[0].iw_issued_partial_dgen, dec_uops[0].iw_issued_partial_dgen connect fp_rename_stage.io.dec_uops[0].iw_issued_partial_agen, dec_uops[0].iw_issued_partial_agen connect fp_rename_stage.io.dec_uops[0].iw_issued, dec_uops[0].iw_issued connect fp_rename_stage.io.dec_uops[0].fu_code[0], dec_uops[0].fu_code[0] connect fp_rename_stage.io.dec_uops[0].fu_code[1], dec_uops[0].fu_code[1] connect fp_rename_stage.io.dec_uops[0].fu_code[2], dec_uops[0].fu_code[2] connect fp_rename_stage.io.dec_uops[0].fu_code[3], dec_uops[0].fu_code[3] connect fp_rename_stage.io.dec_uops[0].fu_code[4], dec_uops[0].fu_code[4] connect fp_rename_stage.io.dec_uops[0].fu_code[5], dec_uops[0].fu_code[5] connect fp_rename_stage.io.dec_uops[0].fu_code[6], dec_uops[0].fu_code[6] connect fp_rename_stage.io.dec_uops[0].fu_code[7], dec_uops[0].fu_code[7] connect fp_rename_stage.io.dec_uops[0].fu_code[8], dec_uops[0].fu_code[8] connect fp_rename_stage.io.dec_uops[0].fu_code[9], dec_uops[0].fu_code[9] connect fp_rename_stage.io.dec_uops[0].iq_type[0], dec_uops[0].iq_type[0] connect fp_rename_stage.io.dec_uops[0].iq_type[1], dec_uops[0].iq_type[1] connect fp_rename_stage.io.dec_uops[0].iq_type[2], dec_uops[0].iq_type[2] connect fp_rename_stage.io.dec_uops[0].iq_type[3], dec_uops[0].iq_type[3] connect fp_rename_stage.io.dec_uops[0].debug_pc, dec_uops[0].debug_pc connect fp_rename_stage.io.dec_uops[0].is_rvc, dec_uops[0].is_rvc connect fp_rename_stage.io.dec_uops[0].debug_inst, dec_uops[0].debug_inst connect fp_rename_stage.io.dec_uops[0].inst, dec_uops[0].inst connect fp_rename_stage.io.dec_uops[1].debug_tsrc, dec_uops[1].debug_tsrc connect fp_rename_stage.io.dec_uops[1].debug_fsrc, dec_uops[1].debug_fsrc connect fp_rename_stage.io.dec_uops[1].bp_xcpt_if, dec_uops[1].bp_xcpt_if connect fp_rename_stage.io.dec_uops[1].bp_debug_if, dec_uops[1].bp_debug_if connect fp_rename_stage.io.dec_uops[1].xcpt_ma_if, dec_uops[1].xcpt_ma_if connect fp_rename_stage.io.dec_uops[1].xcpt_ae_if, dec_uops[1].xcpt_ae_if connect fp_rename_stage.io.dec_uops[1].xcpt_pf_if, dec_uops[1].xcpt_pf_if connect fp_rename_stage.io.dec_uops[1].fp_typ, dec_uops[1].fp_typ connect fp_rename_stage.io.dec_uops[1].fp_rm, dec_uops[1].fp_rm connect fp_rename_stage.io.dec_uops[1].fp_val, dec_uops[1].fp_val connect fp_rename_stage.io.dec_uops[1].fcn_op, dec_uops[1].fcn_op connect fp_rename_stage.io.dec_uops[1].fcn_dw, dec_uops[1].fcn_dw connect fp_rename_stage.io.dec_uops[1].frs3_en, dec_uops[1].frs3_en connect fp_rename_stage.io.dec_uops[1].lrs2_rtype, dec_uops[1].lrs2_rtype connect fp_rename_stage.io.dec_uops[1].lrs1_rtype, dec_uops[1].lrs1_rtype connect fp_rename_stage.io.dec_uops[1].dst_rtype, dec_uops[1].dst_rtype connect fp_rename_stage.io.dec_uops[1].lrs3, dec_uops[1].lrs3 connect fp_rename_stage.io.dec_uops[1].lrs2, dec_uops[1].lrs2 connect fp_rename_stage.io.dec_uops[1].lrs1, dec_uops[1].lrs1 connect fp_rename_stage.io.dec_uops[1].ldst, dec_uops[1].ldst connect fp_rename_stage.io.dec_uops[1].ldst_is_rs1, dec_uops[1].ldst_is_rs1 connect fp_rename_stage.io.dec_uops[1].csr_cmd, dec_uops[1].csr_cmd connect fp_rename_stage.io.dec_uops[1].flush_on_commit, dec_uops[1].flush_on_commit connect fp_rename_stage.io.dec_uops[1].is_unique, dec_uops[1].is_unique connect fp_rename_stage.io.dec_uops[1].uses_stq, dec_uops[1].uses_stq connect fp_rename_stage.io.dec_uops[1].uses_ldq, dec_uops[1].uses_ldq connect fp_rename_stage.io.dec_uops[1].mem_signed, dec_uops[1].mem_signed connect fp_rename_stage.io.dec_uops[1].mem_size, dec_uops[1].mem_size connect fp_rename_stage.io.dec_uops[1].mem_cmd, dec_uops[1].mem_cmd connect fp_rename_stage.io.dec_uops[1].exc_cause, dec_uops[1].exc_cause connect fp_rename_stage.io.dec_uops[1].exception, dec_uops[1].exception connect fp_rename_stage.io.dec_uops[1].stale_pdst, dec_uops[1].stale_pdst connect fp_rename_stage.io.dec_uops[1].ppred_busy, dec_uops[1].ppred_busy connect fp_rename_stage.io.dec_uops[1].prs3_busy, dec_uops[1].prs3_busy connect fp_rename_stage.io.dec_uops[1].prs2_busy, dec_uops[1].prs2_busy connect fp_rename_stage.io.dec_uops[1].prs1_busy, dec_uops[1].prs1_busy connect fp_rename_stage.io.dec_uops[1].ppred, dec_uops[1].ppred connect fp_rename_stage.io.dec_uops[1].prs3, dec_uops[1].prs3 connect fp_rename_stage.io.dec_uops[1].prs2, dec_uops[1].prs2 connect fp_rename_stage.io.dec_uops[1].prs1, dec_uops[1].prs1 connect fp_rename_stage.io.dec_uops[1].pdst, dec_uops[1].pdst connect fp_rename_stage.io.dec_uops[1].rxq_idx, dec_uops[1].rxq_idx connect fp_rename_stage.io.dec_uops[1].stq_idx, dec_uops[1].stq_idx connect fp_rename_stage.io.dec_uops[1].ldq_idx, dec_uops[1].ldq_idx connect fp_rename_stage.io.dec_uops[1].rob_idx, dec_uops[1].rob_idx connect fp_rename_stage.io.dec_uops[1].fp_ctrl.vec, dec_uops[1].fp_ctrl.vec connect fp_rename_stage.io.dec_uops[1].fp_ctrl.wflags, dec_uops[1].fp_ctrl.wflags connect fp_rename_stage.io.dec_uops[1].fp_ctrl.sqrt, dec_uops[1].fp_ctrl.sqrt connect fp_rename_stage.io.dec_uops[1].fp_ctrl.div, dec_uops[1].fp_ctrl.div connect fp_rename_stage.io.dec_uops[1].fp_ctrl.fma, dec_uops[1].fp_ctrl.fma connect fp_rename_stage.io.dec_uops[1].fp_ctrl.fastpipe, dec_uops[1].fp_ctrl.fastpipe connect fp_rename_stage.io.dec_uops[1].fp_ctrl.toint, dec_uops[1].fp_ctrl.toint connect fp_rename_stage.io.dec_uops[1].fp_ctrl.fromint, dec_uops[1].fp_ctrl.fromint connect fp_rename_stage.io.dec_uops[1].fp_ctrl.typeTagOut, dec_uops[1].fp_ctrl.typeTagOut connect fp_rename_stage.io.dec_uops[1].fp_ctrl.typeTagIn, dec_uops[1].fp_ctrl.typeTagIn connect fp_rename_stage.io.dec_uops[1].fp_ctrl.swap23, dec_uops[1].fp_ctrl.swap23 connect fp_rename_stage.io.dec_uops[1].fp_ctrl.swap12, dec_uops[1].fp_ctrl.swap12 connect fp_rename_stage.io.dec_uops[1].fp_ctrl.ren3, dec_uops[1].fp_ctrl.ren3 connect fp_rename_stage.io.dec_uops[1].fp_ctrl.ren2, dec_uops[1].fp_ctrl.ren2 connect fp_rename_stage.io.dec_uops[1].fp_ctrl.ren1, dec_uops[1].fp_ctrl.ren1 connect fp_rename_stage.io.dec_uops[1].fp_ctrl.wen, dec_uops[1].fp_ctrl.wen connect fp_rename_stage.io.dec_uops[1].fp_ctrl.ldst, dec_uops[1].fp_ctrl.ldst connect fp_rename_stage.io.dec_uops[1].op2_sel, dec_uops[1].op2_sel connect fp_rename_stage.io.dec_uops[1].op1_sel, dec_uops[1].op1_sel connect fp_rename_stage.io.dec_uops[1].imm_packed, dec_uops[1].imm_packed connect fp_rename_stage.io.dec_uops[1].pimm, dec_uops[1].pimm connect fp_rename_stage.io.dec_uops[1].imm_sel, dec_uops[1].imm_sel connect fp_rename_stage.io.dec_uops[1].imm_rename, dec_uops[1].imm_rename connect fp_rename_stage.io.dec_uops[1].taken, dec_uops[1].taken connect fp_rename_stage.io.dec_uops[1].pc_lob, dec_uops[1].pc_lob connect fp_rename_stage.io.dec_uops[1].edge_inst, dec_uops[1].edge_inst connect fp_rename_stage.io.dec_uops[1].ftq_idx, dec_uops[1].ftq_idx connect fp_rename_stage.io.dec_uops[1].is_mov, dec_uops[1].is_mov connect fp_rename_stage.io.dec_uops[1].is_rocc, dec_uops[1].is_rocc connect fp_rename_stage.io.dec_uops[1].is_sys_pc2epc, dec_uops[1].is_sys_pc2epc connect fp_rename_stage.io.dec_uops[1].is_eret, dec_uops[1].is_eret connect fp_rename_stage.io.dec_uops[1].is_amo, dec_uops[1].is_amo connect fp_rename_stage.io.dec_uops[1].is_sfence, dec_uops[1].is_sfence connect fp_rename_stage.io.dec_uops[1].is_fencei, dec_uops[1].is_fencei connect fp_rename_stage.io.dec_uops[1].is_fence, dec_uops[1].is_fence connect fp_rename_stage.io.dec_uops[1].is_sfb, dec_uops[1].is_sfb connect fp_rename_stage.io.dec_uops[1].br_type, dec_uops[1].br_type connect fp_rename_stage.io.dec_uops[1].br_tag, dec_uops[1].br_tag connect fp_rename_stage.io.dec_uops[1].br_mask, dec_uops[1].br_mask connect fp_rename_stage.io.dec_uops[1].dis_col_sel, dec_uops[1].dis_col_sel connect fp_rename_stage.io.dec_uops[1].iw_p3_bypass_hint, dec_uops[1].iw_p3_bypass_hint connect fp_rename_stage.io.dec_uops[1].iw_p2_bypass_hint, dec_uops[1].iw_p2_bypass_hint connect fp_rename_stage.io.dec_uops[1].iw_p1_bypass_hint, dec_uops[1].iw_p1_bypass_hint connect fp_rename_stage.io.dec_uops[1].iw_p2_speculative_child, dec_uops[1].iw_p2_speculative_child connect fp_rename_stage.io.dec_uops[1].iw_p1_speculative_child, dec_uops[1].iw_p1_speculative_child connect fp_rename_stage.io.dec_uops[1].iw_issued_partial_dgen, dec_uops[1].iw_issued_partial_dgen connect fp_rename_stage.io.dec_uops[1].iw_issued_partial_agen, dec_uops[1].iw_issued_partial_agen connect fp_rename_stage.io.dec_uops[1].iw_issued, dec_uops[1].iw_issued connect fp_rename_stage.io.dec_uops[1].fu_code[0], dec_uops[1].fu_code[0] connect fp_rename_stage.io.dec_uops[1].fu_code[1], dec_uops[1].fu_code[1] connect fp_rename_stage.io.dec_uops[1].fu_code[2], dec_uops[1].fu_code[2] connect fp_rename_stage.io.dec_uops[1].fu_code[3], dec_uops[1].fu_code[3] connect fp_rename_stage.io.dec_uops[1].fu_code[4], dec_uops[1].fu_code[4] connect fp_rename_stage.io.dec_uops[1].fu_code[5], dec_uops[1].fu_code[5] connect fp_rename_stage.io.dec_uops[1].fu_code[6], dec_uops[1].fu_code[6] connect fp_rename_stage.io.dec_uops[1].fu_code[7], dec_uops[1].fu_code[7] connect fp_rename_stage.io.dec_uops[1].fu_code[8], dec_uops[1].fu_code[8] connect fp_rename_stage.io.dec_uops[1].fu_code[9], dec_uops[1].fu_code[9] connect fp_rename_stage.io.dec_uops[1].iq_type[0], dec_uops[1].iq_type[0] connect fp_rename_stage.io.dec_uops[1].iq_type[1], dec_uops[1].iq_type[1] connect fp_rename_stage.io.dec_uops[1].iq_type[2], dec_uops[1].iq_type[2] connect fp_rename_stage.io.dec_uops[1].iq_type[3], dec_uops[1].iq_type[3] connect fp_rename_stage.io.dec_uops[1].debug_pc, dec_uops[1].debug_pc connect fp_rename_stage.io.dec_uops[1].is_rvc, dec_uops[1].is_rvc connect fp_rename_stage.io.dec_uops[1].debug_inst, dec_uops[1].debug_inst connect fp_rename_stage.io.dec_uops[1].inst, dec_uops[1].inst connect fp_rename_stage.io.dis_fire[0], dis_fire[0] connect fp_rename_stage.io.dis_fire[1], dis_fire[1] connect fp_rename_stage.io.dis_ready, dis_ready connect fp_rename_stage.io.com_valids[0], rob.io.commit.valids[0] connect fp_rename_stage.io.com_valids[1], rob.io.commit.valids[1] connect fp_rename_stage.io.com_uops[0].debug_tsrc, rob.io.commit.uops[0].debug_tsrc connect fp_rename_stage.io.com_uops[0].debug_fsrc, rob.io.commit.uops[0].debug_fsrc connect fp_rename_stage.io.com_uops[0].bp_xcpt_if, rob.io.commit.uops[0].bp_xcpt_if connect fp_rename_stage.io.com_uops[0].bp_debug_if, rob.io.commit.uops[0].bp_debug_if connect fp_rename_stage.io.com_uops[0].xcpt_ma_if, rob.io.commit.uops[0].xcpt_ma_if connect fp_rename_stage.io.com_uops[0].xcpt_ae_if, rob.io.commit.uops[0].xcpt_ae_if connect fp_rename_stage.io.com_uops[0].xcpt_pf_if, rob.io.commit.uops[0].xcpt_pf_if connect fp_rename_stage.io.com_uops[0].fp_typ, rob.io.commit.uops[0].fp_typ connect fp_rename_stage.io.com_uops[0].fp_rm, rob.io.commit.uops[0].fp_rm connect fp_rename_stage.io.com_uops[0].fp_val, rob.io.commit.uops[0].fp_val connect fp_rename_stage.io.com_uops[0].fcn_op, rob.io.commit.uops[0].fcn_op connect fp_rename_stage.io.com_uops[0].fcn_dw, rob.io.commit.uops[0].fcn_dw connect fp_rename_stage.io.com_uops[0].frs3_en, rob.io.commit.uops[0].frs3_en connect fp_rename_stage.io.com_uops[0].lrs2_rtype, rob.io.commit.uops[0].lrs2_rtype connect fp_rename_stage.io.com_uops[0].lrs1_rtype, rob.io.commit.uops[0].lrs1_rtype connect fp_rename_stage.io.com_uops[0].dst_rtype, rob.io.commit.uops[0].dst_rtype connect fp_rename_stage.io.com_uops[0].lrs3, rob.io.commit.uops[0].lrs3 connect fp_rename_stage.io.com_uops[0].lrs2, rob.io.commit.uops[0].lrs2 connect fp_rename_stage.io.com_uops[0].lrs1, rob.io.commit.uops[0].lrs1 connect fp_rename_stage.io.com_uops[0].ldst, rob.io.commit.uops[0].ldst connect fp_rename_stage.io.com_uops[0].ldst_is_rs1, rob.io.commit.uops[0].ldst_is_rs1 connect fp_rename_stage.io.com_uops[0].csr_cmd, rob.io.commit.uops[0].csr_cmd connect fp_rename_stage.io.com_uops[0].flush_on_commit, rob.io.commit.uops[0].flush_on_commit connect fp_rename_stage.io.com_uops[0].is_unique, rob.io.commit.uops[0].is_unique connect fp_rename_stage.io.com_uops[0].uses_stq, rob.io.commit.uops[0].uses_stq connect fp_rename_stage.io.com_uops[0].uses_ldq, rob.io.commit.uops[0].uses_ldq connect fp_rename_stage.io.com_uops[0].mem_signed, rob.io.commit.uops[0].mem_signed connect fp_rename_stage.io.com_uops[0].mem_size, rob.io.commit.uops[0].mem_size connect fp_rename_stage.io.com_uops[0].mem_cmd, rob.io.commit.uops[0].mem_cmd connect fp_rename_stage.io.com_uops[0].exc_cause, rob.io.commit.uops[0].exc_cause connect fp_rename_stage.io.com_uops[0].exception, rob.io.commit.uops[0].exception connect fp_rename_stage.io.com_uops[0].stale_pdst, rob.io.commit.uops[0].stale_pdst connect fp_rename_stage.io.com_uops[0].ppred_busy, rob.io.commit.uops[0].ppred_busy connect fp_rename_stage.io.com_uops[0].prs3_busy, rob.io.commit.uops[0].prs3_busy connect fp_rename_stage.io.com_uops[0].prs2_busy, rob.io.commit.uops[0].prs2_busy connect fp_rename_stage.io.com_uops[0].prs1_busy, rob.io.commit.uops[0].prs1_busy connect fp_rename_stage.io.com_uops[0].ppred, rob.io.commit.uops[0].ppred connect fp_rename_stage.io.com_uops[0].prs3, rob.io.commit.uops[0].prs3 connect fp_rename_stage.io.com_uops[0].prs2, rob.io.commit.uops[0].prs2 connect fp_rename_stage.io.com_uops[0].prs1, rob.io.commit.uops[0].prs1 connect fp_rename_stage.io.com_uops[0].pdst, rob.io.commit.uops[0].pdst connect fp_rename_stage.io.com_uops[0].rxq_idx, rob.io.commit.uops[0].rxq_idx connect fp_rename_stage.io.com_uops[0].stq_idx, rob.io.commit.uops[0].stq_idx connect fp_rename_stage.io.com_uops[0].ldq_idx, rob.io.commit.uops[0].ldq_idx connect fp_rename_stage.io.com_uops[0].rob_idx, rob.io.commit.uops[0].rob_idx connect fp_rename_stage.io.com_uops[0].fp_ctrl.vec, rob.io.commit.uops[0].fp_ctrl.vec connect fp_rename_stage.io.com_uops[0].fp_ctrl.wflags, rob.io.commit.uops[0].fp_ctrl.wflags connect fp_rename_stage.io.com_uops[0].fp_ctrl.sqrt, rob.io.commit.uops[0].fp_ctrl.sqrt connect fp_rename_stage.io.com_uops[0].fp_ctrl.div, rob.io.commit.uops[0].fp_ctrl.div connect fp_rename_stage.io.com_uops[0].fp_ctrl.fma, rob.io.commit.uops[0].fp_ctrl.fma connect fp_rename_stage.io.com_uops[0].fp_ctrl.fastpipe, rob.io.commit.uops[0].fp_ctrl.fastpipe connect fp_rename_stage.io.com_uops[0].fp_ctrl.toint, rob.io.commit.uops[0].fp_ctrl.toint connect fp_rename_stage.io.com_uops[0].fp_ctrl.fromint, rob.io.commit.uops[0].fp_ctrl.fromint connect fp_rename_stage.io.com_uops[0].fp_ctrl.typeTagOut, rob.io.commit.uops[0].fp_ctrl.typeTagOut connect fp_rename_stage.io.com_uops[0].fp_ctrl.typeTagIn, rob.io.commit.uops[0].fp_ctrl.typeTagIn connect fp_rename_stage.io.com_uops[0].fp_ctrl.swap23, rob.io.commit.uops[0].fp_ctrl.swap23 connect fp_rename_stage.io.com_uops[0].fp_ctrl.swap12, rob.io.commit.uops[0].fp_ctrl.swap12 connect fp_rename_stage.io.com_uops[0].fp_ctrl.ren3, rob.io.commit.uops[0].fp_ctrl.ren3 connect fp_rename_stage.io.com_uops[0].fp_ctrl.ren2, rob.io.commit.uops[0].fp_ctrl.ren2 connect fp_rename_stage.io.com_uops[0].fp_ctrl.ren1, rob.io.commit.uops[0].fp_ctrl.ren1 connect fp_rename_stage.io.com_uops[0].fp_ctrl.wen, rob.io.commit.uops[0].fp_ctrl.wen connect fp_rename_stage.io.com_uops[0].fp_ctrl.ldst, rob.io.commit.uops[0].fp_ctrl.ldst connect fp_rename_stage.io.com_uops[0].op2_sel, rob.io.commit.uops[0].op2_sel connect fp_rename_stage.io.com_uops[0].op1_sel, rob.io.commit.uops[0].op1_sel connect fp_rename_stage.io.com_uops[0].imm_packed, rob.io.commit.uops[0].imm_packed connect fp_rename_stage.io.com_uops[0].pimm, rob.io.commit.uops[0].pimm connect fp_rename_stage.io.com_uops[0].imm_sel, rob.io.commit.uops[0].imm_sel connect fp_rename_stage.io.com_uops[0].imm_rename, rob.io.commit.uops[0].imm_rename connect fp_rename_stage.io.com_uops[0].taken, rob.io.commit.uops[0].taken connect fp_rename_stage.io.com_uops[0].pc_lob, rob.io.commit.uops[0].pc_lob connect fp_rename_stage.io.com_uops[0].edge_inst, rob.io.commit.uops[0].edge_inst connect fp_rename_stage.io.com_uops[0].ftq_idx, rob.io.commit.uops[0].ftq_idx connect fp_rename_stage.io.com_uops[0].is_mov, rob.io.commit.uops[0].is_mov connect fp_rename_stage.io.com_uops[0].is_rocc, rob.io.commit.uops[0].is_rocc connect fp_rename_stage.io.com_uops[0].is_sys_pc2epc, rob.io.commit.uops[0].is_sys_pc2epc connect fp_rename_stage.io.com_uops[0].is_eret, rob.io.commit.uops[0].is_eret connect fp_rename_stage.io.com_uops[0].is_amo, rob.io.commit.uops[0].is_amo connect fp_rename_stage.io.com_uops[0].is_sfence, rob.io.commit.uops[0].is_sfence connect fp_rename_stage.io.com_uops[0].is_fencei, rob.io.commit.uops[0].is_fencei connect fp_rename_stage.io.com_uops[0].is_fence, rob.io.commit.uops[0].is_fence connect fp_rename_stage.io.com_uops[0].is_sfb, rob.io.commit.uops[0].is_sfb connect fp_rename_stage.io.com_uops[0].br_type, rob.io.commit.uops[0].br_type connect fp_rename_stage.io.com_uops[0].br_tag, rob.io.commit.uops[0].br_tag connect fp_rename_stage.io.com_uops[0].br_mask, rob.io.commit.uops[0].br_mask connect fp_rename_stage.io.com_uops[0].dis_col_sel, rob.io.commit.uops[0].dis_col_sel connect fp_rename_stage.io.com_uops[0].iw_p3_bypass_hint, rob.io.commit.uops[0].iw_p3_bypass_hint connect fp_rename_stage.io.com_uops[0].iw_p2_bypass_hint, rob.io.commit.uops[0].iw_p2_bypass_hint connect fp_rename_stage.io.com_uops[0].iw_p1_bypass_hint, rob.io.commit.uops[0].iw_p1_bypass_hint connect fp_rename_stage.io.com_uops[0].iw_p2_speculative_child, rob.io.commit.uops[0].iw_p2_speculative_child connect fp_rename_stage.io.com_uops[0].iw_p1_speculative_child, rob.io.commit.uops[0].iw_p1_speculative_child connect fp_rename_stage.io.com_uops[0].iw_issued_partial_dgen, rob.io.commit.uops[0].iw_issued_partial_dgen connect fp_rename_stage.io.com_uops[0].iw_issued_partial_agen, rob.io.commit.uops[0].iw_issued_partial_agen connect fp_rename_stage.io.com_uops[0].iw_issued, rob.io.commit.uops[0].iw_issued connect fp_rename_stage.io.com_uops[0].fu_code[0], rob.io.commit.uops[0].fu_code[0] connect fp_rename_stage.io.com_uops[0].fu_code[1], rob.io.commit.uops[0].fu_code[1] connect fp_rename_stage.io.com_uops[0].fu_code[2], rob.io.commit.uops[0].fu_code[2] connect fp_rename_stage.io.com_uops[0].fu_code[3], rob.io.commit.uops[0].fu_code[3] connect fp_rename_stage.io.com_uops[0].fu_code[4], rob.io.commit.uops[0].fu_code[4] connect fp_rename_stage.io.com_uops[0].fu_code[5], rob.io.commit.uops[0].fu_code[5] connect fp_rename_stage.io.com_uops[0].fu_code[6], rob.io.commit.uops[0].fu_code[6] connect fp_rename_stage.io.com_uops[0].fu_code[7], rob.io.commit.uops[0].fu_code[7] connect fp_rename_stage.io.com_uops[0].fu_code[8], rob.io.commit.uops[0].fu_code[8] connect fp_rename_stage.io.com_uops[0].fu_code[9], rob.io.commit.uops[0].fu_code[9] connect fp_rename_stage.io.com_uops[0].iq_type[0], rob.io.commit.uops[0].iq_type[0] connect fp_rename_stage.io.com_uops[0].iq_type[1], rob.io.commit.uops[0].iq_type[1] connect fp_rename_stage.io.com_uops[0].iq_type[2], rob.io.commit.uops[0].iq_type[2] connect fp_rename_stage.io.com_uops[0].iq_type[3], rob.io.commit.uops[0].iq_type[3] connect fp_rename_stage.io.com_uops[0].debug_pc, rob.io.commit.uops[0].debug_pc connect fp_rename_stage.io.com_uops[0].is_rvc, rob.io.commit.uops[0].is_rvc connect fp_rename_stage.io.com_uops[0].debug_inst, rob.io.commit.uops[0].debug_inst connect fp_rename_stage.io.com_uops[0].inst, rob.io.commit.uops[0].inst connect fp_rename_stage.io.com_uops[1].debug_tsrc, rob.io.commit.uops[1].debug_tsrc connect fp_rename_stage.io.com_uops[1].debug_fsrc, rob.io.commit.uops[1].debug_fsrc connect fp_rename_stage.io.com_uops[1].bp_xcpt_if, rob.io.commit.uops[1].bp_xcpt_if connect fp_rename_stage.io.com_uops[1].bp_debug_if, rob.io.commit.uops[1].bp_debug_if connect fp_rename_stage.io.com_uops[1].xcpt_ma_if, rob.io.commit.uops[1].xcpt_ma_if connect fp_rename_stage.io.com_uops[1].xcpt_ae_if, rob.io.commit.uops[1].xcpt_ae_if connect fp_rename_stage.io.com_uops[1].xcpt_pf_if, rob.io.commit.uops[1].xcpt_pf_if connect fp_rename_stage.io.com_uops[1].fp_typ, rob.io.commit.uops[1].fp_typ connect fp_rename_stage.io.com_uops[1].fp_rm, rob.io.commit.uops[1].fp_rm connect fp_rename_stage.io.com_uops[1].fp_val, rob.io.commit.uops[1].fp_val connect fp_rename_stage.io.com_uops[1].fcn_op, rob.io.commit.uops[1].fcn_op connect fp_rename_stage.io.com_uops[1].fcn_dw, rob.io.commit.uops[1].fcn_dw connect fp_rename_stage.io.com_uops[1].frs3_en, rob.io.commit.uops[1].frs3_en connect fp_rename_stage.io.com_uops[1].lrs2_rtype, rob.io.commit.uops[1].lrs2_rtype connect fp_rename_stage.io.com_uops[1].lrs1_rtype, rob.io.commit.uops[1].lrs1_rtype connect fp_rename_stage.io.com_uops[1].dst_rtype, rob.io.commit.uops[1].dst_rtype connect fp_rename_stage.io.com_uops[1].lrs3, rob.io.commit.uops[1].lrs3 connect fp_rename_stage.io.com_uops[1].lrs2, rob.io.commit.uops[1].lrs2 connect fp_rename_stage.io.com_uops[1].lrs1, rob.io.commit.uops[1].lrs1 connect fp_rename_stage.io.com_uops[1].ldst, rob.io.commit.uops[1].ldst connect fp_rename_stage.io.com_uops[1].ldst_is_rs1, rob.io.commit.uops[1].ldst_is_rs1 connect fp_rename_stage.io.com_uops[1].csr_cmd, rob.io.commit.uops[1].csr_cmd connect fp_rename_stage.io.com_uops[1].flush_on_commit, rob.io.commit.uops[1].flush_on_commit connect fp_rename_stage.io.com_uops[1].is_unique, rob.io.commit.uops[1].is_unique connect fp_rename_stage.io.com_uops[1].uses_stq, rob.io.commit.uops[1].uses_stq connect fp_rename_stage.io.com_uops[1].uses_ldq, rob.io.commit.uops[1].uses_ldq connect fp_rename_stage.io.com_uops[1].mem_signed, rob.io.commit.uops[1].mem_signed connect fp_rename_stage.io.com_uops[1].mem_size, rob.io.commit.uops[1].mem_size connect fp_rename_stage.io.com_uops[1].mem_cmd, rob.io.commit.uops[1].mem_cmd connect fp_rename_stage.io.com_uops[1].exc_cause, rob.io.commit.uops[1].exc_cause connect fp_rename_stage.io.com_uops[1].exception, rob.io.commit.uops[1].exception connect fp_rename_stage.io.com_uops[1].stale_pdst, rob.io.commit.uops[1].stale_pdst connect fp_rename_stage.io.com_uops[1].ppred_busy, rob.io.commit.uops[1].ppred_busy connect fp_rename_stage.io.com_uops[1].prs3_busy, rob.io.commit.uops[1].prs3_busy connect fp_rename_stage.io.com_uops[1].prs2_busy, rob.io.commit.uops[1].prs2_busy connect fp_rename_stage.io.com_uops[1].prs1_busy, rob.io.commit.uops[1].prs1_busy connect fp_rename_stage.io.com_uops[1].ppred, rob.io.commit.uops[1].ppred connect fp_rename_stage.io.com_uops[1].prs3, rob.io.commit.uops[1].prs3 connect fp_rename_stage.io.com_uops[1].prs2, rob.io.commit.uops[1].prs2 connect fp_rename_stage.io.com_uops[1].prs1, rob.io.commit.uops[1].prs1 connect fp_rename_stage.io.com_uops[1].pdst, rob.io.commit.uops[1].pdst connect fp_rename_stage.io.com_uops[1].rxq_idx, rob.io.commit.uops[1].rxq_idx connect fp_rename_stage.io.com_uops[1].stq_idx, rob.io.commit.uops[1].stq_idx connect fp_rename_stage.io.com_uops[1].ldq_idx, rob.io.commit.uops[1].ldq_idx connect fp_rename_stage.io.com_uops[1].rob_idx, rob.io.commit.uops[1].rob_idx connect fp_rename_stage.io.com_uops[1].fp_ctrl.vec, rob.io.commit.uops[1].fp_ctrl.vec connect fp_rename_stage.io.com_uops[1].fp_ctrl.wflags, rob.io.commit.uops[1].fp_ctrl.wflags connect fp_rename_stage.io.com_uops[1].fp_ctrl.sqrt, rob.io.commit.uops[1].fp_ctrl.sqrt connect fp_rename_stage.io.com_uops[1].fp_ctrl.div, rob.io.commit.uops[1].fp_ctrl.div connect fp_rename_stage.io.com_uops[1].fp_ctrl.fma, rob.io.commit.uops[1].fp_ctrl.fma connect fp_rename_stage.io.com_uops[1].fp_ctrl.fastpipe, rob.io.commit.uops[1].fp_ctrl.fastpipe connect fp_rename_stage.io.com_uops[1].fp_ctrl.toint, rob.io.commit.uops[1].fp_ctrl.toint connect fp_rename_stage.io.com_uops[1].fp_ctrl.fromint, rob.io.commit.uops[1].fp_ctrl.fromint connect fp_rename_stage.io.com_uops[1].fp_ctrl.typeTagOut, rob.io.commit.uops[1].fp_ctrl.typeTagOut connect fp_rename_stage.io.com_uops[1].fp_ctrl.typeTagIn, rob.io.commit.uops[1].fp_ctrl.typeTagIn connect fp_rename_stage.io.com_uops[1].fp_ctrl.swap23, rob.io.commit.uops[1].fp_ctrl.swap23 connect fp_rename_stage.io.com_uops[1].fp_ctrl.swap12, rob.io.commit.uops[1].fp_ctrl.swap12 connect fp_rename_stage.io.com_uops[1].fp_ctrl.ren3, rob.io.commit.uops[1].fp_ctrl.ren3 connect fp_rename_stage.io.com_uops[1].fp_ctrl.ren2, rob.io.commit.uops[1].fp_ctrl.ren2 connect fp_rename_stage.io.com_uops[1].fp_ctrl.ren1, rob.io.commit.uops[1].fp_ctrl.ren1 connect fp_rename_stage.io.com_uops[1].fp_ctrl.wen, rob.io.commit.uops[1].fp_ctrl.wen connect fp_rename_stage.io.com_uops[1].fp_ctrl.ldst, rob.io.commit.uops[1].fp_ctrl.ldst connect fp_rename_stage.io.com_uops[1].op2_sel, rob.io.commit.uops[1].op2_sel connect fp_rename_stage.io.com_uops[1].op1_sel, rob.io.commit.uops[1].op1_sel connect fp_rename_stage.io.com_uops[1].imm_packed, rob.io.commit.uops[1].imm_packed connect fp_rename_stage.io.com_uops[1].pimm, rob.io.commit.uops[1].pimm connect fp_rename_stage.io.com_uops[1].imm_sel, rob.io.commit.uops[1].imm_sel connect fp_rename_stage.io.com_uops[1].imm_rename, rob.io.commit.uops[1].imm_rename connect fp_rename_stage.io.com_uops[1].taken, rob.io.commit.uops[1].taken connect fp_rename_stage.io.com_uops[1].pc_lob, rob.io.commit.uops[1].pc_lob connect fp_rename_stage.io.com_uops[1].edge_inst, rob.io.commit.uops[1].edge_inst connect fp_rename_stage.io.com_uops[1].ftq_idx, rob.io.commit.uops[1].ftq_idx connect fp_rename_stage.io.com_uops[1].is_mov, rob.io.commit.uops[1].is_mov connect fp_rename_stage.io.com_uops[1].is_rocc, rob.io.commit.uops[1].is_rocc connect fp_rename_stage.io.com_uops[1].is_sys_pc2epc, rob.io.commit.uops[1].is_sys_pc2epc connect fp_rename_stage.io.com_uops[1].is_eret, rob.io.commit.uops[1].is_eret connect fp_rename_stage.io.com_uops[1].is_amo, rob.io.commit.uops[1].is_amo connect fp_rename_stage.io.com_uops[1].is_sfence, rob.io.commit.uops[1].is_sfence connect fp_rename_stage.io.com_uops[1].is_fencei, rob.io.commit.uops[1].is_fencei connect fp_rename_stage.io.com_uops[1].is_fence, rob.io.commit.uops[1].is_fence connect fp_rename_stage.io.com_uops[1].is_sfb, rob.io.commit.uops[1].is_sfb connect fp_rename_stage.io.com_uops[1].br_type, rob.io.commit.uops[1].br_type connect fp_rename_stage.io.com_uops[1].br_tag, rob.io.commit.uops[1].br_tag connect fp_rename_stage.io.com_uops[1].br_mask, rob.io.commit.uops[1].br_mask connect fp_rename_stage.io.com_uops[1].dis_col_sel, rob.io.commit.uops[1].dis_col_sel connect fp_rename_stage.io.com_uops[1].iw_p3_bypass_hint, rob.io.commit.uops[1].iw_p3_bypass_hint connect fp_rename_stage.io.com_uops[1].iw_p2_bypass_hint, rob.io.commit.uops[1].iw_p2_bypass_hint connect fp_rename_stage.io.com_uops[1].iw_p1_bypass_hint, rob.io.commit.uops[1].iw_p1_bypass_hint connect fp_rename_stage.io.com_uops[1].iw_p2_speculative_child, rob.io.commit.uops[1].iw_p2_speculative_child connect fp_rename_stage.io.com_uops[1].iw_p1_speculative_child, rob.io.commit.uops[1].iw_p1_speculative_child connect fp_rename_stage.io.com_uops[1].iw_issued_partial_dgen, rob.io.commit.uops[1].iw_issued_partial_dgen connect fp_rename_stage.io.com_uops[1].iw_issued_partial_agen, rob.io.commit.uops[1].iw_issued_partial_agen connect fp_rename_stage.io.com_uops[1].iw_issued, rob.io.commit.uops[1].iw_issued connect fp_rename_stage.io.com_uops[1].fu_code[0], rob.io.commit.uops[1].fu_code[0] connect fp_rename_stage.io.com_uops[1].fu_code[1], rob.io.commit.uops[1].fu_code[1] connect fp_rename_stage.io.com_uops[1].fu_code[2], rob.io.commit.uops[1].fu_code[2] connect fp_rename_stage.io.com_uops[1].fu_code[3], rob.io.commit.uops[1].fu_code[3] connect fp_rename_stage.io.com_uops[1].fu_code[4], rob.io.commit.uops[1].fu_code[4] connect fp_rename_stage.io.com_uops[1].fu_code[5], rob.io.commit.uops[1].fu_code[5] connect fp_rename_stage.io.com_uops[1].fu_code[6], rob.io.commit.uops[1].fu_code[6] connect fp_rename_stage.io.com_uops[1].fu_code[7], rob.io.commit.uops[1].fu_code[7] connect fp_rename_stage.io.com_uops[1].fu_code[8], rob.io.commit.uops[1].fu_code[8] connect fp_rename_stage.io.com_uops[1].fu_code[9], rob.io.commit.uops[1].fu_code[9] connect fp_rename_stage.io.com_uops[1].iq_type[0], rob.io.commit.uops[1].iq_type[0] connect fp_rename_stage.io.com_uops[1].iq_type[1], rob.io.commit.uops[1].iq_type[1] connect fp_rename_stage.io.com_uops[1].iq_type[2], rob.io.commit.uops[1].iq_type[2] connect fp_rename_stage.io.com_uops[1].iq_type[3], rob.io.commit.uops[1].iq_type[3] connect fp_rename_stage.io.com_uops[1].debug_pc, rob.io.commit.uops[1].debug_pc connect fp_rename_stage.io.com_uops[1].is_rvc, rob.io.commit.uops[1].is_rvc connect fp_rename_stage.io.com_uops[1].debug_inst, rob.io.commit.uops[1].debug_inst connect fp_rename_stage.io.com_uops[1].inst, rob.io.commit.uops[1].inst connect fp_rename_stage.io.rollback, rob.io.rollback connect dis_uops, rename_stage.io.ren2_uops connect dis_valids, rename_stage.io.ren2_mask connect ren_stalls, rename_stage.io.ren_stalls node _dis_uops_0_prs1_T = eq(dis_uops[0].lrs1_rtype, UInt<2>(0h1)) node _dis_uops_0_prs1_T_1 = eq(dis_uops[0].lrs1_rtype, UInt<2>(0h0)) node _dis_uops_0_prs1_T_2 = mux(_dis_uops_0_prs1_T_1, rename_stage.io.ren2_uops[0].prs1, dis_uops[0].lrs1) node _dis_uops_0_prs1_T_3 = mux(_dis_uops_0_prs1_T, fp_rename_stage.io.ren2_uops[0].prs1, _dis_uops_0_prs1_T_2) connect dis_uops[0].prs1, _dis_uops_0_prs1_T_3 node _dis_uops_0_prs2_T = eq(dis_uops[0].lrs2_rtype, UInt<2>(0h1)) node _dis_uops_0_prs2_T_1 = mux(_dis_uops_0_prs2_T, fp_rename_stage.io.ren2_uops[0].prs2, rename_stage.io.ren2_uops[0].prs2) connect dis_uops[0].prs2, _dis_uops_0_prs2_T_1 connect dis_uops[0].prs3, fp_rename_stage.io.ren2_uops[0].prs3 connect dis_uops[0].ppred, pred_rename_stage.io.ren2_uops[0].ppred node _dis_uops_0_pdst_T = eq(dis_uops[0].dst_rtype, UInt<2>(0h1)) node _dis_uops_0_pdst_T_1 = eq(dis_uops[0].dst_rtype, UInt<2>(0h0)) node _dis_uops_0_pdst_T_2 = neq(dis_uops[0].br_type, UInt<4>(0h0)) node _dis_uops_0_pdst_T_3 = and(_dis_uops_0_pdst_T_2, dis_uops[0].is_sfb) node _dis_uops_0_pdst_T_4 = and(_dis_uops_0_pdst_T_3, UInt<1>(0h1)) inst dis_uops_0_pdst_prng of MaxPeriodFibonacciLFSR_8 connect dis_uops_0_pdst_prng.clock, clock connect dis_uops_0_pdst_prng.reset, reset connect dis_uops_0_pdst_prng.io.seed.valid, UInt<1>(0h0) invalidate dis_uops_0_pdst_prng.io.seed.bits[0] invalidate dis_uops_0_pdst_prng.io.seed.bits[1] invalidate dis_uops_0_pdst_prng.io.seed.bits[2] invalidate dis_uops_0_pdst_prng.io.seed.bits[3] invalidate dis_uops_0_pdst_prng.io.seed.bits[4] invalidate dis_uops_0_pdst_prng.io.seed.bits[5] invalidate dis_uops_0_pdst_prng.io.seed.bits[6] connect dis_uops_0_pdst_prng.io.increment, UInt<1>(0h1) node dis_uops_0_pdst_lo_hi = cat(dis_uops_0_pdst_prng.io.out[2], dis_uops_0_pdst_prng.io.out[1]) node dis_uops_0_pdst_lo = cat(dis_uops_0_pdst_lo_hi, dis_uops_0_pdst_prng.io.out[0]) node dis_uops_0_pdst_hi_lo = cat(dis_uops_0_pdst_prng.io.out[4], dis_uops_0_pdst_prng.io.out[3]) node dis_uops_0_pdst_hi_hi = cat(dis_uops_0_pdst_prng.io.out[6], dis_uops_0_pdst_prng.io.out[5]) node dis_uops_0_pdst_hi = cat(dis_uops_0_pdst_hi_hi, dis_uops_0_pdst_hi_lo) node _dis_uops_0_pdst_T_5 = cat(dis_uops_0_pdst_hi, dis_uops_0_pdst_lo) node _dis_uops_0_pdst_T_6 = mux(_dis_uops_0_pdst_T_4, pred_rename_stage.io.ren2_uops[0].pdst, _dis_uops_0_pdst_T_5) node _dis_uops_0_pdst_T_7 = mux(_dis_uops_0_pdst_T_1, rename_stage.io.ren2_uops[0].pdst, _dis_uops_0_pdst_T_6) node _dis_uops_0_pdst_T_8 = mux(_dis_uops_0_pdst_T, fp_rename_stage.io.ren2_uops[0].pdst, _dis_uops_0_pdst_T_7) connect dis_uops[0].pdst, _dis_uops_0_pdst_T_8 connect dis_uops[0].imm_sel, imm_rename_stage.io.ren2_uops[0].imm_sel connect dis_uops[0].pimm, imm_rename_stage.io.ren2_uops[0].pimm node _dis_uops_0_stale_pdst_T = eq(dis_uops[0].dst_rtype, UInt<2>(0h1)) node _dis_uops_0_stale_pdst_T_1 = mux(_dis_uops_0_stale_pdst_T, fp_rename_stage.io.ren2_uops[0].stale_pdst, rename_stage.io.ren2_uops[0].stale_pdst) connect dis_uops[0].stale_pdst, _dis_uops_0_stale_pdst_T_1 node _dis_uops_0_prs1_busy_T = eq(dis_uops[0].lrs1_rtype, UInt<2>(0h0)) node _dis_uops_0_prs1_busy_T_1 = and(rename_stage.io.ren2_uops[0].prs1_busy, _dis_uops_0_prs1_busy_T) node _dis_uops_0_prs1_busy_T_2 = eq(dis_uops[0].lrs1_rtype, UInt<2>(0h1)) node _dis_uops_0_prs1_busy_T_3 = and(fp_rename_stage.io.ren2_uops[0].prs1_busy, _dis_uops_0_prs1_busy_T_2) node _dis_uops_0_prs1_busy_T_4 = or(_dis_uops_0_prs1_busy_T_1, _dis_uops_0_prs1_busy_T_3) connect dis_uops[0].prs1_busy, _dis_uops_0_prs1_busy_T_4 node _dis_uops_0_prs2_busy_T = eq(dis_uops[0].lrs2_rtype, UInt<2>(0h0)) node _dis_uops_0_prs2_busy_T_1 = and(rename_stage.io.ren2_uops[0].prs2_busy, _dis_uops_0_prs2_busy_T) node _dis_uops_0_prs2_busy_T_2 = eq(dis_uops[0].lrs2_rtype, UInt<2>(0h1)) node _dis_uops_0_prs2_busy_T_3 = and(fp_rename_stage.io.ren2_uops[0].prs2_busy, _dis_uops_0_prs2_busy_T_2) node _dis_uops_0_prs2_busy_T_4 = or(_dis_uops_0_prs2_busy_T_1, _dis_uops_0_prs2_busy_T_3) connect dis_uops[0].prs2_busy, _dis_uops_0_prs2_busy_T_4 node _dis_uops_0_prs3_busy_T = and(fp_rename_stage.io.ren2_uops[0].prs3_busy, dis_uops[0].frs3_en) connect dis_uops[0].prs3_busy, _dis_uops_0_prs3_busy_T node _dis_uops_0_ppred_busy_T = eq(dis_uops[0].br_type, UInt<4>(0h0)) node _dis_uops_0_ppred_busy_T_1 = and(_dis_uops_0_ppred_busy_T, dis_uops[0].is_sfb) node _dis_uops_0_ppred_busy_T_2 = and(_dis_uops_0_ppred_busy_T_1, UInt<1>(0h1)) node _dis_uops_0_ppred_busy_T_3 = and(pred_rename_stage.io.ren2_uops[0].ppred_busy, _dis_uops_0_ppred_busy_T_2) connect dis_uops[0].ppred_busy, _dis_uops_0_ppred_busy_T_3 node _ren_stalls_0_T = or(rename_stage.io.ren_stalls[0], fp_rename_stage.io.ren_stalls[0]) node _ren_stalls_0_T_1 = or(_ren_stalls_0_T, pred_rename_stage.io.ren_stalls[0]) node _ren_stalls_0_T_2 = or(_ren_stalls_0_T_1, imm_rename_stage.io.ren_stalls[0]) connect ren_stalls[0], _ren_stalls_0_T_2 node _dis_uops_1_prs1_T = eq(dis_uops[1].lrs1_rtype, UInt<2>(0h1)) node _dis_uops_1_prs1_T_1 = eq(dis_uops[1].lrs1_rtype, UInt<2>(0h0)) node _dis_uops_1_prs1_T_2 = mux(_dis_uops_1_prs1_T_1, rename_stage.io.ren2_uops[1].prs1, dis_uops[1].lrs1) node _dis_uops_1_prs1_T_3 = mux(_dis_uops_1_prs1_T, fp_rename_stage.io.ren2_uops[1].prs1, _dis_uops_1_prs1_T_2) connect dis_uops[1].prs1, _dis_uops_1_prs1_T_3 node _dis_uops_1_prs2_T = eq(dis_uops[1].lrs2_rtype, UInt<2>(0h1)) node _dis_uops_1_prs2_T_1 = mux(_dis_uops_1_prs2_T, fp_rename_stage.io.ren2_uops[1].prs2, rename_stage.io.ren2_uops[1].prs2) connect dis_uops[1].prs2, _dis_uops_1_prs2_T_1 connect dis_uops[1].prs3, fp_rename_stage.io.ren2_uops[1].prs3 connect dis_uops[1].ppred, pred_rename_stage.io.ren2_uops[1].ppred node _dis_uops_1_pdst_T = eq(dis_uops[1].dst_rtype, UInt<2>(0h1)) node _dis_uops_1_pdst_T_1 = eq(dis_uops[1].dst_rtype, UInt<2>(0h0)) node _dis_uops_1_pdst_T_2 = neq(dis_uops[1].br_type, UInt<4>(0h0)) node _dis_uops_1_pdst_T_3 = and(_dis_uops_1_pdst_T_2, dis_uops[1].is_sfb) node _dis_uops_1_pdst_T_4 = and(_dis_uops_1_pdst_T_3, UInt<1>(0h1)) inst dis_uops_1_pdst_prng of MaxPeriodFibonacciLFSR_9 connect dis_uops_1_pdst_prng.clock, clock connect dis_uops_1_pdst_prng.reset, reset connect dis_uops_1_pdst_prng.io.seed.valid, UInt<1>(0h0) invalidate dis_uops_1_pdst_prng.io.seed.bits[0] invalidate dis_uops_1_pdst_prng.io.seed.bits[1] invalidate dis_uops_1_pdst_prng.io.seed.bits[2] invalidate dis_uops_1_pdst_prng.io.seed.bits[3] invalidate dis_uops_1_pdst_prng.io.seed.bits[4] invalidate dis_uops_1_pdst_prng.io.seed.bits[5] invalidate dis_uops_1_pdst_prng.io.seed.bits[6] connect dis_uops_1_pdst_prng.io.increment, UInt<1>(0h1) node dis_uops_1_pdst_lo_hi = cat(dis_uops_1_pdst_prng.io.out[2], dis_uops_1_pdst_prng.io.out[1]) node dis_uops_1_pdst_lo = cat(dis_uops_1_pdst_lo_hi, dis_uops_1_pdst_prng.io.out[0]) node dis_uops_1_pdst_hi_lo = cat(dis_uops_1_pdst_prng.io.out[4], dis_uops_1_pdst_prng.io.out[3]) node dis_uops_1_pdst_hi_hi = cat(dis_uops_1_pdst_prng.io.out[6], dis_uops_1_pdst_prng.io.out[5]) node dis_uops_1_pdst_hi = cat(dis_uops_1_pdst_hi_hi, dis_uops_1_pdst_hi_lo) node _dis_uops_1_pdst_T_5 = cat(dis_uops_1_pdst_hi, dis_uops_1_pdst_lo) node _dis_uops_1_pdst_T_6 = mux(_dis_uops_1_pdst_T_4, pred_rename_stage.io.ren2_uops[1].pdst, _dis_uops_1_pdst_T_5) node _dis_uops_1_pdst_T_7 = mux(_dis_uops_1_pdst_T_1, rename_stage.io.ren2_uops[1].pdst, _dis_uops_1_pdst_T_6) node _dis_uops_1_pdst_T_8 = mux(_dis_uops_1_pdst_T, fp_rename_stage.io.ren2_uops[1].pdst, _dis_uops_1_pdst_T_7) connect dis_uops[1].pdst, _dis_uops_1_pdst_T_8 connect dis_uops[1].imm_sel, imm_rename_stage.io.ren2_uops[1].imm_sel connect dis_uops[1].pimm, imm_rename_stage.io.ren2_uops[1].pimm node _dis_uops_1_stale_pdst_T = eq(dis_uops[1].dst_rtype, UInt<2>(0h1)) node _dis_uops_1_stale_pdst_T_1 = mux(_dis_uops_1_stale_pdst_T, fp_rename_stage.io.ren2_uops[1].stale_pdst, rename_stage.io.ren2_uops[1].stale_pdst) connect dis_uops[1].stale_pdst, _dis_uops_1_stale_pdst_T_1 node _dis_uops_1_prs1_busy_T = eq(dis_uops[1].lrs1_rtype, UInt<2>(0h0)) node _dis_uops_1_prs1_busy_T_1 = and(rename_stage.io.ren2_uops[1].prs1_busy, _dis_uops_1_prs1_busy_T) node _dis_uops_1_prs1_busy_T_2 = eq(dis_uops[1].lrs1_rtype, UInt<2>(0h1)) node _dis_uops_1_prs1_busy_T_3 = and(fp_rename_stage.io.ren2_uops[1].prs1_busy, _dis_uops_1_prs1_busy_T_2) node _dis_uops_1_prs1_busy_T_4 = or(_dis_uops_1_prs1_busy_T_1, _dis_uops_1_prs1_busy_T_3) connect dis_uops[1].prs1_busy, _dis_uops_1_prs1_busy_T_4 node _dis_uops_1_prs2_busy_T = eq(dis_uops[1].lrs2_rtype, UInt<2>(0h0)) node _dis_uops_1_prs2_busy_T_1 = and(rename_stage.io.ren2_uops[1].prs2_busy, _dis_uops_1_prs2_busy_T) node _dis_uops_1_prs2_busy_T_2 = eq(dis_uops[1].lrs2_rtype, UInt<2>(0h1)) node _dis_uops_1_prs2_busy_T_3 = and(fp_rename_stage.io.ren2_uops[1].prs2_busy, _dis_uops_1_prs2_busy_T_2) node _dis_uops_1_prs2_busy_T_4 = or(_dis_uops_1_prs2_busy_T_1, _dis_uops_1_prs2_busy_T_3) connect dis_uops[1].prs2_busy, _dis_uops_1_prs2_busy_T_4 node _dis_uops_1_prs3_busy_T = and(fp_rename_stage.io.ren2_uops[1].prs3_busy, dis_uops[1].frs3_en) connect dis_uops[1].prs3_busy, _dis_uops_1_prs3_busy_T node _dis_uops_1_ppred_busy_T = eq(dis_uops[1].br_type, UInt<4>(0h0)) node _dis_uops_1_ppred_busy_T_1 = and(_dis_uops_1_ppred_busy_T, dis_uops[1].is_sfb) node _dis_uops_1_ppred_busy_T_2 = and(_dis_uops_1_ppred_busy_T_1, UInt<1>(0h1)) node _dis_uops_1_ppred_busy_T_3 = and(pred_rename_stage.io.ren2_uops[1].ppred_busy, _dis_uops_1_ppred_busy_T_2) connect dis_uops[1].ppred_busy, _dis_uops_1_ppred_busy_T_3 node _ren_stalls_1_T = or(rename_stage.io.ren_stalls[1], fp_rename_stage.io.ren_stalls[1]) node _ren_stalls_1_T_1 = or(_ren_stalls_1_T, pred_rename_stage.io.ren_stalls[1]) node _ren_stalls_1_T_2 = or(_ren_stalls_1_T_1, imm_rename_stage.io.ren_stalls[1]) connect ren_stalls[1], _ren_stalls_1_T_2 node dis_prior_slot_valid_1 = or(UInt<1>(0h0), dis_valids[0]) node dis_prior_slot_valid_2 = or(dis_prior_slot_valid_1, dis_valids[1]) node _dis_prior_slot_unique_T = and(dis_valids[0], dis_uops[0].is_unique) node dis_prior_slot_unique_1 = or(UInt<1>(0h0), _dis_prior_slot_unique_T) node _dis_prior_slot_unique_T_1 = and(dis_valids[1], dis_uops[1].is_unique) node dis_prior_slot_unique_2 = or(dis_prior_slot_unique_1, _dis_prior_slot_unique_T_1) node _wait_for_empty_pipeline_T = bits(custom_csrs.csrs[0].value, 0, 0) node _wait_for_empty_pipeline_T_1 = bits(custom_csrs.csrs[2].value, 3, 3) node _wait_for_empty_pipeline_T_2 = eq(_wait_for_empty_pipeline_T_1, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_3 = and(_wait_for_empty_pipeline_T, _wait_for_empty_pipeline_T_2) node _wait_for_empty_pipeline_T_4 = eq(_wait_for_empty_pipeline_T_3, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_5 = or(dis_uops[0].is_unique, _wait_for_empty_pipeline_T_4) node _wait_for_empty_pipeline_T_6 = eq(rob.io.empty, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_7 = eq(io.lsu.fencei_rdy, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_8 = or(_wait_for_empty_pipeline_T_6, _wait_for_empty_pipeline_T_7) node _wait_for_empty_pipeline_T_9 = or(_wait_for_empty_pipeline_T_8, UInt<1>(0h0)) node wait_for_empty_pipeline_0 = and(_wait_for_empty_pipeline_T_5, _wait_for_empty_pipeline_T_9) node _wait_for_empty_pipeline_T_10 = bits(custom_csrs.csrs[0].value, 0, 0) node _wait_for_empty_pipeline_T_11 = bits(custom_csrs.csrs[2].value, 3, 3) node _wait_for_empty_pipeline_T_12 = eq(_wait_for_empty_pipeline_T_11, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_13 = and(_wait_for_empty_pipeline_T_10, _wait_for_empty_pipeline_T_12) node _wait_for_empty_pipeline_T_14 = eq(_wait_for_empty_pipeline_T_13, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_15 = or(dis_uops[1].is_unique, _wait_for_empty_pipeline_T_14) node _wait_for_empty_pipeline_T_16 = eq(rob.io.empty, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_17 = eq(io.lsu.fencei_rdy, UInt<1>(0h0)) node _wait_for_empty_pipeline_T_18 = or(_wait_for_empty_pipeline_T_16, _wait_for_empty_pipeline_T_17) node _wait_for_empty_pipeline_T_19 = or(_wait_for_empty_pipeline_T_18, dis_prior_slot_valid_1) node wait_for_empty_pipeline_1 = and(_wait_for_empty_pipeline_T_15, _wait_for_empty_pipeline_T_19) node _wait_for_rocc_T = or(dis_uops[0].is_fence, dis_uops[0].is_fencei) node _wait_for_rocc_T_1 = or(io.rocc.busy, UInt<1>(0h0)) node wait_for_rocc_0 = and(_wait_for_rocc_T, _wait_for_rocc_T_1) node _wait_for_rocc_T_2 = or(dis_uops[1].is_fence, dis_uops[1].is_fencei) node _wait_for_rocc_T_3 = or(io.rocc.busy, UInt<1>(0h0)) node wait_for_rocc_1 = and(_wait_for_rocc_T_2, _wait_for_rocc_T_3) node _block_rocc_T = and(dis_valids[0], dis_uops[0].is_rocc) node _block_rocc_T_1 = and(dis_valids[1], dis_uops[1].is_rocc) node block_rocc_1 = or(UInt<1>(0h0), _block_rocc_T) node block_rocc_2 = or(block_rocc_1, _block_rocc_T_1) node _block_brtag_T = eq(dis_uops[0].br_type, UInt<4>(0h1)) node _block_brtag_T_1 = eq(dis_uops[0].br_type, UInt<4>(0h2)) node _block_brtag_T_2 = eq(dis_uops[0].br_type, UInt<4>(0h3)) node _block_brtag_T_3 = eq(dis_uops[0].br_type, UInt<4>(0h4)) node _block_brtag_T_4 = eq(dis_uops[0].br_type, UInt<4>(0h5)) node _block_brtag_T_5 = eq(dis_uops[0].br_type, UInt<4>(0h6)) node _block_brtag_T_6 = or(_block_brtag_T, _block_brtag_T_1) node _block_brtag_T_7 = or(_block_brtag_T_6, _block_brtag_T_2) node _block_brtag_T_8 = or(_block_brtag_T_7, _block_brtag_T_3) node _block_brtag_T_9 = or(_block_brtag_T_8, _block_brtag_T_4) node _block_brtag_T_10 = or(_block_brtag_T_9, _block_brtag_T_5) node _block_brtag_T_11 = eq(dis_uops[0].is_sfb, UInt<1>(0h0)) node _block_brtag_T_12 = and(_block_brtag_T_10, _block_brtag_T_11) node _block_brtag_T_13 = eq(dis_uops[0].br_type, UInt<4>(0h8)) node _block_brtag_T_14 = or(_block_brtag_T_12, _block_brtag_T_13) node _block_brtag_T_15 = and(dis_valids[0], _block_brtag_T_14) node _block_brtag_T_16 = eq(dis_uops[1].br_type, UInt<4>(0h1)) node _block_brtag_T_17 = eq(dis_uops[1].br_type, UInt<4>(0h2)) node _block_brtag_T_18 = eq(dis_uops[1].br_type, UInt<4>(0h3)) node _block_brtag_T_19 = eq(dis_uops[1].br_type, UInt<4>(0h4)) node _block_brtag_T_20 = eq(dis_uops[1].br_type, UInt<4>(0h5)) node _block_brtag_T_21 = eq(dis_uops[1].br_type, UInt<4>(0h6)) node _block_brtag_T_22 = or(_block_brtag_T_16, _block_brtag_T_17) node _block_brtag_T_23 = or(_block_brtag_T_22, _block_brtag_T_18) node _block_brtag_T_24 = or(_block_brtag_T_23, _block_brtag_T_19) node _block_brtag_T_25 = or(_block_brtag_T_24, _block_brtag_T_20) node _block_brtag_T_26 = or(_block_brtag_T_25, _block_brtag_T_21) node _block_brtag_T_27 = eq(dis_uops[1].is_sfb, UInt<1>(0h0)) node _block_brtag_T_28 = and(_block_brtag_T_26, _block_brtag_T_27) node _block_brtag_T_29 = eq(dis_uops[1].br_type, UInt<4>(0h8)) node _block_brtag_T_30 = or(_block_brtag_T_28, _block_brtag_T_29) node _block_brtag_T_31 = and(dis_valids[1], _block_brtag_T_30) node block_brtag_1 = or(UInt<1>(0h0), _block_brtag_T_15) node block_brtag_2 = or(block_brtag_1, _block_brtag_T_31) node _brtag_stall_T = eq(dis_uops[0].br_type, UInt<4>(0h1)) node _brtag_stall_T_1 = eq(dis_uops[0].br_type, UInt<4>(0h2)) node _brtag_stall_T_2 = eq(dis_uops[0].br_type, UInt<4>(0h3)) node _brtag_stall_T_3 = eq(dis_uops[0].br_type, UInt<4>(0h4)) node _brtag_stall_T_4 = eq(dis_uops[0].br_type, UInt<4>(0h5)) node _brtag_stall_T_5 = eq(dis_uops[0].br_type, UInt<4>(0h6)) node _brtag_stall_T_6 = or(_brtag_stall_T, _brtag_stall_T_1) node _brtag_stall_T_7 = or(_brtag_stall_T_6, _brtag_stall_T_2) node _brtag_stall_T_8 = or(_brtag_stall_T_7, _brtag_stall_T_3) node _brtag_stall_T_9 = or(_brtag_stall_T_8, _brtag_stall_T_4) node _brtag_stall_T_10 = or(_brtag_stall_T_9, _brtag_stall_T_5) node _brtag_stall_T_11 = eq(dis_uops[0].is_sfb, UInt<1>(0h0)) node _brtag_stall_T_12 = and(_brtag_stall_T_10, _brtag_stall_T_11) node _brtag_stall_T_13 = eq(dis_uops[0].br_type, UInt<4>(0h8)) node _brtag_stall_T_14 = or(_brtag_stall_T_12, _brtag_stall_T_13) node _brtag_stall_T_15 = eq(dis_uops[1].br_type, UInt<4>(0h1)) node _brtag_stall_T_16 = eq(dis_uops[1].br_type, UInt<4>(0h2)) node _brtag_stall_T_17 = eq(dis_uops[1].br_type, UInt<4>(0h3)) node _brtag_stall_T_18 = eq(dis_uops[1].br_type, UInt<4>(0h4)) node _brtag_stall_T_19 = eq(dis_uops[1].br_type, UInt<4>(0h5)) node _brtag_stall_T_20 = eq(dis_uops[1].br_type, UInt<4>(0h6)) node _brtag_stall_T_21 = or(_brtag_stall_T_15, _brtag_stall_T_16) node _brtag_stall_T_22 = or(_brtag_stall_T_21, _brtag_stall_T_17) node _brtag_stall_T_23 = or(_brtag_stall_T_22, _brtag_stall_T_18) node _brtag_stall_T_24 = or(_brtag_stall_T_23, _brtag_stall_T_19) node _brtag_stall_T_25 = or(_brtag_stall_T_24, _brtag_stall_T_20) node _brtag_stall_T_26 = eq(dis_uops[1].is_sfb, UInt<1>(0h0)) node _brtag_stall_T_27 = and(_brtag_stall_T_25, _brtag_stall_T_26) node _brtag_stall_T_28 = eq(dis_uops[1].br_type, UInt<4>(0h8)) node _brtag_stall_T_29 = or(_brtag_stall_T_27, _brtag_stall_T_28) node _dis_hazards_T = eq(rob.io.ready, UInt<1>(0h0)) node _dis_hazards_T_1 = or(_dis_hazards_T, UInt<1>(0h0)) node _dis_hazards_T_2 = or(_dis_hazards_T_1, ren_stalls[0]) node _dis_hazards_T_3 = and(io.lsu.ldq_full[0], dis_uops[0].uses_ldq) node _dis_hazards_T_4 = or(_dis_hazards_T_2, _dis_hazards_T_3) node _dis_hazards_T_5 = and(io.lsu.stq_full[0], dis_uops[0].uses_stq) node _dis_hazards_T_6 = or(_dis_hazards_T_4, _dis_hazards_T_5) node _dis_hazards_T_7 = eq(dispatcher.io.ren_uops[0].ready, UInt<1>(0h0)) node _dis_hazards_T_8 = or(_dis_hazards_T_6, _dis_hazards_T_7) node _dis_hazards_T_9 = or(_dis_hazards_T_8, wait_for_empty_pipeline_0) node _dis_hazards_T_10 = or(_dis_hazards_T_9, wait_for_rocc_0) node _dis_hazards_T_11 = or(_dis_hazards_T_10, UInt<1>(0h0)) node _dis_hazards_T_12 = or(_dis_hazards_T_11, UInt<1>(0h0)) node _dis_hazards_T_13 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _dis_hazards_T_14 = or(_dis_hazards_T_12, _dis_hazards_T_13) node _dis_hazards_T_15 = or(_dis_hazards_T_14, brupdate.b2.mispredict) node _dis_hazards_T_16 = or(_dis_hazards_T_15, io.ifu.redirect_flush) node dis_hazards_0 = and(dis_valids[0], _dis_hazards_T_16) node _dis_hazards_T_17 = eq(rob.io.ready, UInt<1>(0h0)) node _dis_hazards_T_18 = or(_dis_hazards_T_17, UInt<1>(0h0)) node _dis_hazards_T_19 = or(_dis_hazards_T_18, ren_stalls[1]) node _dis_hazards_T_20 = and(io.lsu.ldq_full[1], dis_uops[1].uses_ldq) node _dis_hazards_T_21 = or(_dis_hazards_T_19, _dis_hazards_T_20) node _dis_hazards_T_22 = and(io.lsu.stq_full[1], dis_uops[1].uses_stq) node _dis_hazards_T_23 = or(_dis_hazards_T_21, _dis_hazards_T_22) node _dis_hazards_T_24 = eq(dispatcher.io.ren_uops[1].ready, UInt<1>(0h0)) node _dis_hazards_T_25 = or(_dis_hazards_T_23, _dis_hazards_T_24) node _dis_hazards_T_26 = or(_dis_hazards_T_25, wait_for_empty_pipeline_1) node _dis_hazards_T_27 = or(_dis_hazards_T_26, wait_for_rocc_1) node _dis_hazards_T_28 = or(_dis_hazards_T_27, dis_prior_slot_unique_1) node _dis_hazards_T_29 = or(_dis_hazards_T_28, UInt<1>(0h0)) node _dis_hazards_T_30 = neq(brupdate.b1.mispredict_mask, UInt<1>(0h0)) node _dis_hazards_T_31 = or(_dis_hazards_T_29, _dis_hazards_T_30) node _dis_hazards_T_32 = or(_dis_hazards_T_31, brupdate.b2.mispredict) node _dis_hazards_T_33 = or(_dis_hazards_T_32, io.ifu.redirect_flush) node dis_hazards_1 = and(dis_valids[1], _dis_hazards_T_33) node _io_lsu_fence_dmem_T = and(dis_valids[0], wait_for_empty_pipeline_0) node _io_lsu_fence_dmem_T_1 = and(dis_valids[1], wait_for_empty_pipeline_1) node _io_lsu_fence_dmem_T_2 = or(_io_lsu_fence_dmem_T, _io_lsu_fence_dmem_T_1) connect io.lsu.fence_dmem, _io_lsu_fence_dmem_T_2 node dis_stalls_0 = or(UInt<1>(0h0), dis_hazards_0) node dis_stalls_1 = or(dis_stalls_0, dis_hazards_1) node _T_111 = eq(dis_stalls_0, UInt<1>(0h0)) node _T_112 = and(dis_valids[0], _T_111) node _T_113 = eq(dis_stalls_1, UInt<1>(0h0)) node _T_114 = and(dis_valids[1], _T_113) connect dis_fire[0], _T_112 connect dis_fire[1], _T_114 node _dis_ready_T = eq(dis_stalls_1, UInt<1>(0h0)) connect dis_ready, _dis_ready_T connect dis_uops[0].ldq_idx, io.lsu.dis_ldq_idx[0] connect dis_uops[0].stq_idx, io.lsu.dis_stq_idx[0] connect dis_uops[1].ldq_idx, io.lsu.dis_ldq_idx[1] connect dis_uops[1].stq_idx, io.lsu.dis_stq_idx[1] connect rob.io.enq_valids[0], dis_fire[0] connect rob.io.enq_valids[1], dis_fire[1] connect rob.io.enq_uops[0].debug_tsrc, dis_uops[0].debug_tsrc connect rob.io.enq_uops[0].debug_fsrc, dis_uops[0].debug_fsrc connect rob.io.enq_uops[0].bp_xcpt_if, dis_uops[0].bp_xcpt_if connect rob.io.enq_uops[0].bp_debug_if, dis_uops[0].bp_debug_if connect rob.io.enq_uops[0].xcpt_ma_if, dis_uops[0].xcpt_ma_if connect rob.io.enq_uops[0].xcpt_ae_if, dis_uops[0].xcpt_ae_if connect rob.io.enq_uops[0].xcpt_pf_if, dis_uops[0].xcpt_pf_if connect rob.io.enq_uops[0].fp_typ, dis_uops[0].fp_typ connect rob.io.enq_uops[0].fp_rm, dis_uops[0].fp_rm connect rob.io.enq_uops[0].fp_val, dis_uops[0].fp_val connect rob.io.enq_uops[0].fcn_op, dis_uops[0].fcn_op connect rob.io.enq_uops[0].fcn_dw, dis_uops[0].fcn_dw connect rob.io.enq_uops[0].frs3_en, dis_uops[0].frs3_en connect rob.io.enq_uops[0].lrs2_rtype, dis_uops[0].lrs2_rtype connect rob.io.enq_uops[0].lrs1_rtype, dis_uops[0].lrs1_rtype connect rob.io.enq_uops[0].dst_rtype, dis_uops[0].dst_rtype connect rob.io.enq_uops[0].lrs3, dis_uops[0].lrs3 connect rob.io.enq_uops[0].lrs2, dis_uops[0].lrs2 connect rob.io.enq_uops[0].lrs1, dis_uops[0].lrs1 connect rob.io.enq_uops[0].ldst, dis_uops[0].ldst connect rob.io.enq_uops[0].ldst_is_rs1, dis_uops[0].ldst_is_rs1 connect rob.io.enq_uops[0].csr_cmd, dis_uops[0].csr_cmd connect rob.io.enq_uops[0].flush_on_commit, dis_uops[0].flush_on_commit connect rob.io.enq_uops[0].is_unique, dis_uops[0].is_unique connect rob.io.enq_uops[0].uses_stq, dis_uops[0].uses_stq connect rob.io.enq_uops[0].uses_ldq, dis_uops[0].uses_ldq connect rob.io.enq_uops[0].mem_signed, dis_uops[0].mem_signed connect rob.io.enq_uops[0].mem_size, dis_uops[0].mem_size connect rob.io.enq_uops[0].mem_cmd, dis_uops[0].mem_cmd connect rob.io.enq_uops[0].exc_cause, dis_uops[0].exc_cause connect rob.io.enq_uops[0].exception, dis_uops[0].exception connect rob.io.enq_uops[0].stale_pdst, dis_uops[0].stale_pdst connect rob.io.enq_uops[0].ppred_busy, dis_uops[0].ppred_busy connect rob.io.enq_uops[0].prs3_busy, dis_uops[0].prs3_busy connect rob.io.enq_uops[0].prs2_busy, dis_uops[0].prs2_busy connect rob.io.enq_uops[0].prs1_busy, dis_uops[0].prs1_busy connect rob.io.enq_uops[0].ppred, dis_uops[0].ppred connect rob.io.enq_uops[0].prs3, dis_uops[0].prs3 connect rob.io.enq_uops[0].prs2, dis_uops[0].prs2 connect rob.io.enq_uops[0].prs1, dis_uops[0].prs1 connect rob.io.enq_uops[0].pdst, dis_uops[0].pdst connect rob.io.enq_uops[0].rxq_idx, dis_uops[0].rxq_idx connect rob.io.enq_uops[0].stq_idx, dis_uops[0].stq_idx connect rob.io.enq_uops[0].ldq_idx, dis_uops[0].ldq_idx connect rob.io.enq_uops[0].rob_idx, dis_uops[0].rob_idx connect rob.io.enq_uops[0].fp_ctrl.vec, dis_uops[0].fp_ctrl.vec connect rob.io.enq_uops[0].fp_ctrl.wflags, dis_uops[0].fp_ctrl.wflags connect rob.io.enq_uops[0].fp_ctrl.sqrt, dis_uops[0].fp_ctrl.sqrt connect rob.io.enq_uops[0].fp_ctrl.div, dis_uops[0].fp_ctrl.div connect rob.io.enq_uops[0].fp_ctrl.fma, dis_uops[0].fp_ctrl.fma connect rob.io.enq_uops[0].fp_ctrl.fastpipe, dis_uops[0].fp_ctrl.fastpipe connect rob.io.enq_uops[0].fp_ctrl.toint, dis_uops[0].fp_ctrl.toint connect rob.io.enq_uops[0].fp_ctrl.fromint, dis_uops[0].fp_ctrl.fromint connect rob.io.enq_uops[0].fp_ctrl.typeTagOut, dis_uops[0].fp_ctrl.typeTagOut connect rob.io.enq_uops[0].fp_ctrl.typeTagIn, dis_uops[0].fp_ctrl.typeTagIn connect rob.io.enq_uops[0].fp_ctrl.swap23, dis_uops[0].fp_ctrl.swap23 connect rob.io.enq_uops[0].fp_ctrl.swap12, dis_uops[0].fp_ctrl.swap12 connect rob.io.enq_uops[0].fp_ctrl.ren3, dis_uops[0].fp_ctrl.ren3 connect rob.io.enq_uops[0].fp_ctrl.ren2, dis_uops[0].fp_ctrl.ren2 connect rob.io.enq_uops[0].fp_ctrl.ren1, dis_uops[0].fp_ctrl.ren1 connect rob.io.enq_uops[0].fp_ctrl.wen, dis_uops[0].fp_ctrl.wen connect rob.io.enq_uops[0].fp_ctrl.ldst, dis_uops[0].fp_ctrl.ldst connect rob.io.enq_uops[0].op2_sel, dis_uops[0].op2_sel connect rob.io.enq_uops[0].op1_sel, dis_uops[0].op1_sel connect rob.io.enq_uops[0].imm_packed, dis_uops[0].imm_packed connect rob.io.enq_uops[0].pimm, dis_uops[0].pimm connect rob.io.enq_uops[0].imm_sel, dis_uops[0].imm_sel connect rob.io.enq_uops[0].imm_rename, dis_uops[0].imm_rename connect rob.io.enq_uops[0].taken, dis_uops[0].taken connect rob.io.enq_uops[0].pc_lob, dis_uops[0].pc_lob connect rob.io.enq_uops[0].edge_inst, dis_uops[0].edge_inst connect rob.io.enq_uops[0].ftq_idx, dis_uops[0].ftq_idx connect rob.io.enq_uops[0].is_mov, dis_uops[0].is_mov connect rob.io.enq_uops[0].is_rocc, dis_uops[0].is_rocc connect rob.io.enq_uops[0].is_sys_pc2epc, dis_uops[0].is_sys_pc2epc connect rob.io.enq_uops[0].is_eret, dis_uops[0].is_eret connect rob.io.enq_uops[0].is_amo, dis_uops[0].is_amo connect rob.io.enq_uops[0].is_sfence, dis_uops[0].is_sfence connect rob.io.enq_uops[0].is_fencei, dis_uops[0].is_fencei connect rob.io.enq_uops[0].is_fence, dis_uops[0].is_fence connect rob.io.enq_uops[0].is_sfb, dis_uops[0].is_sfb connect rob.io.enq_uops[0].br_type, dis_uops[0].br_type connect rob.io.enq_uops[0].br_tag, dis_uops[0].br_tag connect rob.io.enq_uops[0].br_mask, dis_uops[0].br_mask connect rob.io.enq_uops[0].dis_col_sel, dis_uops[0].dis_col_sel connect rob.io.enq_uops[0].iw_p3_bypass_hint, dis_uops[0].iw_p3_bypass_hint connect rob.io.enq_uops[0].iw_p2_bypass_hint, dis_uops[0].iw_p2_bypass_hint connect rob.io.enq_uops[0].iw_p1_bypass_hint, dis_uops[0].iw_p1_bypass_hint connect rob.io.enq_uops[0].iw_p2_speculative_child, dis_uops[0].iw_p2_speculative_child connect rob.io.enq_uops[0].iw_p1_speculative_child, dis_uops[0].iw_p1_speculative_child connect rob.io.enq_uops[0].iw_issued_partial_dgen, dis_uops[0].iw_issued_partial_dgen connect rob.io.enq_uops[0].iw_issued_partial_agen, dis_uops[0].iw_issued_partial_agen connect rob.io.enq_uops[0].iw_issued, dis_uops[0].iw_issued connect rob.io.enq_uops[0].fu_code[0], dis_uops[0].fu_code[0] connect rob.io.enq_uops[0].fu_code[1], dis_uops[0].fu_code[1] connect rob.io.enq_uops[0].fu_code[2], dis_uops[0].fu_code[2] connect rob.io.enq_uops[0].fu_code[3], dis_uops[0].fu_code[3] connect rob.io.enq_uops[0].fu_code[4], dis_uops[0].fu_code[4] connect rob.io.enq_uops[0].fu_code[5], dis_uops[0].fu_code[5] connect rob.io.enq_uops[0].fu_code[6], dis_uops[0].fu_code[6] connect rob.io.enq_uops[0].fu_code[7], dis_uops[0].fu_code[7] connect rob.io.enq_uops[0].fu_code[8], dis_uops[0].fu_code[8] connect rob.io.enq_uops[0].fu_code[9], dis_uops[0].fu_code[9] connect rob.io.enq_uops[0].iq_type[0], dis_uops[0].iq_type[0] connect rob.io.enq_uops[0].iq_type[1], dis_uops[0].iq_type[1] connect rob.io.enq_uops[0].iq_type[2], dis_uops[0].iq_type[2] connect rob.io.enq_uops[0].iq_type[3], dis_uops[0].iq_type[3] connect rob.io.enq_uops[0].debug_pc, dis_uops[0].debug_pc connect rob.io.enq_uops[0].is_rvc, dis_uops[0].is_rvc connect rob.io.enq_uops[0].debug_inst, dis_uops[0].debug_inst connect rob.io.enq_uops[0].inst, dis_uops[0].inst connect rob.io.enq_uops[1].debug_tsrc, dis_uops[1].debug_tsrc connect rob.io.enq_uops[1].debug_fsrc, dis_uops[1].debug_fsrc connect rob.io.enq_uops[1].bp_xcpt_if, dis_uops[1].bp_xcpt_if connect rob.io.enq_uops[1].bp_debug_if, dis_uops[1].bp_debug_if connect rob.io.enq_uops[1].xcpt_ma_if, dis_uops[1].xcpt_ma_if connect rob.io.enq_uops[1].xcpt_ae_if, dis_uops[1].xcpt_ae_if connect rob.io.enq_uops[1].xcpt_pf_if, dis_uops[1].xcpt_pf_if connect rob.io.enq_uops[1].fp_typ, dis_uops[1].fp_typ connect rob.io.enq_uops[1].fp_rm, dis_uops[1].fp_rm connect rob.io.enq_uops[1].fp_val, dis_uops[1].fp_val connect rob.io.enq_uops[1].fcn_op, dis_uops[1].fcn_op connect rob.io.enq_uops[1].fcn_dw, dis_uops[1].fcn_dw connect rob.io.enq_uops[1].frs3_en, dis_uops[1].frs3_en connect rob.io.enq_uops[1].lrs2_rtype, dis_uops[1].lrs2_rtype connect rob.io.enq_uops[1].lrs1_rtype, dis_uops[1].lrs1_rtype connect rob.io.enq_uops[1].dst_rtype, dis_uops[1].dst_rtype connect rob.io.enq_uops[1].lrs3, dis_uops[1].lrs3 connect rob.io.enq_uops[1].lrs2, dis_uops[1].lrs2 connect rob.io.enq_uops[1].lrs1, dis_uops[1].lrs1 connect rob.io.enq_uops[1].ldst, dis_uops[1].ldst connect rob.io.enq_uops[1].ldst_is_rs1, dis_uops[1].ldst_is_rs1 connect rob.io.enq_uops[1].csr_cmd, dis_uops[1].csr_cmd connect rob.io.enq_uops[1].flush_on_commit, dis_uops[1].flush_on_commit connect rob.io.enq_uops[1].is_unique, dis_uops[1].is_unique connect rob.io.enq_uops[1].uses_stq, dis_uops[1].uses_stq connect rob.io.enq_uops[1].uses_ldq, dis_uops[1].uses_ldq connect rob.io.enq_uops[1].mem_signed, dis_uops[1].mem_signed connect rob.io.enq_uops[1].mem_size, dis_uops[1].mem_size connect rob.io.enq_uops[1].mem_cmd, dis_uops[1].mem_cmd connect rob.io.enq_uops[1].exc_cause, dis_uops[1].exc_cause connect rob.io.enq_uops[1].exception, dis_uops[1].exception connect rob.io.enq_uops[1].stale_pdst, dis_uops[1].stale_pdst connect rob.io.enq_uops[1].ppred_busy, dis_uops[1].ppred_busy connect rob.io.enq_uops[1].prs3_busy, dis_uops[1].prs3_busy connect rob.io.enq_uops[1].prs2_busy, dis_uops[1].prs2_busy connect rob.io.enq_uops[1].prs1_busy, dis_uops[1].prs1_busy connect rob.io.enq_uops[1].ppred, dis_uops[1].ppred connect rob.io.enq_uops[1].prs3, dis_uops[1].prs3 connect rob.io.enq_uops[1].prs2, dis_uops[1].prs2 connect rob.io.enq_uops[1].prs1, dis_uops[1].prs1 connect rob.io.enq_uops[1].pdst, dis_uops[1].pdst connect rob.io.enq_uops[1].rxq_idx, dis_uops[1].rxq_idx connect rob.io.enq_uops[1].stq_idx, dis_uops[1].stq_idx connect rob.io.enq_uops[1].ldq_idx, dis_uops[1].ldq_idx connect rob.io.enq_uops[1].rob_idx, dis_uops[1].rob_idx connect rob.io.enq_uops[1].fp_ctrl.vec, dis_uops[1].fp_ctrl.vec connect rob.io.enq_uops[1].fp_ctrl.wflags, dis_uops[1].fp_ctrl.wflags connect rob.io.enq_uops[1].fp_ctrl.sqrt, dis_uops[1].fp_ctrl.sqrt connect rob.io.enq_uops[1].fp_ctrl.div, dis_uops[1].fp_ctrl.div connect rob.io.enq_uops[1].fp_ctrl.fma, dis_uops[1].fp_ctrl.fma connect rob.io.enq_uops[1].fp_ctrl.fastpipe, dis_uops[1].fp_ctrl.fastpipe connect rob.io.enq_uops[1].fp_ctrl.toint, dis_uops[1].fp_ctrl.toint connect rob.io.enq_uops[1].fp_ctrl.fromint, dis_uops[1].fp_ctrl.fromint connect rob.io.enq_uops[1].fp_ctrl.typeTagOut, dis_uops[1].fp_ctrl.typeTagOut connect rob.io.enq_uops[1].fp_ctrl.typeTagIn, dis_uops[1].fp_ctrl.typeTagIn connect rob.io.enq_uops[1].fp_ctrl.swap23, dis_uops[1].fp_ctrl.swap23 connect rob.io.enq_uops[1].fp_ctrl.swap12, dis_uops[1].fp_ctrl.swap12 connect rob.io.enq_uops[1].fp_ctrl.ren3, dis_uops[1].fp_ctrl.ren3 connect rob.io.enq_uops[1].fp_ctrl.ren2, dis_uops[1].fp_ctrl.ren2 connect rob.io.enq_uops[1].fp_ctrl.ren1, dis_uops[1].fp_ctrl.ren1 connect rob.io.enq_uops[1].fp_ctrl.wen, dis_uops[1].fp_ctrl.wen connect rob.io.enq_uops[1].fp_ctrl.ldst, dis_uops[1].fp_ctrl.ldst connect rob.io.enq_uops[1].op2_sel, dis_uops[1].op2_sel connect rob.io.enq_uops[1].op1_sel, dis_uops[1].op1_sel connect rob.io.enq_uops[1].imm_packed, dis_uops[1].imm_packed connect rob.io.enq_uops[1].pimm, dis_uops[1].pimm connect rob.io.enq_uops[1].imm_sel, dis_uops[1].imm_sel connect rob.io.enq_uops[1].imm_rename, dis_uops[1].imm_rename connect rob.io.enq_uops[1].taken, dis_uops[1].taken connect rob.io.enq_uops[1].pc_lob, dis_uops[1].pc_lob connect rob.io.enq_uops[1].edge_inst, dis_uops[1].edge_inst connect rob.io.enq_uops[1].ftq_idx, dis_uops[1].ftq_idx connect rob.io.enq_uops[1].is_mov, dis_uops[1].is_mov connect rob.io.enq_uops[1].is_rocc, dis_uops[1].is_rocc connect rob.io.enq_uops[1].is_sys_pc2epc, dis_uops[1].is_sys_pc2epc connect rob.io.enq_uops[1].is_eret, dis_uops[1].is_eret connect rob.io.enq_uops[1].is_amo, dis_uops[1].is_amo connect rob.io.enq_uops[1].is_sfence, dis_uops[1].is_sfence connect rob.io.enq_uops[1].is_fencei, dis_uops[1].is_fencei connect rob.io.enq_uops[1].is_fence, dis_uops[1].is_fence connect rob.io.enq_uops[1].is_sfb, dis_uops[1].is_sfb connect rob.io.enq_uops[1].br_type, dis_uops[1].br_type connect rob.io.enq_uops[1].br_tag, dis_uops[1].br_tag connect rob.io.enq_uops[1].br_mask, dis_uops[1].br_mask connect rob.io.enq_uops[1].dis_col_sel, dis_uops[1].dis_col_sel connect rob.io.enq_uops[1].iw_p3_bypass_hint, dis_uops[1].iw_p3_bypass_hint connect rob.io.enq_uops[1].iw_p2_bypass_hint, dis_uops[1].iw_p2_bypass_hint connect rob.io.enq_uops[1].iw_p1_bypass_hint, dis_uops[1].iw_p1_bypass_hint connect rob.io.enq_uops[1].iw_p2_speculative_child, dis_uops[1].iw_p2_speculative_child connect rob.io.enq_uops[1].iw_p1_speculative_child, dis_uops[1].iw_p1_speculative_child connect rob.io.enq_uops[1].iw_issued_partial_dgen, dis_uops[1].iw_issued_partial_dgen connect rob.io.enq_uops[1].iw_issued_partial_agen, dis_uops[1].iw_issued_partial_agen connect rob.io.enq_uops[1].iw_issued, dis_uops[1].iw_issued connect rob.io.enq_uops[1].fu_code[0], dis_uops[1].fu_code[0] connect rob.io.enq_uops[1].fu_code[1], dis_uops[1].fu_code[1] connect rob.io.enq_uops[1].fu_code[2], dis_uops[1].fu_code[2] connect rob.io.enq_uops[1].fu_code[3], dis_uops[1].fu_code[3] connect rob.io.enq_uops[1].fu_code[4], dis_uops[1].fu_code[4] connect rob.io.enq_uops[1].fu_code[5], dis_uops[1].fu_code[5] connect rob.io.enq_uops[1].fu_code[6], dis_uops[1].fu_code[6] connect rob.io.enq_uops[1].fu_code[7], dis_uops[1].fu_code[7] connect rob.io.enq_uops[1].fu_code[8], dis_uops[1].fu_code[8] connect rob.io.enq_uops[1].fu_code[9], dis_uops[1].fu_code[9] connect rob.io.enq_uops[1].iq_type[0], dis_uops[1].iq_type[0] connect rob.io.enq_uops[1].iq_type[1], dis_uops[1].iq_type[1] connect rob.io.enq_uops[1].iq_type[2], dis_uops[1].iq_type[2] connect rob.io.enq_uops[1].iq_type[3], dis_uops[1].iq_type[3] connect rob.io.enq_uops[1].debug_pc, dis_uops[1].debug_pc connect rob.io.enq_uops[1].is_rvc, dis_uops[1].is_rvc connect rob.io.enq_uops[1].debug_inst, dis_uops[1].debug_inst connect rob.io.enq_uops[1].inst, dis_uops[1].inst connect rob.io.enq_partial_stall, dis_stalls_1 connect rob.io.debug_tsc, debug_tsc_reg connect rob.io.csr_stall, csr.io.csr_stall node _T_115 = or(dis_fire[0], dis_fire[1]) node _T_116 = mux(dis_fire[0], UInt<1>(0h0), UInt<1>(0h1)) node _T_117 = and(_T_115, dis_uops[_T_116].is_sys_pc2epc) reg REG_2 : UInt<1>, clock connect REG_2, _T_117 when REG_2 : connect io.ifu.commit.valid, UInt<1>(0h1) node _io_ifu_commit_bits_T_1 = mux(dis_valids[0], UInt<1>(0h0), UInt<1>(0h1)) reg io_ifu_commit_bits_REG : UInt, clock connect io_ifu_commit_bits_REG, dis_uops[_io_ifu_commit_bits_T_1].ftq_idx connect io.ifu.commit.bits, io_ifu_commit_bits_REG node _dis_uops_0_rob_idx_T = dshr(rob.io.rob_tail_idx, UInt<1>(0h1)) node _dis_uops_0_rob_idx_T_1 = cat(_dis_uops_0_rob_idx_T, UInt<1>(0h0)) connect dis_uops[0].rob_idx, _dis_uops_0_rob_idx_T_1 node _dis_uops_1_rob_idx_T = dshr(rob.io.rob_tail_idx, UInt<1>(0h1)) node _dis_uops_1_rob_idx_T_1 = cat(_dis_uops_1_rob_idx_T, UInt<1>(0h1)) connect dis_uops[1].rob_idx, _dis_uops_1_rob_idx_T_1 connect dispatcher.io.ren_uops[0].valid, dis_fire[0] connect dispatcher.io.ren_uops[0].bits.debug_tsrc, dis_uops[0].debug_tsrc connect dispatcher.io.ren_uops[0].bits.debug_fsrc, dis_uops[0].debug_fsrc connect dispatcher.io.ren_uops[0].bits.bp_xcpt_if, dis_uops[0].bp_xcpt_if connect dispatcher.io.ren_uops[0].bits.bp_debug_if, dis_uops[0].bp_debug_if connect dispatcher.io.ren_uops[0].bits.xcpt_ma_if, dis_uops[0].xcpt_ma_if connect dispatcher.io.ren_uops[0].bits.xcpt_ae_if, dis_uops[0].xcpt_ae_if connect dispatcher.io.ren_uops[0].bits.xcpt_pf_if, dis_uops[0].xcpt_pf_if connect dispatcher.io.ren_uops[0].bits.fp_typ, dis_uops[0].fp_typ connect dispatcher.io.ren_uops[0].bits.fp_rm, dis_uops[0].fp_rm connect dispatcher.io.ren_uops[0].bits.fp_val, dis_uops[0].fp_val connect dispatcher.io.ren_uops[0].bits.fcn_op, dis_uops[0].fcn_op connect dispatcher.io.ren_uops[0].bits.fcn_dw, dis_uops[0].fcn_dw connect dispatcher.io.ren_uops[0].bits.frs3_en, dis_uops[0].frs3_en connect dispatcher.io.ren_uops[0].bits.lrs2_rtype, dis_uops[0].lrs2_rtype connect dispatcher.io.ren_uops[0].bits.lrs1_rtype, dis_uops[0].lrs1_rtype connect dispatcher.io.ren_uops[0].bits.dst_rtype, dis_uops[0].dst_rtype connect dispatcher.io.ren_uops[0].bits.lrs3, dis_uops[0].lrs3 connect dispatcher.io.ren_uops[0].bits.lrs2, dis_uops[0].lrs2 connect dispatcher.io.ren_uops[0].bits.lrs1, dis_uops[0].lrs1 connect dispatcher.io.ren_uops[0].bits.ldst, dis_uops[0].ldst connect dispatcher.io.ren_uops[0].bits.ldst_is_rs1, dis_uops[0].ldst_is_rs1 connect dispatcher.io.ren_uops[0].bits.csr_cmd, dis_uops[0].csr_cmd connect dispatcher.io.ren_uops[0].bits.flush_on_commit, dis_uops[0].flush_on_commit connect dispatcher.io.ren_uops[0].bits.is_unique, dis_uops[0].is_unique connect dispatcher.io.ren_uops[0].bits.uses_stq, dis_uops[0].uses_stq connect dispatcher.io.ren_uops[0].bits.uses_ldq, dis_uops[0].uses_ldq connect dispatcher.io.ren_uops[0].bits.mem_signed, dis_uops[0].mem_signed connect dispatcher.io.ren_uops[0].bits.mem_size, dis_uops[0].mem_size connect dispatcher.io.ren_uops[0].bits.mem_cmd, dis_uops[0].mem_cmd connect dispatcher.io.ren_uops[0].bits.exc_cause, dis_uops[0].exc_cause connect dispatcher.io.ren_uops[0].bits.exception, dis_uops[0].exception connect dispatcher.io.ren_uops[0].bits.stale_pdst, dis_uops[0].stale_pdst connect dispatcher.io.ren_uops[0].bits.ppred_busy, dis_uops[0].ppred_busy connect dispatcher.io.ren_uops[0].bits.prs3_busy, dis_uops[0].prs3_busy connect dispatcher.io.ren_uops[0].bits.prs2_busy, dis_uops[0].prs2_busy connect dispatcher.io.ren_uops[0].bits.prs1_busy, dis_uops[0].prs1_busy connect dispatcher.io.ren_uops[0].bits.ppred, dis_uops[0].ppred connect dispatcher.io.ren_uops[0].bits.prs3, dis_uops[0].prs3 connect dispatcher.io.ren_uops[0].bits.prs2, dis_uops[0].prs2 connect dispatcher.io.ren_uops[0].bits.prs1, dis_uops[0].prs1 connect dispatcher.io.ren_uops[0].bits.pdst, dis_uops[0].pdst connect dispatcher.io.ren_uops[0].bits.rxq_idx, dis_uops[0].rxq_idx connect dispatcher.io.ren_uops[0].bits.stq_idx, dis_uops[0].stq_idx connect dispatcher.io.ren_uops[0].bits.ldq_idx, dis_uops[0].ldq_idx connect dispatcher.io.ren_uops[0].bits.rob_idx, dis_uops[0].rob_idx connect dispatcher.io.ren_uops[0].bits.fp_ctrl.vec, dis_uops[0].fp_ctrl.vec connect dispatcher.io.ren_uops[0].bits.fp_ctrl.wflags, dis_uops[0].fp_ctrl.wflags connect dispatcher.io.ren_uops[0].bits.fp_ctrl.sqrt, dis_uops[0].fp_ctrl.sqrt connect dispatcher.io.ren_uops[0].bits.fp_ctrl.div, dis_uops[0].fp_ctrl.div connect dispatcher.io.ren_uops[0].bits.fp_ctrl.fma, dis_uops[0].fp_ctrl.fma connect dispatcher.io.ren_uops[0].bits.fp_ctrl.fastpipe, dis_uops[0].fp_ctrl.fastpipe connect dispatcher.io.ren_uops[0].bits.fp_ctrl.toint, dis_uops[0].fp_ctrl.toint connect dispatcher.io.ren_uops[0].bits.fp_ctrl.fromint, dis_uops[0].fp_ctrl.fromint connect dispatcher.io.ren_uops[0].bits.fp_ctrl.typeTagOut, dis_uops[0].fp_ctrl.typeTagOut connect dispatcher.io.ren_uops[0].bits.fp_ctrl.typeTagIn, dis_uops[0].fp_ctrl.typeTagIn connect dispatcher.io.ren_uops[0].bits.fp_ctrl.swap23, dis_uops[0].fp_ctrl.swap23 connect dispatcher.io.ren_uops[0].bits.fp_ctrl.swap12, dis_uops[0].fp_ctrl.swap12 connect dispatcher.io.ren_uops[0].bits.fp_ctrl.ren3, dis_uops[0].fp_ctrl.ren3 connect dispatcher.io.ren_uops[0].bits.fp_ctrl.ren2, dis_uops[0].fp_ctrl.ren2 connect dispatcher.io.ren_uops[0].bits.fp_ctrl.ren1, dis_uops[0].fp_ctrl.ren1 connect dispatcher.io.ren_uops[0].bits.fp_ctrl.wen, dis_uops[0].fp_ctrl.wen connect dispatcher.io.ren_uops[0].bits.fp_ctrl.ldst, dis_uops[0].fp_ctrl.ldst connect dispatcher.io.ren_uops[0].bits.op2_sel, dis_uops[0].op2_sel connect dispatcher.io.ren_uops[0].bits.op1_sel, dis_uops[0].op1_sel connect dispatcher.io.ren_uops[0].bits.imm_packed, dis_uops[0].imm_packed connect dispatcher.io.ren_uops[0].bits.pimm, dis_uops[0].pimm connect dispatcher.io.ren_uops[0].bits.imm_sel, dis_uops[0].imm_sel connect dispatcher.io.ren_uops[0].bits.imm_rename, dis_uops[0].imm_rename connect dispatcher.io.ren_uops[0].bits.taken, dis_uops[0].taken connect dispatcher.io.ren_uops[0].bits.pc_lob, dis_uops[0].pc_lob connect dispatcher.io.ren_uops[0].bits.edge_inst, dis_uops[0].edge_inst connect dispatcher.io.ren_uops[0].bits.ftq_idx, dis_uops[0].ftq_idx connect dispatcher.io.ren_uops[0].bits.is_mov, dis_uops[0].is_mov connect dispatcher.io.ren_uops[0].bits.is_rocc, dis_uops[0].is_rocc connect dispatcher.io.ren_uops[0].bits.is_sys_pc2epc, dis_uops[0].is_sys_pc2epc connect dispatcher.io.ren_uops[0].bits.is_eret, dis_uops[0].is_eret connect dispatcher.io.ren_uops[0].bits.is_amo, dis_uops[0].is_amo connect dispatcher.io.ren_uops[0].bits.is_sfence, dis_uops[0].is_sfence connect dispatcher.io.ren_uops[0].bits.is_fencei, dis_uops[0].is_fencei connect dispatcher.io.ren_uops[0].bits.is_fence, dis_uops[0].is_fence connect dispatcher.io.ren_uops[0].bits.is_sfb, dis_uops[0].is_sfb connect dispatcher.io.ren_uops[0].bits.br_type, dis_uops[0].br_type connect dispatcher.io.ren_uops[0].bits.br_tag, dis_uops[0].br_tag connect dispatcher.io.ren_uops[0].bits.br_mask, dis_uops[0].br_mask connect dispatcher.io.ren_uops[0].bits.dis_col_sel, dis_uops[0].dis_col_sel connect dispatcher.io.ren_uops[0].bits.iw_p3_bypass_hint, dis_uops[0].iw_p3_bypass_hint connect dispatcher.io.ren_uops[0].bits.iw_p2_bypass_hint, dis_uops[0].iw_p2_bypass_hint connect dispatcher.io.ren_uops[0].bits.iw_p1_bypass_hint, dis_uops[0].iw_p1_bypass_hint connect dispatcher.io.ren_uops[0].bits.iw_p2_speculative_child, dis_uops[0].iw_p2_speculative_child connect dispatcher.io.ren_uops[0].bits.iw_p1_speculative_child, dis_uops[0].iw_p1_speculative_child connect dispatcher.io.ren_uops[0].bits.iw_issued_partial_dgen, dis_uops[0].iw_issued_partial_dgen connect dispatcher.io.ren_uops[0].bits.iw_issued_partial_agen, dis_uops[0].iw_issued_partial_agen connect dispatcher.io.ren_uops[0].bits.iw_issued, dis_uops[0].iw_issued connect dispatcher.io.ren_uops[0].bits.fu_code[0], dis_uops[0].fu_code[0] connect dispatcher.io.ren_uops[0].bits.fu_code[1], dis_uops[0].fu_code[1] connect dispatcher.io.ren_uops[0].bits.fu_code[2], dis_uops[0].fu_code[2] connect dispatcher.io.ren_uops[0].bits.fu_code[3], dis_uops[0].fu_code[3] connect dispatcher.io.ren_uops[0].bits.fu_code[4], dis_uops[0].fu_code[4] connect dispatcher.io.ren_uops[0].bits.fu_code[5], dis_uops[0].fu_code[5] connect dispatcher.io.ren_uops[0].bits.fu_code[6], dis_uops[0].fu_code[6] connect dispatcher.io.ren_uops[0].bits.fu_code[7], dis_uops[0].fu_code[7] connect dispatcher.io.ren_uops[0].bits.fu_code[8], dis_uops[0].fu_code[8] connect dispatcher.io.ren_uops[0].bits.fu_code[9], dis_uops[0].fu_code[9] connect dispatcher.io.ren_uops[0].bits.iq_type[0], dis_uops[0].iq_type[0] connect dispatcher.io.ren_uops[0].bits.iq_type[1], dis_uops[0].iq_type[1] connect dispatcher.io.ren_uops[0].bits.iq_type[2], dis_uops[0].iq_type[2] connect dispatcher.io.ren_uops[0].bits.iq_type[3], dis_uops[0].iq_type[3] connect dispatcher.io.ren_uops[0].bits.debug_pc, dis_uops[0].debug_pc connect dispatcher.io.ren_uops[0].bits.is_rvc, dis_uops[0].is_rvc connect dispatcher.io.ren_uops[0].bits.debug_inst, dis_uops[0].debug_inst connect dispatcher.io.ren_uops[0].bits.inst, dis_uops[0].inst connect dispatcher.io.ren_uops[1].valid, dis_fire[1] connect dispatcher.io.ren_uops[1].bits.debug_tsrc, dis_uops[1].debug_tsrc connect dispatcher.io.ren_uops[1].bits.debug_fsrc, dis_uops[1].debug_fsrc connect dispatcher.io.ren_uops[1].bits.bp_xcpt_if, dis_uops[1].bp_xcpt_if connect dispatcher.io.ren_uops[1].bits.bp_debug_if, dis_uops[1].bp_debug_if connect dispatcher.io.ren_uops[1].bits.xcpt_ma_if, dis_uops[1].xcpt_ma_if connect dispatcher.io.ren_uops[1].bits.xcpt_ae_if, dis_uops[1].xcpt_ae_if connect dispatcher.io.ren_uops[1].bits.xcpt_pf_if, dis_uops[1].xcpt_pf_if connect dispatcher.io.ren_uops[1].bits.fp_typ, dis_uops[1].fp_typ connect dispatcher.io.ren_uops[1].bits.fp_rm, dis_uops[1].fp_rm connect dispatcher.io.ren_uops[1].bits.fp_val, dis_uops[1].fp_val connect dispatcher.io.ren_uops[1].bits.fcn_op, dis_uops[1].fcn_op connect dispatcher.io.ren_uops[1].bits.fcn_dw, dis_uops[1].fcn_dw connect dispatcher.io.ren_uops[1].bits.frs3_en, dis_uops[1].frs3_en connect dispatcher.io.ren_uops[1].bits.lrs2_rtype, dis_uops[1].lrs2_rtype connect dispatcher.io.ren_uops[1].bits.lrs1_rtype, dis_uops[1].lrs1_rtype connect dispatcher.io.ren_uops[1].bits.dst_rtype, dis_uops[1].dst_rtype connect dispatcher.io.ren_uops[1].bits.lrs3, dis_uops[1].lrs3 connect dispatcher.io.ren_uops[1].bits.lrs2, dis_uops[1].lrs2 connect dispatcher.io.ren_uops[1].bits.lrs1, dis_uops[1].lrs1 connect dispatcher.io.ren_uops[1].bits.ldst, dis_uops[1].ldst connect dispatcher.io.ren_uops[1].bits.ldst_is_rs1, dis_uops[1].ldst_is_rs1 connect dispatcher.io.ren_uops[1].bits.csr_cmd, dis_uops[1].csr_cmd connect dispatcher.io.ren_uops[1].bits.flush_on_commit, dis_uops[1].flush_on_commit connect dispatcher.io.ren_uops[1].bits.is_unique, dis_uops[1].is_unique connect dispatcher.io.ren_uops[1].bits.uses_stq, dis_uops[1].uses_stq connect dispatcher.io.ren_uops[1].bits.uses_ldq, dis_uops[1].uses_ldq connect dispatcher.io.ren_uops[1].bits.mem_signed, dis_uops[1].mem_signed connect dispatcher.io.ren_uops[1].bits.mem_size, dis_uops[1].mem_size connect dispatcher.io.ren_uops[1].bits.mem_cmd, dis_uops[1].mem_cmd connect dispatcher.io.ren_uops[1].bits.exc_cause, dis_uops[1].exc_cause connect dispatcher.io.ren_uops[1].bits.exception, dis_uops[1].exception connect dispatcher.io.ren_uops[1].bits.stale_pdst, dis_uops[1].stale_pdst connect dispatcher.io.ren_uops[1].bits.ppred_busy, dis_uops[1].ppred_busy connect dispatcher.io.ren_uops[1].bits.prs3_busy, dis_uops[1].prs3_busy connect dispatcher.io.ren_uops[1].bits.prs2_busy, dis_uops[1].prs2_busy connect dispatcher.io.ren_uops[1].bits.prs1_busy, dis_uops[1].prs1_busy connect dispatcher.io.ren_uops[1].bits.ppred, dis_uops[1].ppred connect dispatcher.io.ren_uops[1].bits.prs3, dis_uops[1].prs3 connect dispatcher.io.ren_uops[1].bits.prs2, dis_uops[1].prs2 connect dispatcher.io.ren_uops[1].bits.prs1, dis_uops[1].prs1 connect dispatcher.io.ren_uops[1].bits.pdst, dis_uops[1].pdst connect dispatcher.io.ren_uops[1].bits.rxq_idx, dis_uops[1].rxq_idx connect dispatcher.io.ren_uops[1].bits.stq_idx, dis_uops[1].stq_idx connect dispatcher.io.ren_uops[1].bits.ldq_idx, dis_uops[1].ldq_idx connect dispatcher.io.ren_uops[1].bits.rob_idx, dis_uops[1].rob_idx connect dispatcher.io.ren_uops[1].bits.fp_ctrl.vec, dis_uops[1].fp_ctrl.vec connect dispatcher.io.ren_uops[1].bits.fp_ctrl.wflags, dis_uops[1].fp_ctrl.wflags connect dispatcher.io.ren_uops[1].bits.fp_ctrl.sqrt, dis_uops[1].fp_ctrl.sqrt connect dispatcher.io.ren_uops[1].bits.fp_ctrl.div, dis_uops[1].fp_ctrl.div connect dispatcher.io.ren_uops[1].bits.fp_ctrl.fma, dis_uops[1].fp_ctrl.fma connect dispatcher.io.ren_uops[1].bits.fp_ctrl.fastpipe, dis_uops[1].fp_ctrl.fastpipe connect dispatcher.io.ren_uops[1].bits.fp_ctrl.toint, dis_uops[1].fp_ctrl.toint connect dispatcher.io.ren_uops[1].bits.fp_ctrl.fromint, dis_uops[1].fp_ctrl.fromint connect dispatcher.io.ren_uops[1].bits.fp_ctrl.typeTagOut, dis_uops[1].fp_ctrl.typeTagOut connect dispatcher.io.ren_uops[1].bits.fp_ctrl.typeTagIn, dis_uops[1].fp_ctrl.typeTagIn connect dispatcher.io.ren_uops[1].bits.fp_ctrl.swap23, dis_uops[1].fp_ctrl.swap23 connect dispatcher.io.ren_uops[1].bits.fp_ctrl.swap12, dis_uops[1].fp_ctrl.swap12 connect dispatcher.io.ren_uops[1].bits.fp_ctrl.ren3, dis_uops[1].fp_ctrl.ren3 connect dispatcher.io.ren_uops[1].bits.fp_ctrl.ren2, dis_uops[1].fp_ctrl.ren2 connect dispatcher.io.ren_uops[1].bits.fp_ctrl.ren1, dis_uops[1].fp_ctrl.ren1 connect dispatcher.io.ren_uops[1].bits.fp_ctrl.wen, dis_uops[1].fp_ctrl.wen connect dispatcher.io.ren_uops[1].bits.fp_ctrl.ldst, dis_uops[1].fp_ctrl.ldst connect dispatcher.io.ren_uops[1].bits.op2_sel, dis_uops[1].op2_sel connect dispatcher.io.ren_uops[1].bits.op1_sel, dis_uops[1].op1_sel connect dispatcher.io.ren_uops[1].bits.imm_packed, dis_uops[1].imm_packed connect dispatcher.io.ren_uops[1].bits.pimm, dis_uops[1].pimm connect dispatcher.io.ren_uops[1].bits.imm_sel, dis_uops[1].imm_sel connect dispatcher.io.ren_uops[1].bits.imm_rename, dis_uops[1].imm_rename connect dispatcher.io.ren_uops[1].bits.taken, dis_uops[1].taken connect dispatcher.io.ren_uops[1].bits.pc_lob, dis_uops[1].pc_lob connect dispatcher.io.ren_uops[1].bits.edge_inst, dis_uops[1].edge_inst connect dispatcher.io.ren_uops[1].bits.ftq_idx, dis_uops[1].ftq_idx connect dispatcher.io.ren_uops[1].bits.is_mov, dis_uops[1].is_mov connect dispatcher.io.ren_uops[1].bits.is_rocc, dis_uops[1].is_rocc connect dispatcher.io.ren_uops[1].bits.is_sys_pc2epc, dis_uops[1].is_sys_pc2epc connect dispatcher.io.ren_uops[1].bits.is_eret, dis_uops[1].is_eret connect dispatcher.io.ren_uops[1].bits.is_amo, dis_uops[1].is_amo connect dispatcher.io.ren_uops[1].bits.is_sfence, dis_uops[1].is_sfence connect dispatcher.io.ren_uops[1].bits.is_fencei, dis_uops[1].is_fencei connect dispatcher.io.ren_uops[1].bits.is_fence, dis_uops[1].is_fence connect dispatcher.io.ren_uops[1].bits.is_sfb, dis_uops[1].is_sfb connect dispatcher.io.ren_uops[1].bits.br_type, dis_uops[1].br_type connect dispatcher.io.ren_uops[1].bits.br_tag, dis_uops[1].br_tag connect dispatcher.io.ren_uops[1].bits.br_mask, dis_uops[1].br_mask connect dispatcher.io.ren_uops[1].bits.dis_col_sel, dis_uops[1].dis_col_sel connect dispatcher.io.ren_uops[1].bits.iw_p3_bypass_hint, dis_uops[1].iw_p3_bypass_hint connect dispatcher.io.ren_uops[1].bits.iw_p2_bypass_hint, dis_uops[1].iw_p2_bypass_hint connect dispatcher.io.ren_uops[1].bits.iw_p1_bypass_hint, dis_uops[1].iw_p1_bypass_hint connect dispatcher.io.ren_uops[1].bits.iw_p2_speculative_child, dis_uops[1].iw_p2_speculative_child connect dispatcher.io.ren_uops[1].bits.iw_p1_speculative_child, dis_uops[1].iw_p1_speculative_child connect dispatcher.io.ren_uops[1].bits.iw_issued_partial_dgen, dis_uops[1].iw_issued_partial_dgen connect dispatcher.io.ren_uops[1].bits.iw_issued_partial_agen, dis_uops[1].iw_issued_partial_agen connect dispatcher.io.ren_uops[1].bits.iw_issued, dis_uops[1].iw_issued connect dispatcher.io.ren_uops[1].bits.fu_code[0], dis_uops[1].fu_code[0] connect dispatcher.io.ren_uops[1].bits.fu_code[1], dis_uops[1].fu_code[1] connect dispatcher.io.ren_uops[1].bits.fu_code[2], dis_uops[1].fu_code[2] connect dispatcher.io.ren_uops[1].bits.fu_code[3], dis_uops[1].fu_code[3] connect dispatcher.io.ren_uops[1].bits.fu_code[4], dis_uops[1].fu_code[4] connect dispatcher.io.ren_uops[1].bits.fu_code[5], dis_uops[1].fu_code[5] connect dispatcher.io.ren_uops[1].bits.fu_code[6], dis_uops[1].fu_code[6] connect dispatcher.io.ren_uops[1].bits.fu_code[7], dis_uops[1].fu_code[7] connect dispatcher.io.ren_uops[1].bits.fu_code[8], dis_uops[1].fu_code[8] connect dispatcher.io.ren_uops[1].bits.fu_code[9], dis_uops[1].fu_code[9] connect dispatcher.io.ren_uops[1].bits.iq_type[0], dis_uops[1].iq_type[0] connect dispatcher.io.ren_uops[1].bits.iq_type[1], dis_uops[1].iq_type[1] connect dispatcher.io.ren_uops[1].bits.iq_type[2], dis_uops[1].iq_type[2] connect dispatcher.io.ren_uops[1].bits.iq_type[3], dis_uops[1].iq_type[3] connect dispatcher.io.ren_uops[1].bits.debug_pc, dis_uops[1].debug_pc connect dispatcher.io.ren_uops[1].bits.is_rvc, dis_uops[1].is_rvc connect dispatcher.io.ren_uops[1].bits.debug_inst, dis_uops[1].debug_inst connect dispatcher.io.ren_uops[1].bits.inst, dis_uops[1].inst connect mem_iss_unit.io.dis_uops[0], dispatcher.io.dis_uops.`0`[0] connect mem_iss_unit.io.dis_uops[1], dispatcher.io.dis_uops.`0`[1] connect unq_iss_unit.io.dis_uops[0], dispatcher.io.dis_uops.`1`[0] connect unq_iss_unit.io.dis_uops[1], dispatcher.io.dis_uops.`1`[1] connect alu_iss_unit.io.dis_uops[0], dispatcher.io.dis_uops.`2`[0] connect alu_iss_unit.io.dis_uops[1], dispatcher.io.dis_uops.`2`[1] connect fp_pipeline.io.dis_uops[0], dispatcher.io.dis_uops.`3`[0] connect fp_pipeline.io.dis_uops[1], dispatcher.io.dis_uops.`3`[1] reg uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect uop, dis_uops[0] reg immregfile_io_write_ports_0_valid_REG : UInt<1>, clock connect immregfile_io_write_ports_0_valid_REG, dis_fire[0] node _immregfile_io_write_ports_0_valid_T = eq(uop.imm_sel, UInt<3>(0h6)) node _immregfile_io_write_ports_0_valid_T_1 = eq(uop.imm_sel, UInt<3>(0h5)) node _immregfile_io_write_ports_0_valid_T_2 = or(_immregfile_io_write_ports_0_valid_T, _immregfile_io_write_ports_0_valid_T_1) node _immregfile_io_write_ports_0_valid_T_3 = eq(_immregfile_io_write_ports_0_valid_T_2, UInt<1>(0h0)) node _immregfile_io_write_ports_0_valid_T_4 = and(immregfile_io_write_ports_0_valid_REG, _immregfile_io_write_ports_0_valid_T_3) connect immregfile.io.write_ports[0].valid, _immregfile_io_write_ports_0_valid_T_4 connect immregfile.io.write_ports[0].bits.addr, uop.pimm connect immregfile.io.write_ports[0].bits.data, uop.imm_packed reg bregfile_io_write_ports_0_valid_REG : UInt<1>, clock connect bregfile_io_write_ports_0_valid_REG, dis_fire[0] node _bregfile_io_write_ports_0_valid_T = eq(uop.br_type, UInt<4>(0h1)) node _bregfile_io_write_ports_0_valid_T_1 = eq(uop.br_type, UInt<4>(0h2)) node _bregfile_io_write_ports_0_valid_T_2 = eq(uop.br_type, UInt<4>(0h3)) node _bregfile_io_write_ports_0_valid_T_3 = eq(uop.br_type, UInt<4>(0h4)) node _bregfile_io_write_ports_0_valid_T_4 = eq(uop.br_type, UInt<4>(0h5)) node _bregfile_io_write_ports_0_valid_T_5 = eq(uop.br_type, UInt<4>(0h6)) node _bregfile_io_write_ports_0_valid_T_6 = or(_bregfile_io_write_ports_0_valid_T, _bregfile_io_write_ports_0_valid_T_1) node _bregfile_io_write_ports_0_valid_T_7 = or(_bregfile_io_write_ports_0_valid_T_6, _bregfile_io_write_ports_0_valid_T_2) node _bregfile_io_write_ports_0_valid_T_8 = or(_bregfile_io_write_ports_0_valid_T_7, _bregfile_io_write_ports_0_valid_T_3) node _bregfile_io_write_ports_0_valid_T_9 = or(_bregfile_io_write_ports_0_valid_T_8, _bregfile_io_write_ports_0_valid_T_4) node _bregfile_io_write_ports_0_valid_T_10 = or(_bregfile_io_write_ports_0_valid_T_9, _bregfile_io_write_ports_0_valid_T_5) node _bregfile_io_write_ports_0_valid_T_11 = eq(uop.is_sfb, UInt<1>(0h0)) node _bregfile_io_write_ports_0_valid_T_12 = and(_bregfile_io_write_ports_0_valid_T_10, _bregfile_io_write_ports_0_valid_T_11) node _bregfile_io_write_ports_0_valid_T_13 = eq(uop.br_type, UInt<4>(0h8)) node _bregfile_io_write_ports_0_valid_T_14 = or(_bregfile_io_write_ports_0_valid_T_12, _bregfile_io_write_ports_0_valid_T_13) node _bregfile_io_write_ports_0_valid_T_15 = and(bregfile_io_write_ports_0_valid_REG, _bregfile_io_write_ports_0_valid_T_14) connect bregfile.io.write_ports[0].valid, _bregfile_io_write_ports_0_valid_T_15 connect bregfile.io.write_ports[0].bits.addr, uop.br_tag connect bregfile.io.write_ports[0].bits.data.ldq_idx, uop.ldq_idx connect bregfile.io.write_ports[0].bits.data.stq_idx, uop.stq_idx connect bregfile.io.write_ports[0].bits.data.rxq_idx, uop.rxq_idx reg uop_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, clock connect uop_1, dis_uops[1] reg immregfile_io_write_ports_1_valid_REG : UInt<1>, clock connect immregfile_io_write_ports_1_valid_REG, dis_fire[1] node _immregfile_io_write_ports_1_valid_T = eq(uop_1.imm_sel, UInt<3>(0h6)) node _immregfile_io_write_ports_1_valid_T_1 = eq(uop_1.imm_sel, UInt<3>(0h5)) node _immregfile_io_write_ports_1_valid_T_2 = or(_immregfile_io_write_ports_1_valid_T, _immregfile_io_write_ports_1_valid_T_1) node _immregfile_io_write_ports_1_valid_T_3 = eq(_immregfile_io_write_ports_1_valid_T_2, UInt<1>(0h0)) node _immregfile_io_write_ports_1_valid_T_4 = and(immregfile_io_write_ports_1_valid_REG, _immregfile_io_write_ports_1_valid_T_3) connect immregfile.io.write_ports[1].valid, _immregfile_io_write_ports_1_valid_T_4 connect immregfile.io.write_ports[1].bits.addr, uop_1.pimm connect immregfile.io.write_ports[1].bits.data, uop_1.imm_packed reg bregfile_io_write_ports_1_valid_REG : UInt<1>, clock connect bregfile_io_write_ports_1_valid_REG, dis_fire[1] node _bregfile_io_write_ports_1_valid_T = eq(uop_1.br_type, UInt<4>(0h1)) node _bregfile_io_write_ports_1_valid_T_1 = eq(uop_1.br_type, UInt<4>(0h2)) node _bregfile_io_write_ports_1_valid_T_2 = eq(uop_1.br_type, UInt<4>(0h3)) node _bregfile_io_write_ports_1_valid_T_3 = eq(uop_1.br_type, UInt<4>(0h4)) node _bregfile_io_write_ports_1_valid_T_4 = eq(uop_1.br_type, UInt<4>(0h5)) node _bregfile_io_write_ports_1_valid_T_5 = eq(uop_1.br_type, UInt<4>(0h6)) node _bregfile_io_write_ports_1_valid_T_6 = or(_bregfile_io_write_ports_1_valid_T, _bregfile_io_write_ports_1_valid_T_1) node _bregfile_io_write_ports_1_valid_T_7 = or(_bregfile_io_write_ports_1_valid_T_6, _bregfile_io_write_ports_1_valid_T_2) node _bregfile_io_write_ports_1_valid_T_8 = or(_bregfile_io_write_ports_1_valid_T_7, _bregfile_io_write_ports_1_valid_T_3) node _bregfile_io_write_ports_1_valid_T_9 = or(_bregfile_io_write_ports_1_valid_T_8, _bregfile_io_write_ports_1_valid_T_4) node _bregfile_io_write_ports_1_valid_T_10 = or(_bregfile_io_write_ports_1_valid_T_9, _bregfile_io_write_ports_1_valid_T_5) node _bregfile_io_write_ports_1_valid_T_11 = eq(uop_1.is_sfb, UInt<1>(0h0)) node _bregfile_io_write_ports_1_valid_T_12 = and(_bregfile_io_write_ports_1_valid_T_10, _bregfile_io_write_ports_1_valid_T_11) node _bregfile_io_write_ports_1_valid_T_13 = eq(uop_1.br_type, UInt<4>(0h8)) node _bregfile_io_write_ports_1_valid_T_14 = or(_bregfile_io_write_ports_1_valid_T_12, _bregfile_io_write_ports_1_valid_T_13) node _bregfile_io_write_ports_1_valid_T_15 = and(bregfile_io_write_ports_1_valid_REG, _bregfile_io_write_ports_1_valid_T_14) connect bregfile.io.write_ports[1].valid, _bregfile_io_write_ports_1_valid_T_15 connect bregfile.io.write_ports[1].bits.addr, uop_1.br_tag connect bregfile.io.write_ports[1].bits.data.ldq_idx, uop_1.ldq_idx connect bregfile.io.write_ports[1].bits.data.stq_idx, uop_1.stq_idx connect bregfile.io.write_ports[1].bits.data.rxq_idx, uop_1.rxq_idx connect int_wakeups[0], io.lsu.iwakeups[0] reg rob_io_wb_resps_0_REG : UInt<1>, clock connect rob_io_wb_resps_0_REG, rob.io.flush.valid wire rob_io_wb_resps_0_out : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}} connect rob_io_wb_resps_0_out, io.lsu.iresp[0] node _rob_io_wb_resps_0_out_bits_uop_br_mask_T = not(brupdate.b1.resolve_mask) node _rob_io_wb_resps_0_out_bits_uop_br_mask_T_1 = and(io.lsu.iresp[0].bits.uop.br_mask, _rob_io_wb_resps_0_out_bits_uop_br_mask_T) connect rob_io_wb_resps_0_out.bits.uop.br_mask, _rob_io_wb_resps_0_out_bits_uop_br_mask_T_1 node _rob_io_wb_resps_0_out_valid_T = and(brupdate.b1.mispredict_mask, io.lsu.iresp[0].bits.uop.br_mask) node _rob_io_wb_resps_0_out_valid_T_1 = neq(_rob_io_wb_resps_0_out_valid_T, UInt<1>(0h0)) node _rob_io_wb_resps_0_out_valid_T_2 = or(_rob_io_wb_resps_0_out_valid_T_1, rob_io_wb_resps_0_REG) node _rob_io_wb_resps_0_out_valid_T_3 = eq(_rob_io_wb_resps_0_out_valid_T_2, UInt<1>(0h0)) node _rob_io_wb_resps_0_out_valid_T_4 = and(io.lsu.iresp[0].valid, _rob_io_wb_resps_0_out_valid_T_3) connect rob_io_wb_resps_0_out.valid, _rob_io_wb_resps_0_out_valid_T_4 reg rob_io_wb_resps_0_REG_1 : { valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}, clock connect rob_io_wb_resps_0_REG_1, rob_io_wb_resps_0_out connect rob.io.wb_resps[0].bits.fflags.bits, rob_io_wb_resps_0_REG_1.bits.fflags.bits connect rob.io.wb_resps[0].bits.fflags.valid, rob_io_wb_resps_0_REG_1.bits.fflags.valid connect rob.io.wb_resps[0].bits.predicated, rob_io_wb_resps_0_REG_1.bits.predicated connect rob.io.wb_resps[0].bits.data, rob_io_wb_resps_0_REG_1.bits.data connect rob.io.wb_resps[0].bits.uop.debug_tsrc, rob_io_wb_resps_0_REG_1.bits.uop.debug_tsrc connect rob.io.wb_resps[0].bits.uop.debug_fsrc, rob_io_wb_resps_0_REG_1.bits.uop.debug_fsrc connect rob.io.wb_resps[0].bits.uop.bp_xcpt_if, rob_io_wb_resps_0_REG_1.bits.uop.bp_xcpt_if connect rob.io.wb_resps[0].bits.uop.bp_debug_if, rob_io_wb_resps_0_REG_1.bits.uop.bp_debug_if connect rob.io.wb_resps[0].bits.uop.xcpt_ma_if, rob_io_wb_resps_0_REG_1.bits.uop.xcpt_ma_if connect rob.io.wb_resps[0].bits.uop.xcpt_ae_if, rob_io_wb_resps_0_REG_1.bits.uop.xcpt_ae_if connect rob.io.wb_resps[0].bits.uop.xcpt_pf_if, rob_io_wb_resps_0_REG_1.bits.uop.xcpt_pf_if connect rob.io.wb_resps[0].bits.uop.fp_typ, rob_io_wb_resps_0_REG_1.bits.uop.fp_typ connect rob.io.wb_resps[0].bits.uop.fp_rm, rob_io_wb_resps_0_REG_1.bits.uop.fp_rm connect rob.io.wb_resps[0].bits.uop.fp_val, rob_io_wb_resps_0_REG_1.bits.uop.fp_val connect rob.io.wb_resps[0].bits.uop.fcn_op, rob_io_wb_resps_0_REG_1.bits.uop.fcn_op connect rob.io.wb_resps[0].bits.uop.fcn_dw, rob_io_wb_resps_0_REG_1.bits.uop.fcn_dw connect rob.io.wb_resps[0].bits.uop.frs3_en, rob_io_wb_resps_0_REG_1.bits.uop.frs3_en connect rob.io.wb_resps[0].bits.uop.lrs2_rtype, rob_io_wb_resps_0_REG_1.bits.uop.lrs2_rtype connect rob.io.wb_resps[0].bits.uop.lrs1_rtype, rob_io_wb_resps_0_REG_1.bits.uop.lrs1_rtype connect rob.io.wb_resps[0].bits.uop.dst_rtype, rob_io_wb_resps_0_REG_1.bits.uop.dst_rtype connect rob.io.wb_resps[0].bits.uop.lrs3, rob_io_wb_resps_0_REG_1.bits.uop.lrs3 connect rob.io.wb_resps[0].bits.uop.lrs2, rob_io_wb_resps_0_REG_1.bits.uop.lrs2 connect rob.io.wb_resps[0].bits.uop.lrs1, rob_io_wb_resps_0_REG_1.bits.uop.lrs1 connect rob.io.wb_resps[0].bits.uop.ldst, rob_io_wb_resps_0_REG_1.bits.uop.ldst connect rob.io.wb_resps[0].bits.uop.ldst_is_rs1, rob_io_wb_resps_0_REG_1.bits.uop.ldst_is_rs1 connect rob.io.wb_resps[0].bits.uop.csr_cmd, rob_io_wb_resps_0_REG_1.bits.uop.csr_cmd connect rob.io.wb_resps[0].bits.uop.flush_on_commit, rob_io_wb_resps_0_REG_1.bits.uop.flush_on_commit connect rob.io.wb_resps[0].bits.uop.is_unique, rob_io_wb_resps_0_REG_1.bits.uop.is_unique connect rob.io.wb_resps[0].bits.uop.uses_stq, rob_io_wb_resps_0_REG_1.bits.uop.uses_stq connect rob.io.wb_resps[0].bits.uop.uses_ldq, rob_io_wb_resps_0_REG_1.bits.uop.uses_ldq connect rob.io.wb_resps[0].bits.uop.mem_signed, rob_io_wb_resps_0_REG_1.bits.uop.mem_signed connect rob.io.wb_resps[0].bits.uop.mem_size, rob_io_wb_resps_0_REG_1.bits.uop.mem_size connect rob.io.wb_resps[0].bits.uop.mem_cmd, rob_io_wb_resps_0_REG_1.bits.uop.mem_cmd connect rob.io.wb_resps[0].bits.uop.exc_cause, rob_io_wb_resps_0_REG_1.bits.uop.exc_cause connect rob.io.wb_resps[0].bits.uop.exception, rob_io_wb_resps_0_REG_1.bits.uop.exception connect rob.io.wb_resps[0].bits.uop.stale_pdst, rob_io_wb_resps_0_REG_1.bits.uop.stale_pdst connect rob.io.wb_resps[0].bits.uop.ppred_busy, rob_io_wb_resps_0_REG_1.bits.uop.ppred_busy connect rob.io.wb_resps[0].bits.uop.prs3_busy, rob_io_wb_resps_0_REG_1.bits.uop.prs3_busy connect rob.io.wb_resps[0].bits.uop.prs2_busy, rob_io_wb_resps_0_REG_1.bits.uop.prs2_busy connect rob.io.wb_resps[0].bits.uop.prs1_busy, rob_io_wb_resps_0_REG_1.bits.uop.prs1_busy connect rob.io.wb_resps[0].bits.uop.ppred, rob_io_wb_resps_0_REG_1.bits.uop.ppred connect rob.io.wb_resps[0].bits.uop.prs3, rob_io_wb_resps_0_REG_1.bits.uop.prs3 connect rob.io.wb_resps[0].bits.uop.prs2, rob_io_wb_resps_0_REG_1.bits.uop.prs2 connect rob.io.wb_resps[0].bits.uop.prs1, rob_io_wb_resps_0_REG_1.bits.uop.prs1 connect rob.io.wb_resps[0].bits.uop.pdst, rob_io_wb_resps_0_REG_1.bits.uop.pdst connect rob.io.wb_resps[0].bits.uop.rxq_idx, rob_io_wb_resps_0_REG_1.bits.uop.rxq_idx connect rob.io.wb_resps[0].bits.uop.stq_idx, rob_io_wb_resps_0_REG_1.bits.uop.stq_idx connect rob.io.wb_resps[0].bits.uop.ldq_idx, rob_io_wb_resps_0_REG_1.bits.uop.ldq_idx connect rob.io.wb_resps[0].bits.uop.rob_idx, rob_io_wb_resps_0_REG_1.bits.uop.rob_idx connect rob.io.wb_resps[0].bits.uop.fp_ctrl.vec, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.vec connect rob.io.wb_resps[0].bits.uop.fp_ctrl.wflags, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.wflags connect rob.io.wb_resps[0].bits.uop.fp_ctrl.sqrt, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.sqrt connect rob.io.wb_resps[0].bits.uop.fp_ctrl.div, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.div connect rob.io.wb_resps[0].bits.uop.fp_ctrl.fma, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.fma connect rob.io.wb_resps[0].bits.uop.fp_ctrl.fastpipe, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.fastpipe connect rob.io.wb_resps[0].bits.uop.fp_ctrl.toint, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.toint connect rob.io.wb_resps[0].bits.uop.fp_ctrl.fromint, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.fromint connect rob.io.wb_resps[0].bits.uop.fp_ctrl.typeTagOut, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.typeTagOut connect rob.io.wb_resps[0].bits.uop.fp_ctrl.typeTagIn, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.typeTagIn connect rob.io.wb_resps[0].bits.uop.fp_ctrl.swap23, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.swap23 connect rob.io.wb_resps[0].bits.uop.fp_ctrl.swap12, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.swap12 connect rob.io.wb_resps[0].bits.uop.fp_ctrl.ren3, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.ren3 connect rob.io.wb_resps[0].bits.uop.fp_ctrl.ren2, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.ren2 connect rob.io.wb_resps[0].bits.uop.fp_ctrl.ren1, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.ren1 connect rob.io.wb_resps[0].bits.uop.fp_ctrl.wen, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.wen connect rob.io.wb_resps[0].bits.uop.fp_ctrl.ldst, rob_io_wb_resps_0_REG_1.bits.uop.fp_ctrl.ldst connect rob.io.wb_resps[0].bits.uop.op2_sel, rob_io_wb_resps_0_REG_1.bits.uop.op2_sel connect rob.io.wb_resps[0].bits.uop.op1_sel, rob_io_wb_resps_0_REG_1.bits.uop.op1_sel connect rob.io.wb_resps[0].bits.uop.imm_packed, rob_io_wb_resps_0_REG_1.bits.uop.imm_packed connect rob.io.wb_resps[0].bits.uop.pimm, rob_io_wb_resps_0_REG_1.bits.uop.pimm connect rob.io.wb_resps[0].bits.uop.imm_sel, rob_io_wb_resps_0_REG_1.bits.uop.imm_sel connect rob.io.wb_resps[0].bits.uop.imm_rename, rob_io_wb_resps_0_REG_1.bits.uop.imm_rename connect rob.io.wb_resps[0].bits.uop.taken, rob_io_wb_resps_0_REG_1.bits.uop.taken connect rob.io.wb_resps[0].bits.uop.pc_lob, rob_io_wb_resps_0_REG_1.bits.uop.pc_lob connect rob.io.wb_resps[0].bits.uop.edge_inst, rob_io_wb_resps_0_REG_1.bits.uop.edge_inst connect rob.io.wb_resps[0].bits.uop.ftq_idx, rob_io_wb_resps_0_REG_1.bits.uop.ftq_idx connect rob.io.wb_resps[0].bits.uop.is_mov, rob_io_wb_resps_0_REG_1.bits.uop.is_mov connect rob.io.wb_resps[0].bits.uop.is_rocc, rob_io_wb_resps_0_REG_1.bits.uop.is_rocc connect rob.io.wb_resps[0].bits.uop.is_sys_pc2epc, rob_io_wb_resps_0_REG_1.bits.uop.is_sys_pc2epc connect rob.io.wb_resps[0].bits.uop.is_eret, rob_io_wb_resps_0_REG_1.bits.uop.is_eret connect rob.io.wb_resps[0].bits.uop.is_amo, rob_io_wb_resps_0_REG_1.bits.uop.is_amo connect rob.io.wb_resps[0].bits.uop.is_sfence, rob_io_wb_resps_0_REG_1.bits.uop.is_sfence connect rob.io.wb_resps[0].bits.uop.is_fencei, rob_io_wb_resps_0_REG_1.bits.uop.is_fencei connect rob.io.wb_resps[0].bits.uop.is_fence, rob_io_wb_resps_0_REG_1.bits.uop.is_fence connect rob.io.wb_resps[0].bits.uop.is_sfb, rob_io_wb_resps_0_REG_1.bits.uop.is_sfb connect rob.io.wb_resps[0].bits.uop.br_type, rob_io_wb_resps_0_REG_1.bits.uop.br_type connect rob.io.wb_resps[0].bits.uop.br_tag, rob_io_wb_resps_0_REG_1.bits.uop.br_tag connect rob.io.wb_resps[0].bits.uop.br_mask, rob_io_wb_resps_0_REG_1.bits.uop.br_mask connect rob.io.wb_resps[0].bits.uop.dis_col_sel, rob_io_wb_resps_0_REG_1.bits.uop.dis_col_sel connect rob.io.wb_resps[0].bits.uop.iw_p3_bypass_hint, rob_io_wb_resps_0_REG_1.bits.uop.iw_p3_bypass_hint connect rob.io.wb_resps[0].bits.uop.iw_p2_bypass_hint, rob_io_wb_resps_0_REG_1.bits.uop.iw_p2_bypass_hint connect rob.io.wb_resps[0].bits.uop.iw_p1_bypass_hint, rob_io_wb_resps_0_REG_1.bits.uop.iw_p1_bypass_hint connect rob.io.wb_resps[0].bits.uop.iw_p2_speculative_child, rob_io_wb_resps_0_REG_1.bits.uop.iw_p2_speculative_child connect rob.io.wb_resps[0].bits.uop.iw_p1_speculative_child, rob_io_wb_resps_0_REG_1.bits.uop.iw_p1_speculative_child connect rob.io.wb_resps[0].bits.uop.iw_issued_partial_dgen, rob_io_wb_resps_0_REG_1.bits.uop.iw_issued_partial_dgen connect rob.io.wb_resps[0].bits.uop.iw_issued_partial_agen, rob_io_wb_resps_0_REG_1.bits.uop.iw_issued_partial_agen connect rob.io.wb_resps[0].bits.uop.iw_issued, rob_io_wb_resps_0_REG_1.bits.uop.iw_issued connect rob.io.wb_resps[0].bits.uop.fu_code[0], rob_io_wb_resps_0_REG_1.bits.uop.fu_code[0] connect rob.io.wb_resps[0].bits.uop.fu_code[1], rob_io_wb_resps_0_REG_1.bits.uop.fu_code[1] connect rob.io.wb_resps[0].bits.uop.fu_code[2], rob_io_wb_resps_0_REG_1.bits.uop.fu_code[2] connect rob.io.wb_resps[0].bits.uop.fu_code[3], rob_io_wb_resps_0_REG_1.bits.uop.fu_code[3] connect rob.io.wb_resps[0].bits.uop.fu_code[4], rob_io_wb_resps_0_REG_1.bits.uop.fu_code[4] connect rob.io.wb_resps[0].bits.uop.fu_code[5], rob_io_wb_resps_0_REG_1.bits.uop.fu_code[5] connect rob.io.wb_resps[0].bits.uop.fu_code[6], rob_io_wb_resps_0_REG_1.bits.uop.fu_code[6] connect rob.io.wb_resps[0].bits.uop.fu_code[7], rob_io_wb_resps_0_REG_1.bits.uop.fu_code[7] connect rob.io.wb_resps[0].bits.uop.fu_code[8], rob_io_wb_resps_0_REG_1.bits.uop.fu_code[8] connect rob.io.wb_resps[0].bits.uop.fu_code[9], rob_io_wb_resps_0_REG_1.bits.uop.fu_code[9] connect rob.io.wb_resps[0].bits.uop.iq_type[0], rob_io_wb_resps_0_REG_1.bits.uop.iq_type[0] connect rob.io.wb_resps[0].bits.uop.iq_type[1], rob_io_wb_resps_0_REG_1.bits.uop.iq_type[1] connect rob.io.wb_resps[0].bits.uop.iq_type[2], rob_io_wb_resps_0_REG_1.bits.uop.iq_type[2] connect rob.io.wb_resps[0].bits.uop.iq_type[3], rob_io_wb_resps_0_REG_1.bits.uop.iq_type[3] connect rob.io.wb_resps[0].bits.uop.debug_pc, rob_io_wb_resps_0_REG_1.bits.uop.debug_pc connect rob.io.wb_resps[0].bits.uop.is_rvc, rob_io_wb_resps_0_REG_1.bits.uop.is_rvc connect rob.io.wb_resps[0].bits.uop.debug_inst, rob_io_wb_resps_0_REG_1.bits.uop.debug_inst connect rob.io.wb_resps[0].bits.uop.inst, rob_io_wb_resps_0_REG_1.bits.uop.inst connect rob.io.wb_resps[0].valid, rob_io_wb_resps_0_REG_1.valid reg iregfile_io_write_ports_0_valid_REG : UInt<1>, clock connect iregfile_io_write_ports_0_valid_REG, io.lsu.iresp[0].valid connect iregfile.io.write_ports[0].valid, iregfile_io_write_ports_0_valid_REG reg iregfile_io_write_ports_0_bits_addr_REG : UInt, clock connect iregfile_io_write_ports_0_bits_addr_REG, io.lsu.iresp[0].bits.uop.pdst connect iregfile.io.write_ports[0].bits.addr, iregfile_io_write_ports_0_bits_addr_REG reg iregfile_io_write_ports_0_bits_data_REG : UInt, clock connect iregfile_io_write_ports_0_bits_data_REG, io.lsu.iresp[0].bits.data connect iregfile.io.write_ports[0].bits.data, iregfile_io_write_ports_0_bits_data_REG reg int_bypasses_0_valid_REG : UInt<1>, clock connect int_bypasses_0_valid_REG, io.lsu.iresp[0].valid connect int_bypasses[0].valid, int_bypasses_0_valid_REG reg int_bypasses_0_bits_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}, clock connect int_bypasses_0_bits_REG, io.lsu.iresp[0].bits connect int_bypasses[0].bits, int_bypasses_0_bits_REG inst ll_arb of Arbiter4_ExeUnitResp connect ll_arb.clock, clock connect ll_arb.reset, reset connect ll_arb.io.in[0].valid, unique_exe_unit_0.io_mul_resp.valid connect ll_arb.io.in[0].bits.fflags.bits, unique_exe_unit_0.io_mul_resp.bits.fflags.bits connect ll_arb.io.in[0].bits.fflags.valid, unique_exe_unit_0.io_mul_resp.bits.fflags.valid connect ll_arb.io.in[0].bits.predicated, unique_exe_unit_0.io_mul_resp.bits.predicated connect ll_arb.io.in[0].bits.data, unique_exe_unit_0.io_mul_resp.bits.data connect ll_arb.io.in[0].bits.uop.debug_tsrc, unique_exe_unit_0.io_mul_resp.bits.uop.debug_tsrc connect ll_arb.io.in[0].bits.uop.debug_fsrc, unique_exe_unit_0.io_mul_resp.bits.uop.debug_fsrc connect ll_arb.io.in[0].bits.uop.bp_xcpt_if, unique_exe_unit_0.io_mul_resp.bits.uop.bp_xcpt_if connect ll_arb.io.in[0].bits.uop.bp_debug_if, unique_exe_unit_0.io_mul_resp.bits.uop.bp_debug_if connect ll_arb.io.in[0].bits.uop.xcpt_ma_if, unique_exe_unit_0.io_mul_resp.bits.uop.xcpt_ma_if connect ll_arb.io.in[0].bits.uop.xcpt_ae_if, unique_exe_unit_0.io_mul_resp.bits.uop.xcpt_ae_if connect ll_arb.io.in[0].bits.uop.xcpt_pf_if, unique_exe_unit_0.io_mul_resp.bits.uop.xcpt_pf_if connect ll_arb.io.in[0].bits.uop.fp_typ, unique_exe_unit_0.io_mul_resp.bits.uop.fp_typ connect ll_arb.io.in[0].bits.uop.fp_rm, unique_exe_unit_0.io_mul_resp.bits.uop.fp_rm connect ll_arb.io.in[0].bits.uop.fp_val, unique_exe_unit_0.io_mul_resp.bits.uop.fp_val connect ll_arb.io.in[0].bits.uop.fcn_op, unique_exe_unit_0.io_mul_resp.bits.uop.fcn_op connect ll_arb.io.in[0].bits.uop.fcn_dw, unique_exe_unit_0.io_mul_resp.bits.uop.fcn_dw connect ll_arb.io.in[0].bits.uop.frs3_en, unique_exe_unit_0.io_mul_resp.bits.uop.frs3_en connect ll_arb.io.in[0].bits.uop.lrs2_rtype, unique_exe_unit_0.io_mul_resp.bits.uop.lrs2_rtype connect ll_arb.io.in[0].bits.uop.lrs1_rtype, unique_exe_unit_0.io_mul_resp.bits.uop.lrs1_rtype connect ll_arb.io.in[0].bits.uop.dst_rtype, unique_exe_unit_0.io_mul_resp.bits.uop.dst_rtype connect ll_arb.io.in[0].bits.uop.lrs3, unique_exe_unit_0.io_mul_resp.bits.uop.lrs3 connect ll_arb.io.in[0].bits.uop.lrs2, unique_exe_unit_0.io_mul_resp.bits.uop.lrs2 connect ll_arb.io.in[0].bits.uop.lrs1, unique_exe_unit_0.io_mul_resp.bits.uop.lrs1 connect ll_arb.io.in[0].bits.uop.ldst, unique_exe_unit_0.io_mul_resp.bits.uop.ldst connect ll_arb.io.in[0].bits.uop.ldst_is_rs1, unique_exe_unit_0.io_mul_resp.bits.uop.ldst_is_rs1 connect ll_arb.io.in[0].bits.uop.csr_cmd, unique_exe_unit_0.io_mul_resp.bits.uop.csr_cmd connect ll_arb.io.in[0].bits.uop.flush_on_commit, unique_exe_unit_0.io_mul_resp.bits.uop.flush_on_commit connect ll_arb.io.in[0].bits.uop.is_unique, unique_exe_unit_0.io_mul_resp.bits.uop.is_unique connect ll_arb.io.in[0].bits.uop.uses_stq, unique_exe_unit_0.io_mul_resp.bits.uop.uses_stq connect ll_arb.io.in[0].bits.uop.uses_ldq, unique_exe_unit_0.io_mul_resp.bits.uop.uses_ldq connect ll_arb.io.in[0].bits.uop.mem_signed, unique_exe_unit_0.io_mul_resp.bits.uop.mem_signed connect ll_arb.io.in[0].bits.uop.mem_size, unique_exe_unit_0.io_mul_resp.bits.uop.mem_size connect ll_arb.io.in[0].bits.uop.mem_cmd, unique_exe_unit_0.io_mul_resp.bits.uop.mem_cmd connect ll_arb.io.in[0].bits.uop.exc_cause, unique_exe_unit_0.io_mul_resp.bits.uop.exc_cause connect ll_arb.io.in[0].bits.uop.exception, unique_exe_unit_0.io_mul_resp.bits.uop.exception connect ll_arb.io.in[0].bits.uop.stale_pdst, unique_exe_unit_0.io_mul_resp.bits.uop.stale_pdst connect ll_arb.io.in[0].bits.uop.ppred_busy, unique_exe_unit_0.io_mul_resp.bits.uop.ppred_busy connect ll_arb.io.in[0].bits.uop.prs3_busy, unique_exe_unit_0.io_mul_resp.bits.uop.prs3_busy connect ll_arb.io.in[0].bits.uop.prs2_busy, unique_exe_unit_0.io_mul_resp.bits.uop.prs2_busy connect ll_arb.io.in[0].bits.uop.prs1_busy, unique_exe_unit_0.io_mul_resp.bits.uop.prs1_busy connect ll_arb.io.in[0].bits.uop.ppred, unique_exe_unit_0.io_mul_resp.bits.uop.ppred connect ll_arb.io.in[0].bits.uop.prs3, unique_exe_unit_0.io_mul_resp.bits.uop.prs3 connect ll_arb.io.in[0].bits.uop.prs2, unique_exe_unit_0.io_mul_resp.bits.uop.prs2 connect ll_arb.io.in[0].bits.uop.prs1, unique_exe_unit_0.io_mul_resp.bits.uop.prs1 connect ll_arb.io.in[0].bits.uop.pdst, unique_exe_unit_0.io_mul_resp.bits.uop.pdst connect ll_arb.io.in[0].bits.uop.rxq_idx, unique_exe_unit_0.io_mul_resp.bits.uop.rxq_idx connect ll_arb.io.in[0].bits.uop.stq_idx, unique_exe_unit_0.io_mul_resp.bits.uop.stq_idx connect ll_arb.io.in[0].bits.uop.ldq_idx, unique_exe_unit_0.io_mul_resp.bits.uop.ldq_idx connect ll_arb.io.in[0].bits.uop.rob_idx, unique_exe_unit_0.io_mul_resp.bits.uop.rob_idx connect ll_arb.io.in[0].bits.uop.fp_ctrl.vec, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.vec connect ll_arb.io.in[0].bits.uop.fp_ctrl.wflags, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.wflags connect ll_arb.io.in[0].bits.uop.fp_ctrl.sqrt, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.sqrt connect ll_arb.io.in[0].bits.uop.fp_ctrl.div, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.div connect ll_arb.io.in[0].bits.uop.fp_ctrl.fma, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.fma connect ll_arb.io.in[0].bits.uop.fp_ctrl.fastpipe, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.fastpipe connect ll_arb.io.in[0].bits.uop.fp_ctrl.toint, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.toint connect ll_arb.io.in[0].bits.uop.fp_ctrl.fromint, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.fromint connect ll_arb.io.in[0].bits.uop.fp_ctrl.typeTagOut, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.typeTagOut connect ll_arb.io.in[0].bits.uop.fp_ctrl.typeTagIn, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.typeTagIn connect ll_arb.io.in[0].bits.uop.fp_ctrl.swap23, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.swap23 connect ll_arb.io.in[0].bits.uop.fp_ctrl.swap12, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.swap12 connect ll_arb.io.in[0].bits.uop.fp_ctrl.ren3, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.ren3 connect ll_arb.io.in[0].bits.uop.fp_ctrl.ren2, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.ren2 connect ll_arb.io.in[0].bits.uop.fp_ctrl.ren1, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.ren1 connect ll_arb.io.in[0].bits.uop.fp_ctrl.wen, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.wen connect ll_arb.io.in[0].bits.uop.fp_ctrl.ldst, unique_exe_unit_0.io_mul_resp.bits.uop.fp_ctrl.ldst connect ll_arb.io.in[0].bits.uop.op2_sel, unique_exe_unit_0.io_mul_resp.bits.uop.op2_sel connect ll_arb.io.in[0].bits.uop.op1_sel, unique_exe_unit_0.io_mul_resp.bits.uop.op1_sel connect ll_arb.io.in[0].bits.uop.imm_packed, unique_exe_unit_0.io_mul_resp.bits.uop.imm_packed connect ll_arb.io.in[0].bits.uop.pimm, unique_exe_unit_0.io_mul_resp.bits.uop.pimm connect ll_arb.io.in[0].bits.uop.imm_sel, unique_exe_unit_0.io_mul_resp.bits.uop.imm_sel connect ll_arb.io.in[0].bits.uop.imm_rename, unique_exe_unit_0.io_mul_resp.bits.uop.imm_rename connect ll_arb.io.in[0].bits.uop.taken, unique_exe_unit_0.io_mul_resp.bits.uop.taken connect ll_arb.io.in[0].bits.uop.pc_lob, unique_exe_unit_0.io_mul_resp.bits.uop.pc_lob connect ll_arb.io.in[0].bits.uop.edge_inst, unique_exe_unit_0.io_mul_resp.bits.uop.edge_inst connect ll_arb.io.in[0].bits.uop.ftq_idx, unique_exe_unit_0.io_mul_resp.bits.uop.ftq_idx connect ll_arb.io.in[0].bits.uop.is_mov, unique_exe_unit_0.io_mul_resp.bits.uop.is_mov connect ll_arb.io.in[0].bits.uop.is_rocc, unique_exe_unit_0.io_mul_resp.bits.uop.is_rocc connect ll_arb.io.in[0].bits.uop.is_sys_pc2epc, unique_exe_unit_0.io_mul_resp.bits.uop.is_sys_pc2epc connect ll_arb.io.in[0].bits.uop.is_eret, unique_exe_unit_0.io_mul_resp.bits.uop.is_eret connect ll_arb.io.in[0].bits.uop.is_amo, unique_exe_unit_0.io_mul_resp.bits.uop.is_amo connect ll_arb.io.in[0].bits.uop.is_sfence, unique_exe_unit_0.io_mul_resp.bits.uop.is_sfence connect ll_arb.io.in[0].bits.uop.is_fencei, unique_exe_unit_0.io_mul_resp.bits.uop.is_fencei connect ll_arb.io.in[0].bits.uop.is_fence, unique_exe_unit_0.io_mul_resp.bits.uop.is_fence connect ll_arb.io.in[0].bits.uop.is_sfb, unique_exe_unit_0.io_mul_resp.bits.uop.is_sfb connect ll_arb.io.in[0].bits.uop.br_type, unique_exe_unit_0.io_mul_resp.bits.uop.br_type connect ll_arb.io.in[0].bits.uop.br_tag, unique_exe_unit_0.io_mul_resp.bits.uop.br_tag connect ll_arb.io.in[0].bits.uop.br_mask, unique_exe_unit_0.io_mul_resp.bits.uop.br_mask connect ll_arb.io.in[0].bits.uop.dis_col_sel, unique_exe_unit_0.io_mul_resp.bits.uop.dis_col_sel connect ll_arb.io.in[0].bits.uop.iw_p3_bypass_hint, unique_exe_unit_0.io_mul_resp.bits.uop.iw_p3_bypass_hint connect ll_arb.io.in[0].bits.uop.iw_p2_bypass_hint, unique_exe_unit_0.io_mul_resp.bits.uop.iw_p2_bypass_hint connect ll_arb.io.in[0].bits.uop.iw_p1_bypass_hint, unique_exe_unit_0.io_mul_resp.bits.uop.iw_p1_bypass_hint connect ll_arb.io.in[0].bits.uop.iw_p2_speculative_child, unique_exe_unit_0.io_mul_resp.bits.uop.iw_p2_speculative_child connect ll_arb.io.in[0].bits.uop.iw_p1_speculative_child, unique_exe_unit_0.io_mul_resp.bits.uop.iw_p1_speculative_child connect ll_arb.io.in[0].bits.uop.iw_issued_partial_dgen, unique_exe_unit_0.io_mul_resp.bits.uop.iw_issued_partial_dgen connect ll_arb.io.in[0].bits.uop.iw_issued_partial_agen, unique_exe_unit_0.io_mul_resp.bits.uop.iw_issued_partial_agen connect ll_arb.io.in[0].bits.uop.iw_issued, unique_exe_unit_0.io_mul_resp.bits.uop.iw_issued connect ll_arb.io.in[0].bits.uop.fu_code[0], unique_exe_unit_0.io_mul_resp.bits.uop.fu_code[0] connect ll_arb.io.in[0].bits.uop.fu_code[1], unique_exe_unit_0.io_mul_resp.bits.uop.fu_code[1] connect ll_arb.io.in[0].bits.uop.fu_code[2], unique_exe_unit_0.io_mul_resp.bits.uop.fu_code[2] connect ll_arb.io.in[0].bits.uop.fu_code[3], unique_exe_unit_0.io_mul_resp.bits.uop.fu_code[3] connect ll_arb.io.in[0].bits.uop.fu_code[4], unique_exe_unit_0.io_mul_resp.bits.uop.fu_code[4] connect ll_arb.io.in[0].bits.uop.fu_code[5], unique_exe_unit_0.io_mul_resp.bits.uop.fu_code[5] connect ll_arb.io.in[0].bits.uop.fu_code[6], unique_exe_unit_0.io_mul_resp.bits.uop.fu_code[6] connect ll_arb.io.in[0].bits.uop.fu_code[7], unique_exe_unit_0.io_mul_resp.bits.uop.fu_code[7] connect ll_arb.io.in[0].bits.uop.fu_code[8], unique_exe_unit_0.io_mul_resp.bits.uop.fu_code[8] connect ll_arb.io.in[0].bits.uop.fu_code[9], unique_exe_unit_0.io_mul_resp.bits.uop.fu_code[9] connect ll_arb.io.in[0].bits.uop.iq_type[0], unique_exe_unit_0.io_mul_resp.bits.uop.iq_type[0] connect ll_arb.io.in[0].bits.uop.iq_type[1], unique_exe_unit_0.io_mul_resp.bits.uop.iq_type[1] connect ll_arb.io.in[0].bits.uop.iq_type[2], unique_exe_unit_0.io_mul_resp.bits.uop.iq_type[2] connect ll_arb.io.in[0].bits.uop.iq_type[3], unique_exe_unit_0.io_mul_resp.bits.uop.iq_type[3] connect ll_arb.io.in[0].bits.uop.debug_pc, unique_exe_unit_0.io_mul_resp.bits.uop.debug_pc connect ll_arb.io.in[0].bits.uop.is_rvc, unique_exe_unit_0.io_mul_resp.bits.uop.is_rvc connect ll_arb.io.in[0].bits.uop.debug_inst, unique_exe_unit_0.io_mul_resp.bits.uop.debug_inst connect ll_arb.io.in[0].bits.uop.inst, unique_exe_unit_0.io_mul_resp.bits.uop.inst connect ll_arb.io.in[1], fp_pipeline.io.to_int connect ll_arb.io.in[2], unique_exe_unit_0.io_div_resp connect ll_arb.io.in[3].valid, unique_exe_unit_0.io_csr_resp.valid connect ll_arb.io.in[3].bits.uop.debug_tsrc, unique_exe_unit_0.io_csr_resp.bits.uop.debug_tsrc connect ll_arb.io.in[3].bits.uop.debug_fsrc, unique_exe_unit_0.io_csr_resp.bits.uop.debug_fsrc connect ll_arb.io.in[3].bits.uop.bp_xcpt_if, unique_exe_unit_0.io_csr_resp.bits.uop.bp_xcpt_if connect ll_arb.io.in[3].bits.uop.bp_debug_if, unique_exe_unit_0.io_csr_resp.bits.uop.bp_debug_if connect ll_arb.io.in[3].bits.uop.xcpt_ma_if, unique_exe_unit_0.io_csr_resp.bits.uop.xcpt_ma_if connect ll_arb.io.in[3].bits.uop.xcpt_ae_if, unique_exe_unit_0.io_csr_resp.bits.uop.xcpt_ae_if connect ll_arb.io.in[3].bits.uop.xcpt_pf_if, unique_exe_unit_0.io_csr_resp.bits.uop.xcpt_pf_if connect ll_arb.io.in[3].bits.uop.fp_typ, unique_exe_unit_0.io_csr_resp.bits.uop.fp_typ connect ll_arb.io.in[3].bits.uop.fp_rm, unique_exe_unit_0.io_csr_resp.bits.uop.fp_rm connect ll_arb.io.in[3].bits.uop.fp_val, unique_exe_unit_0.io_csr_resp.bits.uop.fp_val connect ll_arb.io.in[3].bits.uop.fcn_op, unique_exe_unit_0.io_csr_resp.bits.uop.fcn_op connect ll_arb.io.in[3].bits.uop.fcn_dw, unique_exe_unit_0.io_csr_resp.bits.uop.fcn_dw connect ll_arb.io.in[3].bits.uop.frs3_en, unique_exe_unit_0.io_csr_resp.bits.uop.frs3_en connect ll_arb.io.in[3].bits.uop.lrs2_rtype, unique_exe_unit_0.io_csr_resp.bits.uop.lrs2_rtype connect ll_arb.io.in[3].bits.uop.lrs1_rtype, unique_exe_unit_0.io_csr_resp.bits.uop.lrs1_rtype connect ll_arb.io.in[3].bits.uop.dst_rtype, unique_exe_unit_0.io_csr_resp.bits.uop.dst_rtype connect ll_arb.io.in[3].bits.uop.lrs3, unique_exe_unit_0.io_csr_resp.bits.uop.lrs3 connect ll_arb.io.in[3].bits.uop.lrs2, unique_exe_unit_0.io_csr_resp.bits.uop.lrs2 connect ll_arb.io.in[3].bits.uop.lrs1, unique_exe_unit_0.io_csr_resp.bits.uop.lrs1 connect ll_arb.io.in[3].bits.uop.ldst, unique_exe_unit_0.io_csr_resp.bits.uop.ldst connect ll_arb.io.in[3].bits.uop.ldst_is_rs1, unique_exe_unit_0.io_csr_resp.bits.uop.ldst_is_rs1 connect ll_arb.io.in[3].bits.uop.csr_cmd, unique_exe_unit_0.io_csr_resp.bits.uop.csr_cmd connect ll_arb.io.in[3].bits.uop.flush_on_commit, unique_exe_unit_0.io_csr_resp.bits.uop.flush_on_commit connect ll_arb.io.in[3].bits.uop.is_unique, unique_exe_unit_0.io_csr_resp.bits.uop.is_unique connect ll_arb.io.in[3].bits.uop.uses_stq, unique_exe_unit_0.io_csr_resp.bits.uop.uses_stq connect ll_arb.io.in[3].bits.uop.uses_ldq, unique_exe_unit_0.io_csr_resp.bits.uop.uses_ldq connect ll_arb.io.in[3].bits.uop.mem_signed, unique_exe_unit_0.io_csr_resp.bits.uop.mem_signed connect ll_arb.io.in[3].bits.uop.mem_size, unique_exe_unit_0.io_csr_resp.bits.uop.mem_size connect ll_arb.io.in[3].bits.uop.mem_cmd, unique_exe_unit_0.io_csr_resp.bits.uop.mem_cmd connect ll_arb.io.in[3].bits.uop.exc_cause, unique_exe_unit_0.io_csr_resp.bits.uop.exc_cause connect ll_arb.io.in[3].bits.uop.exception, unique_exe_unit_0.io_csr_resp.bits.uop.exception connect ll_arb.io.in[3].bits.uop.stale_pdst, unique_exe_unit_0.io_csr_resp.bits.uop.stale_pdst connect ll_arb.io.in[3].bits.uop.ppred_busy, unique_exe_unit_0.io_csr_resp.bits.uop.ppred_busy connect ll_arb.io.in[3].bits.uop.prs3_busy, unique_exe_unit_0.io_csr_resp.bits.uop.prs3_busy connect ll_arb.io.in[3].bits.uop.prs2_busy, unique_exe_unit_0.io_csr_resp.bits.uop.prs2_busy connect ll_arb.io.in[3].bits.uop.prs1_busy, unique_exe_unit_0.io_csr_resp.bits.uop.prs1_busy connect ll_arb.io.in[3].bits.uop.ppred, unique_exe_unit_0.io_csr_resp.bits.uop.ppred connect ll_arb.io.in[3].bits.uop.prs3, unique_exe_unit_0.io_csr_resp.bits.uop.prs3 connect ll_arb.io.in[3].bits.uop.prs2, unique_exe_unit_0.io_csr_resp.bits.uop.prs2 connect ll_arb.io.in[3].bits.uop.prs1, unique_exe_unit_0.io_csr_resp.bits.uop.prs1 connect ll_arb.io.in[3].bits.uop.pdst, unique_exe_unit_0.io_csr_resp.bits.uop.pdst connect ll_arb.io.in[3].bits.uop.rxq_idx, unique_exe_unit_0.io_csr_resp.bits.uop.rxq_idx connect ll_arb.io.in[3].bits.uop.stq_idx, unique_exe_unit_0.io_csr_resp.bits.uop.stq_idx connect ll_arb.io.in[3].bits.uop.ldq_idx, unique_exe_unit_0.io_csr_resp.bits.uop.ldq_idx connect ll_arb.io.in[3].bits.uop.rob_idx, unique_exe_unit_0.io_csr_resp.bits.uop.rob_idx connect ll_arb.io.in[3].bits.uop.fp_ctrl.vec, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.vec connect ll_arb.io.in[3].bits.uop.fp_ctrl.wflags, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.wflags connect ll_arb.io.in[3].bits.uop.fp_ctrl.sqrt, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.sqrt connect ll_arb.io.in[3].bits.uop.fp_ctrl.div, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.div connect ll_arb.io.in[3].bits.uop.fp_ctrl.fma, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.fma connect ll_arb.io.in[3].bits.uop.fp_ctrl.fastpipe, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.fastpipe connect ll_arb.io.in[3].bits.uop.fp_ctrl.toint, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.toint connect ll_arb.io.in[3].bits.uop.fp_ctrl.fromint, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.fromint connect ll_arb.io.in[3].bits.uop.fp_ctrl.typeTagOut, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.typeTagOut connect ll_arb.io.in[3].bits.uop.fp_ctrl.typeTagIn, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.typeTagIn connect ll_arb.io.in[3].bits.uop.fp_ctrl.swap23, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.swap23 connect ll_arb.io.in[3].bits.uop.fp_ctrl.swap12, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.swap12 connect ll_arb.io.in[3].bits.uop.fp_ctrl.ren3, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.ren3 connect ll_arb.io.in[3].bits.uop.fp_ctrl.ren2, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.ren2 connect ll_arb.io.in[3].bits.uop.fp_ctrl.ren1, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.ren1 connect ll_arb.io.in[3].bits.uop.fp_ctrl.wen, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.wen connect ll_arb.io.in[3].bits.uop.fp_ctrl.ldst, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.ldst connect ll_arb.io.in[3].bits.uop.op2_sel, unique_exe_unit_0.io_csr_resp.bits.uop.op2_sel connect ll_arb.io.in[3].bits.uop.op1_sel, unique_exe_unit_0.io_csr_resp.bits.uop.op1_sel connect ll_arb.io.in[3].bits.uop.imm_packed, unique_exe_unit_0.io_csr_resp.bits.uop.imm_packed connect ll_arb.io.in[3].bits.uop.pimm, unique_exe_unit_0.io_csr_resp.bits.uop.pimm connect ll_arb.io.in[3].bits.uop.imm_sel, unique_exe_unit_0.io_csr_resp.bits.uop.imm_sel connect ll_arb.io.in[3].bits.uop.imm_rename, unique_exe_unit_0.io_csr_resp.bits.uop.imm_rename connect ll_arb.io.in[3].bits.uop.taken, unique_exe_unit_0.io_csr_resp.bits.uop.taken connect ll_arb.io.in[3].bits.uop.pc_lob, unique_exe_unit_0.io_csr_resp.bits.uop.pc_lob connect ll_arb.io.in[3].bits.uop.edge_inst, unique_exe_unit_0.io_csr_resp.bits.uop.edge_inst connect ll_arb.io.in[3].bits.uop.ftq_idx, unique_exe_unit_0.io_csr_resp.bits.uop.ftq_idx connect ll_arb.io.in[3].bits.uop.is_mov, unique_exe_unit_0.io_csr_resp.bits.uop.is_mov connect ll_arb.io.in[3].bits.uop.is_rocc, unique_exe_unit_0.io_csr_resp.bits.uop.is_rocc connect ll_arb.io.in[3].bits.uop.is_sys_pc2epc, unique_exe_unit_0.io_csr_resp.bits.uop.is_sys_pc2epc connect ll_arb.io.in[3].bits.uop.is_eret, unique_exe_unit_0.io_csr_resp.bits.uop.is_eret connect ll_arb.io.in[3].bits.uop.is_amo, unique_exe_unit_0.io_csr_resp.bits.uop.is_amo connect ll_arb.io.in[3].bits.uop.is_sfence, unique_exe_unit_0.io_csr_resp.bits.uop.is_sfence connect ll_arb.io.in[3].bits.uop.is_fencei, unique_exe_unit_0.io_csr_resp.bits.uop.is_fencei connect ll_arb.io.in[3].bits.uop.is_fence, unique_exe_unit_0.io_csr_resp.bits.uop.is_fence connect ll_arb.io.in[3].bits.uop.is_sfb, unique_exe_unit_0.io_csr_resp.bits.uop.is_sfb connect ll_arb.io.in[3].bits.uop.br_type, unique_exe_unit_0.io_csr_resp.bits.uop.br_type connect ll_arb.io.in[3].bits.uop.br_tag, unique_exe_unit_0.io_csr_resp.bits.uop.br_tag connect ll_arb.io.in[3].bits.uop.br_mask, unique_exe_unit_0.io_csr_resp.bits.uop.br_mask connect ll_arb.io.in[3].bits.uop.dis_col_sel, unique_exe_unit_0.io_csr_resp.bits.uop.dis_col_sel connect ll_arb.io.in[3].bits.uop.iw_p3_bypass_hint, unique_exe_unit_0.io_csr_resp.bits.uop.iw_p3_bypass_hint connect ll_arb.io.in[3].bits.uop.iw_p2_bypass_hint, unique_exe_unit_0.io_csr_resp.bits.uop.iw_p2_bypass_hint connect ll_arb.io.in[3].bits.uop.iw_p1_bypass_hint, unique_exe_unit_0.io_csr_resp.bits.uop.iw_p1_bypass_hint connect ll_arb.io.in[3].bits.uop.iw_p2_speculative_child, unique_exe_unit_0.io_csr_resp.bits.uop.iw_p2_speculative_child connect ll_arb.io.in[3].bits.uop.iw_p1_speculative_child, unique_exe_unit_0.io_csr_resp.bits.uop.iw_p1_speculative_child connect ll_arb.io.in[3].bits.uop.iw_issued_partial_dgen, unique_exe_unit_0.io_csr_resp.bits.uop.iw_issued_partial_dgen connect ll_arb.io.in[3].bits.uop.iw_issued_partial_agen, unique_exe_unit_0.io_csr_resp.bits.uop.iw_issued_partial_agen connect ll_arb.io.in[3].bits.uop.iw_issued, unique_exe_unit_0.io_csr_resp.bits.uop.iw_issued connect ll_arb.io.in[3].bits.uop.fu_code[0], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[0] connect ll_arb.io.in[3].bits.uop.fu_code[1], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[1] connect ll_arb.io.in[3].bits.uop.fu_code[2], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[2] connect ll_arb.io.in[3].bits.uop.fu_code[3], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[3] connect ll_arb.io.in[3].bits.uop.fu_code[4], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[4] connect ll_arb.io.in[3].bits.uop.fu_code[5], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[5] connect ll_arb.io.in[3].bits.uop.fu_code[6], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[6] connect ll_arb.io.in[3].bits.uop.fu_code[7], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[7] connect ll_arb.io.in[3].bits.uop.fu_code[8], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[8] connect ll_arb.io.in[3].bits.uop.fu_code[9], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[9] connect ll_arb.io.in[3].bits.uop.iq_type[0], unique_exe_unit_0.io_csr_resp.bits.uop.iq_type[0] connect ll_arb.io.in[3].bits.uop.iq_type[1], unique_exe_unit_0.io_csr_resp.bits.uop.iq_type[1] connect ll_arb.io.in[3].bits.uop.iq_type[2], unique_exe_unit_0.io_csr_resp.bits.uop.iq_type[2] connect ll_arb.io.in[3].bits.uop.iq_type[3], unique_exe_unit_0.io_csr_resp.bits.uop.iq_type[3] connect ll_arb.io.in[3].bits.uop.debug_pc, unique_exe_unit_0.io_csr_resp.bits.uop.debug_pc connect ll_arb.io.in[3].bits.uop.is_rvc, unique_exe_unit_0.io_csr_resp.bits.uop.is_rvc connect ll_arb.io.in[3].bits.uop.debug_inst, unique_exe_unit_0.io_csr_resp.bits.uop.debug_inst connect ll_arb.io.in[3].bits.uop.inst, unique_exe_unit_0.io_csr_resp.bits.uop.inst wire rdata : UInt connect rdata, csr.io.rw.rdata connect ll_arb.io.in[3].bits.data, rdata connect ll_arb.io.in[3].bits.predicated, UInt<1>(0h0) connect ll_arb.io.in[3].bits.fflags.valid, UInt<1>(0h0) connect ll_arb.io.in[3].bits.fflags.bits, UInt<1>(0h0) node _T_118 = eq(ll_arb.io.in[3].ready, UInt<1>(0h0)) node _T_119 = and(ll_arb.io.in[3].valid, _T_118) node _T_120 = eq(_T_119, UInt<1>(0h0)) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed\n at core.scala:929 assert(!(ll_arb.io.in(arb_idx).valid && !ll_arb.io.in(arb_idx).ready))\n") : printf_3 assert(clock, _T_120, UInt<1>(0h1), "") : assert_3 connect ll_arb.io.out.ready, UInt<1>(0h1) node _int_wakeups_1_valid_T = eq(ll_arb.io.out.bits.uop.dst_rtype, UInt<2>(0h0)) node _int_wakeups_1_valid_T_1 = and(ll_arb.io.out.valid, _int_wakeups_1_valid_T) connect int_wakeups[1].valid, _int_wakeups_1_valid_T_1 connect int_wakeups[1].bits.uop, ll_arb.io.out.bits.uop connect int_wakeups[1].bits.speculative_mask, UInt<1>(0h0) connect int_wakeups[1].bits.rebusy, UInt<1>(0h0) connect int_wakeups[1].bits.bypassable, UInt<1>(0h0) reg rob_io_wb_resps_1_valid_REG : UInt<1>, clock connect rob_io_wb_resps_1_valid_REG, rob.io.flush.valid node _rob_io_wb_resps_1_valid_T = and(brupdate.b1.mispredict_mask, ll_arb.io.out.bits.uop.br_mask) node _rob_io_wb_resps_1_valid_T_1 = neq(_rob_io_wb_resps_1_valid_T, UInt<1>(0h0)) node _rob_io_wb_resps_1_valid_T_2 = or(_rob_io_wb_resps_1_valid_T_1, rob_io_wb_resps_1_valid_REG) node _rob_io_wb_resps_1_valid_T_3 = eq(_rob_io_wb_resps_1_valid_T_2, UInt<1>(0h0)) node _rob_io_wb_resps_1_valid_T_4 = and(ll_arb.io.out.valid, _rob_io_wb_resps_1_valid_T_3) reg rob_io_wb_resps_1_valid_REG_1 : UInt<1>, clock connect rob_io_wb_resps_1_valid_REG_1, _rob_io_wb_resps_1_valid_T_4 connect rob.io.wb_resps[1].valid, rob_io_wb_resps_1_valid_REG_1 reg rob_io_wb_resps_1_bits_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}, clock connect rob_io_wb_resps_1_bits_REG, ll_arb.io.out.bits connect rob.io.wb_resps[1].bits.fflags.bits, rob_io_wb_resps_1_bits_REG.fflags.bits connect rob.io.wb_resps[1].bits.fflags.valid, rob_io_wb_resps_1_bits_REG.fflags.valid connect rob.io.wb_resps[1].bits.predicated, rob_io_wb_resps_1_bits_REG.predicated connect rob.io.wb_resps[1].bits.data, rob_io_wb_resps_1_bits_REG.data connect rob.io.wb_resps[1].bits.uop.debug_tsrc, rob_io_wb_resps_1_bits_REG.uop.debug_tsrc connect rob.io.wb_resps[1].bits.uop.debug_fsrc, rob_io_wb_resps_1_bits_REG.uop.debug_fsrc connect rob.io.wb_resps[1].bits.uop.bp_xcpt_if, rob_io_wb_resps_1_bits_REG.uop.bp_xcpt_if connect rob.io.wb_resps[1].bits.uop.bp_debug_if, rob_io_wb_resps_1_bits_REG.uop.bp_debug_if connect rob.io.wb_resps[1].bits.uop.xcpt_ma_if, rob_io_wb_resps_1_bits_REG.uop.xcpt_ma_if connect rob.io.wb_resps[1].bits.uop.xcpt_ae_if, rob_io_wb_resps_1_bits_REG.uop.xcpt_ae_if connect rob.io.wb_resps[1].bits.uop.xcpt_pf_if, rob_io_wb_resps_1_bits_REG.uop.xcpt_pf_if connect rob.io.wb_resps[1].bits.uop.fp_typ, rob_io_wb_resps_1_bits_REG.uop.fp_typ connect rob.io.wb_resps[1].bits.uop.fp_rm, rob_io_wb_resps_1_bits_REG.uop.fp_rm connect rob.io.wb_resps[1].bits.uop.fp_val, rob_io_wb_resps_1_bits_REG.uop.fp_val connect rob.io.wb_resps[1].bits.uop.fcn_op, rob_io_wb_resps_1_bits_REG.uop.fcn_op connect rob.io.wb_resps[1].bits.uop.fcn_dw, rob_io_wb_resps_1_bits_REG.uop.fcn_dw connect rob.io.wb_resps[1].bits.uop.frs3_en, rob_io_wb_resps_1_bits_REG.uop.frs3_en connect rob.io.wb_resps[1].bits.uop.lrs2_rtype, rob_io_wb_resps_1_bits_REG.uop.lrs2_rtype connect rob.io.wb_resps[1].bits.uop.lrs1_rtype, rob_io_wb_resps_1_bits_REG.uop.lrs1_rtype connect rob.io.wb_resps[1].bits.uop.dst_rtype, rob_io_wb_resps_1_bits_REG.uop.dst_rtype connect rob.io.wb_resps[1].bits.uop.lrs3, rob_io_wb_resps_1_bits_REG.uop.lrs3 connect rob.io.wb_resps[1].bits.uop.lrs2, rob_io_wb_resps_1_bits_REG.uop.lrs2 connect rob.io.wb_resps[1].bits.uop.lrs1, rob_io_wb_resps_1_bits_REG.uop.lrs1 connect rob.io.wb_resps[1].bits.uop.ldst, rob_io_wb_resps_1_bits_REG.uop.ldst connect rob.io.wb_resps[1].bits.uop.ldst_is_rs1, rob_io_wb_resps_1_bits_REG.uop.ldst_is_rs1 connect rob.io.wb_resps[1].bits.uop.csr_cmd, rob_io_wb_resps_1_bits_REG.uop.csr_cmd connect rob.io.wb_resps[1].bits.uop.flush_on_commit, rob_io_wb_resps_1_bits_REG.uop.flush_on_commit connect rob.io.wb_resps[1].bits.uop.is_unique, rob_io_wb_resps_1_bits_REG.uop.is_unique connect rob.io.wb_resps[1].bits.uop.uses_stq, rob_io_wb_resps_1_bits_REG.uop.uses_stq connect rob.io.wb_resps[1].bits.uop.uses_ldq, rob_io_wb_resps_1_bits_REG.uop.uses_ldq connect rob.io.wb_resps[1].bits.uop.mem_signed, rob_io_wb_resps_1_bits_REG.uop.mem_signed connect rob.io.wb_resps[1].bits.uop.mem_size, rob_io_wb_resps_1_bits_REG.uop.mem_size connect rob.io.wb_resps[1].bits.uop.mem_cmd, rob_io_wb_resps_1_bits_REG.uop.mem_cmd connect rob.io.wb_resps[1].bits.uop.exc_cause, rob_io_wb_resps_1_bits_REG.uop.exc_cause connect rob.io.wb_resps[1].bits.uop.exception, rob_io_wb_resps_1_bits_REG.uop.exception connect rob.io.wb_resps[1].bits.uop.stale_pdst, rob_io_wb_resps_1_bits_REG.uop.stale_pdst connect rob.io.wb_resps[1].bits.uop.ppred_busy, rob_io_wb_resps_1_bits_REG.uop.ppred_busy connect rob.io.wb_resps[1].bits.uop.prs3_busy, rob_io_wb_resps_1_bits_REG.uop.prs3_busy connect rob.io.wb_resps[1].bits.uop.prs2_busy, rob_io_wb_resps_1_bits_REG.uop.prs2_busy connect rob.io.wb_resps[1].bits.uop.prs1_busy, rob_io_wb_resps_1_bits_REG.uop.prs1_busy connect rob.io.wb_resps[1].bits.uop.ppred, rob_io_wb_resps_1_bits_REG.uop.ppred connect rob.io.wb_resps[1].bits.uop.prs3, rob_io_wb_resps_1_bits_REG.uop.prs3 connect rob.io.wb_resps[1].bits.uop.prs2, rob_io_wb_resps_1_bits_REG.uop.prs2 connect rob.io.wb_resps[1].bits.uop.prs1, rob_io_wb_resps_1_bits_REG.uop.prs1 connect rob.io.wb_resps[1].bits.uop.pdst, rob_io_wb_resps_1_bits_REG.uop.pdst connect rob.io.wb_resps[1].bits.uop.rxq_idx, rob_io_wb_resps_1_bits_REG.uop.rxq_idx connect rob.io.wb_resps[1].bits.uop.stq_idx, rob_io_wb_resps_1_bits_REG.uop.stq_idx connect rob.io.wb_resps[1].bits.uop.ldq_idx, rob_io_wb_resps_1_bits_REG.uop.ldq_idx connect rob.io.wb_resps[1].bits.uop.rob_idx, rob_io_wb_resps_1_bits_REG.uop.rob_idx connect rob.io.wb_resps[1].bits.uop.fp_ctrl.vec, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.vec connect rob.io.wb_resps[1].bits.uop.fp_ctrl.wflags, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.wflags connect rob.io.wb_resps[1].bits.uop.fp_ctrl.sqrt, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.sqrt connect rob.io.wb_resps[1].bits.uop.fp_ctrl.div, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.div connect rob.io.wb_resps[1].bits.uop.fp_ctrl.fma, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.fma connect rob.io.wb_resps[1].bits.uop.fp_ctrl.fastpipe, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.fastpipe connect rob.io.wb_resps[1].bits.uop.fp_ctrl.toint, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.toint connect rob.io.wb_resps[1].bits.uop.fp_ctrl.fromint, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.fromint connect rob.io.wb_resps[1].bits.uop.fp_ctrl.typeTagOut, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.typeTagOut connect rob.io.wb_resps[1].bits.uop.fp_ctrl.typeTagIn, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.typeTagIn connect rob.io.wb_resps[1].bits.uop.fp_ctrl.swap23, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.swap23 connect rob.io.wb_resps[1].bits.uop.fp_ctrl.swap12, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.swap12 connect rob.io.wb_resps[1].bits.uop.fp_ctrl.ren3, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.ren3 connect rob.io.wb_resps[1].bits.uop.fp_ctrl.ren2, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.ren2 connect rob.io.wb_resps[1].bits.uop.fp_ctrl.ren1, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.ren1 connect rob.io.wb_resps[1].bits.uop.fp_ctrl.wen, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.wen connect rob.io.wb_resps[1].bits.uop.fp_ctrl.ldst, rob_io_wb_resps_1_bits_REG.uop.fp_ctrl.ldst connect rob.io.wb_resps[1].bits.uop.op2_sel, rob_io_wb_resps_1_bits_REG.uop.op2_sel connect rob.io.wb_resps[1].bits.uop.op1_sel, rob_io_wb_resps_1_bits_REG.uop.op1_sel connect rob.io.wb_resps[1].bits.uop.imm_packed, rob_io_wb_resps_1_bits_REG.uop.imm_packed connect rob.io.wb_resps[1].bits.uop.pimm, rob_io_wb_resps_1_bits_REG.uop.pimm connect rob.io.wb_resps[1].bits.uop.imm_sel, rob_io_wb_resps_1_bits_REG.uop.imm_sel connect rob.io.wb_resps[1].bits.uop.imm_rename, rob_io_wb_resps_1_bits_REG.uop.imm_rename connect rob.io.wb_resps[1].bits.uop.taken, rob_io_wb_resps_1_bits_REG.uop.taken connect rob.io.wb_resps[1].bits.uop.pc_lob, rob_io_wb_resps_1_bits_REG.uop.pc_lob connect rob.io.wb_resps[1].bits.uop.edge_inst, rob_io_wb_resps_1_bits_REG.uop.edge_inst connect rob.io.wb_resps[1].bits.uop.ftq_idx, rob_io_wb_resps_1_bits_REG.uop.ftq_idx connect rob.io.wb_resps[1].bits.uop.is_mov, rob_io_wb_resps_1_bits_REG.uop.is_mov connect rob.io.wb_resps[1].bits.uop.is_rocc, rob_io_wb_resps_1_bits_REG.uop.is_rocc connect rob.io.wb_resps[1].bits.uop.is_sys_pc2epc, rob_io_wb_resps_1_bits_REG.uop.is_sys_pc2epc connect rob.io.wb_resps[1].bits.uop.is_eret, rob_io_wb_resps_1_bits_REG.uop.is_eret connect rob.io.wb_resps[1].bits.uop.is_amo, rob_io_wb_resps_1_bits_REG.uop.is_amo connect rob.io.wb_resps[1].bits.uop.is_sfence, rob_io_wb_resps_1_bits_REG.uop.is_sfence connect rob.io.wb_resps[1].bits.uop.is_fencei, rob_io_wb_resps_1_bits_REG.uop.is_fencei connect rob.io.wb_resps[1].bits.uop.is_fence, rob_io_wb_resps_1_bits_REG.uop.is_fence connect rob.io.wb_resps[1].bits.uop.is_sfb, rob_io_wb_resps_1_bits_REG.uop.is_sfb connect rob.io.wb_resps[1].bits.uop.br_type, rob_io_wb_resps_1_bits_REG.uop.br_type connect rob.io.wb_resps[1].bits.uop.br_tag, rob_io_wb_resps_1_bits_REG.uop.br_tag connect rob.io.wb_resps[1].bits.uop.br_mask, rob_io_wb_resps_1_bits_REG.uop.br_mask connect rob.io.wb_resps[1].bits.uop.dis_col_sel, rob_io_wb_resps_1_bits_REG.uop.dis_col_sel connect rob.io.wb_resps[1].bits.uop.iw_p3_bypass_hint, rob_io_wb_resps_1_bits_REG.uop.iw_p3_bypass_hint connect rob.io.wb_resps[1].bits.uop.iw_p2_bypass_hint, rob_io_wb_resps_1_bits_REG.uop.iw_p2_bypass_hint connect rob.io.wb_resps[1].bits.uop.iw_p1_bypass_hint, rob_io_wb_resps_1_bits_REG.uop.iw_p1_bypass_hint connect rob.io.wb_resps[1].bits.uop.iw_p2_speculative_child, rob_io_wb_resps_1_bits_REG.uop.iw_p2_speculative_child connect rob.io.wb_resps[1].bits.uop.iw_p1_speculative_child, rob_io_wb_resps_1_bits_REG.uop.iw_p1_speculative_child connect rob.io.wb_resps[1].bits.uop.iw_issued_partial_dgen, rob_io_wb_resps_1_bits_REG.uop.iw_issued_partial_dgen connect rob.io.wb_resps[1].bits.uop.iw_issued_partial_agen, rob_io_wb_resps_1_bits_REG.uop.iw_issued_partial_agen connect rob.io.wb_resps[1].bits.uop.iw_issued, rob_io_wb_resps_1_bits_REG.uop.iw_issued connect rob.io.wb_resps[1].bits.uop.fu_code[0], rob_io_wb_resps_1_bits_REG.uop.fu_code[0] connect rob.io.wb_resps[1].bits.uop.fu_code[1], rob_io_wb_resps_1_bits_REG.uop.fu_code[1] connect rob.io.wb_resps[1].bits.uop.fu_code[2], rob_io_wb_resps_1_bits_REG.uop.fu_code[2] connect rob.io.wb_resps[1].bits.uop.fu_code[3], rob_io_wb_resps_1_bits_REG.uop.fu_code[3] connect rob.io.wb_resps[1].bits.uop.fu_code[4], rob_io_wb_resps_1_bits_REG.uop.fu_code[4] connect rob.io.wb_resps[1].bits.uop.fu_code[5], rob_io_wb_resps_1_bits_REG.uop.fu_code[5] connect rob.io.wb_resps[1].bits.uop.fu_code[6], rob_io_wb_resps_1_bits_REG.uop.fu_code[6] connect rob.io.wb_resps[1].bits.uop.fu_code[7], rob_io_wb_resps_1_bits_REG.uop.fu_code[7] connect rob.io.wb_resps[1].bits.uop.fu_code[8], rob_io_wb_resps_1_bits_REG.uop.fu_code[8] connect rob.io.wb_resps[1].bits.uop.fu_code[9], rob_io_wb_resps_1_bits_REG.uop.fu_code[9] connect rob.io.wb_resps[1].bits.uop.iq_type[0], rob_io_wb_resps_1_bits_REG.uop.iq_type[0] connect rob.io.wb_resps[1].bits.uop.iq_type[1], rob_io_wb_resps_1_bits_REG.uop.iq_type[1] connect rob.io.wb_resps[1].bits.uop.iq_type[2], rob_io_wb_resps_1_bits_REG.uop.iq_type[2] connect rob.io.wb_resps[1].bits.uop.iq_type[3], rob_io_wb_resps_1_bits_REG.uop.iq_type[3] connect rob.io.wb_resps[1].bits.uop.debug_pc, rob_io_wb_resps_1_bits_REG.uop.debug_pc connect rob.io.wb_resps[1].bits.uop.is_rvc, rob_io_wb_resps_1_bits_REG.uop.is_rvc connect rob.io.wb_resps[1].bits.uop.debug_inst, rob_io_wb_resps_1_bits_REG.uop.debug_inst connect rob.io.wb_resps[1].bits.uop.inst, rob_io_wb_resps_1_bits_REG.uop.inst node _iregfile_io_write_ports_1_valid_T = eq(ll_arb.io.out.bits.uop.dst_rtype, UInt<2>(0h0)) node _iregfile_io_write_ports_1_valid_T_1 = and(ll_arb.io.out.valid, _iregfile_io_write_ports_1_valid_T) connect iregfile.io.write_ports[1].valid, _iregfile_io_write_ports_1_valid_T_1 connect iregfile.io.write_ports[1].bits.addr, ll_arb.io.out.bits.uop.pdst connect iregfile.io.write_ports[1].bits.data, ll_arb.io.out.bits.data node _int_bypasses_1_valid_T = eq(alu_exe_unit_0.io_alu_resp.bits.uop.dst_rtype, UInt<2>(0h0)) node _int_bypasses_1_valid_T_1 = and(alu_exe_unit_0.io_alu_resp.valid, _int_bypasses_1_valid_T) connect int_bypasses[1].valid, _int_bypasses_1_valid_T_1 connect int_bypasses[1].bits, alu_exe_unit_0.io_alu_resp.bits connect int_wakeups[2], alu_exe_unit_0.io_fast_wakeup reg rob_io_wb_resps_2_valid_REG : UInt<1>, clock connect rob_io_wb_resps_2_valid_REG, rob.io.flush.valid node _rob_io_wb_resps_2_valid_T = and(brupdate.b1.mispredict_mask, alu_exe_unit_0.io_alu_resp.bits.uop.br_mask) node _rob_io_wb_resps_2_valid_T_1 = neq(_rob_io_wb_resps_2_valid_T, UInt<1>(0h0)) node _rob_io_wb_resps_2_valid_T_2 = or(_rob_io_wb_resps_2_valid_T_1, rob_io_wb_resps_2_valid_REG) node _rob_io_wb_resps_2_valid_T_3 = eq(_rob_io_wb_resps_2_valid_T_2, UInt<1>(0h0)) node _rob_io_wb_resps_2_valid_T_4 = and(alu_exe_unit_0.io_alu_resp.valid, _rob_io_wb_resps_2_valid_T_3) reg rob_io_wb_resps_2_valid_REG_1 : UInt<1>, clock connect rob_io_wb_resps_2_valid_REG_1, _rob_io_wb_resps_2_valid_T_4 connect rob.io.wb_resps[2].valid, rob_io_wb_resps_2_valid_REG_1 reg rob_io_wb_resps_2_bits_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}, clock connect rob_io_wb_resps_2_bits_REG, alu_exe_unit_0.io_alu_resp.bits connect rob.io.wb_resps[2].bits.fflags.bits, rob_io_wb_resps_2_bits_REG.fflags.bits connect rob.io.wb_resps[2].bits.fflags.valid, rob_io_wb_resps_2_bits_REG.fflags.valid connect rob.io.wb_resps[2].bits.predicated, rob_io_wb_resps_2_bits_REG.predicated connect rob.io.wb_resps[2].bits.data, rob_io_wb_resps_2_bits_REG.data connect rob.io.wb_resps[2].bits.uop.debug_tsrc, rob_io_wb_resps_2_bits_REG.uop.debug_tsrc connect rob.io.wb_resps[2].bits.uop.debug_fsrc, rob_io_wb_resps_2_bits_REG.uop.debug_fsrc connect rob.io.wb_resps[2].bits.uop.bp_xcpt_if, rob_io_wb_resps_2_bits_REG.uop.bp_xcpt_if connect rob.io.wb_resps[2].bits.uop.bp_debug_if, rob_io_wb_resps_2_bits_REG.uop.bp_debug_if connect rob.io.wb_resps[2].bits.uop.xcpt_ma_if, rob_io_wb_resps_2_bits_REG.uop.xcpt_ma_if connect rob.io.wb_resps[2].bits.uop.xcpt_ae_if, rob_io_wb_resps_2_bits_REG.uop.xcpt_ae_if connect rob.io.wb_resps[2].bits.uop.xcpt_pf_if, rob_io_wb_resps_2_bits_REG.uop.xcpt_pf_if connect rob.io.wb_resps[2].bits.uop.fp_typ, rob_io_wb_resps_2_bits_REG.uop.fp_typ connect rob.io.wb_resps[2].bits.uop.fp_rm, rob_io_wb_resps_2_bits_REG.uop.fp_rm connect rob.io.wb_resps[2].bits.uop.fp_val, rob_io_wb_resps_2_bits_REG.uop.fp_val connect rob.io.wb_resps[2].bits.uop.fcn_op, rob_io_wb_resps_2_bits_REG.uop.fcn_op connect rob.io.wb_resps[2].bits.uop.fcn_dw, rob_io_wb_resps_2_bits_REG.uop.fcn_dw connect rob.io.wb_resps[2].bits.uop.frs3_en, rob_io_wb_resps_2_bits_REG.uop.frs3_en connect rob.io.wb_resps[2].bits.uop.lrs2_rtype, rob_io_wb_resps_2_bits_REG.uop.lrs2_rtype connect rob.io.wb_resps[2].bits.uop.lrs1_rtype, rob_io_wb_resps_2_bits_REG.uop.lrs1_rtype connect rob.io.wb_resps[2].bits.uop.dst_rtype, rob_io_wb_resps_2_bits_REG.uop.dst_rtype connect rob.io.wb_resps[2].bits.uop.lrs3, rob_io_wb_resps_2_bits_REG.uop.lrs3 connect rob.io.wb_resps[2].bits.uop.lrs2, rob_io_wb_resps_2_bits_REG.uop.lrs2 connect rob.io.wb_resps[2].bits.uop.lrs1, rob_io_wb_resps_2_bits_REG.uop.lrs1 connect rob.io.wb_resps[2].bits.uop.ldst, rob_io_wb_resps_2_bits_REG.uop.ldst connect rob.io.wb_resps[2].bits.uop.ldst_is_rs1, rob_io_wb_resps_2_bits_REG.uop.ldst_is_rs1 connect rob.io.wb_resps[2].bits.uop.csr_cmd, rob_io_wb_resps_2_bits_REG.uop.csr_cmd connect rob.io.wb_resps[2].bits.uop.flush_on_commit, rob_io_wb_resps_2_bits_REG.uop.flush_on_commit connect rob.io.wb_resps[2].bits.uop.is_unique, rob_io_wb_resps_2_bits_REG.uop.is_unique connect rob.io.wb_resps[2].bits.uop.uses_stq, rob_io_wb_resps_2_bits_REG.uop.uses_stq connect rob.io.wb_resps[2].bits.uop.uses_ldq, rob_io_wb_resps_2_bits_REG.uop.uses_ldq connect rob.io.wb_resps[2].bits.uop.mem_signed, rob_io_wb_resps_2_bits_REG.uop.mem_signed connect rob.io.wb_resps[2].bits.uop.mem_size, rob_io_wb_resps_2_bits_REG.uop.mem_size connect rob.io.wb_resps[2].bits.uop.mem_cmd, rob_io_wb_resps_2_bits_REG.uop.mem_cmd connect rob.io.wb_resps[2].bits.uop.exc_cause, rob_io_wb_resps_2_bits_REG.uop.exc_cause connect rob.io.wb_resps[2].bits.uop.exception, rob_io_wb_resps_2_bits_REG.uop.exception connect rob.io.wb_resps[2].bits.uop.stale_pdst, rob_io_wb_resps_2_bits_REG.uop.stale_pdst connect rob.io.wb_resps[2].bits.uop.ppred_busy, rob_io_wb_resps_2_bits_REG.uop.ppred_busy connect rob.io.wb_resps[2].bits.uop.prs3_busy, rob_io_wb_resps_2_bits_REG.uop.prs3_busy connect rob.io.wb_resps[2].bits.uop.prs2_busy, rob_io_wb_resps_2_bits_REG.uop.prs2_busy connect rob.io.wb_resps[2].bits.uop.prs1_busy, rob_io_wb_resps_2_bits_REG.uop.prs1_busy connect rob.io.wb_resps[2].bits.uop.ppred, rob_io_wb_resps_2_bits_REG.uop.ppred connect rob.io.wb_resps[2].bits.uop.prs3, rob_io_wb_resps_2_bits_REG.uop.prs3 connect rob.io.wb_resps[2].bits.uop.prs2, rob_io_wb_resps_2_bits_REG.uop.prs2 connect rob.io.wb_resps[2].bits.uop.prs1, rob_io_wb_resps_2_bits_REG.uop.prs1 connect rob.io.wb_resps[2].bits.uop.pdst, rob_io_wb_resps_2_bits_REG.uop.pdst connect rob.io.wb_resps[2].bits.uop.rxq_idx, rob_io_wb_resps_2_bits_REG.uop.rxq_idx connect rob.io.wb_resps[2].bits.uop.stq_idx, rob_io_wb_resps_2_bits_REG.uop.stq_idx connect rob.io.wb_resps[2].bits.uop.ldq_idx, rob_io_wb_resps_2_bits_REG.uop.ldq_idx connect rob.io.wb_resps[2].bits.uop.rob_idx, rob_io_wb_resps_2_bits_REG.uop.rob_idx connect rob.io.wb_resps[2].bits.uop.fp_ctrl.vec, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.vec connect rob.io.wb_resps[2].bits.uop.fp_ctrl.wflags, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.wflags connect rob.io.wb_resps[2].bits.uop.fp_ctrl.sqrt, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.sqrt connect rob.io.wb_resps[2].bits.uop.fp_ctrl.div, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.div connect rob.io.wb_resps[2].bits.uop.fp_ctrl.fma, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.fma connect rob.io.wb_resps[2].bits.uop.fp_ctrl.fastpipe, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.fastpipe connect rob.io.wb_resps[2].bits.uop.fp_ctrl.toint, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.toint connect rob.io.wb_resps[2].bits.uop.fp_ctrl.fromint, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.fromint connect rob.io.wb_resps[2].bits.uop.fp_ctrl.typeTagOut, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.typeTagOut connect rob.io.wb_resps[2].bits.uop.fp_ctrl.typeTagIn, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.typeTagIn connect rob.io.wb_resps[2].bits.uop.fp_ctrl.swap23, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.swap23 connect rob.io.wb_resps[2].bits.uop.fp_ctrl.swap12, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.swap12 connect rob.io.wb_resps[2].bits.uop.fp_ctrl.ren3, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.ren3 connect rob.io.wb_resps[2].bits.uop.fp_ctrl.ren2, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.ren2 connect rob.io.wb_resps[2].bits.uop.fp_ctrl.ren1, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.ren1 connect rob.io.wb_resps[2].bits.uop.fp_ctrl.wen, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.wen connect rob.io.wb_resps[2].bits.uop.fp_ctrl.ldst, rob_io_wb_resps_2_bits_REG.uop.fp_ctrl.ldst connect rob.io.wb_resps[2].bits.uop.op2_sel, rob_io_wb_resps_2_bits_REG.uop.op2_sel connect rob.io.wb_resps[2].bits.uop.op1_sel, rob_io_wb_resps_2_bits_REG.uop.op1_sel connect rob.io.wb_resps[2].bits.uop.imm_packed, rob_io_wb_resps_2_bits_REG.uop.imm_packed connect rob.io.wb_resps[2].bits.uop.pimm, rob_io_wb_resps_2_bits_REG.uop.pimm connect rob.io.wb_resps[2].bits.uop.imm_sel, rob_io_wb_resps_2_bits_REG.uop.imm_sel connect rob.io.wb_resps[2].bits.uop.imm_rename, rob_io_wb_resps_2_bits_REG.uop.imm_rename connect rob.io.wb_resps[2].bits.uop.taken, rob_io_wb_resps_2_bits_REG.uop.taken connect rob.io.wb_resps[2].bits.uop.pc_lob, rob_io_wb_resps_2_bits_REG.uop.pc_lob connect rob.io.wb_resps[2].bits.uop.edge_inst, rob_io_wb_resps_2_bits_REG.uop.edge_inst connect rob.io.wb_resps[2].bits.uop.ftq_idx, rob_io_wb_resps_2_bits_REG.uop.ftq_idx connect rob.io.wb_resps[2].bits.uop.is_mov, rob_io_wb_resps_2_bits_REG.uop.is_mov connect rob.io.wb_resps[2].bits.uop.is_rocc, rob_io_wb_resps_2_bits_REG.uop.is_rocc connect rob.io.wb_resps[2].bits.uop.is_sys_pc2epc, rob_io_wb_resps_2_bits_REG.uop.is_sys_pc2epc connect rob.io.wb_resps[2].bits.uop.is_eret, rob_io_wb_resps_2_bits_REG.uop.is_eret connect rob.io.wb_resps[2].bits.uop.is_amo, rob_io_wb_resps_2_bits_REG.uop.is_amo connect rob.io.wb_resps[2].bits.uop.is_sfence, rob_io_wb_resps_2_bits_REG.uop.is_sfence connect rob.io.wb_resps[2].bits.uop.is_fencei, rob_io_wb_resps_2_bits_REG.uop.is_fencei connect rob.io.wb_resps[2].bits.uop.is_fence, rob_io_wb_resps_2_bits_REG.uop.is_fence connect rob.io.wb_resps[2].bits.uop.is_sfb, rob_io_wb_resps_2_bits_REG.uop.is_sfb connect rob.io.wb_resps[2].bits.uop.br_type, rob_io_wb_resps_2_bits_REG.uop.br_type connect rob.io.wb_resps[2].bits.uop.br_tag, rob_io_wb_resps_2_bits_REG.uop.br_tag connect rob.io.wb_resps[2].bits.uop.br_mask, rob_io_wb_resps_2_bits_REG.uop.br_mask connect rob.io.wb_resps[2].bits.uop.dis_col_sel, rob_io_wb_resps_2_bits_REG.uop.dis_col_sel connect rob.io.wb_resps[2].bits.uop.iw_p3_bypass_hint, rob_io_wb_resps_2_bits_REG.uop.iw_p3_bypass_hint connect rob.io.wb_resps[2].bits.uop.iw_p2_bypass_hint, rob_io_wb_resps_2_bits_REG.uop.iw_p2_bypass_hint connect rob.io.wb_resps[2].bits.uop.iw_p1_bypass_hint, rob_io_wb_resps_2_bits_REG.uop.iw_p1_bypass_hint connect rob.io.wb_resps[2].bits.uop.iw_p2_speculative_child, rob_io_wb_resps_2_bits_REG.uop.iw_p2_speculative_child connect rob.io.wb_resps[2].bits.uop.iw_p1_speculative_child, rob_io_wb_resps_2_bits_REG.uop.iw_p1_speculative_child connect rob.io.wb_resps[2].bits.uop.iw_issued_partial_dgen, rob_io_wb_resps_2_bits_REG.uop.iw_issued_partial_dgen connect rob.io.wb_resps[2].bits.uop.iw_issued_partial_agen, rob_io_wb_resps_2_bits_REG.uop.iw_issued_partial_agen connect rob.io.wb_resps[2].bits.uop.iw_issued, rob_io_wb_resps_2_bits_REG.uop.iw_issued connect rob.io.wb_resps[2].bits.uop.fu_code[0], rob_io_wb_resps_2_bits_REG.uop.fu_code[0] connect rob.io.wb_resps[2].bits.uop.fu_code[1], rob_io_wb_resps_2_bits_REG.uop.fu_code[1] connect rob.io.wb_resps[2].bits.uop.fu_code[2], rob_io_wb_resps_2_bits_REG.uop.fu_code[2] connect rob.io.wb_resps[2].bits.uop.fu_code[3], rob_io_wb_resps_2_bits_REG.uop.fu_code[3] connect rob.io.wb_resps[2].bits.uop.fu_code[4], rob_io_wb_resps_2_bits_REG.uop.fu_code[4] connect rob.io.wb_resps[2].bits.uop.fu_code[5], rob_io_wb_resps_2_bits_REG.uop.fu_code[5] connect rob.io.wb_resps[2].bits.uop.fu_code[6], rob_io_wb_resps_2_bits_REG.uop.fu_code[6] connect rob.io.wb_resps[2].bits.uop.fu_code[7], rob_io_wb_resps_2_bits_REG.uop.fu_code[7] connect rob.io.wb_resps[2].bits.uop.fu_code[8], rob_io_wb_resps_2_bits_REG.uop.fu_code[8] connect rob.io.wb_resps[2].bits.uop.fu_code[9], rob_io_wb_resps_2_bits_REG.uop.fu_code[9] connect rob.io.wb_resps[2].bits.uop.iq_type[0], rob_io_wb_resps_2_bits_REG.uop.iq_type[0] connect rob.io.wb_resps[2].bits.uop.iq_type[1], rob_io_wb_resps_2_bits_REG.uop.iq_type[1] connect rob.io.wb_resps[2].bits.uop.iq_type[2], rob_io_wb_resps_2_bits_REG.uop.iq_type[2] connect rob.io.wb_resps[2].bits.uop.iq_type[3], rob_io_wb_resps_2_bits_REG.uop.iq_type[3] connect rob.io.wb_resps[2].bits.uop.debug_pc, rob_io_wb_resps_2_bits_REG.uop.debug_pc connect rob.io.wb_resps[2].bits.uop.is_rvc, rob_io_wb_resps_2_bits_REG.uop.is_rvc connect rob.io.wb_resps[2].bits.uop.debug_inst, rob_io_wb_resps_2_bits_REG.uop.debug_inst connect rob.io.wb_resps[2].bits.uop.inst, rob_io_wb_resps_2_bits_REG.uop.inst node _iregfile_io_write_ports_2_valid_T = eq(alu_exe_unit_0.io_alu_resp.bits.uop.dst_rtype, UInt<2>(0h0)) node _iregfile_io_write_ports_2_valid_T_1 = and(alu_exe_unit_0.io_alu_resp.valid, _iregfile_io_write_ports_2_valid_T) connect iregfile.io.write_ports[2].valid, _iregfile_io_write_ports_2_valid_T_1 connect iregfile.io.write_ports[2].bits.addr, alu_exe_unit_0.io_alu_resp.bits.uop.pdst connect iregfile.io.write_ports[2].bits.data, alu_exe_unit_0.io_alu_resp.bits.data connect pred_wakeups[0], alu_exe_unit_0.io_fast_pred_wakeup node _int_bypasses_2_valid_T = eq(alu_exe_unit_1.io_alu_resp.bits.uop.dst_rtype, UInt<2>(0h0)) node _int_bypasses_2_valid_T_1 = and(alu_exe_unit_1.io_alu_resp.valid, _int_bypasses_2_valid_T) connect int_bypasses[2].valid, _int_bypasses_2_valid_T_1 connect int_bypasses[2].bits, alu_exe_unit_1.io_alu_resp.bits connect int_wakeups[3], alu_exe_unit_1.io_fast_wakeup reg rob_io_wb_resps_3_valid_REG : UInt<1>, clock connect rob_io_wb_resps_3_valid_REG, rob.io.flush.valid node _rob_io_wb_resps_3_valid_T = and(brupdate.b1.mispredict_mask, alu_exe_unit_1.io_alu_resp.bits.uop.br_mask) node _rob_io_wb_resps_3_valid_T_1 = neq(_rob_io_wb_resps_3_valid_T, UInt<1>(0h0)) node _rob_io_wb_resps_3_valid_T_2 = or(_rob_io_wb_resps_3_valid_T_1, rob_io_wb_resps_3_valid_REG) node _rob_io_wb_resps_3_valid_T_3 = eq(_rob_io_wb_resps_3_valid_T_2, UInt<1>(0h0)) node _rob_io_wb_resps_3_valid_T_4 = and(alu_exe_unit_1.io_alu_resp.valid, _rob_io_wb_resps_3_valid_T_3) reg rob_io_wb_resps_3_valid_REG_1 : UInt<1>, clock connect rob_io_wb_resps_3_valid_REG_1, _rob_io_wb_resps_3_valid_T_4 connect rob.io.wb_resps[3].valid, rob_io_wb_resps_3_valid_REG_1 reg rob_io_wb_resps_3_bits_REG : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}, clock connect rob_io_wb_resps_3_bits_REG, alu_exe_unit_1.io_alu_resp.bits connect rob.io.wb_resps[3].bits.fflags.bits, rob_io_wb_resps_3_bits_REG.fflags.bits connect rob.io.wb_resps[3].bits.fflags.valid, rob_io_wb_resps_3_bits_REG.fflags.valid connect rob.io.wb_resps[3].bits.predicated, rob_io_wb_resps_3_bits_REG.predicated connect rob.io.wb_resps[3].bits.data, rob_io_wb_resps_3_bits_REG.data connect rob.io.wb_resps[3].bits.uop.debug_tsrc, rob_io_wb_resps_3_bits_REG.uop.debug_tsrc connect rob.io.wb_resps[3].bits.uop.debug_fsrc, rob_io_wb_resps_3_bits_REG.uop.debug_fsrc connect rob.io.wb_resps[3].bits.uop.bp_xcpt_if, rob_io_wb_resps_3_bits_REG.uop.bp_xcpt_if connect rob.io.wb_resps[3].bits.uop.bp_debug_if, rob_io_wb_resps_3_bits_REG.uop.bp_debug_if connect rob.io.wb_resps[3].bits.uop.xcpt_ma_if, rob_io_wb_resps_3_bits_REG.uop.xcpt_ma_if connect rob.io.wb_resps[3].bits.uop.xcpt_ae_if, rob_io_wb_resps_3_bits_REG.uop.xcpt_ae_if connect rob.io.wb_resps[3].bits.uop.xcpt_pf_if, rob_io_wb_resps_3_bits_REG.uop.xcpt_pf_if connect rob.io.wb_resps[3].bits.uop.fp_typ, rob_io_wb_resps_3_bits_REG.uop.fp_typ connect rob.io.wb_resps[3].bits.uop.fp_rm, rob_io_wb_resps_3_bits_REG.uop.fp_rm connect rob.io.wb_resps[3].bits.uop.fp_val, rob_io_wb_resps_3_bits_REG.uop.fp_val connect rob.io.wb_resps[3].bits.uop.fcn_op, rob_io_wb_resps_3_bits_REG.uop.fcn_op connect rob.io.wb_resps[3].bits.uop.fcn_dw, rob_io_wb_resps_3_bits_REG.uop.fcn_dw connect rob.io.wb_resps[3].bits.uop.frs3_en, rob_io_wb_resps_3_bits_REG.uop.frs3_en connect rob.io.wb_resps[3].bits.uop.lrs2_rtype, rob_io_wb_resps_3_bits_REG.uop.lrs2_rtype connect rob.io.wb_resps[3].bits.uop.lrs1_rtype, rob_io_wb_resps_3_bits_REG.uop.lrs1_rtype connect rob.io.wb_resps[3].bits.uop.dst_rtype, rob_io_wb_resps_3_bits_REG.uop.dst_rtype connect rob.io.wb_resps[3].bits.uop.lrs3, rob_io_wb_resps_3_bits_REG.uop.lrs3 connect rob.io.wb_resps[3].bits.uop.lrs2, rob_io_wb_resps_3_bits_REG.uop.lrs2 connect rob.io.wb_resps[3].bits.uop.lrs1, rob_io_wb_resps_3_bits_REG.uop.lrs1 connect rob.io.wb_resps[3].bits.uop.ldst, rob_io_wb_resps_3_bits_REG.uop.ldst connect rob.io.wb_resps[3].bits.uop.ldst_is_rs1, rob_io_wb_resps_3_bits_REG.uop.ldst_is_rs1 connect rob.io.wb_resps[3].bits.uop.csr_cmd, rob_io_wb_resps_3_bits_REG.uop.csr_cmd connect rob.io.wb_resps[3].bits.uop.flush_on_commit, rob_io_wb_resps_3_bits_REG.uop.flush_on_commit connect rob.io.wb_resps[3].bits.uop.is_unique, rob_io_wb_resps_3_bits_REG.uop.is_unique connect rob.io.wb_resps[3].bits.uop.uses_stq, rob_io_wb_resps_3_bits_REG.uop.uses_stq connect rob.io.wb_resps[3].bits.uop.uses_ldq, rob_io_wb_resps_3_bits_REG.uop.uses_ldq connect rob.io.wb_resps[3].bits.uop.mem_signed, rob_io_wb_resps_3_bits_REG.uop.mem_signed connect rob.io.wb_resps[3].bits.uop.mem_size, rob_io_wb_resps_3_bits_REG.uop.mem_size connect rob.io.wb_resps[3].bits.uop.mem_cmd, rob_io_wb_resps_3_bits_REG.uop.mem_cmd connect rob.io.wb_resps[3].bits.uop.exc_cause, rob_io_wb_resps_3_bits_REG.uop.exc_cause connect rob.io.wb_resps[3].bits.uop.exception, rob_io_wb_resps_3_bits_REG.uop.exception connect rob.io.wb_resps[3].bits.uop.stale_pdst, rob_io_wb_resps_3_bits_REG.uop.stale_pdst connect rob.io.wb_resps[3].bits.uop.ppred_busy, rob_io_wb_resps_3_bits_REG.uop.ppred_busy connect rob.io.wb_resps[3].bits.uop.prs3_busy, rob_io_wb_resps_3_bits_REG.uop.prs3_busy connect rob.io.wb_resps[3].bits.uop.prs2_busy, rob_io_wb_resps_3_bits_REG.uop.prs2_busy connect rob.io.wb_resps[3].bits.uop.prs1_busy, rob_io_wb_resps_3_bits_REG.uop.prs1_busy connect rob.io.wb_resps[3].bits.uop.ppred, rob_io_wb_resps_3_bits_REG.uop.ppred connect rob.io.wb_resps[3].bits.uop.prs3, rob_io_wb_resps_3_bits_REG.uop.prs3 connect rob.io.wb_resps[3].bits.uop.prs2, rob_io_wb_resps_3_bits_REG.uop.prs2 connect rob.io.wb_resps[3].bits.uop.prs1, rob_io_wb_resps_3_bits_REG.uop.prs1 connect rob.io.wb_resps[3].bits.uop.pdst, rob_io_wb_resps_3_bits_REG.uop.pdst connect rob.io.wb_resps[3].bits.uop.rxq_idx, rob_io_wb_resps_3_bits_REG.uop.rxq_idx connect rob.io.wb_resps[3].bits.uop.stq_idx, rob_io_wb_resps_3_bits_REG.uop.stq_idx connect rob.io.wb_resps[3].bits.uop.ldq_idx, rob_io_wb_resps_3_bits_REG.uop.ldq_idx connect rob.io.wb_resps[3].bits.uop.rob_idx, rob_io_wb_resps_3_bits_REG.uop.rob_idx connect rob.io.wb_resps[3].bits.uop.fp_ctrl.vec, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.vec connect rob.io.wb_resps[3].bits.uop.fp_ctrl.wflags, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.wflags connect rob.io.wb_resps[3].bits.uop.fp_ctrl.sqrt, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.sqrt connect rob.io.wb_resps[3].bits.uop.fp_ctrl.div, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.div connect rob.io.wb_resps[3].bits.uop.fp_ctrl.fma, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.fma connect rob.io.wb_resps[3].bits.uop.fp_ctrl.fastpipe, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.fastpipe connect rob.io.wb_resps[3].bits.uop.fp_ctrl.toint, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.toint connect rob.io.wb_resps[3].bits.uop.fp_ctrl.fromint, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.fromint connect rob.io.wb_resps[3].bits.uop.fp_ctrl.typeTagOut, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.typeTagOut connect rob.io.wb_resps[3].bits.uop.fp_ctrl.typeTagIn, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.typeTagIn connect rob.io.wb_resps[3].bits.uop.fp_ctrl.swap23, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.swap23 connect rob.io.wb_resps[3].bits.uop.fp_ctrl.swap12, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.swap12 connect rob.io.wb_resps[3].bits.uop.fp_ctrl.ren3, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.ren3 connect rob.io.wb_resps[3].bits.uop.fp_ctrl.ren2, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.ren2 connect rob.io.wb_resps[3].bits.uop.fp_ctrl.ren1, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.ren1 connect rob.io.wb_resps[3].bits.uop.fp_ctrl.wen, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.wen connect rob.io.wb_resps[3].bits.uop.fp_ctrl.ldst, rob_io_wb_resps_3_bits_REG.uop.fp_ctrl.ldst connect rob.io.wb_resps[3].bits.uop.op2_sel, rob_io_wb_resps_3_bits_REG.uop.op2_sel connect rob.io.wb_resps[3].bits.uop.op1_sel, rob_io_wb_resps_3_bits_REG.uop.op1_sel connect rob.io.wb_resps[3].bits.uop.imm_packed, rob_io_wb_resps_3_bits_REG.uop.imm_packed connect rob.io.wb_resps[3].bits.uop.pimm, rob_io_wb_resps_3_bits_REG.uop.pimm connect rob.io.wb_resps[3].bits.uop.imm_sel, rob_io_wb_resps_3_bits_REG.uop.imm_sel connect rob.io.wb_resps[3].bits.uop.imm_rename, rob_io_wb_resps_3_bits_REG.uop.imm_rename connect rob.io.wb_resps[3].bits.uop.taken, rob_io_wb_resps_3_bits_REG.uop.taken connect rob.io.wb_resps[3].bits.uop.pc_lob, rob_io_wb_resps_3_bits_REG.uop.pc_lob connect rob.io.wb_resps[3].bits.uop.edge_inst, rob_io_wb_resps_3_bits_REG.uop.edge_inst connect rob.io.wb_resps[3].bits.uop.ftq_idx, rob_io_wb_resps_3_bits_REG.uop.ftq_idx connect rob.io.wb_resps[3].bits.uop.is_mov, rob_io_wb_resps_3_bits_REG.uop.is_mov connect rob.io.wb_resps[3].bits.uop.is_rocc, rob_io_wb_resps_3_bits_REG.uop.is_rocc connect rob.io.wb_resps[3].bits.uop.is_sys_pc2epc, rob_io_wb_resps_3_bits_REG.uop.is_sys_pc2epc connect rob.io.wb_resps[3].bits.uop.is_eret, rob_io_wb_resps_3_bits_REG.uop.is_eret connect rob.io.wb_resps[3].bits.uop.is_amo, rob_io_wb_resps_3_bits_REG.uop.is_amo connect rob.io.wb_resps[3].bits.uop.is_sfence, rob_io_wb_resps_3_bits_REG.uop.is_sfence connect rob.io.wb_resps[3].bits.uop.is_fencei, rob_io_wb_resps_3_bits_REG.uop.is_fencei connect rob.io.wb_resps[3].bits.uop.is_fence, rob_io_wb_resps_3_bits_REG.uop.is_fence connect rob.io.wb_resps[3].bits.uop.is_sfb, rob_io_wb_resps_3_bits_REG.uop.is_sfb connect rob.io.wb_resps[3].bits.uop.br_type, rob_io_wb_resps_3_bits_REG.uop.br_type connect rob.io.wb_resps[3].bits.uop.br_tag, rob_io_wb_resps_3_bits_REG.uop.br_tag connect rob.io.wb_resps[3].bits.uop.br_mask, rob_io_wb_resps_3_bits_REG.uop.br_mask connect rob.io.wb_resps[3].bits.uop.dis_col_sel, rob_io_wb_resps_3_bits_REG.uop.dis_col_sel connect rob.io.wb_resps[3].bits.uop.iw_p3_bypass_hint, rob_io_wb_resps_3_bits_REG.uop.iw_p3_bypass_hint connect rob.io.wb_resps[3].bits.uop.iw_p2_bypass_hint, rob_io_wb_resps_3_bits_REG.uop.iw_p2_bypass_hint connect rob.io.wb_resps[3].bits.uop.iw_p1_bypass_hint, rob_io_wb_resps_3_bits_REG.uop.iw_p1_bypass_hint connect rob.io.wb_resps[3].bits.uop.iw_p2_speculative_child, rob_io_wb_resps_3_bits_REG.uop.iw_p2_speculative_child connect rob.io.wb_resps[3].bits.uop.iw_p1_speculative_child, rob_io_wb_resps_3_bits_REG.uop.iw_p1_speculative_child connect rob.io.wb_resps[3].bits.uop.iw_issued_partial_dgen, rob_io_wb_resps_3_bits_REG.uop.iw_issued_partial_dgen connect rob.io.wb_resps[3].bits.uop.iw_issued_partial_agen, rob_io_wb_resps_3_bits_REG.uop.iw_issued_partial_agen connect rob.io.wb_resps[3].bits.uop.iw_issued, rob_io_wb_resps_3_bits_REG.uop.iw_issued connect rob.io.wb_resps[3].bits.uop.fu_code[0], rob_io_wb_resps_3_bits_REG.uop.fu_code[0] connect rob.io.wb_resps[3].bits.uop.fu_code[1], rob_io_wb_resps_3_bits_REG.uop.fu_code[1] connect rob.io.wb_resps[3].bits.uop.fu_code[2], rob_io_wb_resps_3_bits_REG.uop.fu_code[2] connect rob.io.wb_resps[3].bits.uop.fu_code[3], rob_io_wb_resps_3_bits_REG.uop.fu_code[3] connect rob.io.wb_resps[3].bits.uop.fu_code[4], rob_io_wb_resps_3_bits_REG.uop.fu_code[4] connect rob.io.wb_resps[3].bits.uop.fu_code[5], rob_io_wb_resps_3_bits_REG.uop.fu_code[5] connect rob.io.wb_resps[3].bits.uop.fu_code[6], rob_io_wb_resps_3_bits_REG.uop.fu_code[6] connect rob.io.wb_resps[3].bits.uop.fu_code[7], rob_io_wb_resps_3_bits_REG.uop.fu_code[7] connect rob.io.wb_resps[3].bits.uop.fu_code[8], rob_io_wb_resps_3_bits_REG.uop.fu_code[8] connect rob.io.wb_resps[3].bits.uop.fu_code[9], rob_io_wb_resps_3_bits_REG.uop.fu_code[9] connect rob.io.wb_resps[3].bits.uop.iq_type[0], rob_io_wb_resps_3_bits_REG.uop.iq_type[0] connect rob.io.wb_resps[3].bits.uop.iq_type[1], rob_io_wb_resps_3_bits_REG.uop.iq_type[1] connect rob.io.wb_resps[3].bits.uop.iq_type[2], rob_io_wb_resps_3_bits_REG.uop.iq_type[2] connect rob.io.wb_resps[3].bits.uop.iq_type[3], rob_io_wb_resps_3_bits_REG.uop.iq_type[3] connect rob.io.wb_resps[3].bits.uop.debug_pc, rob_io_wb_resps_3_bits_REG.uop.debug_pc connect rob.io.wb_resps[3].bits.uop.is_rvc, rob_io_wb_resps_3_bits_REG.uop.is_rvc connect rob.io.wb_resps[3].bits.uop.debug_inst, rob_io_wb_resps_3_bits_REG.uop.debug_inst connect rob.io.wb_resps[3].bits.uop.inst, rob_io_wb_resps_3_bits_REG.uop.inst node _iregfile_io_write_ports_3_valid_T = eq(alu_exe_unit_1.io_alu_resp.bits.uop.dst_rtype, UInt<2>(0h0)) node _iregfile_io_write_ports_3_valid_T_1 = and(alu_exe_unit_1.io_alu_resp.valid, _iregfile_io_write_ports_3_valid_T) connect iregfile.io.write_ports[3].valid, _iregfile_io_write_ports_3_valid_T_1 connect iregfile.io.write_ports[3].bits.addr, alu_exe_unit_1.io_alu_resp.bits.uop.pdst connect iregfile.io.write_ports[3].bits.data, alu_exe_unit_1.io_alu_resp.bits.data connect pred_wakeups[1], alu_exe_unit_1.io_fast_pred_wakeup node _pregfile_write_valids_T = neq(alu_exe_unit_0.io_alu_resp.bits.uop.br_type, UInt<4>(0h0)) node _pregfile_write_valids_T_1 = and(_pregfile_write_valids_T, alu_exe_unit_0.io_alu_resp.bits.uop.is_sfb) node _pregfile_write_valids_T_2 = and(_pregfile_write_valids_T_1, UInt<1>(0h1)) node pregfile_write_valids_0 = and(alu_exe_unit_0.io_alu_resp.valid, _pregfile_write_valids_T_2) node _pregfile_write_valids_T_3 = neq(alu_exe_unit_1.io_alu_resp.bits.uop.br_type, UInt<4>(0h0)) node _pregfile_write_valids_T_4 = and(_pregfile_write_valids_T_3, alu_exe_unit_1.io_alu_resp.bits.uop.is_sfb) node _pregfile_write_valids_T_5 = and(_pregfile_write_valids_T_4, UInt<1>(0h1)) node pregfile_write_valids_1 = and(alu_exe_unit_1.io_alu_resp.valid, _pregfile_write_valids_T_5) node _T_124 = add(pregfile_write_valids_0, pregfile_write_valids_1) node _T_125 = bits(_T_124, 1, 0) node _T_126 = leq(_T_125, UInt<1>(0h1)) node _T_127 = asUInt(reset) node _T_128 = eq(_T_127, UInt<1>(0h0)) when _T_128 : node _T_129 = eq(_T_126, UInt<1>(0h0)) when _T_129 : printf(clock, UInt<1>(0h1), "Assertion failed\n at core.scala:982 assert(PopCount(pregfile_write_valids) <= 1.U)\n") : printf_4 assert(clock, _T_126, UInt<1>(0h1), "") : assert_4 node _pregfile_io_write_ports_0_valid_T = or(pregfile_write_valids_0, pregfile_write_valids_1) connect pregfile.io.write_ports[0].valid, _pregfile_io_write_ports_0_valid_T node _pregfile_io_write_ports_0_bits_addr_T = mux(pregfile_write_valids_0, alu_exe_unit_0.io_alu_resp.bits.uop.pdst, UInt<1>(0h0)) node _pregfile_io_write_ports_0_bits_addr_T_1 = mux(pregfile_write_valids_1, alu_exe_unit_1.io_alu_resp.bits.uop.pdst, UInt<1>(0h0)) node _pregfile_io_write_ports_0_bits_addr_T_2 = or(_pregfile_io_write_ports_0_bits_addr_T, _pregfile_io_write_ports_0_bits_addr_T_1) wire _pregfile_io_write_ports_0_bits_addr_WIRE : UInt<7> connect _pregfile_io_write_ports_0_bits_addr_WIRE, _pregfile_io_write_ports_0_bits_addr_T_2 connect pregfile.io.write_ports[0].bits.addr, _pregfile_io_write_ports_0_bits_addr_WIRE node _pregfile_io_write_ports_0_bits_data_T = mux(pregfile_write_valids_0, alu_exe_unit_0.io_alu_resp.bits.data, UInt<1>(0h0)) node _pregfile_io_write_ports_0_bits_data_T_1 = mux(pregfile_write_valids_1, alu_exe_unit_1.io_alu_resp.bits.data, UInt<1>(0h0)) node _pregfile_io_write_ports_0_bits_data_T_2 = or(_pregfile_io_write_ports_0_bits_data_T, _pregfile_io_write_ports_0_bits_data_T_1) wire _pregfile_io_write_ports_0_bits_data_WIRE : UInt<64> connect _pregfile_io_write_ports_0_bits_data_WIRE, _pregfile_io_write_ports_0_bits_data_T_2 connect pregfile.io.write_ports[0].bits.data, _pregfile_io_write_ports_0_bits_data_WIRE connect alu_iss_unit.io.pred_wakeup_port.valid, pred_wakeup.valid connect alu_iss_unit.io.pred_wakeup_port.bits, pred_wakeup.bits.uop.pdst connect mem_iss_unit.io.pred_wakeup_port.valid, UInt<1>(0h0) invalidate mem_iss_unit.io.pred_wakeup_port.bits connect unq_iss_unit.io.pred_wakeup_port.valid, UInt<1>(0h0) invalidate unq_iss_unit.io.pred_wakeup_port.bits connect rename_stage.io.wakeups[0], int_wakeups[0] connect rename_stage.io.wakeups[1], int_wakeups[1] connect rename_stage.io.wakeups[2], int_wakeups[2] connect rename_stage.io.wakeups[3], int_wakeups[3] connect fp_rename_stage.io.wakeups[0].bits.rebusy, fp_pipeline.io.wakeups[0].bits.rebusy connect fp_rename_stage.io.wakeups[0].bits.speculative_mask, fp_pipeline.io.wakeups[0].bits.speculative_mask connect fp_rename_stage.io.wakeups[0].bits.bypassable, fp_pipeline.io.wakeups[0].bits.bypassable connect fp_rename_stage.io.wakeups[0].bits.uop.debug_tsrc, fp_pipeline.io.wakeups[0].bits.uop.debug_tsrc connect fp_rename_stage.io.wakeups[0].bits.uop.debug_fsrc, fp_pipeline.io.wakeups[0].bits.uop.debug_fsrc connect fp_rename_stage.io.wakeups[0].bits.uop.bp_xcpt_if, fp_pipeline.io.wakeups[0].bits.uop.bp_xcpt_if connect fp_rename_stage.io.wakeups[0].bits.uop.bp_debug_if, fp_pipeline.io.wakeups[0].bits.uop.bp_debug_if connect fp_rename_stage.io.wakeups[0].bits.uop.xcpt_ma_if, fp_pipeline.io.wakeups[0].bits.uop.xcpt_ma_if connect fp_rename_stage.io.wakeups[0].bits.uop.xcpt_ae_if, fp_pipeline.io.wakeups[0].bits.uop.xcpt_ae_if connect fp_rename_stage.io.wakeups[0].bits.uop.xcpt_pf_if, fp_pipeline.io.wakeups[0].bits.uop.xcpt_pf_if connect fp_rename_stage.io.wakeups[0].bits.uop.fp_typ, fp_pipeline.io.wakeups[0].bits.uop.fp_typ connect fp_rename_stage.io.wakeups[0].bits.uop.fp_rm, fp_pipeline.io.wakeups[0].bits.uop.fp_rm connect fp_rename_stage.io.wakeups[0].bits.uop.fp_val, fp_pipeline.io.wakeups[0].bits.uop.fp_val connect fp_rename_stage.io.wakeups[0].bits.uop.fcn_op, fp_pipeline.io.wakeups[0].bits.uop.fcn_op connect fp_rename_stage.io.wakeups[0].bits.uop.fcn_dw, fp_pipeline.io.wakeups[0].bits.uop.fcn_dw connect fp_rename_stage.io.wakeups[0].bits.uop.frs3_en, fp_pipeline.io.wakeups[0].bits.uop.frs3_en connect fp_rename_stage.io.wakeups[0].bits.uop.lrs2_rtype, fp_pipeline.io.wakeups[0].bits.uop.lrs2_rtype connect fp_rename_stage.io.wakeups[0].bits.uop.lrs1_rtype, fp_pipeline.io.wakeups[0].bits.uop.lrs1_rtype connect fp_rename_stage.io.wakeups[0].bits.uop.dst_rtype, fp_pipeline.io.wakeups[0].bits.uop.dst_rtype connect fp_rename_stage.io.wakeups[0].bits.uop.lrs3, fp_pipeline.io.wakeups[0].bits.uop.lrs3 connect fp_rename_stage.io.wakeups[0].bits.uop.lrs2, fp_pipeline.io.wakeups[0].bits.uop.lrs2 connect fp_rename_stage.io.wakeups[0].bits.uop.lrs1, fp_pipeline.io.wakeups[0].bits.uop.lrs1 connect fp_rename_stage.io.wakeups[0].bits.uop.ldst, fp_pipeline.io.wakeups[0].bits.uop.ldst connect fp_rename_stage.io.wakeups[0].bits.uop.ldst_is_rs1, fp_pipeline.io.wakeups[0].bits.uop.ldst_is_rs1 connect fp_rename_stage.io.wakeups[0].bits.uop.csr_cmd, fp_pipeline.io.wakeups[0].bits.uop.csr_cmd connect fp_rename_stage.io.wakeups[0].bits.uop.flush_on_commit, fp_pipeline.io.wakeups[0].bits.uop.flush_on_commit connect fp_rename_stage.io.wakeups[0].bits.uop.is_unique, fp_pipeline.io.wakeups[0].bits.uop.is_unique connect fp_rename_stage.io.wakeups[0].bits.uop.uses_stq, fp_pipeline.io.wakeups[0].bits.uop.uses_stq connect fp_rename_stage.io.wakeups[0].bits.uop.uses_ldq, fp_pipeline.io.wakeups[0].bits.uop.uses_ldq connect fp_rename_stage.io.wakeups[0].bits.uop.mem_signed, fp_pipeline.io.wakeups[0].bits.uop.mem_signed connect fp_rename_stage.io.wakeups[0].bits.uop.mem_size, fp_pipeline.io.wakeups[0].bits.uop.mem_size connect fp_rename_stage.io.wakeups[0].bits.uop.mem_cmd, fp_pipeline.io.wakeups[0].bits.uop.mem_cmd connect fp_rename_stage.io.wakeups[0].bits.uop.exc_cause, fp_pipeline.io.wakeups[0].bits.uop.exc_cause connect fp_rename_stage.io.wakeups[0].bits.uop.exception, fp_pipeline.io.wakeups[0].bits.uop.exception connect fp_rename_stage.io.wakeups[0].bits.uop.stale_pdst, fp_pipeline.io.wakeups[0].bits.uop.stale_pdst connect fp_rename_stage.io.wakeups[0].bits.uop.ppred_busy, fp_pipeline.io.wakeups[0].bits.uop.ppred_busy connect fp_rename_stage.io.wakeups[0].bits.uop.prs3_busy, fp_pipeline.io.wakeups[0].bits.uop.prs3_busy connect fp_rename_stage.io.wakeups[0].bits.uop.prs2_busy, fp_pipeline.io.wakeups[0].bits.uop.prs2_busy connect fp_rename_stage.io.wakeups[0].bits.uop.prs1_busy, fp_pipeline.io.wakeups[0].bits.uop.prs1_busy connect fp_rename_stage.io.wakeups[0].bits.uop.ppred, fp_pipeline.io.wakeups[0].bits.uop.ppred connect fp_rename_stage.io.wakeups[0].bits.uop.prs3, fp_pipeline.io.wakeups[0].bits.uop.prs3 connect fp_rename_stage.io.wakeups[0].bits.uop.prs2, fp_pipeline.io.wakeups[0].bits.uop.prs2 connect fp_rename_stage.io.wakeups[0].bits.uop.prs1, fp_pipeline.io.wakeups[0].bits.uop.prs1 connect fp_rename_stage.io.wakeups[0].bits.uop.pdst, fp_pipeline.io.wakeups[0].bits.uop.pdst connect fp_rename_stage.io.wakeups[0].bits.uop.rxq_idx, fp_pipeline.io.wakeups[0].bits.uop.rxq_idx connect fp_rename_stage.io.wakeups[0].bits.uop.stq_idx, fp_pipeline.io.wakeups[0].bits.uop.stq_idx connect fp_rename_stage.io.wakeups[0].bits.uop.ldq_idx, fp_pipeline.io.wakeups[0].bits.uop.ldq_idx connect fp_rename_stage.io.wakeups[0].bits.uop.rob_idx, fp_pipeline.io.wakeups[0].bits.uop.rob_idx connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.vec, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.vec connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.wflags, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.wflags connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.sqrt, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.sqrt connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.div, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.div connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.fma, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.fma connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.fastpipe, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.fastpipe connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.toint, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.toint connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.fromint, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.fromint connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.typeTagOut, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.typeTagOut connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.typeTagIn, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.typeTagIn connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.swap23, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.swap23 connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.swap12, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.swap12 connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ren3, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.ren3 connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ren2, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.ren2 connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ren1, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.ren1 connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.wen, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.wen connect fp_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ldst, fp_pipeline.io.wakeups[0].bits.uop.fp_ctrl.ldst connect fp_rename_stage.io.wakeups[0].bits.uop.op2_sel, fp_pipeline.io.wakeups[0].bits.uop.op2_sel connect fp_rename_stage.io.wakeups[0].bits.uop.op1_sel, fp_pipeline.io.wakeups[0].bits.uop.op1_sel connect fp_rename_stage.io.wakeups[0].bits.uop.imm_packed, fp_pipeline.io.wakeups[0].bits.uop.imm_packed connect fp_rename_stage.io.wakeups[0].bits.uop.pimm, fp_pipeline.io.wakeups[0].bits.uop.pimm connect fp_rename_stage.io.wakeups[0].bits.uop.imm_sel, fp_pipeline.io.wakeups[0].bits.uop.imm_sel connect fp_rename_stage.io.wakeups[0].bits.uop.imm_rename, fp_pipeline.io.wakeups[0].bits.uop.imm_rename connect fp_rename_stage.io.wakeups[0].bits.uop.taken, fp_pipeline.io.wakeups[0].bits.uop.taken connect fp_rename_stage.io.wakeups[0].bits.uop.pc_lob, fp_pipeline.io.wakeups[0].bits.uop.pc_lob connect fp_rename_stage.io.wakeups[0].bits.uop.edge_inst, fp_pipeline.io.wakeups[0].bits.uop.edge_inst connect fp_rename_stage.io.wakeups[0].bits.uop.ftq_idx, fp_pipeline.io.wakeups[0].bits.uop.ftq_idx connect fp_rename_stage.io.wakeups[0].bits.uop.is_mov, fp_pipeline.io.wakeups[0].bits.uop.is_mov connect fp_rename_stage.io.wakeups[0].bits.uop.is_rocc, fp_pipeline.io.wakeups[0].bits.uop.is_rocc connect fp_rename_stage.io.wakeups[0].bits.uop.is_sys_pc2epc, fp_pipeline.io.wakeups[0].bits.uop.is_sys_pc2epc connect fp_rename_stage.io.wakeups[0].bits.uop.is_eret, fp_pipeline.io.wakeups[0].bits.uop.is_eret connect fp_rename_stage.io.wakeups[0].bits.uop.is_amo, fp_pipeline.io.wakeups[0].bits.uop.is_amo connect fp_rename_stage.io.wakeups[0].bits.uop.is_sfence, fp_pipeline.io.wakeups[0].bits.uop.is_sfence connect fp_rename_stage.io.wakeups[0].bits.uop.is_fencei, fp_pipeline.io.wakeups[0].bits.uop.is_fencei connect fp_rename_stage.io.wakeups[0].bits.uop.is_fence, fp_pipeline.io.wakeups[0].bits.uop.is_fence connect fp_rename_stage.io.wakeups[0].bits.uop.is_sfb, fp_pipeline.io.wakeups[0].bits.uop.is_sfb connect fp_rename_stage.io.wakeups[0].bits.uop.br_type, fp_pipeline.io.wakeups[0].bits.uop.br_type connect fp_rename_stage.io.wakeups[0].bits.uop.br_tag, fp_pipeline.io.wakeups[0].bits.uop.br_tag connect fp_rename_stage.io.wakeups[0].bits.uop.br_mask, fp_pipeline.io.wakeups[0].bits.uop.br_mask connect fp_rename_stage.io.wakeups[0].bits.uop.dis_col_sel, fp_pipeline.io.wakeups[0].bits.uop.dis_col_sel connect fp_rename_stage.io.wakeups[0].bits.uop.iw_p3_bypass_hint, fp_pipeline.io.wakeups[0].bits.uop.iw_p3_bypass_hint connect fp_rename_stage.io.wakeups[0].bits.uop.iw_p2_bypass_hint, fp_pipeline.io.wakeups[0].bits.uop.iw_p2_bypass_hint connect fp_rename_stage.io.wakeups[0].bits.uop.iw_p1_bypass_hint, fp_pipeline.io.wakeups[0].bits.uop.iw_p1_bypass_hint connect fp_rename_stage.io.wakeups[0].bits.uop.iw_p2_speculative_child, fp_pipeline.io.wakeups[0].bits.uop.iw_p2_speculative_child connect fp_rename_stage.io.wakeups[0].bits.uop.iw_p1_speculative_child, fp_pipeline.io.wakeups[0].bits.uop.iw_p1_speculative_child connect fp_rename_stage.io.wakeups[0].bits.uop.iw_issued_partial_dgen, fp_pipeline.io.wakeups[0].bits.uop.iw_issued_partial_dgen connect fp_rename_stage.io.wakeups[0].bits.uop.iw_issued_partial_agen, fp_pipeline.io.wakeups[0].bits.uop.iw_issued_partial_agen connect fp_rename_stage.io.wakeups[0].bits.uop.iw_issued, fp_pipeline.io.wakeups[0].bits.uop.iw_issued connect fp_rename_stage.io.wakeups[0].bits.uop.fu_code[0], fp_pipeline.io.wakeups[0].bits.uop.fu_code[0] connect fp_rename_stage.io.wakeups[0].bits.uop.fu_code[1], fp_pipeline.io.wakeups[0].bits.uop.fu_code[1] connect fp_rename_stage.io.wakeups[0].bits.uop.fu_code[2], fp_pipeline.io.wakeups[0].bits.uop.fu_code[2] connect fp_rename_stage.io.wakeups[0].bits.uop.fu_code[3], fp_pipeline.io.wakeups[0].bits.uop.fu_code[3] connect fp_rename_stage.io.wakeups[0].bits.uop.fu_code[4], fp_pipeline.io.wakeups[0].bits.uop.fu_code[4] connect fp_rename_stage.io.wakeups[0].bits.uop.fu_code[5], fp_pipeline.io.wakeups[0].bits.uop.fu_code[5] connect fp_rename_stage.io.wakeups[0].bits.uop.fu_code[6], fp_pipeline.io.wakeups[0].bits.uop.fu_code[6] connect fp_rename_stage.io.wakeups[0].bits.uop.fu_code[7], fp_pipeline.io.wakeups[0].bits.uop.fu_code[7] connect fp_rename_stage.io.wakeups[0].bits.uop.fu_code[8], fp_pipeline.io.wakeups[0].bits.uop.fu_code[8] connect fp_rename_stage.io.wakeups[0].bits.uop.fu_code[9], fp_pipeline.io.wakeups[0].bits.uop.fu_code[9] connect fp_rename_stage.io.wakeups[0].bits.uop.iq_type[0], fp_pipeline.io.wakeups[0].bits.uop.iq_type[0] connect fp_rename_stage.io.wakeups[0].bits.uop.iq_type[1], fp_pipeline.io.wakeups[0].bits.uop.iq_type[1] connect fp_rename_stage.io.wakeups[0].bits.uop.iq_type[2], fp_pipeline.io.wakeups[0].bits.uop.iq_type[2] connect fp_rename_stage.io.wakeups[0].bits.uop.iq_type[3], fp_pipeline.io.wakeups[0].bits.uop.iq_type[3] connect fp_rename_stage.io.wakeups[0].bits.uop.debug_pc, fp_pipeline.io.wakeups[0].bits.uop.debug_pc connect fp_rename_stage.io.wakeups[0].bits.uop.is_rvc, fp_pipeline.io.wakeups[0].bits.uop.is_rvc connect fp_rename_stage.io.wakeups[0].bits.uop.debug_inst, fp_pipeline.io.wakeups[0].bits.uop.debug_inst connect fp_rename_stage.io.wakeups[0].bits.uop.inst, fp_pipeline.io.wakeups[0].bits.uop.inst connect fp_rename_stage.io.wakeups[0].valid, fp_pipeline.io.wakeups[0].valid connect fp_rename_stage.io.wakeups[1].bits.rebusy, fp_pipeline.io.wakeups[1].bits.rebusy connect fp_rename_stage.io.wakeups[1].bits.speculative_mask, fp_pipeline.io.wakeups[1].bits.speculative_mask connect fp_rename_stage.io.wakeups[1].bits.bypassable, fp_pipeline.io.wakeups[1].bits.bypassable connect fp_rename_stage.io.wakeups[1].bits.uop.debug_tsrc, fp_pipeline.io.wakeups[1].bits.uop.debug_tsrc connect fp_rename_stage.io.wakeups[1].bits.uop.debug_fsrc, fp_pipeline.io.wakeups[1].bits.uop.debug_fsrc connect fp_rename_stage.io.wakeups[1].bits.uop.bp_xcpt_if, fp_pipeline.io.wakeups[1].bits.uop.bp_xcpt_if connect fp_rename_stage.io.wakeups[1].bits.uop.bp_debug_if, fp_pipeline.io.wakeups[1].bits.uop.bp_debug_if connect fp_rename_stage.io.wakeups[1].bits.uop.xcpt_ma_if, fp_pipeline.io.wakeups[1].bits.uop.xcpt_ma_if connect fp_rename_stage.io.wakeups[1].bits.uop.xcpt_ae_if, fp_pipeline.io.wakeups[1].bits.uop.xcpt_ae_if connect fp_rename_stage.io.wakeups[1].bits.uop.xcpt_pf_if, fp_pipeline.io.wakeups[1].bits.uop.xcpt_pf_if connect fp_rename_stage.io.wakeups[1].bits.uop.fp_typ, fp_pipeline.io.wakeups[1].bits.uop.fp_typ connect fp_rename_stage.io.wakeups[1].bits.uop.fp_rm, fp_pipeline.io.wakeups[1].bits.uop.fp_rm connect fp_rename_stage.io.wakeups[1].bits.uop.fp_val, fp_pipeline.io.wakeups[1].bits.uop.fp_val connect fp_rename_stage.io.wakeups[1].bits.uop.fcn_op, fp_pipeline.io.wakeups[1].bits.uop.fcn_op connect fp_rename_stage.io.wakeups[1].bits.uop.fcn_dw, fp_pipeline.io.wakeups[1].bits.uop.fcn_dw connect fp_rename_stage.io.wakeups[1].bits.uop.frs3_en, fp_pipeline.io.wakeups[1].bits.uop.frs3_en connect fp_rename_stage.io.wakeups[1].bits.uop.lrs2_rtype, fp_pipeline.io.wakeups[1].bits.uop.lrs2_rtype connect fp_rename_stage.io.wakeups[1].bits.uop.lrs1_rtype, fp_pipeline.io.wakeups[1].bits.uop.lrs1_rtype connect fp_rename_stage.io.wakeups[1].bits.uop.dst_rtype, fp_pipeline.io.wakeups[1].bits.uop.dst_rtype connect fp_rename_stage.io.wakeups[1].bits.uop.lrs3, fp_pipeline.io.wakeups[1].bits.uop.lrs3 connect fp_rename_stage.io.wakeups[1].bits.uop.lrs2, fp_pipeline.io.wakeups[1].bits.uop.lrs2 connect fp_rename_stage.io.wakeups[1].bits.uop.lrs1, fp_pipeline.io.wakeups[1].bits.uop.lrs1 connect fp_rename_stage.io.wakeups[1].bits.uop.ldst, fp_pipeline.io.wakeups[1].bits.uop.ldst connect fp_rename_stage.io.wakeups[1].bits.uop.ldst_is_rs1, fp_pipeline.io.wakeups[1].bits.uop.ldst_is_rs1 connect fp_rename_stage.io.wakeups[1].bits.uop.csr_cmd, fp_pipeline.io.wakeups[1].bits.uop.csr_cmd connect fp_rename_stage.io.wakeups[1].bits.uop.flush_on_commit, fp_pipeline.io.wakeups[1].bits.uop.flush_on_commit connect fp_rename_stage.io.wakeups[1].bits.uop.is_unique, fp_pipeline.io.wakeups[1].bits.uop.is_unique connect fp_rename_stage.io.wakeups[1].bits.uop.uses_stq, fp_pipeline.io.wakeups[1].bits.uop.uses_stq connect fp_rename_stage.io.wakeups[1].bits.uop.uses_ldq, fp_pipeline.io.wakeups[1].bits.uop.uses_ldq connect fp_rename_stage.io.wakeups[1].bits.uop.mem_signed, fp_pipeline.io.wakeups[1].bits.uop.mem_signed connect fp_rename_stage.io.wakeups[1].bits.uop.mem_size, fp_pipeline.io.wakeups[1].bits.uop.mem_size connect fp_rename_stage.io.wakeups[1].bits.uop.mem_cmd, fp_pipeline.io.wakeups[1].bits.uop.mem_cmd connect fp_rename_stage.io.wakeups[1].bits.uop.exc_cause, fp_pipeline.io.wakeups[1].bits.uop.exc_cause connect fp_rename_stage.io.wakeups[1].bits.uop.exception, fp_pipeline.io.wakeups[1].bits.uop.exception connect fp_rename_stage.io.wakeups[1].bits.uop.stale_pdst, fp_pipeline.io.wakeups[1].bits.uop.stale_pdst connect fp_rename_stage.io.wakeups[1].bits.uop.ppred_busy, fp_pipeline.io.wakeups[1].bits.uop.ppred_busy connect fp_rename_stage.io.wakeups[1].bits.uop.prs3_busy, fp_pipeline.io.wakeups[1].bits.uop.prs3_busy connect fp_rename_stage.io.wakeups[1].bits.uop.prs2_busy, fp_pipeline.io.wakeups[1].bits.uop.prs2_busy connect fp_rename_stage.io.wakeups[1].bits.uop.prs1_busy, fp_pipeline.io.wakeups[1].bits.uop.prs1_busy connect fp_rename_stage.io.wakeups[1].bits.uop.ppred, fp_pipeline.io.wakeups[1].bits.uop.ppred connect fp_rename_stage.io.wakeups[1].bits.uop.prs3, fp_pipeline.io.wakeups[1].bits.uop.prs3 connect fp_rename_stage.io.wakeups[1].bits.uop.prs2, fp_pipeline.io.wakeups[1].bits.uop.prs2 connect fp_rename_stage.io.wakeups[1].bits.uop.prs1, fp_pipeline.io.wakeups[1].bits.uop.prs1 connect fp_rename_stage.io.wakeups[1].bits.uop.pdst, fp_pipeline.io.wakeups[1].bits.uop.pdst connect fp_rename_stage.io.wakeups[1].bits.uop.rxq_idx, fp_pipeline.io.wakeups[1].bits.uop.rxq_idx connect fp_rename_stage.io.wakeups[1].bits.uop.stq_idx, fp_pipeline.io.wakeups[1].bits.uop.stq_idx connect fp_rename_stage.io.wakeups[1].bits.uop.ldq_idx, fp_pipeline.io.wakeups[1].bits.uop.ldq_idx connect fp_rename_stage.io.wakeups[1].bits.uop.rob_idx, fp_pipeline.io.wakeups[1].bits.uop.rob_idx connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.vec, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.vec connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.wflags, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.wflags connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.sqrt, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.sqrt connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.div, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.div connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.fma, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.fma connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.fastpipe, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.fastpipe connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.toint, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.toint connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.fromint, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.fromint connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.typeTagOut, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.typeTagOut connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.typeTagIn, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.typeTagIn connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.swap23, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.swap23 connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.swap12, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.swap12 connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.ren3, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.ren3 connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.ren2, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.ren2 connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.ren1, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.ren1 connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.wen, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.wen connect fp_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.ldst, fp_pipeline.io.wakeups[1].bits.uop.fp_ctrl.ldst connect fp_rename_stage.io.wakeups[1].bits.uop.op2_sel, fp_pipeline.io.wakeups[1].bits.uop.op2_sel connect fp_rename_stage.io.wakeups[1].bits.uop.op1_sel, fp_pipeline.io.wakeups[1].bits.uop.op1_sel connect fp_rename_stage.io.wakeups[1].bits.uop.imm_packed, fp_pipeline.io.wakeups[1].bits.uop.imm_packed connect fp_rename_stage.io.wakeups[1].bits.uop.pimm, fp_pipeline.io.wakeups[1].bits.uop.pimm connect fp_rename_stage.io.wakeups[1].bits.uop.imm_sel, fp_pipeline.io.wakeups[1].bits.uop.imm_sel connect fp_rename_stage.io.wakeups[1].bits.uop.imm_rename, fp_pipeline.io.wakeups[1].bits.uop.imm_rename connect fp_rename_stage.io.wakeups[1].bits.uop.taken, fp_pipeline.io.wakeups[1].bits.uop.taken connect fp_rename_stage.io.wakeups[1].bits.uop.pc_lob, fp_pipeline.io.wakeups[1].bits.uop.pc_lob connect fp_rename_stage.io.wakeups[1].bits.uop.edge_inst, fp_pipeline.io.wakeups[1].bits.uop.edge_inst connect fp_rename_stage.io.wakeups[1].bits.uop.ftq_idx, fp_pipeline.io.wakeups[1].bits.uop.ftq_idx connect fp_rename_stage.io.wakeups[1].bits.uop.is_mov, fp_pipeline.io.wakeups[1].bits.uop.is_mov connect fp_rename_stage.io.wakeups[1].bits.uop.is_rocc, fp_pipeline.io.wakeups[1].bits.uop.is_rocc connect fp_rename_stage.io.wakeups[1].bits.uop.is_sys_pc2epc, fp_pipeline.io.wakeups[1].bits.uop.is_sys_pc2epc connect fp_rename_stage.io.wakeups[1].bits.uop.is_eret, fp_pipeline.io.wakeups[1].bits.uop.is_eret connect fp_rename_stage.io.wakeups[1].bits.uop.is_amo, fp_pipeline.io.wakeups[1].bits.uop.is_amo connect fp_rename_stage.io.wakeups[1].bits.uop.is_sfence, fp_pipeline.io.wakeups[1].bits.uop.is_sfence connect fp_rename_stage.io.wakeups[1].bits.uop.is_fencei, fp_pipeline.io.wakeups[1].bits.uop.is_fencei connect fp_rename_stage.io.wakeups[1].bits.uop.is_fence, fp_pipeline.io.wakeups[1].bits.uop.is_fence connect fp_rename_stage.io.wakeups[1].bits.uop.is_sfb, fp_pipeline.io.wakeups[1].bits.uop.is_sfb connect fp_rename_stage.io.wakeups[1].bits.uop.br_type, fp_pipeline.io.wakeups[1].bits.uop.br_type connect fp_rename_stage.io.wakeups[1].bits.uop.br_tag, fp_pipeline.io.wakeups[1].bits.uop.br_tag connect fp_rename_stage.io.wakeups[1].bits.uop.br_mask, fp_pipeline.io.wakeups[1].bits.uop.br_mask connect fp_rename_stage.io.wakeups[1].bits.uop.dis_col_sel, fp_pipeline.io.wakeups[1].bits.uop.dis_col_sel connect fp_rename_stage.io.wakeups[1].bits.uop.iw_p3_bypass_hint, fp_pipeline.io.wakeups[1].bits.uop.iw_p3_bypass_hint connect fp_rename_stage.io.wakeups[1].bits.uop.iw_p2_bypass_hint, fp_pipeline.io.wakeups[1].bits.uop.iw_p2_bypass_hint connect fp_rename_stage.io.wakeups[1].bits.uop.iw_p1_bypass_hint, fp_pipeline.io.wakeups[1].bits.uop.iw_p1_bypass_hint connect fp_rename_stage.io.wakeups[1].bits.uop.iw_p2_speculative_child, fp_pipeline.io.wakeups[1].bits.uop.iw_p2_speculative_child connect fp_rename_stage.io.wakeups[1].bits.uop.iw_p1_speculative_child, fp_pipeline.io.wakeups[1].bits.uop.iw_p1_speculative_child connect fp_rename_stage.io.wakeups[1].bits.uop.iw_issued_partial_dgen, fp_pipeline.io.wakeups[1].bits.uop.iw_issued_partial_dgen connect fp_rename_stage.io.wakeups[1].bits.uop.iw_issued_partial_agen, fp_pipeline.io.wakeups[1].bits.uop.iw_issued_partial_agen connect fp_rename_stage.io.wakeups[1].bits.uop.iw_issued, fp_pipeline.io.wakeups[1].bits.uop.iw_issued connect fp_rename_stage.io.wakeups[1].bits.uop.fu_code[0], fp_pipeline.io.wakeups[1].bits.uop.fu_code[0] connect fp_rename_stage.io.wakeups[1].bits.uop.fu_code[1], fp_pipeline.io.wakeups[1].bits.uop.fu_code[1] connect fp_rename_stage.io.wakeups[1].bits.uop.fu_code[2], fp_pipeline.io.wakeups[1].bits.uop.fu_code[2] connect fp_rename_stage.io.wakeups[1].bits.uop.fu_code[3], fp_pipeline.io.wakeups[1].bits.uop.fu_code[3] connect fp_rename_stage.io.wakeups[1].bits.uop.fu_code[4], fp_pipeline.io.wakeups[1].bits.uop.fu_code[4] connect fp_rename_stage.io.wakeups[1].bits.uop.fu_code[5], fp_pipeline.io.wakeups[1].bits.uop.fu_code[5] connect fp_rename_stage.io.wakeups[1].bits.uop.fu_code[6], fp_pipeline.io.wakeups[1].bits.uop.fu_code[6] connect fp_rename_stage.io.wakeups[1].bits.uop.fu_code[7], fp_pipeline.io.wakeups[1].bits.uop.fu_code[7] connect fp_rename_stage.io.wakeups[1].bits.uop.fu_code[8], fp_pipeline.io.wakeups[1].bits.uop.fu_code[8] connect fp_rename_stage.io.wakeups[1].bits.uop.fu_code[9], fp_pipeline.io.wakeups[1].bits.uop.fu_code[9] connect fp_rename_stage.io.wakeups[1].bits.uop.iq_type[0], fp_pipeline.io.wakeups[1].bits.uop.iq_type[0] connect fp_rename_stage.io.wakeups[1].bits.uop.iq_type[1], fp_pipeline.io.wakeups[1].bits.uop.iq_type[1] connect fp_rename_stage.io.wakeups[1].bits.uop.iq_type[2], fp_pipeline.io.wakeups[1].bits.uop.iq_type[2] connect fp_rename_stage.io.wakeups[1].bits.uop.iq_type[3], fp_pipeline.io.wakeups[1].bits.uop.iq_type[3] connect fp_rename_stage.io.wakeups[1].bits.uop.debug_pc, fp_pipeline.io.wakeups[1].bits.uop.debug_pc connect fp_rename_stage.io.wakeups[1].bits.uop.is_rvc, fp_pipeline.io.wakeups[1].bits.uop.is_rvc connect fp_rename_stage.io.wakeups[1].bits.uop.debug_inst, fp_pipeline.io.wakeups[1].bits.uop.debug_inst connect fp_rename_stage.io.wakeups[1].bits.uop.inst, fp_pipeline.io.wakeups[1].bits.uop.inst connect fp_rename_stage.io.wakeups[1].valid, fp_pipeline.io.wakeups[1].valid connect pred_rename_stage.io.wakeups[0].bits.rebusy, pred_wakeup.bits.rebusy connect pred_rename_stage.io.wakeups[0].bits.speculative_mask, pred_wakeup.bits.speculative_mask connect pred_rename_stage.io.wakeups[0].bits.bypassable, pred_wakeup.bits.bypassable connect pred_rename_stage.io.wakeups[0].bits.uop.debug_tsrc, pred_wakeup.bits.uop.debug_tsrc connect pred_rename_stage.io.wakeups[0].bits.uop.debug_fsrc, pred_wakeup.bits.uop.debug_fsrc connect pred_rename_stage.io.wakeups[0].bits.uop.bp_xcpt_if, pred_wakeup.bits.uop.bp_xcpt_if connect pred_rename_stage.io.wakeups[0].bits.uop.bp_debug_if, pred_wakeup.bits.uop.bp_debug_if connect pred_rename_stage.io.wakeups[0].bits.uop.xcpt_ma_if, pred_wakeup.bits.uop.xcpt_ma_if connect pred_rename_stage.io.wakeups[0].bits.uop.xcpt_ae_if, pred_wakeup.bits.uop.xcpt_ae_if connect pred_rename_stage.io.wakeups[0].bits.uop.xcpt_pf_if, pred_wakeup.bits.uop.xcpt_pf_if connect pred_rename_stage.io.wakeups[0].bits.uop.fp_typ, pred_wakeup.bits.uop.fp_typ connect pred_rename_stage.io.wakeups[0].bits.uop.fp_rm, pred_wakeup.bits.uop.fp_rm connect pred_rename_stage.io.wakeups[0].bits.uop.fp_val, pred_wakeup.bits.uop.fp_val connect pred_rename_stage.io.wakeups[0].bits.uop.fcn_op, pred_wakeup.bits.uop.fcn_op connect pred_rename_stage.io.wakeups[0].bits.uop.fcn_dw, pred_wakeup.bits.uop.fcn_dw connect pred_rename_stage.io.wakeups[0].bits.uop.frs3_en, pred_wakeup.bits.uop.frs3_en connect pred_rename_stage.io.wakeups[0].bits.uop.lrs2_rtype, pred_wakeup.bits.uop.lrs2_rtype connect pred_rename_stage.io.wakeups[0].bits.uop.lrs1_rtype, pred_wakeup.bits.uop.lrs1_rtype connect pred_rename_stage.io.wakeups[0].bits.uop.dst_rtype, pred_wakeup.bits.uop.dst_rtype connect pred_rename_stage.io.wakeups[0].bits.uop.lrs3, pred_wakeup.bits.uop.lrs3 connect pred_rename_stage.io.wakeups[0].bits.uop.lrs2, pred_wakeup.bits.uop.lrs2 connect pred_rename_stage.io.wakeups[0].bits.uop.lrs1, pred_wakeup.bits.uop.lrs1 connect pred_rename_stage.io.wakeups[0].bits.uop.ldst, pred_wakeup.bits.uop.ldst connect pred_rename_stage.io.wakeups[0].bits.uop.ldst_is_rs1, pred_wakeup.bits.uop.ldst_is_rs1 connect pred_rename_stage.io.wakeups[0].bits.uop.csr_cmd, pred_wakeup.bits.uop.csr_cmd connect pred_rename_stage.io.wakeups[0].bits.uop.flush_on_commit, pred_wakeup.bits.uop.flush_on_commit connect pred_rename_stage.io.wakeups[0].bits.uop.is_unique, pred_wakeup.bits.uop.is_unique connect pred_rename_stage.io.wakeups[0].bits.uop.uses_stq, pred_wakeup.bits.uop.uses_stq connect pred_rename_stage.io.wakeups[0].bits.uop.uses_ldq, pred_wakeup.bits.uop.uses_ldq connect pred_rename_stage.io.wakeups[0].bits.uop.mem_signed, pred_wakeup.bits.uop.mem_signed connect pred_rename_stage.io.wakeups[0].bits.uop.mem_size, pred_wakeup.bits.uop.mem_size connect pred_rename_stage.io.wakeups[0].bits.uop.mem_cmd, pred_wakeup.bits.uop.mem_cmd connect pred_rename_stage.io.wakeups[0].bits.uop.exc_cause, pred_wakeup.bits.uop.exc_cause connect pred_rename_stage.io.wakeups[0].bits.uop.exception, pred_wakeup.bits.uop.exception connect pred_rename_stage.io.wakeups[0].bits.uop.stale_pdst, pred_wakeup.bits.uop.stale_pdst connect pred_rename_stage.io.wakeups[0].bits.uop.ppred_busy, pred_wakeup.bits.uop.ppred_busy connect pred_rename_stage.io.wakeups[0].bits.uop.prs3_busy, pred_wakeup.bits.uop.prs3_busy connect pred_rename_stage.io.wakeups[0].bits.uop.prs2_busy, pred_wakeup.bits.uop.prs2_busy connect pred_rename_stage.io.wakeups[0].bits.uop.prs1_busy, pred_wakeup.bits.uop.prs1_busy connect pred_rename_stage.io.wakeups[0].bits.uop.ppred, pred_wakeup.bits.uop.ppred connect pred_rename_stage.io.wakeups[0].bits.uop.prs3, pred_wakeup.bits.uop.prs3 connect pred_rename_stage.io.wakeups[0].bits.uop.prs2, pred_wakeup.bits.uop.prs2 connect pred_rename_stage.io.wakeups[0].bits.uop.prs1, pred_wakeup.bits.uop.prs1 connect pred_rename_stage.io.wakeups[0].bits.uop.pdst, pred_wakeup.bits.uop.pdst connect pred_rename_stage.io.wakeups[0].bits.uop.rxq_idx, pred_wakeup.bits.uop.rxq_idx connect pred_rename_stage.io.wakeups[0].bits.uop.stq_idx, pred_wakeup.bits.uop.stq_idx connect pred_rename_stage.io.wakeups[0].bits.uop.ldq_idx, pred_wakeup.bits.uop.ldq_idx connect pred_rename_stage.io.wakeups[0].bits.uop.rob_idx, pred_wakeup.bits.uop.rob_idx connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.vec, pred_wakeup.bits.uop.fp_ctrl.vec connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.wflags, pred_wakeup.bits.uop.fp_ctrl.wflags connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.sqrt, pred_wakeup.bits.uop.fp_ctrl.sqrt connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.div, pred_wakeup.bits.uop.fp_ctrl.div connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.fma, pred_wakeup.bits.uop.fp_ctrl.fma connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.fastpipe, pred_wakeup.bits.uop.fp_ctrl.fastpipe connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.toint, pred_wakeup.bits.uop.fp_ctrl.toint connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.fromint, pred_wakeup.bits.uop.fp_ctrl.fromint connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.typeTagOut, pred_wakeup.bits.uop.fp_ctrl.typeTagOut connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.typeTagIn, pred_wakeup.bits.uop.fp_ctrl.typeTagIn connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.swap23, pred_wakeup.bits.uop.fp_ctrl.swap23 connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.swap12, pred_wakeup.bits.uop.fp_ctrl.swap12 connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ren3, pred_wakeup.bits.uop.fp_ctrl.ren3 connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ren2, pred_wakeup.bits.uop.fp_ctrl.ren2 connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ren1, pred_wakeup.bits.uop.fp_ctrl.ren1 connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.wen, pred_wakeup.bits.uop.fp_ctrl.wen connect pred_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ldst, pred_wakeup.bits.uop.fp_ctrl.ldst connect pred_rename_stage.io.wakeups[0].bits.uop.op2_sel, pred_wakeup.bits.uop.op2_sel connect pred_rename_stage.io.wakeups[0].bits.uop.op1_sel, pred_wakeup.bits.uop.op1_sel connect pred_rename_stage.io.wakeups[0].bits.uop.imm_packed, pred_wakeup.bits.uop.imm_packed connect pred_rename_stage.io.wakeups[0].bits.uop.pimm, pred_wakeup.bits.uop.pimm connect pred_rename_stage.io.wakeups[0].bits.uop.imm_sel, pred_wakeup.bits.uop.imm_sel connect pred_rename_stage.io.wakeups[0].bits.uop.imm_rename, pred_wakeup.bits.uop.imm_rename connect pred_rename_stage.io.wakeups[0].bits.uop.taken, pred_wakeup.bits.uop.taken connect pred_rename_stage.io.wakeups[0].bits.uop.pc_lob, pred_wakeup.bits.uop.pc_lob connect pred_rename_stage.io.wakeups[0].bits.uop.edge_inst, pred_wakeup.bits.uop.edge_inst connect pred_rename_stage.io.wakeups[0].bits.uop.ftq_idx, pred_wakeup.bits.uop.ftq_idx connect pred_rename_stage.io.wakeups[0].bits.uop.is_mov, pred_wakeup.bits.uop.is_mov connect pred_rename_stage.io.wakeups[0].bits.uop.is_rocc, pred_wakeup.bits.uop.is_rocc connect pred_rename_stage.io.wakeups[0].bits.uop.is_sys_pc2epc, pred_wakeup.bits.uop.is_sys_pc2epc connect pred_rename_stage.io.wakeups[0].bits.uop.is_eret, pred_wakeup.bits.uop.is_eret connect pred_rename_stage.io.wakeups[0].bits.uop.is_amo, pred_wakeup.bits.uop.is_amo connect pred_rename_stage.io.wakeups[0].bits.uop.is_sfence, pred_wakeup.bits.uop.is_sfence connect pred_rename_stage.io.wakeups[0].bits.uop.is_fencei, pred_wakeup.bits.uop.is_fencei connect pred_rename_stage.io.wakeups[0].bits.uop.is_fence, pred_wakeup.bits.uop.is_fence connect pred_rename_stage.io.wakeups[0].bits.uop.is_sfb, pred_wakeup.bits.uop.is_sfb connect pred_rename_stage.io.wakeups[0].bits.uop.br_type, pred_wakeup.bits.uop.br_type connect pred_rename_stage.io.wakeups[0].bits.uop.br_tag, pred_wakeup.bits.uop.br_tag connect pred_rename_stage.io.wakeups[0].bits.uop.br_mask, pred_wakeup.bits.uop.br_mask connect pred_rename_stage.io.wakeups[0].bits.uop.dis_col_sel, pred_wakeup.bits.uop.dis_col_sel connect pred_rename_stage.io.wakeups[0].bits.uop.iw_p3_bypass_hint, pred_wakeup.bits.uop.iw_p3_bypass_hint connect pred_rename_stage.io.wakeups[0].bits.uop.iw_p2_bypass_hint, pred_wakeup.bits.uop.iw_p2_bypass_hint connect pred_rename_stage.io.wakeups[0].bits.uop.iw_p1_bypass_hint, pred_wakeup.bits.uop.iw_p1_bypass_hint connect pred_rename_stage.io.wakeups[0].bits.uop.iw_p2_speculative_child, pred_wakeup.bits.uop.iw_p2_speculative_child connect pred_rename_stage.io.wakeups[0].bits.uop.iw_p1_speculative_child, pred_wakeup.bits.uop.iw_p1_speculative_child connect pred_rename_stage.io.wakeups[0].bits.uop.iw_issued_partial_dgen, pred_wakeup.bits.uop.iw_issued_partial_dgen connect pred_rename_stage.io.wakeups[0].bits.uop.iw_issued_partial_agen, pred_wakeup.bits.uop.iw_issued_partial_agen connect pred_rename_stage.io.wakeups[0].bits.uop.iw_issued, pred_wakeup.bits.uop.iw_issued connect pred_rename_stage.io.wakeups[0].bits.uop.fu_code[0], pred_wakeup.bits.uop.fu_code[0] connect pred_rename_stage.io.wakeups[0].bits.uop.fu_code[1], pred_wakeup.bits.uop.fu_code[1] connect pred_rename_stage.io.wakeups[0].bits.uop.fu_code[2], pred_wakeup.bits.uop.fu_code[2] connect pred_rename_stage.io.wakeups[0].bits.uop.fu_code[3], pred_wakeup.bits.uop.fu_code[3] connect pred_rename_stage.io.wakeups[0].bits.uop.fu_code[4], pred_wakeup.bits.uop.fu_code[4] connect pred_rename_stage.io.wakeups[0].bits.uop.fu_code[5], pred_wakeup.bits.uop.fu_code[5] connect pred_rename_stage.io.wakeups[0].bits.uop.fu_code[6], pred_wakeup.bits.uop.fu_code[6] connect pred_rename_stage.io.wakeups[0].bits.uop.fu_code[7], pred_wakeup.bits.uop.fu_code[7] connect pred_rename_stage.io.wakeups[0].bits.uop.fu_code[8], pred_wakeup.bits.uop.fu_code[8] connect pred_rename_stage.io.wakeups[0].bits.uop.fu_code[9], pred_wakeup.bits.uop.fu_code[9] connect pred_rename_stage.io.wakeups[0].bits.uop.iq_type[0], pred_wakeup.bits.uop.iq_type[0] connect pred_rename_stage.io.wakeups[0].bits.uop.iq_type[1], pred_wakeup.bits.uop.iq_type[1] connect pred_rename_stage.io.wakeups[0].bits.uop.iq_type[2], pred_wakeup.bits.uop.iq_type[2] connect pred_rename_stage.io.wakeups[0].bits.uop.iq_type[3], pred_wakeup.bits.uop.iq_type[3] connect pred_rename_stage.io.wakeups[0].bits.uop.debug_pc, pred_wakeup.bits.uop.debug_pc connect pred_rename_stage.io.wakeups[0].bits.uop.is_rvc, pred_wakeup.bits.uop.is_rvc connect pred_rename_stage.io.wakeups[0].bits.uop.debug_inst, pred_wakeup.bits.uop.debug_inst connect pred_rename_stage.io.wakeups[0].bits.uop.inst, pred_wakeup.bits.uop.inst connect pred_rename_stage.io.wakeups[0].valid, pred_wakeup.valid connect imm_rename_stage.io.wakeups[0].bits.rebusy, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.rebusy connect imm_rename_stage.io.wakeups[0].bits.speculative_mask, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.speculative_mask connect imm_rename_stage.io.wakeups[0].bits.bypassable, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.bypassable connect imm_rename_stage.io.wakeups[0].bits.uop.debug_tsrc, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_tsrc connect imm_rename_stage.io.wakeups[0].bits.uop.debug_fsrc, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_fsrc connect imm_rename_stage.io.wakeups[0].bits.uop.bp_xcpt_if, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.bp_xcpt_if connect imm_rename_stage.io.wakeups[0].bits.uop.bp_debug_if, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.bp_debug_if connect imm_rename_stage.io.wakeups[0].bits.uop.xcpt_ma_if, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.xcpt_ma_if connect imm_rename_stage.io.wakeups[0].bits.uop.xcpt_ae_if, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.xcpt_ae_if connect imm_rename_stage.io.wakeups[0].bits.uop.xcpt_pf_if, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.xcpt_pf_if connect imm_rename_stage.io.wakeups[0].bits.uop.fp_typ, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_typ connect imm_rename_stage.io.wakeups[0].bits.uop.fp_rm, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_rm connect imm_rename_stage.io.wakeups[0].bits.uop.fp_val, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_val connect imm_rename_stage.io.wakeups[0].bits.uop.fcn_op, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fcn_op connect imm_rename_stage.io.wakeups[0].bits.uop.fcn_dw, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fcn_dw connect imm_rename_stage.io.wakeups[0].bits.uop.frs3_en, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.frs3_en connect imm_rename_stage.io.wakeups[0].bits.uop.lrs2_rtype, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs2_rtype connect imm_rename_stage.io.wakeups[0].bits.uop.lrs1_rtype, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs1_rtype connect imm_rename_stage.io.wakeups[0].bits.uop.dst_rtype, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.dst_rtype connect imm_rename_stage.io.wakeups[0].bits.uop.lrs3, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs3 connect imm_rename_stage.io.wakeups[0].bits.uop.lrs2, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs2 connect imm_rename_stage.io.wakeups[0].bits.uop.lrs1, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs1 connect imm_rename_stage.io.wakeups[0].bits.uop.ldst, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ldst connect imm_rename_stage.io.wakeups[0].bits.uop.ldst_is_rs1, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ldst_is_rs1 connect imm_rename_stage.io.wakeups[0].bits.uop.csr_cmd, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.csr_cmd connect imm_rename_stage.io.wakeups[0].bits.uop.flush_on_commit, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.flush_on_commit connect imm_rename_stage.io.wakeups[0].bits.uop.is_unique, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_unique connect imm_rename_stage.io.wakeups[0].bits.uop.uses_stq, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.uses_stq connect imm_rename_stage.io.wakeups[0].bits.uop.uses_ldq, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.uses_ldq connect imm_rename_stage.io.wakeups[0].bits.uop.mem_signed, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.mem_signed connect imm_rename_stage.io.wakeups[0].bits.uop.mem_size, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.mem_size connect imm_rename_stage.io.wakeups[0].bits.uop.mem_cmd, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.mem_cmd connect imm_rename_stage.io.wakeups[0].bits.uop.exc_cause, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.exc_cause connect imm_rename_stage.io.wakeups[0].bits.uop.exception, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.exception connect imm_rename_stage.io.wakeups[0].bits.uop.stale_pdst, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.stale_pdst connect imm_rename_stage.io.wakeups[0].bits.uop.ppred_busy, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ppred_busy connect imm_rename_stage.io.wakeups[0].bits.uop.prs3_busy, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs3_busy connect imm_rename_stage.io.wakeups[0].bits.uop.prs2_busy, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs2_busy connect imm_rename_stage.io.wakeups[0].bits.uop.prs1_busy, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs1_busy connect imm_rename_stage.io.wakeups[0].bits.uop.ppred, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ppred connect imm_rename_stage.io.wakeups[0].bits.uop.prs3, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs3 connect imm_rename_stage.io.wakeups[0].bits.uop.prs2, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs2 connect imm_rename_stage.io.wakeups[0].bits.uop.prs1, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs1 connect imm_rename_stage.io.wakeups[0].bits.uop.pdst, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.pdst connect imm_rename_stage.io.wakeups[0].bits.uop.rxq_idx, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.rxq_idx connect imm_rename_stage.io.wakeups[0].bits.uop.stq_idx, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.stq_idx connect imm_rename_stage.io.wakeups[0].bits.uop.ldq_idx, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ldq_idx connect imm_rename_stage.io.wakeups[0].bits.uop.rob_idx, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.rob_idx connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.vec, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.vec connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.wflags, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.wflags connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.sqrt, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.sqrt connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.div, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.div connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.fma, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fma connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.fastpipe, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fastpipe connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.toint, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.toint connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.fromint, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fromint connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.typeTagOut, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.typeTagOut connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.typeTagIn, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.typeTagIn connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.swap23, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.swap23 connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.swap12, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.swap12 connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ren3, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren3 connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ren2, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren2 connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ren1, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren1 connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.wen, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.wen connect imm_rename_stage.io.wakeups[0].bits.uop.fp_ctrl.ldst, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ldst connect imm_rename_stage.io.wakeups[0].bits.uop.op2_sel, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.op2_sel connect imm_rename_stage.io.wakeups[0].bits.uop.op1_sel, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.op1_sel connect imm_rename_stage.io.wakeups[0].bits.uop.imm_packed, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.imm_packed connect imm_rename_stage.io.wakeups[0].bits.uop.pimm, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.pimm connect imm_rename_stage.io.wakeups[0].bits.uop.imm_sel, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.imm_sel connect imm_rename_stage.io.wakeups[0].bits.uop.imm_rename, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.imm_rename connect imm_rename_stage.io.wakeups[0].bits.uop.taken, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.taken connect imm_rename_stage.io.wakeups[0].bits.uop.pc_lob, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.pc_lob connect imm_rename_stage.io.wakeups[0].bits.uop.edge_inst, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.edge_inst connect imm_rename_stage.io.wakeups[0].bits.uop.ftq_idx, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ftq_idx connect imm_rename_stage.io.wakeups[0].bits.uop.is_mov, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_mov connect imm_rename_stage.io.wakeups[0].bits.uop.is_rocc, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_rocc connect imm_rename_stage.io.wakeups[0].bits.uop.is_sys_pc2epc, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_sys_pc2epc connect imm_rename_stage.io.wakeups[0].bits.uop.is_eret, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_eret connect imm_rename_stage.io.wakeups[0].bits.uop.is_amo, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_amo connect imm_rename_stage.io.wakeups[0].bits.uop.is_sfence, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_sfence connect imm_rename_stage.io.wakeups[0].bits.uop.is_fencei, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_fencei connect imm_rename_stage.io.wakeups[0].bits.uop.is_fence, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_fence connect imm_rename_stage.io.wakeups[0].bits.uop.is_sfb, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_sfb connect imm_rename_stage.io.wakeups[0].bits.uop.br_type, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.br_type connect imm_rename_stage.io.wakeups[0].bits.uop.br_tag, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.br_tag connect imm_rename_stage.io.wakeups[0].bits.uop.br_mask, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.br_mask connect imm_rename_stage.io.wakeups[0].bits.uop.dis_col_sel, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.dis_col_sel connect imm_rename_stage.io.wakeups[0].bits.uop.iw_p3_bypass_hint, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p3_bypass_hint connect imm_rename_stage.io.wakeups[0].bits.uop.iw_p2_bypass_hint, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p2_bypass_hint connect imm_rename_stage.io.wakeups[0].bits.uop.iw_p1_bypass_hint, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p1_bypass_hint connect imm_rename_stage.io.wakeups[0].bits.uop.iw_p2_speculative_child, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p2_speculative_child connect imm_rename_stage.io.wakeups[0].bits.uop.iw_p1_speculative_child, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p1_speculative_child connect imm_rename_stage.io.wakeups[0].bits.uop.iw_issued_partial_dgen, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_issued_partial_dgen connect imm_rename_stage.io.wakeups[0].bits.uop.iw_issued_partial_agen, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_issued_partial_agen connect imm_rename_stage.io.wakeups[0].bits.uop.iw_issued, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_issued connect imm_rename_stage.io.wakeups[0].bits.uop.fu_code[0], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[0] connect imm_rename_stage.io.wakeups[0].bits.uop.fu_code[1], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[1] connect imm_rename_stage.io.wakeups[0].bits.uop.fu_code[2], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[2] connect imm_rename_stage.io.wakeups[0].bits.uop.fu_code[3], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[3] connect imm_rename_stage.io.wakeups[0].bits.uop.fu_code[4], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[4] connect imm_rename_stage.io.wakeups[0].bits.uop.fu_code[5], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[5] connect imm_rename_stage.io.wakeups[0].bits.uop.fu_code[6], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[6] connect imm_rename_stage.io.wakeups[0].bits.uop.fu_code[7], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[7] connect imm_rename_stage.io.wakeups[0].bits.uop.fu_code[8], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[8] connect imm_rename_stage.io.wakeups[0].bits.uop.fu_code[9], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[9] connect imm_rename_stage.io.wakeups[0].bits.uop.iq_type[0], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[0] connect imm_rename_stage.io.wakeups[0].bits.uop.iq_type[1], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[1] connect imm_rename_stage.io.wakeups[0].bits.uop.iq_type[2], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[2] connect imm_rename_stage.io.wakeups[0].bits.uop.iq_type[3], alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[3] connect imm_rename_stage.io.wakeups[0].bits.uop.debug_pc, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_pc connect imm_rename_stage.io.wakeups[0].bits.uop.is_rvc, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_rvc connect imm_rename_stage.io.wakeups[0].bits.uop.debug_inst, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_inst connect imm_rename_stage.io.wakeups[0].bits.uop.inst, alu_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.inst connect imm_rename_stage.io.wakeups[0].valid, alu_exe_unit_0.io_rrd_immrf_wakeup.valid connect imm_rename_stage.io.wakeups[1].bits.rebusy, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.rebusy connect imm_rename_stage.io.wakeups[1].bits.speculative_mask, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.speculative_mask connect imm_rename_stage.io.wakeups[1].bits.bypassable, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.bypassable connect imm_rename_stage.io.wakeups[1].bits.uop.debug_tsrc, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.debug_tsrc connect imm_rename_stage.io.wakeups[1].bits.uop.debug_fsrc, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.debug_fsrc connect imm_rename_stage.io.wakeups[1].bits.uop.bp_xcpt_if, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.bp_xcpt_if connect imm_rename_stage.io.wakeups[1].bits.uop.bp_debug_if, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.bp_debug_if connect imm_rename_stage.io.wakeups[1].bits.uop.xcpt_ma_if, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.xcpt_ma_if connect imm_rename_stage.io.wakeups[1].bits.uop.xcpt_ae_if, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.xcpt_ae_if connect imm_rename_stage.io.wakeups[1].bits.uop.xcpt_pf_if, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.xcpt_pf_if connect imm_rename_stage.io.wakeups[1].bits.uop.fp_typ, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_typ connect imm_rename_stage.io.wakeups[1].bits.uop.fp_rm, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_rm connect imm_rename_stage.io.wakeups[1].bits.uop.fp_val, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_val connect imm_rename_stage.io.wakeups[1].bits.uop.fcn_op, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fcn_op connect imm_rename_stage.io.wakeups[1].bits.uop.fcn_dw, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fcn_dw connect imm_rename_stage.io.wakeups[1].bits.uop.frs3_en, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.frs3_en connect imm_rename_stage.io.wakeups[1].bits.uop.lrs2_rtype, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.lrs2_rtype connect imm_rename_stage.io.wakeups[1].bits.uop.lrs1_rtype, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.lrs1_rtype connect imm_rename_stage.io.wakeups[1].bits.uop.dst_rtype, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.dst_rtype connect imm_rename_stage.io.wakeups[1].bits.uop.lrs3, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.lrs3 connect imm_rename_stage.io.wakeups[1].bits.uop.lrs2, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.lrs2 connect imm_rename_stage.io.wakeups[1].bits.uop.lrs1, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.lrs1 connect imm_rename_stage.io.wakeups[1].bits.uop.ldst, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ldst connect imm_rename_stage.io.wakeups[1].bits.uop.ldst_is_rs1, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ldst_is_rs1 connect imm_rename_stage.io.wakeups[1].bits.uop.csr_cmd, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.csr_cmd connect imm_rename_stage.io.wakeups[1].bits.uop.flush_on_commit, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.flush_on_commit connect imm_rename_stage.io.wakeups[1].bits.uop.is_unique, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_unique connect imm_rename_stage.io.wakeups[1].bits.uop.uses_stq, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.uses_stq connect imm_rename_stage.io.wakeups[1].bits.uop.uses_ldq, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.uses_ldq connect imm_rename_stage.io.wakeups[1].bits.uop.mem_signed, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.mem_signed connect imm_rename_stage.io.wakeups[1].bits.uop.mem_size, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.mem_size connect imm_rename_stage.io.wakeups[1].bits.uop.mem_cmd, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.mem_cmd connect imm_rename_stage.io.wakeups[1].bits.uop.exc_cause, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.exc_cause connect imm_rename_stage.io.wakeups[1].bits.uop.exception, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.exception connect imm_rename_stage.io.wakeups[1].bits.uop.stale_pdst, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.stale_pdst connect imm_rename_stage.io.wakeups[1].bits.uop.ppred_busy, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ppred_busy connect imm_rename_stage.io.wakeups[1].bits.uop.prs3_busy, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs3_busy connect imm_rename_stage.io.wakeups[1].bits.uop.prs2_busy, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs2_busy connect imm_rename_stage.io.wakeups[1].bits.uop.prs1_busy, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs1_busy connect imm_rename_stage.io.wakeups[1].bits.uop.ppred, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ppred connect imm_rename_stage.io.wakeups[1].bits.uop.prs3, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs3 connect imm_rename_stage.io.wakeups[1].bits.uop.prs2, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs2 connect imm_rename_stage.io.wakeups[1].bits.uop.prs1, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs1 connect imm_rename_stage.io.wakeups[1].bits.uop.pdst, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.pdst connect imm_rename_stage.io.wakeups[1].bits.uop.rxq_idx, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.rxq_idx connect imm_rename_stage.io.wakeups[1].bits.uop.stq_idx, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.stq_idx connect imm_rename_stage.io.wakeups[1].bits.uop.ldq_idx, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ldq_idx connect imm_rename_stage.io.wakeups[1].bits.uop.rob_idx, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.rob_idx connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.vec, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.vec connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.wflags, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.wflags connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.sqrt, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.sqrt connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.div, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.div connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.fma, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fma connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.fastpipe, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fastpipe connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.toint, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.toint connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.fromint, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fromint connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.typeTagOut, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.typeTagOut connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.typeTagIn, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.typeTagIn connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.swap23, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.swap23 connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.swap12, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.swap12 connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.ren3, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren3 connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.ren2, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren2 connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.ren1, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren1 connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.wen, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.wen connect imm_rename_stage.io.wakeups[1].bits.uop.fp_ctrl.ldst, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ldst connect imm_rename_stage.io.wakeups[1].bits.uop.op2_sel, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.op2_sel connect imm_rename_stage.io.wakeups[1].bits.uop.op1_sel, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.op1_sel connect imm_rename_stage.io.wakeups[1].bits.uop.imm_packed, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.imm_packed connect imm_rename_stage.io.wakeups[1].bits.uop.pimm, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.pimm connect imm_rename_stage.io.wakeups[1].bits.uop.imm_sel, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.imm_sel connect imm_rename_stage.io.wakeups[1].bits.uop.imm_rename, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.imm_rename connect imm_rename_stage.io.wakeups[1].bits.uop.taken, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.taken connect imm_rename_stage.io.wakeups[1].bits.uop.pc_lob, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.pc_lob connect imm_rename_stage.io.wakeups[1].bits.uop.edge_inst, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.edge_inst connect imm_rename_stage.io.wakeups[1].bits.uop.ftq_idx, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ftq_idx connect imm_rename_stage.io.wakeups[1].bits.uop.is_mov, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_mov connect imm_rename_stage.io.wakeups[1].bits.uop.is_rocc, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_rocc connect imm_rename_stage.io.wakeups[1].bits.uop.is_sys_pc2epc, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_sys_pc2epc connect imm_rename_stage.io.wakeups[1].bits.uop.is_eret, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_eret connect imm_rename_stage.io.wakeups[1].bits.uop.is_amo, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_amo connect imm_rename_stage.io.wakeups[1].bits.uop.is_sfence, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_sfence connect imm_rename_stage.io.wakeups[1].bits.uop.is_fencei, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_fencei connect imm_rename_stage.io.wakeups[1].bits.uop.is_fence, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_fence connect imm_rename_stage.io.wakeups[1].bits.uop.is_sfb, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_sfb connect imm_rename_stage.io.wakeups[1].bits.uop.br_type, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.br_type connect imm_rename_stage.io.wakeups[1].bits.uop.br_tag, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.br_tag connect imm_rename_stage.io.wakeups[1].bits.uop.br_mask, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.br_mask connect imm_rename_stage.io.wakeups[1].bits.uop.dis_col_sel, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.dis_col_sel connect imm_rename_stage.io.wakeups[1].bits.uop.iw_p3_bypass_hint, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_p3_bypass_hint connect imm_rename_stage.io.wakeups[1].bits.uop.iw_p2_bypass_hint, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_p2_bypass_hint connect imm_rename_stage.io.wakeups[1].bits.uop.iw_p1_bypass_hint, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_p1_bypass_hint connect imm_rename_stage.io.wakeups[1].bits.uop.iw_p2_speculative_child, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_p2_speculative_child connect imm_rename_stage.io.wakeups[1].bits.uop.iw_p1_speculative_child, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_p1_speculative_child connect imm_rename_stage.io.wakeups[1].bits.uop.iw_issued_partial_dgen, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_issued_partial_dgen connect imm_rename_stage.io.wakeups[1].bits.uop.iw_issued_partial_agen, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_issued_partial_agen connect imm_rename_stage.io.wakeups[1].bits.uop.iw_issued, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_issued connect imm_rename_stage.io.wakeups[1].bits.uop.fu_code[0], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[0] connect imm_rename_stage.io.wakeups[1].bits.uop.fu_code[1], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[1] connect imm_rename_stage.io.wakeups[1].bits.uop.fu_code[2], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[2] connect imm_rename_stage.io.wakeups[1].bits.uop.fu_code[3], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[3] connect imm_rename_stage.io.wakeups[1].bits.uop.fu_code[4], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[4] connect imm_rename_stage.io.wakeups[1].bits.uop.fu_code[5], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[5] connect imm_rename_stage.io.wakeups[1].bits.uop.fu_code[6], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[6] connect imm_rename_stage.io.wakeups[1].bits.uop.fu_code[7], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[7] connect imm_rename_stage.io.wakeups[1].bits.uop.fu_code[8], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[8] connect imm_rename_stage.io.wakeups[1].bits.uop.fu_code[9], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[9] connect imm_rename_stage.io.wakeups[1].bits.uop.iq_type[0], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iq_type[0] connect imm_rename_stage.io.wakeups[1].bits.uop.iq_type[1], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iq_type[1] connect imm_rename_stage.io.wakeups[1].bits.uop.iq_type[2], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iq_type[2] connect imm_rename_stage.io.wakeups[1].bits.uop.iq_type[3], alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iq_type[3] connect imm_rename_stage.io.wakeups[1].bits.uop.debug_pc, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.debug_pc connect imm_rename_stage.io.wakeups[1].bits.uop.is_rvc, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_rvc connect imm_rename_stage.io.wakeups[1].bits.uop.debug_inst, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.debug_inst connect imm_rename_stage.io.wakeups[1].bits.uop.inst, alu_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.inst connect imm_rename_stage.io.wakeups[1].valid, alu_exe_unit_1.io_rrd_immrf_wakeup.valid connect imm_rename_stage.io.wakeups[2].bits.rebusy, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.rebusy connect imm_rename_stage.io.wakeups[2].bits.speculative_mask, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.speculative_mask connect imm_rename_stage.io.wakeups[2].bits.bypassable, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.bypassable connect imm_rename_stage.io.wakeups[2].bits.uop.debug_tsrc, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_tsrc connect imm_rename_stage.io.wakeups[2].bits.uop.debug_fsrc, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_fsrc connect imm_rename_stage.io.wakeups[2].bits.uop.bp_xcpt_if, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.bp_xcpt_if connect imm_rename_stage.io.wakeups[2].bits.uop.bp_debug_if, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.bp_debug_if connect imm_rename_stage.io.wakeups[2].bits.uop.xcpt_ma_if, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.xcpt_ma_if connect imm_rename_stage.io.wakeups[2].bits.uop.xcpt_ae_if, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.xcpt_ae_if connect imm_rename_stage.io.wakeups[2].bits.uop.xcpt_pf_if, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.xcpt_pf_if connect imm_rename_stage.io.wakeups[2].bits.uop.fp_typ, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_typ connect imm_rename_stage.io.wakeups[2].bits.uop.fp_rm, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_rm connect imm_rename_stage.io.wakeups[2].bits.uop.fp_val, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_val connect imm_rename_stage.io.wakeups[2].bits.uop.fcn_op, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fcn_op connect imm_rename_stage.io.wakeups[2].bits.uop.fcn_dw, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fcn_dw connect imm_rename_stage.io.wakeups[2].bits.uop.frs3_en, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.frs3_en connect imm_rename_stage.io.wakeups[2].bits.uop.lrs2_rtype, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs2_rtype connect imm_rename_stage.io.wakeups[2].bits.uop.lrs1_rtype, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs1_rtype connect imm_rename_stage.io.wakeups[2].bits.uop.dst_rtype, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.dst_rtype connect imm_rename_stage.io.wakeups[2].bits.uop.lrs3, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs3 connect imm_rename_stage.io.wakeups[2].bits.uop.lrs2, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs2 connect imm_rename_stage.io.wakeups[2].bits.uop.lrs1, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs1 connect imm_rename_stage.io.wakeups[2].bits.uop.ldst, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ldst connect imm_rename_stage.io.wakeups[2].bits.uop.ldst_is_rs1, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ldst_is_rs1 connect imm_rename_stage.io.wakeups[2].bits.uop.csr_cmd, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.csr_cmd connect imm_rename_stage.io.wakeups[2].bits.uop.flush_on_commit, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.flush_on_commit connect imm_rename_stage.io.wakeups[2].bits.uop.is_unique, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_unique connect imm_rename_stage.io.wakeups[2].bits.uop.uses_stq, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.uses_stq connect imm_rename_stage.io.wakeups[2].bits.uop.uses_ldq, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.uses_ldq connect imm_rename_stage.io.wakeups[2].bits.uop.mem_signed, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.mem_signed connect imm_rename_stage.io.wakeups[2].bits.uop.mem_size, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.mem_size connect imm_rename_stage.io.wakeups[2].bits.uop.mem_cmd, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.mem_cmd connect imm_rename_stage.io.wakeups[2].bits.uop.exc_cause, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.exc_cause connect imm_rename_stage.io.wakeups[2].bits.uop.exception, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.exception connect imm_rename_stage.io.wakeups[2].bits.uop.stale_pdst, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.stale_pdst connect imm_rename_stage.io.wakeups[2].bits.uop.ppred_busy, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ppred_busy connect imm_rename_stage.io.wakeups[2].bits.uop.prs3_busy, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs3_busy connect imm_rename_stage.io.wakeups[2].bits.uop.prs2_busy, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs2_busy connect imm_rename_stage.io.wakeups[2].bits.uop.prs1_busy, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs1_busy connect imm_rename_stage.io.wakeups[2].bits.uop.ppred, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ppred connect imm_rename_stage.io.wakeups[2].bits.uop.prs3, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs3 connect imm_rename_stage.io.wakeups[2].bits.uop.prs2, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs2 connect imm_rename_stage.io.wakeups[2].bits.uop.prs1, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs1 connect imm_rename_stage.io.wakeups[2].bits.uop.pdst, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.pdst connect imm_rename_stage.io.wakeups[2].bits.uop.rxq_idx, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.rxq_idx connect imm_rename_stage.io.wakeups[2].bits.uop.stq_idx, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.stq_idx connect imm_rename_stage.io.wakeups[2].bits.uop.ldq_idx, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ldq_idx connect imm_rename_stage.io.wakeups[2].bits.uop.rob_idx, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.rob_idx connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.vec, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.vec connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.wflags, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.wflags connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.sqrt, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.sqrt connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.div, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.div connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.fma, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fma connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.fastpipe, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fastpipe connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.toint, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.toint connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.fromint, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fromint connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.typeTagOut, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.typeTagOut connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.typeTagIn, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.typeTagIn connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.swap23, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.swap23 connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.swap12, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.swap12 connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.ren3, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren3 connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.ren2, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren2 connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.ren1, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren1 connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.wen, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.wen connect imm_rename_stage.io.wakeups[2].bits.uop.fp_ctrl.ldst, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ldst connect imm_rename_stage.io.wakeups[2].bits.uop.op2_sel, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.op2_sel connect imm_rename_stage.io.wakeups[2].bits.uop.op1_sel, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.op1_sel connect imm_rename_stage.io.wakeups[2].bits.uop.imm_packed, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.imm_packed connect imm_rename_stage.io.wakeups[2].bits.uop.pimm, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.pimm connect imm_rename_stage.io.wakeups[2].bits.uop.imm_sel, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.imm_sel connect imm_rename_stage.io.wakeups[2].bits.uop.imm_rename, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.imm_rename connect imm_rename_stage.io.wakeups[2].bits.uop.taken, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.taken connect imm_rename_stage.io.wakeups[2].bits.uop.pc_lob, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.pc_lob connect imm_rename_stage.io.wakeups[2].bits.uop.edge_inst, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.edge_inst connect imm_rename_stage.io.wakeups[2].bits.uop.ftq_idx, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ftq_idx connect imm_rename_stage.io.wakeups[2].bits.uop.is_mov, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_mov connect imm_rename_stage.io.wakeups[2].bits.uop.is_rocc, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_rocc connect imm_rename_stage.io.wakeups[2].bits.uop.is_sys_pc2epc, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_sys_pc2epc connect imm_rename_stage.io.wakeups[2].bits.uop.is_eret, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_eret connect imm_rename_stage.io.wakeups[2].bits.uop.is_amo, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_amo connect imm_rename_stage.io.wakeups[2].bits.uop.is_sfence, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_sfence connect imm_rename_stage.io.wakeups[2].bits.uop.is_fencei, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_fencei connect imm_rename_stage.io.wakeups[2].bits.uop.is_fence, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_fence connect imm_rename_stage.io.wakeups[2].bits.uop.is_sfb, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_sfb connect imm_rename_stage.io.wakeups[2].bits.uop.br_type, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.br_type connect imm_rename_stage.io.wakeups[2].bits.uop.br_tag, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.br_tag connect imm_rename_stage.io.wakeups[2].bits.uop.br_mask, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.br_mask connect imm_rename_stage.io.wakeups[2].bits.uop.dis_col_sel, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.dis_col_sel connect imm_rename_stage.io.wakeups[2].bits.uop.iw_p3_bypass_hint, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p3_bypass_hint connect imm_rename_stage.io.wakeups[2].bits.uop.iw_p2_bypass_hint, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p2_bypass_hint connect imm_rename_stage.io.wakeups[2].bits.uop.iw_p1_bypass_hint, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p1_bypass_hint connect imm_rename_stage.io.wakeups[2].bits.uop.iw_p2_speculative_child, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p2_speculative_child connect imm_rename_stage.io.wakeups[2].bits.uop.iw_p1_speculative_child, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p1_speculative_child connect imm_rename_stage.io.wakeups[2].bits.uop.iw_issued_partial_dgen, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_issued_partial_dgen connect imm_rename_stage.io.wakeups[2].bits.uop.iw_issued_partial_agen, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_issued_partial_agen connect imm_rename_stage.io.wakeups[2].bits.uop.iw_issued, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_issued connect imm_rename_stage.io.wakeups[2].bits.uop.fu_code[0], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[0] connect imm_rename_stage.io.wakeups[2].bits.uop.fu_code[1], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[1] connect imm_rename_stage.io.wakeups[2].bits.uop.fu_code[2], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[2] connect imm_rename_stage.io.wakeups[2].bits.uop.fu_code[3], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[3] connect imm_rename_stage.io.wakeups[2].bits.uop.fu_code[4], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[4] connect imm_rename_stage.io.wakeups[2].bits.uop.fu_code[5], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[5] connect imm_rename_stage.io.wakeups[2].bits.uop.fu_code[6], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[6] connect imm_rename_stage.io.wakeups[2].bits.uop.fu_code[7], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[7] connect imm_rename_stage.io.wakeups[2].bits.uop.fu_code[8], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[8] connect imm_rename_stage.io.wakeups[2].bits.uop.fu_code[9], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[9] connect imm_rename_stage.io.wakeups[2].bits.uop.iq_type[0], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[0] connect imm_rename_stage.io.wakeups[2].bits.uop.iq_type[1], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[1] connect imm_rename_stage.io.wakeups[2].bits.uop.iq_type[2], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[2] connect imm_rename_stage.io.wakeups[2].bits.uop.iq_type[3], mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[3] connect imm_rename_stage.io.wakeups[2].bits.uop.debug_pc, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_pc connect imm_rename_stage.io.wakeups[2].bits.uop.is_rvc, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_rvc connect imm_rename_stage.io.wakeups[2].bits.uop.debug_inst, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_inst connect imm_rename_stage.io.wakeups[2].bits.uop.inst, mem_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.inst connect imm_rename_stage.io.wakeups[2].valid, mem_exe_unit_0.io_rrd_immrf_wakeup.valid connect imm_rename_stage.io.wakeups[3].bits.rebusy, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.rebusy connect imm_rename_stage.io.wakeups[3].bits.speculative_mask, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.speculative_mask connect imm_rename_stage.io.wakeups[3].bits.bypassable, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.bypassable connect imm_rename_stage.io.wakeups[3].bits.uop.debug_tsrc, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.debug_tsrc connect imm_rename_stage.io.wakeups[3].bits.uop.debug_fsrc, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.debug_fsrc connect imm_rename_stage.io.wakeups[3].bits.uop.bp_xcpt_if, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.bp_xcpt_if connect imm_rename_stage.io.wakeups[3].bits.uop.bp_debug_if, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.bp_debug_if connect imm_rename_stage.io.wakeups[3].bits.uop.xcpt_ma_if, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.xcpt_ma_if connect imm_rename_stage.io.wakeups[3].bits.uop.xcpt_ae_if, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.xcpt_ae_if connect imm_rename_stage.io.wakeups[3].bits.uop.xcpt_pf_if, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.xcpt_pf_if connect imm_rename_stage.io.wakeups[3].bits.uop.fp_typ, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_typ connect imm_rename_stage.io.wakeups[3].bits.uop.fp_rm, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_rm connect imm_rename_stage.io.wakeups[3].bits.uop.fp_val, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_val connect imm_rename_stage.io.wakeups[3].bits.uop.fcn_op, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fcn_op connect imm_rename_stage.io.wakeups[3].bits.uop.fcn_dw, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fcn_dw connect imm_rename_stage.io.wakeups[3].bits.uop.frs3_en, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.frs3_en connect imm_rename_stage.io.wakeups[3].bits.uop.lrs2_rtype, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.lrs2_rtype connect imm_rename_stage.io.wakeups[3].bits.uop.lrs1_rtype, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.lrs1_rtype connect imm_rename_stage.io.wakeups[3].bits.uop.dst_rtype, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.dst_rtype connect imm_rename_stage.io.wakeups[3].bits.uop.lrs3, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.lrs3 connect imm_rename_stage.io.wakeups[3].bits.uop.lrs2, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.lrs2 connect imm_rename_stage.io.wakeups[3].bits.uop.lrs1, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.lrs1 connect imm_rename_stage.io.wakeups[3].bits.uop.ldst, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ldst connect imm_rename_stage.io.wakeups[3].bits.uop.ldst_is_rs1, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ldst_is_rs1 connect imm_rename_stage.io.wakeups[3].bits.uop.csr_cmd, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.csr_cmd connect imm_rename_stage.io.wakeups[3].bits.uop.flush_on_commit, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.flush_on_commit connect imm_rename_stage.io.wakeups[3].bits.uop.is_unique, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_unique connect imm_rename_stage.io.wakeups[3].bits.uop.uses_stq, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.uses_stq connect imm_rename_stage.io.wakeups[3].bits.uop.uses_ldq, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.uses_ldq connect imm_rename_stage.io.wakeups[3].bits.uop.mem_signed, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.mem_signed connect imm_rename_stage.io.wakeups[3].bits.uop.mem_size, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.mem_size connect imm_rename_stage.io.wakeups[3].bits.uop.mem_cmd, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.mem_cmd connect imm_rename_stage.io.wakeups[3].bits.uop.exc_cause, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.exc_cause connect imm_rename_stage.io.wakeups[3].bits.uop.exception, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.exception connect imm_rename_stage.io.wakeups[3].bits.uop.stale_pdst, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.stale_pdst connect imm_rename_stage.io.wakeups[3].bits.uop.ppred_busy, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ppred_busy connect imm_rename_stage.io.wakeups[3].bits.uop.prs3_busy, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs3_busy connect imm_rename_stage.io.wakeups[3].bits.uop.prs2_busy, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs2_busy connect imm_rename_stage.io.wakeups[3].bits.uop.prs1_busy, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs1_busy connect imm_rename_stage.io.wakeups[3].bits.uop.ppred, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ppred connect imm_rename_stage.io.wakeups[3].bits.uop.prs3, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs3 connect imm_rename_stage.io.wakeups[3].bits.uop.prs2, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs2 connect imm_rename_stage.io.wakeups[3].bits.uop.prs1, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.prs1 connect imm_rename_stage.io.wakeups[3].bits.uop.pdst, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.pdst connect imm_rename_stage.io.wakeups[3].bits.uop.rxq_idx, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.rxq_idx connect imm_rename_stage.io.wakeups[3].bits.uop.stq_idx, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.stq_idx connect imm_rename_stage.io.wakeups[3].bits.uop.ldq_idx, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ldq_idx connect imm_rename_stage.io.wakeups[3].bits.uop.rob_idx, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.rob_idx connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.vec, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.vec connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.wflags, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.wflags connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.sqrt, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.sqrt connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.div, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.div connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.fma, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fma connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.fastpipe, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fastpipe connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.toint, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.toint connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.fromint, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fromint connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.typeTagOut, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.typeTagOut connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.typeTagIn, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.typeTagIn connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.swap23, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.swap23 connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.swap12, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.swap12 connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.ren3, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren3 connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.ren2, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren2 connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.ren1, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren1 connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.wen, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.wen connect imm_rename_stage.io.wakeups[3].bits.uop.fp_ctrl.ldst, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ldst connect imm_rename_stage.io.wakeups[3].bits.uop.op2_sel, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.op2_sel connect imm_rename_stage.io.wakeups[3].bits.uop.op1_sel, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.op1_sel connect imm_rename_stage.io.wakeups[3].bits.uop.imm_packed, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.imm_packed connect imm_rename_stage.io.wakeups[3].bits.uop.pimm, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.pimm connect imm_rename_stage.io.wakeups[3].bits.uop.imm_sel, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.imm_sel connect imm_rename_stage.io.wakeups[3].bits.uop.imm_rename, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.imm_rename connect imm_rename_stage.io.wakeups[3].bits.uop.taken, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.taken connect imm_rename_stage.io.wakeups[3].bits.uop.pc_lob, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.pc_lob connect imm_rename_stage.io.wakeups[3].bits.uop.edge_inst, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.edge_inst connect imm_rename_stage.io.wakeups[3].bits.uop.ftq_idx, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.ftq_idx connect imm_rename_stage.io.wakeups[3].bits.uop.is_mov, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_mov connect imm_rename_stage.io.wakeups[3].bits.uop.is_rocc, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_rocc connect imm_rename_stage.io.wakeups[3].bits.uop.is_sys_pc2epc, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_sys_pc2epc connect imm_rename_stage.io.wakeups[3].bits.uop.is_eret, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_eret connect imm_rename_stage.io.wakeups[3].bits.uop.is_amo, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_amo connect imm_rename_stage.io.wakeups[3].bits.uop.is_sfence, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_sfence connect imm_rename_stage.io.wakeups[3].bits.uop.is_fencei, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_fencei connect imm_rename_stage.io.wakeups[3].bits.uop.is_fence, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_fence connect imm_rename_stage.io.wakeups[3].bits.uop.is_sfb, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_sfb connect imm_rename_stage.io.wakeups[3].bits.uop.br_type, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.br_type connect imm_rename_stage.io.wakeups[3].bits.uop.br_tag, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.br_tag connect imm_rename_stage.io.wakeups[3].bits.uop.br_mask, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.br_mask connect imm_rename_stage.io.wakeups[3].bits.uop.dis_col_sel, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.dis_col_sel connect imm_rename_stage.io.wakeups[3].bits.uop.iw_p3_bypass_hint, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_p3_bypass_hint connect imm_rename_stage.io.wakeups[3].bits.uop.iw_p2_bypass_hint, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_p2_bypass_hint connect imm_rename_stage.io.wakeups[3].bits.uop.iw_p1_bypass_hint, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_p1_bypass_hint connect imm_rename_stage.io.wakeups[3].bits.uop.iw_p2_speculative_child, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_p2_speculative_child connect imm_rename_stage.io.wakeups[3].bits.uop.iw_p1_speculative_child, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_p1_speculative_child connect imm_rename_stage.io.wakeups[3].bits.uop.iw_issued_partial_dgen, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_issued_partial_dgen connect imm_rename_stage.io.wakeups[3].bits.uop.iw_issued_partial_agen, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_issued_partial_agen connect imm_rename_stage.io.wakeups[3].bits.uop.iw_issued, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iw_issued connect imm_rename_stage.io.wakeups[3].bits.uop.fu_code[0], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[0] connect imm_rename_stage.io.wakeups[3].bits.uop.fu_code[1], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[1] connect imm_rename_stage.io.wakeups[3].bits.uop.fu_code[2], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[2] connect imm_rename_stage.io.wakeups[3].bits.uop.fu_code[3], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[3] connect imm_rename_stage.io.wakeups[3].bits.uop.fu_code[4], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[4] connect imm_rename_stage.io.wakeups[3].bits.uop.fu_code[5], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[5] connect imm_rename_stage.io.wakeups[3].bits.uop.fu_code[6], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[6] connect imm_rename_stage.io.wakeups[3].bits.uop.fu_code[7], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[7] connect imm_rename_stage.io.wakeups[3].bits.uop.fu_code[8], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[8] connect imm_rename_stage.io.wakeups[3].bits.uop.fu_code[9], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.fu_code[9] connect imm_rename_stage.io.wakeups[3].bits.uop.iq_type[0], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iq_type[0] connect imm_rename_stage.io.wakeups[3].bits.uop.iq_type[1], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iq_type[1] connect imm_rename_stage.io.wakeups[3].bits.uop.iq_type[2], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iq_type[2] connect imm_rename_stage.io.wakeups[3].bits.uop.iq_type[3], mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.iq_type[3] connect imm_rename_stage.io.wakeups[3].bits.uop.debug_pc, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.debug_pc connect imm_rename_stage.io.wakeups[3].bits.uop.is_rvc, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.is_rvc connect imm_rename_stage.io.wakeups[3].bits.uop.debug_inst, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.debug_inst connect imm_rename_stage.io.wakeups[3].bits.uop.inst, mem_exe_unit_1.io_rrd_immrf_wakeup.bits.uop.inst connect imm_rename_stage.io.wakeups[3].valid, mem_exe_unit_1.io_rrd_immrf_wakeup.valid connect imm_rename_stage.io.wakeups[4].bits.rebusy, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.rebusy connect imm_rename_stage.io.wakeups[4].bits.speculative_mask, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.speculative_mask connect imm_rename_stage.io.wakeups[4].bits.bypassable, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.bypassable connect imm_rename_stage.io.wakeups[4].bits.uop.debug_tsrc, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_tsrc connect imm_rename_stage.io.wakeups[4].bits.uop.debug_fsrc, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_fsrc connect imm_rename_stage.io.wakeups[4].bits.uop.bp_xcpt_if, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.bp_xcpt_if connect imm_rename_stage.io.wakeups[4].bits.uop.bp_debug_if, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.bp_debug_if connect imm_rename_stage.io.wakeups[4].bits.uop.xcpt_ma_if, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.xcpt_ma_if connect imm_rename_stage.io.wakeups[4].bits.uop.xcpt_ae_if, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.xcpt_ae_if connect imm_rename_stage.io.wakeups[4].bits.uop.xcpt_pf_if, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.xcpt_pf_if connect imm_rename_stage.io.wakeups[4].bits.uop.fp_typ, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_typ connect imm_rename_stage.io.wakeups[4].bits.uop.fp_rm, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_rm connect imm_rename_stage.io.wakeups[4].bits.uop.fp_val, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_val connect imm_rename_stage.io.wakeups[4].bits.uop.fcn_op, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fcn_op connect imm_rename_stage.io.wakeups[4].bits.uop.fcn_dw, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fcn_dw connect imm_rename_stage.io.wakeups[4].bits.uop.frs3_en, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.frs3_en connect imm_rename_stage.io.wakeups[4].bits.uop.lrs2_rtype, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs2_rtype connect imm_rename_stage.io.wakeups[4].bits.uop.lrs1_rtype, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs1_rtype connect imm_rename_stage.io.wakeups[4].bits.uop.dst_rtype, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.dst_rtype connect imm_rename_stage.io.wakeups[4].bits.uop.lrs3, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs3 connect imm_rename_stage.io.wakeups[4].bits.uop.lrs2, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs2 connect imm_rename_stage.io.wakeups[4].bits.uop.lrs1, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.lrs1 connect imm_rename_stage.io.wakeups[4].bits.uop.ldst, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ldst connect imm_rename_stage.io.wakeups[4].bits.uop.ldst_is_rs1, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ldst_is_rs1 connect imm_rename_stage.io.wakeups[4].bits.uop.csr_cmd, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.csr_cmd connect imm_rename_stage.io.wakeups[4].bits.uop.flush_on_commit, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.flush_on_commit connect imm_rename_stage.io.wakeups[4].bits.uop.is_unique, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_unique connect imm_rename_stage.io.wakeups[4].bits.uop.uses_stq, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.uses_stq connect imm_rename_stage.io.wakeups[4].bits.uop.uses_ldq, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.uses_ldq connect imm_rename_stage.io.wakeups[4].bits.uop.mem_signed, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.mem_signed connect imm_rename_stage.io.wakeups[4].bits.uop.mem_size, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.mem_size connect imm_rename_stage.io.wakeups[4].bits.uop.mem_cmd, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.mem_cmd connect imm_rename_stage.io.wakeups[4].bits.uop.exc_cause, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.exc_cause connect imm_rename_stage.io.wakeups[4].bits.uop.exception, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.exception connect imm_rename_stage.io.wakeups[4].bits.uop.stale_pdst, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.stale_pdst connect imm_rename_stage.io.wakeups[4].bits.uop.ppred_busy, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ppred_busy connect imm_rename_stage.io.wakeups[4].bits.uop.prs3_busy, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs3_busy connect imm_rename_stage.io.wakeups[4].bits.uop.prs2_busy, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs2_busy connect imm_rename_stage.io.wakeups[4].bits.uop.prs1_busy, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs1_busy connect imm_rename_stage.io.wakeups[4].bits.uop.ppred, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ppred connect imm_rename_stage.io.wakeups[4].bits.uop.prs3, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs3 connect imm_rename_stage.io.wakeups[4].bits.uop.prs2, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs2 connect imm_rename_stage.io.wakeups[4].bits.uop.prs1, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.prs1 connect imm_rename_stage.io.wakeups[4].bits.uop.pdst, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.pdst connect imm_rename_stage.io.wakeups[4].bits.uop.rxq_idx, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.rxq_idx connect imm_rename_stage.io.wakeups[4].bits.uop.stq_idx, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.stq_idx connect imm_rename_stage.io.wakeups[4].bits.uop.ldq_idx, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ldq_idx connect imm_rename_stage.io.wakeups[4].bits.uop.rob_idx, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.rob_idx connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.vec, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.vec connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.wflags, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.wflags connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.sqrt, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.sqrt connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.div, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.div connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.fma, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fma connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.fastpipe, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fastpipe connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.toint, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.toint connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.fromint, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.fromint connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.typeTagOut, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.typeTagOut connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.typeTagIn, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.typeTagIn connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.swap23, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.swap23 connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.swap12, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.swap12 connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.ren3, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren3 connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.ren2, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren2 connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.ren1, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ren1 connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.wen, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.wen connect imm_rename_stage.io.wakeups[4].bits.uop.fp_ctrl.ldst, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fp_ctrl.ldst connect imm_rename_stage.io.wakeups[4].bits.uop.op2_sel, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.op2_sel connect imm_rename_stage.io.wakeups[4].bits.uop.op1_sel, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.op1_sel connect imm_rename_stage.io.wakeups[4].bits.uop.imm_packed, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.imm_packed connect imm_rename_stage.io.wakeups[4].bits.uop.pimm, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.pimm connect imm_rename_stage.io.wakeups[4].bits.uop.imm_sel, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.imm_sel connect imm_rename_stage.io.wakeups[4].bits.uop.imm_rename, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.imm_rename connect imm_rename_stage.io.wakeups[4].bits.uop.taken, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.taken connect imm_rename_stage.io.wakeups[4].bits.uop.pc_lob, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.pc_lob connect imm_rename_stage.io.wakeups[4].bits.uop.edge_inst, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.edge_inst connect imm_rename_stage.io.wakeups[4].bits.uop.ftq_idx, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.ftq_idx connect imm_rename_stage.io.wakeups[4].bits.uop.is_mov, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_mov connect imm_rename_stage.io.wakeups[4].bits.uop.is_rocc, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_rocc connect imm_rename_stage.io.wakeups[4].bits.uop.is_sys_pc2epc, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_sys_pc2epc connect imm_rename_stage.io.wakeups[4].bits.uop.is_eret, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_eret connect imm_rename_stage.io.wakeups[4].bits.uop.is_amo, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_amo connect imm_rename_stage.io.wakeups[4].bits.uop.is_sfence, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_sfence connect imm_rename_stage.io.wakeups[4].bits.uop.is_fencei, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_fencei connect imm_rename_stage.io.wakeups[4].bits.uop.is_fence, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_fence connect imm_rename_stage.io.wakeups[4].bits.uop.is_sfb, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_sfb connect imm_rename_stage.io.wakeups[4].bits.uop.br_type, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.br_type connect imm_rename_stage.io.wakeups[4].bits.uop.br_tag, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.br_tag connect imm_rename_stage.io.wakeups[4].bits.uop.br_mask, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.br_mask connect imm_rename_stage.io.wakeups[4].bits.uop.dis_col_sel, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.dis_col_sel connect imm_rename_stage.io.wakeups[4].bits.uop.iw_p3_bypass_hint, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p3_bypass_hint connect imm_rename_stage.io.wakeups[4].bits.uop.iw_p2_bypass_hint, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p2_bypass_hint connect imm_rename_stage.io.wakeups[4].bits.uop.iw_p1_bypass_hint, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p1_bypass_hint connect imm_rename_stage.io.wakeups[4].bits.uop.iw_p2_speculative_child, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p2_speculative_child connect imm_rename_stage.io.wakeups[4].bits.uop.iw_p1_speculative_child, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_p1_speculative_child connect imm_rename_stage.io.wakeups[4].bits.uop.iw_issued_partial_dgen, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_issued_partial_dgen connect imm_rename_stage.io.wakeups[4].bits.uop.iw_issued_partial_agen, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_issued_partial_agen connect imm_rename_stage.io.wakeups[4].bits.uop.iw_issued, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iw_issued connect imm_rename_stage.io.wakeups[4].bits.uop.fu_code[0], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[0] connect imm_rename_stage.io.wakeups[4].bits.uop.fu_code[1], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[1] connect imm_rename_stage.io.wakeups[4].bits.uop.fu_code[2], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[2] connect imm_rename_stage.io.wakeups[4].bits.uop.fu_code[3], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[3] connect imm_rename_stage.io.wakeups[4].bits.uop.fu_code[4], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[4] connect imm_rename_stage.io.wakeups[4].bits.uop.fu_code[5], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[5] connect imm_rename_stage.io.wakeups[4].bits.uop.fu_code[6], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[6] connect imm_rename_stage.io.wakeups[4].bits.uop.fu_code[7], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[7] connect imm_rename_stage.io.wakeups[4].bits.uop.fu_code[8], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[8] connect imm_rename_stage.io.wakeups[4].bits.uop.fu_code[9], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.fu_code[9] connect imm_rename_stage.io.wakeups[4].bits.uop.iq_type[0], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[0] connect imm_rename_stage.io.wakeups[4].bits.uop.iq_type[1], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[1] connect imm_rename_stage.io.wakeups[4].bits.uop.iq_type[2], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[2] connect imm_rename_stage.io.wakeups[4].bits.uop.iq_type[3], unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.iq_type[3] connect imm_rename_stage.io.wakeups[4].bits.uop.debug_pc, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_pc connect imm_rename_stage.io.wakeups[4].bits.uop.is_rvc, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.is_rvc connect imm_rename_stage.io.wakeups[4].bits.uop.debug_inst, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.debug_inst connect imm_rename_stage.io.wakeups[4].bits.uop.inst, unique_exe_unit_0.io_rrd_immrf_wakeup.bits.uop.inst connect imm_rename_stage.io.wakeups[4].valid, unique_exe_unit_0.io_rrd_immrf_wakeup.valid node _rename_stage_io_child_rebusys_T = or(alu_exe_unit_0.io_child_rebusy, alu_exe_unit_1.io_child_rebusy) connect rename_stage.io.child_rebusys, _rename_stage_io_child_rebusys_T connect imm_rename_stage.io.child_rebusys, UInt<1>(0h0) connect pred_rename_stage.io.child_rebusys, UInt<1>(0h0) connect fp_rename_stage.io.child_rebusys, UInt<1>(0h0) connect mem_iss_unit.io.fu_types[0][0], mem_exe_unit_0.io_ready_fu_types[0] connect mem_iss_unit.io.fu_types[0][1], mem_exe_unit_0.io_ready_fu_types[1] connect mem_iss_unit.io.fu_types[0][2], mem_exe_unit_0.io_ready_fu_types[2] connect mem_iss_unit.io.fu_types[0][3], mem_exe_unit_0.io_ready_fu_types[3] connect mem_iss_unit.io.fu_types[0][4], mem_exe_unit_0.io_ready_fu_types[4] connect mem_iss_unit.io.fu_types[0][5], mem_exe_unit_0.io_ready_fu_types[5] connect mem_iss_unit.io.fu_types[0][6], mem_exe_unit_0.io_ready_fu_types[6] connect mem_iss_unit.io.fu_types[0][7], mem_exe_unit_0.io_ready_fu_types[7] connect mem_iss_unit.io.fu_types[0][8], mem_exe_unit_0.io_ready_fu_types[8] connect mem_iss_unit.io.fu_types[0][9], mem_exe_unit_0.io_ready_fu_types[9] connect mem_iss_unit.io.fu_types[1][0], mem_exe_unit_1.io_ready_fu_types[0] connect mem_iss_unit.io.fu_types[1][1], mem_exe_unit_1.io_ready_fu_types[1] connect mem_iss_unit.io.fu_types[1][2], mem_exe_unit_1.io_ready_fu_types[2] connect mem_iss_unit.io.fu_types[1][3], mem_exe_unit_1.io_ready_fu_types[3] connect mem_iss_unit.io.fu_types[1][4], mem_exe_unit_1.io_ready_fu_types[4] connect mem_iss_unit.io.fu_types[1][5], mem_exe_unit_1.io_ready_fu_types[5] connect mem_iss_unit.io.fu_types[1][6], mem_exe_unit_1.io_ready_fu_types[6] connect mem_iss_unit.io.fu_types[1][7], mem_exe_unit_1.io_ready_fu_types[7] connect mem_iss_unit.io.fu_types[1][8], mem_exe_unit_1.io_ready_fu_types[8] connect mem_iss_unit.io.fu_types[1][9], mem_exe_unit_1.io_ready_fu_types[9] connect alu_iss_unit.io.fu_types[0][0], alu_exe_unit_0.io_ready_fu_types[0] connect alu_iss_unit.io.fu_types[0][1], alu_exe_unit_0.io_ready_fu_types[1] connect alu_iss_unit.io.fu_types[0][2], alu_exe_unit_0.io_ready_fu_types[2] connect alu_iss_unit.io.fu_types[0][3], alu_exe_unit_0.io_ready_fu_types[3] connect alu_iss_unit.io.fu_types[0][4], alu_exe_unit_0.io_ready_fu_types[4] connect alu_iss_unit.io.fu_types[0][5], alu_exe_unit_0.io_ready_fu_types[5] connect alu_iss_unit.io.fu_types[0][6], alu_exe_unit_0.io_ready_fu_types[6] connect alu_iss_unit.io.fu_types[0][7], alu_exe_unit_0.io_ready_fu_types[7] connect alu_iss_unit.io.fu_types[0][8], alu_exe_unit_0.io_ready_fu_types[8] connect alu_iss_unit.io.fu_types[0][9], alu_exe_unit_0.io_ready_fu_types[9] connect alu_iss_unit.io.fu_types[1][0], alu_exe_unit_1.io_ready_fu_types[0] connect alu_iss_unit.io.fu_types[1][1], alu_exe_unit_1.io_ready_fu_types[1] connect alu_iss_unit.io.fu_types[1][2], alu_exe_unit_1.io_ready_fu_types[2] connect alu_iss_unit.io.fu_types[1][3], alu_exe_unit_1.io_ready_fu_types[3] connect alu_iss_unit.io.fu_types[1][4], alu_exe_unit_1.io_ready_fu_types[4] connect alu_iss_unit.io.fu_types[1][5], alu_exe_unit_1.io_ready_fu_types[5] connect alu_iss_unit.io.fu_types[1][6], alu_exe_unit_1.io_ready_fu_types[6] connect alu_iss_unit.io.fu_types[1][7], alu_exe_unit_1.io_ready_fu_types[7] connect alu_iss_unit.io.fu_types[1][8], alu_exe_unit_1.io_ready_fu_types[8] connect alu_iss_unit.io.fu_types[1][9], alu_exe_unit_1.io_ready_fu_types[9] connect unq_iss_unit.io.fu_types[0][0], unique_exe_unit_0.io_ready_fu_types[0] connect unq_iss_unit.io.fu_types[0][1], unique_exe_unit_0.io_ready_fu_types[1] connect unq_iss_unit.io.fu_types[0][2], unique_exe_unit_0.io_ready_fu_types[2] connect unq_iss_unit.io.fu_types[0][3], unique_exe_unit_0.io_ready_fu_types[3] connect unq_iss_unit.io.fu_types[0][4], unique_exe_unit_0.io_ready_fu_types[4] connect unq_iss_unit.io.fu_types[0][5], unique_exe_unit_0.io_ready_fu_types[5] connect unq_iss_unit.io.fu_types[0][6], unique_exe_unit_0.io_ready_fu_types[6] connect unq_iss_unit.io.fu_types[0][7], unique_exe_unit_0.io_ready_fu_types[7] connect unq_iss_unit.io.fu_types[0][8], unique_exe_unit_0.io_ready_fu_types[8] connect unq_iss_unit.io.fu_types[0][9], unique_exe_unit_0.io_ready_fu_types[9] connect mem_iss_unit.io.tsc_reg, debug_tsc_reg connect mem_iss_unit.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect mem_iss_unit.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect mem_iss_unit.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect mem_iss_unit.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect mem_iss_unit.io.brupdate.b2.taken, brupdate.b2.taken connect mem_iss_unit.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect mem_iss_unit.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect mem_iss_unit.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect mem_iss_unit.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect mem_iss_unit.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect mem_iss_unit.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect mem_iss_unit.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect mem_iss_unit.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect mem_iss_unit.io.brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect mem_iss_unit.io.brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect mem_iss_unit.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect mem_iss_unit.io.brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect mem_iss_unit.io.brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect mem_iss_unit.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect mem_iss_unit.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect mem_iss_unit.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect mem_iss_unit.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect mem_iss_unit.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect mem_iss_unit.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect mem_iss_unit.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect mem_iss_unit.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect mem_iss_unit.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect mem_iss_unit.io.brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect mem_iss_unit.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect mem_iss_unit.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect mem_iss_unit.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect mem_iss_unit.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect mem_iss_unit.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect mem_iss_unit.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect mem_iss_unit.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect mem_iss_unit.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect mem_iss_unit.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect mem_iss_unit.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect mem_iss_unit.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect mem_iss_unit.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect mem_iss_unit.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect mem_iss_unit.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect mem_iss_unit.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect mem_iss_unit.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect mem_iss_unit.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect mem_iss_unit.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect mem_iss_unit.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect mem_iss_unit.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect mem_iss_unit.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect mem_iss_unit.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect mem_iss_unit.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect mem_iss_unit.io.brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect mem_iss_unit.io.brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect mem_iss_unit.io.brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect mem_iss_unit.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect mem_iss_unit.io.brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect mem_iss_unit.io.brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect mem_iss_unit.io.brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect mem_iss_unit.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect mem_iss_unit.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect mem_iss_unit.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect mem_iss_unit.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect mem_iss_unit.io.brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect mem_iss_unit.io.brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect mem_iss_unit.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect mem_iss_unit.io.brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect mem_iss_unit.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect mem_iss_unit.io.brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect mem_iss_unit.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect mem_iss_unit.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect mem_iss_unit.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect mem_iss_unit.io.brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect mem_iss_unit.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect mem_iss_unit.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect mem_iss_unit.io.brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect mem_iss_unit.io.brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect mem_iss_unit.io.brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect mem_iss_unit.io.brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect mem_iss_unit.io.brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect mem_iss_unit.io.brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect mem_iss_unit.io.brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect mem_iss_unit.io.brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect mem_iss_unit.io.brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect mem_iss_unit.io.brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect mem_iss_unit.io.brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect mem_iss_unit.io.brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect mem_iss_unit.io.brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect mem_iss_unit.io.brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect mem_iss_unit.io.brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect mem_iss_unit.io.brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect mem_iss_unit.io.brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect mem_iss_unit.io.brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect mem_iss_unit.io.brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect mem_iss_unit.io.brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect mem_iss_unit.io.brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect mem_iss_unit.io.brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect mem_iss_unit.io.brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect mem_iss_unit.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect mem_iss_unit.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect mem_iss_unit.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect mem_iss_unit.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect mem_iss_unit.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect mem_iss_unit.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask reg mem_iss_unit_io_flush_pipeline_REG : UInt<1>, clock connect mem_iss_unit_io_flush_pipeline_REG, rob.io.flush.valid connect mem_iss_unit.io.flush_pipeline, mem_iss_unit_io_flush_pipeline_REG node _mem_iss_unit_io_child_rebusys_T = or(alu_exe_unit_0.io_child_rebusy, alu_exe_unit_1.io_child_rebusy) connect mem_iss_unit.io.child_rebusys, _mem_iss_unit_io_child_rebusys_T connect mem_iss_unit.io.wakeup_ports[0].bits.rebusy, int_wakeups[0].bits.rebusy connect mem_iss_unit.io.wakeup_ports[0].bits.speculative_mask, int_wakeups[0].bits.speculative_mask connect mem_iss_unit.io.wakeup_ports[0].bits.bypassable, int_wakeups[0].bits.bypassable connect mem_iss_unit.io.wakeup_ports[0].bits.uop.debug_tsrc, int_wakeups[0].bits.uop.debug_tsrc connect mem_iss_unit.io.wakeup_ports[0].bits.uop.debug_fsrc, int_wakeups[0].bits.uop.debug_fsrc connect mem_iss_unit.io.wakeup_ports[0].bits.uop.bp_xcpt_if, int_wakeups[0].bits.uop.bp_xcpt_if connect mem_iss_unit.io.wakeup_ports[0].bits.uop.bp_debug_if, int_wakeups[0].bits.uop.bp_debug_if connect mem_iss_unit.io.wakeup_ports[0].bits.uop.xcpt_ma_if, int_wakeups[0].bits.uop.xcpt_ma_if connect mem_iss_unit.io.wakeup_ports[0].bits.uop.xcpt_ae_if, int_wakeups[0].bits.uop.xcpt_ae_if connect mem_iss_unit.io.wakeup_ports[0].bits.uop.xcpt_pf_if, int_wakeups[0].bits.uop.xcpt_pf_if connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_typ, int_wakeups[0].bits.uop.fp_typ connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_rm, int_wakeups[0].bits.uop.fp_rm connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_val, int_wakeups[0].bits.uop.fp_val connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fcn_op, int_wakeups[0].bits.uop.fcn_op connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fcn_dw, int_wakeups[0].bits.uop.fcn_dw connect mem_iss_unit.io.wakeup_ports[0].bits.uop.frs3_en, int_wakeups[0].bits.uop.frs3_en connect mem_iss_unit.io.wakeup_ports[0].bits.uop.lrs2_rtype, int_wakeups[0].bits.uop.lrs2_rtype connect mem_iss_unit.io.wakeup_ports[0].bits.uop.lrs1_rtype, int_wakeups[0].bits.uop.lrs1_rtype connect mem_iss_unit.io.wakeup_ports[0].bits.uop.dst_rtype, int_wakeups[0].bits.uop.dst_rtype connect mem_iss_unit.io.wakeup_ports[0].bits.uop.lrs3, int_wakeups[0].bits.uop.lrs3 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.lrs2, int_wakeups[0].bits.uop.lrs2 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.lrs1, int_wakeups[0].bits.uop.lrs1 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.ldst, int_wakeups[0].bits.uop.ldst connect mem_iss_unit.io.wakeup_ports[0].bits.uop.ldst_is_rs1, int_wakeups[0].bits.uop.ldst_is_rs1 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.csr_cmd, int_wakeups[0].bits.uop.csr_cmd connect mem_iss_unit.io.wakeup_ports[0].bits.uop.flush_on_commit, int_wakeups[0].bits.uop.flush_on_commit connect mem_iss_unit.io.wakeup_ports[0].bits.uop.is_unique, int_wakeups[0].bits.uop.is_unique connect mem_iss_unit.io.wakeup_ports[0].bits.uop.uses_stq, int_wakeups[0].bits.uop.uses_stq connect mem_iss_unit.io.wakeup_ports[0].bits.uop.uses_ldq, int_wakeups[0].bits.uop.uses_ldq connect mem_iss_unit.io.wakeup_ports[0].bits.uop.mem_signed, int_wakeups[0].bits.uop.mem_signed connect mem_iss_unit.io.wakeup_ports[0].bits.uop.mem_size, int_wakeups[0].bits.uop.mem_size connect mem_iss_unit.io.wakeup_ports[0].bits.uop.mem_cmd, int_wakeups[0].bits.uop.mem_cmd connect mem_iss_unit.io.wakeup_ports[0].bits.uop.exc_cause, int_wakeups[0].bits.uop.exc_cause connect mem_iss_unit.io.wakeup_ports[0].bits.uop.exception, int_wakeups[0].bits.uop.exception connect mem_iss_unit.io.wakeup_ports[0].bits.uop.stale_pdst, int_wakeups[0].bits.uop.stale_pdst connect mem_iss_unit.io.wakeup_ports[0].bits.uop.ppred_busy, int_wakeups[0].bits.uop.ppred_busy connect mem_iss_unit.io.wakeup_ports[0].bits.uop.prs3_busy, int_wakeups[0].bits.uop.prs3_busy connect mem_iss_unit.io.wakeup_ports[0].bits.uop.prs2_busy, int_wakeups[0].bits.uop.prs2_busy connect mem_iss_unit.io.wakeup_ports[0].bits.uop.prs1_busy, int_wakeups[0].bits.uop.prs1_busy connect mem_iss_unit.io.wakeup_ports[0].bits.uop.ppred, int_wakeups[0].bits.uop.ppred connect mem_iss_unit.io.wakeup_ports[0].bits.uop.prs3, int_wakeups[0].bits.uop.prs3 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.prs2, int_wakeups[0].bits.uop.prs2 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.prs1, int_wakeups[0].bits.uop.prs1 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.pdst, int_wakeups[0].bits.uop.pdst connect mem_iss_unit.io.wakeup_ports[0].bits.uop.rxq_idx, int_wakeups[0].bits.uop.rxq_idx connect mem_iss_unit.io.wakeup_ports[0].bits.uop.stq_idx, int_wakeups[0].bits.uop.stq_idx connect mem_iss_unit.io.wakeup_ports[0].bits.uop.ldq_idx, int_wakeups[0].bits.uop.ldq_idx connect mem_iss_unit.io.wakeup_ports[0].bits.uop.rob_idx, int_wakeups[0].bits.uop.rob_idx connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, int_wakeups[0].bits.uop.fp_ctrl.vec connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, int_wakeups[0].bits.uop.fp_ctrl.wflags connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, int_wakeups[0].bits.uop.fp_ctrl.sqrt connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.div, int_wakeups[0].bits.uop.fp_ctrl.div connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, int_wakeups[0].bits.uop.fp_ctrl.fma connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, int_wakeups[0].bits.uop.fp_ctrl.fastpipe connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, int_wakeups[0].bits.uop.fp_ctrl.toint connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, int_wakeups[0].bits.uop.fp_ctrl.fromint connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, int_wakeups[0].bits.uop.fp_ctrl.typeTagOut connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, int_wakeups[0].bits.uop.fp_ctrl.typeTagIn connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, int_wakeups[0].bits.uop.fp_ctrl.swap23 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, int_wakeups[0].bits.uop.fp_ctrl.swap12 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, int_wakeups[0].bits.uop.fp_ctrl.ren3 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, int_wakeups[0].bits.uop.fp_ctrl.ren2 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, int_wakeups[0].bits.uop.fp_ctrl.ren1 connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, int_wakeups[0].bits.uop.fp_ctrl.wen connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, int_wakeups[0].bits.uop.fp_ctrl.ldst connect mem_iss_unit.io.wakeup_ports[0].bits.uop.op2_sel, int_wakeups[0].bits.uop.op2_sel connect mem_iss_unit.io.wakeup_ports[0].bits.uop.op1_sel, int_wakeups[0].bits.uop.op1_sel connect mem_iss_unit.io.wakeup_ports[0].bits.uop.imm_packed, int_wakeups[0].bits.uop.imm_packed connect mem_iss_unit.io.wakeup_ports[0].bits.uop.pimm, int_wakeups[0].bits.uop.pimm connect mem_iss_unit.io.wakeup_ports[0].bits.uop.imm_sel, int_wakeups[0].bits.uop.imm_sel connect mem_iss_unit.io.wakeup_ports[0].bits.uop.imm_rename, int_wakeups[0].bits.uop.imm_rename connect mem_iss_unit.io.wakeup_ports[0].bits.uop.taken, int_wakeups[0].bits.uop.taken connect mem_iss_unit.io.wakeup_ports[0].bits.uop.pc_lob, int_wakeups[0].bits.uop.pc_lob connect mem_iss_unit.io.wakeup_ports[0].bits.uop.edge_inst, int_wakeups[0].bits.uop.edge_inst connect mem_iss_unit.io.wakeup_ports[0].bits.uop.ftq_idx, int_wakeups[0].bits.uop.ftq_idx connect mem_iss_unit.io.wakeup_ports[0].bits.uop.is_mov, int_wakeups[0].bits.uop.is_mov connect mem_iss_unit.io.wakeup_ports[0].bits.uop.is_rocc, int_wakeups[0].bits.uop.is_rocc connect mem_iss_unit.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, int_wakeups[0].bits.uop.is_sys_pc2epc connect mem_iss_unit.io.wakeup_ports[0].bits.uop.is_eret, int_wakeups[0].bits.uop.is_eret connect mem_iss_unit.io.wakeup_ports[0].bits.uop.is_amo, int_wakeups[0].bits.uop.is_amo connect mem_iss_unit.io.wakeup_ports[0].bits.uop.is_sfence, int_wakeups[0].bits.uop.is_sfence connect mem_iss_unit.io.wakeup_ports[0].bits.uop.is_fencei, int_wakeups[0].bits.uop.is_fencei connect mem_iss_unit.io.wakeup_ports[0].bits.uop.is_fence, int_wakeups[0].bits.uop.is_fence connect mem_iss_unit.io.wakeup_ports[0].bits.uop.is_sfb, int_wakeups[0].bits.uop.is_sfb connect mem_iss_unit.io.wakeup_ports[0].bits.uop.br_type, int_wakeups[0].bits.uop.br_type connect mem_iss_unit.io.wakeup_ports[0].bits.uop.br_tag, int_wakeups[0].bits.uop.br_tag connect mem_iss_unit.io.wakeup_ports[0].bits.uop.br_mask, int_wakeups[0].bits.uop.br_mask connect mem_iss_unit.io.wakeup_ports[0].bits.uop.dis_col_sel, int_wakeups[0].bits.uop.dis_col_sel connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, int_wakeups[0].bits.uop.iw_p3_bypass_hint connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, int_wakeups[0].bits.uop.iw_p2_bypass_hint connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, int_wakeups[0].bits.uop.iw_p1_bypass_hint connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, int_wakeups[0].bits.uop.iw_p2_speculative_child connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, int_wakeups[0].bits.uop.iw_p1_speculative_child connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, int_wakeups[0].bits.uop.iw_issued_partial_dgen connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, int_wakeups[0].bits.uop.iw_issued_partial_agen connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iw_issued, int_wakeups[0].bits.uop.iw_issued connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[0], int_wakeups[0].bits.uop.fu_code[0] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[1], int_wakeups[0].bits.uop.fu_code[1] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[2], int_wakeups[0].bits.uop.fu_code[2] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[3], int_wakeups[0].bits.uop.fu_code[3] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[4], int_wakeups[0].bits.uop.fu_code[4] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[5], int_wakeups[0].bits.uop.fu_code[5] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[6], int_wakeups[0].bits.uop.fu_code[6] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[7], int_wakeups[0].bits.uop.fu_code[7] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[8], int_wakeups[0].bits.uop.fu_code[8] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[9], int_wakeups[0].bits.uop.fu_code[9] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[0], int_wakeups[0].bits.uop.iq_type[0] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[1], int_wakeups[0].bits.uop.iq_type[1] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[2], int_wakeups[0].bits.uop.iq_type[2] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[3], int_wakeups[0].bits.uop.iq_type[3] connect mem_iss_unit.io.wakeup_ports[0].bits.uop.debug_pc, int_wakeups[0].bits.uop.debug_pc connect mem_iss_unit.io.wakeup_ports[0].bits.uop.is_rvc, int_wakeups[0].bits.uop.is_rvc connect mem_iss_unit.io.wakeup_ports[0].bits.uop.debug_inst, int_wakeups[0].bits.uop.debug_inst connect mem_iss_unit.io.wakeup_ports[0].bits.uop.inst, int_wakeups[0].bits.uop.inst connect mem_iss_unit.io.wakeup_ports[0].valid, int_wakeups[0].valid connect mem_iss_unit.io.wakeup_ports[1].bits.rebusy, int_wakeups[1].bits.rebusy connect mem_iss_unit.io.wakeup_ports[1].bits.speculative_mask, int_wakeups[1].bits.speculative_mask connect mem_iss_unit.io.wakeup_ports[1].bits.bypassable, int_wakeups[1].bits.bypassable connect mem_iss_unit.io.wakeup_ports[1].bits.uop.debug_tsrc, int_wakeups[1].bits.uop.debug_tsrc connect mem_iss_unit.io.wakeup_ports[1].bits.uop.debug_fsrc, int_wakeups[1].bits.uop.debug_fsrc connect mem_iss_unit.io.wakeup_ports[1].bits.uop.bp_xcpt_if, int_wakeups[1].bits.uop.bp_xcpt_if connect mem_iss_unit.io.wakeup_ports[1].bits.uop.bp_debug_if, int_wakeups[1].bits.uop.bp_debug_if connect mem_iss_unit.io.wakeup_ports[1].bits.uop.xcpt_ma_if, int_wakeups[1].bits.uop.xcpt_ma_if connect mem_iss_unit.io.wakeup_ports[1].bits.uop.xcpt_ae_if, int_wakeups[1].bits.uop.xcpt_ae_if connect mem_iss_unit.io.wakeup_ports[1].bits.uop.xcpt_pf_if, int_wakeups[1].bits.uop.xcpt_pf_if connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_typ, int_wakeups[1].bits.uop.fp_typ connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_rm, int_wakeups[1].bits.uop.fp_rm connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_val, int_wakeups[1].bits.uop.fp_val connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fcn_op, int_wakeups[1].bits.uop.fcn_op connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fcn_dw, int_wakeups[1].bits.uop.fcn_dw connect mem_iss_unit.io.wakeup_ports[1].bits.uop.frs3_en, int_wakeups[1].bits.uop.frs3_en connect mem_iss_unit.io.wakeup_ports[1].bits.uop.lrs2_rtype, int_wakeups[1].bits.uop.lrs2_rtype connect mem_iss_unit.io.wakeup_ports[1].bits.uop.lrs1_rtype, int_wakeups[1].bits.uop.lrs1_rtype connect mem_iss_unit.io.wakeup_ports[1].bits.uop.dst_rtype, int_wakeups[1].bits.uop.dst_rtype connect mem_iss_unit.io.wakeup_ports[1].bits.uop.lrs3, int_wakeups[1].bits.uop.lrs3 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.lrs2, int_wakeups[1].bits.uop.lrs2 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.lrs1, int_wakeups[1].bits.uop.lrs1 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.ldst, int_wakeups[1].bits.uop.ldst connect mem_iss_unit.io.wakeup_ports[1].bits.uop.ldst_is_rs1, int_wakeups[1].bits.uop.ldst_is_rs1 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.csr_cmd, int_wakeups[1].bits.uop.csr_cmd connect mem_iss_unit.io.wakeup_ports[1].bits.uop.flush_on_commit, int_wakeups[1].bits.uop.flush_on_commit connect mem_iss_unit.io.wakeup_ports[1].bits.uop.is_unique, int_wakeups[1].bits.uop.is_unique connect mem_iss_unit.io.wakeup_ports[1].bits.uop.uses_stq, int_wakeups[1].bits.uop.uses_stq connect mem_iss_unit.io.wakeup_ports[1].bits.uop.uses_ldq, int_wakeups[1].bits.uop.uses_ldq connect mem_iss_unit.io.wakeup_ports[1].bits.uop.mem_signed, int_wakeups[1].bits.uop.mem_signed connect mem_iss_unit.io.wakeup_ports[1].bits.uop.mem_size, int_wakeups[1].bits.uop.mem_size connect mem_iss_unit.io.wakeup_ports[1].bits.uop.mem_cmd, int_wakeups[1].bits.uop.mem_cmd connect mem_iss_unit.io.wakeup_ports[1].bits.uop.exc_cause, int_wakeups[1].bits.uop.exc_cause connect mem_iss_unit.io.wakeup_ports[1].bits.uop.exception, int_wakeups[1].bits.uop.exception connect mem_iss_unit.io.wakeup_ports[1].bits.uop.stale_pdst, int_wakeups[1].bits.uop.stale_pdst connect mem_iss_unit.io.wakeup_ports[1].bits.uop.ppred_busy, int_wakeups[1].bits.uop.ppred_busy connect mem_iss_unit.io.wakeup_ports[1].bits.uop.prs3_busy, int_wakeups[1].bits.uop.prs3_busy connect mem_iss_unit.io.wakeup_ports[1].bits.uop.prs2_busy, int_wakeups[1].bits.uop.prs2_busy connect mem_iss_unit.io.wakeup_ports[1].bits.uop.prs1_busy, int_wakeups[1].bits.uop.prs1_busy connect mem_iss_unit.io.wakeup_ports[1].bits.uop.ppred, int_wakeups[1].bits.uop.ppred connect mem_iss_unit.io.wakeup_ports[1].bits.uop.prs3, int_wakeups[1].bits.uop.prs3 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.prs2, int_wakeups[1].bits.uop.prs2 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.prs1, int_wakeups[1].bits.uop.prs1 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.pdst, int_wakeups[1].bits.uop.pdst connect mem_iss_unit.io.wakeup_ports[1].bits.uop.rxq_idx, int_wakeups[1].bits.uop.rxq_idx connect mem_iss_unit.io.wakeup_ports[1].bits.uop.stq_idx, int_wakeups[1].bits.uop.stq_idx connect mem_iss_unit.io.wakeup_ports[1].bits.uop.ldq_idx, int_wakeups[1].bits.uop.ldq_idx connect mem_iss_unit.io.wakeup_ports[1].bits.uop.rob_idx, int_wakeups[1].bits.uop.rob_idx connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, int_wakeups[1].bits.uop.fp_ctrl.vec connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, int_wakeups[1].bits.uop.fp_ctrl.wflags connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, int_wakeups[1].bits.uop.fp_ctrl.sqrt connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.div, int_wakeups[1].bits.uop.fp_ctrl.div connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, int_wakeups[1].bits.uop.fp_ctrl.fma connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, int_wakeups[1].bits.uop.fp_ctrl.fastpipe connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, int_wakeups[1].bits.uop.fp_ctrl.toint connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, int_wakeups[1].bits.uop.fp_ctrl.fromint connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, int_wakeups[1].bits.uop.fp_ctrl.typeTagOut connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, int_wakeups[1].bits.uop.fp_ctrl.typeTagIn connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, int_wakeups[1].bits.uop.fp_ctrl.swap23 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, int_wakeups[1].bits.uop.fp_ctrl.swap12 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, int_wakeups[1].bits.uop.fp_ctrl.ren3 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, int_wakeups[1].bits.uop.fp_ctrl.ren2 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, int_wakeups[1].bits.uop.fp_ctrl.ren1 connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, int_wakeups[1].bits.uop.fp_ctrl.wen connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, int_wakeups[1].bits.uop.fp_ctrl.ldst connect mem_iss_unit.io.wakeup_ports[1].bits.uop.op2_sel, int_wakeups[1].bits.uop.op2_sel connect mem_iss_unit.io.wakeup_ports[1].bits.uop.op1_sel, int_wakeups[1].bits.uop.op1_sel connect mem_iss_unit.io.wakeup_ports[1].bits.uop.imm_packed, int_wakeups[1].bits.uop.imm_packed connect mem_iss_unit.io.wakeup_ports[1].bits.uop.pimm, int_wakeups[1].bits.uop.pimm connect mem_iss_unit.io.wakeup_ports[1].bits.uop.imm_sel, int_wakeups[1].bits.uop.imm_sel connect mem_iss_unit.io.wakeup_ports[1].bits.uop.imm_rename, int_wakeups[1].bits.uop.imm_rename connect mem_iss_unit.io.wakeup_ports[1].bits.uop.taken, int_wakeups[1].bits.uop.taken connect mem_iss_unit.io.wakeup_ports[1].bits.uop.pc_lob, int_wakeups[1].bits.uop.pc_lob connect mem_iss_unit.io.wakeup_ports[1].bits.uop.edge_inst, int_wakeups[1].bits.uop.edge_inst connect mem_iss_unit.io.wakeup_ports[1].bits.uop.ftq_idx, int_wakeups[1].bits.uop.ftq_idx connect mem_iss_unit.io.wakeup_ports[1].bits.uop.is_mov, int_wakeups[1].bits.uop.is_mov connect mem_iss_unit.io.wakeup_ports[1].bits.uop.is_rocc, int_wakeups[1].bits.uop.is_rocc connect mem_iss_unit.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, int_wakeups[1].bits.uop.is_sys_pc2epc connect mem_iss_unit.io.wakeup_ports[1].bits.uop.is_eret, int_wakeups[1].bits.uop.is_eret connect mem_iss_unit.io.wakeup_ports[1].bits.uop.is_amo, int_wakeups[1].bits.uop.is_amo connect mem_iss_unit.io.wakeup_ports[1].bits.uop.is_sfence, int_wakeups[1].bits.uop.is_sfence connect mem_iss_unit.io.wakeup_ports[1].bits.uop.is_fencei, int_wakeups[1].bits.uop.is_fencei connect mem_iss_unit.io.wakeup_ports[1].bits.uop.is_fence, int_wakeups[1].bits.uop.is_fence connect mem_iss_unit.io.wakeup_ports[1].bits.uop.is_sfb, int_wakeups[1].bits.uop.is_sfb connect mem_iss_unit.io.wakeup_ports[1].bits.uop.br_type, int_wakeups[1].bits.uop.br_type connect mem_iss_unit.io.wakeup_ports[1].bits.uop.br_tag, int_wakeups[1].bits.uop.br_tag connect mem_iss_unit.io.wakeup_ports[1].bits.uop.br_mask, int_wakeups[1].bits.uop.br_mask connect mem_iss_unit.io.wakeup_ports[1].bits.uop.dis_col_sel, int_wakeups[1].bits.uop.dis_col_sel connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, int_wakeups[1].bits.uop.iw_p3_bypass_hint connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, int_wakeups[1].bits.uop.iw_p2_bypass_hint connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, int_wakeups[1].bits.uop.iw_p1_bypass_hint connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, int_wakeups[1].bits.uop.iw_p2_speculative_child connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, int_wakeups[1].bits.uop.iw_p1_speculative_child connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, int_wakeups[1].bits.uop.iw_issued_partial_dgen connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, int_wakeups[1].bits.uop.iw_issued_partial_agen connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iw_issued, int_wakeups[1].bits.uop.iw_issued connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[0], int_wakeups[1].bits.uop.fu_code[0] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[1], int_wakeups[1].bits.uop.fu_code[1] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[2], int_wakeups[1].bits.uop.fu_code[2] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[3], int_wakeups[1].bits.uop.fu_code[3] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[4], int_wakeups[1].bits.uop.fu_code[4] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[5], int_wakeups[1].bits.uop.fu_code[5] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[6], int_wakeups[1].bits.uop.fu_code[6] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[7], int_wakeups[1].bits.uop.fu_code[7] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[8], int_wakeups[1].bits.uop.fu_code[8] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[9], int_wakeups[1].bits.uop.fu_code[9] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[0], int_wakeups[1].bits.uop.iq_type[0] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[1], int_wakeups[1].bits.uop.iq_type[1] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[2], int_wakeups[1].bits.uop.iq_type[2] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[3], int_wakeups[1].bits.uop.iq_type[3] connect mem_iss_unit.io.wakeup_ports[1].bits.uop.debug_pc, int_wakeups[1].bits.uop.debug_pc connect mem_iss_unit.io.wakeup_ports[1].bits.uop.is_rvc, int_wakeups[1].bits.uop.is_rvc connect mem_iss_unit.io.wakeup_ports[1].bits.uop.debug_inst, int_wakeups[1].bits.uop.debug_inst connect mem_iss_unit.io.wakeup_ports[1].bits.uop.inst, int_wakeups[1].bits.uop.inst connect mem_iss_unit.io.wakeup_ports[1].valid, int_wakeups[1].valid connect mem_iss_unit.io.wakeup_ports[2].bits.rebusy, int_wakeups[2].bits.rebusy connect mem_iss_unit.io.wakeup_ports[2].bits.speculative_mask, int_wakeups[2].bits.speculative_mask connect mem_iss_unit.io.wakeup_ports[2].bits.bypassable, int_wakeups[2].bits.bypassable connect mem_iss_unit.io.wakeup_ports[2].bits.uop.debug_tsrc, int_wakeups[2].bits.uop.debug_tsrc connect mem_iss_unit.io.wakeup_ports[2].bits.uop.debug_fsrc, int_wakeups[2].bits.uop.debug_fsrc connect mem_iss_unit.io.wakeup_ports[2].bits.uop.bp_xcpt_if, int_wakeups[2].bits.uop.bp_xcpt_if connect mem_iss_unit.io.wakeup_ports[2].bits.uop.bp_debug_if, int_wakeups[2].bits.uop.bp_debug_if connect mem_iss_unit.io.wakeup_ports[2].bits.uop.xcpt_ma_if, int_wakeups[2].bits.uop.xcpt_ma_if connect mem_iss_unit.io.wakeup_ports[2].bits.uop.xcpt_ae_if, int_wakeups[2].bits.uop.xcpt_ae_if connect mem_iss_unit.io.wakeup_ports[2].bits.uop.xcpt_pf_if, int_wakeups[2].bits.uop.xcpt_pf_if connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_typ, int_wakeups[2].bits.uop.fp_typ connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_rm, int_wakeups[2].bits.uop.fp_rm connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_val, int_wakeups[2].bits.uop.fp_val connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fcn_op, int_wakeups[2].bits.uop.fcn_op connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fcn_dw, int_wakeups[2].bits.uop.fcn_dw connect mem_iss_unit.io.wakeup_ports[2].bits.uop.frs3_en, int_wakeups[2].bits.uop.frs3_en connect mem_iss_unit.io.wakeup_ports[2].bits.uop.lrs2_rtype, int_wakeups[2].bits.uop.lrs2_rtype connect mem_iss_unit.io.wakeup_ports[2].bits.uop.lrs1_rtype, int_wakeups[2].bits.uop.lrs1_rtype connect mem_iss_unit.io.wakeup_ports[2].bits.uop.dst_rtype, int_wakeups[2].bits.uop.dst_rtype connect mem_iss_unit.io.wakeup_ports[2].bits.uop.lrs3, int_wakeups[2].bits.uop.lrs3 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.lrs2, int_wakeups[2].bits.uop.lrs2 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.lrs1, int_wakeups[2].bits.uop.lrs1 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.ldst, int_wakeups[2].bits.uop.ldst connect mem_iss_unit.io.wakeup_ports[2].bits.uop.ldst_is_rs1, int_wakeups[2].bits.uop.ldst_is_rs1 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.csr_cmd, int_wakeups[2].bits.uop.csr_cmd connect mem_iss_unit.io.wakeup_ports[2].bits.uop.flush_on_commit, int_wakeups[2].bits.uop.flush_on_commit connect mem_iss_unit.io.wakeup_ports[2].bits.uop.is_unique, int_wakeups[2].bits.uop.is_unique connect mem_iss_unit.io.wakeup_ports[2].bits.uop.uses_stq, int_wakeups[2].bits.uop.uses_stq connect mem_iss_unit.io.wakeup_ports[2].bits.uop.uses_ldq, int_wakeups[2].bits.uop.uses_ldq connect mem_iss_unit.io.wakeup_ports[2].bits.uop.mem_signed, int_wakeups[2].bits.uop.mem_signed connect mem_iss_unit.io.wakeup_ports[2].bits.uop.mem_size, int_wakeups[2].bits.uop.mem_size connect mem_iss_unit.io.wakeup_ports[2].bits.uop.mem_cmd, int_wakeups[2].bits.uop.mem_cmd connect mem_iss_unit.io.wakeup_ports[2].bits.uop.exc_cause, int_wakeups[2].bits.uop.exc_cause connect mem_iss_unit.io.wakeup_ports[2].bits.uop.exception, int_wakeups[2].bits.uop.exception connect mem_iss_unit.io.wakeup_ports[2].bits.uop.stale_pdst, int_wakeups[2].bits.uop.stale_pdst connect mem_iss_unit.io.wakeup_ports[2].bits.uop.ppred_busy, int_wakeups[2].bits.uop.ppred_busy connect mem_iss_unit.io.wakeup_ports[2].bits.uop.prs3_busy, int_wakeups[2].bits.uop.prs3_busy connect mem_iss_unit.io.wakeup_ports[2].bits.uop.prs2_busy, int_wakeups[2].bits.uop.prs2_busy connect mem_iss_unit.io.wakeup_ports[2].bits.uop.prs1_busy, int_wakeups[2].bits.uop.prs1_busy connect mem_iss_unit.io.wakeup_ports[2].bits.uop.ppred, int_wakeups[2].bits.uop.ppred connect mem_iss_unit.io.wakeup_ports[2].bits.uop.prs3, int_wakeups[2].bits.uop.prs3 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.prs2, int_wakeups[2].bits.uop.prs2 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.prs1, int_wakeups[2].bits.uop.prs1 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.pdst, int_wakeups[2].bits.uop.pdst connect mem_iss_unit.io.wakeup_ports[2].bits.uop.rxq_idx, int_wakeups[2].bits.uop.rxq_idx connect mem_iss_unit.io.wakeup_ports[2].bits.uop.stq_idx, int_wakeups[2].bits.uop.stq_idx connect mem_iss_unit.io.wakeup_ports[2].bits.uop.ldq_idx, int_wakeups[2].bits.uop.ldq_idx connect mem_iss_unit.io.wakeup_ports[2].bits.uop.rob_idx, int_wakeups[2].bits.uop.rob_idx connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, int_wakeups[2].bits.uop.fp_ctrl.vec connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, int_wakeups[2].bits.uop.fp_ctrl.wflags connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, int_wakeups[2].bits.uop.fp_ctrl.sqrt connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.div, int_wakeups[2].bits.uop.fp_ctrl.div connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, int_wakeups[2].bits.uop.fp_ctrl.fma connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, int_wakeups[2].bits.uop.fp_ctrl.fastpipe connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, int_wakeups[2].bits.uop.fp_ctrl.toint connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, int_wakeups[2].bits.uop.fp_ctrl.fromint connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, int_wakeups[2].bits.uop.fp_ctrl.typeTagOut connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, int_wakeups[2].bits.uop.fp_ctrl.typeTagIn connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, int_wakeups[2].bits.uop.fp_ctrl.swap23 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, int_wakeups[2].bits.uop.fp_ctrl.swap12 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, int_wakeups[2].bits.uop.fp_ctrl.ren3 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, int_wakeups[2].bits.uop.fp_ctrl.ren2 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, int_wakeups[2].bits.uop.fp_ctrl.ren1 connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, int_wakeups[2].bits.uop.fp_ctrl.wen connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, int_wakeups[2].bits.uop.fp_ctrl.ldst connect mem_iss_unit.io.wakeup_ports[2].bits.uop.op2_sel, int_wakeups[2].bits.uop.op2_sel connect mem_iss_unit.io.wakeup_ports[2].bits.uop.op1_sel, int_wakeups[2].bits.uop.op1_sel connect mem_iss_unit.io.wakeup_ports[2].bits.uop.imm_packed, int_wakeups[2].bits.uop.imm_packed connect mem_iss_unit.io.wakeup_ports[2].bits.uop.pimm, int_wakeups[2].bits.uop.pimm connect mem_iss_unit.io.wakeup_ports[2].bits.uop.imm_sel, int_wakeups[2].bits.uop.imm_sel connect mem_iss_unit.io.wakeup_ports[2].bits.uop.imm_rename, int_wakeups[2].bits.uop.imm_rename connect mem_iss_unit.io.wakeup_ports[2].bits.uop.taken, int_wakeups[2].bits.uop.taken connect mem_iss_unit.io.wakeup_ports[2].bits.uop.pc_lob, int_wakeups[2].bits.uop.pc_lob connect mem_iss_unit.io.wakeup_ports[2].bits.uop.edge_inst, int_wakeups[2].bits.uop.edge_inst connect mem_iss_unit.io.wakeup_ports[2].bits.uop.ftq_idx, int_wakeups[2].bits.uop.ftq_idx connect mem_iss_unit.io.wakeup_ports[2].bits.uop.is_mov, int_wakeups[2].bits.uop.is_mov connect mem_iss_unit.io.wakeup_ports[2].bits.uop.is_rocc, int_wakeups[2].bits.uop.is_rocc connect mem_iss_unit.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, int_wakeups[2].bits.uop.is_sys_pc2epc connect mem_iss_unit.io.wakeup_ports[2].bits.uop.is_eret, int_wakeups[2].bits.uop.is_eret connect mem_iss_unit.io.wakeup_ports[2].bits.uop.is_amo, int_wakeups[2].bits.uop.is_amo connect mem_iss_unit.io.wakeup_ports[2].bits.uop.is_sfence, int_wakeups[2].bits.uop.is_sfence connect mem_iss_unit.io.wakeup_ports[2].bits.uop.is_fencei, int_wakeups[2].bits.uop.is_fencei connect mem_iss_unit.io.wakeup_ports[2].bits.uop.is_fence, int_wakeups[2].bits.uop.is_fence connect mem_iss_unit.io.wakeup_ports[2].bits.uop.is_sfb, int_wakeups[2].bits.uop.is_sfb connect mem_iss_unit.io.wakeup_ports[2].bits.uop.br_type, int_wakeups[2].bits.uop.br_type connect mem_iss_unit.io.wakeup_ports[2].bits.uop.br_tag, int_wakeups[2].bits.uop.br_tag connect mem_iss_unit.io.wakeup_ports[2].bits.uop.br_mask, int_wakeups[2].bits.uop.br_mask connect mem_iss_unit.io.wakeup_ports[2].bits.uop.dis_col_sel, int_wakeups[2].bits.uop.dis_col_sel connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, int_wakeups[2].bits.uop.iw_p3_bypass_hint connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, int_wakeups[2].bits.uop.iw_p2_bypass_hint connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, int_wakeups[2].bits.uop.iw_p1_bypass_hint connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, int_wakeups[2].bits.uop.iw_p2_speculative_child connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, int_wakeups[2].bits.uop.iw_p1_speculative_child connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, int_wakeups[2].bits.uop.iw_issued_partial_dgen connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, int_wakeups[2].bits.uop.iw_issued_partial_agen connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iw_issued, int_wakeups[2].bits.uop.iw_issued connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[0], int_wakeups[2].bits.uop.fu_code[0] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[1], int_wakeups[2].bits.uop.fu_code[1] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[2], int_wakeups[2].bits.uop.fu_code[2] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[3], int_wakeups[2].bits.uop.fu_code[3] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[4], int_wakeups[2].bits.uop.fu_code[4] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[5], int_wakeups[2].bits.uop.fu_code[5] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[6], int_wakeups[2].bits.uop.fu_code[6] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[7], int_wakeups[2].bits.uop.fu_code[7] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[8], int_wakeups[2].bits.uop.fu_code[8] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[9], int_wakeups[2].bits.uop.fu_code[9] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[0], int_wakeups[2].bits.uop.iq_type[0] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[1], int_wakeups[2].bits.uop.iq_type[1] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[2], int_wakeups[2].bits.uop.iq_type[2] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[3], int_wakeups[2].bits.uop.iq_type[3] connect mem_iss_unit.io.wakeup_ports[2].bits.uop.debug_pc, int_wakeups[2].bits.uop.debug_pc connect mem_iss_unit.io.wakeup_ports[2].bits.uop.is_rvc, int_wakeups[2].bits.uop.is_rvc connect mem_iss_unit.io.wakeup_ports[2].bits.uop.debug_inst, int_wakeups[2].bits.uop.debug_inst connect mem_iss_unit.io.wakeup_ports[2].bits.uop.inst, int_wakeups[2].bits.uop.inst connect mem_iss_unit.io.wakeup_ports[2].valid, int_wakeups[2].valid connect mem_iss_unit.io.wakeup_ports[3].bits.rebusy, int_wakeups[3].bits.rebusy connect mem_iss_unit.io.wakeup_ports[3].bits.speculative_mask, int_wakeups[3].bits.speculative_mask connect mem_iss_unit.io.wakeup_ports[3].bits.bypassable, int_wakeups[3].bits.bypassable connect mem_iss_unit.io.wakeup_ports[3].bits.uop.debug_tsrc, int_wakeups[3].bits.uop.debug_tsrc connect mem_iss_unit.io.wakeup_ports[3].bits.uop.debug_fsrc, int_wakeups[3].bits.uop.debug_fsrc connect mem_iss_unit.io.wakeup_ports[3].bits.uop.bp_xcpt_if, int_wakeups[3].bits.uop.bp_xcpt_if connect mem_iss_unit.io.wakeup_ports[3].bits.uop.bp_debug_if, int_wakeups[3].bits.uop.bp_debug_if connect mem_iss_unit.io.wakeup_ports[3].bits.uop.xcpt_ma_if, int_wakeups[3].bits.uop.xcpt_ma_if connect mem_iss_unit.io.wakeup_ports[3].bits.uop.xcpt_ae_if, int_wakeups[3].bits.uop.xcpt_ae_if connect mem_iss_unit.io.wakeup_ports[3].bits.uop.xcpt_pf_if, int_wakeups[3].bits.uop.xcpt_pf_if connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_typ, int_wakeups[3].bits.uop.fp_typ connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_rm, int_wakeups[3].bits.uop.fp_rm connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_val, int_wakeups[3].bits.uop.fp_val connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fcn_op, int_wakeups[3].bits.uop.fcn_op connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fcn_dw, int_wakeups[3].bits.uop.fcn_dw connect mem_iss_unit.io.wakeup_ports[3].bits.uop.frs3_en, int_wakeups[3].bits.uop.frs3_en connect mem_iss_unit.io.wakeup_ports[3].bits.uop.lrs2_rtype, int_wakeups[3].bits.uop.lrs2_rtype connect mem_iss_unit.io.wakeup_ports[3].bits.uop.lrs1_rtype, int_wakeups[3].bits.uop.lrs1_rtype connect mem_iss_unit.io.wakeup_ports[3].bits.uop.dst_rtype, int_wakeups[3].bits.uop.dst_rtype connect mem_iss_unit.io.wakeup_ports[3].bits.uop.lrs3, int_wakeups[3].bits.uop.lrs3 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.lrs2, int_wakeups[3].bits.uop.lrs2 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.lrs1, int_wakeups[3].bits.uop.lrs1 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.ldst, int_wakeups[3].bits.uop.ldst connect mem_iss_unit.io.wakeup_ports[3].bits.uop.ldst_is_rs1, int_wakeups[3].bits.uop.ldst_is_rs1 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.csr_cmd, int_wakeups[3].bits.uop.csr_cmd connect mem_iss_unit.io.wakeup_ports[3].bits.uop.flush_on_commit, int_wakeups[3].bits.uop.flush_on_commit connect mem_iss_unit.io.wakeup_ports[3].bits.uop.is_unique, int_wakeups[3].bits.uop.is_unique connect mem_iss_unit.io.wakeup_ports[3].bits.uop.uses_stq, int_wakeups[3].bits.uop.uses_stq connect mem_iss_unit.io.wakeup_ports[3].bits.uop.uses_ldq, int_wakeups[3].bits.uop.uses_ldq connect mem_iss_unit.io.wakeup_ports[3].bits.uop.mem_signed, int_wakeups[3].bits.uop.mem_signed connect mem_iss_unit.io.wakeup_ports[3].bits.uop.mem_size, int_wakeups[3].bits.uop.mem_size connect mem_iss_unit.io.wakeup_ports[3].bits.uop.mem_cmd, int_wakeups[3].bits.uop.mem_cmd connect mem_iss_unit.io.wakeup_ports[3].bits.uop.exc_cause, int_wakeups[3].bits.uop.exc_cause connect mem_iss_unit.io.wakeup_ports[3].bits.uop.exception, int_wakeups[3].bits.uop.exception connect mem_iss_unit.io.wakeup_ports[3].bits.uop.stale_pdst, int_wakeups[3].bits.uop.stale_pdst connect mem_iss_unit.io.wakeup_ports[3].bits.uop.ppred_busy, int_wakeups[3].bits.uop.ppred_busy connect mem_iss_unit.io.wakeup_ports[3].bits.uop.prs3_busy, int_wakeups[3].bits.uop.prs3_busy connect mem_iss_unit.io.wakeup_ports[3].bits.uop.prs2_busy, int_wakeups[3].bits.uop.prs2_busy connect mem_iss_unit.io.wakeup_ports[3].bits.uop.prs1_busy, int_wakeups[3].bits.uop.prs1_busy connect mem_iss_unit.io.wakeup_ports[3].bits.uop.ppred, int_wakeups[3].bits.uop.ppred connect mem_iss_unit.io.wakeup_ports[3].bits.uop.prs3, int_wakeups[3].bits.uop.prs3 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.prs2, int_wakeups[3].bits.uop.prs2 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.prs1, int_wakeups[3].bits.uop.prs1 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.pdst, int_wakeups[3].bits.uop.pdst connect mem_iss_unit.io.wakeup_ports[3].bits.uop.rxq_idx, int_wakeups[3].bits.uop.rxq_idx connect mem_iss_unit.io.wakeup_ports[3].bits.uop.stq_idx, int_wakeups[3].bits.uop.stq_idx connect mem_iss_unit.io.wakeup_ports[3].bits.uop.ldq_idx, int_wakeups[3].bits.uop.ldq_idx connect mem_iss_unit.io.wakeup_ports[3].bits.uop.rob_idx, int_wakeups[3].bits.uop.rob_idx connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, int_wakeups[3].bits.uop.fp_ctrl.vec connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, int_wakeups[3].bits.uop.fp_ctrl.wflags connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, int_wakeups[3].bits.uop.fp_ctrl.sqrt connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.div, int_wakeups[3].bits.uop.fp_ctrl.div connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, int_wakeups[3].bits.uop.fp_ctrl.fma connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, int_wakeups[3].bits.uop.fp_ctrl.fastpipe connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, int_wakeups[3].bits.uop.fp_ctrl.toint connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, int_wakeups[3].bits.uop.fp_ctrl.fromint connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, int_wakeups[3].bits.uop.fp_ctrl.typeTagOut connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, int_wakeups[3].bits.uop.fp_ctrl.typeTagIn connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, int_wakeups[3].bits.uop.fp_ctrl.swap23 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, int_wakeups[3].bits.uop.fp_ctrl.swap12 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, int_wakeups[3].bits.uop.fp_ctrl.ren3 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, int_wakeups[3].bits.uop.fp_ctrl.ren2 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, int_wakeups[3].bits.uop.fp_ctrl.ren1 connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, int_wakeups[3].bits.uop.fp_ctrl.wen connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, int_wakeups[3].bits.uop.fp_ctrl.ldst connect mem_iss_unit.io.wakeup_ports[3].bits.uop.op2_sel, int_wakeups[3].bits.uop.op2_sel connect mem_iss_unit.io.wakeup_ports[3].bits.uop.op1_sel, int_wakeups[3].bits.uop.op1_sel connect mem_iss_unit.io.wakeup_ports[3].bits.uop.imm_packed, int_wakeups[3].bits.uop.imm_packed connect mem_iss_unit.io.wakeup_ports[3].bits.uop.pimm, int_wakeups[3].bits.uop.pimm connect mem_iss_unit.io.wakeup_ports[3].bits.uop.imm_sel, int_wakeups[3].bits.uop.imm_sel connect mem_iss_unit.io.wakeup_ports[3].bits.uop.imm_rename, int_wakeups[3].bits.uop.imm_rename connect mem_iss_unit.io.wakeup_ports[3].bits.uop.taken, int_wakeups[3].bits.uop.taken connect mem_iss_unit.io.wakeup_ports[3].bits.uop.pc_lob, int_wakeups[3].bits.uop.pc_lob connect mem_iss_unit.io.wakeup_ports[3].bits.uop.edge_inst, int_wakeups[3].bits.uop.edge_inst connect mem_iss_unit.io.wakeup_ports[3].bits.uop.ftq_idx, int_wakeups[3].bits.uop.ftq_idx connect mem_iss_unit.io.wakeup_ports[3].bits.uop.is_mov, int_wakeups[3].bits.uop.is_mov connect mem_iss_unit.io.wakeup_ports[3].bits.uop.is_rocc, int_wakeups[3].bits.uop.is_rocc connect mem_iss_unit.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, int_wakeups[3].bits.uop.is_sys_pc2epc connect mem_iss_unit.io.wakeup_ports[3].bits.uop.is_eret, int_wakeups[3].bits.uop.is_eret connect mem_iss_unit.io.wakeup_ports[3].bits.uop.is_amo, int_wakeups[3].bits.uop.is_amo connect mem_iss_unit.io.wakeup_ports[3].bits.uop.is_sfence, int_wakeups[3].bits.uop.is_sfence connect mem_iss_unit.io.wakeup_ports[3].bits.uop.is_fencei, int_wakeups[3].bits.uop.is_fencei connect mem_iss_unit.io.wakeup_ports[3].bits.uop.is_fence, int_wakeups[3].bits.uop.is_fence connect mem_iss_unit.io.wakeup_ports[3].bits.uop.is_sfb, int_wakeups[3].bits.uop.is_sfb connect mem_iss_unit.io.wakeup_ports[3].bits.uop.br_type, int_wakeups[3].bits.uop.br_type connect mem_iss_unit.io.wakeup_ports[3].bits.uop.br_tag, int_wakeups[3].bits.uop.br_tag connect mem_iss_unit.io.wakeup_ports[3].bits.uop.br_mask, int_wakeups[3].bits.uop.br_mask connect mem_iss_unit.io.wakeup_ports[3].bits.uop.dis_col_sel, int_wakeups[3].bits.uop.dis_col_sel connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, int_wakeups[3].bits.uop.iw_p3_bypass_hint connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, int_wakeups[3].bits.uop.iw_p2_bypass_hint connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, int_wakeups[3].bits.uop.iw_p1_bypass_hint connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, int_wakeups[3].bits.uop.iw_p2_speculative_child connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, int_wakeups[3].bits.uop.iw_p1_speculative_child connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, int_wakeups[3].bits.uop.iw_issued_partial_dgen connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, int_wakeups[3].bits.uop.iw_issued_partial_agen connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iw_issued, int_wakeups[3].bits.uop.iw_issued connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[0], int_wakeups[3].bits.uop.fu_code[0] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[1], int_wakeups[3].bits.uop.fu_code[1] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[2], int_wakeups[3].bits.uop.fu_code[2] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[3], int_wakeups[3].bits.uop.fu_code[3] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[4], int_wakeups[3].bits.uop.fu_code[4] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[5], int_wakeups[3].bits.uop.fu_code[5] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[6], int_wakeups[3].bits.uop.fu_code[6] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[7], int_wakeups[3].bits.uop.fu_code[7] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[8], int_wakeups[3].bits.uop.fu_code[8] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[9], int_wakeups[3].bits.uop.fu_code[9] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[0], int_wakeups[3].bits.uop.iq_type[0] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[1], int_wakeups[3].bits.uop.iq_type[1] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[2], int_wakeups[3].bits.uop.iq_type[2] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[3], int_wakeups[3].bits.uop.iq_type[3] connect mem_iss_unit.io.wakeup_ports[3].bits.uop.debug_pc, int_wakeups[3].bits.uop.debug_pc connect mem_iss_unit.io.wakeup_ports[3].bits.uop.is_rvc, int_wakeups[3].bits.uop.is_rvc connect mem_iss_unit.io.wakeup_ports[3].bits.uop.debug_inst, int_wakeups[3].bits.uop.debug_inst connect mem_iss_unit.io.wakeup_ports[3].bits.uop.inst, int_wakeups[3].bits.uop.inst connect mem_iss_unit.io.wakeup_ports[3].valid, int_wakeups[3].valid connect alu_iss_unit.io.tsc_reg, debug_tsc_reg connect alu_iss_unit.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect alu_iss_unit.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect alu_iss_unit.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect alu_iss_unit.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect alu_iss_unit.io.brupdate.b2.taken, brupdate.b2.taken connect alu_iss_unit.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect alu_iss_unit.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect alu_iss_unit.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect alu_iss_unit.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect alu_iss_unit.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect alu_iss_unit.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect alu_iss_unit.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect alu_iss_unit.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect alu_iss_unit.io.brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect alu_iss_unit.io.brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect alu_iss_unit.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect alu_iss_unit.io.brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect alu_iss_unit.io.brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect alu_iss_unit.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect alu_iss_unit.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect alu_iss_unit.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect alu_iss_unit.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect alu_iss_unit.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect alu_iss_unit.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect alu_iss_unit.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect alu_iss_unit.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect alu_iss_unit.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect alu_iss_unit.io.brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect alu_iss_unit.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect alu_iss_unit.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect alu_iss_unit.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect alu_iss_unit.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect alu_iss_unit.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect alu_iss_unit.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect alu_iss_unit.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect alu_iss_unit.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect alu_iss_unit.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect alu_iss_unit.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect alu_iss_unit.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect alu_iss_unit.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect alu_iss_unit.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect alu_iss_unit.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect alu_iss_unit.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect alu_iss_unit.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect alu_iss_unit.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect alu_iss_unit.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect alu_iss_unit.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect alu_iss_unit.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect alu_iss_unit.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect alu_iss_unit.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect alu_iss_unit.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect alu_iss_unit.io.brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect alu_iss_unit.io.brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect alu_iss_unit.io.brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect alu_iss_unit.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect alu_iss_unit.io.brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect alu_iss_unit.io.brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect alu_iss_unit.io.brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect alu_iss_unit.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect alu_iss_unit.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect alu_iss_unit.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect alu_iss_unit.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect alu_iss_unit.io.brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect alu_iss_unit.io.brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect alu_iss_unit.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect alu_iss_unit.io.brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect alu_iss_unit.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect alu_iss_unit.io.brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect alu_iss_unit.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect alu_iss_unit.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect alu_iss_unit.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect alu_iss_unit.io.brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect alu_iss_unit.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect alu_iss_unit.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect alu_iss_unit.io.brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect alu_iss_unit.io.brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect alu_iss_unit.io.brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect alu_iss_unit.io.brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect alu_iss_unit.io.brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect alu_iss_unit.io.brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect alu_iss_unit.io.brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect alu_iss_unit.io.brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect alu_iss_unit.io.brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect alu_iss_unit.io.brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect alu_iss_unit.io.brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect alu_iss_unit.io.brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect alu_iss_unit.io.brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect alu_iss_unit.io.brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect alu_iss_unit.io.brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect alu_iss_unit.io.brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect alu_iss_unit.io.brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect alu_iss_unit.io.brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect alu_iss_unit.io.brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect alu_iss_unit.io.brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect alu_iss_unit.io.brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect alu_iss_unit.io.brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect alu_iss_unit.io.brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect alu_iss_unit.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect alu_iss_unit.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect alu_iss_unit.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect alu_iss_unit.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect alu_iss_unit.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect alu_iss_unit.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask reg alu_iss_unit_io_flush_pipeline_REG : UInt<1>, clock connect alu_iss_unit_io_flush_pipeline_REG, rob.io.flush.valid connect alu_iss_unit.io.flush_pipeline, alu_iss_unit_io_flush_pipeline_REG node _alu_iss_unit_io_child_rebusys_T = or(alu_exe_unit_0.io_child_rebusy, alu_exe_unit_1.io_child_rebusy) connect alu_iss_unit.io.child_rebusys, _alu_iss_unit_io_child_rebusys_T connect alu_iss_unit.io.wakeup_ports[0].bits.rebusy, int_wakeups[0].bits.rebusy connect alu_iss_unit.io.wakeup_ports[0].bits.speculative_mask, int_wakeups[0].bits.speculative_mask connect alu_iss_unit.io.wakeup_ports[0].bits.bypassable, int_wakeups[0].bits.bypassable connect alu_iss_unit.io.wakeup_ports[0].bits.uop.debug_tsrc, int_wakeups[0].bits.uop.debug_tsrc connect alu_iss_unit.io.wakeup_ports[0].bits.uop.debug_fsrc, int_wakeups[0].bits.uop.debug_fsrc connect alu_iss_unit.io.wakeup_ports[0].bits.uop.bp_xcpt_if, int_wakeups[0].bits.uop.bp_xcpt_if connect alu_iss_unit.io.wakeup_ports[0].bits.uop.bp_debug_if, int_wakeups[0].bits.uop.bp_debug_if connect alu_iss_unit.io.wakeup_ports[0].bits.uop.xcpt_ma_if, int_wakeups[0].bits.uop.xcpt_ma_if connect alu_iss_unit.io.wakeup_ports[0].bits.uop.xcpt_ae_if, int_wakeups[0].bits.uop.xcpt_ae_if connect alu_iss_unit.io.wakeup_ports[0].bits.uop.xcpt_pf_if, int_wakeups[0].bits.uop.xcpt_pf_if connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_typ, int_wakeups[0].bits.uop.fp_typ connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_rm, int_wakeups[0].bits.uop.fp_rm connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_val, int_wakeups[0].bits.uop.fp_val connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fcn_op, int_wakeups[0].bits.uop.fcn_op connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fcn_dw, int_wakeups[0].bits.uop.fcn_dw connect alu_iss_unit.io.wakeup_ports[0].bits.uop.frs3_en, int_wakeups[0].bits.uop.frs3_en connect alu_iss_unit.io.wakeup_ports[0].bits.uop.lrs2_rtype, int_wakeups[0].bits.uop.lrs2_rtype connect alu_iss_unit.io.wakeup_ports[0].bits.uop.lrs1_rtype, int_wakeups[0].bits.uop.lrs1_rtype connect alu_iss_unit.io.wakeup_ports[0].bits.uop.dst_rtype, int_wakeups[0].bits.uop.dst_rtype connect alu_iss_unit.io.wakeup_ports[0].bits.uop.lrs3, int_wakeups[0].bits.uop.lrs3 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.lrs2, int_wakeups[0].bits.uop.lrs2 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.lrs1, int_wakeups[0].bits.uop.lrs1 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.ldst, int_wakeups[0].bits.uop.ldst connect alu_iss_unit.io.wakeup_ports[0].bits.uop.ldst_is_rs1, int_wakeups[0].bits.uop.ldst_is_rs1 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.csr_cmd, int_wakeups[0].bits.uop.csr_cmd connect alu_iss_unit.io.wakeup_ports[0].bits.uop.flush_on_commit, int_wakeups[0].bits.uop.flush_on_commit connect alu_iss_unit.io.wakeup_ports[0].bits.uop.is_unique, int_wakeups[0].bits.uop.is_unique connect alu_iss_unit.io.wakeup_ports[0].bits.uop.uses_stq, int_wakeups[0].bits.uop.uses_stq connect alu_iss_unit.io.wakeup_ports[0].bits.uop.uses_ldq, int_wakeups[0].bits.uop.uses_ldq connect alu_iss_unit.io.wakeup_ports[0].bits.uop.mem_signed, int_wakeups[0].bits.uop.mem_signed connect alu_iss_unit.io.wakeup_ports[0].bits.uop.mem_size, int_wakeups[0].bits.uop.mem_size connect alu_iss_unit.io.wakeup_ports[0].bits.uop.mem_cmd, int_wakeups[0].bits.uop.mem_cmd connect alu_iss_unit.io.wakeup_ports[0].bits.uop.exc_cause, int_wakeups[0].bits.uop.exc_cause connect alu_iss_unit.io.wakeup_ports[0].bits.uop.exception, int_wakeups[0].bits.uop.exception connect alu_iss_unit.io.wakeup_ports[0].bits.uop.stale_pdst, int_wakeups[0].bits.uop.stale_pdst connect alu_iss_unit.io.wakeup_ports[0].bits.uop.ppred_busy, int_wakeups[0].bits.uop.ppred_busy connect alu_iss_unit.io.wakeup_ports[0].bits.uop.prs3_busy, int_wakeups[0].bits.uop.prs3_busy connect alu_iss_unit.io.wakeup_ports[0].bits.uop.prs2_busy, int_wakeups[0].bits.uop.prs2_busy connect alu_iss_unit.io.wakeup_ports[0].bits.uop.prs1_busy, int_wakeups[0].bits.uop.prs1_busy connect alu_iss_unit.io.wakeup_ports[0].bits.uop.ppred, int_wakeups[0].bits.uop.ppred connect alu_iss_unit.io.wakeup_ports[0].bits.uop.prs3, int_wakeups[0].bits.uop.prs3 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.prs2, int_wakeups[0].bits.uop.prs2 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.prs1, int_wakeups[0].bits.uop.prs1 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.pdst, int_wakeups[0].bits.uop.pdst connect alu_iss_unit.io.wakeup_ports[0].bits.uop.rxq_idx, int_wakeups[0].bits.uop.rxq_idx connect alu_iss_unit.io.wakeup_ports[0].bits.uop.stq_idx, int_wakeups[0].bits.uop.stq_idx connect alu_iss_unit.io.wakeup_ports[0].bits.uop.ldq_idx, int_wakeups[0].bits.uop.ldq_idx connect alu_iss_unit.io.wakeup_ports[0].bits.uop.rob_idx, int_wakeups[0].bits.uop.rob_idx connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, int_wakeups[0].bits.uop.fp_ctrl.vec connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, int_wakeups[0].bits.uop.fp_ctrl.wflags connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, int_wakeups[0].bits.uop.fp_ctrl.sqrt connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.div, int_wakeups[0].bits.uop.fp_ctrl.div connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, int_wakeups[0].bits.uop.fp_ctrl.fma connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, int_wakeups[0].bits.uop.fp_ctrl.fastpipe connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, int_wakeups[0].bits.uop.fp_ctrl.toint connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, int_wakeups[0].bits.uop.fp_ctrl.fromint connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, int_wakeups[0].bits.uop.fp_ctrl.typeTagOut connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, int_wakeups[0].bits.uop.fp_ctrl.typeTagIn connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, int_wakeups[0].bits.uop.fp_ctrl.swap23 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, int_wakeups[0].bits.uop.fp_ctrl.swap12 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, int_wakeups[0].bits.uop.fp_ctrl.ren3 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, int_wakeups[0].bits.uop.fp_ctrl.ren2 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, int_wakeups[0].bits.uop.fp_ctrl.ren1 connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, int_wakeups[0].bits.uop.fp_ctrl.wen connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, int_wakeups[0].bits.uop.fp_ctrl.ldst connect alu_iss_unit.io.wakeup_ports[0].bits.uop.op2_sel, int_wakeups[0].bits.uop.op2_sel connect alu_iss_unit.io.wakeup_ports[0].bits.uop.op1_sel, int_wakeups[0].bits.uop.op1_sel connect alu_iss_unit.io.wakeup_ports[0].bits.uop.imm_packed, int_wakeups[0].bits.uop.imm_packed connect alu_iss_unit.io.wakeup_ports[0].bits.uop.pimm, int_wakeups[0].bits.uop.pimm connect alu_iss_unit.io.wakeup_ports[0].bits.uop.imm_sel, int_wakeups[0].bits.uop.imm_sel connect alu_iss_unit.io.wakeup_ports[0].bits.uop.imm_rename, int_wakeups[0].bits.uop.imm_rename connect alu_iss_unit.io.wakeup_ports[0].bits.uop.taken, int_wakeups[0].bits.uop.taken connect alu_iss_unit.io.wakeup_ports[0].bits.uop.pc_lob, int_wakeups[0].bits.uop.pc_lob connect alu_iss_unit.io.wakeup_ports[0].bits.uop.edge_inst, int_wakeups[0].bits.uop.edge_inst connect alu_iss_unit.io.wakeup_ports[0].bits.uop.ftq_idx, int_wakeups[0].bits.uop.ftq_idx connect alu_iss_unit.io.wakeup_ports[0].bits.uop.is_mov, int_wakeups[0].bits.uop.is_mov connect alu_iss_unit.io.wakeup_ports[0].bits.uop.is_rocc, int_wakeups[0].bits.uop.is_rocc connect alu_iss_unit.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, int_wakeups[0].bits.uop.is_sys_pc2epc connect alu_iss_unit.io.wakeup_ports[0].bits.uop.is_eret, int_wakeups[0].bits.uop.is_eret connect alu_iss_unit.io.wakeup_ports[0].bits.uop.is_amo, int_wakeups[0].bits.uop.is_amo connect alu_iss_unit.io.wakeup_ports[0].bits.uop.is_sfence, int_wakeups[0].bits.uop.is_sfence connect alu_iss_unit.io.wakeup_ports[0].bits.uop.is_fencei, int_wakeups[0].bits.uop.is_fencei connect alu_iss_unit.io.wakeup_ports[0].bits.uop.is_fence, int_wakeups[0].bits.uop.is_fence connect alu_iss_unit.io.wakeup_ports[0].bits.uop.is_sfb, int_wakeups[0].bits.uop.is_sfb connect alu_iss_unit.io.wakeup_ports[0].bits.uop.br_type, int_wakeups[0].bits.uop.br_type connect alu_iss_unit.io.wakeup_ports[0].bits.uop.br_tag, int_wakeups[0].bits.uop.br_tag connect alu_iss_unit.io.wakeup_ports[0].bits.uop.br_mask, int_wakeups[0].bits.uop.br_mask connect alu_iss_unit.io.wakeup_ports[0].bits.uop.dis_col_sel, int_wakeups[0].bits.uop.dis_col_sel connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, int_wakeups[0].bits.uop.iw_p3_bypass_hint connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, int_wakeups[0].bits.uop.iw_p2_bypass_hint connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, int_wakeups[0].bits.uop.iw_p1_bypass_hint connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, int_wakeups[0].bits.uop.iw_p2_speculative_child connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, int_wakeups[0].bits.uop.iw_p1_speculative_child connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, int_wakeups[0].bits.uop.iw_issued_partial_dgen connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, int_wakeups[0].bits.uop.iw_issued_partial_agen connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iw_issued, int_wakeups[0].bits.uop.iw_issued connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[0], int_wakeups[0].bits.uop.fu_code[0] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[1], int_wakeups[0].bits.uop.fu_code[1] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[2], int_wakeups[0].bits.uop.fu_code[2] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[3], int_wakeups[0].bits.uop.fu_code[3] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[4], int_wakeups[0].bits.uop.fu_code[4] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[5], int_wakeups[0].bits.uop.fu_code[5] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[6], int_wakeups[0].bits.uop.fu_code[6] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[7], int_wakeups[0].bits.uop.fu_code[7] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[8], int_wakeups[0].bits.uop.fu_code[8] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[9], int_wakeups[0].bits.uop.fu_code[9] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[0], int_wakeups[0].bits.uop.iq_type[0] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[1], int_wakeups[0].bits.uop.iq_type[1] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[2], int_wakeups[0].bits.uop.iq_type[2] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[3], int_wakeups[0].bits.uop.iq_type[3] connect alu_iss_unit.io.wakeup_ports[0].bits.uop.debug_pc, int_wakeups[0].bits.uop.debug_pc connect alu_iss_unit.io.wakeup_ports[0].bits.uop.is_rvc, int_wakeups[0].bits.uop.is_rvc connect alu_iss_unit.io.wakeup_ports[0].bits.uop.debug_inst, int_wakeups[0].bits.uop.debug_inst connect alu_iss_unit.io.wakeup_ports[0].bits.uop.inst, int_wakeups[0].bits.uop.inst connect alu_iss_unit.io.wakeup_ports[0].valid, int_wakeups[0].valid connect alu_iss_unit.io.wakeup_ports[1].bits.rebusy, int_wakeups[1].bits.rebusy connect alu_iss_unit.io.wakeup_ports[1].bits.speculative_mask, int_wakeups[1].bits.speculative_mask connect alu_iss_unit.io.wakeup_ports[1].bits.bypassable, int_wakeups[1].bits.bypassable connect alu_iss_unit.io.wakeup_ports[1].bits.uop.debug_tsrc, int_wakeups[1].bits.uop.debug_tsrc connect alu_iss_unit.io.wakeup_ports[1].bits.uop.debug_fsrc, int_wakeups[1].bits.uop.debug_fsrc connect alu_iss_unit.io.wakeup_ports[1].bits.uop.bp_xcpt_if, int_wakeups[1].bits.uop.bp_xcpt_if connect alu_iss_unit.io.wakeup_ports[1].bits.uop.bp_debug_if, int_wakeups[1].bits.uop.bp_debug_if connect alu_iss_unit.io.wakeup_ports[1].bits.uop.xcpt_ma_if, int_wakeups[1].bits.uop.xcpt_ma_if connect alu_iss_unit.io.wakeup_ports[1].bits.uop.xcpt_ae_if, int_wakeups[1].bits.uop.xcpt_ae_if connect alu_iss_unit.io.wakeup_ports[1].bits.uop.xcpt_pf_if, int_wakeups[1].bits.uop.xcpt_pf_if connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_typ, int_wakeups[1].bits.uop.fp_typ connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_rm, int_wakeups[1].bits.uop.fp_rm connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_val, int_wakeups[1].bits.uop.fp_val connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fcn_op, int_wakeups[1].bits.uop.fcn_op connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fcn_dw, int_wakeups[1].bits.uop.fcn_dw connect alu_iss_unit.io.wakeup_ports[1].bits.uop.frs3_en, int_wakeups[1].bits.uop.frs3_en connect alu_iss_unit.io.wakeup_ports[1].bits.uop.lrs2_rtype, int_wakeups[1].bits.uop.lrs2_rtype connect alu_iss_unit.io.wakeup_ports[1].bits.uop.lrs1_rtype, int_wakeups[1].bits.uop.lrs1_rtype connect alu_iss_unit.io.wakeup_ports[1].bits.uop.dst_rtype, int_wakeups[1].bits.uop.dst_rtype connect alu_iss_unit.io.wakeup_ports[1].bits.uop.lrs3, int_wakeups[1].bits.uop.lrs3 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.lrs2, int_wakeups[1].bits.uop.lrs2 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.lrs1, int_wakeups[1].bits.uop.lrs1 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.ldst, int_wakeups[1].bits.uop.ldst connect alu_iss_unit.io.wakeup_ports[1].bits.uop.ldst_is_rs1, int_wakeups[1].bits.uop.ldst_is_rs1 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.csr_cmd, int_wakeups[1].bits.uop.csr_cmd connect alu_iss_unit.io.wakeup_ports[1].bits.uop.flush_on_commit, int_wakeups[1].bits.uop.flush_on_commit connect alu_iss_unit.io.wakeup_ports[1].bits.uop.is_unique, int_wakeups[1].bits.uop.is_unique connect alu_iss_unit.io.wakeup_ports[1].bits.uop.uses_stq, int_wakeups[1].bits.uop.uses_stq connect alu_iss_unit.io.wakeup_ports[1].bits.uop.uses_ldq, int_wakeups[1].bits.uop.uses_ldq connect alu_iss_unit.io.wakeup_ports[1].bits.uop.mem_signed, int_wakeups[1].bits.uop.mem_signed connect alu_iss_unit.io.wakeup_ports[1].bits.uop.mem_size, int_wakeups[1].bits.uop.mem_size connect alu_iss_unit.io.wakeup_ports[1].bits.uop.mem_cmd, int_wakeups[1].bits.uop.mem_cmd connect alu_iss_unit.io.wakeup_ports[1].bits.uop.exc_cause, int_wakeups[1].bits.uop.exc_cause connect alu_iss_unit.io.wakeup_ports[1].bits.uop.exception, int_wakeups[1].bits.uop.exception connect alu_iss_unit.io.wakeup_ports[1].bits.uop.stale_pdst, int_wakeups[1].bits.uop.stale_pdst connect alu_iss_unit.io.wakeup_ports[1].bits.uop.ppred_busy, int_wakeups[1].bits.uop.ppred_busy connect alu_iss_unit.io.wakeup_ports[1].bits.uop.prs3_busy, int_wakeups[1].bits.uop.prs3_busy connect alu_iss_unit.io.wakeup_ports[1].bits.uop.prs2_busy, int_wakeups[1].bits.uop.prs2_busy connect alu_iss_unit.io.wakeup_ports[1].bits.uop.prs1_busy, int_wakeups[1].bits.uop.prs1_busy connect alu_iss_unit.io.wakeup_ports[1].bits.uop.ppred, int_wakeups[1].bits.uop.ppred connect alu_iss_unit.io.wakeup_ports[1].bits.uop.prs3, int_wakeups[1].bits.uop.prs3 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.prs2, int_wakeups[1].bits.uop.prs2 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.prs1, int_wakeups[1].bits.uop.prs1 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.pdst, int_wakeups[1].bits.uop.pdst connect alu_iss_unit.io.wakeup_ports[1].bits.uop.rxq_idx, int_wakeups[1].bits.uop.rxq_idx connect alu_iss_unit.io.wakeup_ports[1].bits.uop.stq_idx, int_wakeups[1].bits.uop.stq_idx connect alu_iss_unit.io.wakeup_ports[1].bits.uop.ldq_idx, int_wakeups[1].bits.uop.ldq_idx connect alu_iss_unit.io.wakeup_ports[1].bits.uop.rob_idx, int_wakeups[1].bits.uop.rob_idx connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, int_wakeups[1].bits.uop.fp_ctrl.vec connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, int_wakeups[1].bits.uop.fp_ctrl.wflags connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, int_wakeups[1].bits.uop.fp_ctrl.sqrt connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.div, int_wakeups[1].bits.uop.fp_ctrl.div connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, int_wakeups[1].bits.uop.fp_ctrl.fma connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, int_wakeups[1].bits.uop.fp_ctrl.fastpipe connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, int_wakeups[1].bits.uop.fp_ctrl.toint connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, int_wakeups[1].bits.uop.fp_ctrl.fromint connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, int_wakeups[1].bits.uop.fp_ctrl.typeTagOut connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, int_wakeups[1].bits.uop.fp_ctrl.typeTagIn connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, int_wakeups[1].bits.uop.fp_ctrl.swap23 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, int_wakeups[1].bits.uop.fp_ctrl.swap12 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, int_wakeups[1].bits.uop.fp_ctrl.ren3 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, int_wakeups[1].bits.uop.fp_ctrl.ren2 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, int_wakeups[1].bits.uop.fp_ctrl.ren1 connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, int_wakeups[1].bits.uop.fp_ctrl.wen connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, int_wakeups[1].bits.uop.fp_ctrl.ldst connect alu_iss_unit.io.wakeup_ports[1].bits.uop.op2_sel, int_wakeups[1].bits.uop.op2_sel connect alu_iss_unit.io.wakeup_ports[1].bits.uop.op1_sel, int_wakeups[1].bits.uop.op1_sel connect alu_iss_unit.io.wakeup_ports[1].bits.uop.imm_packed, int_wakeups[1].bits.uop.imm_packed connect alu_iss_unit.io.wakeup_ports[1].bits.uop.pimm, int_wakeups[1].bits.uop.pimm connect alu_iss_unit.io.wakeup_ports[1].bits.uop.imm_sel, int_wakeups[1].bits.uop.imm_sel connect alu_iss_unit.io.wakeup_ports[1].bits.uop.imm_rename, int_wakeups[1].bits.uop.imm_rename connect alu_iss_unit.io.wakeup_ports[1].bits.uop.taken, int_wakeups[1].bits.uop.taken connect alu_iss_unit.io.wakeup_ports[1].bits.uop.pc_lob, int_wakeups[1].bits.uop.pc_lob connect alu_iss_unit.io.wakeup_ports[1].bits.uop.edge_inst, int_wakeups[1].bits.uop.edge_inst connect alu_iss_unit.io.wakeup_ports[1].bits.uop.ftq_idx, int_wakeups[1].bits.uop.ftq_idx connect alu_iss_unit.io.wakeup_ports[1].bits.uop.is_mov, int_wakeups[1].bits.uop.is_mov connect alu_iss_unit.io.wakeup_ports[1].bits.uop.is_rocc, int_wakeups[1].bits.uop.is_rocc connect alu_iss_unit.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, int_wakeups[1].bits.uop.is_sys_pc2epc connect alu_iss_unit.io.wakeup_ports[1].bits.uop.is_eret, int_wakeups[1].bits.uop.is_eret connect alu_iss_unit.io.wakeup_ports[1].bits.uop.is_amo, int_wakeups[1].bits.uop.is_amo connect alu_iss_unit.io.wakeup_ports[1].bits.uop.is_sfence, int_wakeups[1].bits.uop.is_sfence connect alu_iss_unit.io.wakeup_ports[1].bits.uop.is_fencei, int_wakeups[1].bits.uop.is_fencei connect alu_iss_unit.io.wakeup_ports[1].bits.uop.is_fence, int_wakeups[1].bits.uop.is_fence connect alu_iss_unit.io.wakeup_ports[1].bits.uop.is_sfb, int_wakeups[1].bits.uop.is_sfb connect alu_iss_unit.io.wakeup_ports[1].bits.uop.br_type, int_wakeups[1].bits.uop.br_type connect alu_iss_unit.io.wakeup_ports[1].bits.uop.br_tag, int_wakeups[1].bits.uop.br_tag connect alu_iss_unit.io.wakeup_ports[1].bits.uop.br_mask, int_wakeups[1].bits.uop.br_mask connect alu_iss_unit.io.wakeup_ports[1].bits.uop.dis_col_sel, int_wakeups[1].bits.uop.dis_col_sel connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, int_wakeups[1].bits.uop.iw_p3_bypass_hint connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, int_wakeups[1].bits.uop.iw_p2_bypass_hint connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, int_wakeups[1].bits.uop.iw_p1_bypass_hint connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, int_wakeups[1].bits.uop.iw_p2_speculative_child connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, int_wakeups[1].bits.uop.iw_p1_speculative_child connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, int_wakeups[1].bits.uop.iw_issued_partial_dgen connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, int_wakeups[1].bits.uop.iw_issued_partial_agen connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iw_issued, int_wakeups[1].bits.uop.iw_issued connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[0], int_wakeups[1].bits.uop.fu_code[0] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[1], int_wakeups[1].bits.uop.fu_code[1] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[2], int_wakeups[1].bits.uop.fu_code[2] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[3], int_wakeups[1].bits.uop.fu_code[3] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[4], int_wakeups[1].bits.uop.fu_code[4] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[5], int_wakeups[1].bits.uop.fu_code[5] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[6], int_wakeups[1].bits.uop.fu_code[6] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[7], int_wakeups[1].bits.uop.fu_code[7] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[8], int_wakeups[1].bits.uop.fu_code[8] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[9], int_wakeups[1].bits.uop.fu_code[9] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[0], int_wakeups[1].bits.uop.iq_type[0] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[1], int_wakeups[1].bits.uop.iq_type[1] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[2], int_wakeups[1].bits.uop.iq_type[2] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[3], int_wakeups[1].bits.uop.iq_type[3] connect alu_iss_unit.io.wakeup_ports[1].bits.uop.debug_pc, int_wakeups[1].bits.uop.debug_pc connect alu_iss_unit.io.wakeup_ports[1].bits.uop.is_rvc, int_wakeups[1].bits.uop.is_rvc connect alu_iss_unit.io.wakeup_ports[1].bits.uop.debug_inst, int_wakeups[1].bits.uop.debug_inst connect alu_iss_unit.io.wakeup_ports[1].bits.uop.inst, int_wakeups[1].bits.uop.inst connect alu_iss_unit.io.wakeup_ports[1].valid, int_wakeups[1].valid connect alu_iss_unit.io.wakeup_ports[2].bits.rebusy, int_wakeups[2].bits.rebusy connect alu_iss_unit.io.wakeup_ports[2].bits.speculative_mask, int_wakeups[2].bits.speculative_mask connect alu_iss_unit.io.wakeup_ports[2].bits.bypassable, int_wakeups[2].bits.bypassable connect alu_iss_unit.io.wakeup_ports[2].bits.uop.debug_tsrc, int_wakeups[2].bits.uop.debug_tsrc connect alu_iss_unit.io.wakeup_ports[2].bits.uop.debug_fsrc, int_wakeups[2].bits.uop.debug_fsrc connect alu_iss_unit.io.wakeup_ports[2].bits.uop.bp_xcpt_if, int_wakeups[2].bits.uop.bp_xcpt_if connect alu_iss_unit.io.wakeup_ports[2].bits.uop.bp_debug_if, int_wakeups[2].bits.uop.bp_debug_if connect alu_iss_unit.io.wakeup_ports[2].bits.uop.xcpt_ma_if, int_wakeups[2].bits.uop.xcpt_ma_if connect alu_iss_unit.io.wakeup_ports[2].bits.uop.xcpt_ae_if, int_wakeups[2].bits.uop.xcpt_ae_if connect alu_iss_unit.io.wakeup_ports[2].bits.uop.xcpt_pf_if, int_wakeups[2].bits.uop.xcpt_pf_if connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_typ, int_wakeups[2].bits.uop.fp_typ connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_rm, int_wakeups[2].bits.uop.fp_rm connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_val, int_wakeups[2].bits.uop.fp_val connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fcn_op, int_wakeups[2].bits.uop.fcn_op connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fcn_dw, int_wakeups[2].bits.uop.fcn_dw connect alu_iss_unit.io.wakeup_ports[2].bits.uop.frs3_en, int_wakeups[2].bits.uop.frs3_en connect alu_iss_unit.io.wakeup_ports[2].bits.uop.lrs2_rtype, int_wakeups[2].bits.uop.lrs2_rtype connect alu_iss_unit.io.wakeup_ports[2].bits.uop.lrs1_rtype, int_wakeups[2].bits.uop.lrs1_rtype connect alu_iss_unit.io.wakeup_ports[2].bits.uop.dst_rtype, int_wakeups[2].bits.uop.dst_rtype connect alu_iss_unit.io.wakeup_ports[2].bits.uop.lrs3, int_wakeups[2].bits.uop.lrs3 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.lrs2, int_wakeups[2].bits.uop.lrs2 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.lrs1, int_wakeups[2].bits.uop.lrs1 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.ldst, int_wakeups[2].bits.uop.ldst connect alu_iss_unit.io.wakeup_ports[2].bits.uop.ldst_is_rs1, int_wakeups[2].bits.uop.ldst_is_rs1 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.csr_cmd, int_wakeups[2].bits.uop.csr_cmd connect alu_iss_unit.io.wakeup_ports[2].bits.uop.flush_on_commit, int_wakeups[2].bits.uop.flush_on_commit connect alu_iss_unit.io.wakeup_ports[2].bits.uop.is_unique, int_wakeups[2].bits.uop.is_unique connect alu_iss_unit.io.wakeup_ports[2].bits.uop.uses_stq, int_wakeups[2].bits.uop.uses_stq connect alu_iss_unit.io.wakeup_ports[2].bits.uop.uses_ldq, int_wakeups[2].bits.uop.uses_ldq connect alu_iss_unit.io.wakeup_ports[2].bits.uop.mem_signed, int_wakeups[2].bits.uop.mem_signed connect alu_iss_unit.io.wakeup_ports[2].bits.uop.mem_size, int_wakeups[2].bits.uop.mem_size connect alu_iss_unit.io.wakeup_ports[2].bits.uop.mem_cmd, int_wakeups[2].bits.uop.mem_cmd connect alu_iss_unit.io.wakeup_ports[2].bits.uop.exc_cause, int_wakeups[2].bits.uop.exc_cause connect alu_iss_unit.io.wakeup_ports[2].bits.uop.exception, int_wakeups[2].bits.uop.exception connect alu_iss_unit.io.wakeup_ports[2].bits.uop.stale_pdst, int_wakeups[2].bits.uop.stale_pdst connect alu_iss_unit.io.wakeup_ports[2].bits.uop.ppred_busy, int_wakeups[2].bits.uop.ppred_busy connect alu_iss_unit.io.wakeup_ports[2].bits.uop.prs3_busy, int_wakeups[2].bits.uop.prs3_busy connect alu_iss_unit.io.wakeup_ports[2].bits.uop.prs2_busy, int_wakeups[2].bits.uop.prs2_busy connect alu_iss_unit.io.wakeup_ports[2].bits.uop.prs1_busy, int_wakeups[2].bits.uop.prs1_busy connect alu_iss_unit.io.wakeup_ports[2].bits.uop.ppred, int_wakeups[2].bits.uop.ppred connect alu_iss_unit.io.wakeup_ports[2].bits.uop.prs3, int_wakeups[2].bits.uop.prs3 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.prs2, int_wakeups[2].bits.uop.prs2 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.prs1, int_wakeups[2].bits.uop.prs1 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.pdst, int_wakeups[2].bits.uop.pdst connect alu_iss_unit.io.wakeup_ports[2].bits.uop.rxq_idx, int_wakeups[2].bits.uop.rxq_idx connect alu_iss_unit.io.wakeup_ports[2].bits.uop.stq_idx, int_wakeups[2].bits.uop.stq_idx connect alu_iss_unit.io.wakeup_ports[2].bits.uop.ldq_idx, int_wakeups[2].bits.uop.ldq_idx connect alu_iss_unit.io.wakeup_ports[2].bits.uop.rob_idx, int_wakeups[2].bits.uop.rob_idx connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, int_wakeups[2].bits.uop.fp_ctrl.vec connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, int_wakeups[2].bits.uop.fp_ctrl.wflags connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, int_wakeups[2].bits.uop.fp_ctrl.sqrt connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.div, int_wakeups[2].bits.uop.fp_ctrl.div connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, int_wakeups[2].bits.uop.fp_ctrl.fma connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, int_wakeups[2].bits.uop.fp_ctrl.fastpipe connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, int_wakeups[2].bits.uop.fp_ctrl.toint connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, int_wakeups[2].bits.uop.fp_ctrl.fromint connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, int_wakeups[2].bits.uop.fp_ctrl.typeTagOut connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, int_wakeups[2].bits.uop.fp_ctrl.typeTagIn connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, int_wakeups[2].bits.uop.fp_ctrl.swap23 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, int_wakeups[2].bits.uop.fp_ctrl.swap12 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, int_wakeups[2].bits.uop.fp_ctrl.ren3 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, int_wakeups[2].bits.uop.fp_ctrl.ren2 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, int_wakeups[2].bits.uop.fp_ctrl.ren1 connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, int_wakeups[2].bits.uop.fp_ctrl.wen connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, int_wakeups[2].bits.uop.fp_ctrl.ldst connect alu_iss_unit.io.wakeup_ports[2].bits.uop.op2_sel, int_wakeups[2].bits.uop.op2_sel connect alu_iss_unit.io.wakeup_ports[2].bits.uop.op1_sel, int_wakeups[2].bits.uop.op1_sel connect alu_iss_unit.io.wakeup_ports[2].bits.uop.imm_packed, int_wakeups[2].bits.uop.imm_packed connect alu_iss_unit.io.wakeup_ports[2].bits.uop.pimm, int_wakeups[2].bits.uop.pimm connect alu_iss_unit.io.wakeup_ports[2].bits.uop.imm_sel, int_wakeups[2].bits.uop.imm_sel connect alu_iss_unit.io.wakeup_ports[2].bits.uop.imm_rename, int_wakeups[2].bits.uop.imm_rename connect alu_iss_unit.io.wakeup_ports[2].bits.uop.taken, int_wakeups[2].bits.uop.taken connect alu_iss_unit.io.wakeup_ports[2].bits.uop.pc_lob, int_wakeups[2].bits.uop.pc_lob connect alu_iss_unit.io.wakeup_ports[2].bits.uop.edge_inst, int_wakeups[2].bits.uop.edge_inst connect alu_iss_unit.io.wakeup_ports[2].bits.uop.ftq_idx, int_wakeups[2].bits.uop.ftq_idx connect alu_iss_unit.io.wakeup_ports[2].bits.uop.is_mov, int_wakeups[2].bits.uop.is_mov connect alu_iss_unit.io.wakeup_ports[2].bits.uop.is_rocc, int_wakeups[2].bits.uop.is_rocc connect alu_iss_unit.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, int_wakeups[2].bits.uop.is_sys_pc2epc connect alu_iss_unit.io.wakeup_ports[2].bits.uop.is_eret, int_wakeups[2].bits.uop.is_eret connect alu_iss_unit.io.wakeup_ports[2].bits.uop.is_amo, int_wakeups[2].bits.uop.is_amo connect alu_iss_unit.io.wakeup_ports[2].bits.uop.is_sfence, int_wakeups[2].bits.uop.is_sfence connect alu_iss_unit.io.wakeup_ports[2].bits.uop.is_fencei, int_wakeups[2].bits.uop.is_fencei connect alu_iss_unit.io.wakeup_ports[2].bits.uop.is_fence, int_wakeups[2].bits.uop.is_fence connect alu_iss_unit.io.wakeup_ports[2].bits.uop.is_sfb, int_wakeups[2].bits.uop.is_sfb connect alu_iss_unit.io.wakeup_ports[2].bits.uop.br_type, int_wakeups[2].bits.uop.br_type connect alu_iss_unit.io.wakeup_ports[2].bits.uop.br_tag, int_wakeups[2].bits.uop.br_tag connect alu_iss_unit.io.wakeup_ports[2].bits.uop.br_mask, int_wakeups[2].bits.uop.br_mask connect alu_iss_unit.io.wakeup_ports[2].bits.uop.dis_col_sel, int_wakeups[2].bits.uop.dis_col_sel connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, int_wakeups[2].bits.uop.iw_p3_bypass_hint connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, int_wakeups[2].bits.uop.iw_p2_bypass_hint connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, int_wakeups[2].bits.uop.iw_p1_bypass_hint connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, int_wakeups[2].bits.uop.iw_p2_speculative_child connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, int_wakeups[2].bits.uop.iw_p1_speculative_child connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, int_wakeups[2].bits.uop.iw_issued_partial_dgen connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, int_wakeups[2].bits.uop.iw_issued_partial_agen connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iw_issued, int_wakeups[2].bits.uop.iw_issued connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[0], int_wakeups[2].bits.uop.fu_code[0] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[1], int_wakeups[2].bits.uop.fu_code[1] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[2], int_wakeups[2].bits.uop.fu_code[2] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[3], int_wakeups[2].bits.uop.fu_code[3] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[4], int_wakeups[2].bits.uop.fu_code[4] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[5], int_wakeups[2].bits.uop.fu_code[5] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[6], int_wakeups[2].bits.uop.fu_code[6] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[7], int_wakeups[2].bits.uop.fu_code[7] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[8], int_wakeups[2].bits.uop.fu_code[8] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[9], int_wakeups[2].bits.uop.fu_code[9] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[0], int_wakeups[2].bits.uop.iq_type[0] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[1], int_wakeups[2].bits.uop.iq_type[1] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[2], int_wakeups[2].bits.uop.iq_type[2] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[3], int_wakeups[2].bits.uop.iq_type[3] connect alu_iss_unit.io.wakeup_ports[2].bits.uop.debug_pc, int_wakeups[2].bits.uop.debug_pc connect alu_iss_unit.io.wakeup_ports[2].bits.uop.is_rvc, int_wakeups[2].bits.uop.is_rvc connect alu_iss_unit.io.wakeup_ports[2].bits.uop.debug_inst, int_wakeups[2].bits.uop.debug_inst connect alu_iss_unit.io.wakeup_ports[2].bits.uop.inst, int_wakeups[2].bits.uop.inst connect alu_iss_unit.io.wakeup_ports[2].valid, int_wakeups[2].valid connect alu_iss_unit.io.wakeup_ports[3].bits.rebusy, int_wakeups[3].bits.rebusy connect alu_iss_unit.io.wakeup_ports[3].bits.speculative_mask, int_wakeups[3].bits.speculative_mask connect alu_iss_unit.io.wakeup_ports[3].bits.bypassable, int_wakeups[3].bits.bypassable connect alu_iss_unit.io.wakeup_ports[3].bits.uop.debug_tsrc, int_wakeups[3].bits.uop.debug_tsrc connect alu_iss_unit.io.wakeup_ports[3].bits.uop.debug_fsrc, int_wakeups[3].bits.uop.debug_fsrc connect alu_iss_unit.io.wakeup_ports[3].bits.uop.bp_xcpt_if, int_wakeups[3].bits.uop.bp_xcpt_if connect alu_iss_unit.io.wakeup_ports[3].bits.uop.bp_debug_if, int_wakeups[3].bits.uop.bp_debug_if connect alu_iss_unit.io.wakeup_ports[3].bits.uop.xcpt_ma_if, int_wakeups[3].bits.uop.xcpt_ma_if connect alu_iss_unit.io.wakeup_ports[3].bits.uop.xcpt_ae_if, int_wakeups[3].bits.uop.xcpt_ae_if connect alu_iss_unit.io.wakeup_ports[3].bits.uop.xcpt_pf_if, int_wakeups[3].bits.uop.xcpt_pf_if connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_typ, int_wakeups[3].bits.uop.fp_typ connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_rm, int_wakeups[3].bits.uop.fp_rm connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_val, int_wakeups[3].bits.uop.fp_val connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fcn_op, int_wakeups[3].bits.uop.fcn_op connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fcn_dw, int_wakeups[3].bits.uop.fcn_dw connect alu_iss_unit.io.wakeup_ports[3].bits.uop.frs3_en, int_wakeups[3].bits.uop.frs3_en connect alu_iss_unit.io.wakeup_ports[3].bits.uop.lrs2_rtype, int_wakeups[3].bits.uop.lrs2_rtype connect alu_iss_unit.io.wakeup_ports[3].bits.uop.lrs1_rtype, int_wakeups[3].bits.uop.lrs1_rtype connect alu_iss_unit.io.wakeup_ports[3].bits.uop.dst_rtype, int_wakeups[3].bits.uop.dst_rtype connect alu_iss_unit.io.wakeup_ports[3].bits.uop.lrs3, int_wakeups[3].bits.uop.lrs3 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.lrs2, int_wakeups[3].bits.uop.lrs2 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.lrs1, int_wakeups[3].bits.uop.lrs1 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.ldst, int_wakeups[3].bits.uop.ldst connect alu_iss_unit.io.wakeup_ports[3].bits.uop.ldst_is_rs1, int_wakeups[3].bits.uop.ldst_is_rs1 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.csr_cmd, int_wakeups[3].bits.uop.csr_cmd connect alu_iss_unit.io.wakeup_ports[3].bits.uop.flush_on_commit, int_wakeups[3].bits.uop.flush_on_commit connect alu_iss_unit.io.wakeup_ports[3].bits.uop.is_unique, int_wakeups[3].bits.uop.is_unique connect alu_iss_unit.io.wakeup_ports[3].bits.uop.uses_stq, int_wakeups[3].bits.uop.uses_stq connect alu_iss_unit.io.wakeup_ports[3].bits.uop.uses_ldq, int_wakeups[3].bits.uop.uses_ldq connect alu_iss_unit.io.wakeup_ports[3].bits.uop.mem_signed, int_wakeups[3].bits.uop.mem_signed connect alu_iss_unit.io.wakeup_ports[3].bits.uop.mem_size, int_wakeups[3].bits.uop.mem_size connect alu_iss_unit.io.wakeup_ports[3].bits.uop.mem_cmd, int_wakeups[3].bits.uop.mem_cmd connect alu_iss_unit.io.wakeup_ports[3].bits.uop.exc_cause, int_wakeups[3].bits.uop.exc_cause connect alu_iss_unit.io.wakeup_ports[3].bits.uop.exception, int_wakeups[3].bits.uop.exception connect alu_iss_unit.io.wakeup_ports[3].bits.uop.stale_pdst, int_wakeups[3].bits.uop.stale_pdst connect alu_iss_unit.io.wakeup_ports[3].bits.uop.ppred_busy, int_wakeups[3].bits.uop.ppred_busy connect alu_iss_unit.io.wakeup_ports[3].bits.uop.prs3_busy, int_wakeups[3].bits.uop.prs3_busy connect alu_iss_unit.io.wakeup_ports[3].bits.uop.prs2_busy, int_wakeups[3].bits.uop.prs2_busy connect alu_iss_unit.io.wakeup_ports[3].bits.uop.prs1_busy, int_wakeups[3].bits.uop.prs1_busy connect alu_iss_unit.io.wakeup_ports[3].bits.uop.ppred, int_wakeups[3].bits.uop.ppred connect alu_iss_unit.io.wakeup_ports[3].bits.uop.prs3, int_wakeups[3].bits.uop.prs3 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.prs2, int_wakeups[3].bits.uop.prs2 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.prs1, int_wakeups[3].bits.uop.prs1 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.pdst, int_wakeups[3].bits.uop.pdst connect alu_iss_unit.io.wakeup_ports[3].bits.uop.rxq_idx, int_wakeups[3].bits.uop.rxq_idx connect alu_iss_unit.io.wakeup_ports[3].bits.uop.stq_idx, int_wakeups[3].bits.uop.stq_idx connect alu_iss_unit.io.wakeup_ports[3].bits.uop.ldq_idx, int_wakeups[3].bits.uop.ldq_idx connect alu_iss_unit.io.wakeup_ports[3].bits.uop.rob_idx, int_wakeups[3].bits.uop.rob_idx connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, int_wakeups[3].bits.uop.fp_ctrl.vec connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, int_wakeups[3].bits.uop.fp_ctrl.wflags connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, int_wakeups[3].bits.uop.fp_ctrl.sqrt connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.div, int_wakeups[3].bits.uop.fp_ctrl.div connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, int_wakeups[3].bits.uop.fp_ctrl.fma connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, int_wakeups[3].bits.uop.fp_ctrl.fastpipe connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, int_wakeups[3].bits.uop.fp_ctrl.toint connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, int_wakeups[3].bits.uop.fp_ctrl.fromint connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, int_wakeups[3].bits.uop.fp_ctrl.typeTagOut connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, int_wakeups[3].bits.uop.fp_ctrl.typeTagIn connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, int_wakeups[3].bits.uop.fp_ctrl.swap23 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, int_wakeups[3].bits.uop.fp_ctrl.swap12 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, int_wakeups[3].bits.uop.fp_ctrl.ren3 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, int_wakeups[3].bits.uop.fp_ctrl.ren2 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, int_wakeups[3].bits.uop.fp_ctrl.ren1 connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, int_wakeups[3].bits.uop.fp_ctrl.wen connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, int_wakeups[3].bits.uop.fp_ctrl.ldst connect alu_iss_unit.io.wakeup_ports[3].bits.uop.op2_sel, int_wakeups[3].bits.uop.op2_sel connect alu_iss_unit.io.wakeup_ports[3].bits.uop.op1_sel, int_wakeups[3].bits.uop.op1_sel connect alu_iss_unit.io.wakeup_ports[3].bits.uop.imm_packed, int_wakeups[3].bits.uop.imm_packed connect alu_iss_unit.io.wakeup_ports[3].bits.uop.pimm, int_wakeups[3].bits.uop.pimm connect alu_iss_unit.io.wakeup_ports[3].bits.uop.imm_sel, int_wakeups[3].bits.uop.imm_sel connect alu_iss_unit.io.wakeup_ports[3].bits.uop.imm_rename, int_wakeups[3].bits.uop.imm_rename connect alu_iss_unit.io.wakeup_ports[3].bits.uop.taken, int_wakeups[3].bits.uop.taken connect alu_iss_unit.io.wakeup_ports[3].bits.uop.pc_lob, int_wakeups[3].bits.uop.pc_lob connect alu_iss_unit.io.wakeup_ports[3].bits.uop.edge_inst, int_wakeups[3].bits.uop.edge_inst connect alu_iss_unit.io.wakeup_ports[3].bits.uop.ftq_idx, int_wakeups[3].bits.uop.ftq_idx connect alu_iss_unit.io.wakeup_ports[3].bits.uop.is_mov, int_wakeups[3].bits.uop.is_mov connect alu_iss_unit.io.wakeup_ports[3].bits.uop.is_rocc, int_wakeups[3].bits.uop.is_rocc connect alu_iss_unit.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, int_wakeups[3].bits.uop.is_sys_pc2epc connect alu_iss_unit.io.wakeup_ports[3].bits.uop.is_eret, int_wakeups[3].bits.uop.is_eret connect alu_iss_unit.io.wakeup_ports[3].bits.uop.is_amo, int_wakeups[3].bits.uop.is_amo connect alu_iss_unit.io.wakeup_ports[3].bits.uop.is_sfence, int_wakeups[3].bits.uop.is_sfence connect alu_iss_unit.io.wakeup_ports[3].bits.uop.is_fencei, int_wakeups[3].bits.uop.is_fencei connect alu_iss_unit.io.wakeup_ports[3].bits.uop.is_fence, int_wakeups[3].bits.uop.is_fence connect alu_iss_unit.io.wakeup_ports[3].bits.uop.is_sfb, int_wakeups[3].bits.uop.is_sfb connect alu_iss_unit.io.wakeup_ports[3].bits.uop.br_type, int_wakeups[3].bits.uop.br_type connect alu_iss_unit.io.wakeup_ports[3].bits.uop.br_tag, int_wakeups[3].bits.uop.br_tag connect alu_iss_unit.io.wakeup_ports[3].bits.uop.br_mask, int_wakeups[3].bits.uop.br_mask connect alu_iss_unit.io.wakeup_ports[3].bits.uop.dis_col_sel, int_wakeups[3].bits.uop.dis_col_sel connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, int_wakeups[3].bits.uop.iw_p3_bypass_hint connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, int_wakeups[3].bits.uop.iw_p2_bypass_hint connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, int_wakeups[3].bits.uop.iw_p1_bypass_hint connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, int_wakeups[3].bits.uop.iw_p2_speculative_child connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, int_wakeups[3].bits.uop.iw_p1_speculative_child connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, int_wakeups[3].bits.uop.iw_issued_partial_dgen connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, int_wakeups[3].bits.uop.iw_issued_partial_agen connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iw_issued, int_wakeups[3].bits.uop.iw_issued connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[0], int_wakeups[3].bits.uop.fu_code[0] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[1], int_wakeups[3].bits.uop.fu_code[1] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[2], int_wakeups[3].bits.uop.fu_code[2] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[3], int_wakeups[3].bits.uop.fu_code[3] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[4], int_wakeups[3].bits.uop.fu_code[4] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[5], int_wakeups[3].bits.uop.fu_code[5] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[6], int_wakeups[3].bits.uop.fu_code[6] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[7], int_wakeups[3].bits.uop.fu_code[7] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[8], int_wakeups[3].bits.uop.fu_code[8] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[9], int_wakeups[3].bits.uop.fu_code[9] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[0], int_wakeups[3].bits.uop.iq_type[0] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[1], int_wakeups[3].bits.uop.iq_type[1] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[2], int_wakeups[3].bits.uop.iq_type[2] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[3], int_wakeups[3].bits.uop.iq_type[3] connect alu_iss_unit.io.wakeup_ports[3].bits.uop.debug_pc, int_wakeups[3].bits.uop.debug_pc connect alu_iss_unit.io.wakeup_ports[3].bits.uop.is_rvc, int_wakeups[3].bits.uop.is_rvc connect alu_iss_unit.io.wakeup_ports[3].bits.uop.debug_inst, int_wakeups[3].bits.uop.debug_inst connect alu_iss_unit.io.wakeup_ports[3].bits.uop.inst, int_wakeups[3].bits.uop.inst connect alu_iss_unit.io.wakeup_ports[3].valid, int_wakeups[3].valid connect unq_iss_unit.io.tsc_reg, debug_tsc_reg connect unq_iss_unit.io.brupdate.b2.target_offset, brupdate.b2.target_offset connect unq_iss_unit.io.brupdate.b2.jalr_target, brupdate.b2.jalr_target connect unq_iss_unit.io.brupdate.b2.pc_sel, brupdate.b2.pc_sel connect unq_iss_unit.io.brupdate.b2.cfi_type, brupdate.b2.cfi_type connect unq_iss_unit.io.brupdate.b2.taken, brupdate.b2.taken connect unq_iss_unit.io.brupdate.b2.mispredict, brupdate.b2.mispredict connect unq_iss_unit.io.brupdate.b2.uop.debug_tsrc, brupdate.b2.uop.debug_tsrc connect unq_iss_unit.io.brupdate.b2.uop.debug_fsrc, brupdate.b2.uop.debug_fsrc connect unq_iss_unit.io.brupdate.b2.uop.bp_xcpt_if, brupdate.b2.uop.bp_xcpt_if connect unq_iss_unit.io.brupdate.b2.uop.bp_debug_if, brupdate.b2.uop.bp_debug_if connect unq_iss_unit.io.brupdate.b2.uop.xcpt_ma_if, brupdate.b2.uop.xcpt_ma_if connect unq_iss_unit.io.brupdate.b2.uop.xcpt_ae_if, brupdate.b2.uop.xcpt_ae_if connect unq_iss_unit.io.brupdate.b2.uop.xcpt_pf_if, brupdate.b2.uop.xcpt_pf_if connect unq_iss_unit.io.brupdate.b2.uop.fp_typ, brupdate.b2.uop.fp_typ connect unq_iss_unit.io.brupdate.b2.uop.fp_rm, brupdate.b2.uop.fp_rm connect unq_iss_unit.io.brupdate.b2.uop.fp_val, brupdate.b2.uop.fp_val connect unq_iss_unit.io.brupdate.b2.uop.fcn_op, brupdate.b2.uop.fcn_op connect unq_iss_unit.io.brupdate.b2.uop.fcn_dw, brupdate.b2.uop.fcn_dw connect unq_iss_unit.io.brupdate.b2.uop.frs3_en, brupdate.b2.uop.frs3_en connect unq_iss_unit.io.brupdate.b2.uop.lrs2_rtype, brupdate.b2.uop.lrs2_rtype connect unq_iss_unit.io.brupdate.b2.uop.lrs1_rtype, brupdate.b2.uop.lrs1_rtype connect unq_iss_unit.io.brupdate.b2.uop.dst_rtype, brupdate.b2.uop.dst_rtype connect unq_iss_unit.io.brupdate.b2.uop.lrs3, brupdate.b2.uop.lrs3 connect unq_iss_unit.io.brupdate.b2.uop.lrs2, brupdate.b2.uop.lrs2 connect unq_iss_unit.io.brupdate.b2.uop.lrs1, brupdate.b2.uop.lrs1 connect unq_iss_unit.io.brupdate.b2.uop.ldst, brupdate.b2.uop.ldst connect unq_iss_unit.io.brupdate.b2.uop.ldst_is_rs1, brupdate.b2.uop.ldst_is_rs1 connect unq_iss_unit.io.brupdate.b2.uop.csr_cmd, brupdate.b2.uop.csr_cmd connect unq_iss_unit.io.brupdate.b2.uop.flush_on_commit, brupdate.b2.uop.flush_on_commit connect unq_iss_unit.io.brupdate.b2.uop.is_unique, brupdate.b2.uop.is_unique connect unq_iss_unit.io.brupdate.b2.uop.uses_stq, brupdate.b2.uop.uses_stq connect unq_iss_unit.io.brupdate.b2.uop.uses_ldq, brupdate.b2.uop.uses_ldq connect unq_iss_unit.io.brupdate.b2.uop.mem_signed, brupdate.b2.uop.mem_signed connect unq_iss_unit.io.brupdate.b2.uop.mem_size, brupdate.b2.uop.mem_size connect unq_iss_unit.io.brupdate.b2.uop.mem_cmd, brupdate.b2.uop.mem_cmd connect unq_iss_unit.io.brupdate.b2.uop.exc_cause, brupdate.b2.uop.exc_cause connect unq_iss_unit.io.brupdate.b2.uop.exception, brupdate.b2.uop.exception connect unq_iss_unit.io.brupdate.b2.uop.stale_pdst, brupdate.b2.uop.stale_pdst connect unq_iss_unit.io.brupdate.b2.uop.ppred_busy, brupdate.b2.uop.ppred_busy connect unq_iss_unit.io.brupdate.b2.uop.prs3_busy, brupdate.b2.uop.prs3_busy connect unq_iss_unit.io.brupdate.b2.uop.prs2_busy, brupdate.b2.uop.prs2_busy connect unq_iss_unit.io.brupdate.b2.uop.prs1_busy, brupdate.b2.uop.prs1_busy connect unq_iss_unit.io.brupdate.b2.uop.ppred, brupdate.b2.uop.ppred connect unq_iss_unit.io.brupdate.b2.uop.prs3, brupdate.b2.uop.prs3 connect unq_iss_unit.io.brupdate.b2.uop.prs2, brupdate.b2.uop.prs2 connect unq_iss_unit.io.brupdate.b2.uop.prs1, brupdate.b2.uop.prs1 connect unq_iss_unit.io.brupdate.b2.uop.pdst, brupdate.b2.uop.pdst connect unq_iss_unit.io.brupdate.b2.uop.rxq_idx, brupdate.b2.uop.rxq_idx connect unq_iss_unit.io.brupdate.b2.uop.stq_idx, brupdate.b2.uop.stq_idx connect unq_iss_unit.io.brupdate.b2.uop.ldq_idx, brupdate.b2.uop.ldq_idx connect unq_iss_unit.io.brupdate.b2.uop.rob_idx, brupdate.b2.uop.rob_idx connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.vec, brupdate.b2.uop.fp_ctrl.vec connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.wflags, brupdate.b2.uop.fp_ctrl.wflags connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.sqrt, brupdate.b2.uop.fp_ctrl.sqrt connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.div, brupdate.b2.uop.fp_ctrl.div connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.fma, brupdate.b2.uop.fp_ctrl.fma connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.fastpipe, brupdate.b2.uop.fp_ctrl.fastpipe connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.toint, brupdate.b2.uop.fp_ctrl.toint connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.fromint, brupdate.b2.uop.fp_ctrl.fromint connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.typeTagOut, brupdate.b2.uop.fp_ctrl.typeTagOut connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.typeTagIn, brupdate.b2.uop.fp_ctrl.typeTagIn connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.swap23, brupdate.b2.uop.fp_ctrl.swap23 connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.swap12, brupdate.b2.uop.fp_ctrl.swap12 connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.ren3, brupdate.b2.uop.fp_ctrl.ren3 connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.ren2, brupdate.b2.uop.fp_ctrl.ren2 connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.ren1, brupdate.b2.uop.fp_ctrl.ren1 connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.wen, brupdate.b2.uop.fp_ctrl.wen connect unq_iss_unit.io.brupdate.b2.uop.fp_ctrl.ldst, brupdate.b2.uop.fp_ctrl.ldst connect unq_iss_unit.io.brupdate.b2.uop.op2_sel, brupdate.b2.uop.op2_sel connect unq_iss_unit.io.brupdate.b2.uop.op1_sel, brupdate.b2.uop.op1_sel connect unq_iss_unit.io.brupdate.b2.uop.imm_packed, brupdate.b2.uop.imm_packed connect unq_iss_unit.io.brupdate.b2.uop.pimm, brupdate.b2.uop.pimm connect unq_iss_unit.io.brupdate.b2.uop.imm_sel, brupdate.b2.uop.imm_sel connect unq_iss_unit.io.brupdate.b2.uop.imm_rename, brupdate.b2.uop.imm_rename connect unq_iss_unit.io.brupdate.b2.uop.taken, brupdate.b2.uop.taken connect unq_iss_unit.io.brupdate.b2.uop.pc_lob, brupdate.b2.uop.pc_lob connect unq_iss_unit.io.brupdate.b2.uop.edge_inst, brupdate.b2.uop.edge_inst connect unq_iss_unit.io.brupdate.b2.uop.ftq_idx, brupdate.b2.uop.ftq_idx connect unq_iss_unit.io.brupdate.b2.uop.is_mov, brupdate.b2.uop.is_mov connect unq_iss_unit.io.brupdate.b2.uop.is_rocc, brupdate.b2.uop.is_rocc connect unq_iss_unit.io.brupdate.b2.uop.is_sys_pc2epc, brupdate.b2.uop.is_sys_pc2epc connect unq_iss_unit.io.brupdate.b2.uop.is_eret, brupdate.b2.uop.is_eret connect unq_iss_unit.io.brupdate.b2.uop.is_amo, brupdate.b2.uop.is_amo connect unq_iss_unit.io.brupdate.b2.uop.is_sfence, brupdate.b2.uop.is_sfence connect unq_iss_unit.io.brupdate.b2.uop.is_fencei, brupdate.b2.uop.is_fencei connect unq_iss_unit.io.brupdate.b2.uop.is_fence, brupdate.b2.uop.is_fence connect unq_iss_unit.io.brupdate.b2.uop.is_sfb, brupdate.b2.uop.is_sfb connect unq_iss_unit.io.brupdate.b2.uop.br_type, brupdate.b2.uop.br_type connect unq_iss_unit.io.brupdate.b2.uop.br_tag, brupdate.b2.uop.br_tag connect unq_iss_unit.io.brupdate.b2.uop.br_mask, brupdate.b2.uop.br_mask connect unq_iss_unit.io.brupdate.b2.uop.dis_col_sel, brupdate.b2.uop.dis_col_sel connect unq_iss_unit.io.brupdate.b2.uop.iw_p3_bypass_hint, brupdate.b2.uop.iw_p3_bypass_hint connect unq_iss_unit.io.brupdate.b2.uop.iw_p2_bypass_hint, brupdate.b2.uop.iw_p2_bypass_hint connect unq_iss_unit.io.brupdate.b2.uop.iw_p1_bypass_hint, brupdate.b2.uop.iw_p1_bypass_hint connect unq_iss_unit.io.brupdate.b2.uop.iw_p2_speculative_child, brupdate.b2.uop.iw_p2_speculative_child connect unq_iss_unit.io.brupdate.b2.uop.iw_p1_speculative_child, brupdate.b2.uop.iw_p1_speculative_child connect unq_iss_unit.io.brupdate.b2.uop.iw_issued_partial_dgen, brupdate.b2.uop.iw_issued_partial_dgen connect unq_iss_unit.io.brupdate.b2.uop.iw_issued_partial_agen, brupdate.b2.uop.iw_issued_partial_agen connect unq_iss_unit.io.brupdate.b2.uop.iw_issued, brupdate.b2.uop.iw_issued connect unq_iss_unit.io.brupdate.b2.uop.fu_code[0], brupdate.b2.uop.fu_code[0] connect unq_iss_unit.io.brupdate.b2.uop.fu_code[1], brupdate.b2.uop.fu_code[1] connect unq_iss_unit.io.brupdate.b2.uop.fu_code[2], brupdate.b2.uop.fu_code[2] connect unq_iss_unit.io.brupdate.b2.uop.fu_code[3], brupdate.b2.uop.fu_code[3] connect unq_iss_unit.io.brupdate.b2.uop.fu_code[4], brupdate.b2.uop.fu_code[4] connect unq_iss_unit.io.brupdate.b2.uop.fu_code[5], brupdate.b2.uop.fu_code[5] connect unq_iss_unit.io.brupdate.b2.uop.fu_code[6], brupdate.b2.uop.fu_code[6] connect unq_iss_unit.io.brupdate.b2.uop.fu_code[7], brupdate.b2.uop.fu_code[7] connect unq_iss_unit.io.brupdate.b2.uop.fu_code[8], brupdate.b2.uop.fu_code[8] connect unq_iss_unit.io.brupdate.b2.uop.fu_code[9], brupdate.b2.uop.fu_code[9] connect unq_iss_unit.io.brupdate.b2.uop.iq_type[0], brupdate.b2.uop.iq_type[0] connect unq_iss_unit.io.brupdate.b2.uop.iq_type[1], brupdate.b2.uop.iq_type[1] connect unq_iss_unit.io.brupdate.b2.uop.iq_type[2], brupdate.b2.uop.iq_type[2] connect unq_iss_unit.io.brupdate.b2.uop.iq_type[3], brupdate.b2.uop.iq_type[3] connect unq_iss_unit.io.brupdate.b2.uop.debug_pc, brupdate.b2.uop.debug_pc connect unq_iss_unit.io.brupdate.b2.uop.is_rvc, brupdate.b2.uop.is_rvc connect unq_iss_unit.io.brupdate.b2.uop.debug_inst, brupdate.b2.uop.debug_inst connect unq_iss_unit.io.brupdate.b2.uop.inst, brupdate.b2.uop.inst connect unq_iss_unit.io.brupdate.b1.mispredict_mask, brupdate.b1.mispredict_mask connect unq_iss_unit.io.brupdate.b1.resolve_mask, brupdate.b1.resolve_mask reg unq_iss_unit_io_flush_pipeline_REG : UInt<1>, clock connect unq_iss_unit_io_flush_pipeline_REG, rob.io.flush.valid connect unq_iss_unit.io.flush_pipeline, unq_iss_unit_io_flush_pipeline_REG node _unq_iss_unit_io_child_rebusys_T = or(alu_exe_unit_0.io_child_rebusy, alu_exe_unit_1.io_child_rebusy) connect unq_iss_unit.io.child_rebusys, _unq_iss_unit_io_child_rebusys_T connect unq_iss_unit.io.wakeup_ports[0].bits.rebusy, int_wakeups[0].bits.rebusy connect unq_iss_unit.io.wakeup_ports[0].bits.speculative_mask, int_wakeups[0].bits.speculative_mask connect unq_iss_unit.io.wakeup_ports[0].bits.bypassable, int_wakeups[0].bits.bypassable connect unq_iss_unit.io.wakeup_ports[0].bits.uop.debug_tsrc, int_wakeups[0].bits.uop.debug_tsrc connect unq_iss_unit.io.wakeup_ports[0].bits.uop.debug_fsrc, int_wakeups[0].bits.uop.debug_fsrc connect unq_iss_unit.io.wakeup_ports[0].bits.uop.bp_xcpt_if, int_wakeups[0].bits.uop.bp_xcpt_if connect unq_iss_unit.io.wakeup_ports[0].bits.uop.bp_debug_if, int_wakeups[0].bits.uop.bp_debug_if connect unq_iss_unit.io.wakeup_ports[0].bits.uop.xcpt_ma_if, int_wakeups[0].bits.uop.xcpt_ma_if connect unq_iss_unit.io.wakeup_ports[0].bits.uop.xcpt_ae_if, int_wakeups[0].bits.uop.xcpt_ae_if connect unq_iss_unit.io.wakeup_ports[0].bits.uop.xcpt_pf_if, int_wakeups[0].bits.uop.xcpt_pf_if connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_typ, int_wakeups[0].bits.uop.fp_typ connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_rm, int_wakeups[0].bits.uop.fp_rm connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_val, int_wakeups[0].bits.uop.fp_val connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fcn_op, int_wakeups[0].bits.uop.fcn_op connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fcn_dw, int_wakeups[0].bits.uop.fcn_dw connect unq_iss_unit.io.wakeup_ports[0].bits.uop.frs3_en, int_wakeups[0].bits.uop.frs3_en connect unq_iss_unit.io.wakeup_ports[0].bits.uop.lrs2_rtype, int_wakeups[0].bits.uop.lrs2_rtype connect unq_iss_unit.io.wakeup_ports[0].bits.uop.lrs1_rtype, int_wakeups[0].bits.uop.lrs1_rtype connect unq_iss_unit.io.wakeup_ports[0].bits.uop.dst_rtype, int_wakeups[0].bits.uop.dst_rtype connect unq_iss_unit.io.wakeup_ports[0].bits.uop.lrs3, int_wakeups[0].bits.uop.lrs3 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.lrs2, int_wakeups[0].bits.uop.lrs2 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.lrs1, int_wakeups[0].bits.uop.lrs1 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.ldst, int_wakeups[0].bits.uop.ldst connect unq_iss_unit.io.wakeup_ports[0].bits.uop.ldst_is_rs1, int_wakeups[0].bits.uop.ldst_is_rs1 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.csr_cmd, int_wakeups[0].bits.uop.csr_cmd connect unq_iss_unit.io.wakeup_ports[0].bits.uop.flush_on_commit, int_wakeups[0].bits.uop.flush_on_commit connect unq_iss_unit.io.wakeup_ports[0].bits.uop.is_unique, int_wakeups[0].bits.uop.is_unique connect unq_iss_unit.io.wakeup_ports[0].bits.uop.uses_stq, int_wakeups[0].bits.uop.uses_stq connect unq_iss_unit.io.wakeup_ports[0].bits.uop.uses_ldq, int_wakeups[0].bits.uop.uses_ldq connect unq_iss_unit.io.wakeup_ports[0].bits.uop.mem_signed, int_wakeups[0].bits.uop.mem_signed connect unq_iss_unit.io.wakeup_ports[0].bits.uop.mem_size, int_wakeups[0].bits.uop.mem_size connect unq_iss_unit.io.wakeup_ports[0].bits.uop.mem_cmd, int_wakeups[0].bits.uop.mem_cmd connect unq_iss_unit.io.wakeup_ports[0].bits.uop.exc_cause, int_wakeups[0].bits.uop.exc_cause connect unq_iss_unit.io.wakeup_ports[0].bits.uop.exception, int_wakeups[0].bits.uop.exception connect unq_iss_unit.io.wakeup_ports[0].bits.uop.stale_pdst, int_wakeups[0].bits.uop.stale_pdst connect unq_iss_unit.io.wakeup_ports[0].bits.uop.ppred_busy, int_wakeups[0].bits.uop.ppred_busy connect unq_iss_unit.io.wakeup_ports[0].bits.uop.prs3_busy, int_wakeups[0].bits.uop.prs3_busy connect unq_iss_unit.io.wakeup_ports[0].bits.uop.prs2_busy, int_wakeups[0].bits.uop.prs2_busy connect unq_iss_unit.io.wakeup_ports[0].bits.uop.prs1_busy, int_wakeups[0].bits.uop.prs1_busy connect unq_iss_unit.io.wakeup_ports[0].bits.uop.ppred, int_wakeups[0].bits.uop.ppred connect unq_iss_unit.io.wakeup_ports[0].bits.uop.prs3, int_wakeups[0].bits.uop.prs3 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.prs2, int_wakeups[0].bits.uop.prs2 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.prs1, int_wakeups[0].bits.uop.prs1 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.pdst, int_wakeups[0].bits.uop.pdst connect unq_iss_unit.io.wakeup_ports[0].bits.uop.rxq_idx, int_wakeups[0].bits.uop.rxq_idx connect unq_iss_unit.io.wakeup_ports[0].bits.uop.stq_idx, int_wakeups[0].bits.uop.stq_idx connect unq_iss_unit.io.wakeup_ports[0].bits.uop.ldq_idx, int_wakeups[0].bits.uop.ldq_idx connect unq_iss_unit.io.wakeup_ports[0].bits.uop.rob_idx, int_wakeups[0].bits.uop.rob_idx connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.vec, int_wakeups[0].bits.uop.fp_ctrl.vec connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.wflags, int_wakeups[0].bits.uop.fp_ctrl.wflags connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.sqrt, int_wakeups[0].bits.uop.fp_ctrl.sqrt connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.div, int_wakeups[0].bits.uop.fp_ctrl.div connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fma, int_wakeups[0].bits.uop.fp_ctrl.fma connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fastpipe, int_wakeups[0].bits.uop.fp_ctrl.fastpipe connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.toint, int_wakeups[0].bits.uop.fp_ctrl.toint connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.fromint, int_wakeups[0].bits.uop.fp_ctrl.fromint connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagOut, int_wakeups[0].bits.uop.fp_ctrl.typeTagOut connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.typeTagIn, int_wakeups[0].bits.uop.fp_ctrl.typeTagIn connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.swap23, int_wakeups[0].bits.uop.fp_ctrl.swap23 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.swap12, int_wakeups[0].bits.uop.fp_ctrl.swap12 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren3, int_wakeups[0].bits.uop.fp_ctrl.ren3 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren2, int_wakeups[0].bits.uop.fp_ctrl.ren2 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ren1, int_wakeups[0].bits.uop.fp_ctrl.ren1 connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.wen, int_wakeups[0].bits.uop.fp_ctrl.wen connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fp_ctrl.ldst, int_wakeups[0].bits.uop.fp_ctrl.ldst connect unq_iss_unit.io.wakeup_ports[0].bits.uop.op2_sel, int_wakeups[0].bits.uop.op2_sel connect unq_iss_unit.io.wakeup_ports[0].bits.uop.op1_sel, int_wakeups[0].bits.uop.op1_sel connect unq_iss_unit.io.wakeup_ports[0].bits.uop.imm_packed, int_wakeups[0].bits.uop.imm_packed connect unq_iss_unit.io.wakeup_ports[0].bits.uop.pimm, int_wakeups[0].bits.uop.pimm connect unq_iss_unit.io.wakeup_ports[0].bits.uop.imm_sel, int_wakeups[0].bits.uop.imm_sel connect unq_iss_unit.io.wakeup_ports[0].bits.uop.imm_rename, int_wakeups[0].bits.uop.imm_rename connect unq_iss_unit.io.wakeup_ports[0].bits.uop.taken, int_wakeups[0].bits.uop.taken connect unq_iss_unit.io.wakeup_ports[0].bits.uop.pc_lob, int_wakeups[0].bits.uop.pc_lob connect unq_iss_unit.io.wakeup_ports[0].bits.uop.edge_inst, int_wakeups[0].bits.uop.edge_inst connect unq_iss_unit.io.wakeup_ports[0].bits.uop.ftq_idx, int_wakeups[0].bits.uop.ftq_idx connect unq_iss_unit.io.wakeup_ports[0].bits.uop.is_mov, int_wakeups[0].bits.uop.is_mov connect unq_iss_unit.io.wakeup_ports[0].bits.uop.is_rocc, int_wakeups[0].bits.uop.is_rocc connect unq_iss_unit.io.wakeup_ports[0].bits.uop.is_sys_pc2epc, int_wakeups[0].bits.uop.is_sys_pc2epc connect unq_iss_unit.io.wakeup_ports[0].bits.uop.is_eret, int_wakeups[0].bits.uop.is_eret connect unq_iss_unit.io.wakeup_ports[0].bits.uop.is_amo, int_wakeups[0].bits.uop.is_amo connect unq_iss_unit.io.wakeup_ports[0].bits.uop.is_sfence, int_wakeups[0].bits.uop.is_sfence connect unq_iss_unit.io.wakeup_ports[0].bits.uop.is_fencei, int_wakeups[0].bits.uop.is_fencei connect unq_iss_unit.io.wakeup_ports[0].bits.uop.is_fence, int_wakeups[0].bits.uop.is_fence connect unq_iss_unit.io.wakeup_ports[0].bits.uop.is_sfb, int_wakeups[0].bits.uop.is_sfb connect unq_iss_unit.io.wakeup_ports[0].bits.uop.br_type, int_wakeups[0].bits.uop.br_type connect unq_iss_unit.io.wakeup_ports[0].bits.uop.br_tag, int_wakeups[0].bits.uop.br_tag connect unq_iss_unit.io.wakeup_ports[0].bits.uop.br_mask, int_wakeups[0].bits.uop.br_mask connect unq_iss_unit.io.wakeup_ports[0].bits.uop.dis_col_sel, int_wakeups[0].bits.uop.dis_col_sel connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iw_p3_bypass_hint, int_wakeups[0].bits.uop.iw_p3_bypass_hint connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iw_p2_bypass_hint, int_wakeups[0].bits.uop.iw_p2_bypass_hint connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iw_p1_bypass_hint, int_wakeups[0].bits.uop.iw_p1_bypass_hint connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iw_p2_speculative_child, int_wakeups[0].bits.uop.iw_p2_speculative_child connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iw_p1_speculative_child, int_wakeups[0].bits.uop.iw_p1_speculative_child connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iw_issued_partial_dgen, int_wakeups[0].bits.uop.iw_issued_partial_dgen connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iw_issued_partial_agen, int_wakeups[0].bits.uop.iw_issued_partial_agen connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iw_issued, int_wakeups[0].bits.uop.iw_issued connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[0], int_wakeups[0].bits.uop.fu_code[0] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[1], int_wakeups[0].bits.uop.fu_code[1] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[2], int_wakeups[0].bits.uop.fu_code[2] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[3], int_wakeups[0].bits.uop.fu_code[3] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[4], int_wakeups[0].bits.uop.fu_code[4] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[5], int_wakeups[0].bits.uop.fu_code[5] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[6], int_wakeups[0].bits.uop.fu_code[6] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[7], int_wakeups[0].bits.uop.fu_code[7] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[8], int_wakeups[0].bits.uop.fu_code[8] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.fu_code[9], int_wakeups[0].bits.uop.fu_code[9] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[0], int_wakeups[0].bits.uop.iq_type[0] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[1], int_wakeups[0].bits.uop.iq_type[1] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[2], int_wakeups[0].bits.uop.iq_type[2] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.iq_type[3], int_wakeups[0].bits.uop.iq_type[3] connect unq_iss_unit.io.wakeup_ports[0].bits.uop.debug_pc, int_wakeups[0].bits.uop.debug_pc connect unq_iss_unit.io.wakeup_ports[0].bits.uop.is_rvc, int_wakeups[0].bits.uop.is_rvc connect unq_iss_unit.io.wakeup_ports[0].bits.uop.debug_inst, int_wakeups[0].bits.uop.debug_inst connect unq_iss_unit.io.wakeup_ports[0].bits.uop.inst, int_wakeups[0].bits.uop.inst connect unq_iss_unit.io.wakeup_ports[0].valid, int_wakeups[0].valid connect unq_iss_unit.io.wakeup_ports[1].bits.rebusy, int_wakeups[1].bits.rebusy connect unq_iss_unit.io.wakeup_ports[1].bits.speculative_mask, int_wakeups[1].bits.speculative_mask connect unq_iss_unit.io.wakeup_ports[1].bits.bypassable, int_wakeups[1].bits.bypassable connect unq_iss_unit.io.wakeup_ports[1].bits.uop.debug_tsrc, int_wakeups[1].bits.uop.debug_tsrc connect unq_iss_unit.io.wakeup_ports[1].bits.uop.debug_fsrc, int_wakeups[1].bits.uop.debug_fsrc connect unq_iss_unit.io.wakeup_ports[1].bits.uop.bp_xcpt_if, int_wakeups[1].bits.uop.bp_xcpt_if connect unq_iss_unit.io.wakeup_ports[1].bits.uop.bp_debug_if, int_wakeups[1].bits.uop.bp_debug_if connect unq_iss_unit.io.wakeup_ports[1].bits.uop.xcpt_ma_if, int_wakeups[1].bits.uop.xcpt_ma_if connect unq_iss_unit.io.wakeup_ports[1].bits.uop.xcpt_ae_if, int_wakeups[1].bits.uop.xcpt_ae_if connect unq_iss_unit.io.wakeup_ports[1].bits.uop.xcpt_pf_if, int_wakeups[1].bits.uop.xcpt_pf_if connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_typ, int_wakeups[1].bits.uop.fp_typ connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_rm, int_wakeups[1].bits.uop.fp_rm connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_val, int_wakeups[1].bits.uop.fp_val connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fcn_op, int_wakeups[1].bits.uop.fcn_op connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fcn_dw, int_wakeups[1].bits.uop.fcn_dw connect unq_iss_unit.io.wakeup_ports[1].bits.uop.frs3_en, int_wakeups[1].bits.uop.frs3_en connect unq_iss_unit.io.wakeup_ports[1].bits.uop.lrs2_rtype, int_wakeups[1].bits.uop.lrs2_rtype connect unq_iss_unit.io.wakeup_ports[1].bits.uop.lrs1_rtype, int_wakeups[1].bits.uop.lrs1_rtype connect unq_iss_unit.io.wakeup_ports[1].bits.uop.dst_rtype, int_wakeups[1].bits.uop.dst_rtype connect unq_iss_unit.io.wakeup_ports[1].bits.uop.lrs3, int_wakeups[1].bits.uop.lrs3 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.lrs2, int_wakeups[1].bits.uop.lrs2 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.lrs1, int_wakeups[1].bits.uop.lrs1 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.ldst, int_wakeups[1].bits.uop.ldst connect unq_iss_unit.io.wakeup_ports[1].bits.uop.ldst_is_rs1, int_wakeups[1].bits.uop.ldst_is_rs1 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.csr_cmd, int_wakeups[1].bits.uop.csr_cmd connect unq_iss_unit.io.wakeup_ports[1].bits.uop.flush_on_commit, int_wakeups[1].bits.uop.flush_on_commit connect unq_iss_unit.io.wakeup_ports[1].bits.uop.is_unique, int_wakeups[1].bits.uop.is_unique connect unq_iss_unit.io.wakeup_ports[1].bits.uop.uses_stq, int_wakeups[1].bits.uop.uses_stq connect unq_iss_unit.io.wakeup_ports[1].bits.uop.uses_ldq, int_wakeups[1].bits.uop.uses_ldq connect unq_iss_unit.io.wakeup_ports[1].bits.uop.mem_signed, int_wakeups[1].bits.uop.mem_signed connect unq_iss_unit.io.wakeup_ports[1].bits.uop.mem_size, int_wakeups[1].bits.uop.mem_size connect unq_iss_unit.io.wakeup_ports[1].bits.uop.mem_cmd, int_wakeups[1].bits.uop.mem_cmd connect unq_iss_unit.io.wakeup_ports[1].bits.uop.exc_cause, int_wakeups[1].bits.uop.exc_cause connect unq_iss_unit.io.wakeup_ports[1].bits.uop.exception, int_wakeups[1].bits.uop.exception connect unq_iss_unit.io.wakeup_ports[1].bits.uop.stale_pdst, int_wakeups[1].bits.uop.stale_pdst connect unq_iss_unit.io.wakeup_ports[1].bits.uop.ppred_busy, int_wakeups[1].bits.uop.ppred_busy connect unq_iss_unit.io.wakeup_ports[1].bits.uop.prs3_busy, int_wakeups[1].bits.uop.prs3_busy connect unq_iss_unit.io.wakeup_ports[1].bits.uop.prs2_busy, int_wakeups[1].bits.uop.prs2_busy connect unq_iss_unit.io.wakeup_ports[1].bits.uop.prs1_busy, int_wakeups[1].bits.uop.prs1_busy connect unq_iss_unit.io.wakeup_ports[1].bits.uop.ppred, int_wakeups[1].bits.uop.ppred connect unq_iss_unit.io.wakeup_ports[1].bits.uop.prs3, int_wakeups[1].bits.uop.prs3 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.prs2, int_wakeups[1].bits.uop.prs2 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.prs1, int_wakeups[1].bits.uop.prs1 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.pdst, int_wakeups[1].bits.uop.pdst connect unq_iss_unit.io.wakeup_ports[1].bits.uop.rxq_idx, int_wakeups[1].bits.uop.rxq_idx connect unq_iss_unit.io.wakeup_ports[1].bits.uop.stq_idx, int_wakeups[1].bits.uop.stq_idx connect unq_iss_unit.io.wakeup_ports[1].bits.uop.ldq_idx, int_wakeups[1].bits.uop.ldq_idx connect unq_iss_unit.io.wakeup_ports[1].bits.uop.rob_idx, int_wakeups[1].bits.uop.rob_idx connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.vec, int_wakeups[1].bits.uop.fp_ctrl.vec connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.wflags, int_wakeups[1].bits.uop.fp_ctrl.wflags connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.sqrt, int_wakeups[1].bits.uop.fp_ctrl.sqrt connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.div, int_wakeups[1].bits.uop.fp_ctrl.div connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fma, int_wakeups[1].bits.uop.fp_ctrl.fma connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fastpipe, int_wakeups[1].bits.uop.fp_ctrl.fastpipe connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.toint, int_wakeups[1].bits.uop.fp_ctrl.toint connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.fromint, int_wakeups[1].bits.uop.fp_ctrl.fromint connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagOut, int_wakeups[1].bits.uop.fp_ctrl.typeTagOut connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.typeTagIn, int_wakeups[1].bits.uop.fp_ctrl.typeTagIn connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.swap23, int_wakeups[1].bits.uop.fp_ctrl.swap23 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.swap12, int_wakeups[1].bits.uop.fp_ctrl.swap12 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren3, int_wakeups[1].bits.uop.fp_ctrl.ren3 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren2, int_wakeups[1].bits.uop.fp_ctrl.ren2 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ren1, int_wakeups[1].bits.uop.fp_ctrl.ren1 connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.wen, int_wakeups[1].bits.uop.fp_ctrl.wen connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fp_ctrl.ldst, int_wakeups[1].bits.uop.fp_ctrl.ldst connect unq_iss_unit.io.wakeup_ports[1].bits.uop.op2_sel, int_wakeups[1].bits.uop.op2_sel connect unq_iss_unit.io.wakeup_ports[1].bits.uop.op1_sel, int_wakeups[1].bits.uop.op1_sel connect unq_iss_unit.io.wakeup_ports[1].bits.uop.imm_packed, int_wakeups[1].bits.uop.imm_packed connect unq_iss_unit.io.wakeup_ports[1].bits.uop.pimm, int_wakeups[1].bits.uop.pimm connect unq_iss_unit.io.wakeup_ports[1].bits.uop.imm_sel, int_wakeups[1].bits.uop.imm_sel connect unq_iss_unit.io.wakeup_ports[1].bits.uop.imm_rename, int_wakeups[1].bits.uop.imm_rename connect unq_iss_unit.io.wakeup_ports[1].bits.uop.taken, int_wakeups[1].bits.uop.taken connect unq_iss_unit.io.wakeup_ports[1].bits.uop.pc_lob, int_wakeups[1].bits.uop.pc_lob connect unq_iss_unit.io.wakeup_ports[1].bits.uop.edge_inst, int_wakeups[1].bits.uop.edge_inst connect unq_iss_unit.io.wakeup_ports[1].bits.uop.ftq_idx, int_wakeups[1].bits.uop.ftq_idx connect unq_iss_unit.io.wakeup_ports[1].bits.uop.is_mov, int_wakeups[1].bits.uop.is_mov connect unq_iss_unit.io.wakeup_ports[1].bits.uop.is_rocc, int_wakeups[1].bits.uop.is_rocc connect unq_iss_unit.io.wakeup_ports[1].bits.uop.is_sys_pc2epc, int_wakeups[1].bits.uop.is_sys_pc2epc connect unq_iss_unit.io.wakeup_ports[1].bits.uop.is_eret, int_wakeups[1].bits.uop.is_eret connect unq_iss_unit.io.wakeup_ports[1].bits.uop.is_amo, int_wakeups[1].bits.uop.is_amo connect unq_iss_unit.io.wakeup_ports[1].bits.uop.is_sfence, int_wakeups[1].bits.uop.is_sfence connect unq_iss_unit.io.wakeup_ports[1].bits.uop.is_fencei, int_wakeups[1].bits.uop.is_fencei connect unq_iss_unit.io.wakeup_ports[1].bits.uop.is_fence, int_wakeups[1].bits.uop.is_fence connect unq_iss_unit.io.wakeup_ports[1].bits.uop.is_sfb, int_wakeups[1].bits.uop.is_sfb connect unq_iss_unit.io.wakeup_ports[1].bits.uop.br_type, int_wakeups[1].bits.uop.br_type connect unq_iss_unit.io.wakeup_ports[1].bits.uop.br_tag, int_wakeups[1].bits.uop.br_tag connect unq_iss_unit.io.wakeup_ports[1].bits.uop.br_mask, int_wakeups[1].bits.uop.br_mask connect unq_iss_unit.io.wakeup_ports[1].bits.uop.dis_col_sel, int_wakeups[1].bits.uop.dis_col_sel connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iw_p3_bypass_hint, int_wakeups[1].bits.uop.iw_p3_bypass_hint connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iw_p2_bypass_hint, int_wakeups[1].bits.uop.iw_p2_bypass_hint connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iw_p1_bypass_hint, int_wakeups[1].bits.uop.iw_p1_bypass_hint connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iw_p2_speculative_child, int_wakeups[1].bits.uop.iw_p2_speculative_child connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iw_p1_speculative_child, int_wakeups[1].bits.uop.iw_p1_speculative_child connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iw_issued_partial_dgen, int_wakeups[1].bits.uop.iw_issued_partial_dgen connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iw_issued_partial_agen, int_wakeups[1].bits.uop.iw_issued_partial_agen connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iw_issued, int_wakeups[1].bits.uop.iw_issued connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[0], int_wakeups[1].bits.uop.fu_code[0] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[1], int_wakeups[1].bits.uop.fu_code[1] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[2], int_wakeups[1].bits.uop.fu_code[2] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[3], int_wakeups[1].bits.uop.fu_code[3] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[4], int_wakeups[1].bits.uop.fu_code[4] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[5], int_wakeups[1].bits.uop.fu_code[5] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[6], int_wakeups[1].bits.uop.fu_code[6] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[7], int_wakeups[1].bits.uop.fu_code[7] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[8], int_wakeups[1].bits.uop.fu_code[8] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.fu_code[9], int_wakeups[1].bits.uop.fu_code[9] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[0], int_wakeups[1].bits.uop.iq_type[0] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[1], int_wakeups[1].bits.uop.iq_type[1] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[2], int_wakeups[1].bits.uop.iq_type[2] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.iq_type[3], int_wakeups[1].bits.uop.iq_type[3] connect unq_iss_unit.io.wakeup_ports[1].bits.uop.debug_pc, int_wakeups[1].bits.uop.debug_pc connect unq_iss_unit.io.wakeup_ports[1].bits.uop.is_rvc, int_wakeups[1].bits.uop.is_rvc connect unq_iss_unit.io.wakeup_ports[1].bits.uop.debug_inst, int_wakeups[1].bits.uop.debug_inst connect unq_iss_unit.io.wakeup_ports[1].bits.uop.inst, int_wakeups[1].bits.uop.inst connect unq_iss_unit.io.wakeup_ports[1].valid, int_wakeups[1].valid connect unq_iss_unit.io.wakeup_ports[2].bits.rebusy, int_wakeups[2].bits.rebusy connect unq_iss_unit.io.wakeup_ports[2].bits.speculative_mask, int_wakeups[2].bits.speculative_mask connect unq_iss_unit.io.wakeup_ports[2].bits.bypassable, int_wakeups[2].bits.bypassable connect unq_iss_unit.io.wakeup_ports[2].bits.uop.debug_tsrc, int_wakeups[2].bits.uop.debug_tsrc connect unq_iss_unit.io.wakeup_ports[2].bits.uop.debug_fsrc, int_wakeups[2].bits.uop.debug_fsrc connect unq_iss_unit.io.wakeup_ports[2].bits.uop.bp_xcpt_if, int_wakeups[2].bits.uop.bp_xcpt_if connect unq_iss_unit.io.wakeup_ports[2].bits.uop.bp_debug_if, int_wakeups[2].bits.uop.bp_debug_if connect unq_iss_unit.io.wakeup_ports[2].bits.uop.xcpt_ma_if, int_wakeups[2].bits.uop.xcpt_ma_if connect unq_iss_unit.io.wakeup_ports[2].bits.uop.xcpt_ae_if, int_wakeups[2].bits.uop.xcpt_ae_if connect unq_iss_unit.io.wakeup_ports[2].bits.uop.xcpt_pf_if, int_wakeups[2].bits.uop.xcpt_pf_if connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_typ, int_wakeups[2].bits.uop.fp_typ connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_rm, int_wakeups[2].bits.uop.fp_rm connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_val, int_wakeups[2].bits.uop.fp_val connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fcn_op, int_wakeups[2].bits.uop.fcn_op connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fcn_dw, int_wakeups[2].bits.uop.fcn_dw connect unq_iss_unit.io.wakeup_ports[2].bits.uop.frs3_en, int_wakeups[2].bits.uop.frs3_en connect unq_iss_unit.io.wakeup_ports[2].bits.uop.lrs2_rtype, int_wakeups[2].bits.uop.lrs2_rtype connect unq_iss_unit.io.wakeup_ports[2].bits.uop.lrs1_rtype, int_wakeups[2].bits.uop.lrs1_rtype connect unq_iss_unit.io.wakeup_ports[2].bits.uop.dst_rtype, int_wakeups[2].bits.uop.dst_rtype connect unq_iss_unit.io.wakeup_ports[2].bits.uop.lrs3, int_wakeups[2].bits.uop.lrs3 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.lrs2, int_wakeups[2].bits.uop.lrs2 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.lrs1, int_wakeups[2].bits.uop.lrs1 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.ldst, int_wakeups[2].bits.uop.ldst connect unq_iss_unit.io.wakeup_ports[2].bits.uop.ldst_is_rs1, int_wakeups[2].bits.uop.ldst_is_rs1 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.csr_cmd, int_wakeups[2].bits.uop.csr_cmd connect unq_iss_unit.io.wakeup_ports[2].bits.uop.flush_on_commit, int_wakeups[2].bits.uop.flush_on_commit connect unq_iss_unit.io.wakeup_ports[2].bits.uop.is_unique, int_wakeups[2].bits.uop.is_unique connect unq_iss_unit.io.wakeup_ports[2].bits.uop.uses_stq, int_wakeups[2].bits.uop.uses_stq connect unq_iss_unit.io.wakeup_ports[2].bits.uop.uses_ldq, int_wakeups[2].bits.uop.uses_ldq connect unq_iss_unit.io.wakeup_ports[2].bits.uop.mem_signed, int_wakeups[2].bits.uop.mem_signed connect unq_iss_unit.io.wakeup_ports[2].bits.uop.mem_size, int_wakeups[2].bits.uop.mem_size connect unq_iss_unit.io.wakeup_ports[2].bits.uop.mem_cmd, int_wakeups[2].bits.uop.mem_cmd connect unq_iss_unit.io.wakeup_ports[2].bits.uop.exc_cause, int_wakeups[2].bits.uop.exc_cause connect unq_iss_unit.io.wakeup_ports[2].bits.uop.exception, int_wakeups[2].bits.uop.exception connect unq_iss_unit.io.wakeup_ports[2].bits.uop.stale_pdst, int_wakeups[2].bits.uop.stale_pdst connect unq_iss_unit.io.wakeup_ports[2].bits.uop.ppred_busy, int_wakeups[2].bits.uop.ppred_busy connect unq_iss_unit.io.wakeup_ports[2].bits.uop.prs3_busy, int_wakeups[2].bits.uop.prs3_busy connect unq_iss_unit.io.wakeup_ports[2].bits.uop.prs2_busy, int_wakeups[2].bits.uop.prs2_busy connect unq_iss_unit.io.wakeup_ports[2].bits.uop.prs1_busy, int_wakeups[2].bits.uop.prs1_busy connect unq_iss_unit.io.wakeup_ports[2].bits.uop.ppred, int_wakeups[2].bits.uop.ppred connect unq_iss_unit.io.wakeup_ports[2].bits.uop.prs3, int_wakeups[2].bits.uop.prs3 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.prs2, int_wakeups[2].bits.uop.prs2 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.prs1, int_wakeups[2].bits.uop.prs1 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.pdst, int_wakeups[2].bits.uop.pdst connect unq_iss_unit.io.wakeup_ports[2].bits.uop.rxq_idx, int_wakeups[2].bits.uop.rxq_idx connect unq_iss_unit.io.wakeup_ports[2].bits.uop.stq_idx, int_wakeups[2].bits.uop.stq_idx connect unq_iss_unit.io.wakeup_ports[2].bits.uop.ldq_idx, int_wakeups[2].bits.uop.ldq_idx connect unq_iss_unit.io.wakeup_ports[2].bits.uop.rob_idx, int_wakeups[2].bits.uop.rob_idx connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.vec, int_wakeups[2].bits.uop.fp_ctrl.vec connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.wflags, int_wakeups[2].bits.uop.fp_ctrl.wflags connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.sqrt, int_wakeups[2].bits.uop.fp_ctrl.sqrt connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.div, int_wakeups[2].bits.uop.fp_ctrl.div connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.fma, int_wakeups[2].bits.uop.fp_ctrl.fma connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.fastpipe, int_wakeups[2].bits.uop.fp_ctrl.fastpipe connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.toint, int_wakeups[2].bits.uop.fp_ctrl.toint connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.fromint, int_wakeups[2].bits.uop.fp_ctrl.fromint connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagOut, int_wakeups[2].bits.uop.fp_ctrl.typeTagOut connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.typeTagIn, int_wakeups[2].bits.uop.fp_ctrl.typeTagIn connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.swap23, int_wakeups[2].bits.uop.fp_ctrl.swap23 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.swap12, int_wakeups[2].bits.uop.fp_ctrl.swap12 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ren3, int_wakeups[2].bits.uop.fp_ctrl.ren3 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ren2, int_wakeups[2].bits.uop.fp_ctrl.ren2 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ren1, int_wakeups[2].bits.uop.fp_ctrl.ren1 connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.wen, int_wakeups[2].bits.uop.fp_ctrl.wen connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fp_ctrl.ldst, int_wakeups[2].bits.uop.fp_ctrl.ldst connect unq_iss_unit.io.wakeup_ports[2].bits.uop.op2_sel, int_wakeups[2].bits.uop.op2_sel connect unq_iss_unit.io.wakeup_ports[2].bits.uop.op1_sel, int_wakeups[2].bits.uop.op1_sel connect unq_iss_unit.io.wakeup_ports[2].bits.uop.imm_packed, int_wakeups[2].bits.uop.imm_packed connect unq_iss_unit.io.wakeup_ports[2].bits.uop.pimm, int_wakeups[2].bits.uop.pimm connect unq_iss_unit.io.wakeup_ports[2].bits.uop.imm_sel, int_wakeups[2].bits.uop.imm_sel connect unq_iss_unit.io.wakeup_ports[2].bits.uop.imm_rename, int_wakeups[2].bits.uop.imm_rename connect unq_iss_unit.io.wakeup_ports[2].bits.uop.taken, int_wakeups[2].bits.uop.taken connect unq_iss_unit.io.wakeup_ports[2].bits.uop.pc_lob, int_wakeups[2].bits.uop.pc_lob connect unq_iss_unit.io.wakeup_ports[2].bits.uop.edge_inst, int_wakeups[2].bits.uop.edge_inst connect unq_iss_unit.io.wakeup_ports[2].bits.uop.ftq_idx, int_wakeups[2].bits.uop.ftq_idx connect unq_iss_unit.io.wakeup_ports[2].bits.uop.is_mov, int_wakeups[2].bits.uop.is_mov connect unq_iss_unit.io.wakeup_ports[2].bits.uop.is_rocc, int_wakeups[2].bits.uop.is_rocc connect unq_iss_unit.io.wakeup_ports[2].bits.uop.is_sys_pc2epc, int_wakeups[2].bits.uop.is_sys_pc2epc connect unq_iss_unit.io.wakeup_ports[2].bits.uop.is_eret, int_wakeups[2].bits.uop.is_eret connect unq_iss_unit.io.wakeup_ports[2].bits.uop.is_amo, int_wakeups[2].bits.uop.is_amo connect unq_iss_unit.io.wakeup_ports[2].bits.uop.is_sfence, int_wakeups[2].bits.uop.is_sfence connect unq_iss_unit.io.wakeup_ports[2].bits.uop.is_fencei, int_wakeups[2].bits.uop.is_fencei connect unq_iss_unit.io.wakeup_ports[2].bits.uop.is_fence, int_wakeups[2].bits.uop.is_fence connect unq_iss_unit.io.wakeup_ports[2].bits.uop.is_sfb, int_wakeups[2].bits.uop.is_sfb connect unq_iss_unit.io.wakeup_ports[2].bits.uop.br_type, int_wakeups[2].bits.uop.br_type connect unq_iss_unit.io.wakeup_ports[2].bits.uop.br_tag, int_wakeups[2].bits.uop.br_tag connect unq_iss_unit.io.wakeup_ports[2].bits.uop.br_mask, int_wakeups[2].bits.uop.br_mask connect unq_iss_unit.io.wakeup_ports[2].bits.uop.dis_col_sel, int_wakeups[2].bits.uop.dis_col_sel connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iw_p3_bypass_hint, int_wakeups[2].bits.uop.iw_p3_bypass_hint connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iw_p2_bypass_hint, int_wakeups[2].bits.uop.iw_p2_bypass_hint connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iw_p1_bypass_hint, int_wakeups[2].bits.uop.iw_p1_bypass_hint connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iw_p2_speculative_child, int_wakeups[2].bits.uop.iw_p2_speculative_child connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iw_p1_speculative_child, int_wakeups[2].bits.uop.iw_p1_speculative_child connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iw_issued_partial_dgen, int_wakeups[2].bits.uop.iw_issued_partial_dgen connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iw_issued_partial_agen, int_wakeups[2].bits.uop.iw_issued_partial_agen connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iw_issued, int_wakeups[2].bits.uop.iw_issued connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[0], int_wakeups[2].bits.uop.fu_code[0] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[1], int_wakeups[2].bits.uop.fu_code[1] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[2], int_wakeups[2].bits.uop.fu_code[2] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[3], int_wakeups[2].bits.uop.fu_code[3] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[4], int_wakeups[2].bits.uop.fu_code[4] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[5], int_wakeups[2].bits.uop.fu_code[5] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[6], int_wakeups[2].bits.uop.fu_code[6] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[7], int_wakeups[2].bits.uop.fu_code[7] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[8], int_wakeups[2].bits.uop.fu_code[8] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.fu_code[9], int_wakeups[2].bits.uop.fu_code[9] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[0], int_wakeups[2].bits.uop.iq_type[0] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[1], int_wakeups[2].bits.uop.iq_type[1] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[2], int_wakeups[2].bits.uop.iq_type[2] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.iq_type[3], int_wakeups[2].bits.uop.iq_type[3] connect unq_iss_unit.io.wakeup_ports[2].bits.uop.debug_pc, int_wakeups[2].bits.uop.debug_pc connect unq_iss_unit.io.wakeup_ports[2].bits.uop.is_rvc, int_wakeups[2].bits.uop.is_rvc connect unq_iss_unit.io.wakeup_ports[2].bits.uop.debug_inst, int_wakeups[2].bits.uop.debug_inst connect unq_iss_unit.io.wakeup_ports[2].bits.uop.inst, int_wakeups[2].bits.uop.inst connect unq_iss_unit.io.wakeup_ports[2].valid, int_wakeups[2].valid connect unq_iss_unit.io.wakeup_ports[3].bits.rebusy, int_wakeups[3].bits.rebusy connect unq_iss_unit.io.wakeup_ports[3].bits.speculative_mask, int_wakeups[3].bits.speculative_mask connect unq_iss_unit.io.wakeup_ports[3].bits.bypassable, int_wakeups[3].bits.bypassable connect unq_iss_unit.io.wakeup_ports[3].bits.uop.debug_tsrc, int_wakeups[3].bits.uop.debug_tsrc connect unq_iss_unit.io.wakeup_ports[3].bits.uop.debug_fsrc, int_wakeups[3].bits.uop.debug_fsrc connect unq_iss_unit.io.wakeup_ports[3].bits.uop.bp_xcpt_if, int_wakeups[3].bits.uop.bp_xcpt_if connect unq_iss_unit.io.wakeup_ports[3].bits.uop.bp_debug_if, int_wakeups[3].bits.uop.bp_debug_if connect unq_iss_unit.io.wakeup_ports[3].bits.uop.xcpt_ma_if, int_wakeups[3].bits.uop.xcpt_ma_if connect unq_iss_unit.io.wakeup_ports[3].bits.uop.xcpt_ae_if, int_wakeups[3].bits.uop.xcpt_ae_if connect unq_iss_unit.io.wakeup_ports[3].bits.uop.xcpt_pf_if, int_wakeups[3].bits.uop.xcpt_pf_if connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_typ, int_wakeups[3].bits.uop.fp_typ connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_rm, int_wakeups[3].bits.uop.fp_rm connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_val, int_wakeups[3].bits.uop.fp_val connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fcn_op, int_wakeups[3].bits.uop.fcn_op connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fcn_dw, int_wakeups[3].bits.uop.fcn_dw connect unq_iss_unit.io.wakeup_ports[3].bits.uop.frs3_en, int_wakeups[3].bits.uop.frs3_en connect unq_iss_unit.io.wakeup_ports[3].bits.uop.lrs2_rtype, int_wakeups[3].bits.uop.lrs2_rtype connect unq_iss_unit.io.wakeup_ports[3].bits.uop.lrs1_rtype, int_wakeups[3].bits.uop.lrs1_rtype connect unq_iss_unit.io.wakeup_ports[3].bits.uop.dst_rtype, int_wakeups[3].bits.uop.dst_rtype connect unq_iss_unit.io.wakeup_ports[3].bits.uop.lrs3, int_wakeups[3].bits.uop.lrs3 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.lrs2, int_wakeups[3].bits.uop.lrs2 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.lrs1, int_wakeups[3].bits.uop.lrs1 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.ldst, int_wakeups[3].bits.uop.ldst connect unq_iss_unit.io.wakeup_ports[3].bits.uop.ldst_is_rs1, int_wakeups[3].bits.uop.ldst_is_rs1 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.csr_cmd, int_wakeups[3].bits.uop.csr_cmd connect unq_iss_unit.io.wakeup_ports[3].bits.uop.flush_on_commit, int_wakeups[3].bits.uop.flush_on_commit connect unq_iss_unit.io.wakeup_ports[3].bits.uop.is_unique, int_wakeups[3].bits.uop.is_unique connect unq_iss_unit.io.wakeup_ports[3].bits.uop.uses_stq, int_wakeups[3].bits.uop.uses_stq connect unq_iss_unit.io.wakeup_ports[3].bits.uop.uses_ldq, int_wakeups[3].bits.uop.uses_ldq connect unq_iss_unit.io.wakeup_ports[3].bits.uop.mem_signed, int_wakeups[3].bits.uop.mem_signed connect unq_iss_unit.io.wakeup_ports[3].bits.uop.mem_size, int_wakeups[3].bits.uop.mem_size connect unq_iss_unit.io.wakeup_ports[3].bits.uop.mem_cmd, int_wakeups[3].bits.uop.mem_cmd connect unq_iss_unit.io.wakeup_ports[3].bits.uop.exc_cause, int_wakeups[3].bits.uop.exc_cause connect unq_iss_unit.io.wakeup_ports[3].bits.uop.exception, int_wakeups[3].bits.uop.exception connect unq_iss_unit.io.wakeup_ports[3].bits.uop.stale_pdst, int_wakeups[3].bits.uop.stale_pdst connect unq_iss_unit.io.wakeup_ports[3].bits.uop.ppred_busy, int_wakeups[3].bits.uop.ppred_busy connect unq_iss_unit.io.wakeup_ports[3].bits.uop.prs3_busy, int_wakeups[3].bits.uop.prs3_busy connect unq_iss_unit.io.wakeup_ports[3].bits.uop.prs2_busy, int_wakeups[3].bits.uop.prs2_busy connect unq_iss_unit.io.wakeup_ports[3].bits.uop.prs1_busy, int_wakeups[3].bits.uop.prs1_busy connect unq_iss_unit.io.wakeup_ports[3].bits.uop.ppred, int_wakeups[3].bits.uop.ppred connect unq_iss_unit.io.wakeup_ports[3].bits.uop.prs3, int_wakeups[3].bits.uop.prs3 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.prs2, int_wakeups[3].bits.uop.prs2 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.prs1, int_wakeups[3].bits.uop.prs1 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.pdst, int_wakeups[3].bits.uop.pdst connect unq_iss_unit.io.wakeup_ports[3].bits.uop.rxq_idx, int_wakeups[3].bits.uop.rxq_idx connect unq_iss_unit.io.wakeup_ports[3].bits.uop.stq_idx, int_wakeups[3].bits.uop.stq_idx connect unq_iss_unit.io.wakeup_ports[3].bits.uop.ldq_idx, int_wakeups[3].bits.uop.ldq_idx connect unq_iss_unit.io.wakeup_ports[3].bits.uop.rob_idx, int_wakeups[3].bits.uop.rob_idx connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.vec, int_wakeups[3].bits.uop.fp_ctrl.vec connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.wflags, int_wakeups[3].bits.uop.fp_ctrl.wflags connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.sqrt, int_wakeups[3].bits.uop.fp_ctrl.sqrt connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.div, int_wakeups[3].bits.uop.fp_ctrl.div connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.fma, int_wakeups[3].bits.uop.fp_ctrl.fma connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.fastpipe, int_wakeups[3].bits.uop.fp_ctrl.fastpipe connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.toint, int_wakeups[3].bits.uop.fp_ctrl.toint connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.fromint, int_wakeups[3].bits.uop.fp_ctrl.fromint connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagOut, int_wakeups[3].bits.uop.fp_ctrl.typeTagOut connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.typeTagIn, int_wakeups[3].bits.uop.fp_ctrl.typeTagIn connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.swap23, int_wakeups[3].bits.uop.fp_ctrl.swap23 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.swap12, int_wakeups[3].bits.uop.fp_ctrl.swap12 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ren3, int_wakeups[3].bits.uop.fp_ctrl.ren3 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ren2, int_wakeups[3].bits.uop.fp_ctrl.ren2 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ren1, int_wakeups[3].bits.uop.fp_ctrl.ren1 connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.wen, int_wakeups[3].bits.uop.fp_ctrl.wen connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fp_ctrl.ldst, int_wakeups[3].bits.uop.fp_ctrl.ldst connect unq_iss_unit.io.wakeup_ports[3].bits.uop.op2_sel, int_wakeups[3].bits.uop.op2_sel connect unq_iss_unit.io.wakeup_ports[3].bits.uop.op1_sel, int_wakeups[3].bits.uop.op1_sel connect unq_iss_unit.io.wakeup_ports[3].bits.uop.imm_packed, int_wakeups[3].bits.uop.imm_packed connect unq_iss_unit.io.wakeup_ports[3].bits.uop.pimm, int_wakeups[3].bits.uop.pimm connect unq_iss_unit.io.wakeup_ports[3].bits.uop.imm_sel, int_wakeups[3].bits.uop.imm_sel connect unq_iss_unit.io.wakeup_ports[3].bits.uop.imm_rename, int_wakeups[3].bits.uop.imm_rename connect unq_iss_unit.io.wakeup_ports[3].bits.uop.taken, int_wakeups[3].bits.uop.taken connect unq_iss_unit.io.wakeup_ports[3].bits.uop.pc_lob, int_wakeups[3].bits.uop.pc_lob connect unq_iss_unit.io.wakeup_ports[3].bits.uop.edge_inst, int_wakeups[3].bits.uop.edge_inst connect unq_iss_unit.io.wakeup_ports[3].bits.uop.ftq_idx, int_wakeups[3].bits.uop.ftq_idx connect unq_iss_unit.io.wakeup_ports[3].bits.uop.is_mov, int_wakeups[3].bits.uop.is_mov connect unq_iss_unit.io.wakeup_ports[3].bits.uop.is_rocc, int_wakeups[3].bits.uop.is_rocc connect unq_iss_unit.io.wakeup_ports[3].bits.uop.is_sys_pc2epc, int_wakeups[3].bits.uop.is_sys_pc2epc connect unq_iss_unit.io.wakeup_ports[3].bits.uop.is_eret, int_wakeups[3].bits.uop.is_eret connect unq_iss_unit.io.wakeup_ports[3].bits.uop.is_amo, int_wakeups[3].bits.uop.is_amo connect unq_iss_unit.io.wakeup_ports[3].bits.uop.is_sfence, int_wakeups[3].bits.uop.is_sfence connect unq_iss_unit.io.wakeup_ports[3].bits.uop.is_fencei, int_wakeups[3].bits.uop.is_fencei connect unq_iss_unit.io.wakeup_ports[3].bits.uop.is_fence, int_wakeups[3].bits.uop.is_fence connect unq_iss_unit.io.wakeup_ports[3].bits.uop.is_sfb, int_wakeups[3].bits.uop.is_sfb connect unq_iss_unit.io.wakeup_ports[3].bits.uop.br_type, int_wakeups[3].bits.uop.br_type connect unq_iss_unit.io.wakeup_ports[3].bits.uop.br_tag, int_wakeups[3].bits.uop.br_tag connect unq_iss_unit.io.wakeup_ports[3].bits.uop.br_mask, int_wakeups[3].bits.uop.br_mask connect unq_iss_unit.io.wakeup_ports[3].bits.uop.dis_col_sel, int_wakeups[3].bits.uop.dis_col_sel connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iw_p3_bypass_hint, int_wakeups[3].bits.uop.iw_p3_bypass_hint connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iw_p2_bypass_hint, int_wakeups[3].bits.uop.iw_p2_bypass_hint connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iw_p1_bypass_hint, int_wakeups[3].bits.uop.iw_p1_bypass_hint connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iw_p2_speculative_child, int_wakeups[3].bits.uop.iw_p2_speculative_child connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iw_p1_speculative_child, int_wakeups[3].bits.uop.iw_p1_speculative_child connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iw_issued_partial_dgen, int_wakeups[3].bits.uop.iw_issued_partial_dgen connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iw_issued_partial_agen, int_wakeups[3].bits.uop.iw_issued_partial_agen connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iw_issued, int_wakeups[3].bits.uop.iw_issued connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[0], int_wakeups[3].bits.uop.fu_code[0] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[1], int_wakeups[3].bits.uop.fu_code[1] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[2], int_wakeups[3].bits.uop.fu_code[2] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[3], int_wakeups[3].bits.uop.fu_code[3] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[4], int_wakeups[3].bits.uop.fu_code[4] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[5], int_wakeups[3].bits.uop.fu_code[5] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[6], int_wakeups[3].bits.uop.fu_code[6] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[7], int_wakeups[3].bits.uop.fu_code[7] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[8], int_wakeups[3].bits.uop.fu_code[8] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.fu_code[9], int_wakeups[3].bits.uop.fu_code[9] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[0], int_wakeups[3].bits.uop.iq_type[0] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[1], int_wakeups[3].bits.uop.iq_type[1] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[2], int_wakeups[3].bits.uop.iq_type[2] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.iq_type[3], int_wakeups[3].bits.uop.iq_type[3] connect unq_iss_unit.io.wakeup_ports[3].bits.uop.debug_pc, int_wakeups[3].bits.uop.debug_pc connect unq_iss_unit.io.wakeup_ports[3].bits.uop.is_rvc, int_wakeups[3].bits.uop.is_rvc connect unq_iss_unit.io.wakeup_ports[3].bits.uop.debug_inst, int_wakeups[3].bits.uop.debug_inst connect unq_iss_unit.io.wakeup_ports[3].bits.uop.inst, int_wakeups[3].bits.uop.inst connect unq_iss_unit.io.wakeup_ports[3].valid, int_wakeups[3].valid node _mem_iss_unit_io_squash_grant_T = or(mem_exe_unit_0.io_squash_iss, mem_exe_unit_1.io_squash_iss) node _mem_iss_unit_io_squash_grant_T_1 = or(alu_exe_unit_0.io_squash_iss, alu_exe_unit_1.io_squash_iss) node _mem_iss_unit_io_squash_grant_T_2 = or(_mem_iss_unit_io_squash_grant_T, _mem_iss_unit_io_squash_grant_T_1) node _mem_iss_unit_io_squash_grant_T_3 = or(_mem_iss_unit_io_squash_grant_T_2, io.lsu.iwakeups[0].bits.rebusy) connect mem_iss_unit.io.squash_grant, _mem_iss_unit_io_squash_grant_T_3 node _unq_iss_unit_io_squash_grant_T = or(alu_exe_unit_0.io_squash_iss, alu_exe_unit_1.io_squash_iss) node _unq_iss_unit_io_squash_grant_T_1 = or(unique_exe_unit_0.io_squash_iss, _unq_iss_unit_io_squash_grant_T) node _unq_iss_unit_io_squash_grant_T_2 = or(_unq_iss_unit_io_squash_grant_T_1, io.lsu.iwakeups[0].bits.rebusy) connect unq_iss_unit.io.squash_grant, _unq_iss_unit_io_squash_grant_T_2 node _alu_iss_unit_io_squash_grant_T = or(alu_exe_unit_0.io_squash_iss, alu_exe_unit_1.io_squash_iss) node _alu_iss_unit_io_squash_grant_T_1 = or(_alu_iss_unit_io_squash_grant_T, io.lsu.iwakeups[0].bits.rebusy) connect alu_iss_unit.io.squash_grant, _alu_iss_unit_io_squash_grant_T_1 connect mem_exe_unit_0.io_iss_uop.bits.debug_tsrc, mem_iss_unit.io.iss_uops[0].bits.debug_tsrc connect mem_exe_unit_0.io_iss_uop.bits.debug_fsrc, mem_iss_unit.io.iss_uops[0].bits.debug_fsrc connect mem_exe_unit_0.io_iss_uop.bits.bp_xcpt_if, mem_iss_unit.io.iss_uops[0].bits.bp_xcpt_if connect mem_exe_unit_0.io_iss_uop.bits.bp_debug_if, mem_iss_unit.io.iss_uops[0].bits.bp_debug_if connect mem_exe_unit_0.io_iss_uop.bits.xcpt_ma_if, mem_iss_unit.io.iss_uops[0].bits.xcpt_ma_if connect mem_exe_unit_0.io_iss_uop.bits.xcpt_ae_if, mem_iss_unit.io.iss_uops[0].bits.xcpt_ae_if connect mem_exe_unit_0.io_iss_uop.bits.xcpt_pf_if, mem_iss_unit.io.iss_uops[0].bits.xcpt_pf_if connect mem_exe_unit_0.io_iss_uop.bits.fp_typ, mem_iss_unit.io.iss_uops[0].bits.fp_typ connect mem_exe_unit_0.io_iss_uop.bits.fp_rm, mem_iss_unit.io.iss_uops[0].bits.fp_rm connect mem_exe_unit_0.io_iss_uop.bits.fp_val, mem_iss_unit.io.iss_uops[0].bits.fp_val connect mem_exe_unit_0.io_iss_uop.bits.fcn_op, mem_iss_unit.io.iss_uops[0].bits.fcn_op connect mem_exe_unit_0.io_iss_uop.bits.fcn_dw, mem_iss_unit.io.iss_uops[0].bits.fcn_dw connect mem_exe_unit_0.io_iss_uop.bits.frs3_en, mem_iss_unit.io.iss_uops[0].bits.frs3_en connect mem_exe_unit_0.io_iss_uop.bits.lrs2_rtype, mem_iss_unit.io.iss_uops[0].bits.lrs2_rtype connect mem_exe_unit_0.io_iss_uop.bits.lrs1_rtype, mem_iss_unit.io.iss_uops[0].bits.lrs1_rtype connect mem_exe_unit_0.io_iss_uop.bits.dst_rtype, mem_iss_unit.io.iss_uops[0].bits.dst_rtype connect mem_exe_unit_0.io_iss_uop.bits.lrs3, mem_iss_unit.io.iss_uops[0].bits.lrs3 connect mem_exe_unit_0.io_iss_uop.bits.lrs2, mem_iss_unit.io.iss_uops[0].bits.lrs2 connect mem_exe_unit_0.io_iss_uop.bits.lrs1, mem_iss_unit.io.iss_uops[0].bits.lrs1 connect mem_exe_unit_0.io_iss_uop.bits.ldst, mem_iss_unit.io.iss_uops[0].bits.ldst connect mem_exe_unit_0.io_iss_uop.bits.ldst_is_rs1, mem_iss_unit.io.iss_uops[0].bits.ldst_is_rs1 connect mem_exe_unit_0.io_iss_uop.bits.csr_cmd, mem_iss_unit.io.iss_uops[0].bits.csr_cmd connect mem_exe_unit_0.io_iss_uop.bits.flush_on_commit, mem_iss_unit.io.iss_uops[0].bits.flush_on_commit connect mem_exe_unit_0.io_iss_uop.bits.is_unique, mem_iss_unit.io.iss_uops[0].bits.is_unique connect mem_exe_unit_0.io_iss_uop.bits.uses_stq, mem_iss_unit.io.iss_uops[0].bits.uses_stq connect mem_exe_unit_0.io_iss_uop.bits.uses_ldq, mem_iss_unit.io.iss_uops[0].bits.uses_ldq connect mem_exe_unit_0.io_iss_uop.bits.mem_signed, mem_iss_unit.io.iss_uops[0].bits.mem_signed connect mem_exe_unit_0.io_iss_uop.bits.mem_size, mem_iss_unit.io.iss_uops[0].bits.mem_size connect mem_exe_unit_0.io_iss_uop.bits.mem_cmd, mem_iss_unit.io.iss_uops[0].bits.mem_cmd connect mem_exe_unit_0.io_iss_uop.bits.exc_cause, mem_iss_unit.io.iss_uops[0].bits.exc_cause connect mem_exe_unit_0.io_iss_uop.bits.exception, mem_iss_unit.io.iss_uops[0].bits.exception connect mem_exe_unit_0.io_iss_uop.bits.stale_pdst, mem_iss_unit.io.iss_uops[0].bits.stale_pdst connect mem_exe_unit_0.io_iss_uop.bits.ppred_busy, mem_iss_unit.io.iss_uops[0].bits.ppred_busy connect mem_exe_unit_0.io_iss_uop.bits.prs3_busy, mem_iss_unit.io.iss_uops[0].bits.prs3_busy connect mem_exe_unit_0.io_iss_uop.bits.prs2_busy, mem_iss_unit.io.iss_uops[0].bits.prs2_busy connect mem_exe_unit_0.io_iss_uop.bits.prs1_busy, mem_iss_unit.io.iss_uops[0].bits.prs1_busy connect mem_exe_unit_0.io_iss_uop.bits.ppred, mem_iss_unit.io.iss_uops[0].bits.ppred connect mem_exe_unit_0.io_iss_uop.bits.prs3, mem_iss_unit.io.iss_uops[0].bits.prs3 connect mem_exe_unit_0.io_iss_uop.bits.prs2, mem_iss_unit.io.iss_uops[0].bits.prs2 connect mem_exe_unit_0.io_iss_uop.bits.prs1, mem_iss_unit.io.iss_uops[0].bits.prs1 connect mem_exe_unit_0.io_iss_uop.bits.pdst, mem_iss_unit.io.iss_uops[0].bits.pdst connect mem_exe_unit_0.io_iss_uop.bits.rxq_idx, mem_iss_unit.io.iss_uops[0].bits.rxq_idx connect mem_exe_unit_0.io_iss_uop.bits.stq_idx, mem_iss_unit.io.iss_uops[0].bits.stq_idx connect mem_exe_unit_0.io_iss_uop.bits.ldq_idx, mem_iss_unit.io.iss_uops[0].bits.ldq_idx connect mem_exe_unit_0.io_iss_uop.bits.rob_idx, mem_iss_unit.io.iss_uops[0].bits.rob_idx connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.vec, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.vec connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.wflags, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.wflags connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.sqrt, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.sqrt connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.div, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.div connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.fma, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.fma connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.fastpipe, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.fastpipe connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.toint, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.toint connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.fromint, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.fromint connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.typeTagOut, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.typeTagOut connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.typeTagIn, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.typeTagIn connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.swap23, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.swap23 connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.swap12, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.swap12 connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren3, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.ren3 connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren2, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.ren2 connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren1, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.ren1 connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.wen, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.wen connect mem_exe_unit_0.io_iss_uop.bits.fp_ctrl.ldst, mem_iss_unit.io.iss_uops[0].bits.fp_ctrl.ldst connect mem_exe_unit_0.io_iss_uop.bits.op2_sel, mem_iss_unit.io.iss_uops[0].bits.op2_sel connect mem_exe_unit_0.io_iss_uop.bits.op1_sel, mem_iss_unit.io.iss_uops[0].bits.op1_sel connect mem_exe_unit_0.io_iss_uop.bits.imm_packed, mem_iss_unit.io.iss_uops[0].bits.imm_packed connect mem_exe_unit_0.io_iss_uop.bits.pimm, mem_iss_unit.io.iss_uops[0].bits.pimm connect mem_exe_unit_0.io_iss_uop.bits.imm_sel, mem_iss_unit.io.iss_uops[0].bits.imm_sel connect mem_exe_unit_0.io_iss_uop.bits.imm_rename, mem_iss_unit.io.iss_uops[0].bits.imm_rename connect mem_exe_unit_0.io_iss_uop.bits.taken, mem_iss_unit.io.iss_uops[0].bits.taken connect mem_exe_unit_0.io_iss_uop.bits.pc_lob, mem_iss_unit.io.iss_uops[0].bits.pc_lob connect mem_exe_unit_0.io_iss_uop.bits.edge_inst, mem_iss_unit.io.iss_uops[0].bits.edge_inst connect mem_exe_unit_0.io_iss_uop.bits.ftq_idx, mem_iss_unit.io.iss_uops[0].bits.ftq_idx connect mem_exe_unit_0.io_iss_uop.bits.is_mov, mem_iss_unit.io.iss_uops[0].bits.is_mov connect mem_exe_unit_0.io_iss_uop.bits.is_rocc, mem_iss_unit.io.iss_uops[0].bits.is_rocc connect mem_exe_unit_0.io_iss_uop.bits.is_sys_pc2epc, mem_iss_unit.io.iss_uops[0].bits.is_sys_pc2epc connect mem_exe_unit_0.io_iss_uop.bits.is_eret, mem_iss_unit.io.iss_uops[0].bits.is_eret connect mem_exe_unit_0.io_iss_uop.bits.is_amo, mem_iss_unit.io.iss_uops[0].bits.is_amo connect mem_exe_unit_0.io_iss_uop.bits.is_sfence, mem_iss_unit.io.iss_uops[0].bits.is_sfence connect mem_exe_unit_0.io_iss_uop.bits.is_fencei, mem_iss_unit.io.iss_uops[0].bits.is_fencei connect mem_exe_unit_0.io_iss_uop.bits.is_fence, mem_iss_unit.io.iss_uops[0].bits.is_fence connect mem_exe_unit_0.io_iss_uop.bits.is_sfb, mem_iss_unit.io.iss_uops[0].bits.is_sfb connect mem_exe_unit_0.io_iss_uop.bits.br_type, mem_iss_unit.io.iss_uops[0].bits.br_type connect mem_exe_unit_0.io_iss_uop.bits.br_tag, mem_iss_unit.io.iss_uops[0].bits.br_tag connect mem_exe_unit_0.io_iss_uop.bits.br_mask, mem_iss_unit.io.iss_uops[0].bits.br_mask connect mem_exe_unit_0.io_iss_uop.bits.dis_col_sel, mem_iss_unit.io.iss_uops[0].bits.dis_col_sel connect mem_exe_unit_0.io_iss_uop.bits.iw_p3_bypass_hint, mem_iss_unit.io.iss_uops[0].bits.iw_p3_bypass_hint connect mem_exe_unit_0.io_iss_uop.bits.iw_p2_bypass_hint, mem_iss_unit.io.iss_uops[0].bits.iw_p2_bypass_hint connect mem_exe_unit_0.io_iss_uop.bits.iw_p1_bypass_hint, mem_iss_unit.io.iss_uops[0].bits.iw_p1_bypass_hint connect mem_exe_unit_0.io_iss_uop.bits.iw_p2_speculative_child, mem_iss_unit.io.iss_uops[0].bits.iw_p2_speculative_child connect mem_exe_unit_0.io_iss_uop.bits.iw_p1_speculative_child, mem_iss_unit.io.iss_uops[0].bits.iw_p1_speculative_child connect mem_exe_unit_0.io_iss_uop.bits.iw_issued_partial_dgen, mem_iss_unit.io.iss_uops[0].bits.iw_issued_partial_dgen connect mem_exe_unit_0.io_iss_uop.bits.iw_issued_partial_agen, mem_iss_unit.io.iss_uops[0].bits.iw_issued_partial_agen connect mem_exe_unit_0.io_iss_uop.bits.iw_issued, mem_iss_unit.io.iss_uops[0].bits.iw_issued connect mem_exe_unit_0.io_iss_uop.bits.fu_code[0], mem_iss_unit.io.iss_uops[0].bits.fu_code[0] connect mem_exe_unit_0.io_iss_uop.bits.fu_code[1], mem_iss_unit.io.iss_uops[0].bits.fu_code[1] connect mem_exe_unit_0.io_iss_uop.bits.fu_code[2], mem_iss_unit.io.iss_uops[0].bits.fu_code[2] connect mem_exe_unit_0.io_iss_uop.bits.fu_code[3], mem_iss_unit.io.iss_uops[0].bits.fu_code[3] connect mem_exe_unit_0.io_iss_uop.bits.fu_code[4], mem_iss_unit.io.iss_uops[0].bits.fu_code[4] connect mem_exe_unit_0.io_iss_uop.bits.fu_code[5], mem_iss_unit.io.iss_uops[0].bits.fu_code[5] connect mem_exe_unit_0.io_iss_uop.bits.fu_code[6], mem_iss_unit.io.iss_uops[0].bits.fu_code[6] connect mem_exe_unit_0.io_iss_uop.bits.fu_code[7], mem_iss_unit.io.iss_uops[0].bits.fu_code[7] connect mem_exe_unit_0.io_iss_uop.bits.fu_code[8], mem_iss_unit.io.iss_uops[0].bits.fu_code[8] connect mem_exe_unit_0.io_iss_uop.bits.fu_code[9], mem_iss_unit.io.iss_uops[0].bits.fu_code[9] connect mem_exe_unit_0.io_iss_uop.bits.iq_type[0], mem_iss_unit.io.iss_uops[0].bits.iq_type[0] connect mem_exe_unit_0.io_iss_uop.bits.iq_type[1], mem_iss_unit.io.iss_uops[0].bits.iq_type[1] connect mem_exe_unit_0.io_iss_uop.bits.iq_type[2], mem_iss_unit.io.iss_uops[0].bits.iq_type[2] connect mem_exe_unit_0.io_iss_uop.bits.iq_type[3], mem_iss_unit.io.iss_uops[0].bits.iq_type[3] connect mem_exe_unit_0.io_iss_uop.bits.debug_pc, mem_iss_unit.io.iss_uops[0].bits.debug_pc connect mem_exe_unit_0.io_iss_uop.bits.is_rvc, mem_iss_unit.io.iss_uops[0].bits.is_rvc connect mem_exe_unit_0.io_iss_uop.bits.debug_inst, mem_iss_unit.io.iss_uops[0].bits.debug_inst connect mem_exe_unit_0.io_iss_uop.bits.inst, mem_iss_unit.io.iss_uops[0].bits.inst connect mem_exe_unit_0.io_iss_uop.valid, mem_iss_unit.io.iss_uops[0].valid connect mem_exe_unit_1.io_iss_uop.bits.debug_tsrc, mem_iss_unit.io.iss_uops[1].bits.debug_tsrc connect mem_exe_unit_1.io_iss_uop.bits.debug_fsrc, mem_iss_unit.io.iss_uops[1].bits.debug_fsrc connect mem_exe_unit_1.io_iss_uop.bits.bp_xcpt_if, mem_iss_unit.io.iss_uops[1].bits.bp_xcpt_if connect mem_exe_unit_1.io_iss_uop.bits.bp_debug_if, mem_iss_unit.io.iss_uops[1].bits.bp_debug_if connect mem_exe_unit_1.io_iss_uop.bits.xcpt_ma_if, mem_iss_unit.io.iss_uops[1].bits.xcpt_ma_if connect mem_exe_unit_1.io_iss_uop.bits.xcpt_ae_if, mem_iss_unit.io.iss_uops[1].bits.xcpt_ae_if connect mem_exe_unit_1.io_iss_uop.bits.xcpt_pf_if, mem_iss_unit.io.iss_uops[1].bits.xcpt_pf_if connect mem_exe_unit_1.io_iss_uop.bits.fp_typ, mem_iss_unit.io.iss_uops[1].bits.fp_typ connect mem_exe_unit_1.io_iss_uop.bits.fp_rm, mem_iss_unit.io.iss_uops[1].bits.fp_rm connect mem_exe_unit_1.io_iss_uop.bits.fp_val, mem_iss_unit.io.iss_uops[1].bits.fp_val connect mem_exe_unit_1.io_iss_uop.bits.fcn_op, mem_iss_unit.io.iss_uops[1].bits.fcn_op connect mem_exe_unit_1.io_iss_uop.bits.fcn_dw, mem_iss_unit.io.iss_uops[1].bits.fcn_dw connect mem_exe_unit_1.io_iss_uop.bits.frs3_en, mem_iss_unit.io.iss_uops[1].bits.frs3_en connect mem_exe_unit_1.io_iss_uop.bits.lrs2_rtype, mem_iss_unit.io.iss_uops[1].bits.lrs2_rtype connect mem_exe_unit_1.io_iss_uop.bits.lrs1_rtype, mem_iss_unit.io.iss_uops[1].bits.lrs1_rtype connect mem_exe_unit_1.io_iss_uop.bits.dst_rtype, mem_iss_unit.io.iss_uops[1].bits.dst_rtype connect mem_exe_unit_1.io_iss_uop.bits.lrs3, mem_iss_unit.io.iss_uops[1].bits.lrs3 connect mem_exe_unit_1.io_iss_uop.bits.lrs2, mem_iss_unit.io.iss_uops[1].bits.lrs2 connect mem_exe_unit_1.io_iss_uop.bits.lrs1, mem_iss_unit.io.iss_uops[1].bits.lrs1 connect mem_exe_unit_1.io_iss_uop.bits.ldst, mem_iss_unit.io.iss_uops[1].bits.ldst connect mem_exe_unit_1.io_iss_uop.bits.ldst_is_rs1, mem_iss_unit.io.iss_uops[1].bits.ldst_is_rs1 connect mem_exe_unit_1.io_iss_uop.bits.csr_cmd, mem_iss_unit.io.iss_uops[1].bits.csr_cmd connect mem_exe_unit_1.io_iss_uop.bits.flush_on_commit, mem_iss_unit.io.iss_uops[1].bits.flush_on_commit connect mem_exe_unit_1.io_iss_uop.bits.is_unique, mem_iss_unit.io.iss_uops[1].bits.is_unique connect mem_exe_unit_1.io_iss_uop.bits.uses_stq, mem_iss_unit.io.iss_uops[1].bits.uses_stq connect mem_exe_unit_1.io_iss_uop.bits.uses_ldq, mem_iss_unit.io.iss_uops[1].bits.uses_ldq connect mem_exe_unit_1.io_iss_uop.bits.mem_signed, mem_iss_unit.io.iss_uops[1].bits.mem_signed connect mem_exe_unit_1.io_iss_uop.bits.mem_size, mem_iss_unit.io.iss_uops[1].bits.mem_size connect mem_exe_unit_1.io_iss_uop.bits.mem_cmd, mem_iss_unit.io.iss_uops[1].bits.mem_cmd connect mem_exe_unit_1.io_iss_uop.bits.exc_cause, mem_iss_unit.io.iss_uops[1].bits.exc_cause connect mem_exe_unit_1.io_iss_uop.bits.exception, mem_iss_unit.io.iss_uops[1].bits.exception connect mem_exe_unit_1.io_iss_uop.bits.stale_pdst, mem_iss_unit.io.iss_uops[1].bits.stale_pdst connect mem_exe_unit_1.io_iss_uop.bits.ppred_busy, mem_iss_unit.io.iss_uops[1].bits.ppred_busy connect mem_exe_unit_1.io_iss_uop.bits.prs3_busy, mem_iss_unit.io.iss_uops[1].bits.prs3_busy connect mem_exe_unit_1.io_iss_uop.bits.prs2_busy, mem_iss_unit.io.iss_uops[1].bits.prs2_busy connect mem_exe_unit_1.io_iss_uop.bits.prs1_busy, mem_iss_unit.io.iss_uops[1].bits.prs1_busy connect mem_exe_unit_1.io_iss_uop.bits.ppred, mem_iss_unit.io.iss_uops[1].bits.ppred connect mem_exe_unit_1.io_iss_uop.bits.prs3, mem_iss_unit.io.iss_uops[1].bits.prs3 connect mem_exe_unit_1.io_iss_uop.bits.prs2, mem_iss_unit.io.iss_uops[1].bits.prs2 connect mem_exe_unit_1.io_iss_uop.bits.prs1, mem_iss_unit.io.iss_uops[1].bits.prs1 connect mem_exe_unit_1.io_iss_uop.bits.pdst, mem_iss_unit.io.iss_uops[1].bits.pdst connect mem_exe_unit_1.io_iss_uop.bits.rxq_idx, mem_iss_unit.io.iss_uops[1].bits.rxq_idx connect mem_exe_unit_1.io_iss_uop.bits.stq_idx, mem_iss_unit.io.iss_uops[1].bits.stq_idx connect mem_exe_unit_1.io_iss_uop.bits.ldq_idx, mem_iss_unit.io.iss_uops[1].bits.ldq_idx connect mem_exe_unit_1.io_iss_uop.bits.rob_idx, mem_iss_unit.io.iss_uops[1].bits.rob_idx connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.vec, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.vec connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.wflags, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.wflags connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.sqrt, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.sqrt connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.div, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.div connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.fma, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.fma connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.fastpipe, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.fastpipe connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.toint, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.toint connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.fromint, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.fromint connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.typeTagOut, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.typeTagOut connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.typeTagIn, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.typeTagIn connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.swap23, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.swap23 connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.swap12, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.swap12 connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.ren3, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.ren3 connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.ren2, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.ren2 connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.ren1, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.ren1 connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.wen, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.wen connect mem_exe_unit_1.io_iss_uop.bits.fp_ctrl.ldst, mem_iss_unit.io.iss_uops[1].bits.fp_ctrl.ldst connect mem_exe_unit_1.io_iss_uop.bits.op2_sel, mem_iss_unit.io.iss_uops[1].bits.op2_sel connect mem_exe_unit_1.io_iss_uop.bits.op1_sel, mem_iss_unit.io.iss_uops[1].bits.op1_sel connect mem_exe_unit_1.io_iss_uop.bits.imm_packed, mem_iss_unit.io.iss_uops[1].bits.imm_packed connect mem_exe_unit_1.io_iss_uop.bits.pimm, mem_iss_unit.io.iss_uops[1].bits.pimm connect mem_exe_unit_1.io_iss_uop.bits.imm_sel, mem_iss_unit.io.iss_uops[1].bits.imm_sel connect mem_exe_unit_1.io_iss_uop.bits.imm_rename, mem_iss_unit.io.iss_uops[1].bits.imm_rename connect mem_exe_unit_1.io_iss_uop.bits.taken, mem_iss_unit.io.iss_uops[1].bits.taken connect mem_exe_unit_1.io_iss_uop.bits.pc_lob, mem_iss_unit.io.iss_uops[1].bits.pc_lob connect mem_exe_unit_1.io_iss_uop.bits.edge_inst, mem_iss_unit.io.iss_uops[1].bits.edge_inst connect mem_exe_unit_1.io_iss_uop.bits.ftq_idx, mem_iss_unit.io.iss_uops[1].bits.ftq_idx connect mem_exe_unit_1.io_iss_uop.bits.is_mov, mem_iss_unit.io.iss_uops[1].bits.is_mov connect mem_exe_unit_1.io_iss_uop.bits.is_rocc, mem_iss_unit.io.iss_uops[1].bits.is_rocc connect mem_exe_unit_1.io_iss_uop.bits.is_sys_pc2epc, mem_iss_unit.io.iss_uops[1].bits.is_sys_pc2epc connect mem_exe_unit_1.io_iss_uop.bits.is_eret, mem_iss_unit.io.iss_uops[1].bits.is_eret connect mem_exe_unit_1.io_iss_uop.bits.is_amo, mem_iss_unit.io.iss_uops[1].bits.is_amo connect mem_exe_unit_1.io_iss_uop.bits.is_sfence, mem_iss_unit.io.iss_uops[1].bits.is_sfence connect mem_exe_unit_1.io_iss_uop.bits.is_fencei, mem_iss_unit.io.iss_uops[1].bits.is_fencei connect mem_exe_unit_1.io_iss_uop.bits.is_fence, mem_iss_unit.io.iss_uops[1].bits.is_fence connect mem_exe_unit_1.io_iss_uop.bits.is_sfb, mem_iss_unit.io.iss_uops[1].bits.is_sfb connect mem_exe_unit_1.io_iss_uop.bits.br_type, mem_iss_unit.io.iss_uops[1].bits.br_type connect mem_exe_unit_1.io_iss_uop.bits.br_tag, mem_iss_unit.io.iss_uops[1].bits.br_tag connect mem_exe_unit_1.io_iss_uop.bits.br_mask, mem_iss_unit.io.iss_uops[1].bits.br_mask connect mem_exe_unit_1.io_iss_uop.bits.dis_col_sel, mem_iss_unit.io.iss_uops[1].bits.dis_col_sel connect mem_exe_unit_1.io_iss_uop.bits.iw_p3_bypass_hint, mem_iss_unit.io.iss_uops[1].bits.iw_p3_bypass_hint connect mem_exe_unit_1.io_iss_uop.bits.iw_p2_bypass_hint, mem_iss_unit.io.iss_uops[1].bits.iw_p2_bypass_hint connect mem_exe_unit_1.io_iss_uop.bits.iw_p1_bypass_hint, mem_iss_unit.io.iss_uops[1].bits.iw_p1_bypass_hint connect mem_exe_unit_1.io_iss_uop.bits.iw_p2_speculative_child, mem_iss_unit.io.iss_uops[1].bits.iw_p2_speculative_child connect mem_exe_unit_1.io_iss_uop.bits.iw_p1_speculative_child, mem_iss_unit.io.iss_uops[1].bits.iw_p1_speculative_child connect mem_exe_unit_1.io_iss_uop.bits.iw_issued_partial_dgen, mem_iss_unit.io.iss_uops[1].bits.iw_issued_partial_dgen connect mem_exe_unit_1.io_iss_uop.bits.iw_issued_partial_agen, mem_iss_unit.io.iss_uops[1].bits.iw_issued_partial_agen connect mem_exe_unit_1.io_iss_uop.bits.iw_issued, mem_iss_unit.io.iss_uops[1].bits.iw_issued connect mem_exe_unit_1.io_iss_uop.bits.fu_code[0], mem_iss_unit.io.iss_uops[1].bits.fu_code[0] connect mem_exe_unit_1.io_iss_uop.bits.fu_code[1], mem_iss_unit.io.iss_uops[1].bits.fu_code[1] connect mem_exe_unit_1.io_iss_uop.bits.fu_code[2], mem_iss_unit.io.iss_uops[1].bits.fu_code[2] connect mem_exe_unit_1.io_iss_uop.bits.fu_code[3], mem_iss_unit.io.iss_uops[1].bits.fu_code[3] connect mem_exe_unit_1.io_iss_uop.bits.fu_code[4], mem_iss_unit.io.iss_uops[1].bits.fu_code[4] connect mem_exe_unit_1.io_iss_uop.bits.fu_code[5], mem_iss_unit.io.iss_uops[1].bits.fu_code[5] connect mem_exe_unit_1.io_iss_uop.bits.fu_code[6], mem_iss_unit.io.iss_uops[1].bits.fu_code[6] connect mem_exe_unit_1.io_iss_uop.bits.fu_code[7], mem_iss_unit.io.iss_uops[1].bits.fu_code[7] connect mem_exe_unit_1.io_iss_uop.bits.fu_code[8], mem_iss_unit.io.iss_uops[1].bits.fu_code[8] connect mem_exe_unit_1.io_iss_uop.bits.fu_code[9], mem_iss_unit.io.iss_uops[1].bits.fu_code[9] connect mem_exe_unit_1.io_iss_uop.bits.iq_type[0], mem_iss_unit.io.iss_uops[1].bits.iq_type[0] connect mem_exe_unit_1.io_iss_uop.bits.iq_type[1], mem_iss_unit.io.iss_uops[1].bits.iq_type[1] connect mem_exe_unit_1.io_iss_uop.bits.iq_type[2], mem_iss_unit.io.iss_uops[1].bits.iq_type[2] connect mem_exe_unit_1.io_iss_uop.bits.iq_type[3], mem_iss_unit.io.iss_uops[1].bits.iq_type[3] connect mem_exe_unit_1.io_iss_uop.bits.debug_pc, mem_iss_unit.io.iss_uops[1].bits.debug_pc connect mem_exe_unit_1.io_iss_uop.bits.is_rvc, mem_iss_unit.io.iss_uops[1].bits.is_rvc connect mem_exe_unit_1.io_iss_uop.bits.debug_inst, mem_iss_unit.io.iss_uops[1].bits.debug_inst connect mem_exe_unit_1.io_iss_uop.bits.inst, mem_iss_unit.io.iss_uops[1].bits.inst connect mem_exe_unit_1.io_iss_uop.valid, mem_iss_unit.io.iss_uops[1].valid connect alu_exe_unit_0.io_iss_uop.bits.debug_tsrc, alu_iss_unit.io.iss_uops[0].bits.debug_tsrc connect alu_exe_unit_0.io_iss_uop.bits.debug_fsrc, alu_iss_unit.io.iss_uops[0].bits.debug_fsrc connect alu_exe_unit_0.io_iss_uop.bits.bp_xcpt_if, alu_iss_unit.io.iss_uops[0].bits.bp_xcpt_if connect alu_exe_unit_0.io_iss_uop.bits.bp_debug_if, alu_iss_unit.io.iss_uops[0].bits.bp_debug_if connect alu_exe_unit_0.io_iss_uop.bits.xcpt_ma_if, alu_iss_unit.io.iss_uops[0].bits.xcpt_ma_if connect alu_exe_unit_0.io_iss_uop.bits.xcpt_ae_if, alu_iss_unit.io.iss_uops[0].bits.xcpt_ae_if connect alu_exe_unit_0.io_iss_uop.bits.xcpt_pf_if, alu_iss_unit.io.iss_uops[0].bits.xcpt_pf_if connect alu_exe_unit_0.io_iss_uop.bits.fp_typ, alu_iss_unit.io.iss_uops[0].bits.fp_typ connect alu_exe_unit_0.io_iss_uop.bits.fp_rm, alu_iss_unit.io.iss_uops[0].bits.fp_rm connect alu_exe_unit_0.io_iss_uop.bits.fp_val, alu_iss_unit.io.iss_uops[0].bits.fp_val connect alu_exe_unit_0.io_iss_uop.bits.fcn_op, alu_iss_unit.io.iss_uops[0].bits.fcn_op connect alu_exe_unit_0.io_iss_uop.bits.fcn_dw, alu_iss_unit.io.iss_uops[0].bits.fcn_dw connect alu_exe_unit_0.io_iss_uop.bits.frs3_en, alu_iss_unit.io.iss_uops[0].bits.frs3_en connect alu_exe_unit_0.io_iss_uop.bits.lrs2_rtype, alu_iss_unit.io.iss_uops[0].bits.lrs2_rtype connect alu_exe_unit_0.io_iss_uop.bits.lrs1_rtype, alu_iss_unit.io.iss_uops[0].bits.lrs1_rtype connect alu_exe_unit_0.io_iss_uop.bits.dst_rtype, alu_iss_unit.io.iss_uops[0].bits.dst_rtype connect alu_exe_unit_0.io_iss_uop.bits.lrs3, alu_iss_unit.io.iss_uops[0].bits.lrs3 connect alu_exe_unit_0.io_iss_uop.bits.lrs2, alu_iss_unit.io.iss_uops[0].bits.lrs2 connect alu_exe_unit_0.io_iss_uop.bits.lrs1, alu_iss_unit.io.iss_uops[0].bits.lrs1 connect alu_exe_unit_0.io_iss_uop.bits.ldst, alu_iss_unit.io.iss_uops[0].bits.ldst connect alu_exe_unit_0.io_iss_uop.bits.ldst_is_rs1, alu_iss_unit.io.iss_uops[0].bits.ldst_is_rs1 connect alu_exe_unit_0.io_iss_uop.bits.csr_cmd, alu_iss_unit.io.iss_uops[0].bits.csr_cmd connect alu_exe_unit_0.io_iss_uop.bits.flush_on_commit, alu_iss_unit.io.iss_uops[0].bits.flush_on_commit connect alu_exe_unit_0.io_iss_uop.bits.is_unique, alu_iss_unit.io.iss_uops[0].bits.is_unique connect alu_exe_unit_0.io_iss_uop.bits.uses_stq, alu_iss_unit.io.iss_uops[0].bits.uses_stq connect alu_exe_unit_0.io_iss_uop.bits.uses_ldq, alu_iss_unit.io.iss_uops[0].bits.uses_ldq connect alu_exe_unit_0.io_iss_uop.bits.mem_signed, alu_iss_unit.io.iss_uops[0].bits.mem_signed connect alu_exe_unit_0.io_iss_uop.bits.mem_size, alu_iss_unit.io.iss_uops[0].bits.mem_size connect alu_exe_unit_0.io_iss_uop.bits.mem_cmd, alu_iss_unit.io.iss_uops[0].bits.mem_cmd connect alu_exe_unit_0.io_iss_uop.bits.exc_cause, alu_iss_unit.io.iss_uops[0].bits.exc_cause connect alu_exe_unit_0.io_iss_uop.bits.exception, alu_iss_unit.io.iss_uops[0].bits.exception connect alu_exe_unit_0.io_iss_uop.bits.stale_pdst, alu_iss_unit.io.iss_uops[0].bits.stale_pdst connect alu_exe_unit_0.io_iss_uop.bits.ppred_busy, alu_iss_unit.io.iss_uops[0].bits.ppred_busy connect alu_exe_unit_0.io_iss_uop.bits.prs3_busy, alu_iss_unit.io.iss_uops[0].bits.prs3_busy connect alu_exe_unit_0.io_iss_uop.bits.prs2_busy, alu_iss_unit.io.iss_uops[0].bits.prs2_busy connect alu_exe_unit_0.io_iss_uop.bits.prs1_busy, alu_iss_unit.io.iss_uops[0].bits.prs1_busy connect alu_exe_unit_0.io_iss_uop.bits.ppred, alu_iss_unit.io.iss_uops[0].bits.ppred connect alu_exe_unit_0.io_iss_uop.bits.prs3, alu_iss_unit.io.iss_uops[0].bits.prs3 connect alu_exe_unit_0.io_iss_uop.bits.prs2, alu_iss_unit.io.iss_uops[0].bits.prs2 connect alu_exe_unit_0.io_iss_uop.bits.prs1, alu_iss_unit.io.iss_uops[0].bits.prs1 connect alu_exe_unit_0.io_iss_uop.bits.pdst, alu_iss_unit.io.iss_uops[0].bits.pdst connect alu_exe_unit_0.io_iss_uop.bits.rxq_idx, alu_iss_unit.io.iss_uops[0].bits.rxq_idx connect alu_exe_unit_0.io_iss_uop.bits.stq_idx, alu_iss_unit.io.iss_uops[0].bits.stq_idx connect alu_exe_unit_0.io_iss_uop.bits.ldq_idx, alu_iss_unit.io.iss_uops[0].bits.ldq_idx connect alu_exe_unit_0.io_iss_uop.bits.rob_idx, alu_iss_unit.io.iss_uops[0].bits.rob_idx connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.vec, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.vec connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.wflags, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.wflags connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.sqrt, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.sqrt connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.div, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.div connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.fma, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.fma connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.fastpipe, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.fastpipe connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.toint, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.toint connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.fromint, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.fromint connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.typeTagOut, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.typeTagOut connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.typeTagIn, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.typeTagIn connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.swap23, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.swap23 connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.swap12, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.swap12 connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren3, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.ren3 connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren2, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.ren2 connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren1, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.ren1 connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.wen, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.wen connect alu_exe_unit_0.io_iss_uop.bits.fp_ctrl.ldst, alu_iss_unit.io.iss_uops[0].bits.fp_ctrl.ldst connect alu_exe_unit_0.io_iss_uop.bits.op2_sel, alu_iss_unit.io.iss_uops[0].bits.op2_sel connect alu_exe_unit_0.io_iss_uop.bits.op1_sel, alu_iss_unit.io.iss_uops[0].bits.op1_sel connect alu_exe_unit_0.io_iss_uop.bits.imm_packed, alu_iss_unit.io.iss_uops[0].bits.imm_packed connect alu_exe_unit_0.io_iss_uop.bits.pimm, alu_iss_unit.io.iss_uops[0].bits.pimm connect alu_exe_unit_0.io_iss_uop.bits.imm_sel, alu_iss_unit.io.iss_uops[0].bits.imm_sel connect alu_exe_unit_0.io_iss_uop.bits.imm_rename, alu_iss_unit.io.iss_uops[0].bits.imm_rename connect alu_exe_unit_0.io_iss_uop.bits.taken, alu_iss_unit.io.iss_uops[0].bits.taken connect alu_exe_unit_0.io_iss_uop.bits.pc_lob, alu_iss_unit.io.iss_uops[0].bits.pc_lob connect alu_exe_unit_0.io_iss_uop.bits.edge_inst, alu_iss_unit.io.iss_uops[0].bits.edge_inst connect alu_exe_unit_0.io_iss_uop.bits.ftq_idx, alu_iss_unit.io.iss_uops[0].bits.ftq_idx connect alu_exe_unit_0.io_iss_uop.bits.is_mov, alu_iss_unit.io.iss_uops[0].bits.is_mov connect alu_exe_unit_0.io_iss_uop.bits.is_rocc, alu_iss_unit.io.iss_uops[0].bits.is_rocc connect alu_exe_unit_0.io_iss_uop.bits.is_sys_pc2epc, alu_iss_unit.io.iss_uops[0].bits.is_sys_pc2epc connect alu_exe_unit_0.io_iss_uop.bits.is_eret, alu_iss_unit.io.iss_uops[0].bits.is_eret connect alu_exe_unit_0.io_iss_uop.bits.is_amo, alu_iss_unit.io.iss_uops[0].bits.is_amo connect alu_exe_unit_0.io_iss_uop.bits.is_sfence, alu_iss_unit.io.iss_uops[0].bits.is_sfence connect alu_exe_unit_0.io_iss_uop.bits.is_fencei, alu_iss_unit.io.iss_uops[0].bits.is_fencei connect alu_exe_unit_0.io_iss_uop.bits.is_fence, alu_iss_unit.io.iss_uops[0].bits.is_fence connect alu_exe_unit_0.io_iss_uop.bits.is_sfb, alu_iss_unit.io.iss_uops[0].bits.is_sfb connect alu_exe_unit_0.io_iss_uop.bits.br_type, alu_iss_unit.io.iss_uops[0].bits.br_type connect alu_exe_unit_0.io_iss_uop.bits.br_tag, alu_iss_unit.io.iss_uops[0].bits.br_tag connect alu_exe_unit_0.io_iss_uop.bits.br_mask, alu_iss_unit.io.iss_uops[0].bits.br_mask connect alu_exe_unit_0.io_iss_uop.bits.dis_col_sel, alu_iss_unit.io.iss_uops[0].bits.dis_col_sel connect alu_exe_unit_0.io_iss_uop.bits.iw_p3_bypass_hint, alu_iss_unit.io.iss_uops[0].bits.iw_p3_bypass_hint connect alu_exe_unit_0.io_iss_uop.bits.iw_p2_bypass_hint, alu_iss_unit.io.iss_uops[0].bits.iw_p2_bypass_hint connect alu_exe_unit_0.io_iss_uop.bits.iw_p1_bypass_hint, alu_iss_unit.io.iss_uops[0].bits.iw_p1_bypass_hint connect alu_exe_unit_0.io_iss_uop.bits.iw_p2_speculative_child, alu_iss_unit.io.iss_uops[0].bits.iw_p2_speculative_child connect alu_exe_unit_0.io_iss_uop.bits.iw_p1_speculative_child, alu_iss_unit.io.iss_uops[0].bits.iw_p1_speculative_child connect alu_exe_unit_0.io_iss_uop.bits.iw_issued_partial_dgen, alu_iss_unit.io.iss_uops[0].bits.iw_issued_partial_dgen connect alu_exe_unit_0.io_iss_uop.bits.iw_issued_partial_agen, alu_iss_unit.io.iss_uops[0].bits.iw_issued_partial_agen connect alu_exe_unit_0.io_iss_uop.bits.iw_issued, alu_iss_unit.io.iss_uops[0].bits.iw_issued connect alu_exe_unit_0.io_iss_uop.bits.fu_code[0], alu_iss_unit.io.iss_uops[0].bits.fu_code[0] connect alu_exe_unit_0.io_iss_uop.bits.fu_code[1], alu_iss_unit.io.iss_uops[0].bits.fu_code[1] connect alu_exe_unit_0.io_iss_uop.bits.fu_code[2], alu_iss_unit.io.iss_uops[0].bits.fu_code[2] connect alu_exe_unit_0.io_iss_uop.bits.fu_code[3], alu_iss_unit.io.iss_uops[0].bits.fu_code[3] connect alu_exe_unit_0.io_iss_uop.bits.fu_code[4], alu_iss_unit.io.iss_uops[0].bits.fu_code[4] connect alu_exe_unit_0.io_iss_uop.bits.fu_code[5], alu_iss_unit.io.iss_uops[0].bits.fu_code[5] connect alu_exe_unit_0.io_iss_uop.bits.fu_code[6], alu_iss_unit.io.iss_uops[0].bits.fu_code[6] connect alu_exe_unit_0.io_iss_uop.bits.fu_code[7], alu_iss_unit.io.iss_uops[0].bits.fu_code[7] connect alu_exe_unit_0.io_iss_uop.bits.fu_code[8], alu_iss_unit.io.iss_uops[0].bits.fu_code[8] connect alu_exe_unit_0.io_iss_uop.bits.fu_code[9], alu_iss_unit.io.iss_uops[0].bits.fu_code[9] connect alu_exe_unit_0.io_iss_uop.bits.iq_type[0], alu_iss_unit.io.iss_uops[0].bits.iq_type[0] connect alu_exe_unit_0.io_iss_uop.bits.iq_type[1], alu_iss_unit.io.iss_uops[0].bits.iq_type[1] connect alu_exe_unit_0.io_iss_uop.bits.iq_type[2], alu_iss_unit.io.iss_uops[0].bits.iq_type[2] connect alu_exe_unit_0.io_iss_uop.bits.iq_type[3], alu_iss_unit.io.iss_uops[0].bits.iq_type[3] connect alu_exe_unit_0.io_iss_uop.bits.debug_pc, alu_iss_unit.io.iss_uops[0].bits.debug_pc connect alu_exe_unit_0.io_iss_uop.bits.is_rvc, alu_iss_unit.io.iss_uops[0].bits.is_rvc connect alu_exe_unit_0.io_iss_uop.bits.debug_inst, alu_iss_unit.io.iss_uops[0].bits.debug_inst connect alu_exe_unit_0.io_iss_uop.bits.inst, alu_iss_unit.io.iss_uops[0].bits.inst connect alu_exe_unit_0.io_iss_uop.valid, alu_iss_unit.io.iss_uops[0].valid connect alu_exe_unit_1.io_iss_uop.bits.debug_tsrc, alu_iss_unit.io.iss_uops[1].bits.debug_tsrc connect alu_exe_unit_1.io_iss_uop.bits.debug_fsrc, alu_iss_unit.io.iss_uops[1].bits.debug_fsrc connect alu_exe_unit_1.io_iss_uop.bits.bp_xcpt_if, alu_iss_unit.io.iss_uops[1].bits.bp_xcpt_if connect alu_exe_unit_1.io_iss_uop.bits.bp_debug_if, alu_iss_unit.io.iss_uops[1].bits.bp_debug_if connect alu_exe_unit_1.io_iss_uop.bits.xcpt_ma_if, alu_iss_unit.io.iss_uops[1].bits.xcpt_ma_if connect alu_exe_unit_1.io_iss_uop.bits.xcpt_ae_if, alu_iss_unit.io.iss_uops[1].bits.xcpt_ae_if connect alu_exe_unit_1.io_iss_uop.bits.xcpt_pf_if, alu_iss_unit.io.iss_uops[1].bits.xcpt_pf_if connect alu_exe_unit_1.io_iss_uop.bits.fp_typ, alu_iss_unit.io.iss_uops[1].bits.fp_typ connect alu_exe_unit_1.io_iss_uop.bits.fp_rm, alu_iss_unit.io.iss_uops[1].bits.fp_rm connect alu_exe_unit_1.io_iss_uop.bits.fp_val, alu_iss_unit.io.iss_uops[1].bits.fp_val connect alu_exe_unit_1.io_iss_uop.bits.fcn_op, alu_iss_unit.io.iss_uops[1].bits.fcn_op connect alu_exe_unit_1.io_iss_uop.bits.fcn_dw, alu_iss_unit.io.iss_uops[1].bits.fcn_dw connect alu_exe_unit_1.io_iss_uop.bits.frs3_en, alu_iss_unit.io.iss_uops[1].bits.frs3_en connect alu_exe_unit_1.io_iss_uop.bits.lrs2_rtype, alu_iss_unit.io.iss_uops[1].bits.lrs2_rtype connect alu_exe_unit_1.io_iss_uop.bits.lrs1_rtype, alu_iss_unit.io.iss_uops[1].bits.lrs1_rtype connect alu_exe_unit_1.io_iss_uop.bits.dst_rtype, alu_iss_unit.io.iss_uops[1].bits.dst_rtype connect alu_exe_unit_1.io_iss_uop.bits.lrs3, alu_iss_unit.io.iss_uops[1].bits.lrs3 connect alu_exe_unit_1.io_iss_uop.bits.lrs2, alu_iss_unit.io.iss_uops[1].bits.lrs2 connect alu_exe_unit_1.io_iss_uop.bits.lrs1, alu_iss_unit.io.iss_uops[1].bits.lrs1 connect alu_exe_unit_1.io_iss_uop.bits.ldst, alu_iss_unit.io.iss_uops[1].bits.ldst connect alu_exe_unit_1.io_iss_uop.bits.ldst_is_rs1, alu_iss_unit.io.iss_uops[1].bits.ldst_is_rs1 connect alu_exe_unit_1.io_iss_uop.bits.csr_cmd, alu_iss_unit.io.iss_uops[1].bits.csr_cmd connect alu_exe_unit_1.io_iss_uop.bits.flush_on_commit, alu_iss_unit.io.iss_uops[1].bits.flush_on_commit connect alu_exe_unit_1.io_iss_uop.bits.is_unique, alu_iss_unit.io.iss_uops[1].bits.is_unique connect alu_exe_unit_1.io_iss_uop.bits.uses_stq, alu_iss_unit.io.iss_uops[1].bits.uses_stq connect alu_exe_unit_1.io_iss_uop.bits.uses_ldq, alu_iss_unit.io.iss_uops[1].bits.uses_ldq connect alu_exe_unit_1.io_iss_uop.bits.mem_signed, alu_iss_unit.io.iss_uops[1].bits.mem_signed connect alu_exe_unit_1.io_iss_uop.bits.mem_size, alu_iss_unit.io.iss_uops[1].bits.mem_size connect alu_exe_unit_1.io_iss_uop.bits.mem_cmd, alu_iss_unit.io.iss_uops[1].bits.mem_cmd connect alu_exe_unit_1.io_iss_uop.bits.exc_cause, alu_iss_unit.io.iss_uops[1].bits.exc_cause connect alu_exe_unit_1.io_iss_uop.bits.exception, alu_iss_unit.io.iss_uops[1].bits.exception connect alu_exe_unit_1.io_iss_uop.bits.stale_pdst, alu_iss_unit.io.iss_uops[1].bits.stale_pdst connect alu_exe_unit_1.io_iss_uop.bits.ppred_busy, alu_iss_unit.io.iss_uops[1].bits.ppred_busy connect alu_exe_unit_1.io_iss_uop.bits.prs3_busy, alu_iss_unit.io.iss_uops[1].bits.prs3_busy connect alu_exe_unit_1.io_iss_uop.bits.prs2_busy, alu_iss_unit.io.iss_uops[1].bits.prs2_busy connect alu_exe_unit_1.io_iss_uop.bits.prs1_busy, alu_iss_unit.io.iss_uops[1].bits.prs1_busy connect alu_exe_unit_1.io_iss_uop.bits.ppred, alu_iss_unit.io.iss_uops[1].bits.ppred connect alu_exe_unit_1.io_iss_uop.bits.prs3, alu_iss_unit.io.iss_uops[1].bits.prs3 connect alu_exe_unit_1.io_iss_uop.bits.prs2, alu_iss_unit.io.iss_uops[1].bits.prs2 connect alu_exe_unit_1.io_iss_uop.bits.prs1, alu_iss_unit.io.iss_uops[1].bits.prs1 connect alu_exe_unit_1.io_iss_uop.bits.pdst, alu_iss_unit.io.iss_uops[1].bits.pdst connect alu_exe_unit_1.io_iss_uop.bits.rxq_idx, alu_iss_unit.io.iss_uops[1].bits.rxq_idx connect alu_exe_unit_1.io_iss_uop.bits.stq_idx, alu_iss_unit.io.iss_uops[1].bits.stq_idx connect alu_exe_unit_1.io_iss_uop.bits.ldq_idx, alu_iss_unit.io.iss_uops[1].bits.ldq_idx connect alu_exe_unit_1.io_iss_uop.bits.rob_idx, alu_iss_unit.io.iss_uops[1].bits.rob_idx connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.vec, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.vec connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.wflags, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.wflags connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.sqrt, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.sqrt connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.div, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.div connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.fma, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.fma connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.fastpipe, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.fastpipe connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.toint, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.toint connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.fromint, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.fromint connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.typeTagOut, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.typeTagOut connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.typeTagIn, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.typeTagIn connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.swap23, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.swap23 connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.swap12, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.swap12 connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.ren3, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.ren3 connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.ren2, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.ren2 connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.ren1, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.ren1 connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.wen, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.wen connect alu_exe_unit_1.io_iss_uop.bits.fp_ctrl.ldst, alu_iss_unit.io.iss_uops[1].bits.fp_ctrl.ldst connect alu_exe_unit_1.io_iss_uop.bits.op2_sel, alu_iss_unit.io.iss_uops[1].bits.op2_sel connect alu_exe_unit_1.io_iss_uop.bits.op1_sel, alu_iss_unit.io.iss_uops[1].bits.op1_sel connect alu_exe_unit_1.io_iss_uop.bits.imm_packed, alu_iss_unit.io.iss_uops[1].bits.imm_packed connect alu_exe_unit_1.io_iss_uop.bits.pimm, alu_iss_unit.io.iss_uops[1].bits.pimm connect alu_exe_unit_1.io_iss_uop.bits.imm_sel, alu_iss_unit.io.iss_uops[1].bits.imm_sel connect alu_exe_unit_1.io_iss_uop.bits.imm_rename, alu_iss_unit.io.iss_uops[1].bits.imm_rename connect alu_exe_unit_1.io_iss_uop.bits.taken, alu_iss_unit.io.iss_uops[1].bits.taken connect alu_exe_unit_1.io_iss_uop.bits.pc_lob, alu_iss_unit.io.iss_uops[1].bits.pc_lob connect alu_exe_unit_1.io_iss_uop.bits.edge_inst, alu_iss_unit.io.iss_uops[1].bits.edge_inst connect alu_exe_unit_1.io_iss_uop.bits.ftq_idx, alu_iss_unit.io.iss_uops[1].bits.ftq_idx connect alu_exe_unit_1.io_iss_uop.bits.is_mov, alu_iss_unit.io.iss_uops[1].bits.is_mov connect alu_exe_unit_1.io_iss_uop.bits.is_rocc, alu_iss_unit.io.iss_uops[1].bits.is_rocc connect alu_exe_unit_1.io_iss_uop.bits.is_sys_pc2epc, alu_iss_unit.io.iss_uops[1].bits.is_sys_pc2epc connect alu_exe_unit_1.io_iss_uop.bits.is_eret, alu_iss_unit.io.iss_uops[1].bits.is_eret connect alu_exe_unit_1.io_iss_uop.bits.is_amo, alu_iss_unit.io.iss_uops[1].bits.is_amo connect alu_exe_unit_1.io_iss_uop.bits.is_sfence, alu_iss_unit.io.iss_uops[1].bits.is_sfence connect alu_exe_unit_1.io_iss_uop.bits.is_fencei, alu_iss_unit.io.iss_uops[1].bits.is_fencei connect alu_exe_unit_1.io_iss_uop.bits.is_fence, alu_iss_unit.io.iss_uops[1].bits.is_fence connect alu_exe_unit_1.io_iss_uop.bits.is_sfb, alu_iss_unit.io.iss_uops[1].bits.is_sfb connect alu_exe_unit_1.io_iss_uop.bits.br_type, alu_iss_unit.io.iss_uops[1].bits.br_type connect alu_exe_unit_1.io_iss_uop.bits.br_tag, alu_iss_unit.io.iss_uops[1].bits.br_tag connect alu_exe_unit_1.io_iss_uop.bits.br_mask, alu_iss_unit.io.iss_uops[1].bits.br_mask connect alu_exe_unit_1.io_iss_uop.bits.dis_col_sel, alu_iss_unit.io.iss_uops[1].bits.dis_col_sel connect alu_exe_unit_1.io_iss_uop.bits.iw_p3_bypass_hint, alu_iss_unit.io.iss_uops[1].bits.iw_p3_bypass_hint connect alu_exe_unit_1.io_iss_uop.bits.iw_p2_bypass_hint, alu_iss_unit.io.iss_uops[1].bits.iw_p2_bypass_hint connect alu_exe_unit_1.io_iss_uop.bits.iw_p1_bypass_hint, alu_iss_unit.io.iss_uops[1].bits.iw_p1_bypass_hint connect alu_exe_unit_1.io_iss_uop.bits.iw_p2_speculative_child, alu_iss_unit.io.iss_uops[1].bits.iw_p2_speculative_child connect alu_exe_unit_1.io_iss_uop.bits.iw_p1_speculative_child, alu_iss_unit.io.iss_uops[1].bits.iw_p1_speculative_child connect alu_exe_unit_1.io_iss_uop.bits.iw_issued_partial_dgen, alu_iss_unit.io.iss_uops[1].bits.iw_issued_partial_dgen connect alu_exe_unit_1.io_iss_uop.bits.iw_issued_partial_agen, alu_iss_unit.io.iss_uops[1].bits.iw_issued_partial_agen connect alu_exe_unit_1.io_iss_uop.bits.iw_issued, alu_iss_unit.io.iss_uops[1].bits.iw_issued connect alu_exe_unit_1.io_iss_uop.bits.fu_code[0], alu_iss_unit.io.iss_uops[1].bits.fu_code[0] connect alu_exe_unit_1.io_iss_uop.bits.fu_code[1], alu_iss_unit.io.iss_uops[1].bits.fu_code[1] connect alu_exe_unit_1.io_iss_uop.bits.fu_code[2], alu_iss_unit.io.iss_uops[1].bits.fu_code[2] connect alu_exe_unit_1.io_iss_uop.bits.fu_code[3], alu_iss_unit.io.iss_uops[1].bits.fu_code[3] connect alu_exe_unit_1.io_iss_uop.bits.fu_code[4], alu_iss_unit.io.iss_uops[1].bits.fu_code[4] connect alu_exe_unit_1.io_iss_uop.bits.fu_code[5], alu_iss_unit.io.iss_uops[1].bits.fu_code[5] connect alu_exe_unit_1.io_iss_uop.bits.fu_code[6], alu_iss_unit.io.iss_uops[1].bits.fu_code[6] connect alu_exe_unit_1.io_iss_uop.bits.fu_code[7], alu_iss_unit.io.iss_uops[1].bits.fu_code[7] connect alu_exe_unit_1.io_iss_uop.bits.fu_code[8], alu_iss_unit.io.iss_uops[1].bits.fu_code[8] connect alu_exe_unit_1.io_iss_uop.bits.fu_code[9], alu_iss_unit.io.iss_uops[1].bits.fu_code[9] connect alu_exe_unit_1.io_iss_uop.bits.iq_type[0], alu_iss_unit.io.iss_uops[1].bits.iq_type[0] connect alu_exe_unit_1.io_iss_uop.bits.iq_type[1], alu_iss_unit.io.iss_uops[1].bits.iq_type[1] connect alu_exe_unit_1.io_iss_uop.bits.iq_type[2], alu_iss_unit.io.iss_uops[1].bits.iq_type[2] connect alu_exe_unit_1.io_iss_uop.bits.iq_type[3], alu_iss_unit.io.iss_uops[1].bits.iq_type[3] connect alu_exe_unit_1.io_iss_uop.bits.debug_pc, alu_iss_unit.io.iss_uops[1].bits.debug_pc connect alu_exe_unit_1.io_iss_uop.bits.is_rvc, alu_iss_unit.io.iss_uops[1].bits.is_rvc connect alu_exe_unit_1.io_iss_uop.bits.debug_inst, alu_iss_unit.io.iss_uops[1].bits.debug_inst connect alu_exe_unit_1.io_iss_uop.bits.inst, alu_iss_unit.io.iss_uops[1].bits.inst connect alu_exe_unit_1.io_iss_uop.valid, alu_iss_unit.io.iss_uops[1].valid connect unique_exe_unit_0.io_iss_uop.bits.debug_tsrc, unq_iss_unit.io.iss_uops[0].bits.debug_tsrc connect unique_exe_unit_0.io_iss_uop.bits.debug_fsrc, unq_iss_unit.io.iss_uops[0].bits.debug_fsrc connect unique_exe_unit_0.io_iss_uop.bits.bp_xcpt_if, unq_iss_unit.io.iss_uops[0].bits.bp_xcpt_if connect unique_exe_unit_0.io_iss_uop.bits.bp_debug_if, unq_iss_unit.io.iss_uops[0].bits.bp_debug_if connect unique_exe_unit_0.io_iss_uop.bits.xcpt_ma_if, unq_iss_unit.io.iss_uops[0].bits.xcpt_ma_if connect unique_exe_unit_0.io_iss_uop.bits.xcpt_ae_if, unq_iss_unit.io.iss_uops[0].bits.xcpt_ae_if connect unique_exe_unit_0.io_iss_uop.bits.xcpt_pf_if, unq_iss_unit.io.iss_uops[0].bits.xcpt_pf_if connect unique_exe_unit_0.io_iss_uop.bits.fp_typ, unq_iss_unit.io.iss_uops[0].bits.fp_typ connect unique_exe_unit_0.io_iss_uop.bits.fp_rm, unq_iss_unit.io.iss_uops[0].bits.fp_rm connect unique_exe_unit_0.io_iss_uop.bits.fp_val, unq_iss_unit.io.iss_uops[0].bits.fp_val connect unique_exe_unit_0.io_iss_uop.bits.fcn_op, unq_iss_unit.io.iss_uops[0].bits.fcn_op connect unique_exe_unit_0.io_iss_uop.bits.fcn_dw, unq_iss_unit.io.iss_uops[0].bits.fcn_dw connect unique_exe_unit_0.io_iss_uop.bits.frs3_en, unq_iss_unit.io.iss_uops[0].bits.frs3_en connect unique_exe_unit_0.io_iss_uop.bits.lrs2_rtype, unq_iss_unit.io.iss_uops[0].bits.lrs2_rtype connect unique_exe_unit_0.io_iss_uop.bits.lrs1_rtype, unq_iss_unit.io.iss_uops[0].bits.lrs1_rtype connect unique_exe_unit_0.io_iss_uop.bits.dst_rtype, unq_iss_unit.io.iss_uops[0].bits.dst_rtype connect unique_exe_unit_0.io_iss_uop.bits.lrs3, unq_iss_unit.io.iss_uops[0].bits.lrs3 connect unique_exe_unit_0.io_iss_uop.bits.lrs2, unq_iss_unit.io.iss_uops[0].bits.lrs2 connect unique_exe_unit_0.io_iss_uop.bits.lrs1, unq_iss_unit.io.iss_uops[0].bits.lrs1 connect unique_exe_unit_0.io_iss_uop.bits.ldst, unq_iss_unit.io.iss_uops[0].bits.ldst connect unique_exe_unit_0.io_iss_uop.bits.ldst_is_rs1, unq_iss_unit.io.iss_uops[0].bits.ldst_is_rs1 connect unique_exe_unit_0.io_iss_uop.bits.csr_cmd, unq_iss_unit.io.iss_uops[0].bits.csr_cmd connect unique_exe_unit_0.io_iss_uop.bits.flush_on_commit, unq_iss_unit.io.iss_uops[0].bits.flush_on_commit connect unique_exe_unit_0.io_iss_uop.bits.is_unique, unq_iss_unit.io.iss_uops[0].bits.is_unique connect unique_exe_unit_0.io_iss_uop.bits.uses_stq, unq_iss_unit.io.iss_uops[0].bits.uses_stq connect unique_exe_unit_0.io_iss_uop.bits.uses_ldq, unq_iss_unit.io.iss_uops[0].bits.uses_ldq connect unique_exe_unit_0.io_iss_uop.bits.mem_signed, unq_iss_unit.io.iss_uops[0].bits.mem_signed connect unique_exe_unit_0.io_iss_uop.bits.mem_size, unq_iss_unit.io.iss_uops[0].bits.mem_size connect unique_exe_unit_0.io_iss_uop.bits.mem_cmd, unq_iss_unit.io.iss_uops[0].bits.mem_cmd connect unique_exe_unit_0.io_iss_uop.bits.exc_cause, unq_iss_unit.io.iss_uops[0].bits.exc_cause connect unique_exe_unit_0.io_iss_uop.bits.exception, unq_iss_unit.io.iss_uops[0].bits.exception connect unique_exe_unit_0.io_iss_uop.bits.stale_pdst, unq_iss_unit.io.iss_uops[0].bits.stale_pdst connect unique_exe_unit_0.io_iss_uop.bits.ppred_busy, unq_iss_unit.io.iss_uops[0].bits.ppred_busy connect unique_exe_unit_0.io_iss_uop.bits.prs3_busy, unq_iss_unit.io.iss_uops[0].bits.prs3_busy connect unique_exe_unit_0.io_iss_uop.bits.prs2_busy, unq_iss_unit.io.iss_uops[0].bits.prs2_busy connect unique_exe_unit_0.io_iss_uop.bits.prs1_busy, unq_iss_unit.io.iss_uops[0].bits.prs1_busy connect unique_exe_unit_0.io_iss_uop.bits.ppred, unq_iss_unit.io.iss_uops[0].bits.ppred connect unique_exe_unit_0.io_iss_uop.bits.prs3, unq_iss_unit.io.iss_uops[0].bits.prs3 connect unique_exe_unit_0.io_iss_uop.bits.prs2, unq_iss_unit.io.iss_uops[0].bits.prs2 connect unique_exe_unit_0.io_iss_uop.bits.prs1, unq_iss_unit.io.iss_uops[0].bits.prs1 connect unique_exe_unit_0.io_iss_uop.bits.pdst, unq_iss_unit.io.iss_uops[0].bits.pdst connect unique_exe_unit_0.io_iss_uop.bits.rxq_idx, unq_iss_unit.io.iss_uops[0].bits.rxq_idx connect unique_exe_unit_0.io_iss_uop.bits.stq_idx, unq_iss_unit.io.iss_uops[0].bits.stq_idx connect unique_exe_unit_0.io_iss_uop.bits.ldq_idx, unq_iss_unit.io.iss_uops[0].bits.ldq_idx connect unique_exe_unit_0.io_iss_uop.bits.rob_idx, unq_iss_unit.io.iss_uops[0].bits.rob_idx connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.vec, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.vec connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.wflags, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.wflags connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.sqrt, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.sqrt connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.div, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.div connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.fma, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.fma connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.fastpipe, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.fastpipe connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.toint, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.toint connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.fromint, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.fromint connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.typeTagOut, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.typeTagOut connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.typeTagIn, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.typeTagIn connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.swap23, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.swap23 connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.swap12, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.swap12 connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren3, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.ren3 connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren2, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.ren2 connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.ren1, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.ren1 connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.wen, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.wen connect unique_exe_unit_0.io_iss_uop.bits.fp_ctrl.ldst, unq_iss_unit.io.iss_uops[0].bits.fp_ctrl.ldst connect unique_exe_unit_0.io_iss_uop.bits.op2_sel, unq_iss_unit.io.iss_uops[0].bits.op2_sel connect unique_exe_unit_0.io_iss_uop.bits.op1_sel, unq_iss_unit.io.iss_uops[0].bits.op1_sel connect unique_exe_unit_0.io_iss_uop.bits.imm_packed, unq_iss_unit.io.iss_uops[0].bits.imm_packed connect unique_exe_unit_0.io_iss_uop.bits.pimm, unq_iss_unit.io.iss_uops[0].bits.pimm connect unique_exe_unit_0.io_iss_uop.bits.imm_sel, unq_iss_unit.io.iss_uops[0].bits.imm_sel connect unique_exe_unit_0.io_iss_uop.bits.imm_rename, unq_iss_unit.io.iss_uops[0].bits.imm_rename connect unique_exe_unit_0.io_iss_uop.bits.taken, unq_iss_unit.io.iss_uops[0].bits.taken connect unique_exe_unit_0.io_iss_uop.bits.pc_lob, unq_iss_unit.io.iss_uops[0].bits.pc_lob connect unique_exe_unit_0.io_iss_uop.bits.edge_inst, unq_iss_unit.io.iss_uops[0].bits.edge_inst connect unique_exe_unit_0.io_iss_uop.bits.ftq_idx, unq_iss_unit.io.iss_uops[0].bits.ftq_idx connect unique_exe_unit_0.io_iss_uop.bits.is_mov, unq_iss_unit.io.iss_uops[0].bits.is_mov connect unique_exe_unit_0.io_iss_uop.bits.is_rocc, unq_iss_unit.io.iss_uops[0].bits.is_rocc connect unique_exe_unit_0.io_iss_uop.bits.is_sys_pc2epc, unq_iss_unit.io.iss_uops[0].bits.is_sys_pc2epc connect unique_exe_unit_0.io_iss_uop.bits.is_eret, unq_iss_unit.io.iss_uops[0].bits.is_eret connect unique_exe_unit_0.io_iss_uop.bits.is_amo, unq_iss_unit.io.iss_uops[0].bits.is_amo connect unique_exe_unit_0.io_iss_uop.bits.is_sfence, unq_iss_unit.io.iss_uops[0].bits.is_sfence connect unique_exe_unit_0.io_iss_uop.bits.is_fencei, unq_iss_unit.io.iss_uops[0].bits.is_fencei connect unique_exe_unit_0.io_iss_uop.bits.is_fence, unq_iss_unit.io.iss_uops[0].bits.is_fence connect unique_exe_unit_0.io_iss_uop.bits.is_sfb, unq_iss_unit.io.iss_uops[0].bits.is_sfb connect unique_exe_unit_0.io_iss_uop.bits.br_type, unq_iss_unit.io.iss_uops[0].bits.br_type connect unique_exe_unit_0.io_iss_uop.bits.br_tag, unq_iss_unit.io.iss_uops[0].bits.br_tag connect unique_exe_unit_0.io_iss_uop.bits.br_mask, unq_iss_unit.io.iss_uops[0].bits.br_mask connect unique_exe_unit_0.io_iss_uop.bits.dis_col_sel, unq_iss_unit.io.iss_uops[0].bits.dis_col_sel connect unique_exe_unit_0.io_iss_uop.bits.iw_p3_bypass_hint, unq_iss_unit.io.iss_uops[0].bits.iw_p3_bypass_hint connect unique_exe_unit_0.io_iss_uop.bits.iw_p2_bypass_hint, unq_iss_unit.io.iss_uops[0].bits.iw_p2_bypass_hint connect unique_exe_unit_0.io_iss_uop.bits.iw_p1_bypass_hint, unq_iss_unit.io.iss_uops[0].bits.iw_p1_bypass_hint connect unique_exe_unit_0.io_iss_uop.bits.iw_p2_speculative_child, unq_iss_unit.io.iss_uops[0].bits.iw_p2_speculative_child connect unique_exe_unit_0.io_iss_uop.bits.iw_p1_speculative_child, unq_iss_unit.io.iss_uops[0].bits.iw_p1_speculative_child connect unique_exe_unit_0.io_iss_uop.bits.iw_issued_partial_dgen, unq_iss_unit.io.iss_uops[0].bits.iw_issued_partial_dgen connect unique_exe_unit_0.io_iss_uop.bits.iw_issued_partial_agen, unq_iss_unit.io.iss_uops[0].bits.iw_issued_partial_agen connect unique_exe_unit_0.io_iss_uop.bits.iw_issued, unq_iss_unit.io.iss_uops[0].bits.iw_issued connect unique_exe_unit_0.io_iss_uop.bits.fu_code[0], unq_iss_unit.io.iss_uops[0].bits.fu_code[0] connect unique_exe_unit_0.io_iss_uop.bits.fu_code[1], unq_iss_unit.io.iss_uops[0].bits.fu_code[1] connect unique_exe_unit_0.io_iss_uop.bits.fu_code[2], unq_iss_unit.io.iss_uops[0].bits.fu_code[2] connect unique_exe_unit_0.io_iss_uop.bits.fu_code[3], unq_iss_unit.io.iss_uops[0].bits.fu_code[3] connect unique_exe_unit_0.io_iss_uop.bits.fu_code[4], unq_iss_unit.io.iss_uops[0].bits.fu_code[4] connect unique_exe_unit_0.io_iss_uop.bits.fu_code[5], unq_iss_unit.io.iss_uops[0].bits.fu_code[5] connect unique_exe_unit_0.io_iss_uop.bits.fu_code[6], unq_iss_unit.io.iss_uops[0].bits.fu_code[6] connect unique_exe_unit_0.io_iss_uop.bits.fu_code[7], unq_iss_unit.io.iss_uops[0].bits.fu_code[7] connect unique_exe_unit_0.io_iss_uop.bits.fu_code[8], unq_iss_unit.io.iss_uops[0].bits.fu_code[8] connect unique_exe_unit_0.io_iss_uop.bits.fu_code[9], unq_iss_unit.io.iss_uops[0].bits.fu_code[9] connect unique_exe_unit_0.io_iss_uop.bits.iq_type[0], unq_iss_unit.io.iss_uops[0].bits.iq_type[0] connect unique_exe_unit_0.io_iss_uop.bits.iq_type[1], unq_iss_unit.io.iss_uops[0].bits.iq_type[1] connect unique_exe_unit_0.io_iss_uop.bits.iq_type[2], unq_iss_unit.io.iss_uops[0].bits.iq_type[2] connect unique_exe_unit_0.io_iss_uop.bits.iq_type[3], unq_iss_unit.io.iss_uops[0].bits.iq_type[3] connect unique_exe_unit_0.io_iss_uop.bits.debug_pc, unq_iss_unit.io.iss_uops[0].bits.debug_pc connect unique_exe_unit_0.io_iss_uop.bits.is_rvc, unq_iss_unit.io.iss_uops[0].bits.is_rvc connect unique_exe_unit_0.io_iss_uop.bits.debug_inst, unq_iss_unit.io.iss_uops[0].bits.debug_inst connect unique_exe_unit_0.io_iss_uop.bits.inst, unq_iss_unit.io.iss_uops[0].bits.inst connect unique_exe_unit_0.io_iss_uop.valid, unq_iss_unit.io.iss_uops[0].valid connect iregfile.io.arb_read_reqs[0], alu_exe_unit_0.io_arb_irf_reqs[0] connect iregfile.io.arb_read_reqs[1], alu_exe_unit_0.io_arb_irf_reqs[1] connect immregfile.io.arb_read_reqs[0], alu_exe_unit_0.io_arb_immrf_req connect alu_exe_unit_0.io_arb_rebusys[0].bits.rebusy, io.lsu.iwakeups[0].bits.rebusy connect alu_exe_unit_0.io_arb_rebusys[0].bits.speculative_mask, io.lsu.iwakeups[0].bits.speculative_mask connect alu_exe_unit_0.io_arb_rebusys[0].bits.bypassable, io.lsu.iwakeups[0].bits.bypassable connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_tsrc, io.lsu.iwakeups[0].bits.uop.debug_tsrc connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_fsrc, io.lsu.iwakeups[0].bits.uop.debug_fsrc connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.bp_xcpt_if, io.lsu.iwakeups[0].bits.uop.bp_xcpt_if connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.bp_debug_if, io.lsu.iwakeups[0].bits.uop.bp_debug_if connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.xcpt_ma_if, io.lsu.iwakeups[0].bits.uop.xcpt_ma_if connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.xcpt_ae_if, io.lsu.iwakeups[0].bits.uop.xcpt_ae_if connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.xcpt_pf_if, io.lsu.iwakeups[0].bits.uop.xcpt_pf_if connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_typ, io.lsu.iwakeups[0].bits.uop.fp_typ connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_rm, io.lsu.iwakeups[0].bits.uop.fp_rm connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_val, io.lsu.iwakeups[0].bits.uop.fp_val connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fcn_op, io.lsu.iwakeups[0].bits.uop.fcn_op connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fcn_dw, io.lsu.iwakeups[0].bits.uop.fcn_dw connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.frs3_en, io.lsu.iwakeups[0].bits.uop.frs3_en connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs2_rtype, io.lsu.iwakeups[0].bits.uop.lrs2_rtype connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs1_rtype, io.lsu.iwakeups[0].bits.uop.lrs1_rtype connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.dst_rtype, io.lsu.iwakeups[0].bits.uop.dst_rtype connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs3, io.lsu.iwakeups[0].bits.uop.lrs3 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs2, io.lsu.iwakeups[0].bits.uop.lrs2 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs1, io.lsu.iwakeups[0].bits.uop.lrs1 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.ldst, io.lsu.iwakeups[0].bits.uop.ldst connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.ldst_is_rs1, io.lsu.iwakeups[0].bits.uop.ldst_is_rs1 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.csr_cmd, io.lsu.iwakeups[0].bits.uop.csr_cmd connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.flush_on_commit, io.lsu.iwakeups[0].bits.uop.flush_on_commit connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.is_unique, io.lsu.iwakeups[0].bits.uop.is_unique connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.uses_stq, io.lsu.iwakeups[0].bits.uop.uses_stq connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.uses_ldq, io.lsu.iwakeups[0].bits.uop.uses_ldq connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.mem_signed, io.lsu.iwakeups[0].bits.uop.mem_signed connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.mem_size, io.lsu.iwakeups[0].bits.uop.mem_size connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.mem_cmd, io.lsu.iwakeups[0].bits.uop.mem_cmd connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.exc_cause, io.lsu.iwakeups[0].bits.uop.exc_cause connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.exception, io.lsu.iwakeups[0].bits.uop.exception connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.stale_pdst, io.lsu.iwakeups[0].bits.uop.stale_pdst connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.ppred_busy, io.lsu.iwakeups[0].bits.uop.ppred_busy connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.prs3_busy, io.lsu.iwakeups[0].bits.uop.prs3_busy connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.prs2_busy, io.lsu.iwakeups[0].bits.uop.prs2_busy connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.prs1_busy, io.lsu.iwakeups[0].bits.uop.prs1_busy connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.ppred, io.lsu.iwakeups[0].bits.uop.ppred connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.prs3, io.lsu.iwakeups[0].bits.uop.prs3 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.prs2, io.lsu.iwakeups[0].bits.uop.prs2 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.prs1, io.lsu.iwakeups[0].bits.uop.prs1 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.pdst, io.lsu.iwakeups[0].bits.uop.pdst connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.rxq_idx, io.lsu.iwakeups[0].bits.uop.rxq_idx connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.stq_idx, io.lsu.iwakeups[0].bits.uop.stq_idx connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.ldq_idx, io.lsu.iwakeups[0].bits.uop.ldq_idx connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.rob_idx, io.lsu.iwakeups[0].bits.uop.rob_idx connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.vec, io.lsu.iwakeups[0].bits.uop.fp_ctrl.vec connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.wflags, io.lsu.iwakeups[0].bits.uop.fp_ctrl.wflags connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.sqrt, io.lsu.iwakeups[0].bits.uop.fp_ctrl.sqrt connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.div, io.lsu.iwakeups[0].bits.uop.fp_ctrl.div connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.fma, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fma connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.fastpipe, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fastpipe connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.toint, io.lsu.iwakeups[0].bits.uop.fp_ctrl.toint connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.fromint, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fromint connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.typeTagOut, io.lsu.iwakeups[0].bits.uop.fp_ctrl.typeTagOut connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.typeTagIn, io.lsu.iwakeups[0].bits.uop.fp_ctrl.typeTagIn connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.swap23, io.lsu.iwakeups[0].bits.uop.fp_ctrl.swap23 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.swap12, io.lsu.iwakeups[0].bits.uop.fp_ctrl.swap12 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ren3, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren3 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ren2, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren2 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ren1, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren1 connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.wen, io.lsu.iwakeups[0].bits.uop.fp_ctrl.wen connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ldst, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ldst connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.op2_sel, io.lsu.iwakeups[0].bits.uop.op2_sel connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.op1_sel, io.lsu.iwakeups[0].bits.uop.op1_sel connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.imm_packed, io.lsu.iwakeups[0].bits.uop.imm_packed connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.pimm, io.lsu.iwakeups[0].bits.uop.pimm connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.imm_sel, io.lsu.iwakeups[0].bits.uop.imm_sel connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.imm_rename, io.lsu.iwakeups[0].bits.uop.imm_rename connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.taken, io.lsu.iwakeups[0].bits.uop.taken connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.pc_lob, io.lsu.iwakeups[0].bits.uop.pc_lob connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.edge_inst, io.lsu.iwakeups[0].bits.uop.edge_inst connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.ftq_idx, io.lsu.iwakeups[0].bits.uop.ftq_idx connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.is_mov, io.lsu.iwakeups[0].bits.uop.is_mov connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.is_rocc, io.lsu.iwakeups[0].bits.uop.is_rocc connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.is_sys_pc2epc, io.lsu.iwakeups[0].bits.uop.is_sys_pc2epc connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.is_eret, io.lsu.iwakeups[0].bits.uop.is_eret connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.is_amo, io.lsu.iwakeups[0].bits.uop.is_amo connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.is_sfence, io.lsu.iwakeups[0].bits.uop.is_sfence connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.is_fencei, io.lsu.iwakeups[0].bits.uop.is_fencei connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.is_fence, io.lsu.iwakeups[0].bits.uop.is_fence connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.is_sfb, io.lsu.iwakeups[0].bits.uop.is_sfb connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.br_type, io.lsu.iwakeups[0].bits.uop.br_type connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.br_tag, io.lsu.iwakeups[0].bits.uop.br_tag connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.br_mask, io.lsu.iwakeups[0].bits.uop.br_mask connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.dis_col_sel, io.lsu.iwakeups[0].bits.uop.dis_col_sel connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p3_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p3_bypass_hint connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p2_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p2_bypass_hint connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p1_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p1_bypass_hint connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p2_speculative_child, io.lsu.iwakeups[0].bits.uop.iw_p2_speculative_child connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p1_speculative_child, io.lsu.iwakeups[0].bits.uop.iw_p1_speculative_child connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_issued_partial_dgen, io.lsu.iwakeups[0].bits.uop.iw_issued_partial_dgen connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_issued_partial_agen, io.lsu.iwakeups[0].bits.uop.iw_issued_partial_agen connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_issued, io.lsu.iwakeups[0].bits.uop.iw_issued connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[0], io.lsu.iwakeups[0].bits.uop.fu_code[0] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[1], io.lsu.iwakeups[0].bits.uop.fu_code[1] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[2], io.lsu.iwakeups[0].bits.uop.fu_code[2] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[3], io.lsu.iwakeups[0].bits.uop.fu_code[3] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[4], io.lsu.iwakeups[0].bits.uop.fu_code[4] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[5], io.lsu.iwakeups[0].bits.uop.fu_code[5] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[6], io.lsu.iwakeups[0].bits.uop.fu_code[6] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[7], io.lsu.iwakeups[0].bits.uop.fu_code[7] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[8], io.lsu.iwakeups[0].bits.uop.fu_code[8] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[9], io.lsu.iwakeups[0].bits.uop.fu_code[9] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[0], io.lsu.iwakeups[0].bits.uop.iq_type[0] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[1], io.lsu.iwakeups[0].bits.uop.iq_type[1] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[2], io.lsu.iwakeups[0].bits.uop.iq_type[2] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[3], io.lsu.iwakeups[0].bits.uop.iq_type[3] connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_pc, io.lsu.iwakeups[0].bits.uop.debug_pc connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.is_rvc, io.lsu.iwakeups[0].bits.uop.is_rvc connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_inst, io.lsu.iwakeups[0].bits.uop.debug_inst connect alu_exe_unit_0.io_arb_rebusys[0].bits.uop.inst, io.lsu.iwakeups[0].bits.uop.inst connect alu_exe_unit_0.io_arb_rebusys[0].valid, io.lsu.iwakeups[0].valid connect iregfile.io.arb_read_reqs[2], alu_exe_unit_1.io_arb_irf_reqs[0] connect iregfile.io.arb_read_reqs[3], alu_exe_unit_1.io_arb_irf_reqs[1] connect immregfile.io.arb_read_reqs[1], alu_exe_unit_1.io_arb_immrf_req connect alu_exe_unit_1.io_arb_rebusys[0].bits.rebusy, io.lsu.iwakeups[0].bits.rebusy connect alu_exe_unit_1.io_arb_rebusys[0].bits.speculative_mask, io.lsu.iwakeups[0].bits.speculative_mask connect alu_exe_unit_1.io_arb_rebusys[0].bits.bypassable, io.lsu.iwakeups[0].bits.bypassable connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.debug_tsrc, io.lsu.iwakeups[0].bits.uop.debug_tsrc connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.debug_fsrc, io.lsu.iwakeups[0].bits.uop.debug_fsrc connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.bp_xcpt_if, io.lsu.iwakeups[0].bits.uop.bp_xcpt_if connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.bp_debug_if, io.lsu.iwakeups[0].bits.uop.bp_debug_if connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.xcpt_ma_if, io.lsu.iwakeups[0].bits.uop.xcpt_ma_if connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.xcpt_ae_if, io.lsu.iwakeups[0].bits.uop.xcpt_ae_if connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.xcpt_pf_if, io.lsu.iwakeups[0].bits.uop.xcpt_pf_if connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_typ, io.lsu.iwakeups[0].bits.uop.fp_typ connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_rm, io.lsu.iwakeups[0].bits.uop.fp_rm connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_val, io.lsu.iwakeups[0].bits.uop.fp_val connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fcn_op, io.lsu.iwakeups[0].bits.uop.fcn_op connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fcn_dw, io.lsu.iwakeups[0].bits.uop.fcn_dw connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.frs3_en, io.lsu.iwakeups[0].bits.uop.frs3_en connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.lrs2_rtype, io.lsu.iwakeups[0].bits.uop.lrs2_rtype connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.lrs1_rtype, io.lsu.iwakeups[0].bits.uop.lrs1_rtype connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.dst_rtype, io.lsu.iwakeups[0].bits.uop.dst_rtype connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.lrs3, io.lsu.iwakeups[0].bits.uop.lrs3 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.lrs2, io.lsu.iwakeups[0].bits.uop.lrs2 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.lrs1, io.lsu.iwakeups[0].bits.uop.lrs1 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.ldst, io.lsu.iwakeups[0].bits.uop.ldst connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.ldst_is_rs1, io.lsu.iwakeups[0].bits.uop.ldst_is_rs1 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.csr_cmd, io.lsu.iwakeups[0].bits.uop.csr_cmd connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.flush_on_commit, io.lsu.iwakeups[0].bits.uop.flush_on_commit connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.is_unique, io.lsu.iwakeups[0].bits.uop.is_unique connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.uses_stq, io.lsu.iwakeups[0].bits.uop.uses_stq connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.uses_ldq, io.lsu.iwakeups[0].bits.uop.uses_ldq connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.mem_signed, io.lsu.iwakeups[0].bits.uop.mem_signed connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.mem_size, io.lsu.iwakeups[0].bits.uop.mem_size connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.mem_cmd, io.lsu.iwakeups[0].bits.uop.mem_cmd connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.exc_cause, io.lsu.iwakeups[0].bits.uop.exc_cause connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.exception, io.lsu.iwakeups[0].bits.uop.exception connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.stale_pdst, io.lsu.iwakeups[0].bits.uop.stale_pdst connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.ppred_busy, io.lsu.iwakeups[0].bits.uop.ppred_busy connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.prs3_busy, io.lsu.iwakeups[0].bits.uop.prs3_busy connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.prs2_busy, io.lsu.iwakeups[0].bits.uop.prs2_busy connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.prs1_busy, io.lsu.iwakeups[0].bits.uop.prs1_busy connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.ppred, io.lsu.iwakeups[0].bits.uop.ppred connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.prs3, io.lsu.iwakeups[0].bits.uop.prs3 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.prs2, io.lsu.iwakeups[0].bits.uop.prs2 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.prs1, io.lsu.iwakeups[0].bits.uop.prs1 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.pdst, io.lsu.iwakeups[0].bits.uop.pdst connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.rxq_idx, io.lsu.iwakeups[0].bits.uop.rxq_idx connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.stq_idx, io.lsu.iwakeups[0].bits.uop.stq_idx connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.ldq_idx, io.lsu.iwakeups[0].bits.uop.ldq_idx connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.rob_idx, io.lsu.iwakeups[0].bits.uop.rob_idx connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.vec, io.lsu.iwakeups[0].bits.uop.fp_ctrl.vec connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.wflags, io.lsu.iwakeups[0].bits.uop.fp_ctrl.wflags connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.sqrt, io.lsu.iwakeups[0].bits.uop.fp_ctrl.sqrt connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.div, io.lsu.iwakeups[0].bits.uop.fp_ctrl.div connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.fma, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fma connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.fastpipe, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fastpipe connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.toint, io.lsu.iwakeups[0].bits.uop.fp_ctrl.toint connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.fromint, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fromint connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.typeTagOut, io.lsu.iwakeups[0].bits.uop.fp_ctrl.typeTagOut connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.typeTagIn, io.lsu.iwakeups[0].bits.uop.fp_ctrl.typeTagIn connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.swap23, io.lsu.iwakeups[0].bits.uop.fp_ctrl.swap23 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.swap12, io.lsu.iwakeups[0].bits.uop.fp_ctrl.swap12 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.ren3, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren3 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.ren2, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren2 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.ren1, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren1 connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.wen, io.lsu.iwakeups[0].bits.uop.fp_ctrl.wen connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.ldst, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ldst connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.op2_sel, io.lsu.iwakeups[0].bits.uop.op2_sel connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.op1_sel, io.lsu.iwakeups[0].bits.uop.op1_sel connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.imm_packed, io.lsu.iwakeups[0].bits.uop.imm_packed connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.pimm, io.lsu.iwakeups[0].bits.uop.pimm connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.imm_sel, io.lsu.iwakeups[0].bits.uop.imm_sel connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.imm_rename, io.lsu.iwakeups[0].bits.uop.imm_rename connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.taken, io.lsu.iwakeups[0].bits.uop.taken connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.pc_lob, io.lsu.iwakeups[0].bits.uop.pc_lob connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.edge_inst, io.lsu.iwakeups[0].bits.uop.edge_inst connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.ftq_idx, io.lsu.iwakeups[0].bits.uop.ftq_idx connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.is_mov, io.lsu.iwakeups[0].bits.uop.is_mov connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.is_rocc, io.lsu.iwakeups[0].bits.uop.is_rocc connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.is_sys_pc2epc, io.lsu.iwakeups[0].bits.uop.is_sys_pc2epc connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.is_eret, io.lsu.iwakeups[0].bits.uop.is_eret connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.is_amo, io.lsu.iwakeups[0].bits.uop.is_amo connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.is_sfence, io.lsu.iwakeups[0].bits.uop.is_sfence connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.is_fencei, io.lsu.iwakeups[0].bits.uop.is_fencei connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.is_fence, io.lsu.iwakeups[0].bits.uop.is_fence connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.is_sfb, io.lsu.iwakeups[0].bits.uop.is_sfb connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.br_type, io.lsu.iwakeups[0].bits.uop.br_type connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.br_tag, io.lsu.iwakeups[0].bits.uop.br_tag connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.br_mask, io.lsu.iwakeups[0].bits.uop.br_mask connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.dis_col_sel, io.lsu.iwakeups[0].bits.uop.dis_col_sel connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_p3_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p3_bypass_hint connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_p2_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p2_bypass_hint connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_p1_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p1_bypass_hint connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_p2_speculative_child, io.lsu.iwakeups[0].bits.uop.iw_p2_speculative_child connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_p1_speculative_child, io.lsu.iwakeups[0].bits.uop.iw_p1_speculative_child connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_issued_partial_dgen, io.lsu.iwakeups[0].bits.uop.iw_issued_partial_dgen connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_issued_partial_agen, io.lsu.iwakeups[0].bits.uop.iw_issued_partial_agen connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_issued, io.lsu.iwakeups[0].bits.uop.iw_issued connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[0], io.lsu.iwakeups[0].bits.uop.fu_code[0] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[1], io.lsu.iwakeups[0].bits.uop.fu_code[1] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[2], io.lsu.iwakeups[0].bits.uop.fu_code[2] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[3], io.lsu.iwakeups[0].bits.uop.fu_code[3] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[4], io.lsu.iwakeups[0].bits.uop.fu_code[4] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[5], io.lsu.iwakeups[0].bits.uop.fu_code[5] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[6], io.lsu.iwakeups[0].bits.uop.fu_code[6] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[7], io.lsu.iwakeups[0].bits.uop.fu_code[7] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[8], io.lsu.iwakeups[0].bits.uop.fu_code[8] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[9], io.lsu.iwakeups[0].bits.uop.fu_code[9] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iq_type[0], io.lsu.iwakeups[0].bits.uop.iq_type[0] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iq_type[1], io.lsu.iwakeups[0].bits.uop.iq_type[1] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iq_type[2], io.lsu.iwakeups[0].bits.uop.iq_type[2] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.iq_type[3], io.lsu.iwakeups[0].bits.uop.iq_type[3] connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.debug_pc, io.lsu.iwakeups[0].bits.uop.debug_pc connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.is_rvc, io.lsu.iwakeups[0].bits.uop.is_rvc connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.debug_inst, io.lsu.iwakeups[0].bits.uop.debug_inst connect alu_exe_unit_1.io_arb_rebusys[0].bits.uop.inst, io.lsu.iwakeups[0].bits.uop.inst connect alu_exe_unit_1.io_arb_rebusys[0].valid, io.lsu.iwakeups[0].valid connect iregfile.io.arb_read_reqs[4], mem_exe_unit_0.io_arb_irf_reqs[0] connect immregfile.io.arb_read_reqs[2], mem_exe_unit_0.io_arb_immrf_req connect mem_exe_unit_0.io_arb_rebusys[0].bits.rebusy, io.lsu.iwakeups[0].bits.rebusy connect mem_exe_unit_0.io_arb_rebusys[0].bits.speculative_mask, io.lsu.iwakeups[0].bits.speculative_mask connect mem_exe_unit_0.io_arb_rebusys[0].bits.bypassable, io.lsu.iwakeups[0].bits.bypassable connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_tsrc, io.lsu.iwakeups[0].bits.uop.debug_tsrc connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_fsrc, io.lsu.iwakeups[0].bits.uop.debug_fsrc connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.bp_xcpt_if, io.lsu.iwakeups[0].bits.uop.bp_xcpt_if connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.bp_debug_if, io.lsu.iwakeups[0].bits.uop.bp_debug_if connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.xcpt_ma_if, io.lsu.iwakeups[0].bits.uop.xcpt_ma_if connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.xcpt_ae_if, io.lsu.iwakeups[0].bits.uop.xcpt_ae_if connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.xcpt_pf_if, io.lsu.iwakeups[0].bits.uop.xcpt_pf_if connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_typ, io.lsu.iwakeups[0].bits.uop.fp_typ connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_rm, io.lsu.iwakeups[0].bits.uop.fp_rm connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_val, io.lsu.iwakeups[0].bits.uop.fp_val connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fcn_op, io.lsu.iwakeups[0].bits.uop.fcn_op connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fcn_dw, io.lsu.iwakeups[0].bits.uop.fcn_dw connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.frs3_en, io.lsu.iwakeups[0].bits.uop.frs3_en connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs2_rtype, io.lsu.iwakeups[0].bits.uop.lrs2_rtype connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs1_rtype, io.lsu.iwakeups[0].bits.uop.lrs1_rtype connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.dst_rtype, io.lsu.iwakeups[0].bits.uop.dst_rtype connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs3, io.lsu.iwakeups[0].bits.uop.lrs3 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs2, io.lsu.iwakeups[0].bits.uop.lrs2 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs1, io.lsu.iwakeups[0].bits.uop.lrs1 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.ldst, io.lsu.iwakeups[0].bits.uop.ldst connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.ldst_is_rs1, io.lsu.iwakeups[0].bits.uop.ldst_is_rs1 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.csr_cmd, io.lsu.iwakeups[0].bits.uop.csr_cmd connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.flush_on_commit, io.lsu.iwakeups[0].bits.uop.flush_on_commit connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.is_unique, io.lsu.iwakeups[0].bits.uop.is_unique connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.uses_stq, io.lsu.iwakeups[0].bits.uop.uses_stq connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.uses_ldq, io.lsu.iwakeups[0].bits.uop.uses_ldq connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.mem_signed, io.lsu.iwakeups[0].bits.uop.mem_signed connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.mem_size, io.lsu.iwakeups[0].bits.uop.mem_size connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.mem_cmd, io.lsu.iwakeups[0].bits.uop.mem_cmd connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.exc_cause, io.lsu.iwakeups[0].bits.uop.exc_cause connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.exception, io.lsu.iwakeups[0].bits.uop.exception connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.stale_pdst, io.lsu.iwakeups[0].bits.uop.stale_pdst connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.ppred_busy, io.lsu.iwakeups[0].bits.uop.ppred_busy connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.prs3_busy, io.lsu.iwakeups[0].bits.uop.prs3_busy connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.prs2_busy, io.lsu.iwakeups[0].bits.uop.prs2_busy connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.prs1_busy, io.lsu.iwakeups[0].bits.uop.prs1_busy connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.ppred, io.lsu.iwakeups[0].bits.uop.ppred connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.prs3, io.lsu.iwakeups[0].bits.uop.prs3 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.prs2, io.lsu.iwakeups[0].bits.uop.prs2 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.prs1, io.lsu.iwakeups[0].bits.uop.prs1 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.pdst, io.lsu.iwakeups[0].bits.uop.pdst connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.rxq_idx, io.lsu.iwakeups[0].bits.uop.rxq_idx connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.stq_idx, io.lsu.iwakeups[0].bits.uop.stq_idx connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.ldq_idx, io.lsu.iwakeups[0].bits.uop.ldq_idx connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.rob_idx, io.lsu.iwakeups[0].bits.uop.rob_idx connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.vec, io.lsu.iwakeups[0].bits.uop.fp_ctrl.vec connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.wflags, io.lsu.iwakeups[0].bits.uop.fp_ctrl.wflags connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.sqrt, io.lsu.iwakeups[0].bits.uop.fp_ctrl.sqrt connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.div, io.lsu.iwakeups[0].bits.uop.fp_ctrl.div connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.fma, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fma connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.fastpipe, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fastpipe connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.toint, io.lsu.iwakeups[0].bits.uop.fp_ctrl.toint connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.fromint, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fromint connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.typeTagOut, io.lsu.iwakeups[0].bits.uop.fp_ctrl.typeTagOut connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.typeTagIn, io.lsu.iwakeups[0].bits.uop.fp_ctrl.typeTagIn connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.swap23, io.lsu.iwakeups[0].bits.uop.fp_ctrl.swap23 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.swap12, io.lsu.iwakeups[0].bits.uop.fp_ctrl.swap12 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ren3, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren3 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ren2, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren2 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ren1, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren1 connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.wen, io.lsu.iwakeups[0].bits.uop.fp_ctrl.wen connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ldst, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ldst connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.op2_sel, io.lsu.iwakeups[0].bits.uop.op2_sel connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.op1_sel, io.lsu.iwakeups[0].bits.uop.op1_sel connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.imm_packed, io.lsu.iwakeups[0].bits.uop.imm_packed connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.pimm, io.lsu.iwakeups[0].bits.uop.pimm connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.imm_sel, io.lsu.iwakeups[0].bits.uop.imm_sel connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.imm_rename, io.lsu.iwakeups[0].bits.uop.imm_rename connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.taken, io.lsu.iwakeups[0].bits.uop.taken connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.pc_lob, io.lsu.iwakeups[0].bits.uop.pc_lob connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.edge_inst, io.lsu.iwakeups[0].bits.uop.edge_inst connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.ftq_idx, io.lsu.iwakeups[0].bits.uop.ftq_idx connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.is_mov, io.lsu.iwakeups[0].bits.uop.is_mov connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.is_rocc, io.lsu.iwakeups[0].bits.uop.is_rocc connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.is_sys_pc2epc, io.lsu.iwakeups[0].bits.uop.is_sys_pc2epc connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.is_eret, io.lsu.iwakeups[0].bits.uop.is_eret connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.is_amo, io.lsu.iwakeups[0].bits.uop.is_amo connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.is_sfence, io.lsu.iwakeups[0].bits.uop.is_sfence connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.is_fencei, io.lsu.iwakeups[0].bits.uop.is_fencei connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.is_fence, io.lsu.iwakeups[0].bits.uop.is_fence connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.is_sfb, io.lsu.iwakeups[0].bits.uop.is_sfb connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.br_type, io.lsu.iwakeups[0].bits.uop.br_type connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.br_tag, io.lsu.iwakeups[0].bits.uop.br_tag connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.br_mask, io.lsu.iwakeups[0].bits.uop.br_mask connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.dis_col_sel, io.lsu.iwakeups[0].bits.uop.dis_col_sel connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p3_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p3_bypass_hint connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p2_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p2_bypass_hint connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p1_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p1_bypass_hint connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p2_speculative_child, io.lsu.iwakeups[0].bits.uop.iw_p2_speculative_child connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p1_speculative_child, io.lsu.iwakeups[0].bits.uop.iw_p1_speculative_child connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_issued_partial_dgen, io.lsu.iwakeups[0].bits.uop.iw_issued_partial_dgen connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_issued_partial_agen, io.lsu.iwakeups[0].bits.uop.iw_issued_partial_agen connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_issued, io.lsu.iwakeups[0].bits.uop.iw_issued connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[0], io.lsu.iwakeups[0].bits.uop.fu_code[0] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[1], io.lsu.iwakeups[0].bits.uop.fu_code[1] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[2], io.lsu.iwakeups[0].bits.uop.fu_code[2] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[3], io.lsu.iwakeups[0].bits.uop.fu_code[3] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[4], io.lsu.iwakeups[0].bits.uop.fu_code[4] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[5], io.lsu.iwakeups[0].bits.uop.fu_code[5] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[6], io.lsu.iwakeups[0].bits.uop.fu_code[6] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[7], io.lsu.iwakeups[0].bits.uop.fu_code[7] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[8], io.lsu.iwakeups[0].bits.uop.fu_code[8] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[9], io.lsu.iwakeups[0].bits.uop.fu_code[9] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[0], io.lsu.iwakeups[0].bits.uop.iq_type[0] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[1], io.lsu.iwakeups[0].bits.uop.iq_type[1] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[2], io.lsu.iwakeups[0].bits.uop.iq_type[2] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[3], io.lsu.iwakeups[0].bits.uop.iq_type[3] connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_pc, io.lsu.iwakeups[0].bits.uop.debug_pc connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.is_rvc, io.lsu.iwakeups[0].bits.uop.is_rvc connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_inst, io.lsu.iwakeups[0].bits.uop.debug_inst connect mem_exe_unit_0.io_arb_rebusys[0].bits.uop.inst, io.lsu.iwakeups[0].bits.uop.inst connect mem_exe_unit_0.io_arb_rebusys[0].valid, io.lsu.iwakeups[0].valid connect iregfile.io.arb_read_reqs[5], mem_exe_unit_1.io_arb_irf_reqs[0] connect immregfile.io.arb_read_reqs[3], mem_exe_unit_1.io_arb_immrf_req connect mem_exe_unit_1.io_arb_rebusys[0].bits.rebusy, io.lsu.iwakeups[0].bits.rebusy connect mem_exe_unit_1.io_arb_rebusys[0].bits.speculative_mask, io.lsu.iwakeups[0].bits.speculative_mask connect mem_exe_unit_1.io_arb_rebusys[0].bits.bypassable, io.lsu.iwakeups[0].bits.bypassable connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.debug_tsrc, io.lsu.iwakeups[0].bits.uop.debug_tsrc connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.debug_fsrc, io.lsu.iwakeups[0].bits.uop.debug_fsrc connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.bp_xcpt_if, io.lsu.iwakeups[0].bits.uop.bp_xcpt_if connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.bp_debug_if, io.lsu.iwakeups[0].bits.uop.bp_debug_if connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.xcpt_ma_if, io.lsu.iwakeups[0].bits.uop.xcpt_ma_if connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.xcpt_ae_if, io.lsu.iwakeups[0].bits.uop.xcpt_ae_if connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.xcpt_pf_if, io.lsu.iwakeups[0].bits.uop.xcpt_pf_if connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_typ, io.lsu.iwakeups[0].bits.uop.fp_typ connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_rm, io.lsu.iwakeups[0].bits.uop.fp_rm connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_val, io.lsu.iwakeups[0].bits.uop.fp_val connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fcn_op, io.lsu.iwakeups[0].bits.uop.fcn_op connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fcn_dw, io.lsu.iwakeups[0].bits.uop.fcn_dw connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.frs3_en, io.lsu.iwakeups[0].bits.uop.frs3_en connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.lrs2_rtype, io.lsu.iwakeups[0].bits.uop.lrs2_rtype connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.lrs1_rtype, io.lsu.iwakeups[0].bits.uop.lrs1_rtype connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.dst_rtype, io.lsu.iwakeups[0].bits.uop.dst_rtype connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.lrs3, io.lsu.iwakeups[0].bits.uop.lrs3 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.lrs2, io.lsu.iwakeups[0].bits.uop.lrs2 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.lrs1, io.lsu.iwakeups[0].bits.uop.lrs1 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.ldst, io.lsu.iwakeups[0].bits.uop.ldst connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.ldst_is_rs1, io.lsu.iwakeups[0].bits.uop.ldst_is_rs1 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.csr_cmd, io.lsu.iwakeups[0].bits.uop.csr_cmd connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.flush_on_commit, io.lsu.iwakeups[0].bits.uop.flush_on_commit connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.is_unique, io.lsu.iwakeups[0].bits.uop.is_unique connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.uses_stq, io.lsu.iwakeups[0].bits.uop.uses_stq connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.uses_ldq, io.lsu.iwakeups[0].bits.uop.uses_ldq connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.mem_signed, io.lsu.iwakeups[0].bits.uop.mem_signed connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.mem_size, io.lsu.iwakeups[0].bits.uop.mem_size connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.mem_cmd, io.lsu.iwakeups[0].bits.uop.mem_cmd connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.exc_cause, io.lsu.iwakeups[0].bits.uop.exc_cause connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.exception, io.lsu.iwakeups[0].bits.uop.exception connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.stale_pdst, io.lsu.iwakeups[0].bits.uop.stale_pdst connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.ppred_busy, io.lsu.iwakeups[0].bits.uop.ppred_busy connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.prs3_busy, io.lsu.iwakeups[0].bits.uop.prs3_busy connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.prs2_busy, io.lsu.iwakeups[0].bits.uop.prs2_busy connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.prs1_busy, io.lsu.iwakeups[0].bits.uop.prs1_busy connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.ppred, io.lsu.iwakeups[0].bits.uop.ppred connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.prs3, io.lsu.iwakeups[0].bits.uop.prs3 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.prs2, io.lsu.iwakeups[0].bits.uop.prs2 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.prs1, io.lsu.iwakeups[0].bits.uop.prs1 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.pdst, io.lsu.iwakeups[0].bits.uop.pdst connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.rxq_idx, io.lsu.iwakeups[0].bits.uop.rxq_idx connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.stq_idx, io.lsu.iwakeups[0].bits.uop.stq_idx connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.ldq_idx, io.lsu.iwakeups[0].bits.uop.ldq_idx connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.rob_idx, io.lsu.iwakeups[0].bits.uop.rob_idx connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.vec, io.lsu.iwakeups[0].bits.uop.fp_ctrl.vec connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.wflags, io.lsu.iwakeups[0].bits.uop.fp_ctrl.wflags connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.sqrt, io.lsu.iwakeups[0].bits.uop.fp_ctrl.sqrt connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.div, io.lsu.iwakeups[0].bits.uop.fp_ctrl.div connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.fma, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fma connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.fastpipe, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fastpipe connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.toint, io.lsu.iwakeups[0].bits.uop.fp_ctrl.toint connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.fromint, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fromint connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.typeTagOut, io.lsu.iwakeups[0].bits.uop.fp_ctrl.typeTagOut connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.typeTagIn, io.lsu.iwakeups[0].bits.uop.fp_ctrl.typeTagIn connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.swap23, io.lsu.iwakeups[0].bits.uop.fp_ctrl.swap23 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.swap12, io.lsu.iwakeups[0].bits.uop.fp_ctrl.swap12 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.ren3, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren3 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.ren2, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren2 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.ren1, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren1 connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.wen, io.lsu.iwakeups[0].bits.uop.fp_ctrl.wen connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fp_ctrl.ldst, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ldst connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.op2_sel, io.lsu.iwakeups[0].bits.uop.op2_sel connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.op1_sel, io.lsu.iwakeups[0].bits.uop.op1_sel connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.imm_packed, io.lsu.iwakeups[0].bits.uop.imm_packed connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.pimm, io.lsu.iwakeups[0].bits.uop.pimm connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.imm_sel, io.lsu.iwakeups[0].bits.uop.imm_sel connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.imm_rename, io.lsu.iwakeups[0].bits.uop.imm_rename connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.taken, io.lsu.iwakeups[0].bits.uop.taken connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.pc_lob, io.lsu.iwakeups[0].bits.uop.pc_lob connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.edge_inst, io.lsu.iwakeups[0].bits.uop.edge_inst connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.ftq_idx, io.lsu.iwakeups[0].bits.uop.ftq_idx connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.is_mov, io.lsu.iwakeups[0].bits.uop.is_mov connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.is_rocc, io.lsu.iwakeups[0].bits.uop.is_rocc connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.is_sys_pc2epc, io.lsu.iwakeups[0].bits.uop.is_sys_pc2epc connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.is_eret, io.lsu.iwakeups[0].bits.uop.is_eret connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.is_amo, io.lsu.iwakeups[0].bits.uop.is_amo connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.is_sfence, io.lsu.iwakeups[0].bits.uop.is_sfence connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.is_fencei, io.lsu.iwakeups[0].bits.uop.is_fencei connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.is_fence, io.lsu.iwakeups[0].bits.uop.is_fence connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.is_sfb, io.lsu.iwakeups[0].bits.uop.is_sfb connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.br_type, io.lsu.iwakeups[0].bits.uop.br_type connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.br_tag, io.lsu.iwakeups[0].bits.uop.br_tag connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.br_mask, io.lsu.iwakeups[0].bits.uop.br_mask connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.dis_col_sel, io.lsu.iwakeups[0].bits.uop.dis_col_sel connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_p3_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p3_bypass_hint connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_p2_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p2_bypass_hint connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_p1_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p1_bypass_hint connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_p2_speculative_child, io.lsu.iwakeups[0].bits.uop.iw_p2_speculative_child connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_p1_speculative_child, io.lsu.iwakeups[0].bits.uop.iw_p1_speculative_child connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_issued_partial_dgen, io.lsu.iwakeups[0].bits.uop.iw_issued_partial_dgen connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_issued_partial_agen, io.lsu.iwakeups[0].bits.uop.iw_issued_partial_agen connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iw_issued, io.lsu.iwakeups[0].bits.uop.iw_issued connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[0], io.lsu.iwakeups[0].bits.uop.fu_code[0] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[1], io.lsu.iwakeups[0].bits.uop.fu_code[1] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[2], io.lsu.iwakeups[0].bits.uop.fu_code[2] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[3], io.lsu.iwakeups[0].bits.uop.fu_code[3] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[4], io.lsu.iwakeups[0].bits.uop.fu_code[4] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[5], io.lsu.iwakeups[0].bits.uop.fu_code[5] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[6], io.lsu.iwakeups[0].bits.uop.fu_code[6] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[7], io.lsu.iwakeups[0].bits.uop.fu_code[7] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[8], io.lsu.iwakeups[0].bits.uop.fu_code[8] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.fu_code[9], io.lsu.iwakeups[0].bits.uop.fu_code[9] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iq_type[0], io.lsu.iwakeups[0].bits.uop.iq_type[0] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iq_type[1], io.lsu.iwakeups[0].bits.uop.iq_type[1] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iq_type[2], io.lsu.iwakeups[0].bits.uop.iq_type[2] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.iq_type[3], io.lsu.iwakeups[0].bits.uop.iq_type[3] connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.debug_pc, io.lsu.iwakeups[0].bits.uop.debug_pc connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.is_rvc, io.lsu.iwakeups[0].bits.uop.is_rvc connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.debug_inst, io.lsu.iwakeups[0].bits.uop.debug_inst connect mem_exe_unit_1.io_arb_rebusys[0].bits.uop.inst, io.lsu.iwakeups[0].bits.uop.inst connect mem_exe_unit_1.io_arb_rebusys[0].valid, io.lsu.iwakeups[0].valid connect iregfile.io.arb_read_reqs[6], unique_exe_unit_0.io_arb_irf_reqs[0] connect iregfile.io.arb_read_reqs[7], unique_exe_unit_0.io_arb_irf_reqs[1] connect immregfile.io.arb_read_reqs[4], unique_exe_unit_0.io_arb_immrf_req connect unique_exe_unit_0.io_arb_rebusys[0].bits.rebusy, io.lsu.iwakeups[0].bits.rebusy connect unique_exe_unit_0.io_arb_rebusys[0].bits.speculative_mask, io.lsu.iwakeups[0].bits.speculative_mask connect unique_exe_unit_0.io_arb_rebusys[0].bits.bypassable, io.lsu.iwakeups[0].bits.bypassable connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_tsrc, io.lsu.iwakeups[0].bits.uop.debug_tsrc connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_fsrc, io.lsu.iwakeups[0].bits.uop.debug_fsrc connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.bp_xcpt_if, io.lsu.iwakeups[0].bits.uop.bp_xcpt_if connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.bp_debug_if, io.lsu.iwakeups[0].bits.uop.bp_debug_if connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.xcpt_ma_if, io.lsu.iwakeups[0].bits.uop.xcpt_ma_if connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.xcpt_ae_if, io.lsu.iwakeups[0].bits.uop.xcpt_ae_if connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.xcpt_pf_if, io.lsu.iwakeups[0].bits.uop.xcpt_pf_if connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_typ, io.lsu.iwakeups[0].bits.uop.fp_typ connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_rm, io.lsu.iwakeups[0].bits.uop.fp_rm connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_val, io.lsu.iwakeups[0].bits.uop.fp_val connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fcn_op, io.lsu.iwakeups[0].bits.uop.fcn_op connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fcn_dw, io.lsu.iwakeups[0].bits.uop.fcn_dw connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.frs3_en, io.lsu.iwakeups[0].bits.uop.frs3_en connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs2_rtype, io.lsu.iwakeups[0].bits.uop.lrs2_rtype connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs1_rtype, io.lsu.iwakeups[0].bits.uop.lrs1_rtype connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.dst_rtype, io.lsu.iwakeups[0].bits.uop.dst_rtype connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs3, io.lsu.iwakeups[0].bits.uop.lrs3 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs2, io.lsu.iwakeups[0].bits.uop.lrs2 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.lrs1, io.lsu.iwakeups[0].bits.uop.lrs1 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.ldst, io.lsu.iwakeups[0].bits.uop.ldst connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.ldst_is_rs1, io.lsu.iwakeups[0].bits.uop.ldst_is_rs1 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.csr_cmd, io.lsu.iwakeups[0].bits.uop.csr_cmd connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.flush_on_commit, io.lsu.iwakeups[0].bits.uop.flush_on_commit connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.is_unique, io.lsu.iwakeups[0].bits.uop.is_unique connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.uses_stq, io.lsu.iwakeups[0].bits.uop.uses_stq connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.uses_ldq, io.lsu.iwakeups[0].bits.uop.uses_ldq connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.mem_signed, io.lsu.iwakeups[0].bits.uop.mem_signed connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.mem_size, io.lsu.iwakeups[0].bits.uop.mem_size connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.mem_cmd, io.lsu.iwakeups[0].bits.uop.mem_cmd connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.exc_cause, io.lsu.iwakeups[0].bits.uop.exc_cause connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.exception, io.lsu.iwakeups[0].bits.uop.exception connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.stale_pdst, io.lsu.iwakeups[0].bits.uop.stale_pdst connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.ppred_busy, io.lsu.iwakeups[0].bits.uop.ppred_busy connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.prs3_busy, io.lsu.iwakeups[0].bits.uop.prs3_busy connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.prs2_busy, io.lsu.iwakeups[0].bits.uop.prs2_busy connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.prs1_busy, io.lsu.iwakeups[0].bits.uop.prs1_busy connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.ppred, io.lsu.iwakeups[0].bits.uop.ppred connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.prs3, io.lsu.iwakeups[0].bits.uop.prs3 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.prs2, io.lsu.iwakeups[0].bits.uop.prs2 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.prs1, io.lsu.iwakeups[0].bits.uop.prs1 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.pdst, io.lsu.iwakeups[0].bits.uop.pdst connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.rxq_idx, io.lsu.iwakeups[0].bits.uop.rxq_idx connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.stq_idx, io.lsu.iwakeups[0].bits.uop.stq_idx connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.ldq_idx, io.lsu.iwakeups[0].bits.uop.ldq_idx connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.rob_idx, io.lsu.iwakeups[0].bits.uop.rob_idx connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.vec, io.lsu.iwakeups[0].bits.uop.fp_ctrl.vec connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.wflags, io.lsu.iwakeups[0].bits.uop.fp_ctrl.wflags connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.sqrt, io.lsu.iwakeups[0].bits.uop.fp_ctrl.sqrt connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.div, io.lsu.iwakeups[0].bits.uop.fp_ctrl.div connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.fma, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fma connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.fastpipe, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fastpipe connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.toint, io.lsu.iwakeups[0].bits.uop.fp_ctrl.toint connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.fromint, io.lsu.iwakeups[0].bits.uop.fp_ctrl.fromint connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.typeTagOut, io.lsu.iwakeups[0].bits.uop.fp_ctrl.typeTagOut connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.typeTagIn, io.lsu.iwakeups[0].bits.uop.fp_ctrl.typeTagIn connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.swap23, io.lsu.iwakeups[0].bits.uop.fp_ctrl.swap23 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.swap12, io.lsu.iwakeups[0].bits.uop.fp_ctrl.swap12 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ren3, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren3 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ren2, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren2 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ren1, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ren1 connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.wen, io.lsu.iwakeups[0].bits.uop.fp_ctrl.wen connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fp_ctrl.ldst, io.lsu.iwakeups[0].bits.uop.fp_ctrl.ldst connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.op2_sel, io.lsu.iwakeups[0].bits.uop.op2_sel connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.op1_sel, io.lsu.iwakeups[0].bits.uop.op1_sel connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.imm_packed, io.lsu.iwakeups[0].bits.uop.imm_packed connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.pimm, io.lsu.iwakeups[0].bits.uop.pimm connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.imm_sel, io.lsu.iwakeups[0].bits.uop.imm_sel connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.imm_rename, io.lsu.iwakeups[0].bits.uop.imm_rename connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.taken, io.lsu.iwakeups[0].bits.uop.taken connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.pc_lob, io.lsu.iwakeups[0].bits.uop.pc_lob connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.edge_inst, io.lsu.iwakeups[0].bits.uop.edge_inst connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.ftq_idx, io.lsu.iwakeups[0].bits.uop.ftq_idx connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.is_mov, io.lsu.iwakeups[0].bits.uop.is_mov connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.is_rocc, io.lsu.iwakeups[0].bits.uop.is_rocc connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.is_sys_pc2epc, io.lsu.iwakeups[0].bits.uop.is_sys_pc2epc connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.is_eret, io.lsu.iwakeups[0].bits.uop.is_eret connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.is_amo, io.lsu.iwakeups[0].bits.uop.is_amo connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.is_sfence, io.lsu.iwakeups[0].bits.uop.is_sfence connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.is_fencei, io.lsu.iwakeups[0].bits.uop.is_fencei connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.is_fence, io.lsu.iwakeups[0].bits.uop.is_fence connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.is_sfb, io.lsu.iwakeups[0].bits.uop.is_sfb connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.br_type, io.lsu.iwakeups[0].bits.uop.br_type connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.br_tag, io.lsu.iwakeups[0].bits.uop.br_tag connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.br_mask, io.lsu.iwakeups[0].bits.uop.br_mask connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.dis_col_sel, io.lsu.iwakeups[0].bits.uop.dis_col_sel connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p3_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p3_bypass_hint connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p2_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p2_bypass_hint connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p1_bypass_hint, io.lsu.iwakeups[0].bits.uop.iw_p1_bypass_hint connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p2_speculative_child, io.lsu.iwakeups[0].bits.uop.iw_p2_speculative_child connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_p1_speculative_child, io.lsu.iwakeups[0].bits.uop.iw_p1_speculative_child connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_issued_partial_dgen, io.lsu.iwakeups[0].bits.uop.iw_issued_partial_dgen connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_issued_partial_agen, io.lsu.iwakeups[0].bits.uop.iw_issued_partial_agen connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iw_issued, io.lsu.iwakeups[0].bits.uop.iw_issued connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[0], io.lsu.iwakeups[0].bits.uop.fu_code[0] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[1], io.lsu.iwakeups[0].bits.uop.fu_code[1] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[2], io.lsu.iwakeups[0].bits.uop.fu_code[2] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[3], io.lsu.iwakeups[0].bits.uop.fu_code[3] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[4], io.lsu.iwakeups[0].bits.uop.fu_code[4] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[5], io.lsu.iwakeups[0].bits.uop.fu_code[5] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[6], io.lsu.iwakeups[0].bits.uop.fu_code[6] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[7], io.lsu.iwakeups[0].bits.uop.fu_code[7] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[8], io.lsu.iwakeups[0].bits.uop.fu_code[8] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.fu_code[9], io.lsu.iwakeups[0].bits.uop.fu_code[9] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[0], io.lsu.iwakeups[0].bits.uop.iq_type[0] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[1], io.lsu.iwakeups[0].bits.uop.iq_type[1] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[2], io.lsu.iwakeups[0].bits.uop.iq_type[2] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.iq_type[3], io.lsu.iwakeups[0].bits.uop.iq_type[3] connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_pc, io.lsu.iwakeups[0].bits.uop.debug_pc connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.is_rvc, io.lsu.iwakeups[0].bits.uop.is_rvc connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.debug_inst, io.lsu.iwakeups[0].bits.uop.debug_inst connect unique_exe_unit_0.io_arb_rebusys[0].bits.uop.inst, io.lsu.iwakeups[0].bits.uop.inst connect unique_exe_unit_0.io_arb_rebusys[0].valid, io.lsu.iwakeups[0].valid connect pregfile.io.arb_read_reqs[0], alu_exe_unit_0.io_arb_prf_req connect bregfile.io.arb_read_reqs[0], alu_exe_unit_0.io_arb_brf_req connect pregfile.io.arb_read_reqs[1], alu_exe_unit_1.io_arb_prf_req connect bregfile.io.arb_read_reqs[1], alu_exe_unit_1.io_arb_brf_req connect alu_exe_unit_0.io_rrd_irf_resps[0], iregfile.io.rrd_read_resps[0] connect alu_exe_unit_0.io_rrd_irf_resps[1], iregfile.io.rrd_read_resps[1] connect alu_exe_unit_0.io_rrd_immrf_resp, immregfile.io.rrd_read_resps[0] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.fflags.bits, int_bypasses[0].bits.fflags.bits connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.fflags.valid, int_bypasses[0].bits.fflags.valid connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.predicated, int_bypasses[0].bits.predicated connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.data, int_bypasses[0].bits.data connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_tsrc, int_bypasses[0].bits.uop.debug_tsrc connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_fsrc, int_bypasses[0].bits.uop.debug_fsrc connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.bp_xcpt_if, int_bypasses[0].bits.uop.bp_xcpt_if connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.bp_debug_if, int_bypasses[0].bits.uop.bp_debug_if connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.xcpt_ma_if, int_bypasses[0].bits.uop.xcpt_ma_if connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.xcpt_ae_if, int_bypasses[0].bits.uop.xcpt_ae_if connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.xcpt_pf_if, int_bypasses[0].bits.uop.xcpt_pf_if connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_typ, int_bypasses[0].bits.uop.fp_typ connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_rm, int_bypasses[0].bits.uop.fp_rm connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_val, int_bypasses[0].bits.uop.fp_val connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fcn_op, int_bypasses[0].bits.uop.fcn_op connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fcn_dw, int_bypasses[0].bits.uop.fcn_dw connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.frs3_en, int_bypasses[0].bits.uop.frs3_en connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs2_rtype, int_bypasses[0].bits.uop.lrs2_rtype connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs1_rtype, int_bypasses[0].bits.uop.lrs1_rtype connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.dst_rtype, int_bypasses[0].bits.uop.dst_rtype connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs3, int_bypasses[0].bits.uop.lrs3 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs2, int_bypasses[0].bits.uop.lrs2 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs1, int_bypasses[0].bits.uop.lrs1 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ldst, int_bypasses[0].bits.uop.ldst connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ldst_is_rs1, int_bypasses[0].bits.uop.ldst_is_rs1 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.csr_cmd, int_bypasses[0].bits.uop.csr_cmd connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.flush_on_commit, int_bypasses[0].bits.uop.flush_on_commit connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_unique, int_bypasses[0].bits.uop.is_unique connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.uses_stq, int_bypasses[0].bits.uop.uses_stq connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.uses_ldq, int_bypasses[0].bits.uop.uses_ldq connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.mem_signed, int_bypasses[0].bits.uop.mem_signed connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.mem_size, int_bypasses[0].bits.uop.mem_size connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.mem_cmd, int_bypasses[0].bits.uop.mem_cmd connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.exc_cause, int_bypasses[0].bits.uop.exc_cause connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.exception, int_bypasses[0].bits.uop.exception connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.stale_pdst, int_bypasses[0].bits.uop.stale_pdst connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ppred_busy, int_bypasses[0].bits.uop.ppred_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs3_busy, int_bypasses[0].bits.uop.prs3_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs2_busy, int_bypasses[0].bits.uop.prs2_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs1_busy, int_bypasses[0].bits.uop.prs1_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ppred, int_bypasses[0].bits.uop.ppred connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs3, int_bypasses[0].bits.uop.prs3 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs2, int_bypasses[0].bits.uop.prs2 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs1, int_bypasses[0].bits.uop.prs1 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.pdst, int_bypasses[0].bits.uop.pdst connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.rxq_idx, int_bypasses[0].bits.uop.rxq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.stq_idx, int_bypasses[0].bits.uop.stq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ldq_idx, int_bypasses[0].bits.uop.ldq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.rob_idx, int_bypasses[0].bits.uop.rob_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.vec, int_bypasses[0].bits.uop.fp_ctrl.vec connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.wflags, int_bypasses[0].bits.uop.fp_ctrl.wflags connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.sqrt, int_bypasses[0].bits.uop.fp_ctrl.sqrt connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.div, int_bypasses[0].bits.uop.fp_ctrl.div connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fma, int_bypasses[0].bits.uop.fp_ctrl.fma connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fastpipe, int_bypasses[0].bits.uop.fp_ctrl.fastpipe connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.toint, int_bypasses[0].bits.uop.fp_ctrl.toint connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fromint, int_bypasses[0].bits.uop.fp_ctrl.fromint connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.typeTagOut, int_bypasses[0].bits.uop.fp_ctrl.typeTagOut connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.typeTagIn, int_bypasses[0].bits.uop.fp_ctrl.typeTagIn connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.swap23, int_bypasses[0].bits.uop.fp_ctrl.swap23 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.swap12, int_bypasses[0].bits.uop.fp_ctrl.swap12 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren3, int_bypasses[0].bits.uop.fp_ctrl.ren3 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren2, int_bypasses[0].bits.uop.fp_ctrl.ren2 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren1, int_bypasses[0].bits.uop.fp_ctrl.ren1 connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.wen, int_bypasses[0].bits.uop.fp_ctrl.wen connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ldst, int_bypasses[0].bits.uop.fp_ctrl.ldst connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.op2_sel, int_bypasses[0].bits.uop.op2_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.op1_sel, int_bypasses[0].bits.uop.op1_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.imm_packed, int_bypasses[0].bits.uop.imm_packed connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.pimm, int_bypasses[0].bits.uop.pimm connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.imm_sel, int_bypasses[0].bits.uop.imm_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.imm_rename, int_bypasses[0].bits.uop.imm_rename connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.taken, int_bypasses[0].bits.uop.taken connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.pc_lob, int_bypasses[0].bits.uop.pc_lob connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.edge_inst, int_bypasses[0].bits.uop.edge_inst connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ftq_idx, int_bypasses[0].bits.uop.ftq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_mov, int_bypasses[0].bits.uop.is_mov connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_rocc, int_bypasses[0].bits.uop.is_rocc connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_sys_pc2epc, int_bypasses[0].bits.uop.is_sys_pc2epc connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_eret, int_bypasses[0].bits.uop.is_eret connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_amo, int_bypasses[0].bits.uop.is_amo connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_sfence, int_bypasses[0].bits.uop.is_sfence connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_fencei, int_bypasses[0].bits.uop.is_fencei connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_fence, int_bypasses[0].bits.uop.is_fence connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_sfb, int_bypasses[0].bits.uop.is_sfb connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.br_type, int_bypasses[0].bits.uop.br_type connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.br_tag, int_bypasses[0].bits.uop.br_tag connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.br_mask, int_bypasses[0].bits.uop.br_mask connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.dis_col_sel, int_bypasses[0].bits.uop.dis_col_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p3_bypass_hint, int_bypasses[0].bits.uop.iw_p3_bypass_hint connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p2_bypass_hint, int_bypasses[0].bits.uop.iw_p2_bypass_hint connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p1_bypass_hint, int_bypasses[0].bits.uop.iw_p1_bypass_hint connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p2_speculative_child, int_bypasses[0].bits.uop.iw_p2_speculative_child connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p1_speculative_child, int_bypasses[0].bits.uop.iw_p1_speculative_child connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_issued_partial_dgen, int_bypasses[0].bits.uop.iw_issued_partial_dgen connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_issued_partial_agen, int_bypasses[0].bits.uop.iw_issued_partial_agen connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_issued, int_bypasses[0].bits.uop.iw_issued connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[0], int_bypasses[0].bits.uop.fu_code[0] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[1], int_bypasses[0].bits.uop.fu_code[1] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[2], int_bypasses[0].bits.uop.fu_code[2] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[3], int_bypasses[0].bits.uop.fu_code[3] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[4], int_bypasses[0].bits.uop.fu_code[4] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[5], int_bypasses[0].bits.uop.fu_code[5] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[6], int_bypasses[0].bits.uop.fu_code[6] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[7], int_bypasses[0].bits.uop.fu_code[7] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[8], int_bypasses[0].bits.uop.fu_code[8] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[9], int_bypasses[0].bits.uop.fu_code[9] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[0], int_bypasses[0].bits.uop.iq_type[0] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[1], int_bypasses[0].bits.uop.iq_type[1] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[2], int_bypasses[0].bits.uop.iq_type[2] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[3], int_bypasses[0].bits.uop.iq_type[3] connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_pc, int_bypasses[0].bits.uop.debug_pc connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_rvc, int_bypasses[0].bits.uop.is_rvc connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_inst, int_bypasses[0].bits.uop.debug_inst connect alu_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.inst, int_bypasses[0].bits.uop.inst connect alu_exe_unit_0.io_rrd_irf_bypasses[0].valid, int_bypasses[0].valid connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.fflags.bits, int_bypasses[1].bits.fflags.bits connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.fflags.valid, int_bypasses[1].bits.fflags.valid connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.predicated, int_bypasses[1].bits.predicated connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.data, int_bypasses[1].bits.data connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_tsrc, int_bypasses[1].bits.uop.debug_tsrc connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_fsrc, int_bypasses[1].bits.uop.debug_fsrc connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.bp_xcpt_if, int_bypasses[1].bits.uop.bp_xcpt_if connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.bp_debug_if, int_bypasses[1].bits.uop.bp_debug_if connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.xcpt_ma_if, int_bypasses[1].bits.uop.xcpt_ma_if connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.xcpt_ae_if, int_bypasses[1].bits.uop.xcpt_ae_if connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.xcpt_pf_if, int_bypasses[1].bits.uop.xcpt_pf_if connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_typ, int_bypasses[1].bits.uop.fp_typ connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_rm, int_bypasses[1].bits.uop.fp_rm connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_val, int_bypasses[1].bits.uop.fp_val connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fcn_op, int_bypasses[1].bits.uop.fcn_op connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fcn_dw, int_bypasses[1].bits.uop.fcn_dw connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.frs3_en, int_bypasses[1].bits.uop.frs3_en connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs2_rtype, int_bypasses[1].bits.uop.lrs2_rtype connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs1_rtype, int_bypasses[1].bits.uop.lrs1_rtype connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.dst_rtype, int_bypasses[1].bits.uop.dst_rtype connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs3, int_bypasses[1].bits.uop.lrs3 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs2, int_bypasses[1].bits.uop.lrs2 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs1, int_bypasses[1].bits.uop.lrs1 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ldst, int_bypasses[1].bits.uop.ldst connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ldst_is_rs1, int_bypasses[1].bits.uop.ldst_is_rs1 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.csr_cmd, int_bypasses[1].bits.uop.csr_cmd connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.flush_on_commit, int_bypasses[1].bits.uop.flush_on_commit connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_unique, int_bypasses[1].bits.uop.is_unique connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.uses_stq, int_bypasses[1].bits.uop.uses_stq connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.uses_ldq, int_bypasses[1].bits.uop.uses_ldq connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.mem_signed, int_bypasses[1].bits.uop.mem_signed connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.mem_size, int_bypasses[1].bits.uop.mem_size connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.mem_cmd, int_bypasses[1].bits.uop.mem_cmd connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.exc_cause, int_bypasses[1].bits.uop.exc_cause connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.exception, int_bypasses[1].bits.uop.exception connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.stale_pdst, int_bypasses[1].bits.uop.stale_pdst connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ppred_busy, int_bypasses[1].bits.uop.ppred_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs3_busy, int_bypasses[1].bits.uop.prs3_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs2_busy, int_bypasses[1].bits.uop.prs2_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs1_busy, int_bypasses[1].bits.uop.prs1_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ppred, int_bypasses[1].bits.uop.ppred connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs3, int_bypasses[1].bits.uop.prs3 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs2, int_bypasses[1].bits.uop.prs2 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs1, int_bypasses[1].bits.uop.prs1 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.pdst, int_bypasses[1].bits.uop.pdst connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.rxq_idx, int_bypasses[1].bits.uop.rxq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.stq_idx, int_bypasses[1].bits.uop.stq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ldq_idx, int_bypasses[1].bits.uop.ldq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.rob_idx, int_bypasses[1].bits.uop.rob_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.vec, int_bypasses[1].bits.uop.fp_ctrl.vec connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.wflags, int_bypasses[1].bits.uop.fp_ctrl.wflags connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.sqrt, int_bypasses[1].bits.uop.fp_ctrl.sqrt connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.div, int_bypasses[1].bits.uop.fp_ctrl.div connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fma, int_bypasses[1].bits.uop.fp_ctrl.fma connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fastpipe, int_bypasses[1].bits.uop.fp_ctrl.fastpipe connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.toint, int_bypasses[1].bits.uop.fp_ctrl.toint connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fromint, int_bypasses[1].bits.uop.fp_ctrl.fromint connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.typeTagOut, int_bypasses[1].bits.uop.fp_ctrl.typeTagOut connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.typeTagIn, int_bypasses[1].bits.uop.fp_ctrl.typeTagIn connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.swap23, int_bypasses[1].bits.uop.fp_ctrl.swap23 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.swap12, int_bypasses[1].bits.uop.fp_ctrl.swap12 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren3, int_bypasses[1].bits.uop.fp_ctrl.ren3 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren2, int_bypasses[1].bits.uop.fp_ctrl.ren2 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren1, int_bypasses[1].bits.uop.fp_ctrl.ren1 connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.wen, int_bypasses[1].bits.uop.fp_ctrl.wen connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ldst, int_bypasses[1].bits.uop.fp_ctrl.ldst connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.op2_sel, int_bypasses[1].bits.uop.op2_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.op1_sel, int_bypasses[1].bits.uop.op1_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.imm_packed, int_bypasses[1].bits.uop.imm_packed connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.pimm, int_bypasses[1].bits.uop.pimm connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.imm_sel, int_bypasses[1].bits.uop.imm_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.imm_rename, int_bypasses[1].bits.uop.imm_rename connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.taken, int_bypasses[1].bits.uop.taken connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.pc_lob, int_bypasses[1].bits.uop.pc_lob connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.edge_inst, int_bypasses[1].bits.uop.edge_inst connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ftq_idx, int_bypasses[1].bits.uop.ftq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_mov, int_bypasses[1].bits.uop.is_mov connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_rocc, int_bypasses[1].bits.uop.is_rocc connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_sys_pc2epc, int_bypasses[1].bits.uop.is_sys_pc2epc connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_eret, int_bypasses[1].bits.uop.is_eret connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_amo, int_bypasses[1].bits.uop.is_amo connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_sfence, int_bypasses[1].bits.uop.is_sfence connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_fencei, int_bypasses[1].bits.uop.is_fencei connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_fence, int_bypasses[1].bits.uop.is_fence connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_sfb, int_bypasses[1].bits.uop.is_sfb connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.br_type, int_bypasses[1].bits.uop.br_type connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.br_tag, int_bypasses[1].bits.uop.br_tag connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.br_mask, int_bypasses[1].bits.uop.br_mask connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.dis_col_sel, int_bypasses[1].bits.uop.dis_col_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p3_bypass_hint, int_bypasses[1].bits.uop.iw_p3_bypass_hint connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p2_bypass_hint, int_bypasses[1].bits.uop.iw_p2_bypass_hint connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p1_bypass_hint, int_bypasses[1].bits.uop.iw_p1_bypass_hint connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p2_speculative_child, int_bypasses[1].bits.uop.iw_p2_speculative_child connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p1_speculative_child, int_bypasses[1].bits.uop.iw_p1_speculative_child connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_issued_partial_dgen, int_bypasses[1].bits.uop.iw_issued_partial_dgen connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_issued_partial_agen, int_bypasses[1].bits.uop.iw_issued_partial_agen connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_issued, int_bypasses[1].bits.uop.iw_issued connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[0], int_bypasses[1].bits.uop.fu_code[0] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[1], int_bypasses[1].bits.uop.fu_code[1] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[2], int_bypasses[1].bits.uop.fu_code[2] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[3], int_bypasses[1].bits.uop.fu_code[3] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[4], int_bypasses[1].bits.uop.fu_code[4] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[5], int_bypasses[1].bits.uop.fu_code[5] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[6], int_bypasses[1].bits.uop.fu_code[6] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[7], int_bypasses[1].bits.uop.fu_code[7] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[8], int_bypasses[1].bits.uop.fu_code[8] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[9], int_bypasses[1].bits.uop.fu_code[9] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[0], int_bypasses[1].bits.uop.iq_type[0] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[1], int_bypasses[1].bits.uop.iq_type[1] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[2], int_bypasses[1].bits.uop.iq_type[2] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[3], int_bypasses[1].bits.uop.iq_type[3] connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_pc, int_bypasses[1].bits.uop.debug_pc connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_rvc, int_bypasses[1].bits.uop.is_rvc connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_inst, int_bypasses[1].bits.uop.debug_inst connect alu_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.inst, int_bypasses[1].bits.uop.inst connect alu_exe_unit_0.io_rrd_irf_bypasses[1].valid, int_bypasses[1].valid connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.fflags.bits, int_bypasses[2].bits.fflags.bits connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.fflags.valid, int_bypasses[2].bits.fflags.valid connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.predicated, int_bypasses[2].bits.predicated connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.data, int_bypasses[2].bits.data connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_tsrc, int_bypasses[2].bits.uop.debug_tsrc connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_fsrc, int_bypasses[2].bits.uop.debug_fsrc connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.bp_xcpt_if, int_bypasses[2].bits.uop.bp_xcpt_if connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.bp_debug_if, int_bypasses[2].bits.uop.bp_debug_if connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.xcpt_ma_if, int_bypasses[2].bits.uop.xcpt_ma_if connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.xcpt_ae_if, int_bypasses[2].bits.uop.xcpt_ae_if connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.xcpt_pf_if, int_bypasses[2].bits.uop.xcpt_pf_if connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_typ, int_bypasses[2].bits.uop.fp_typ connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_rm, int_bypasses[2].bits.uop.fp_rm connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_val, int_bypasses[2].bits.uop.fp_val connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fcn_op, int_bypasses[2].bits.uop.fcn_op connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fcn_dw, int_bypasses[2].bits.uop.fcn_dw connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.frs3_en, int_bypasses[2].bits.uop.frs3_en connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs2_rtype, int_bypasses[2].bits.uop.lrs2_rtype connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs1_rtype, int_bypasses[2].bits.uop.lrs1_rtype connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.dst_rtype, int_bypasses[2].bits.uop.dst_rtype connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs3, int_bypasses[2].bits.uop.lrs3 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs2, int_bypasses[2].bits.uop.lrs2 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs1, int_bypasses[2].bits.uop.lrs1 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ldst, int_bypasses[2].bits.uop.ldst connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ldst_is_rs1, int_bypasses[2].bits.uop.ldst_is_rs1 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.csr_cmd, int_bypasses[2].bits.uop.csr_cmd connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.flush_on_commit, int_bypasses[2].bits.uop.flush_on_commit connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_unique, int_bypasses[2].bits.uop.is_unique connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.uses_stq, int_bypasses[2].bits.uop.uses_stq connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.uses_ldq, int_bypasses[2].bits.uop.uses_ldq connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.mem_signed, int_bypasses[2].bits.uop.mem_signed connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.mem_size, int_bypasses[2].bits.uop.mem_size connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.mem_cmd, int_bypasses[2].bits.uop.mem_cmd connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.exc_cause, int_bypasses[2].bits.uop.exc_cause connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.exception, int_bypasses[2].bits.uop.exception connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.stale_pdst, int_bypasses[2].bits.uop.stale_pdst connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ppred_busy, int_bypasses[2].bits.uop.ppred_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs3_busy, int_bypasses[2].bits.uop.prs3_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs2_busy, int_bypasses[2].bits.uop.prs2_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs1_busy, int_bypasses[2].bits.uop.prs1_busy connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ppred, int_bypasses[2].bits.uop.ppred connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs3, int_bypasses[2].bits.uop.prs3 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs2, int_bypasses[2].bits.uop.prs2 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs1, int_bypasses[2].bits.uop.prs1 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.pdst, int_bypasses[2].bits.uop.pdst connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.rxq_idx, int_bypasses[2].bits.uop.rxq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.stq_idx, int_bypasses[2].bits.uop.stq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ldq_idx, int_bypasses[2].bits.uop.ldq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.rob_idx, int_bypasses[2].bits.uop.rob_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.vec, int_bypasses[2].bits.uop.fp_ctrl.vec connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.wflags, int_bypasses[2].bits.uop.fp_ctrl.wflags connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.sqrt, int_bypasses[2].bits.uop.fp_ctrl.sqrt connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.div, int_bypasses[2].bits.uop.fp_ctrl.div connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fma, int_bypasses[2].bits.uop.fp_ctrl.fma connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fastpipe, int_bypasses[2].bits.uop.fp_ctrl.fastpipe connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.toint, int_bypasses[2].bits.uop.fp_ctrl.toint connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fromint, int_bypasses[2].bits.uop.fp_ctrl.fromint connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.typeTagOut, int_bypasses[2].bits.uop.fp_ctrl.typeTagOut connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.typeTagIn, int_bypasses[2].bits.uop.fp_ctrl.typeTagIn connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.swap23, int_bypasses[2].bits.uop.fp_ctrl.swap23 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.swap12, int_bypasses[2].bits.uop.fp_ctrl.swap12 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren3, int_bypasses[2].bits.uop.fp_ctrl.ren3 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren2, int_bypasses[2].bits.uop.fp_ctrl.ren2 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren1, int_bypasses[2].bits.uop.fp_ctrl.ren1 connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.wen, int_bypasses[2].bits.uop.fp_ctrl.wen connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ldst, int_bypasses[2].bits.uop.fp_ctrl.ldst connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.op2_sel, int_bypasses[2].bits.uop.op2_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.op1_sel, int_bypasses[2].bits.uop.op1_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.imm_packed, int_bypasses[2].bits.uop.imm_packed connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.pimm, int_bypasses[2].bits.uop.pimm connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.imm_sel, int_bypasses[2].bits.uop.imm_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.imm_rename, int_bypasses[2].bits.uop.imm_rename connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.taken, int_bypasses[2].bits.uop.taken connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.pc_lob, int_bypasses[2].bits.uop.pc_lob connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.edge_inst, int_bypasses[2].bits.uop.edge_inst connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ftq_idx, int_bypasses[2].bits.uop.ftq_idx connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_mov, int_bypasses[2].bits.uop.is_mov connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_rocc, int_bypasses[2].bits.uop.is_rocc connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_sys_pc2epc, int_bypasses[2].bits.uop.is_sys_pc2epc connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_eret, int_bypasses[2].bits.uop.is_eret connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_amo, int_bypasses[2].bits.uop.is_amo connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_sfence, int_bypasses[2].bits.uop.is_sfence connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_fencei, int_bypasses[2].bits.uop.is_fencei connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_fence, int_bypasses[2].bits.uop.is_fence connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_sfb, int_bypasses[2].bits.uop.is_sfb connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.br_type, int_bypasses[2].bits.uop.br_type connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.br_tag, int_bypasses[2].bits.uop.br_tag connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.br_mask, int_bypasses[2].bits.uop.br_mask connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.dis_col_sel, int_bypasses[2].bits.uop.dis_col_sel connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p3_bypass_hint, int_bypasses[2].bits.uop.iw_p3_bypass_hint connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p2_bypass_hint, int_bypasses[2].bits.uop.iw_p2_bypass_hint connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p1_bypass_hint, int_bypasses[2].bits.uop.iw_p1_bypass_hint connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p2_speculative_child, int_bypasses[2].bits.uop.iw_p2_speculative_child connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p1_speculative_child, int_bypasses[2].bits.uop.iw_p1_speculative_child connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_issued_partial_dgen, int_bypasses[2].bits.uop.iw_issued_partial_dgen connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_issued_partial_agen, int_bypasses[2].bits.uop.iw_issued_partial_agen connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_issued, int_bypasses[2].bits.uop.iw_issued connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[0], int_bypasses[2].bits.uop.fu_code[0] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[1], int_bypasses[2].bits.uop.fu_code[1] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[2], int_bypasses[2].bits.uop.fu_code[2] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[3], int_bypasses[2].bits.uop.fu_code[3] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[4], int_bypasses[2].bits.uop.fu_code[4] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[5], int_bypasses[2].bits.uop.fu_code[5] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[6], int_bypasses[2].bits.uop.fu_code[6] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[7], int_bypasses[2].bits.uop.fu_code[7] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[8], int_bypasses[2].bits.uop.fu_code[8] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[9], int_bypasses[2].bits.uop.fu_code[9] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[0], int_bypasses[2].bits.uop.iq_type[0] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[1], int_bypasses[2].bits.uop.iq_type[1] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[2], int_bypasses[2].bits.uop.iq_type[2] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[3], int_bypasses[2].bits.uop.iq_type[3] connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_pc, int_bypasses[2].bits.uop.debug_pc connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_rvc, int_bypasses[2].bits.uop.is_rvc connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_inst, int_bypasses[2].bits.uop.debug_inst connect alu_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.inst, int_bypasses[2].bits.uop.inst connect alu_exe_unit_0.io_rrd_irf_bypasses[2].valid, int_bypasses[2].valid connect alu_exe_unit_1.io_rrd_irf_resps[0], iregfile.io.rrd_read_resps[2] connect alu_exe_unit_1.io_rrd_irf_resps[1], iregfile.io.rrd_read_resps[3] connect alu_exe_unit_1.io_rrd_immrf_resp, immregfile.io.rrd_read_resps[1] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.fflags.bits, int_bypasses[0].bits.fflags.bits connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.fflags.valid, int_bypasses[0].bits.fflags.valid connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.predicated, int_bypasses[0].bits.predicated connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.data, int_bypasses[0].bits.data connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.debug_tsrc, int_bypasses[0].bits.uop.debug_tsrc connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.debug_fsrc, int_bypasses[0].bits.uop.debug_fsrc connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.bp_xcpt_if, int_bypasses[0].bits.uop.bp_xcpt_if connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.bp_debug_if, int_bypasses[0].bits.uop.bp_debug_if connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.xcpt_ma_if, int_bypasses[0].bits.uop.xcpt_ma_if connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.xcpt_ae_if, int_bypasses[0].bits.uop.xcpt_ae_if connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.xcpt_pf_if, int_bypasses[0].bits.uop.xcpt_pf_if connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_typ, int_bypasses[0].bits.uop.fp_typ connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_rm, int_bypasses[0].bits.uop.fp_rm connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_val, int_bypasses[0].bits.uop.fp_val connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fcn_op, int_bypasses[0].bits.uop.fcn_op connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fcn_dw, int_bypasses[0].bits.uop.fcn_dw connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.frs3_en, int_bypasses[0].bits.uop.frs3_en connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.lrs2_rtype, int_bypasses[0].bits.uop.lrs2_rtype connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.lrs1_rtype, int_bypasses[0].bits.uop.lrs1_rtype connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.dst_rtype, int_bypasses[0].bits.uop.dst_rtype connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.lrs3, int_bypasses[0].bits.uop.lrs3 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.lrs2, int_bypasses[0].bits.uop.lrs2 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.lrs1, int_bypasses[0].bits.uop.lrs1 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ldst, int_bypasses[0].bits.uop.ldst connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ldst_is_rs1, int_bypasses[0].bits.uop.ldst_is_rs1 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.csr_cmd, int_bypasses[0].bits.uop.csr_cmd connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.flush_on_commit, int_bypasses[0].bits.uop.flush_on_commit connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_unique, int_bypasses[0].bits.uop.is_unique connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.uses_stq, int_bypasses[0].bits.uop.uses_stq connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.uses_ldq, int_bypasses[0].bits.uop.uses_ldq connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.mem_signed, int_bypasses[0].bits.uop.mem_signed connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.mem_size, int_bypasses[0].bits.uop.mem_size connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.mem_cmd, int_bypasses[0].bits.uop.mem_cmd connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.exc_cause, int_bypasses[0].bits.uop.exc_cause connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.exception, int_bypasses[0].bits.uop.exception connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.stale_pdst, int_bypasses[0].bits.uop.stale_pdst connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ppred_busy, int_bypasses[0].bits.uop.ppred_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs3_busy, int_bypasses[0].bits.uop.prs3_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs2_busy, int_bypasses[0].bits.uop.prs2_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs1_busy, int_bypasses[0].bits.uop.prs1_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ppred, int_bypasses[0].bits.uop.ppred connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs3, int_bypasses[0].bits.uop.prs3 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs2, int_bypasses[0].bits.uop.prs2 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs1, int_bypasses[0].bits.uop.prs1 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.pdst, int_bypasses[0].bits.uop.pdst connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.rxq_idx, int_bypasses[0].bits.uop.rxq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.stq_idx, int_bypasses[0].bits.uop.stq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ldq_idx, int_bypasses[0].bits.uop.ldq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.rob_idx, int_bypasses[0].bits.uop.rob_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.vec, int_bypasses[0].bits.uop.fp_ctrl.vec connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.wflags, int_bypasses[0].bits.uop.fp_ctrl.wflags connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.sqrt, int_bypasses[0].bits.uop.fp_ctrl.sqrt connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.div, int_bypasses[0].bits.uop.fp_ctrl.div connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fma, int_bypasses[0].bits.uop.fp_ctrl.fma connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fastpipe, int_bypasses[0].bits.uop.fp_ctrl.fastpipe connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.toint, int_bypasses[0].bits.uop.fp_ctrl.toint connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fromint, int_bypasses[0].bits.uop.fp_ctrl.fromint connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.typeTagOut, int_bypasses[0].bits.uop.fp_ctrl.typeTagOut connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.typeTagIn, int_bypasses[0].bits.uop.fp_ctrl.typeTagIn connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.swap23, int_bypasses[0].bits.uop.fp_ctrl.swap23 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.swap12, int_bypasses[0].bits.uop.fp_ctrl.swap12 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren3, int_bypasses[0].bits.uop.fp_ctrl.ren3 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren2, int_bypasses[0].bits.uop.fp_ctrl.ren2 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren1, int_bypasses[0].bits.uop.fp_ctrl.ren1 connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.wen, int_bypasses[0].bits.uop.fp_ctrl.wen connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ldst, int_bypasses[0].bits.uop.fp_ctrl.ldst connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.op2_sel, int_bypasses[0].bits.uop.op2_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.op1_sel, int_bypasses[0].bits.uop.op1_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.imm_packed, int_bypasses[0].bits.uop.imm_packed connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.pimm, int_bypasses[0].bits.uop.pimm connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.imm_sel, int_bypasses[0].bits.uop.imm_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.imm_rename, int_bypasses[0].bits.uop.imm_rename connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.taken, int_bypasses[0].bits.uop.taken connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.pc_lob, int_bypasses[0].bits.uop.pc_lob connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.edge_inst, int_bypasses[0].bits.uop.edge_inst connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ftq_idx, int_bypasses[0].bits.uop.ftq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_mov, int_bypasses[0].bits.uop.is_mov connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_rocc, int_bypasses[0].bits.uop.is_rocc connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_sys_pc2epc, int_bypasses[0].bits.uop.is_sys_pc2epc connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_eret, int_bypasses[0].bits.uop.is_eret connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_amo, int_bypasses[0].bits.uop.is_amo connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_sfence, int_bypasses[0].bits.uop.is_sfence connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_fencei, int_bypasses[0].bits.uop.is_fencei connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_fence, int_bypasses[0].bits.uop.is_fence connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_sfb, int_bypasses[0].bits.uop.is_sfb connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.br_type, int_bypasses[0].bits.uop.br_type connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.br_tag, int_bypasses[0].bits.uop.br_tag connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.br_mask, int_bypasses[0].bits.uop.br_mask connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.dis_col_sel, int_bypasses[0].bits.uop.dis_col_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_p3_bypass_hint, int_bypasses[0].bits.uop.iw_p3_bypass_hint connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_p2_bypass_hint, int_bypasses[0].bits.uop.iw_p2_bypass_hint connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_p1_bypass_hint, int_bypasses[0].bits.uop.iw_p1_bypass_hint connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_p2_speculative_child, int_bypasses[0].bits.uop.iw_p2_speculative_child connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_p1_speculative_child, int_bypasses[0].bits.uop.iw_p1_speculative_child connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_issued_partial_dgen, int_bypasses[0].bits.uop.iw_issued_partial_dgen connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_issued_partial_agen, int_bypasses[0].bits.uop.iw_issued_partial_agen connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_issued, int_bypasses[0].bits.uop.iw_issued connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[0], int_bypasses[0].bits.uop.fu_code[0] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[1], int_bypasses[0].bits.uop.fu_code[1] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[2], int_bypasses[0].bits.uop.fu_code[2] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[3], int_bypasses[0].bits.uop.fu_code[3] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[4], int_bypasses[0].bits.uop.fu_code[4] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[5], int_bypasses[0].bits.uop.fu_code[5] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[6], int_bypasses[0].bits.uop.fu_code[6] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[7], int_bypasses[0].bits.uop.fu_code[7] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[8], int_bypasses[0].bits.uop.fu_code[8] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[9], int_bypasses[0].bits.uop.fu_code[9] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iq_type[0], int_bypasses[0].bits.uop.iq_type[0] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iq_type[1], int_bypasses[0].bits.uop.iq_type[1] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iq_type[2], int_bypasses[0].bits.uop.iq_type[2] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iq_type[3], int_bypasses[0].bits.uop.iq_type[3] connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.debug_pc, int_bypasses[0].bits.uop.debug_pc connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_rvc, int_bypasses[0].bits.uop.is_rvc connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.debug_inst, int_bypasses[0].bits.uop.debug_inst connect alu_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.inst, int_bypasses[0].bits.uop.inst connect alu_exe_unit_1.io_rrd_irf_bypasses[0].valid, int_bypasses[0].valid connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.fflags.bits, int_bypasses[1].bits.fflags.bits connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.fflags.valid, int_bypasses[1].bits.fflags.valid connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.predicated, int_bypasses[1].bits.predicated connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.data, int_bypasses[1].bits.data connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.debug_tsrc, int_bypasses[1].bits.uop.debug_tsrc connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.debug_fsrc, int_bypasses[1].bits.uop.debug_fsrc connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.bp_xcpt_if, int_bypasses[1].bits.uop.bp_xcpt_if connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.bp_debug_if, int_bypasses[1].bits.uop.bp_debug_if connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.xcpt_ma_if, int_bypasses[1].bits.uop.xcpt_ma_if connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.xcpt_ae_if, int_bypasses[1].bits.uop.xcpt_ae_if connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.xcpt_pf_if, int_bypasses[1].bits.uop.xcpt_pf_if connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_typ, int_bypasses[1].bits.uop.fp_typ connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_rm, int_bypasses[1].bits.uop.fp_rm connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_val, int_bypasses[1].bits.uop.fp_val connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fcn_op, int_bypasses[1].bits.uop.fcn_op connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fcn_dw, int_bypasses[1].bits.uop.fcn_dw connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.frs3_en, int_bypasses[1].bits.uop.frs3_en connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.lrs2_rtype, int_bypasses[1].bits.uop.lrs2_rtype connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.lrs1_rtype, int_bypasses[1].bits.uop.lrs1_rtype connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.dst_rtype, int_bypasses[1].bits.uop.dst_rtype connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.lrs3, int_bypasses[1].bits.uop.lrs3 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.lrs2, int_bypasses[1].bits.uop.lrs2 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.lrs1, int_bypasses[1].bits.uop.lrs1 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ldst, int_bypasses[1].bits.uop.ldst connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ldst_is_rs1, int_bypasses[1].bits.uop.ldst_is_rs1 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.csr_cmd, int_bypasses[1].bits.uop.csr_cmd connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.flush_on_commit, int_bypasses[1].bits.uop.flush_on_commit connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_unique, int_bypasses[1].bits.uop.is_unique connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.uses_stq, int_bypasses[1].bits.uop.uses_stq connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.uses_ldq, int_bypasses[1].bits.uop.uses_ldq connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.mem_signed, int_bypasses[1].bits.uop.mem_signed connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.mem_size, int_bypasses[1].bits.uop.mem_size connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.mem_cmd, int_bypasses[1].bits.uop.mem_cmd connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.exc_cause, int_bypasses[1].bits.uop.exc_cause connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.exception, int_bypasses[1].bits.uop.exception connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.stale_pdst, int_bypasses[1].bits.uop.stale_pdst connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ppred_busy, int_bypasses[1].bits.uop.ppred_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs3_busy, int_bypasses[1].bits.uop.prs3_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs2_busy, int_bypasses[1].bits.uop.prs2_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs1_busy, int_bypasses[1].bits.uop.prs1_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ppred, int_bypasses[1].bits.uop.ppred connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs3, int_bypasses[1].bits.uop.prs3 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs2, int_bypasses[1].bits.uop.prs2 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs1, int_bypasses[1].bits.uop.prs1 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.pdst, int_bypasses[1].bits.uop.pdst connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.rxq_idx, int_bypasses[1].bits.uop.rxq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.stq_idx, int_bypasses[1].bits.uop.stq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ldq_idx, int_bypasses[1].bits.uop.ldq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.rob_idx, int_bypasses[1].bits.uop.rob_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.vec, int_bypasses[1].bits.uop.fp_ctrl.vec connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.wflags, int_bypasses[1].bits.uop.fp_ctrl.wflags connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.sqrt, int_bypasses[1].bits.uop.fp_ctrl.sqrt connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.div, int_bypasses[1].bits.uop.fp_ctrl.div connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fma, int_bypasses[1].bits.uop.fp_ctrl.fma connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fastpipe, int_bypasses[1].bits.uop.fp_ctrl.fastpipe connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.toint, int_bypasses[1].bits.uop.fp_ctrl.toint connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fromint, int_bypasses[1].bits.uop.fp_ctrl.fromint connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.typeTagOut, int_bypasses[1].bits.uop.fp_ctrl.typeTagOut connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.typeTagIn, int_bypasses[1].bits.uop.fp_ctrl.typeTagIn connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.swap23, int_bypasses[1].bits.uop.fp_ctrl.swap23 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.swap12, int_bypasses[1].bits.uop.fp_ctrl.swap12 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren3, int_bypasses[1].bits.uop.fp_ctrl.ren3 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren2, int_bypasses[1].bits.uop.fp_ctrl.ren2 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren1, int_bypasses[1].bits.uop.fp_ctrl.ren1 connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.wen, int_bypasses[1].bits.uop.fp_ctrl.wen connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ldst, int_bypasses[1].bits.uop.fp_ctrl.ldst connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.op2_sel, int_bypasses[1].bits.uop.op2_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.op1_sel, int_bypasses[1].bits.uop.op1_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.imm_packed, int_bypasses[1].bits.uop.imm_packed connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.pimm, int_bypasses[1].bits.uop.pimm connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.imm_sel, int_bypasses[1].bits.uop.imm_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.imm_rename, int_bypasses[1].bits.uop.imm_rename connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.taken, int_bypasses[1].bits.uop.taken connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.pc_lob, int_bypasses[1].bits.uop.pc_lob connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.edge_inst, int_bypasses[1].bits.uop.edge_inst connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ftq_idx, int_bypasses[1].bits.uop.ftq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_mov, int_bypasses[1].bits.uop.is_mov connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_rocc, int_bypasses[1].bits.uop.is_rocc connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_sys_pc2epc, int_bypasses[1].bits.uop.is_sys_pc2epc connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_eret, int_bypasses[1].bits.uop.is_eret connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_amo, int_bypasses[1].bits.uop.is_amo connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_sfence, int_bypasses[1].bits.uop.is_sfence connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_fencei, int_bypasses[1].bits.uop.is_fencei connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_fence, int_bypasses[1].bits.uop.is_fence connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_sfb, int_bypasses[1].bits.uop.is_sfb connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.br_type, int_bypasses[1].bits.uop.br_type connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.br_tag, int_bypasses[1].bits.uop.br_tag connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.br_mask, int_bypasses[1].bits.uop.br_mask connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.dis_col_sel, int_bypasses[1].bits.uop.dis_col_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_p3_bypass_hint, int_bypasses[1].bits.uop.iw_p3_bypass_hint connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_p2_bypass_hint, int_bypasses[1].bits.uop.iw_p2_bypass_hint connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_p1_bypass_hint, int_bypasses[1].bits.uop.iw_p1_bypass_hint connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_p2_speculative_child, int_bypasses[1].bits.uop.iw_p2_speculative_child connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_p1_speculative_child, int_bypasses[1].bits.uop.iw_p1_speculative_child connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_issued_partial_dgen, int_bypasses[1].bits.uop.iw_issued_partial_dgen connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_issued_partial_agen, int_bypasses[1].bits.uop.iw_issued_partial_agen connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_issued, int_bypasses[1].bits.uop.iw_issued connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[0], int_bypasses[1].bits.uop.fu_code[0] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[1], int_bypasses[1].bits.uop.fu_code[1] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[2], int_bypasses[1].bits.uop.fu_code[2] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[3], int_bypasses[1].bits.uop.fu_code[3] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[4], int_bypasses[1].bits.uop.fu_code[4] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[5], int_bypasses[1].bits.uop.fu_code[5] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[6], int_bypasses[1].bits.uop.fu_code[6] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[7], int_bypasses[1].bits.uop.fu_code[7] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[8], int_bypasses[1].bits.uop.fu_code[8] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[9], int_bypasses[1].bits.uop.fu_code[9] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iq_type[0], int_bypasses[1].bits.uop.iq_type[0] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iq_type[1], int_bypasses[1].bits.uop.iq_type[1] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iq_type[2], int_bypasses[1].bits.uop.iq_type[2] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iq_type[3], int_bypasses[1].bits.uop.iq_type[3] connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.debug_pc, int_bypasses[1].bits.uop.debug_pc connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_rvc, int_bypasses[1].bits.uop.is_rvc connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.debug_inst, int_bypasses[1].bits.uop.debug_inst connect alu_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.inst, int_bypasses[1].bits.uop.inst connect alu_exe_unit_1.io_rrd_irf_bypasses[1].valid, int_bypasses[1].valid connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.fflags.bits, int_bypasses[2].bits.fflags.bits connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.fflags.valid, int_bypasses[2].bits.fflags.valid connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.predicated, int_bypasses[2].bits.predicated connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.data, int_bypasses[2].bits.data connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.debug_tsrc, int_bypasses[2].bits.uop.debug_tsrc connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.debug_fsrc, int_bypasses[2].bits.uop.debug_fsrc connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.bp_xcpt_if, int_bypasses[2].bits.uop.bp_xcpt_if connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.bp_debug_if, int_bypasses[2].bits.uop.bp_debug_if connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.xcpt_ma_if, int_bypasses[2].bits.uop.xcpt_ma_if connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.xcpt_ae_if, int_bypasses[2].bits.uop.xcpt_ae_if connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.xcpt_pf_if, int_bypasses[2].bits.uop.xcpt_pf_if connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_typ, int_bypasses[2].bits.uop.fp_typ connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_rm, int_bypasses[2].bits.uop.fp_rm connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_val, int_bypasses[2].bits.uop.fp_val connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fcn_op, int_bypasses[2].bits.uop.fcn_op connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fcn_dw, int_bypasses[2].bits.uop.fcn_dw connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.frs3_en, int_bypasses[2].bits.uop.frs3_en connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.lrs2_rtype, int_bypasses[2].bits.uop.lrs2_rtype connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.lrs1_rtype, int_bypasses[2].bits.uop.lrs1_rtype connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.dst_rtype, int_bypasses[2].bits.uop.dst_rtype connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.lrs3, int_bypasses[2].bits.uop.lrs3 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.lrs2, int_bypasses[2].bits.uop.lrs2 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.lrs1, int_bypasses[2].bits.uop.lrs1 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ldst, int_bypasses[2].bits.uop.ldst connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ldst_is_rs1, int_bypasses[2].bits.uop.ldst_is_rs1 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.csr_cmd, int_bypasses[2].bits.uop.csr_cmd connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.flush_on_commit, int_bypasses[2].bits.uop.flush_on_commit connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_unique, int_bypasses[2].bits.uop.is_unique connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.uses_stq, int_bypasses[2].bits.uop.uses_stq connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.uses_ldq, int_bypasses[2].bits.uop.uses_ldq connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.mem_signed, int_bypasses[2].bits.uop.mem_signed connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.mem_size, int_bypasses[2].bits.uop.mem_size connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.mem_cmd, int_bypasses[2].bits.uop.mem_cmd connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.exc_cause, int_bypasses[2].bits.uop.exc_cause connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.exception, int_bypasses[2].bits.uop.exception connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.stale_pdst, int_bypasses[2].bits.uop.stale_pdst connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ppred_busy, int_bypasses[2].bits.uop.ppred_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs3_busy, int_bypasses[2].bits.uop.prs3_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs2_busy, int_bypasses[2].bits.uop.prs2_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs1_busy, int_bypasses[2].bits.uop.prs1_busy connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ppred, int_bypasses[2].bits.uop.ppred connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs3, int_bypasses[2].bits.uop.prs3 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs2, int_bypasses[2].bits.uop.prs2 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs1, int_bypasses[2].bits.uop.prs1 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.pdst, int_bypasses[2].bits.uop.pdst connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.rxq_idx, int_bypasses[2].bits.uop.rxq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.stq_idx, int_bypasses[2].bits.uop.stq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ldq_idx, int_bypasses[2].bits.uop.ldq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.rob_idx, int_bypasses[2].bits.uop.rob_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.vec, int_bypasses[2].bits.uop.fp_ctrl.vec connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.wflags, int_bypasses[2].bits.uop.fp_ctrl.wflags connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.sqrt, int_bypasses[2].bits.uop.fp_ctrl.sqrt connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.div, int_bypasses[2].bits.uop.fp_ctrl.div connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fma, int_bypasses[2].bits.uop.fp_ctrl.fma connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fastpipe, int_bypasses[2].bits.uop.fp_ctrl.fastpipe connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.toint, int_bypasses[2].bits.uop.fp_ctrl.toint connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fromint, int_bypasses[2].bits.uop.fp_ctrl.fromint connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.typeTagOut, int_bypasses[2].bits.uop.fp_ctrl.typeTagOut connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.typeTagIn, int_bypasses[2].bits.uop.fp_ctrl.typeTagIn connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.swap23, int_bypasses[2].bits.uop.fp_ctrl.swap23 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.swap12, int_bypasses[2].bits.uop.fp_ctrl.swap12 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren3, int_bypasses[2].bits.uop.fp_ctrl.ren3 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren2, int_bypasses[2].bits.uop.fp_ctrl.ren2 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren1, int_bypasses[2].bits.uop.fp_ctrl.ren1 connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.wen, int_bypasses[2].bits.uop.fp_ctrl.wen connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ldst, int_bypasses[2].bits.uop.fp_ctrl.ldst connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.op2_sel, int_bypasses[2].bits.uop.op2_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.op1_sel, int_bypasses[2].bits.uop.op1_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.imm_packed, int_bypasses[2].bits.uop.imm_packed connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.pimm, int_bypasses[2].bits.uop.pimm connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.imm_sel, int_bypasses[2].bits.uop.imm_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.imm_rename, int_bypasses[2].bits.uop.imm_rename connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.taken, int_bypasses[2].bits.uop.taken connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.pc_lob, int_bypasses[2].bits.uop.pc_lob connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.edge_inst, int_bypasses[2].bits.uop.edge_inst connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ftq_idx, int_bypasses[2].bits.uop.ftq_idx connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_mov, int_bypasses[2].bits.uop.is_mov connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_rocc, int_bypasses[2].bits.uop.is_rocc connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_sys_pc2epc, int_bypasses[2].bits.uop.is_sys_pc2epc connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_eret, int_bypasses[2].bits.uop.is_eret connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_amo, int_bypasses[2].bits.uop.is_amo connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_sfence, int_bypasses[2].bits.uop.is_sfence connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_fencei, int_bypasses[2].bits.uop.is_fencei connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_fence, int_bypasses[2].bits.uop.is_fence connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_sfb, int_bypasses[2].bits.uop.is_sfb connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.br_type, int_bypasses[2].bits.uop.br_type connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.br_tag, int_bypasses[2].bits.uop.br_tag connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.br_mask, int_bypasses[2].bits.uop.br_mask connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.dis_col_sel, int_bypasses[2].bits.uop.dis_col_sel connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_p3_bypass_hint, int_bypasses[2].bits.uop.iw_p3_bypass_hint connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_p2_bypass_hint, int_bypasses[2].bits.uop.iw_p2_bypass_hint connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_p1_bypass_hint, int_bypasses[2].bits.uop.iw_p1_bypass_hint connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_p2_speculative_child, int_bypasses[2].bits.uop.iw_p2_speculative_child connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_p1_speculative_child, int_bypasses[2].bits.uop.iw_p1_speculative_child connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_issued_partial_dgen, int_bypasses[2].bits.uop.iw_issued_partial_dgen connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_issued_partial_agen, int_bypasses[2].bits.uop.iw_issued_partial_agen connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_issued, int_bypasses[2].bits.uop.iw_issued connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[0], int_bypasses[2].bits.uop.fu_code[0] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[1], int_bypasses[2].bits.uop.fu_code[1] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[2], int_bypasses[2].bits.uop.fu_code[2] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[3], int_bypasses[2].bits.uop.fu_code[3] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[4], int_bypasses[2].bits.uop.fu_code[4] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[5], int_bypasses[2].bits.uop.fu_code[5] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[6], int_bypasses[2].bits.uop.fu_code[6] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[7], int_bypasses[2].bits.uop.fu_code[7] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[8], int_bypasses[2].bits.uop.fu_code[8] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[9], int_bypasses[2].bits.uop.fu_code[9] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iq_type[0], int_bypasses[2].bits.uop.iq_type[0] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iq_type[1], int_bypasses[2].bits.uop.iq_type[1] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iq_type[2], int_bypasses[2].bits.uop.iq_type[2] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iq_type[3], int_bypasses[2].bits.uop.iq_type[3] connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.debug_pc, int_bypasses[2].bits.uop.debug_pc connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_rvc, int_bypasses[2].bits.uop.is_rvc connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.debug_inst, int_bypasses[2].bits.uop.debug_inst connect alu_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.inst, int_bypasses[2].bits.uop.inst connect alu_exe_unit_1.io_rrd_irf_bypasses[2].valid, int_bypasses[2].valid connect mem_exe_unit_0.io_rrd_irf_resps[0], iregfile.io.rrd_read_resps[4] connect mem_exe_unit_0.io_rrd_immrf_resp, immregfile.io.rrd_read_resps[2] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.fflags.bits, int_bypasses[0].bits.fflags.bits connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.fflags.valid, int_bypasses[0].bits.fflags.valid connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.predicated, int_bypasses[0].bits.predicated connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.data, int_bypasses[0].bits.data connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_tsrc, int_bypasses[0].bits.uop.debug_tsrc connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_fsrc, int_bypasses[0].bits.uop.debug_fsrc connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.bp_xcpt_if, int_bypasses[0].bits.uop.bp_xcpt_if connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.bp_debug_if, int_bypasses[0].bits.uop.bp_debug_if connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.xcpt_ma_if, int_bypasses[0].bits.uop.xcpt_ma_if connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.xcpt_ae_if, int_bypasses[0].bits.uop.xcpt_ae_if connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.xcpt_pf_if, int_bypasses[0].bits.uop.xcpt_pf_if connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_typ, int_bypasses[0].bits.uop.fp_typ connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_rm, int_bypasses[0].bits.uop.fp_rm connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_val, int_bypasses[0].bits.uop.fp_val connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fcn_op, int_bypasses[0].bits.uop.fcn_op connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fcn_dw, int_bypasses[0].bits.uop.fcn_dw connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.frs3_en, int_bypasses[0].bits.uop.frs3_en connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs2_rtype, int_bypasses[0].bits.uop.lrs2_rtype connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs1_rtype, int_bypasses[0].bits.uop.lrs1_rtype connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.dst_rtype, int_bypasses[0].bits.uop.dst_rtype connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs3, int_bypasses[0].bits.uop.lrs3 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs2, int_bypasses[0].bits.uop.lrs2 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs1, int_bypasses[0].bits.uop.lrs1 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ldst, int_bypasses[0].bits.uop.ldst connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ldst_is_rs1, int_bypasses[0].bits.uop.ldst_is_rs1 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.csr_cmd, int_bypasses[0].bits.uop.csr_cmd connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.flush_on_commit, int_bypasses[0].bits.uop.flush_on_commit connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_unique, int_bypasses[0].bits.uop.is_unique connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.uses_stq, int_bypasses[0].bits.uop.uses_stq connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.uses_ldq, int_bypasses[0].bits.uop.uses_ldq connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.mem_signed, int_bypasses[0].bits.uop.mem_signed connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.mem_size, int_bypasses[0].bits.uop.mem_size connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.mem_cmd, int_bypasses[0].bits.uop.mem_cmd connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.exc_cause, int_bypasses[0].bits.uop.exc_cause connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.exception, int_bypasses[0].bits.uop.exception connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.stale_pdst, int_bypasses[0].bits.uop.stale_pdst connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ppred_busy, int_bypasses[0].bits.uop.ppred_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs3_busy, int_bypasses[0].bits.uop.prs3_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs2_busy, int_bypasses[0].bits.uop.prs2_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs1_busy, int_bypasses[0].bits.uop.prs1_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ppred, int_bypasses[0].bits.uop.ppred connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs3, int_bypasses[0].bits.uop.prs3 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs2, int_bypasses[0].bits.uop.prs2 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs1, int_bypasses[0].bits.uop.prs1 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.pdst, int_bypasses[0].bits.uop.pdst connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.rxq_idx, int_bypasses[0].bits.uop.rxq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.stq_idx, int_bypasses[0].bits.uop.stq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ldq_idx, int_bypasses[0].bits.uop.ldq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.rob_idx, int_bypasses[0].bits.uop.rob_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.vec, int_bypasses[0].bits.uop.fp_ctrl.vec connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.wflags, int_bypasses[0].bits.uop.fp_ctrl.wflags connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.sqrt, int_bypasses[0].bits.uop.fp_ctrl.sqrt connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.div, int_bypasses[0].bits.uop.fp_ctrl.div connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fma, int_bypasses[0].bits.uop.fp_ctrl.fma connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fastpipe, int_bypasses[0].bits.uop.fp_ctrl.fastpipe connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.toint, int_bypasses[0].bits.uop.fp_ctrl.toint connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fromint, int_bypasses[0].bits.uop.fp_ctrl.fromint connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.typeTagOut, int_bypasses[0].bits.uop.fp_ctrl.typeTagOut connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.typeTagIn, int_bypasses[0].bits.uop.fp_ctrl.typeTagIn connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.swap23, int_bypasses[0].bits.uop.fp_ctrl.swap23 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.swap12, int_bypasses[0].bits.uop.fp_ctrl.swap12 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren3, int_bypasses[0].bits.uop.fp_ctrl.ren3 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren2, int_bypasses[0].bits.uop.fp_ctrl.ren2 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren1, int_bypasses[0].bits.uop.fp_ctrl.ren1 connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.wen, int_bypasses[0].bits.uop.fp_ctrl.wen connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ldst, int_bypasses[0].bits.uop.fp_ctrl.ldst connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.op2_sel, int_bypasses[0].bits.uop.op2_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.op1_sel, int_bypasses[0].bits.uop.op1_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.imm_packed, int_bypasses[0].bits.uop.imm_packed connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.pimm, int_bypasses[0].bits.uop.pimm connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.imm_sel, int_bypasses[0].bits.uop.imm_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.imm_rename, int_bypasses[0].bits.uop.imm_rename connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.taken, int_bypasses[0].bits.uop.taken connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.pc_lob, int_bypasses[0].bits.uop.pc_lob connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.edge_inst, int_bypasses[0].bits.uop.edge_inst connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ftq_idx, int_bypasses[0].bits.uop.ftq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_mov, int_bypasses[0].bits.uop.is_mov connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_rocc, int_bypasses[0].bits.uop.is_rocc connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_sys_pc2epc, int_bypasses[0].bits.uop.is_sys_pc2epc connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_eret, int_bypasses[0].bits.uop.is_eret connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_amo, int_bypasses[0].bits.uop.is_amo connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_sfence, int_bypasses[0].bits.uop.is_sfence connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_fencei, int_bypasses[0].bits.uop.is_fencei connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_fence, int_bypasses[0].bits.uop.is_fence connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_sfb, int_bypasses[0].bits.uop.is_sfb connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.br_type, int_bypasses[0].bits.uop.br_type connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.br_tag, int_bypasses[0].bits.uop.br_tag connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.br_mask, int_bypasses[0].bits.uop.br_mask connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.dis_col_sel, int_bypasses[0].bits.uop.dis_col_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p3_bypass_hint, int_bypasses[0].bits.uop.iw_p3_bypass_hint connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p2_bypass_hint, int_bypasses[0].bits.uop.iw_p2_bypass_hint connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p1_bypass_hint, int_bypasses[0].bits.uop.iw_p1_bypass_hint connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p2_speculative_child, int_bypasses[0].bits.uop.iw_p2_speculative_child connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p1_speculative_child, int_bypasses[0].bits.uop.iw_p1_speculative_child connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_issued_partial_dgen, int_bypasses[0].bits.uop.iw_issued_partial_dgen connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_issued_partial_agen, int_bypasses[0].bits.uop.iw_issued_partial_agen connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_issued, int_bypasses[0].bits.uop.iw_issued connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[0], int_bypasses[0].bits.uop.fu_code[0] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[1], int_bypasses[0].bits.uop.fu_code[1] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[2], int_bypasses[0].bits.uop.fu_code[2] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[3], int_bypasses[0].bits.uop.fu_code[3] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[4], int_bypasses[0].bits.uop.fu_code[4] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[5], int_bypasses[0].bits.uop.fu_code[5] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[6], int_bypasses[0].bits.uop.fu_code[6] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[7], int_bypasses[0].bits.uop.fu_code[7] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[8], int_bypasses[0].bits.uop.fu_code[8] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[9], int_bypasses[0].bits.uop.fu_code[9] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[0], int_bypasses[0].bits.uop.iq_type[0] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[1], int_bypasses[0].bits.uop.iq_type[1] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[2], int_bypasses[0].bits.uop.iq_type[2] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[3], int_bypasses[0].bits.uop.iq_type[3] connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_pc, int_bypasses[0].bits.uop.debug_pc connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_rvc, int_bypasses[0].bits.uop.is_rvc connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_inst, int_bypasses[0].bits.uop.debug_inst connect mem_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.inst, int_bypasses[0].bits.uop.inst connect mem_exe_unit_0.io_rrd_irf_bypasses[0].valid, int_bypasses[0].valid connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.fflags.bits, int_bypasses[1].bits.fflags.bits connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.fflags.valid, int_bypasses[1].bits.fflags.valid connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.predicated, int_bypasses[1].bits.predicated connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.data, int_bypasses[1].bits.data connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_tsrc, int_bypasses[1].bits.uop.debug_tsrc connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_fsrc, int_bypasses[1].bits.uop.debug_fsrc connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.bp_xcpt_if, int_bypasses[1].bits.uop.bp_xcpt_if connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.bp_debug_if, int_bypasses[1].bits.uop.bp_debug_if connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.xcpt_ma_if, int_bypasses[1].bits.uop.xcpt_ma_if connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.xcpt_ae_if, int_bypasses[1].bits.uop.xcpt_ae_if connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.xcpt_pf_if, int_bypasses[1].bits.uop.xcpt_pf_if connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_typ, int_bypasses[1].bits.uop.fp_typ connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_rm, int_bypasses[1].bits.uop.fp_rm connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_val, int_bypasses[1].bits.uop.fp_val connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fcn_op, int_bypasses[1].bits.uop.fcn_op connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fcn_dw, int_bypasses[1].bits.uop.fcn_dw connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.frs3_en, int_bypasses[1].bits.uop.frs3_en connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs2_rtype, int_bypasses[1].bits.uop.lrs2_rtype connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs1_rtype, int_bypasses[1].bits.uop.lrs1_rtype connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.dst_rtype, int_bypasses[1].bits.uop.dst_rtype connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs3, int_bypasses[1].bits.uop.lrs3 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs2, int_bypasses[1].bits.uop.lrs2 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs1, int_bypasses[1].bits.uop.lrs1 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ldst, int_bypasses[1].bits.uop.ldst connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ldst_is_rs1, int_bypasses[1].bits.uop.ldst_is_rs1 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.csr_cmd, int_bypasses[1].bits.uop.csr_cmd connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.flush_on_commit, int_bypasses[1].bits.uop.flush_on_commit connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_unique, int_bypasses[1].bits.uop.is_unique connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.uses_stq, int_bypasses[1].bits.uop.uses_stq connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.uses_ldq, int_bypasses[1].bits.uop.uses_ldq connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.mem_signed, int_bypasses[1].bits.uop.mem_signed connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.mem_size, int_bypasses[1].bits.uop.mem_size connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.mem_cmd, int_bypasses[1].bits.uop.mem_cmd connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.exc_cause, int_bypasses[1].bits.uop.exc_cause connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.exception, int_bypasses[1].bits.uop.exception connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.stale_pdst, int_bypasses[1].bits.uop.stale_pdst connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ppred_busy, int_bypasses[1].bits.uop.ppred_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs3_busy, int_bypasses[1].bits.uop.prs3_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs2_busy, int_bypasses[1].bits.uop.prs2_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs1_busy, int_bypasses[1].bits.uop.prs1_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ppred, int_bypasses[1].bits.uop.ppred connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs3, int_bypasses[1].bits.uop.prs3 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs2, int_bypasses[1].bits.uop.prs2 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs1, int_bypasses[1].bits.uop.prs1 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.pdst, int_bypasses[1].bits.uop.pdst connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.rxq_idx, int_bypasses[1].bits.uop.rxq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.stq_idx, int_bypasses[1].bits.uop.stq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ldq_idx, int_bypasses[1].bits.uop.ldq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.rob_idx, int_bypasses[1].bits.uop.rob_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.vec, int_bypasses[1].bits.uop.fp_ctrl.vec connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.wflags, int_bypasses[1].bits.uop.fp_ctrl.wflags connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.sqrt, int_bypasses[1].bits.uop.fp_ctrl.sqrt connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.div, int_bypasses[1].bits.uop.fp_ctrl.div connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fma, int_bypasses[1].bits.uop.fp_ctrl.fma connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fastpipe, int_bypasses[1].bits.uop.fp_ctrl.fastpipe connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.toint, int_bypasses[1].bits.uop.fp_ctrl.toint connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fromint, int_bypasses[1].bits.uop.fp_ctrl.fromint connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.typeTagOut, int_bypasses[1].bits.uop.fp_ctrl.typeTagOut connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.typeTagIn, int_bypasses[1].bits.uop.fp_ctrl.typeTagIn connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.swap23, int_bypasses[1].bits.uop.fp_ctrl.swap23 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.swap12, int_bypasses[1].bits.uop.fp_ctrl.swap12 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren3, int_bypasses[1].bits.uop.fp_ctrl.ren3 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren2, int_bypasses[1].bits.uop.fp_ctrl.ren2 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren1, int_bypasses[1].bits.uop.fp_ctrl.ren1 connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.wen, int_bypasses[1].bits.uop.fp_ctrl.wen connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ldst, int_bypasses[1].bits.uop.fp_ctrl.ldst connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.op2_sel, int_bypasses[1].bits.uop.op2_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.op1_sel, int_bypasses[1].bits.uop.op1_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.imm_packed, int_bypasses[1].bits.uop.imm_packed connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.pimm, int_bypasses[1].bits.uop.pimm connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.imm_sel, int_bypasses[1].bits.uop.imm_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.imm_rename, int_bypasses[1].bits.uop.imm_rename connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.taken, int_bypasses[1].bits.uop.taken connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.pc_lob, int_bypasses[1].bits.uop.pc_lob connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.edge_inst, int_bypasses[1].bits.uop.edge_inst connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ftq_idx, int_bypasses[1].bits.uop.ftq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_mov, int_bypasses[1].bits.uop.is_mov connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_rocc, int_bypasses[1].bits.uop.is_rocc connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_sys_pc2epc, int_bypasses[1].bits.uop.is_sys_pc2epc connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_eret, int_bypasses[1].bits.uop.is_eret connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_amo, int_bypasses[1].bits.uop.is_amo connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_sfence, int_bypasses[1].bits.uop.is_sfence connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_fencei, int_bypasses[1].bits.uop.is_fencei connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_fence, int_bypasses[1].bits.uop.is_fence connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_sfb, int_bypasses[1].bits.uop.is_sfb connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.br_type, int_bypasses[1].bits.uop.br_type connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.br_tag, int_bypasses[1].bits.uop.br_tag connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.br_mask, int_bypasses[1].bits.uop.br_mask connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.dis_col_sel, int_bypasses[1].bits.uop.dis_col_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p3_bypass_hint, int_bypasses[1].bits.uop.iw_p3_bypass_hint connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p2_bypass_hint, int_bypasses[1].bits.uop.iw_p2_bypass_hint connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p1_bypass_hint, int_bypasses[1].bits.uop.iw_p1_bypass_hint connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p2_speculative_child, int_bypasses[1].bits.uop.iw_p2_speculative_child connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p1_speculative_child, int_bypasses[1].bits.uop.iw_p1_speculative_child connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_issued_partial_dgen, int_bypasses[1].bits.uop.iw_issued_partial_dgen connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_issued_partial_agen, int_bypasses[1].bits.uop.iw_issued_partial_agen connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_issued, int_bypasses[1].bits.uop.iw_issued connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[0], int_bypasses[1].bits.uop.fu_code[0] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[1], int_bypasses[1].bits.uop.fu_code[1] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[2], int_bypasses[1].bits.uop.fu_code[2] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[3], int_bypasses[1].bits.uop.fu_code[3] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[4], int_bypasses[1].bits.uop.fu_code[4] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[5], int_bypasses[1].bits.uop.fu_code[5] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[6], int_bypasses[1].bits.uop.fu_code[6] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[7], int_bypasses[1].bits.uop.fu_code[7] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[8], int_bypasses[1].bits.uop.fu_code[8] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[9], int_bypasses[1].bits.uop.fu_code[9] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[0], int_bypasses[1].bits.uop.iq_type[0] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[1], int_bypasses[1].bits.uop.iq_type[1] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[2], int_bypasses[1].bits.uop.iq_type[2] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[3], int_bypasses[1].bits.uop.iq_type[3] connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_pc, int_bypasses[1].bits.uop.debug_pc connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_rvc, int_bypasses[1].bits.uop.is_rvc connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_inst, int_bypasses[1].bits.uop.debug_inst connect mem_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.inst, int_bypasses[1].bits.uop.inst connect mem_exe_unit_0.io_rrd_irf_bypasses[1].valid, int_bypasses[1].valid connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.fflags.bits, int_bypasses[2].bits.fflags.bits connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.fflags.valid, int_bypasses[2].bits.fflags.valid connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.predicated, int_bypasses[2].bits.predicated connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.data, int_bypasses[2].bits.data connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_tsrc, int_bypasses[2].bits.uop.debug_tsrc connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_fsrc, int_bypasses[2].bits.uop.debug_fsrc connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.bp_xcpt_if, int_bypasses[2].bits.uop.bp_xcpt_if connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.bp_debug_if, int_bypasses[2].bits.uop.bp_debug_if connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.xcpt_ma_if, int_bypasses[2].bits.uop.xcpt_ma_if connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.xcpt_ae_if, int_bypasses[2].bits.uop.xcpt_ae_if connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.xcpt_pf_if, int_bypasses[2].bits.uop.xcpt_pf_if connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_typ, int_bypasses[2].bits.uop.fp_typ connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_rm, int_bypasses[2].bits.uop.fp_rm connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_val, int_bypasses[2].bits.uop.fp_val connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fcn_op, int_bypasses[2].bits.uop.fcn_op connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fcn_dw, int_bypasses[2].bits.uop.fcn_dw connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.frs3_en, int_bypasses[2].bits.uop.frs3_en connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs2_rtype, int_bypasses[2].bits.uop.lrs2_rtype connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs1_rtype, int_bypasses[2].bits.uop.lrs1_rtype connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.dst_rtype, int_bypasses[2].bits.uop.dst_rtype connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs3, int_bypasses[2].bits.uop.lrs3 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs2, int_bypasses[2].bits.uop.lrs2 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs1, int_bypasses[2].bits.uop.lrs1 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ldst, int_bypasses[2].bits.uop.ldst connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ldst_is_rs1, int_bypasses[2].bits.uop.ldst_is_rs1 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.csr_cmd, int_bypasses[2].bits.uop.csr_cmd connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.flush_on_commit, int_bypasses[2].bits.uop.flush_on_commit connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_unique, int_bypasses[2].bits.uop.is_unique connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.uses_stq, int_bypasses[2].bits.uop.uses_stq connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.uses_ldq, int_bypasses[2].bits.uop.uses_ldq connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.mem_signed, int_bypasses[2].bits.uop.mem_signed connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.mem_size, int_bypasses[2].bits.uop.mem_size connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.mem_cmd, int_bypasses[2].bits.uop.mem_cmd connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.exc_cause, int_bypasses[2].bits.uop.exc_cause connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.exception, int_bypasses[2].bits.uop.exception connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.stale_pdst, int_bypasses[2].bits.uop.stale_pdst connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ppred_busy, int_bypasses[2].bits.uop.ppred_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs3_busy, int_bypasses[2].bits.uop.prs3_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs2_busy, int_bypasses[2].bits.uop.prs2_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs1_busy, int_bypasses[2].bits.uop.prs1_busy connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ppred, int_bypasses[2].bits.uop.ppred connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs3, int_bypasses[2].bits.uop.prs3 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs2, int_bypasses[2].bits.uop.prs2 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs1, int_bypasses[2].bits.uop.prs1 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.pdst, int_bypasses[2].bits.uop.pdst connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.rxq_idx, int_bypasses[2].bits.uop.rxq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.stq_idx, int_bypasses[2].bits.uop.stq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ldq_idx, int_bypasses[2].bits.uop.ldq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.rob_idx, int_bypasses[2].bits.uop.rob_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.vec, int_bypasses[2].bits.uop.fp_ctrl.vec connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.wflags, int_bypasses[2].bits.uop.fp_ctrl.wflags connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.sqrt, int_bypasses[2].bits.uop.fp_ctrl.sqrt connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.div, int_bypasses[2].bits.uop.fp_ctrl.div connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fma, int_bypasses[2].bits.uop.fp_ctrl.fma connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fastpipe, int_bypasses[2].bits.uop.fp_ctrl.fastpipe connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.toint, int_bypasses[2].bits.uop.fp_ctrl.toint connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fromint, int_bypasses[2].bits.uop.fp_ctrl.fromint connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.typeTagOut, int_bypasses[2].bits.uop.fp_ctrl.typeTagOut connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.typeTagIn, int_bypasses[2].bits.uop.fp_ctrl.typeTagIn connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.swap23, int_bypasses[2].bits.uop.fp_ctrl.swap23 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.swap12, int_bypasses[2].bits.uop.fp_ctrl.swap12 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren3, int_bypasses[2].bits.uop.fp_ctrl.ren3 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren2, int_bypasses[2].bits.uop.fp_ctrl.ren2 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren1, int_bypasses[2].bits.uop.fp_ctrl.ren1 connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.wen, int_bypasses[2].bits.uop.fp_ctrl.wen connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ldst, int_bypasses[2].bits.uop.fp_ctrl.ldst connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.op2_sel, int_bypasses[2].bits.uop.op2_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.op1_sel, int_bypasses[2].bits.uop.op1_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.imm_packed, int_bypasses[2].bits.uop.imm_packed connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.pimm, int_bypasses[2].bits.uop.pimm connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.imm_sel, int_bypasses[2].bits.uop.imm_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.imm_rename, int_bypasses[2].bits.uop.imm_rename connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.taken, int_bypasses[2].bits.uop.taken connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.pc_lob, int_bypasses[2].bits.uop.pc_lob connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.edge_inst, int_bypasses[2].bits.uop.edge_inst connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ftq_idx, int_bypasses[2].bits.uop.ftq_idx connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_mov, int_bypasses[2].bits.uop.is_mov connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_rocc, int_bypasses[2].bits.uop.is_rocc connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_sys_pc2epc, int_bypasses[2].bits.uop.is_sys_pc2epc connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_eret, int_bypasses[2].bits.uop.is_eret connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_amo, int_bypasses[2].bits.uop.is_amo connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_sfence, int_bypasses[2].bits.uop.is_sfence connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_fencei, int_bypasses[2].bits.uop.is_fencei connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_fence, int_bypasses[2].bits.uop.is_fence connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_sfb, int_bypasses[2].bits.uop.is_sfb connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.br_type, int_bypasses[2].bits.uop.br_type connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.br_tag, int_bypasses[2].bits.uop.br_tag connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.br_mask, int_bypasses[2].bits.uop.br_mask connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.dis_col_sel, int_bypasses[2].bits.uop.dis_col_sel connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p3_bypass_hint, int_bypasses[2].bits.uop.iw_p3_bypass_hint connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p2_bypass_hint, int_bypasses[2].bits.uop.iw_p2_bypass_hint connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p1_bypass_hint, int_bypasses[2].bits.uop.iw_p1_bypass_hint connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p2_speculative_child, int_bypasses[2].bits.uop.iw_p2_speculative_child connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p1_speculative_child, int_bypasses[2].bits.uop.iw_p1_speculative_child connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_issued_partial_dgen, int_bypasses[2].bits.uop.iw_issued_partial_dgen connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_issued_partial_agen, int_bypasses[2].bits.uop.iw_issued_partial_agen connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_issued, int_bypasses[2].bits.uop.iw_issued connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[0], int_bypasses[2].bits.uop.fu_code[0] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[1], int_bypasses[2].bits.uop.fu_code[1] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[2], int_bypasses[2].bits.uop.fu_code[2] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[3], int_bypasses[2].bits.uop.fu_code[3] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[4], int_bypasses[2].bits.uop.fu_code[4] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[5], int_bypasses[2].bits.uop.fu_code[5] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[6], int_bypasses[2].bits.uop.fu_code[6] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[7], int_bypasses[2].bits.uop.fu_code[7] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[8], int_bypasses[2].bits.uop.fu_code[8] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[9], int_bypasses[2].bits.uop.fu_code[9] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[0], int_bypasses[2].bits.uop.iq_type[0] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[1], int_bypasses[2].bits.uop.iq_type[1] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[2], int_bypasses[2].bits.uop.iq_type[2] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[3], int_bypasses[2].bits.uop.iq_type[3] connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_pc, int_bypasses[2].bits.uop.debug_pc connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_rvc, int_bypasses[2].bits.uop.is_rvc connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_inst, int_bypasses[2].bits.uop.debug_inst connect mem_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.inst, int_bypasses[2].bits.uop.inst connect mem_exe_unit_0.io_rrd_irf_bypasses[2].valid, int_bypasses[2].valid connect mem_exe_unit_1.io_rrd_irf_resps[0], iregfile.io.rrd_read_resps[5] connect mem_exe_unit_1.io_rrd_immrf_resp, immregfile.io.rrd_read_resps[3] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.fflags.bits, int_bypasses[0].bits.fflags.bits connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.fflags.valid, int_bypasses[0].bits.fflags.valid connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.predicated, int_bypasses[0].bits.predicated connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.data, int_bypasses[0].bits.data connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.debug_tsrc, int_bypasses[0].bits.uop.debug_tsrc connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.debug_fsrc, int_bypasses[0].bits.uop.debug_fsrc connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.bp_xcpt_if, int_bypasses[0].bits.uop.bp_xcpt_if connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.bp_debug_if, int_bypasses[0].bits.uop.bp_debug_if connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.xcpt_ma_if, int_bypasses[0].bits.uop.xcpt_ma_if connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.xcpt_ae_if, int_bypasses[0].bits.uop.xcpt_ae_if connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.xcpt_pf_if, int_bypasses[0].bits.uop.xcpt_pf_if connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_typ, int_bypasses[0].bits.uop.fp_typ connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_rm, int_bypasses[0].bits.uop.fp_rm connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_val, int_bypasses[0].bits.uop.fp_val connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fcn_op, int_bypasses[0].bits.uop.fcn_op connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fcn_dw, int_bypasses[0].bits.uop.fcn_dw connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.frs3_en, int_bypasses[0].bits.uop.frs3_en connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.lrs2_rtype, int_bypasses[0].bits.uop.lrs2_rtype connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.lrs1_rtype, int_bypasses[0].bits.uop.lrs1_rtype connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.dst_rtype, int_bypasses[0].bits.uop.dst_rtype connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.lrs3, int_bypasses[0].bits.uop.lrs3 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.lrs2, int_bypasses[0].bits.uop.lrs2 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.lrs1, int_bypasses[0].bits.uop.lrs1 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ldst, int_bypasses[0].bits.uop.ldst connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ldst_is_rs1, int_bypasses[0].bits.uop.ldst_is_rs1 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.csr_cmd, int_bypasses[0].bits.uop.csr_cmd connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.flush_on_commit, int_bypasses[0].bits.uop.flush_on_commit connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_unique, int_bypasses[0].bits.uop.is_unique connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.uses_stq, int_bypasses[0].bits.uop.uses_stq connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.uses_ldq, int_bypasses[0].bits.uop.uses_ldq connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.mem_signed, int_bypasses[0].bits.uop.mem_signed connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.mem_size, int_bypasses[0].bits.uop.mem_size connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.mem_cmd, int_bypasses[0].bits.uop.mem_cmd connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.exc_cause, int_bypasses[0].bits.uop.exc_cause connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.exception, int_bypasses[0].bits.uop.exception connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.stale_pdst, int_bypasses[0].bits.uop.stale_pdst connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ppred_busy, int_bypasses[0].bits.uop.ppred_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs3_busy, int_bypasses[0].bits.uop.prs3_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs2_busy, int_bypasses[0].bits.uop.prs2_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs1_busy, int_bypasses[0].bits.uop.prs1_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ppred, int_bypasses[0].bits.uop.ppred connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs3, int_bypasses[0].bits.uop.prs3 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs2, int_bypasses[0].bits.uop.prs2 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.prs1, int_bypasses[0].bits.uop.prs1 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.pdst, int_bypasses[0].bits.uop.pdst connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.rxq_idx, int_bypasses[0].bits.uop.rxq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.stq_idx, int_bypasses[0].bits.uop.stq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ldq_idx, int_bypasses[0].bits.uop.ldq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.rob_idx, int_bypasses[0].bits.uop.rob_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.vec, int_bypasses[0].bits.uop.fp_ctrl.vec connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.wflags, int_bypasses[0].bits.uop.fp_ctrl.wflags connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.sqrt, int_bypasses[0].bits.uop.fp_ctrl.sqrt connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.div, int_bypasses[0].bits.uop.fp_ctrl.div connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fma, int_bypasses[0].bits.uop.fp_ctrl.fma connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fastpipe, int_bypasses[0].bits.uop.fp_ctrl.fastpipe connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.toint, int_bypasses[0].bits.uop.fp_ctrl.toint connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fromint, int_bypasses[0].bits.uop.fp_ctrl.fromint connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.typeTagOut, int_bypasses[0].bits.uop.fp_ctrl.typeTagOut connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.typeTagIn, int_bypasses[0].bits.uop.fp_ctrl.typeTagIn connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.swap23, int_bypasses[0].bits.uop.fp_ctrl.swap23 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.swap12, int_bypasses[0].bits.uop.fp_ctrl.swap12 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren3, int_bypasses[0].bits.uop.fp_ctrl.ren3 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren2, int_bypasses[0].bits.uop.fp_ctrl.ren2 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren1, int_bypasses[0].bits.uop.fp_ctrl.ren1 connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.wen, int_bypasses[0].bits.uop.fp_ctrl.wen connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ldst, int_bypasses[0].bits.uop.fp_ctrl.ldst connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.op2_sel, int_bypasses[0].bits.uop.op2_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.op1_sel, int_bypasses[0].bits.uop.op1_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.imm_packed, int_bypasses[0].bits.uop.imm_packed connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.pimm, int_bypasses[0].bits.uop.pimm connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.imm_sel, int_bypasses[0].bits.uop.imm_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.imm_rename, int_bypasses[0].bits.uop.imm_rename connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.taken, int_bypasses[0].bits.uop.taken connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.pc_lob, int_bypasses[0].bits.uop.pc_lob connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.edge_inst, int_bypasses[0].bits.uop.edge_inst connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.ftq_idx, int_bypasses[0].bits.uop.ftq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_mov, int_bypasses[0].bits.uop.is_mov connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_rocc, int_bypasses[0].bits.uop.is_rocc connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_sys_pc2epc, int_bypasses[0].bits.uop.is_sys_pc2epc connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_eret, int_bypasses[0].bits.uop.is_eret connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_amo, int_bypasses[0].bits.uop.is_amo connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_sfence, int_bypasses[0].bits.uop.is_sfence connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_fencei, int_bypasses[0].bits.uop.is_fencei connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_fence, int_bypasses[0].bits.uop.is_fence connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_sfb, int_bypasses[0].bits.uop.is_sfb connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.br_type, int_bypasses[0].bits.uop.br_type connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.br_tag, int_bypasses[0].bits.uop.br_tag connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.br_mask, int_bypasses[0].bits.uop.br_mask connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.dis_col_sel, int_bypasses[0].bits.uop.dis_col_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_p3_bypass_hint, int_bypasses[0].bits.uop.iw_p3_bypass_hint connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_p2_bypass_hint, int_bypasses[0].bits.uop.iw_p2_bypass_hint connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_p1_bypass_hint, int_bypasses[0].bits.uop.iw_p1_bypass_hint connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_p2_speculative_child, int_bypasses[0].bits.uop.iw_p2_speculative_child connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_p1_speculative_child, int_bypasses[0].bits.uop.iw_p1_speculative_child connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_issued_partial_dgen, int_bypasses[0].bits.uop.iw_issued_partial_dgen connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_issued_partial_agen, int_bypasses[0].bits.uop.iw_issued_partial_agen connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iw_issued, int_bypasses[0].bits.uop.iw_issued connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[0], int_bypasses[0].bits.uop.fu_code[0] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[1], int_bypasses[0].bits.uop.fu_code[1] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[2], int_bypasses[0].bits.uop.fu_code[2] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[3], int_bypasses[0].bits.uop.fu_code[3] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[4], int_bypasses[0].bits.uop.fu_code[4] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[5], int_bypasses[0].bits.uop.fu_code[5] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[6], int_bypasses[0].bits.uop.fu_code[6] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[7], int_bypasses[0].bits.uop.fu_code[7] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[8], int_bypasses[0].bits.uop.fu_code[8] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.fu_code[9], int_bypasses[0].bits.uop.fu_code[9] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iq_type[0], int_bypasses[0].bits.uop.iq_type[0] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iq_type[1], int_bypasses[0].bits.uop.iq_type[1] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iq_type[2], int_bypasses[0].bits.uop.iq_type[2] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.iq_type[3], int_bypasses[0].bits.uop.iq_type[3] connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.debug_pc, int_bypasses[0].bits.uop.debug_pc connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.is_rvc, int_bypasses[0].bits.uop.is_rvc connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.debug_inst, int_bypasses[0].bits.uop.debug_inst connect mem_exe_unit_1.io_rrd_irf_bypasses[0].bits.uop.inst, int_bypasses[0].bits.uop.inst connect mem_exe_unit_1.io_rrd_irf_bypasses[0].valid, int_bypasses[0].valid connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.fflags.bits, int_bypasses[1].bits.fflags.bits connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.fflags.valid, int_bypasses[1].bits.fflags.valid connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.predicated, int_bypasses[1].bits.predicated connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.data, int_bypasses[1].bits.data connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.debug_tsrc, int_bypasses[1].bits.uop.debug_tsrc connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.debug_fsrc, int_bypasses[1].bits.uop.debug_fsrc connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.bp_xcpt_if, int_bypasses[1].bits.uop.bp_xcpt_if connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.bp_debug_if, int_bypasses[1].bits.uop.bp_debug_if connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.xcpt_ma_if, int_bypasses[1].bits.uop.xcpt_ma_if connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.xcpt_ae_if, int_bypasses[1].bits.uop.xcpt_ae_if connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.xcpt_pf_if, int_bypasses[1].bits.uop.xcpt_pf_if connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_typ, int_bypasses[1].bits.uop.fp_typ connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_rm, int_bypasses[1].bits.uop.fp_rm connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_val, int_bypasses[1].bits.uop.fp_val connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fcn_op, int_bypasses[1].bits.uop.fcn_op connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fcn_dw, int_bypasses[1].bits.uop.fcn_dw connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.frs3_en, int_bypasses[1].bits.uop.frs3_en connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.lrs2_rtype, int_bypasses[1].bits.uop.lrs2_rtype connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.lrs1_rtype, int_bypasses[1].bits.uop.lrs1_rtype connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.dst_rtype, int_bypasses[1].bits.uop.dst_rtype connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.lrs3, int_bypasses[1].bits.uop.lrs3 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.lrs2, int_bypasses[1].bits.uop.lrs2 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.lrs1, int_bypasses[1].bits.uop.lrs1 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ldst, int_bypasses[1].bits.uop.ldst connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ldst_is_rs1, int_bypasses[1].bits.uop.ldst_is_rs1 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.csr_cmd, int_bypasses[1].bits.uop.csr_cmd connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.flush_on_commit, int_bypasses[1].bits.uop.flush_on_commit connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_unique, int_bypasses[1].bits.uop.is_unique connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.uses_stq, int_bypasses[1].bits.uop.uses_stq connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.uses_ldq, int_bypasses[1].bits.uop.uses_ldq connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.mem_signed, int_bypasses[1].bits.uop.mem_signed connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.mem_size, int_bypasses[1].bits.uop.mem_size connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.mem_cmd, int_bypasses[1].bits.uop.mem_cmd connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.exc_cause, int_bypasses[1].bits.uop.exc_cause connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.exception, int_bypasses[1].bits.uop.exception connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.stale_pdst, int_bypasses[1].bits.uop.stale_pdst connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ppred_busy, int_bypasses[1].bits.uop.ppred_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs3_busy, int_bypasses[1].bits.uop.prs3_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs2_busy, int_bypasses[1].bits.uop.prs2_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs1_busy, int_bypasses[1].bits.uop.prs1_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ppred, int_bypasses[1].bits.uop.ppred connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs3, int_bypasses[1].bits.uop.prs3 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs2, int_bypasses[1].bits.uop.prs2 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.prs1, int_bypasses[1].bits.uop.prs1 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.pdst, int_bypasses[1].bits.uop.pdst connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.rxq_idx, int_bypasses[1].bits.uop.rxq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.stq_idx, int_bypasses[1].bits.uop.stq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ldq_idx, int_bypasses[1].bits.uop.ldq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.rob_idx, int_bypasses[1].bits.uop.rob_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.vec, int_bypasses[1].bits.uop.fp_ctrl.vec connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.wflags, int_bypasses[1].bits.uop.fp_ctrl.wflags connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.sqrt, int_bypasses[1].bits.uop.fp_ctrl.sqrt connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.div, int_bypasses[1].bits.uop.fp_ctrl.div connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fma, int_bypasses[1].bits.uop.fp_ctrl.fma connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fastpipe, int_bypasses[1].bits.uop.fp_ctrl.fastpipe connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.toint, int_bypasses[1].bits.uop.fp_ctrl.toint connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fromint, int_bypasses[1].bits.uop.fp_ctrl.fromint connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.typeTagOut, int_bypasses[1].bits.uop.fp_ctrl.typeTagOut connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.typeTagIn, int_bypasses[1].bits.uop.fp_ctrl.typeTagIn connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.swap23, int_bypasses[1].bits.uop.fp_ctrl.swap23 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.swap12, int_bypasses[1].bits.uop.fp_ctrl.swap12 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren3, int_bypasses[1].bits.uop.fp_ctrl.ren3 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren2, int_bypasses[1].bits.uop.fp_ctrl.ren2 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren1, int_bypasses[1].bits.uop.fp_ctrl.ren1 connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.wen, int_bypasses[1].bits.uop.fp_ctrl.wen connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ldst, int_bypasses[1].bits.uop.fp_ctrl.ldst connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.op2_sel, int_bypasses[1].bits.uop.op2_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.op1_sel, int_bypasses[1].bits.uop.op1_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.imm_packed, int_bypasses[1].bits.uop.imm_packed connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.pimm, int_bypasses[1].bits.uop.pimm connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.imm_sel, int_bypasses[1].bits.uop.imm_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.imm_rename, int_bypasses[1].bits.uop.imm_rename connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.taken, int_bypasses[1].bits.uop.taken connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.pc_lob, int_bypasses[1].bits.uop.pc_lob connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.edge_inst, int_bypasses[1].bits.uop.edge_inst connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.ftq_idx, int_bypasses[1].bits.uop.ftq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_mov, int_bypasses[1].bits.uop.is_mov connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_rocc, int_bypasses[1].bits.uop.is_rocc connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_sys_pc2epc, int_bypasses[1].bits.uop.is_sys_pc2epc connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_eret, int_bypasses[1].bits.uop.is_eret connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_amo, int_bypasses[1].bits.uop.is_amo connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_sfence, int_bypasses[1].bits.uop.is_sfence connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_fencei, int_bypasses[1].bits.uop.is_fencei connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_fence, int_bypasses[1].bits.uop.is_fence connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_sfb, int_bypasses[1].bits.uop.is_sfb connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.br_type, int_bypasses[1].bits.uop.br_type connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.br_tag, int_bypasses[1].bits.uop.br_tag connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.br_mask, int_bypasses[1].bits.uop.br_mask connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.dis_col_sel, int_bypasses[1].bits.uop.dis_col_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_p3_bypass_hint, int_bypasses[1].bits.uop.iw_p3_bypass_hint connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_p2_bypass_hint, int_bypasses[1].bits.uop.iw_p2_bypass_hint connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_p1_bypass_hint, int_bypasses[1].bits.uop.iw_p1_bypass_hint connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_p2_speculative_child, int_bypasses[1].bits.uop.iw_p2_speculative_child connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_p1_speculative_child, int_bypasses[1].bits.uop.iw_p1_speculative_child connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_issued_partial_dgen, int_bypasses[1].bits.uop.iw_issued_partial_dgen connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_issued_partial_agen, int_bypasses[1].bits.uop.iw_issued_partial_agen connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iw_issued, int_bypasses[1].bits.uop.iw_issued connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[0], int_bypasses[1].bits.uop.fu_code[0] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[1], int_bypasses[1].bits.uop.fu_code[1] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[2], int_bypasses[1].bits.uop.fu_code[2] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[3], int_bypasses[1].bits.uop.fu_code[3] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[4], int_bypasses[1].bits.uop.fu_code[4] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[5], int_bypasses[1].bits.uop.fu_code[5] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[6], int_bypasses[1].bits.uop.fu_code[6] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[7], int_bypasses[1].bits.uop.fu_code[7] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[8], int_bypasses[1].bits.uop.fu_code[8] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.fu_code[9], int_bypasses[1].bits.uop.fu_code[9] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iq_type[0], int_bypasses[1].bits.uop.iq_type[0] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iq_type[1], int_bypasses[1].bits.uop.iq_type[1] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iq_type[2], int_bypasses[1].bits.uop.iq_type[2] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.iq_type[3], int_bypasses[1].bits.uop.iq_type[3] connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.debug_pc, int_bypasses[1].bits.uop.debug_pc connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.is_rvc, int_bypasses[1].bits.uop.is_rvc connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.debug_inst, int_bypasses[1].bits.uop.debug_inst connect mem_exe_unit_1.io_rrd_irf_bypasses[1].bits.uop.inst, int_bypasses[1].bits.uop.inst connect mem_exe_unit_1.io_rrd_irf_bypasses[1].valid, int_bypasses[1].valid connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.fflags.bits, int_bypasses[2].bits.fflags.bits connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.fflags.valid, int_bypasses[2].bits.fflags.valid connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.predicated, int_bypasses[2].bits.predicated connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.data, int_bypasses[2].bits.data connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.debug_tsrc, int_bypasses[2].bits.uop.debug_tsrc connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.debug_fsrc, int_bypasses[2].bits.uop.debug_fsrc connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.bp_xcpt_if, int_bypasses[2].bits.uop.bp_xcpt_if connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.bp_debug_if, int_bypasses[2].bits.uop.bp_debug_if connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.xcpt_ma_if, int_bypasses[2].bits.uop.xcpt_ma_if connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.xcpt_ae_if, int_bypasses[2].bits.uop.xcpt_ae_if connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.xcpt_pf_if, int_bypasses[2].bits.uop.xcpt_pf_if connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_typ, int_bypasses[2].bits.uop.fp_typ connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_rm, int_bypasses[2].bits.uop.fp_rm connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_val, int_bypasses[2].bits.uop.fp_val connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fcn_op, int_bypasses[2].bits.uop.fcn_op connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fcn_dw, int_bypasses[2].bits.uop.fcn_dw connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.frs3_en, int_bypasses[2].bits.uop.frs3_en connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.lrs2_rtype, int_bypasses[2].bits.uop.lrs2_rtype connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.lrs1_rtype, int_bypasses[2].bits.uop.lrs1_rtype connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.dst_rtype, int_bypasses[2].bits.uop.dst_rtype connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.lrs3, int_bypasses[2].bits.uop.lrs3 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.lrs2, int_bypasses[2].bits.uop.lrs2 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.lrs1, int_bypasses[2].bits.uop.lrs1 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ldst, int_bypasses[2].bits.uop.ldst connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ldst_is_rs1, int_bypasses[2].bits.uop.ldst_is_rs1 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.csr_cmd, int_bypasses[2].bits.uop.csr_cmd connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.flush_on_commit, int_bypasses[2].bits.uop.flush_on_commit connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_unique, int_bypasses[2].bits.uop.is_unique connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.uses_stq, int_bypasses[2].bits.uop.uses_stq connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.uses_ldq, int_bypasses[2].bits.uop.uses_ldq connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.mem_signed, int_bypasses[2].bits.uop.mem_signed connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.mem_size, int_bypasses[2].bits.uop.mem_size connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.mem_cmd, int_bypasses[2].bits.uop.mem_cmd connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.exc_cause, int_bypasses[2].bits.uop.exc_cause connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.exception, int_bypasses[2].bits.uop.exception connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.stale_pdst, int_bypasses[2].bits.uop.stale_pdst connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ppred_busy, int_bypasses[2].bits.uop.ppred_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs3_busy, int_bypasses[2].bits.uop.prs3_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs2_busy, int_bypasses[2].bits.uop.prs2_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs1_busy, int_bypasses[2].bits.uop.prs1_busy connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ppred, int_bypasses[2].bits.uop.ppred connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs3, int_bypasses[2].bits.uop.prs3 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs2, int_bypasses[2].bits.uop.prs2 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.prs1, int_bypasses[2].bits.uop.prs1 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.pdst, int_bypasses[2].bits.uop.pdst connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.rxq_idx, int_bypasses[2].bits.uop.rxq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.stq_idx, int_bypasses[2].bits.uop.stq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ldq_idx, int_bypasses[2].bits.uop.ldq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.rob_idx, int_bypasses[2].bits.uop.rob_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.vec, int_bypasses[2].bits.uop.fp_ctrl.vec connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.wflags, int_bypasses[2].bits.uop.fp_ctrl.wflags connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.sqrt, int_bypasses[2].bits.uop.fp_ctrl.sqrt connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.div, int_bypasses[2].bits.uop.fp_ctrl.div connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fma, int_bypasses[2].bits.uop.fp_ctrl.fma connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fastpipe, int_bypasses[2].bits.uop.fp_ctrl.fastpipe connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.toint, int_bypasses[2].bits.uop.fp_ctrl.toint connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fromint, int_bypasses[2].bits.uop.fp_ctrl.fromint connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.typeTagOut, int_bypasses[2].bits.uop.fp_ctrl.typeTagOut connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.typeTagIn, int_bypasses[2].bits.uop.fp_ctrl.typeTagIn connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.swap23, int_bypasses[2].bits.uop.fp_ctrl.swap23 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.swap12, int_bypasses[2].bits.uop.fp_ctrl.swap12 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren3, int_bypasses[2].bits.uop.fp_ctrl.ren3 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren2, int_bypasses[2].bits.uop.fp_ctrl.ren2 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren1, int_bypasses[2].bits.uop.fp_ctrl.ren1 connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.wen, int_bypasses[2].bits.uop.fp_ctrl.wen connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ldst, int_bypasses[2].bits.uop.fp_ctrl.ldst connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.op2_sel, int_bypasses[2].bits.uop.op2_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.op1_sel, int_bypasses[2].bits.uop.op1_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.imm_packed, int_bypasses[2].bits.uop.imm_packed connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.pimm, int_bypasses[2].bits.uop.pimm connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.imm_sel, int_bypasses[2].bits.uop.imm_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.imm_rename, int_bypasses[2].bits.uop.imm_rename connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.taken, int_bypasses[2].bits.uop.taken connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.pc_lob, int_bypasses[2].bits.uop.pc_lob connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.edge_inst, int_bypasses[2].bits.uop.edge_inst connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.ftq_idx, int_bypasses[2].bits.uop.ftq_idx connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_mov, int_bypasses[2].bits.uop.is_mov connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_rocc, int_bypasses[2].bits.uop.is_rocc connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_sys_pc2epc, int_bypasses[2].bits.uop.is_sys_pc2epc connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_eret, int_bypasses[2].bits.uop.is_eret connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_amo, int_bypasses[2].bits.uop.is_amo connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_sfence, int_bypasses[2].bits.uop.is_sfence connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_fencei, int_bypasses[2].bits.uop.is_fencei connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_fence, int_bypasses[2].bits.uop.is_fence connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_sfb, int_bypasses[2].bits.uop.is_sfb connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.br_type, int_bypasses[2].bits.uop.br_type connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.br_tag, int_bypasses[2].bits.uop.br_tag connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.br_mask, int_bypasses[2].bits.uop.br_mask connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.dis_col_sel, int_bypasses[2].bits.uop.dis_col_sel connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_p3_bypass_hint, int_bypasses[2].bits.uop.iw_p3_bypass_hint connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_p2_bypass_hint, int_bypasses[2].bits.uop.iw_p2_bypass_hint connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_p1_bypass_hint, int_bypasses[2].bits.uop.iw_p1_bypass_hint connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_p2_speculative_child, int_bypasses[2].bits.uop.iw_p2_speculative_child connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_p1_speculative_child, int_bypasses[2].bits.uop.iw_p1_speculative_child connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_issued_partial_dgen, int_bypasses[2].bits.uop.iw_issued_partial_dgen connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_issued_partial_agen, int_bypasses[2].bits.uop.iw_issued_partial_agen connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iw_issued, int_bypasses[2].bits.uop.iw_issued connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[0], int_bypasses[2].bits.uop.fu_code[0] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[1], int_bypasses[2].bits.uop.fu_code[1] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[2], int_bypasses[2].bits.uop.fu_code[2] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[3], int_bypasses[2].bits.uop.fu_code[3] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[4], int_bypasses[2].bits.uop.fu_code[4] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[5], int_bypasses[2].bits.uop.fu_code[5] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[6], int_bypasses[2].bits.uop.fu_code[6] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[7], int_bypasses[2].bits.uop.fu_code[7] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[8], int_bypasses[2].bits.uop.fu_code[8] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.fu_code[9], int_bypasses[2].bits.uop.fu_code[9] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iq_type[0], int_bypasses[2].bits.uop.iq_type[0] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iq_type[1], int_bypasses[2].bits.uop.iq_type[1] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iq_type[2], int_bypasses[2].bits.uop.iq_type[2] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.iq_type[3], int_bypasses[2].bits.uop.iq_type[3] connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.debug_pc, int_bypasses[2].bits.uop.debug_pc connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.is_rvc, int_bypasses[2].bits.uop.is_rvc connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.debug_inst, int_bypasses[2].bits.uop.debug_inst connect mem_exe_unit_1.io_rrd_irf_bypasses[2].bits.uop.inst, int_bypasses[2].bits.uop.inst connect mem_exe_unit_1.io_rrd_irf_bypasses[2].valid, int_bypasses[2].valid connect unique_exe_unit_0.io_rrd_irf_resps[0], iregfile.io.rrd_read_resps[6] connect unique_exe_unit_0.io_rrd_irf_resps[1], iregfile.io.rrd_read_resps[7] connect unique_exe_unit_0.io_rrd_immrf_resp, immregfile.io.rrd_read_resps[4] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.fflags.bits, int_bypasses[0].bits.fflags.bits connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.fflags.valid, int_bypasses[0].bits.fflags.valid connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.predicated, int_bypasses[0].bits.predicated connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.data, int_bypasses[0].bits.data connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_tsrc, int_bypasses[0].bits.uop.debug_tsrc connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_fsrc, int_bypasses[0].bits.uop.debug_fsrc connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.bp_xcpt_if, int_bypasses[0].bits.uop.bp_xcpt_if connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.bp_debug_if, int_bypasses[0].bits.uop.bp_debug_if connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.xcpt_ma_if, int_bypasses[0].bits.uop.xcpt_ma_if connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.xcpt_ae_if, int_bypasses[0].bits.uop.xcpt_ae_if connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.xcpt_pf_if, int_bypasses[0].bits.uop.xcpt_pf_if connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_typ, int_bypasses[0].bits.uop.fp_typ connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_rm, int_bypasses[0].bits.uop.fp_rm connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_val, int_bypasses[0].bits.uop.fp_val connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fcn_op, int_bypasses[0].bits.uop.fcn_op connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fcn_dw, int_bypasses[0].bits.uop.fcn_dw connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.frs3_en, int_bypasses[0].bits.uop.frs3_en connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs2_rtype, int_bypasses[0].bits.uop.lrs2_rtype connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs1_rtype, int_bypasses[0].bits.uop.lrs1_rtype connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.dst_rtype, int_bypasses[0].bits.uop.dst_rtype connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs3, int_bypasses[0].bits.uop.lrs3 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs2, int_bypasses[0].bits.uop.lrs2 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.lrs1, int_bypasses[0].bits.uop.lrs1 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ldst, int_bypasses[0].bits.uop.ldst connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ldst_is_rs1, int_bypasses[0].bits.uop.ldst_is_rs1 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.csr_cmd, int_bypasses[0].bits.uop.csr_cmd connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.flush_on_commit, int_bypasses[0].bits.uop.flush_on_commit connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_unique, int_bypasses[0].bits.uop.is_unique connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.uses_stq, int_bypasses[0].bits.uop.uses_stq connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.uses_ldq, int_bypasses[0].bits.uop.uses_ldq connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.mem_signed, int_bypasses[0].bits.uop.mem_signed connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.mem_size, int_bypasses[0].bits.uop.mem_size connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.mem_cmd, int_bypasses[0].bits.uop.mem_cmd connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.exc_cause, int_bypasses[0].bits.uop.exc_cause connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.exception, int_bypasses[0].bits.uop.exception connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.stale_pdst, int_bypasses[0].bits.uop.stale_pdst connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ppred_busy, int_bypasses[0].bits.uop.ppred_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs3_busy, int_bypasses[0].bits.uop.prs3_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs2_busy, int_bypasses[0].bits.uop.prs2_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs1_busy, int_bypasses[0].bits.uop.prs1_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ppred, int_bypasses[0].bits.uop.ppred connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs3, int_bypasses[0].bits.uop.prs3 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs2, int_bypasses[0].bits.uop.prs2 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.prs1, int_bypasses[0].bits.uop.prs1 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.pdst, int_bypasses[0].bits.uop.pdst connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.rxq_idx, int_bypasses[0].bits.uop.rxq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.stq_idx, int_bypasses[0].bits.uop.stq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ldq_idx, int_bypasses[0].bits.uop.ldq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.rob_idx, int_bypasses[0].bits.uop.rob_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.vec, int_bypasses[0].bits.uop.fp_ctrl.vec connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.wflags, int_bypasses[0].bits.uop.fp_ctrl.wflags connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.sqrt, int_bypasses[0].bits.uop.fp_ctrl.sqrt connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.div, int_bypasses[0].bits.uop.fp_ctrl.div connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fma, int_bypasses[0].bits.uop.fp_ctrl.fma connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fastpipe, int_bypasses[0].bits.uop.fp_ctrl.fastpipe connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.toint, int_bypasses[0].bits.uop.fp_ctrl.toint connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.fromint, int_bypasses[0].bits.uop.fp_ctrl.fromint connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.typeTagOut, int_bypasses[0].bits.uop.fp_ctrl.typeTagOut connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.typeTagIn, int_bypasses[0].bits.uop.fp_ctrl.typeTagIn connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.swap23, int_bypasses[0].bits.uop.fp_ctrl.swap23 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.swap12, int_bypasses[0].bits.uop.fp_ctrl.swap12 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren3, int_bypasses[0].bits.uop.fp_ctrl.ren3 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren2, int_bypasses[0].bits.uop.fp_ctrl.ren2 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ren1, int_bypasses[0].bits.uop.fp_ctrl.ren1 connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.wen, int_bypasses[0].bits.uop.fp_ctrl.wen connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fp_ctrl.ldst, int_bypasses[0].bits.uop.fp_ctrl.ldst connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.op2_sel, int_bypasses[0].bits.uop.op2_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.op1_sel, int_bypasses[0].bits.uop.op1_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.imm_packed, int_bypasses[0].bits.uop.imm_packed connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.pimm, int_bypasses[0].bits.uop.pimm connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.imm_sel, int_bypasses[0].bits.uop.imm_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.imm_rename, int_bypasses[0].bits.uop.imm_rename connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.taken, int_bypasses[0].bits.uop.taken connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.pc_lob, int_bypasses[0].bits.uop.pc_lob connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.edge_inst, int_bypasses[0].bits.uop.edge_inst connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.ftq_idx, int_bypasses[0].bits.uop.ftq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_mov, int_bypasses[0].bits.uop.is_mov connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_rocc, int_bypasses[0].bits.uop.is_rocc connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_sys_pc2epc, int_bypasses[0].bits.uop.is_sys_pc2epc connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_eret, int_bypasses[0].bits.uop.is_eret connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_amo, int_bypasses[0].bits.uop.is_amo connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_sfence, int_bypasses[0].bits.uop.is_sfence connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_fencei, int_bypasses[0].bits.uop.is_fencei connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_fence, int_bypasses[0].bits.uop.is_fence connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_sfb, int_bypasses[0].bits.uop.is_sfb connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.br_type, int_bypasses[0].bits.uop.br_type connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.br_tag, int_bypasses[0].bits.uop.br_tag connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.br_mask, int_bypasses[0].bits.uop.br_mask connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.dis_col_sel, int_bypasses[0].bits.uop.dis_col_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p3_bypass_hint, int_bypasses[0].bits.uop.iw_p3_bypass_hint connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p2_bypass_hint, int_bypasses[0].bits.uop.iw_p2_bypass_hint connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p1_bypass_hint, int_bypasses[0].bits.uop.iw_p1_bypass_hint connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p2_speculative_child, int_bypasses[0].bits.uop.iw_p2_speculative_child connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_p1_speculative_child, int_bypasses[0].bits.uop.iw_p1_speculative_child connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_issued_partial_dgen, int_bypasses[0].bits.uop.iw_issued_partial_dgen connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_issued_partial_agen, int_bypasses[0].bits.uop.iw_issued_partial_agen connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iw_issued, int_bypasses[0].bits.uop.iw_issued connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[0], int_bypasses[0].bits.uop.fu_code[0] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[1], int_bypasses[0].bits.uop.fu_code[1] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[2], int_bypasses[0].bits.uop.fu_code[2] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[3], int_bypasses[0].bits.uop.fu_code[3] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[4], int_bypasses[0].bits.uop.fu_code[4] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[5], int_bypasses[0].bits.uop.fu_code[5] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[6], int_bypasses[0].bits.uop.fu_code[6] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[7], int_bypasses[0].bits.uop.fu_code[7] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[8], int_bypasses[0].bits.uop.fu_code[8] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.fu_code[9], int_bypasses[0].bits.uop.fu_code[9] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[0], int_bypasses[0].bits.uop.iq_type[0] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[1], int_bypasses[0].bits.uop.iq_type[1] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[2], int_bypasses[0].bits.uop.iq_type[2] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.iq_type[3], int_bypasses[0].bits.uop.iq_type[3] connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_pc, int_bypasses[0].bits.uop.debug_pc connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.is_rvc, int_bypasses[0].bits.uop.is_rvc connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.debug_inst, int_bypasses[0].bits.uop.debug_inst connect unique_exe_unit_0.io_rrd_irf_bypasses[0].bits.uop.inst, int_bypasses[0].bits.uop.inst connect unique_exe_unit_0.io_rrd_irf_bypasses[0].valid, int_bypasses[0].valid connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.fflags.bits, int_bypasses[1].bits.fflags.bits connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.fflags.valid, int_bypasses[1].bits.fflags.valid connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.predicated, int_bypasses[1].bits.predicated connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.data, int_bypasses[1].bits.data connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_tsrc, int_bypasses[1].bits.uop.debug_tsrc connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_fsrc, int_bypasses[1].bits.uop.debug_fsrc connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.bp_xcpt_if, int_bypasses[1].bits.uop.bp_xcpt_if connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.bp_debug_if, int_bypasses[1].bits.uop.bp_debug_if connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.xcpt_ma_if, int_bypasses[1].bits.uop.xcpt_ma_if connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.xcpt_ae_if, int_bypasses[1].bits.uop.xcpt_ae_if connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.xcpt_pf_if, int_bypasses[1].bits.uop.xcpt_pf_if connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_typ, int_bypasses[1].bits.uop.fp_typ connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_rm, int_bypasses[1].bits.uop.fp_rm connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_val, int_bypasses[1].bits.uop.fp_val connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fcn_op, int_bypasses[1].bits.uop.fcn_op connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fcn_dw, int_bypasses[1].bits.uop.fcn_dw connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.frs3_en, int_bypasses[1].bits.uop.frs3_en connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs2_rtype, int_bypasses[1].bits.uop.lrs2_rtype connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs1_rtype, int_bypasses[1].bits.uop.lrs1_rtype connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.dst_rtype, int_bypasses[1].bits.uop.dst_rtype connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs3, int_bypasses[1].bits.uop.lrs3 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs2, int_bypasses[1].bits.uop.lrs2 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.lrs1, int_bypasses[1].bits.uop.lrs1 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ldst, int_bypasses[1].bits.uop.ldst connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ldst_is_rs1, int_bypasses[1].bits.uop.ldst_is_rs1 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.csr_cmd, int_bypasses[1].bits.uop.csr_cmd connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.flush_on_commit, int_bypasses[1].bits.uop.flush_on_commit connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_unique, int_bypasses[1].bits.uop.is_unique connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.uses_stq, int_bypasses[1].bits.uop.uses_stq connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.uses_ldq, int_bypasses[1].bits.uop.uses_ldq connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.mem_signed, int_bypasses[1].bits.uop.mem_signed connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.mem_size, int_bypasses[1].bits.uop.mem_size connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.mem_cmd, int_bypasses[1].bits.uop.mem_cmd connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.exc_cause, int_bypasses[1].bits.uop.exc_cause connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.exception, int_bypasses[1].bits.uop.exception connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.stale_pdst, int_bypasses[1].bits.uop.stale_pdst connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ppred_busy, int_bypasses[1].bits.uop.ppred_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs3_busy, int_bypasses[1].bits.uop.prs3_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs2_busy, int_bypasses[1].bits.uop.prs2_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs1_busy, int_bypasses[1].bits.uop.prs1_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ppred, int_bypasses[1].bits.uop.ppred connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs3, int_bypasses[1].bits.uop.prs3 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs2, int_bypasses[1].bits.uop.prs2 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.prs1, int_bypasses[1].bits.uop.prs1 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.pdst, int_bypasses[1].bits.uop.pdst connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.rxq_idx, int_bypasses[1].bits.uop.rxq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.stq_idx, int_bypasses[1].bits.uop.stq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ldq_idx, int_bypasses[1].bits.uop.ldq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.rob_idx, int_bypasses[1].bits.uop.rob_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.vec, int_bypasses[1].bits.uop.fp_ctrl.vec connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.wflags, int_bypasses[1].bits.uop.fp_ctrl.wflags connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.sqrt, int_bypasses[1].bits.uop.fp_ctrl.sqrt connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.div, int_bypasses[1].bits.uop.fp_ctrl.div connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fma, int_bypasses[1].bits.uop.fp_ctrl.fma connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fastpipe, int_bypasses[1].bits.uop.fp_ctrl.fastpipe connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.toint, int_bypasses[1].bits.uop.fp_ctrl.toint connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.fromint, int_bypasses[1].bits.uop.fp_ctrl.fromint connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.typeTagOut, int_bypasses[1].bits.uop.fp_ctrl.typeTagOut connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.typeTagIn, int_bypasses[1].bits.uop.fp_ctrl.typeTagIn connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.swap23, int_bypasses[1].bits.uop.fp_ctrl.swap23 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.swap12, int_bypasses[1].bits.uop.fp_ctrl.swap12 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren3, int_bypasses[1].bits.uop.fp_ctrl.ren3 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren2, int_bypasses[1].bits.uop.fp_ctrl.ren2 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ren1, int_bypasses[1].bits.uop.fp_ctrl.ren1 connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.wen, int_bypasses[1].bits.uop.fp_ctrl.wen connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fp_ctrl.ldst, int_bypasses[1].bits.uop.fp_ctrl.ldst connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.op2_sel, int_bypasses[1].bits.uop.op2_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.op1_sel, int_bypasses[1].bits.uop.op1_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.imm_packed, int_bypasses[1].bits.uop.imm_packed connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.pimm, int_bypasses[1].bits.uop.pimm connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.imm_sel, int_bypasses[1].bits.uop.imm_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.imm_rename, int_bypasses[1].bits.uop.imm_rename connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.taken, int_bypasses[1].bits.uop.taken connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.pc_lob, int_bypasses[1].bits.uop.pc_lob connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.edge_inst, int_bypasses[1].bits.uop.edge_inst connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.ftq_idx, int_bypasses[1].bits.uop.ftq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_mov, int_bypasses[1].bits.uop.is_mov connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_rocc, int_bypasses[1].bits.uop.is_rocc connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_sys_pc2epc, int_bypasses[1].bits.uop.is_sys_pc2epc connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_eret, int_bypasses[1].bits.uop.is_eret connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_amo, int_bypasses[1].bits.uop.is_amo connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_sfence, int_bypasses[1].bits.uop.is_sfence connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_fencei, int_bypasses[1].bits.uop.is_fencei connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_fence, int_bypasses[1].bits.uop.is_fence connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_sfb, int_bypasses[1].bits.uop.is_sfb connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.br_type, int_bypasses[1].bits.uop.br_type connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.br_tag, int_bypasses[1].bits.uop.br_tag connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.br_mask, int_bypasses[1].bits.uop.br_mask connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.dis_col_sel, int_bypasses[1].bits.uop.dis_col_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p3_bypass_hint, int_bypasses[1].bits.uop.iw_p3_bypass_hint connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p2_bypass_hint, int_bypasses[1].bits.uop.iw_p2_bypass_hint connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p1_bypass_hint, int_bypasses[1].bits.uop.iw_p1_bypass_hint connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p2_speculative_child, int_bypasses[1].bits.uop.iw_p2_speculative_child connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_p1_speculative_child, int_bypasses[1].bits.uop.iw_p1_speculative_child connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_issued_partial_dgen, int_bypasses[1].bits.uop.iw_issued_partial_dgen connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_issued_partial_agen, int_bypasses[1].bits.uop.iw_issued_partial_agen connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iw_issued, int_bypasses[1].bits.uop.iw_issued connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[0], int_bypasses[1].bits.uop.fu_code[0] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[1], int_bypasses[1].bits.uop.fu_code[1] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[2], int_bypasses[1].bits.uop.fu_code[2] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[3], int_bypasses[1].bits.uop.fu_code[3] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[4], int_bypasses[1].bits.uop.fu_code[4] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[5], int_bypasses[1].bits.uop.fu_code[5] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[6], int_bypasses[1].bits.uop.fu_code[6] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[7], int_bypasses[1].bits.uop.fu_code[7] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[8], int_bypasses[1].bits.uop.fu_code[8] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.fu_code[9], int_bypasses[1].bits.uop.fu_code[9] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[0], int_bypasses[1].bits.uop.iq_type[0] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[1], int_bypasses[1].bits.uop.iq_type[1] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[2], int_bypasses[1].bits.uop.iq_type[2] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.iq_type[3], int_bypasses[1].bits.uop.iq_type[3] connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_pc, int_bypasses[1].bits.uop.debug_pc connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.is_rvc, int_bypasses[1].bits.uop.is_rvc connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.debug_inst, int_bypasses[1].bits.uop.debug_inst connect unique_exe_unit_0.io_rrd_irf_bypasses[1].bits.uop.inst, int_bypasses[1].bits.uop.inst connect unique_exe_unit_0.io_rrd_irf_bypasses[1].valid, int_bypasses[1].valid connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.fflags.bits, int_bypasses[2].bits.fflags.bits connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.fflags.valid, int_bypasses[2].bits.fflags.valid connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.predicated, int_bypasses[2].bits.predicated connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.data, int_bypasses[2].bits.data connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_tsrc, int_bypasses[2].bits.uop.debug_tsrc connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_fsrc, int_bypasses[2].bits.uop.debug_fsrc connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.bp_xcpt_if, int_bypasses[2].bits.uop.bp_xcpt_if connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.bp_debug_if, int_bypasses[2].bits.uop.bp_debug_if connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.xcpt_ma_if, int_bypasses[2].bits.uop.xcpt_ma_if connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.xcpt_ae_if, int_bypasses[2].bits.uop.xcpt_ae_if connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.xcpt_pf_if, int_bypasses[2].bits.uop.xcpt_pf_if connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_typ, int_bypasses[2].bits.uop.fp_typ connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_rm, int_bypasses[2].bits.uop.fp_rm connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_val, int_bypasses[2].bits.uop.fp_val connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fcn_op, int_bypasses[2].bits.uop.fcn_op connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fcn_dw, int_bypasses[2].bits.uop.fcn_dw connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.frs3_en, int_bypasses[2].bits.uop.frs3_en connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs2_rtype, int_bypasses[2].bits.uop.lrs2_rtype connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs1_rtype, int_bypasses[2].bits.uop.lrs1_rtype connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.dst_rtype, int_bypasses[2].bits.uop.dst_rtype connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs3, int_bypasses[2].bits.uop.lrs3 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs2, int_bypasses[2].bits.uop.lrs2 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.lrs1, int_bypasses[2].bits.uop.lrs1 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ldst, int_bypasses[2].bits.uop.ldst connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ldst_is_rs1, int_bypasses[2].bits.uop.ldst_is_rs1 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.csr_cmd, int_bypasses[2].bits.uop.csr_cmd connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.flush_on_commit, int_bypasses[2].bits.uop.flush_on_commit connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_unique, int_bypasses[2].bits.uop.is_unique connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.uses_stq, int_bypasses[2].bits.uop.uses_stq connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.uses_ldq, int_bypasses[2].bits.uop.uses_ldq connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.mem_signed, int_bypasses[2].bits.uop.mem_signed connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.mem_size, int_bypasses[2].bits.uop.mem_size connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.mem_cmd, int_bypasses[2].bits.uop.mem_cmd connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.exc_cause, int_bypasses[2].bits.uop.exc_cause connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.exception, int_bypasses[2].bits.uop.exception connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.stale_pdst, int_bypasses[2].bits.uop.stale_pdst connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ppred_busy, int_bypasses[2].bits.uop.ppred_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs3_busy, int_bypasses[2].bits.uop.prs3_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs2_busy, int_bypasses[2].bits.uop.prs2_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs1_busy, int_bypasses[2].bits.uop.prs1_busy connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ppred, int_bypasses[2].bits.uop.ppred connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs3, int_bypasses[2].bits.uop.prs3 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs2, int_bypasses[2].bits.uop.prs2 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.prs1, int_bypasses[2].bits.uop.prs1 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.pdst, int_bypasses[2].bits.uop.pdst connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.rxq_idx, int_bypasses[2].bits.uop.rxq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.stq_idx, int_bypasses[2].bits.uop.stq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ldq_idx, int_bypasses[2].bits.uop.ldq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.rob_idx, int_bypasses[2].bits.uop.rob_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.vec, int_bypasses[2].bits.uop.fp_ctrl.vec connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.wflags, int_bypasses[2].bits.uop.fp_ctrl.wflags connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.sqrt, int_bypasses[2].bits.uop.fp_ctrl.sqrt connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.div, int_bypasses[2].bits.uop.fp_ctrl.div connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fma, int_bypasses[2].bits.uop.fp_ctrl.fma connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fastpipe, int_bypasses[2].bits.uop.fp_ctrl.fastpipe connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.toint, int_bypasses[2].bits.uop.fp_ctrl.toint connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.fromint, int_bypasses[2].bits.uop.fp_ctrl.fromint connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.typeTagOut, int_bypasses[2].bits.uop.fp_ctrl.typeTagOut connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.typeTagIn, int_bypasses[2].bits.uop.fp_ctrl.typeTagIn connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.swap23, int_bypasses[2].bits.uop.fp_ctrl.swap23 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.swap12, int_bypasses[2].bits.uop.fp_ctrl.swap12 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren3, int_bypasses[2].bits.uop.fp_ctrl.ren3 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren2, int_bypasses[2].bits.uop.fp_ctrl.ren2 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ren1, int_bypasses[2].bits.uop.fp_ctrl.ren1 connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.wen, int_bypasses[2].bits.uop.fp_ctrl.wen connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fp_ctrl.ldst, int_bypasses[2].bits.uop.fp_ctrl.ldst connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.op2_sel, int_bypasses[2].bits.uop.op2_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.op1_sel, int_bypasses[2].bits.uop.op1_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.imm_packed, int_bypasses[2].bits.uop.imm_packed connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.pimm, int_bypasses[2].bits.uop.pimm connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.imm_sel, int_bypasses[2].bits.uop.imm_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.imm_rename, int_bypasses[2].bits.uop.imm_rename connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.taken, int_bypasses[2].bits.uop.taken connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.pc_lob, int_bypasses[2].bits.uop.pc_lob connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.edge_inst, int_bypasses[2].bits.uop.edge_inst connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.ftq_idx, int_bypasses[2].bits.uop.ftq_idx connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_mov, int_bypasses[2].bits.uop.is_mov connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_rocc, int_bypasses[2].bits.uop.is_rocc connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_sys_pc2epc, int_bypasses[2].bits.uop.is_sys_pc2epc connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_eret, int_bypasses[2].bits.uop.is_eret connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_amo, int_bypasses[2].bits.uop.is_amo connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_sfence, int_bypasses[2].bits.uop.is_sfence connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_fencei, int_bypasses[2].bits.uop.is_fencei connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_fence, int_bypasses[2].bits.uop.is_fence connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_sfb, int_bypasses[2].bits.uop.is_sfb connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.br_type, int_bypasses[2].bits.uop.br_type connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.br_tag, int_bypasses[2].bits.uop.br_tag connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.br_mask, int_bypasses[2].bits.uop.br_mask connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.dis_col_sel, int_bypasses[2].bits.uop.dis_col_sel connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p3_bypass_hint, int_bypasses[2].bits.uop.iw_p3_bypass_hint connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p2_bypass_hint, int_bypasses[2].bits.uop.iw_p2_bypass_hint connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p1_bypass_hint, int_bypasses[2].bits.uop.iw_p1_bypass_hint connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p2_speculative_child, int_bypasses[2].bits.uop.iw_p2_speculative_child connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_p1_speculative_child, int_bypasses[2].bits.uop.iw_p1_speculative_child connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_issued_partial_dgen, int_bypasses[2].bits.uop.iw_issued_partial_dgen connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_issued_partial_agen, int_bypasses[2].bits.uop.iw_issued_partial_agen connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iw_issued, int_bypasses[2].bits.uop.iw_issued connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[0], int_bypasses[2].bits.uop.fu_code[0] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[1], int_bypasses[2].bits.uop.fu_code[1] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[2], int_bypasses[2].bits.uop.fu_code[2] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[3], int_bypasses[2].bits.uop.fu_code[3] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[4], int_bypasses[2].bits.uop.fu_code[4] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[5], int_bypasses[2].bits.uop.fu_code[5] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[6], int_bypasses[2].bits.uop.fu_code[6] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[7], int_bypasses[2].bits.uop.fu_code[7] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[8], int_bypasses[2].bits.uop.fu_code[8] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.fu_code[9], int_bypasses[2].bits.uop.fu_code[9] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[0], int_bypasses[2].bits.uop.iq_type[0] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[1], int_bypasses[2].bits.uop.iq_type[1] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[2], int_bypasses[2].bits.uop.iq_type[2] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.iq_type[3], int_bypasses[2].bits.uop.iq_type[3] connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_pc, int_bypasses[2].bits.uop.debug_pc connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.is_rvc, int_bypasses[2].bits.uop.is_rvc connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.debug_inst, int_bypasses[2].bits.uop.debug_inst connect unique_exe_unit_0.io_rrd_irf_bypasses[2].bits.uop.inst, int_bypasses[2].bits.uop.inst connect unique_exe_unit_0.io_rrd_irf_bypasses[2].valid, int_bypasses[2].valid connect alu_exe_unit_0.io_rrd_prf_resp, pregfile.io.rrd_read_resps[0] connect alu_exe_unit_0.io_rrd_brf_resp.rxq_idx, bregfile.io.rrd_read_resps[0].rxq_idx connect alu_exe_unit_0.io_rrd_brf_resp.stq_idx, bregfile.io.rrd_read_resps[0].stq_idx connect alu_exe_unit_0.io_rrd_brf_resp.ldq_idx, bregfile.io.rrd_read_resps[0].ldq_idx connect alu_exe_unit_1.io_rrd_prf_resp, pregfile.io.rrd_read_resps[1] connect alu_exe_unit_1.io_rrd_brf_resp.rxq_idx, bregfile.io.rrd_read_resps[1].rxq_idx connect alu_exe_unit_1.io_rrd_brf_resp.stq_idx, bregfile.io.rrd_read_resps[1].stq_idx connect alu_exe_unit_1.io_rrd_brf_resp.ldq_idx, bregfile.io.rrd_read_resps[1].ldq_idx connect io.lsu.sfence, unique_exe_unit_0.io_sfence connect io.ifu.sfence, unique_exe_unit_0.io_sfence connect csr.io.rw.addr, unique_exe_unit_0.io_csr_resp.bits.addr node _csr_io_rw_cmd_T = mux(unique_exe_unit_0.io_csr_resp.valid, UInt<1>(0h0), UInt<3>(0h4)) node _csr_io_rw_cmd_T_1 = not(_csr_io_rw_cmd_T) node _csr_io_rw_cmd_T_2 = and(unique_exe_unit_0.io_csr_resp.bits.uop.csr_cmd, _csr_io_rw_cmd_T_1) connect csr.io.rw.cmd, _csr_io_rw_cmd_T_2 connect csr.io.rw.wdata, unique_exe_unit_0.io_csr_resp.bits.data node _rob_io_csr_replay_valid_T = and(unique_exe_unit_0.io_csr_resp.valid, csr.io.rw_stall) connect rob.io.csr_replay.valid, _rob_io_csr_replay_valid_T connect rob.io.csr_replay.bits.uop.debug_tsrc, unique_exe_unit_0.io_csr_resp.bits.uop.debug_tsrc connect rob.io.csr_replay.bits.uop.debug_fsrc, unique_exe_unit_0.io_csr_resp.bits.uop.debug_fsrc connect rob.io.csr_replay.bits.uop.bp_xcpt_if, unique_exe_unit_0.io_csr_resp.bits.uop.bp_xcpt_if connect rob.io.csr_replay.bits.uop.bp_debug_if, unique_exe_unit_0.io_csr_resp.bits.uop.bp_debug_if connect rob.io.csr_replay.bits.uop.xcpt_ma_if, unique_exe_unit_0.io_csr_resp.bits.uop.xcpt_ma_if connect rob.io.csr_replay.bits.uop.xcpt_ae_if, unique_exe_unit_0.io_csr_resp.bits.uop.xcpt_ae_if connect rob.io.csr_replay.bits.uop.xcpt_pf_if, unique_exe_unit_0.io_csr_resp.bits.uop.xcpt_pf_if connect rob.io.csr_replay.bits.uop.fp_typ, unique_exe_unit_0.io_csr_resp.bits.uop.fp_typ connect rob.io.csr_replay.bits.uop.fp_rm, unique_exe_unit_0.io_csr_resp.bits.uop.fp_rm connect rob.io.csr_replay.bits.uop.fp_val, unique_exe_unit_0.io_csr_resp.bits.uop.fp_val connect rob.io.csr_replay.bits.uop.fcn_op, unique_exe_unit_0.io_csr_resp.bits.uop.fcn_op connect rob.io.csr_replay.bits.uop.fcn_dw, unique_exe_unit_0.io_csr_resp.bits.uop.fcn_dw connect rob.io.csr_replay.bits.uop.frs3_en, unique_exe_unit_0.io_csr_resp.bits.uop.frs3_en connect rob.io.csr_replay.bits.uop.lrs2_rtype, unique_exe_unit_0.io_csr_resp.bits.uop.lrs2_rtype connect rob.io.csr_replay.bits.uop.lrs1_rtype, unique_exe_unit_0.io_csr_resp.bits.uop.lrs1_rtype connect rob.io.csr_replay.bits.uop.dst_rtype, unique_exe_unit_0.io_csr_resp.bits.uop.dst_rtype connect rob.io.csr_replay.bits.uop.lrs3, unique_exe_unit_0.io_csr_resp.bits.uop.lrs3 connect rob.io.csr_replay.bits.uop.lrs2, unique_exe_unit_0.io_csr_resp.bits.uop.lrs2 connect rob.io.csr_replay.bits.uop.lrs1, unique_exe_unit_0.io_csr_resp.bits.uop.lrs1 connect rob.io.csr_replay.bits.uop.ldst, unique_exe_unit_0.io_csr_resp.bits.uop.ldst connect rob.io.csr_replay.bits.uop.ldst_is_rs1, unique_exe_unit_0.io_csr_resp.bits.uop.ldst_is_rs1 connect rob.io.csr_replay.bits.uop.csr_cmd, unique_exe_unit_0.io_csr_resp.bits.uop.csr_cmd connect rob.io.csr_replay.bits.uop.flush_on_commit, unique_exe_unit_0.io_csr_resp.bits.uop.flush_on_commit connect rob.io.csr_replay.bits.uop.is_unique, unique_exe_unit_0.io_csr_resp.bits.uop.is_unique connect rob.io.csr_replay.bits.uop.uses_stq, unique_exe_unit_0.io_csr_resp.bits.uop.uses_stq connect rob.io.csr_replay.bits.uop.uses_ldq, unique_exe_unit_0.io_csr_resp.bits.uop.uses_ldq connect rob.io.csr_replay.bits.uop.mem_signed, unique_exe_unit_0.io_csr_resp.bits.uop.mem_signed connect rob.io.csr_replay.bits.uop.mem_size, unique_exe_unit_0.io_csr_resp.bits.uop.mem_size connect rob.io.csr_replay.bits.uop.mem_cmd, unique_exe_unit_0.io_csr_resp.bits.uop.mem_cmd connect rob.io.csr_replay.bits.uop.exc_cause, unique_exe_unit_0.io_csr_resp.bits.uop.exc_cause connect rob.io.csr_replay.bits.uop.exception, unique_exe_unit_0.io_csr_resp.bits.uop.exception connect rob.io.csr_replay.bits.uop.stale_pdst, unique_exe_unit_0.io_csr_resp.bits.uop.stale_pdst connect rob.io.csr_replay.bits.uop.ppred_busy, unique_exe_unit_0.io_csr_resp.bits.uop.ppred_busy connect rob.io.csr_replay.bits.uop.prs3_busy, unique_exe_unit_0.io_csr_resp.bits.uop.prs3_busy connect rob.io.csr_replay.bits.uop.prs2_busy, unique_exe_unit_0.io_csr_resp.bits.uop.prs2_busy connect rob.io.csr_replay.bits.uop.prs1_busy, unique_exe_unit_0.io_csr_resp.bits.uop.prs1_busy connect rob.io.csr_replay.bits.uop.ppred, unique_exe_unit_0.io_csr_resp.bits.uop.ppred connect rob.io.csr_replay.bits.uop.prs3, unique_exe_unit_0.io_csr_resp.bits.uop.prs3 connect rob.io.csr_replay.bits.uop.prs2, unique_exe_unit_0.io_csr_resp.bits.uop.prs2 connect rob.io.csr_replay.bits.uop.prs1, unique_exe_unit_0.io_csr_resp.bits.uop.prs1 connect rob.io.csr_replay.bits.uop.pdst, unique_exe_unit_0.io_csr_resp.bits.uop.pdst connect rob.io.csr_replay.bits.uop.rxq_idx, unique_exe_unit_0.io_csr_resp.bits.uop.rxq_idx connect rob.io.csr_replay.bits.uop.stq_idx, unique_exe_unit_0.io_csr_resp.bits.uop.stq_idx connect rob.io.csr_replay.bits.uop.ldq_idx, unique_exe_unit_0.io_csr_resp.bits.uop.ldq_idx connect rob.io.csr_replay.bits.uop.rob_idx, unique_exe_unit_0.io_csr_resp.bits.uop.rob_idx connect rob.io.csr_replay.bits.uop.fp_ctrl.vec, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.vec connect rob.io.csr_replay.bits.uop.fp_ctrl.wflags, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.wflags connect rob.io.csr_replay.bits.uop.fp_ctrl.sqrt, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.sqrt connect rob.io.csr_replay.bits.uop.fp_ctrl.div, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.div connect rob.io.csr_replay.bits.uop.fp_ctrl.fma, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.fma connect rob.io.csr_replay.bits.uop.fp_ctrl.fastpipe, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.fastpipe connect rob.io.csr_replay.bits.uop.fp_ctrl.toint, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.toint connect rob.io.csr_replay.bits.uop.fp_ctrl.fromint, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.fromint connect rob.io.csr_replay.bits.uop.fp_ctrl.typeTagOut, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.typeTagOut connect rob.io.csr_replay.bits.uop.fp_ctrl.typeTagIn, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.typeTagIn connect rob.io.csr_replay.bits.uop.fp_ctrl.swap23, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.swap23 connect rob.io.csr_replay.bits.uop.fp_ctrl.swap12, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.swap12 connect rob.io.csr_replay.bits.uop.fp_ctrl.ren3, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.ren3 connect rob.io.csr_replay.bits.uop.fp_ctrl.ren2, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.ren2 connect rob.io.csr_replay.bits.uop.fp_ctrl.ren1, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.ren1 connect rob.io.csr_replay.bits.uop.fp_ctrl.wen, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.wen connect rob.io.csr_replay.bits.uop.fp_ctrl.ldst, unique_exe_unit_0.io_csr_resp.bits.uop.fp_ctrl.ldst connect rob.io.csr_replay.bits.uop.op2_sel, unique_exe_unit_0.io_csr_resp.bits.uop.op2_sel connect rob.io.csr_replay.bits.uop.op1_sel, unique_exe_unit_0.io_csr_resp.bits.uop.op1_sel connect rob.io.csr_replay.bits.uop.imm_packed, unique_exe_unit_0.io_csr_resp.bits.uop.imm_packed connect rob.io.csr_replay.bits.uop.pimm, unique_exe_unit_0.io_csr_resp.bits.uop.pimm connect rob.io.csr_replay.bits.uop.imm_sel, unique_exe_unit_0.io_csr_resp.bits.uop.imm_sel connect rob.io.csr_replay.bits.uop.imm_rename, unique_exe_unit_0.io_csr_resp.bits.uop.imm_rename connect rob.io.csr_replay.bits.uop.taken, unique_exe_unit_0.io_csr_resp.bits.uop.taken connect rob.io.csr_replay.bits.uop.pc_lob, unique_exe_unit_0.io_csr_resp.bits.uop.pc_lob connect rob.io.csr_replay.bits.uop.edge_inst, unique_exe_unit_0.io_csr_resp.bits.uop.edge_inst connect rob.io.csr_replay.bits.uop.ftq_idx, unique_exe_unit_0.io_csr_resp.bits.uop.ftq_idx connect rob.io.csr_replay.bits.uop.is_mov, unique_exe_unit_0.io_csr_resp.bits.uop.is_mov connect rob.io.csr_replay.bits.uop.is_rocc, unique_exe_unit_0.io_csr_resp.bits.uop.is_rocc connect rob.io.csr_replay.bits.uop.is_sys_pc2epc, unique_exe_unit_0.io_csr_resp.bits.uop.is_sys_pc2epc connect rob.io.csr_replay.bits.uop.is_eret, unique_exe_unit_0.io_csr_resp.bits.uop.is_eret connect rob.io.csr_replay.bits.uop.is_amo, unique_exe_unit_0.io_csr_resp.bits.uop.is_amo connect rob.io.csr_replay.bits.uop.is_sfence, unique_exe_unit_0.io_csr_resp.bits.uop.is_sfence connect rob.io.csr_replay.bits.uop.is_fencei, unique_exe_unit_0.io_csr_resp.bits.uop.is_fencei connect rob.io.csr_replay.bits.uop.is_fence, unique_exe_unit_0.io_csr_resp.bits.uop.is_fence connect rob.io.csr_replay.bits.uop.is_sfb, unique_exe_unit_0.io_csr_resp.bits.uop.is_sfb connect rob.io.csr_replay.bits.uop.br_type, unique_exe_unit_0.io_csr_resp.bits.uop.br_type connect rob.io.csr_replay.bits.uop.br_tag, unique_exe_unit_0.io_csr_resp.bits.uop.br_tag connect rob.io.csr_replay.bits.uop.br_mask, unique_exe_unit_0.io_csr_resp.bits.uop.br_mask connect rob.io.csr_replay.bits.uop.dis_col_sel, unique_exe_unit_0.io_csr_resp.bits.uop.dis_col_sel connect rob.io.csr_replay.bits.uop.iw_p3_bypass_hint, unique_exe_unit_0.io_csr_resp.bits.uop.iw_p3_bypass_hint connect rob.io.csr_replay.bits.uop.iw_p2_bypass_hint, unique_exe_unit_0.io_csr_resp.bits.uop.iw_p2_bypass_hint connect rob.io.csr_replay.bits.uop.iw_p1_bypass_hint, unique_exe_unit_0.io_csr_resp.bits.uop.iw_p1_bypass_hint connect rob.io.csr_replay.bits.uop.iw_p2_speculative_child, unique_exe_unit_0.io_csr_resp.bits.uop.iw_p2_speculative_child connect rob.io.csr_replay.bits.uop.iw_p1_speculative_child, unique_exe_unit_0.io_csr_resp.bits.uop.iw_p1_speculative_child connect rob.io.csr_replay.bits.uop.iw_issued_partial_dgen, unique_exe_unit_0.io_csr_resp.bits.uop.iw_issued_partial_dgen connect rob.io.csr_replay.bits.uop.iw_issued_partial_agen, unique_exe_unit_0.io_csr_resp.bits.uop.iw_issued_partial_agen connect rob.io.csr_replay.bits.uop.iw_issued, unique_exe_unit_0.io_csr_resp.bits.uop.iw_issued connect rob.io.csr_replay.bits.uop.fu_code[0], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[0] connect rob.io.csr_replay.bits.uop.fu_code[1], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[1] connect rob.io.csr_replay.bits.uop.fu_code[2], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[2] connect rob.io.csr_replay.bits.uop.fu_code[3], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[3] connect rob.io.csr_replay.bits.uop.fu_code[4], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[4] connect rob.io.csr_replay.bits.uop.fu_code[5], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[5] connect rob.io.csr_replay.bits.uop.fu_code[6], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[6] connect rob.io.csr_replay.bits.uop.fu_code[7], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[7] connect rob.io.csr_replay.bits.uop.fu_code[8], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[8] connect rob.io.csr_replay.bits.uop.fu_code[9], unique_exe_unit_0.io_csr_resp.bits.uop.fu_code[9] connect rob.io.csr_replay.bits.uop.iq_type[0], unique_exe_unit_0.io_csr_resp.bits.uop.iq_type[0] connect rob.io.csr_replay.bits.uop.iq_type[1], unique_exe_unit_0.io_csr_resp.bits.uop.iq_type[1] connect rob.io.csr_replay.bits.uop.iq_type[2], unique_exe_unit_0.io_csr_resp.bits.uop.iq_type[2] connect rob.io.csr_replay.bits.uop.iq_type[3], unique_exe_unit_0.io_csr_resp.bits.uop.iq_type[3] connect rob.io.csr_replay.bits.uop.debug_pc, unique_exe_unit_0.io_csr_resp.bits.uop.debug_pc connect rob.io.csr_replay.bits.uop.is_rvc, unique_exe_unit_0.io_csr_resp.bits.uop.is_rvc connect rob.io.csr_replay.bits.uop.debug_inst, unique_exe_unit_0.io_csr_resp.bits.uop.debug_inst connect rob.io.csr_replay.bits.uop.inst, unique_exe_unit_0.io_csr_resp.bits.uop.inst connect rob.io.csr_replay.bits.cause, UInt<5>(0h11) invalidate rob.io.csr_replay.bits.badvaddr node _csr_io_retire_T = cat(rob.io.commit.arch_valids[1], rob.io.commit.arch_valids[0]) node _csr_io_retire_T_1 = bits(_csr_io_retire_T, 0, 0) node _csr_io_retire_T_2 = bits(_csr_io_retire_T, 1, 1) node _csr_io_retire_T_3 = add(_csr_io_retire_T_1, _csr_io_retire_T_2) node _csr_io_retire_T_4 = bits(_csr_io_retire_T_3, 1, 0) reg csr_io_retire_REG : UInt, clock connect csr_io_retire_REG, _csr_io_retire_T_4 connect csr.io.retire, csr_io_retire_REG reg csr_io_exception_REG : UInt<1>, clock connect csr_io_exception_REG, rob.io.com_xcpt.valid connect csr.io.exception, csr_io_exception_REG node _csr_io_pc_T = not(io.ifu.com_pc) node _csr_io_pc_T_1 = or(_csr_io_pc_T, UInt<6>(0h3f)) node _csr_io_pc_T_2 = not(_csr_io_pc_T_1) reg csr_io_pc_REG : UInt, clock connect csr_io_pc_REG, rob.io.com_xcpt.bits.pc_lob node _csr_io_pc_T_3 = add(_csr_io_pc_T_2, csr_io_pc_REG) node _csr_io_pc_T_4 = tail(_csr_io_pc_T_3, 1) reg csr_io_pc_REG_1 : UInt<1>, clock connect csr_io_pc_REG_1, rob.io.com_xcpt.bits.edge_inst node _csr_io_pc_T_5 = mux(csr_io_pc_REG_1, UInt<2>(0h2), UInt<1>(0h0)) node _csr_io_pc_T_6 = sub(_csr_io_pc_T_4, _csr_io_pc_T_5) node _csr_io_pc_T_7 = tail(_csr_io_pc_T_6, 1) connect csr.io.pc, _csr_io_pc_T_7 reg csr_io_cause_REG : UInt, clock connect csr_io_cause_REG, rob.io.com_xcpt.bits.cause connect csr.io.cause, csr_io_cause_REG connect csr.io.ungated_clock, clock node _tval_valid_T = eq(csr.io.cause, UInt<2>(0h3)) node _tval_valid_T_1 = eq(csr.io.cause, UInt<3>(0h4)) node _tval_valid_T_2 = eq(csr.io.cause, UInt<3>(0h6)) node _tval_valid_T_3 = eq(csr.io.cause, UInt<3>(0h5)) node _tval_valid_T_4 = eq(csr.io.cause, UInt<3>(0h7)) node _tval_valid_T_5 = eq(csr.io.cause, UInt<1>(0h1)) node _tval_valid_T_6 = eq(csr.io.cause, UInt<4>(0hd)) node _tval_valid_T_7 = eq(csr.io.cause, UInt<4>(0hf)) node _tval_valid_T_8 = eq(csr.io.cause, UInt<4>(0hc)) node _tval_valid_T_9 = or(_tval_valid_T, _tval_valid_T_1) node _tval_valid_T_10 = or(_tval_valid_T_9, _tval_valid_T_2) node _tval_valid_T_11 = or(_tval_valid_T_10, _tval_valid_T_3) node _tval_valid_T_12 = or(_tval_valid_T_11, _tval_valid_T_4) node _tval_valid_T_13 = or(_tval_valid_T_12, _tval_valid_T_5) node _tval_valid_T_14 = or(_tval_valid_T_13, _tval_valid_T_6) node _tval_valid_T_15 = or(_tval_valid_T_14, _tval_valid_T_7) node _tval_valid_T_16 = or(_tval_valid_T_15, _tval_valid_T_8) node tval_valid = and(csr.io.exception, _tval_valid_T_16) node _csr_io_tval_a_T = asSInt(rob.io.com_xcpt.bits.badvaddr) node csr_io_tval_a = shr(_csr_io_tval_a_T, 39) node _csr_io_tval_msb_T = eq(csr_io_tval_a, asSInt(UInt<1>(0h0))) node _csr_io_tval_msb_T_1 = eq(csr_io_tval_a, asSInt(UInt<1>(0h1))) node _csr_io_tval_msb_T_2 = or(_csr_io_tval_msb_T, _csr_io_tval_msb_T_1) node _csr_io_tval_msb_T_3 = bits(rob.io.com_xcpt.bits.badvaddr, 39, 39) node _csr_io_tval_msb_T_4 = bits(rob.io.com_xcpt.bits.badvaddr, 38, 38) node _csr_io_tval_msb_T_5 = eq(_csr_io_tval_msb_T_4, UInt<1>(0h0)) node csr_io_tval_msb = mux(_csr_io_tval_msb_T_2, _csr_io_tval_msb_T_3, _csr_io_tval_msb_T_5) node _csr_io_tval_T = bits(rob.io.com_xcpt.bits.badvaddr, 38, 0) node _csr_io_tval_T_1 = cat(csr_io_tval_msb, _csr_io_tval_T) reg csr_io_tval_REG : UInt, clock connect csr_io_tval_REG, _csr_io_tval_T_1 node _csr_io_tval_T_2 = mux(tval_valid, csr_io_tval_REG, UInt<1>(0h0)) connect csr.io.tval, _csr_io_tval_T_2 connect csr.io.fcsr_flags.valid, rob.io.commit.fflags.valid connect csr.io.fcsr_flags.bits, rob.io.commit.fflags.bits connect csr.io.set_fs_dirty, rob.io.commit.fflags.valid connect alu_exe_unit_0.io_fcsr_rm, csr.io.fcsr_rm connect alu_exe_unit_1.io_fcsr_rm, csr.io.fcsr_rm connect mem_exe_unit_0.io_fcsr_rm, csr.io.fcsr_rm connect mem_exe_unit_1.io_fcsr_rm, csr.io.fcsr_rm connect unique_exe_unit_0.io_fcsr_rm, csr.io.fcsr_rm connect io.fcsr_rm, csr.io.fcsr_rm connect fp_pipeline.io.fcsr_rm, csr.io.fcsr_rm connect csr.io.hartid, io.hartid connect csr.io.interrupts.seip, io.interrupts.seip connect csr.io.interrupts.meip, io.interrupts.meip connect csr.io.interrupts.msip, io.interrupts.msip connect csr.io.interrupts.mtip, io.interrupts.mtip connect csr.io.interrupts.debug, io.interrupts.debug invalidate csr.io.htval invalidate csr.io.gva connect io.lsu.dis_uops[0].valid, dis_fire[0] connect io.lsu.dis_uops[0].bits, dis_uops[0] connect io.lsu.dis_uops[1].valid, dis_fire[1] connect io.lsu.dis_uops[1].bits, dis_uops[1] connect io.lsu.commit, rob.io.commit connect io.lsu.commit_load_at_rob_head, rob.io.com_load_is_at_rob_head reg io_lsu_exception_REG : UInt<1>, clock connect io_lsu_exception_REG, rob.io.flush.valid connect io.lsu.exception, io_lsu_exception_REG connect io.lsu.brupdate, brupdate connect io.lsu.rob_head_idx, rob.io.rob_head_idx connect io.lsu.rob_pnr_idx, rob.io.rob_pnr_idx connect io.lsu.tsc_reg, debug_tsc_reg connect fp_pipeline.io.from_int, unique_exe_unit_0.io_ifpu_resp connect fp_pipeline.io.ll_wports, io.lsu.fresp connect rob.io.wb_resps[4].bits.fflags.bits, fp_pipeline.io.wb[0].bits.fflags.bits connect rob.io.wb_resps[4].bits.fflags.valid, fp_pipeline.io.wb[0].bits.fflags.valid connect rob.io.wb_resps[4].bits.predicated, fp_pipeline.io.wb[0].bits.predicated connect rob.io.wb_resps[4].bits.data, fp_pipeline.io.wb[0].bits.data connect rob.io.wb_resps[4].bits.uop.debug_tsrc, fp_pipeline.io.wb[0].bits.uop.debug_tsrc connect rob.io.wb_resps[4].bits.uop.debug_fsrc, fp_pipeline.io.wb[0].bits.uop.debug_fsrc connect rob.io.wb_resps[4].bits.uop.bp_xcpt_if, fp_pipeline.io.wb[0].bits.uop.bp_xcpt_if connect rob.io.wb_resps[4].bits.uop.bp_debug_if, fp_pipeline.io.wb[0].bits.uop.bp_debug_if connect rob.io.wb_resps[4].bits.uop.xcpt_ma_if, fp_pipeline.io.wb[0].bits.uop.xcpt_ma_if connect rob.io.wb_resps[4].bits.uop.xcpt_ae_if, fp_pipeline.io.wb[0].bits.uop.xcpt_ae_if connect rob.io.wb_resps[4].bits.uop.xcpt_pf_if, fp_pipeline.io.wb[0].bits.uop.xcpt_pf_if connect rob.io.wb_resps[4].bits.uop.fp_typ, fp_pipeline.io.wb[0].bits.uop.fp_typ connect rob.io.wb_resps[4].bits.uop.fp_rm, fp_pipeline.io.wb[0].bits.uop.fp_rm connect rob.io.wb_resps[4].bits.uop.fp_val, fp_pipeline.io.wb[0].bits.uop.fp_val connect rob.io.wb_resps[4].bits.uop.fcn_op, fp_pipeline.io.wb[0].bits.uop.fcn_op connect rob.io.wb_resps[4].bits.uop.fcn_dw, fp_pipeline.io.wb[0].bits.uop.fcn_dw connect rob.io.wb_resps[4].bits.uop.frs3_en, fp_pipeline.io.wb[0].bits.uop.frs3_en connect rob.io.wb_resps[4].bits.uop.lrs2_rtype, fp_pipeline.io.wb[0].bits.uop.lrs2_rtype connect rob.io.wb_resps[4].bits.uop.lrs1_rtype, fp_pipeline.io.wb[0].bits.uop.lrs1_rtype connect rob.io.wb_resps[4].bits.uop.dst_rtype, fp_pipeline.io.wb[0].bits.uop.dst_rtype connect rob.io.wb_resps[4].bits.uop.lrs3, fp_pipeline.io.wb[0].bits.uop.lrs3 connect rob.io.wb_resps[4].bits.uop.lrs2, fp_pipeline.io.wb[0].bits.uop.lrs2 connect rob.io.wb_resps[4].bits.uop.lrs1, fp_pipeline.io.wb[0].bits.uop.lrs1 connect rob.io.wb_resps[4].bits.uop.ldst, fp_pipeline.io.wb[0].bits.uop.ldst connect rob.io.wb_resps[4].bits.uop.ldst_is_rs1, fp_pipeline.io.wb[0].bits.uop.ldst_is_rs1 connect rob.io.wb_resps[4].bits.uop.csr_cmd, fp_pipeline.io.wb[0].bits.uop.csr_cmd connect rob.io.wb_resps[4].bits.uop.flush_on_commit, fp_pipeline.io.wb[0].bits.uop.flush_on_commit connect rob.io.wb_resps[4].bits.uop.is_unique, fp_pipeline.io.wb[0].bits.uop.is_unique connect rob.io.wb_resps[4].bits.uop.uses_stq, fp_pipeline.io.wb[0].bits.uop.uses_stq connect rob.io.wb_resps[4].bits.uop.uses_ldq, fp_pipeline.io.wb[0].bits.uop.uses_ldq connect rob.io.wb_resps[4].bits.uop.mem_signed, fp_pipeline.io.wb[0].bits.uop.mem_signed connect rob.io.wb_resps[4].bits.uop.mem_size, fp_pipeline.io.wb[0].bits.uop.mem_size connect rob.io.wb_resps[4].bits.uop.mem_cmd, fp_pipeline.io.wb[0].bits.uop.mem_cmd connect rob.io.wb_resps[4].bits.uop.exc_cause, fp_pipeline.io.wb[0].bits.uop.exc_cause connect rob.io.wb_resps[4].bits.uop.exception, fp_pipeline.io.wb[0].bits.uop.exception connect rob.io.wb_resps[4].bits.uop.stale_pdst, fp_pipeline.io.wb[0].bits.uop.stale_pdst connect rob.io.wb_resps[4].bits.uop.ppred_busy, fp_pipeline.io.wb[0].bits.uop.ppred_busy connect rob.io.wb_resps[4].bits.uop.prs3_busy, fp_pipeline.io.wb[0].bits.uop.prs3_busy connect rob.io.wb_resps[4].bits.uop.prs2_busy, fp_pipeline.io.wb[0].bits.uop.prs2_busy connect rob.io.wb_resps[4].bits.uop.prs1_busy, fp_pipeline.io.wb[0].bits.uop.prs1_busy connect rob.io.wb_resps[4].bits.uop.ppred, fp_pipeline.io.wb[0].bits.uop.ppred connect rob.io.wb_resps[4].bits.uop.prs3, fp_pipeline.io.wb[0].bits.uop.prs3 connect rob.io.wb_resps[4].bits.uop.prs2, fp_pipeline.io.wb[0].bits.uop.prs2 connect rob.io.wb_resps[4].bits.uop.prs1, fp_pipeline.io.wb[0].bits.uop.prs1 connect rob.io.wb_resps[4].bits.uop.pdst, fp_pipeline.io.wb[0].bits.uop.pdst connect rob.io.wb_resps[4].bits.uop.rxq_idx, fp_pipeline.io.wb[0].bits.uop.rxq_idx connect rob.io.wb_resps[4].bits.uop.stq_idx, fp_pipeline.io.wb[0].bits.uop.stq_idx connect rob.io.wb_resps[4].bits.uop.ldq_idx, fp_pipeline.io.wb[0].bits.uop.ldq_idx connect rob.io.wb_resps[4].bits.uop.rob_idx, fp_pipeline.io.wb[0].bits.uop.rob_idx connect rob.io.wb_resps[4].bits.uop.fp_ctrl.vec, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.vec connect rob.io.wb_resps[4].bits.uop.fp_ctrl.wflags, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.wflags connect rob.io.wb_resps[4].bits.uop.fp_ctrl.sqrt, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.sqrt connect rob.io.wb_resps[4].bits.uop.fp_ctrl.div, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.div connect rob.io.wb_resps[4].bits.uop.fp_ctrl.fma, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.fma connect rob.io.wb_resps[4].bits.uop.fp_ctrl.fastpipe, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.fastpipe connect rob.io.wb_resps[4].bits.uop.fp_ctrl.toint, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.toint connect rob.io.wb_resps[4].bits.uop.fp_ctrl.fromint, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.fromint connect rob.io.wb_resps[4].bits.uop.fp_ctrl.typeTagOut, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.typeTagOut connect rob.io.wb_resps[4].bits.uop.fp_ctrl.typeTagIn, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.typeTagIn connect rob.io.wb_resps[4].bits.uop.fp_ctrl.swap23, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.swap23 connect rob.io.wb_resps[4].bits.uop.fp_ctrl.swap12, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.swap12 connect rob.io.wb_resps[4].bits.uop.fp_ctrl.ren3, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.ren3 connect rob.io.wb_resps[4].bits.uop.fp_ctrl.ren2, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.ren2 connect rob.io.wb_resps[4].bits.uop.fp_ctrl.ren1, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.ren1 connect rob.io.wb_resps[4].bits.uop.fp_ctrl.wen, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.wen connect rob.io.wb_resps[4].bits.uop.fp_ctrl.ldst, fp_pipeline.io.wb[0].bits.uop.fp_ctrl.ldst connect rob.io.wb_resps[4].bits.uop.op2_sel, fp_pipeline.io.wb[0].bits.uop.op2_sel connect rob.io.wb_resps[4].bits.uop.op1_sel, fp_pipeline.io.wb[0].bits.uop.op1_sel connect rob.io.wb_resps[4].bits.uop.imm_packed, fp_pipeline.io.wb[0].bits.uop.imm_packed connect rob.io.wb_resps[4].bits.uop.pimm, fp_pipeline.io.wb[0].bits.uop.pimm connect rob.io.wb_resps[4].bits.uop.imm_sel, fp_pipeline.io.wb[0].bits.uop.imm_sel connect rob.io.wb_resps[4].bits.uop.imm_rename, fp_pipeline.io.wb[0].bits.uop.imm_rename connect rob.io.wb_resps[4].bits.uop.taken, fp_pipeline.io.wb[0].bits.uop.taken connect rob.io.wb_resps[4].bits.uop.pc_lob, fp_pipeline.io.wb[0].bits.uop.pc_lob connect rob.io.wb_resps[4].bits.uop.edge_inst, fp_pipeline.io.wb[0].bits.uop.edge_inst connect rob.io.wb_resps[4].bits.uop.ftq_idx, fp_pipeline.io.wb[0].bits.uop.ftq_idx connect rob.io.wb_resps[4].bits.uop.is_mov, fp_pipeline.io.wb[0].bits.uop.is_mov connect rob.io.wb_resps[4].bits.uop.is_rocc, fp_pipeline.io.wb[0].bits.uop.is_rocc connect rob.io.wb_resps[4].bits.uop.is_sys_pc2epc, fp_pipeline.io.wb[0].bits.uop.is_sys_pc2epc connect rob.io.wb_resps[4].bits.uop.is_eret, fp_pipeline.io.wb[0].bits.uop.is_eret connect rob.io.wb_resps[4].bits.uop.is_amo, fp_pipeline.io.wb[0].bits.uop.is_amo connect rob.io.wb_resps[4].bits.uop.is_sfence, fp_pipeline.io.wb[0].bits.uop.is_sfence connect rob.io.wb_resps[4].bits.uop.is_fencei, fp_pipeline.io.wb[0].bits.uop.is_fencei connect rob.io.wb_resps[4].bits.uop.is_fence, fp_pipeline.io.wb[0].bits.uop.is_fence connect rob.io.wb_resps[4].bits.uop.is_sfb, fp_pipeline.io.wb[0].bits.uop.is_sfb connect rob.io.wb_resps[4].bits.uop.br_type, fp_pipeline.io.wb[0].bits.uop.br_type connect rob.io.wb_resps[4].bits.uop.br_tag, fp_pipeline.io.wb[0].bits.uop.br_tag connect rob.io.wb_resps[4].bits.uop.br_mask, fp_pipeline.io.wb[0].bits.uop.br_mask connect rob.io.wb_resps[4].bits.uop.dis_col_sel, fp_pipeline.io.wb[0].bits.uop.dis_col_sel connect rob.io.wb_resps[4].bits.uop.iw_p3_bypass_hint, fp_pipeline.io.wb[0].bits.uop.iw_p3_bypass_hint connect rob.io.wb_resps[4].bits.uop.iw_p2_bypass_hint, fp_pipeline.io.wb[0].bits.uop.iw_p2_bypass_hint connect rob.io.wb_resps[4].bits.uop.iw_p1_bypass_hint, fp_pipeline.io.wb[0].bits.uop.iw_p1_bypass_hint connect rob.io.wb_resps[4].bits.uop.iw_p2_speculative_child, fp_pipeline.io.wb[0].bits.uop.iw_p2_speculative_child connect rob.io.wb_resps[4].bits.uop.iw_p1_speculative_child, fp_pipeline.io.wb[0].bits.uop.iw_p1_speculative_child connect rob.io.wb_resps[4].bits.uop.iw_issued_partial_dgen, fp_pipeline.io.wb[0].bits.uop.iw_issued_partial_dgen connect rob.io.wb_resps[4].bits.uop.iw_issued_partial_agen, fp_pipeline.io.wb[0].bits.uop.iw_issued_partial_agen connect rob.io.wb_resps[4].bits.uop.iw_issued, fp_pipeline.io.wb[0].bits.uop.iw_issued connect rob.io.wb_resps[4].bits.uop.fu_code[0], fp_pipeline.io.wb[0].bits.uop.fu_code[0] connect rob.io.wb_resps[4].bits.uop.fu_code[1], fp_pipeline.io.wb[0].bits.uop.fu_code[1] connect rob.io.wb_resps[4].bits.uop.fu_code[2], fp_pipeline.io.wb[0].bits.uop.fu_code[2] connect rob.io.wb_resps[4].bits.uop.fu_code[3], fp_pipeline.io.wb[0].bits.uop.fu_code[3] connect rob.io.wb_resps[4].bits.uop.fu_code[4], fp_pipeline.io.wb[0].bits.uop.fu_code[4] connect rob.io.wb_resps[4].bits.uop.fu_code[5], fp_pipeline.io.wb[0].bits.uop.fu_code[5] connect rob.io.wb_resps[4].bits.uop.fu_code[6], fp_pipeline.io.wb[0].bits.uop.fu_code[6] connect rob.io.wb_resps[4].bits.uop.fu_code[7], fp_pipeline.io.wb[0].bits.uop.fu_code[7] connect rob.io.wb_resps[4].bits.uop.fu_code[8], fp_pipeline.io.wb[0].bits.uop.fu_code[8] connect rob.io.wb_resps[4].bits.uop.fu_code[9], fp_pipeline.io.wb[0].bits.uop.fu_code[9] connect rob.io.wb_resps[4].bits.uop.iq_type[0], fp_pipeline.io.wb[0].bits.uop.iq_type[0] connect rob.io.wb_resps[4].bits.uop.iq_type[1], fp_pipeline.io.wb[0].bits.uop.iq_type[1] connect rob.io.wb_resps[4].bits.uop.iq_type[2], fp_pipeline.io.wb[0].bits.uop.iq_type[2] connect rob.io.wb_resps[4].bits.uop.iq_type[3], fp_pipeline.io.wb[0].bits.uop.iq_type[3] connect rob.io.wb_resps[4].bits.uop.debug_pc, fp_pipeline.io.wb[0].bits.uop.debug_pc connect rob.io.wb_resps[4].bits.uop.is_rvc, fp_pipeline.io.wb[0].bits.uop.is_rvc connect rob.io.wb_resps[4].bits.uop.debug_inst, fp_pipeline.io.wb[0].bits.uop.debug_inst connect rob.io.wb_resps[4].bits.uop.inst, fp_pipeline.io.wb[0].bits.uop.inst connect rob.io.wb_resps[4].valid, fp_pipeline.io.wb[0].valid node rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp = bits(fp_pipeline.io.wb[0].bits.data, 63, 52) node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isZero_T = bits(rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp, 11, 9) node rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isZero = eq(_rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isSpecial_T = bits(rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp, 11, 10) node rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isSpecial = eq(_rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire rob_io_wb_resps_4_bits_data_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isNaN_T = bits(rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp, 9, 9) node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isNaN_T_1 = and(rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isSpecial, _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isNaN_T) connect rob_io_wb_resps_4_bits_data_unrecoded_rawIn.isNaN, _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isNaN_T_1 node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T = bits(rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp, 9, 9) node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T_1 = eq(_rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T_2 = and(rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isSpecial, _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T_1) connect rob_io_wb_resps_4_bits_data_unrecoded_rawIn.isInf, _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T_2 connect rob_io_wb_resps_4_bits_data_unrecoded_rawIn.isZero, rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isZero node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sign_T = bits(fp_pipeline.io.wb[0].bits.data, 64, 64) connect rob_io_wb_resps_4_bits_data_unrecoded_rawIn.sign, _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sign_T node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sExp_T = cvt(rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp) connect rob_io_wb_resps_4_bits_data_unrecoded_rawIn.sExp, _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sExp_T node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T = eq(rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T) node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_2 = bits(fp_pipeline.io.wb[0].bits.data, 51, 0) node _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_3 = cat(_rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_1, _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_2) connect rob_io_wb_resps_4_bits_data_unrecoded_rawIn.sig, _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_3 node rob_io_wb_resps_4_bits_data_unrecoded_isSubnormal = lt(rob_io_wb_resps_4_bits_data_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist_T = bits(rob_io_wb_resps_4_bits_data_unrecoded_rawIn.sExp, 5, 0) node _rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist_T) node rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist = tail(_rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist_T_1, 1) node _rob_io_wb_resps_4_bits_data_unrecoded_denormFract_T = shr(rob_io_wb_resps_4_bits_data_unrecoded_rawIn.sig, 1) node _rob_io_wb_resps_4_bits_data_unrecoded_denormFract_T_1 = dshr(_rob_io_wb_resps_4_bits_data_unrecoded_denormFract_T, rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist) node rob_io_wb_resps_4_bits_data_unrecoded_denormFract = bits(_rob_io_wb_resps_4_bits_data_unrecoded_denormFract_T_1, 51, 0) node _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T = bits(rob_io_wb_resps_4_bits_data_unrecoded_rawIn.sExp, 10, 0) node _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_1 = sub(_rob_io_wb_resps_4_bits_data_unrecoded_expOut_T, UInt<11>(0h401)) node _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_2 = tail(_rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_1, 1) node _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_3 = mux(rob_io_wb_resps_4_bits_data_unrecoded_isSubnormal, UInt<1>(0h0), _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_2) node _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_4 = or(rob_io_wb_resps_4_bits_data_unrecoded_rawIn.isNaN, rob_io_wb_resps_4_bits_data_unrecoded_rawIn.isInf) node _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_5 = mux(_rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node rob_io_wb_resps_4_bits_data_unrecoded_expOut = or(_rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_3, _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_5) node _rob_io_wb_resps_4_bits_data_unrecoded_fractOut_T = bits(rob_io_wb_resps_4_bits_data_unrecoded_rawIn.sig, 51, 0) node _rob_io_wb_resps_4_bits_data_unrecoded_fractOut_T_1 = mux(rob_io_wb_resps_4_bits_data_unrecoded_rawIn.isInf, UInt<1>(0h0), _rob_io_wb_resps_4_bits_data_unrecoded_fractOut_T) node rob_io_wb_resps_4_bits_data_unrecoded_fractOut = mux(rob_io_wb_resps_4_bits_data_unrecoded_isSubnormal, rob_io_wb_resps_4_bits_data_unrecoded_denormFract, _rob_io_wb_resps_4_bits_data_unrecoded_fractOut_T_1) node rob_io_wb_resps_4_bits_data_unrecoded_hi = cat(rob_io_wb_resps_4_bits_data_unrecoded_rawIn.sign, rob_io_wb_resps_4_bits_data_unrecoded_expOut) node rob_io_wb_resps_4_bits_data_unrecoded = cat(rob_io_wb_resps_4_bits_data_unrecoded_hi, rob_io_wb_resps_4_bits_data_unrecoded_fractOut) node _rob_io_wb_resps_4_bits_data_prevRecoded_T = bits(fp_pipeline.io.wb[0].bits.data, 31, 31) node _rob_io_wb_resps_4_bits_data_prevRecoded_T_1 = bits(fp_pipeline.io.wb[0].bits.data, 52, 52) node _rob_io_wb_resps_4_bits_data_prevRecoded_T_2 = bits(fp_pipeline.io.wb[0].bits.data, 30, 0) node rob_io_wb_resps_4_bits_data_prevRecoded_hi = cat(_rob_io_wb_resps_4_bits_data_prevRecoded_T, _rob_io_wb_resps_4_bits_data_prevRecoded_T_1) node rob_io_wb_resps_4_bits_data_prevRecoded = cat(rob_io_wb_resps_4_bits_data_prevRecoded_hi, _rob_io_wb_resps_4_bits_data_prevRecoded_T_2) node rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp = bits(rob_io_wb_resps_4_bits_data_prevRecoded, 31, 23) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isZero_T = bits(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp, 8, 6) node rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isZero = eq(_rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isSpecial_T = bits(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp, 8, 7) node rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isSpecial = eq(_rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isNaN_T = bits(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp, 6, 6) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1 = and(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isSpecial, _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isNaN_T) connect rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.isNaN, _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1 node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T = bits(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp, 6, 6) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T_2 = and(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isSpecial, _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T_1) connect rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.isInf, _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T_2 connect rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.isZero, rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isZero node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sign_T = bits(rob_io_wb_resps_4_bits_data_prevRecoded, 32, 32) connect rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.sign, _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sign_T node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sExp_T = cvt(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp) connect rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.sExp, _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sExp_T node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T = eq(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_2 = bits(rob_io_wb_resps_4_bits_data_prevRecoded, 22, 0) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_3 = cat(_rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_1, _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_2) connect rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.sig, _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_3 node rob_io_wb_resps_4_bits_data_prevUnrecoded_isSubnormal = lt(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist_T = bits(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.sExp, 4, 0) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist_T) node rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist = tail(_rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist_T_1, 1) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract_T = shr(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.sig, 1) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract_T_1 = dshr(_rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract_T, rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist) node rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract = bits(_rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract_T_1, 22, 0) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T = bits(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.sExp, 7, 0) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_1 = sub(_rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T, UInt<8>(0h81)) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_2 = tail(_rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_1, 1) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_3 = mux(rob_io_wb_resps_4_bits_data_prevUnrecoded_isSubnormal, UInt<1>(0h0), _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_2) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_4 = or(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.isNaN, rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.isInf) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_5 = mux(_rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut = or(_rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_3, _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_5) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut_T = bits(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.sig, 22, 0) node _rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut_T_1 = mux(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut_T) node rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut = mux(rob_io_wb_resps_4_bits_data_prevUnrecoded_isSubnormal, rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract, _rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut_T_1) node rob_io_wb_resps_4_bits_data_prevUnrecoded_hi = cat(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn.sign, rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut) node rob_io_wb_resps_4_bits_data_prevUnrecoded = cat(rob_io_wb_resps_4_bits_data_prevUnrecoded_hi, rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut) node _rob_io_wb_resps_4_bits_data_T = shr(rob_io_wb_resps_4_bits_data_unrecoded, 32) node _rob_io_wb_resps_4_bits_data_T_1 = bits(fp_pipeline.io.wb[0].bits.data, 63, 61) node _rob_io_wb_resps_4_bits_data_T_2 = andr(_rob_io_wb_resps_4_bits_data_T_1) node _rob_io_wb_resps_4_bits_data_T_3 = bits(rob_io_wb_resps_4_bits_data_unrecoded, 31, 0) node _rob_io_wb_resps_4_bits_data_T_4 = mux(_rob_io_wb_resps_4_bits_data_T_2, rob_io_wb_resps_4_bits_data_prevUnrecoded, _rob_io_wb_resps_4_bits_data_T_3) node _rob_io_wb_resps_4_bits_data_T_5 = cat(_rob_io_wb_resps_4_bits_data_T, _rob_io_wb_resps_4_bits_data_T_4) connect rob.io.wb_resps[4].bits.data, _rob_io_wb_resps_4_bits_data_T_5 connect rob.io.wb_resps[5].bits.fflags.bits, fp_pipeline.io.wb[1].bits.fflags.bits connect rob.io.wb_resps[5].bits.fflags.valid, fp_pipeline.io.wb[1].bits.fflags.valid connect rob.io.wb_resps[5].bits.predicated, fp_pipeline.io.wb[1].bits.predicated connect rob.io.wb_resps[5].bits.data, fp_pipeline.io.wb[1].bits.data connect rob.io.wb_resps[5].bits.uop.debug_tsrc, fp_pipeline.io.wb[1].bits.uop.debug_tsrc connect rob.io.wb_resps[5].bits.uop.debug_fsrc, fp_pipeline.io.wb[1].bits.uop.debug_fsrc connect rob.io.wb_resps[5].bits.uop.bp_xcpt_if, fp_pipeline.io.wb[1].bits.uop.bp_xcpt_if connect rob.io.wb_resps[5].bits.uop.bp_debug_if, fp_pipeline.io.wb[1].bits.uop.bp_debug_if connect rob.io.wb_resps[5].bits.uop.xcpt_ma_if, fp_pipeline.io.wb[1].bits.uop.xcpt_ma_if connect rob.io.wb_resps[5].bits.uop.xcpt_ae_if, fp_pipeline.io.wb[1].bits.uop.xcpt_ae_if connect rob.io.wb_resps[5].bits.uop.xcpt_pf_if, fp_pipeline.io.wb[1].bits.uop.xcpt_pf_if connect rob.io.wb_resps[5].bits.uop.fp_typ, fp_pipeline.io.wb[1].bits.uop.fp_typ connect rob.io.wb_resps[5].bits.uop.fp_rm, fp_pipeline.io.wb[1].bits.uop.fp_rm connect rob.io.wb_resps[5].bits.uop.fp_val, fp_pipeline.io.wb[1].bits.uop.fp_val connect rob.io.wb_resps[5].bits.uop.fcn_op, fp_pipeline.io.wb[1].bits.uop.fcn_op connect rob.io.wb_resps[5].bits.uop.fcn_dw, fp_pipeline.io.wb[1].bits.uop.fcn_dw connect rob.io.wb_resps[5].bits.uop.frs3_en, fp_pipeline.io.wb[1].bits.uop.frs3_en connect rob.io.wb_resps[5].bits.uop.lrs2_rtype, fp_pipeline.io.wb[1].bits.uop.lrs2_rtype connect rob.io.wb_resps[5].bits.uop.lrs1_rtype, fp_pipeline.io.wb[1].bits.uop.lrs1_rtype connect rob.io.wb_resps[5].bits.uop.dst_rtype, fp_pipeline.io.wb[1].bits.uop.dst_rtype connect rob.io.wb_resps[5].bits.uop.lrs3, fp_pipeline.io.wb[1].bits.uop.lrs3 connect rob.io.wb_resps[5].bits.uop.lrs2, fp_pipeline.io.wb[1].bits.uop.lrs2 connect rob.io.wb_resps[5].bits.uop.lrs1, fp_pipeline.io.wb[1].bits.uop.lrs1 connect rob.io.wb_resps[5].bits.uop.ldst, fp_pipeline.io.wb[1].bits.uop.ldst connect rob.io.wb_resps[5].bits.uop.ldst_is_rs1, fp_pipeline.io.wb[1].bits.uop.ldst_is_rs1 connect rob.io.wb_resps[5].bits.uop.csr_cmd, fp_pipeline.io.wb[1].bits.uop.csr_cmd connect rob.io.wb_resps[5].bits.uop.flush_on_commit, fp_pipeline.io.wb[1].bits.uop.flush_on_commit connect rob.io.wb_resps[5].bits.uop.is_unique, fp_pipeline.io.wb[1].bits.uop.is_unique connect rob.io.wb_resps[5].bits.uop.uses_stq, fp_pipeline.io.wb[1].bits.uop.uses_stq connect rob.io.wb_resps[5].bits.uop.uses_ldq, fp_pipeline.io.wb[1].bits.uop.uses_ldq connect rob.io.wb_resps[5].bits.uop.mem_signed, fp_pipeline.io.wb[1].bits.uop.mem_signed connect rob.io.wb_resps[5].bits.uop.mem_size, fp_pipeline.io.wb[1].bits.uop.mem_size connect rob.io.wb_resps[5].bits.uop.mem_cmd, fp_pipeline.io.wb[1].bits.uop.mem_cmd connect rob.io.wb_resps[5].bits.uop.exc_cause, fp_pipeline.io.wb[1].bits.uop.exc_cause connect rob.io.wb_resps[5].bits.uop.exception, fp_pipeline.io.wb[1].bits.uop.exception connect rob.io.wb_resps[5].bits.uop.stale_pdst, fp_pipeline.io.wb[1].bits.uop.stale_pdst connect rob.io.wb_resps[5].bits.uop.ppred_busy, fp_pipeline.io.wb[1].bits.uop.ppred_busy connect rob.io.wb_resps[5].bits.uop.prs3_busy, fp_pipeline.io.wb[1].bits.uop.prs3_busy connect rob.io.wb_resps[5].bits.uop.prs2_busy, fp_pipeline.io.wb[1].bits.uop.prs2_busy connect rob.io.wb_resps[5].bits.uop.prs1_busy, fp_pipeline.io.wb[1].bits.uop.prs1_busy connect rob.io.wb_resps[5].bits.uop.ppred, fp_pipeline.io.wb[1].bits.uop.ppred connect rob.io.wb_resps[5].bits.uop.prs3, fp_pipeline.io.wb[1].bits.uop.prs3 connect rob.io.wb_resps[5].bits.uop.prs2, fp_pipeline.io.wb[1].bits.uop.prs2 connect rob.io.wb_resps[5].bits.uop.prs1, fp_pipeline.io.wb[1].bits.uop.prs1 connect rob.io.wb_resps[5].bits.uop.pdst, fp_pipeline.io.wb[1].bits.uop.pdst connect rob.io.wb_resps[5].bits.uop.rxq_idx, fp_pipeline.io.wb[1].bits.uop.rxq_idx connect rob.io.wb_resps[5].bits.uop.stq_idx, fp_pipeline.io.wb[1].bits.uop.stq_idx connect rob.io.wb_resps[5].bits.uop.ldq_idx, fp_pipeline.io.wb[1].bits.uop.ldq_idx connect rob.io.wb_resps[5].bits.uop.rob_idx, fp_pipeline.io.wb[1].bits.uop.rob_idx connect rob.io.wb_resps[5].bits.uop.fp_ctrl.vec, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.vec connect rob.io.wb_resps[5].bits.uop.fp_ctrl.wflags, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.wflags connect rob.io.wb_resps[5].bits.uop.fp_ctrl.sqrt, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.sqrt connect rob.io.wb_resps[5].bits.uop.fp_ctrl.div, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.div connect rob.io.wb_resps[5].bits.uop.fp_ctrl.fma, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.fma connect rob.io.wb_resps[5].bits.uop.fp_ctrl.fastpipe, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.fastpipe connect rob.io.wb_resps[5].bits.uop.fp_ctrl.toint, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.toint connect rob.io.wb_resps[5].bits.uop.fp_ctrl.fromint, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.fromint connect rob.io.wb_resps[5].bits.uop.fp_ctrl.typeTagOut, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.typeTagOut connect rob.io.wb_resps[5].bits.uop.fp_ctrl.typeTagIn, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.typeTagIn connect rob.io.wb_resps[5].bits.uop.fp_ctrl.swap23, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.swap23 connect rob.io.wb_resps[5].bits.uop.fp_ctrl.swap12, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.swap12 connect rob.io.wb_resps[5].bits.uop.fp_ctrl.ren3, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.ren3 connect rob.io.wb_resps[5].bits.uop.fp_ctrl.ren2, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.ren2 connect rob.io.wb_resps[5].bits.uop.fp_ctrl.ren1, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.ren1 connect rob.io.wb_resps[5].bits.uop.fp_ctrl.wen, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.wen connect rob.io.wb_resps[5].bits.uop.fp_ctrl.ldst, fp_pipeline.io.wb[1].bits.uop.fp_ctrl.ldst connect rob.io.wb_resps[5].bits.uop.op2_sel, fp_pipeline.io.wb[1].bits.uop.op2_sel connect rob.io.wb_resps[5].bits.uop.op1_sel, fp_pipeline.io.wb[1].bits.uop.op1_sel connect rob.io.wb_resps[5].bits.uop.imm_packed, fp_pipeline.io.wb[1].bits.uop.imm_packed connect rob.io.wb_resps[5].bits.uop.pimm, fp_pipeline.io.wb[1].bits.uop.pimm connect rob.io.wb_resps[5].bits.uop.imm_sel, fp_pipeline.io.wb[1].bits.uop.imm_sel connect rob.io.wb_resps[5].bits.uop.imm_rename, fp_pipeline.io.wb[1].bits.uop.imm_rename connect rob.io.wb_resps[5].bits.uop.taken, fp_pipeline.io.wb[1].bits.uop.taken connect rob.io.wb_resps[5].bits.uop.pc_lob, fp_pipeline.io.wb[1].bits.uop.pc_lob connect rob.io.wb_resps[5].bits.uop.edge_inst, fp_pipeline.io.wb[1].bits.uop.edge_inst connect rob.io.wb_resps[5].bits.uop.ftq_idx, fp_pipeline.io.wb[1].bits.uop.ftq_idx connect rob.io.wb_resps[5].bits.uop.is_mov, fp_pipeline.io.wb[1].bits.uop.is_mov connect rob.io.wb_resps[5].bits.uop.is_rocc, fp_pipeline.io.wb[1].bits.uop.is_rocc connect rob.io.wb_resps[5].bits.uop.is_sys_pc2epc, fp_pipeline.io.wb[1].bits.uop.is_sys_pc2epc connect rob.io.wb_resps[5].bits.uop.is_eret, fp_pipeline.io.wb[1].bits.uop.is_eret connect rob.io.wb_resps[5].bits.uop.is_amo, fp_pipeline.io.wb[1].bits.uop.is_amo connect rob.io.wb_resps[5].bits.uop.is_sfence, fp_pipeline.io.wb[1].bits.uop.is_sfence connect rob.io.wb_resps[5].bits.uop.is_fencei, fp_pipeline.io.wb[1].bits.uop.is_fencei connect rob.io.wb_resps[5].bits.uop.is_fence, fp_pipeline.io.wb[1].bits.uop.is_fence connect rob.io.wb_resps[5].bits.uop.is_sfb, fp_pipeline.io.wb[1].bits.uop.is_sfb connect rob.io.wb_resps[5].bits.uop.br_type, fp_pipeline.io.wb[1].bits.uop.br_type connect rob.io.wb_resps[5].bits.uop.br_tag, fp_pipeline.io.wb[1].bits.uop.br_tag connect rob.io.wb_resps[5].bits.uop.br_mask, fp_pipeline.io.wb[1].bits.uop.br_mask connect rob.io.wb_resps[5].bits.uop.dis_col_sel, fp_pipeline.io.wb[1].bits.uop.dis_col_sel connect rob.io.wb_resps[5].bits.uop.iw_p3_bypass_hint, fp_pipeline.io.wb[1].bits.uop.iw_p3_bypass_hint connect rob.io.wb_resps[5].bits.uop.iw_p2_bypass_hint, fp_pipeline.io.wb[1].bits.uop.iw_p2_bypass_hint connect rob.io.wb_resps[5].bits.uop.iw_p1_bypass_hint, fp_pipeline.io.wb[1].bits.uop.iw_p1_bypass_hint connect rob.io.wb_resps[5].bits.uop.iw_p2_speculative_child, fp_pipeline.io.wb[1].bits.uop.iw_p2_speculative_child connect rob.io.wb_resps[5].bits.uop.iw_p1_speculative_child, fp_pipeline.io.wb[1].bits.uop.iw_p1_speculative_child connect rob.io.wb_resps[5].bits.uop.iw_issued_partial_dgen, fp_pipeline.io.wb[1].bits.uop.iw_issued_partial_dgen connect rob.io.wb_resps[5].bits.uop.iw_issued_partial_agen, fp_pipeline.io.wb[1].bits.uop.iw_issued_partial_agen connect rob.io.wb_resps[5].bits.uop.iw_issued, fp_pipeline.io.wb[1].bits.uop.iw_issued connect rob.io.wb_resps[5].bits.uop.fu_code[0], fp_pipeline.io.wb[1].bits.uop.fu_code[0] connect rob.io.wb_resps[5].bits.uop.fu_code[1], fp_pipeline.io.wb[1].bits.uop.fu_code[1] connect rob.io.wb_resps[5].bits.uop.fu_code[2], fp_pipeline.io.wb[1].bits.uop.fu_code[2] connect rob.io.wb_resps[5].bits.uop.fu_code[3], fp_pipeline.io.wb[1].bits.uop.fu_code[3] connect rob.io.wb_resps[5].bits.uop.fu_code[4], fp_pipeline.io.wb[1].bits.uop.fu_code[4] connect rob.io.wb_resps[5].bits.uop.fu_code[5], fp_pipeline.io.wb[1].bits.uop.fu_code[5] connect rob.io.wb_resps[5].bits.uop.fu_code[6], fp_pipeline.io.wb[1].bits.uop.fu_code[6] connect rob.io.wb_resps[5].bits.uop.fu_code[7], fp_pipeline.io.wb[1].bits.uop.fu_code[7] connect rob.io.wb_resps[5].bits.uop.fu_code[8], fp_pipeline.io.wb[1].bits.uop.fu_code[8] connect rob.io.wb_resps[5].bits.uop.fu_code[9], fp_pipeline.io.wb[1].bits.uop.fu_code[9] connect rob.io.wb_resps[5].bits.uop.iq_type[0], fp_pipeline.io.wb[1].bits.uop.iq_type[0] connect rob.io.wb_resps[5].bits.uop.iq_type[1], fp_pipeline.io.wb[1].bits.uop.iq_type[1] connect rob.io.wb_resps[5].bits.uop.iq_type[2], fp_pipeline.io.wb[1].bits.uop.iq_type[2] connect rob.io.wb_resps[5].bits.uop.iq_type[3], fp_pipeline.io.wb[1].bits.uop.iq_type[3] connect rob.io.wb_resps[5].bits.uop.debug_pc, fp_pipeline.io.wb[1].bits.uop.debug_pc connect rob.io.wb_resps[5].bits.uop.is_rvc, fp_pipeline.io.wb[1].bits.uop.is_rvc connect rob.io.wb_resps[5].bits.uop.debug_inst, fp_pipeline.io.wb[1].bits.uop.debug_inst connect rob.io.wb_resps[5].bits.uop.inst, fp_pipeline.io.wb[1].bits.uop.inst connect rob.io.wb_resps[5].valid, fp_pipeline.io.wb[1].valid node rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp = bits(fp_pipeline.io.wb[1].bits.data, 63, 52) node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isZero_T = bits(rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp, 11, 9) node rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isZero = eq(_rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isSpecial_T = bits(rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp, 11, 10) node rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isSpecial = eq(_rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire rob_io_wb_resps_5_bits_data_unrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isNaN_T = bits(rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp, 9, 9) node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isNaN_T_1 = and(rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isSpecial, _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isNaN_T) connect rob_io_wb_resps_5_bits_data_unrecoded_rawIn.isNaN, _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isNaN_T_1 node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T = bits(rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp, 9, 9) node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T_1 = eq(_rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T_2 = and(rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isSpecial, _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T_1) connect rob_io_wb_resps_5_bits_data_unrecoded_rawIn.isInf, _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T_2 connect rob_io_wb_resps_5_bits_data_unrecoded_rawIn.isZero, rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isZero node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sign_T = bits(fp_pipeline.io.wb[1].bits.data, 64, 64) connect rob_io_wb_resps_5_bits_data_unrecoded_rawIn.sign, _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sign_T node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sExp_T = cvt(rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp) connect rob_io_wb_resps_5_bits_data_unrecoded_rawIn.sExp, _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sExp_T node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T = eq(rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isZero, UInt<1>(0h0)) node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T) node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_2 = bits(fp_pipeline.io.wb[1].bits.data, 51, 0) node _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_3 = cat(_rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_1, _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_2) connect rob_io_wb_resps_5_bits_data_unrecoded_rawIn.sig, _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_3 node rob_io_wb_resps_5_bits_data_unrecoded_isSubnormal = lt(rob_io_wb_resps_5_bits_data_unrecoded_rawIn.sExp, asSInt(UInt<12>(0h402))) node _rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist_T = bits(rob_io_wb_resps_5_bits_data_unrecoded_rawIn.sExp, 5, 0) node _rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist_T) node rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist = tail(_rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist_T_1, 1) node _rob_io_wb_resps_5_bits_data_unrecoded_denormFract_T = shr(rob_io_wb_resps_5_bits_data_unrecoded_rawIn.sig, 1) node _rob_io_wb_resps_5_bits_data_unrecoded_denormFract_T_1 = dshr(_rob_io_wb_resps_5_bits_data_unrecoded_denormFract_T, rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist) node rob_io_wb_resps_5_bits_data_unrecoded_denormFract = bits(_rob_io_wb_resps_5_bits_data_unrecoded_denormFract_T_1, 51, 0) node _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T = bits(rob_io_wb_resps_5_bits_data_unrecoded_rawIn.sExp, 10, 0) node _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_1 = sub(_rob_io_wb_resps_5_bits_data_unrecoded_expOut_T, UInt<11>(0h401)) node _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_2 = tail(_rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_1, 1) node _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_3 = mux(rob_io_wb_resps_5_bits_data_unrecoded_isSubnormal, UInt<1>(0h0), _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_2) node _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_4 = or(rob_io_wb_resps_5_bits_data_unrecoded_rawIn.isNaN, rob_io_wb_resps_5_bits_data_unrecoded_rawIn.isInf) node _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_5 = mux(_rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_4, UInt<11>(0h7ff), UInt<11>(0h0)) node rob_io_wb_resps_5_bits_data_unrecoded_expOut = or(_rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_3, _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_5) node _rob_io_wb_resps_5_bits_data_unrecoded_fractOut_T = bits(rob_io_wb_resps_5_bits_data_unrecoded_rawIn.sig, 51, 0) node _rob_io_wb_resps_5_bits_data_unrecoded_fractOut_T_1 = mux(rob_io_wb_resps_5_bits_data_unrecoded_rawIn.isInf, UInt<1>(0h0), _rob_io_wb_resps_5_bits_data_unrecoded_fractOut_T) node rob_io_wb_resps_5_bits_data_unrecoded_fractOut = mux(rob_io_wb_resps_5_bits_data_unrecoded_isSubnormal, rob_io_wb_resps_5_bits_data_unrecoded_denormFract, _rob_io_wb_resps_5_bits_data_unrecoded_fractOut_T_1) node rob_io_wb_resps_5_bits_data_unrecoded_hi = cat(rob_io_wb_resps_5_bits_data_unrecoded_rawIn.sign, rob_io_wb_resps_5_bits_data_unrecoded_expOut) node rob_io_wb_resps_5_bits_data_unrecoded = cat(rob_io_wb_resps_5_bits_data_unrecoded_hi, rob_io_wb_resps_5_bits_data_unrecoded_fractOut) node _rob_io_wb_resps_5_bits_data_prevRecoded_T = bits(fp_pipeline.io.wb[1].bits.data, 31, 31) node _rob_io_wb_resps_5_bits_data_prevRecoded_T_1 = bits(fp_pipeline.io.wb[1].bits.data, 52, 52) node _rob_io_wb_resps_5_bits_data_prevRecoded_T_2 = bits(fp_pipeline.io.wb[1].bits.data, 30, 0) node rob_io_wb_resps_5_bits_data_prevRecoded_hi = cat(_rob_io_wb_resps_5_bits_data_prevRecoded_T, _rob_io_wb_resps_5_bits_data_prevRecoded_T_1) node rob_io_wb_resps_5_bits_data_prevRecoded = cat(rob_io_wb_resps_5_bits_data_prevRecoded_hi, _rob_io_wb_resps_5_bits_data_prevRecoded_T_2) node rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp = bits(rob_io_wb_resps_5_bits_data_prevRecoded, 31, 23) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isZero_T = bits(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp, 8, 6) node rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isZero = eq(_rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isZero_T, UInt<1>(0h0)) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isSpecial_T = bits(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp, 8, 7) node rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isSpecial = eq(_rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isSpecial_T, UInt<2>(0h3)) wire rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isNaN_T = bits(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp, 6, 6) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1 = and(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isSpecial, _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isNaN_T) connect rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.isNaN, _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1 node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T = bits(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp, 6, 6) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T_1 = eq(_rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T, UInt<1>(0h0)) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T_2 = and(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isSpecial, _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T_1) connect rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.isInf, _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T_2 connect rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.isZero, rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isZero node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sign_T = bits(rob_io_wb_resps_5_bits_data_prevRecoded, 32, 32) connect rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.sign, _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sign_T node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sExp_T = cvt(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp) connect rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.sExp, _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sExp_T node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T = eq(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isZero, UInt<1>(0h0)) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_2 = bits(rob_io_wb_resps_5_bits_data_prevRecoded, 22, 0) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_3 = cat(_rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_1, _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_2) connect rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.sig, _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_3 node rob_io_wb_resps_5_bits_data_prevUnrecoded_isSubnormal = lt(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.sExp, asSInt(UInt<9>(0h82))) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist_T = bits(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.sExp, 4, 0) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist_T_1 = sub(UInt<1>(0h1), _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist_T) node rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist = tail(_rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist_T_1, 1) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract_T = shr(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.sig, 1) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract_T_1 = dshr(_rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract_T, rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist) node rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract = bits(_rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract_T_1, 22, 0) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T = bits(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.sExp, 7, 0) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_1 = sub(_rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T, UInt<8>(0h81)) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_2 = tail(_rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_1, 1) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_3 = mux(rob_io_wb_resps_5_bits_data_prevUnrecoded_isSubnormal, UInt<1>(0h0), _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_2) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_4 = or(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.isNaN, rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.isInf) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_5 = mux(_rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_4, UInt<8>(0hff), UInt<8>(0h0)) node rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut = or(_rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_3, _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_5) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut_T = bits(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.sig, 22, 0) node _rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut_T_1 = mux(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.isInf, UInt<1>(0h0), _rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut_T) node rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut = mux(rob_io_wb_resps_5_bits_data_prevUnrecoded_isSubnormal, rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract, _rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut_T_1) node rob_io_wb_resps_5_bits_data_prevUnrecoded_hi = cat(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn.sign, rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut) node rob_io_wb_resps_5_bits_data_prevUnrecoded = cat(rob_io_wb_resps_5_bits_data_prevUnrecoded_hi, rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut) node _rob_io_wb_resps_5_bits_data_T = shr(rob_io_wb_resps_5_bits_data_unrecoded, 32) node _rob_io_wb_resps_5_bits_data_T_1 = bits(fp_pipeline.io.wb[1].bits.data, 63, 61) node _rob_io_wb_resps_5_bits_data_T_2 = andr(_rob_io_wb_resps_5_bits_data_T_1) node _rob_io_wb_resps_5_bits_data_T_3 = bits(rob_io_wb_resps_5_bits_data_unrecoded, 31, 0) node _rob_io_wb_resps_5_bits_data_T_4 = mux(_rob_io_wb_resps_5_bits_data_T_2, rob_io_wb_resps_5_bits_data_prevUnrecoded, _rob_io_wb_resps_5_bits_data_T_3) node _rob_io_wb_resps_5_bits_data_T_5 = cat(_rob_io_wb_resps_5_bits_data_T, _rob_io_wb_resps_5_bits_data_T_4) connect rob.io.wb_resps[5].bits.data, _rob_io_wb_resps_5_bits_data_T_5 connect rob.io.brupdate, brupdate connect io.lsu.status, csr.io.status connect io.lsu.bp, csr.io.bp connect io.lsu.mcontext, csr.io.mcontext connect io.lsu.scontext, csr.io.scontext connect alu_exe_unit_0.io_status.uie, csr.io.status.uie connect alu_exe_unit_0.io_status.sie, csr.io.status.sie connect alu_exe_unit_0.io_status.hie, csr.io.status.hie connect alu_exe_unit_0.io_status.mie, csr.io.status.mie connect alu_exe_unit_0.io_status.upie, csr.io.status.upie connect alu_exe_unit_0.io_status.spie, csr.io.status.spie connect alu_exe_unit_0.io_status.ube, csr.io.status.ube connect alu_exe_unit_0.io_status.mpie, csr.io.status.mpie connect alu_exe_unit_0.io_status.spp, csr.io.status.spp connect alu_exe_unit_0.io_status.vs, csr.io.status.vs connect alu_exe_unit_0.io_status.mpp, csr.io.status.mpp connect alu_exe_unit_0.io_status.fs, csr.io.status.fs connect alu_exe_unit_0.io_status.xs, csr.io.status.xs connect alu_exe_unit_0.io_status.mprv, csr.io.status.mprv connect alu_exe_unit_0.io_status.sum, csr.io.status.sum connect alu_exe_unit_0.io_status.mxr, csr.io.status.mxr connect alu_exe_unit_0.io_status.tvm, csr.io.status.tvm connect alu_exe_unit_0.io_status.tw, csr.io.status.tw connect alu_exe_unit_0.io_status.tsr, csr.io.status.tsr connect alu_exe_unit_0.io_status.zero1, csr.io.status.zero1 connect alu_exe_unit_0.io_status.sd_rv32, csr.io.status.sd_rv32 connect alu_exe_unit_0.io_status.uxl, csr.io.status.uxl connect alu_exe_unit_0.io_status.sxl, csr.io.status.sxl connect alu_exe_unit_0.io_status.sbe, csr.io.status.sbe connect alu_exe_unit_0.io_status.mbe, csr.io.status.mbe connect alu_exe_unit_0.io_status.gva, csr.io.status.gva connect alu_exe_unit_0.io_status.mpv, csr.io.status.mpv connect alu_exe_unit_0.io_status.zero2, csr.io.status.zero2 connect alu_exe_unit_0.io_status.sd, csr.io.status.sd connect alu_exe_unit_0.io_status.v, csr.io.status.v connect alu_exe_unit_0.io_status.prv, csr.io.status.prv connect alu_exe_unit_0.io_status.dv, csr.io.status.dv connect alu_exe_unit_0.io_status.dprv, csr.io.status.dprv connect alu_exe_unit_0.io_status.isa, csr.io.status.isa connect alu_exe_unit_0.io_status.wfi, csr.io.status.wfi connect alu_exe_unit_0.io_status.cease, csr.io.status.cease connect alu_exe_unit_0.io_status.debug, csr.io.status.debug connect alu_exe_unit_1.io_status.uie, csr.io.status.uie connect alu_exe_unit_1.io_status.sie, csr.io.status.sie connect alu_exe_unit_1.io_status.hie, csr.io.status.hie connect alu_exe_unit_1.io_status.mie, csr.io.status.mie connect alu_exe_unit_1.io_status.upie, csr.io.status.upie connect alu_exe_unit_1.io_status.spie, csr.io.status.spie connect alu_exe_unit_1.io_status.ube, csr.io.status.ube connect alu_exe_unit_1.io_status.mpie, csr.io.status.mpie connect alu_exe_unit_1.io_status.spp, csr.io.status.spp connect alu_exe_unit_1.io_status.vs, csr.io.status.vs connect alu_exe_unit_1.io_status.mpp, csr.io.status.mpp connect alu_exe_unit_1.io_status.fs, csr.io.status.fs connect alu_exe_unit_1.io_status.xs, csr.io.status.xs connect alu_exe_unit_1.io_status.mprv, csr.io.status.mprv connect alu_exe_unit_1.io_status.sum, csr.io.status.sum connect alu_exe_unit_1.io_status.mxr, csr.io.status.mxr connect alu_exe_unit_1.io_status.tvm, csr.io.status.tvm connect alu_exe_unit_1.io_status.tw, csr.io.status.tw connect alu_exe_unit_1.io_status.tsr, csr.io.status.tsr connect alu_exe_unit_1.io_status.zero1, csr.io.status.zero1 connect alu_exe_unit_1.io_status.sd_rv32, csr.io.status.sd_rv32 connect alu_exe_unit_1.io_status.uxl, csr.io.status.uxl connect alu_exe_unit_1.io_status.sxl, csr.io.status.sxl connect alu_exe_unit_1.io_status.sbe, csr.io.status.sbe connect alu_exe_unit_1.io_status.mbe, csr.io.status.mbe connect alu_exe_unit_1.io_status.gva, csr.io.status.gva connect alu_exe_unit_1.io_status.mpv, csr.io.status.mpv connect alu_exe_unit_1.io_status.zero2, csr.io.status.zero2 connect alu_exe_unit_1.io_status.sd, csr.io.status.sd connect alu_exe_unit_1.io_status.v, csr.io.status.v connect alu_exe_unit_1.io_status.prv, csr.io.status.prv connect alu_exe_unit_1.io_status.dv, csr.io.status.dv connect alu_exe_unit_1.io_status.dprv, csr.io.status.dprv connect alu_exe_unit_1.io_status.isa, csr.io.status.isa connect alu_exe_unit_1.io_status.wfi, csr.io.status.wfi connect alu_exe_unit_1.io_status.cease, csr.io.status.cease connect alu_exe_unit_1.io_status.debug, csr.io.status.debug connect mem_exe_unit_0.io_status.uie, csr.io.status.uie connect mem_exe_unit_0.io_status.sie, csr.io.status.sie connect mem_exe_unit_0.io_status.hie, csr.io.status.hie connect mem_exe_unit_0.io_status.mie, csr.io.status.mie connect mem_exe_unit_0.io_status.upie, csr.io.status.upie connect mem_exe_unit_0.io_status.spie, csr.io.status.spie connect mem_exe_unit_0.io_status.ube, csr.io.status.ube connect mem_exe_unit_0.io_status.mpie, csr.io.status.mpie connect mem_exe_unit_0.io_status.spp, csr.io.status.spp connect mem_exe_unit_0.io_status.vs, csr.io.status.vs connect mem_exe_unit_0.io_status.mpp, csr.io.status.mpp connect mem_exe_unit_0.io_status.fs, csr.io.status.fs connect mem_exe_unit_0.io_status.xs, csr.io.status.xs connect mem_exe_unit_0.io_status.mprv, csr.io.status.mprv connect mem_exe_unit_0.io_status.sum, csr.io.status.sum connect mem_exe_unit_0.io_status.mxr, csr.io.status.mxr connect mem_exe_unit_0.io_status.tvm, csr.io.status.tvm connect mem_exe_unit_0.io_status.tw, csr.io.status.tw connect mem_exe_unit_0.io_status.tsr, csr.io.status.tsr connect mem_exe_unit_0.io_status.zero1, csr.io.status.zero1 connect mem_exe_unit_0.io_status.sd_rv32, csr.io.status.sd_rv32 connect mem_exe_unit_0.io_status.uxl, csr.io.status.uxl connect mem_exe_unit_0.io_status.sxl, csr.io.status.sxl connect mem_exe_unit_0.io_status.sbe, csr.io.status.sbe connect mem_exe_unit_0.io_status.mbe, csr.io.status.mbe connect mem_exe_unit_0.io_status.gva, csr.io.status.gva connect mem_exe_unit_0.io_status.mpv, csr.io.status.mpv connect mem_exe_unit_0.io_status.zero2, csr.io.status.zero2 connect mem_exe_unit_0.io_status.sd, csr.io.status.sd connect mem_exe_unit_0.io_status.v, csr.io.status.v connect mem_exe_unit_0.io_status.prv, csr.io.status.prv connect mem_exe_unit_0.io_status.dv, csr.io.status.dv connect mem_exe_unit_0.io_status.dprv, csr.io.status.dprv connect mem_exe_unit_0.io_status.isa, csr.io.status.isa connect mem_exe_unit_0.io_status.wfi, csr.io.status.wfi connect mem_exe_unit_0.io_status.cease, csr.io.status.cease connect mem_exe_unit_0.io_status.debug, csr.io.status.debug connect mem_exe_unit_1.io_status.uie, csr.io.status.uie connect mem_exe_unit_1.io_status.sie, csr.io.status.sie connect mem_exe_unit_1.io_status.hie, csr.io.status.hie connect mem_exe_unit_1.io_status.mie, csr.io.status.mie connect mem_exe_unit_1.io_status.upie, csr.io.status.upie connect mem_exe_unit_1.io_status.spie, csr.io.status.spie connect mem_exe_unit_1.io_status.ube, csr.io.status.ube connect mem_exe_unit_1.io_status.mpie, csr.io.status.mpie connect mem_exe_unit_1.io_status.spp, csr.io.status.spp connect mem_exe_unit_1.io_status.vs, csr.io.status.vs connect mem_exe_unit_1.io_status.mpp, csr.io.status.mpp connect mem_exe_unit_1.io_status.fs, csr.io.status.fs connect mem_exe_unit_1.io_status.xs, csr.io.status.xs connect mem_exe_unit_1.io_status.mprv, csr.io.status.mprv connect mem_exe_unit_1.io_status.sum, csr.io.status.sum connect mem_exe_unit_1.io_status.mxr, csr.io.status.mxr connect mem_exe_unit_1.io_status.tvm, csr.io.status.tvm connect mem_exe_unit_1.io_status.tw, csr.io.status.tw connect mem_exe_unit_1.io_status.tsr, csr.io.status.tsr connect mem_exe_unit_1.io_status.zero1, csr.io.status.zero1 connect mem_exe_unit_1.io_status.sd_rv32, csr.io.status.sd_rv32 connect mem_exe_unit_1.io_status.uxl, csr.io.status.uxl connect mem_exe_unit_1.io_status.sxl, csr.io.status.sxl connect mem_exe_unit_1.io_status.sbe, csr.io.status.sbe connect mem_exe_unit_1.io_status.mbe, csr.io.status.mbe connect mem_exe_unit_1.io_status.gva, csr.io.status.gva connect mem_exe_unit_1.io_status.mpv, csr.io.status.mpv connect mem_exe_unit_1.io_status.zero2, csr.io.status.zero2 connect mem_exe_unit_1.io_status.sd, csr.io.status.sd connect mem_exe_unit_1.io_status.v, csr.io.status.v connect mem_exe_unit_1.io_status.prv, csr.io.status.prv connect mem_exe_unit_1.io_status.dv, csr.io.status.dv connect mem_exe_unit_1.io_status.dprv, csr.io.status.dprv connect mem_exe_unit_1.io_status.isa, csr.io.status.isa connect mem_exe_unit_1.io_status.wfi, csr.io.status.wfi connect mem_exe_unit_1.io_status.cease, csr.io.status.cease connect mem_exe_unit_1.io_status.debug, csr.io.status.debug connect unique_exe_unit_0.io_status.uie, csr.io.status.uie connect unique_exe_unit_0.io_status.sie, csr.io.status.sie connect unique_exe_unit_0.io_status.hie, csr.io.status.hie connect unique_exe_unit_0.io_status.mie, csr.io.status.mie connect unique_exe_unit_0.io_status.upie, csr.io.status.upie connect unique_exe_unit_0.io_status.spie, csr.io.status.spie connect unique_exe_unit_0.io_status.ube, csr.io.status.ube connect unique_exe_unit_0.io_status.mpie, csr.io.status.mpie connect unique_exe_unit_0.io_status.spp, csr.io.status.spp connect unique_exe_unit_0.io_status.vs, csr.io.status.vs connect unique_exe_unit_0.io_status.mpp, csr.io.status.mpp connect unique_exe_unit_0.io_status.fs, csr.io.status.fs connect unique_exe_unit_0.io_status.xs, csr.io.status.xs connect unique_exe_unit_0.io_status.mprv, csr.io.status.mprv connect unique_exe_unit_0.io_status.sum, csr.io.status.sum connect unique_exe_unit_0.io_status.mxr, csr.io.status.mxr connect unique_exe_unit_0.io_status.tvm, csr.io.status.tvm connect unique_exe_unit_0.io_status.tw, csr.io.status.tw connect unique_exe_unit_0.io_status.tsr, csr.io.status.tsr connect unique_exe_unit_0.io_status.zero1, csr.io.status.zero1 connect unique_exe_unit_0.io_status.sd_rv32, csr.io.status.sd_rv32 connect unique_exe_unit_0.io_status.uxl, csr.io.status.uxl connect unique_exe_unit_0.io_status.sxl, csr.io.status.sxl connect unique_exe_unit_0.io_status.sbe, csr.io.status.sbe connect unique_exe_unit_0.io_status.mbe, csr.io.status.mbe connect unique_exe_unit_0.io_status.gva, csr.io.status.gva connect unique_exe_unit_0.io_status.mpv, csr.io.status.mpv connect unique_exe_unit_0.io_status.zero2, csr.io.status.zero2 connect unique_exe_unit_0.io_status.sd, csr.io.status.sd connect unique_exe_unit_0.io_status.v, csr.io.status.v connect unique_exe_unit_0.io_status.prv, csr.io.status.prv connect unique_exe_unit_0.io_status.dv, csr.io.status.dv connect unique_exe_unit_0.io_status.dprv, csr.io.status.dprv connect unique_exe_unit_0.io_status.isa, csr.io.status.isa connect unique_exe_unit_0.io_status.wfi, csr.io.status.wfi connect unique_exe_unit_0.io_status.cease, csr.io.status.cease connect unique_exe_unit_0.io_status.debug, csr.io.status.debug connect fp_pipeline.io.status.uie, csr.io.status.uie connect fp_pipeline.io.status.sie, csr.io.status.sie connect fp_pipeline.io.status.hie, csr.io.status.hie connect fp_pipeline.io.status.mie, csr.io.status.mie connect fp_pipeline.io.status.upie, csr.io.status.upie connect fp_pipeline.io.status.spie, csr.io.status.spie connect fp_pipeline.io.status.ube, csr.io.status.ube connect fp_pipeline.io.status.mpie, csr.io.status.mpie connect fp_pipeline.io.status.spp, csr.io.status.spp connect fp_pipeline.io.status.vs, csr.io.status.vs connect fp_pipeline.io.status.mpp, csr.io.status.mpp connect fp_pipeline.io.status.fs, csr.io.status.fs connect fp_pipeline.io.status.xs, csr.io.status.xs connect fp_pipeline.io.status.mprv, csr.io.status.mprv connect fp_pipeline.io.status.sum, csr.io.status.sum connect fp_pipeline.io.status.mxr, csr.io.status.mxr connect fp_pipeline.io.status.tvm, csr.io.status.tvm connect fp_pipeline.io.status.tw, csr.io.status.tw connect fp_pipeline.io.status.tsr, csr.io.status.tsr connect fp_pipeline.io.status.zero1, csr.io.status.zero1 connect fp_pipeline.io.status.sd_rv32, csr.io.status.sd_rv32 connect fp_pipeline.io.status.uxl, csr.io.status.uxl connect fp_pipeline.io.status.sxl, csr.io.status.sxl connect fp_pipeline.io.status.sbe, csr.io.status.sbe connect fp_pipeline.io.status.mbe, csr.io.status.mbe connect fp_pipeline.io.status.gva, csr.io.status.gva connect fp_pipeline.io.status.mpv, csr.io.status.mpv connect fp_pipeline.io.status.zero2, csr.io.status.zero2 connect fp_pipeline.io.status.sd, csr.io.status.sd connect fp_pipeline.io.status.v, csr.io.status.v connect fp_pipeline.io.status.prv, csr.io.status.prv connect fp_pipeline.io.status.dv, csr.io.status.dv connect fp_pipeline.io.status.dprv, csr.io.status.dprv connect fp_pipeline.io.status.isa, csr.io.status.isa connect fp_pipeline.io.status.wfi, csr.io.status.wfi connect fp_pipeline.io.status.cease, csr.io.status.cease connect fp_pipeline.io.status.debug, csr.io.status.debug connect rob.io.lsu_clr_bsy[0].bits, io.lsu.clr_bsy[0].bits connect rob.io.lsu_clr_bsy[0].valid, io.lsu.clr_bsy[0].valid connect rob.io.lsu_clr_bsy[1].bits, io.lsu.clr_bsy[1].bits connect rob.io.lsu_clr_bsy[1].valid, io.lsu.clr_bsy[1].valid connect rob.io.lsu_clr_unsafe[0].bits, io.lsu.clr_unsafe[0].bits connect rob.io.lsu_clr_unsafe[0].valid, io.lsu.clr_unsafe[0].valid connect rob.io.lxcpt, io.lsu.lxcpt node _T_130 = eq(csr.io.singleStep, UInt<1>(0h0)) node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(_T_130, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: [core] single-step is unsupported.\n at core.scala:1242 assert (!(csr.io.singleStep), \"[core] single-step is unsupported.\")\n") : printf_5 assert(clock, _T_130, UInt<1>(0h1), "") : assert_5 reg fp_pipeline_io_flush_pipeline_REG : UInt<1>, clock connect fp_pipeline_io_flush_pipeline_REG, rob.io.flush.valid connect fp_pipeline.io.flush_pipeline, fp_pipeline_io_flush_pipeline_REG reg alu_exe_unit_0_io_kill_REG : UInt<1>, clock connect alu_exe_unit_0_io_kill_REG, rob.io.flush.valid connect alu_exe_unit_0.io_kill, alu_exe_unit_0_io_kill_REG reg alu_exe_unit_1_io_kill_REG : UInt<1>, clock connect alu_exe_unit_1_io_kill_REG, rob.io.flush.valid connect alu_exe_unit_1.io_kill, alu_exe_unit_1_io_kill_REG reg mem_exe_unit_0_io_kill_REG : UInt<1>, clock connect mem_exe_unit_0_io_kill_REG, rob.io.flush.valid connect mem_exe_unit_0.io_kill, mem_exe_unit_0_io_kill_REG reg mem_exe_unit_1_io_kill_REG : UInt<1>, clock connect mem_exe_unit_1_io_kill_REG, rob.io.flush.valid connect mem_exe_unit_1.io_kill, mem_exe_unit_1_io_kill_REG reg unique_exe_unit_0_io_kill_REG : UInt<1>, clock connect unique_exe_unit_0_io_kill_REG, rob.io.flush.valid connect unique_exe_unit_0.io_kill, unique_exe_unit_0_io_kill_REG node _T_134 = eq(rob.io.flush.valid, UInt<1>(0h0)) node _T_135 = and(rob.io.com_xcpt.valid, _T_134) node _T_136 = eq(_T_135, UInt<1>(0h0)) node _T_137 = asUInt(reset) node _T_138 = eq(_T_137, UInt<1>(0h0)) when _T_138 : node _T_139 = eq(_T_136, UInt<1>(0h0)) when _T_139 : printf(clock, UInt<1>(0h1), "Assertion failed: [core] exception occurred, but pipeline flush signal not set!\n at core.scala:1256 assert (!(rob.io.com_xcpt.valid && !rob.io.flush.valid),\n") : printf_6 assert(clock, _T_136, UInt<1>(0h1), "") : assert_6 regreset small : UInt<5>, clock, reset, UInt<5>(0h0) node nextSmall = add(small, UInt<1>(0h1)) node _T_140 = eq(UInt<1>(0h0), UInt<1>(0h0)) when _T_140 : connect small, nextSmall regreset large : UInt<27>, clock, reset, UInt<27>(0h0) node _large_T = bits(nextSmall, 5, 5) node _large_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _large_T_2 = and(_large_T, _large_T_1) when _large_T_2 : node _large_r_T = add(large, UInt<1>(0h1)) node _large_r_T_1 = tail(_large_r_T, 1) connect large, _large_r_T_1 node value = cat(large, small) node _T_141 = cat(rob.io.commit.valids[1], rob.io.commit.valids[0]) node _T_142 = orr(_T_141) node _T_143 = or(_T_142, csr.io.csr_stall) node _T_144 = or(_T_143, io.rocc.busy) node _T_145 = asUInt(reset) node _T_146 = or(_T_144, _T_145) when _T_146 : connect small, UInt<1>(0h0) node _large_T_3 = shr(UInt<1>(0h0), 5) connect large, _large_T_3 inst plusarg_reader of plusarg_reader_86 node _T_147 = dshr(value, plusarg_reader.out) node _T_148 = bits(_T_147, 0, 0) node _T_149 = eq(_T_148, UInt<1>(0h0)) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: Pipeline has hung.\n at core.scala:1273 assert (!(idle_cycles.value(PlusArg(\"boom_timeout\", 13, width=5))), \"Pipeline has hung.\")\n") : printf_7 assert(clock, _T_149, UInt<1>(0h1), "") : assert_7 connect fp_pipeline.io.debug_tsc_reg, debug_tsc_reg wire coreMonitorBundle : { clock : Clock, reset : UInt<1>, excpt : UInt<1>, priv_mode : UInt<3>, hartid : UInt<64>, timer : UInt<32>, valid : UInt<1>, pc : UInt<64>, wrdst : UInt<5>, wrdata : UInt<64>, wrenx : UInt<1>, wrenf : UInt<1>, rd0src : UInt<5>, rd0val : UInt<64>, rd1src : UInt<5>, rd1val : UInt<64>, inst : UInt<32>} invalidate coreMonitorBundle.inst invalidate coreMonitorBundle.rd1val invalidate coreMonitorBundle.rd1src invalidate coreMonitorBundle.rd0val invalidate coreMonitorBundle.rd0src invalidate coreMonitorBundle.wrenf invalidate coreMonitorBundle.wrenx invalidate coreMonitorBundle.wrdata invalidate coreMonitorBundle.wrdst invalidate coreMonitorBundle.pc invalidate coreMonitorBundle.valid invalidate coreMonitorBundle.timer invalidate coreMonitorBundle.hartid invalidate coreMonitorBundle.priv_mode invalidate coreMonitorBundle.excpt invalidate coreMonitorBundle.reset invalidate coreMonitorBundle.clock connect coreMonitorBundle.clock, clock connect coreMonitorBundle.reset, reset connect io.ptw.ptbr, csr.io.ptbr connect io.ptw.status, csr.io.status connect io.ptw.pmp, csr.io.pmp connect io.ptw.sfence.bits.hg, io.ifu.sfence.bits.hg connect io.ptw.sfence.bits.hv, io.ifu.sfence.bits.hv connect io.ptw.sfence.bits.asid, io.ifu.sfence.bits.asid connect io.ptw.sfence.bits.addr, io.ifu.sfence.bits.addr connect io.ptw.sfence.bits.rs2, io.ifu.sfence.bits.rs2 connect io.ptw.sfence.bits.rs1, io.ifu.sfence.bits.rs1 connect io.ptw.sfence.valid, io.ifu.sfence.valid invalidate io.rocc.exception invalidate io.rocc.interrupt invalidate io.rocc.busy invalidate io.rocc.mem.clock_enabled invalidate io.rocc.mem.keep_clock_enabled invalidate io.rocc.mem.perf.storeBufferEmptyAfterStore invalidate io.rocc.mem.perf.storeBufferEmptyAfterLoad invalidate io.rocc.mem.perf.canAcceptLoadThenLoad invalidate io.rocc.mem.perf.canAcceptStoreThenRMW invalidate io.rocc.mem.perf.canAcceptStoreThenLoad invalidate io.rocc.mem.perf.blocked invalidate io.rocc.mem.perf.tlbMiss invalidate io.rocc.mem.perf.grant invalidate io.rocc.mem.perf.release invalidate io.rocc.mem.perf.acquire invalidate io.rocc.mem.store_pending invalidate io.rocc.mem.ordered invalidate io.rocc.mem.s2_gpa_is_pte invalidate io.rocc.mem.s2_gpa invalidate io.rocc.mem.s2_xcpt.ae.st invalidate io.rocc.mem.s2_xcpt.ae.ld invalidate io.rocc.mem.s2_xcpt.gf.st invalidate io.rocc.mem.s2_xcpt.gf.ld invalidate io.rocc.mem.s2_xcpt.pf.st invalidate io.rocc.mem.s2_xcpt.pf.ld invalidate io.rocc.mem.s2_xcpt.ma.st invalidate io.rocc.mem.s2_xcpt.ma.ld invalidate io.rocc.mem.replay_next invalidate io.rocc.mem.resp.bits.store_data invalidate io.rocc.mem.resp.bits.data_raw invalidate io.rocc.mem.resp.bits.data_word_bypass invalidate io.rocc.mem.resp.bits.has_data invalidate io.rocc.mem.resp.bits.replay invalidate io.rocc.mem.resp.bits.mask invalidate io.rocc.mem.resp.bits.data invalidate io.rocc.mem.resp.bits.dv invalidate io.rocc.mem.resp.bits.dprv invalidate io.rocc.mem.resp.bits.signed invalidate io.rocc.mem.resp.bits.size invalidate io.rocc.mem.resp.bits.cmd invalidate io.rocc.mem.resp.bits.tag invalidate io.rocc.mem.resp.bits.addr invalidate io.rocc.mem.resp.valid invalidate io.rocc.mem.s2_paddr invalidate io.rocc.mem.s2_uncached invalidate io.rocc.mem.s2_kill invalidate io.rocc.mem.s2_nack_cause_raw invalidate io.rocc.mem.s2_nack invalidate io.rocc.mem.s1_data.mask invalidate io.rocc.mem.s1_data.data invalidate io.rocc.mem.s1_kill invalidate io.rocc.mem.req.bits.mask invalidate io.rocc.mem.req.bits.data invalidate io.rocc.mem.req.bits.no_xcpt invalidate io.rocc.mem.req.bits.no_alloc invalidate io.rocc.mem.req.bits.no_resp invalidate io.rocc.mem.req.bits.phys invalidate io.rocc.mem.req.bits.dv invalidate io.rocc.mem.req.bits.dprv invalidate io.rocc.mem.req.bits.signed invalidate io.rocc.mem.req.bits.size invalidate io.rocc.mem.req.bits.cmd invalidate io.rocc.mem.req.bits.tag invalidate io.rocc.mem.req.bits.addr invalidate io.rocc.mem.req.valid invalidate io.rocc.mem.req.ready invalidate io.rocc.resp.bits.data invalidate io.rocc.resp.bits.rd invalidate io.rocc.resp.valid invalidate io.rocc.resp.ready invalidate io.rocc.cmd.bits.status.uie invalidate io.rocc.cmd.bits.status.sie invalidate io.rocc.cmd.bits.status.hie invalidate io.rocc.cmd.bits.status.mie invalidate io.rocc.cmd.bits.status.upie invalidate io.rocc.cmd.bits.status.spie invalidate io.rocc.cmd.bits.status.ube invalidate io.rocc.cmd.bits.status.mpie invalidate io.rocc.cmd.bits.status.spp invalidate io.rocc.cmd.bits.status.vs invalidate io.rocc.cmd.bits.status.mpp invalidate io.rocc.cmd.bits.status.fs invalidate io.rocc.cmd.bits.status.xs invalidate io.rocc.cmd.bits.status.mprv invalidate io.rocc.cmd.bits.status.sum invalidate io.rocc.cmd.bits.status.mxr invalidate io.rocc.cmd.bits.status.tvm invalidate io.rocc.cmd.bits.status.tw invalidate io.rocc.cmd.bits.status.tsr invalidate io.rocc.cmd.bits.status.zero1 invalidate io.rocc.cmd.bits.status.sd_rv32 invalidate io.rocc.cmd.bits.status.uxl invalidate io.rocc.cmd.bits.status.sxl invalidate io.rocc.cmd.bits.status.sbe invalidate io.rocc.cmd.bits.status.mbe invalidate io.rocc.cmd.bits.status.gva invalidate io.rocc.cmd.bits.status.mpv invalidate io.rocc.cmd.bits.status.zero2 invalidate io.rocc.cmd.bits.status.sd invalidate io.rocc.cmd.bits.status.v invalidate io.rocc.cmd.bits.status.prv invalidate io.rocc.cmd.bits.status.dv invalidate io.rocc.cmd.bits.status.dprv invalidate io.rocc.cmd.bits.status.isa invalidate io.rocc.cmd.bits.status.wfi invalidate io.rocc.cmd.bits.status.cease invalidate io.rocc.cmd.bits.status.debug invalidate io.rocc.cmd.bits.rs2 invalidate io.rocc.cmd.bits.rs1 invalidate io.rocc.cmd.bits.inst.opcode invalidate io.rocc.cmd.bits.inst.rd invalidate io.rocc.cmd.bits.inst.xs2 invalidate io.rocc.cmd.bits.inst.xs1 invalidate io.rocc.cmd.bits.inst.xd invalidate io.rocc.cmd.bits.inst.rs1 invalidate io.rocc.cmd.bits.inst.rs2 invalidate io.rocc.cmd.bits.inst.funct invalidate io.rocc.cmd.valid invalidate io.rocc.cmd.ready node _io_rocc_exception_T = orr(csr.io.status.xs) node _io_rocc_exception_T_1 = and(csr.io.exception, _io_rocc_exception_T) connect io.rocc.exception, _io_rocc_exception_T_1 invalidate io.trace.custom.rob_empty invalidate io.trace.time invalidate io.trace.insns[0].tval invalidate io.trace.insns[0].cause invalidate io.trace.insns[0].interrupt invalidate io.trace.insns[0].exception invalidate io.trace.insns[0].priv invalidate io.trace.insns[0].insn invalidate io.trace.insns[0].iaddr invalidate io.trace.insns[0].valid invalidate io.trace.insns[1].tval invalidate io.trace.insns[1].cause invalidate io.trace.insns[1].interrupt invalidate io.trace.insns[1].exception invalidate io.trace.insns[1].priv invalidate io.trace.insns[1].insn invalidate io.trace.insns[1].iaddr invalidate io.trace.insns[1].valid connect io.trace.time, csr.io.time connect io.trace.insns[0].valid, UInt<1>(0h0) connect io.trace.insns[1].valid, UInt<1>(0h0) connect io.trace.custom.rob_empty, rob.io.empty invalidate io.ifu.debug_ftq_idx[0] invalidate io.ifu.debug_ftq_idx[1]
module BoomCore( // @[core.scala:50:7] input clock, // @[core.scala:50:7] input reset, // @[core.scala:50:7] input io_hartid, // @[core.scala:54:14] input io_interrupts_debug, // @[core.scala:54:14] input io_interrupts_mtip, // @[core.scala:54:14] input io_interrupts_msip, // @[core.scala:54:14] input io_interrupts_meip, // @[core.scala:54:14] input io_interrupts_seip, // @[core.scala:54:14] output io_ifu_fetchpacket_ready, // @[core.scala:54:14] input io_ifu_fetchpacket_valid, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_valid, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_is_rvc, // @[core.scala:54:14] input [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_is_sfb, // @[core.scala:54:14] input [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_edge_inst, // @[core.scala:54:14] input [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_taken, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if, // @[core.scala:54:14] input [2:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_valid, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_1_bits_inst, // @[core.scala:54:14] input [31:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_inst, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_is_rvc, // @[core.scala:54:14] input [39:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_pc, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_is_sfb, // @[core.scala:54:14] input [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_edge_inst, // @[core.scala:54:14] input [5:0] io_ifu_fetchpacket_bits_uops_1_bits_pc_lob, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_taken, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if, // @[core.scala:54:14] input io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if, // @[core.scala:54:14] input [2:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc, // @[core.scala:54:14] output [4:0] io_ifu_arb_ftq_reqs_0, // @[core.scala:54:14] output [4:0] io_ifu_arb_ftq_reqs_1, // @[core.scala:54:14] output [4:0] io_ifu_arb_ftq_reqs_2, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_0_valid, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_0_entry_cfi_idx_valid, // @[core.scala:54:14] input [1:0] io_ifu_rrd_ftq_resps_0_entry_cfi_idx_bits, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_0_entry_cfi_taken, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_0_entry_cfi_mispredicted, // @[core.scala:54:14] input [2:0] io_ifu_rrd_ftq_resps_0_entry_cfi_type, // @[core.scala:54:14] input [3:0] io_ifu_rrd_ftq_resps_0_entry_br_mask, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_0_entry_cfi_is_call, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_0_entry_cfi_is_ret, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_0_entry_cfi_npc_plus4, // @[core.scala:54:14] input [39:0] io_ifu_rrd_ftq_resps_0_entry_ras_top, // @[core.scala:54:14] input [4:0] io_ifu_rrd_ftq_resps_0_entry_ras_idx, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_0_entry_start_bank, // @[core.scala:54:14] input [63:0] io_ifu_rrd_ftq_resps_0_ghist_old_history, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_taken, // @[core.scala:54:14] input [4:0] io_ifu_rrd_ftq_resps_0_ghist_ras_idx, // @[core.scala:54:14] input [39:0] io_ifu_rrd_ftq_resps_0_pc, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_1_valid, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_1_entry_cfi_idx_valid, // @[core.scala:54:14] input [1:0] io_ifu_rrd_ftq_resps_1_entry_cfi_idx_bits, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_1_entry_cfi_taken, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_1_entry_cfi_mispredicted, // @[core.scala:54:14] input [2:0] io_ifu_rrd_ftq_resps_1_entry_cfi_type, // @[core.scala:54:14] input [3:0] io_ifu_rrd_ftq_resps_1_entry_br_mask, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_1_entry_cfi_is_call, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_1_entry_cfi_is_ret, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_1_entry_cfi_npc_plus4, // @[core.scala:54:14] input [39:0] io_ifu_rrd_ftq_resps_1_entry_ras_top, // @[core.scala:54:14] input [4:0] io_ifu_rrd_ftq_resps_1_entry_ras_idx, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_1_entry_start_bank, // @[core.scala:54:14] input [39:0] io_ifu_rrd_ftq_resps_1_pc, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_2_valid, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_2_entry_cfi_idx_valid, // @[core.scala:54:14] input [1:0] io_ifu_rrd_ftq_resps_2_entry_cfi_idx_bits, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_2_entry_cfi_taken, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_2_entry_cfi_mispredicted, // @[core.scala:54:14] input [2:0] io_ifu_rrd_ftq_resps_2_entry_cfi_type, // @[core.scala:54:14] input [3:0] io_ifu_rrd_ftq_resps_2_entry_br_mask, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_2_entry_cfi_is_call, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_2_entry_cfi_is_ret, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_2_entry_cfi_npc_plus4, // @[core.scala:54:14] input [39:0] io_ifu_rrd_ftq_resps_2_entry_ras_top, // @[core.scala:54:14] input [4:0] io_ifu_rrd_ftq_resps_2_entry_ras_idx, // @[core.scala:54:14] input io_ifu_rrd_ftq_resps_2_entry_start_bank, // @[core.scala:54:14] input [39:0] io_ifu_rrd_ftq_resps_2_pc, // @[core.scala:54:14] input [39:0] io_ifu_com_pc, // @[core.scala:54:14] input [39:0] io_ifu_debug_fetch_pc_0, // @[core.scala:54:14] input [39:0] io_ifu_debug_fetch_pc_1, // @[core.scala:54:14] output io_ifu_status_debug, // @[core.scala:54:14] output io_ifu_status_cease, // @[core.scala:54:14] output io_ifu_status_wfi, // @[core.scala:54:14] output [1:0] io_ifu_status_dprv, // @[core.scala:54:14] output io_ifu_status_dv, // @[core.scala:54:14] output [1:0] io_ifu_status_prv, // @[core.scala:54:14] output io_ifu_status_v, // @[core.scala:54:14] output io_ifu_status_sd, // @[core.scala:54:14] output io_ifu_status_mpv, // @[core.scala:54:14] output io_ifu_status_gva, // @[core.scala:54:14] output io_ifu_status_tsr, // @[core.scala:54:14] output io_ifu_status_tw, // @[core.scala:54:14] output io_ifu_status_tvm, // @[core.scala:54:14] output io_ifu_status_mxr, // @[core.scala:54:14] output io_ifu_status_sum, // @[core.scala:54:14] output io_ifu_status_mprv, // @[core.scala:54:14] output [1:0] io_ifu_status_fs, // @[core.scala:54:14] output [1:0] io_ifu_status_mpp, // @[core.scala:54:14] output io_ifu_status_spp, // @[core.scala:54:14] output io_ifu_status_mpie, // @[core.scala:54:14] output io_ifu_status_spie, // @[core.scala:54:14] output io_ifu_status_mie, // @[core.scala:54:14] output io_ifu_status_sie, // @[core.scala:54:14] output io_ifu_sfence_valid, // @[core.scala:54:14] output io_ifu_sfence_bits_rs1, // @[core.scala:54:14] output io_ifu_sfence_bits_rs2, // @[core.scala:54:14] output [38:0] io_ifu_sfence_bits_addr, // @[core.scala:54:14] output io_ifu_sfence_bits_asid, // @[core.scala:54:14] output io_ifu_sfence_bits_hv, // @[core.scala:54:14] output io_ifu_sfence_bits_hg, // @[core.scala:54:14] output [11:0] io_ifu_brupdate_b1_resolve_mask, // @[core.scala:54:14] output [11:0] io_ifu_brupdate_b1_mispredict_mask, // @[core.scala:54:14] output [31:0] io_ifu_brupdate_b2_uop_inst, // @[core.scala:54:14] output [31:0] io_ifu_brupdate_b2_uop_debug_inst, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_ifu_brupdate_b2_uop_debug_pc, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iq_type_0, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iq_type_1, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iq_type_2, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iq_type_3, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fu_code_0, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fu_code_1, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fu_code_2, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fu_code_3, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fu_code_4, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fu_code_5, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fu_code_6, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fu_code_7, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fu_code_8, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fu_code_9, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iw_issued, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iw_issued_partial_agen, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iw_issued_partial_dgen, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_iw_p1_speculative_child, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_iw_p2_speculative_child, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iw_p1_bypass_hint, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iw_p2_bypass_hint, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_iw_p3_bypass_hint, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_dis_col_sel, // @[core.scala:54:14] output [11:0] io_ifu_brupdate_b2_uop_br_mask, // @[core.scala:54:14] output [3:0] io_ifu_brupdate_b2_uop_br_tag, // @[core.scala:54:14] output [3:0] io_ifu_brupdate_b2_uop_br_type, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_sfb, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_fence, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_fencei, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_sfence, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_amo, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_eret, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_rocc, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_mov, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_ftq_idx, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_pc_lob, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_taken, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_imm_rename, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_imm_sel, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_pimm, // @[core.scala:54:14] output [19:0] io_ifu_brupdate_b2_uop_imm_packed, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_op1_sel, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_op2_sel, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_ldst, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_wen, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_ren1, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_ren2, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_ren3, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_swap12, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_swap23, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_fromint, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_toint, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_fastpipe, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_fma, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_div, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_sqrt, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_wflags, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_ctrl_vec, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_rob_idx, // @[core.scala:54:14] output [3:0] io_ifu_brupdate_b2_uop_ldq_idx, // @[core.scala:54:14] output [3:0] io_ifu_brupdate_b2_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_pdst, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_prs1, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_prs2, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_prs3, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_ppred, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_prs1_busy, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_prs2_busy, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_prs3_busy, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_ifu_brupdate_b2_uop_stale_pdst, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_exception, // @[core.scala:54:14] output [63:0] io_ifu_brupdate_b2_uop_exc_cause, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_mem_size, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_mem_signed, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_uses_ldq, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_uses_stq, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_is_unique, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_flush_on_commit, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_csr_cmd, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_ldst, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_lrs1, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_lrs2, // @[core.scala:54:14] output [5:0] io_ifu_brupdate_b2_uop_lrs3, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_frs3_en, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fcn_dw, // @[core.scala:54:14] output [4:0] io_ifu_brupdate_b2_uop_fcn_op, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_fp_val, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_fp_rm, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_uop_fp_typ, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_xcpt_pf_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_xcpt_ae_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_xcpt_ma_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_bp_debug_if, // @[core.scala:54:14] output io_ifu_brupdate_b2_uop_bp_xcpt_if, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_debug_fsrc, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_uop_debug_tsrc, // @[core.scala:54:14] output io_ifu_brupdate_b2_mispredict, // @[core.scala:54:14] output io_ifu_brupdate_b2_taken, // @[core.scala:54:14] output [2:0] io_ifu_brupdate_b2_cfi_type, // @[core.scala:54:14] output [1:0] io_ifu_brupdate_b2_pc_sel, // @[core.scala:54:14] output [39:0] io_ifu_brupdate_b2_jalr_target, // @[core.scala:54:14] output [20:0] io_ifu_brupdate_b2_target_offset, // @[core.scala:54:14] output io_ifu_redirect_flush, // @[core.scala:54:14] output io_ifu_redirect_val, // @[core.scala:54:14] output [39:0] io_ifu_redirect_pc, // @[core.scala:54:14] output [4:0] io_ifu_redirect_ftq_idx, // @[core.scala:54:14] output [63:0] io_ifu_redirect_ghist_old_history, // @[core.scala:54:14] output io_ifu_redirect_ghist_current_saw_branch_not_taken, // @[core.scala:54:14] output io_ifu_redirect_ghist_new_saw_branch_not_taken, // @[core.scala:54:14] output io_ifu_redirect_ghist_new_saw_branch_taken, // @[core.scala:54:14] output [4:0] io_ifu_redirect_ghist_ras_idx, // @[core.scala:54:14] output io_ifu_commit_valid, // @[core.scala:54:14] output [31:0] io_ifu_commit_bits, // @[core.scala:54:14] output io_ifu_flush_icache, // @[core.scala:54:14] output io_ifu_enable_bpd, // @[core.scala:54:14] input io_ifu_perf_acquire, // @[core.scala:54:14] input io_ifu_perf_tlbMiss, // @[core.scala:54:14] output [3:0] io_ptw_ptbr_mode, // @[core.scala:54:14] output [43:0] io_ptw_ptbr_ppn, // @[core.scala:54:14] output io_ptw_sfence_valid, // @[core.scala:54:14] output io_ptw_sfence_bits_rs1, // @[core.scala:54:14] output io_ptw_sfence_bits_rs2, // @[core.scala:54:14] output [38:0] io_ptw_sfence_bits_addr, // @[core.scala:54:14] output io_ptw_sfence_bits_asid, // @[core.scala:54:14] output io_ptw_sfence_bits_hv, // @[core.scala:54:14] output io_ptw_sfence_bits_hg, // @[core.scala:54:14] output io_ptw_status_debug, // @[core.scala:54:14] output io_ptw_status_cease, // @[core.scala:54:14] output io_ptw_status_wfi, // @[core.scala:54:14] output [1:0] io_ptw_status_dprv, // @[core.scala:54:14] output io_ptw_status_dv, // @[core.scala:54:14] output [1:0] io_ptw_status_prv, // @[core.scala:54:14] output io_ptw_status_v, // @[core.scala:54:14] output io_ptw_status_sd, // @[core.scala:54:14] output io_ptw_status_mpv, // @[core.scala:54:14] output io_ptw_status_gva, // @[core.scala:54:14] output io_ptw_status_tsr, // @[core.scala:54:14] output io_ptw_status_tw, // @[core.scala:54:14] output io_ptw_status_tvm, // @[core.scala:54:14] output io_ptw_status_mxr, // @[core.scala:54:14] output io_ptw_status_sum, // @[core.scala:54:14] output io_ptw_status_mprv, // @[core.scala:54:14] output [1:0] io_ptw_status_fs, // @[core.scala:54:14] output [1:0] io_ptw_status_mpp, // @[core.scala:54:14] output io_ptw_status_spp, // @[core.scala:54:14] output io_ptw_status_mpie, // @[core.scala:54:14] output io_ptw_status_spie, // @[core.scala:54:14] output io_ptw_status_mie, // @[core.scala:54:14] output io_ptw_status_sie, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_0_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_0_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_0_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_0_mask, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_1_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_1_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_1_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_1_mask, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_2_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_2_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_2_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_2_mask, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_3_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_3_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_3_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_3_mask, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_4_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_4_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_4_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_4_mask, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_5_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_5_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_5_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_5_mask, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_6_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_6_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_6_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_6_mask, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_l, // @[core.scala:54:14] output [1:0] io_ptw_pmp_7_cfg_a, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_x, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_w, // @[core.scala:54:14] output io_ptw_pmp_7_cfg_r, // @[core.scala:54:14] output [29:0] io_ptw_pmp_7_addr, // @[core.scala:54:14] output [31:0] io_ptw_pmp_7_mask, // @[core.scala:54:14] input io_ptw_perf_l2miss, // @[core.scala:54:14] input io_ptw_perf_l2hit, // @[core.scala:54:14] input io_ptw_perf_pte_miss, // @[core.scala:54:14] input io_ptw_clock_enabled, // @[core.scala:54:14] output io_lsu_agen_0_valid, // @[core.scala:54:14] output [31:0] io_lsu_agen_0_bits_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_agen_0_bits_uop_debug_inst, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_agen_0_bits_uop_debug_pc, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_iq_type_0, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_iq_type_1, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_iq_type_2, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_iq_type_3, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fu_code_0, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fu_code_1, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fu_code_2, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fu_code_3, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fu_code_4, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fu_code_5, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fu_code_6, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fu_code_7, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fu_code_8, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fu_code_9, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_iw_issued, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_iw_issued_partial_agen, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_iw_issued_partial_dgen, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_iw_p1_speculative_child, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_iw_p2_speculative_child, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_iw_p1_bypass_hint, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_iw_p2_bypass_hint, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_iw_p3_bypass_hint, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_dis_col_sel, // @[core.scala:54:14] output [11:0] io_lsu_agen_0_bits_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_agen_0_bits_uop_br_tag, // @[core.scala:54:14] output [3:0] io_lsu_agen_0_bits_uop_br_type, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_is_sfb, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_is_fence, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_is_fencei, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_is_sfence, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_is_amo, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_is_eret, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_is_rocc, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_is_mov, // @[core.scala:54:14] output [4:0] io_lsu_agen_0_bits_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_agen_0_bits_uop_pc_lob, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_taken, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_imm_rename, // @[core.scala:54:14] output [2:0] io_lsu_agen_0_bits_uop_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_agen_0_bits_uop_pimm, // @[core.scala:54:14] output [19:0] io_lsu_agen_0_bits_uop_imm_packed, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_agen_0_bits_uop_op2_sel, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_ldst, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_wen, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_ren1, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_ren2, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_ren3, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_swap12, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_swap23, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_fromint, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_toint, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_fma, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_div, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_sqrt, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_wflags, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_ctrl_vec, // @[core.scala:54:14] output [5:0] io_lsu_agen_0_bits_uop_rob_idx, // @[core.scala:54:14] output [3:0] io_lsu_agen_0_bits_uop_ldq_idx, // @[core.scala:54:14] output [3:0] io_lsu_agen_0_bits_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_agen_0_bits_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_agen_0_bits_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_agen_0_bits_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_agen_0_bits_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_agen_0_bits_uop_ppred, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_agen_0_bits_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_agen_0_bits_uop_exc_cause, // @[core.scala:54:14] output [4:0] io_lsu_agen_0_bits_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_mem_size, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_mem_signed, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_uses_stq, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_is_unique, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_flush_on_commit, // @[core.scala:54:14] output [2:0] io_lsu_agen_0_bits_uop_csr_cmd, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_agen_0_bits_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_agen_0_bits_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_agen_0_bits_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_agen_0_bits_uop_lrs3, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_frs3_en, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fcn_dw, // @[core.scala:54:14] output [4:0] io_lsu_agen_0_bits_uop_fcn_op, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_fp_val, // @[core.scala:54:14] output [2:0] io_lsu_agen_0_bits_uop_fp_rm, // @[core.scala:54:14] output [1:0] io_lsu_agen_0_bits_uop_fp_typ, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_agen_0_bits_uop_bp_xcpt_if, // @[core.scala:54:14] output [2:0] io_lsu_agen_0_bits_uop_debug_fsrc, // @[core.scala:54:14] output [2:0] io_lsu_agen_0_bits_uop_debug_tsrc, // @[core.scala:54:14] output [63:0] io_lsu_agen_0_bits_data, // @[core.scala:54:14] output io_lsu_dgen_0_valid, // @[core.scala:54:14] output [31:0] io_lsu_dgen_0_bits_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_dgen_0_bits_uop_debug_inst, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_dgen_0_bits_uop_debug_pc, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_iq_type_0, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_iq_type_1, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_iq_type_2, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_iq_type_3, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fu_code_0, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fu_code_1, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fu_code_2, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fu_code_3, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fu_code_4, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fu_code_5, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fu_code_6, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fu_code_7, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fu_code_8, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fu_code_9, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_iw_issued, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_iw_issued_partial_agen, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_iw_p1_speculative_child, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_iw_p2_speculative_child, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_dis_col_sel, // @[core.scala:54:14] output [11:0] io_lsu_dgen_0_bits_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_dgen_0_bits_uop_br_tag, // @[core.scala:54:14] output [3:0] io_lsu_dgen_0_bits_uop_br_type, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_is_sfb, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_is_fence, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_is_fencei, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_is_sfence, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_is_amo, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_is_eret, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_is_rocc, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_is_mov, // @[core.scala:54:14] output [4:0] io_lsu_dgen_0_bits_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_dgen_0_bits_uop_pc_lob, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_taken, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_imm_rename, // @[core.scala:54:14] output [2:0] io_lsu_dgen_0_bits_uop_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_dgen_0_bits_uop_pimm, // @[core.scala:54:14] output [19:0] io_lsu_dgen_0_bits_uop_imm_packed, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_dgen_0_bits_uop_op2_sel, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_ldst, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_wen, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_ren1, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_ren2, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_ren3, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_swap12, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_swap23, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_fromint, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_toint, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_fma, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_div, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_wflags, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_ctrl_vec, // @[core.scala:54:14] output [5:0] io_lsu_dgen_0_bits_uop_rob_idx, // @[core.scala:54:14] output [3:0] io_lsu_dgen_0_bits_uop_ldq_idx, // @[core.scala:54:14] output [3:0] io_lsu_dgen_0_bits_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_dgen_0_bits_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_dgen_0_bits_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_dgen_0_bits_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_dgen_0_bits_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_dgen_0_bits_uop_ppred, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_dgen_0_bits_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_dgen_0_bits_uop_exc_cause, // @[core.scala:54:14] output [4:0] io_lsu_dgen_0_bits_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_mem_size, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_mem_signed, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_uses_stq, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_is_unique, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_flush_on_commit, // @[core.scala:54:14] output [2:0] io_lsu_dgen_0_bits_uop_csr_cmd, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_dgen_0_bits_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_dgen_0_bits_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_dgen_0_bits_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_dgen_0_bits_uop_lrs3, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_frs3_en, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fcn_dw, // @[core.scala:54:14] output [4:0] io_lsu_dgen_0_bits_uop_fcn_op, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_fp_val, // @[core.scala:54:14] output [2:0] io_lsu_dgen_0_bits_uop_fp_rm, // @[core.scala:54:14] output [1:0] io_lsu_dgen_0_bits_uop_fp_typ, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_dgen_0_bits_uop_bp_xcpt_if, // @[core.scala:54:14] output [2:0] io_lsu_dgen_0_bits_uop_debug_fsrc, // @[core.scala:54:14] output [2:0] io_lsu_dgen_0_bits_uop_debug_tsrc, // @[core.scala:54:14] output [63:0] io_lsu_dgen_0_bits_data, // @[core.scala:54:14] output io_lsu_dgen_1_valid, // @[core.scala:54:14] output [31:0] io_lsu_dgen_1_bits_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_dgen_1_bits_uop_debug_inst, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_dgen_1_bits_uop_debug_pc, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_iq_type_0, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_iq_type_1, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_iq_type_2, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_iq_type_3, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fu_code_0, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fu_code_1, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fu_code_2, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fu_code_3, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fu_code_4, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fu_code_5, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fu_code_6, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fu_code_7, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fu_code_8, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fu_code_9, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_iw_issued, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_iw_issued_partial_agen, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_iw_p1_speculative_child, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_iw_p2_speculative_child, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_dis_col_sel, // @[core.scala:54:14] output [11:0] io_lsu_dgen_1_bits_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_dgen_1_bits_uop_br_tag, // @[core.scala:54:14] output [3:0] io_lsu_dgen_1_bits_uop_br_type, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_is_sfb, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_is_fence, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_is_fencei, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_is_sfence, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_is_amo, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_is_eret, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_is_rocc, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_is_mov, // @[core.scala:54:14] output [4:0] io_lsu_dgen_1_bits_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_dgen_1_bits_uop_pc_lob, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_taken, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_imm_rename, // @[core.scala:54:14] output [2:0] io_lsu_dgen_1_bits_uop_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_dgen_1_bits_uop_pimm, // @[core.scala:54:14] output [19:0] io_lsu_dgen_1_bits_uop_imm_packed, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_dgen_1_bits_uop_op2_sel, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_ldst, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_wen, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_ren1, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_ren2, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_ren3, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_swap12, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_swap23, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_fromint, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_toint, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_fma, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_div, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_wflags, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_ctrl_vec, // @[core.scala:54:14] output [5:0] io_lsu_dgen_1_bits_uop_rob_idx, // @[core.scala:54:14] output [3:0] io_lsu_dgen_1_bits_uop_ldq_idx, // @[core.scala:54:14] output [3:0] io_lsu_dgen_1_bits_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_dgen_1_bits_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_dgen_1_bits_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_dgen_1_bits_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_dgen_1_bits_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_dgen_1_bits_uop_ppred, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_dgen_1_bits_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_dgen_1_bits_uop_exc_cause, // @[core.scala:54:14] output [4:0] io_lsu_dgen_1_bits_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_mem_size, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_mem_signed, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_uses_stq, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_is_unique, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_flush_on_commit, // @[core.scala:54:14] output [2:0] io_lsu_dgen_1_bits_uop_csr_cmd, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_dgen_1_bits_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_dgen_1_bits_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_dgen_1_bits_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_dgen_1_bits_uop_lrs3, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_frs3_en, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fcn_dw, // @[core.scala:54:14] output [4:0] io_lsu_dgen_1_bits_uop_fcn_op, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_fp_val, // @[core.scala:54:14] output [2:0] io_lsu_dgen_1_bits_uop_fp_rm, // @[core.scala:54:14] output [1:0] io_lsu_dgen_1_bits_uop_fp_typ, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_dgen_1_bits_uop_bp_xcpt_if, // @[core.scala:54:14] output [2:0] io_lsu_dgen_1_bits_uop_debug_fsrc, // @[core.scala:54:14] output [2:0] io_lsu_dgen_1_bits_uop_debug_tsrc, // @[core.scala:54:14] output [63:0] io_lsu_dgen_1_bits_data, // @[core.scala:54:14] output io_lsu_dgen_2_valid, // @[core.scala:54:14] output [31:0] io_lsu_dgen_2_bits_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_dgen_2_bits_uop_debug_inst, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_dgen_2_bits_uop_debug_pc, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_iq_type_0, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_iq_type_1, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_iq_type_2, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_iq_type_3, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fu_code_0, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fu_code_1, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fu_code_2, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fu_code_3, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fu_code_4, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fu_code_5, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fu_code_6, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fu_code_7, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fu_code_8, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fu_code_9, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_iw_issued, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_iw_issued_partial_agen, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_iw_p1_speculative_child, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_iw_p2_speculative_child, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_dis_col_sel, // @[core.scala:54:14] output [11:0] io_lsu_dgen_2_bits_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_dgen_2_bits_uop_br_tag, // @[core.scala:54:14] output [3:0] io_lsu_dgen_2_bits_uop_br_type, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_is_sfb, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_is_fence, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_is_fencei, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_is_sfence, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_is_amo, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_is_eret, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_is_rocc, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_is_mov, // @[core.scala:54:14] output [4:0] io_lsu_dgen_2_bits_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_dgen_2_bits_uop_pc_lob, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_taken, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_imm_rename, // @[core.scala:54:14] output [2:0] io_lsu_dgen_2_bits_uop_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_dgen_2_bits_uop_pimm, // @[core.scala:54:14] output [19:0] io_lsu_dgen_2_bits_uop_imm_packed, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_dgen_2_bits_uop_op2_sel, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_ldst, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_wen, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_ren1, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_ren2, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_ren3, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_swap12, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_swap23, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_fromint, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_toint, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_fma, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_div, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_wflags, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_ctrl_vec, // @[core.scala:54:14] output [5:0] io_lsu_dgen_2_bits_uop_rob_idx, // @[core.scala:54:14] output [3:0] io_lsu_dgen_2_bits_uop_ldq_idx, // @[core.scala:54:14] output [3:0] io_lsu_dgen_2_bits_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_dgen_2_bits_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_dgen_2_bits_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_dgen_2_bits_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_dgen_2_bits_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_dgen_2_bits_uop_ppred, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_dgen_2_bits_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_dgen_2_bits_uop_exc_cause, // @[core.scala:54:14] output [4:0] io_lsu_dgen_2_bits_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_mem_size, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_mem_signed, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_uses_stq, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_is_unique, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_flush_on_commit, // @[core.scala:54:14] output [2:0] io_lsu_dgen_2_bits_uop_csr_cmd, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_dgen_2_bits_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_dgen_2_bits_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_dgen_2_bits_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_dgen_2_bits_uop_lrs3, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_frs3_en, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fcn_dw, // @[core.scala:54:14] output [4:0] io_lsu_dgen_2_bits_uop_fcn_op, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_fp_val, // @[core.scala:54:14] output [2:0] io_lsu_dgen_2_bits_uop_fp_rm, // @[core.scala:54:14] output [1:0] io_lsu_dgen_2_bits_uop_fp_typ, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_dgen_2_bits_uop_bp_xcpt_if, // @[core.scala:54:14] output [2:0] io_lsu_dgen_2_bits_uop_debug_fsrc, // @[core.scala:54:14] output [2:0] io_lsu_dgen_2_bits_uop_debug_tsrc, // @[core.scala:54:14] output [63:0] io_lsu_dgen_2_bits_data, // @[core.scala:54:14] input io_lsu_iwakeups_0_valid, // @[core.scala:54:14] input [31:0] io_lsu_iwakeups_0_bits_uop_inst, // @[core.scala:54:14] input [31:0] io_lsu_iwakeups_0_bits_uop_debug_inst, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_is_rvc, // @[core.scala:54:14] input [39:0] io_lsu_iwakeups_0_bits_uop_debug_pc, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_iq_type_0, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_iq_type_1, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_iq_type_2, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_iq_type_3, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fu_code_0, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fu_code_1, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fu_code_2, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fu_code_3, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fu_code_4, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fu_code_5, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fu_code_6, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fu_code_7, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fu_code_8, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fu_code_9, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_iw_issued, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_dis_col_sel, // @[core.scala:54:14] input [11:0] io_lsu_iwakeups_0_bits_uop_br_mask, // @[core.scala:54:14] input [3:0] io_lsu_iwakeups_0_bits_uop_br_tag, // @[core.scala:54:14] input [3:0] io_lsu_iwakeups_0_bits_uop_br_type, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_is_sfb, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_is_fence, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_is_fencei, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_is_sfence, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_is_amo, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_is_eret, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_is_rocc, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_is_mov, // @[core.scala:54:14] input [4:0] io_lsu_iwakeups_0_bits_uop_ftq_idx, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_edge_inst, // @[core.scala:54:14] input [5:0] io_lsu_iwakeups_0_bits_uop_pc_lob, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_taken, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_imm_rename, // @[core.scala:54:14] input [2:0] io_lsu_iwakeups_0_bits_uop_imm_sel, // @[core.scala:54:14] input [4:0] io_lsu_iwakeups_0_bits_uop_pimm, // @[core.scala:54:14] input [19:0] io_lsu_iwakeups_0_bits_uop_imm_packed, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_op1_sel, // @[core.scala:54:14] input [2:0] io_lsu_iwakeups_0_bits_uop_op2_sel, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_div, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec, // @[core.scala:54:14] input [5:0] io_lsu_iwakeups_0_bits_uop_rob_idx, // @[core.scala:54:14] input [3:0] io_lsu_iwakeups_0_bits_uop_ldq_idx, // @[core.scala:54:14] input [3:0] io_lsu_iwakeups_0_bits_uop_stq_idx, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_rxq_idx, // @[core.scala:54:14] input [6:0] io_lsu_iwakeups_0_bits_uop_pdst, // @[core.scala:54:14] input [6:0] io_lsu_iwakeups_0_bits_uop_prs1, // @[core.scala:54:14] input [6:0] io_lsu_iwakeups_0_bits_uop_prs2, // @[core.scala:54:14] input [6:0] io_lsu_iwakeups_0_bits_uop_prs3, // @[core.scala:54:14] input [4:0] io_lsu_iwakeups_0_bits_uop_ppred, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_prs1_busy, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_prs2_busy, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_prs3_busy, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_ppred_busy, // @[core.scala:54:14] input [6:0] io_lsu_iwakeups_0_bits_uop_stale_pdst, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_exception, // @[core.scala:54:14] input [63:0] io_lsu_iwakeups_0_bits_uop_exc_cause, // @[core.scala:54:14] input [4:0] io_lsu_iwakeups_0_bits_uop_mem_cmd, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_mem_size, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_mem_signed, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_uses_ldq, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_uses_stq, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_is_unique, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_flush_on_commit, // @[core.scala:54:14] input [2:0] io_lsu_iwakeups_0_bits_uop_csr_cmd, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_ldst_is_rs1, // @[core.scala:54:14] input [5:0] io_lsu_iwakeups_0_bits_uop_ldst, // @[core.scala:54:14] input [5:0] io_lsu_iwakeups_0_bits_uop_lrs1, // @[core.scala:54:14] input [5:0] io_lsu_iwakeups_0_bits_uop_lrs2, // @[core.scala:54:14] input [5:0] io_lsu_iwakeups_0_bits_uop_lrs3, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_dst_rtype, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_lrs1_rtype, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_lrs2_rtype, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_frs3_en, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fcn_dw, // @[core.scala:54:14] input [4:0] io_lsu_iwakeups_0_bits_uop_fcn_op, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_fp_val, // @[core.scala:54:14] input [2:0] io_lsu_iwakeups_0_bits_uop_fp_rm, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_uop_fp_typ, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_xcpt_pf_if, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_xcpt_ae_if, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_xcpt_ma_if, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_bp_debug_if, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_uop_bp_xcpt_if, // @[core.scala:54:14] input [2:0] io_lsu_iwakeups_0_bits_uop_debug_fsrc, // @[core.scala:54:14] input [2:0] io_lsu_iwakeups_0_bits_uop_debug_tsrc, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_bypassable, // @[core.scala:54:14] input [1:0] io_lsu_iwakeups_0_bits_speculative_mask, // @[core.scala:54:14] input io_lsu_iwakeups_0_bits_rebusy, // @[core.scala:54:14] input io_lsu_iresp_0_valid, // @[core.scala:54:14] input [31:0] io_lsu_iresp_0_bits_uop_inst, // @[core.scala:54:14] input [31:0] io_lsu_iresp_0_bits_uop_debug_inst, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_is_rvc, // @[core.scala:54:14] input [39:0] io_lsu_iresp_0_bits_uop_debug_pc, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_iq_type_0, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_iq_type_1, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_iq_type_2, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_iq_type_3, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fu_code_0, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fu_code_1, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fu_code_2, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fu_code_3, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fu_code_4, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fu_code_5, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fu_code_6, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fu_code_7, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fu_code_8, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fu_code_9, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_iw_issued, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_iw_issued_partial_agen, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_iw_p1_speculative_child, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_iw_p2_speculative_child, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_dis_col_sel, // @[core.scala:54:14] input [11:0] io_lsu_iresp_0_bits_uop_br_mask, // @[core.scala:54:14] input [3:0] io_lsu_iresp_0_bits_uop_br_tag, // @[core.scala:54:14] input [3:0] io_lsu_iresp_0_bits_uop_br_type, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_is_sfb, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_is_fence, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_is_fencei, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_is_sfence, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_is_amo, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_is_eret, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_is_rocc, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_is_mov, // @[core.scala:54:14] input [4:0] io_lsu_iresp_0_bits_uop_ftq_idx, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_edge_inst, // @[core.scala:54:14] input [5:0] io_lsu_iresp_0_bits_uop_pc_lob, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_taken, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_imm_rename, // @[core.scala:54:14] input [2:0] io_lsu_iresp_0_bits_uop_imm_sel, // @[core.scala:54:14] input [4:0] io_lsu_iresp_0_bits_uop_pimm, // @[core.scala:54:14] input [19:0] io_lsu_iresp_0_bits_uop_imm_packed, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_op1_sel, // @[core.scala:54:14] input [2:0] io_lsu_iresp_0_bits_uop_op2_sel, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ldst, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_wen, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ren1, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ren2, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_ren3, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_swap12, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_swap23, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_fromint, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_toint, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_fma, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_div, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_wflags, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_ctrl_vec, // @[core.scala:54:14] input [5:0] io_lsu_iresp_0_bits_uop_rob_idx, // @[core.scala:54:14] input [3:0] io_lsu_iresp_0_bits_uop_ldq_idx, // @[core.scala:54:14] input [3:0] io_lsu_iresp_0_bits_uop_stq_idx, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_rxq_idx, // @[core.scala:54:14] input [6:0] io_lsu_iresp_0_bits_uop_pdst, // @[core.scala:54:14] input [6:0] io_lsu_iresp_0_bits_uop_prs1, // @[core.scala:54:14] input [6:0] io_lsu_iresp_0_bits_uop_prs2, // @[core.scala:54:14] input [6:0] io_lsu_iresp_0_bits_uop_prs3, // @[core.scala:54:14] input [4:0] io_lsu_iresp_0_bits_uop_ppred, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_prs1_busy, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_prs2_busy, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_prs3_busy, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_ppred_busy, // @[core.scala:54:14] input [6:0] io_lsu_iresp_0_bits_uop_stale_pdst, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_exception, // @[core.scala:54:14] input [63:0] io_lsu_iresp_0_bits_uop_exc_cause, // @[core.scala:54:14] input [4:0] io_lsu_iresp_0_bits_uop_mem_cmd, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_mem_size, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_mem_signed, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_uses_ldq, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_uses_stq, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_is_unique, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_flush_on_commit, // @[core.scala:54:14] input [2:0] io_lsu_iresp_0_bits_uop_csr_cmd, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_ldst_is_rs1, // @[core.scala:54:14] input [5:0] io_lsu_iresp_0_bits_uop_ldst, // @[core.scala:54:14] input [5:0] io_lsu_iresp_0_bits_uop_lrs1, // @[core.scala:54:14] input [5:0] io_lsu_iresp_0_bits_uop_lrs2, // @[core.scala:54:14] input [5:0] io_lsu_iresp_0_bits_uop_lrs3, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_dst_rtype, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_lrs1_rtype, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_lrs2_rtype, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_frs3_en, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fcn_dw, // @[core.scala:54:14] input [4:0] io_lsu_iresp_0_bits_uop_fcn_op, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_fp_val, // @[core.scala:54:14] input [2:0] io_lsu_iresp_0_bits_uop_fp_rm, // @[core.scala:54:14] input [1:0] io_lsu_iresp_0_bits_uop_fp_typ, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_xcpt_pf_if, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_xcpt_ae_if, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_xcpt_ma_if, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_bp_debug_if, // @[core.scala:54:14] input io_lsu_iresp_0_bits_uop_bp_xcpt_if, // @[core.scala:54:14] input [2:0] io_lsu_iresp_0_bits_uop_debug_fsrc, // @[core.scala:54:14] input [2:0] io_lsu_iresp_0_bits_uop_debug_tsrc, // @[core.scala:54:14] input [63:0] io_lsu_iresp_0_bits_data, // @[core.scala:54:14] input io_lsu_fresp_0_valid, // @[core.scala:54:14] input [31:0] io_lsu_fresp_0_bits_uop_inst, // @[core.scala:54:14] input [31:0] io_lsu_fresp_0_bits_uop_debug_inst, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_is_rvc, // @[core.scala:54:14] input [39:0] io_lsu_fresp_0_bits_uop_debug_pc, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_iq_type_0, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_iq_type_1, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_iq_type_2, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_iq_type_3, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fu_code_0, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fu_code_1, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fu_code_2, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fu_code_3, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fu_code_4, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fu_code_5, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fu_code_6, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fu_code_7, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fu_code_8, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fu_code_9, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_iw_issued, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_iw_issued_partial_agen, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_iw_p1_speculative_child, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_iw_p2_speculative_child, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_dis_col_sel, // @[core.scala:54:14] input [11:0] io_lsu_fresp_0_bits_uop_br_mask, // @[core.scala:54:14] input [3:0] io_lsu_fresp_0_bits_uop_br_tag, // @[core.scala:54:14] input [3:0] io_lsu_fresp_0_bits_uop_br_type, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_is_sfb, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_is_fence, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_is_fencei, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_is_sfence, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_is_amo, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_is_eret, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_is_rocc, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_is_mov, // @[core.scala:54:14] input [4:0] io_lsu_fresp_0_bits_uop_ftq_idx, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_edge_inst, // @[core.scala:54:14] input [5:0] io_lsu_fresp_0_bits_uop_pc_lob, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_taken, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_imm_rename, // @[core.scala:54:14] input [2:0] io_lsu_fresp_0_bits_uop_imm_sel, // @[core.scala:54:14] input [4:0] io_lsu_fresp_0_bits_uop_pimm, // @[core.scala:54:14] input [19:0] io_lsu_fresp_0_bits_uop_imm_packed, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_op1_sel, // @[core.scala:54:14] input [2:0] io_lsu_fresp_0_bits_uop_op2_sel, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ldst, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_wen, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ren1, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ren2, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_ren3, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_swap12, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_swap23, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_fromint, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_toint, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_fma, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_div, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_wflags, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_ctrl_vec, // @[core.scala:54:14] input [5:0] io_lsu_fresp_0_bits_uop_rob_idx, // @[core.scala:54:14] input [3:0] io_lsu_fresp_0_bits_uop_ldq_idx, // @[core.scala:54:14] input [3:0] io_lsu_fresp_0_bits_uop_stq_idx, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_rxq_idx, // @[core.scala:54:14] input [6:0] io_lsu_fresp_0_bits_uop_pdst, // @[core.scala:54:14] input [6:0] io_lsu_fresp_0_bits_uop_prs1, // @[core.scala:54:14] input [6:0] io_lsu_fresp_0_bits_uop_prs2, // @[core.scala:54:14] input [6:0] io_lsu_fresp_0_bits_uop_prs3, // @[core.scala:54:14] input [4:0] io_lsu_fresp_0_bits_uop_ppred, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_prs1_busy, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_prs2_busy, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_prs3_busy, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_ppred_busy, // @[core.scala:54:14] input [6:0] io_lsu_fresp_0_bits_uop_stale_pdst, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_exception, // @[core.scala:54:14] input [63:0] io_lsu_fresp_0_bits_uop_exc_cause, // @[core.scala:54:14] input [4:0] io_lsu_fresp_0_bits_uop_mem_cmd, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_mem_size, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_mem_signed, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_uses_ldq, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_uses_stq, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_is_unique, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_flush_on_commit, // @[core.scala:54:14] input [2:0] io_lsu_fresp_0_bits_uop_csr_cmd, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_ldst_is_rs1, // @[core.scala:54:14] input [5:0] io_lsu_fresp_0_bits_uop_ldst, // @[core.scala:54:14] input [5:0] io_lsu_fresp_0_bits_uop_lrs1, // @[core.scala:54:14] input [5:0] io_lsu_fresp_0_bits_uop_lrs2, // @[core.scala:54:14] input [5:0] io_lsu_fresp_0_bits_uop_lrs3, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_dst_rtype, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_lrs1_rtype, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_lrs2_rtype, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_frs3_en, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fcn_dw, // @[core.scala:54:14] input [4:0] io_lsu_fresp_0_bits_uop_fcn_op, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_fp_val, // @[core.scala:54:14] input [2:0] io_lsu_fresp_0_bits_uop_fp_rm, // @[core.scala:54:14] input [1:0] io_lsu_fresp_0_bits_uop_fp_typ, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_xcpt_pf_if, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_xcpt_ae_if, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_xcpt_ma_if, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_bp_debug_if, // @[core.scala:54:14] input io_lsu_fresp_0_bits_uop_bp_xcpt_if, // @[core.scala:54:14] input [2:0] io_lsu_fresp_0_bits_uop_debug_fsrc, // @[core.scala:54:14] input [2:0] io_lsu_fresp_0_bits_uop_debug_tsrc, // @[core.scala:54:14] input [63:0] io_lsu_fresp_0_bits_data, // @[core.scala:54:14] output io_lsu_sfence_valid, // @[core.scala:54:14] output io_lsu_sfence_bits_rs1, // @[core.scala:54:14] output io_lsu_sfence_bits_rs2, // @[core.scala:54:14] output [38:0] io_lsu_sfence_bits_addr, // @[core.scala:54:14] output io_lsu_sfence_bits_asid, // @[core.scala:54:14] output io_lsu_sfence_bits_hv, // @[core.scala:54:14] output io_lsu_sfence_bits_hg, // @[core.scala:54:14] output io_lsu_dis_uops_0_valid, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_0_bits_inst, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_0_bits_debug_inst, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_dis_uops_0_bits_debug_pc, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iq_type_0, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iq_type_1, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iq_type_2, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iq_type_3, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fu_code_0, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fu_code_1, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fu_code_2, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fu_code_3, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fu_code_4, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fu_code_5, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fu_code_6, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fu_code_7, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fu_code_8, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fu_code_9, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iw_issued, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iw_issued_partial_agen, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iw_issued_partial_dgen, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_iw_p1_speculative_child, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_iw_p2_speculative_child, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iw_p1_bypass_hint, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iw_p2_bypass_hint, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_iw_p3_bypass_hint, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_dis_col_sel, // @[core.scala:54:14] output [11:0] io_lsu_dis_uops_0_bits_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_0_bits_br_tag, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_0_bits_br_type, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_sfb, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_fence, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_fencei, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_sfence, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_amo, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_eret, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_rocc, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_mov, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_ftq_idx, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_pc_lob, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_taken, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_imm_rename, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_pimm, // @[core.scala:54:14] output [19:0] io_lsu_dis_uops_0_bits_imm_packed, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_op2_sel, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_ldst, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_wen, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_ren1, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_ren2, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_ren3, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_swap12, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_swap23, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_fromint, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_toint, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_fma, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_div, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_sqrt, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_wflags, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_ctrl_vec, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_rob_idx, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_0_bits_ldq_idx, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_0_bits_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_pdst, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_prs1, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_prs2, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_prs3, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_ppred, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_prs1_busy, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_prs2_busy, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_prs3_busy, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_0_bits_stale_pdst, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_exception, // @[core.scala:54:14] output [63:0] io_lsu_dis_uops_0_bits_exc_cause, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_mem_size, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_mem_signed, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_uses_ldq, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_uses_stq, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_is_unique, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_flush_on_commit, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_csr_cmd, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_ldst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_0_bits_lrs3, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_frs3_en, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fcn_dw, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_0_bits_fcn_op, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_fp_val, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_fp_rm, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_0_bits_fp_typ, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_bp_debug_if, // @[core.scala:54:14] output io_lsu_dis_uops_0_bits_bp_xcpt_if, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_debug_fsrc, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_0_bits_debug_tsrc, // @[core.scala:54:14] output io_lsu_dis_uops_1_valid, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_1_bits_inst, // @[core.scala:54:14] output [31:0] io_lsu_dis_uops_1_bits_debug_inst, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_dis_uops_1_bits_debug_pc, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iq_type_0, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iq_type_1, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iq_type_2, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iq_type_3, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fu_code_0, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fu_code_1, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fu_code_2, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fu_code_3, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fu_code_4, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fu_code_5, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fu_code_6, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fu_code_7, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fu_code_8, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fu_code_9, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iw_issued, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iw_issued_partial_agen, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iw_issued_partial_dgen, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_iw_p1_speculative_child, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_iw_p2_speculative_child, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iw_p1_bypass_hint, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iw_p2_bypass_hint, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_iw_p3_bypass_hint, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_dis_col_sel, // @[core.scala:54:14] output [11:0] io_lsu_dis_uops_1_bits_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_1_bits_br_tag, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_1_bits_br_type, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_sfb, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_fence, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_fencei, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_sfence, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_amo, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_eret, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_rocc, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_mov, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_ftq_idx, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_pc_lob, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_taken, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_imm_rename, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_pimm, // @[core.scala:54:14] output [19:0] io_lsu_dis_uops_1_bits_imm_packed, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_op2_sel, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_ldst, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_wen, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_ren1, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_ren2, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_ren3, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_swap12, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_swap23, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_fp_ctrl_typeTagIn, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_fp_ctrl_typeTagOut, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_fromint, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_toint, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_fastpipe, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_fma, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_div, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_sqrt, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_wflags, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_ctrl_vec, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_rob_idx, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_1_bits_ldq_idx, // @[core.scala:54:14] output [3:0] io_lsu_dis_uops_1_bits_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_pdst, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_prs1, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_prs2, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_prs3, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_ppred, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_prs1_busy, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_prs2_busy, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_prs3_busy, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_dis_uops_1_bits_stale_pdst, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_exception, // @[core.scala:54:14] output [63:0] io_lsu_dis_uops_1_bits_exc_cause, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_mem_size, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_mem_signed, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_uses_ldq, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_uses_stq, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_is_unique, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_flush_on_commit, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_csr_cmd, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_ldst, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_dis_uops_1_bits_lrs3, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_lrs2_rtype, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_frs3_en, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fcn_dw, // @[core.scala:54:14] output [4:0] io_lsu_dis_uops_1_bits_fcn_op, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_fp_val, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_fp_rm, // @[core.scala:54:14] output [1:0] io_lsu_dis_uops_1_bits_fp_typ, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_bp_debug_if, // @[core.scala:54:14] output io_lsu_dis_uops_1_bits_bp_xcpt_if, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_debug_fsrc, // @[core.scala:54:14] output [2:0] io_lsu_dis_uops_1_bits_debug_tsrc, // @[core.scala:54:14] input [3:0] io_lsu_dis_ldq_idx_0, // @[core.scala:54:14] input [3:0] io_lsu_dis_ldq_idx_1, // @[core.scala:54:14] input [3:0] io_lsu_dis_stq_idx_0, // @[core.scala:54:14] input [3:0] io_lsu_dis_stq_idx_1, // @[core.scala:54:14] input io_lsu_ldq_full_0, // @[core.scala:54:14] input io_lsu_ldq_full_1, // @[core.scala:54:14] input io_lsu_stq_full_0, // @[core.scala:54:14] input io_lsu_stq_full_1, // @[core.scala:54:14] output io_lsu_commit_valids_0, // @[core.scala:54:14] output io_lsu_commit_valids_1, // @[core.scala:54:14] output io_lsu_commit_arch_valids_0, // @[core.scala:54:14] output io_lsu_commit_arch_valids_1, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_0_inst, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_0_debug_inst, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_commit_uops_0_debug_pc, // @[core.scala:54:14] output io_lsu_commit_uops_0_iq_type_0, // @[core.scala:54:14] output io_lsu_commit_uops_0_iq_type_1, // @[core.scala:54:14] output io_lsu_commit_uops_0_iq_type_2, // @[core.scala:54:14] output io_lsu_commit_uops_0_iq_type_3, // @[core.scala:54:14] output io_lsu_commit_uops_0_fu_code_0, // @[core.scala:54:14] output io_lsu_commit_uops_0_fu_code_1, // @[core.scala:54:14] output io_lsu_commit_uops_0_fu_code_2, // @[core.scala:54:14] output io_lsu_commit_uops_0_fu_code_3, // @[core.scala:54:14] output io_lsu_commit_uops_0_fu_code_4, // @[core.scala:54:14] output io_lsu_commit_uops_0_fu_code_5, // @[core.scala:54:14] output io_lsu_commit_uops_0_fu_code_6, // @[core.scala:54:14] output io_lsu_commit_uops_0_fu_code_7, // @[core.scala:54:14] output io_lsu_commit_uops_0_fu_code_8, // @[core.scala:54:14] output io_lsu_commit_uops_0_fu_code_9, // @[core.scala:54:14] output io_lsu_commit_uops_0_iw_issued, // @[core.scala:54:14] output io_lsu_commit_uops_0_iw_issued_partial_agen, // @[core.scala:54:14] output io_lsu_commit_uops_0_iw_issued_partial_dgen, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_iw_p1_speculative_child, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_iw_p2_speculative_child, // @[core.scala:54:14] output io_lsu_commit_uops_0_iw_p1_bypass_hint, // @[core.scala:54:14] output io_lsu_commit_uops_0_iw_p2_bypass_hint, // @[core.scala:54:14] output io_lsu_commit_uops_0_iw_p3_bypass_hint, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_dis_col_sel, // @[core.scala:54:14] output [11:0] io_lsu_commit_uops_0_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_0_br_tag, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_0_br_type, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_sfb, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_fence, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_fencei, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_sfence, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_amo, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_eret, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_rocc, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_mov, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_ftq_idx, // @[core.scala:54:14] output io_lsu_commit_uops_0_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_pc_lob, // @[core.scala:54:14] output io_lsu_commit_uops_0_taken, // @[core.scala:54:14] output io_lsu_commit_uops_0_imm_rename, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_pimm, // @[core.scala:54:14] output [19:0] io_lsu_commit_uops_0_imm_packed, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_op2_sel, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_ldst, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_wen, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_ren1, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_ren2, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_ren3, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_swap12, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_swap23, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagIn, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagOut, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_fromint, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_toint, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_fastpipe, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_fma, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_div, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_sqrt, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_wflags, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_ctrl_vec, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_rob_idx, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_0_ldq_idx, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_0_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_pdst, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_prs1, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_prs2, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_prs3, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_ppred, // @[core.scala:54:14] output io_lsu_commit_uops_0_prs1_busy, // @[core.scala:54:14] output io_lsu_commit_uops_0_prs2_busy, // @[core.scala:54:14] output io_lsu_commit_uops_0_prs3_busy, // @[core.scala:54:14] output io_lsu_commit_uops_0_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_0_stale_pdst, // @[core.scala:54:14] output io_lsu_commit_uops_0_exception, // @[core.scala:54:14] output [63:0] io_lsu_commit_uops_0_exc_cause, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_mem_size, // @[core.scala:54:14] output io_lsu_commit_uops_0_mem_signed, // @[core.scala:54:14] output io_lsu_commit_uops_0_uses_ldq, // @[core.scala:54:14] output io_lsu_commit_uops_0_uses_stq, // @[core.scala:54:14] output io_lsu_commit_uops_0_is_unique, // @[core.scala:54:14] output io_lsu_commit_uops_0_flush_on_commit, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_csr_cmd, // @[core.scala:54:14] output io_lsu_commit_uops_0_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_ldst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_0_lrs3, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_lrs2_rtype, // @[core.scala:54:14] output io_lsu_commit_uops_0_frs3_en, // @[core.scala:54:14] output io_lsu_commit_uops_0_fcn_dw, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_0_fcn_op, // @[core.scala:54:14] output io_lsu_commit_uops_0_fp_val, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_fp_rm, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_0_fp_typ, // @[core.scala:54:14] output io_lsu_commit_uops_0_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_bp_debug_if, // @[core.scala:54:14] output io_lsu_commit_uops_0_bp_xcpt_if, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_debug_fsrc, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_0_debug_tsrc, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_1_inst, // @[core.scala:54:14] output [31:0] io_lsu_commit_uops_1_debug_inst, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_commit_uops_1_debug_pc, // @[core.scala:54:14] output io_lsu_commit_uops_1_iq_type_0, // @[core.scala:54:14] output io_lsu_commit_uops_1_iq_type_1, // @[core.scala:54:14] output io_lsu_commit_uops_1_iq_type_2, // @[core.scala:54:14] output io_lsu_commit_uops_1_iq_type_3, // @[core.scala:54:14] output io_lsu_commit_uops_1_fu_code_0, // @[core.scala:54:14] output io_lsu_commit_uops_1_fu_code_1, // @[core.scala:54:14] output io_lsu_commit_uops_1_fu_code_2, // @[core.scala:54:14] output io_lsu_commit_uops_1_fu_code_3, // @[core.scala:54:14] output io_lsu_commit_uops_1_fu_code_4, // @[core.scala:54:14] output io_lsu_commit_uops_1_fu_code_5, // @[core.scala:54:14] output io_lsu_commit_uops_1_fu_code_6, // @[core.scala:54:14] output io_lsu_commit_uops_1_fu_code_7, // @[core.scala:54:14] output io_lsu_commit_uops_1_fu_code_8, // @[core.scala:54:14] output io_lsu_commit_uops_1_fu_code_9, // @[core.scala:54:14] output io_lsu_commit_uops_1_iw_issued, // @[core.scala:54:14] output io_lsu_commit_uops_1_iw_issued_partial_agen, // @[core.scala:54:14] output io_lsu_commit_uops_1_iw_issued_partial_dgen, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_iw_p1_speculative_child, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_iw_p2_speculative_child, // @[core.scala:54:14] output io_lsu_commit_uops_1_iw_p1_bypass_hint, // @[core.scala:54:14] output io_lsu_commit_uops_1_iw_p2_bypass_hint, // @[core.scala:54:14] output io_lsu_commit_uops_1_iw_p3_bypass_hint, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_dis_col_sel, // @[core.scala:54:14] output [11:0] io_lsu_commit_uops_1_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_1_br_tag, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_1_br_type, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_sfb, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_fence, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_fencei, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_sfence, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_amo, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_eret, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_rocc, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_mov, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_ftq_idx, // @[core.scala:54:14] output io_lsu_commit_uops_1_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_pc_lob, // @[core.scala:54:14] output io_lsu_commit_uops_1_taken, // @[core.scala:54:14] output io_lsu_commit_uops_1_imm_rename, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_pimm, // @[core.scala:54:14] output [19:0] io_lsu_commit_uops_1_imm_packed, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_op2_sel, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_ldst, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_wen, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_ren1, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_ren2, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_ren3, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_swap12, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_swap23, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_fp_ctrl_typeTagIn, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_fp_ctrl_typeTagOut, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_fromint, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_toint, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_fastpipe, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_fma, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_div, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_sqrt, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_wflags, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_ctrl_vec, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_rob_idx, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_1_ldq_idx, // @[core.scala:54:14] output [3:0] io_lsu_commit_uops_1_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_pdst, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_prs1, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_prs2, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_prs3, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_ppred, // @[core.scala:54:14] output io_lsu_commit_uops_1_prs1_busy, // @[core.scala:54:14] output io_lsu_commit_uops_1_prs2_busy, // @[core.scala:54:14] output io_lsu_commit_uops_1_prs3_busy, // @[core.scala:54:14] output io_lsu_commit_uops_1_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_commit_uops_1_stale_pdst, // @[core.scala:54:14] output io_lsu_commit_uops_1_exception, // @[core.scala:54:14] output [63:0] io_lsu_commit_uops_1_exc_cause, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_mem_size, // @[core.scala:54:14] output io_lsu_commit_uops_1_mem_signed, // @[core.scala:54:14] output io_lsu_commit_uops_1_uses_ldq, // @[core.scala:54:14] output io_lsu_commit_uops_1_uses_stq, // @[core.scala:54:14] output io_lsu_commit_uops_1_is_unique, // @[core.scala:54:14] output io_lsu_commit_uops_1_flush_on_commit, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_csr_cmd, // @[core.scala:54:14] output io_lsu_commit_uops_1_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_ldst, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_commit_uops_1_lrs3, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_lrs2_rtype, // @[core.scala:54:14] output io_lsu_commit_uops_1_frs3_en, // @[core.scala:54:14] output io_lsu_commit_uops_1_fcn_dw, // @[core.scala:54:14] output [4:0] io_lsu_commit_uops_1_fcn_op, // @[core.scala:54:14] output io_lsu_commit_uops_1_fp_val, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_fp_rm, // @[core.scala:54:14] output [1:0] io_lsu_commit_uops_1_fp_typ, // @[core.scala:54:14] output io_lsu_commit_uops_1_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_bp_debug_if, // @[core.scala:54:14] output io_lsu_commit_uops_1_bp_xcpt_if, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_debug_fsrc, // @[core.scala:54:14] output [2:0] io_lsu_commit_uops_1_debug_tsrc, // @[core.scala:54:14] output io_lsu_commit_fflags_valid, // @[core.scala:54:14] output [4:0] io_lsu_commit_fflags_bits, // @[core.scala:54:14] output [63:0] io_lsu_commit_debug_wdata_0, // @[core.scala:54:14] output [63:0] io_lsu_commit_debug_wdata_1, // @[core.scala:54:14] output io_lsu_commit_load_at_rob_head, // @[core.scala:54:14] input io_lsu_clr_bsy_0_valid, // @[core.scala:54:14] input [5:0] io_lsu_clr_bsy_0_bits, // @[core.scala:54:14] input io_lsu_clr_bsy_1_valid, // @[core.scala:54:14] input [5:0] io_lsu_clr_bsy_1_bits, // @[core.scala:54:14] input io_lsu_clr_unsafe_0_valid, // @[core.scala:54:14] input [5:0] io_lsu_clr_unsafe_0_bits, // @[core.scala:54:14] output io_lsu_fence_dmem, // @[core.scala:54:14] output [11:0] io_lsu_brupdate_b1_resolve_mask, // @[core.scala:54:14] output [11:0] io_lsu_brupdate_b1_mispredict_mask, // @[core.scala:54:14] output [31:0] io_lsu_brupdate_b2_uop_inst, // @[core.scala:54:14] output [31:0] io_lsu_brupdate_b2_uop_debug_inst, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_rvc, // @[core.scala:54:14] output [39:0] io_lsu_brupdate_b2_uop_debug_pc, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iq_type_0, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iq_type_1, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iq_type_2, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iq_type_3, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fu_code_0, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fu_code_1, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fu_code_2, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fu_code_3, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fu_code_4, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fu_code_5, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fu_code_6, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fu_code_7, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fu_code_8, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fu_code_9, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iw_issued, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iw_issued_partial_agen, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iw_issued_partial_dgen, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_iw_p1_speculative_child, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_iw_p2_speculative_child, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iw_p1_bypass_hint, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iw_p2_bypass_hint, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_iw_p3_bypass_hint, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_dis_col_sel, // @[core.scala:54:14] output [11:0] io_lsu_brupdate_b2_uop_br_mask, // @[core.scala:54:14] output [3:0] io_lsu_brupdate_b2_uop_br_tag, // @[core.scala:54:14] output [3:0] io_lsu_brupdate_b2_uop_br_type, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_sfb, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_fence, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_fencei, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_sfence, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_amo, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_eret, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_sys_pc2epc, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_rocc, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_mov, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_ftq_idx, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_edge_inst, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_pc_lob, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_taken, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_imm_rename, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_imm_sel, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_pimm, // @[core.scala:54:14] output [19:0] io_lsu_brupdate_b2_uop_imm_packed, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_op1_sel, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_op2_sel, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_ldst, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_wen, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_ren1, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_ren2, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_ren3, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_swap12, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_swap23, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_fromint, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_toint, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_fma, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_div, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_sqrt, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_wflags, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_ctrl_vec, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_rob_idx, // @[core.scala:54:14] output [3:0] io_lsu_brupdate_b2_uop_ldq_idx, // @[core.scala:54:14] output [3:0] io_lsu_brupdate_b2_uop_stq_idx, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_rxq_idx, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_pdst, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_prs1, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_prs2, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_prs3, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_ppred, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_prs1_busy, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_prs2_busy, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_prs3_busy, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ppred_busy, // @[core.scala:54:14] output [6:0] io_lsu_brupdate_b2_uop_stale_pdst, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_exception, // @[core.scala:54:14] output [63:0] io_lsu_brupdate_b2_uop_exc_cause, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_mem_cmd, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_mem_size, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_mem_signed, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_uses_ldq, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_uses_stq, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_is_unique, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_flush_on_commit, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_csr_cmd, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_ldst_is_rs1, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_ldst, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_lrs1, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_lrs2, // @[core.scala:54:14] output [5:0] io_lsu_brupdate_b2_uop_lrs3, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_dst_rtype, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_frs3_en, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fcn_dw, // @[core.scala:54:14] output [4:0] io_lsu_brupdate_b2_uop_fcn_op, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_fp_val, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_fp_rm, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_uop_fp_typ, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_xcpt_pf_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_xcpt_ae_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_xcpt_ma_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_bp_debug_if, // @[core.scala:54:14] output io_lsu_brupdate_b2_uop_bp_xcpt_if, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_debug_fsrc, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_uop_debug_tsrc, // @[core.scala:54:14] output io_lsu_brupdate_b2_mispredict, // @[core.scala:54:14] output io_lsu_brupdate_b2_taken, // @[core.scala:54:14] output [2:0] io_lsu_brupdate_b2_cfi_type, // @[core.scala:54:14] output [1:0] io_lsu_brupdate_b2_pc_sel, // @[core.scala:54:14] output [39:0] io_lsu_brupdate_b2_jalr_target, // @[core.scala:54:14] output [20:0] io_lsu_brupdate_b2_target_offset, // @[core.scala:54:14] output [5:0] io_lsu_rob_pnr_idx, // @[core.scala:54:14] output [5:0] io_lsu_rob_head_idx, // @[core.scala:54:14] output io_lsu_exception, // @[core.scala:54:14] input io_lsu_fencei_rdy, // @[core.scala:54:14] input io_lsu_lxcpt_valid, // @[core.scala:54:14] input [31:0] io_lsu_lxcpt_bits_uop_inst, // @[core.scala:54:14] input [31:0] io_lsu_lxcpt_bits_uop_debug_inst, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_rvc, // @[core.scala:54:14] input [39:0] io_lsu_lxcpt_bits_uop_debug_pc, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iq_type_0, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iq_type_1, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iq_type_2, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iq_type_3, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fu_code_0, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fu_code_1, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fu_code_2, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fu_code_3, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fu_code_4, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fu_code_5, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fu_code_6, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fu_code_7, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fu_code_8, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fu_code_9, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iw_issued, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iw_issued_partial_agen, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_iw_p1_speculative_child, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_iw_p2_speculative_child, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_dis_col_sel, // @[core.scala:54:14] input [11:0] io_lsu_lxcpt_bits_uop_br_mask, // @[core.scala:54:14] input [3:0] io_lsu_lxcpt_bits_uop_br_tag, // @[core.scala:54:14] input [3:0] io_lsu_lxcpt_bits_uop_br_type, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_sfb, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_fence, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_fencei, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_sfence, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_amo, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_eret, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_sys_pc2epc, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_rocc, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_mov, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_ftq_idx, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_edge_inst, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_pc_lob, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_taken, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_imm_rename, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_imm_sel, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_pimm, // @[core.scala:54:14] input [19:0] io_lsu_lxcpt_bits_uop_imm_packed, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_op1_sel, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_op2_sel, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ldst, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_wen, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ren1, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ren2, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_ren3, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_swap12, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_swap23, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_fromint, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_toint, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_fma, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_div, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_wflags, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_ctrl_vec, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_rob_idx, // @[core.scala:54:14] input [3:0] io_lsu_lxcpt_bits_uop_ldq_idx, // @[core.scala:54:14] input [3:0] io_lsu_lxcpt_bits_uop_stq_idx, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_rxq_idx, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_pdst, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_prs1, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_prs2, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_prs3, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_ppred, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_prs1_busy, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_prs2_busy, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_prs3_busy, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ppred_busy, // @[core.scala:54:14] input [6:0] io_lsu_lxcpt_bits_uop_stale_pdst, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_exception, // @[core.scala:54:14] input [63:0] io_lsu_lxcpt_bits_uop_exc_cause, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_mem_cmd, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_mem_size, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_mem_signed, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_uses_ldq, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_uses_stq, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_is_unique, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_flush_on_commit, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_csr_cmd, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_ldst_is_rs1, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_ldst, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs1, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs2, // @[core.scala:54:14] input [5:0] io_lsu_lxcpt_bits_uop_lrs3, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_dst_rtype, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_frs3_en, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fcn_dw, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_uop_fcn_op, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_fp_val, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_fp_rm, // @[core.scala:54:14] input [1:0] io_lsu_lxcpt_bits_uop_fp_typ, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_xcpt_pf_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_xcpt_ae_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_xcpt_ma_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_bp_debug_if, // @[core.scala:54:14] input io_lsu_lxcpt_bits_uop_bp_xcpt_if, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_debug_fsrc, // @[core.scala:54:14] input [2:0] io_lsu_lxcpt_bits_uop_debug_tsrc, // @[core.scala:54:14] input [4:0] io_lsu_lxcpt_bits_cause, // @[core.scala:54:14] input [39:0] io_lsu_lxcpt_bits_badvaddr, // @[core.scala:54:14] output [63:0] io_lsu_tsc_reg, // @[core.scala:54:14] output io_lsu_status_debug, // @[core.scala:54:14] output io_lsu_status_cease, // @[core.scala:54:14] output io_lsu_status_wfi, // @[core.scala:54:14] output [1:0] io_lsu_status_dprv, // @[core.scala:54:14] output io_lsu_status_dv, // @[core.scala:54:14] output [1:0] io_lsu_status_prv, // @[core.scala:54:14] output io_lsu_status_v, // @[core.scala:54:14] output io_lsu_status_sd, // @[core.scala:54:14] output io_lsu_status_mpv, // @[core.scala:54:14] output io_lsu_status_gva, // @[core.scala:54:14] output io_lsu_status_tsr, // @[core.scala:54:14] output io_lsu_status_tw, // @[core.scala:54:14] output io_lsu_status_tvm, // @[core.scala:54:14] output io_lsu_status_mxr, // @[core.scala:54:14] output io_lsu_status_sum, // @[core.scala:54:14] output io_lsu_status_mprv, // @[core.scala:54:14] output [1:0] io_lsu_status_fs, // @[core.scala:54:14] output [1:0] io_lsu_status_mpp, // @[core.scala:54:14] output io_lsu_status_spp, // @[core.scala:54:14] output io_lsu_status_mpie, // @[core.scala:54:14] output io_lsu_status_spie, // @[core.scala:54:14] output io_lsu_status_mie, // @[core.scala:54:14] output io_lsu_status_sie, // @[core.scala:54:14] input io_lsu_perf_acquire, // @[core.scala:54:14] input io_lsu_perf_release, // @[core.scala:54:14] input io_lsu_perf_tlbMiss, // @[core.scala:54:14] input io_ptw_tlb_req_ready, // @[core.scala:54:14] input io_ptw_tlb_resp_valid, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_ae_ptw, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_ae_final, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pf, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_gf, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_hr, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_hw, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_hx, // @[core.scala:54:14] input [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future, // @[core.scala:54:14] input [43:0] io_ptw_tlb_resp_bits_pte_ppn, // @[core.scala:54:14] input [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_d, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_a, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_g, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_u, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_x, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_w, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_r, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_pte_v, // @[core.scala:54:14] input [1:0] io_ptw_tlb_resp_bits_level, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_homogeneous, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_gpa_valid, // @[core.scala:54:14] input [38:0] io_ptw_tlb_resp_bits_gpa_bits, // @[core.scala:54:14] input io_ptw_tlb_resp_bits_gpa_is_pte, // @[core.scala:54:14] input [3:0] io_ptw_tlb_ptbr_mode, // @[core.scala:54:14] input [43:0] io_ptw_tlb_ptbr_ppn, // @[core.scala:54:14] input io_ptw_tlb_status_debug, // @[core.scala:54:14] input io_ptw_tlb_status_cease, // @[core.scala:54:14] input io_ptw_tlb_status_wfi, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_dprv, // @[core.scala:54:14] input io_ptw_tlb_status_dv, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_prv, // @[core.scala:54:14] input io_ptw_tlb_status_v, // @[core.scala:54:14] input io_ptw_tlb_status_sd, // @[core.scala:54:14] input io_ptw_tlb_status_mpv, // @[core.scala:54:14] input io_ptw_tlb_status_gva, // @[core.scala:54:14] input io_ptw_tlb_status_tsr, // @[core.scala:54:14] input io_ptw_tlb_status_tw, // @[core.scala:54:14] input io_ptw_tlb_status_tvm, // @[core.scala:54:14] input io_ptw_tlb_status_mxr, // @[core.scala:54:14] input io_ptw_tlb_status_sum, // @[core.scala:54:14] input io_ptw_tlb_status_mprv, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_fs, // @[core.scala:54:14] input [1:0] io_ptw_tlb_status_mpp, // @[core.scala:54:14] input io_ptw_tlb_status_spp, // @[core.scala:54:14] input io_ptw_tlb_status_mpie, // @[core.scala:54:14] input io_ptw_tlb_status_spie, // @[core.scala:54:14] input io_ptw_tlb_status_mie, // @[core.scala:54:14] input io_ptw_tlb_status_sie, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_0_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_0_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_0_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_0_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_1_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_1_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_1_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_1_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_2_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_2_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_2_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_2_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_3_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_3_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_3_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_3_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_4_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_4_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_4_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_4_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_5_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_5_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_5_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_5_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_6_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_6_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_6_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_6_mask, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_l, // @[core.scala:54:14] input [1:0] io_ptw_tlb_pmp_7_cfg_a, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_x, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_w, // @[core.scala:54:14] input io_ptw_tlb_pmp_7_cfg_r, // @[core.scala:54:14] input [29:0] io_ptw_tlb_pmp_7_addr, // @[core.scala:54:14] input [31:0] io_ptw_tlb_pmp_7_mask, // @[core.scala:54:14] output [63:0] io_trace_time, // @[core.scala:54:14] output io_trace_custom_rob_empty // @[core.scala:54:14] ); wire dis_valids_0; // @[core.scala:189:24] wire dec_valids_0; // @[core.scala:180:24] wire io_ifu_sfence_bits_hg_0; // @[core.scala:50:7] wire io_ifu_sfence_bits_hv_0; // @[core.scala:50:7] wire io_ifu_sfence_bits_asid_0; // @[core.scala:50:7] wire [38:0] io_ifu_sfence_bits_addr_0; // @[core.scala:50:7] wire io_ifu_sfence_bits_rs2_0; // @[core.scala:50:7] wire io_ifu_sfence_bits_rs1_0; // @[core.scala:50:7] wire io_ifu_sfence_valid_0; // @[core.scala:50:7] wire [4:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _ll_arb_io_in_1_ready; // @[core.scala:883:22] wire _ll_arb_io_in_2_ready; // @[core.scala:883:22] wire _ll_arb_io_in_3_ready; // @[core.scala:883:22] wire _ll_arb_io_out_valid; // @[core.scala:883:22] wire [31:0] _ll_arb_io_out_bits_uop_inst; // @[core.scala:883:22] wire [31:0] _ll_arb_io_out_bits_uop_debug_inst; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_is_rvc; // @[core.scala:883:22] wire [39:0] _ll_arb_io_out_bits_uop_debug_pc; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_iq_type_0; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_iq_type_1; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_iq_type_2; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_iq_type_3; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fu_code_0; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fu_code_1; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fu_code_2; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fu_code_3; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fu_code_4; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fu_code_5; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fu_code_6; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fu_code_7; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fu_code_8; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fu_code_9; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_iw_issued; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_iw_issued_partial_agen; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_iw_issued_partial_dgen; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_iw_p1_speculative_child; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_iw_p2_speculative_child; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_iw_p1_bypass_hint; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_iw_p2_bypass_hint; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_iw_p3_bypass_hint; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_dis_col_sel; // @[core.scala:883:22] wire [11:0] _ll_arb_io_out_bits_uop_br_mask; // @[core.scala:883:22] wire [3:0] _ll_arb_io_out_bits_uop_br_tag; // @[core.scala:883:22] wire [3:0] _ll_arb_io_out_bits_uop_br_type; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_is_sfb; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_is_fence; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_is_fencei; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_is_sfence; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_is_amo; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_is_eret; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_is_sys_pc2epc; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_is_rocc; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_is_mov; // @[core.scala:883:22] wire [4:0] _ll_arb_io_out_bits_uop_ftq_idx; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_edge_inst; // @[core.scala:883:22] wire [5:0] _ll_arb_io_out_bits_uop_pc_lob; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_taken; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_imm_rename; // @[core.scala:883:22] wire [2:0] _ll_arb_io_out_bits_uop_imm_sel; // @[core.scala:883:22] wire [4:0] _ll_arb_io_out_bits_uop_pimm; // @[core.scala:883:22] wire [19:0] _ll_arb_io_out_bits_uop_imm_packed; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_op1_sel; // @[core.scala:883:22] wire [2:0] _ll_arb_io_out_bits_uop_op2_sel; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_ldst; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_wen; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_ren1; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_ren2; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_ren3; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_swap12; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_swap23; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_fromint; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_toint; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_fastpipe; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_fma; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_div; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_sqrt; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_wflags; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_ctrl_vec; // @[core.scala:883:22] wire [5:0] _ll_arb_io_out_bits_uop_rob_idx; // @[core.scala:883:22] wire [3:0] _ll_arb_io_out_bits_uop_ldq_idx; // @[core.scala:883:22] wire [3:0] _ll_arb_io_out_bits_uop_stq_idx; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_rxq_idx; // @[core.scala:883:22] wire [6:0] _ll_arb_io_out_bits_uop_pdst; // @[core.scala:883:22] wire [6:0] _ll_arb_io_out_bits_uop_prs1; // @[core.scala:883:22] wire [6:0] _ll_arb_io_out_bits_uop_prs2; // @[core.scala:883:22] wire [6:0] _ll_arb_io_out_bits_uop_prs3; // @[core.scala:883:22] wire [4:0] _ll_arb_io_out_bits_uop_ppred; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_prs1_busy; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_prs2_busy; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_prs3_busy; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_ppred_busy; // @[core.scala:883:22] wire [6:0] _ll_arb_io_out_bits_uop_stale_pdst; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_exception; // @[core.scala:883:22] wire [63:0] _ll_arb_io_out_bits_uop_exc_cause; // @[core.scala:883:22] wire [4:0] _ll_arb_io_out_bits_uop_mem_cmd; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_mem_size; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_mem_signed; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_uses_ldq; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_uses_stq; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_is_unique; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_flush_on_commit; // @[core.scala:883:22] wire [2:0] _ll_arb_io_out_bits_uop_csr_cmd; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_ldst_is_rs1; // @[core.scala:883:22] wire [5:0] _ll_arb_io_out_bits_uop_ldst; // @[core.scala:883:22] wire [5:0] _ll_arb_io_out_bits_uop_lrs1; // @[core.scala:883:22] wire [5:0] _ll_arb_io_out_bits_uop_lrs2; // @[core.scala:883:22] wire [5:0] _ll_arb_io_out_bits_uop_lrs3; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_dst_rtype; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_lrs1_rtype; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_lrs2_rtype; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_frs3_en; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fcn_dw; // @[core.scala:883:22] wire [4:0] _ll_arb_io_out_bits_uop_fcn_op; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_fp_val; // @[core.scala:883:22] wire [2:0] _ll_arb_io_out_bits_uop_fp_rm; // @[core.scala:883:22] wire [1:0] _ll_arb_io_out_bits_uop_fp_typ; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_xcpt_pf_if; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_xcpt_ae_if; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_xcpt_ma_if; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_bp_debug_if; // @[core.scala:883:22] wire _ll_arb_io_out_bits_uop_bp_xcpt_if; // @[core.scala:883:22] wire [2:0] _ll_arb_io_out_bits_uop_debug_fsrc; // @[core.scala:883:22] wire [2:0] _ll_arb_io_out_bits_uop_debug_tsrc; // @[core.scala:883:22] wire [63:0] _ll_arb_io_out_bits_data; // @[core.scala:883:22] wire _ll_arb_io_out_bits_predicated; // @[core.scala:883:22] wire _ll_arb_io_out_bits_fflags_valid; // @[core.scala:883:22] wire [4:0] _ll_arb_io_out_bits_fflags_bits; // @[core.scala:883:22] wire _dis_uops_1_pdst_prng_io_out_0; // @[PRNG.scala:91:22] wire _dis_uops_1_pdst_prng_io_out_1; // @[PRNG.scala:91:22] wire _dis_uops_1_pdst_prng_io_out_2; // @[PRNG.scala:91:22] wire _dis_uops_1_pdst_prng_io_out_3; // @[PRNG.scala:91:22] wire _dis_uops_1_pdst_prng_io_out_4; // @[PRNG.scala:91:22] wire _dis_uops_1_pdst_prng_io_out_5; // @[PRNG.scala:91:22] wire _dis_uops_1_pdst_prng_io_out_6; // @[PRNG.scala:91:22] wire _dis_uops_0_pdst_prng_io_out_0; // @[PRNG.scala:91:22] wire _dis_uops_0_pdst_prng_io_out_1; // @[PRNG.scala:91:22] wire _dis_uops_0_pdst_prng_io_out_2; // @[PRNG.scala:91:22] wire _dis_uops_0_pdst_prng_io_out_3; // @[PRNG.scala:91:22] wire _dis_uops_0_pdst_prng_io_out_4; // @[PRNG.scala:91:22] wire _dis_uops_0_pdst_prng_io_out_5; // @[PRNG.scala:91:22] wire _dis_uops_0_pdst_prng_io_out_6; // @[PRNG.scala:91:22] wire _csr_io_decode_0_fp_illegal; // @[core.scala:294:19] wire _csr_io_decode_0_fp_csr; // @[core.scala:294:19] wire _csr_io_decode_0_read_illegal; // @[core.scala:294:19] wire _csr_io_decode_0_write_illegal; // @[core.scala:294:19] wire _csr_io_decode_0_write_flush; // @[core.scala:294:19] wire _csr_io_decode_0_system_illegal; // @[core.scala:294:19] wire _csr_io_decode_0_virtual_access_illegal; // @[core.scala:294:19] wire _csr_io_decode_0_virtual_system_illegal; // @[core.scala:294:19] wire _csr_io_decode_1_fp_illegal; // @[core.scala:294:19] wire _csr_io_decode_1_fp_csr; // @[core.scala:294:19] wire _csr_io_decode_1_read_illegal; // @[core.scala:294:19] wire _csr_io_decode_1_write_illegal; // @[core.scala:294:19] wire _csr_io_decode_1_write_flush; // @[core.scala:294:19] wire _csr_io_decode_1_system_illegal; // @[core.scala:294:19] wire _csr_io_decode_1_virtual_access_illegal; // @[core.scala:294:19] wire _csr_io_decode_1_virtual_system_illegal; // @[core.scala:294:19] wire _csr_io_csr_stall; // @[core.scala:294:19] wire _csr_io_singleStep; // @[core.scala:294:19] wire _csr_io_status_debug; // @[core.scala:294:19] wire _csr_io_status_cease; // @[core.scala:294:19] wire _csr_io_status_wfi; // @[core.scala:294:19] wire [1:0] _csr_io_status_dprv; // @[core.scala:294:19] wire _csr_io_status_dv; // @[core.scala:294:19] wire [1:0] _csr_io_status_prv; // @[core.scala:294:19] wire _csr_io_status_v; // @[core.scala:294:19] wire _csr_io_status_sd; // @[core.scala:294:19] wire _csr_io_status_mpv; // @[core.scala:294:19] wire _csr_io_status_gva; // @[core.scala:294:19] wire _csr_io_status_tsr; // @[core.scala:294:19] wire _csr_io_status_tw; // @[core.scala:294:19] wire _csr_io_status_tvm; // @[core.scala:294:19] wire _csr_io_status_mxr; // @[core.scala:294:19] wire _csr_io_status_sum; // @[core.scala:294:19] wire _csr_io_status_mprv; // @[core.scala:294:19] wire [1:0] _csr_io_status_fs; // @[core.scala:294:19] wire [1:0] _csr_io_status_mpp; // @[core.scala:294:19] wire _csr_io_status_spp; // @[core.scala:294:19] wire _csr_io_status_mpie; // @[core.scala:294:19] wire _csr_io_status_spie; // @[core.scala:294:19] wire _csr_io_status_mie; // @[core.scala:294:19] wire _csr_io_status_sie; // @[core.scala:294:19] wire [39:0] _csr_io_evec; // @[core.scala:294:19] wire [2:0] _csr_io_fcsr_rm; // @[core.scala:294:19] wire _csr_io_interrupt; // @[core.scala:294:19] wire [63:0] _csr_io_interrupt_cause; // @[core.scala:294:19] wire [63:0] _csr_io_counters_0_eventSel; // @[core.scala:294:19] wire [63:0] _csr_io_counters_1_eventSel; // @[core.scala:294:19] wire [63:0] _csr_io_counters_2_eventSel; // @[core.scala:294:19] wire [63:0] _csr_io_counters_3_eventSel; // @[core.scala:294:19] wire [63:0] _csr_io_counters_4_eventSel; // @[core.scala:294:19] wire [63:0] _csr_io_counters_5_eventSel; // @[core.scala:294:19] wire [5:0] _rob_io_rob_tail_idx; // @[core.scala:159:32] wire _rob_io_commit_valids_0; // @[core.scala:159:32] wire _rob_io_commit_valids_1; // @[core.scala:159:32] wire _rob_io_commit_arch_valids_0; // @[core.scala:159:32] wire _rob_io_commit_arch_valids_1; // @[core.scala:159:32] wire [31:0] _rob_io_commit_uops_0_inst; // @[core.scala:159:32] wire [31:0] _rob_io_commit_uops_0_debug_inst; // @[core.scala:159:32] wire _rob_io_commit_uops_0_is_rvc; // @[core.scala:159:32] wire [39:0] _rob_io_commit_uops_0_debug_pc; // @[core.scala:159:32] wire _rob_io_commit_uops_0_iq_type_0; // @[core.scala:159:32] wire _rob_io_commit_uops_0_iq_type_1; // @[core.scala:159:32] wire _rob_io_commit_uops_0_iq_type_2; // @[core.scala:159:32] wire _rob_io_commit_uops_0_iq_type_3; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fu_code_0; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fu_code_1; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fu_code_2; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fu_code_3; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fu_code_4; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fu_code_5; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fu_code_6; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fu_code_7; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fu_code_8; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fu_code_9; // @[core.scala:159:32] wire _rob_io_commit_uops_0_iw_issued; // @[core.scala:159:32] wire _rob_io_commit_uops_0_iw_issued_partial_agen; // @[core.scala:159:32] wire _rob_io_commit_uops_0_iw_issued_partial_dgen; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_iw_p1_speculative_child; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_iw_p2_speculative_child; // @[core.scala:159:32] wire _rob_io_commit_uops_0_iw_p1_bypass_hint; // @[core.scala:159:32] wire _rob_io_commit_uops_0_iw_p2_bypass_hint; // @[core.scala:159:32] wire _rob_io_commit_uops_0_iw_p3_bypass_hint; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_dis_col_sel; // @[core.scala:159:32] wire [11:0] _rob_io_commit_uops_0_br_mask; // @[core.scala:159:32] wire [3:0] _rob_io_commit_uops_0_br_tag; // @[core.scala:159:32] wire [3:0] _rob_io_commit_uops_0_br_type; // @[core.scala:159:32] wire _rob_io_commit_uops_0_is_sfb; // @[core.scala:159:32] wire _rob_io_commit_uops_0_is_fence; // @[core.scala:159:32] wire _rob_io_commit_uops_0_is_fencei; // @[core.scala:159:32] wire _rob_io_commit_uops_0_is_sfence; // @[core.scala:159:32] wire _rob_io_commit_uops_0_is_amo; // @[core.scala:159:32] wire _rob_io_commit_uops_0_is_eret; // @[core.scala:159:32] wire _rob_io_commit_uops_0_is_sys_pc2epc; // @[core.scala:159:32] wire _rob_io_commit_uops_0_is_rocc; // @[core.scala:159:32] wire _rob_io_commit_uops_0_is_mov; // @[core.scala:159:32] wire [4:0] _rob_io_commit_uops_0_ftq_idx; // @[core.scala:159:32] wire _rob_io_commit_uops_0_edge_inst; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_0_pc_lob; // @[core.scala:159:32] wire _rob_io_commit_uops_0_taken; // @[core.scala:159:32] wire _rob_io_commit_uops_0_imm_rename; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_0_imm_sel; // @[core.scala:159:32] wire [4:0] _rob_io_commit_uops_0_pimm; // @[core.scala:159:32] wire [19:0] _rob_io_commit_uops_0_imm_packed; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_op1_sel; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_0_op2_sel; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_ldst; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_wen; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_ren1; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_ren2; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_ren3; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_swap12; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_swap23; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_fp_ctrl_typeTagIn; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_fp_ctrl_typeTagOut; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_fromint; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_toint; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_fastpipe; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_fma; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_div; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_sqrt; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_wflags; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_ctrl_vec; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_0_rob_idx; // @[core.scala:159:32] wire [3:0] _rob_io_commit_uops_0_ldq_idx; // @[core.scala:159:32] wire [3:0] _rob_io_commit_uops_0_stq_idx; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_rxq_idx; // @[core.scala:159:32] wire [6:0] _rob_io_commit_uops_0_pdst; // @[core.scala:159:32] wire [6:0] _rob_io_commit_uops_0_prs1; // @[core.scala:159:32] wire [6:0] _rob_io_commit_uops_0_prs2; // @[core.scala:159:32] wire [6:0] _rob_io_commit_uops_0_prs3; // @[core.scala:159:32] wire [4:0] _rob_io_commit_uops_0_ppred; // @[core.scala:159:32] wire _rob_io_commit_uops_0_prs1_busy; // @[core.scala:159:32] wire _rob_io_commit_uops_0_prs2_busy; // @[core.scala:159:32] wire _rob_io_commit_uops_0_prs3_busy; // @[core.scala:159:32] wire _rob_io_commit_uops_0_ppred_busy; // @[core.scala:159:32] wire [6:0] _rob_io_commit_uops_0_stale_pdst; // @[core.scala:159:32] wire _rob_io_commit_uops_0_exception; // @[core.scala:159:32] wire [63:0] _rob_io_commit_uops_0_exc_cause; // @[core.scala:159:32] wire [4:0] _rob_io_commit_uops_0_mem_cmd; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_mem_size; // @[core.scala:159:32] wire _rob_io_commit_uops_0_mem_signed; // @[core.scala:159:32] wire _rob_io_commit_uops_0_uses_ldq; // @[core.scala:159:32] wire _rob_io_commit_uops_0_uses_stq; // @[core.scala:159:32] wire _rob_io_commit_uops_0_is_unique; // @[core.scala:159:32] wire _rob_io_commit_uops_0_flush_on_commit; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_0_csr_cmd; // @[core.scala:159:32] wire _rob_io_commit_uops_0_ldst_is_rs1; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_0_ldst; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_0_lrs1; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_0_lrs2; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_0_lrs3; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_dst_rtype; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_lrs1_rtype; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_lrs2_rtype; // @[core.scala:159:32] wire _rob_io_commit_uops_0_frs3_en; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fcn_dw; // @[core.scala:159:32] wire [4:0] _rob_io_commit_uops_0_fcn_op; // @[core.scala:159:32] wire _rob_io_commit_uops_0_fp_val; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_0_fp_rm; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_0_fp_typ; // @[core.scala:159:32] wire _rob_io_commit_uops_0_xcpt_pf_if; // @[core.scala:159:32] wire _rob_io_commit_uops_0_xcpt_ae_if; // @[core.scala:159:32] wire _rob_io_commit_uops_0_xcpt_ma_if; // @[core.scala:159:32] wire _rob_io_commit_uops_0_bp_debug_if; // @[core.scala:159:32] wire _rob_io_commit_uops_0_bp_xcpt_if; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_0_debug_fsrc; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_0_debug_tsrc; // @[core.scala:159:32] wire [31:0] _rob_io_commit_uops_1_inst; // @[core.scala:159:32] wire [31:0] _rob_io_commit_uops_1_debug_inst; // @[core.scala:159:32] wire _rob_io_commit_uops_1_is_rvc; // @[core.scala:159:32] wire [39:0] _rob_io_commit_uops_1_debug_pc; // @[core.scala:159:32] wire _rob_io_commit_uops_1_iq_type_0; // @[core.scala:159:32] wire _rob_io_commit_uops_1_iq_type_1; // @[core.scala:159:32] wire _rob_io_commit_uops_1_iq_type_2; // @[core.scala:159:32] wire _rob_io_commit_uops_1_iq_type_3; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fu_code_0; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fu_code_1; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fu_code_2; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fu_code_3; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fu_code_4; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fu_code_5; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fu_code_6; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fu_code_7; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fu_code_8; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fu_code_9; // @[core.scala:159:32] wire _rob_io_commit_uops_1_iw_issued; // @[core.scala:159:32] wire _rob_io_commit_uops_1_iw_issued_partial_agen; // @[core.scala:159:32] wire _rob_io_commit_uops_1_iw_issued_partial_dgen; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_iw_p1_speculative_child; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_iw_p2_speculative_child; // @[core.scala:159:32] wire _rob_io_commit_uops_1_iw_p1_bypass_hint; // @[core.scala:159:32] wire _rob_io_commit_uops_1_iw_p2_bypass_hint; // @[core.scala:159:32] wire _rob_io_commit_uops_1_iw_p3_bypass_hint; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_dis_col_sel; // @[core.scala:159:32] wire [11:0] _rob_io_commit_uops_1_br_mask; // @[core.scala:159:32] wire [3:0] _rob_io_commit_uops_1_br_tag; // @[core.scala:159:32] wire [3:0] _rob_io_commit_uops_1_br_type; // @[core.scala:159:32] wire _rob_io_commit_uops_1_is_sfb; // @[core.scala:159:32] wire _rob_io_commit_uops_1_is_fence; // @[core.scala:159:32] wire _rob_io_commit_uops_1_is_fencei; // @[core.scala:159:32] wire _rob_io_commit_uops_1_is_sfence; // @[core.scala:159:32] wire _rob_io_commit_uops_1_is_amo; // @[core.scala:159:32] wire _rob_io_commit_uops_1_is_eret; // @[core.scala:159:32] wire _rob_io_commit_uops_1_is_sys_pc2epc; // @[core.scala:159:32] wire _rob_io_commit_uops_1_is_rocc; // @[core.scala:159:32] wire _rob_io_commit_uops_1_is_mov; // @[core.scala:159:32] wire [4:0] _rob_io_commit_uops_1_ftq_idx; // @[core.scala:159:32] wire _rob_io_commit_uops_1_edge_inst; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_1_pc_lob; // @[core.scala:159:32] wire _rob_io_commit_uops_1_taken; // @[core.scala:159:32] wire _rob_io_commit_uops_1_imm_rename; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_1_imm_sel; // @[core.scala:159:32] wire [4:0] _rob_io_commit_uops_1_pimm; // @[core.scala:159:32] wire [19:0] _rob_io_commit_uops_1_imm_packed; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_op1_sel; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_1_op2_sel; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_ldst; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_wen; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_ren1; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_ren2; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_ren3; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_swap12; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_swap23; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_fp_ctrl_typeTagIn; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_fp_ctrl_typeTagOut; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_fromint; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_toint; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_fastpipe; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_fma; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_div; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_sqrt; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_wflags; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_ctrl_vec; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_1_rob_idx; // @[core.scala:159:32] wire [3:0] _rob_io_commit_uops_1_ldq_idx; // @[core.scala:159:32] wire [3:0] _rob_io_commit_uops_1_stq_idx; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_rxq_idx; // @[core.scala:159:32] wire [6:0] _rob_io_commit_uops_1_pdst; // @[core.scala:159:32] wire [6:0] _rob_io_commit_uops_1_prs1; // @[core.scala:159:32] wire [6:0] _rob_io_commit_uops_1_prs2; // @[core.scala:159:32] wire [6:0] _rob_io_commit_uops_1_prs3; // @[core.scala:159:32] wire [4:0] _rob_io_commit_uops_1_ppred; // @[core.scala:159:32] wire _rob_io_commit_uops_1_prs1_busy; // @[core.scala:159:32] wire _rob_io_commit_uops_1_prs2_busy; // @[core.scala:159:32] wire _rob_io_commit_uops_1_prs3_busy; // @[core.scala:159:32] wire _rob_io_commit_uops_1_ppred_busy; // @[core.scala:159:32] wire [6:0] _rob_io_commit_uops_1_stale_pdst; // @[core.scala:159:32] wire _rob_io_commit_uops_1_exception; // @[core.scala:159:32] wire [63:0] _rob_io_commit_uops_1_exc_cause; // @[core.scala:159:32] wire [4:0] _rob_io_commit_uops_1_mem_cmd; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_mem_size; // @[core.scala:159:32] wire _rob_io_commit_uops_1_mem_signed; // @[core.scala:159:32] wire _rob_io_commit_uops_1_uses_ldq; // @[core.scala:159:32] wire _rob_io_commit_uops_1_uses_stq; // @[core.scala:159:32] wire _rob_io_commit_uops_1_is_unique; // @[core.scala:159:32] wire _rob_io_commit_uops_1_flush_on_commit; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_1_csr_cmd; // @[core.scala:159:32] wire _rob_io_commit_uops_1_ldst_is_rs1; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_1_ldst; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_1_lrs1; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_1_lrs2; // @[core.scala:159:32] wire [5:0] _rob_io_commit_uops_1_lrs3; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_dst_rtype; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_lrs1_rtype; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_lrs2_rtype; // @[core.scala:159:32] wire _rob_io_commit_uops_1_frs3_en; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fcn_dw; // @[core.scala:159:32] wire [4:0] _rob_io_commit_uops_1_fcn_op; // @[core.scala:159:32] wire _rob_io_commit_uops_1_fp_val; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_1_fp_rm; // @[core.scala:159:32] wire [1:0] _rob_io_commit_uops_1_fp_typ; // @[core.scala:159:32] wire _rob_io_commit_uops_1_xcpt_pf_if; // @[core.scala:159:32] wire _rob_io_commit_uops_1_xcpt_ae_if; // @[core.scala:159:32] wire _rob_io_commit_uops_1_xcpt_ma_if; // @[core.scala:159:32] wire _rob_io_commit_uops_1_bp_debug_if; // @[core.scala:159:32] wire _rob_io_commit_uops_1_bp_xcpt_if; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_1_debug_fsrc; // @[core.scala:159:32] wire [2:0] _rob_io_commit_uops_1_debug_tsrc; // @[core.scala:159:32] wire _rob_io_commit_fflags_valid; // @[core.scala:159:32] wire [4:0] _rob_io_commit_fflags_bits; // @[core.scala:159:32] wire _rob_io_rollback; // @[core.scala:159:32] wire _rob_io_com_xcpt_valid; // @[core.scala:159:32] wire [4:0] _rob_io_com_xcpt_bits_ftq_idx; // @[core.scala:159:32] wire _rob_io_com_xcpt_bits_edge_inst; // @[core.scala:159:32] wire [5:0] _rob_io_com_xcpt_bits_pc_lob; // @[core.scala:159:32] wire [63:0] _rob_io_com_xcpt_bits_cause; // @[core.scala:159:32] wire [63:0] _rob_io_com_xcpt_bits_badvaddr; // @[core.scala:159:32] wire _rob_io_flush_valid; // @[core.scala:159:32] wire [4:0] _rob_io_flush_bits_ftq_idx; // @[core.scala:159:32] wire _rob_io_flush_bits_edge_inst; // @[core.scala:159:32] wire _rob_io_flush_bits_is_rvc; // @[core.scala:159:32] wire [5:0] _rob_io_flush_bits_pc_lob; // @[core.scala:159:32] wire [2:0] _rob_io_flush_bits_flush_typ; // @[core.scala:159:32] wire _rob_io_empty; // @[core.scala:159:32] wire _rob_io_ready; // @[core.scala:159:32] wire _rob_io_flush_frontend; // @[core.scala:159:32] wire [3:0] _bregfile_io_rrd_read_resps_0_ldq_idx; // @[core.scala:152:32] wire [3:0] _bregfile_io_rrd_read_resps_0_stq_idx; // @[core.scala:152:32] wire [1:0] _bregfile_io_rrd_read_resps_0_rxq_idx; // @[core.scala:152:32] wire [3:0] _bregfile_io_rrd_read_resps_1_ldq_idx; // @[core.scala:152:32] wire [3:0] _bregfile_io_rrd_read_resps_1_stq_idx; // @[core.scala:152:32] wire [1:0] _bregfile_io_rrd_read_resps_1_rxq_idx; // @[core.scala:152:32] wire [19:0] _immregfile_io_rrd_read_resps_0; // @[core.scala:145:32] wire [19:0] _immregfile_io_rrd_read_resps_1; // @[core.scala:145:32] wire [19:0] _immregfile_io_rrd_read_resps_2; // @[core.scala:145:32] wire [19:0] _immregfile_io_rrd_read_resps_3; // @[core.scala:145:32] wire [19:0] _immregfile_io_rrd_read_resps_4; // @[core.scala:145:32] wire _pregfile_io_rrd_read_resps_0; // @[core.scala:138:32] wire _pregfile_io_rrd_read_resps_1; // @[core.scala:138:32] wire _iregfile_io_arb_read_reqs_0_ready; // @[core.scala:127:32] wire _iregfile_io_arb_read_reqs_1_ready; // @[core.scala:127:32] wire _iregfile_io_arb_read_reqs_2_ready; // @[core.scala:127:32] wire _iregfile_io_arb_read_reqs_3_ready; // @[core.scala:127:32] wire _iregfile_io_arb_read_reqs_4_ready; // @[core.scala:127:32] wire _iregfile_io_arb_read_reqs_5_ready; // @[core.scala:127:32] wire _iregfile_io_arb_read_reqs_6_ready; // @[core.scala:127:32] wire _iregfile_io_arb_read_reqs_7_ready; // @[core.scala:127:32] wire [63:0] _iregfile_io_rrd_read_resps_0; // @[core.scala:127:32] wire [63:0] _iregfile_io_rrd_read_resps_1; // @[core.scala:127:32] wire [63:0] _iregfile_io_rrd_read_resps_2; // @[core.scala:127:32] wire [63:0] _iregfile_io_rrd_read_resps_3; // @[core.scala:127:32] wire [63:0] _iregfile_io_rrd_read_resps_4; // @[core.scala:127:32] wire [63:0] _iregfile_io_rrd_read_resps_5; // @[core.scala:127:32] wire [63:0] _iregfile_io_rrd_read_resps_6; // @[core.scala:127:32] wire [63:0] _iregfile_io_rrd_read_resps_7; // @[core.scala:127:32] wire _dispatcher_io_ren_uops_0_ready; // @[core.scala:125:32] wire _dispatcher_io_ren_uops_1_ready; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_valid; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_3_0_bits_inst; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_3_0_bits_debug_inst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_is_rvc; // @[core.scala:125:32] wire [39:0] _dispatcher_io_dis_uops_3_0_bits_debug_pc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_iq_type_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_iq_type_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_iq_type_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_iq_type_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fu_code_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fu_code_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fu_code_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fu_code_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fu_code_4; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fu_code_5; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fu_code_6; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fu_code_7; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fu_code_8; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fu_code_9; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_iw_issued; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_iw_issued_partial_agen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_iw_issued_partial_dgen; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_iw_p1_speculative_child; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_iw_p2_speculative_child; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_iw_p1_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_iw_p2_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_iw_p3_bypass_hint; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_dis_col_sel; // @[core.scala:125:32] wire [11:0] _dispatcher_io_dis_uops_3_0_bits_br_mask; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_3_0_bits_br_tag; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_3_0_bits_br_type; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_is_sfb; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_is_fence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_is_fencei; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_is_sfence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_is_amo; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_is_eret; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_is_sys_pc2epc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_is_rocc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_is_mov; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_3_0_bits_ftq_idx; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_edge_inst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_0_bits_pc_lob; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_taken; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_imm_rename; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_0_bits_imm_sel; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_3_0_bits_pimm; // @[core.scala:125:32] wire [19:0] _dispatcher_io_dis_uops_3_0_bits_imm_packed; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_op1_sel; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_0_bits_op2_sel; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_ldst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_wen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_ren1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_ren2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_ren3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_swap12; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_swap23; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_typeTagIn; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_typeTagOut; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_fromint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_toint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_fastpipe; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_fma; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_div; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_sqrt; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_wflags; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_ctrl_vec; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_0_bits_rob_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_3_0_bits_ldq_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_3_0_bits_stq_idx; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_rxq_idx; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_3_0_bits_pdst; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_3_0_bits_prs1; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_3_0_bits_prs2; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_3_0_bits_prs3; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_3_0_bits_ppred; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_prs1_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_prs2_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_prs3_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_ppred_busy; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_3_0_bits_stale_pdst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_exception; // @[core.scala:125:32] wire [63:0] _dispatcher_io_dis_uops_3_0_bits_exc_cause; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_3_0_bits_mem_cmd; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_mem_size; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_mem_signed; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_uses_ldq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_uses_stq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_is_unique; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_flush_on_commit; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_0_bits_csr_cmd; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_ldst_is_rs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_0_bits_ldst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_0_bits_lrs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_0_bits_lrs2; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_0_bits_lrs3; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_dst_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_lrs1_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_lrs2_rtype; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_frs3_en; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fcn_dw; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_3_0_bits_fcn_op; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_fp_val; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_0_bits_fp_rm; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_0_bits_fp_typ; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_xcpt_pf_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_xcpt_ae_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_xcpt_ma_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_bp_debug_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_0_bits_bp_xcpt_if; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_0_bits_debug_fsrc; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_0_bits_debug_tsrc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_valid; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_3_1_bits_inst; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_3_1_bits_debug_inst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_is_rvc; // @[core.scala:125:32] wire [39:0] _dispatcher_io_dis_uops_3_1_bits_debug_pc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_iq_type_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_iq_type_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_iq_type_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_iq_type_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fu_code_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fu_code_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fu_code_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fu_code_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fu_code_4; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fu_code_5; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fu_code_6; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fu_code_7; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fu_code_8; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fu_code_9; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_iw_issued; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_iw_issued_partial_agen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_iw_issued_partial_dgen; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_iw_p1_speculative_child; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_iw_p2_speculative_child; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_iw_p1_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_iw_p2_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_iw_p3_bypass_hint; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_dis_col_sel; // @[core.scala:125:32] wire [11:0] _dispatcher_io_dis_uops_3_1_bits_br_mask; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_3_1_bits_br_tag; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_3_1_bits_br_type; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_is_sfb; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_is_fence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_is_fencei; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_is_sfence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_is_amo; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_is_eret; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_is_sys_pc2epc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_is_rocc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_is_mov; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_3_1_bits_ftq_idx; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_edge_inst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_1_bits_pc_lob; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_taken; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_imm_rename; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_1_bits_imm_sel; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_3_1_bits_pimm; // @[core.scala:125:32] wire [19:0] _dispatcher_io_dis_uops_3_1_bits_imm_packed; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_op1_sel; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_1_bits_op2_sel; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_ldst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_wen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_ren1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_ren2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_ren3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_swap12; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_swap23; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_typeTagIn; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_typeTagOut; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_fromint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_toint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_fastpipe; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_fma; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_div; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_sqrt; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_wflags; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_ctrl_vec; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_1_bits_rob_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_3_1_bits_ldq_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_3_1_bits_stq_idx; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_rxq_idx; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_3_1_bits_pdst; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_3_1_bits_prs1; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_3_1_bits_prs2; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_3_1_bits_prs3; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_3_1_bits_ppred; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_prs1_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_prs2_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_prs3_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_ppred_busy; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_3_1_bits_stale_pdst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_exception; // @[core.scala:125:32] wire [63:0] _dispatcher_io_dis_uops_3_1_bits_exc_cause; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_3_1_bits_mem_cmd; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_mem_size; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_mem_signed; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_uses_ldq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_uses_stq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_is_unique; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_flush_on_commit; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_1_bits_csr_cmd; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_ldst_is_rs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_1_bits_ldst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_1_bits_lrs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_1_bits_lrs2; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_3_1_bits_lrs3; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_dst_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_lrs1_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_lrs2_rtype; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_frs3_en; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fcn_dw; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_3_1_bits_fcn_op; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_fp_val; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_1_bits_fp_rm; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_3_1_bits_fp_typ; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_xcpt_pf_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_xcpt_ae_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_xcpt_ma_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_bp_debug_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_3_1_bits_bp_xcpt_if; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_1_bits_debug_fsrc; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_3_1_bits_debug_tsrc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_valid; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_2_0_bits_inst; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_2_0_bits_debug_inst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_is_rvc; // @[core.scala:125:32] wire [39:0] _dispatcher_io_dis_uops_2_0_bits_debug_pc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_iq_type_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_iq_type_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_iq_type_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_iq_type_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fu_code_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fu_code_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fu_code_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fu_code_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fu_code_4; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fu_code_5; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fu_code_6; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fu_code_7; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fu_code_8; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fu_code_9; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_iw_issued; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_iw_issued_partial_agen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_iw_issued_partial_dgen; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_iw_p1_speculative_child; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_iw_p2_speculative_child; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_iw_p1_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_iw_p2_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_iw_p3_bypass_hint; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_dis_col_sel; // @[core.scala:125:32] wire [11:0] _dispatcher_io_dis_uops_2_0_bits_br_mask; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_2_0_bits_br_tag; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_2_0_bits_br_type; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_is_sfb; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_is_fence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_is_fencei; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_is_sfence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_is_amo; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_is_eret; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_is_sys_pc2epc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_is_rocc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_is_mov; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ftq_idx; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_edge_inst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_pc_lob; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_taken; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_imm_rename; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_imm_sel; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_pimm; // @[core.scala:125:32] wire [19:0] _dispatcher_io_dis_uops_2_0_bits_imm_packed; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_op1_sel; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_op2_sel; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_ldst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_wen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_ren1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_ren2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_ren3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_swap12; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_swap23; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_typeTagIn; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_typeTagOut; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_fromint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_toint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_fastpipe; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_fma; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_div; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_sqrt; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_wflags; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_ctrl_vec; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_rob_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_2_0_bits_ldq_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_2_0_bits_stq_idx; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_rxq_idx; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_pdst; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs1; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs2; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_prs3; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_ppred; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_prs1_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_prs2_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_prs3_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_ppred_busy; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_2_0_bits_stale_pdst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_exception; // @[core.scala:125:32] wire [63:0] _dispatcher_io_dis_uops_2_0_bits_exc_cause; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_mem_cmd; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_mem_size; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_mem_signed; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_uses_ldq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_uses_stq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_is_unique; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_flush_on_commit; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_csr_cmd; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_ldst_is_rs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_ldst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs2; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_0_bits_lrs3; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_dst_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs1_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_lrs2_rtype; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_frs3_en; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fcn_dw; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_2_0_bits_fcn_op; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_fp_val; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_fp_rm; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_0_bits_fp_typ; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_xcpt_pf_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ae_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_xcpt_ma_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_bp_debug_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_0_bits_bp_xcpt_if; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_debug_fsrc; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_0_bits_debug_tsrc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_valid; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_2_1_bits_inst; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_2_1_bits_debug_inst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_is_rvc; // @[core.scala:125:32] wire [39:0] _dispatcher_io_dis_uops_2_1_bits_debug_pc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_iq_type_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_iq_type_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_iq_type_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_iq_type_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fu_code_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fu_code_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fu_code_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fu_code_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fu_code_4; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fu_code_5; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fu_code_6; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fu_code_7; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fu_code_8; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fu_code_9; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_iw_issued; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_iw_issued_partial_agen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_iw_issued_partial_dgen; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_iw_p1_speculative_child; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_iw_p2_speculative_child; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_iw_p1_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_iw_p2_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_iw_p3_bypass_hint; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_dis_col_sel; // @[core.scala:125:32] wire [11:0] _dispatcher_io_dis_uops_2_1_bits_br_mask; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_2_1_bits_br_tag; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_2_1_bits_br_type; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_is_sfb; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_is_fence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_is_fencei; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_is_sfence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_is_amo; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_is_eret; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_is_sys_pc2epc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_is_rocc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_is_mov; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ftq_idx; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_edge_inst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_pc_lob; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_taken; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_imm_rename; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_imm_sel; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_pimm; // @[core.scala:125:32] wire [19:0] _dispatcher_io_dis_uops_2_1_bits_imm_packed; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_op1_sel; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_op2_sel; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_ldst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_wen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_ren1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_ren2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_ren3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_swap12; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_swap23; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_typeTagIn; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_typeTagOut; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_fromint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_toint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_fastpipe; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_fma; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_div; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_sqrt; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_wflags; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_ctrl_vec; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_rob_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_2_1_bits_ldq_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_2_1_bits_stq_idx; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_rxq_idx; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_pdst; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs1; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs2; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_prs3; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_ppred; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_prs1_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_prs2_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_prs3_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_ppred_busy; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_2_1_bits_stale_pdst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_exception; // @[core.scala:125:32] wire [63:0] _dispatcher_io_dis_uops_2_1_bits_exc_cause; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_mem_cmd; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_mem_size; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_mem_signed; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_uses_ldq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_uses_stq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_is_unique; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_flush_on_commit; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_csr_cmd; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_ldst_is_rs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_ldst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs2; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_2_1_bits_lrs3; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_dst_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_lrs1_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_lrs2_rtype; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_frs3_en; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fcn_dw; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_2_1_bits_fcn_op; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_fp_val; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_fp_rm; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_2_1_bits_fp_typ; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_xcpt_pf_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_xcpt_ae_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_xcpt_ma_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_bp_debug_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_2_1_bits_bp_xcpt_if; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_debug_fsrc; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_2_1_bits_debug_tsrc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_valid; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_1_0_bits_inst; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_1_0_bits_debug_inst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_is_rvc; // @[core.scala:125:32] wire [39:0] _dispatcher_io_dis_uops_1_0_bits_debug_pc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_iq_type_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_iq_type_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_iq_type_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_iq_type_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fu_code_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fu_code_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fu_code_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fu_code_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fu_code_4; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fu_code_5; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fu_code_6; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fu_code_7; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fu_code_8; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fu_code_9; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_iw_issued; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_iw_issued_partial_agen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_iw_issued_partial_dgen; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_iw_p1_speculative_child; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_iw_p2_speculative_child; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_iw_p1_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_iw_p2_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_iw_p3_bypass_hint; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_dis_col_sel; // @[core.scala:125:32] wire [11:0] _dispatcher_io_dis_uops_1_0_bits_br_mask; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_1_0_bits_br_tag; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_1_0_bits_br_type; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_is_sfb; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_is_fence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_is_fencei; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_is_sfence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_is_amo; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_is_eret; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_is_sys_pc2epc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_is_rocc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_is_mov; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ftq_idx; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_edge_inst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_pc_lob; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_taken; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_imm_rename; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_imm_sel; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_pimm; // @[core.scala:125:32] wire [19:0] _dispatcher_io_dis_uops_1_0_bits_imm_packed; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_op1_sel; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_op2_sel; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_ldst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_wen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_ren1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_ren2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_ren3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_swap12; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_swap23; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_typeTagIn; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_typeTagOut; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_fromint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_toint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_fastpipe; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_fma; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_div; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_sqrt; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_wflags; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_ctrl_vec; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_rob_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_1_0_bits_ldq_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_1_0_bits_stq_idx; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_rxq_idx; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_pdst; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs1; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs2; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_prs3; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_ppred; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_prs1_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_prs2_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_prs3_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_ppred_busy; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_1_0_bits_stale_pdst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_exception; // @[core.scala:125:32] wire [63:0] _dispatcher_io_dis_uops_1_0_bits_exc_cause; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_mem_cmd; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_mem_size; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_mem_signed; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_uses_ldq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_uses_stq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_is_unique; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_flush_on_commit; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_csr_cmd; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_ldst_is_rs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_ldst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs2; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_0_bits_lrs3; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_dst_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs1_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_lrs2_rtype; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_frs3_en; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fcn_dw; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_1_0_bits_fcn_op; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_fp_val; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_fp_rm; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_0_bits_fp_typ; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_xcpt_pf_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ae_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_xcpt_ma_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_bp_debug_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_0_bits_bp_xcpt_if; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_debug_fsrc; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_0_bits_debug_tsrc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_valid; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_1_1_bits_inst; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_1_1_bits_debug_inst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_is_rvc; // @[core.scala:125:32] wire [39:0] _dispatcher_io_dis_uops_1_1_bits_debug_pc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_iq_type_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_iq_type_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_iq_type_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_iq_type_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fu_code_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fu_code_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fu_code_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fu_code_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fu_code_4; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fu_code_5; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fu_code_6; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fu_code_7; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fu_code_8; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fu_code_9; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_iw_issued; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_iw_issued_partial_agen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_iw_issued_partial_dgen; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_iw_p1_speculative_child; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_iw_p2_speculative_child; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_iw_p1_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_iw_p2_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_iw_p3_bypass_hint; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_dis_col_sel; // @[core.scala:125:32] wire [11:0] _dispatcher_io_dis_uops_1_1_bits_br_mask; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_1_1_bits_br_tag; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_1_1_bits_br_type; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_is_sfb; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_is_fence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_is_fencei; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_is_sfence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_is_amo; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_is_eret; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_is_sys_pc2epc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_is_rocc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_is_mov; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ftq_idx; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_edge_inst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_pc_lob; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_taken; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_imm_rename; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_imm_sel; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_pimm; // @[core.scala:125:32] wire [19:0] _dispatcher_io_dis_uops_1_1_bits_imm_packed; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_op1_sel; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_op2_sel; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_ldst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_wen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_ren1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_ren2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_ren3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_swap12; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_swap23; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_typeTagIn; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_typeTagOut; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_fromint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_toint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_fastpipe; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_fma; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_div; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_sqrt; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_wflags; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_ctrl_vec; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_rob_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_1_1_bits_ldq_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_1_1_bits_stq_idx; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_rxq_idx; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_pdst; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs1; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs2; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_prs3; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_ppred; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_prs1_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_prs2_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_prs3_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_ppred_busy; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_1_1_bits_stale_pdst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_exception; // @[core.scala:125:32] wire [63:0] _dispatcher_io_dis_uops_1_1_bits_exc_cause; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_mem_cmd; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_mem_size; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_mem_signed; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_uses_ldq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_uses_stq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_is_unique; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_flush_on_commit; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_csr_cmd; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_ldst_is_rs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_ldst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs2; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_1_1_bits_lrs3; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_dst_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_lrs1_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_lrs2_rtype; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_frs3_en; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fcn_dw; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_1_1_bits_fcn_op; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_fp_val; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_fp_rm; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_1_1_bits_fp_typ; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_xcpt_pf_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_xcpt_ae_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_xcpt_ma_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_bp_debug_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_1_1_bits_bp_xcpt_if; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_debug_fsrc; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_1_1_bits_debug_tsrc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_valid; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_0_0_bits_inst; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_0_0_bits_debug_inst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_is_rvc; // @[core.scala:125:32] wire [39:0] _dispatcher_io_dis_uops_0_0_bits_debug_pc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_iq_type_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_iq_type_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_iq_type_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_iq_type_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fu_code_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fu_code_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fu_code_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fu_code_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fu_code_4; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fu_code_5; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fu_code_6; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fu_code_7; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fu_code_8; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fu_code_9; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_iw_issued; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_iw_issued_partial_agen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_iw_issued_partial_dgen; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_iw_p1_speculative_child; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_iw_p2_speculative_child; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_iw_p1_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_iw_p2_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_iw_p3_bypass_hint; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_dis_col_sel; // @[core.scala:125:32] wire [11:0] _dispatcher_io_dis_uops_0_0_bits_br_mask; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_0_0_bits_br_tag; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_0_0_bits_br_type; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_is_sfb; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_is_fence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_is_fencei; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_is_sfence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_is_amo; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_is_eret; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_is_sys_pc2epc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_is_rocc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_is_mov; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ftq_idx; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_edge_inst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_pc_lob; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_taken; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_imm_rename; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_imm_sel; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_pimm; // @[core.scala:125:32] wire [19:0] _dispatcher_io_dis_uops_0_0_bits_imm_packed; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_op1_sel; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_op2_sel; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_ldst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_wen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_ren1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_ren2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_ren3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_swap12; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_swap23; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_typeTagIn; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_typeTagOut; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_fromint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_toint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_fastpipe; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_fma; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_div; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_sqrt; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_wflags; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_ctrl_vec; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_rob_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_0_0_bits_ldq_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_0_0_bits_stq_idx; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_rxq_idx; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_pdst; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs1; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs2; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_prs3; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_ppred; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_prs1_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_prs2_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_prs3_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_ppred_busy; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_0_0_bits_stale_pdst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_exception; // @[core.scala:125:32] wire [63:0] _dispatcher_io_dis_uops_0_0_bits_exc_cause; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_mem_cmd; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_mem_size; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_mem_signed; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_uses_ldq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_uses_stq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_is_unique; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_flush_on_commit; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_csr_cmd; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_ldst_is_rs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_ldst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs2; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_0_bits_lrs3; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_dst_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs1_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_lrs2_rtype; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_frs3_en; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fcn_dw; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_0_0_bits_fcn_op; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_fp_val; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_fp_rm; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_0_bits_fp_typ; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_xcpt_pf_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ae_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_xcpt_ma_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_bp_debug_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_0_bits_bp_xcpt_if; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_debug_fsrc; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_0_bits_debug_tsrc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_valid; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_0_1_bits_inst; // @[core.scala:125:32] wire [31:0] _dispatcher_io_dis_uops_0_1_bits_debug_inst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_is_rvc; // @[core.scala:125:32] wire [39:0] _dispatcher_io_dis_uops_0_1_bits_debug_pc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_iq_type_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_iq_type_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_iq_type_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_iq_type_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fu_code_0; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fu_code_1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fu_code_2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fu_code_3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fu_code_4; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fu_code_5; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fu_code_6; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fu_code_7; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fu_code_8; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fu_code_9; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_iw_issued; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_iw_issued_partial_agen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_iw_issued_partial_dgen; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_iw_p1_speculative_child; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_iw_p2_speculative_child; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_iw_p1_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_iw_p2_bypass_hint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_iw_p3_bypass_hint; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_dis_col_sel; // @[core.scala:125:32] wire [11:0] _dispatcher_io_dis_uops_0_1_bits_br_mask; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_0_1_bits_br_tag; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_0_1_bits_br_type; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_is_sfb; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_is_fence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_is_fencei; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_is_sfence; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_is_amo; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_is_eret; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_is_sys_pc2epc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_is_rocc; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_is_mov; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ftq_idx; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_edge_inst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_pc_lob; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_taken; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_imm_rename; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_imm_sel; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_pimm; // @[core.scala:125:32] wire [19:0] _dispatcher_io_dis_uops_0_1_bits_imm_packed; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_op1_sel; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_op2_sel; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_ldst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_wen; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_ren1; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_ren2; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_ren3; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_swap12; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_swap23; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_typeTagIn; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_typeTagOut; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_fromint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_toint; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_fastpipe; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_fma; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_div; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_sqrt; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_wflags; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_ctrl_vec; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_rob_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_0_1_bits_ldq_idx; // @[core.scala:125:32] wire [3:0] _dispatcher_io_dis_uops_0_1_bits_stq_idx; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_rxq_idx; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_pdst; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs1; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs2; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_prs3; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_ppred; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_prs1_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_prs2_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_prs3_busy; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_ppred_busy; // @[core.scala:125:32] wire [6:0] _dispatcher_io_dis_uops_0_1_bits_stale_pdst; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_exception; // @[core.scala:125:32] wire [63:0] _dispatcher_io_dis_uops_0_1_bits_exc_cause; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_mem_cmd; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_mem_size; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_mem_signed; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_uses_ldq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_uses_stq; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_is_unique; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_flush_on_commit; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_csr_cmd; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_ldst_is_rs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_ldst; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs1; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs2; // @[core.scala:125:32] wire [5:0] _dispatcher_io_dis_uops_0_1_bits_lrs3; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_dst_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_lrs1_rtype; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_lrs2_rtype; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_frs3_en; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fcn_dw; // @[core.scala:125:32] wire [4:0] _dispatcher_io_dis_uops_0_1_bits_fcn_op; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_fp_val; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_fp_rm; // @[core.scala:125:32] wire [1:0] _dispatcher_io_dis_uops_0_1_bits_fp_typ; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_xcpt_pf_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_xcpt_ae_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_xcpt_ma_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_bp_debug_if; // @[core.scala:125:32] wire _dispatcher_io_dis_uops_0_1_bits_bp_xcpt_if; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_debug_fsrc; // @[core.scala:125:32] wire [2:0] _dispatcher_io_dis_uops_0_1_bits_debug_tsrc; // @[core.scala:125:32] wire _alu_iss_unit_io_dis_uops_0_ready; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_dis_uops_1_ready; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_valid; // @[issue-unit.scala:81:13] wire [31:0] _alu_iss_unit_io_iss_uops_0_bits_inst; // @[issue-unit.scala:81:13] wire [31:0] _alu_iss_unit_io_iss_uops_0_bits_debug_inst; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_is_rvc; // @[issue-unit.scala:81:13] wire [39:0] _alu_iss_unit_io_iss_uops_0_bits_debug_pc; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_iq_type_0; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_iq_type_1; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_iq_type_2; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_iq_type_3; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fu_code_0; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fu_code_1; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fu_code_2; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fu_code_3; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fu_code_4; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fu_code_5; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fu_code_6; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fu_code_7; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fu_code_8; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fu_code_9; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_iw_issued; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_dis_col_sel; // @[issue-unit.scala:81:13] wire [11:0] _alu_iss_unit_io_iss_uops_0_bits_br_mask; // @[issue-unit.scala:81:13] wire [3:0] _alu_iss_unit_io_iss_uops_0_bits_br_tag; // @[issue-unit.scala:81:13] wire [3:0] _alu_iss_unit_io_iss_uops_0_bits_br_type; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_is_sfb; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_is_fence; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_is_fencei; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_is_sfence; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_is_amo; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_is_eret; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_is_rocc; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_is_mov; // @[issue-unit.scala:81:13] wire [4:0] _alu_iss_unit_io_iss_uops_0_bits_ftq_idx; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_edge_inst; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_0_bits_pc_lob; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_taken; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_imm_rename; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_0_bits_imm_sel; // @[issue-unit.scala:81:13] wire [4:0] _alu_iss_unit_io_iss_uops_0_bits_pimm; // @[issue-unit.scala:81:13] wire [19:0] _alu_iss_unit_io_iss_uops_0_bits_imm_packed; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_op1_sel; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_0_bits_op2_sel; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_div; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_0_bits_rob_idx; // @[issue-unit.scala:81:13] wire [3:0] _alu_iss_unit_io_iss_uops_0_bits_ldq_idx; // @[issue-unit.scala:81:13] wire [3:0] _alu_iss_unit_io_iss_uops_0_bits_stq_idx; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_rxq_idx; // @[issue-unit.scala:81:13] wire [6:0] _alu_iss_unit_io_iss_uops_0_bits_pdst; // @[issue-unit.scala:81:13] wire [6:0] _alu_iss_unit_io_iss_uops_0_bits_prs1; // @[issue-unit.scala:81:13] wire [6:0] _alu_iss_unit_io_iss_uops_0_bits_prs2; // @[issue-unit.scala:81:13] wire [6:0] _alu_iss_unit_io_iss_uops_0_bits_prs3; // @[issue-unit.scala:81:13] wire [4:0] _alu_iss_unit_io_iss_uops_0_bits_ppred; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_prs1_busy; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_prs2_busy; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_prs3_busy; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_ppred_busy; // @[issue-unit.scala:81:13] wire [6:0] _alu_iss_unit_io_iss_uops_0_bits_stale_pdst; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_exception; // @[issue-unit.scala:81:13] wire [63:0] _alu_iss_unit_io_iss_uops_0_bits_exc_cause; // @[issue-unit.scala:81:13] wire [4:0] _alu_iss_unit_io_iss_uops_0_bits_mem_cmd; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_mem_size; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_mem_signed; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_uses_ldq; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_uses_stq; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_is_unique; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_flush_on_commit; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_0_bits_csr_cmd; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_ldst_is_rs1; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_0_bits_ldst; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_0_bits_lrs1; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_0_bits_lrs2; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_0_bits_lrs3; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_dst_rtype; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_lrs1_rtype; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_lrs2_rtype; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_frs3_en; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fcn_dw; // @[issue-unit.scala:81:13] wire [4:0] _alu_iss_unit_io_iss_uops_0_bits_fcn_op; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_fp_val; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_0_bits_fp_rm; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_0_bits_fp_typ; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_xcpt_pf_if; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_xcpt_ae_if; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_xcpt_ma_if; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_bp_debug_if; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_0_bits_bp_xcpt_if; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_0_bits_debug_fsrc; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_0_bits_debug_tsrc; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_valid; // @[issue-unit.scala:81:13] wire [31:0] _alu_iss_unit_io_iss_uops_1_bits_inst; // @[issue-unit.scala:81:13] wire [31:0] _alu_iss_unit_io_iss_uops_1_bits_debug_inst; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_is_rvc; // @[issue-unit.scala:81:13] wire [39:0] _alu_iss_unit_io_iss_uops_1_bits_debug_pc; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_iq_type_0; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_iq_type_1; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_iq_type_2; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_iq_type_3; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fu_code_0; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fu_code_1; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fu_code_2; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fu_code_3; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fu_code_4; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fu_code_5; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fu_code_6; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fu_code_7; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fu_code_8; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fu_code_9; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_iw_issued; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_iw_p1_speculative_child; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_iw_p2_speculative_child; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_dis_col_sel; // @[issue-unit.scala:81:13] wire [11:0] _alu_iss_unit_io_iss_uops_1_bits_br_mask; // @[issue-unit.scala:81:13] wire [3:0] _alu_iss_unit_io_iss_uops_1_bits_br_tag; // @[issue-unit.scala:81:13] wire [3:0] _alu_iss_unit_io_iss_uops_1_bits_br_type; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_is_sfb; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_is_fence; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_is_fencei; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_is_sfence; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_is_amo; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_is_eret; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_is_sys_pc2epc; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_is_rocc; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_is_mov; // @[issue-unit.scala:81:13] wire [4:0] _alu_iss_unit_io_iss_uops_1_bits_ftq_idx; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_edge_inst; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_1_bits_pc_lob; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_taken; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_imm_rename; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_1_bits_imm_sel; // @[issue-unit.scala:81:13] wire [4:0] _alu_iss_unit_io_iss_uops_1_bits_pimm; // @[issue-unit.scala:81:13] wire [19:0] _alu_iss_unit_io_iss_uops_1_bits_imm_packed; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_op1_sel; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_1_bits_op2_sel; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_ldst; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_wen; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_ren1; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_ren2; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_ren3; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_swap12; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_swap23; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_fromint; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_toint; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_fma; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_div; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_wflags; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_ctrl_vec; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_1_bits_rob_idx; // @[issue-unit.scala:81:13] wire [3:0] _alu_iss_unit_io_iss_uops_1_bits_ldq_idx; // @[issue-unit.scala:81:13] wire [3:0] _alu_iss_unit_io_iss_uops_1_bits_stq_idx; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_rxq_idx; // @[issue-unit.scala:81:13] wire [6:0] _alu_iss_unit_io_iss_uops_1_bits_pdst; // @[issue-unit.scala:81:13] wire [6:0] _alu_iss_unit_io_iss_uops_1_bits_prs1; // @[issue-unit.scala:81:13] wire [6:0] _alu_iss_unit_io_iss_uops_1_bits_prs2; // @[issue-unit.scala:81:13] wire [6:0] _alu_iss_unit_io_iss_uops_1_bits_prs3; // @[issue-unit.scala:81:13] wire [4:0] _alu_iss_unit_io_iss_uops_1_bits_ppred; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_prs1_busy; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_prs2_busy; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_prs3_busy; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_ppred_busy; // @[issue-unit.scala:81:13] wire [6:0] _alu_iss_unit_io_iss_uops_1_bits_stale_pdst; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_exception; // @[issue-unit.scala:81:13] wire [63:0] _alu_iss_unit_io_iss_uops_1_bits_exc_cause; // @[issue-unit.scala:81:13] wire [4:0] _alu_iss_unit_io_iss_uops_1_bits_mem_cmd; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_mem_size; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_mem_signed; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_uses_ldq; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_uses_stq; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_is_unique; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_flush_on_commit; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_1_bits_csr_cmd; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_ldst_is_rs1; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_1_bits_ldst; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_1_bits_lrs1; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_1_bits_lrs2; // @[issue-unit.scala:81:13] wire [5:0] _alu_iss_unit_io_iss_uops_1_bits_lrs3; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_dst_rtype; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_lrs1_rtype; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_lrs2_rtype; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_frs3_en; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fcn_dw; // @[issue-unit.scala:81:13] wire [4:0] _alu_iss_unit_io_iss_uops_1_bits_fcn_op; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_fp_val; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_1_bits_fp_rm; // @[issue-unit.scala:81:13] wire [1:0] _alu_iss_unit_io_iss_uops_1_bits_fp_typ; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_xcpt_pf_if; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_xcpt_ae_if; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_xcpt_ma_if; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_bp_debug_if; // @[issue-unit.scala:81:13] wire _alu_iss_unit_io_iss_uops_1_bits_bp_xcpt_if; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_1_bits_debug_fsrc; // @[issue-unit.scala:81:13] wire [2:0] _alu_iss_unit_io_iss_uops_1_bits_debug_tsrc; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_dis_uops_0_ready; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_dis_uops_1_ready; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_valid; // @[issue-unit.scala:81:13] wire [31:0] _unq_iss_unit_io_iss_uops_0_bits_inst; // @[issue-unit.scala:81:13] wire [31:0] _unq_iss_unit_io_iss_uops_0_bits_debug_inst; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_is_rvc; // @[issue-unit.scala:81:13] wire [39:0] _unq_iss_unit_io_iss_uops_0_bits_debug_pc; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_iq_type_0; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_iq_type_1; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_iq_type_2; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_iq_type_3; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fu_code_0; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fu_code_1; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fu_code_2; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fu_code_3; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fu_code_4; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fu_code_5; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fu_code_6; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fu_code_7; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fu_code_8; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fu_code_9; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_iw_issued; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_dis_col_sel; // @[issue-unit.scala:81:13] wire [11:0] _unq_iss_unit_io_iss_uops_0_bits_br_mask; // @[issue-unit.scala:81:13] wire [3:0] _unq_iss_unit_io_iss_uops_0_bits_br_tag; // @[issue-unit.scala:81:13] wire [3:0] _unq_iss_unit_io_iss_uops_0_bits_br_type; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_is_sfb; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_is_fence; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_is_fencei; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_is_sfence; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_is_amo; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_is_eret; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_is_rocc; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_is_mov; // @[issue-unit.scala:81:13] wire [4:0] _unq_iss_unit_io_iss_uops_0_bits_ftq_idx; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_edge_inst; // @[issue-unit.scala:81:13] wire [5:0] _unq_iss_unit_io_iss_uops_0_bits_pc_lob; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_taken; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_imm_rename; // @[issue-unit.scala:81:13] wire [2:0] _unq_iss_unit_io_iss_uops_0_bits_imm_sel; // @[issue-unit.scala:81:13] wire [4:0] _unq_iss_unit_io_iss_uops_0_bits_pimm; // @[issue-unit.scala:81:13] wire [19:0] _unq_iss_unit_io_iss_uops_0_bits_imm_packed; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_op1_sel; // @[issue-unit.scala:81:13] wire [2:0] _unq_iss_unit_io_iss_uops_0_bits_op2_sel; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_div; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit.scala:81:13] wire [5:0] _unq_iss_unit_io_iss_uops_0_bits_rob_idx; // @[issue-unit.scala:81:13] wire [3:0] _unq_iss_unit_io_iss_uops_0_bits_ldq_idx; // @[issue-unit.scala:81:13] wire [3:0] _unq_iss_unit_io_iss_uops_0_bits_stq_idx; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_rxq_idx; // @[issue-unit.scala:81:13] wire [6:0] _unq_iss_unit_io_iss_uops_0_bits_pdst; // @[issue-unit.scala:81:13] wire [6:0] _unq_iss_unit_io_iss_uops_0_bits_prs1; // @[issue-unit.scala:81:13] wire [6:0] _unq_iss_unit_io_iss_uops_0_bits_prs2; // @[issue-unit.scala:81:13] wire [6:0] _unq_iss_unit_io_iss_uops_0_bits_prs3; // @[issue-unit.scala:81:13] wire [4:0] _unq_iss_unit_io_iss_uops_0_bits_ppred; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_prs1_busy; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_prs2_busy; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_prs3_busy; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_ppred_busy; // @[issue-unit.scala:81:13] wire [6:0] _unq_iss_unit_io_iss_uops_0_bits_stale_pdst; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_exception; // @[issue-unit.scala:81:13] wire [63:0] _unq_iss_unit_io_iss_uops_0_bits_exc_cause; // @[issue-unit.scala:81:13] wire [4:0] _unq_iss_unit_io_iss_uops_0_bits_mem_cmd; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_mem_size; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_mem_signed; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_uses_ldq; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_uses_stq; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_is_unique; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_flush_on_commit; // @[issue-unit.scala:81:13] wire [2:0] _unq_iss_unit_io_iss_uops_0_bits_csr_cmd; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_ldst_is_rs1; // @[issue-unit.scala:81:13] wire [5:0] _unq_iss_unit_io_iss_uops_0_bits_ldst; // @[issue-unit.scala:81:13] wire [5:0] _unq_iss_unit_io_iss_uops_0_bits_lrs1; // @[issue-unit.scala:81:13] wire [5:0] _unq_iss_unit_io_iss_uops_0_bits_lrs2; // @[issue-unit.scala:81:13] wire [5:0] _unq_iss_unit_io_iss_uops_0_bits_lrs3; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_dst_rtype; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_lrs1_rtype; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_lrs2_rtype; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_frs3_en; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fcn_dw; // @[issue-unit.scala:81:13] wire [4:0] _unq_iss_unit_io_iss_uops_0_bits_fcn_op; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_fp_val; // @[issue-unit.scala:81:13] wire [2:0] _unq_iss_unit_io_iss_uops_0_bits_fp_rm; // @[issue-unit.scala:81:13] wire [1:0] _unq_iss_unit_io_iss_uops_0_bits_fp_typ; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_xcpt_pf_if; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_xcpt_ae_if; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_xcpt_ma_if; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_bp_debug_if; // @[issue-unit.scala:81:13] wire _unq_iss_unit_io_iss_uops_0_bits_bp_xcpt_if; // @[issue-unit.scala:81:13] wire [2:0] _unq_iss_unit_io_iss_uops_0_bits_debug_fsrc; // @[issue-unit.scala:81:13] wire [2:0] _unq_iss_unit_io_iss_uops_0_bits_debug_tsrc; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_dis_uops_0_ready; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_dis_uops_1_ready; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_valid; // @[issue-unit.scala:81:13] wire [31:0] _mem_iss_unit_io_iss_uops_0_bits_inst; // @[issue-unit.scala:81:13] wire [31:0] _mem_iss_unit_io_iss_uops_0_bits_debug_inst; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_is_rvc; // @[issue-unit.scala:81:13] wire [39:0] _mem_iss_unit_io_iss_uops_0_bits_debug_pc; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_iq_type_0; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_iq_type_1; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_iq_type_2; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_iq_type_3; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fu_code_0; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fu_code_1; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fu_code_2; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fu_code_3; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fu_code_4; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fu_code_5; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fu_code_6; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fu_code_7; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fu_code_8; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fu_code_9; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_iw_issued; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_iw_issued_partial_agen; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_iw_issued_partial_dgen; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_0_bits_iw_p1_speculative_child; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_0_bits_iw_p2_speculative_child; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_iw_p1_bypass_hint; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_iw_p2_bypass_hint; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_iw_p3_bypass_hint; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_0_bits_dis_col_sel; // @[issue-unit.scala:81:13] wire [11:0] _mem_iss_unit_io_iss_uops_0_bits_br_mask; // @[issue-unit.scala:81:13] wire [3:0] _mem_iss_unit_io_iss_uops_0_bits_br_tag; // @[issue-unit.scala:81:13] wire [3:0] _mem_iss_unit_io_iss_uops_0_bits_br_type; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_is_sfb; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_is_fence; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_is_fencei; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_is_sfence; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_is_amo; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_is_eret; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_is_sys_pc2epc; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_is_rocc; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_is_mov; // @[issue-unit.scala:81:13] wire [4:0] _mem_iss_unit_io_iss_uops_0_bits_ftq_idx; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_edge_inst; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_0_bits_pc_lob; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_taken; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_imm_rename; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_0_bits_imm_sel; // @[issue-unit.scala:81:13] wire [4:0] _mem_iss_unit_io_iss_uops_0_bits_pimm; // @[issue-unit.scala:81:13] wire [19:0] _mem_iss_unit_io_iss_uops_0_bits_imm_packed; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_0_bits_op1_sel; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_0_bits_op2_sel; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_ldst; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_wen; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_ren1; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_ren2; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_ren3; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_swap12; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_swap23; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_typeTagIn; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_typeTagOut; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_fromint; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_toint; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_fastpipe; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_fma; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_div; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_sqrt; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_wflags; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_ctrl_vec; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_0_bits_rob_idx; // @[issue-unit.scala:81:13] wire [3:0] _mem_iss_unit_io_iss_uops_0_bits_ldq_idx; // @[issue-unit.scala:81:13] wire [3:0] _mem_iss_unit_io_iss_uops_0_bits_stq_idx; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_0_bits_rxq_idx; // @[issue-unit.scala:81:13] wire [6:0] _mem_iss_unit_io_iss_uops_0_bits_pdst; // @[issue-unit.scala:81:13] wire [6:0] _mem_iss_unit_io_iss_uops_0_bits_prs1; // @[issue-unit.scala:81:13] wire [6:0] _mem_iss_unit_io_iss_uops_0_bits_prs2; // @[issue-unit.scala:81:13] wire [6:0] _mem_iss_unit_io_iss_uops_0_bits_prs3; // @[issue-unit.scala:81:13] wire [4:0] _mem_iss_unit_io_iss_uops_0_bits_ppred; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_prs1_busy; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_prs2_busy; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_prs3_busy; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_ppred_busy; // @[issue-unit.scala:81:13] wire [6:0] _mem_iss_unit_io_iss_uops_0_bits_stale_pdst; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_exception; // @[issue-unit.scala:81:13] wire [63:0] _mem_iss_unit_io_iss_uops_0_bits_exc_cause; // @[issue-unit.scala:81:13] wire [4:0] _mem_iss_unit_io_iss_uops_0_bits_mem_cmd; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_0_bits_mem_size; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_mem_signed; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_uses_ldq; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_uses_stq; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_is_unique; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_flush_on_commit; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_0_bits_csr_cmd; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_ldst_is_rs1; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_0_bits_ldst; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_0_bits_lrs1; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_0_bits_lrs2; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_0_bits_lrs3; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_0_bits_dst_rtype; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_0_bits_lrs1_rtype; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_frs3_en; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fcn_dw; // @[issue-unit.scala:81:13] wire [4:0] _mem_iss_unit_io_iss_uops_0_bits_fcn_op; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_fp_val; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_0_bits_fp_rm; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_0_bits_fp_typ; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_xcpt_pf_if; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_xcpt_ae_if; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_xcpt_ma_if; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_bp_debug_if; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_0_bits_bp_xcpt_if; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_0_bits_debug_fsrc; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_0_bits_debug_tsrc; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_valid; // @[issue-unit.scala:81:13] wire [31:0] _mem_iss_unit_io_iss_uops_1_bits_inst; // @[issue-unit.scala:81:13] wire [31:0] _mem_iss_unit_io_iss_uops_1_bits_debug_inst; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_is_rvc; // @[issue-unit.scala:81:13] wire [39:0] _mem_iss_unit_io_iss_uops_1_bits_debug_pc; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_iq_type_0; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_iq_type_1; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_iq_type_2; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_iq_type_3; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fu_code_0; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fu_code_1; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fu_code_2; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fu_code_3; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fu_code_4; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fu_code_5; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fu_code_6; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fu_code_7; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fu_code_8; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fu_code_9; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_iw_issued; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_iw_issued_partial_agen; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_iw_issued_partial_dgen; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_1_bits_iw_p1_speculative_child; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_1_bits_iw_p2_speculative_child; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_iw_p1_bypass_hint; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_iw_p2_bypass_hint; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_iw_p3_bypass_hint; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_1_bits_dis_col_sel; // @[issue-unit.scala:81:13] wire [11:0] _mem_iss_unit_io_iss_uops_1_bits_br_mask; // @[issue-unit.scala:81:13] wire [3:0] _mem_iss_unit_io_iss_uops_1_bits_br_tag; // @[issue-unit.scala:81:13] wire [3:0] _mem_iss_unit_io_iss_uops_1_bits_br_type; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_is_sfb; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_is_fence; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_is_fencei; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_is_sfence; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_is_amo; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_is_eret; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_is_sys_pc2epc; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_is_rocc; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_is_mov; // @[issue-unit.scala:81:13] wire [4:0] _mem_iss_unit_io_iss_uops_1_bits_ftq_idx; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_edge_inst; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_1_bits_pc_lob; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_taken; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_imm_rename; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_1_bits_imm_sel; // @[issue-unit.scala:81:13] wire [4:0] _mem_iss_unit_io_iss_uops_1_bits_pimm; // @[issue-unit.scala:81:13] wire [19:0] _mem_iss_unit_io_iss_uops_1_bits_imm_packed; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_1_bits_op1_sel; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_1_bits_op2_sel; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_ldst; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_wen; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_ren1; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_ren2; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_ren3; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_swap12; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_swap23; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_typeTagIn; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_typeTagOut; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_fromint; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_toint; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_fastpipe; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_fma; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_div; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_sqrt; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_wflags; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_ctrl_vec; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_1_bits_rob_idx; // @[issue-unit.scala:81:13] wire [3:0] _mem_iss_unit_io_iss_uops_1_bits_ldq_idx; // @[issue-unit.scala:81:13] wire [3:0] _mem_iss_unit_io_iss_uops_1_bits_stq_idx; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_1_bits_rxq_idx; // @[issue-unit.scala:81:13] wire [6:0] _mem_iss_unit_io_iss_uops_1_bits_pdst; // @[issue-unit.scala:81:13] wire [6:0] _mem_iss_unit_io_iss_uops_1_bits_prs1; // @[issue-unit.scala:81:13] wire [6:0] _mem_iss_unit_io_iss_uops_1_bits_prs2; // @[issue-unit.scala:81:13] wire [6:0] _mem_iss_unit_io_iss_uops_1_bits_prs3; // @[issue-unit.scala:81:13] wire [4:0] _mem_iss_unit_io_iss_uops_1_bits_ppred; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_prs1_busy; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_prs2_busy; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_prs3_busy; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_ppred_busy; // @[issue-unit.scala:81:13] wire [6:0] _mem_iss_unit_io_iss_uops_1_bits_stale_pdst; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_exception; // @[issue-unit.scala:81:13] wire [63:0] _mem_iss_unit_io_iss_uops_1_bits_exc_cause; // @[issue-unit.scala:81:13] wire [4:0] _mem_iss_unit_io_iss_uops_1_bits_mem_cmd; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_1_bits_mem_size; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_mem_signed; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_uses_ldq; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_uses_stq; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_is_unique; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_flush_on_commit; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_1_bits_csr_cmd; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_ldst_is_rs1; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_1_bits_ldst; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_1_bits_lrs1; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_1_bits_lrs2; // @[issue-unit.scala:81:13] wire [5:0] _mem_iss_unit_io_iss_uops_1_bits_lrs3; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_1_bits_dst_rtype; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_1_bits_lrs1_rtype; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_frs3_en; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fcn_dw; // @[issue-unit.scala:81:13] wire [4:0] _mem_iss_unit_io_iss_uops_1_bits_fcn_op; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_fp_val; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_1_bits_fp_rm; // @[issue-unit.scala:81:13] wire [1:0] _mem_iss_unit_io_iss_uops_1_bits_fp_typ; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_xcpt_pf_if; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_xcpt_ae_if; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_xcpt_ma_if; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_bp_debug_if; // @[issue-unit.scala:81:13] wire _mem_iss_unit_io_iss_uops_1_bits_bp_xcpt_if; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_1_bits_debug_fsrc; // @[issue-unit.scala:81:13] wire [2:0] _mem_iss_unit_io_iss_uops_1_bits_debug_tsrc; // @[issue-unit.scala:81:13] wire _imm_rename_stage_io_ren_stalls_0; // @[core.scala:119:33] wire _imm_rename_stage_io_ren_stalls_1; // @[core.scala:119:33] wire [6:0] _pred_rename_stage_io_ren2_uops_0_pdst; // @[core.scala:118:33] wire _pred_rename_stage_io_ren2_uops_0_ppred_busy; // @[core.scala:118:33] wire [6:0] _pred_rename_stage_io_ren2_uops_1_pdst; // @[core.scala:118:33] wire _pred_rename_stage_io_ren2_uops_1_ppred_busy; // @[core.scala:118:33] wire _fp_rename_stage_io_ren_stalls_0; // @[core.scala:117:33] wire _fp_rename_stage_io_ren_stalls_1; // @[core.scala:117:33] wire [6:0] _fp_rename_stage_io_ren2_uops_0_pdst; // @[core.scala:117:33] wire [6:0] _fp_rename_stage_io_ren2_uops_0_prs1; // @[core.scala:117:33] wire [6:0] _fp_rename_stage_io_ren2_uops_0_prs2; // @[core.scala:117:33] wire _fp_rename_stage_io_ren2_uops_0_prs1_busy; // @[core.scala:117:33] wire _fp_rename_stage_io_ren2_uops_0_prs2_busy; // @[core.scala:117:33] wire _fp_rename_stage_io_ren2_uops_0_prs3_busy; // @[core.scala:117:33] wire [6:0] _fp_rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:117:33] wire [6:0] _fp_rename_stage_io_ren2_uops_1_pdst; // @[core.scala:117:33] wire [6:0] _fp_rename_stage_io_ren2_uops_1_prs1; // @[core.scala:117:33] wire [6:0] _fp_rename_stage_io_ren2_uops_1_prs2; // @[core.scala:117:33] wire _fp_rename_stage_io_ren2_uops_1_prs1_busy; // @[core.scala:117:33] wire _fp_rename_stage_io_ren2_uops_1_prs2_busy; // @[core.scala:117:33] wire _fp_rename_stage_io_ren2_uops_1_prs3_busy; // @[core.scala:117:33] wire [6:0] _fp_rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:117:33] wire _rename_stage_io_ren_stalls_0; // @[core.scala:116:33] wire _rename_stage_io_ren_stalls_1; // @[core.scala:116:33] wire [6:0] _rename_stage_io_ren2_uops_0_pdst; // @[core.scala:116:33] wire [6:0] _rename_stage_io_ren2_uops_0_prs1; // @[core.scala:116:33] wire [6:0] _rename_stage_io_ren2_uops_0_prs2; // @[core.scala:116:33] wire _rename_stage_io_ren2_uops_0_prs1_busy; // @[core.scala:116:33] wire _rename_stage_io_ren2_uops_0_prs2_busy; // @[core.scala:116:33] wire [6:0] _rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:116:33] wire [6:0] _rename_stage_io_ren2_uops_1_pdst; // @[core.scala:116:33] wire [6:0] _rename_stage_io_ren2_uops_1_prs1; // @[core.scala:116:33] wire [6:0] _rename_stage_io_ren2_uops_1_prs2; // @[core.scala:116:33] wire _rename_stage_io_ren2_uops_1_prs1_busy; // @[core.scala:116:33] wire _rename_stage_io_ren2_uops_1_prs2_busy; // @[core.scala:116:33] wire [6:0] _rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:116:33] wire [31:0] _decode_1_io_csr_decode_inst; // @[core.scala:114:66] wire [31:0] _decode_0_io_csr_decode_inst; // @[core.scala:114:66] wire _fp_pipeline_io_dis_uops_0_ready; // @[core.scala:99:27] wire _fp_pipeline_io_dis_uops_1_ready; // @[core.scala:99:27] wire _fp_pipeline_io_from_int_ready; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_valid; // @[core.scala:99:27] wire [31:0] _fp_pipeline_io_to_int_bits_uop_inst; // @[core.scala:99:27] wire [31:0] _fp_pipeline_io_to_int_bits_uop_debug_inst; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_is_rvc; // @[core.scala:99:27] wire [39:0] _fp_pipeline_io_to_int_bits_uop_debug_pc; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_iq_type_0; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_iq_type_1; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_iq_type_2; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_iq_type_3; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fu_code_0; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fu_code_1; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fu_code_2; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fu_code_3; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fu_code_4; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fu_code_5; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fu_code_6; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fu_code_7; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fu_code_8; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fu_code_9; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_iw_issued; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_iw_issued_partial_agen; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_iw_issued_partial_dgen; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_iw_p1_speculative_child; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_iw_p2_speculative_child; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_iw_p1_bypass_hint; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_iw_p2_bypass_hint; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_iw_p3_bypass_hint; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_dis_col_sel; // @[core.scala:99:27] wire [11:0] _fp_pipeline_io_to_int_bits_uop_br_mask; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_to_int_bits_uop_br_tag; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_to_int_bits_uop_br_type; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_is_sfb; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_is_fence; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_is_fencei; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_is_sfence; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_is_amo; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_is_eret; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_is_sys_pc2epc; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_is_rocc; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_is_mov; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_to_int_bits_uop_ftq_idx; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_edge_inst; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_to_int_bits_uop_pc_lob; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_taken; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_imm_rename; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_to_int_bits_uop_imm_sel; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_to_int_bits_uop_pimm; // @[core.scala:99:27] wire [19:0] _fp_pipeline_io_to_int_bits_uop_imm_packed; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_op1_sel; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_to_int_bits_uop_op2_sel; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_ldst; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_wen; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_ren1; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_ren2; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_ren3; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_swap12; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_swap23; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_fromint; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_toint; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_fastpipe; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_fma; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_div; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_sqrt; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_wflags; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_ctrl_vec; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_to_int_bits_uop_rob_idx; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_to_int_bits_uop_ldq_idx; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_to_int_bits_uop_stq_idx; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_rxq_idx; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_to_int_bits_uop_pdst; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_to_int_bits_uop_prs1; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_to_int_bits_uop_prs2; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_to_int_bits_uop_prs3; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_to_int_bits_uop_ppred; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_prs1_busy; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_prs2_busy; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_prs3_busy; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_ppred_busy; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_to_int_bits_uop_stale_pdst; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_exception; // @[core.scala:99:27] wire [63:0] _fp_pipeline_io_to_int_bits_uop_exc_cause; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_to_int_bits_uop_mem_cmd; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_mem_size; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_mem_signed; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_uses_ldq; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_uses_stq; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_is_unique; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_flush_on_commit; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_to_int_bits_uop_csr_cmd; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_ldst_is_rs1; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_to_int_bits_uop_ldst; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_to_int_bits_uop_lrs1; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_to_int_bits_uop_lrs2; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_to_int_bits_uop_lrs3; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_dst_rtype; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_lrs1_rtype; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_lrs2_rtype; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_frs3_en; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fcn_dw; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_to_int_bits_uop_fcn_op; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_fp_val; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_to_int_bits_uop_fp_rm; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_to_int_bits_uop_fp_typ; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_xcpt_pf_if; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_xcpt_ae_if; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_xcpt_ma_if; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_bp_debug_if; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_uop_bp_xcpt_if; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_to_int_bits_uop_debug_fsrc; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_to_int_bits_uop_debug_tsrc; // @[core.scala:99:27] wire [63:0] _fp_pipeline_io_to_int_bits_data; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_predicated; // @[core.scala:99:27] wire _fp_pipeline_io_to_int_bits_fflags_valid; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_to_int_bits_fflags_bits; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_valid; // @[core.scala:99:27] wire [31:0] _fp_pipeline_io_wakeups_0_bits_uop_inst; // @[core.scala:99:27] wire [31:0] _fp_pipeline_io_wakeups_0_bits_uop_debug_inst; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_is_rvc; // @[core.scala:99:27] wire [39:0] _fp_pipeline_io_wakeups_0_bits_uop_debug_pc; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_iq_type_0; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_iq_type_1; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_iq_type_2; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_iq_type_3; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fu_code_0; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fu_code_1; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fu_code_2; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fu_code_3; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fu_code_4; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fu_code_5; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fu_code_6; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fu_code_7; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fu_code_8; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fu_code_9; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_iw_issued; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_iw_issued_partial_agen; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_iw_p1_speculative_child; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_iw_p2_speculative_child; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_dis_col_sel; // @[core.scala:99:27] wire [11:0] _fp_pipeline_io_wakeups_0_bits_uop_br_mask; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wakeups_0_bits_uop_br_tag; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wakeups_0_bits_uop_br_type; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_is_sfb; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_is_fence; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_is_fencei; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_is_sfence; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_is_amo; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_is_eret; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_is_rocc; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_is_mov; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wakeups_0_bits_uop_ftq_idx; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_edge_inst; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_0_bits_uop_pc_lob; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_taken; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_imm_rename; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_0_bits_uop_imm_sel; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wakeups_0_bits_uop_pimm; // @[core.scala:99:27] wire [19:0] _fp_pipeline_io_wakeups_0_bits_uop_imm_packed; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_op1_sel; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_0_bits_uop_op2_sel; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_ldst; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_wen; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_ren1; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_ren2; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_ren3; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_swap12; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_swap23; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_fromint; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_toint; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_fma; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_div; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_wflags; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_ctrl_vec; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_0_bits_uop_rob_idx; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wakeups_0_bits_uop_ldq_idx; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wakeups_0_bits_uop_stq_idx; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_rxq_idx; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wakeups_0_bits_uop_pdst; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wakeups_0_bits_uop_prs1; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wakeups_0_bits_uop_prs2; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wakeups_0_bits_uop_prs3; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wakeups_0_bits_uop_ppred; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_prs1_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_prs2_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_prs3_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_ppred_busy; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wakeups_0_bits_uop_stale_pdst; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_exception; // @[core.scala:99:27] wire [63:0] _fp_pipeline_io_wakeups_0_bits_uop_exc_cause; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wakeups_0_bits_uop_mem_cmd; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_mem_size; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_mem_signed; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_uses_ldq; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_uses_stq; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_is_unique; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_0_bits_uop_csr_cmd; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_0_bits_uop_ldst; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_0_bits_uop_lrs1; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_0_bits_uop_lrs2; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_0_bits_uop_lrs3; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_dst_rtype; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_frs3_en; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fcn_dw; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wakeups_0_bits_uop_fcn_op; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_fp_val; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_0_bits_uop_fp_rm; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_0_bits_uop_fp_typ; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_valid; // @[core.scala:99:27] wire [31:0] _fp_pipeline_io_wakeups_1_bits_uop_inst; // @[core.scala:99:27] wire [31:0] _fp_pipeline_io_wakeups_1_bits_uop_debug_inst; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_is_rvc; // @[core.scala:99:27] wire [39:0] _fp_pipeline_io_wakeups_1_bits_uop_debug_pc; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_iq_type_0; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_iq_type_1; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_iq_type_2; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_iq_type_3; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fu_code_0; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fu_code_1; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fu_code_2; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fu_code_3; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fu_code_4; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fu_code_5; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fu_code_6; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fu_code_7; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fu_code_8; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fu_code_9; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_iw_issued; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_iw_issued_partial_agen; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_iw_issued_partial_dgen; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_iw_p1_speculative_child; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_iw_p2_speculative_child; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_iw_p1_bypass_hint; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_iw_p2_bypass_hint; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_iw_p3_bypass_hint; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_dis_col_sel; // @[core.scala:99:27] wire [11:0] _fp_pipeline_io_wakeups_1_bits_uop_br_mask; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wakeups_1_bits_uop_br_tag; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wakeups_1_bits_uop_br_type; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_is_sfb; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_is_fence; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_is_fencei; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_is_sfence; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_is_amo; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_is_eret; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_is_rocc; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_is_mov; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wakeups_1_bits_uop_ftq_idx; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_edge_inst; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_1_bits_uop_pc_lob; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_taken; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_imm_rename; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_1_bits_uop_imm_sel; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wakeups_1_bits_uop_pimm; // @[core.scala:99:27] wire [19:0] _fp_pipeline_io_wakeups_1_bits_uop_imm_packed; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_op1_sel; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_1_bits_uop_op2_sel; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_ldst; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_wen; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_ren1; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_ren2; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_ren3; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_swap12; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_swap23; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_fromint; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_toint; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_fma; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_div; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_sqrt; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_wflags; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_ctrl_vec; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_1_bits_uop_rob_idx; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wakeups_1_bits_uop_ldq_idx; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wakeups_1_bits_uop_stq_idx; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_rxq_idx; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wakeups_1_bits_uop_pdst; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wakeups_1_bits_uop_prs1; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wakeups_1_bits_uop_prs2; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wakeups_1_bits_uop_prs3; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wakeups_1_bits_uop_ppred; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_prs1_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_prs2_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_prs3_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_ppred_busy; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wakeups_1_bits_uop_stale_pdst; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_exception; // @[core.scala:99:27] wire [63:0] _fp_pipeline_io_wakeups_1_bits_uop_exc_cause; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wakeups_1_bits_uop_mem_cmd; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_mem_size; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_mem_signed; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_uses_ldq; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_uses_stq; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_is_unique; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_1_bits_uop_csr_cmd; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_1_bits_uop_ldst; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_1_bits_uop_lrs1; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_1_bits_uop_lrs2; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wakeups_1_bits_uop_lrs3; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_dst_rtype; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_frs3_en; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fcn_dw; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wakeups_1_bits_uop_fcn_op; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_fp_val; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_1_bits_uop_fp_rm; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wakeups_1_bits_uop_fp_typ; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:99:27] wire _fp_pipeline_io_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_valid; // @[core.scala:99:27] wire [31:0] _fp_pipeline_io_wb_0_bits_uop_inst; // @[core.scala:99:27] wire [31:0] _fp_pipeline_io_wb_0_bits_uop_debug_inst; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_is_rvc; // @[core.scala:99:27] wire [39:0] _fp_pipeline_io_wb_0_bits_uop_debug_pc; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_iq_type_0; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_iq_type_1; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_iq_type_2; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_iq_type_3; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fu_code_0; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fu_code_1; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fu_code_2; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fu_code_3; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fu_code_4; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fu_code_5; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fu_code_6; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fu_code_7; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fu_code_8; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fu_code_9; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_iw_issued; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_iw_issued_partial_agen; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_iw_issued_partial_dgen; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_iw_p1_speculative_child; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_iw_p2_speculative_child; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_iw_p1_bypass_hint; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_iw_p2_bypass_hint; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_iw_p3_bypass_hint; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_dis_col_sel; // @[core.scala:99:27] wire [11:0] _fp_pipeline_io_wb_0_bits_uop_br_mask; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wb_0_bits_uop_br_tag; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wb_0_bits_uop_br_type; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_is_sfb; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_is_fence; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_is_fencei; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_is_sfence; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_is_amo; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_is_eret; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_is_sys_pc2epc; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_is_rocc; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_is_mov; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_0_bits_uop_ftq_idx; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_edge_inst; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_0_bits_uop_pc_lob; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_taken; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_imm_rename; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_0_bits_uop_imm_sel; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_0_bits_uop_pimm; // @[core.scala:99:27] wire [19:0] _fp_pipeline_io_wb_0_bits_uop_imm_packed; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_op1_sel; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_0_bits_uop_op2_sel; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_ldst; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_wen; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_ren1; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_ren2; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_ren3; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_swap12; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_swap23; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_fromint; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_toint; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_fastpipe; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_fma; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_div; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_sqrt; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_wflags; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_ctrl_vec; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_0_bits_uop_rob_idx; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wb_0_bits_uop_ldq_idx; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wb_0_bits_uop_stq_idx; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_rxq_idx; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wb_0_bits_uop_pdst; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wb_0_bits_uop_prs1; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wb_0_bits_uop_prs2; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wb_0_bits_uop_prs3; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_0_bits_uop_ppred; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_prs1_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_prs2_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_prs3_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_ppred_busy; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wb_0_bits_uop_stale_pdst; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_exception; // @[core.scala:99:27] wire [63:0] _fp_pipeline_io_wb_0_bits_uop_exc_cause; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_0_bits_uop_mem_cmd; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_mem_size; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_mem_signed; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_uses_ldq; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_uses_stq; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_is_unique; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_flush_on_commit; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_0_bits_uop_csr_cmd; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_ldst_is_rs1; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_0_bits_uop_ldst; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_0_bits_uop_lrs1; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_0_bits_uop_lrs2; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_0_bits_uop_lrs3; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_dst_rtype; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_lrs1_rtype; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_lrs2_rtype; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_frs3_en; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fcn_dw; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_0_bits_uop_fcn_op; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_fp_val; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_0_bits_uop_fp_rm; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_0_bits_uop_fp_typ; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_xcpt_pf_if; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_xcpt_ae_if; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_xcpt_ma_if; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_bp_debug_if; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_uop_bp_xcpt_if; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_0_bits_uop_debug_fsrc; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_0_bits_uop_debug_tsrc; // @[core.scala:99:27] wire [64:0] _fp_pipeline_io_wb_0_bits_data; // @[core.scala:99:27] wire _fp_pipeline_io_wb_0_bits_fflags_valid; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_0_bits_fflags_bits; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_valid; // @[core.scala:99:27] wire [31:0] _fp_pipeline_io_wb_1_bits_uop_inst; // @[core.scala:99:27] wire [31:0] _fp_pipeline_io_wb_1_bits_uop_debug_inst; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_is_rvc; // @[core.scala:99:27] wire [39:0] _fp_pipeline_io_wb_1_bits_uop_debug_pc; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_iq_type_0; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_iq_type_1; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_iq_type_2; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_iq_type_3; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fu_code_0; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fu_code_1; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fu_code_2; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fu_code_3; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fu_code_4; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fu_code_5; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fu_code_6; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fu_code_7; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fu_code_8; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fu_code_9; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_iw_issued; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_iw_issued_partial_agen; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_iw_issued_partial_dgen; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_iw_p1_speculative_child; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_iw_p2_speculative_child; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_iw_p1_bypass_hint; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_iw_p2_bypass_hint; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_iw_p3_bypass_hint; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_dis_col_sel; // @[core.scala:99:27] wire [11:0] _fp_pipeline_io_wb_1_bits_uop_br_mask; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wb_1_bits_uop_br_tag; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wb_1_bits_uop_br_type; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_is_sfb; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_is_fence; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_is_fencei; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_is_sfence; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_is_amo; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_is_eret; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_is_sys_pc2epc; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_is_rocc; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_is_mov; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_1_bits_uop_ftq_idx; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_edge_inst; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_1_bits_uop_pc_lob; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_taken; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_imm_rename; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_1_bits_uop_imm_sel; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_1_bits_uop_pimm; // @[core.scala:99:27] wire [19:0] _fp_pipeline_io_wb_1_bits_uop_imm_packed; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_op1_sel; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_1_bits_uop_op2_sel; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_ldst; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_wen; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_ren1; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_ren2; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_ren3; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_swap12; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_swap23; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_fromint; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_toint; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_fastpipe; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_fma; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_div; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_sqrt; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_wflags; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_ctrl_vec; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_1_bits_uop_rob_idx; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wb_1_bits_uop_ldq_idx; // @[core.scala:99:27] wire [3:0] _fp_pipeline_io_wb_1_bits_uop_stq_idx; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_rxq_idx; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wb_1_bits_uop_pdst; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wb_1_bits_uop_prs1; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wb_1_bits_uop_prs2; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wb_1_bits_uop_prs3; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_1_bits_uop_ppred; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_prs1_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_prs2_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_prs3_busy; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_ppred_busy; // @[core.scala:99:27] wire [6:0] _fp_pipeline_io_wb_1_bits_uop_stale_pdst; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_exception; // @[core.scala:99:27] wire [63:0] _fp_pipeline_io_wb_1_bits_uop_exc_cause; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_1_bits_uop_mem_cmd; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_mem_size; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_mem_signed; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_uses_ldq; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_uses_stq; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_is_unique; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_flush_on_commit; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_1_bits_uop_csr_cmd; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_ldst_is_rs1; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_1_bits_uop_ldst; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_1_bits_uop_lrs1; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_1_bits_uop_lrs2; // @[core.scala:99:27] wire [5:0] _fp_pipeline_io_wb_1_bits_uop_lrs3; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_dst_rtype; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_lrs1_rtype; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_lrs2_rtype; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_frs3_en; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fcn_dw; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_1_bits_uop_fcn_op; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_fp_val; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_1_bits_uop_fp_rm; // @[core.scala:99:27] wire [1:0] _fp_pipeline_io_wb_1_bits_uop_fp_typ; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_xcpt_pf_if; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_xcpt_ae_if; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_xcpt_ma_if; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_bp_debug_if; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_uop_bp_xcpt_if; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_1_bits_uop_debug_fsrc; // @[core.scala:99:27] wire [2:0] _fp_pipeline_io_wb_1_bits_uop_debug_tsrc; // @[core.scala:99:27] wire [64:0] _fp_pipeline_io_wb_1_bits_data; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_predicated; // @[core.scala:99:27] wire _fp_pipeline_io_wb_1_bits_fflags_valid; // @[core.scala:99:27] wire [4:0] _fp_pipeline_io_wb_1_bits_fflags_bits; // @[core.scala:99:27] wire _alu_exe_unit_1_io_arb_irf_reqs_0_valid; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_arb_irf_reqs_0_bits; // @[core.scala:92:11] wire _alu_exe_unit_1_io_arb_irf_reqs_1_valid; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_arb_irf_reqs_1_bits; // @[core.scala:92:11] wire _alu_exe_unit_1_io_arb_prf_req_valid; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_arb_prf_req_bits; // @[core.scala:92:11] wire _alu_exe_unit_1_io_arb_immrf_req_valid; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_arb_immrf_req_bits; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_valid; // @[core.scala:92:11] wire [31:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_inst; // @[core.scala:92:11] wire [31:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_debug_inst; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_rvc; // @[core.scala:92:11] wire [39:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_debug_pc; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iq_type_0; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iq_type_1; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iq_type_2; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iq_type_3; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_0; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_1; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_2; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_3; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_4; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_5; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_6; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_7; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_8; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_9; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_issued; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_agen; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_dgen; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_p1_speculative_child; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_p2_speculative_child; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_p1_bypass_hint; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_p2_bypass_hint; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_p3_bypass_hint; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_dis_col_sel; // @[core.scala:92:11] wire [11:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_br_mask; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_br_tag; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_br_type; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_sfb; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_fence; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_fencei; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_sfence; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_amo; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_eret; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_rocc; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_mov; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ftq_idx; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_edge_inst; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_pc_lob; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_taken; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_imm_rename; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_imm_sel; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_pimm; // @[core.scala:92:11] wire [19:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_imm_packed; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_op1_sel; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_op2_sel; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ldst; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wen; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren1; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren2; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren3; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap12; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap23; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fromint; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_toint; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fastpipe; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fma; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_div; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_sqrt; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wflags; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_vec; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_rob_idx; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ldq_idx; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_stq_idx; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_rxq_idx; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_pdst; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs1; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs2; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs3; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ppred; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs1_busy; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs2_busy; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs3_busy; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ppred_busy; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_stale_pdst; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_exception; // @[core.scala:92:11] wire [63:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_exc_cause; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_mem_cmd; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_mem_size; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_mem_signed; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_uses_ldq; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_uses_stq; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_unique; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_flush_on_commit; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_csr_cmd; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ldst; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_lrs1; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_lrs2; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_lrs3; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_dst_rtype; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_lrs1_rtype; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_lrs2_rtype; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_frs3_en; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fcn_dw; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fcn_op; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_val; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_rm; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_typ; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_bp_debug_if; // @[core.scala:92:11] wire _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_debug_fsrc; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_debug_tsrc; // @[core.scala:92:11] wire _alu_exe_unit_1_io_arb_brf_req_valid; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_1_io_arb_brf_req_bits; // @[core.scala:92:11] wire _alu_exe_unit_1_io_arb_ftq_reqs_0_valid; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_arb_ftq_reqs_0_bits; // @[core.scala:92:11] wire _alu_exe_unit_1_io_arb_ftq_reqs_1_valid; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_arb_ftq_reqs_1_bits; // @[core.scala:92:11] wire _alu_exe_unit_1_io_squash_iss; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_child_rebusy; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_valid; // @[core.scala:92:11] wire [31:0] _alu_exe_unit_1_io_alu_resp_bits_uop_inst; // @[core.scala:92:11] wire [31:0] _alu_exe_unit_1_io_alu_resp_bits_uop_debug_inst; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_is_rvc; // @[core.scala:92:11] wire [39:0] _alu_exe_unit_1_io_alu_resp_bits_uop_debug_pc; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_iq_type_0; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_iq_type_1; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_iq_type_2; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_iq_type_3; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fu_code_0; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fu_code_1; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fu_code_2; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fu_code_3; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fu_code_4; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fu_code_5; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fu_code_6; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fu_code_7; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fu_code_8; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fu_code_9; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_iw_issued; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_iw_issued_partial_agen; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_iw_issued_partial_dgen; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_iw_p1_speculative_child; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_iw_p2_speculative_child; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_iw_p1_bypass_hint; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_iw_p2_bypass_hint; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_iw_p3_bypass_hint; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_dis_col_sel; // @[core.scala:92:11] wire [11:0] _alu_exe_unit_1_io_alu_resp_bits_uop_br_mask; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_1_io_alu_resp_bits_uop_br_tag; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_1_io_alu_resp_bits_uop_br_type; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_is_sfb; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_is_fence; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_is_fencei; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_is_sfence; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_is_amo; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_is_eret; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_is_sys_pc2epc; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_is_rocc; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_is_mov; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_alu_resp_bits_uop_ftq_idx; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_edge_inst; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_alu_resp_bits_uop_pc_lob; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_taken; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_imm_rename; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_alu_resp_bits_uop_imm_sel; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_alu_resp_bits_uop_pimm; // @[core.scala:92:11] wire [19:0] _alu_exe_unit_1_io_alu_resp_bits_uop_imm_packed; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_op1_sel; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_alu_resp_bits_uop_op2_sel; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_ldst; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_wen; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_ren1; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_ren2; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_ren3; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_swap12; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_swap23; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_fromint; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_toint; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_fastpipe; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_fma; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_div; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_sqrt; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_wflags; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_ctrl_vec; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_alu_resp_bits_uop_rob_idx; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_1_io_alu_resp_bits_uop_ldq_idx; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_1_io_alu_resp_bits_uop_stq_idx; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_rxq_idx; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_alu_resp_bits_uop_pdst; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_alu_resp_bits_uop_prs1; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_alu_resp_bits_uop_prs2; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_alu_resp_bits_uop_prs3; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_alu_resp_bits_uop_ppred; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_prs1_busy; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_prs2_busy; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_prs3_busy; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_ppred_busy; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_1_io_alu_resp_bits_uop_stale_pdst; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_exception; // @[core.scala:92:11] wire [63:0] _alu_exe_unit_1_io_alu_resp_bits_uop_exc_cause; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_alu_resp_bits_uop_mem_cmd; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_mem_size; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_mem_signed; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_uses_ldq; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_uses_stq; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_is_unique; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_flush_on_commit; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_alu_resp_bits_uop_csr_cmd; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_ldst_is_rs1; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_alu_resp_bits_uop_ldst; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_alu_resp_bits_uop_lrs1; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_alu_resp_bits_uop_lrs2; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_1_io_alu_resp_bits_uop_lrs3; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_dst_rtype; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_lrs1_rtype; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_lrs2_rtype; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_frs3_en; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fcn_dw; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_1_io_alu_resp_bits_uop_fcn_op; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_fp_val; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_alu_resp_bits_uop_fp_rm; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_1_io_alu_resp_bits_uop_fp_typ; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_xcpt_pf_if; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_xcpt_ae_if; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_xcpt_ma_if; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_bp_debug_if; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_uop_bp_xcpt_if; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_alu_resp_bits_uop_debug_fsrc; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_1_io_alu_resp_bits_uop_debug_tsrc; // @[core.scala:92:11] wire [63:0] _alu_exe_unit_1_io_alu_resp_bits_data; // @[core.scala:92:11] wire _alu_exe_unit_1_io_alu_resp_bits_predicated; // @[core.scala:92:11] wire _alu_exe_unit_1_io_brinfo_valid; // @[core.scala:92:11] wire [11:0] _alu_exe_unit_1_io_brinfo_bits_uop_br_mask; // @[core.scala:92:11] wire _alu_exe_unit_0_io_arb_irf_reqs_0_valid; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_arb_irf_reqs_0_bits; // @[core.scala:92:11] wire _alu_exe_unit_0_io_arb_irf_reqs_1_valid; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_arb_irf_reqs_1_bits; // @[core.scala:92:11] wire _alu_exe_unit_0_io_arb_prf_req_valid; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_arb_prf_req_bits; // @[core.scala:92:11] wire _alu_exe_unit_0_io_arb_immrf_req_valid; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_arb_immrf_req_bits; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_valid; // @[core.scala:92:11] wire [31:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_inst; // @[core.scala:92:11] wire [31:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_inst; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_rvc; // @[core.scala:92:11] wire [39:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_pc; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_0; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_1; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_2; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_3; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_0; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_1; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_2; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_3; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_4; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_5; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_6; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_7; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_8; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_9; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_issued; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_agen; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_dgen; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p1_speculative_child; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p2_speculative_child; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p1_bypass_hint; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p2_bypass_hint; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p3_bypass_hint; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_dis_col_sel; // @[core.scala:92:11] wire [11:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_br_mask; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_br_tag; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_br_type; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_sfb; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_fence; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_fencei; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_sfence; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_amo; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_eret; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_rocc; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_mov; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ftq_idx; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_edge_inst; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_pc_lob; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_taken; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_imm_rename; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_imm_sel; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_pimm; // @[core.scala:92:11] wire [19:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_imm_packed; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_op1_sel; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_op2_sel; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ldst; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wen; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren1; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren2; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren3; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap12; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap23; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fromint; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_toint; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fastpipe; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fma; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_div; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_sqrt; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wflags; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_vec; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_rob_idx; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ldq_idx; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_stq_idx; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_rxq_idx; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_pdst; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs1; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs2; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs3; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ppred; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs1_busy; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs2_busy; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs3_busy; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ppred_busy; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_stale_pdst; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_exception; // @[core.scala:92:11] wire [63:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_exc_cause; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_mem_cmd; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_mem_size; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_mem_signed; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_uses_ldq; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_uses_stq; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_unique; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_flush_on_commit; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_csr_cmd; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ldst; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs1; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs2; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs3; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_dst_rtype; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs1_rtype; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs2_rtype; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_frs3_en; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fcn_dw; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fcn_op; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_val; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_rm; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_typ; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_bp_debug_if; // @[core.scala:92:11] wire _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_fsrc; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_tsrc; // @[core.scala:92:11] wire _alu_exe_unit_0_io_arb_brf_req_valid; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_0_io_arb_brf_req_bits; // @[core.scala:92:11] wire _alu_exe_unit_0_io_arb_ftq_reqs_0_valid; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_arb_ftq_reqs_0_bits; // @[core.scala:92:11] wire _alu_exe_unit_0_io_arb_ftq_reqs_1_valid; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_arb_ftq_reqs_1_bits; // @[core.scala:92:11] wire _alu_exe_unit_0_io_squash_iss; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_child_rebusy; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_valid; // @[core.scala:92:11] wire [31:0] _alu_exe_unit_0_io_alu_resp_bits_uop_inst; // @[core.scala:92:11] wire [31:0] _alu_exe_unit_0_io_alu_resp_bits_uop_debug_inst; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_is_rvc; // @[core.scala:92:11] wire [39:0] _alu_exe_unit_0_io_alu_resp_bits_uop_debug_pc; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_iq_type_0; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_iq_type_1; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_iq_type_2; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_iq_type_3; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fu_code_0; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fu_code_1; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fu_code_2; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fu_code_3; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fu_code_4; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fu_code_5; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fu_code_6; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fu_code_7; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fu_code_8; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fu_code_9; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_iw_issued; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_iw_issued_partial_agen; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_iw_issued_partial_dgen; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_iw_p1_speculative_child; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_iw_p2_speculative_child; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_iw_p1_bypass_hint; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_iw_p2_bypass_hint; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_iw_p3_bypass_hint; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_dis_col_sel; // @[core.scala:92:11] wire [11:0] _alu_exe_unit_0_io_alu_resp_bits_uop_br_mask; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_0_io_alu_resp_bits_uop_br_tag; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_0_io_alu_resp_bits_uop_br_type; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_is_sfb; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_is_fence; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_is_fencei; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_is_sfence; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_is_amo; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_is_eret; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_is_sys_pc2epc; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_is_rocc; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_is_mov; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_alu_resp_bits_uop_ftq_idx; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_edge_inst; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_alu_resp_bits_uop_pc_lob; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_taken; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_imm_rename; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_alu_resp_bits_uop_imm_sel; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_alu_resp_bits_uop_pimm; // @[core.scala:92:11] wire [19:0] _alu_exe_unit_0_io_alu_resp_bits_uop_imm_packed; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_op1_sel; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_alu_resp_bits_uop_op2_sel; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_ldst; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_wen; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_ren1; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_ren2; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_ren3; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_swap12; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_swap23; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_fromint; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_toint; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_fastpipe; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_fma; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_div; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_sqrt; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_wflags; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_ctrl_vec; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_alu_resp_bits_uop_rob_idx; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_0_io_alu_resp_bits_uop_ldq_idx; // @[core.scala:92:11] wire [3:0] _alu_exe_unit_0_io_alu_resp_bits_uop_stq_idx; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_rxq_idx; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_alu_resp_bits_uop_pdst; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_alu_resp_bits_uop_prs1; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_alu_resp_bits_uop_prs2; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_alu_resp_bits_uop_prs3; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_alu_resp_bits_uop_ppred; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_prs1_busy; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_prs2_busy; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_prs3_busy; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_ppred_busy; // @[core.scala:92:11] wire [6:0] _alu_exe_unit_0_io_alu_resp_bits_uop_stale_pdst; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_exception; // @[core.scala:92:11] wire [63:0] _alu_exe_unit_0_io_alu_resp_bits_uop_exc_cause; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_alu_resp_bits_uop_mem_cmd; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_mem_size; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_mem_signed; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_uses_ldq; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_uses_stq; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_is_unique; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_flush_on_commit; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_alu_resp_bits_uop_csr_cmd; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_ldst_is_rs1; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_alu_resp_bits_uop_ldst; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_alu_resp_bits_uop_lrs1; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_alu_resp_bits_uop_lrs2; // @[core.scala:92:11] wire [5:0] _alu_exe_unit_0_io_alu_resp_bits_uop_lrs3; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_dst_rtype; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_lrs1_rtype; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_lrs2_rtype; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_frs3_en; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fcn_dw; // @[core.scala:92:11] wire [4:0] _alu_exe_unit_0_io_alu_resp_bits_uop_fcn_op; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_fp_val; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_alu_resp_bits_uop_fp_rm; // @[core.scala:92:11] wire [1:0] _alu_exe_unit_0_io_alu_resp_bits_uop_fp_typ; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_xcpt_pf_if; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_xcpt_ae_if; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_xcpt_ma_if; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_bp_debug_if; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_uop_bp_xcpt_if; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_alu_resp_bits_uop_debug_fsrc; // @[core.scala:92:11] wire [2:0] _alu_exe_unit_0_io_alu_resp_bits_uop_debug_tsrc; // @[core.scala:92:11] wire [63:0] _alu_exe_unit_0_io_alu_resp_bits_data; // @[core.scala:92:11] wire _alu_exe_unit_0_io_alu_resp_bits_predicated; // @[core.scala:92:11] wire _alu_exe_unit_0_io_brinfo_valid; // @[core.scala:92:11] wire [11:0] _alu_exe_unit_0_io_brinfo_bits_uop_br_mask; // @[core.scala:92:11] wire _unique_exe_unit_0_io_ready_fu_types_4; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ready_fu_types_8; // @[core.scala:81:11] wire _unique_exe_unit_0_io_arb_irf_reqs_0_valid; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_arb_irf_reqs_0_bits; // @[core.scala:81:11] wire _unique_exe_unit_0_io_arb_irf_reqs_1_valid; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_arb_irf_reqs_1_bits; // @[core.scala:81:11] wire _unique_exe_unit_0_io_arb_immrf_req_valid; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_arb_immrf_req_bits; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_valid; // @[core.scala:81:11] wire [31:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_inst; // @[core.scala:81:11] wire [31:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_inst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_rvc; // @[core.scala:81:11] wire [39:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_pc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_0; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_0; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_4; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_5; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_6; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_7; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_8; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_9; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_issued; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_agen; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_dgen; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p1_speculative_child; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p2_speculative_child; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p1_bypass_hint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p2_bypass_hint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p3_bypass_hint; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_dis_col_sel; // @[core.scala:81:11] wire [11:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_br_mask; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_br_tag; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_br_type; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_sfb; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_fence; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_fencei; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_sfence; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_amo; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_eret; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_rocc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_mov; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ftq_idx; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_edge_inst; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_pc_lob; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_taken; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_imm_rename; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_imm_sel; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_pimm; // @[core.scala:81:11] wire [19:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_imm_packed; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_op1_sel; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_op2_sel; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ldst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wen; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap12; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap23; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fromint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_toint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fastpipe; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fma; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_div; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_sqrt; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wflags; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_vec; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_rob_idx; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ldq_idx; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_stq_idx; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_rxq_idx; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_pdst; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs1; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs2; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs3; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ppred; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs1_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs2_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs3_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ppred_busy; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_stale_pdst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_exception; // @[core.scala:81:11] wire [63:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_exc_cause; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_mem_cmd; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_mem_size; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_mem_signed; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_uses_ldq; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_uses_stq; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_unique; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_flush_on_commit; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_csr_cmd; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ldst; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs1; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs2; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs3; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_dst_rtype; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs1_rtype; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs2_rtype; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_frs3_en; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fcn_dw; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fcn_op; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_val; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_rm; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_typ; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_bp_debug_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_fsrc; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_tsrc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_squash_iss; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_valid; // @[core.scala:81:11] wire [31:0] _unique_exe_unit_0_io_mul_resp_bits_uop_inst; // @[core.scala:81:11] wire [31:0] _unique_exe_unit_0_io_mul_resp_bits_uop_debug_inst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_is_rvc; // @[core.scala:81:11] wire [39:0] _unique_exe_unit_0_io_mul_resp_bits_uop_debug_pc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_iq_type_0; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_iq_type_1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_iq_type_2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_iq_type_3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fu_code_0; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fu_code_1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fu_code_2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fu_code_3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fu_code_4; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fu_code_5; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fu_code_6; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fu_code_7; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fu_code_8; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fu_code_9; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_iw_issued; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_iw_issued_partial_agen; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_iw_issued_partial_dgen; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_iw_p1_speculative_child; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_iw_p2_speculative_child; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_iw_p1_bypass_hint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_iw_p2_bypass_hint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_iw_p3_bypass_hint; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_dis_col_sel; // @[core.scala:81:11] wire [11:0] _unique_exe_unit_0_io_mul_resp_bits_uop_br_mask; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_mul_resp_bits_uop_br_tag; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_mul_resp_bits_uop_br_type; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_is_sfb; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_is_fence; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_is_fencei; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_is_sfence; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_is_amo; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_is_eret; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_is_sys_pc2epc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_is_rocc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_is_mov; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_mul_resp_bits_uop_ftq_idx; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_edge_inst; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_mul_resp_bits_uop_pc_lob; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_taken; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_imm_rename; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_mul_resp_bits_uop_imm_sel; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_mul_resp_bits_uop_pimm; // @[core.scala:81:11] wire [19:0] _unique_exe_unit_0_io_mul_resp_bits_uop_imm_packed; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_op1_sel; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_mul_resp_bits_uop_op2_sel; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_ldst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_wen; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_ren1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_ren2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_ren3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_swap12; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_swap23; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_fromint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_toint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_fastpipe; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_fma; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_div; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_sqrt; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_wflags; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_ctrl_vec; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_mul_resp_bits_uop_rob_idx; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_mul_resp_bits_uop_ldq_idx; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_mul_resp_bits_uop_stq_idx; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_rxq_idx; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_mul_resp_bits_uop_pdst; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_mul_resp_bits_uop_prs1; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_mul_resp_bits_uop_prs2; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_mul_resp_bits_uop_prs3; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_mul_resp_bits_uop_ppred; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_prs1_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_prs2_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_prs3_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_ppred_busy; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_mul_resp_bits_uop_stale_pdst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_exception; // @[core.scala:81:11] wire [63:0] _unique_exe_unit_0_io_mul_resp_bits_uop_exc_cause; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_mul_resp_bits_uop_mem_cmd; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_mem_size; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_mem_signed; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_uses_ldq; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_uses_stq; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_is_unique; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_flush_on_commit; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_mul_resp_bits_uop_csr_cmd; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_ldst_is_rs1; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_mul_resp_bits_uop_ldst; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_mul_resp_bits_uop_lrs1; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_mul_resp_bits_uop_lrs2; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_mul_resp_bits_uop_lrs3; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_dst_rtype; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_lrs1_rtype; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_lrs2_rtype; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_frs3_en; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fcn_dw; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_mul_resp_bits_uop_fcn_op; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_fp_val; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_mul_resp_bits_uop_fp_rm; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_mul_resp_bits_uop_fp_typ; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_xcpt_pf_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_xcpt_ae_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_xcpt_ma_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_bp_debug_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_mul_resp_bits_uop_bp_xcpt_if; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_mul_resp_bits_uop_debug_fsrc; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_mul_resp_bits_uop_debug_tsrc; // @[core.scala:81:11] wire [63:0] _unique_exe_unit_0_io_mul_resp_bits_data; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_valid; // @[core.scala:81:11] wire [31:0] _unique_exe_unit_0_io_csr_resp_bits_uop_inst; // @[core.scala:81:11] wire [31:0] _unique_exe_unit_0_io_csr_resp_bits_uop_debug_inst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_is_rvc; // @[core.scala:81:11] wire [39:0] _unique_exe_unit_0_io_csr_resp_bits_uop_debug_pc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_iq_type_0; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_iq_type_1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_iq_type_2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_iq_type_3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fu_code_0; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fu_code_1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fu_code_2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fu_code_3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fu_code_4; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fu_code_5; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fu_code_6; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fu_code_7; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fu_code_8; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fu_code_9; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_iw_issued; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_iw_issued_partial_agen; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_iw_issued_partial_dgen; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_iw_p1_speculative_child; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_iw_p2_speculative_child; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_iw_p1_bypass_hint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_iw_p2_bypass_hint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_iw_p3_bypass_hint; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_dis_col_sel; // @[core.scala:81:11] wire [11:0] _unique_exe_unit_0_io_csr_resp_bits_uop_br_mask; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_csr_resp_bits_uop_br_tag; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_csr_resp_bits_uop_br_type; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_is_sfb; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_is_fence; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_is_fencei; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_is_sfence; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_is_amo; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_is_eret; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_is_sys_pc2epc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_is_rocc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_is_mov; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_csr_resp_bits_uop_ftq_idx; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_edge_inst; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_csr_resp_bits_uop_pc_lob; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_taken; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_imm_rename; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_csr_resp_bits_uop_imm_sel; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_csr_resp_bits_uop_pimm; // @[core.scala:81:11] wire [19:0] _unique_exe_unit_0_io_csr_resp_bits_uop_imm_packed; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_op1_sel; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_csr_resp_bits_uop_op2_sel; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_ldst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_wen; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_ren1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_ren2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_ren3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_swap12; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_swap23; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_fromint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_toint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_fastpipe; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_fma; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_div; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_sqrt; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_wflags; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_ctrl_vec; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_csr_resp_bits_uop_rob_idx; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_csr_resp_bits_uop_ldq_idx; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_csr_resp_bits_uop_stq_idx; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_rxq_idx; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_csr_resp_bits_uop_pdst; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_csr_resp_bits_uop_prs1; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_csr_resp_bits_uop_prs2; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_csr_resp_bits_uop_prs3; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_csr_resp_bits_uop_ppred; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_prs1_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_prs2_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_prs3_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_ppred_busy; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_csr_resp_bits_uop_stale_pdst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_exception; // @[core.scala:81:11] wire [63:0] _unique_exe_unit_0_io_csr_resp_bits_uop_exc_cause; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_csr_resp_bits_uop_mem_cmd; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_mem_size; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_mem_signed; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_uses_ldq; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_uses_stq; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_is_unique; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_flush_on_commit; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_csr_resp_bits_uop_csr_cmd; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_ldst_is_rs1; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_csr_resp_bits_uop_ldst; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_csr_resp_bits_uop_lrs1; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_csr_resp_bits_uop_lrs2; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_csr_resp_bits_uop_lrs3; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_dst_rtype; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_lrs1_rtype; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_lrs2_rtype; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_frs3_en; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fcn_dw; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_csr_resp_bits_uop_fcn_op; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_fp_val; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_csr_resp_bits_uop_fp_rm; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_csr_resp_bits_uop_fp_typ; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_xcpt_pf_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_xcpt_ae_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_xcpt_ma_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_bp_debug_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_csr_resp_bits_uop_bp_xcpt_if; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_csr_resp_bits_uop_debug_fsrc; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_csr_resp_bits_uop_debug_tsrc; // @[core.scala:81:11] wire [63:0] _unique_exe_unit_0_io_csr_resp_bits_data; // @[core.scala:81:11] wire [11:0] _unique_exe_unit_0_io_csr_resp_bits_addr; // @[core.scala:81:11] wire _unique_exe_unit_0_io_sfence_valid; // @[core.scala:81:11] wire _unique_exe_unit_0_io_sfence_bits_rs1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_sfence_bits_rs2; // @[core.scala:81:11] wire [38:0] _unique_exe_unit_0_io_sfence_bits_addr; // @[core.scala:81:11] wire _unique_exe_unit_0_io_sfence_bits_asid; // @[core.scala:81:11] wire _unique_exe_unit_0_io_sfence_bits_hv; // @[core.scala:81:11] wire _unique_exe_unit_0_io_sfence_bits_hg; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_valid; // @[core.scala:81:11] wire [31:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_inst; // @[core.scala:81:11] wire [31:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_debug_inst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_is_rvc; // @[core.scala:81:11] wire [39:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_debug_pc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_iq_type_0; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_iq_type_1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_iq_type_2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_iq_type_3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fu_code_0; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fu_code_1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fu_code_2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fu_code_3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fu_code_4; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fu_code_5; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fu_code_6; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fu_code_7; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fu_code_8; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fu_code_9; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_iw_issued; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_iw_issued_partial_agen; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_iw_issued_partial_dgen; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_iw_p1_speculative_child; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_iw_p2_speculative_child; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_iw_p1_bypass_hint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_iw_p2_bypass_hint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_iw_p3_bypass_hint; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_dis_col_sel; // @[core.scala:81:11] wire [11:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_br_mask; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_br_tag; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_br_type; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_is_sfb; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_is_fence; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_is_fencei; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_is_sfence; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_is_amo; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_is_eret; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_is_sys_pc2epc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_is_rocc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_is_mov; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_ftq_idx; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_edge_inst; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_pc_lob; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_taken; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_imm_rename; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_imm_sel; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_pimm; // @[core.scala:81:11] wire [19:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_imm_packed; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_op1_sel; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_op2_sel; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_ldst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_wen; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_ren1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_ren2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_ren3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_swap12; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_swap23; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_fromint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_toint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_fastpipe; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_fma; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_div; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_sqrt; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_wflags; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_ctrl_vec; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_rob_idx; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_ldq_idx; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_stq_idx; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_rxq_idx; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_pdst; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_prs1; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_prs2; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_prs3; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_ppred; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_prs1_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_prs2_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_prs3_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_ppred_busy; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_stale_pdst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_exception; // @[core.scala:81:11] wire [63:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_exc_cause; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_mem_cmd; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_mem_size; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_mem_signed; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_uses_ldq; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_uses_stq; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_is_unique; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_flush_on_commit; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_csr_cmd; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_ldst_is_rs1; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_ldst; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_lrs1; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_lrs2; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_lrs3; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_dst_rtype; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_lrs1_rtype; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_lrs2_rtype; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_frs3_en; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fcn_dw; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_fcn_op; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_val; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_rm; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_fp_typ; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_xcpt_pf_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_xcpt_ae_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_xcpt_ma_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_bp_debug_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_uop_bp_xcpt_if; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_debug_fsrc; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_ifpu_resp_bits_uop_debug_tsrc; // @[core.scala:81:11] wire [64:0] _unique_exe_unit_0_io_ifpu_resp_bits_data; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_predicated; // @[core.scala:81:11] wire _unique_exe_unit_0_io_ifpu_resp_bits_fflags_valid; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_ifpu_resp_bits_fflags_bits; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_valid; // @[core.scala:81:11] wire [31:0] _unique_exe_unit_0_io_div_resp_bits_uop_inst; // @[core.scala:81:11] wire [31:0] _unique_exe_unit_0_io_div_resp_bits_uop_debug_inst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_is_rvc; // @[core.scala:81:11] wire [39:0] _unique_exe_unit_0_io_div_resp_bits_uop_debug_pc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_iq_type_0; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_iq_type_1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_iq_type_2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_iq_type_3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fu_code_0; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fu_code_1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fu_code_2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fu_code_3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fu_code_4; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fu_code_5; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fu_code_6; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fu_code_7; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fu_code_8; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fu_code_9; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_iw_issued; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_iw_issued_partial_agen; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_iw_issued_partial_dgen; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_iw_p1_speculative_child; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_iw_p2_speculative_child; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_iw_p1_bypass_hint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_iw_p2_bypass_hint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_iw_p3_bypass_hint; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_dis_col_sel; // @[core.scala:81:11] wire [11:0] _unique_exe_unit_0_io_div_resp_bits_uop_br_mask; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_div_resp_bits_uop_br_tag; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_div_resp_bits_uop_br_type; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_is_sfb; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_is_fence; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_is_fencei; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_is_sfence; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_is_amo; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_is_eret; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_is_sys_pc2epc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_is_rocc; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_is_mov; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_div_resp_bits_uop_ftq_idx; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_edge_inst; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_div_resp_bits_uop_pc_lob; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_taken; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_imm_rename; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_div_resp_bits_uop_imm_sel; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_div_resp_bits_uop_pimm; // @[core.scala:81:11] wire [19:0] _unique_exe_unit_0_io_div_resp_bits_uop_imm_packed; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_op1_sel; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_div_resp_bits_uop_op2_sel; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_ldst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_wen; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_ren1; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_ren2; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_ren3; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_swap12; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_swap23; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_fromint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_toint; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_fastpipe; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_fma; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_div; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_sqrt; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_wflags; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_ctrl_vec; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_div_resp_bits_uop_rob_idx; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_div_resp_bits_uop_ldq_idx; // @[core.scala:81:11] wire [3:0] _unique_exe_unit_0_io_div_resp_bits_uop_stq_idx; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_rxq_idx; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_div_resp_bits_uop_pdst; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_div_resp_bits_uop_prs1; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_div_resp_bits_uop_prs2; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_div_resp_bits_uop_prs3; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_div_resp_bits_uop_ppred; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_prs1_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_prs2_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_prs3_busy; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_ppred_busy; // @[core.scala:81:11] wire [6:0] _unique_exe_unit_0_io_div_resp_bits_uop_stale_pdst; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_exception; // @[core.scala:81:11] wire [63:0] _unique_exe_unit_0_io_div_resp_bits_uop_exc_cause; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_div_resp_bits_uop_mem_cmd; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_mem_size; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_mem_signed; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_uses_ldq; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_uses_stq; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_is_unique; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_flush_on_commit; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_div_resp_bits_uop_csr_cmd; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_ldst_is_rs1; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_div_resp_bits_uop_ldst; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_div_resp_bits_uop_lrs1; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_div_resp_bits_uop_lrs2; // @[core.scala:81:11] wire [5:0] _unique_exe_unit_0_io_div_resp_bits_uop_lrs3; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_dst_rtype; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_lrs1_rtype; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_lrs2_rtype; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_frs3_en; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fcn_dw; // @[core.scala:81:11] wire [4:0] _unique_exe_unit_0_io_div_resp_bits_uop_fcn_op; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_fp_val; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_div_resp_bits_uop_fp_rm; // @[core.scala:81:11] wire [1:0] _unique_exe_unit_0_io_div_resp_bits_uop_fp_typ; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_xcpt_pf_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_xcpt_ae_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_xcpt_ma_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_bp_debug_if; // @[core.scala:81:11] wire _unique_exe_unit_0_io_div_resp_bits_uop_bp_xcpt_if; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_div_resp_bits_uop_debug_fsrc; // @[core.scala:81:11] wire [2:0] _unique_exe_unit_0_io_div_resp_bits_uop_debug_tsrc; // @[core.scala:81:11] wire [63:0] _unique_exe_unit_0_io_div_resp_bits_data; // @[core.scala:81:11] wire _mem_exe_unit_1_io_ready_fu_types_1; // @[core.scala:74:11] wire _mem_exe_unit_1_io_arb_irf_reqs_0_valid; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_1_io_arb_irf_reqs_0_bits; // @[core.scala:74:11] wire _mem_exe_unit_1_io_arb_immrf_req_valid; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_1_io_arb_immrf_req_bits; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_valid; // @[core.scala:74:11] wire [31:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_inst; // @[core.scala:74:11] wire [31:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_debug_inst; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_rvc; // @[core.scala:74:11] wire [39:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_debug_pc; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iq_type_0; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iq_type_1; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iq_type_2; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iq_type_3; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_0; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_1; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_2; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_3; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_4; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_5; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_6; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_7; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_8; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fu_code_9; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_issued; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_agen; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_dgen; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_p1_speculative_child; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_p2_speculative_child; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_p1_bypass_hint; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_p2_bypass_hint; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_iw_p3_bypass_hint; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_dis_col_sel; // @[core.scala:74:11] wire [11:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_br_mask; // @[core.scala:74:11] wire [3:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_br_tag; // @[core.scala:74:11] wire [3:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_br_type; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_sfb; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_fence; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_fencei; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_sfence; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_amo; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_eret; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_rocc; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_mov; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ftq_idx; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_edge_inst; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_pc_lob; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_taken; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_imm_rename; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_imm_sel; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_pimm; // @[core.scala:74:11] wire [19:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_imm_packed; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_op1_sel; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_op2_sel; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ldst; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wen; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren1; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren2; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren3; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap12; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap23; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fromint; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_toint; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fastpipe; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fma; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_div; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_sqrt; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wflags; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_vec; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_rob_idx; // @[core.scala:74:11] wire [3:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ldq_idx; // @[core.scala:74:11] wire [3:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_stq_idx; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_rxq_idx; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_pdst; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs1; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs2; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs3; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ppred; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs1_busy; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs2_busy; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_prs3_busy; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ppred_busy; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_stale_pdst; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_exception; // @[core.scala:74:11] wire [63:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_exc_cause; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_mem_cmd; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_mem_size; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_mem_signed; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_uses_ldq; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_uses_stq; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_is_unique; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_flush_on_commit; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_csr_cmd; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_ldst; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_lrs1; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_lrs2; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_lrs3; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_dst_rtype; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_lrs1_rtype; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_lrs2_rtype; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_frs3_en; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fcn_dw; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fcn_op; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_val; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_rm; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_fp_typ; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_bp_debug_if; // @[core.scala:74:11] wire _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_debug_fsrc; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_1_io_rrd_immrf_wakeup_bits_uop_debug_tsrc; // @[core.scala:74:11] wire _mem_exe_unit_1_io_squash_iss; // @[core.scala:74:11] wire _mem_exe_unit_0_io_arb_irf_reqs_0_valid; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_0_io_arb_irf_reqs_0_bits; // @[core.scala:74:11] wire _mem_exe_unit_0_io_arb_immrf_req_valid; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_0_io_arb_immrf_req_bits; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_valid; // @[core.scala:74:11] wire [31:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_inst; // @[core.scala:74:11] wire [31:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_inst; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_rvc; // @[core.scala:74:11] wire [39:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_pc; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_0; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_1; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_2; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iq_type_3; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_0; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_1; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_2; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_3; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_4; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_5; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_6; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_7; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_8; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fu_code_9; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_issued; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_agen; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_issued_partial_dgen; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p1_speculative_child; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p2_speculative_child; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p1_bypass_hint; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p2_bypass_hint; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_iw_p3_bypass_hint; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_dis_col_sel; // @[core.scala:74:11] wire [11:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_br_mask; // @[core.scala:74:11] wire [3:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_br_tag; // @[core.scala:74:11] wire [3:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_br_type; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_sfb; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_fence; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_fencei; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_sfence; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_amo; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_eret; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_sys_pc2epc; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_rocc; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_mov; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ftq_idx; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_edge_inst; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_pc_lob; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_taken; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_imm_rename; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_imm_sel; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_pimm; // @[core.scala:74:11] wire [19:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_imm_packed; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_op1_sel; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_op2_sel; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ldst; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wen; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren1; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren2; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_ren3; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap12; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_swap23; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fromint; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_toint; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fastpipe; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_fma; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_div; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_sqrt; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_wflags; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_ctrl_vec; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_rob_idx; // @[core.scala:74:11] wire [3:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ldq_idx; // @[core.scala:74:11] wire [3:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_stq_idx; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_rxq_idx; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_pdst; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs1; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs2; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs3; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ppred; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs1_busy; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs2_busy; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_prs3_busy; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ppred_busy; // @[core.scala:74:11] wire [6:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_stale_pdst; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_exception; // @[core.scala:74:11] wire [63:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_exc_cause; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_mem_cmd; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_mem_size; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_mem_signed; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_uses_ldq; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_uses_stq; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_is_unique; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_flush_on_commit; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_csr_cmd; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ldst_is_rs1; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_ldst; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs1; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs2; // @[core.scala:74:11] wire [5:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs3; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_dst_rtype; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs1_rtype; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_lrs2_rtype; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_frs3_en; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fcn_dw; // @[core.scala:74:11] wire [4:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fcn_op; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_val; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_rm; // @[core.scala:74:11] wire [1:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_fp_typ; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_xcpt_pf_if; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_xcpt_ae_if; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_xcpt_ma_if; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_bp_debug_if; // @[core.scala:74:11] wire _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_bp_xcpt_if; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_fsrc; // @[core.scala:74:11] wire [2:0] _mem_exe_unit_0_io_rrd_immrf_wakeup_bits_uop_debug_tsrc; // @[core.scala:74:11] wire _mem_exe_unit_0_io_squash_iss; // @[core.scala:74:11] wire io_hartid_0 = io_hartid; // @[core.scala:50:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[core.scala:50:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[core.scala:50:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[core.scala:50:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[core.scala:50:7] wire io_interrupts_seip_0 = io_interrupts_seip; // @[core.scala:50:7] wire io_ifu_fetchpacket_valid_0 = io_ifu_fetchpacket_valid; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_valid_0 = io_ifu_fetchpacket_bits_uops_0_valid; // @[core.scala:50:7] wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_inst; // @[core.scala:50:7] wire [31:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_inst; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_rvc; // @[core.scala:50:7] wire [39:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_pc; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_0_bits_is_sfb; // @[core.scala:50:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_0_bits_ftq_idx; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_0_bits_edge_inst; // @[core.scala:50:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_0_bits_pc_lob; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_taken_0 = io_ifu_fetchpacket_bits_uops_0_bits_taken; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_pf_if; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ae_if; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_debug_if; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_0_bits_bp_xcpt_if; // @[core.scala:50:7] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_0_bits_debug_fsrc; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_valid_0 = io_ifu_fetchpacket_bits_uops_1_valid; // @[core.scala:50:7] wire [31:0] io_ifu_fetchpacket_bits_uops_1_bits_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_inst; // @[core.scala:50:7] wire [31:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_inst; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_rvc_0 = io_ifu_fetchpacket_bits_uops_1_bits_is_rvc; // @[core.scala:50:7] wire [39:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_pc_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_pc; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_sfb_0 = io_ifu_fetchpacket_bits_uops_1_bits_is_sfb; // @[core.scala:50:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx_0 = io_ifu_fetchpacket_bits_uops_1_bits_ftq_idx; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_edge_inst_0 = io_ifu_fetchpacket_bits_uops_1_bits_edge_inst; // @[core.scala:50:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_pc_lob_0 = io_ifu_fetchpacket_bits_uops_1_bits_pc_lob; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_taken_0 = io_ifu_fetchpacket_bits_uops_1_bits_taken; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_xcpt_pf_if; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ae_if; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_bp_debug_if; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if_0 = io_ifu_fetchpacket_bits_uops_1_bits_bp_xcpt_if; // @[core.scala:50:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc_0 = io_ifu_fetchpacket_bits_uops_1_bits_debug_fsrc; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_0_valid_0 = io_ifu_rrd_ftq_resps_0_valid; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_0_entry_cfi_idx_valid_0 = io_ifu_rrd_ftq_resps_0_entry_cfi_idx_valid; // @[core.scala:50:7] wire [1:0] io_ifu_rrd_ftq_resps_0_entry_cfi_idx_bits_0 = io_ifu_rrd_ftq_resps_0_entry_cfi_idx_bits; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_0_entry_cfi_taken_0 = io_ifu_rrd_ftq_resps_0_entry_cfi_taken; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_0_entry_cfi_mispredicted_0 = io_ifu_rrd_ftq_resps_0_entry_cfi_mispredicted; // @[core.scala:50:7] wire [2:0] io_ifu_rrd_ftq_resps_0_entry_cfi_type_0 = io_ifu_rrd_ftq_resps_0_entry_cfi_type; // @[core.scala:50:7] wire [3:0] io_ifu_rrd_ftq_resps_0_entry_br_mask_0 = io_ifu_rrd_ftq_resps_0_entry_br_mask; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_0_entry_cfi_is_call_0 = io_ifu_rrd_ftq_resps_0_entry_cfi_is_call; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_0_entry_cfi_is_ret_0 = io_ifu_rrd_ftq_resps_0_entry_cfi_is_ret; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_0_entry_cfi_npc_plus4_0 = io_ifu_rrd_ftq_resps_0_entry_cfi_npc_plus4; // @[core.scala:50:7] wire [39:0] io_ifu_rrd_ftq_resps_0_entry_ras_top_0 = io_ifu_rrd_ftq_resps_0_entry_ras_top; // @[core.scala:50:7] wire [4:0] io_ifu_rrd_ftq_resps_0_entry_ras_idx_0 = io_ifu_rrd_ftq_resps_0_entry_ras_idx; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_0_entry_start_bank_0 = io_ifu_rrd_ftq_resps_0_entry_start_bank; // @[core.scala:50:7] wire [63:0] io_ifu_rrd_ftq_resps_0_ghist_old_history_0 = io_ifu_rrd_ftq_resps_0_ghist_old_history; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken_0 = io_ifu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken_0 = io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_taken_0 = io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_taken; // @[core.scala:50:7] wire [4:0] io_ifu_rrd_ftq_resps_0_ghist_ras_idx_0 = io_ifu_rrd_ftq_resps_0_ghist_ras_idx; // @[core.scala:50:7] wire [39:0] io_ifu_rrd_ftq_resps_0_pc_0 = io_ifu_rrd_ftq_resps_0_pc; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_1_valid_0 = io_ifu_rrd_ftq_resps_1_valid; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_1_entry_cfi_idx_valid_0 = io_ifu_rrd_ftq_resps_1_entry_cfi_idx_valid; // @[core.scala:50:7] wire [1:0] io_ifu_rrd_ftq_resps_1_entry_cfi_idx_bits_0 = io_ifu_rrd_ftq_resps_1_entry_cfi_idx_bits; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_1_entry_cfi_taken_0 = io_ifu_rrd_ftq_resps_1_entry_cfi_taken; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_1_entry_cfi_mispredicted_0 = io_ifu_rrd_ftq_resps_1_entry_cfi_mispredicted; // @[core.scala:50:7] wire [2:0] io_ifu_rrd_ftq_resps_1_entry_cfi_type_0 = io_ifu_rrd_ftq_resps_1_entry_cfi_type; // @[core.scala:50:7] wire [3:0] io_ifu_rrd_ftq_resps_1_entry_br_mask_0 = io_ifu_rrd_ftq_resps_1_entry_br_mask; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_1_entry_cfi_is_call_0 = io_ifu_rrd_ftq_resps_1_entry_cfi_is_call; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_1_entry_cfi_is_ret_0 = io_ifu_rrd_ftq_resps_1_entry_cfi_is_ret; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_1_entry_cfi_npc_plus4_0 = io_ifu_rrd_ftq_resps_1_entry_cfi_npc_plus4; // @[core.scala:50:7] wire [39:0] io_ifu_rrd_ftq_resps_1_entry_ras_top_0 = io_ifu_rrd_ftq_resps_1_entry_ras_top; // @[core.scala:50:7] wire [4:0] io_ifu_rrd_ftq_resps_1_entry_ras_idx_0 = io_ifu_rrd_ftq_resps_1_entry_ras_idx; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_1_entry_start_bank_0 = io_ifu_rrd_ftq_resps_1_entry_start_bank; // @[core.scala:50:7] wire [39:0] io_ifu_rrd_ftq_resps_1_pc_0 = io_ifu_rrd_ftq_resps_1_pc; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_2_valid_0 = io_ifu_rrd_ftq_resps_2_valid; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_2_entry_cfi_idx_valid_0 = io_ifu_rrd_ftq_resps_2_entry_cfi_idx_valid; // @[core.scala:50:7] wire [1:0] io_ifu_rrd_ftq_resps_2_entry_cfi_idx_bits_0 = io_ifu_rrd_ftq_resps_2_entry_cfi_idx_bits; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_2_entry_cfi_taken_0 = io_ifu_rrd_ftq_resps_2_entry_cfi_taken; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_2_entry_cfi_mispredicted_0 = io_ifu_rrd_ftq_resps_2_entry_cfi_mispredicted; // @[core.scala:50:7] wire [2:0] io_ifu_rrd_ftq_resps_2_entry_cfi_type_0 = io_ifu_rrd_ftq_resps_2_entry_cfi_type; // @[core.scala:50:7] wire [3:0] io_ifu_rrd_ftq_resps_2_entry_br_mask_0 = io_ifu_rrd_ftq_resps_2_entry_br_mask; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_2_entry_cfi_is_call_0 = io_ifu_rrd_ftq_resps_2_entry_cfi_is_call; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_2_entry_cfi_is_ret_0 = io_ifu_rrd_ftq_resps_2_entry_cfi_is_ret; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_2_entry_cfi_npc_plus4_0 = io_ifu_rrd_ftq_resps_2_entry_cfi_npc_plus4; // @[core.scala:50:7] wire [39:0] io_ifu_rrd_ftq_resps_2_entry_ras_top_0 = io_ifu_rrd_ftq_resps_2_entry_ras_top; // @[core.scala:50:7] wire [4:0] io_ifu_rrd_ftq_resps_2_entry_ras_idx_0 = io_ifu_rrd_ftq_resps_2_entry_ras_idx; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_2_entry_start_bank_0 = io_ifu_rrd_ftq_resps_2_entry_start_bank; // @[core.scala:50:7] wire [39:0] io_ifu_rrd_ftq_resps_2_pc_0 = io_ifu_rrd_ftq_resps_2_pc; // @[core.scala:50:7] wire [39:0] io_ifu_com_pc_0 = io_ifu_com_pc; // @[core.scala:50:7] wire [39:0] io_ifu_debug_fetch_pc_0_0 = io_ifu_debug_fetch_pc_0; // @[core.scala:50:7] wire [39:0] io_ifu_debug_fetch_pc_1_0 = io_ifu_debug_fetch_pc_1; // @[core.scala:50:7] wire io_ifu_perf_acquire_0 = io_ifu_perf_acquire; // @[core.scala:50:7] wire io_ifu_perf_tlbMiss_0 = io_ifu_perf_tlbMiss; // @[core.scala:50:7] wire io_ptw_perf_l2miss_0 = io_ptw_perf_l2miss; // @[core.scala:50:7] wire io_ptw_perf_l2hit_0 = io_ptw_perf_l2hit; // @[core.scala:50:7] wire io_ptw_perf_pte_miss_0 = io_ptw_perf_pte_miss; // @[core.scala:50:7] wire io_ptw_clock_enabled_0 = io_ptw_clock_enabled; // @[core.scala:50:7] wire io_lsu_iwakeups_0_valid_0 = io_lsu_iwakeups_0_valid; // @[core.scala:50:7] wire [31:0] io_lsu_iwakeups_0_bits_uop_inst_0 = io_lsu_iwakeups_0_bits_uop_inst; // @[core.scala:50:7] wire [31:0] io_lsu_iwakeups_0_bits_uop_debug_inst_0 = io_lsu_iwakeups_0_bits_uop_debug_inst; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_is_rvc_0 = io_lsu_iwakeups_0_bits_uop_is_rvc; // @[core.scala:50:7] wire [39:0] io_lsu_iwakeups_0_bits_uop_debug_pc_0 = io_lsu_iwakeups_0_bits_uop_debug_pc; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_0_0 = io_lsu_iwakeups_0_bits_uop_iq_type_0; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_1_0 = io_lsu_iwakeups_0_bits_uop_iq_type_1; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_2_0 = io_lsu_iwakeups_0_bits_uop_iq_type_2; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_iq_type_3_0 = io_lsu_iwakeups_0_bits_uop_iq_type_3; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_0_0 = io_lsu_iwakeups_0_bits_uop_fu_code_0; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_1_0 = io_lsu_iwakeups_0_bits_uop_fu_code_1; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_2_0 = io_lsu_iwakeups_0_bits_uop_fu_code_2; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_3_0 = io_lsu_iwakeups_0_bits_uop_fu_code_3; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_4_0 = io_lsu_iwakeups_0_bits_uop_fu_code_4; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_5_0 = io_lsu_iwakeups_0_bits_uop_fu_code_5; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_6_0 = io_lsu_iwakeups_0_bits_uop_fu_code_6; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_7_0 = io_lsu_iwakeups_0_bits_uop_fu_code_7; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_8_0 = io_lsu_iwakeups_0_bits_uop_fu_code_8; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fu_code_9_0 = io_lsu_iwakeups_0_bits_uop_fu_code_9; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_iw_issued_0 = io_lsu_iwakeups_0_bits_uop_iw_issued; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_dis_col_sel_0 = io_lsu_iwakeups_0_bits_uop_dis_col_sel; // @[core.scala:50:7] wire [11:0] io_lsu_iwakeups_0_bits_uop_br_mask_0 = io_lsu_iwakeups_0_bits_uop_br_mask; // @[core.scala:50:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_br_tag_0 = io_lsu_iwakeups_0_bits_uop_br_tag; // @[core.scala:50:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_br_type_0 = io_lsu_iwakeups_0_bits_uop_br_type; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_is_sfb_0 = io_lsu_iwakeups_0_bits_uop_is_sfb; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_is_fence_0 = io_lsu_iwakeups_0_bits_uop_is_fence; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_is_fencei_0 = io_lsu_iwakeups_0_bits_uop_is_fencei; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_is_sfence_0 = io_lsu_iwakeups_0_bits_uop_is_sfence; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_is_amo_0 = io_lsu_iwakeups_0_bits_uop_is_amo; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_is_eret_0 = io_lsu_iwakeups_0_bits_uop_is_eret; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc_0 = io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_is_rocc_0 = io_lsu_iwakeups_0_bits_uop_is_rocc; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_is_mov_0 = io_lsu_iwakeups_0_bits_uop_is_mov; // @[core.scala:50:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_ftq_idx_0 = io_lsu_iwakeups_0_bits_uop_ftq_idx; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_edge_inst_0 = io_lsu_iwakeups_0_bits_uop_edge_inst; // @[core.scala:50:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_pc_lob_0 = io_lsu_iwakeups_0_bits_uop_pc_lob; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_taken_0 = io_lsu_iwakeups_0_bits_uop_taken; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_imm_rename_0 = io_lsu_iwakeups_0_bits_uop_imm_rename; // @[core.scala:50:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_imm_sel_0 = io_lsu_iwakeups_0_bits_uop_imm_sel; // @[core.scala:50:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_pimm_0 = io_lsu_iwakeups_0_bits_uop_pimm; // @[core.scala:50:7] wire [19:0] io_lsu_iwakeups_0_bits_uop_imm_packed_0 = io_lsu_iwakeups_0_bits_uop_imm_packed; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_op1_sel_0 = io_lsu_iwakeups_0_bits_uop_op1_sel; // @[core.scala:50:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_op2_sel_0 = io_lsu_iwakeups_0_bits_uop_op2_sel; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_div_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_div; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec_0 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec; // @[core.scala:50:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_rob_idx_0 = io_lsu_iwakeups_0_bits_uop_rob_idx; // @[core.scala:50:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_ldq_idx_0 = io_lsu_iwakeups_0_bits_uop_ldq_idx; // @[core.scala:50:7] wire [3:0] io_lsu_iwakeups_0_bits_uop_stq_idx_0 = io_lsu_iwakeups_0_bits_uop_stq_idx; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_rxq_idx_0 = io_lsu_iwakeups_0_bits_uop_rxq_idx; // @[core.scala:50:7] wire [6:0] io_lsu_iwakeups_0_bits_uop_pdst_0 = io_lsu_iwakeups_0_bits_uop_pdst; // @[core.scala:50:7] wire [6:0] io_lsu_iwakeups_0_bits_uop_prs1_0 = io_lsu_iwakeups_0_bits_uop_prs1; // @[core.scala:50:7] wire [6:0] io_lsu_iwakeups_0_bits_uop_prs2_0 = io_lsu_iwakeups_0_bits_uop_prs2; // @[core.scala:50:7] wire [6:0] io_lsu_iwakeups_0_bits_uop_prs3_0 = io_lsu_iwakeups_0_bits_uop_prs3; // @[core.scala:50:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_ppred_0 = io_lsu_iwakeups_0_bits_uop_ppred; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_prs1_busy_0 = io_lsu_iwakeups_0_bits_uop_prs1_busy; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_prs2_busy_0 = io_lsu_iwakeups_0_bits_uop_prs2_busy; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_prs3_busy_0 = io_lsu_iwakeups_0_bits_uop_prs3_busy; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_ppred_busy_0 = io_lsu_iwakeups_0_bits_uop_ppred_busy; // @[core.scala:50:7] wire [6:0] io_lsu_iwakeups_0_bits_uop_stale_pdst_0 = io_lsu_iwakeups_0_bits_uop_stale_pdst; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_exception_0 = io_lsu_iwakeups_0_bits_uop_exception; // @[core.scala:50:7] wire [63:0] io_lsu_iwakeups_0_bits_uop_exc_cause_0 = io_lsu_iwakeups_0_bits_uop_exc_cause; // @[core.scala:50:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_mem_cmd_0 = io_lsu_iwakeups_0_bits_uop_mem_cmd; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_mem_size_0 = io_lsu_iwakeups_0_bits_uop_mem_size; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_mem_signed_0 = io_lsu_iwakeups_0_bits_uop_mem_signed; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_uses_ldq_0 = io_lsu_iwakeups_0_bits_uop_uses_ldq; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_uses_stq_0 = io_lsu_iwakeups_0_bits_uop_uses_stq; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_is_unique_0 = io_lsu_iwakeups_0_bits_uop_is_unique; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_flush_on_commit_0 = io_lsu_iwakeups_0_bits_uop_flush_on_commit; // @[core.scala:50:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_csr_cmd_0 = io_lsu_iwakeups_0_bits_uop_csr_cmd; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_ldst_is_rs1_0 = io_lsu_iwakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:50:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_ldst_0 = io_lsu_iwakeups_0_bits_uop_ldst; // @[core.scala:50:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs1_0 = io_lsu_iwakeups_0_bits_uop_lrs1; // @[core.scala:50:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs2_0 = io_lsu_iwakeups_0_bits_uop_lrs2; // @[core.scala:50:7] wire [5:0] io_lsu_iwakeups_0_bits_uop_lrs3_0 = io_lsu_iwakeups_0_bits_uop_lrs3; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_dst_rtype_0 = io_lsu_iwakeups_0_bits_uop_dst_rtype; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_lrs1_rtype_0 = io_lsu_iwakeups_0_bits_uop_lrs1_rtype; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_lrs2_rtype_0 = io_lsu_iwakeups_0_bits_uop_lrs2_rtype; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_frs3_en_0 = io_lsu_iwakeups_0_bits_uop_frs3_en; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fcn_dw_0 = io_lsu_iwakeups_0_bits_uop_fcn_dw; // @[core.scala:50:7] wire [4:0] io_lsu_iwakeups_0_bits_uop_fcn_op_0 = io_lsu_iwakeups_0_bits_uop_fcn_op; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_fp_val_0 = io_lsu_iwakeups_0_bits_uop_fp_val; // @[core.scala:50:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_fp_rm_0 = io_lsu_iwakeups_0_bits_uop_fp_rm; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_uop_fp_typ_0 = io_lsu_iwakeups_0_bits_uop_fp_typ; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_xcpt_pf_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_xcpt_ae_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_xcpt_ma_if_0 = io_lsu_iwakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_bp_debug_if_0 = io_lsu_iwakeups_0_bits_uop_bp_debug_if; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_uop_bp_xcpt_if_0 = io_lsu_iwakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:50:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_debug_fsrc_0 = io_lsu_iwakeups_0_bits_uop_debug_fsrc; // @[core.scala:50:7] wire [2:0] io_lsu_iwakeups_0_bits_uop_debug_tsrc_0 = io_lsu_iwakeups_0_bits_uop_debug_tsrc; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_bypassable_0 = io_lsu_iwakeups_0_bits_bypassable; // @[core.scala:50:7] wire [1:0] io_lsu_iwakeups_0_bits_speculative_mask_0 = io_lsu_iwakeups_0_bits_speculative_mask; // @[core.scala:50:7] wire io_lsu_iwakeups_0_bits_rebusy_0 = io_lsu_iwakeups_0_bits_rebusy; // @[core.scala:50:7] wire io_lsu_iresp_0_valid_0 = io_lsu_iresp_0_valid; // @[core.scala:50:7] wire [31:0] io_lsu_iresp_0_bits_uop_inst_0 = io_lsu_iresp_0_bits_uop_inst; // @[core.scala:50:7] wire [31:0] io_lsu_iresp_0_bits_uop_debug_inst_0 = io_lsu_iresp_0_bits_uop_debug_inst; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_is_rvc_0 = io_lsu_iresp_0_bits_uop_is_rvc; // @[core.scala:50:7] wire [39:0] io_lsu_iresp_0_bits_uop_debug_pc_0 = io_lsu_iresp_0_bits_uop_debug_pc; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_iq_type_0_0 = io_lsu_iresp_0_bits_uop_iq_type_0; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_iq_type_1_0 = io_lsu_iresp_0_bits_uop_iq_type_1; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_iq_type_2_0 = io_lsu_iresp_0_bits_uop_iq_type_2; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_iq_type_3_0 = io_lsu_iresp_0_bits_uop_iq_type_3; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fu_code_0_0 = io_lsu_iresp_0_bits_uop_fu_code_0; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fu_code_1_0 = io_lsu_iresp_0_bits_uop_fu_code_1; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fu_code_2_0 = io_lsu_iresp_0_bits_uop_fu_code_2; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fu_code_3_0 = io_lsu_iresp_0_bits_uop_fu_code_3; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fu_code_4_0 = io_lsu_iresp_0_bits_uop_fu_code_4; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fu_code_5_0 = io_lsu_iresp_0_bits_uop_fu_code_5; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fu_code_6_0 = io_lsu_iresp_0_bits_uop_fu_code_6; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fu_code_7_0 = io_lsu_iresp_0_bits_uop_fu_code_7; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fu_code_8_0 = io_lsu_iresp_0_bits_uop_fu_code_8; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fu_code_9_0 = io_lsu_iresp_0_bits_uop_fu_code_9; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_iw_issued_0 = io_lsu_iresp_0_bits_uop_iw_issued; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_iresp_0_bits_uop_iw_issued_partial_agen; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_iresp_0_bits_uop_iw_p1_speculative_child; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_iresp_0_bits_uop_iw_p2_speculative_child; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_dis_col_sel_0 = io_lsu_iresp_0_bits_uop_dis_col_sel; // @[core.scala:50:7] wire [11:0] io_lsu_iresp_0_bits_uop_br_mask_0 = io_lsu_iresp_0_bits_uop_br_mask; // @[core.scala:50:7] wire [3:0] io_lsu_iresp_0_bits_uop_br_tag_0 = io_lsu_iresp_0_bits_uop_br_tag; // @[core.scala:50:7] wire [3:0] io_lsu_iresp_0_bits_uop_br_type_0 = io_lsu_iresp_0_bits_uop_br_type; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_is_sfb_0 = io_lsu_iresp_0_bits_uop_is_sfb; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_is_fence_0 = io_lsu_iresp_0_bits_uop_is_fence; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_is_fencei_0 = io_lsu_iresp_0_bits_uop_is_fencei; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_is_sfence_0 = io_lsu_iresp_0_bits_uop_is_sfence; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_is_amo_0 = io_lsu_iresp_0_bits_uop_is_amo; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_is_eret_0 = io_lsu_iresp_0_bits_uop_is_eret; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_iresp_0_bits_uop_is_sys_pc2epc; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_is_rocc_0 = io_lsu_iresp_0_bits_uop_is_rocc; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_is_mov_0 = io_lsu_iresp_0_bits_uop_is_mov; // @[core.scala:50:7] wire [4:0] io_lsu_iresp_0_bits_uop_ftq_idx_0 = io_lsu_iresp_0_bits_uop_ftq_idx; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_edge_inst_0 = io_lsu_iresp_0_bits_uop_edge_inst; // @[core.scala:50:7] wire [5:0] io_lsu_iresp_0_bits_uop_pc_lob_0 = io_lsu_iresp_0_bits_uop_pc_lob; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_taken_0 = io_lsu_iresp_0_bits_uop_taken; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_imm_rename_0 = io_lsu_iresp_0_bits_uop_imm_rename; // @[core.scala:50:7] wire [2:0] io_lsu_iresp_0_bits_uop_imm_sel_0 = io_lsu_iresp_0_bits_uop_imm_sel; // @[core.scala:50:7] wire [4:0] io_lsu_iresp_0_bits_uop_pimm_0 = io_lsu_iresp_0_bits_uop_pimm; // @[core.scala:50:7] wire [19:0] io_lsu_iresp_0_bits_uop_imm_packed_0 = io_lsu_iresp_0_bits_uop_imm_packed; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_op1_sel_0 = io_lsu_iresp_0_bits_uop_op1_sel; // @[core.scala:50:7] wire [2:0] io_lsu_iresp_0_bits_uop_op2_sel_0 = io_lsu_iresp_0_bits_uop_op2_sel; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ldst; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_wen_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_wen; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren1; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren2; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren3; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_swap12; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_swap23; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fromint; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_toint_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_toint; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_fma_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_fma; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_div_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_div; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_wflags; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_ctrl_vec_0 = io_lsu_iresp_0_bits_uop_fp_ctrl_vec; // @[core.scala:50:7] wire [5:0] io_lsu_iresp_0_bits_uop_rob_idx_0 = io_lsu_iresp_0_bits_uop_rob_idx; // @[core.scala:50:7] wire [3:0] io_lsu_iresp_0_bits_uop_ldq_idx_0 = io_lsu_iresp_0_bits_uop_ldq_idx; // @[core.scala:50:7] wire [3:0] io_lsu_iresp_0_bits_uop_stq_idx_0 = io_lsu_iresp_0_bits_uop_stq_idx; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_rxq_idx_0 = io_lsu_iresp_0_bits_uop_rxq_idx; // @[core.scala:50:7] wire [6:0] io_lsu_iresp_0_bits_uop_pdst_0 = io_lsu_iresp_0_bits_uop_pdst; // @[core.scala:50:7] wire [6:0] io_lsu_iresp_0_bits_uop_prs1_0 = io_lsu_iresp_0_bits_uop_prs1; // @[core.scala:50:7] wire [6:0] io_lsu_iresp_0_bits_uop_prs2_0 = io_lsu_iresp_0_bits_uop_prs2; // @[core.scala:50:7] wire [6:0] io_lsu_iresp_0_bits_uop_prs3_0 = io_lsu_iresp_0_bits_uop_prs3; // @[core.scala:50:7] wire [4:0] io_lsu_iresp_0_bits_uop_ppred_0 = io_lsu_iresp_0_bits_uop_ppred; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_prs1_busy_0 = io_lsu_iresp_0_bits_uop_prs1_busy; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_prs2_busy_0 = io_lsu_iresp_0_bits_uop_prs2_busy; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_prs3_busy_0 = io_lsu_iresp_0_bits_uop_prs3_busy; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_ppred_busy_0 = io_lsu_iresp_0_bits_uop_ppred_busy; // @[core.scala:50:7] wire [6:0] io_lsu_iresp_0_bits_uop_stale_pdst_0 = io_lsu_iresp_0_bits_uop_stale_pdst; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_exception_0 = io_lsu_iresp_0_bits_uop_exception; // @[core.scala:50:7] wire [63:0] io_lsu_iresp_0_bits_uop_exc_cause_0 = io_lsu_iresp_0_bits_uop_exc_cause; // @[core.scala:50:7] wire [4:0] io_lsu_iresp_0_bits_uop_mem_cmd_0 = io_lsu_iresp_0_bits_uop_mem_cmd; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_mem_size_0 = io_lsu_iresp_0_bits_uop_mem_size; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_mem_signed_0 = io_lsu_iresp_0_bits_uop_mem_signed; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_uses_ldq_0 = io_lsu_iresp_0_bits_uop_uses_ldq; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_uses_stq_0 = io_lsu_iresp_0_bits_uop_uses_stq; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_is_unique_0 = io_lsu_iresp_0_bits_uop_is_unique; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_flush_on_commit_0 = io_lsu_iresp_0_bits_uop_flush_on_commit; // @[core.scala:50:7] wire [2:0] io_lsu_iresp_0_bits_uop_csr_cmd_0 = io_lsu_iresp_0_bits_uop_csr_cmd; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_ldst_is_rs1_0 = io_lsu_iresp_0_bits_uop_ldst_is_rs1; // @[core.scala:50:7] wire [5:0] io_lsu_iresp_0_bits_uop_ldst_0 = io_lsu_iresp_0_bits_uop_ldst; // @[core.scala:50:7] wire [5:0] io_lsu_iresp_0_bits_uop_lrs1_0 = io_lsu_iresp_0_bits_uop_lrs1; // @[core.scala:50:7] wire [5:0] io_lsu_iresp_0_bits_uop_lrs2_0 = io_lsu_iresp_0_bits_uop_lrs2; // @[core.scala:50:7] wire [5:0] io_lsu_iresp_0_bits_uop_lrs3_0 = io_lsu_iresp_0_bits_uop_lrs3; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_dst_rtype_0 = io_lsu_iresp_0_bits_uop_dst_rtype; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_lrs1_rtype_0 = io_lsu_iresp_0_bits_uop_lrs1_rtype; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_lrs2_rtype_0 = io_lsu_iresp_0_bits_uop_lrs2_rtype; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_frs3_en_0 = io_lsu_iresp_0_bits_uop_frs3_en; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fcn_dw_0 = io_lsu_iresp_0_bits_uop_fcn_dw; // @[core.scala:50:7] wire [4:0] io_lsu_iresp_0_bits_uop_fcn_op_0 = io_lsu_iresp_0_bits_uop_fcn_op; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_fp_val_0 = io_lsu_iresp_0_bits_uop_fp_val; // @[core.scala:50:7] wire [2:0] io_lsu_iresp_0_bits_uop_fp_rm_0 = io_lsu_iresp_0_bits_uop_fp_rm; // @[core.scala:50:7] wire [1:0] io_lsu_iresp_0_bits_uop_fp_typ_0 = io_lsu_iresp_0_bits_uop_fp_typ; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_xcpt_pf_if_0 = io_lsu_iresp_0_bits_uop_xcpt_pf_if; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_xcpt_ae_if_0 = io_lsu_iresp_0_bits_uop_xcpt_ae_if; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_xcpt_ma_if_0 = io_lsu_iresp_0_bits_uop_xcpt_ma_if; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_bp_debug_if_0 = io_lsu_iresp_0_bits_uop_bp_debug_if; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_uop_bp_xcpt_if_0 = io_lsu_iresp_0_bits_uop_bp_xcpt_if; // @[core.scala:50:7] wire [2:0] io_lsu_iresp_0_bits_uop_debug_fsrc_0 = io_lsu_iresp_0_bits_uop_debug_fsrc; // @[core.scala:50:7] wire [2:0] io_lsu_iresp_0_bits_uop_debug_tsrc_0 = io_lsu_iresp_0_bits_uop_debug_tsrc; // @[core.scala:50:7] wire [63:0] io_lsu_iresp_0_bits_data_0 = io_lsu_iresp_0_bits_data; // @[core.scala:50:7] wire io_lsu_fresp_0_valid_0 = io_lsu_fresp_0_valid; // @[core.scala:50:7] wire [31:0] io_lsu_fresp_0_bits_uop_inst_0 = io_lsu_fresp_0_bits_uop_inst; // @[core.scala:50:7] wire [31:0] io_lsu_fresp_0_bits_uop_debug_inst_0 = io_lsu_fresp_0_bits_uop_debug_inst; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_is_rvc_0 = io_lsu_fresp_0_bits_uop_is_rvc; // @[core.scala:50:7] wire [39:0] io_lsu_fresp_0_bits_uop_debug_pc_0 = io_lsu_fresp_0_bits_uop_debug_pc; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_iq_type_0_0 = io_lsu_fresp_0_bits_uop_iq_type_0; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_iq_type_1_0 = io_lsu_fresp_0_bits_uop_iq_type_1; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_iq_type_2_0 = io_lsu_fresp_0_bits_uop_iq_type_2; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_iq_type_3_0 = io_lsu_fresp_0_bits_uop_iq_type_3; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fu_code_0_0 = io_lsu_fresp_0_bits_uop_fu_code_0; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fu_code_1_0 = io_lsu_fresp_0_bits_uop_fu_code_1; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fu_code_2_0 = io_lsu_fresp_0_bits_uop_fu_code_2; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fu_code_3_0 = io_lsu_fresp_0_bits_uop_fu_code_3; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fu_code_4_0 = io_lsu_fresp_0_bits_uop_fu_code_4; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fu_code_5_0 = io_lsu_fresp_0_bits_uop_fu_code_5; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fu_code_6_0 = io_lsu_fresp_0_bits_uop_fu_code_6; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fu_code_7_0 = io_lsu_fresp_0_bits_uop_fu_code_7; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fu_code_8_0 = io_lsu_fresp_0_bits_uop_fu_code_8; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fu_code_9_0 = io_lsu_fresp_0_bits_uop_fu_code_9; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_iw_issued_0 = io_lsu_fresp_0_bits_uop_iw_issued; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_iw_issued_partial_agen_0 = io_lsu_fresp_0_bits_uop_iw_issued_partial_agen; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen_0 = io_lsu_fresp_0_bits_uop_iw_issued_partial_dgen; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_iw_p1_speculative_child_0 = io_lsu_fresp_0_bits_uop_iw_p1_speculative_child; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_iw_p2_speculative_child_0 = io_lsu_fresp_0_bits_uop_iw_p2_speculative_child; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p1_bypass_hint; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p2_bypass_hint; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint_0 = io_lsu_fresp_0_bits_uop_iw_p3_bypass_hint; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_dis_col_sel_0 = io_lsu_fresp_0_bits_uop_dis_col_sel; // @[core.scala:50:7] wire [11:0] io_lsu_fresp_0_bits_uop_br_mask_0 = io_lsu_fresp_0_bits_uop_br_mask; // @[core.scala:50:7] wire [3:0] io_lsu_fresp_0_bits_uop_br_tag_0 = io_lsu_fresp_0_bits_uop_br_tag; // @[core.scala:50:7] wire [3:0] io_lsu_fresp_0_bits_uop_br_type_0 = io_lsu_fresp_0_bits_uop_br_type; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_is_sfb_0 = io_lsu_fresp_0_bits_uop_is_sfb; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_is_fence_0 = io_lsu_fresp_0_bits_uop_is_fence; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_is_fencei_0 = io_lsu_fresp_0_bits_uop_is_fencei; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_is_sfence_0 = io_lsu_fresp_0_bits_uop_is_sfence; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_is_amo_0 = io_lsu_fresp_0_bits_uop_is_amo; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_is_eret_0 = io_lsu_fresp_0_bits_uop_is_eret; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_is_sys_pc2epc_0 = io_lsu_fresp_0_bits_uop_is_sys_pc2epc; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_is_rocc_0 = io_lsu_fresp_0_bits_uop_is_rocc; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_is_mov_0 = io_lsu_fresp_0_bits_uop_is_mov; // @[core.scala:50:7] wire [4:0] io_lsu_fresp_0_bits_uop_ftq_idx_0 = io_lsu_fresp_0_bits_uop_ftq_idx; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_edge_inst_0 = io_lsu_fresp_0_bits_uop_edge_inst; // @[core.scala:50:7] wire [5:0] io_lsu_fresp_0_bits_uop_pc_lob_0 = io_lsu_fresp_0_bits_uop_pc_lob; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_taken_0 = io_lsu_fresp_0_bits_uop_taken; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_imm_rename_0 = io_lsu_fresp_0_bits_uop_imm_rename; // @[core.scala:50:7] wire [2:0] io_lsu_fresp_0_bits_uop_imm_sel_0 = io_lsu_fresp_0_bits_uop_imm_sel; // @[core.scala:50:7] wire [4:0] io_lsu_fresp_0_bits_uop_pimm_0 = io_lsu_fresp_0_bits_uop_pimm; // @[core.scala:50:7] wire [19:0] io_lsu_fresp_0_bits_uop_imm_packed_0 = io_lsu_fresp_0_bits_uop_imm_packed; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_op1_sel_0 = io_lsu_fresp_0_bits_uop_op1_sel; // @[core.scala:50:7] wire [2:0] io_lsu_fresp_0_bits_uop_op2_sel_0 = io_lsu_fresp_0_bits_uop_op2_sel; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ldst_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ldst; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_wen_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_wen; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren1_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren1; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren2_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren2; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_ren3_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_ren3; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_swap12_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_swap12; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_swap23_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_swap23; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_fromint_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fromint; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_toint_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_toint; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fastpipe; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_fma_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_fma; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_div_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_div; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_sqrt; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_wflags_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_wflags; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_ctrl_vec_0 = io_lsu_fresp_0_bits_uop_fp_ctrl_vec; // @[core.scala:50:7] wire [5:0] io_lsu_fresp_0_bits_uop_rob_idx_0 = io_lsu_fresp_0_bits_uop_rob_idx; // @[core.scala:50:7] wire [3:0] io_lsu_fresp_0_bits_uop_ldq_idx_0 = io_lsu_fresp_0_bits_uop_ldq_idx; // @[core.scala:50:7] wire [3:0] io_lsu_fresp_0_bits_uop_stq_idx_0 = io_lsu_fresp_0_bits_uop_stq_idx; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_rxq_idx_0 = io_lsu_fresp_0_bits_uop_rxq_idx; // @[core.scala:50:7] wire [6:0] io_lsu_fresp_0_bits_uop_pdst_0 = io_lsu_fresp_0_bits_uop_pdst; // @[core.scala:50:7] wire [6:0] io_lsu_fresp_0_bits_uop_prs1_0 = io_lsu_fresp_0_bits_uop_prs1; // @[core.scala:50:7] wire [6:0] io_lsu_fresp_0_bits_uop_prs2_0 = io_lsu_fresp_0_bits_uop_prs2; // @[core.scala:50:7] wire [6:0] io_lsu_fresp_0_bits_uop_prs3_0 = io_lsu_fresp_0_bits_uop_prs3; // @[core.scala:50:7] wire [4:0] io_lsu_fresp_0_bits_uop_ppred_0 = io_lsu_fresp_0_bits_uop_ppred; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_prs1_busy_0 = io_lsu_fresp_0_bits_uop_prs1_busy; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_prs2_busy_0 = io_lsu_fresp_0_bits_uop_prs2_busy; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_prs3_busy_0 = io_lsu_fresp_0_bits_uop_prs3_busy; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_ppred_busy_0 = io_lsu_fresp_0_bits_uop_ppred_busy; // @[core.scala:50:7] wire [6:0] io_lsu_fresp_0_bits_uop_stale_pdst_0 = io_lsu_fresp_0_bits_uop_stale_pdst; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_exception_0 = io_lsu_fresp_0_bits_uop_exception; // @[core.scala:50:7] wire [63:0] io_lsu_fresp_0_bits_uop_exc_cause_0 = io_lsu_fresp_0_bits_uop_exc_cause; // @[core.scala:50:7] wire [4:0] io_lsu_fresp_0_bits_uop_mem_cmd_0 = io_lsu_fresp_0_bits_uop_mem_cmd; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_mem_size_0 = io_lsu_fresp_0_bits_uop_mem_size; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_mem_signed_0 = io_lsu_fresp_0_bits_uop_mem_signed; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_uses_ldq_0 = io_lsu_fresp_0_bits_uop_uses_ldq; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_uses_stq_0 = io_lsu_fresp_0_bits_uop_uses_stq; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_is_unique_0 = io_lsu_fresp_0_bits_uop_is_unique; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_flush_on_commit_0 = io_lsu_fresp_0_bits_uop_flush_on_commit; // @[core.scala:50:7] wire [2:0] io_lsu_fresp_0_bits_uop_csr_cmd_0 = io_lsu_fresp_0_bits_uop_csr_cmd; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_ldst_is_rs1_0 = io_lsu_fresp_0_bits_uop_ldst_is_rs1; // @[core.scala:50:7] wire [5:0] io_lsu_fresp_0_bits_uop_ldst_0 = io_lsu_fresp_0_bits_uop_ldst; // @[core.scala:50:7] wire [5:0] io_lsu_fresp_0_bits_uop_lrs1_0 = io_lsu_fresp_0_bits_uop_lrs1; // @[core.scala:50:7] wire [5:0] io_lsu_fresp_0_bits_uop_lrs2_0 = io_lsu_fresp_0_bits_uop_lrs2; // @[core.scala:50:7] wire [5:0] io_lsu_fresp_0_bits_uop_lrs3_0 = io_lsu_fresp_0_bits_uop_lrs3; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_dst_rtype_0 = io_lsu_fresp_0_bits_uop_dst_rtype; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_lrs1_rtype_0 = io_lsu_fresp_0_bits_uop_lrs1_rtype; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_lrs2_rtype_0 = io_lsu_fresp_0_bits_uop_lrs2_rtype; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_frs3_en_0 = io_lsu_fresp_0_bits_uop_frs3_en; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fcn_dw_0 = io_lsu_fresp_0_bits_uop_fcn_dw; // @[core.scala:50:7] wire [4:0] io_lsu_fresp_0_bits_uop_fcn_op_0 = io_lsu_fresp_0_bits_uop_fcn_op; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_fp_val_0 = io_lsu_fresp_0_bits_uop_fp_val; // @[core.scala:50:7] wire [2:0] io_lsu_fresp_0_bits_uop_fp_rm_0 = io_lsu_fresp_0_bits_uop_fp_rm; // @[core.scala:50:7] wire [1:0] io_lsu_fresp_0_bits_uop_fp_typ_0 = io_lsu_fresp_0_bits_uop_fp_typ; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_xcpt_pf_if_0 = io_lsu_fresp_0_bits_uop_xcpt_pf_if; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_xcpt_ae_if_0 = io_lsu_fresp_0_bits_uop_xcpt_ae_if; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_xcpt_ma_if_0 = io_lsu_fresp_0_bits_uop_xcpt_ma_if; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_bp_debug_if_0 = io_lsu_fresp_0_bits_uop_bp_debug_if; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_uop_bp_xcpt_if_0 = io_lsu_fresp_0_bits_uop_bp_xcpt_if; // @[core.scala:50:7] wire [2:0] io_lsu_fresp_0_bits_uop_debug_fsrc_0 = io_lsu_fresp_0_bits_uop_debug_fsrc; // @[core.scala:50:7] wire [2:0] io_lsu_fresp_0_bits_uop_debug_tsrc_0 = io_lsu_fresp_0_bits_uop_debug_tsrc; // @[core.scala:50:7] wire [63:0] io_lsu_fresp_0_bits_data_0 = io_lsu_fresp_0_bits_data; // @[core.scala:50:7] wire [3:0] io_lsu_dis_ldq_idx_0_0 = io_lsu_dis_ldq_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dis_ldq_idx_1_0 = io_lsu_dis_ldq_idx_1; // @[core.scala:50:7] wire [3:0] io_lsu_dis_stq_idx_0_0 = io_lsu_dis_stq_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dis_stq_idx_1_0 = io_lsu_dis_stq_idx_1; // @[core.scala:50:7] wire io_lsu_ldq_full_0_0 = io_lsu_ldq_full_0; // @[core.scala:50:7] wire io_lsu_ldq_full_1_0 = io_lsu_ldq_full_1; // @[core.scala:50:7] wire io_lsu_stq_full_0_0 = io_lsu_stq_full_0; // @[core.scala:50:7] wire io_lsu_stq_full_1_0 = io_lsu_stq_full_1; // @[core.scala:50:7] wire io_lsu_clr_bsy_0_valid_0 = io_lsu_clr_bsy_0_valid; // @[core.scala:50:7] wire [5:0] io_lsu_clr_bsy_0_bits_0 = io_lsu_clr_bsy_0_bits; // @[core.scala:50:7] wire io_lsu_clr_bsy_1_valid_0 = io_lsu_clr_bsy_1_valid; // @[core.scala:50:7] wire [5:0] io_lsu_clr_bsy_1_bits_0 = io_lsu_clr_bsy_1_bits; // @[core.scala:50:7] wire io_lsu_clr_unsafe_0_valid_0 = io_lsu_clr_unsafe_0_valid; // @[core.scala:50:7] wire [5:0] io_lsu_clr_unsafe_0_bits_0 = io_lsu_clr_unsafe_0_bits; // @[core.scala:50:7] wire io_lsu_fencei_rdy_0 = io_lsu_fencei_rdy; // @[core.scala:50:7] wire io_lsu_lxcpt_valid_0 = io_lsu_lxcpt_valid; // @[core.scala:50:7] wire [31:0] io_lsu_lxcpt_bits_uop_inst_0 = io_lsu_lxcpt_bits_uop_inst; // @[core.scala:50:7] wire [31:0] io_lsu_lxcpt_bits_uop_debug_inst_0 = io_lsu_lxcpt_bits_uop_debug_inst; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_is_rvc_0 = io_lsu_lxcpt_bits_uop_is_rvc; // @[core.scala:50:7] wire [39:0] io_lsu_lxcpt_bits_uop_debug_pc_0 = io_lsu_lxcpt_bits_uop_debug_pc; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_iq_type_0_0 = io_lsu_lxcpt_bits_uop_iq_type_0; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_iq_type_1_0 = io_lsu_lxcpt_bits_uop_iq_type_1; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_iq_type_2_0 = io_lsu_lxcpt_bits_uop_iq_type_2; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_iq_type_3_0 = io_lsu_lxcpt_bits_uop_iq_type_3; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fu_code_0_0 = io_lsu_lxcpt_bits_uop_fu_code_0; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fu_code_1_0 = io_lsu_lxcpt_bits_uop_fu_code_1; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fu_code_2_0 = io_lsu_lxcpt_bits_uop_fu_code_2; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fu_code_3_0 = io_lsu_lxcpt_bits_uop_fu_code_3; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fu_code_4_0 = io_lsu_lxcpt_bits_uop_fu_code_4; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fu_code_5_0 = io_lsu_lxcpt_bits_uop_fu_code_5; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fu_code_6_0 = io_lsu_lxcpt_bits_uop_fu_code_6; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fu_code_7_0 = io_lsu_lxcpt_bits_uop_fu_code_7; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fu_code_8_0 = io_lsu_lxcpt_bits_uop_fu_code_8; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fu_code_9_0 = io_lsu_lxcpt_bits_uop_fu_code_9; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_iw_issued_0 = io_lsu_lxcpt_bits_uop_iw_issued; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_iw_issued_partial_agen_0 = io_lsu_lxcpt_bits_uop_iw_issued_partial_agen; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen_0 = io_lsu_lxcpt_bits_uop_iw_issued_partial_dgen; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_iw_p1_speculative_child_0 = io_lsu_lxcpt_bits_uop_iw_p1_speculative_child; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_iw_p2_speculative_child_0 = io_lsu_lxcpt_bits_uop_iw_p2_speculative_child; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p1_bypass_hint; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p2_bypass_hint; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint_0 = io_lsu_lxcpt_bits_uop_iw_p3_bypass_hint; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_dis_col_sel_0 = io_lsu_lxcpt_bits_uop_dis_col_sel; // @[core.scala:50:7] wire [11:0] io_lsu_lxcpt_bits_uop_br_mask_0 = io_lsu_lxcpt_bits_uop_br_mask; // @[core.scala:50:7] wire [3:0] io_lsu_lxcpt_bits_uop_br_tag_0 = io_lsu_lxcpt_bits_uop_br_tag; // @[core.scala:50:7] wire [3:0] io_lsu_lxcpt_bits_uop_br_type_0 = io_lsu_lxcpt_bits_uop_br_type; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_is_sfb_0 = io_lsu_lxcpt_bits_uop_is_sfb; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_is_fence_0 = io_lsu_lxcpt_bits_uop_is_fence; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_is_fencei_0 = io_lsu_lxcpt_bits_uop_is_fencei; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_is_sfence_0 = io_lsu_lxcpt_bits_uop_is_sfence; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_is_amo_0 = io_lsu_lxcpt_bits_uop_is_amo; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_is_eret_0 = io_lsu_lxcpt_bits_uop_is_eret; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_is_sys_pc2epc_0 = io_lsu_lxcpt_bits_uop_is_sys_pc2epc; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_is_rocc_0 = io_lsu_lxcpt_bits_uop_is_rocc; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_is_mov_0 = io_lsu_lxcpt_bits_uop_is_mov; // @[core.scala:50:7] wire [4:0] io_lsu_lxcpt_bits_uop_ftq_idx_0 = io_lsu_lxcpt_bits_uop_ftq_idx; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_edge_inst_0 = io_lsu_lxcpt_bits_uop_edge_inst; // @[core.scala:50:7] wire [5:0] io_lsu_lxcpt_bits_uop_pc_lob_0 = io_lsu_lxcpt_bits_uop_pc_lob; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_taken_0 = io_lsu_lxcpt_bits_uop_taken; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_imm_rename_0 = io_lsu_lxcpt_bits_uop_imm_rename; // @[core.scala:50:7] wire [2:0] io_lsu_lxcpt_bits_uop_imm_sel_0 = io_lsu_lxcpt_bits_uop_imm_sel; // @[core.scala:50:7] wire [4:0] io_lsu_lxcpt_bits_uop_pimm_0 = io_lsu_lxcpt_bits_uop_pimm; // @[core.scala:50:7] wire [19:0] io_lsu_lxcpt_bits_uop_imm_packed_0 = io_lsu_lxcpt_bits_uop_imm_packed; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_op1_sel_0 = io_lsu_lxcpt_bits_uop_op1_sel; // @[core.scala:50:7] wire [2:0] io_lsu_lxcpt_bits_uop_op2_sel_0 = io_lsu_lxcpt_bits_uop_op2_sel; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ldst_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ldst; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_wen_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_wen; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren1_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren1; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren2_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren2; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_ren3_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_ren3; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_swap12_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_swap12; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_swap23_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_swap23; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_fromint_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fromint; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_toint_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_toint; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fastpipe; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_fma_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_fma; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_div_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_div; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_sqrt; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_wflags_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_wflags; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_ctrl_vec_0 = io_lsu_lxcpt_bits_uop_fp_ctrl_vec; // @[core.scala:50:7] wire [5:0] io_lsu_lxcpt_bits_uop_rob_idx_0 = io_lsu_lxcpt_bits_uop_rob_idx; // @[core.scala:50:7] wire [3:0] io_lsu_lxcpt_bits_uop_ldq_idx_0 = io_lsu_lxcpt_bits_uop_ldq_idx; // @[core.scala:50:7] wire [3:0] io_lsu_lxcpt_bits_uop_stq_idx_0 = io_lsu_lxcpt_bits_uop_stq_idx; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_rxq_idx_0 = io_lsu_lxcpt_bits_uop_rxq_idx; // @[core.scala:50:7] wire [6:0] io_lsu_lxcpt_bits_uop_pdst_0 = io_lsu_lxcpt_bits_uop_pdst; // @[core.scala:50:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs1_0 = io_lsu_lxcpt_bits_uop_prs1; // @[core.scala:50:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs2_0 = io_lsu_lxcpt_bits_uop_prs2; // @[core.scala:50:7] wire [6:0] io_lsu_lxcpt_bits_uop_prs3_0 = io_lsu_lxcpt_bits_uop_prs3; // @[core.scala:50:7] wire [4:0] io_lsu_lxcpt_bits_uop_ppred_0 = io_lsu_lxcpt_bits_uop_ppred; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_prs1_busy_0 = io_lsu_lxcpt_bits_uop_prs1_busy; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_prs2_busy_0 = io_lsu_lxcpt_bits_uop_prs2_busy; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_prs3_busy_0 = io_lsu_lxcpt_bits_uop_prs3_busy; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_ppred_busy_0 = io_lsu_lxcpt_bits_uop_ppred_busy; // @[core.scala:50:7] wire [6:0] io_lsu_lxcpt_bits_uop_stale_pdst_0 = io_lsu_lxcpt_bits_uop_stale_pdst; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_exception_0 = io_lsu_lxcpt_bits_uop_exception; // @[core.scala:50:7] wire [63:0] io_lsu_lxcpt_bits_uop_exc_cause_0 = io_lsu_lxcpt_bits_uop_exc_cause; // @[core.scala:50:7] wire [4:0] io_lsu_lxcpt_bits_uop_mem_cmd_0 = io_lsu_lxcpt_bits_uop_mem_cmd; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_mem_size_0 = io_lsu_lxcpt_bits_uop_mem_size; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_mem_signed_0 = io_lsu_lxcpt_bits_uop_mem_signed; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_uses_ldq_0 = io_lsu_lxcpt_bits_uop_uses_ldq; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_uses_stq_0 = io_lsu_lxcpt_bits_uop_uses_stq; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_is_unique_0 = io_lsu_lxcpt_bits_uop_is_unique; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_flush_on_commit_0 = io_lsu_lxcpt_bits_uop_flush_on_commit; // @[core.scala:50:7] wire [2:0] io_lsu_lxcpt_bits_uop_csr_cmd_0 = io_lsu_lxcpt_bits_uop_csr_cmd; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_ldst_is_rs1_0 = io_lsu_lxcpt_bits_uop_ldst_is_rs1; // @[core.scala:50:7] wire [5:0] io_lsu_lxcpt_bits_uop_ldst_0 = io_lsu_lxcpt_bits_uop_ldst; // @[core.scala:50:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs1_0 = io_lsu_lxcpt_bits_uop_lrs1; // @[core.scala:50:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs2_0 = io_lsu_lxcpt_bits_uop_lrs2; // @[core.scala:50:7] wire [5:0] io_lsu_lxcpt_bits_uop_lrs3_0 = io_lsu_lxcpt_bits_uop_lrs3; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_dst_rtype_0 = io_lsu_lxcpt_bits_uop_dst_rtype; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs1_rtype_0 = io_lsu_lxcpt_bits_uop_lrs1_rtype; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_lrs2_rtype_0 = io_lsu_lxcpt_bits_uop_lrs2_rtype; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_frs3_en_0 = io_lsu_lxcpt_bits_uop_frs3_en; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fcn_dw_0 = io_lsu_lxcpt_bits_uop_fcn_dw; // @[core.scala:50:7] wire [4:0] io_lsu_lxcpt_bits_uop_fcn_op_0 = io_lsu_lxcpt_bits_uop_fcn_op; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_fp_val_0 = io_lsu_lxcpt_bits_uop_fp_val; // @[core.scala:50:7] wire [2:0] io_lsu_lxcpt_bits_uop_fp_rm_0 = io_lsu_lxcpt_bits_uop_fp_rm; // @[core.scala:50:7] wire [1:0] io_lsu_lxcpt_bits_uop_fp_typ_0 = io_lsu_lxcpt_bits_uop_fp_typ; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_xcpt_pf_if_0 = io_lsu_lxcpt_bits_uop_xcpt_pf_if; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_xcpt_ae_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ae_if; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_xcpt_ma_if_0 = io_lsu_lxcpt_bits_uop_xcpt_ma_if; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_bp_debug_if_0 = io_lsu_lxcpt_bits_uop_bp_debug_if; // @[core.scala:50:7] wire io_lsu_lxcpt_bits_uop_bp_xcpt_if_0 = io_lsu_lxcpt_bits_uop_bp_xcpt_if; // @[core.scala:50:7] wire [2:0] io_lsu_lxcpt_bits_uop_debug_fsrc_0 = io_lsu_lxcpt_bits_uop_debug_fsrc; // @[core.scala:50:7] wire [2:0] io_lsu_lxcpt_bits_uop_debug_tsrc_0 = io_lsu_lxcpt_bits_uop_debug_tsrc; // @[core.scala:50:7] wire [4:0] io_lsu_lxcpt_bits_cause_0 = io_lsu_lxcpt_bits_cause; // @[core.scala:50:7] wire [39:0] io_lsu_lxcpt_bits_badvaddr_0 = io_lsu_lxcpt_bits_badvaddr; // @[core.scala:50:7] wire io_lsu_perf_acquire_0 = io_lsu_perf_acquire; // @[core.scala:50:7] wire io_lsu_perf_release_0 = io_lsu_perf_release; // @[core.scala:50:7] wire io_lsu_perf_tlbMiss_0 = io_lsu_perf_tlbMiss; // @[core.scala:50:7] wire io_ptw_tlb_req_ready_0 = io_ptw_tlb_req_ready; // @[core.scala:50:7] wire io_ptw_tlb_resp_valid_0 = io_ptw_tlb_resp_valid; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_ae_ptw_0 = io_ptw_tlb_resp_bits_ae_ptw; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_ae_final_0 = io_ptw_tlb_resp_bits_ae_final; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_pf_0 = io_ptw_tlb_resp_bits_pf; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_gf_0 = io_ptw_tlb_resp_bits_gf; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_hr_0 = io_ptw_tlb_resp_bits_hr; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_hw_0 = io_ptw_tlb_resp_bits_hw; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_hx_0 = io_ptw_tlb_resp_bits_hx; // @[core.scala:50:7] wire [9:0] io_ptw_tlb_resp_bits_pte_reserved_for_future_0 = io_ptw_tlb_resp_bits_pte_reserved_for_future; // @[core.scala:50:7] wire [43:0] io_ptw_tlb_resp_bits_pte_ppn_0 = io_ptw_tlb_resp_bits_pte_ppn; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_resp_bits_pte_reserved_for_software_0 = io_ptw_tlb_resp_bits_pte_reserved_for_software; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_pte_d_0 = io_ptw_tlb_resp_bits_pte_d; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_pte_a_0 = io_ptw_tlb_resp_bits_pte_a; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_pte_g_0 = io_ptw_tlb_resp_bits_pte_g; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_pte_u_0 = io_ptw_tlb_resp_bits_pte_u; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_pte_x_0 = io_ptw_tlb_resp_bits_pte_x; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_pte_w_0 = io_ptw_tlb_resp_bits_pte_w; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_pte_r_0 = io_ptw_tlb_resp_bits_pte_r; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_pte_v_0 = io_ptw_tlb_resp_bits_pte_v; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_resp_bits_level_0 = io_ptw_tlb_resp_bits_level; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_homogeneous_0 = io_ptw_tlb_resp_bits_homogeneous; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_gpa_valid_0 = io_ptw_tlb_resp_bits_gpa_valid; // @[core.scala:50:7] wire [38:0] io_ptw_tlb_resp_bits_gpa_bits_0 = io_ptw_tlb_resp_bits_gpa_bits; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_gpa_is_pte_0 = io_ptw_tlb_resp_bits_gpa_is_pte; // @[core.scala:50:7] wire [3:0] io_ptw_tlb_ptbr_mode_0 = io_ptw_tlb_ptbr_mode; // @[core.scala:50:7] wire [43:0] io_ptw_tlb_ptbr_ppn_0 = io_ptw_tlb_ptbr_ppn; // @[core.scala:50:7] wire io_ptw_tlb_status_debug_0 = io_ptw_tlb_status_debug; // @[core.scala:50:7] wire io_ptw_tlb_status_cease_0 = io_ptw_tlb_status_cease; // @[core.scala:50:7] wire io_ptw_tlb_status_wfi_0 = io_ptw_tlb_status_wfi; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_status_dprv_0 = io_ptw_tlb_status_dprv; // @[core.scala:50:7] wire io_ptw_tlb_status_dv_0 = io_ptw_tlb_status_dv; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_status_prv_0 = io_ptw_tlb_status_prv; // @[core.scala:50:7] wire io_ptw_tlb_status_v_0 = io_ptw_tlb_status_v; // @[core.scala:50:7] wire io_ptw_tlb_status_sd_0 = io_ptw_tlb_status_sd; // @[core.scala:50:7] wire io_ptw_tlb_status_mpv_0 = io_ptw_tlb_status_mpv; // @[core.scala:50:7] wire io_ptw_tlb_status_gva_0 = io_ptw_tlb_status_gva; // @[core.scala:50:7] wire io_ptw_tlb_status_tsr_0 = io_ptw_tlb_status_tsr; // @[core.scala:50:7] wire io_ptw_tlb_status_tw_0 = io_ptw_tlb_status_tw; // @[core.scala:50:7] wire io_ptw_tlb_status_tvm_0 = io_ptw_tlb_status_tvm; // @[core.scala:50:7] wire io_ptw_tlb_status_mxr_0 = io_ptw_tlb_status_mxr; // @[core.scala:50:7] wire io_ptw_tlb_status_sum_0 = io_ptw_tlb_status_sum; // @[core.scala:50:7] wire io_ptw_tlb_status_mprv_0 = io_ptw_tlb_status_mprv; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_status_fs_0 = io_ptw_tlb_status_fs; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_status_mpp_0 = io_ptw_tlb_status_mpp; // @[core.scala:50:7] wire io_ptw_tlb_status_spp_0 = io_ptw_tlb_status_spp; // @[core.scala:50:7] wire io_ptw_tlb_status_mpie_0 = io_ptw_tlb_status_mpie; // @[core.scala:50:7] wire io_ptw_tlb_status_spie_0 = io_ptw_tlb_status_spie; // @[core.scala:50:7] wire io_ptw_tlb_status_mie_0 = io_ptw_tlb_status_mie; // @[core.scala:50:7] wire io_ptw_tlb_status_sie_0 = io_ptw_tlb_status_sie; // @[core.scala:50:7] wire io_ptw_tlb_pmp_0_cfg_l_0 = io_ptw_tlb_pmp_0_cfg_l; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_0_cfg_a_0 = io_ptw_tlb_pmp_0_cfg_a; // @[core.scala:50:7] wire io_ptw_tlb_pmp_0_cfg_x_0 = io_ptw_tlb_pmp_0_cfg_x; // @[core.scala:50:7] wire io_ptw_tlb_pmp_0_cfg_w_0 = io_ptw_tlb_pmp_0_cfg_w; // @[core.scala:50:7] wire io_ptw_tlb_pmp_0_cfg_r_0 = io_ptw_tlb_pmp_0_cfg_r; // @[core.scala:50:7] wire [29:0] io_ptw_tlb_pmp_0_addr_0 = io_ptw_tlb_pmp_0_addr; // @[core.scala:50:7] wire [31:0] io_ptw_tlb_pmp_0_mask_0 = io_ptw_tlb_pmp_0_mask; // @[core.scala:50:7] wire io_ptw_tlb_pmp_1_cfg_l_0 = io_ptw_tlb_pmp_1_cfg_l; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_1_cfg_a_0 = io_ptw_tlb_pmp_1_cfg_a; // @[core.scala:50:7] wire io_ptw_tlb_pmp_1_cfg_x_0 = io_ptw_tlb_pmp_1_cfg_x; // @[core.scala:50:7] wire io_ptw_tlb_pmp_1_cfg_w_0 = io_ptw_tlb_pmp_1_cfg_w; // @[core.scala:50:7] wire io_ptw_tlb_pmp_1_cfg_r_0 = io_ptw_tlb_pmp_1_cfg_r; // @[core.scala:50:7] wire [29:0] io_ptw_tlb_pmp_1_addr_0 = io_ptw_tlb_pmp_1_addr; // @[core.scala:50:7] wire [31:0] io_ptw_tlb_pmp_1_mask_0 = io_ptw_tlb_pmp_1_mask; // @[core.scala:50:7] wire io_ptw_tlb_pmp_2_cfg_l_0 = io_ptw_tlb_pmp_2_cfg_l; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_2_cfg_a_0 = io_ptw_tlb_pmp_2_cfg_a; // @[core.scala:50:7] wire io_ptw_tlb_pmp_2_cfg_x_0 = io_ptw_tlb_pmp_2_cfg_x; // @[core.scala:50:7] wire io_ptw_tlb_pmp_2_cfg_w_0 = io_ptw_tlb_pmp_2_cfg_w; // @[core.scala:50:7] wire io_ptw_tlb_pmp_2_cfg_r_0 = io_ptw_tlb_pmp_2_cfg_r; // @[core.scala:50:7] wire [29:0] io_ptw_tlb_pmp_2_addr_0 = io_ptw_tlb_pmp_2_addr; // @[core.scala:50:7] wire [31:0] io_ptw_tlb_pmp_2_mask_0 = io_ptw_tlb_pmp_2_mask; // @[core.scala:50:7] wire io_ptw_tlb_pmp_3_cfg_l_0 = io_ptw_tlb_pmp_3_cfg_l; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_3_cfg_a_0 = io_ptw_tlb_pmp_3_cfg_a; // @[core.scala:50:7] wire io_ptw_tlb_pmp_3_cfg_x_0 = io_ptw_tlb_pmp_3_cfg_x; // @[core.scala:50:7] wire io_ptw_tlb_pmp_3_cfg_w_0 = io_ptw_tlb_pmp_3_cfg_w; // @[core.scala:50:7] wire io_ptw_tlb_pmp_3_cfg_r_0 = io_ptw_tlb_pmp_3_cfg_r; // @[core.scala:50:7] wire [29:0] io_ptw_tlb_pmp_3_addr_0 = io_ptw_tlb_pmp_3_addr; // @[core.scala:50:7] wire [31:0] io_ptw_tlb_pmp_3_mask_0 = io_ptw_tlb_pmp_3_mask; // @[core.scala:50:7] wire io_ptw_tlb_pmp_4_cfg_l_0 = io_ptw_tlb_pmp_4_cfg_l; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_4_cfg_a_0 = io_ptw_tlb_pmp_4_cfg_a; // @[core.scala:50:7] wire io_ptw_tlb_pmp_4_cfg_x_0 = io_ptw_tlb_pmp_4_cfg_x; // @[core.scala:50:7] wire io_ptw_tlb_pmp_4_cfg_w_0 = io_ptw_tlb_pmp_4_cfg_w; // @[core.scala:50:7] wire io_ptw_tlb_pmp_4_cfg_r_0 = io_ptw_tlb_pmp_4_cfg_r; // @[core.scala:50:7] wire [29:0] io_ptw_tlb_pmp_4_addr_0 = io_ptw_tlb_pmp_4_addr; // @[core.scala:50:7] wire [31:0] io_ptw_tlb_pmp_4_mask_0 = io_ptw_tlb_pmp_4_mask; // @[core.scala:50:7] wire io_ptw_tlb_pmp_5_cfg_l_0 = io_ptw_tlb_pmp_5_cfg_l; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_5_cfg_a_0 = io_ptw_tlb_pmp_5_cfg_a; // @[core.scala:50:7] wire io_ptw_tlb_pmp_5_cfg_x_0 = io_ptw_tlb_pmp_5_cfg_x; // @[core.scala:50:7] wire io_ptw_tlb_pmp_5_cfg_w_0 = io_ptw_tlb_pmp_5_cfg_w; // @[core.scala:50:7] wire io_ptw_tlb_pmp_5_cfg_r_0 = io_ptw_tlb_pmp_5_cfg_r; // @[core.scala:50:7] wire [29:0] io_ptw_tlb_pmp_5_addr_0 = io_ptw_tlb_pmp_5_addr; // @[core.scala:50:7] wire [31:0] io_ptw_tlb_pmp_5_mask_0 = io_ptw_tlb_pmp_5_mask; // @[core.scala:50:7] wire io_ptw_tlb_pmp_6_cfg_l_0 = io_ptw_tlb_pmp_6_cfg_l; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_6_cfg_a_0 = io_ptw_tlb_pmp_6_cfg_a; // @[core.scala:50:7] wire io_ptw_tlb_pmp_6_cfg_x_0 = io_ptw_tlb_pmp_6_cfg_x; // @[core.scala:50:7] wire io_ptw_tlb_pmp_6_cfg_w_0 = io_ptw_tlb_pmp_6_cfg_w; // @[core.scala:50:7] wire io_ptw_tlb_pmp_6_cfg_r_0 = io_ptw_tlb_pmp_6_cfg_r; // @[core.scala:50:7] wire [29:0] io_ptw_tlb_pmp_6_addr_0 = io_ptw_tlb_pmp_6_addr; // @[core.scala:50:7] wire [31:0] io_ptw_tlb_pmp_6_mask_0 = io_ptw_tlb_pmp_6_mask; // @[core.scala:50:7] wire io_ptw_tlb_pmp_7_cfg_l_0 = io_ptw_tlb_pmp_7_cfg_l; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_7_cfg_a_0 = io_ptw_tlb_pmp_7_cfg_a; // @[core.scala:50:7] wire io_ptw_tlb_pmp_7_cfg_x_0 = io_ptw_tlb_pmp_7_cfg_x; // @[core.scala:50:7] wire io_ptw_tlb_pmp_7_cfg_w_0 = io_ptw_tlb_pmp_7_cfg_w; // @[core.scala:50:7] wire io_ptw_tlb_pmp_7_cfg_r_0 = io_ptw_tlb_pmp_7_cfg_r; // @[core.scala:50:7] wire [29:0] io_ptw_tlb_pmp_7_addr_0 = io_ptw_tlb_pmp_7_addr; // @[core.scala:50:7] wire [31:0] io_ptw_tlb_pmp_7_mask_0 = io_ptw_tlb_pmp_7_mask; // @[core.scala:50:7] wire coreMonitorBundle_clock = clock; // @[core.scala:1347:31] wire coreMonitorBundle_reset = reset; // @[core.scala:1347:31] wire io_ifu_fetchpacket_bits_uops_0_bits_iq_type_0 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iq_type_1 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iq_type_2 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iq_type_3 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fu_code_0 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fu_code_1 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fu_code_2 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fu_code_3 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fu_code_4 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fu_code_5 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fu_code_6 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fu_code_7 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fu_code_8 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fu_code_9 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iw_issued = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iw_issued_partial_agen = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iw_issued_partial_dgen = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p1_bypass_hint = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p2_bypass_hint = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_iw_p3_bypass_hint = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_fence = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_fencei = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_sfence = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_amo = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_eret = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_sys_pc2epc = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_rocc = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_mov = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_imm_rename = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_ldst = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_wen = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_ren1 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_ren2 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_ren3 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_swap12 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_swap23 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_fromint = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_toint = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_fastpipe = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_fma = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_div = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_sqrt = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_wflags = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_vec = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_prs1_busy = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_prs2_busy = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_prs3_busy = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ppred_busy = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_exception = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_mem_signed = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_uses_ldq = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_uses_stq = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_is_unique = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_flush_on_commit = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_ldst_is_rs1 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_frs3_en = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fcn_dw = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_fp_val = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_0_bits_xcpt_ma_if = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iq_type_0 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iq_type_1 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iq_type_2 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iq_type_3 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fu_code_0 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fu_code_1 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fu_code_2 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fu_code_3 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fu_code_4 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fu_code_5 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fu_code_6 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fu_code_7 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fu_code_8 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fu_code_9 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iw_issued = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iw_issued_partial_agen = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iw_issued_partial_dgen = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iw_p1_bypass_hint = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iw_p2_bypass_hint = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_iw_p3_bypass_hint = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_fence = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_fencei = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_sfence = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_amo = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_eret = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_sys_pc2epc = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_rocc = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_mov = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_imm_rename = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_ldst = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_wen = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_ren1 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_ren2 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_ren3 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_swap12 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_swap23 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_fromint = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_toint = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_fastpipe = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_fma = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_div = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_sqrt = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_wflags = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_vec = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_prs1_busy = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_prs2_busy = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_prs3_busy = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ppred_busy = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_exception = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_mem_signed = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_uses_ldq = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_uses_stq = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_is_unique = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_flush_on_commit = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_ldst_is_rs1 = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_frs3_en = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fcn_dw = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_fp_val = 1'h0; // @[core.scala:50:7] wire io_ifu_fetchpacket_bits_uops_1_bits_xcpt_ma_if = 1'h0; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_1_ghist_current_saw_branch_not_taken = 1'h0; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_1_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_1_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_2_ghist_current_saw_branch_not_taken = 1'h0; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_2_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:50:7] wire io_ifu_rrd_ftq_resps_2_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:50:7] wire io_ifu_status_mbe = 1'h0; // @[core.scala:50:7] wire io_ifu_status_sbe = 1'h0; // @[core.scala:50:7] wire io_ifu_status_sd_rv32 = 1'h0; // @[core.scala:50:7] wire io_ifu_status_ube = 1'h0; // @[core.scala:50:7] wire io_ifu_status_upie = 1'h0; // @[core.scala:50:7] wire io_ifu_status_hie = 1'h0; // @[core.scala:50:7] wire io_ifu_status_uie = 1'h0; // @[core.scala:50:7] wire io_ptw_status_mbe = 1'h0; // @[core.scala:50:7] wire io_ptw_status_sbe = 1'h0; // @[core.scala:50:7] wire io_ptw_status_sd_rv32 = 1'h0; // @[core.scala:50:7] wire io_ptw_status_ube = 1'h0; // @[core.scala:50:7] wire io_ptw_status_upie = 1'h0; // @[core.scala:50:7] wire io_ptw_status_hie = 1'h0; // @[core.scala:50:7] wire io_ptw_status_uie = 1'h0; // @[core.scala:50:7] wire io_ptw_hstatus_vtsr = 1'h0; // @[core.scala:50:7] wire io_ptw_hstatus_vtw = 1'h0; // @[core.scala:50:7] wire io_ptw_hstatus_vtvm = 1'h0; // @[core.scala:50:7] wire io_ptw_hstatus_hu = 1'h0; // @[core.scala:50:7] wire io_ptw_hstatus_spvp = 1'h0; // @[core.scala:50:7] wire io_ptw_hstatus_spv = 1'h0; // @[core.scala:50:7] wire io_ptw_hstatus_gva = 1'h0; // @[core.scala:50:7] wire io_ptw_hstatus_vsbe = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_debug = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_cease = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_wfi = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_dv = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_v = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_sd = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_mpv = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_gva = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_mbe = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_sbe = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_sd_rv32 = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_tsr = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_tw = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_tvm = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_mxr = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_sum = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_mprv = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_spp = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_mpie = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_ube = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_spie = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_upie = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_mie = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_hie = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_sie = 1'h0; // @[core.scala:50:7] wire io_ptw_gstatus_uie = 1'h0; // @[core.scala:50:7] wire io_ptw_perf_pte_hit = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_0_ren = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_0_wen = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_0_stall = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_0_set = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_1_ren = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_1_wen = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_1_stall = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_1_set = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_2_ren = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_2_wen = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_2_stall = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_2_set = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_3_ren = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_3_wen = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_3_stall = 1'h0; // @[core.scala:50:7] wire io_ptw_customCSRs_csrs_3_set = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_ready = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_valid = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_inst_xd = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_inst_xs1 = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_inst_xs2 = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_debug = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_cease = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_wfi = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_dv = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_v = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_sd = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_mpv = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_gva = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_mbe = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_sbe = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_sd_rv32 = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_tsr = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_tw = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_tvm = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_mxr = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_sum = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_mprv = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_spp = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_mpie = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_ube = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_spie = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_upie = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_mie = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_hie = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_sie = 1'h0; // @[core.scala:50:7] wire io_rocc_cmd_bits_status_uie = 1'h0; // @[core.scala:50:7] wire io_rocc_resp_ready = 1'h0; // @[core.scala:50:7] wire io_rocc_resp_valid = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_req_ready = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_req_valid = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_req_bits_signed = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_req_bits_dv = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_req_bits_phys = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_req_bits_no_resp = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_req_bits_no_alloc = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_req_bits_no_xcpt = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s1_kill = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_nack = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_nack_cause_raw = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_kill = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_uncached = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_resp_valid = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_resp_bits_signed = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_resp_bits_dv = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_resp_bits_replay = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_resp_bits_has_data = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_replay_next = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_xcpt_ma_ld = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_xcpt_ma_st = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_xcpt_pf_ld = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_xcpt_pf_st = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_xcpt_gf_ld = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_xcpt_gf_st = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_xcpt_ae_ld = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_xcpt_ae_st = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_s2_gpa_is_pte = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_ordered = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_store_pending = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_perf_acquire = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_perf_release = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_perf_grant = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_perf_tlbMiss = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_perf_blocked = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_perf_canAcceptStoreThenLoad = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_perf_canAcceptStoreThenRMW = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_perf_canAcceptLoadThenLoad = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_perf_storeBufferEmptyAfterLoad = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_perf_storeBufferEmptyAfterStore = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_keep_clock_enabled = 1'h0; // @[core.scala:50:7] wire io_rocc_mem_clock_enabled = 1'h0; // @[core.scala:50:7] wire io_rocc_busy = 1'h0; // @[core.scala:50:7] wire io_rocc_interrupt = 1'h0; // @[core.scala:50:7] wire io_rocc_exception = 1'h0; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_predicated = 1'h0; // @[core.scala:50:7] wire io_lsu_iresp_0_bits_fflags_valid = 1'h0; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_predicated = 1'h0; // @[core.scala:50:7] wire io_lsu_fresp_0_bits_fflags_valid = 1'h0; // @[core.scala:50:7] wire io_lsu_status_mbe = 1'h0; // @[core.scala:50:7] wire io_lsu_status_sbe = 1'h0; // @[core.scala:50:7] wire io_lsu_status_sd_rv32 = 1'h0; // @[core.scala:50:7] wire io_lsu_status_ube = 1'h0; // @[core.scala:50:7] wire io_lsu_status_upie = 1'h0; // @[core.scala:50:7] wire io_lsu_status_hie = 1'h0; // @[core.scala:50:7] wire io_lsu_status_uie = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_req_valid = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_req_bits_valid = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_req_bits_bits_need_gpa = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_req_bits_bits_vstage1 = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_req_bits_bits_stage2 = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_resp_bits_fragmented_superpage = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_status_mbe = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_status_sbe = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_status_sd_rv32 = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_status_ube = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_status_upie = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_status_hie = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_status_uie = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_hstatus_vtsr = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_hstatus_vtw = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_hstatus_vtvm = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_hstatus_hu = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_hstatus_spvp = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_hstatus_spv = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_hstatus_gva = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_hstatus_vsbe = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_debug = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_cease = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_wfi = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_dv = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_v = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_sd = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_mpv = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_gva = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_mbe = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_sbe = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_sd_rv32 = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_tsr = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_tw = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_tvm = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_mxr = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_sum = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_mprv = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_spp = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_mpie = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_ube = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_spie = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_upie = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_mie = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_hie = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_sie = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_gstatus_uie = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_0_ren = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_0_wen = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_0_stall = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_0_set = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_1_ren = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_1_wen = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_1_stall = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_1_set = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_2_ren = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_2_wen = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_2_stall = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_2_set = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_3_ren = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_3_wen = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_3_stall = 1'h0; // @[core.scala:50:7] wire io_ptw_tlb_customCSRs_csrs_3_set = 1'h0; // @[core.scala:50:7] wire io_trace_insns_0_valid = 1'h0; // @[core.scala:50:7] wire io_trace_insns_0_exception = 1'h0; // @[core.scala:50:7] wire io_trace_insns_0_interrupt = 1'h0; // @[core.scala:50:7] wire io_trace_insns_1_valid = 1'h0; // @[core.scala:50:7] wire io_trace_insns_1_exception = 1'h0; // @[core.scala:50:7] wire io_trace_insns_1_interrupt = 1'h0; // @[core.scala:50:7] wire int_wakeups_1_bits_bypassable = 1'h0; // @[core.scala:164:26] wire int_wakeups_1_bits_rebusy = 1'h0; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_iw_issued_partial_agen = 1'h0; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_iw_issued_partial_dgen = 1'h0; // @[core.scala:164:26] wire int_wakeups_2_bits_rebusy = 1'h0; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_iw_issued_partial_agen = 1'h0; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_iw_issued_partial_dgen = 1'h0; // @[core.scala:164:26] wire int_wakeups_3_bits_rebusy = 1'h0; // @[core.scala:164:26] wire pred_wakeups_0_bits_bypassable = 1'h0; // @[core.scala:165:26] wire pred_wakeups_0_bits_rebusy = 1'h0; // @[core.scala:165:26] wire pred_wakeups_1_bits_bypassable = 1'h0; // @[core.scala:165:26] wire pred_wakeups_1_bits_rebusy = 1'h0; // @[core.scala:165:26] wire pred_wakeup_bits_uop_is_rvc = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_iq_type_0 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_iq_type_1 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_iq_type_2 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_iq_type_3 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fu_code_0 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fu_code_1 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fu_code_2 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fu_code_3 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fu_code_4 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fu_code_5 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fu_code_6 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fu_code_7 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fu_code_8 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fu_code_9 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_iw_issued = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_iw_issued_partial_agen = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_iw_issued_partial_dgen = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_iw_p1_bypass_hint = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_iw_p2_bypass_hint = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_iw_p3_bypass_hint = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_is_sfb = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_is_fence = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_is_fencei = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_is_sfence = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_is_amo = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_is_eret = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_is_sys_pc2epc = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_is_rocc = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_is_mov = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_edge_inst = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_taken = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_imm_rename = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_ldst = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_wen = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_ren1 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_ren2 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_ren3 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_swap12 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_swap23 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_fromint = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_toint = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_fastpipe = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_fma = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_div = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_sqrt = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_wflags = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_ctrl_vec = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_prs1_busy = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_prs2_busy = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_prs3_busy = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_ppred_busy = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_exception = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_mem_signed = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_uses_ldq = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_uses_stq = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_is_unique = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_flush_on_commit = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_ldst_is_rs1 = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_frs3_en = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fcn_dw = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_fp_val = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_xcpt_pf_if = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_xcpt_ae_if = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_xcpt_ma_if = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_bp_debug_if = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_uop_bp_xcpt_if = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_bypassable = 1'h0; // @[core.scala:169:26] wire pred_wakeup_bits_rebusy = 1'h0; // @[core.scala:169:26] wire int_bypasses_1_bits_fflags_valid = 1'h0; // @[core.scala:174:27] wire int_bypasses_2_bits_fflags_valid = 1'h0; // @[core.scala:174:27] wire dec_uops_0_iw_issued = 1'h0; // @[core.scala:181:24] wire dec_uops_0_iw_issued_partial_agen = 1'h0; // @[core.scala:181:24] wire dec_uops_0_iw_issued_partial_dgen = 1'h0; // @[core.scala:181:24] wire dec_uops_0_iw_p1_bypass_hint = 1'h0; // @[core.scala:181:24] wire dec_uops_0_iw_p2_bypass_hint = 1'h0; // @[core.scala:181:24] wire dec_uops_0_iw_p3_bypass_hint = 1'h0; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_vec = 1'h0; // @[core.scala:181:24] wire dec_uops_0_prs1_busy = 1'h0; // @[core.scala:181:24] wire dec_uops_0_prs2_busy = 1'h0; // @[core.scala:181:24] wire dec_uops_0_prs3_busy = 1'h0; // @[core.scala:181:24] wire dec_uops_0_ppred_busy = 1'h0; // @[core.scala:181:24] wire dec_uops_0_xcpt_ma_if = 1'h0; // @[core.scala:181:24] wire dec_uops_1_iw_issued = 1'h0; // @[core.scala:181:24] wire dec_uops_1_iw_issued_partial_agen = 1'h0; // @[core.scala:181:24] wire dec_uops_1_iw_issued_partial_dgen = 1'h0; // @[core.scala:181:24] wire dec_uops_1_iw_p1_bypass_hint = 1'h0; // @[core.scala:181:24] wire dec_uops_1_iw_p2_bypass_hint = 1'h0; // @[core.scala:181:24] wire dec_uops_1_iw_p3_bypass_hint = 1'h0; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_vec = 1'h0; // @[core.scala:181:24] wire dec_uops_1_prs1_busy = 1'h0; // @[core.scala:181:24] wire dec_uops_1_prs2_busy = 1'h0; // @[core.scala:181:24] wire dec_uops_1_prs3_busy = 1'h0; // @[core.scala:181:24] wire dec_uops_1_ppred_busy = 1'h0; // @[core.scala:181:24] wire dec_uops_1_xcpt_ma_if = 1'h0; // @[core.scala:181:24] wire _hits_WIRE_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_3 = 1'h0; // @[Events.scala:13:33] wire hits_1 = 1'h0; // @[Events.scala:13:25] wire hits_2 = 1'h0; // @[Events.scala:13:25] wire hits_3 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_1_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_1_3 = 1'h0; // @[Events.scala:13:33] wire hits_1_0 = 1'h0; // @[Events.scala:13:25] wire _hits_WIRE_2_0 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_1 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_2 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_3 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_4 = 1'h0; // @[Events.scala:13:33] wire _hits_WIRE_2_5 = 1'h0; // @[Events.scala:13:33] wire custom_csrs_csrs_0_stall = 1'h0; // @[core.scala:301:25] wire custom_csrs_csrs_0_set = 1'h0; // @[core.scala:301:25] wire custom_csrs_csrs_1_stall = 1'h0; // @[core.scala:301:25] wire custom_csrs_csrs_1_set = 1'h0; // @[core.scala:301:25] wire custom_csrs_csrs_2_stall = 1'h0; // @[core.scala:301:25] wire custom_csrs_csrs_2_set = 1'h0; // @[core.scala:301:25] wire custom_csrs_csrs_3_stall = 1'h0; // @[core.scala:301:25] wire custom_csrs_csrs_3_set = 1'h0; // @[core.scala:301:25] wire _new_ghist_WIRE_current_saw_branch_not_taken = 1'h0; // @[core.scala:426:44] wire _new_ghist_WIRE_new_saw_branch_not_taken = 1'h0; // @[core.scala:426:44] wire _new_ghist_WIRE_new_saw_branch_taken = 1'h0; // @[core.scala:426:44] wire new_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:426:29] wire new_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:426:29] wire next_ghist_current_saw_branch_not_taken = 1'h0; // @[frontend.scala:74:27] wire next_ghist_new_saw_branch_not_taken = 1'h0; // @[frontend.scala:74:27] wire next_ghist_new_saw_branch_taken = 1'h0; // @[frontend.scala:74:27] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_ghist_current_saw_branch_not_taken = 1'h0; // @[core.scala:573:50] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:573:50] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:573:50] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_ghist_current_saw_branch_not_taken = 1'h0; // @[core.scala:573:50] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:573:50] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:573:50] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_ghist_current_saw_branch_not_taken = 1'h0; // @[core.scala:573:50] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:573:50] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:573:50] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_ghist_current_saw_branch_not_taken = 1'h0; // @[core.scala:573:50] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_ghist_new_saw_branch_not_taken = 1'h0; // @[core.scala:573:50] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_ghist_new_saw_branch_taken = 1'h0; // @[core.scala:573:50] wire _wait_for_rocc_T_1 = 1'h0; // @[core.scala:737:90] wire wait_for_rocc_0 = 1'h0; // @[core.scala:737:73] wire _wait_for_rocc_T_3 = 1'h0; // @[core.scala:737:90] wire wait_for_rocc_1 = 1'h0; // @[core.scala:737:73] wire rob_io_wb_resps_0_out_bits_predicated = 1'h0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_fflags_valid = 1'h0; // @[util.scala:114:23] wire _rob_io_csr_replay_valid_T = 1'h0; // @[core.scala:1106:45] wire _large_T_3 = 1'h0; // @[Counters.scala:68:28] wire coreMonitorBundle_excpt = 1'h0; // @[core.scala:1347:31] wire coreMonitorBundle_valid = 1'h0; // @[core.scala:1347:31] wire coreMonitorBundle_wrenx = 1'h0; // @[core.scala:1347:31] wire coreMonitorBundle_wrenf = 1'h0; // @[core.scala:1347:31] wire _io_rocc_exception_T = 1'h0; // @[core.scala:1366:61] wire _io_rocc_exception_T_1 = 1'h0; // @[core.scala:1366:41] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_iw_p1_speculative_child = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_iw_p2_speculative_child = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_dis_col_sel = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_op1_sel = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_typeTagIn = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_fp_ctrl_typeTagOut = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_rxq_idx = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_size = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_dst_rtype = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1_rtype = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2_rtype = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_0_bits_fp_typ = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_iw_p1_speculative_child = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_iw_p2_speculative_child = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_dis_col_sel = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_op1_sel = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_typeTagIn = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_fp_ctrl_typeTagOut = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_rxq_idx = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_mem_size = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_dst_rtype = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs1_rtype = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs2_rtype = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_fetchpacket_bits_uops_1_bits_fp_typ = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_status_xs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ifu_status_vs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_status_xs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_status_vs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_hstatus_vsxl = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_hstatus_zero3 = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_hstatus_zero2 = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_gstatus_dprv = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_gstatus_prv = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_gstatus_sxl = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_gstatus_uxl = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_gstatus_xs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_gstatus_fs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_gstatus_mpp = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_gstatus_vs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_0_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_1_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_2_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_3_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_4_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_5_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_6_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_7_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_cmd_bits_status_dprv = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_cmd_bits_status_prv = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_cmd_bits_status_sxl = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_cmd_bits_status_uxl = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_cmd_bits_status_xs = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_cmd_bits_status_fs = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_cmd_bits_status_mpp = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_cmd_bits_status_vs = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_mem_req_bits_size = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_mem_req_bits_dprv = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_mem_resp_bits_size = 2'h0; // @[core.scala:50:7] wire [1:0] io_rocc_mem_resp_bits_dprv = 2'h0; // @[core.scala:50:7] wire [1:0] io_lsu_status_xs = 2'h0; // @[core.scala:50:7] wire [1:0] io_lsu_status_vs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_status_xs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_status_vs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_hstatus_vsxl = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_hstatus_zero3 = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_hstatus_zero2 = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_gstatus_dprv = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_gstatus_prv = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_gstatus_sxl = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_gstatus_uxl = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_gstatus_xs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_gstatus_fs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_gstatus_mpp = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_gstatus_vs = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_0_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_1_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_2_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_3_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_4_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_5_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_6_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_pmp_7_cfg_res = 2'h0; // @[core.scala:50:7] wire [1:0] int_wakeups_1_bits_speculative_mask = 2'h0; // @[core.scala:164:26] wire [1:0] pred_wakeups_0_bits_speculative_mask = 2'h0; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_speculative_mask = 2'h0; // @[core.scala:165:26] wire [1:0] pred_wakeup_bits_uop_iw_p1_speculative_child = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_uop_iw_p2_speculative_child = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_uop_dis_col_sel = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_uop_op1_sel = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_uop_fp_ctrl_typeTagIn = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_uop_fp_ctrl_typeTagOut = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_uop_rxq_idx = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_uop_mem_size = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_uop_dst_rtype = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_uop_lrs1_rtype = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_uop_lrs2_rtype = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_uop_fp_typ = 2'h0; // @[core.scala:169:26] wire [1:0] pred_wakeup_bits_speculative_mask = 2'h0; // @[core.scala:169:26] wire [1:0] dec_uops_0_iw_p1_speculative_child = 2'h0; // @[core.scala:181:24] wire [1:0] dec_uops_0_iw_p2_speculative_child = 2'h0; // @[core.scala:181:24] wire [1:0] dec_uops_0_dis_col_sel = 2'h0; // @[core.scala:181:24] wire [1:0] dec_uops_0_rxq_idx = 2'h0; // @[core.scala:181:24] wire [1:0] dec_uops_1_iw_p1_speculative_child = 2'h0; // @[core.scala:181:24] wire [1:0] dec_uops_1_iw_p2_speculative_child = 2'h0; // @[core.scala:181:24] wire [1:0] dec_uops_1_dis_col_sel = 2'h0; // @[core.scala:181:24] wire [1:0] dec_uops_1_rxq_idx = 2'h0; // @[core.scala:181:24] wire [1:0] csr_io_counters_0_inc_sets_hi = 2'h0; // @[Events.scala:16:21] wire [1:0] csr_io_counters_1_inc_sets_hi = 2'h0; // @[Events.scala:16:21] wire [1:0] csr_io_counters_2_inc_sets_hi = 2'h0; // @[Events.scala:16:21] wire [1:0] csr_io_counters_3_inc_sets_hi = 2'h0; // @[Events.scala:16:21] wire [1:0] csr_io_counters_4_inc_sets_hi = 2'h0; // @[Events.scala:16:21] wire [1:0] csr_io_counters_5_inc_sets_hi = 2'h0; // @[Events.scala:16:21] wire [11:0] io_ifu_fetchpacket_bits_uops_0_bits_br_mask = 12'h0; // @[core.scala:50:7] wire [11:0] io_ifu_fetchpacket_bits_uops_1_bits_br_mask = 12'h0; // @[core.scala:50:7] wire [11:0] pred_wakeup_bits_uop_br_mask = 12'h0; // @[core.scala:169:26] wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_br_tag = 4'h0; // @[core.scala:50:7] wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_br_type = 4'h0; // @[core.scala:50:7] wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_ldq_idx = 4'h0; // @[core.scala:50:7] wire [3:0] io_ifu_fetchpacket_bits_uops_0_bits_stq_idx = 4'h0; // @[core.scala:50:7] wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_br_tag = 4'h0; // @[core.scala:50:7] wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_br_type = 4'h0; // @[core.scala:50:7] wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_ldq_idx = 4'h0; // @[core.scala:50:7] wire [3:0] io_ifu_fetchpacket_bits_uops_1_bits_stq_idx = 4'h0; // @[core.scala:50:7] wire [3:0] io_ptw_hgatp_mode = 4'h0; // @[core.scala:50:7] wire [3:0] io_ptw_vsatp_mode = 4'h0; // @[core.scala:50:7] wire [3:0] io_ptw_tlb_hgatp_mode = 4'h0; // @[core.scala:50:7] wire [3:0] io_ptw_tlb_vsatp_mode = 4'h0; // @[core.scala:50:7] wire [3:0] pred_wakeup_bits_uop_br_tag = 4'h0; // @[core.scala:169:26] wire [3:0] pred_wakeup_bits_uop_br_type = 4'h0; // @[core.scala:169:26] wire [3:0] pred_wakeup_bits_uop_ldq_idx = 4'h0; // @[core.scala:169:26] wire [3:0] pred_wakeup_bits_uop_stq_idx = 4'h0; // @[core.scala:169:26] wire [3:0] dec_uops_0_ldq_idx = 4'h0; // @[core.scala:181:24] wire [3:0] dec_uops_0_stq_idx = 4'h0; // @[core.scala:181:24] wire [3:0] dec_uops_1_ldq_idx = 4'h0; // @[core.scala:181:24] wire [3:0] dec_uops_1_stq_idx = 4'h0; // @[core.scala:181:24] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_imm_sel = 3'h0; // @[core.scala:50:7] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_op2_sel = 3'h0; // @[core.scala:50:7] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_csr_cmd = 3'h0; // @[core.scala:50:7] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_fp_rm = 3'h0; // @[core.scala:50:7] wire [2:0] io_ifu_fetchpacket_bits_uops_0_bits_debug_tsrc = 3'h0; // @[core.scala:50:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_imm_sel = 3'h0; // @[core.scala:50:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_op2_sel = 3'h0; // @[core.scala:50:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_csr_cmd = 3'h0; // @[core.scala:50:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_fp_rm = 3'h0; // @[core.scala:50:7] wire [2:0] io_ifu_fetchpacket_bits_uops_1_bits_debug_tsrc = 3'h0; // @[core.scala:50:7] wire [2:0] io_trace_insns_0_priv = 3'h0; // @[core.scala:50:7] wire [2:0] io_trace_insns_1_priv = 3'h0; // @[core.scala:50:7] wire [2:0] pred_wakeup_bits_uop_imm_sel = 3'h0; // @[core.scala:169:26] wire [2:0] pred_wakeup_bits_uop_op2_sel = 3'h0; // @[core.scala:169:26] wire [2:0] pred_wakeup_bits_uop_csr_cmd = 3'h0; // @[core.scala:169:26] wire [2:0] pred_wakeup_bits_uop_fp_rm = 3'h0; // @[core.scala:169:26] wire [2:0] pred_wakeup_bits_uop_debug_fsrc = 3'h0; // @[core.scala:169:26] wire [2:0] pred_wakeup_bits_uop_debug_tsrc = 3'h0; // @[core.scala:169:26] wire [2:0] dec_uops_0_debug_tsrc = 3'h0; // @[core.scala:181:24] wire [2:0] dec_uops_1_debug_tsrc = 3'h0; // @[core.scala:181:24] wire [2:0] coreMonitorBundle_priv_mode = 3'h0; // @[core.scala:1347:31] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_pimm = 5'h0; // @[core.scala:50:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_ppred = 5'h0; // @[core.scala:50:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_mem_cmd = 5'h0; // @[core.scala:50:7] wire [4:0] io_ifu_fetchpacket_bits_uops_0_bits_fcn_op = 5'h0; // @[core.scala:50:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_pimm = 5'h0; // @[core.scala:50:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_ppred = 5'h0; // @[core.scala:50:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_mem_cmd = 5'h0; // @[core.scala:50:7] wire [4:0] io_ifu_fetchpacket_bits_uops_1_bits_fcn_op = 5'h0; // @[core.scala:50:7] wire [4:0] io_ifu_rrd_ftq_resps_1_ghist_ras_idx = 5'h0; // @[core.scala:50:7] wire [4:0] io_ifu_rrd_ftq_resps_2_ghist_ras_idx = 5'h0; // @[core.scala:50:7] wire [4:0] io_ifu_debug_ftq_idx_0 = 5'h0; // @[core.scala:50:7] wire [4:0] io_ifu_debug_ftq_idx_1 = 5'h0; // @[core.scala:50:7] wire [4:0] io_ptw_hstatus_zero1 = 5'h0; // @[core.scala:50:7] wire [4:0] io_rocc_cmd_bits_inst_rs2 = 5'h0; // @[core.scala:50:7] wire [4:0] io_rocc_cmd_bits_inst_rs1 = 5'h0; // @[core.scala:50:7] wire [4:0] io_rocc_cmd_bits_inst_rd = 5'h0; // @[core.scala:50:7] wire [4:0] io_rocc_resp_bits_rd = 5'h0; // @[core.scala:50:7] wire [4:0] io_rocc_mem_req_bits_cmd = 5'h0; // @[core.scala:50:7] wire [4:0] io_rocc_mem_resp_bits_cmd = 5'h0; // @[core.scala:50:7] wire [4:0] io_lsu_iresp_0_bits_fflags_bits = 5'h0; // @[core.scala:50:7] wire [4:0] io_lsu_fresp_0_bits_fflags_bits = 5'h0; // @[core.scala:50:7] wire [4:0] io_ptw_tlb_hstatus_zero1 = 5'h0; // @[core.scala:50:7] wire [4:0] pred_wakeup_bits_uop_ftq_idx = 5'h0; // @[core.scala:169:26] wire [4:0] pred_wakeup_bits_uop_pimm = 5'h0; // @[core.scala:169:26] wire [4:0] pred_wakeup_bits_uop_ppred = 5'h0; // @[core.scala:169:26] wire [4:0] pred_wakeup_bits_uop_mem_cmd = 5'h0; // @[core.scala:169:26] wire [4:0] pred_wakeup_bits_uop_fcn_op = 5'h0; // @[core.scala:169:26] wire [4:0] int_bypasses_1_bits_fflags_bits = 5'h0; // @[core.scala:174:27] wire [4:0] int_bypasses_2_bits_fflags_bits = 5'h0; // @[core.scala:174:27] wire [4:0] dec_uops_0_ppred = 5'h0; // @[core.scala:181:24] wire [4:0] dec_uops_1_ppred = 5'h0; // @[core.scala:181:24] wire [4:0] _new_ghist_WIRE_ras_idx = 5'h0; // @[core.scala:426:44] wire [4:0] _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_ghist_ras_idx = 5'h0; // @[core.scala:573:50] wire [4:0] _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_ghist_ras_idx = 5'h0; // @[core.scala:573:50] wire [4:0] _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_ghist_ras_idx = 5'h0; // @[core.scala:573:50] wire [4:0] _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_ghist_ras_idx = 5'h0; // @[core.scala:573:50] wire [4:0] rob_io_wb_resps_0_out_bits_fflags_bits = 5'h0; // @[util.scala:114:23] wire [4:0] coreMonitorBundle_wrdst = 5'h0; // @[core.scala:1347:31] wire [4:0] coreMonitorBundle_rd0src = 5'h0; // @[core.scala:1347:31] wire [4:0] coreMonitorBundle_rd1src = 5'h0; // @[core.scala:1347:31] wire [19:0] io_ifu_fetchpacket_bits_uops_0_bits_imm_packed = 20'h0; // @[core.scala:50:7] wire [19:0] io_ifu_fetchpacket_bits_uops_1_bits_imm_packed = 20'h0; // @[core.scala:50:7] wire [19:0] pred_wakeup_bits_uop_imm_packed = 20'h0; // @[core.scala:169:26] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_rob_idx = 6'h0; // @[core.scala:50:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_ldst = 6'h0; // @[core.scala:50:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs1 = 6'h0; // @[core.scala:50:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs2 = 6'h0; // @[core.scala:50:7] wire [5:0] io_ifu_fetchpacket_bits_uops_0_bits_lrs3 = 6'h0; // @[core.scala:50:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_rob_idx = 6'h0; // @[core.scala:50:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_ldst = 6'h0; // @[core.scala:50:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs1 = 6'h0; // @[core.scala:50:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs2 = 6'h0; // @[core.scala:50:7] wire [5:0] io_ifu_fetchpacket_bits_uops_1_bits_lrs3 = 6'h0; // @[core.scala:50:7] wire [5:0] io_ptw_hstatus_vgein = 6'h0; // @[core.scala:50:7] wire [5:0] io_ptw_tlb_hstatus_vgein = 6'h0; // @[core.scala:50:7] wire [5:0] pred_wakeup_bits_uop_pc_lob = 6'h0; // @[core.scala:169:26] wire [5:0] pred_wakeup_bits_uop_rob_idx = 6'h0; // @[core.scala:169:26] wire [5:0] pred_wakeup_bits_uop_ldst = 6'h0; // @[core.scala:169:26] wire [5:0] pred_wakeup_bits_uop_lrs1 = 6'h0; // @[core.scala:169:26] wire [5:0] pred_wakeup_bits_uop_lrs2 = 6'h0; // @[core.scala:169:26] wire [5:0] pred_wakeup_bits_uop_lrs3 = 6'h0; // @[core.scala:169:26] wire [5:0] dec_uops_0_rob_idx = 6'h0; // @[core.scala:181:24] wire [5:0] dec_uops_1_rob_idx = 6'h0; // @[core.scala:181:24] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_pdst = 7'h0; // @[core.scala:50:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs1 = 7'h0; // @[core.scala:50:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs2 = 7'h0; // @[core.scala:50:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_prs3 = 7'h0; // @[core.scala:50:7] wire [6:0] io_ifu_fetchpacket_bits_uops_0_bits_stale_pdst = 7'h0; // @[core.scala:50:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_pdst = 7'h0; // @[core.scala:50:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs1 = 7'h0; // @[core.scala:50:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs2 = 7'h0; // @[core.scala:50:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_prs3 = 7'h0; // @[core.scala:50:7] wire [6:0] io_ifu_fetchpacket_bits_uops_1_bits_stale_pdst = 7'h0; // @[core.scala:50:7] wire [6:0] io_rocc_cmd_bits_inst_funct = 7'h0; // @[core.scala:50:7] wire [6:0] io_rocc_cmd_bits_inst_opcode = 7'h0; // @[core.scala:50:7] wire [6:0] io_rocc_mem_req_bits_tag = 7'h0; // @[core.scala:50:7] wire [6:0] io_rocc_mem_resp_bits_tag = 7'h0; // @[core.scala:50:7] wire [6:0] pred_wakeup_bits_uop_prs1 = 7'h0; // @[core.scala:169:26] wire [6:0] pred_wakeup_bits_uop_prs2 = 7'h0; // @[core.scala:169:26] wire [6:0] pred_wakeup_bits_uop_prs3 = 7'h0; // @[core.scala:169:26] wire [6:0] pred_wakeup_bits_uop_stale_pdst = 7'h0; // @[core.scala:169:26] wire [6:0] dec_uops_0_pdst = 7'h0; // @[core.scala:181:24] wire [6:0] dec_uops_0_prs1 = 7'h0; // @[core.scala:181:24] wire [6:0] dec_uops_0_prs2 = 7'h0; // @[core.scala:181:24] wire [6:0] dec_uops_0_prs3 = 7'h0; // @[core.scala:181:24] wire [6:0] dec_uops_0_stale_pdst = 7'h0; // @[core.scala:181:24] wire [6:0] dec_uops_1_pdst = 7'h0; // @[core.scala:181:24] wire [6:0] dec_uops_1_prs1 = 7'h0; // @[core.scala:181:24] wire [6:0] dec_uops_1_prs2 = 7'h0; // @[core.scala:181:24] wire [6:0] dec_uops_1_prs3 = 7'h0; // @[core.scala:181:24] wire [6:0] dec_uops_1_stale_pdst = 7'h0; // @[core.scala:181:24] wire [63:0] io_ifu_fetchpacket_bits_uops_0_bits_exc_cause = 64'h0; // @[core.scala:50:7] wire [63:0] io_ifu_fetchpacket_bits_uops_1_bits_exc_cause = 64'h0; // @[core.scala:50:7] wire [63:0] io_ifu_rrd_ftq_resps_1_ghist_old_history = 64'h0; // @[core.scala:50:7] wire [63:0] io_ifu_rrd_ftq_resps_2_ghist_old_history = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_0_wdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_0_value = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_0_sdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_1_wdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_1_value = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_1_sdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_2_wdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_2_value = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_2_sdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_3_wdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_3_value = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_customCSRs_csrs_3_sdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_rocc_cmd_bits_rs1 = 64'h0; // @[core.scala:50:7] wire [63:0] io_rocc_cmd_bits_rs2 = 64'h0; // @[core.scala:50:7] wire [63:0] io_rocc_resp_bits_data = 64'h0; // @[core.scala:50:7] wire [63:0] io_rocc_mem_req_bits_data = 64'h0; // @[core.scala:50:7] wire [63:0] io_rocc_mem_s1_data_data = 64'h0; // @[core.scala:50:7] wire [63:0] io_rocc_mem_resp_bits_data = 64'h0; // @[core.scala:50:7] wire [63:0] io_rocc_mem_resp_bits_data_word_bypass = 64'h0; // @[core.scala:50:7] wire [63:0] io_rocc_mem_resp_bits_data_raw = 64'h0; // @[core.scala:50:7] wire [63:0] io_rocc_mem_resp_bits_store_data = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_0_wdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_0_value = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_0_sdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_1_wdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_1_value = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_1_sdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_2_wdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_2_value = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_2_sdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_3_wdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_3_value = 64'h0; // @[core.scala:50:7] wire [63:0] io_ptw_tlb_customCSRs_csrs_3_sdata = 64'h0; // @[core.scala:50:7] wire [63:0] io_trace_insns_0_cause = 64'h0; // @[core.scala:50:7] wire [63:0] io_trace_insns_1_cause = 64'h0; // @[core.scala:50:7] wire [63:0] pred_wakeup_bits_uop_exc_cause = 64'h0; // @[core.scala:169:26] wire [63:0] custom_csrs_csrs_0_sdata = 64'h0; // @[core.scala:301:25] wire [63:0] custom_csrs_csrs_1_sdata = 64'h0; // @[core.scala:301:25] wire [63:0] custom_csrs_csrs_2_sdata = 64'h0; // @[core.scala:301:25] wire [63:0] custom_csrs_csrs_3_sdata = 64'h0; // @[core.scala:301:25] wire [63:0] _debug_brs_WIRE_0 = 64'h0; // @[core.scala:315:38] wire [63:0] _debug_brs_WIRE_1 = 64'h0; // @[core.scala:315:38] wire [63:0] _debug_brs_WIRE_2 = 64'h0; // @[core.scala:315:38] wire [63:0] _debug_brs_WIRE_3 = 64'h0; // @[core.scala:315:38] wire [63:0] _debug_brs_WIRE_4 = 64'h0; // @[core.scala:315:38] wire [63:0] _debug_jals_WIRE_0 = 64'h0; // @[core.scala:316:38] wire [63:0] _debug_jals_WIRE_1 = 64'h0; // @[core.scala:316:38] wire [63:0] _debug_jals_WIRE_2 = 64'h0; // @[core.scala:316:38] wire [63:0] _debug_jals_WIRE_3 = 64'h0; // @[core.scala:316:38] wire [63:0] _debug_jals_WIRE_4 = 64'h0; // @[core.scala:316:38] wire [63:0] _debug_jalrs_WIRE_0 = 64'h0; // @[core.scala:317:38] wire [63:0] _debug_jalrs_WIRE_1 = 64'h0; // @[core.scala:317:38] wire [63:0] _debug_jalrs_WIRE_2 = 64'h0; // @[core.scala:317:38] wire [63:0] _debug_jalrs_WIRE_3 = 64'h0; // @[core.scala:317:38] wire [63:0] _debug_jalrs_WIRE_4 = 64'h0; // @[core.scala:317:38] wire [63:0] _new_ghist_WIRE_old_history = 64'h0; // @[core.scala:426:44] wire [63:0] new_ghist_old_history = 64'h0; // @[core.scala:426:29] wire [63:0] _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_ghist_old_history = 64'h0; // @[core.scala:573:50] wire [63:0] _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_ghist_old_history = 64'h0; // @[core.scala:573:50] wire [63:0] _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_ghist_old_history = 64'h0; // @[core.scala:573:50] wire [63:0] _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_ghist_old_history = 64'h0; // @[core.scala:573:50] wire [63:0] coreMonitorBundle_hartid = 64'h0; // @[core.scala:1347:31] wire [63:0] coreMonitorBundle_pc = 64'h0; // @[core.scala:1347:31] wire [63:0] coreMonitorBundle_wrdata = 64'h0; // @[core.scala:1347:31] wire [63:0] coreMonitorBundle_rd0val = 64'h0; // @[core.scala:1347:31] wire [63:0] coreMonitorBundle_rd1val = 64'h0; // @[core.scala:1347:31] wire [31:0] io_ifu_status_isa = 32'h14112D; // @[core.scala:50:7] wire [31:0] io_ptw_status_isa = 32'h14112D; // @[core.scala:50:7] wire [31:0] io_lsu_status_isa = 32'h14112D; // @[core.scala:50:7] wire [31:0] io_ptw_tlb_status_isa = 32'h14112D; // @[core.scala:50:7] wire [22:0] io_ifu_status_zero2 = 23'h0; // @[core.scala:50:7] wire [22:0] io_ptw_status_zero2 = 23'h0; // @[core.scala:50:7] wire [22:0] io_ptw_gstatus_zero2 = 23'h0; // @[core.scala:50:7] wire [22:0] io_rocc_cmd_bits_status_zero2 = 23'h0; // @[core.scala:50:7] wire [22:0] io_lsu_status_zero2 = 23'h0; // @[core.scala:50:7] wire [22:0] io_ptw_tlb_status_zero2 = 23'h0; // @[core.scala:50:7] wire [22:0] io_ptw_tlb_gstatus_zero2 = 23'h0; // @[core.scala:50:7] wire [7:0] io_ifu_status_zero1 = 8'h0; // @[core.scala:50:7] wire [7:0] io_ptw_status_zero1 = 8'h0; // @[core.scala:50:7] wire [7:0] io_ptw_gstatus_zero1 = 8'h0; // @[core.scala:50:7] wire [7:0] io_rocc_cmd_bits_status_zero1 = 8'h0; // @[core.scala:50:7] wire [7:0] io_rocc_mem_req_bits_mask = 8'h0; // @[core.scala:50:7] wire [7:0] io_rocc_mem_s1_data_mask = 8'h0; // @[core.scala:50:7] wire [7:0] io_rocc_mem_resp_bits_mask = 8'h0; // @[core.scala:50:7] wire [7:0] io_lsu_status_zero1 = 8'h0; // @[core.scala:50:7] wire [7:0] io_ptw_tlb_status_zero1 = 8'h0; // @[core.scala:50:7] wire [7:0] io_ptw_tlb_gstatus_zero1 = 8'h0; // @[core.scala:50:7] wire [15:0] io_ptw_ptbr_asid = 16'h0; // @[core.scala:50:7] wire [15:0] io_ptw_hgatp_asid = 16'h0; // @[core.scala:50:7] wire [15:0] io_ptw_vsatp_asid = 16'h0; // @[core.scala:50:7] wire [15:0] io_ptw_tlb_ptbr_asid = 16'h0; // @[core.scala:50:7] wire [15:0] io_ptw_tlb_hgatp_asid = 16'h0; // @[core.scala:50:7] wire [15:0] io_ptw_tlb_vsatp_asid = 16'h0; // @[core.scala:50:7] wire [1:0] io_ifu_status_sxl = 2'h2; // @[core.scala:50:7] wire [1:0] io_ifu_status_uxl = 2'h2; // @[core.scala:50:7] wire [1:0] io_ptw_status_sxl = 2'h2; // @[core.scala:50:7] wire [1:0] io_ptw_status_uxl = 2'h2; // @[core.scala:50:7] wire [1:0] io_lsu_status_sxl = 2'h2; // @[core.scala:50:7] wire [1:0] io_lsu_status_uxl = 2'h2; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_status_sxl = 2'h2; // @[core.scala:50:7] wire [1:0] io_ptw_tlb_status_uxl = 2'h2; // @[core.scala:50:7] wire [1:0] int_wakeups_3_bits_speculative_mask = 2'h2; // @[core.scala:164:26] wire [1:0] _data_sel_T_1 = 2'h2; // @[OneHot.scala:58:35] wire [1:0] _data_sel_T_3 = 2'h2; // @[OneHot.scala:58:35] wire [1:0] _data_sel_T_5 = 2'h2; // @[OneHot.scala:58:35] wire [1:0] _data_sel_T_7 = 2'h2; // @[OneHot.scala:58:35] wire [43:0] io_ptw_hgatp_ppn = 44'h0; // @[core.scala:50:7] wire [43:0] io_ptw_vsatp_ppn = 44'h0; // @[core.scala:50:7] wire [43:0] io_ptw_tlb_hgatp_ppn = 44'h0; // @[core.scala:50:7] wire [43:0] io_ptw_tlb_vsatp_ppn = 44'h0; // @[core.scala:50:7] wire [29:0] io_ptw_hstatus_zero6 = 30'h0; // @[core.scala:50:7] wire [29:0] io_ptw_tlb_hstatus_zero6 = 30'h0; // @[core.scala:50:7] wire [8:0] io_ptw_hstatus_zero5 = 9'h0; // @[core.scala:50:7] wire [8:0] io_ptw_tlb_hstatus_zero5 = 9'h0; // @[core.scala:50:7] wire [31:0] io_ptw_gstatus_isa = 32'h0; // @[core.scala:50:7] wire [31:0] io_rocc_cmd_bits_status_isa = 32'h0; // @[core.scala:50:7] wire [31:0] io_rocc_mem_s2_paddr = 32'h0; // @[core.scala:50:7] wire [31:0] io_lsu_commit_debug_insts_0 = 32'h0; // @[core.scala:50:7] wire [31:0] io_lsu_commit_debug_insts_1 = 32'h0; // @[core.scala:50:7] wire [31:0] io_ptw_tlb_gstatus_isa = 32'h0; // @[core.scala:50:7] wire [31:0] io_trace_insns_0_insn = 32'h0; // @[core.scala:50:7] wire [31:0] io_trace_insns_1_insn = 32'h0; // @[core.scala:50:7] wire [31:0] pred_wakeup_bits_uop_inst = 32'h0; // @[core.scala:169:26] wire [31:0] pred_wakeup_bits_uop_debug_inst = 32'h0; // @[core.scala:169:26] wire [31:0] coreMonitorBundle_timer = 32'h0; // @[core.scala:1347:31] wire [31:0] coreMonitorBundle_inst = 32'h0; // @[core.scala:1347:31] wire [39:0] io_rocc_mem_req_bits_addr = 40'h0; // @[core.scala:50:7] wire [39:0] io_rocc_mem_resp_bits_addr = 40'h0; // @[core.scala:50:7] wire [39:0] io_rocc_mem_s2_gpa = 40'h0; // @[core.scala:50:7] wire [39:0] io_trace_insns_0_iaddr = 40'h0; // @[core.scala:50:7] wire [39:0] io_trace_insns_0_tval = 40'h0; // @[core.scala:50:7] wire [39:0] io_trace_insns_1_iaddr = 40'h0; // @[core.scala:50:7] wire [39:0] io_trace_insns_1_tval = 40'h0; // @[core.scala:50:7] wire [39:0] pred_wakeup_bits_uop_debug_pc = 40'h0; // @[core.scala:169:26] wire [26:0] io_ptw_tlb_req_bits_bits_addr = 27'h0; // @[core.scala:50:7] wire int_wakeups_2_bits_bypassable = 1'h1; // @[core.scala:164:26] wire int_wakeups_3_bits_bypassable = 1'h1; // @[core.scala:164:26] wire new_ghist_current_saw_branch_not_taken = 1'h1; // @[core.scala:426:29] wire flush_pc_req_ready = 1'h1; // @[core.scala:539:26] wire _large_T_1 = 1'h1; // @[Counters.scala:51:36] wire [1:0] int_wakeups_2_bits_speculative_mask = 2'h1; // @[core.scala:164:26] wire [1:0] _data_sel_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _data_sel_T_2 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _data_sel_T_4 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _data_sel_T_6 = 2'h1; // @[OneHot.scala:58:35] wire [3:0] _cfi_idx_T_1 = 4'h8; // @[core.scala:462:45] wire [3:0] _next_ghist_not_taken_branches_T_11 = 4'hF; // @[frontend.scala:78:45] wire dec_ready; // @[core.scala:184:24] wire [4:0] new_ghist_ras_idx = io_ifu_rrd_ftq_resps_0_entry_ras_idx_0; // @[core.scala:50:7, :426:29] wire _cfi_idx_T = io_ifu_rrd_ftq_resps_0_entry_start_bank_0; // @[core.scala:50:7, :462:32] wire io_ptw_sfence_valid_0 = io_ifu_sfence_valid_0; // @[core.scala:50:7] wire io_ptw_sfence_bits_rs1_0 = io_ifu_sfence_bits_rs1_0; // @[core.scala:50:7] wire io_ptw_sfence_bits_rs2_0 = io_ifu_sfence_bits_rs2_0; // @[core.scala:50:7] wire [38:0] io_ptw_sfence_bits_addr_0 = io_ifu_sfence_bits_addr_0; // @[core.scala:50:7] wire io_ptw_sfence_bits_asid_0 = io_ifu_sfence_bits_asid_0; // @[core.scala:50:7] wire io_ptw_sfence_bits_hv_0 = io_ifu_sfence_bits_hv_0; // @[core.scala:50:7] wire io_ptw_sfence_bits_hg_0 = io_ifu_sfence_bits_hg_0; // @[core.scala:50:7] wire [11:0] brupdate_b1_resolve_mask; // @[core.scala:209:23] wire [11:0] brupdate_b1_mispredict_mask; // @[core.scala:209:23] wire [31:0] brupdate_b2_uop_inst; // @[core.scala:209:23] wire [31:0] brupdate_b2_uop_debug_inst; // @[core.scala:209:23] wire brupdate_b2_uop_is_rvc; // @[core.scala:209:23] wire [39:0] brupdate_b2_uop_debug_pc; // @[core.scala:209:23] wire brupdate_b2_uop_iq_type_0; // @[core.scala:209:23] wire brupdate_b2_uop_iq_type_1; // @[core.scala:209:23] wire brupdate_b2_uop_iq_type_2; // @[core.scala:209:23] wire brupdate_b2_uop_iq_type_3; // @[core.scala:209:23] wire brupdate_b2_uop_fu_code_0; // @[core.scala:209:23] wire brupdate_b2_uop_fu_code_1; // @[core.scala:209:23] wire brupdate_b2_uop_fu_code_2; // @[core.scala:209:23] wire brupdate_b2_uop_fu_code_3; // @[core.scala:209:23] wire brupdate_b2_uop_fu_code_4; // @[core.scala:209:23] wire brupdate_b2_uop_fu_code_5; // @[core.scala:209:23] wire brupdate_b2_uop_fu_code_6; // @[core.scala:209:23] wire brupdate_b2_uop_fu_code_7; // @[core.scala:209:23] wire brupdate_b2_uop_fu_code_8; // @[core.scala:209:23] wire brupdate_b2_uop_fu_code_9; // @[core.scala:209:23] wire brupdate_b2_uop_iw_issued; // @[core.scala:209:23] wire brupdate_b2_uop_iw_issued_partial_agen; // @[core.scala:209:23] wire brupdate_b2_uop_iw_issued_partial_dgen; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_iw_p1_speculative_child; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_iw_p2_speculative_child; // @[core.scala:209:23] wire brupdate_b2_uop_iw_p1_bypass_hint; // @[core.scala:209:23] wire brupdate_b2_uop_iw_p2_bypass_hint; // @[core.scala:209:23] wire brupdate_b2_uop_iw_p3_bypass_hint; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_dis_col_sel; // @[core.scala:209:23] wire [11:0] brupdate_b2_uop_br_mask; // @[core.scala:209:23] wire [3:0] brupdate_b2_uop_br_tag; // @[core.scala:209:23] wire [3:0] brupdate_b2_uop_br_type; // @[core.scala:209:23] wire brupdate_b2_uop_is_sfb; // @[core.scala:209:23] wire brupdate_b2_uop_is_fence; // @[core.scala:209:23] wire brupdate_b2_uop_is_fencei; // @[core.scala:209:23] wire brupdate_b2_uop_is_sfence; // @[core.scala:209:23] wire brupdate_b2_uop_is_amo; // @[core.scala:209:23] wire brupdate_b2_uop_is_eret; // @[core.scala:209:23] wire brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:209:23] wire brupdate_b2_uop_is_rocc; // @[core.scala:209:23] wire brupdate_b2_uop_is_mov; // @[core.scala:209:23] wire [4:0] brupdate_b2_uop_ftq_idx; // @[core.scala:209:23] wire brupdate_b2_uop_edge_inst; // @[core.scala:209:23] wire [5:0] brupdate_b2_uop_pc_lob; // @[core.scala:209:23] wire brupdate_b2_uop_taken; // @[core.scala:209:23] wire brupdate_b2_uop_imm_rename; // @[core.scala:209:23] wire [2:0] brupdate_b2_uop_imm_sel; // @[core.scala:209:23] wire [4:0] brupdate_b2_uop_pimm; // @[core.scala:209:23] wire [19:0] brupdate_b2_uop_imm_packed; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_op1_sel; // @[core.scala:209:23] wire [2:0] brupdate_b2_uop_op2_sel; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_ldst; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_wen; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_ren1; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_ren2; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_ren3; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_swap12; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_swap23; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_fp_ctrl_typeTagIn; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_fp_ctrl_typeTagOut; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_fromint; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_toint; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_fastpipe; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_fma; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_div; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_sqrt; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_wflags; // @[core.scala:209:23] wire brupdate_b2_uop_fp_ctrl_vec; // @[core.scala:209:23] wire [5:0] brupdate_b2_uop_rob_idx; // @[core.scala:209:23] wire [3:0] brupdate_b2_uop_ldq_idx; // @[core.scala:209:23] wire [3:0] brupdate_b2_uop_stq_idx; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_rxq_idx; // @[core.scala:209:23] wire [6:0] brupdate_b2_uop_pdst; // @[core.scala:209:23] wire [6:0] brupdate_b2_uop_prs1; // @[core.scala:209:23] wire [6:0] brupdate_b2_uop_prs2; // @[core.scala:209:23] wire [6:0] brupdate_b2_uop_prs3; // @[core.scala:209:23] wire [4:0] brupdate_b2_uop_ppred; // @[core.scala:209:23] wire brupdate_b2_uop_prs1_busy; // @[core.scala:209:23] wire brupdate_b2_uop_prs2_busy; // @[core.scala:209:23] wire brupdate_b2_uop_prs3_busy; // @[core.scala:209:23] wire brupdate_b2_uop_ppred_busy; // @[core.scala:209:23] wire [6:0] brupdate_b2_uop_stale_pdst; // @[core.scala:209:23] wire brupdate_b2_uop_exception; // @[core.scala:209:23] wire [63:0] brupdate_b2_uop_exc_cause; // @[core.scala:209:23] wire [4:0] brupdate_b2_uop_mem_cmd; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_mem_size; // @[core.scala:209:23] wire brupdate_b2_uop_mem_signed; // @[core.scala:209:23] wire brupdate_b2_uop_uses_ldq; // @[core.scala:209:23] wire brupdate_b2_uop_uses_stq; // @[core.scala:209:23] wire brupdate_b2_uop_is_unique; // @[core.scala:209:23] wire brupdate_b2_uop_flush_on_commit; // @[core.scala:209:23] wire [2:0] brupdate_b2_uop_csr_cmd; // @[core.scala:209:23] wire brupdate_b2_uop_ldst_is_rs1; // @[core.scala:209:23] wire [5:0] brupdate_b2_uop_ldst; // @[core.scala:209:23] wire [5:0] brupdate_b2_uop_lrs1; // @[core.scala:209:23] wire [5:0] brupdate_b2_uop_lrs2; // @[core.scala:209:23] wire [5:0] brupdate_b2_uop_lrs3; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_dst_rtype; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_lrs1_rtype; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_lrs2_rtype; // @[core.scala:209:23] wire brupdate_b2_uop_frs3_en; // @[core.scala:209:23] wire brupdate_b2_uop_fcn_dw; // @[core.scala:209:23] wire [4:0] brupdate_b2_uop_fcn_op; // @[core.scala:209:23] wire brupdate_b2_uop_fp_val; // @[core.scala:209:23] wire [2:0] brupdate_b2_uop_fp_rm; // @[core.scala:209:23] wire [1:0] brupdate_b2_uop_fp_typ; // @[core.scala:209:23] wire brupdate_b2_uop_xcpt_pf_if; // @[core.scala:209:23] wire brupdate_b2_uop_xcpt_ae_if; // @[core.scala:209:23] wire brupdate_b2_uop_xcpt_ma_if; // @[core.scala:209:23] wire brupdate_b2_uop_bp_debug_if; // @[core.scala:209:23] wire brupdate_b2_uop_bp_xcpt_if; // @[core.scala:209:23] wire [2:0] brupdate_b2_uop_debug_fsrc; // @[core.scala:209:23] wire [2:0] brupdate_b2_uop_debug_tsrc; // @[core.scala:209:23] wire brupdate_b2_mispredict; // @[core.scala:209:23] wire brupdate_b2_taken; // @[core.scala:209:23] wire [2:0] brupdate_b2_cfi_type; // @[core.scala:209:23] wire [1:0] brupdate_b2_pc_sel; // @[core.scala:209:23] wire [39:0] brupdate_b2_jalr_target; // @[core.scala:209:23] wire [20:0] brupdate_b2_target_offset; // @[core.scala:209:23] wire _io_ifu_flush_icache_T_10; // @[core.scala:410:13] wire _io_ifu_enable_bpd_T; // @[parameters.scala:182:50] wire hits_2_0 = io_ifu_perf_acquire_0; // @[Events.scala:13:25] wire hits_2_3 = io_ifu_perf_tlbMiss_0; // @[Events.scala:13:25] wire hits_2_5 = io_ptw_perf_l2miss_0; // @[Events.scala:13:25] wire int_wakeups_0_valid = io_lsu_iwakeups_0_valid_0; // @[core.scala:50:7, :164:26] wire [31:0] int_wakeups_0_bits_uop_inst = io_lsu_iwakeups_0_bits_uop_inst_0; // @[core.scala:50:7, :164:26] wire [31:0] int_wakeups_0_bits_uop_debug_inst = io_lsu_iwakeups_0_bits_uop_debug_inst_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_is_rvc = io_lsu_iwakeups_0_bits_uop_is_rvc_0; // @[core.scala:50:7, :164:26] wire [39:0] int_wakeups_0_bits_uop_debug_pc = io_lsu_iwakeups_0_bits_uop_debug_pc_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_iq_type_0 = io_lsu_iwakeups_0_bits_uop_iq_type_0_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_iq_type_1 = io_lsu_iwakeups_0_bits_uop_iq_type_1_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_iq_type_2 = io_lsu_iwakeups_0_bits_uop_iq_type_2_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_iq_type_3 = io_lsu_iwakeups_0_bits_uop_iq_type_3_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fu_code_0 = io_lsu_iwakeups_0_bits_uop_fu_code_0_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fu_code_1 = io_lsu_iwakeups_0_bits_uop_fu_code_1_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fu_code_2 = io_lsu_iwakeups_0_bits_uop_fu_code_2_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fu_code_3 = io_lsu_iwakeups_0_bits_uop_fu_code_3_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fu_code_4 = io_lsu_iwakeups_0_bits_uop_fu_code_4_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fu_code_5 = io_lsu_iwakeups_0_bits_uop_fu_code_5_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fu_code_6 = io_lsu_iwakeups_0_bits_uop_fu_code_6_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fu_code_7 = io_lsu_iwakeups_0_bits_uop_fu_code_7_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fu_code_8 = io_lsu_iwakeups_0_bits_uop_fu_code_8_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fu_code_9 = io_lsu_iwakeups_0_bits_uop_fu_code_9_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_iw_issued = io_lsu_iwakeups_0_bits_uop_iw_issued_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_iw_issued_partial_agen = io_lsu_iwakeups_0_bits_uop_iw_issued_partial_agen_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_iw_issued_partial_dgen = io_lsu_iwakeups_0_bits_uop_iw_issued_partial_dgen_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_iw_p1_speculative_child = io_lsu_iwakeups_0_bits_uop_iw_p1_speculative_child_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_iw_p2_speculative_child = io_lsu_iwakeups_0_bits_uop_iw_p2_speculative_child_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_iw_p1_bypass_hint = io_lsu_iwakeups_0_bits_uop_iw_p1_bypass_hint_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_iw_p2_bypass_hint = io_lsu_iwakeups_0_bits_uop_iw_p2_bypass_hint_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_iw_p3_bypass_hint = io_lsu_iwakeups_0_bits_uop_iw_p3_bypass_hint_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_dis_col_sel = io_lsu_iwakeups_0_bits_uop_dis_col_sel_0; // @[core.scala:50:7, :164:26] wire [11:0] int_wakeups_0_bits_uop_br_mask = io_lsu_iwakeups_0_bits_uop_br_mask_0; // @[core.scala:50:7, :164:26] wire [3:0] int_wakeups_0_bits_uop_br_tag = io_lsu_iwakeups_0_bits_uop_br_tag_0; // @[core.scala:50:7, :164:26] wire [3:0] int_wakeups_0_bits_uop_br_type = io_lsu_iwakeups_0_bits_uop_br_type_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_is_sfb = io_lsu_iwakeups_0_bits_uop_is_sfb_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_is_fence = io_lsu_iwakeups_0_bits_uop_is_fence_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_is_fencei = io_lsu_iwakeups_0_bits_uop_is_fencei_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_is_sfence = io_lsu_iwakeups_0_bits_uop_is_sfence_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_is_amo = io_lsu_iwakeups_0_bits_uop_is_amo_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_is_eret = io_lsu_iwakeups_0_bits_uop_is_eret_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_is_sys_pc2epc = io_lsu_iwakeups_0_bits_uop_is_sys_pc2epc_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_is_rocc = io_lsu_iwakeups_0_bits_uop_is_rocc_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_is_mov = io_lsu_iwakeups_0_bits_uop_is_mov_0; // @[core.scala:50:7, :164:26] wire [4:0] int_wakeups_0_bits_uop_ftq_idx = io_lsu_iwakeups_0_bits_uop_ftq_idx_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_edge_inst = io_lsu_iwakeups_0_bits_uop_edge_inst_0; // @[core.scala:50:7, :164:26] wire [5:0] int_wakeups_0_bits_uop_pc_lob = io_lsu_iwakeups_0_bits_uop_pc_lob_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_taken = io_lsu_iwakeups_0_bits_uop_taken_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_imm_rename = io_lsu_iwakeups_0_bits_uop_imm_rename_0; // @[core.scala:50:7, :164:26] wire [2:0] int_wakeups_0_bits_uop_imm_sel = io_lsu_iwakeups_0_bits_uop_imm_sel_0; // @[core.scala:50:7, :164:26] wire [4:0] int_wakeups_0_bits_uop_pimm = io_lsu_iwakeups_0_bits_uop_pimm_0; // @[core.scala:50:7, :164:26] wire [19:0] int_wakeups_0_bits_uop_imm_packed = io_lsu_iwakeups_0_bits_uop_imm_packed_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_op1_sel = io_lsu_iwakeups_0_bits_uop_op1_sel_0; // @[core.scala:50:7, :164:26] wire [2:0] int_wakeups_0_bits_uop_op2_sel = io_lsu_iwakeups_0_bits_uop_op2_sel_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_ldst = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ldst_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_wen = io_lsu_iwakeups_0_bits_uop_fp_ctrl_wen_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_ren1 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren1_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_ren2 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren2_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_ren3 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_ren3_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_swap12 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap12_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_swap23 = io_lsu_iwakeups_0_bits_uop_fp_ctrl_swap23_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_fp_ctrl_typeTagIn = io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagIn_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_fp_ctrl_typeTagOut = io_lsu_iwakeups_0_bits_uop_fp_ctrl_typeTagOut_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_fromint = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fromint_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_toint = io_lsu_iwakeups_0_bits_uop_fp_ctrl_toint_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_fastpipe = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fastpipe_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_fma = io_lsu_iwakeups_0_bits_uop_fp_ctrl_fma_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_div = io_lsu_iwakeups_0_bits_uop_fp_ctrl_div_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_sqrt = io_lsu_iwakeups_0_bits_uop_fp_ctrl_sqrt_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_wflags = io_lsu_iwakeups_0_bits_uop_fp_ctrl_wflags_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_ctrl_vec = io_lsu_iwakeups_0_bits_uop_fp_ctrl_vec_0; // @[core.scala:50:7, :164:26] wire [5:0] int_wakeups_0_bits_uop_rob_idx = io_lsu_iwakeups_0_bits_uop_rob_idx_0; // @[core.scala:50:7, :164:26] wire [3:0] int_wakeups_0_bits_uop_ldq_idx = io_lsu_iwakeups_0_bits_uop_ldq_idx_0; // @[core.scala:50:7, :164:26] wire [3:0] int_wakeups_0_bits_uop_stq_idx = io_lsu_iwakeups_0_bits_uop_stq_idx_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_rxq_idx = io_lsu_iwakeups_0_bits_uop_rxq_idx_0; // @[core.scala:50:7, :164:26] wire [6:0] int_wakeups_0_bits_uop_pdst = io_lsu_iwakeups_0_bits_uop_pdst_0; // @[core.scala:50:7, :164:26] wire [6:0] int_wakeups_0_bits_uop_prs1 = io_lsu_iwakeups_0_bits_uop_prs1_0; // @[core.scala:50:7, :164:26] wire [6:0] int_wakeups_0_bits_uop_prs2 = io_lsu_iwakeups_0_bits_uop_prs2_0; // @[core.scala:50:7, :164:26] wire [6:0] int_wakeups_0_bits_uop_prs3 = io_lsu_iwakeups_0_bits_uop_prs3_0; // @[core.scala:50:7, :164:26] wire [4:0] int_wakeups_0_bits_uop_ppred = io_lsu_iwakeups_0_bits_uop_ppred_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_prs1_busy = io_lsu_iwakeups_0_bits_uop_prs1_busy_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_prs2_busy = io_lsu_iwakeups_0_bits_uop_prs2_busy_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_prs3_busy = io_lsu_iwakeups_0_bits_uop_prs3_busy_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_ppred_busy = io_lsu_iwakeups_0_bits_uop_ppred_busy_0; // @[core.scala:50:7, :164:26] wire [6:0] int_wakeups_0_bits_uop_stale_pdst = io_lsu_iwakeups_0_bits_uop_stale_pdst_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_exception = io_lsu_iwakeups_0_bits_uop_exception_0; // @[core.scala:50:7, :164:26] wire [63:0] int_wakeups_0_bits_uop_exc_cause = io_lsu_iwakeups_0_bits_uop_exc_cause_0; // @[core.scala:50:7, :164:26] wire [4:0] int_wakeups_0_bits_uop_mem_cmd = io_lsu_iwakeups_0_bits_uop_mem_cmd_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_mem_size = io_lsu_iwakeups_0_bits_uop_mem_size_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_mem_signed = io_lsu_iwakeups_0_bits_uop_mem_signed_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_uses_ldq = io_lsu_iwakeups_0_bits_uop_uses_ldq_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_uses_stq = io_lsu_iwakeups_0_bits_uop_uses_stq_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_is_unique = io_lsu_iwakeups_0_bits_uop_is_unique_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_flush_on_commit = io_lsu_iwakeups_0_bits_uop_flush_on_commit_0; // @[core.scala:50:7, :164:26] wire [2:0] int_wakeups_0_bits_uop_csr_cmd = io_lsu_iwakeups_0_bits_uop_csr_cmd_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_ldst_is_rs1 = io_lsu_iwakeups_0_bits_uop_ldst_is_rs1_0; // @[core.scala:50:7, :164:26] wire [5:0] int_wakeups_0_bits_uop_ldst = io_lsu_iwakeups_0_bits_uop_ldst_0; // @[core.scala:50:7, :164:26] wire [5:0] int_wakeups_0_bits_uop_lrs1 = io_lsu_iwakeups_0_bits_uop_lrs1_0; // @[core.scala:50:7, :164:26] wire [5:0] int_wakeups_0_bits_uop_lrs2 = io_lsu_iwakeups_0_bits_uop_lrs2_0; // @[core.scala:50:7, :164:26] wire [5:0] int_wakeups_0_bits_uop_lrs3 = io_lsu_iwakeups_0_bits_uop_lrs3_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_dst_rtype = io_lsu_iwakeups_0_bits_uop_dst_rtype_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_lrs1_rtype = io_lsu_iwakeups_0_bits_uop_lrs1_rtype_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_lrs2_rtype = io_lsu_iwakeups_0_bits_uop_lrs2_rtype_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_frs3_en = io_lsu_iwakeups_0_bits_uop_frs3_en_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fcn_dw = io_lsu_iwakeups_0_bits_uop_fcn_dw_0; // @[core.scala:50:7, :164:26] wire [4:0] int_wakeups_0_bits_uop_fcn_op = io_lsu_iwakeups_0_bits_uop_fcn_op_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_fp_val = io_lsu_iwakeups_0_bits_uop_fp_val_0; // @[core.scala:50:7, :164:26] wire [2:0] int_wakeups_0_bits_uop_fp_rm = io_lsu_iwakeups_0_bits_uop_fp_rm_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_uop_fp_typ = io_lsu_iwakeups_0_bits_uop_fp_typ_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_xcpt_pf_if = io_lsu_iwakeups_0_bits_uop_xcpt_pf_if_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_xcpt_ae_if = io_lsu_iwakeups_0_bits_uop_xcpt_ae_if_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_xcpt_ma_if = io_lsu_iwakeups_0_bits_uop_xcpt_ma_if_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_bp_debug_if = io_lsu_iwakeups_0_bits_uop_bp_debug_if_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_uop_bp_xcpt_if = io_lsu_iwakeups_0_bits_uop_bp_xcpt_if_0; // @[core.scala:50:7, :164:26] wire [2:0] int_wakeups_0_bits_uop_debug_fsrc = io_lsu_iwakeups_0_bits_uop_debug_fsrc_0; // @[core.scala:50:7, :164:26] wire [2:0] int_wakeups_0_bits_uop_debug_tsrc = io_lsu_iwakeups_0_bits_uop_debug_tsrc_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_bypassable = io_lsu_iwakeups_0_bits_bypassable_0; // @[core.scala:50:7, :164:26] wire [1:0] int_wakeups_0_bits_speculative_mask = io_lsu_iwakeups_0_bits_speculative_mask_0; // @[core.scala:50:7, :164:26] wire int_wakeups_0_bits_rebusy = io_lsu_iwakeups_0_bits_rebusy_0; // @[core.scala:50:7, :164:26] wire [31:0] rob_io_wb_resps_0_out_bits_uop_inst = io_lsu_iresp_0_bits_uop_inst_0; // @[util.scala:114:23] wire [31:0] rob_io_wb_resps_0_out_bits_uop_debug_inst = io_lsu_iresp_0_bits_uop_debug_inst_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_is_rvc = io_lsu_iresp_0_bits_uop_is_rvc_0; // @[util.scala:114:23] wire [39:0] rob_io_wb_resps_0_out_bits_uop_debug_pc = io_lsu_iresp_0_bits_uop_debug_pc_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_iq_type_0 = io_lsu_iresp_0_bits_uop_iq_type_0_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_iq_type_1 = io_lsu_iresp_0_bits_uop_iq_type_1_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_iq_type_2 = io_lsu_iresp_0_bits_uop_iq_type_2_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_iq_type_3 = io_lsu_iresp_0_bits_uop_iq_type_3_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fu_code_0 = io_lsu_iresp_0_bits_uop_fu_code_0_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fu_code_1 = io_lsu_iresp_0_bits_uop_fu_code_1_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fu_code_2 = io_lsu_iresp_0_bits_uop_fu_code_2_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fu_code_3 = io_lsu_iresp_0_bits_uop_fu_code_3_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fu_code_4 = io_lsu_iresp_0_bits_uop_fu_code_4_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fu_code_5 = io_lsu_iresp_0_bits_uop_fu_code_5_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fu_code_6 = io_lsu_iresp_0_bits_uop_fu_code_6_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fu_code_7 = io_lsu_iresp_0_bits_uop_fu_code_7_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fu_code_8 = io_lsu_iresp_0_bits_uop_fu_code_8_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fu_code_9 = io_lsu_iresp_0_bits_uop_fu_code_9_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_iw_issued = io_lsu_iresp_0_bits_uop_iw_issued_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_iw_issued_partial_agen = io_lsu_iresp_0_bits_uop_iw_issued_partial_agen_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_iw_issued_partial_dgen = io_lsu_iresp_0_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_iw_p1_speculative_child = io_lsu_iresp_0_bits_uop_iw_p1_speculative_child_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_iw_p2_speculative_child = io_lsu_iresp_0_bits_uop_iw_p2_speculative_child_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_iw_p1_bypass_hint = io_lsu_iresp_0_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_iw_p2_bypass_hint = io_lsu_iresp_0_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_iw_p3_bypass_hint = io_lsu_iresp_0_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_dis_col_sel = io_lsu_iresp_0_bits_uop_dis_col_sel_0; // @[util.scala:114:23] wire [3:0] rob_io_wb_resps_0_out_bits_uop_br_tag = io_lsu_iresp_0_bits_uop_br_tag_0; // @[util.scala:114:23] wire [3:0] rob_io_wb_resps_0_out_bits_uop_br_type = io_lsu_iresp_0_bits_uop_br_type_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_is_sfb = io_lsu_iresp_0_bits_uop_is_sfb_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_is_fence = io_lsu_iresp_0_bits_uop_is_fence_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_is_fencei = io_lsu_iresp_0_bits_uop_is_fencei_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_is_sfence = io_lsu_iresp_0_bits_uop_is_sfence_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_is_amo = io_lsu_iresp_0_bits_uop_is_amo_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_is_eret = io_lsu_iresp_0_bits_uop_is_eret_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_is_sys_pc2epc = io_lsu_iresp_0_bits_uop_is_sys_pc2epc_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_is_rocc = io_lsu_iresp_0_bits_uop_is_rocc_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_is_mov = io_lsu_iresp_0_bits_uop_is_mov_0; // @[util.scala:114:23] wire [4:0] rob_io_wb_resps_0_out_bits_uop_ftq_idx = io_lsu_iresp_0_bits_uop_ftq_idx_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_edge_inst = io_lsu_iresp_0_bits_uop_edge_inst_0; // @[util.scala:114:23] wire [5:0] rob_io_wb_resps_0_out_bits_uop_pc_lob = io_lsu_iresp_0_bits_uop_pc_lob_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_taken = io_lsu_iresp_0_bits_uop_taken_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_imm_rename = io_lsu_iresp_0_bits_uop_imm_rename_0; // @[util.scala:114:23] wire [2:0] rob_io_wb_resps_0_out_bits_uop_imm_sel = io_lsu_iresp_0_bits_uop_imm_sel_0; // @[util.scala:114:23] wire [4:0] rob_io_wb_resps_0_out_bits_uop_pimm = io_lsu_iresp_0_bits_uop_pimm_0; // @[util.scala:114:23] wire [19:0] rob_io_wb_resps_0_out_bits_uop_imm_packed = io_lsu_iresp_0_bits_uop_imm_packed_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_op1_sel = io_lsu_iresp_0_bits_uop_op1_sel_0; // @[util.scala:114:23] wire [2:0] rob_io_wb_resps_0_out_bits_uop_op2_sel = io_lsu_iresp_0_bits_uop_op2_sel_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_ldst = io_lsu_iresp_0_bits_uop_fp_ctrl_ldst_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_wen = io_lsu_iresp_0_bits_uop_fp_ctrl_wen_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_ren1 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren1_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_ren2 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren2_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_ren3 = io_lsu_iresp_0_bits_uop_fp_ctrl_ren3_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_swap12 = io_lsu_iresp_0_bits_uop_fp_ctrl_swap12_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_swap23 = io_lsu_iresp_0_bits_uop_fp_ctrl_swap23_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_fp_ctrl_typeTagIn = io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_fp_ctrl_typeTagOut = io_lsu_iresp_0_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_fromint = io_lsu_iresp_0_bits_uop_fp_ctrl_fromint_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_toint = io_lsu_iresp_0_bits_uop_fp_ctrl_toint_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_fastpipe = io_lsu_iresp_0_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_fma = io_lsu_iresp_0_bits_uop_fp_ctrl_fma_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_div = io_lsu_iresp_0_bits_uop_fp_ctrl_div_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_sqrt = io_lsu_iresp_0_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_wflags = io_lsu_iresp_0_bits_uop_fp_ctrl_wflags_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_ctrl_vec = io_lsu_iresp_0_bits_uop_fp_ctrl_vec_0; // @[util.scala:114:23] wire [5:0] rob_io_wb_resps_0_out_bits_uop_rob_idx = io_lsu_iresp_0_bits_uop_rob_idx_0; // @[util.scala:114:23] wire [3:0] rob_io_wb_resps_0_out_bits_uop_ldq_idx = io_lsu_iresp_0_bits_uop_ldq_idx_0; // @[util.scala:114:23] wire [3:0] rob_io_wb_resps_0_out_bits_uop_stq_idx = io_lsu_iresp_0_bits_uop_stq_idx_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_rxq_idx = io_lsu_iresp_0_bits_uop_rxq_idx_0; // @[util.scala:114:23] wire [6:0] rob_io_wb_resps_0_out_bits_uop_pdst = io_lsu_iresp_0_bits_uop_pdst_0; // @[util.scala:114:23] wire [6:0] rob_io_wb_resps_0_out_bits_uop_prs1 = io_lsu_iresp_0_bits_uop_prs1_0; // @[util.scala:114:23] wire [6:0] rob_io_wb_resps_0_out_bits_uop_prs2 = io_lsu_iresp_0_bits_uop_prs2_0; // @[util.scala:114:23] wire [6:0] rob_io_wb_resps_0_out_bits_uop_prs3 = io_lsu_iresp_0_bits_uop_prs3_0; // @[util.scala:114:23] wire [4:0] rob_io_wb_resps_0_out_bits_uop_ppred = io_lsu_iresp_0_bits_uop_ppred_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_prs1_busy = io_lsu_iresp_0_bits_uop_prs1_busy_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_prs2_busy = io_lsu_iresp_0_bits_uop_prs2_busy_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_prs3_busy = io_lsu_iresp_0_bits_uop_prs3_busy_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_ppred_busy = io_lsu_iresp_0_bits_uop_ppred_busy_0; // @[util.scala:114:23] wire [6:0] rob_io_wb_resps_0_out_bits_uop_stale_pdst = io_lsu_iresp_0_bits_uop_stale_pdst_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_exception = io_lsu_iresp_0_bits_uop_exception_0; // @[util.scala:114:23] wire [63:0] rob_io_wb_resps_0_out_bits_uop_exc_cause = io_lsu_iresp_0_bits_uop_exc_cause_0; // @[util.scala:114:23] wire [4:0] rob_io_wb_resps_0_out_bits_uop_mem_cmd = io_lsu_iresp_0_bits_uop_mem_cmd_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_mem_size = io_lsu_iresp_0_bits_uop_mem_size_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_mem_signed = io_lsu_iresp_0_bits_uop_mem_signed_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_uses_ldq = io_lsu_iresp_0_bits_uop_uses_ldq_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_uses_stq = io_lsu_iresp_0_bits_uop_uses_stq_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_is_unique = io_lsu_iresp_0_bits_uop_is_unique_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_flush_on_commit = io_lsu_iresp_0_bits_uop_flush_on_commit_0; // @[util.scala:114:23] wire [2:0] rob_io_wb_resps_0_out_bits_uop_csr_cmd = io_lsu_iresp_0_bits_uop_csr_cmd_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_ldst_is_rs1 = io_lsu_iresp_0_bits_uop_ldst_is_rs1_0; // @[util.scala:114:23] wire [5:0] rob_io_wb_resps_0_out_bits_uop_ldst = io_lsu_iresp_0_bits_uop_ldst_0; // @[util.scala:114:23] wire [5:0] rob_io_wb_resps_0_out_bits_uop_lrs1 = io_lsu_iresp_0_bits_uop_lrs1_0; // @[util.scala:114:23] wire [5:0] rob_io_wb_resps_0_out_bits_uop_lrs2 = io_lsu_iresp_0_bits_uop_lrs2_0; // @[util.scala:114:23] wire [5:0] rob_io_wb_resps_0_out_bits_uop_lrs3 = io_lsu_iresp_0_bits_uop_lrs3_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_dst_rtype = io_lsu_iresp_0_bits_uop_dst_rtype_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_lrs1_rtype = io_lsu_iresp_0_bits_uop_lrs1_rtype_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_lrs2_rtype = io_lsu_iresp_0_bits_uop_lrs2_rtype_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_frs3_en = io_lsu_iresp_0_bits_uop_frs3_en_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fcn_dw = io_lsu_iresp_0_bits_uop_fcn_dw_0; // @[util.scala:114:23] wire [4:0] rob_io_wb_resps_0_out_bits_uop_fcn_op = io_lsu_iresp_0_bits_uop_fcn_op_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_fp_val = io_lsu_iresp_0_bits_uop_fp_val_0; // @[util.scala:114:23] wire [2:0] rob_io_wb_resps_0_out_bits_uop_fp_rm = io_lsu_iresp_0_bits_uop_fp_rm_0; // @[util.scala:114:23] wire [1:0] rob_io_wb_resps_0_out_bits_uop_fp_typ = io_lsu_iresp_0_bits_uop_fp_typ_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_xcpt_pf_if = io_lsu_iresp_0_bits_uop_xcpt_pf_if_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_xcpt_ae_if = io_lsu_iresp_0_bits_uop_xcpt_ae_if_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_xcpt_ma_if = io_lsu_iresp_0_bits_uop_xcpt_ma_if_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_bp_debug_if = io_lsu_iresp_0_bits_uop_bp_debug_if_0; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_bits_uop_bp_xcpt_if = io_lsu_iresp_0_bits_uop_bp_xcpt_if_0; // @[util.scala:114:23] wire [2:0] rob_io_wb_resps_0_out_bits_uop_debug_fsrc = io_lsu_iresp_0_bits_uop_debug_fsrc_0; // @[util.scala:114:23] wire [2:0] rob_io_wb_resps_0_out_bits_uop_debug_tsrc = io_lsu_iresp_0_bits_uop_debug_tsrc_0; // @[util.scala:114:23] wire [63:0] rob_io_wb_resps_0_out_bits_data = io_lsu_iresp_0_bits_data_0; // @[util.scala:114:23] wire dis_fire_0; // @[core.scala:191:24] wire [31:0] dis_uops_0_inst; // @[core.scala:190:24] wire [31:0] dis_uops_0_debug_inst; // @[core.scala:190:24] wire dis_uops_0_is_rvc; // @[core.scala:190:24] wire [39:0] dis_uops_0_debug_pc; // @[core.scala:190:24] wire dis_uops_0_iq_type_0; // @[core.scala:190:24] wire dis_uops_0_iq_type_1; // @[core.scala:190:24] wire dis_uops_0_iq_type_2; // @[core.scala:190:24] wire dis_uops_0_iq_type_3; // @[core.scala:190:24] wire dis_uops_0_fu_code_0; // @[core.scala:190:24] wire dis_uops_0_fu_code_1; // @[core.scala:190:24] wire dis_uops_0_fu_code_2; // @[core.scala:190:24] wire dis_uops_0_fu_code_3; // @[core.scala:190:24] wire dis_uops_0_fu_code_4; // @[core.scala:190:24] wire dis_uops_0_fu_code_5; // @[core.scala:190:24] wire dis_uops_0_fu_code_6; // @[core.scala:190:24] wire dis_uops_0_fu_code_7; // @[core.scala:190:24] wire dis_uops_0_fu_code_8; // @[core.scala:190:24] wire dis_uops_0_fu_code_9; // @[core.scala:190:24] wire dis_uops_0_iw_issued; // @[core.scala:190:24] wire dis_uops_0_iw_issued_partial_agen; // @[core.scala:190:24] wire dis_uops_0_iw_issued_partial_dgen; // @[core.scala:190:24] wire [1:0] dis_uops_0_iw_p1_speculative_child; // @[core.scala:190:24] wire [1:0] dis_uops_0_iw_p2_speculative_child; // @[core.scala:190:24] wire dis_uops_0_iw_p1_bypass_hint; // @[core.scala:190:24] wire dis_uops_0_iw_p2_bypass_hint; // @[core.scala:190:24] wire dis_uops_0_iw_p3_bypass_hint; // @[core.scala:190:24] wire [1:0] dis_uops_0_dis_col_sel; // @[core.scala:190:24] wire [11:0] dis_uops_0_br_mask; // @[core.scala:190:24] wire [3:0] dis_uops_0_br_tag; // @[core.scala:190:24] wire [3:0] dis_uops_0_br_type; // @[core.scala:190:24] wire dis_uops_0_is_sfb; // @[core.scala:190:24] wire dis_uops_0_is_fence; // @[core.scala:190:24] wire dis_uops_0_is_fencei; // @[core.scala:190:24] wire dis_uops_0_is_sfence; // @[core.scala:190:24] wire dis_uops_0_is_amo; // @[core.scala:190:24] wire dis_uops_0_is_eret; // @[core.scala:190:24] wire dis_uops_0_is_sys_pc2epc; // @[core.scala:190:24] wire dis_uops_0_is_rocc; // @[core.scala:190:24] wire dis_uops_0_is_mov; // @[core.scala:190:24] wire [4:0] dis_uops_0_ftq_idx; // @[core.scala:190:24] wire dis_uops_0_edge_inst; // @[core.scala:190:24] wire [5:0] dis_uops_0_pc_lob; // @[core.scala:190:24] wire dis_uops_0_taken; // @[core.scala:190:24] wire dis_uops_0_imm_rename; // @[core.scala:190:24] wire [2:0] dis_uops_0_imm_sel; // @[core.scala:190:24] wire [4:0] dis_uops_0_pimm; // @[core.scala:190:24] wire [19:0] dis_uops_0_imm_packed; // @[core.scala:190:24] wire [1:0] dis_uops_0_op1_sel; // @[core.scala:190:24] wire [2:0] dis_uops_0_op2_sel; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_ldst; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_wen; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_ren1; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_ren2; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_ren3; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_swap12; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_swap23; // @[core.scala:190:24] wire [1:0] dis_uops_0_fp_ctrl_typeTagIn; // @[core.scala:190:24] wire [1:0] dis_uops_0_fp_ctrl_typeTagOut; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_fromint; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_toint; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_fastpipe; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_fma; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_div; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_sqrt; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_wflags; // @[core.scala:190:24] wire dis_uops_0_fp_ctrl_vec; // @[core.scala:190:24] wire [5:0] dis_uops_0_rob_idx; // @[core.scala:190:24] wire [3:0] dis_uops_0_ldq_idx; // @[core.scala:190:24] wire [3:0] dis_uops_0_stq_idx; // @[core.scala:190:24] wire [1:0] dis_uops_0_rxq_idx; // @[core.scala:190:24] wire [6:0] dis_uops_0_pdst; // @[core.scala:190:24] wire [6:0] dis_uops_0_prs1; // @[core.scala:190:24] wire [6:0] dis_uops_0_prs2; // @[core.scala:190:24] wire [6:0] dis_uops_0_prs3; // @[core.scala:190:24] wire [4:0] dis_uops_0_ppred; // @[core.scala:190:24] wire dis_uops_0_prs1_busy; // @[core.scala:190:24] wire dis_uops_0_prs2_busy; // @[core.scala:190:24] wire dis_uops_0_prs3_busy; // @[core.scala:190:24] wire dis_uops_0_ppred_busy; // @[core.scala:190:24] wire [6:0] dis_uops_0_stale_pdst; // @[core.scala:190:24] wire dis_uops_0_exception; // @[core.scala:190:24] wire [63:0] dis_uops_0_exc_cause; // @[core.scala:190:24] wire [4:0] dis_uops_0_mem_cmd; // @[core.scala:190:24] wire [1:0] dis_uops_0_mem_size; // @[core.scala:190:24] wire dis_uops_0_mem_signed; // @[core.scala:190:24] wire dis_uops_0_uses_ldq; // @[core.scala:190:24] wire dis_uops_0_uses_stq; // @[core.scala:190:24] wire dis_uops_0_is_unique; // @[core.scala:190:24] wire dis_uops_0_flush_on_commit; // @[core.scala:190:24] wire [2:0] dis_uops_0_csr_cmd; // @[core.scala:190:24] wire dis_uops_0_ldst_is_rs1; // @[core.scala:190:24] wire [5:0] dis_uops_0_ldst; // @[core.scala:190:24] wire [5:0] dis_uops_0_lrs1; // @[core.scala:190:24] wire [5:0] dis_uops_0_lrs2; // @[core.scala:190:24] wire [5:0] dis_uops_0_lrs3; // @[core.scala:190:24] wire [1:0] dis_uops_0_dst_rtype; // @[core.scala:190:24] wire [1:0] dis_uops_0_lrs1_rtype; // @[core.scala:190:24] wire [1:0] dis_uops_0_lrs2_rtype; // @[core.scala:190:24] wire dis_uops_0_frs3_en; // @[core.scala:190:24] wire dis_uops_0_fcn_dw; // @[core.scala:190:24] wire [4:0] dis_uops_0_fcn_op; // @[core.scala:190:24] wire dis_uops_0_fp_val; // @[core.scala:190:24] wire [2:0] dis_uops_0_fp_rm; // @[core.scala:190:24] wire [1:0] dis_uops_0_fp_typ; // @[core.scala:190:24] wire dis_uops_0_xcpt_pf_if; // @[core.scala:190:24] wire dis_uops_0_xcpt_ae_if; // @[core.scala:190:24] wire dis_uops_0_xcpt_ma_if; // @[core.scala:190:24] wire dis_uops_0_bp_debug_if; // @[core.scala:190:24] wire dis_uops_0_bp_xcpt_if; // @[core.scala:190:24] wire [2:0] dis_uops_0_debug_fsrc; // @[core.scala:190:24] wire [2:0] dis_uops_0_debug_tsrc; // @[core.scala:190:24] wire dis_fire_1; // @[core.scala:191:24] wire [31:0] dis_uops_1_inst; // @[core.scala:190:24] wire [31:0] dis_uops_1_debug_inst; // @[core.scala:190:24] wire dis_uops_1_is_rvc; // @[core.scala:190:24] wire [39:0] dis_uops_1_debug_pc; // @[core.scala:190:24] wire dis_uops_1_iq_type_0; // @[core.scala:190:24] wire dis_uops_1_iq_type_1; // @[core.scala:190:24] wire dis_uops_1_iq_type_2; // @[core.scala:190:24] wire dis_uops_1_iq_type_3; // @[core.scala:190:24] wire dis_uops_1_fu_code_0; // @[core.scala:190:24] wire dis_uops_1_fu_code_1; // @[core.scala:190:24] wire dis_uops_1_fu_code_2; // @[core.scala:190:24] wire dis_uops_1_fu_code_3; // @[core.scala:190:24] wire dis_uops_1_fu_code_4; // @[core.scala:190:24] wire dis_uops_1_fu_code_5; // @[core.scala:190:24] wire dis_uops_1_fu_code_6; // @[core.scala:190:24] wire dis_uops_1_fu_code_7; // @[core.scala:190:24] wire dis_uops_1_fu_code_8; // @[core.scala:190:24] wire dis_uops_1_fu_code_9; // @[core.scala:190:24] wire dis_uops_1_iw_issued; // @[core.scala:190:24] wire dis_uops_1_iw_issued_partial_agen; // @[core.scala:190:24] wire dis_uops_1_iw_issued_partial_dgen; // @[core.scala:190:24] wire [1:0] dis_uops_1_iw_p1_speculative_child; // @[core.scala:190:24] wire [1:0] dis_uops_1_iw_p2_speculative_child; // @[core.scala:190:24] wire dis_uops_1_iw_p1_bypass_hint; // @[core.scala:190:24] wire dis_uops_1_iw_p2_bypass_hint; // @[core.scala:190:24] wire dis_uops_1_iw_p3_bypass_hint; // @[core.scala:190:24] wire [1:0] dis_uops_1_dis_col_sel; // @[core.scala:190:24] wire [11:0] dis_uops_1_br_mask; // @[core.scala:190:24] wire [3:0] dis_uops_1_br_tag; // @[core.scala:190:24] wire [3:0] dis_uops_1_br_type; // @[core.scala:190:24] wire dis_uops_1_is_sfb; // @[core.scala:190:24] wire dis_uops_1_is_fence; // @[core.scala:190:24] wire dis_uops_1_is_fencei; // @[core.scala:190:24] wire dis_uops_1_is_sfence; // @[core.scala:190:24] wire dis_uops_1_is_amo; // @[core.scala:190:24] wire dis_uops_1_is_eret; // @[core.scala:190:24] wire dis_uops_1_is_sys_pc2epc; // @[core.scala:190:24] wire dis_uops_1_is_rocc; // @[core.scala:190:24] wire dis_uops_1_is_mov; // @[core.scala:190:24] wire [4:0] dis_uops_1_ftq_idx; // @[core.scala:190:24] wire dis_uops_1_edge_inst; // @[core.scala:190:24] wire [5:0] dis_uops_1_pc_lob; // @[core.scala:190:24] wire dis_uops_1_taken; // @[core.scala:190:24] wire dis_uops_1_imm_rename; // @[core.scala:190:24] wire [2:0] dis_uops_1_imm_sel; // @[core.scala:190:24] wire [4:0] dis_uops_1_pimm; // @[core.scala:190:24] wire [19:0] dis_uops_1_imm_packed; // @[core.scala:190:24] wire [1:0] dis_uops_1_op1_sel; // @[core.scala:190:24] wire [2:0] dis_uops_1_op2_sel; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_ldst; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_wen; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_ren1; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_ren2; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_ren3; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_swap12; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_swap23; // @[core.scala:190:24] wire [1:0] dis_uops_1_fp_ctrl_typeTagIn; // @[core.scala:190:24] wire [1:0] dis_uops_1_fp_ctrl_typeTagOut; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_fromint; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_toint; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_fastpipe; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_fma; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_div; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_sqrt; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_wflags; // @[core.scala:190:24] wire dis_uops_1_fp_ctrl_vec; // @[core.scala:190:24] wire [5:0] dis_uops_1_rob_idx; // @[core.scala:190:24] wire [3:0] dis_uops_1_ldq_idx; // @[core.scala:190:24] wire [3:0] dis_uops_1_stq_idx; // @[core.scala:190:24] wire [1:0] dis_uops_1_rxq_idx; // @[core.scala:190:24] wire [6:0] dis_uops_1_pdst; // @[core.scala:190:24] wire [6:0] dis_uops_1_prs1; // @[core.scala:190:24] wire [6:0] dis_uops_1_prs2; // @[core.scala:190:24] wire [6:0] dis_uops_1_prs3; // @[core.scala:190:24] wire [4:0] dis_uops_1_ppred; // @[core.scala:190:24] wire dis_uops_1_prs1_busy; // @[core.scala:190:24] wire dis_uops_1_prs2_busy; // @[core.scala:190:24] wire dis_uops_1_prs3_busy; // @[core.scala:190:24] wire dis_uops_1_ppred_busy; // @[core.scala:190:24] wire [6:0] dis_uops_1_stale_pdst; // @[core.scala:190:24] wire dis_uops_1_exception; // @[core.scala:190:24] wire [63:0] dis_uops_1_exc_cause; // @[core.scala:190:24] wire [4:0] dis_uops_1_mem_cmd; // @[core.scala:190:24] wire [1:0] dis_uops_1_mem_size; // @[core.scala:190:24] wire dis_uops_1_mem_signed; // @[core.scala:190:24] wire dis_uops_1_uses_ldq; // @[core.scala:190:24] wire dis_uops_1_uses_stq; // @[core.scala:190:24] wire dis_uops_1_is_unique; // @[core.scala:190:24] wire dis_uops_1_flush_on_commit; // @[core.scala:190:24] wire [2:0] dis_uops_1_csr_cmd; // @[core.scala:190:24] wire dis_uops_1_ldst_is_rs1; // @[core.scala:190:24] wire [5:0] dis_uops_1_ldst; // @[core.scala:190:24] wire [5:0] dis_uops_1_lrs1; // @[core.scala:190:24] wire [5:0] dis_uops_1_lrs2; // @[core.scala:190:24] wire [5:0] dis_uops_1_lrs3; // @[core.scala:190:24] wire [1:0] dis_uops_1_dst_rtype; // @[core.scala:190:24] wire [1:0] dis_uops_1_lrs1_rtype; // @[core.scala:190:24] wire [1:0] dis_uops_1_lrs2_rtype; // @[core.scala:190:24] wire dis_uops_1_frs3_en; // @[core.scala:190:24] wire dis_uops_1_fcn_dw; // @[core.scala:190:24] wire [4:0] dis_uops_1_fcn_op; // @[core.scala:190:24] wire dis_uops_1_fp_val; // @[core.scala:190:24] wire [2:0] dis_uops_1_fp_rm; // @[core.scala:190:24] wire [1:0] dis_uops_1_fp_typ; // @[core.scala:190:24] wire dis_uops_1_xcpt_pf_if; // @[core.scala:190:24] wire dis_uops_1_xcpt_ae_if; // @[core.scala:190:24] wire dis_uops_1_xcpt_ma_if; // @[core.scala:190:24] wire dis_uops_1_bp_debug_if; // @[core.scala:190:24] wire dis_uops_1_bp_xcpt_if; // @[core.scala:190:24] wire [2:0] dis_uops_1_debug_fsrc; // @[core.scala:190:24] wire [2:0] dis_uops_1_debug_tsrc; // @[core.scala:190:24] assign dis_uops_0_ldq_idx = io_lsu_dis_ldq_idx_0_0; // @[core.scala:50:7, :190:24] assign dis_uops_1_ldq_idx = io_lsu_dis_ldq_idx_1_0; // @[core.scala:50:7, :190:24] assign dis_uops_0_stq_idx = io_lsu_dis_stq_idx_0_0; // @[core.scala:50:7, :190:24] assign dis_uops_1_stq_idx = io_lsu_dis_stq_idx_1_0; // @[core.scala:50:7, :190:24] wire _io_lsu_fence_dmem_T_2; // @[core.scala:765:101] wire hits_2_1 = io_lsu_perf_acquire_0; // @[Events.scala:13:25] wire hits_2_2 = io_lsu_perf_release_0; // @[Events.scala:13:25] wire hits_2_4 = io_lsu_perf_tlbMiss_0; // @[Events.scala:13:25] wire io_ifu_fetchpacket_ready_0; // @[core.scala:50:7] wire [4:0] io_ifu_arb_ftq_reqs_0_0; // @[core.scala:50:7] wire [4:0] io_ifu_arb_ftq_reqs_1_0; // @[core.scala:50:7] wire [4:0] io_ifu_arb_ftq_reqs_2_0; // @[core.scala:50:7] wire io_ifu_status_debug_0; // @[core.scala:50:7] wire io_ifu_status_cease_0; // @[core.scala:50:7] wire io_ifu_status_wfi_0; // @[core.scala:50:7] wire [1:0] io_ifu_status_dprv_0; // @[core.scala:50:7] wire io_ifu_status_dv_0; // @[core.scala:50:7] wire [1:0] io_ifu_status_prv_0; // @[core.scala:50:7] wire io_ifu_status_v_0; // @[core.scala:50:7] wire io_ifu_status_sd_0; // @[core.scala:50:7] wire io_ifu_status_mpv_0; // @[core.scala:50:7] wire io_ifu_status_gva_0; // @[core.scala:50:7] wire io_ifu_status_tsr_0; // @[core.scala:50:7] wire io_ifu_status_tw_0; // @[core.scala:50:7] wire io_ifu_status_tvm_0; // @[core.scala:50:7] wire io_ifu_status_mxr_0; // @[core.scala:50:7] wire io_ifu_status_sum_0; // @[core.scala:50:7] wire io_ifu_status_mprv_0; // @[core.scala:50:7] wire [1:0] io_ifu_status_fs_0; // @[core.scala:50:7] wire [1:0] io_ifu_status_mpp_0; // @[core.scala:50:7] wire io_ifu_status_spp_0; // @[core.scala:50:7] wire io_ifu_status_mpie_0; // @[core.scala:50:7] wire io_ifu_status_spie_0; // @[core.scala:50:7] wire io_ifu_status_mie_0; // @[core.scala:50:7] wire io_ifu_status_sie_0; // @[core.scala:50:7] wire [11:0] io_ifu_brupdate_b1_resolve_mask_0; // @[core.scala:50:7] wire [11:0] io_ifu_brupdate_b1_mispredict_mask_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_iq_type_0_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_iq_type_1_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_iq_type_2_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_iq_type_3_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fu_code_0_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fu_code_1_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fu_code_2_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fu_code_3_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fu_code_4_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fu_code_5_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fu_code_6_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fu_code_7_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fu_code_8_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fu_code_9_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_ldst_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_wen_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_ren1_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_ren2_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_ren3_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_swap12_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_swap23_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_fromint_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_toint_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_fma_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_div_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_wflags_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_ctrl_vec_0; // @[core.scala:50:7] wire [31:0] io_ifu_brupdate_b2_uop_inst_0; // @[core.scala:50:7] wire [31:0] io_ifu_brupdate_b2_uop_debug_inst_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_is_rvc_0; // @[core.scala:50:7] wire [39:0] io_ifu_brupdate_b2_uop_debug_pc_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_iw_issued_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_iw_issued_partial_agen_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_iw_p1_speculative_child_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_iw_p2_speculative_child_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_dis_col_sel_0; // @[core.scala:50:7] wire [11:0] io_ifu_brupdate_b2_uop_br_mask_0; // @[core.scala:50:7] wire [3:0] io_ifu_brupdate_b2_uop_br_tag_0; // @[core.scala:50:7] wire [3:0] io_ifu_brupdate_b2_uop_br_type_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_is_sfb_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_is_fence_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_is_fencei_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_is_sfence_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_is_amo_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_is_eret_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_is_sys_pc2epc_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_is_rocc_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_is_mov_0; // @[core.scala:50:7] wire [4:0] io_ifu_brupdate_b2_uop_ftq_idx_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_edge_inst_0; // @[core.scala:50:7] wire [5:0] io_ifu_brupdate_b2_uop_pc_lob_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_taken_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_imm_rename_0; // @[core.scala:50:7] wire [2:0] io_ifu_brupdate_b2_uop_imm_sel_0; // @[core.scala:50:7] wire [4:0] io_ifu_brupdate_b2_uop_pimm_0; // @[core.scala:50:7] wire [19:0] io_ifu_brupdate_b2_uop_imm_packed_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_op1_sel_0; // @[core.scala:50:7] wire [2:0] io_ifu_brupdate_b2_uop_op2_sel_0; // @[core.scala:50:7] wire [5:0] io_ifu_brupdate_b2_uop_rob_idx_0; // @[core.scala:50:7] wire [3:0] io_ifu_brupdate_b2_uop_ldq_idx_0; // @[core.scala:50:7] wire [3:0] io_ifu_brupdate_b2_uop_stq_idx_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_rxq_idx_0; // @[core.scala:50:7] wire [6:0] io_ifu_brupdate_b2_uop_pdst_0; // @[core.scala:50:7] wire [6:0] io_ifu_brupdate_b2_uop_prs1_0; // @[core.scala:50:7] wire [6:0] io_ifu_brupdate_b2_uop_prs2_0; // @[core.scala:50:7] wire [6:0] io_ifu_brupdate_b2_uop_prs3_0; // @[core.scala:50:7] wire [4:0] io_ifu_brupdate_b2_uop_ppred_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_prs1_busy_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_prs2_busy_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_prs3_busy_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_ppred_busy_0; // @[core.scala:50:7] wire [6:0] io_ifu_brupdate_b2_uop_stale_pdst_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_exception_0; // @[core.scala:50:7] wire [63:0] io_ifu_brupdate_b2_uop_exc_cause_0; // @[core.scala:50:7] wire [4:0] io_ifu_brupdate_b2_uop_mem_cmd_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_mem_size_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_mem_signed_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_uses_ldq_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_uses_stq_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_is_unique_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_flush_on_commit_0; // @[core.scala:50:7] wire [2:0] io_ifu_brupdate_b2_uop_csr_cmd_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_ldst_is_rs1_0; // @[core.scala:50:7] wire [5:0] io_ifu_brupdate_b2_uop_ldst_0; // @[core.scala:50:7] wire [5:0] io_ifu_brupdate_b2_uop_lrs1_0; // @[core.scala:50:7] wire [5:0] io_ifu_brupdate_b2_uop_lrs2_0; // @[core.scala:50:7] wire [5:0] io_ifu_brupdate_b2_uop_lrs3_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_dst_rtype_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_lrs1_rtype_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_lrs2_rtype_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_frs3_en_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fcn_dw_0; // @[core.scala:50:7] wire [4:0] io_ifu_brupdate_b2_uop_fcn_op_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_fp_val_0; // @[core.scala:50:7] wire [2:0] io_ifu_brupdate_b2_uop_fp_rm_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_uop_fp_typ_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_xcpt_pf_if_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_xcpt_ae_if_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_xcpt_ma_if_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_bp_debug_if_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_uop_bp_xcpt_if_0; // @[core.scala:50:7] wire [2:0] io_ifu_brupdate_b2_uop_debug_fsrc_0; // @[core.scala:50:7] wire [2:0] io_ifu_brupdate_b2_uop_debug_tsrc_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_mispredict_0; // @[core.scala:50:7] wire io_ifu_brupdate_b2_taken_0; // @[core.scala:50:7] wire [2:0] io_ifu_brupdate_b2_cfi_type_0; // @[core.scala:50:7] wire [1:0] io_ifu_brupdate_b2_pc_sel_0; // @[core.scala:50:7] wire [39:0] io_ifu_brupdate_b2_jalr_target_0; // @[core.scala:50:7] wire [20:0] io_ifu_brupdate_b2_target_offset_0; // @[core.scala:50:7] wire [63:0] io_ifu_redirect_ghist_old_history_0; // @[core.scala:50:7] wire io_ifu_redirect_ghist_current_saw_branch_not_taken_0; // @[core.scala:50:7] wire io_ifu_redirect_ghist_new_saw_branch_not_taken_0; // @[core.scala:50:7] wire io_ifu_redirect_ghist_new_saw_branch_taken_0; // @[core.scala:50:7] wire [4:0] io_ifu_redirect_ghist_ras_idx_0; // @[core.scala:50:7] wire io_ifu_commit_valid_0; // @[core.scala:50:7] wire [31:0] io_ifu_commit_bits_0; // @[core.scala:50:7] wire io_ifu_redirect_flush_0; // @[core.scala:50:7] wire io_ifu_redirect_val_0; // @[core.scala:50:7] wire [39:0] io_ifu_redirect_pc_0; // @[core.scala:50:7] wire [4:0] io_ifu_redirect_ftq_idx_0; // @[core.scala:50:7] wire io_ifu_flush_icache_0; // @[core.scala:50:7] wire io_ifu_enable_bpd_0; // @[core.scala:50:7] wire [3:0] io_ptw_ptbr_mode_0; // @[core.scala:50:7] wire [43:0] io_ptw_ptbr_ppn_0; // @[core.scala:50:7] wire io_ptw_status_debug_0; // @[core.scala:50:7] wire io_ptw_status_cease_0; // @[core.scala:50:7] wire io_ptw_status_wfi_0; // @[core.scala:50:7] wire [1:0] io_ptw_status_dprv_0; // @[core.scala:50:7] wire io_ptw_status_dv_0; // @[core.scala:50:7] wire [1:0] io_ptw_status_prv_0; // @[core.scala:50:7] wire io_ptw_status_v_0; // @[core.scala:50:7] wire io_ptw_status_sd_0; // @[core.scala:50:7] wire io_ptw_status_mpv_0; // @[core.scala:50:7] wire io_ptw_status_gva_0; // @[core.scala:50:7] wire io_ptw_status_tsr_0; // @[core.scala:50:7] wire io_ptw_status_tw_0; // @[core.scala:50:7] wire io_ptw_status_tvm_0; // @[core.scala:50:7] wire io_ptw_status_mxr_0; // @[core.scala:50:7] wire io_ptw_status_sum_0; // @[core.scala:50:7] wire io_ptw_status_mprv_0; // @[core.scala:50:7] wire [1:0] io_ptw_status_fs_0; // @[core.scala:50:7] wire [1:0] io_ptw_status_mpp_0; // @[core.scala:50:7] wire io_ptw_status_spp_0; // @[core.scala:50:7] wire io_ptw_status_mpie_0; // @[core.scala:50:7] wire io_ptw_status_spie_0; // @[core.scala:50:7] wire io_ptw_status_mie_0; // @[core.scala:50:7] wire io_ptw_status_sie_0; // @[core.scala:50:7] wire io_ptw_pmp_0_cfg_l_0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_0_cfg_a_0; // @[core.scala:50:7] wire io_ptw_pmp_0_cfg_x_0; // @[core.scala:50:7] wire io_ptw_pmp_0_cfg_w_0; // @[core.scala:50:7] wire io_ptw_pmp_0_cfg_r_0; // @[core.scala:50:7] wire [29:0] io_ptw_pmp_0_addr_0; // @[core.scala:50:7] wire [31:0] io_ptw_pmp_0_mask_0; // @[core.scala:50:7] wire io_ptw_pmp_1_cfg_l_0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_1_cfg_a_0; // @[core.scala:50:7] wire io_ptw_pmp_1_cfg_x_0; // @[core.scala:50:7] wire io_ptw_pmp_1_cfg_w_0; // @[core.scala:50:7] wire io_ptw_pmp_1_cfg_r_0; // @[core.scala:50:7] wire [29:0] io_ptw_pmp_1_addr_0; // @[core.scala:50:7] wire [31:0] io_ptw_pmp_1_mask_0; // @[core.scala:50:7] wire io_ptw_pmp_2_cfg_l_0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_2_cfg_a_0; // @[core.scala:50:7] wire io_ptw_pmp_2_cfg_x_0; // @[core.scala:50:7] wire io_ptw_pmp_2_cfg_w_0; // @[core.scala:50:7] wire io_ptw_pmp_2_cfg_r_0; // @[core.scala:50:7] wire [29:0] io_ptw_pmp_2_addr_0; // @[core.scala:50:7] wire [31:0] io_ptw_pmp_2_mask_0; // @[core.scala:50:7] wire io_ptw_pmp_3_cfg_l_0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_3_cfg_a_0; // @[core.scala:50:7] wire io_ptw_pmp_3_cfg_x_0; // @[core.scala:50:7] wire io_ptw_pmp_3_cfg_w_0; // @[core.scala:50:7] wire io_ptw_pmp_3_cfg_r_0; // @[core.scala:50:7] wire [29:0] io_ptw_pmp_3_addr_0; // @[core.scala:50:7] wire [31:0] io_ptw_pmp_3_mask_0; // @[core.scala:50:7] wire io_ptw_pmp_4_cfg_l_0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_4_cfg_a_0; // @[core.scala:50:7] wire io_ptw_pmp_4_cfg_x_0; // @[core.scala:50:7] wire io_ptw_pmp_4_cfg_w_0; // @[core.scala:50:7] wire io_ptw_pmp_4_cfg_r_0; // @[core.scala:50:7] wire [29:0] io_ptw_pmp_4_addr_0; // @[core.scala:50:7] wire [31:0] io_ptw_pmp_4_mask_0; // @[core.scala:50:7] wire io_ptw_pmp_5_cfg_l_0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_5_cfg_a_0; // @[core.scala:50:7] wire io_ptw_pmp_5_cfg_x_0; // @[core.scala:50:7] wire io_ptw_pmp_5_cfg_w_0; // @[core.scala:50:7] wire io_ptw_pmp_5_cfg_r_0; // @[core.scala:50:7] wire [29:0] io_ptw_pmp_5_addr_0; // @[core.scala:50:7] wire [31:0] io_ptw_pmp_5_mask_0; // @[core.scala:50:7] wire io_ptw_pmp_6_cfg_l_0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_6_cfg_a_0; // @[core.scala:50:7] wire io_ptw_pmp_6_cfg_x_0; // @[core.scala:50:7] wire io_ptw_pmp_6_cfg_w_0; // @[core.scala:50:7] wire io_ptw_pmp_6_cfg_r_0; // @[core.scala:50:7] wire [29:0] io_ptw_pmp_6_addr_0; // @[core.scala:50:7] wire [31:0] io_ptw_pmp_6_mask_0; // @[core.scala:50:7] wire io_ptw_pmp_7_cfg_l_0; // @[core.scala:50:7] wire [1:0] io_ptw_pmp_7_cfg_a_0; // @[core.scala:50:7] wire io_ptw_pmp_7_cfg_x_0; // @[core.scala:50:7] wire io_ptw_pmp_7_cfg_w_0; // @[core.scala:50:7] wire io_ptw_pmp_7_cfg_r_0; // @[core.scala:50:7] wire [29:0] io_ptw_pmp_7_addr_0; // @[core.scala:50:7] wire [31:0] io_ptw_pmp_7_mask_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_iq_type_0_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_iq_type_1_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_iq_type_2_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_iq_type_3_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fu_code_0_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fu_code_1_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fu_code_2_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fu_code_3_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fu_code_4_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fu_code_5_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fu_code_6_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fu_code_7_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fu_code_8_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fu_code_9_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ldst_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_wen_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ren1_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ren2_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_ren3_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_swap12_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_swap23_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_fp_ctrl_typeTagIn_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_fp_ctrl_typeTagOut_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_fromint_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_toint_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_fastpipe_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_fma_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_div_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_sqrt_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_wflags_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_ctrl_vec_0; // @[core.scala:50:7] wire [31:0] io_lsu_agen_0_bits_uop_inst_0; // @[core.scala:50:7] wire [31:0] io_lsu_agen_0_bits_uop_debug_inst_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_is_rvc_0; // @[core.scala:50:7] wire [39:0] io_lsu_agen_0_bits_uop_debug_pc_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_iw_issued_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_iw_issued_partial_agen_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_iw_issued_partial_dgen_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_iw_p1_speculative_child_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_iw_p2_speculative_child_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_iw_p1_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_iw_p2_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_iw_p3_bypass_hint_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_dis_col_sel_0; // @[core.scala:50:7] wire [11:0] io_lsu_agen_0_bits_uop_br_mask_0; // @[core.scala:50:7] wire [3:0] io_lsu_agen_0_bits_uop_br_tag_0; // @[core.scala:50:7] wire [3:0] io_lsu_agen_0_bits_uop_br_type_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_is_sfb_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_is_fence_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_is_fencei_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_is_sfence_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_is_amo_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_is_eret_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_is_sys_pc2epc_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_is_rocc_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_is_mov_0; // @[core.scala:50:7] wire [4:0] io_lsu_agen_0_bits_uop_ftq_idx_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_edge_inst_0; // @[core.scala:50:7] wire [5:0] io_lsu_agen_0_bits_uop_pc_lob_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_taken_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_imm_rename_0; // @[core.scala:50:7] wire [2:0] io_lsu_agen_0_bits_uop_imm_sel_0; // @[core.scala:50:7] wire [4:0] io_lsu_agen_0_bits_uop_pimm_0; // @[core.scala:50:7] wire [19:0] io_lsu_agen_0_bits_uop_imm_packed_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_op1_sel_0; // @[core.scala:50:7] wire [2:0] io_lsu_agen_0_bits_uop_op2_sel_0; // @[core.scala:50:7] wire [5:0] io_lsu_agen_0_bits_uop_rob_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_agen_0_bits_uop_ldq_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_agen_0_bits_uop_stq_idx_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_rxq_idx_0; // @[core.scala:50:7] wire [6:0] io_lsu_agen_0_bits_uop_pdst_0; // @[core.scala:50:7] wire [6:0] io_lsu_agen_0_bits_uop_prs1_0; // @[core.scala:50:7] wire [6:0] io_lsu_agen_0_bits_uop_prs2_0; // @[core.scala:50:7] wire [6:0] io_lsu_agen_0_bits_uop_prs3_0; // @[core.scala:50:7] wire [4:0] io_lsu_agen_0_bits_uop_ppred_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_prs1_busy_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_prs2_busy_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_prs3_busy_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_ppred_busy_0; // @[core.scala:50:7] wire [6:0] io_lsu_agen_0_bits_uop_stale_pdst_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_exception_0; // @[core.scala:50:7] wire [63:0] io_lsu_agen_0_bits_uop_exc_cause_0; // @[core.scala:50:7] wire [4:0] io_lsu_agen_0_bits_uop_mem_cmd_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_mem_size_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_mem_signed_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_uses_ldq_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_uses_stq_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_is_unique_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_flush_on_commit_0; // @[core.scala:50:7] wire [2:0] io_lsu_agen_0_bits_uop_csr_cmd_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_ldst_is_rs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_agen_0_bits_uop_ldst_0; // @[core.scala:50:7] wire [5:0] io_lsu_agen_0_bits_uop_lrs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_agen_0_bits_uop_lrs2_0; // @[core.scala:50:7] wire [5:0] io_lsu_agen_0_bits_uop_lrs3_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_dst_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_lrs1_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_lrs2_rtype_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_frs3_en_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fcn_dw_0; // @[core.scala:50:7] wire [4:0] io_lsu_agen_0_bits_uop_fcn_op_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_fp_val_0; // @[core.scala:50:7] wire [2:0] io_lsu_agen_0_bits_uop_fp_rm_0; // @[core.scala:50:7] wire [1:0] io_lsu_agen_0_bits_uop_fp_typ_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_xcpt_pf_if_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_xcpt_ae_if_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_xcpt_ma_if_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_bp_debug_if_0; // @[core.scala:50:7] wire io_lsu_agen_0_bits_uop_bp_xcpt_if_0; // @[core.scala:50:7] wire [2:0] io_lsu_agen_0_bits_uop_debug_fsrc_0; // @[core.scala:50:7] wire [2:0] io_lsu_agen_0_bits_uop_debug_tsrc_0; // @[core.scala:50:7] wire [63:0] io_lsu_agen_0_bits_data_0; // @[core.scala:50:7] wire io_lsu_agen_0_valid_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_iq_type_0_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_iq_type_1_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_iq_type_2_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_iq_type_3_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fu_code_0_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fu_code_1_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fu_code_2_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fu_code_3_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fu_code_4_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fu_code_5_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fu_code_6_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fu_code_7_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fu_code_8_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fu_code_9_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ldst_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_wen_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren1_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren2_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_ren3_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_swap12_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_swap23_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagIn_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_fp_ctrl_typeTagOut_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_fromint_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_toint_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_fastpipe_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_fma_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_div_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_sqrt_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_wflags_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_ctrl_vec_0; // @[core.scala:50:7] wire [31:0] io_lsu_dgen_0_bits_uop_inst_0; // @[core.scala:50:7] wire [31:0] io_lsu_dgen_0_bits_uop_debug_inst_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_is_rvc_0; // @[core.scala:50:7] wire [39:0] io_lsu_dgen_0_bits_uop_debug_pc_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_iw_issued_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_iw_issued_partial_agen_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_iw_issued_partial_dgen_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_iw_p1_speculative_child_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_iw_p2_speculative_child_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_iw_p1_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_iw_p2_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_iw_p3_bypass_hint_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_dis_col_sel_0; // @[core.scala:50:7] wire [11:0] io_lsu_dgen_0_bits_uop_br_mask_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_0_bits_uop_br_tag_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_0_bits_uop_br_type_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_is_sfb_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_is_fence_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_is_fencei_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_is_sfence_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_is_amo_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_is_eret_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_is_sys_pc2epc_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_is_rocc_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_is_mov_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_0_bits_uop_ftq_idx_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_edge_inst_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_0_bits_uop_pc_lob_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_taken_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_imm_rename_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_0_bits_uop_imm_sel_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_0_bits_uop_pimm_0; // @[core.scala:50:7] wire [19:0] io_lsu_dgen_0_bits_uop_imm_packed_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_op1_sel_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_0_bits_uop_op2_sel_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_0_bits_uop_rob_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_0_bits_uop_ldq_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_0_bits_uop_stq_idx_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_rxq_idx_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_0_bits_uop_pdst_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_0_bits_uop_prs1_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_0_bits_uop_prs2_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_0_bits_uop_prs3_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_0_bits_uop_ppred_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_prs1_busy_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_prs2_busy_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_prs3_busy_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_ppred_busy_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_0_bits_uop_stale_pdst_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_exception_0; // @[core.scala:50:7] wire [63:0] io_lsu_dgen_0_bits_uop_exc_cause_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_0_bits_uop_mem_cmd_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_mem_size_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_mem_signed_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_uses_ldq_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_uses_stq_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_is_unique_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_flush_on_commit_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_0_bits_uop_csr_cmd_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_ldst_is_rs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_0_bits_uop_ldst_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_0_bits_uop_lrs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_0_bits_uop_lrs2_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_0_bits_uop_lrs3_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_dst_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_lrs1_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_lrs2_rtype_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_frs3_en_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fcn_dw_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_0_bits_uop_fcn_op_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_fp_val_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_0_bits_uop_fp_rm_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_0_bits_uop_fp_typ_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_xcpt_pf_if_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_xcpt_ae_if_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_xcpt_ma_if_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_bp_debug_if_0; // @[core.scala:50:7] wire io_lsu_dgen_0_bits_uop_bp_xcpt_if_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_0_bits_uop_debug_fsrc_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_0_bits_uop_debug_tsrc_0; // @[core.scala:50:7] wire [63:0] io_lsu_dgen_0_bits_data_0; // @[core.scala:50:7] wire io_lsu_dgen_0_valid_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_iq_type_0_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_iq_type_1_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_iq_type_2_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_iq_type_3_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fu_code_0_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fu_code_1_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fu_code_2_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fu_code_3_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fu_code_4_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fu_code_5_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fu_code_6_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fu_code_7_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fu_code_8_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fu_code_9_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ldst_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_wen_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren1_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren2_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_ren3_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_swap12_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_swap23_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagIn_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_fp_ctrl_typeTagOut_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_fromint_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_toint_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_fastpipe_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_fma_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_div_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_sqrt_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_wflags_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_ctrl_vec_0; // @[core.scala:50:7] wire [31:0] io_lsu_dgen_1_bits_uop_inst_0; // @[core.scala:50:7] wire [31:0] io_lsu_dgen_1_bits_uop_debug_inst_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_is_rvc_0; // @[core.scala:50:7] wire [39:0] io_lsu_dgen_1_bits_uop_debug_pc_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_iw_issued_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_iw_issued_partial_agen_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_iw_issued_partial_dgen_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_iw_p1_speculative_child_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_iw_p2_speculative_child_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_iw_p1_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_iw_p2_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_iw_p3_bypass_hint_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_dis_col_sel_0; // @[core.scala:50:7] wire [11:0] io_lsu_dgen_1_bits_uop_br_mask_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_1_bits_uop_br_tag_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_1_bits_uop_br_type_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_is_sfb_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_is_fence_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_is_fencei_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_is_sfence_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_is_amo_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_is_eret_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_is_sys_pc2epc_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_is_rocc_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_is_mov_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_1_bits_uop_ftq_idx_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_edge_inst_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_1_bits_uop_pc_lob_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_taken_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_imm_rename_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_1_bits_uop_imm_sel_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_1_bits_uop_pimm_0; // @[core.scala:50:7] wire [19:0] io_lsu_dgen_1_bits_uop_imm_packed_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_op1_sel_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_1_bits_uop_op2_sel_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_1_bits_uop_rob_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_1_bits_uop_ldq_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_1_bits_uop_stq_idx_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_rxq_idx_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_1_bits_uop_pdst_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_1_bits_uop_prs1_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_1_bits_uop_prs2_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_1_bits_uop_prs3_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_1_bits_uop_ppred_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_prs1_busy_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_prs2_busy_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_prs3_busy_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_ppred_busy_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_1_bits_uop_stale_pdst_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_exception_0; // @[core.scala:50:7] wire [63:0] io_lsu_dgen_1_bits_uop_exc_cause_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_1_bits_uop_mem_cmd_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_mem_size_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_mem_signed_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_uses_ldq_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_uses_stq_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_is_unique_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_flush_on_commit_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_1_bits_uop_csr_cmd_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_ldst_is_rs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_1_bits_uop_ldst_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_1_bits_uop_lrs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_1_bits_uop_lrs2_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_1_bits_uop_lrs3_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_dst_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_lrs1_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_lrs2_rtype_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_frs3_en_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fcn_dw_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_1_bits_uop_fcn_op_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_fp_val_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_1_bits_uop_fp_rm_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_1_bits_uop_fp_typ_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_xcpt_pf_if_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_xcpt_ae_if_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_xcpt_ma_if_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_bp_debug_if_0; // @[core.scala:50:7] wire io_lsu_dgen_1_bits_uop_bp_xcpt_if_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_1_bits_uop_debug_fsrc_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_1_bits_uop_debug_tsrc_0; // @[core.scala:50:7] wire [63:0] io_lsu_dgen_1_bits_data_0; // @[core.scala:50:7] wire io_lsu_dgen_1_valid_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_iq_type_0_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_iq_type_1_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_iq_type_2_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_iq_type_3_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fu_code_0_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fu_code_1_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fu_code_2_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fu_code_3_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fu_code_4_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fu_code_5_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fu_code_6_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fu_code_7_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fu_code_8_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fu_code_9_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ldst_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_wen_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren1_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren2_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_ren3_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_swap12_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_swap23_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagIn_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_fp_ctrl_typeTagOut_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_fromint_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_toint_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_fastpipe_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_fma_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_div_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_sqrt_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_wflags_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_ctrl_vec_0; // @[core.scala:50:7] wire [31:0] io_lsu_dgen_2_bits_uop_inst_0; // @[core.scala:50:7] wire [31:0] io_lsu_dgen_2_bits_uop_debug_inst_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_is_rvc_0; // @[core.scala:50:7] wire [39:0] io_lsu_dgen_2_bits_uop_debug_pc_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_iw_issued_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_iw_issued_partial_agen_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_iw_issued_partial_dgen_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_iw_p1_speculative_child_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_iw_p2_speculative_child_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_iw_p1_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_iw_p2_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_iw_p3_bypass_hint_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_dis_col_sel_0; // @[core.scala:50:7] wire [11:0] io_lsu_dgen_2_bits_uop_br_mask_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_2_bits_uop_br_tag_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_2_bits_uop_br_type_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_is_sfb_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_is_fence_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_is_fencei_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_is_sfence_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_is_amo_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_is_eret_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_is_sys_pc2epc_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_is_rocc_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_is_mov_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_2_bits_uop_ftq_idx_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_edge_inst_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_2_bits_uop_pc_lob_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_taken_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_imm_rename_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_2_bits_uop_imm_sel_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_2_bits_uop_pimm_0; // @[core.scala:50:7] wire [19:0] io_lsu_dgen_2_bits_uop_imm_packed_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_op1_sel_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_2_bits_uop_op2_sel_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_2_bits_uop_rob_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_2_bits_uop_ldq_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dgen_2_bits_uop_stq_idx_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_rxq_idx_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_2_bits_uop_pdst_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_2_bits_uop_prs1_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_2_bits_uop_prs2_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_2_bits_uop_prs3_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_2_bits_uop_ppred_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_prs1_busy_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_prs2_busy_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_prs3_busy_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_ppred_busy_0; // @[core.scala:50:7] wire [6:0] io_lsu_dgen_2_bits_uop_stale_pdst_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_exception_0; // @[core.scala:50:7] wire [63:0] io_lsu_dgen_2_bits_uop_exc_cause_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_2_bits_uop_mem_cmd_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_mem_size_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_mem_signed_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_uses_ldq_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_uses_stq_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_is_unique_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_flush_on_commit_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_2_bits_uop_csr_cmd_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_ldst_is_rs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_2_bits_uop_ldst_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_2_bits_uop_lrs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_2_bits_uop_lrs2_0; // @[core.scala:50:7] wire [5:0] io_lsu_dgen_2_bits_uop_lrs3_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_dst_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_lrs1_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_lrs2_rtype_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_frs3_en_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fcn_dw_0; // @[core.scala:50:7] wire [4:0] io_lsu_dgen_2_bits_uop_fcn_op_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_fp_val_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_2_bits_uop_fp_rm_0; // @[core.scala:50:7] wire [1:0] io_lsu_dgen_2_bits_uop_fp_typ_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_xcpt_pf_if_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_xcpt_ae_if_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_xcpt_ma_if_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_bp_debug_if_0; // @[core.scala:50:7] wire io_lsu_dgen_2_bits_uop_bp_xcpt_if_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_2_bits_uop_debug_fsrc_0; // @[core.scala:50:7] wire [2:0] io_lsu_dgen_2_bits_uop_debug_tsrc_0; // @[core.scala:50:7] wire [63:0] io_lsu_dgen_2_bits_data_0; // @[core.scala:50:7] wire io_lsu_dgen_2_valid_0; // @[core.scala:50:7] wire io_lsu_sfence_bits_rs1_0; // @[core.scala:50:7] wire io_lsu_sfence_bits_rs2_0; // @[core.scala:50:7] wire [38:0] io_lsu_sfence_bits_addr_0; // @[core.scala:50:7] wire io_lsu_sfence_bits_asid_0; // @[core.scala:50:7] wire io_lsu_sfence_bits_hv_0; // @[core.scala:50:7] wire io_lsu_sfence_bits_hg_0; // @[core.scala:50:7] wire io_lsu_sfence_valid_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_iq_type_0_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_iq_type_1_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_iq_type_2_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_iq_type_3_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fu_code_0_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fu_code_1_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fu_code_2_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fu_code_3_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fu_code_4_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fu_code_5_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fu_code_6_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fu_code_7_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fu_code_8_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fu_code_9_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ldst_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_wen_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ren1_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ren2_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_ren3_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_swap12_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_swap23_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_fromint_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_toint_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_fma_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_div_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_sqrt_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_wflags_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_ctrl_vec_0; // @[core.scala:50:7] wire [31:0] io_lsu_dis_uops_0_bits_inst_0; // @[core.scala:50:7] wire [31:0] io_lsu_dis_uops_0_bits_debug_inst_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_is_rvc_0; // @[core.scala:50:7] wire [39:0] io_lsu_dis_uops_0_bits_debug_pc_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_iw_issued_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_iw_issued_partial_agen_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_iw_issued_partial_dgen_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_iw_p1_speculative_child_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_iw_p2_speculative_child_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_iw_p1_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_iw_p2_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_iw_p3_bypass_hint_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_dis_col_sel_0; // @[core.scala:50:7] wire [11:0] io_lsu_dis_uops_0_bits_br_mask_0; // @[core.scala:50:7] wire [3:0] io_lsu_dis_uops_0_bits_br_tag_0; // @[core.scala:50:7] wire [3:0] io_lsu_dis_uops_0_bits_br_type_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_is_sfb_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_is_fence_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_is_fencei_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_is_sfence_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_is_amo_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_is_eret_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_is_sys_pc2epc_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_is_rocc_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_is_mov_0; // @[core.scala:50:7] wire [4:0] io_lsu_dis_uops_0_bits_ftq_idx_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_edge_inst_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_0_bits_pc_lob_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_taken_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_imm_rename_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_0_bits_imm_sel_0; // @[core.scala:50:7] wire [4:0] io_lsu_dis_uops_0_bits_pimm_0; // @[core.scala:50:7] wire [19:0] io_lsu_dis_uops_0_bits_imm_packed_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_op1_sel_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_0_bits_op2_sel_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_0_bits_rob_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dis_uops_0_bits_ldq_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dis_uops_0_bits_stq_idx_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_rxq_idx_0; // @[core.scala:50:7] wire [6:0] io_lsu_dis_uops_0_bits_pdst_0; // @[core.scala:50:7] wire [6:0] io_lsu_dis_uops_0_bits_prs1_0; // @[core.scala:50:7] wire [6:0] io_lsu_dis_uops_0_bits_prs2_0; // @[core.scala:50:7] wire [6:0] io_lsu_dis_uops_0_bits_prs3_0; // @[core.scala:50:7] wire [4:0] io_lsu_dis_uops_0_bits_ppred_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_prs1_busy_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_prs2_busy_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_prs3_busy_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_ppred_busy_0; // @[core.scala:50:7] wire [6:0] io_lsu_dis_uops_0_bits_stale_pdst_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_exception_0; // @[core.scala:50:7] wire [63:0] io_lsu_dis_uops_0_bits_exc_cause_0; // @[core.scala:50:7] wire [4:0] io_lsu_dis_uops_0_bits_mem_cmd_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_mem_size_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_mem_signed_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_uses_ldq_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_uses_stq_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_is_unique_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_flush_on_commit_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_0_bits_csr_cmd_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_ldst_is_rs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_0_bits_ldst_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs2_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_0_bits_lrs3_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_dst_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs1_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_lrs2_rtype_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_frs3_en_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fcn_dw_0; // @[core.scala:50:7] wire [4:0] io_lsu_dis_uops_0_bits_fcn_op_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_fp_val_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_0_bits_fp_rm_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_0_bits_fp_typ_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_xcpt_pf_if_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_xcpt_ae_if_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_xcpt_ma_if_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_bp_debug_if_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_bits_bp_xcpt_if_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_0_bits_debug_fsrc_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_0_bits_debug_tsrc_0; // @[core.scala:50:7] wire io_lsu_dis_uops_0_valid_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_iq_type_0_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_iq_type_1_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_iq_type_2_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_iq_type_3_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fu_code_0_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fu_code_1_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fu_code_2_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fu_code_3_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fu_code_4_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fu_code_5_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fu_code_6_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fu_code_7_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fu_code_8_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fu_code_9_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_ldst_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_wen_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_ren1_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_ren2_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_ren3_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_swap12_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_swap23_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_fp_ctrl_typeTagIn_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_fp_ctrl_typeTagOut_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_fromint_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_toint_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_fastpipe_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_fma_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_div_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_sqrt_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_wflags_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_ctrl_vec_0; // @[core.scala:50:7] wire [31:0] io_lsu_dis_uops_1_bits_inst_0; // @[core.scala:50:7] wire [31:0] io_lsu_dis_uops_1_bits_debug_inst_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_is_rvc_0; // @[core.scala:50:7] wire [39:0] io_lsu_dis_uops_1_bits_debug_pc_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_iw_issued_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_iw_issued_partial_agen_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_iw_issued_partial_dgen_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_iw_p1_speculative_child_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_iw_p2_speculative_child_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_iw_p1_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_iw_p2_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_iw_p3_bypass_hint_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_dis_col_sel_0; // @[core.scala:50:7] wire [11:0] io_lsu_dis_uops_1_bits_br_mask_0; // @[core.scala:50:7] wire [3:0] io_lsu_dis_uops_1_bits_br_tag_0; // @[core.scala:50:7] wire [3:0] io_lsu_dis_uops_1_bits_br_type_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_is_sfb_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_is_fence_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_is_fencei_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_is_sfence_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_is_amo_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_is_eret_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_is_sys_pc2epc_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_is_rocc_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_is_mov_0; // @[core.scala:50:7] wire [4:0] io_lsu_dis_uops_1_bits_ftq_idx_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_edge_inst_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_1_bits_pc_lob_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_taken_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_imm_rename_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_1_bits_imm_sel_0; // @[core.scala:50:7] wire [4:0] io_lsu_dis_uops_1_bits_pimm_0; // @[core.scala:50:7] wire [19:0] io_lsu_dis_uops_1_bits_imm_packed_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_op1_sel_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_1_bits_op2_sel_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_1_bits_rob_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dis_uops_1_bits_ldq_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_dis_uops_1_bits_stq_idx_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_rxq_idx_0; // @[core.scala:50:7] wire [6:0] io_lsu_dis_uops_1_bits_pdst_0; // @[core.scala:50:7] wire [6:0] io_lsu_dis_uops_1_bits_prs1_0; // @[core.scala:50:7] wire [6:0] io_lsu_dis_uops_1_bits_prs2_0; // @[core.scala:50:7] wire [6:0] io_lsu_dis_uops_1_bits_prs3_0; // @[core.scala:50:7] wire [4:0] io_lsu_dis_uops_1_bits_ppred_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_prs1_busy_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_prs2_busy_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_prs3_busy_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_ppred_busy_0; // @[core.scala:50:7] wire [6:0] io_lsu_dis_uops_1_bits_stale_pdst_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_exception_0; // @[core.scala:50:7] wire [63:0] io_lsu_dis_uops_1_bits_exc_cause_0; // @[core.scala:50:7] wire [4:0] io_lsu_dis_uops_1_bits_mem_cmd_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_mem_size_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_mem_signed_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_uses_ldq_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_uses_stq_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_is_unique_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_flush_on_commit_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_1_bits_csr_cmd_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_ldst_is_rs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_1_bits_ldst_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_1_bits_lrs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_1_bits_lrs2_0; // @[core.scala:50:7] wire [5:0] io_lsu_dis_uops_1_bits_lrs3_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_dst_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_lrs1_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_lrs2_rtype_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_frs3_en_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fcn_dw_0; // @[core.scala:50:7] wire [4:0] io_lsu_dis_uops_1_bits_fcn_op_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_fp_val_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_1_bits_fp_rm_0; // @[core.scala:50:7] wire [1:0] io_lsu_dis_uops_1_bits_fp_typ_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_xcpt_pf_if_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_xcpt_ae_if_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_xcpt_ma_if_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_bp_debug_if_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_bits_bp_xcpt_if_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_1_bits_debug_fsrc_0; // @[core.scala:50:7] wire [2:0] io_lsu_dis_uops_1_bits_debug_tsrc_0; // @[core.scala:50:7] wire io_lsu_dis_uops_1_valid_0; // @[core.scala:50:7] wire io_lsu_commit_valids_0_0; // @[core.scala:50:7] wire io_lsu_commit_valids_1_0; // @[core.scala:50:7] wire io_lsu_commit_arch_valids_0_0; // @[core.scala:50:7] wire io_lsu_commit_arch_valids_1_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_iq_type_0_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_iq_type_1_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_iq_type_2_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_iq_type_3_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fu_code_0_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fu_code_1_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fu_code_2_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fu_code_3_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fu_code_4_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fu_code_5_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fu_code_6_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fu_code_7_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fu_code_8_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fu_code_9_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_ldst_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_wen_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_ren1_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_ren2_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_ren3_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_swap12_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_swap23_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagIn_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_fp_ctrl_typeTagOut_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_fromint_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_toint_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_fastpipe_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_fma_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_div_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_sqrt_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_wflags_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_ctrl_vec_0; // @[core.scala:50:7] wire [31:0] io_lsu_commit_uops_0_inst_0; // @[core.scala:50:7] wire [31:0] io_lsu_commit_uops_0_debug_inst_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_is_rvc_0; // @[core.scala:50:7] wire [39:0] io_lsu_commit_uops_0_debug_pc_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_iw_issued_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_iw_issued_partial_agen_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_iw_issued_partial_dgen_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_iw_p1_speculative_child_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_iw_p2_speculative_child_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_iw_p1_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_iw_p2_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_iw_p3_bypass_hint_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_dis_col_sel_0; // @[core.scala:50:7] wire [11:0] io_lsu_commit_uops_0_br_mask_0; // @[core.scala:50:7] wire [3:0] io_lsu_commit_uops_0_br_tag_0; // @[core.scala:50:7] wire [3:0] io_lsu_commit_uops_0_br_type_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_is_sfb_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_is_fence_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_is_fencei_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_is_sfence_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_is_amo_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_is_eret_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_is_sys_pc2epc_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_is_rocc_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_is_mov_0; // @[core.scala:50:7] wire [4:0] io_lsu_commit_uops_0_ftq_idx_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_edge_inst_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_0_pc_lob_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_taken_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_imm_rename_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_0_imm_sel_0; // @[core.scala:50:7] wire [4:0] io_lsu_commit_uops_0_pimm_0; // @[core.scala:50:7] wire [19:0] io_lsu_commit_uops_0_imm_packed_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_op1_sel_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_0_op2_sel_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_0_rob_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_commit_uops_0_ldq_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_commit_uops_0_stq_idx_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_rxq_idx_0; // @[core.scala:50:7] wire [6:0] io_lsu_commit_uops_0_pdst_0; // @[core.scala:50:7] wire [6:0] io_lsu_commit_uops_0_prs1_0; // @[core.scala:50:7] wire [6:0] io_lsu_commit_uops_0_prs2_0; // @[core.scala:50:7] wire [6:0] io_lsu_commit_uops_0_prs3_0; // @[core.scala:50:7] wire [4:0] io_lsu_commit_uops_0_ppred_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_prs1_busy_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_prs2_busy_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_prs3_busy_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_ppred_busy_0; // @[core.scala:50:7] wire [6:0] io_lsu_commit_uops_0_stale_pdst_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_exception_0; // @[core.scala:50:7] wire [63:0] io_lsu_commit_uops_0_exc_cause_0; // @[core.scala:50:7] wire [4:0] io_lsu_commit_uops_0_mem_cmd_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_mem_size_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_mem_signed_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_uses_ldq_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_uses_stq_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_is_unique_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_flush_on_commit_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_0_csr_cmd_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_ldst_is_rs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_0_ldst_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_0_lrs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_0_lrs2_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_0_lrs3_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_dst_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_lrs1_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_lrs2_rtype_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_frs3_en_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fcn_dw_0; // @[core.scala:50:7] wire [4:0] io_lsu_commit_uops_0_fcn_op_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_fp_val_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_0_fp_rm_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_0_fp_typ_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_xcpt_pf_if_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_xcpt_ae_if_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_xcpt_ma_if_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_bp_debug_if_0; // @[core.scala:50:7] wire io_lsu_commit_uops_0_bp_xcpt_if_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_0_debug_fsrc_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_0_debug_tsrc_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_iq_type_0_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_iq_type_1_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_iq_type_2_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_iq_type_3_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fu_code_0_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fu_code_1_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fu_code_2_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fu_code_3_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fu_code_4_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fu_code_5_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fu_code_6_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fu_code_7_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fu_code_8_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fu_code_9_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_ldst_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_wen_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_ren1_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_ren2_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_ren3_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_swap12_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_swap23_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_fp_ctrl_typeTagIn_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_fp_ctrl_typeTagOut_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_fromint_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_toint_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_fastpipe_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_fma_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_div_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_sqrt_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_wflags_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_ctrl_vec_0; // @[core.scala:50:7] wire [31:0] io_lsu_commit_uops_1_inst_0; // @[core.scala:50:7] wire [31:0] io_lsu_commit_uops_1_debug_inst_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_is_rvc_0; // @[core.scala:50:7] wire [39:0] io_lsu_commit_uops_1_debug_pc_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_iw_issued_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_iw_issued_partial_agen_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_iw_issued_partial_dgen_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_iw_p1_speculative_child_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_iw_p2_speculative_child_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_iw_p1_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_iw_p2_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_iw_p3_bypass_hint_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_dis_col_sel_0; // @[core.scala:50:7] wire [11:0] io_lsu_commit_uops_1_br_mask_0; // @[core.scala:50:7] wire [3:0] io_lsu_commit_uops_1_br_tag_0; // @[core.scala:50:7] wire [3:0] io_lsu_commit_uops_1_br_type_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_is_sfb_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_is_fence_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_is_fencei_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_is_sfence_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_is_amo_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_is_eret_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_is_sys_pc2epc_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_is_rocc_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_is_mov_0; // @[core.scala:50:7] wire [4:0] io_lsu_commit_uops_1_ftq_idx_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_edge_inst_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_1_pc_lob_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_taken_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_imm_rename_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_1_imm_sel_0; // @[core.scala:50:7] wire [4:0] io_lsu_commit_uops_1_pimm_0; // @[core.scala:50:7] wire [19:0] io_lsu_commit_uops_1_imm_packed_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_op1_sel_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_1_op2_sel_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_1_rob_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_commit_uops_1_ldq_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_commit_uops_1_stq_idx_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_rxq_idx_0; // @[core.scala:50:7] wire [6:0] io_lsu_commit_uops_1_pdst_0; // @[core.scala:50:7] wire [6:0] io_lsu_commit_uops_1_prs1_0; // @[core.scala:50:7] wire [6:0] io_lsu_commit_uops_1_prs2_0; // @[core.scala:50:7] wire [6:0] io_lsu_commit_uops_1_prs3_0; // @[core.scala:50:7] wire [4:0] io_lsu_commit_uops_1_ppred_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_prs1_busy_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_prs2_busy_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_prs3_busy_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_ppred_busy_0; // @[core.scala:50:7] wire [6:0] io_lsu_commit_uops_1_stale_pdst_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_exception_0; // @[core.scala:50:7] wire [63:0] io_lsu_commit_uops_1_exc_cause_0; // @[core.scala:50:7] wire [4:0] io_lsu_commit_uops_1_mem_cmd_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_mem_size_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_mem_signed_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_uses_ldq_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_uses_stq_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_is_unique_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_flush_on_commit_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_1_csr_cmd_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_ldst_is_rs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_1_ldst_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_1_lrs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_1_lrs2_0; // @[core.scala:50:7] wire [5:0] io_lsu_commit_uops_1_lrs3_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_dst_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_lrs1_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_lrs2_rtype_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_frs3_en_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fcn_dw_0; // @[core.scala:50:7] wire [4:0] io_lsu_commit_uops_1_fcn_op_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_fp_val_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_1_fp_rm_0; // @[core.scala:50:7] wire [1:0] io_lsu_commit_uops_1_fp_typ_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_xcpt_pf_if_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_xcpt_ae_if_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_xcpt_ma_if_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_bp_debug_if_0; // @[core.scala:50:7] wire io_lsu_commit_uops_1_bp_xcpt_if_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_1_debug_fsrc_0; // @[core.scala:50:7] wire [2:0] io_lsu_commit_uops_1_debug_tsrc_0; // @[core.scala:50:7] wire io_lsu_commit_fflags_valid_0; // @[core.scala:50:7] wire [4:0] io_lsu_commit_fflags_bits_0; // @[core.scala:50:7] wire [63:0] io_lsu_commit_debug_wdata_0_0; // @[core.scala:50:7] wire [63:0] io_lsu_commit_debug_wdata_1_0; // @[core.scala:50:7] wire [11:0] io_lsu_brupdate_b1_resolve_mask_0; // @[core.scala:50:7] wire [11:0] io_lsu_brupdate_b1_mispredict_mask_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_iq_type_0_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_iq_type_1_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_iq_type_2_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_iq_type_3_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fu_code_0_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fu_code_1_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fu_code_2_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fu_code_3_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fu_code_4_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fu_code_5_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fu_code_6_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fu_code_7_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fu_code_8_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fu_code_9_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ldst_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_wen_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren1_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren2_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_ren3_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_swap12_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_swap23_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fromint_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_toint_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_fma_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_div_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_sqrt_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_wflags_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_ctrl_vec_0; // @[core.scala:50:7] wire [31:0] io_lsu_brupdate_b2_uop_inst_0; // @[core.scala:50:7] wire [31:0] io_lsu_brupdate_b2_uop_debug_inst_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_is_rvc_0; // @[core.scala:50:7] wire [39:0] io_lsu_brupdate_b2_uop_debug_pc_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_iw_issued_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_iw_issued_partial_agen_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_iw_issued_partial_dgen_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_iw_p1_speculative_child_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_iw_p2_speculative_child_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_iw_p1_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_iw_p2_bypass_hint_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_iw_p3_bypass_hint_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_dis_col_sel_0; // @[core.scala:50:7] wire [11:0] io_lsu_brupdate_b2_uop_br_mask_0; // @[core.scala:50:7] wire [3:0] io_lsu_brupdate_b2_uop_br_tag_0; // @[core.scala:50:7] wire [3:0] io_lsu_brupdate_b2_uop_br_type_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_is_sfb_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_is_fence_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_is_fencei_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_is_sfence_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_is_amo_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_is_eret_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_is_sys_pc2epc_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_is_rocc_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_is_mov_0; // @[core.scala:50:7] wire [4:0] io_lsu_brupdate_b2_uop_ftq_idx_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_edge_inst_0; // @[core.scala:50:7] wire [5:0] io_lsu_brupdate_b2_uop_pc_lob_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_taken_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_imm_rename_0; // @[core.scala:50:7] wire [2:0] io_lsu_brupdate_b2_uop_imm_sel_0; // @[core.scala:50:7] wire [4:0] io_lsu_brupdate_b2_uop_pimm_0; // @[core.scala:50:7] wire [19:0] io_lsu_brupdate_b2_uop_imm_packed_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_op1_sel_0; // @[core.scala:50:7] wire [2:0] io_lsu_brupdate_b2_uop_op2_sel_0; // @[core.scala:50:7] wire [5:0] io_lsu_brupdate_b2_uop_rob_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_brupdate_b2_uop_ldq_idx_0; // @[core.scala:50:7] wire [3:0] io_lsu_brupdate_b2_uop_stq_idx_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_rxq_idx_0; // @[core.scala:50:7] wire [6:0] io_lsu_brupdate_b2_uop_pdst_0; // @[core.scala:50:7] wire [6:0] io_lsu_brupdate_b2_uop_prs1_0; // @[core.scala:50:7] wire [6:0] io_lsu_brupdate_b2_uop_prs2_0; // @[core.scala:50:7] wire [6:0] io_lsu_brupdate_b2_uop_prs3_0; // @[core.scala:50:7] wire [4:0] io_lsu_brupdate_b2_uop_ppred_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_prs1_busy_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_prs2_busy_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_prs3_busy_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_ppred_busy_0; // @[core.scala:50:7] wire [6:0] io_lsu_brupdate_b2_uop_stale_pdst_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_exception_0; // @[core.scala:50:7] wire [63:0] io_lsu_brupdate_b2_uop_exc_cause_0; // @[core.scala:50:7] wire [4:0] io_lsu_brupdate_b2_uop_mem_cmd_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_mem_size_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_mem_signed_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_uses_ldq_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_uses_stq_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_is_unique_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_flush_on_commit_0; // @[core.scala:50:7] wire [2:0] io_lsu_brupdate_b2_uop_csr_cmd_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_ldst_is_rs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_brupdate_b2_uop_ldst_0; // @[core.scala:50:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs1_0; // @[core.scala:50:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs2_0; // @[core.scala:50:7] wire [5:0] io_lsu_brupdate_b2_uop_lrs3_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_dst_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs1_rtype_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_lrs2_rtype_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_frs3_en_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fcn_dw_0; // @[core.scala:50:7] wire [4:0] io_lsu_brupdate_b2_uop_fcn_op_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_fp_val_0; // @[core.scala:50:7] wire [2:0] io_lsu_brupdate_b2_uop_fp_rm_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_uop_fp_typ_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_xcpt_pf_if_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_xcpt_ae_if_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_xcpt_ma_if_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_bp_debug_if_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_uop_bp_xcpt_if_0; // @[core.scala:50:7] wire [2:0] io_lsu_brupdate_b2_uop_debug_fsrc_0; // @[core.scala:50:7] wire [2:0] io_lsu_brupdate_b2_uop_debug_tsrc_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_mispredict_0; // @[core.scala:50:7] wire io_lsu_brupdate_b2_taken_0; // @[core.scala:50:7] wire [2:0] io_lsu_brupdate_b2_cfi_type_0; // @[core.scala:50:7] wire [1:0] io_lsu_brupdate_b2_pc_sel_0; // @[core.scala:50:7] wire [39:0] io_lsu_brupdate_b2_jalr_target_0; // @[core.scala:50:7] wire [20:0] io_lsu_brupdate_b2_target_offset_0; // @[core.scala:50:7] wire io_lsu_status_debug_0; // @[core.scala:50:7] wire io_lsu_status_cease_0; // @[core.scala:50:7] wire io_lsu_status_wfi_0; // @[core.scala:50:7] wire [1:0] io_lsu_status_dprv_0; // @[core.scala:50:7] wire io_lsu_status_dv_0; // @[core.scala:50:7] wire [1:0] io_lsu_status_prv_0; // @[core.scala:50:7] wire io_lsu_status_v_0; // @[core.scala:50:7] wire io_lsu_status_sd_0; // @[core.scala:50:7] wire io_lsu_status_mpv_0; // @[core.scala:50:7] wire io_lsu_status_gva_0; // @[core.scala:50:7] wire io_lsu_status_tsr_0; // @[core.scala:50:7] wire io_lsu_status_tw_0; // @[core.scala:50:7] wire io_lsu_status_tvm_0; // @[core.scala:50:7] wire io_lsu_status_mxr_0; // @[core.scala:50:7] wire io_lsu_status_sum_0; // @[core.scala:50:7] wire io_lsu_status_mprv_0; // @[core.scala:50:7] wire [1:0] io_lsu_status_fs_0; // @[core.scala:50:7] wire [1:0] io_lsu_status_mpp_0; // @[core.scala:50:7] wire io_lsu_status_spp_0; // @[core.scala:50:7] wire io_lsu_status_mpie_0; // @[core.scala:50:7] wire io_lsu_status_spie_0; // @[core.scala:50:7] wire io_lsu_status_mie_0; // @[core.scala:50:7] wire io_lsu_status_sie_0; // @[core.scala:50:7] wire io_lsu_commit_load_at_rob_head_0; // @[core.scala:50:7] wire io_lsu_fence_dmem_0; // @[core.scala:50:7] wire [5:0] io_lsu_rob_pnr_idx_0; // @[core.scala:50:7] wire [5:0] io_lsu_rob_head_idx_0; // @[core.scala:50:7] wire io_lsu_exception_0; // @[core.scala:50:7] wire [63:0] io_lsu_tsc_reg_0; // @[core.scala:50:7] wire io_trace_custom_rob_empty_0; // @[core.scala:50:7] wire [63:0] io_trace_time_0; // @[core.scala:50:7] wire [2:0] io_fcsr_rm; // @[core.scala:50:7] wire _int_wakeups_1_valid_T_1; // @[core.scala:937:52] wire int_wakeups_1_bits_uop_iq_type_0; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_iq_type_1; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_iq_type_2; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_iq_type_3; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fu_code_0; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fu_code_1; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fu_code_2; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fu_code_3; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fu_code_4; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fu_code_5; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fu_code_6; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fu_code_7; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fu_code_8; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fu_code_9; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_ldst; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_wen; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_ren1; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_ren2; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_ren3; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_swap12; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_swap23; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_fromint; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_toint; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_fma; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_div; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_sqrt; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_wflags; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_ctrl_vec; // @[core.scala:164:26] wire [31:0] int_wakeups_1_bits_uop_inst; // @[core.scala:164:26] wire [31:0] int_wakeups_1_bits_uop_debug_inst; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_is_rvc; // @[core.scala:164:26] wire [39:0] int_wakeups_1_bits_uop_debug_pc; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_iw_issued; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_iw_issued_partial_agen; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_iw_issued_partial_dgen; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_iw_p1_speculative_child; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_iw_p2_speculative_child; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_iw_p1_bypass_hint; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_iw_p2_bypass_hint; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_iw_p3_bypass_hint; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_dis_col_sel; // @[core.scala:164:26] wire [11:0] int_wakeups_1_bits_uop_br_mask; // @[core.scala:164:26] wire [3:0] int_wakeups_1_bits_uop_br_tag; // @[core.scala:164:26] wire [3:0] int_wakeups_1_bits_uop_br_type; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_is_sfb; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_is_fence; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_is_fencei; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_is_sfence; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_is_amo; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_is_eret; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_is_rocc; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_is_mov; // @[core.scala:164:26] wire [4:0] int_wakeups_1_bits_uop_ftq_idx; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_edge_inst; // @[core.scala:164:26] wire [5:0] int_wakeups_1_bits_uop_pc_lob; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_taken; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_imm_rename; // @[core.scala:164:26] wire [2:0] int_wakeups_1_bits_uop_imm_sel; // @[core.scala:164:26] wire [4:0] int_wakeups_1_bits_uop_pimm; // @[core.scala:164:26] wire [19:0] int_wakeups_1_bits_uop_imm_packed; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_op1_sel; // @[core.scala:164:26] wire [2:0] int_wakeups_1_bits_uop_op2_sel; // @[core.scala:164:26] wire [5:0] int_wakeups_1_bits_uop_rob_idx; // @[core.scala:164:26] wire [3:0] int_wakeups_1_bits_uop_ldq_idx; // @[core.scala:164:26] wire [3:0] int_wakeups_1_bits_uop_stq_idx; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_rxq_idx; // @[core.scala:164:26] wire [6:0] int_wakeups_1_bits_uop_pdst; // @[core.scala:164:26] wire [6:0] int_wakeups_1_bits_uop_prs1; // @[core.scala:164:26] wire [6:0] int_wakeups_1_bits_uop_prs2; // @[core.scala:164:26] wire [6:0] int_wakeups_1_bits_uop_prs3; // @[core.scala:164:26] wire [4:0] int_wakeups_1_bits_uop_ppred; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_prs1_busy; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_prs2_busy; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_prs3_busy; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_ppred_busy; // @[core.scala:164:26] wire [6:0] int_wakeups_1_bits_uop_stale_pdst; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_exception; // @[core.scala:164:26] wire [63:0] int_wakeups_1_bits_uop_exc_cause; // @[core.scala:164:26] wire [4:0] int_wakeups_1_bits_uop_mem_cmd; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_mem_size; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_mem_signed; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_uses_ldq; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_uses_stq; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_is_unique; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:164:26] wire [2:0] int_wakeups_1_bits_uop_csr_cmd; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:164:26] wire [5:0] int_wakeups_1_bits_uop_ldst; // @[core.scala:164:26] wire [5:0] int_wakeups_1_bits_uop_lrs1; // @[core.scala:164:26] wire [5:0] int_wakeups_1_bits_uop_lrs2; // @[core.scala:164:26] wire [5:0] int_wakeups_1_bits_uop_lrs3; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_dst_rtype; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_frs3_en; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fcn_dw; // @[core.scala:164:26] wire [4:0] int_wakeups_1_bits_uop_fcn_op; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_fp_val; // @[core.scala:164:26] wire [2:0] int_wakeups_1_bits_uop_fp_rm; // @[core.scala:164:26] wire [1:0] int_wakeups_1_bits_uop_fp_typ; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:164:26] wire int_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:164:26] wire [2:0] int_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:164:26] wire [2:0] int_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:164:26] wire int_wakeups_1_valid; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_iq_type_0; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_iq_type_1; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_iq_type_2; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_iq_type_3; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fu_code_0; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fu_code_1; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fu_code_2; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fu_code_3; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fu_code_4; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fu_code_5; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fu_code_6; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fu_code_7; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fu_code_8; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fu_code_9; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_ldst; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_wen; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_ren1; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_ren2; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_ren3; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_swap12; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_swap23; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_fromint; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_toint; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_fastpipe; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_fma; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_div; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_sqrt; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_wflags; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_ctrl_vec; // @[core.scala:164:26] wire [31:0] int_wakeups_2_bits_uop_inst; // @[core.scala:164:26] wire [31:0] int_wakeups_2_bits_uop_debug_inst; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_is_rvc; // @[core.scala:164:26] wire [39:0] int_wakeups_2_bits_uop_debug_pc; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_iw_issued; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_iw_p1_speculative_child; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_iw_p2_speculative_child; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_iw_p1_bypass_hint; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_iw_p2_bypass_hint; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_iw_p3_bypass_hint; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_dis_col_sel; // @[core.scala:164:26] wire [11:0] int_wakeups_2_bits_uop_br_mask; // @[core.scala:164:26] wire [3:0] int_wakeups_2_bits_uop_br_tag; // @[core.scala:164:26] wire [3:0] int_wakeups_2_bits_uop_br_type; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_is_sfb; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_is_fence; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_is_fencei; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_is_sfence; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_is_amo; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_is_eret; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_is_sys_pc2epc; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_is_rocc; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_is_mov; // @[core.scala:164:26] wire [4:0] int_wakeups_2_bits_uop_ftq_idx; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_edge_inst; // @[core.scala:164:26] wire [5:0] int_wakeups_2_bits_uop_pc_lob; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_taken; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_imm_rename; // @[core.scala:164:26] wire [2:0] int_wakeups_2_bits_uop_imm_sel; // @[core.scala:164:26] wire [4:0] int_wakeups_2_bits_uop_pimm; // @[core.scala:164:26] wire [19:0] int_wakeups_2_bits_uop_imm_packed; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_op1_sel; // @[core.scala:164:26] wire [2:0] int_wakeups_2_bits_uop_op2_sel; // @[core.scala:164:26] wire [5:0] int_wakeups_2_bits_uop_rob_idx; // @[core.scala:164:26] wire [3:0] int_wakeups_2_bits_uop_ldq_idx; // @[core.scala:164:26] wire [3:0] int_wakeups_2_bits_uop_stq_idx; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_rxq_idx; // @[core.scala:164:26] wire [6:0] int_wakeups_2_bits_uop_pdst; // @[core.scala:164:26] wire [6:0] int_wakeups_2_bits_uop_prs1; // @[core.scala:164:26] wire [6:0] int_wakeups_2_bits_uop_prs2; // @[core.scala:164:26] wire [6:0] int_wakeups_2_bits_uop_prs3; // @[core.scala:164:26] wire [4:0] int_wakeups_2_bits_uop_ppred; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_prs1_busy; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_prs2_busy; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_prs3_busy; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_ppred_busy; // @[core.scala:164:26] wire [6:0] int_wakeups_2_bits_uop_stale_pdst; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_exception; // @[core.scala:164:26] wire [63:0] int_wakeups_2_bits_uop_exc_cause; // @[core.scala:164:26] wire [4:0] int_wakeups_2_bits_uop_mem_cmd; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_mem_size; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_mem_signed; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_uses_ldq; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_uses_stq; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_is_unique; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_flush_on_commit; // @[core.scala:164:26] wire [2:0] int_wakeups_2_bits_uop_csr_cmd; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_ldst_is_rs1; // @[core.scala:164:26] wire [5:0] int_wakeups_2_bits_uop_ldst; // @[core.scala:164:26] wire [5:0] int_wakeups_2_bits_uop_lrs1; // @[core.scala:164:26] wire [5:0] int_wakeups_2_bits_uop_lrs2; // @[core.scala:164:26] wire [5:0] int_wakeups_2_bits_uop_lrs3; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_dst_rtype; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_lrs1_rtype; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_lrs2_rtype; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_frs3_en; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fcn_dw; // @[core.scala:164:26] wire [4:0] int_wakeups_2_bits_uop_fcn_op; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_fp_val; // @[core.scala:164:26] wire [2:0] int_wakeups_2_bits_uop_fp_rm; // @[core.scala:164:26] wire [1:0] int_wakeups_2_bits_uop_fp_typ; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_xcpt_pf_if; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_xcpt_ae_if; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_xcpt_ma_if; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_bp_debug_if; // @[core.scala:164:26] wire int_wakeups_2_bits_uop_bp_xcpt_if; // @[core.scala:164:26] wire [2:0] int_wakeups_2_bits_uop_debug_fsrc; // @[core.scala:164:26] wire [2:0] int_wakeups_2_bits_uop_debug_tsrc; // @[core.scala:164:26] wire int_wakeups_2_valid; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_iq_type_0; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_iq_type_1; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_iq_type_2; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_iq_type_3; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fu_code_0; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fu_code_1; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fu_code_2; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fu_code_3; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fu_code_4; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fu_code_5; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fu_code_6; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fu_code_7; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fu_code_8; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fu_code_9; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_ldst; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_wen; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_ren1; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_ren2; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_ren3; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_swap12; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_swap23; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_fromint; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_toint; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_fastpipe; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_fma; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_div; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_sqrt; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_wflags; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_ctrl_vec; // @[core.scala:164:26] wire [31:0] int_wakeups_3_bits_uop_inst; // @[core.scala:164:26] wire [31:0] int_wakeups_3_bits_uop_debug_inst; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_is_rvc; // @[core.scala:164:26] wire [39:0] int_wakeups_3_bits_uop_debug_pc; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_iw_issued; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_iw_p1_speculative_child; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_iw_p2_speculative_child; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_iw_p1_bypass_hint; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_iw_p2_bypass_hint; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_iw_p3_bypass_hint; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_dis_col_sel; // @[core.scala:164:26] wire [11:0] int_wakeups_3_bits_uop_br_mask; // @[core.scala:164:26] wire [3:0] int_wakeups_3_bits_uop_br_tag; // @[core.scala:164:26] wire [3:0] int_wakeups_3_bits_uop_br_type; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_is_sfb; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_is_fence; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_is_fencei; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_is_sfence; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_is_amo; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_is_eret; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_is_sys_pc2epc; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_is_rocc; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_is_mov; // @[core.scala:164:26] wire [4:0] int_wakeups_3_bits_uop_ftq_idx; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_edge_inst; // @[core.scala:164:26] wire [5:0] int_wakeups_3_bits_uop_pc_lob; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_taken; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_imm_rename; // @[core.scala:164:26] wire [2:0] int_wakeups_3_bits_uop_imm_sel; // @[core.scala:164:26] wire [4:0] int_wakeups_3_bits_uop_pimm; // @[core.scala:164:26] wire [19:0] int_wakeups_3_bits_uop_imm_packed; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_op1_sel; // @[core.scala:164:26] wire [2:0] int_wakeups_3_bits_uop_op2_sel; // @[core.scala:164:26] wire [5:0] int_wakeups_3_bits_uop_rob_idx; // @[core.scala:164:26] wire [3:0] int_wakeups_3_bits_uop_ldq_idx; // @[core.scala:164:26] wire [3:0] int_wakeups_3_bits_uop_stq_idx; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_rxq_idx; // @[core.scala:164:26] wire [6:0] int_wakeups_3_bits_uop_pdst; // @[core.scala:164:26] wire [6:0] int_wakeups_3_bits_uop_prs1; // @[core.scala:164:26] wire [6:0] int_wakeups_3_bits_uop_prs2; // @[core.scala:164:26] wire [6:0] int_wakeups_3_bits_uop_prs3; // @[core.scala:164:26] wire [4:0] int_wakeups_3_bits_uop_ppred; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_prs1_busy; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_prs2_busy; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_prs3_busy; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_ppred_busy; // @[core.scala:164:26] wire [6:0] int_wakeups_3_bits_uop_stale_pdst; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_exception; // @[core.scala:164:26] wire [63:0] int_wakeups_3_bits_uop_exc_cause; // @[core.scala:164:26] wire [4:0] int_wakeups_3_bits_uop_mem_cmd; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_mem_size; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_mem_signed; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_uses_ldq; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_uses_stq; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_is_unique; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_flush_on_commit; // @[core.scala:164:26] wire [2:0] int_wakeups_3_bits_uop_csr_cmd; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_ldst_is_rs1; // @[core.scala:164:26] wire [5:0] int_wakeups_3_bits_uop_ldst; // @[core.scala:164:26] wire [5:0] int_wakeups_3_bits_uop_lrs1; // @[core.scala:164:26] wire [5:0] int_wakeups_3_bits_uop_lrs2; // @[core.scala:164:26] wire [5:0] int_wakeups_3_bits_uop_lrs3; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_dst_rtype; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_lrs1_rtype; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_lrs2_rtype; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_frs3_en; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fcn_dw; // @[core.scala:164:26] wire [4:0] int_wakeups_3_bits_uop_fcn_op; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_fp_val; // @[core.scala:164:26] wire [2:0] int_wakeups_3_bits_uop_fp_rm; // @[core.scala:164:26] wire [1:0] int_wakeups_3_bits_uop_fp_typ; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_xcpt_pf_if; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_xcpt_ae_if; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_xcpt_ma_if; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_bp_debug_if; // @[core.scala:164:26] wire int_wakeups_3_bits_uop_bp_xcpt_if; // @[core.scala:164:26] wire [2:0] int_wakeups_3_bits_uop_debug_fsrc; // @[core.scala:164:26] wire [2:0] int_wakeups_3_bits_uop_debug_tsrc; // @[core.scala:164:26] wire int_wakeups_3_valid; // @[core.scala:164:26] wire pred_wakeups_0_bits_uop_iq_type_0; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_iq_type_1; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_iq_type_2; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_iq_type_3; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fu_code_0; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fu_code_1; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fu_code_2; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fu_code_3; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fu_code_4; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fu_code_5; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fu_code_6; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fu_code_7; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fu_code_8; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fu_code_9; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_ldst; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_wen; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_ren1; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_ren2; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_ren3; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_swap12; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_swap23; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_fromint; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_toint; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_fastpipe; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_fma; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_div; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_sqrt; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_wflags; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_ctrl_vec; // @[core.scala:165:26] wire [31:0] pred_wakeups_0_bits_uop_inst; // @[core.scala:165:26] wire [31:0] pred_wakeups_0_bits_uop_debug_inst; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_is_rvc; // @[core.scala:165:26] wire [39:0] pred_wakeups_0_bits_uop_debug_pc; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_iw_issued; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_iw_issued_partial_agen; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_iw_issued_partial_dgen; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_iw_p1_speculative_child; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_iw_p2_speculative_child; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_iw_p1_bypass_hint; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_iw_p2_bypass_hint; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_iw_p3_bypass_hint; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_dis_col_sel; // @[core.scala:165:26] wire [11:0] pred_wakeups_0_bits_uop_br_mask; // @[core.scala:165:26] wire [3:0] pred_wakeups_0_bits_uop_br_tag; // @[core.scala:165:26] wire [3:0] pred_wakeups_0_bits_uop_br_type; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_is_sfb; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_is_fence; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_is_fencei; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_is_sfence; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_is_amo; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_is_eret; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_is_sys_pc2epc; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_is_rocc; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_is_mov; // @[core.scala:165:26] wire [4:0] pred_wakeups_0_bits_uop_ftq_idx; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_edge_inst; // @[core.scala:165:26] wire [5:0] pred_wakeups_0_bits_uop_pc_lob; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_taken; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_imm_rename; // @[core.scala:165:26] wire [2:0] pred_wakeups_0_bits_uop_imm_sel; // @[core.scala:165:26] wire [4:0] pred_wakeups_0_bits_uop_pimm; // @[core.scala:165:26] wire [19:0] pred_wakeups_0_bits_uop_imm_packed; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_op1_sel; // @[core.scala:165:26] wire [2:0] pred_wakeups_0_bits_uop_op2_sel; // @[core.scala:165:26] wire [5:0] pred_wakeups_0_bits_uop_rob_idx; // @[core.scala:165:26] wire [3:0] pred_wakeups_0_bits_uop_ldq_idx; // @[core.scala:165:26] wire [3:0] pred_wakeups_0_bits_uop_stq_idx; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_rxq_idx; // @[core.scala:165:26] wire [6:0] pred_wakeups_0_bits_uop_pdst; // @[core.scala:165:26] wire [6:0] pred_wakeups_0_bits_uop_prs1; // @[core.scala:165:26] wire [6:0] pred_wakeups_0_bits_uop_prs2; // @[core.scala:165:26] wire [6:0] pred_wakeups_0_bits_uop_prs3; // @[core.scala:165:26] wire [4:0] pred_wakeups_0_bits_uop_ppred; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_prs1_busy; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_prs2_busy; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_prs3_busy; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_ppred_busy; // @[core.scala:165:26] wire [6:0] pred_wakeups_0_bits_uop_stale_pdst; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_exception; // @[core.scala:165:26] wire [63:0] pred_wakeups_0_bits_uop_exc_cause; // @[core.scala:165:26] wire [4:0] pred_wakeups_0_bits_uop_mem_cmd; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_mem_size; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_mem_signed; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_uses_ldq; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_uses_stq; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_is_unique; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_flush_on_commit; // @[core.scala:165:26] wire [2:0] pred_wakeups_0_bits_uop_csr_cmd; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_ldst_is_rs1; // @[core.scala:165:26] wire [5:0] pred_wakeups_0_bits_uop_ldst; // @[core.scala:165:26] wire [5:0] pred_wakeups_0_bits_uop_lrs1; // @[core.scala:165:26] wire [5:0] pred_wakeups_0_bits_uop_lrs2; // @[core.scala:165:26] wire [5:0] pred_wakeups_0_bits_uop_lrs3; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_dst_rtype; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_lrs1_rtype; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_lrs2_rtype; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_frs3_en; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fcn_dw; // @[core.scala:165:26] wire [4:0] pred_wakeups_0_bits_uop_fcn_op; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_fp_val; // @[core.scala:165:26] wire [2:0] pred_wakeups_0_bits_uop_fp_rm; // @[core.scala:165:26] wire [1:0] pred_wakeups_0_bits_uop_fp_typ; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_xcpt_pf_if; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_xcpt_ae_if; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_xcpt_ma_if; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_bp_debug_if; // @[core.scala:165:26] wire pred_wakeups_0_bits_uop_bp_xcpt_if; // @[core.scala:165:26] wire [2:0] pred_wakeups_0_bits_uop_debug_fsrc; // @[core.scala:165:26] wire [2:0] pred_wakeups_0_bits_uop_debug_tsrc; // @[core.scala:165:26] wire pred_wakeups_0_valid; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_iq_type_0; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_iq_type_1; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_iq_type_2; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_iq_type_3; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fu_code_0; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fu_code_1; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fu_code_2; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fu_code_3; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fu_code_4; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fu_code_5; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fu_code_6; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fu_code_7; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fu_code_8; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fu_code_9; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_ldst; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_wen; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_ren1; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_ren2; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_ren3; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_swap12; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_swap23; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_fromint; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_toint; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_fastpipe; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_fma; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_div; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_sqrt; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_wflags; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_ctrl_vec; // @[core.scala:165:26] wire [31:0] pred_wakeups_1_bits_uop_inst; // @[core.scala:165:26] wire [31:0] pred_wakeups_1_bits_uop_debug_inst; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_is_rvc; // @[core.scala:165:26] wire [39:0] pred_wakeups_1_bits_uop_debug_pc; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_iw_issued; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_iw_issued_partial_agen; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_iw_issued_partial_dgen; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_iw_p1_speculative_child; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_iw_p2_speculative_child; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_iw_p1_bypass_hint; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_iw_p2_bypass_hint; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_iw_p3_bypass_hint; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_dis_col_sel; // @[core.scala:165:26] wire [11:0] pred_wakeups_1_bits_uop_br_mask; // @[core.scala:165:26] wire [3:0] pred_wakeups_1_bits_uop_br_tag; // @[core.scala:165:26] wire [3:0] pred_wakeups_1_bits_uop_br_type; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_is_sfb; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_is_fence; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_is_fencei; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_is_sfence; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_is_amo; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_is_eret; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_is_sys_pc2epc; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_is_rocc; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_is_mov; // @[core.scala:165:26] wire [4:0] pred_wakeups_1_bits_uop_ftq_idx; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_edge_inst; // @[core.scala:165:26] wire [5:0] pred_wakeups_1_bits_uop_pc_lob; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_taken; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_imm_rename; // @[core.scala:165:26] wire [2:0] pred_wakeups_1_bits_uop_imm_sel; // @[core.scala:165:26] wire [4:0] pred_wakeups_1_bits_uop_pimm; // @[core.scala:165:26] wire [19:0] pred_wakeups_1_bits_uop_imm_packed; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_op1_sel; // @[core.scala:165:26] wire [2:0] pred_wakeups_1_bits_uop_op2_sel; // @[core.scala:165:26] wire [5:0] pred_wakeups_1_bits_uop_rob_idx; // @[core.scala:165:26] wire [3:0] pred_wakeups_1_bits_uop_ldq_idx; // @[core.scala:165:26] wire [3:0] pred_wakeups_1_bits_uop_stq_idx; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_rxq_idx; // @[core.scala:165:26] wire [6:0] pred_wakeups_1_bits_uop_pdst; // @[core.scala:165:26] wire [6:0] pred_wakeups_1_bits_uop_prs1; // @[core.scala:165:26] wire [6:0] pred_wakeups_1_bits_uop_prs2; // @[core.scala:165:26] wire [6:0] pred_wakeups_1_bits_uop_prs3; // @[core.scala:165:26] wire [4:0] pred_wakeups_1_bits_uop_ppred; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_prs1_busy; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_prs2_busy; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_prs3_busy; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_ppred_busy; // @[core.scala:165:26] wire [6:0] pred_wakeups_1_bits_uop_stale_pdst; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_exception; // @[core.scala:165:26] wire [63:0] pred_wakeups_1_bits_uop_exc_cause; // @[core.scala:165:26] wire [4:0] pred_wakeups_1_bits_uop_mem_cmd; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_mem_size; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_mem_signed; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_uses_ldq; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_uses_stq; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_is_unique; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_flush_on_commit; // @[core.scala:165:26] wire [2:0] pred_wakeups_1_bits_uop_csr_cmd; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_ldst_is_rs1; // @[core.scala:165:26] wire [5:0] pred_wakeups_1_bits_uop_ldst; // @[core.scala:165:26] wire [5:0] pred_wakeups_1_bits_uop_lrs1; // @[core.scala:165:26] wire [5:0] pred_wakeups_1_bits_uop_lrs2; // @[core.scala:165:26] wire [5:0] pred_wakeups_1_bits_uop_lrs3; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_dst_rtype; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_lrs1_rtype; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_lrs2_rtype; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_frs3_en; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fcn_dw; // @[core.scala:165:26] wire [4:0] pred_wakeups_1_bits_uop_fcn_op; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_fp_val; // @[core.scala:165:26] wire [2:0] pred_wakeups_1_bits_uop_fp_rm; // @[core.scala:165:26] wire [1:0] pred_wakeups_1_bits_uop_fp_typ; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_xcpt_pf_if; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_xcpt_ae_if; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_xcpt_ma_if; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_bp_debug_if; // @[core.scala:165:26] wire pred_wakeups_1_bits_uop_bp_xcpt_if; // @[core.scala:165:26] wire [2:0] pred_wakeups_1_bits_uop_debug_fsrc; // @[core.scala:165:26] wire [2:0] pred_wakeups_1_bits_uop_debug_tsrc; // @[core.scala:165:26] wire pred_wakeups_1_valid; // @[core.scala:165:26] wire _pred_wakeup_valid_T; // @[core.scala:170:66] wire [6:0] _pred_wakeup_bits_uop_pdst_WIRE; // @[Mux.scala:30:73] wire [6:0] pred_wakeup_bits_uop_pdst; // @[core.scala:169:26] wire pred_wakeup_valid; // @[core.scala:169:26] assign _pred_wakeup_valid_T = pred_wakeups_0_valid | pred_wakeups_1_valid; // @[core.scala:165:26, :170:66] assign pred_wakeup_valid = _pred_wakeup_valid_T; // @[core.scala:169:26, :170:66] wire [6:0] _pred_wakeup_bits_uop_pdst_T = pred_wakeups_0_valid ? pred_wakeups_0_bits_uop_pdst : 7'h0; // @[Mux.scala:30:73] wire [6:0] _pred_wakeup_bits_uop_pdst_T_1 = pred_wakeups_1_valid ? pred_wakeups_1_bits_uop_pdst : 7'h0; // @[Mux.scala:30:73] wire [6:0] _pred_wakeup_bits_uop_pdst_T_2 = _pred_wakeup_bits_uop_pdst_T | _pred_wakeup_bits_uop_pdst_T_1; // @[Mux.scala:30:73] assign _pred_wakeup_bits_uop_pdst_WIRE = _pred_wakeup_bits_uop_pdst_T_2; // @[Mux.scala:30:73] assign pred_wakeup_bits_uop_pdst = _pred_wakeup_bits_uop_pdst_WIRE; // @[Mux.scala:30:73] wire _int_bypasses_1_valid_T_1; // @[core.scala:958:62] wire _int_bypasses_2_valid_T_1; // @[core.scala:958:62] wire int_bypasses_0_bits_uop_iq_type_0; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_iq_type_1; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_iq_type_2; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_iq_type_3; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fu_code_0; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fu_code_1; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fu_code_2; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fu_code_3; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fu_code_4; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fu_code_5; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fu_code_6; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fu_code_7; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fu_code_8; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fu_code_9; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_ldst; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_wen; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_ren1; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_ren2; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_ren3; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_swap12; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_swap23; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_fromint; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_toint; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_fastpipe; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_fma; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_div; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_sqrt; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_wflags; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_ctrl_vec; // @[core.scala:174:27] wire [31:0] int_bypasses_0_bits_uop_inst; // @[core.scala:174:27] wire [31:0] int_bypasses_0_bits_uop_debug_inst; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_is_rvc; // @[core.scala:174:27] wire [39:0] int_bypasses_0_bits_uop_debug_pc; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_iw_issued; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_iw_issued_partial_agen; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_iw_issued_partial_dgen; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_iw_p1_speculative_child; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_iw_p2_speculative_child; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_iw_p1_bypass_hint; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_iw_p2_bypass_hint; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_iw_p3_bypass_hint; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_dis_col_sel; // @[core.scala:174:27] wire [11:0] int_bypasses_0_bits_uop_br_mask; // @[core.scala:174:27] wire [3:0] int_bypasses_0_bits_uop_br_tag; // @[core.scala:174:27] wire [3:0] int_bypasses_0_bits_uop_br_type; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_is_sfb; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_is_fence; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_is_fencei; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_is_sfence; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_is_amo; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_is_eret; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_is_sys_pc2epc; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_is_rocc; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_is_mov; // @[core.scala:174:27] wire [4:0] int_bypasses_0_bits_uop_ftq_idx; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_edge_inst; // @[core.scala:174:27] wire [5:0] int_bypasses_0_bits_uop_pc_lob; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_taken; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_imm_rename; // @[core.scala:174:27] wire [2:0] int_bypasses_0_bits_uop_imm_sel; // @[core.scala:174:27] wire [4:0] int_bypasses_0_bits_uop_pimm; // @[core.scala:174:27] wire [19:0] int_bypasses_0_bits_uop_imm_packed; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_op1_sel; // @[core.scala:174:27] wire [2:0] int_bypasses_0_bits_uop_op2_sel; // @[core.scala:174:27] wire [5:0] int_bypasses_0_bits_uop_rob_idx; // @[core.scala:174:27] wire [3:0] int_bypasses_0_bits_uop_ldq_idx; // @[core.scala:174:27] wire [3:0] int_bypasses_0_bits_uop_stq_idx; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_rxq_idx; // @[core.scala:174:27] wire [6:0] int_bypasses_0_bits_uop_pdst; // @[core.scala:174:27] wire [6:0] int_bypasses_0_bits_uop_prs1; // @[core.scala:174:27] wire [6:0] int_bypasses_0_bits_uop_prs2; // @[core.scala:174:27] wire [6:0] int_bypasses_0_bits_uop_prs3; // @[core.scala:174:27] wire [4:0] int_bypasses_0_bits_uop_ppred; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_prs1_busy; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_prs2_busy; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_prs3_busy; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_ppred_busy; // @[core.scala:174:27] wire [6:0] int_bypasses_0_bits_uop_stale_pdst; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_exception; // @[core.scala:174:27] wire [63:0] int_bypasses_0_bits_uop_exc_cause; // @[core.scala:174:27] wire [4:0] int_bypasses_0_bits_uop_mem_cmd; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_mem_size; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_mem_signed; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_uses_ldq; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_uses_stq; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_is_unique; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_flush_on_commit; // @[core.scala:174:27] wire [2:0] int_bypasses_0_bits_uop_csr_cmd; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_ldst_is_rs1; // @[core.scala:174:27] wire [5:0] int_bypasses_0_bits_uop_ldst; // @[core.scala:174:27] wire [5:0] int_bypasses_0_bits_uop_lrs1; // @[core.scala:174:27] wire [5:0] int_bypasses_0_bits_uop_lrs2; // @[core.scala:174:27] wire [5:0] int_bypasses_0_bits_uop_lrs3; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_dst_rtype; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_lrs1_rtype; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_lrs2_rtype; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_frs3_en; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fcn_dw; // @[core.scala:174:27] wire [4:0] int_bypasses_0_bits_uop_fcn_op; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_fp_val; // @[core.scala:174:27] wire [2:0] int_bypasses_0_bits_uop_fp_rm; // @[core.scala:174:27] wire [1:0] int_bypasses_0_bits_uop_fp_typ; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_xcpt_pf_if; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_xcpt_ae_if; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_xcpt_ma_if; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_bp_debug_if; // @[core.scala:174:27] wire int_bypasses_0_bits_uop_bp_xcpt_if; // @[core.scala:174:27] wire [2:0] int_bypasses_0_bits_uop_debug_fsrc; // @[core.scala:174:27] wire [2:0] int_bypasses_0_bits_uop_debug_tsrc; // @[core.scala:174:27] wire int_bypasses_0_bits_fflags_valid; // @[core.scala:174:27] wire [4:0] int_bypasses_0_bits_fflags_bits; // @[core.scala:174:27] wire [63:0] int_bypasses_0_bits_data; // @[core.scala:174:27] wire int_bypasses_0_bits_predicated; // @[core.scala:174:27] wire int_bypasses_0_valid; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_iq_type_0; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_iq_type_1; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_iq_type_2; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_iq_type_3; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fu_code_0; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fu_code_1; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fu_code_2; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fu_code_3; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fu_code_4; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fu_code_5; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fu_code_6; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fu_code_7; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fu_code_8; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fu_code_9; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_ldst; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_wen; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_ren1; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_ren2; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_ren3; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_swap12; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_swap23; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_fromint; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_toint; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_fastpipe; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_fma; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_div; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_sqrt; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_wflags; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_ctrl_vec; // @[core.scala:174:27] wire [31:0] int_bypasses_1_bits_uop_inst; // @[core.scala:174:27] wire [31:0] int_bypasses_1_bits_uop_debug_inst; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_is_rvc; // @[core.scala:174:27] wire [39:0] int_bypasses_1_bits_uop_debug_pc; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_iw_issued; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_iw_issued_partial_agen; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_iw_issued_partial_dgen; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_iw_p1_speculative_child; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_iw_p2_speculative_child; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_iw_p1_bypass_hint; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_iw_p2_bypass_hint; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_iw_p3_bypass_hint; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_dis_col_sel; // @[core.scala:174:27] wire [11:0] int_bypasses_1_bits_uop_br_mask; // @[core.scala:174:27] wire [3:0] int_bypasses_1_bits_uop_br_tag; // @[core.scala:174:27] wire [3:0] int_bypasses_1_bits_uop_br_type; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_is_sfb; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_is_fence; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_is_fencei; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_is_sfence; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_is_amo; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_is_eret; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_is_sys_pc2epc; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_is_rocc; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_is_mov; // @[core.scala:174:27] wire [4:0] int_bypasses_1_bits_uop_ftq_idx; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_edge_inst; // @[core.scala:174:27] wire [5:0] int_bypasses_1_bits_uop_pc_lob; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_taken; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_imm_rename; // @[core.scala:174:27] wire [2:0] int_bypasses_1_bits_uop_imm_sel; // @[core.scala:174:27] wire [4:0] int_bypasses_1_bits_uop_pimm; // @[core.scala:174:27] wire [19:0] int_bypasses_1_bits_uop_imm_packed; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_op1_sel; // @[core.scala:174:27] wire [2:0] int_bypasses_1_bits_uop_op2_sel; // @[core.scala:174:27] wire [5:0] int_bypasses_1_bits_uop_rob_idx; // @[core.scala:174:27] wire [3:0] int_bypasses_1_bits_uop_ldq_idx; // @[core.scala:174:27] wire [3:0] int_bypasses_1_bits_uop_stq_idx; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_rxq_idx; // @[core.scala:174:27] wire [6:0] int_bypasses_1_bits_uop_pdst; // @[core.scala:174:27] wire [6:0] int_bypasses_1_bits_uop_prs1; // @[core.scala:174:27] wire [6:0] int_bypasses_1_bits_uop_prs2; // @[core.scala:174:27] wire [6:0] int_bypasses_1_bits_uop_prs3; // @[core.scala:174:27] wire [4:0] int_bypasses_1_bits_uop_ppred; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_prs1_busy; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_prs2_busy; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_prs3_busy; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_ppred_busy; // @[core.scala:174:27] wire [6:0] int_bypasses_1_bits_uop_stale_pdst; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_exception; // @[core.scala:174:27] wire [63:0] int_bypasses_1_bits_uop_exc_cause; // @[core.scala:174:27] wire [4:0] int_bypasses_1_bits_uop_mem_cmd; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_mem_size; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_mem_signed; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_uses_ldq; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_uses_stq; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_is_unique; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_flush_on_commit; // @[core.scala:174:27] wire [2:0] int_bypasses_1_bits_uop_csr_cmd; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_ldst_is_rs1; // @[core.scala:174:27] wire [5:0] int_bypasses_1_bits_uop_ldst; // @[core.scala:174:27] wire [5:0] int_bypasses_1_bits_uop_lrs1; // @[core.scala:174:27] wire [5:0] int_bypasses_1_bits_uop_lrs2; // @[core.scala:174:27] wire [5:0] int_bypasses_1_bits_uop_lrs3; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_dst_rtype; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_lrs1_rtype; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_lrs2_rtype; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_frs3_en; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fcn_dw; // @[core.scala:174:27] wire [4:0] int_bypasses_1_bits_uop_fcn_op; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_fp_val; // @[core.scala:174:27] wire [2:0] int_bypasses_1_bits_uop_fp_rm; // @[core.scala:174:27] wire [1:0] int_bypasses_1_bits_uop_fp_typ; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_xcpt_pf_if; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_xcpt_ae_if; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_xcpt_ma_if; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_bp_debug_if; // @[core.scala:174:27] wire int_bypasses_1_bits_uop_bp_xcpt_if; // @[core.scala:174:27] wire [2:0] int_bypasses_1_bits_uop_debug_fsrc; // @[core.scala:174:27] wire [2:0] int_bypasses_1_bits_uop_debug_tsrc; // @[core.scala:174:27] wire [63:0] int_bypasses_1_bits_data; // @[core.scala:174:27] wire int_bypasses_1_bits_predicated; // @[core.scala:174:27] wire int_bypasses_1_valid; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_iq_type_0; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_iq_type_1; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_iq_type_2; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_iq_type_3; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fu_code_0; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fu_code_1; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fu_code_2; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fu_code_3; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fu_code_4; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fu_code_5; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fu_code_6; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fu_code_7; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fu_code_8; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fu_code_9; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_ldst; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_wen; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_ren1; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_ren2; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_ren3; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_swap12; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_swap23; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_fromint; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_toint; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_fastpipe; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_fma; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_div; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_sqrt; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_wflags; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_ctrl_vec; // @[core.scala:174:27] wire [31:0] int_bypasses_2_bits_uop_inst; // @[core.scala:174:27] wire [31:0] int_bypasses_2_bits_uop_debug_inst; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_is_rvc; // @[core.scala:174:27] wire [39:0] int_bypasses_2_bits_uop_debug_pc; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_iw_issued; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_iw_issued_partial_agen; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_iw_issued_partial_dgen; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_iw_p1_speculative_child; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_iw_p2_speculative_child; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_iw_p1_bypass_hint; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_iw_p2_bypass_hint; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_iw_p3_bypass_hint; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_dis_col_sel; // @[core.scala:174:27] wire [11:0] int_bypasses_2_bits_uop_br_mask; // @[core.scala:174:27] wire [3:0] int_bypasses_2_bits_uop_br_tag; // @[core.scala:174:27] wire [3:0] int_bypasses_2_bits_uop_br_type; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_is_sfb; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_is_fence; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_is_fencei; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_is_sfence; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_is_amo; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_is_eret; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_is_sys_pc2epc; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_is_rocc; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_is_mov; // @[core.scala:174:27] wire [4:0] int_bypasses_2_bits_uop_ftq_idx; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_edge_inst; // @[core.scala:174:27] wire [5:0] int_bypasses_2_bits_uop_pc_lob; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_taken; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_imm_rename; // @[core.scala:174:27] wire [2:0] int_bypasses_2_bits_uop_imm_sel; // @[core.scala:174:27] wire [4:0] int_bypasses_2_bits_uop_pimm; // @[core.scala:174:27] wire [19:0] int_bypasses_2_bits_uop_imm_packed; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_op1_sel; // @[core.scala:174:27] wire [2:0] int_bypasses_2_bits_uop_op2_sel; // @[core.scala:174:27] wire [5:0] int_bypasses_2_bits_uop_rob_idx; // @[core.scala:174:27] wire [3:0] int_bypasses_2_bits_uop_ldq_idx; // @[core.scala:174:27] wire [3:0] int_bypasses_2_bits_uop_stq_idx; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_rxq_idx; // @[core.scala:174:27] wire [6:0] int_bypasses_2_bits_uop_pdst; // @[core.scala:174:27] wire [6:0] int_bypasses_2_bits_uop_prs1; // @[core.scala:174:27] wire [6:0] int_bypasses_2_bits_uop_prs2; // @[core.scala:174:27] wire [6:0] int_bypasses_2_bits_uop_prs3; // @[core.scala:174:27] wire [4:0] int_bypasses_2_bits_uop_ppred; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_prs1_busy; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_prs2_busy; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_prs3_busy; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_ppred_busy; // @[core.scala:174:27] wire [6:0] int_bypasses_2_bits_uop_stale_pdst; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_exception; // @[core.scala:174:27] wire [63:0] int_bypasses_2_bits_uop_exc_cause; // @[core.scala:174:27] wire [4:0] int_bypasses_2_bits_uop_mem_cmd; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_mem_size; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_mem_signed; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_uses_ldq; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_uses_stq; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_is_unique; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_flush_on_commit; // @[core.scala:174:27] wire [2:0] int_bypasses_2_bits_uop_csr_cmd; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_ldst_is_rs1; // @[core.scala:174:27] wire [5:0] int_bypasses_2_bits_uop_ldst; // @[core.scala:174:27] wire [5:0] int_bypasses_2_bits_uop_lrs1; // @[core.scala:174:27] wire [5:0] int_bypasses_2_bits_uop_lrs2; // @[core.scala:174:27] wire [5:0] int_bypasses_2_bits_uop_lrs3; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_dst_rtype; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_lrs1_rtype; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_lrs2_rtype; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_frs3_en; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fcn_dw; // @[core.scala:174:27] wire [4:0] int_bypasses_2_bits_uop_fcn_op; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_fp_val; // @[core.scala:174:27] wire [2:0] int_bypasses_2_bits_uop_fp_rm; // @[core.scala:174:27] wire [1:0] int_bypasses_2_bits_uop_fp_typ; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_xcpt_pf_if; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_xcpt_ae_if; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_xcpt_ma_if; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_bp_debug_if; // @[core.scala:174:27] wire int_bypasses_2_bits_uop_bp_xcpt_if; // @[core.scala:174:27] wire [2:0] int_bypasses_2_bits_uop_debug_fsrc; // @[core.scala:174:27] wire [2:0] int_bypasses_2_bits_uop_debug_tsrc; // @[core.scala:174:27] wire [63:0] int_bypasses_2_bits_data; // @[core.scala:174:27] wire int_bypasses_2_bits_predicated; // @[core.scala:174:27] wire int_bypasses_2_valid; // @[core.scala:174:27] wire _dec_valids_0_T_3; // @[core.scala:519:97] wire _dec_valids_1_T_3; // @[core.scala:519:97] wire dec_prior_slot_valid_1 = dec_valids_0; // @[core.scala:180:24, :605:71] wire dec_valids_1; // @[core.scala:180:24] wire dec_uops_0_iq_type_0; // @[core.scala:181:24] wire dec_uops_0_iq_type_1; // @[core.scala:181:24] wire dec_uops_0_iq_type_2; // @[core.scala:181:24] wire dec_uops_0_iq_type_3; // @[core.scala:181:24] wire dec_uops_0_fu_code_0; // @[core.scala:181:24] wire dec_uops_0_fu_code_1; // @[core.scala:181:24] wire dec_uops_0_fu_code_2; // @[core.scala:181:24] wire dec_uops_0_fu_code_3; // @[core.scala:181:24] wire dec_uops_0_fu_code_4; // @[core.scala:181:24] wire dec_uops_0_fu_code_5; // @[core.scala:181:24] wire dec_uops_0_fu_code_6; // @[core.scala:181:24] wire dec_uops_0_fu_code_7; // @[core.scala:181:24] wire dec_uops_0_fu_code_8; // @[core.scala:181:24] wire dec_uops_0_fu_code_9; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_ldst; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_wen; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_ren1; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_ren2; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_ren3; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_swap12; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_swap23; // @[core.scala:181:24] wire [1:0] dec_uops_0_fp_ctrl_typeTagIn; // @[core.scala:181:24] wire [1:0] dec_uops_0_fp_ctrl_typeTagOut; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_fromint; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_toint; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_fastpipe; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_fma; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_div; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_sqrt; // @[core.scala:181:24] wire dec_uops_0_fp_ctrl_wflags; // @[core.scala:181:24] wire [31:0] dec_uops_0_inst; // @[core.scala:181:24] wire [31:0] dec_uops_0_debug_inst; // @[core.scala:181:24] wire dec_uops_0_is_rvc; // @[core.scala:181:24] wire [39:0] dec_uops_0_debug_pc; // @[core.scala:181:24] wire [11:0] dec_uops_0_br_mask; // @[core.scala:181:24] wire [3:0] dec_uops_0_br_tag; // @[core.scala:181:24] wire [3:0] dec_uops_0_br_type; // @[core.scala:181:24] wire dec_uops_0_is_sfb; // @[core.scala:181:24] wire dec_uops_0_is_fence; // @[core.scala:181:24] wire dec_uops_0_is_fencei; // @[core.scala:181:24] wire dec_uops_0_is_sfence; // @[core.scala:181:24] wire dec_uops_0_is_amo; // @[core.scala:181:24] wire dec_uops_0_is_eret; // @[core.scala:181:24] wire dec_uops_0_is_sys_pc2epc; // @[core.scala:181:24] wire dec_uops_0_is_rocc; // @[core.scala:181:24] wire dec_uops_0_is_mov; // @[core.scala:181:24] wire [4:0] dec_uops_0_ftq_idx; // @[core.scala:181:24] wire dec_uops_0_edge_inst; // @[core.scala:181:24] wire [5:0] dec_uops_0_pc_lob; // @[core.scala:181:24] wire dec_uops_0_taken; // @[core.scala:181:24] wire dec_uops_0_imm_rename; // @[core.scala:181:24] wire [2:0] dec_uops_0_imm_sel; // @[core.scala:181:24] wire [4:0] dec_uops_0_pimm; // @[core.scala:181:24] wire [19:0] dec_uops_0_imm_packed; // @[core.scala:181:24] wire [1:0] dec_uops_0_op1_sel; // @[core.scala:181:24] wire [2:0] dec_uops_0_op2_sel; // @[core.scala:181:24] wire dec_uops_0_exception; // @[core.scala:181:24] wire [63:0] dec_uops_0_exc_cause; // @[core.scala:181:24] wire [4:0] dec_uops_0_mem_cmd; // @[core.scala:181:24] wire [1:0] dec_uops_0_mem_size; // @[core.scala:181:24] wire dec_uops_0_mem_signed; // @[core.scala:181:24] wire dec_uops_0_uses_ldq; // @[core.scala:181:24] wire dec_uops_0_uses_stq; // @[core.scala:181:24] wire dec_uops_0_is_unique; // @[core.scala:181:24] wire dec_uops_0_flush_on_commit; // @[core.scala:181:24] wire [2:0] dec_uops_0_csr_cmd; // @[core.scala:181:24] wire dec_uops_0_ldst_is_rs1; // @[core.scala:181:24] wire [5:0] dec_uops_0_ldst; // @[core.scala:181:24] wire [5:0] dec_uops_0_lrs1; // @[core.scala:181:24] wire [5:0] dec_uops_0_lrs2; // @[core.scala:181:24] wire [5:0] dec_uops_0_lrs3; // @[core.scala:181:24] wire [1:0] dec_uops_0_dst_rtype; // @[core.scala:181:24] wire [1:0] dec_uops_0_lrs1_rtype; // @[core.scala:181:24] wire [1:0] dec_uops_0_lrs2_rtype; // @[core.scala:181:24] wire dec_uops_0_frs3_en; // @[core.scala:181:24] wire dec_uops_0_fcn_dw; // @[core.scala:181:24] wire [4:0] dec_uops_0_fcn_op; // @[core.scala:181:24] wire dec_uops_0_fp_val; // @[core.scala:181:24] wire [2:0] dec_uops_0_fp_rm; // @[core.scala:181:24] wire [1:0] dec_uops_0_fp_typ; // @[core.scala:181:24] wire dec_uops_0_xcpt_pf_if; // @[core.scala:181:24] wire dec_uops_0_xcpt_ae_if; // @[core.scala:181:24] wire dec_uops_0_bp_debug_if; // @[core.scala:181:24] wire dec_uops_0_bp_xcpt_if; // @[core.scala:181:24] wire [2:0] dec_uops_0_debug_fsrc; // @[core.scala:181:24] wire dec_uops_1_iq_type_0; // @[core.scala:181:24] wire dec_uops_1_iq_type_1; // @[core.scala:181:24] wire dec_uops_1_iq_type_2; // @[core.scala:181:24] wire dec_uops_1_iq_type_3; // @[core.scala:181:24] wire dec_uops_1_fu_code_0; // @[core.scala:181:24] wire dec_uops_1_fu_code_1; // @[core.scala:181:24] wire dec_uops_1_fu_code_2; // @[core.scala:181:24] wire dec_uops_1_fu_code_3; // @[core.scala:181:24] wire dec_uops_1_fu_code_4; // @[core.scala:181:24] wire dec_uops_1_fu_code_5; // @[core.scala:181:24] wire dec_uops_1_fu_code_6; // @[core.scala:181:24] wire dec_uops_1_fu_code_7; // @[core.scala:181:24] wire dec_uops_1_fu_code_8; // @[core.scala:181:24] wire dec_uops_1_fu_code_9; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_ldst; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_wen; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_ren1; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_ren2; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_ren3; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_swap12; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_swap23; // @[core.scala:181:24] wire [1:0] dec_uops_1_fp_ctrl_typeTagIn; // @[core.scala:181:24] wire [1:0] dec_uops_1_fp_ctrl_typeTagOut; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_fromint; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_toint; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_fastpipe; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_fma; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_div; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_sqrt; // @[core.scala:181:24] wire dec_uops_1_fp_ctrl_wflags; // @[core.scala:181:24] wire [31:0] dec_uops_1_inst; // @[core.scala:181:24] wire [31:0] dec_uops_1_debug_inst; // @[core.scala:181:24] wire dec_uops_1_is_rvc; // @[core.scala:181:24] wire [39:0] dec_uops_1_debug_pc; // @[core.scala:181:24] wire [11:0] dec_uops_1_br_mask; // @[core.scala:181:24] wire [3:0] dec_uops_1_br_tag; // @[core.scala:181:24] wire [3:0] dec_uops_1_br_type; // @[core.scala:181:24] wire dec_uops_1_is_sfb; // @[core.scala:181:24] wire dec_uops_1_is_fence; // @[core.scala:181:24] wire dec_uops_1_is_fencei; // @[core.scala:181:24] wire dec_uops_1_is_sfence; // @[core.scala:181:24] wire dec_uops_1_is_amo; // @[core.scala:181:24] wire dec_uops_1_is_eret; // @[core.scala:181:24] wire dec_uops_1_is_sys_pc2epc; // @[core.scala:181:24] wire dec_uops_1_is_rocc; // @[core.scala:181:24] wire dec_uops_1_is_mov; // @[core.scala:181:24] wire [4:0] dec_uops_1_ftq_idx; // @[core.scala:181:24] wire dec_uops_1_edge_inst; // @[core.scala:181:24] wire [5:0] dec_uops_1_pc_lob; // @[core.scala:181:24] wire dec_uops_1_taken; // @[core.scala:181:24] wire dec_uops_1_imm_rename; // @[core.scala:181:24] wire [2:0] dec_uops_1_imm_sel; // @[core.scala:181:24] wire [4:0] dec_uops_1_pimm; // @[core.scala:181:24] wire [19:0] dec_uops_1_imm_packed; // @[core.scala:181:24] wire [1:0] dec_uops_1_op1_sel; // @[core.scala:181:24] wire [2:0] dec_uops_1_op2_sel; // @[core.scala:181:24] wire dec_uops_1_exception; // @[core.scala:181:24] wire [63:0] dec_uops_1_exc_cause; // @[core.scala:181:24] wire [4:0] dec_uops_1_mem_cmd; // @[core.scala:181:24] wire [1:0] dec_uops_1_mem_size; // @[core.scala:181:24] wire dec_uops_1_mem_signed; // @[core.scala:181:24] wire dec_uops_1_uses_ldq; // @[core.scala:181:24] wire dec_uops_1_uses_stq; // @[core.scala:181:24] wire dec_uops_1_is_unique; // @[core.scala:181:24] wire dec_uops_1_flush_on_commit; // @[core.scala:181:24] wire [2:0] dec_uops_1_csr_cmd; // @[core.scala:181:24] wire dec_uops_1_ldst_is_rs1; // @[core.scala:181:24] wire [5:0] dec_uops_1_ldst; // @[core.scala:181:24] wire [5:0] dec_uops_1_lrs1; // @[core.scala:181:24] wire [5:0] dec_uops_1_lrs2; // @[core.scala:181:24] wire [5:0] dec_uops_1_lrs3; // @[core.scala:181:24] wire [1:0] dec_uops_1_dst_rtype; // @[core.scala:181:24] wire [1:0] dec_uops_1_lrs1_rtype; // @[core.scala:181:24] wire [1:0] dec_uops_1_lrs2_rtype; // @[core.scala:181:24] wire dec_uops_1_frs3_en; // @[core.scala:181:24] wire dec_uops_1_fcn_dw; // @[core.scala:181:24] wire [4:0] dec_uops_1_fcn_op; // @[core.scala:181:24] wire dec_uops_1_fp_val; // @[core.scala:181:24] wire [2:0] dec_uops_1_fp_rm; // @[core.scala:181:24] wire [1:0] dec_uops_1_fp_typ; // @[core.scala:181:24] wire dec_uops_1_xcpt_pf_if; // @[core.scala:181:24] wire dec_uops_1_xcpt_ae_if; // @[core.scala:181:24] wire dec_uops_1_bp_debug_if; // @[core.scala:181:24] wire dec_uops_1_bp_xcpt_if; // @[core.scala:181:24] wire [2:0] dec_uops_1_debug_fsrc; // @[core.scala:181:24] wire dec_fire_0; // @[core.scala:182:24] wire dec_fire_1; // @[core.scala:182:24] assign dec_ready = dec_fire_1; // @[core.scala:182:24, :184:24] assign io_ifu_fetchpacket_ready_0 = dec_ready; // @[core.scala:50:7, :184:24] wire dec_xcpts_0; // @[core.scala:185:24] wire dec_xcpts_1; // @[core.scala:185:24] wire _ren_stalls_0_T_2; // @[core.scala:719:74] wire _ren_stalls_1_T_2; // @[core.scala:719:74] wire ren_stalls_0; // @[core.scala:186:24] wire ren_stalls_1; // @[core.scala:186:24] wire dis_prior_slot_valid_1 = dis_valids_0; // @[core.scala:189:24, :731:71] wire dis_valids_1; // @[core.scala:189:24] assign io_lsu_dis_uops_0_bits_inst_0 = dis_uops_0_inst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_debug_inst_0 = dis_uops_0_debug_inst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_is_rvc_0 = dis_uops_0_is_rvc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_debug_pc_0 = dis_uops_0_debug_pc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iq_type_0_0 = dis_uops_0_iq_type_0; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iq_type_1_0 = dis_uops_0_iq_type_1; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iq_type_2_0 = dis_uops_0_iq_type_2; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iq_type_3_0 = dis_uops_0_iq_type_3; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fu_code_0_0 = dis_uops_0_fu_code_0; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fu_code_1_0 = dis_uops_0_fu_code_1; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fu_code_2_0 = dis_uops_0_fu_code_2; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fu_code_3_0 = dis_uops_0_fu_code_3; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fu_code_4_0 = dis_uops_0_fu_code_4; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fu_code_5_0 = dis_uops_0_fu_code_5; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fu_code_6_0 = dis_uops_0_fu_code_6; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fu_code_7_0 = dis_uops_0_fu_code_7; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fu_code_8_0 = dis_uops_0_fu_code_8; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fu_code_9_0 = dis_uops_0_fu_code_9; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iw_issued_0 = dis_uops_0_iw_issued; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iw_issued_partial_agen_0 = dis_uops_0_iw_issued_partial_agen; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iw_issued_partial_dgen_0 = dis_uops_0_iw_issued_partial_dgen; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iw_p1_speculative_child_0 = dis_uops_0_iw_p1_speculative_child; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iw_p2_speculative_child_0 = dis_uops_0_iw_p2_speculative_child; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iw_p1_bypass_hint_0 = dis_uops_0_iw_p1_bypass_hint; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iw_p2_bypass_hint_0 = dis_uops_0_iw_p2_bypass_hint; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_iw_p3_bypass_hint_0 = dis_uops_0_iw_p3_bypass_hint; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_dis_col_sel_0 = dis_uops_0_dis_col_sel; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_br_mask_0 = dis_uops_0_br_mask; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_br_tag_0 = dis_uops_0_br_tag; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_br_type_0 = dis_uops_0_br_type; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_is_sfb_0 = dis_uops_0_is_sfb; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_is_fence_0 = dis_uops_0_is_fence; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_is_fencei_0 = dis_uops_0_is_fencei; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_is_sfence_0 = dis_uops_0_is_sfence; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_is_amo_0 = dis_uops_0_is_amo; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_is_eret_0 = dis_uops_0_is_eret; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_is_sys_pc2epc_0 = dis_uops_0_is_sys_pc2epc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_is_rocc_0 = dis_uops_0_is_rocc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_is_mov_0 = dis_uops_0_is_mov; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_ftq_idx_0 = dis_uops_0_ftq_idx; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_edge_inst_0 = dis_uops_0_edge_inst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_pc_lob_0 = dis_uops_0_pc_lob; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_taken_0 = dis_uops_0_taken; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_imm_rename_0 = dis_uops_0_imm_rename; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_imm_sel_0 = dis_uops_0_imm_sel; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_pimm_0 = dis_uops_0_pimm; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_imm_packed_0 = dis_uops_0_imm_packed; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_op1_sel_0 = dis_uops_0_op1_sel; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_op2_sel_0 = dis_uops_0_op2_sel; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_ldst_0 = dis_uops_0_fp_ctrl_ldst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_wen_0 = dis_uops_0_fp_ctrl_wen; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_ren1_0 = dis_uops_0_fp_ctrl_ren1; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_ren2_0 = dis_uops_0_fp_ctrl_ren2; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_ren3_0 = dis_uops_0_fp_ctrl_ren3; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_swap12_0 = dis_uops_0_fp_ctrl_swap12; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_swap23_0 = dis_uops_0_fp_ctrl_swap23; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_typeTagIn_0 = dis_uops_0_fp_ctrl_typeTagIn; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_typeTagOut_0 = dis_uops_0_fp_ctrl_typeTagOut; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_fromint_0 = dis_uops_0_fp_ctrl_fromint; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_toint_0 = dis_uops_0_fp_ctrl_toint; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_fastpipe_0 = dis_uops_0_fp_ctrl_fastpipe; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_fma_0 = dis_uops_0_fp_ctrl_fma; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_div_0 = dis_uops_0_fp_ctrl_div; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_sqrt_0 = dis_uops_0_fp_ctrl_sqrt; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_wflags_0 = dis_uops_0_fp_ctrl_wflags; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_ctrl_vec_0 = dis_uops_0_fp_ctrl_vec; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_rob_idx_0 = dis_uops_0_rob_idx; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_ldq_idx_0 = dis_uops_0_ldq_idx; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_stq_idx_0 = dis_uops_0_stq_idx; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_rxq_idx_0 = dis_uops_0_rxq_idx; // @[core.scala:50:7, :190:24] wire [6:0] _dis_uops_0_pdst_T_8; // @[core.scala:702:28] assign io_lsu_dis_uops_0_bits_pdst_0 = dis_uops_0_pdst; // @[core.scala:50:7, :190:24] wire [6:0] _dis_uops_0_prs1_T_3; // @[core.scala:697:28] assign io_lsu_dis_uops_0_bits_prs1_0 = dis_uops_0_prs1; // @[core.scala:50:7, :190:24] wire [6:0] _dis_uops_0_prs2_T_1; // @[core.scala:699:28] assign io_lsu_dis_uops_0_bits_prs2_0 = dis_uops_0_prs2; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_prs3_0 = dis_uops_0_prs3; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_ppred_0 = dis_uops_0_ppred; // @[core.scala:50:7, :190:24] wire _dis_uops_0_prs1_busy_T_4; // @[core.scala:712:85] assign io_lsu_dis_uops_0_bits_prs1_busy_0 = dis_uops_0_prs1_busy; // @[core.scala:50:7, :190:24] wire _dis_uops_0_prs2_busy_T_4; // @[core.scala:714:85] assign io_lsu_dis_uops_0_bits_prs2_busy_0 = dis_uops_0_prs2_busy; // @[core.scala:50:7, :190:24] wire _dis_uops_0_prs3_busy_T; // @[core.scala:716:46] assign io_lsu_dis_uops_0_bits_prs3_busy_0 = dis_uops_0_prs3_busy; // @[core.scala:50:7, :190:24] wire _dis_uops_0_ppred_busy_T_3; // @[core.scala:717:48] assign io_lsu_dis_uops_0_bits_ppred_busy_0 = dis_uops_0_ppred_busy; // @[core.scala:50:7, :190:24] wire [6:0] _dis_uops_0_stale_pdst_T_1; // @[core.scala:710:34] assign io_lsu_dis_uops_0_bits_stale_pdst_0 = dis_uops_0_stale_pdst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_exception_0 = dis_uops_0_exception; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_exc_cause_0 = dis_uops_0_exc_cause; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_mem_cmd_0 = dis_uops_0_mem_cmd; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_mem_size_0 = dis_uops_0_mem_size; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_mem_signed_0 = dis_uops_0_mem_signed; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_uses_ldq_0 = dis_uops_0_uses_ldq; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_uses_stq_0 = dis_uops_0_uses_stq; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_is_unique_0 = dis_uops_0_is_unique; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_flush_on_commit_0 = dis_uops_0_flush_on_commit; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_csr_cmd_0 = dis_uops_0_csr_cmd; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_ldst_is_rs1_0 = dis_uops_0_ldst_is_rs1; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_ldst_0 = dis_uops_0_ldst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_lrs1_0 = dis_uops_0_lrs1; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_lrs2_0 = dis_uops_0_lrs2; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_lrs3_0 = dis_uops_0_lrs3; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_dst_rtype_0 = dis_uops_0_dst_rtype; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_lrs1_rtype_0 = dis_uops_0_lrs1_rtype; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_lrs2_rtype_0 = dis_uops_0_lrs2_rtype; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_frs3_en_0 = dis_uops_0_frs3_en; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fcn_dw_0 = dis_uops_0_fcn_dw; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fcn_op_0 = dis_uops_0_fcn_op; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_val_0 = dis_uops_0_fp_val; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_rm_0 = dis_uops_0_fp_rm; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_fp_typ_0 = dis_uops_0_fp_typ; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_xcpt_pf_if_0 = dis_uops_0_xcpt_pf_if; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_xcpt_ae_if_0 = dis_uops_0_xcpt_ae_if; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_xcpt_ma_if_0 = dis_uops_0_xcpt_ma_if; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_bp_debug_if_0 = dis_uops_0_bp_debug_if; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_bp_xcpt_if_0 = dis_uops_0_bp_xcpt_if; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_debug_fsrc_0 = dis_uops_0_debug_fsrc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_bits_debug_tsrc_0 = dis_uops_0_debug_tsrc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_inst_0 = dis_uops_1_inst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_debug_inst_0 = dis_uops_1_debug_inst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_is_rvc_0 = dis_uops_1_is_rvc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_debug_pc_0 = dis_uops_1_debug_pc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iq_type_0_0 = dis_uops_1_iq_type_0; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iq_type_1_0 = dis_uops_1_iq_type_1; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iq_type_2_0 = dis_uops_1_iq_type_2; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iq_type_3_0 = dis_uops_1_iq_type_3; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fu_code_0_0 = dis_uops_1_fu_code_0; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fu_code_1_0 = dis_uops_1_fu_code_1; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fu_code_2_0 = dis_uops_1_fu_code_2; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fu_code_3_0 = dis_uops_1_fu_code_3; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fu_code_4_0 = dis_uops_1_fu_code_4; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fu_code_5_0 = dis_uops_1_fu_code_5; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fu_code_6_0 = dis_uops_1_fu_code_6; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fu_code_7_0 = dis_uops_1_fu_code_7; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fu_code_8_0 = dis_uops_1_fu_code_8; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fu_code_9_0 = dis_uops_1_fu_code_9; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iw_issued_0 = dis_uops_1_iw_issued; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iw_issued_partial_agen_0 = dis_uops_1_iw_issued_partial_agen; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iw_issued_partial_dgen_0 = dis_uops_1_iw_issued_partial_dgen; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iw_p1_speculative_child_0 = dis_uops_1_iw_p1_speculative_child; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iw_p2_speculative_child_0 = dis_uops_1_iw_p2_speculative_child; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iw_p1_bypass_hint_0 = dis_uops_1_iw_p1_bypass_hint; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iw_p2_bypass_hint_0 = dis_uops_1_iw_p2_bypass_hint; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_iw_p3_bypass_hint_0 = dis_uops_1_iw_p3_bypass_hint; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_dis_col_sel_0 = dis_uops_1_dis_col_sel; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_br_mask_0 = dis_uops_1_br_mask; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_br_tag_0 = dis_uops_1_br_tag; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_br_type_0 = dis_uops_1_br_type; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_is_sfb_0 = dis_uops_1_is_sfb; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_is_fence_0 = dis_uops_1_is_fence; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_is_fencei_0 = dis_uops_1_is_fencei; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_is_sfence_0 = dis_uops_1_is_sfence; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_is_amo_0 = dis_uops_1_is_amo; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_is_eret_0 = dis_uops_1_is_eret; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_is_sys_pc2epc_0 = dis_uops_1_is_sys_pc2epc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_is_rocc_0 = dis_uops_1_is_rocc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_is_mov_0 = dis_uops_1_is_mov; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_ftq_idx_0 = dis_uops_1_ftq_idx; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_edge_inst_0 = dis_uops_1_edge_inst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_pc_lob_0 = dis_uops_1_pc_lob; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_taken_0 = dis_uops_1_taken; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_imm_rename_0 = dis_uops_1_imm_rename; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_imm_sel_0 = dis_uops_1_imm_sel; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_pimm_0 = dis_uops_1_pimm; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_imm_packed_0 = dis_uops_1_imm_packed; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_op1_sel_0 = dis_uops_1_op1_sel; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_op2_sel_0 = dis_uops_1_op2_sel; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_ldst_0 = dis_uops_1_fp_ctrl_ldst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_wen_0 = dis_uops_1_fp_ctrl_wen; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_ren1_0 = dis_uops_1_fp_ctrl_ren1; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_ren2_0 = dis_uops_1_fp_ctrl_ren2; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_ren3_0 = dis_uops_1_fp_ctrl_ren3; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_swap12_0 = dis_uops_1_fp_ctrl_swap12; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_swap23_0 = dis_uops_1_fp_ctrl_swap23; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_typeTagIn_0 = dis_uops_1_fp_ctrl_typeTagIn; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_typeTagOut_0 = dis_uops_1_fp_ctrl_typeTagOut; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_fromint_0 = dis_uops_1_fp_ctrl_fromint; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_toint_0 = dis_uops_1_fp_ctrl_toint; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_fastpipe_0 = dis_uops_1_fp_ctrl_fastpipe; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_fma_0 = dis_uops_1_fp_ctrl_fma; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_div_0 = dis_uops_1_fp_ctrl_div; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_sqrt_0 = dis_uops_1_fp_ctrl_sqrt; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_wflags_0 = dis_uops_1_fp_ctrl_wflags; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_ctrl_vec_0 = dis_uops_1_fp_ctrl_vec; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_rob_idx_0 = dis_uops_1_rob_idx; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_ldq_idx_0 = dis_uops_1_ldq_idx; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_stq_idx_0 = dis_uops_1_stq_idx; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_rxq_idx_0 = dis_uops_1_rxq_idx; // @[core.scala:50:7, :190:24] wire [6:0] _dis_uops_1_pdst_T_8; // @[core.scala:702:28] assign io_lsu_dis_uops_1_bits_pdst_0 = dis_uops_1_pdst; // @[core.scala:50:7, :190:24] wire [6:0] _dis_uops_1_prs1_T_3; // @[core.scala:697:28] assign io_lsu_dis_uops_1_bits_prs1_0 = dis_uops_1_prs1; // @[core.scala:50:7, :190:24] wire [6:0] _dis_uops_1_prs2_T_1; // @[core.scala:699:28] assign io_lsu_dis_uops_1_bits_prs2_0 = dis_uops_1_prs2; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_prs3_0 = dis_uops_1_prs3; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_ppred_0 = dis_uops_1_ppred; // @[core.scala:50:7, :190:24] wire _dis_uops_1_prs1_busy_T_4; // @[core.scala:712:85] assign io_lsu_dis_uops_1_bits_prs1_busy_0 = dis_uops_1_prs1_busy; // @[core.scala:50:7, :190:24] wire _dis_uops_1_prs2_busy_T_4; // @[core.scala:714:85] assign io_lsu_dis_uops_1_bits_prs2_busy_0 = dis_uops_1_prs2_busy; // @[core.scala:50:7, :190:24] wire _dis_uops_1_prs3_busy_T; // @[core.scala:716:46] assign io_lsu_dis_uops_1_bits_prs3_busy_0 = dis_uops_1_prs3_busy; // @[core.scala:50:7, :190:24] wire _dis_uops_1_ppred_busy_T_3; // @[core.scala:717:48] assign io_lsu_dis_uops_1_bits_ppred_busy_0 = dis_uops_1_ppred_busy; // @[core.scala:50:7, :190:24] wire [6:0] _dis_uops_1_stale_pdst_T_1; // @[core.scala:710:34] assign io_lsu_dis_uops_1_bits_stale_pdst_0 = dis_uops_1_stale_pdst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_exception_0 = dis_uops_1_exception; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_exc_cause_0 = dis_uops_1_exc_cause; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_mem_cmd_0 = dis_uops_1_mem_cmd; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_mem_size_0 = dis_uops_1_mem_size; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_mem_signed_0 = dis_uops_1_mem_signed; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_uses_ldq_0 = dis_uops_1_uses_ldq; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_uses_stq_0 = dis_uops_1_uses_stq; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_is_unique_0 = dis_uops_1_is_unique; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_flush_on_commit_0 = dis_uops_1_flush_on_commit; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_csr_cmd_0 = dis_uops_1_csr_cmd; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_ldst_is_rs1_0 = dis_uops_1_ldst_is_rs1; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_ldst_0 = dis_uops_1_ldst; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_lrs1_0 = dis_uops_1_lrs1; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_lrs2_0 = dis_uops_1_lrs2; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_lrs3_0 = dis_uops_1_lrs3; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_dst_rtype_0 = dis_uops_1_dst_rtype; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_lrs1_rtype_0 = dis_uops_1_lrs1_rtype; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_lrs2_rtype_0 = dis_uops_1_lrs2_rtype; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_frs3_en_0 = dis_uops_1_frs3_en; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fcn_dw_0 = dis_uops_1_fcn_dw; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fcn_op_0 = dis_uops_1_fcn_op; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_val_0 = dis_uops_1_fp_val; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_rm_0 = dis_uops_1_fp_rm; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_fp_typ_0 = dis_uops_1_fp_typ; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_xcpt_pf_if_0 = dis_uops_1_xcpt_pf_if; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_xcpt_ae_if_0 = dis_uops_1_xcpt_ae_if; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_xcpt_ma_if_0 = dis_uops_1_xcpt_ma_if; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_bp_debug_if_0 = dis_uops_1_bp_debug_if; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_bp_xcpt_if_0 = dis_uops_1_bp_xcpt_if; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_debug_fsrc_0 = dis_uops_1_debug_fsrc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_1_bits_debug_tsrc_0 = dis_uops_1_debug_tsrc; // @[core.scala:50:7, :190:24] assign io_lsu_dis_uops_0_valid_0 = dis_fire_0; // @[core.scala:50:7, :191:24] assign io_lsu_dis_uops_1_valid_0 = dis_fire_1; // @[core.scala:50:7, :191:24] wire _dis_ready_T; // @[core.scala:769:16] wire dis_ready; // @[core.scala:192:24] reg brinfos_0_valid; // @[core.scala:203:20] reg [31:0] brinfos_0_bits_uop_inst; // @[core.scala:203:20] reg [31:0] brinfos_0_bits_uop_debug_inst; // @[core.scala:203:20] reg brinfos_0_bits_uop_is_rvc; // @[core.scala:203:20] reg [39:0] brinfos_0_bits_uop_debug_pc; // @[core.scala:203:20] reg brinfos_0_bits_uop_iq_type_0; // @[core.scala:203:20] reg brinfos_0_bits_uop_iq_type_1; // @[core.scala:203:20] reg brinfos_0_bits_uop_iq_type_2; // @[core.scala:203:20] reg brinfos_0_bits_uop_iq_type_3; // @[core.scala:203:20] reg brinfos_0_bits_uop_fu_code_0; // @[core.scala:203:20] reg brinfos_0_bits_uop_fu_code_1; // @[core.scala:203:20] reg brinfos_0_bits_uop_fu_code_2; // @[core.scala:203:20] reg brinfos_0_bits_uop_fu_code_3; // @[core.scala:203:20] reg brinfos_0_bits_uop_fu_code_4; // @[core.scala:203:20] reg brinfos_0_bits_uop_fu_code_5; // @[core.scala:203:20] reg brinfos_0_bits_uop_fu_code_6; // @[core.scala:203:20] reg brinfos_0_bits_uop_fu_code_7; // @[core.scala:203:20] reg brinfos_0_bits_uop_fu_code_8; // @[core.scala:203:20] reg brinfos_0_bits_uop_fu_code_9; // @[core.scala:203:20] reg brinfos_0_bits_uop_iw_issued; // @[core.scala:203:20] reg brinfos_0_bits_uop_iw_issued_partial_agen; // @[core.scala:203:20] reg brinfos_0_bits_uop_iw_issued_partial_dgen; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_iw_p1_speculative_child; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_iw_p2_speculative_child; // @[core.scala:203:20] reg brinfos_0_bits_uop_iw_p1_bypass_hint; // @[core.scala:203:20] reg brinfos_0_bits_uop_iw_p2_bypass_hint; // @[core.scala:203:20] reg brinfos_0_bits_uop_iw_p3_bypass_hint; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_dis_col_sel; // @[core.scala:203:20] reg [11:0] brinfos_0_bits_uop_br_mask; // @[core.scala:203:20] reg [3:0] brinfos_0_bits_uop_br_tag; // @[core.scala:203:20] reg [3:0] brinfos_0_bits_uop_br_type; // @[core.scala:203:20] reg brinfos_0_bits_uop_is_sfb; // @[core.scala:203:20] reg brinfos_0_bits_uop_is_fence; // @[core.scala:203:20] reg brinfos_0_bits_uop_is_fencei; // @[core.scala:203:20] reg brinfos_0_bits_uop_is_sfence; // @[core.scala:203:20] reg brinfos_0_bits_uop_is_amo; // @[core.scala:203:20] reg brinfos_0_bits_uop_is_eret; // @[core.scala:203:20] reg brinfos_0_bits_uop_is_sys_pc2epc; // @[core.scala:203:20] reg brinfos_0_bits_uop_is_rocc; // @[core.scala:203:20] reg brinfos_0_bits_uop_is_mov; // @[core.scala:203:20] reg [4:0] brinfos_0_bits_uop_ftq_idx; // @[core.scala:203:20] reg brinfos_0_bits_uop_edge_inst; // @[core.scala:203:20] reg [5:0] brinfos_0_bits_uop_pc_lob; // @[core.scala:203:20] reg brinfos_0_bits_uop_taken; // @[core.scala:203:20] reg brinfos_0_bits_uop_imm_rename; // @[core.scala:203:20] reg [2:0] brinfos_0_bits_uop_imm_sel; // @[core.scala:203:20] reg [4:0] brinfos_0_bits_uop_pimm; // @[core.scala:203:20] reg [19:0] brinfos_0_bits_uop_imm_packed; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_op1_sel; // @[core.scala:203:20] reg [2:0] brinfos_0_bits_uop_op2_sel; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_ldst; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_wen; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_ren1; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_ren2; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_ren3; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_swap12; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_swap23; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_fromint; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_toint; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_fastpipe; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_fma; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_div; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_sqrt; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_wflags; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_ctrl_vec; // @[core.scala:203:20] reg [5:0] brinfos_0_bits_uop_rob_idx; // @[core.scala:203:20] reg [3:0] brinfos_0_bits_uop_ldq_idx; // @[core.scala:203:20] reg [3:0] brinfos_0_bits_uop_stq_idx; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_rxq_idx; // @[core.scala:203:20] reg [6:0] brinfos_0_bits_uop_pdst; // @[core.scala:203:20] reg [6:0] brinfos_0_bits_uop_prs1; // @[core.scala:203:20] reg [6:0] brinfos_0_bits_uop_prs2; // @[core.scala:203:20] reg [6:0] brinfos_0_bits_uop_prs3; // @[core.scala:203:20] reg [4:0] brinfos_0_bits_uop_ppred; // @[core.scala:203:20] reg brinfos_0_bits_uop_prs1_busy; // @[core.scala:203:20] reg brinfos_0_bits_uop_prs2_busy; // @[core.scala:203:20] reg brinfos_0_bits_uop_prs3_busy; // @[core.scala:203:20] reg brinfos_0_bits_uop_ppred_busy; // @[core.scala:203:20] reg [6:0] brinfos_0_bits_uop_stale_pdst; // @[core.scala:203:20] reg brinfos_0_bits_uop_exception; // @[core.scala:203:20] reg [63:0] brinfos_0_bits_uop_exc_cause; // @[core.scala:203:20] reg [4:0] brinfos_0_bits_uop_mem_cmd; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_mem_size; // @[core.scala:203:20] reg brinfos_0_bits_uop_mem_signed; // @[core.scala:203:20] reg brinfos_0_bits_uop_uses_ldq; // @[core.scala:203:20] reg brinfos_0_bits_uop_uses_stq; // @[core.scala:203:20] reg brinfos_0_bits_uop_is_unique; // @[core.scala:203:20] reg brinfos_0_bits_uop_flush_on_commit; // @[core.scala:203:20] reg [2:0] brinfos_0_bits_uop_csr_cmd; // @[core.scala:203:20] reg brinfos_0_bits_uop_ldst_is_rs1; // @[core.scala:203:20] reg [5:0] brinfos_0_bits_uop_ldst; // @[core.scala:203:20] reg [5:0] brinfos_0_bits_uop_lrs1; // @[core.scala:203:20] reg [5:0] brinfos_0_bits_uop_lrs2; // @[core.scala:203:20] reg [5:0] brinfos_0_bits_uop_lrs3; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_dst_rtype; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_lrs1_rtype; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_lrs2_rtype; // @[core.scala:203:20] reg brinfos_0_bits_uop_frs3_en; // @[core.scala:203:20] reg brinfos_0_bits_uop_fcn_dw; // @[core.scala:203:20] reg [4:0] brinfos_0_bits_uop_fcn_op; // @[core.scala:203:20] reg brinfos_0_bits_uop_fp_val; // @[core.scala:203:20] reg [2:0] brinfos_0_bits_uop_fp_rm; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_uop_fp_typ; // @[core.scala:203:20] reg brinfos_0_bits_uop_xcpt_pf_if; // @[core.scala:203:20] reg brinfos_0_bits_uop_xcpt_ae_if; // @[core.scala:203:20] reg brinfos_0_bits_uop_xcpt_ma_if; // @[core.scala:203:20] reg brinfos_0_bits_uop_bp_debug_if; // @[core.scala:203:20] reg brinfos_0_bits_uop_bp_xcpt_if; // @[core.scala:203:20] reg [2:0] brinfos_0_bits_uop_debug_fsrc; // @[core.scala:203:20] reg [2:0] brinfos_0_bits_uop_debug_tsrc; // @[core.scala:203:20] reg brinfos_0_bits_mispredict; // @[core.scala:203:20] reg brinfos_0_bits_taken; // @[core.scala:203:20] reg [2:0] brinfos_0_bits_cfi_type; // @[core.scala:203:20] reg [1:0] brinfos_0_bits_pc_sel; // @[core.scala:203:20] reg [39:0] brinfos_0_bits_jalr_target; // @[core.scala:203:20] reg [20:0] brinfos_0_bits_target_offset; // @[core.scala:203:20] wire [20:0] _b2_target_offset_T = brinfos_0_bits_target_offset; // @[Mux.scala:30:73] reg brinfos_1_valid; // @[core.scala:203:20] reg [31:0] brinfos_1_bits_uop_inst; // @[core.scala:203:20] reg [31:0] brinfos_1_bits_uop_debug_inst; // @[core.scala:203:20] reg brinfos_1_bits_uop_is_rvc; // @[core.scala:203:20] reg [39:0] brinfos_1_bits_uop_debug_pc; // @[core.scala:203:20] reg brinfos_1_bits_uop_iq_type_0; // @[core.scala:203:20] reg brinfos_1_bits_uop_iq_type_1; // @[core.scala:203:20] reg brinfos_1_bits_uop_iq_type_2; // @[core.scala:203:20] reg brinfos_1_bits_uop_iq_type_3; // @[core.scala:203:20] reg brinfos_1_bits_uop_fu_code_0; // @[core.scala:203:20] reg brinfos_1_bits_uop_fu_code_1; // @[core.scala:203:20] reg brinfos_1_bits_uop_fu_code_2; // @[core.scala:203:20] reg brinfos_1_bits_uop_fu_code_3; // @[core.scala:203:20] reg brinfos_1_bits_uop_fu_code_4; // @[core.scala:203:20] reg brinfos_1_bits_uop_fu_code_5; // @[core.scala:203:20] reg brinfos_1_bits_uop_fu_code_6; // @[core.scala:203:20] reg brinfos_1_bits_uop_fu_code_7; // @[core.scala:203:20] reg brinfos_1_bits_uop_fu_code_8; // @[core.scala:203:20] reg brinfos_1_bits_uop_fu_code_9; // @[core.scala:203:20] reg brinfos_1_bits_uop_iw_issued; // @[core.scala:203:20] reg brinfos_1_bits_uop_iw_issued_partial_agen; // @[core.scala:203:20] reg brinfos_1_bits_uop_iw_issued_partial_dgen; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_iw_p1_speculative_child; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_iw_p2_speculative_child; // @[core.scala:203:20] reg brinfos_1_bits_uop_iw_p1_bypass_hint; // @[core.scala:203:20] reg brinfos_1_bits_uop_iw_p2_bypass_hint; // @[core.scala:203:20] reg brinfos_1_bits_uop_iw_p3_bypass_hint; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_dis_col_sel; // @[core.scala:203:20] reg [11:0] brinfos_1_bits_uop_br_mask; // @[core.scala:203:20] reg [3:0] brinfos_1_bits_uop_br_tag; // @[core.scala:203:20] reg [3:0] brinfos_1_bits_uop_br_type; // @[core.scala:203:20] reg brinfos_1_bits_uop_is_sfb; // @[core.scala:203:20] reg brinfos_1_bits_uop_is_fence; // @[core.scala:203:20] reg brinfos_1_bits_uop_is_fencei; // @[core.scala:203:20] reg brinfos_1_bits_uop_is_sfence; // @[core.scala:203:20] reg brinfos_1_bits_uop_is_amo; // @[core.scala:203:20] reg brinfos_1_bits_uop_is_eret; // @[core.scala:203:20] reg brinfos_1_bits_uop_is_sys_pc2epc; // @[core.scala:203:20] reg brinfos_1_bits_uop_is_rocc; // @[core.scala:203:20] reg brinfos_1_bits_uop_is_mov; // @[core.scala:203:20] reg [4:0] brinfos_1_bits_uop_ftq_idx; // @[core.scala:203:20] reg brinfos_1_bits_uop_edge_inst; // @[core.scala:203:20] reg [5:0] brinfos_1_bits_uop_pc_lob; // @[core.scala:203:20] reg brinfos_1_bits_uop_taken; // @[core.scala:203:20] reg brinfos_1_bits_uop_imm_rename; // @[core.scala:203:20] reg [2:0] brinfos_1_bits_uop_imm_sel; // @[core.scala:203:20] reg [4:0] brinfos_1_bits_uop_pimm; // @[core.scala:203:20] reg [19:0] brinfos_1_bits_uop_imm_packed; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_op1_sel; // @[core.scala:203:20] reg [2:0] brinfos_1_bits_uop_op2_sel; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_ldst; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_wen; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_ren1; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_ren2; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_ren3; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_swap12; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_swap23; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_fromint; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_toint; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_fastpipe; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_fma; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_div; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_sqrt; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_wflags; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_ctrl_vec; // @[core.scala:203:20] reg [5:0] brinfos_1_bits_uop_rob_idx; // @[core.scala:203:20] reg [3:0] brinfos_1_bits_uop_ldq_idx; // @[core.scala:203:20] reg [3:0] brinfos_1_bits_uop_stq_idx; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_rxq_idx; // @[core.scala:203:20] reg [6:0] brinfos_1_bits_uop_pdst; // @[core.scala:203:20] reg [6:0] brinfos_1_bits_uop_prs1; // @[core.scala:203:20] reg [6:0] brinfos_1_bits_uop_prs2; // @[core.scala:203:20] reg [6:0] brinfos_1_bits_uop_prs3; // @[core.scala:203:20] reg [4:0] brinfos_1_bits_uop_ppred; // @[core.scala:203:20] reg brinfos_1_bits_uop_prs1_busy; // @[core.scala:203:20] reg brinfos_1_bits_uop_prs2_busy; // @[core.scala:203:20] reg brinfos_1_bits_uop_prs3_busy; // @[core.scala:203:20] reg brinfos_1_bits_uop_ppred_busy; // @[core.scala:203:20] reg [6:0] brinfos_1_bits_uop_stale_pdst; // @[core.scala:203:20] reg brinfos_1_bits_uop_exception; // @[core.scala:203:20] reg [63:0] brinfos_1_bits_uop_exc_cause; // @[core.scala:203:20] reg [4:0] brinfos_1_bits_uop_mem_cmd; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_mem_size; // @[core.scala:203:20] reg brinfos_1_bits_uop_mem_signed; // @[core.scala:203:20] reg brinfos_1_bits_uop_uses_ldq; // @[core.scala:203:20] reg brinfos_1_bits_uop_uses_stq; // @[core.scala:203:20] reg brinfos_1_bits_uop_is_unique; // @[core.scala:203:20] reg brinfos_1_bits_uop_flush_on_commit; // @[core.scala:203:20] reg [2:0] brinfos_1_bits_uop_csr_cmd; // @[core.scala:203:20] reg brinfos_1_bits_uop_ldst_is_rs1; // @[core.scala:203:20] reg [5:0] brinfos_1_bits_uop_ldst; // @[core.scala:203:20] reg [5:0] brinfos_1_bits_uop_lrs1; // @[core.scala:203:20] reg [5:0] brinfos_1_bits_uop_lrs2; // @[core.scala:203:20] reg [5:0] brinfos_1_bits_uop_lrs3; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_dst_rtype; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_lrs1_rtype; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_lrs2_rtype; // @[core.scala:203:20] reg brinfos_1_bits_uop_frs3_en; // @[core.scala:203:20] reg brinfos_1_bits_uop_fcn_dw; // @[core.scala:203:20] reg [4:0] brinfos_1_bits_uop_fcn_op; // @[core.scala:203:20] reg brinfos_1_bits_uop_fp_val; // @[core.scala:203:20] reg [2:0] brinfos_1_bits_uop_fp_rm; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_uop_fp_typ; // @[core.scala:203:20] reg brinfos_1_bits_uop_xcpt_pf_if; // @[core.scala:203:20] reg brinfos_1_bits_uop_xcpt_ae_if; // @[core.scala:203:20] reg brinfos_1_bits_uop_xcpt_ma_if; // @[core.scala:203:20] reg brinfos_1_bits_uop_bp_debug_if; // @[core.scala:203:20] reg brinfos_1_bits_uop_bp_xcpt_if; // @[core.scala:203:20] reg [2:0] brinfos_1_bits_uop_debug_fsrc; // @[core.scala:203:20] reg [2:0] brinfos_1_bits_uop_debug_tsrc; // @[core.scala:203:20] reg brinfos_1_bits_mispredict; // @[core.scala:203:20] reg brinfos_1_bits_taken; // @[core.scala:203:20] reg [2:0] brinfos_1_bits_cfi_type; // @[core.scala:203:20] reg [1:0] brinfos_1_bits_pc_sel; // @[core.scala:203:20] reg [39:0] brinfos_1_bits_jalr_target; // @[core.scala:203:20] reg [20:0] brinfos_1_bits_target_offset; // @[core.scala:203:20] wire [20:0] _b2_target_offset_T_2 = brinfos_1_bits_target_offset; // @[Mux.scala:30:73] wire [11:0] b1_resolve_mask; // @[core.scala:210:19] assign io_ifu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b1_resolve_mask_0 = brupdate_b1_resolve_mask; // @[core.scala:50:7, :209:23] wire [11:0] b1_mispredict_mask; // @[core.scala:210:19] assign io_ifu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b1_mispredict_mask_0 = brupdate_b1_mispredict_mask; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_inst_0 = brupdate_b2_uop_inst; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_debug_inst_0 = brupdate_b2_uop_debug_inst; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_is_rvc_0 = brupdate_b2_uop_is_rvc; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_debug_pc_0 = brupdate_b2_uop_debug_pc; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iq_type_0_0 = brupdate_b2_uop_iq_type_0; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iq_type_0_0 = brupdate_b2_uop_iq_type_0; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iq_type_1_0 = brupdate_b2_uop_iq_type_1; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iq_type_1_0 = brupdate_b2_uop_iq_type_1; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iq_type_2_0 = brupdate_b2_uop_iq_type_2; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iq_type_2_0 = brupdate_b2_uop_iq_type_2; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iq_type_3_0 = brupdate_b2_uop_iq_type_3; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iq_type_3_0 = brupdate_b2_uop_iq_type_3; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fu_code_0_0 = brupdate_b2_uop_fu_code_0; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fu_code_0_0 = brupdate_b2_uop_fu_code_0; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fu_code_1_0 = brupdate_b2_uop_fu_code_1; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fu_code_1_0 = brupdate_b2_uop_fu_code_1; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fu_code_2_0 = brupdate_b2_uop_fu_code_2; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fu_code_2_0 = brupdate_b2_uop_fu_code_2; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fu_code_3_0 = brupdate_b2_uop_fu_code_3; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fu_code_3_0 = brupdate_b2_uop_fu_code_3; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fu_code_4_0 = brupdate_b2_uop_fu_code_4; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fu_code_4_0 = brupdate_b2_uop_fu_code_4; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fu_code_5_0 = brupdate_b2_uop_fu_code_5; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fu_code_5_0 = brupdate_b2_uop_fu_code_5; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fu_code_6_0 = brupdate_b2_uop_fu_code_6; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fu_code_6_0 = brupdate_b2_uop_fu_code_6; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fu_code_7_0 = brupdate_b2_uop_fu_code_7; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fu_code_7_0 = brupdate_b2_uop_fu_code_7; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fu_code_8_0 = brupdate_b2_uop_fu_code_8; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fu_code_8_0 = brupdate_b2_uop_fu_code_8; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fu_code_9_0 = brupdate_b2_uop_fu_code_9; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fu_code_9_0 = brupdate_b2_uop_fu_code_9; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iw_issued_0 = brupdate_b2_uop_iw_issued; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iw_issued_0 = brupdate_b2_uop_iw_issued; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iw_issued_partial_agen_0 = brupdate_b2_uop_iw_issued_partial_agen; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iw_issued_partial_agen_0 = brupdate_b2_uop_iw_issued_partial_agen; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iw_issued_partial_dgen_0 = brupdate_b2_uop_iw_issued_partial_dgen; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iw_issued_partial_dgen_0 = brupdate_b2_uop_iw_issued_partial_dgen; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iw_p1_speculative_child_0 = brupdate_b2_uop_iw_p1_speculative_child; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iw_p1_speculative_child_0 = brupdate_b2_uop_iw_p1_speculative_child; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iw_p2_speculative_child_0 = brupdate_b2_uop_iw_p2_speculative_child; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iw_p2_speculative_child_0 = brupdate_b2_uop_iw_p2_speculative_child; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iw_p1_bypass_hint_0 = brupdate_b2_uop_iw_p1_bypass_hint; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iw_p1_bypass_hint_0 = brupdate_b2_uop_iw_p1_bypass_hint; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iw_p2_bypass_hint_0 = brupdate_b2_uop_iw_p2_bypass_hint; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iw_p2_bypass_hint_0 = brupdate_b2_uop_iw_p2_bypass_hint; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_iw_p3_bypass_hint_0 = brupdate_b2_uop_iw_p3_bypass_hint; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_iw_p3_bypass_hint_0 = brupdate_b2_uop_iw_p3_bypass_hint; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_dis_col_sel_0 = brupdate_b2_uop_dis_col_sel; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_dis_col_sel_0 = brupdate_b2_uop_dis_col_sel; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_br_mask_0 = brupdate_b2_uop_br_mask; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_br_tag_0 = brupdate_b2_uop_br_tag; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_br_type_0 = brupdate_b2_uop_br_type; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_br_type_0 = brupdate_b2_uop_br_type; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_is_sfb_0 = brupdate_b2_uop_is_sfb; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_is_fence_0 = brupdate_b2_uop_is_fence; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_is_fencei_0 = brupdate_b2_uop_is_fencei; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_is_sfence_0 = brupdate_b2_uop_is_sfence; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_is_sfence_0 = brupdate_b2_uop_is_sfence; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_is_amo_0 = brupdate_b2_uop_is_amo; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_is_eret_0 = brupdate_b2_uop_is_eret; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_is_eret_0 = brupdate_b2_uop_is_eret; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_is_sys_pc2epc_0 = brupdate_b2_uop_is_sys_pc2epc; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_is_rocc_0 = brupdate_b2_uop_is_rocc; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_is_rocc_0 = brupdate_b2_uop_is_rocc; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_is_mov_0 = brupdate_b2_uop_is_mov; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_is_mov_0 = brupdate_b2_uop_is_mov; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_ftq_idx_0 = brupdate_b2_uop_ftq_idx; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_edge_inst_0 = brupdate_b2_uop_edge_inst; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_pc_lob_0 = brupdate_b2_uop_pc_lob; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_taken_0 = brupdate_b2_uop_taken; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_imm_rename_0 = brupdate_b2_uop_imm_rename; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_imm_rename_0 = brupdate_b2_uop_imm_rename; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_imm_sel_0 = brupdate_b2_uop_imm_sel; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_imm_sel_0 = brupdate_b2_uop_imm_sel; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_pimm_0 = brupdate_b2_uop_pimm; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_pimm_0 = brupdate_b2_uop_pimm; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_imm_packed_0 = brupdate_b2_uop_imm_packed; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_op1_sel_0 = brupdate_b2_uop_op1_sel; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_op1_sel_0 = brupdate_b2_uop_op1_sel; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_op2_sel_0 = brupdate_b2_uop_op2_sel; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_op2_sel_0 = brupdate_b2_uop_op2_sel; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_ldst_0 = brupdate_b2_uop_fp_ctrl_ldst; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_ldst_0 = brupdate_b2_uop_fp_ctrl_ldst; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_wen_0 = brupdate_b2_uop_fp_ctrl_wen; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_wen_0 = brupdate_b2_uop_fp_ctrl_wen; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_ren1_0 = brupdate_b2_uop_fp_ctrl_ren1; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_ren1_0 = brupdate_b2_uop_fp_ctrl_ren1; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_ren2_0 = brupdate_b2_uop_fp_ctrl_ren2; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_ren2_0 = brupdate_b2_uop_fp_ctrl_ren2; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_ren3_0 = brupdate_b2_uop_fp_ctrl_ren3; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_ren3_0 = brupdate_b2_uop_fp_ctrl_ren3; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_swap12_0 = brupdate_b2_uop_fp_ctrl_swap12; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_swap12_0 = brupdate_b2_uop_fp_ctrl_swap12; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_swap23_0 = brupdate_b2_uop_fp_ctrl_swap23; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_swap23_0 = brupdate_b2_uop_fp_ctrl_swap23; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = brupdate_b2_uop_fp_ctrl_typeTagIn; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = brupdate_b2_uop_fp_ctrl_typeTagIn; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = brupdate_b2_uop_fp_ctrl_typeTagOut; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = brupdate_b2_uop_fp_ctrl_typeTagOut; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_fromint_0 = brupdate_b2_uop_fp_ctrl_fromint; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_fromint_0 = brupdate_b2_uop_fp_ctrl_fromint; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_toint_0 = brupdate_b2_uop_fp_ctrl_toint; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_toint_0 = brupdate_b2_uop_fp_ctrl_toint; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_fastpipe_0 = brupdate_b2_uop_fp_ctrl_fastpipe; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_fastpipe_0 = brupdate_b2_uop_fp_ctrl_fastpipe; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_fma_0 = brupdate_b2_uop_fp_ctrl_fma; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_fma_0 = brupdate_b2_uop_fp_ctrl_fma; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_div_0 = brupdate_b2_uop_fp_ctrl_div; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_div_0 = brupdate_b2_uop_fp_ctrl_div; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_sqrt_0 = brupdate_b2_uop_fp_ctrl_sqrt; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_sqrt_0 = brupdate_b2_uop_fp_ctrl_sqrt; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_wflags_0 = brupdate_b2_uop_fp_ctrl_wflags; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_wflags_0 = brupdate_b2_uop_fp_ctrl_wflags; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_ctrl_vec_0 = brupdate_b2_uop_fp_ctrl_vec; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_ctrl_vec_0 = brupdate_b2_uop_fp_ctrl_vec; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_rob_idx_0 = brupdate_b2_uop_rob_idx; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_ldq_idx_0 = brupdate_b2_uop_ldq_idx; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_stq_idx_0 = brupdate_b2_uop_stq_idx; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_rxq_idx_0 = brupdate_b2_uop_rxq_idx; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_pdst_0 = brupdate_b2_uop_pdst; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_prs1_0 = brupdate_b2_uop_prs1; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_prs2_0 = brupdate_b2_uop_prs2; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_prs3_0 = brupdate_b2_uop_prs3; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_ppred_0 = brupdate_b2_uop_ppred; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_prs1_busy_0 = brupdate_b2_uop_prs1_busy; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_prs2_busy_0 = brupdate_b2_uop_prs2_busy; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_prs3_busy_0 = brupdate_b2_uop_prs3_busy; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_ppred_busy_0 = brupdate_b2_uop_ppred_busy; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_stale_pdst_0 = brupdate_b2_uop_stale_pdst; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_exception_0 = brupdate_b2_uop_exception; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_exc_cause_0 = brupdate_b2_uop_exc_cause; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_mem_cmd_0 = brupdate_b2_uop_mem_cmd; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_mem_size_0 = brupdate_b2_uop_mem_size; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_mem_signed_0 = brupdate_b2_uop_mem_signed; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_uses_ldq_0 = brupdate_b2_uop_uses_ldq; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_uses_stq_0 = brupdate_b2_uop_uses_stq; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_is_unique_0 = brupdate_b2_uop_is_unique; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_flush_on_commit_0 = brupdate_b2_uop_flush_on_commit; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_csr_cmd_0 = brupdate_b2_uop_csr_cmd; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_csr_cmd_0 = brupdate_b2_uop_csr_cmd; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_ldst_is_rs1_0 = brupdate_b2_uop_ldst_is_rs1; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_ldst_0 = brupdate_b2_uop_ldst; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_lrs1_0 = brupdate_b2_uop_lrs1; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_lrs2_0 = brupdate_b2_uop_lrs2; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_lrs3_0 = brupdate_b2_uop_lrs3; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_dst_rtype_0 = brupdate_b2_uop_dst_rtype; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_lrs1_rtype_0 = brupdate_b2_uop_lrs1_rtype; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_lrs2_rtype_0 = brupdate_b2_uop_lrs2_rtype; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_frs3_en_0 = brupdate_b2_uop_frs3_en; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fcn_dw_0 = brupdate_b2_uop_fcn_dw; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fcn_dw_0 = brupdate_b2_uop_fcn_dw; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fcn_op_0 = brupdate_b2_uop_fcn_op; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fcn_op_0 = brupdate_b2_uop_fcn_op; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_val_0 = brupdate_b2_uop_fp_val; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_rm_0 = brupdate_b2_uop_fp_rm; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_rm_0 = brupdate_b2_uop_fp_rm; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_fp_typ_0 = brupdate_b2_uop_fp_typ; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_fp_typ_0 = brupdate_b2_uop_fp_typ; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_xcpt_pf_if_0 = brupdate_b2_uop_xcpt_pf_if; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_xcpt_ae_if_0 = brupdate_b2_uop_xcpt_ae_if; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_xcpt_ma_if_0 = brupdate_b2_uop_xcpt_ma_if; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_bp_debug_if_0 = brupdate_b2_uop_bp_debug_if; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_bp_xcpt_if_0 = brupdate_b2_uop_bp_xcpt_if; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_debug_fsrc_0 = brupdate_b2_uop_debug_fsrc; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_uop_debug_tsrc_0 = brupdate_b2_uop_debug_tsrc; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_mispredict_0 = brupdate_b2_mispredict; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_taken_0 = brupdate_b2_taken; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_taken_0 = brupdate_b2_taken; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_cfi_type_0 = brupdate_b2_cfi_type; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_pc_sel_0 = brupdate_b2_pc_sel; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_jalr_target_0 = brupdate_b2_jalr_target; // @[core.scala:50:7, :209:23] assign io_ifu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset; // @[core.scala:50:7, :209:23] assign io_lsu_brupdate_b2_target_offset_0 = brupdate_b2_target_offset; // @[core.scala:50:7, :209:23] assign brupdate_b1_resolve_mask = b1_resolve_mask; // @[core.scala:209:23, :210:19] assign brupdate_b1_mispredict_mask = b1_mispredict_mask; // @[core.scala:209:23, :210:19] reg [31:0] b2_uop_inst; // @[core.scala:211:18] assign brupdate_b2_uop_inst = b2_uop_inst; // @[core.scala:209:23, :211:18] reg [31:0] b2_uop_debug_inst; // @[core.scala:211:18] assign brupdate_b2_uop_debug_inst = b2_uop_debug_inst; // @[core.scala:209:23, :211:18] reg b2_uop_is_rvc; // @[core.scala:211:18] assign brupdate_b2_uop_is_rvc = b2_uop_is_rvc; // @[core.scala:209:23, :211:18] reg [39:0] b2_uop_debug_pc; // @[core.scala:211:18] assign brupdate_b2_uop_debug_pc = b2_uop_debug_pc; // @[core.scala:209:23, :211:18] reg b2_uop_iq_type_0; // @[core.scala:211:18] assign brupdate_b2_uop_iq_type_0 = b2_uop_iq_type_0; // @[core.scala:209:23, :211:18] reg b2_uop_iq_type_1; // @[core.scala:211:18] assign brupdate_b2_uop_iq_type_1 = b2_uop_iq_type_1; // @[core.scala:209:23, :211:18] reg b2_uop_iq_type_2; // @[core.scala:211:18] assign brupdate_b2_uop_iq_type_2 = b2_uop_iq_type_2; // @[core.scala:209:23, :211:18] reg b2_uop_iq_type_3; // @[core.scala:211:18] assign brupdate_b2_uop_iq_type_3 = b2_uop_iq_type_3; // @[core.scala:209:23, :211:18] reg b2_uop_fu_code_0; // @[core.scala:211:18] assign brupdate_b2_uop_fu_code_0 = b2_uop_fu_code_0; // @[core.scala:209:23, :211:18] reg b2_uop_fu_code_1; // @[core.scala:211:18] assign brupdate_b2_uop_fu_code_1 = b2_uop_fu_code_1; // @[core.scala:209:23, :211:18] reg b2_uop_fu_code_2; // @[core.scala:211:18] assign brupdate_b2_uop_fu_code_2 = b2_uop_fu_code_2; // @[core.scala:209:23, :211:18] reg b2_uop_fu_code_3; // @[core.scala:211:18] assign brupdate_b2_uop_fu_code_3 = b2_uop_fu_code_3; // @[core.scala:209:23, :211:18] reg b2_uop_fu_code_4; // @[core.scala:211:18] assign brupdate_b2_uop_fu_code_4 = b2_uop_fu_code_4; // @[core.scala:209:23, :211:18] reg b2_uop_fu_code_5; // @[core.scala:211:18] assign brupdate_b2_uop_fu_code_5 = b2_uop_fu_code_5; // @[core.scala:209:23, :211:18] reg b2_uop_fu_code_6; // @[core.scala:211:18] assign brupdate_b2_uop_fu_code_6 = b2_uop_fu_code_6; // @[core.scala:209:23, :211:18] reg b2_uop_fu_code_7; // @[core.scala:211:18] assign brupdate_b2_uop_fu_code_7 = b2_uop_fu_code_7; // @[core.scala:209:23, :211:18] reg b2_uop_fu_code_8; // @[core.scala:211:18] assign brupdate_b2_uop_fu_code_8 = b2_uop_fu_code_8; // @[core.scala:209:23, :211:18] reg b2_uop_fu_code_9; // @[core.scala:211:18] assign brupdate_b2_uop_fu_code_9 = b2_uop_fu_code_9; // @[core.scala:209:23, :211:18] reg b2_uop_iw_issued; // @[core.scala:211:18] assign brupdate_b2_uop_iw_issued = b2_uop_iw_issued; // @[core.scala:209:23, :211:18] reg b2_uop_iw_issued_partial_agen; // @[core.scala:211:18] assign brupdate_b2_uop_iw_issued_partial_agen = b2_uop_iw_issued_partial_agen; // @[core.scala:209:23, :211:18] reg b2_uop_iw_issued_partial_dgen; // @[core.scala:211:18] assign brupdate_b2_uop_iw_issued_partial_dgen = b2_uop_iw_issued_partial_dgen; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_iw_p1_speculative_child; // @[core.scala:211:18] assign brupdate_b2_uop_iw_p1_speculative_child = b2_uop_iw_p1_speculative_child; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_iw_p2_speculative_child; // @[core.scala:211:18] assign brupdate_b2_uop_iw_p2_speculative_child = b2_uop_iw_p2_speculative_child; // @[core.scala:209:23, :211:18] reg b2_uop_iw_p1_bypass_hint; // @[core.scala:211:18] assign brupdate_b2_uop_iw_p1_bypass_hint = b2_uop_iw_p1_bypass_hint; // @[core.scala:209:23, :211:18] reg b2_uop_iw_p2_bypass_hint; // @[core.scala:211:18] assign brupdate_b2_uop_iw_p2_bypass_hint = b2_uop_iw_p2_bypass_hint; // @[core.scala:209:23, :211:18] reg b2_uop_iw_p3_bypass_hint; // @[core.scala:211:18] assign brupdate_b2_uop_iw_p3_bypass_hint = b2_uop_iw_p3_bypass_hint; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_dis_col_sel; // @[core.scala:211:18] assign brupdate_b2_uop_dis_col_sel = b2_uop_dis_col_sel; // @[core.scala:209:23, :211:18] reg [11:0] b2_uop_br_mask; // @[core.scala:211:18] assign brupdate_b2_uop_br_mask = b2_uop_br_mask; // @[core.scala:209:23, :211:18] reg [3:0] b2_uop_br_tag; // @[core.scala:211:18] assign brupdate_b2_uop_br_tag = b2_uop_br_tag; // @[core.scala:209:23, :211:18] reg [3:0] b2_uop_br_type; // @[core.scala:211:18] assign brupdate_b2_uop_br_type = b2_uop_br_type; // @[core.scala:209:23, :211:18] reg b2_uop_is_sfb; // @[core.scala:211:18] assign brupdate_b2_uop_is_sfb = b2_uop_is_sfb; // @[core.scala:209:23, :211:18] reg b2_uop_is_fence; // @[core.scala:211:18] assign brupdate_b2_uop_is_fence = b2_uop_is_fence; // @[core.scala:209:23, :211:18] reg b2_uop_is_fencei; // @[core.scala:211:18] assign brupdate_b2_uop_is_fencei = b2_uop_is_fencei; // @[core.scala:209:23, :211:18] reg b2_uop_is_sfence; // @[core.scala:211:18] assign brupdate_b2_uop_is_sfence = b2_uop_is_sfence; // @[core.scala:209:23, :211:18] reg b2_uop_is_amo; // @[core.scala:211:18] assign brupdate_b2_uop_is_amo = b2_uop_is_amo; // @[core.scala:209:23, :211:18] reg b2_uop_is_eret; // @[core.scala:211:18] assign brupdate_b2_uop_is_eret = b2_uop_is_eret; // @[core.scala:209:23, :211:18] reg b2_uop_is_sys_pc2epc; // @[core.scala:211:18] assign brupdate_b2_uop_is_sys_pc2epc = b2_uop_is_sys_pc2epc; // @[core.scala:209:23, :211:18] reg b2_uop_is_rocc; // @[core.scala:211:18] assign brupdate_b2_uop_is_rocc = b2_uop_is_rocc; // @[core.scala:209:23, :211:18] reg b2_uop_is_mov; // @[core.scala:211:18] assign brupdate_b2_uop_is_mov = b2_uop_is_mov; // @[core.scala:209:23, :211:18] reg [4:0] b2_uop_ftq_idx; // @[core.scala:211:18] assign brupdate_b2_uop_ftq_idx = b2_uop_ftq_idx; // @[core.scala:209:23, :211:18] reg b2_uop_edge_inst; // @[core.scala:211:18] assign brupdate_b2_uop_edge_inst = b2_uop_edge_inst; // @[core.scala:209:23, :211:18] reg [5:0] b2_uop_pc_lob; // @[core.scala:211:18] assign brupdate_b2_uop_pc_lob = b2_uop_pc_lob; // @[core.scala:209:23, :211:18] reg b2_uop_taken; // @[core.scala:211:18] assign brupdate_b2_uop_taken = b2_uop_taken; // @[core.scala:209:23, :211:18] reg b2_uop_imm_rename; // @[core.scala:211:18] assign brupdate_b2_uop_imm_rename = b2_uop_imm_rename; // @[core.scala:209:23, :211:18] reg [2:0] b2_uop_imm_sel; // @[core.scala:211:18] assign brupdate_b2_uop_imm_sel = b2_uop_imm_sel; // @[core.scala:209:23, :211:18] reg [4:0] b2_uop_pimm; // @[core.scala:211:18] assign brupdate_b2_uop_pimm = b2_uop_pimm; // @[core.scala:209:23, :211:18] reg [19:0] b2_uop_imm_packed; // @[core.scala:211:18] assign brupdate_b2_uop_imm_packed = b2_uop_imm_packed; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_op1_sel; // @[core.scala:211:18] assign brupdate_b2_uop_op1_sel = b2_uop_op1_sel; // @[core.scala:209:23, :211:18] reg [2:0] b2_uop_op2_sel; // @[core.scala:211:18] assign brupdate_b2_uop_op2_sel = b2_uop_op2_sel; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_ldst; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_ldst = b2_uop_fp_ctrl_ldst; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_wen; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_wen = b2_uop_fp_ctrl_wen; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_ren1; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_ren1 = b2_uop_fp_ctrl_ren1; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_ren2; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_ren2 = b2_uop_fp_ctrl_ren2; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_ren3; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_ren3 = b2_uop_fp_ctrl_ren3; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_swap12; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_swap12 = b2_uop_fp_ctrl_swap12; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_swap23; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_swap23 = b2_uop_fp_ctrl_swap23; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_fp_ctrl_typeTagIn; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_typeTagIn = b2_uop_fp_ctrl_typeTagIn; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_fp_ctrl_typeTagOut; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_typeTagOut = b2_uop_fp_ctrl_typeTagOut; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_fromint; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_fromint = b2_uop_fp_ctrl_fromint; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_toint; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_toint = b2_uop_fp_ctrl_toint; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_fastpipe; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_fastpipe = b2_uop_fp_ctrl_fastpipe; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_fma; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_fma = b2_uop_fp_ctrl_fma; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_div; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_div = b2_uop_fp_ctrl_div; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_sqrt; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_sqrt = b2_uop_fp_ctrl_sqrt; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_wflags; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_wflags = b2_uop_fp_ctrl_wflags; // @[core.scala:209:23, :211:18] reg b2_uop_fp_ctrl_vec; // @[core.scala:211:18] assign brupdate_b2_uop_fp_ctrl_vec = b2_uop_fp_ctrl_vec; // @[core.scala:209:23, :211:18] reg [5:0] b2_uop_rob_idx; // @[core.scala:211:18] assign brupdate_b2_uop_rob_idx = b2_uop_rob_idx; // @[core.scala:209:23, :211:18] reg [3:0] b2_uop_ldq_idx; // @[core.scala:211:18] assign brupdate_b2_uop_ldq_idx = b2_uop_ldq_idx; // @[core.scala:209:23, :211:18] reg [3:0] b2_uop_stq_idx; // @[core.scala:211:18] assign brupdate_b2_uop_stq_idx = b2_uop_stq_idx; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_rxq_idx; // @[core.scala:211:18] assign brupdate_b2_uop_rxq_idx = b2_uop_rxq_idx; // @[core.scala:209:23, :211:18] reg [6:0] b2_uop_pdst; // @[core.scala:211:18] assign brupdate_b2_uop_pdst = b2_uop_pdst; // @[core.scala:209:23, :211:18] reg [6:0] b2_uop_prs1; // @[core.scala:211:18] assign brupdate_b2_uop_prs1 = b2_uop_prs1; // @[core.scala:209:23, :211:18] reg [6:0] b2_uop_prs2; // @[core.scala:211:18] assign brupdate_b2_uop_prs2 = b2_uop_prs2; // @[core.scala:209:23, :211:18] reg [6:0] b2_uop_prs3; // @[core.scala:211:18] assign brupdate_b2_uop_prs3 = b2_uop_prs3; // @[core.scala:209:23, :211:18] reg [4:0] b2_uop_ppred; // @[core.scala:211:18] assign brupdate_b2_uop_ppred = b2_uop_ppred; // @[core.scala:209:23, :211:18] reg b2_uop_prs1_busy; // @[core.scala:211:18] assign brupdate_b2_uop_prs1_busy = b2_uop_prs1_busy; // @[core.scala:209:23, :211:18] reg b2_uop_prs2_busy; // @[core.scala:211:18] assign brupdate_b2_uop_prs2_busy = b2_uop_prs2_busy; // @[core.scala:209:23, :211:18] reg b2_uop_prs3_busy; // @[core.scala:211:18] assign brupdate_b2_uop_prs3_busy = b2_uop_prs3_busy; // @[core.scala:209:23, :211:18] reg b2_uop_ppred_busy; // @[core.scala:211:18] assign brupdate_b2_uop_ppred_busy = b2_uop_ppred_busy; // @[core.scala:209:23, :211:18] reg [6:0] b2_uop_stale_pdst; // @[core.scala:211:18] assign brupdate_b2_uop_stale_pdst = b2_uop_stale_pdst; // @[core.scala:209:23, :211:18] reg b2_uop_exception; // @[core.scala:211:18] assign brupdate_b2_uop_exception = b2_uop_exception; // @[core.scala:209:23, :211:18] reg [63:0] b2_uop_exc_cause; // @[core.scala:211:18] assign brupdate_b2_uop_exc_cause = b2_uop_exc_cause; // @[core.scala:209:23, :211:18] reg [4:0] b2_uop_mem_cmd; // @[core.scala:211:18] assign brupdate_b2_uop_mem_cmd = b2_uop_mem_cmd; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_mem_size; // @[core.scala:211:18] assign brupdate_b2_uop_mem_size = b2_uop_mem_size; // @[core.scala:209:23, :211:18] reg b2_uop_mem_signed; // @[core.scala:211:18] assign brupdate_b2_uop_mem_signed = b2_uop_mem_signed; // @[core.scala:209:23, :211:18] reg b2_uop_uses_ldq; // @[core.scala:211:18] assign brupdate_b2_uop_uses_ldq = b2_uop_uses_ldq; // @[core.scala:209:23, :211:18] reg b2_uop_uses_stq; // @[core.scala:211:18] assign brupdate_b2_uop_uses_stq = b2_uop_uses_stq; // @[core.scala:209:23, :211:18] reg b2_uop_is_unique; // @[core.scala:211:18] assign brupdate_b2_uop_is_unique = b2_uop_is_unique; // @[core.scala:209:23, :211:18] reg b2_uop_flush_on_commit; // @[core.scala:211:18] assign brupdate_b2_uop_flush_on_commit = b2_uop_flush_on_commit; // @[core.scala:209:23, :211:18] reg [2:0] b2_uop_csr_cmd; // @[core.scala:211:18] assign brupdate_b2_uop_csr_cmd = b2_uop_csr_cmd; // @[core.scala:209:23, :211:18] reg b2_uop_ldst_is_rs1; // @[core.scala:211:18] assign brupdate_b2_uop_ldst_is_rs1 = b2_uop_ldst_is_rs1; // @[core.scala:209:23, :211:18] reg [5:0] b2_uop_ldst; // @[core.scala:211:18] assign brupdate_b2_uop_ldst = b2_uop_ldst; // @[core.scala:209:23, :211:18] reg [5:0] b2_uop_lrs1; // @[core.scala:211:18] assign brupdate_b2_uop_lrs1 = b2_uop_lrs1; // @[core.scala:209:23, :211:18] reg [5:0] b2_uop_lrs2; // @[core.scala:211:18] assign brupdate_b2_uop_lrs2 = b2_uop_lrs2; // @[core.scala:209:23, :211:18] reg [5:0] b2_uop_lrs3; // @[core.scala:211:18] assign brupdate_b2_uop_lrs3 = b2_uop_lrs3; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_dst_rtype; // @[core.scala:211:18] assign brupdate_b2_uop_dst_rtype = b2_uop_dst_rtype; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_lrs1_rtype; // @[core.scala:211:18] assign brupdate_b2_uop_lrs1_rtype = b2_uop_lrs1_rtype; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_lrs2_rtype; // @[core.scala:211:18] assign brupdate_b2_uop_lrs2_rtype = b2_uop_lrs2_rtype; // @[core.scala:209:23, :211:18] reg b2_uop_frs3_en; // @[core.scala:211:18] assign brupdate_b2_uop_frs3_en = b2_uop_frs3_en; // @[core.scala:209:23, :211:18] reg b2_uop_fcn_dw; // @[core.scala:211:18] assign brupdate_b2_uop_fcn_dw = b2_uop_fcn_dw; // @[core.scala:209:23, :211:18] reg [4:0] b2_uop_fcn_op; // @[core.scala:211:18] assign brupdate_b2_uop_fcn_op = b2_uop_fcn_op; // @[core.scala:209:23, :211:18] reg b2_uop_fp_val; // @[core.scala:211:18] assign brupdate_b2_uop_fp_val = b2_uop_fp_val; // @[core.scala:209:23, :211:18] reg [2:0] b2_uop_fp_rm; // @[core.scala:211:18] assign brupdate_b2_uop_fp_rm = b2_uop_fp_rm; // @[core.scala:209:23, :211:18] reg [1:0] b2_uop_fp_typ; // @[core.scala:211:18] assign brupdate_b2_uop_fp_typ = b2_uop_fp_typ; // @[core.scala:209:23, :211:18] reg b2_uop_xcpt_pf_if; // @[core.scala:211:18] assign brupdate_b2_uop_xcpt_pf_if = b2_uop_xcpt_pf_if; // @[core.scala:209:23, :211:18] reg b2_uop_xcpt_ae_if; // @[core.scala:211:18] assign brupdate_b2_uop_xcpt_ae_if = b2_uop_xcpt_ae_if; // @[core.scala:209:23, :211:18] reg b2_uop_xcpt_ma_if; // @[core.scala:211:18] assign brupdate_b2_uop_xcpt_ma_if = b2_uop_xcpt_ma_if; // @[core.scala:209:23, :211:18] reg b2_uop_bp_debug_if; // @[core.scala:211:18] assign brupdate_b2_uop_bp_debug_if = b2_uop_bp_debug_if; // @[core.scala:209:23, :211:18] reg b2_uop_bp_xcpt_if; // @[core.scala:211:18] assign brupdate_b2_uop_bp_xcpt_if = b2_uop_bp_xcpt_if; // @[core.scala:209:23, :211:18] reg [2:0] b2_uop_debug_fsrc; // @[core.scala:211:18] assign brupdate_b2_uop_debug_fsrc = b2_uop_debug_fsrc; // @[core.scala:209:23, :211:18] reg [2:0] b2_uop_debug_tsrc; // @[core.scala:211:18] assign brupdate_b2_uop_debug_tsrc = b2_uop_debug_tsrc; // @[core.scala:209:23, :211:18] reg b2_mispredict; // @[core.scala:211:18] assign brupdate_b2_mispredict = b2_mispredict; // @[core.scala:209:23, :211:18] wire hits_1_1 = b2_mispredict; // @[Events.scala:13:25] reg b2_taken; // @[core.scala:211:18] assign brupdate_b2_taken = b2_taken; // @[core.scala:209:23, :211:18] reg [2:0] b2_cfi_type; // @[core.scala:211:18] assign brupdate_b2_cfi_type = b2_cfi_type; // @[core.scala:209:23, :211:18] reg [1:0] b2_pc_sel; // @[core.scala:211:18] assign brupdate_b2_pc_sel = b2_pc_sel; // @[core.scala:209:23, :211:18] reg [39:0] b2_jalr_target; // @[core.scala:211:18] assign brupdate_b2_jalr_target = b2_jalr_target; // @[core.scala:209:23, :211:18] reg [20:0] b2_target_offset; // @[core.scala:211:18] assign brupdate_b2_target_offset = b2_target_offset; // @[core.scala:209:23, :211:18] wire [11:0] _brinfos_0_bits_out_uop_br_mask_T_1; // @[util.scala:97:21] wire brinfos_0_bits_out_uop_iq_type_0; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_iq_type_1; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_iq_type_2; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_iq_type_3; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fu_code_0; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fu_code_1; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fu_code_2; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fu_code_3; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fu_code_4; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fu_code_5; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fu_code_6; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fu_code_7; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fu_code_8; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fu_code_9; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_ldst; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_wen; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_ren1; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_ren2; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_ren3; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_swap12; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_swap23; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_fromint; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_toint; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_fastpipe; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_fma; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_div; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_sqrt; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_wflags; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_ctrl_vec; // @[util.scala:109:23] wire [31:0] brinfos_0_bits_out_uop_inst; // @[util.scala:109:23] wire [31:0] brinfos_0_bits_out_uop_debug_inst; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_is_rvc; // @[util.scala:109:23] wire [39:0] brinfos_0_bits_out_uop_debug_pc; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_iw_issued; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_iw_issued_partial_agen; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_iw_issued_partial_dgen; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_iw_p1_speculative_child; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_iw_p2_speculative_child; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_iw_p1_bypass_hint; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_iw_p2_bypass_hint; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_iw_p3_bypass_hint; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_dis_col_sel; // @[util.scala:109:23] wire [11:0] brinfos_0_bits_out_uop_br_mask; // @[util.scala:109:23] wire [3:0] brinfos_0_bits_out_uop_br_tag; // @[util.scala:109:23] wire [3:0] brinfos_0_bits_out_uop_br_type; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_is_sfb; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_is_fence; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_is_fencei; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_is_sfence; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_is_amo; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_is_eret; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_is_sys_pc2epc; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_is_rocc; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_is_mov; // @[util.scala:109:23] wire [4:0] brinfos_0_bits_out_uop_ftq_idx; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_edge_inst; // @[util.scala:109:23] wire [5:0] brinfos_0_bits_out_uop_pc_lob; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_taken; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_imm_rename; // @[util.scala:109:23] wire [2:0] brinfos_0_bits_out_uop_imm_sel; // @[util.scala:109:23] wire [4:0] brinfos_0_bits_out_uop_pimm; // @[util.scala:109:23] wire [19:0] brinfos_0_bits_out_uop_imm_packed; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_op1_sel; // @[util.scala:109:23] wire [2:0] brinfos_0_bits_out_uop_op2_sel; // @[util.scala:109:23] wire [5:0] brinfos_0_bits_out_uop_rob_idx; // @[util.scala:109:23] wire [3:0] brinfos_0_bits_out_uop_ldq_idx; // @[util.scala:109:23] wire [3:0] brinfos_0_bits_out_uop_stq_idx; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_rxq_idx; // @[util.scala:109:23] wire [6:0] brinfos_0_bits_out_uop_pdst; // @[util.scala:109:23] wire [6:0] brinfos_0_bits_out_uop_prs1; // @[util.scala:109:23] wire [6:0] brinfos_0_bits_out_uop_prs2; // @[util.scala:109:23] wire [6:0] brinfos_0_bits_out_uop_prs3; // @[util.scala:109:23] wire [4:0] brinfos_0_bits_out_uop_ppred; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_prs1_busy; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_prs2_busy; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_prs3_busy; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_ppred_busy; // @[util.scala:109:23] wire [6:0] brinfos_0_bits_out_uop_stale_pdst; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_exception; // @[util.scala:109:23] wire [63:0] brinfos_0_bits_out_uop_exc_cause; // @[util.scala:109:23] wire [4:0] brinfos_0_bits_out_uop_mem_cmd; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_mem_size; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_mem_signed; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_uses_ldq; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_uses_stq; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_is_unique; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_flush_on_commit; // @[util.scala:109:23] wire [2:0] brinfos_0_bits_out_uop_csr_cmd; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_ldst_is_rs1; // @[util.scala:109:23] wire [5:0] brinfos_0_bits_out_uop_ldst; // @[util.scala:109:23] wire [5:0] brinfos_0_bits_out_uop_lrs1; // @[util.scala:109:23] wire [5:0] brinfos_0_bits_out_uop_lrs2; // @[util.scala:109:23] wire [5:0] brinfos_0_bits_out_uop_lrs3; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_dst_rtype; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_lrs1_rtype; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_lrs2_rtype; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_frs3_en; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fcn_dw; // @[util.scala:109:23] wire [4:0] brinfos_0_bits_out_uop_fcn_op; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_fp_val; // @[util.scala:109:23] wire [2:0] brinfos_0_bits_out_uop_fp_rm; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_uop_fp_typ; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_xcpt_pf_if; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_xcpt_ae_if; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_xcpt_ma_if; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_bp_debug_if; // @[util.scala:109:23] wire brinfos_0_bits_out_uop_bp_xcpt_if; // @[util.scala:109:23] wire [2:0] brinfos_0_bits_out_uop_debug_fsrc; // @[util.scala:109:23] wire [2:0] brinfos_0_bits_out_uop_debug_tsrc; // @[util.scala:109:23] wire brinfos_0_bits_out_mispredict; // @[util.scala:109:23] wire brinfos_0_bits_out_taken; // @[util.scala:109:23] wire [2:0] brinfos_0_bits_out_cfi_type; // @[util.scala:109:23] wire [1:0] brinfos_0_bits_out_pc_sel; // @[util.scala:109:23] wire [39:0] brinfos_0_bits_out_jalr_target; // @[util.scala:109:23] wire [20:0] brinfos_0_bits_out_target_offset; // @[util.scala:109:23] wire [11:0] _brinfos_0_bits_out_uop_br_mask_T = ~brupdate_b1_resolve_mask; // @[util.scala:97:23] assign _brinfos_0_bits_out_uop_br_mask_T_1 = _alu_exe_unit_0_io_brinfo_bits_uop_br_mask & _brinfos_0_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign brinfos_0_bits_out_uop_br_mask = _brinfos_0_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] wire _brinfos_0_valid_T = ~_rob_io_flush_valid; // @[core.scala:159:32, :218:37] wire _brinfos_0_valid_T_1 = _alu_exe_unit_0_io_brinfo_valid & _brinfos_0_valid_T; // @[core.scala:92:11, :218:{34,37}] reg brinfos_0_valid_REG; // @[core.scala:218:95] wire [11:0] _brinfos_0_valid_T_2 = brupdate_b1_mispredict_mask & _alu_exe_unit_0_io_brinfo_bits_uop_br_mask; // @[util.scala:126:51] wire _brinfos_0_valid_T_3 = |_brinfos_0_valid_T_2; // @[util.scala:126:{51,59}] wire _brinfos_0_valid_T_4 = _brinfos_0_valid_T_3 | brinfos_0_valid_REG; // @[util.scala:61:61, :126:59] wire _brinfos_0_valid_T_5 = ~_brinfos_0_valid_T_4; // @[util.scala:61:61] wire _brinfos_0_valid_T_6 = _brinfos_0_valid_T_1 & _brinfos_0_valid_T_5; // @[core.scala:218:{34,57,60}] wire [11:0] _brinfos_1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21] wire brinfos_1_bits_out_uop_iq_type_0; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_iq_type_1; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_iq_type_2; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_iq_type_3; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fu_code_0; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fu_code_1; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fu_code_2; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fu_code_3; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fu_code_4; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fu_code_5; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fu_code_6; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fu_code_7; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fu_code_8; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fu_code_9; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_ldst; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_wen; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_ren1; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_ren2; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_ren3; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_swap12; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_swap23; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_fp_ctrl_typeTagIn; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_fp_ctrl_typeTagOut; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_fromint; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_toint; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_fastpipe; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_fma; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_div; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_sqrt; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_wflags; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_ctrl_vec; // @[util.scala:109:23] wire [31:0] brinfos_1_bits_out_uop_inst; // @[util.scala:109:23] wire [31:0] brinfos_1_bits_out_uop_debug_inst; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_is_rvc; // @[util.scala:109:23] wire [39:0] brinfos_1_bits_out_uop_debug_pc; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_iw_issued; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_iw_issued_partial_agen; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_iw_issued_partial_dgen; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_iw_p1_speculative_child; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_iw_p2_speculative_child; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_iw_p1_bypass_hint; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_iw_p2_bypass_hint; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_iw_p3_bypass_hint; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_dis_col_sel; // @[util.scala:109:23] wire [11:0] brinfos_1_bits_out_uop_br_mask; // @[util.scala:109:23] wire [3:0] brinfos_1_bits_out_uop_br_tag; // @[util.scala:109:23] wire [3:0] brinfos_1_bits_out_uop_br_type; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_is_sfb; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_is_fence; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_is_fencei; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_is_sfence; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_is_amo; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_is_eret; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_is_sys_pc2epc; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_is_rocc; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_is_mov; // @[util.scala:109:23] wire [4:0] brinfos_1_bits_out_uop_ftq_idx; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_edge_inst; // @[util.scala:109:23] wire [5:0] brinfos_1_bits_out_uop_pc_lob; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_taken; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_imm_rename; // @[util.scala:109:23] wire [2:0] brinfos_1_bits_out_uop_imm_sel; // @[util.scala:109:23] wire [4:0] brinfos_1_bits_out_uop_pimm; // @[util.scala:109:23] wire [19:0] brinfos_1_bits_out_uop_imm_packed; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_op1_sel; // @[util.scala:109:23] wire [2:0] brinfos_1_bits_out_uop_op2_sel; // @[util.scala:109:23] wire [5:0] brinfos_1_bits_out_uop_rob_idx; // @[util.scala:109:23] wire [3:0] brinfos_1_bits_out_uop_ldq_idx; // @[util.scala:109:23] wire [3:0] brinfos_1_bits_out_uop_stq_idx; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_rxq_idx; // @[util.scala:109:23] wire [6:0] brinfos_1_bits_out_uop_pdst; // @[util.scala:109:23] wire [6:0] brinfos_1_bits_out_uop_prs1; // @[util.scala:109:23] wire [6:0] brinfos_1_bits_out_uop_prs2; // @[util.scala:109:23] wire [6:0] brinfos_1_bits_out_uop_prs3; // @[util.scala:109:23] wire [4:0] brinfos_1_bits_out_uop_ppred; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_prs1_busy; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_prs2_busy; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_prs3_busy; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_ppred_busy; // @[util.scala:109:23] wire [6:0] brinfos_1_bits_out_uop_stale_pdst; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_exception; // @[util.scala:109:23] wire [63:0] brinfos_1_bits_out_uop_exc_cause; // @[util.scala:109:23] wire [4:0] brinfos_1_bits_out_uop_mem_cmd; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_mem_size; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_mem_signed; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_uses_ldq; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_uses_stq; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_is_unique; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_flush_on_commit; // @[util.scala:109:23] wire [2:0] brinfos_1_bits_out_uop_csr_cmd; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_ldst_is_rs1; // @[util.scala:109:23] wire [5:0] brinfos_1_bits_out_uop_ldst; // @[util.scala:109:23] wire [5:0] brinfos_1_bits_out_uop_lrs1; // @[util.scala:109:23] wire [5:0] brinfos_1_bits_out_uop_lrs2; // @[util.scala:109:23] wire [5:0] brinfos_1_bits_out_uop_lrs3; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_dst_rtype; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_lrs1_rtype; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_lrs2_rtype; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_frs3_en; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fcn_dw; // @[util.scala:109:23] wire [4:0] brinfos_1_bits_out_uop_fcn_op; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_fp_val; // @[util.scala:109:23] wire [2:0] brinfos_1_bits_out_uop_fp_rm; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_uop_fp_typ; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_xcpt_pf_if; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_xcpt_ae_if; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_xcpt_ma_if; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_bp_debug_if; // @[util.scala:109:23] wire brinfos_1_bits_out_uop_bp_xcpt_if; // @[util.scala:109:23] wire [2:0] brinfos_1_bits_out_uop_debug_fsrc; // @[util.scala:109:23] wire [2:0] brinfos_1_bits_out_uop_debug_tsrc; // @[util.scala:109:23] wire brinfos_1_bits_out_mispredict; // @[util.scala:109:23] wire brinfos_1_bits_out_taken; // @[util.scala:109:23] wire [2:0] brinfos_1_bits_out_cfi_type; // @[util.scala:109:23] wire [1:0] brinfos_1_bits_out_pc_sel; // @[util.scala:109:23] wire [39:0] brinfos_1_bits_out_jalr_target; // @[util.scala:109:23] wire [20:0] brinfos_1_bits_out_target_offset; // @[util.scala:109:23] wire [11:0] _brinfos_1_bits_out_uop_br_mask_T = ~brupdate_b1_resolve_mask; // @[util.scala:97:23] assign _brinfos_1_bits_out_uop_br_mask_T_1 = _alu_exe_unit_1_io_brinfo_bits_uop_br_mask & _brinfos_1_bits_out_uop_br_mask_T; // @[util.scala:97:{21,23}] assign brinfos_1_bits_out_uop_br_mask = _brinfos_1_bits_out_uop_br_mask_T_1; // @[util.scala:97:21, :109:23] wire _brinfos_1_valid_T = ~_rob_io_flush_valid; // @[core.scala:159:32, :218:37] wire _brinfos_1_valid_T_1 = _alu_exe_unit_1_io_brinfo_valid & _brinfos_1_valid_T; // @[core.scala:92:11, :218:{34,37}] reg brinfos_1_valid_REG; // @[core.scala:218:95] wire [11:0] _brinfos_1_valid_T_2 = brupdate_b1_mispredict_mask & _alu_exe_unit_1_io_brinfo_bits_uop_br_mask; // @[util.scala:126:51] wire _brinfos_1_valid_T_3 = |_brinfos_1_valid_T_2; // @[util.scala:126:{51,59}] wire _brinfos_1_valid_T_4 = _brinfos_1_valid_T_3 | brinfos_1_valid_REG; // @[util.scala:61:61, :126:59] wire _brinfos_1_valid_T_5 = ~_brinfos_1_valid_T_4; // @[util.scala:61:61] wire _brinfos_1_valid_T_6 = _brinfos_1_valid_T_1 & _brinfos_1_valid_T_5; // @[core.scala:218:{34,57,60}] wire [15:0] _GEN = {12'h0, brinfos_0_bits_uop_br_tag}; // @[core.scala:203:20, :220:47] wire [15:0] _b1_resolve_mask_T = {15'h0, brinfos_0_valid} << _GEN; // @[core.scala:203:20, :220:47] wire [15:0] _GEN_0 = {12'h0, brinfos_1_bits_uop_br_tag}; // @[core.scala:203:20, :220:47] wire [15:0] _b1_resolve_mask_T_1 = {15'h0, brinfos_1_valid} << _GEN_0; // @[core.scala:203:20, :220:47] wire [15:0] _b1_resolve_mask_T_2 = _b1_resolve_mask_T | _b1_resolve_mask_T_1; // @[core.scala:220:{47,77}] assign b1_resolve_mask = _b1_resolve_mask_T_2[11:0]; // @[core.scala:210:19, :220:{19,77}] wire _GEN_1 = brinfos_0_valid & brinfos_0_bits_mispredict; // @[core.scala:203:20, :221:51] wire _b1_mispredict_mask_T; // @[core.scala:221:51] assign _b1_mispredict_mask_T = _GEN_1; // @[core.scala:221:51] wire _live_brinfos_T; // @[core.scala:224:54] assign _live_brinfos_T = _GEN_1; // @[core.scala:221:51, :224:54] wire [15:0] _b1_mispredict_mask_T_1 = {15'h0, _b1_mispredict_mask_T} << _GEN; // @[core.scala:220:47, :221:{51,73}] wire _GEN_2 = brinfos_1_valid & brinfos_1_bits_mispredict; // @[core.scala:203:20, :221:51] wire _b1_mispredict_mask_T_2; // @[core.scala:221:51] assign _b1_mispredict_mask_T_2 = _GEN_2; // @[core.scala:221:51] wire _live_brinfos_T_5; // @[core.scala:224:54] assign _live_brinfos_T_5 = _GEN_2; // @[core.scala:221:51, :224:54] wire [15:0] _b1_mispredict_mask_T_3 = {15'h0, _b1_mispredict_mask_T_2} << _GEN_0; // @[core.scala:220:47, :221:{51,73}] wire [15:0] _b1_mispredict_mask_T_4 = _b1_mispredict_mask_T_1 | _b1_mispredict_mask_T_3; // @[core.scala:221:{73,103}] assign b1_mispredict_mask = _b1_mispredict_mask_T_4[11:0]; // @[core.scala:210:19, :221:{22,103}] reg live_brinfos_REG; // @[core.scala:224:114] wire [11:0] _live_brinfos_T_1 = brupdate_b1_mispredict_mask & brinfos_0_bits_uop_br_mask; // @[util.scala:126:51] wire _live_brinfos_T_2 = |_live_brinfos_T_1; // @[util.scala:126:{51,59}] wire _live_brinfos_T_3 = _live_brinfos_T_2 | live_brinfos_REG; // @[util.scala:61:61, :126:59] wire _live_brinfos_T_4 = ~_live_brinfos_T_3; // @[util.scala:61:61] wire live_brinfos_0 = _live_brinfos_T & _live_brinfos_T_4; // @[core.scala:224:{54,76,79}] reg live_brinfos_REG_1; // @[core.scala:224:114] wire [11:0] _live_brinfos_T_6 = brupdate_b1_mispredict_mask & brinfos_1_bits_uop_br_mask; // @[util.scala:126:51] wire _live_brinfos_T_7 = |_live_brinfos_T_6; // @[util.scala:126:{51,59}] wire _live_brinfos_T_8 = _live_brinfos_T_7 | live_brinfos_REG_1; // @[util.scala:61:61, :126:59] wire _live_brinfos_T_9 = ~_live_brinfos_T_8; // @[util.scala:61:61] wire live_brinfos_1 = _live_brinfos_T_5 & _live_brinfos_T_9; // @[core.scala:224:{54,76,79}] wire mispredict_val = live_brinfos_0 | live_brinfos_1; // @[core.scala:224:76, :225:48] wire mispredict_pc_req_valid = mispredict_val; // @[core.scala:225:48, :538:31] wire [2:0] _b2_cfi_type_T = live_brinfos_0 ? brinfos_0_bits_cfi_type : 3'h0; // @[Mux.scala:30:73] wire [2:0] _b2_cfi_type_T_1 = live_brinfos_1 ? brinfos_1_bits_cfi_type : 3'h0; // @[Mux.scala:30:73] wire [2:0] _b2_cfi_type_T_2 = _b2_cfi_type_T | _b2_cfi_type_T_1; // @[Mux.scala:30:73] wire [2:0] _b2_cfi_type_WIRE = _b2_cfi_type_T_2; // @[Mux.scala:30:73] wire _b2_taken_T = live_brinfos_0 & brinfos_0_bits_taken; // @[Mux.scala:30:73] wire _b2_taken_T_1 = live_brinfos_1 & brinfos_1_bits_taken; // @[Mux.scala:30:73] wire _b2_taken_T_2 = _b2_taken_T | _b2_taken_T_1; // @[Mux.scala:30:73] wire _b2_taken_WIRE = _b2_taken_T_2; // @[Mux.scala:30:73] wire [1:0] _b2_pc_sel_T = live_brinfos_0 ? brinfos_0_bits_pc_sel : 2'h0; // @[Mux.scala:30:73] wire [1:0] _b2_pc_sel_T_1 = live_brinfos_1 ? brinfos_1_bits_pc_sel : 2'h0; // @[Mux.scala:30:73] wire [1:0] _b2_pc_sel_T_2 = _b2_pc_sel_T | _b2_pc_sel_T_1; // @[Mux.scala:30:73] wire [1:0] _b2_pc_sel_WIRE = _b2_pc_sel_T_2; // @[Mux.scala:30:73] wire [31:0] _b2_uop_T_inst = live_brinfos_0 ? brinfos_0_bits_uop_inst : brinfos_1_bits_uop_inst; // @[Mux.scala:50:70] wire [31:0] _b2_uop_T_debug_inst = live_brinfos_0 ? brinfos_0_bits_uop_debug_inst : brinfos_1_bits_uop_debug_inst; // @[Mux.scala:50:70] wire _b2_uop_T_is_rvc = live_brinfos_0 ? brinfos_0_bits_uop_is_rvc : brinfos_1_bits_uop_is_rvc; // @[Mux.scala:50:70] wire [39:0] _b2_uop_T_debug_pc = live_brinfos_0 ? brinfos_0_bits_uop_debug_pc : brinfos_1_bits_uop_debug_pc; // @[Mux.scala:50:70] wire _b2_uop_T_iq_type_0 = live_brinfos_0 ? brinfos_0_bits_uop_iq_type_0 : brinfos_1_bits_uop_iq_type_0; // @[Mux.scala:50:70] wire _b2_uop_T_iq_type_1 = live_brinfos_0 ? brinfos_0_bits_uop_iq_type_1 : brinfos_1_bits_uop_iq_type_1; // @[Mux.scala:50:70] wire _b2_uop_T_iq_type_2 = live_brinfos_0 ? brinfos_0_bits_uop_iq_type_2 : brinfos_1_bits_uop_iq_type_2; // @[Mux.scala:50:70] wire _b2_uop_T_iq_type_3 = live_brinfos_0 ? brinfos_0_bits_uop_iq_type_3 : brinfos_1_bits_uop_iq_type_3; // @[Mux.scala:50:70] wire _b2_uop_T_fu_code_0 = live_brinfos_0 ? brinfos_0_bits_uop_fu_code_0 : brinfos_1_bits_uop_fu_code_0; // @[Mux.scala:50:70] wire _b2_uop_T_fu_code_1 = live_brinfos_0 ? brinfos_0_bits_uop_fu_code_1 : brinfos_1_bits_uop_fu_code_1; // @[Mux.scala:50:70] wire _b2_uop_T_fu_code_2 = live_brinfos_0 ? brinfos_0_bits_uop_fu_code_2 : brinfos_1_bits_uop_fu_code_2; // @[Mux.scala:50:70] wire _b2_uop_T_fu_code_3 = live_brinfos_0 ? brinfos_0_bits_uop_fu_code_3 : brinfos_1_bits_uop_fu_code_3; // @[Mux.scala:50:70] wire _b2_uop_T_fu_code_4 = live_brinfos_0 ? brinfos_0_bits_uop_fu_code_4 : brinfos_1_bits_uop_fu_code_4; // @[Mux.scala:50:70] wire _b2_uop_T_fu_code_5 = live_brinfos_0 ? brinfos_0_bits_uop_fu_code_5 : brinfos_1_bits_uop_fu_code_5; // @[Mux.scala:50:70] wire _b2_uop_T_fu_code_6 = live_brinfos_0 ? brinfos_0_bits_uop_fu_code_6 : brinfos_1_bits_uop_fu_code_6; // @[Mux.scala:50:70] wire _b2_uop_T_fu_code_7 = live_brinfos_0 ? brinfos_0_bits_uop_fu_code_7 : brinfos_1_bits_uop_fu_code_7; // @[Mux.scala:50:70] wire _b2_uop_T_fu_code_8 = live_brinfos_0 ? brinfos_0_bits_uop_fu_code_8 : brinfos_1_bits_uop_fu_code_8; // @[Mux.scala:50:70] wire _b2_uop_T_fu_code_9 = live_brinfos_0 ? brinfos_0_bits_uop_fu_code_9 : brinfos_1_bits_uop_fu_code_9; // @[Mux.scala:50:70] wire _b2_uop_T_iw_issued = live_brinfos_0 ? brinfos_0_bits_uop_iw_issued : brinfos_1_bits_uop_iw_issued; // @[Mux.scala:50:70] wire _b2_uop_T_iw_issued_partial_agen = live_brinfos_0 ? brinfos_0_bits_uop_iw_issued_partial_agen : brinfos_1_bits_uop_iw_issued_partial_agen; // @[Mux.scala:50:70] wire _b2_uop_T_iw_issued_partial_dgen = live_brinfos_0 ? brinfos_0_bits_uop_iw_issued_partial_dgen : brinfos_1_bits_uop_iw_issued_partial_dgen; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_iw_p1_speculative_child = live_brinfos_0 ? brinfos_0_bits_uop_iw_p1_speculative_child : brinfos_1_bits_uop_iw_p1_speculative_child; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_iw_p2_speculative_child = live_brinfos_0 ? brinfos_0_bits_uop_iw_p2_speculative_child : brinfos_1_bits_uop_iw_p2_speculative_child; // @[Mux.scala:50:70] wire _b2_uop_T_iw_p1_bypass_hint = live_brinfos_0 ? brinfos_0_bits_uop_iw_p1_bypass_hint : brinfos_1_bits_uop_iw_p1_bypass_hint; // @[Mux.scala:50:70] wire _b2_uop_T_iw_p2_bypass_hint = live_brinfos_0 ? brinfos_0_bits_uop_iw_p2_bypass_hint : brinfos_1_bits_uop_iw_p2_bypass_hint; // @[Mux.scala:50:70] wire _b2_uop_T_iw_p3_bypass_hint = live_brinfos_0 ? brinfos_0_bits_uop_iw_p3_bypass_hint : brinfos_1_bits_uop_iw_p3_bypass_hint; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_dis_col_sel = live_brinfos_0 ? brinfos_0_bits_uop_dis_col_sel : brinfos_1_bits_uop_dis_col_sel; // @[Mux.scala:50:70] wire [11:0] _b2_uop_T_br_mask = live_brinfos_0 ? brinfos_0_bits_uop_br_mask : brinfos_1_bits_uop_br_mask; // @[Mux.scala:50:70] wire [3:0] _b2_uop_T_br_tag = live_brinfos_0 ? brinfos_0_bits_uop_br_tag : brinfos_1_bits_uop_br_tag; // @[Mux.scala:50:70] wire [3:0] _b2_uop_T_br_type = live_brinfos_0 ? brinfos_0_bits_uop_br_type : brinfos_1_bits_uop_br_type; // @[Mux.scala:50:70] wire _b2_uop_T_is_sfb = live_brinfos_0 ? brinfos_0_bits_uop_is_sfb : brinfos_1_bits_uop_is_sfb; // @[Mux.scala:50:70] wire _b2_uop_T_is_fence = live_brinfos_0 ? brinfos_0_bits_uop_is_fence : brinfos_1_bits_uop_is_fence; // @[Mux.scala:50:70] wire _b2_uop_T_is_fencei = live_brinfos_0 ? brinfos_0_bits_uop_is_fencei : brinfos_1_bits_uop_is_fencei; // @[Mux.scala:50:70] wire _b2_uop_T_is_sfence = live_brinfos_0 ? brinfos_0_bits_uop_is_sfence : brinfos_1_bits_uop_is_sfence; // @[Mux.scala:50:70] wire _b2_uop_T_is_amo = live_brinfos_0 ? brinfos_0_bits_uop_is_amo : brinfos_1_bits_uop_is_amo; // @[Mux.scala:50:70] wire _b2_uop_T_is_eret = live_brinfos_0 ? brinfos_0_bits_uop_is_eret : brinfos_1_bits_uop_is_eret; // @[Mux.scala:50:70] wire _b2_uop_T_is_sys_pc2epc = live_brinfos_0 ? brinfos_0_bits_uop_is_sys_pc2epc : brinfos_1_bits_uop_is_sys_pc2epc; // @[Mux.scala:50:70] wire _b2_uop_T_is_rocc = live_brinfos_0 ? brinfos_0_bits_uop_is_rocc : brinfos_1_bits_uop_is_rocc; // @[Mux.scala:50:70] wire _b2_uop_T_is_mov = live_brinfos_0 ? brinfos_0_bits_uop_is_mov : brinfos_1_bits_uop_is_mov; // @[Mux.scala:50:70] wire [4:0] _b2_uop_T_ftq_idx = live_brinfos_0 ? brinfos_0_bits_uop_ftq_idx : brinfos_1_bits_uop_ftq_idx; // @[Mux.scala:50:70] wire _b2_uop_T_edge_inst = live_brinfos_0 ? brinfos_0_bits_uop_edge_inst : brinfos_1_bits_uop_edge_inst; // @[Mux.scala:50:70] wire [5:0] _b2_uop_T_pc_lob = live_brinfos_0 ? brinfos_0_bits_uop_pc_lob : brinfos_1_bits_uop_pc_lob; // @[Mux.scala:50:70] wire _b2_uop_T_taken = live_brinfos_0 ? brinfos_0_bits_uop_taken : brinfos_1_bits_uop_taken; // @[Mux.scala:50:70] wire _b2_uop_T_imm_rename = live_brinfos_0 ? brinfos_0_bits_uop_imm_rename : brinfos_1_bits_uop_imm_rename; // @[Mux.scala:50:70] wire [2:0] _b2_uop_T_imm_sel = live_brinfos_0 ? brinfos_0_bits_uop_imm_sel : brinfos_1_bits_uop_imm_sel; // @[Mux.scala:50:70] wire [4:0] _b2_uop_T_pimm = live_brinfos_0 ? brinfos_0_bits_uop_pimm : brinfos_1_bits_uop_pimm; // @[Mux.scala:50:70] wire [19:0] _b2_uop_T_imm_packed = live_brinfos_0 ? brinfos_0_bits_uop_imm_packed : brinfos_1_bits_uop_imm_packed; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_op1_sel = live_brinfos_0 ? brinfos_0_bits_uop_op1_sel : brinfos_1_bits_uop_op1_sel; // @[Mux.scala:50:70] wire [2:0] _b2_uop_T_op2_sel = live_brinfos_0 ? brinfos_0_bits_uop_op2_sel : brinfos_1_bits_uop_op2_sel; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_ldst = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_ldst : brinfos_1_bits_uop_fp_ctrl_ldst; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_wen = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_wen : brinfos_1_bits_uop_fp_ctrl_wen; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_ren1 = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_ren1 : brinfos_1_bits_uop_fp_ctrl_ren1; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_ren2 = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_ren2 : brinfos_1_bits_uop_fp_ctrl_ren2; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_ren3 = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_ren3 : brinfos_1_bits_uop_fp_ctrl_ren3; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_swap12 = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_swap12 : brinfos_1_bits_uop_fp_ctrl_swap12; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_swap23 = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_swap23 : brinfos_1_bits_uop_fp_ctrl_swap23; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_fp_ctrl_typeTagIn = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_typeTagIn : brinfos_1_bits_uop_fp_ctrl_typeTagIn; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_fp_ctrl_typeTagOut = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_typeTagOut : brinfos_1_bits_uop_fp_ctrl_typeTagOut; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_fromint = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_fromint : brinfos_1_bits_uop_fp_ctrl_fromint; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_toint = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_toint : brinfos_1_bits_uop_fp_ctrl_toint; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_fastpipe = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_fastpipe : brinfos_1_bits_uop_fp_ctrl_fastpipe; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_fma = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_fma : brinfos_1_bits_uop_fp_ctrl_fma; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_div = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_div : brinfos_1_bits_uop_fp_ctrl_div; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_sqrt = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_sqrt : brinfos_1_bits_uop_fp_ctrl_sqrt; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_wflags = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_wflags : brinfos_1_bits_uop_fp_ctrl_wflags; // @[Mux.scala:50:70] wire _b2_uop_T_fp_ctrl_vec = live_brinfos_0 ? brinfos_0_bits_uop_fp_ctrl_vec : brinfos_1_bits_uop_fp_ctrl_vec; // @[Mux.scala:50:70] wire [5:0] _b2_uop_T_rob_idx = live_brinfos_0 ? brinfos_0_bits_uop_rob_idx : brinfos_1_bits_uop_rob_idx; // @[Mux.scala:50:70] wire [3:0] _b2_uop_T_ldq_idx = live_brinfos_0 ? brinfos_0_bits_uop_ldq_idx : brinfos_1_bits_uop_ldq_idx; // @[Mux.scala:50:70] wire [3:0] _b2_uop_T_stq_idx = live_brinfos_0 ? brinfos_0_bits_uop_stq_idx : brinfos_1_bits_uop_stq_idx; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_rxq_idx = live_brinfos_0 ? brinfos_0_bits_uop_rxq_idx : brinfos_1_bits_uop_rxq_idx; // @[Mux.scala:50:70] wire [6:0] _b2_uop_T_pdst = live_brinfos_0 ? brinfos_0_bits_uop_pdst : brinfos_1_bits_uop_pdst; // @[Mux.scala:50:70] wire [6:0] _b2_uop_T_prs1 = live_brinfos_0 ? brinfos_0_bits_uop_prs1 : brinfos_1_bits_uop_prs1; // @[Mux.scala:50:70] wire [6:0] _b2_uop_T_prs2 = live_brinfos_0 ? brinfos_0_bits_uop_prs2 : brinfos_1_bits_uop_prs2; // @[Mux.scala:50:70] wire [6:0] _b2_uop_T_prs3 = live_brinfos_0 ? brinfos_0_bits_uop_prs3 : brinfos_1_bits_uop_prs3; // @[Mux.scala:50:70] wire [4:0] _b2_uop_T_ppred = live_brinfos_0 ? brinfos_0_bits_uop_ppred : brinfos_1_bits_uop_ppred; // @[Mux.scala:50:70] wire _b2_uop_T_prs1_busy = live_brinfos_0 ? brinfos_0_bits_uop_prs1_busy : brinfos_1_bits_uop_prs1_busy; // @[Mux.scala:50:70] wire _b2_uop_T_prs2_busy = live_brinfos_0 ? brinfos_0_bits_uop_prs2_busy : brinfos_1_bits_uop_prs2_busy; // @[Mux.scala:50:70] wire _b2_uop_T_prs3_busy = live_brinfos_0 ? brinfos_0_bits_uop_prs3_busy : brinfos_1_bits_uop_prs3_busy; // @[Mux.scala:50:70] wire _b2_uop_T_ppred_busy = live_brinfos_0 ? brinfos_0_bits_uop_ppred_busy : brinfos_1_bits_uop_ppred_busy; // @[Mux.scala:50:70] wire [6:0] _b2_uop_T_stale_pdst = live_brinfos_0 ? brinfos_0_bits_uop_stale_pdst : brinfos_1_bits_uop_stale_pdst; // @[Mux.scala:50:70] wire _b2_uop_T_exception = live_brinfos_0 ? brinfos_0_bits_uop_exception : brinfos_1_bits_uop_exception; // @[Mux.scala:50:70] wire [63:0] _b2_uop_T_exc_cause = live_brinfos_0 ? brinfos_0_bits_uop_exc_cause : brinfos_1_bits_uop_exc_cause; // @[Mux.scala:50:70] wire [4:0] _b2_uop_T_mem_cmd = live_brinfos_0 ? brinfos_0_bits_uop_mem_cmd : brinfos_1_bits_uop_mem_cmd; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_mem_size = live_brinfos_0 ? brinfos_0_bits_uop_mem_size : brinfos_1_bits_uop_mem_size; // @[Mux.scala:50:70] wire _b2_uop_T_mem_signed = live_brinfos_0 ? brinfos_0_bits_uop_mem_signed : brinfos_1_bits_uop_mem_signed; // @[Mux.scala:50:70] wire _b2_uop_T_uses_ldq = live_brinfos_0 ? brinfos_0_bits_uop_uses_ldq : brinfos_1_bits_uop_uses_ldq; // @[Mux.scala:50:70] wire _b2_uop_T_uses_stq = live_brinfos_0 ? brinfos_0_bits_uop_uses_stq : brinfos_1_bits_uop_uses_stq; // @[Mux.scala:50:70] wire _b2_uop_T_is_unique = live_brinfos_0 ? brinfos_0_bits_uop_is_unique : brinfos_1_bits_uop_is_unique; // @[Mux.scala:50:70] wire _b2_uop_T_flush_on_commit = live_brinfos_0 ? brinfos_0_bits_uop_flush_on_commit : brinfos_1_bits_uop_flush_on_commit; // @[Mux.scala:50:70] wire [2:0] _b2_uop_T_csr_cmd = live_brinfos_0 ? brinfos_0_bits_uop_csr_cmd : brinfos_1_bits_uop_csr_cmd; // @[Mux.scala:50:70] wire _b2_uop_T_ldst_is_rs1 = live_brinfos_0 ? brinfos_0_bits_uop_ldst_is_rs1 : brinfos_1_bits_uop_ldst_is_rs1; // @[Mux.scala:50:70] wire [5:0] _b2_uop_T_ldst = live_brinfos_0 ? brinfos_0_bits_uop_ldst : brinfos_1_bits_uop_ldst; // @[Mux.scala:50:70] wire [5:0] _b2_uop_T_lrs1 = live_brinfos_0 ? brinfos_0_bits_uop_lrs1 : brinfos_1_bits_uop_lrs1; // @[Mux.scala:50:70] wire [5:0] _b2_uop_T_lrs2 = live_brinfos_0 ? brinfos_0_bits_uop_lrs2 : brinfos_1_bits_uop_lrs2; // @[Mux.scala:50:70] wire [5:0] _b2_uop_T_lrs3 = live_brinfos_0 ? brinfos_0_bits_uop_lrs3 : brinfos_1_bits_uop_lrs3; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_dst_rtype = live_brinfos_0 ? brinfos_0_bits_uop_dst_rtype : brinfos_1_bits_uop_dst_rtype; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_lrs1_rtype = live_brinfos_0 ? brinfos_0_bits_uop_lrs1_rtype : brinfos_1_bits_uop_lrs1_rtype; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_lrs2_rtype = live_brinfos_0 ? brinfos_0_bits_uop_lrs2_rtype : brinfos_1_bits_uop_lrs2_rtype; // @[Mux.scala:50:70] wire _b2_uop_T_frs3_en = live_brinfos_0 ? brinfos_0_bits_uop_frs3_en : brinfos_1_bits_uop_frs3_en; // @[Mux.scala:50:70] wire _b2_uop_T_fcn_dw = live_brinfos_0 ? brinfos_0_bits_uop_fcn_dw : brinfos_1_bits_uop_fcn_dw; // @[Mux.scala:50:70] wire [4:0] _b2_uop_T_fcn_op = live_brinfos_0 ? brinfos_0_bits_uop_fcn_op : brinfos_1_bits_uop_fcn_op; // @[Mux.scala:50:70] wire _b2_uop_T_fp_val = live_brinfos_0 ? brinfos_0_bits_uop_fp_val : brinfos_1_bits_uop_fp_val; // @[Mux.scala:50:70] wire [2:0] _b2_uop_T_fp_rm = live_brinfos_0 ? brinfos_0_bits_uop_fp_rm : brinfos_1_bits_uop_fp_rm; // @[Mux.scala:50:70] wire [1:0] _b2_uop_T_fp_typ = live_brinfos_0 ? brinfos_0_bits_uop_fp_typ : brinfos_1_bits_uop_fp_typ; // @[Mux.scala:50:70] wire _b2_uop_T_xcpt_pf_if = live_brinfos_0 ? brinfos_0_bits_uop_xcpt_pf_if : brinfos_1_bits_uop_xcpt_pf_if; // @[Mux.scala:50:70] wire _b2_uop_T_xcpt_ae_if = live_brinfos_0 ? brinfos_0_bits_uop_xcpt_ae_if : brinfos_1_bits_uop_xcpt_ae_if; // @[Mux.scala:50:70] wire _b2_uop_T_xcpt_ma_if = live_brinfos_0 ? brinfos_0_bits_uop_xcpt_ma_if : brinfos_1_bits_uop_xcpt_ma_if; // @[Mux.scala:50:70] wire _b2_uop_T_bp_debug_if = live_brinfos_0 ? brinfos_0_bits_uop_bp_debug_if : brinfos_1_bits_uop_bp_debug_if; // @[Mux.scala:50:70] wire _b2_uop_T_bp_xcpt_if = live_brinfos_0 ? brinfos_0_bits_uop_bp_xcpt_if : brinfos_1_bits_uop_bp_xcpt_if; // @[Mux.scala:50:70] wire [2:0] _b2_uop_T_debug_fsrc = live_brinfos_0 ? brinfos_0_bits_uop_debug_fsrc : brinfos_1_bits_uop_debug_fsrc; // @[Mux.scala:50:70] wire [2:0] _b2_uop_T_debug_tsrc = live_brinfos_0 ? brinfos_0_bits_uop_debug_tsrc : brinfos_1_bits_uop_debug_tsrc; // @[Mux.scala:50:70] wire [31:0] b2_uop_out_inst = _b2_uop_T_inst; // @[Mux.scala:50:70] wire [31:0] b2_uop_out_debug_inst = _b2_uop_T_debug_inst; // @[Mux.scala:50:70] wire b2_uop_out_is_rvc = _b2_uop_T_is_rvc; // @[Mux.scala:50:70] wire [39:0] b2_uop_out_debug_pc = _b2_uop_T_debug_pc; // @[Mux.scala:50:70] wire b2_uop_out_iq_type_0 = _b2_uop_T_iq_type_0; // @[Mux.scala:50:70] wire b2_uop_out_iq_type_1 = _b2_uop_T_iq_type_1; // @[Mux.scala:50:70] wire b2_uop_out_iq_type_2 = _b2_uop_T_iq_type_2; // @[Mux.scala:50:70] wire b2_uop_out_iq_type_3 = _b2_uop_T_iq_type_3; // @[Mux.scala:50:70] wire b2_uop_out_fu_code_0 = _b2_uop_T_fu_code_0; // @[Mux.scala:50:70] wire b2_uop_out_fu_code_1 = _b2_uop_T_fu_code_1; // @[Mux.scala:50:70] wire b2_uop_out_fu_code_2 = _b2_uop_T_fu_code_2; // @[Mux.scala:50:70] wire b2_uop_out_fu_code_3 = _b2_uop_T_fu_code_3; // @[Mux.scala:50:70] wire b2_uop_out_fu_code_4 = _b2_uop_T_fu_code_4; // @[Mux.scala:50:70] wire b2_uop_out_fu_code_5 = _b2_uop_T_fu_code_5; // @[Mux.scala:50:70] wire b2_uop_out_fu_code_6 = _b2_uop_T_fu_code_6; // @[Mux.scala:50:70] wire b2_uop_out_fu_code_7 = _b2_uop_T_fu_code_7; // @[Mux.scala:50:70] wire b2_uop_out_fu_code_8 = _b2_uop_T_fu_code_8; // @[Mux.scala:50:70] wire b2_uop_out_fu_code_9 = _b2_uop_T_fu_code_9; // @[Mux.scala:50:70] wire b2_uop_out_iw_issued = _b2_uop_T_iw_issued; // @[Mux.scala:50:70] wire b2_uop_out_iw_issued_partial_agen = _b2_uop_T_iw_issued_partial_agen; // @[Mux.scala:50:70] wire b2_uop_out_iw_issued_partial_dgen = _b2_uop_T_iw_issued_partial_dgen; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_iw_p1_speculative_child = _b2_uop_T_iw_p1_speculative_child; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_iw_p2_speculative_child = _b2_uop_T_iw_p2_speculative_child; // @[Mux.scala:50:70] wire b2_uop_out_iw_p1_bypass_hint = _b2_uop_T_iw_p1_bypass_hint; // @[Mux.scala:50:70] wire b2_uop_out_iw_p2_bypass_hint = _b2_uop_T_iw_p2_bypass_hint; // @[Mux.scala:50:70] wire b2_uop_out_iw_p3_bypass_hint = _b2_uop_T_iw_p3_bypass_hint; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_dis_col_sel = _b2_uop_T_dis_col_sel; // @[Mux.scala:50:70] wire [3:0] b2_uop_out_br_tag = _b2_uop_T_br_tag; // @[Mux.scala:50:70] wire [3:0] b2_uop_out_br_type = _b2_uop_T_br_type; // @[Mux.scala:50:70] wire b2_uop_out_is_sfb = _b2_uop_T_is_sfb; // @[Mux.scala:50:70] wire b2_uop_out_is_fence = _b2_uop_T_is_fence; // @[Mux.scala:50:70] wire b2_uop_out_is_fencei = _b2_uop_T_is_fencei; // @[Mux.scala:50:70] wire b2_uop_out_is_sfence = _b2_uop_T_is_sfence; // @[Mux.scala:50:70] wire b2_uop_out_is_amo = _b2_uop_T_is_amo; // @[Mux.scala:50:70] wire b2_uop_out_is_eret = _b2_uop_T_is_eret; // @[Mux.scala:50:70] wire b2_uop_out_is_sys_pc2epc = _b2_uop_T_is_sys_pc2epc; // @[Mux.scala:50:70] wire b2_uop_out_is_rocc = _b2_uop_T_is_rocc; // @[Mux.scala:50:70] wire b2_uop_out_is_mov = _b2_uop_T_is_mov; // @[Mux.scala:50:70] wire [4:0] b2_uop_out_ftq_idx = _b2_uop_T_ftq_idx; // @[Mux.scala:50:70] wire b2_uop_out_edge_inst = _b2_uop_T_edge_inst; // @[Mux.scala:50:70] wire [5:0] b2_uop_out_pc_lob = _b2_uop_T_pc_lob; // @[Mux.scala:50:70] wire b2_uop_out_taken = _b2_uop_T_taken; // @[Mux.scala:50:70] wire b2_uop_out_imm_rename = _b2_uop_T_imm_rename; // @[Mux.scala:50:70] wire [2:0] b2_uop_out_imm_sel = _b2_uop_T_imm_sel; // @[Mux.scala:50:70] wire [4:0] b2_uop_out_pimm = _b2_uop_T_pimm; // @[Mux.scala:50:70] wire [19:0] b2_uop_out_imm_packed = _b2_uop_T_imm_packed; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_op1_sel = _b2_uop_T_op1_sel; // @[Mux.scala:50:70] wire [2:0] b2_uop_out_op2_sel = _b2_uop_T_op2_sel; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_ldst = _b2_uop_T_fp_ctrl_ldst; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_wen = _b2_uop_T_fp_ctrl_wen; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_ren1 = _b2_uop_T_fp_ctrl_ren1; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_ren2 = _b2_uop_T_fp_ctrl_ren2; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_ren3 = _b2_uop_T_fp_ctrl_ren3; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_swap12 = _b2_uop_T_fp_ctrl_swap12; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_swap23 = _b2_uop_T_fp_ctrl_swap23; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_fp_ctrl_typeTagIn = _b2_uop_T_fp_ctrl_typeTagIn; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_fp_ctrl_typeTagOut = _b2_uop_T_fp_ctrl_typeTagOut; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_fromint = _b2_uop_T_fp_ctrl_fromint; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_toint = _b2_uop_T_fp_ctrl_toint; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_fastpipe = _b2_uop_T_fp_ctrl_fastpipe; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_fma = _b2_uop_T_fp_ctrl_fma; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_div = _b2_uop_T_fp_ctrl_div; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_sqrt = _b2_uop_T_fp_ctrl_sqrt; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_wflags = _b2_uop_T_fp_ctrl_wflags; // @[Mux.scala:50:70] wire b2_uop_out_fp_ctrl_vec = _b2_uop_T_fp_ctrl_vec; // @[Mux.scala:50:70] wire [5:0] b2_uop_out_rob_idx = _b2_uop_T_rob_idx; // @[Mux.scala:50:70] wire [3:0] b2_uop_out_ldq_idx = _b2_uop_T_ldq_idx; // @[Mux.scala:50:70] wire [3:0] b2_uop_out_stq_idx = _b2_uop_T_stq_idx; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_rxq_idx = _b2_uop_T_rxq_idx; // @[Mux.scala:50:70] wire [6:0] b2_uop_out_pdst = _b2_uop_T_pdst; // @[Mux.scala:50:70] wire [6:0] b2_uop_out_prs1 = _b2_uop_T_prs1; // @[Mux.scala:50:70] wire [6:0] b2_uop_out_prs2 = _b2_uop_T_prs2; // @[Mux.scala:50:70] wire [6:0] b2_uop_out_prs3 = _b2_uop_T_prs3; // @[Mux.scala:50:70] wire [4:0] b2_uop_out_ppred = _b2_uop_T_ppred; // @[Mux.scala:50:70] wire b2_uop_out_prs1_busy = _b2_uop_T_prs1_busy; // @[Mux.scala:50:70] wire b2_uop_out_prs2_busy = _b2_uop_T_prs2_busy; // @[Mux.scala:50:70] wire b2_uop_out_prs3_busy = _b2_uop_T_prs3_busy; // @[Mux.scala:50:70] wire b2_uop_out_ppred_busy = _b2_uop_T_ppred_busy; // @[Mux.scala:50:70] wire [6:0] b2_uop_out_stale_pdst = _b2_uop_T_stale_pdst; // @[Mux.scala:50:70] wire b2_uop_out_exception = _b2_uop_T_exception; // @[Mux.scala:50:70] wire [63:0] b2_uop_out_exc_cause = _b2_uop_T_exc_cause; // @[Mux.scala:50:70] wire [4:0] b2_uop_out_mem_cmd = _b2_uop_T_mem_cmd; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_mem_size = _b2_uop_T_mem_size; // @[Mux.scala:50:70] wire b2_uop_out_mem_signed = _b2_uop_T_mem_signed; // @[Mux.scala:50:70] wire b2_uop_out_uses_ldq = _b2_uop_T_uses_ldq; // @[Mux.scala:50:70] wire b2_uop_out_uses_stq = _b2_uop_T_uses_stq; // @[Mux.scala:50:70] wire b2_uop_out_is_unique = _b2_uop_T_is_unique; // @[Mux.scala:50:70] wire b2_uop_out_flush_on_commit = _b2_uop_T_flush_on_commit; // @[Mux.scala:50:70] wire [2:0] b2_uop_out_csr_cmd = _b2_uop_T_csr_cmd; // @[Mux.scala:50:70] wire b2_uop_out_ldst_is_rs1 = _b2_uop_T_ldst_is_rs1; // @[Mux.scala:50:70] wire [5:0] b2_uop_out_ldst = _b2_uop_T_ldst; // @[Mux.scala:50:70] wire [5:0] b2_uop_out_lrs1 = _b2_uop_T_lrs1; // @[Mux.scala:50:70] wire [5:0] b2_uop_out_lrs2 = _b2_uop_T_lrs2; // @[Mux.scala:50:70] wire [5:0] b2_uop_out_lrs3 = _b2_uop_T_lrs3; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_dst_rtype = _b2_uop_T_dst_rtype; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_lrs1_rtype = _b2_uop_T_lrs1_rtype; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_lrs2_rtype = _b2_uop_T_lrs2_rtype; // @[Mux.scala:50:70] wire b2_uop_out_frs3_en = _b2_uop_T_frs3_en; // @[Mux.scala:50:70] wire b2_uop_out_fcn_dw = _b2_uop_T_fcn_dw; // @[Mux.scala:50:70] wire [4:0] b2_uop_out_fcn_op = _b2_uop_T_fcn_op; // @[Mux.scala:50:70] wire b2_uop_out_fp_val = _b2_uop_T_fp_val; // @[Mux.scala:50:70] wire [2:0] b2_uop_out_fp_rm = _b2_uop_T_fp_rm; // @[Mux.scala:50:70] wire [1:0] b2_uop_out_fp_typ = _b2_uop_T_fp_typ; // @[Mux.scala:50:70] wire b2_uop_out_xcpt_pf_if = _b2_uop_T_xcpt_pf_if; // @[Mux.scala:50:70] wire b2_uop_out_xcpt_ae_if = _b2_uop_T_xcpt_ae_if; // @[Mux.scala:50:70] wire b2_uop_out_xcpt_ma_if = _b2_uop_T_xcpt_ma_if; // @[Mux.scala:50:70] wire b2_uop_out_bp_debug_if = _b2_uop_T_bp_debug_if; // @[Mux.scala:50:70] wire b2_uop_out_bp_xcpt_if = _b2_uop_T_bp_xcpt_if; // @[Mux.scala:50:70] wire [2:0] b2_uop_out_debug_fsrc = _b2_uop_T_debug_fsrc; // @[Mux.scala:50:70] wire [2:0] b2_uop_out_debug_tsrc = _b2_uop_T_debug_tsrc; // @[Mux.scala:50:70] wire [11:0] _b2_uop_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] b2_uop_out_br_mask; // @[util.scala:104:23] wire [11:0] _b2_uop_out_br_mask_T = ~brupdate_b1_resolve_mask; // @[util.scala:93:27, :97:23] assign _b2_uop_out_br_mask_T_1 = _b2_uop_T_br_mask & _b2_uop_out_br_mask_T; // @[Mux.scala:50:70] assign b2_uop_out_br_mask = _b2_uop_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire [39:0] _b2_jalr_target_T = live_brinfos_0 ? brinfos_0_bits_jalr_target : 40'h0; // @[Mux.scala:30:73] wire [39:0] _b2_jalr_target_T_1 = live_brinfos_1 ? brinfos_1_bits_jalr_target : 40'h0; // @[Mux.scala:30:73] wire [39:0] _b2_jalr_target_T_2 = _b2_jalr_target_T | _b2_jalr_target_T_1; // @[Mux.scala:30:73] wire [39:0] _b2_jalr_target_WIRE = _b2_jalr_target_T_2; // @[Mux.scala:30:73] wire [20:0] _b2_target_offset_T_1; // @[Mux.scala:30:73] assign _b2_target_offset_T_1 = _b2_target_offset_T; // @[Mux.scala:30:73] wire [20:0] _b2_target_offset_WIRE = _b2_target_offset_T_1; // @[Mux.scala:30:73] wire [20:0] _b2_target_offset_T_3; // @[Mux.scala:30:73] assign _b2_target_offset_T_3 = _b2_target_offset_T_2; // @[Mux.scala:30:73] wire [20:0] _b2_target_offset_WIRE_1 = _b2_target_offset_T_3; // @[Mux.scala:30:73] wire [20:0] _b2_target_offset_T_4 = live_brinfos_0 ? _b2_target_offset_WIRE : 21'h0; // @[Mux.scala:30:73] wire [20:0] _b2_target_offset_T_5 = live_brinfos_1 ? _b2_target_offset_WIRE_1 : 21'h0; // @[Mux.scala:30:73] wire [20:0] _b2_target_offset_T_6 = _b2_target_offset_T_4 | _b2_target_offset_T_5; // @[Mux.scala:30:73] wire [20:0] _b2_target_offset_T_7 = _b2_target_offset_T_6; // @[Mux.scala:30:73] wire [20:0] _b2_target_offset_T_8 = _b2_target_offset_T_7; // @[Mux.scala:30:73] wire [20:0] _b2_target_offset_T_9; // @[Mux.scala:30:73] assign _b2_target_offset_T_9 = _b2_target_offset_T_8; // @[Mux.scala:30:73] wire [20:0] _b2_target_offset_WIRE_2 = _b2_target_offset_T_9; // @[Mux.scala:30:73] wire [4:0] _oldest_mispredict_ftq_idx_T = live_brinfos_0 ? brinfos_0_bits_uop_ftq_idx : 5'h0; // @[Mux.scala:30:73] wire [4:0] _oldest_mispredict_ftq_idx_T_1 = live_brinfos_1 ? brinfos_1_bits_uop_ftq_idx : 5'h0; // @[Mux.scala:30:73] wire [4:0] _oldest_mispredict_ftq_idx_T_2 = _oldest_mispredict_ftq_idx_T | _oldest_mispredict_ftq_idx_T_1; // @[Mux.scala:30:73] wire [4:0] oldest_mispredict_ftq_idx = _oldest_mispredict_ftq_idx_T_2; // @[Mux.scala:30:73] wire [4:0] mispredict_pc_req_bits = oldest_mispredict_ftq_idx; // @[Mux.scala:30:73] wire hits_0; // @[Events.scala:13:25] wire _csr_io_counters_5_inc_sets_T_3; // @[core.scala:281:65] wire hits_1_2; // @[Events.scala:13:25] wire hits_1_3; // @[Events.scala:13:25] wire custom_csrs_csrs_0_ren; // @[core.scala:301:25] wire custom_csrs_csrs_0_wen; // @[core.scala:301:25] wire [63:0] custom_csrs_csrs_0_wdata; // @[core.scala:301:25] wire [63:0] custom_csrs_csrs_0_value; // @[core.scala:301:25] wire custom_csrs_csrs_1_ren; // @[core.scala:301:25] wire custom_csrs_csrs_1_wen; // @[core.scala:301:25] wire [63:0] custom_csrs_csrs_1_wdata; // @[core.scala:301:25] wire [63:0] custom_csrs_csrs_1_value; // @[core.scala:301:25] wire custom_csrs_csrs_2_ren; // @[core.scala:301:25] wire custom_csrs_csrs_2_wen; // @[core.scala:301:25] wire [63:0] custom_csrs_csrs_2_wdata; // @[core.scala:301:25] wire [63:0] custom_csrs_csrs_2_value; // @[core.scala:301:25] wire custom_csrs_csrs_3_ren; // @[core.scala:301:25] wire custom_csrs_csrs_3_wen; // @[core.scala:301:25] wire [63:0] custom_csrs_csrs_3_wdata; // @[core.scala:301:25] wire [63:0] custom_csrs_csrs_3_value; // @[core.scala:301:25] assign _io_ifu_enable_bpd_T = custom_csrs_csrs_1_value[0]; // @[core.scala:301:25] assign io_ifu_enable_bpd_0 = _io_ifu_enable_bpd_T; // @[core.scala:50:7] wire [1:0] csr_io_counters_0_inc_set = _csr_io_counters_0_eventSel[1:0]; // @[Events.scala:40:13] wire [55:0] csr_io_counters_0_inc_mask = _csr_io_counters_0_eventSel[63:8]; // @[Events.scala:40:44] wire [1:0] _GEN_3 = {1'h0, hits_0}; // @[Events.scala:13:25, :16:21] wire [1:0] csr_io_counters_0_inc_sets_lo; // @[Events.scala:16:21] assign csr_io_counters_0_inc_sets_lo = _GEN_3; // @[Events.scala:16:21] wire [1:0] csr_io_counters_1_inc_sets_lo; // @[Events.scala:16:21] assign csr_io_counters_1_inc_sets_lo = _GEN_3; // @[Events.scala:16:21] wire [1:0] csr_io_counters_2_inc_sets_lo; // @[Events.scala:16:21] assign csr_io_counters_2_inc_sets_lo = _GEN_3; // @[Events.scala:16:21] wire [1:0] csr_io_counters_3_inc_sets_lo; // @[Events.scala:16:21] assign csr_io_counters_3_inc_sets_lo = _GEN_3; // @[Events.scala:16:21] wire [1:0] csr_io_counters_4_inc_sets_lo; // @[Events.scala:16:21] assign csr_io_counters_4_inc_sets_lo = _GEN_3; // @[Events.scala:16:21] wire [1:0] csr_io_counters_5_inc_sets_lo; // @[Events.scala:16:21] assign csr_io_counters_5_inc_sets_lo = _GEN_3; // @[Events.scala:16:21] wire [3:0] _csr_io_counters_0_inc_sets_T = {2'h0, csr_io_counters_0_inc_sets_lo}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_0_inc_sets_T_1 = {52'h0, csr_io_counters_0_inc_mask[3:0] & _csr_io_counters_0_inc_sets_T}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_0_inc_sets_0 = |_csr_io_counters_0_inc_sets_T_1; // @[core.scala:271:{68,76}] wire _GEN_4 = b2_cfi_type == 3'h3; // @[core.scala:211:18, :282:63] wire _csr_io_counters_0_inc_sets_T_2; // @[core.scala:282:63] assign _csr_io_counters_0_inc_sets_T_2 = _GEN_4; // @[core.scala:282:63] wire _csr_io_counters_1_inc_sets_T_2; // @[core.scala:282:63] assign _csr_io_counters_1_inc_sets_T_2 = _GEN_4; // @[core.scala:282:63] wire _csr_io_counters_2_inc_sets_T_2; // @[core.scala:282:63] assign _csr_io_counters_2_inc_sets_T_2 = _GEN_4; // @[core.scala:282:63] wire _csr_io_counters_3_inc_sets_T_2; // @[core.scala:282:63] assign _csr_io_counters_3_inc_sets_T_2 = _GEN_4; // @[core.scala:282:63] wire _csr_io_counters_4_inc_sets_T_2; // @[core.scala:282:63] assign _csr_io_counters_4_inc_sets_T_2 = _GEN_4; // @[core.scala:282:63] wire _csr_io_counters_5_inc_sets_T_2; // @[core.scala:282:63] assign _csr_io_counters_5_inc_sets_T_2 = _GEN_4; // @[core.scala:282:63] wire _csr_io_counters_0_inc_sets_T_3 = b2_mispredict & _csr_io_counters_0_inc_sets_T_2; // @[core.scala:211:18, :281:65, :282:63] wire [1:0] _GEN_5 = {hits_1_1, 1'h0}; // @[Events.scala:13:25, :16:21] wire [1:0] csr_io_counters_0_inc_sets_lo_1; // @[Events.scala:16:21] assign csr_io_counters_0_inc_sets_lo_1 = _GEN_5; // @[Events.scala:16:21] wire [1:0] csr_io_counters_1_inc_sets_lo_1; // @[Events.scala:16:21] assign csr_io_counters_1_inc_sets_lo_1 = _GEN_5; // @[Events.scala:16:21] wire [1:0] csr_io_counters_2_inc_sets_lo_1; // @[Events.scala:16:21] assign csr_io_counters_2_inc_sets_lo_1 = _GEN_5; // @[Events.scala:16:21] wire [1:0] csr_io_counters_3_inc_sets_lo_1; // @[Events.scala:16:21] assign csr_io_counters_3_inc_sets_lo_1 = _GEN_5; // @[Events.scala:16:21] wire [1:0] csr_io_counters_4_inc_sets_lo_1; // @[Events.scala:16:21] assign csr_io_counters_4_inc_sets_lo_1 = _GEN_5; // @[Events.scala:16:21] wire [1:0] csr_io_counters_5_inc_sets_lo_1; // @[Events.scala:16:21] assign csr_io_counters_5_inc_sets_lo_1 = _GEN_5; // @[Events.scala:16:21] wire [1:0] _GEN_6 = {hits_1_3, hits_1_2}; // @[Events.scala:13:25, :16:21] wire [1:0] csr_io_counters_0_inc_sets_hi_1; // @[Events.scala:16:21] assign csr_io_counters_0_inc_sets_hi_1 = _GEN_6; // @[Events.scala:16:21] wire [1:0] csr_io_counters_1_inc_sets_hi_1; // @[Events.scala:16:21] assign csr_io_counters_1_inc_sets_hi_1 = _GEN_6; // @[Events.scala:16:21] wire [1:0] csr_io_counters_2_inc_sets_hi_1; // @[Events.scala:16:21] assign csr_io_counters_2_inc_sets_hi_1 = _GEN_6; // @[Events.scala:16:21] wire [1:0] csr_io_counters_3_inc_sets_hi_1; // @[Events.scala:16:21] assign csr_io_counters_3_inc_sets_hi_1 = _GEN_6; // @[Events.scala:16:21] wire [1:0] csr_io_counters_4_inc_sets_hi_1; // @[Events.scala:16:21] assign csr_io_counters_4_inc_sets_hi_1 = _GEN_6; // @[Events.scala:16:21] wire [1:0] csr_io_counters_5_inc_sets_hi_1; // @[Events.scala:16:21] assign csr_io_counters_5_inc_sets_hi_1 = _GEN_6; // @[Events.scala:16:21] wire [3:0] _csr_io_counters_0_inc_sets_T_4 = {csr_io_counters_0_inc_sets_hi_1, csr_io_counters_0_inc_sets_lo_1}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_0_inc_sets_T_5 = {52'h0, csr_io_counters_0_inc_mask[3:0] & _csr_io_counters_0_inc_sets_T_4}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_0_inc_sets_1 = |_csr_io_counters_0_inc_sets_T_5; // @[core.scala:277:{68,76}] wire [1:0] _GEN_7 = {hits_2_2, hits_2_1}; // @[Events.scala:13:25, :16:21] wire [1:0] csr_io_counters_0_inc_sets_lo_hi; // @[Events.scala:16:21] assign csr_io_counters_0_inc_sets_lo_hi = _GEN_7; // @[Events.scala:16:21] wire [1:0] csr_io_counters_1_inc_sets_lo_hi; // @[Events.scala:16:21] assign csr_io_counters_1_inc_sets_lo_hi = _GEN_7; // @[Events.scala:16:21] wire [1:0] csr_io_counters_2_inc_sets_lo_hi; // @[Events.scala:16:21] assign csr_io_counters_2_inc_sets_lo_hi = _GEN_7; // @[Events.scala:16:21] wire [1:0] csr_io_counters_3_inc_sets_lo_hi; // @[Events.scala:16:21] assign csr_io_counters_3_inc_sets_lo_hi = _GEN_7; // @[Events.scala:16:21] wire [1:0] csr_io_counters_4_inc_sets_lo_hi; // @[Events.scala:16:21] assign csr_io_counters_4_inc_sets_lo_hi = _GEN_7; // @[Events.scala:16:21] wire [1:0] csr_io_counters_5_inc_sets_lo_hi; // @[Events.scala:16:21] assign csr_io_counters_5_inc_sets_lo_hi = _GEN_7; // @[Events.scala:16:21] wire [2:0] csr_io_counters_0_inc_sets_lo_2 = {csr_io_counters_0_inc_sets_lo_hi, hits_2_0}; // @[Events.scala:13:25, :16:21] wire [1:0] _GEN_8 = {hits_2_5, hits_2_4}; // @[Events.scala:13:25, :16:21] wire [1:0] csr_io_counters_0_inc_sets_hi_hi; // @[Events.scala:16:21] assign csr_io_counters_0_inc_sets_hi_hi = _GEN_8; // @[Events.scala:16:21] wire [1:0] csr_io_counters_1_inc_sets_hi_hi; // @[Events.scala:16:21] assign csr_io_counters_1_inc_sets_hi_hi = _GEN_8; // @[Events.scala:16:21] wire [1:0] csr_io_counters_2_inc_sets_hi_hi; // @[Events.scala:16:21] assign csr_io_counters_2_inc_sets_hi_hi = _GEN_8; // @[Events.scala:16:21] wire [1:0] csr_io_counters_3_inc_sets_hi_hi; // @[Events.scala:16:21] assign csr_io_counters_3_inc_sets_hi_hi = _GEN_8; // @[Events.scala:16:21] wire [1:0] csr_io_counters_4_inc_sets_hi_hi; // @[Events.scala:16:21] assign csr_io_counters_4_inc_sets_hi_hi = _GEN_8; // @[Events.scala:16:21] wire [1:0] csr_io_counters_5_inc_sets_hi_hi; // @[Events.scala:16:21] assign csr_io_counters_5_inc_sets_hi_hi = _GEN_8; // @[Events.scala:16:21] wire [2:0] csr_io_counters_0_inc_sets_hi_2 = {csr_io_counters_0_inc_sets_hi_hi, hits_2_3}; // @[Events.scala:13:25, :16:21] wire [5:0] _csr_io_counters_0_inc_sets_T_6 = {csr_io_counters_0_inc_sets_hi_2, csr_io_counters_0_inc_sets_lo_2}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_0_inc_sets_T_7 = {50'h0, csr_io_counters_0_inc_mask[5:0] & _csr_io_counters_0_inc_sets_T_6}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_0_inc_sets_2 = |_csr_io_counters_0_inc_sets_T_7; // @[core.scala:287:{68,76}] wire _csr_io_counters_0_inc_T = csr_io_counters_0_inc_set == 2'h1; // @[package.scala:39:86] wire _csr_io_counters_0_inc_T_1 = _csr_io_counters_0_inc_T ? csr_io_counters_0_inc_sets_1 : csr_io_counters_0_inc_sets_0; // @[package.scala:39:{76,86}] wire _csr_io_counters_0_inc_T_2 = csr_io_counters_0_inc_set == 2'h2; // @[package.scala:39:86] wire _csr_io_counters_0_inc_T_3 = _csr_io_counters_0_inc_T_2 ? csr_io_counters_0_inc_sets_2 : _csr_io_counters_0_inc_T_1; // @[package.scala:39:{76,86}] wire _csr_io_counters_0_inc_T_4 = &csr_io_counters_0_inc_set; // @[package.scala:39:86] wire _csr_io_counters_0_inc_T_5 = _csr_io_counters_0_inc_T_4 ? csr_io_counters_0_inc_sets_2 : _csr_io_counters_0_inc_T_3; // @[package.scala:39:{76,86}] reg csr_io_counters_0_inc_REG; // @[core.scala:308:50] wire [1:0] csr_io_counters_1_inc_set = _csr_io_counters_1_eventSel[1:0]; // @[Events.scala:40:13] wire [55:0] csr_io_counters_1_inc_mask = _csr_io_counters_1_eventSel[63:8]; // @[Events.scala:40:44] wire [3:0] _csr_io_counters_1_inc_sets_T = {2'h0, csr_io_counters_1_inc_sets_lo}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_1_inc_sets_T_1 = {52'h0, csr_io_counters_1_inc_mask[3:0] & _csr_io_counters_1_inc_sets_T}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_1_inc_sets_0 = |_csr_io_counters_1_inc_sets_T_1; // @[core.scala:271:{68,76}] wire _csr_io_counters_1_inc_sets_T_3 = b2_mispredict & _csr_io_counters_1_inc_sets_T_2; // @[core.scala:211:18, :281:65, :282:63] wire [3:0] _csr_io_counters_1_inc_sets_T_4 = {csr_io_counters_1_inc_sets_hi_1, csr_io_counters_1_inc_sets_lo_1}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_1_inc_sets_T_5 = {52'h0, csr_io_counters_1_inc_mask[3:0] & _csr_io_counters_1_inc_sets_T_4}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_1_inc_sets_1 = |_csr_io_counters_1_inc_sets_T_5; // @[core.scala:277:{68,76}] wire [2:0] csr_io_counters_1_inc_sets_lo_2 = {csr_io_counters_1_inc_sets_lo_hi, hits_2_0}; // @[Events.scala:13:25, :16:21] wire [2:0] csr_io_counters_1_inc_sets_hi_2 = {csr_io_counters_1_inc_sets_hi_hi, hits_2_3}; // @[Events.scala:13:25, :16:21] wire [5:0] _csr_io_counters_1_inc_sets_T_6 = {csr_io_counters_1_inc_sets_hi_2, csr_io_counters_1_inc_sets_lo_2}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_1_inc_sets_T_7 = {50'h0, csr_io_counters_1_inc_mask[5:0] & _csr_io_counters_1_inc_sets_T_6}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_1_inc_sets_2 = |_csr_io_counters_1_inc_sets_T_7; // @[core.scala:287:{68,76}] wire _csr_io_counters_1_inc_T = csr_io_counters_1_inc_set == 2'h1; // @[package.scala:39:86] wire _csr_io_counters_1_inc_T_1 = _csr_io_counters_1_inc_T ? csr_io_counters_1_inc_sets_1 : csr_io_counters_1_inc_sets_0; // @[package.scala:39:{76,86}] wire _csr_io_counters_1_inc_T_2 = csr_io_counters_1_inc_set == 2'h2; // @[package.scala:39:86] wire _csr_io_counters_1_inc_T_3 = _csr_io_counters_1_inc_T_2 ? csr_io_counters_1_inc_sets_2 : _csr_io_counters_1_inc_T_1; // @[package.scala:39:{76,86}] wire _csr_io_counters_1_inc_T_4 = &csr_io_counters_1_inc_set; // @[package.scala:39:86] wire _csr_io_counters_1_inc_T_5 = _csr_io_counters_1_inc_T_4 ? csr_io_counters_1_inc_sets_2 : _csr_io_counters_1_inc_T_3; // @[package.scala:39:{76,86}] reg csr_io_counters_1_inc_REG; // @[core.scala:308:50] wire [1:0] csr_io_counters_2_inc_set = _csr_io_counters_2_eventSel[1:0]; // @[Events.scala:40:13] wire [55:0] csr_io_counters_2_inc_mask = _csr_io_counters_2_eventSel[63:8]; // @[Events.scala:40:44] wire [3:0] _csr_io_counters_2_inc_sets_T = {2'h0, csr_io_counters_2_inc_sets_lo}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_2_inc_sets_T_1 = {52'h0, csr_io_counters_2_inc_mask[3:0] & _csr_io_counters_2_inc_sets_T}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_2_inc_sets_0 = |_csr_io_counters_2_inc_sets_T_1; // @[core.scala:271:{68,76}] wire _csr_io_counters_2_inc_sets_T_3 = b2_mispredict & _csr_io_counters_2_inc_sets_T_2; // @[core.scala:211:18, :281:65, :282:63] wire [3:0] _csr_io_counters_2_inc_sets_T_4 = {csr_io_counters_2_inc_sets_hi_1, csr_io_counters_2_inc_sets_lo_1}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_2_inc_sets_T_5 = {52'h0, csr_io_counters_2_inc_mask[3:0] & _csr_io_counters_2_inc_sets_T_4}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_2_inc_sets_1 = |_csr_io_counters_2_inc_sets_T_5; // @[core.scala:277:{68,76}] wire [2:0] csr_io_counters_2_inc_sets_lo_2 = {csr_io_counters_2_inc_sets_lo_hi, hits_2_0}; // @[Events.scala:13:25, :16:21] wire [2:0] csr_io_counters_2_inc_sets_hi_2 = {csr_io_counters_2_inc_sets_hi_hi, hits_2_3}; // @[Events.scala:13:25, :16:21] wire [5:0] _csr_io_counters_2_inc_sets_T_6 = {csr_io_counters_2_inc_sets_hi_2, csr_io_counters_2_inc_sets_lo_2}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_2_inc_sets_T_7 = {50'h0, csr_io_counters_2_inc_mask[5:0] & _csr_io_counters_2_inc_sets_T_6}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_2_inc_sets_2 = |_csr_io_counters_2_inc_sets_T_7; // @[core.scala:287:{68,76}] wire _csr_io_counters_2_inc_T = csr_io_counters_2_inc_set == 2'h1; // @[package.scala:39:86] wire _csr_io_counters_2_inc_T_1 = _csr_io_counters_2_inc_T ? csr_io_counters_2_inc_sets_1 : csr_io_counters_2_inc_sets_0; // @[package.scala:39:{76,86}] wire _csr_io_counters_2_inc_T_2 = csr_io_counters_2_inc_set == 2'h2; // @[package.scala:39:86] wire _csr_io_counters_2_inc_T_3 = _csr_io_counters_2_inc_T_2 ? csr_io_counters_2_inc_sets_2 : _csr_io_counters_2_inc_T_1; // @[package.scala:39:{76,86}] wire _csr_io_counters_2_inc_T_4 = &csr_io_counters_2_inc_set; // @[package.scala:39:86] wire _csr_io_counters_2_inc_T_5 = _csr_io_counters_2_inc_T_4 ? csr_io_counters_2_inc_sets_2 : _csr_io_counters_2_inc_T_3; // @[package.scala:39:{76,86}] reg csr_io_counters_2_inc_REG; // @[core.scala:308:50] wire [1:0] csr_io_counters_3_inc_set = _csr_io_counters_3_eventSel[1:0]; // @[Events.scala:40:13] wire [55:0] csr_io_counters_3_inc_mask = _csr_io_counters_3_eventSel[63:8]; // @[Events.scala:40:44] wire [3:0] _csr_io_counters_3_inc_sets_T = {2'h0, csr_io_counters_3_inc_sets_lo}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_3_inc_sets_T_1 = {52'h0, csr_io_counters_3_inc_mask[3:0] & _csr_io_counters_3_inc_sets_T}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_3_inc_sets_0 = |_csr_io_counters_3_inc_sets_T_1; // @[core.scala:271:{68,76}] wire _csr_io_counters_3_inc_sets_T_3 = b2_mispredict & _csr_io_counters_3_inc_sets_T_2; // @[core.scala:211:18, :281:65, :282:63] wire [3:0] _csr_io_counters_3_inc_sets_T_4 = {csr_io_counters_3_inc_sets_hi_1, csr_io_counters_3_inc_sets_lo_1}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_3_inc_sets_T_5 = {52'h0, csr_io_counters_3_inc_mask[3:0] & _csr_io_counters_3_inc_sets_T_4}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_3_inc_sets_1 = |_csr_io_counters_3_inc_sets_T_5; // @[core.scala:277:{68,76}] wire [2:0] csr_io_counters_3_inc_sets_lo_2 = {csr_io_counters_3_inc_sets_lo_hi, hits_2_0}; // @[Events.scala:13:25, :16:21] wire [2:0] csr_io_counters_3_inc_sets_hi_2 = {csr_io_counters_3_inc_sets_hi_hi, hits_2_3}; // @[Events.scala:13:25, :16:21] wire [5:0] _csr_io_counters_3_inc_sets_T_6 = {csr_io_counters_3_inc_sets_hi_2, csr_io_counters_3_inc_sets_lo_2}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_3_inc_sets_T_7 = {50'h0, csr_io_counters_3_inc_mask[5:0] & _csr_io_counters_3_inc_sets_T_6}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_3_inc_sets_2 = |_csr_io_counters_3_inc_sets_T_7; // @[core.scala:287:{68,76}] wire _csr_io_counters_3_inc_T = csr_io_counters_3_inc_set == 2'h1; // @[package.scala:39:86] wire _csr_io_counters_3_inc_T_1 = _csr_io_counters_3_inc_T ? csr_io_counters_3_inc_sets_1 : csr_io_counters_3_inc_sets_0; // @[package.scala:39:{76,86}] wire _csr_io_counters_3_inc_T_2 = csr_io_counters_3_inc_set == 2'h2; // @[package.scala:39:86] wire _csr_io_counters_3_inc_T_3 = _csr_io_counters_3_inc_T_2 ? csr_io_counters_3_inc_sets_2 : _csr_io_counters_3_inc_T_1; // @[package.scala:39:{76,86}] wire _csr_io_counters_3_inc_T_4 = &csr_io_counters_3_inc_set; // @[package.scala:39:86] wire _csr_io_counters_3_inc_T_5 = _csr_io_counters_3_inc_T_4 ? csr_io_counters_3_inc_sets_2 : _csr_io_counters_3_inc_T_3; // @[package.scala:39:{76,86}] reg csr_io_counters_3_inc_REG; // @[core.scala:308:50] wire [1:0] csr_io_counters_4_inc_set = _csr_io_counters_4_eventSel[1:0]; // @[Events.scala:40:13] wire [55:0] csr_io_counters_4_inc_mask = _csr_io_counters_4_eventSel[63:8]; // @[Events.scala:40:44] wire [3:0] _csr_io_counters_4_inc_sets_T = {2'h0, csr_io_counters_4_inc_sets_lo}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_4_inc_sets_T_1 = {52'h0, csr_io_counters_4_inc_mask[3:0] & _csr_io_counters_4_inc_sets_T}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_4_inc_sets_0 = |_csr_io_counters_4_inc_sets_T_1; // @[core.scala:271:{68,76}] wire _csr_io_counters_4_inc_sets_T_3 = b2_mispredict & _csr_io_counters_4_inc_sets_T_2; // @[core.scala:211:18, :281:65, :282:63] wire [3:0] _csr_io_counters_4_inc_sets_T_4 = {csr_io_counters_4_inc_sets_hi_1, csr_io_counters_4_inc_sets_lo_1}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_4_inc_sets_T_5 = {52'h0, csr_io_counters_4_inc_mask[3:0] & _csr_io_counters_4_inc_sets_T_4}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_4_inc_sets_1 = |_csr_io_counters_4_inc_sets_T_5; // @[core.scala:277:{68,76}] wire [2:0] csr_io_counters_4_inc_sets_lo_2 = {csr_io_counters_4_inc_sets_lo_hi, hits_2_0}; // @[Events.scala:13:25, :16:21] wire [2:0] csr_io_counters_4_inc_sets_hi_2 = {csr_io_counters_4_inc_sets_hi_hi, hits_2_3}; // @[Events.scala:13:25, :16:21] wire [5:0] _csr_io_counters_4_inc_sets_T_6 = {csr_io_counters_4_inc_sets_hi_2, csr_io_counters_4_inc_sets_lo_2}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_4_inc_sets_T_7 = {50'h0, csr_io_counters_4_inc_mask[5:0] & _csr_io_counters_4_inc_sets_T_6}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_4_inc_sets_2 = |_csr_io_counters_4_inc_sets_T_7; // @[core.scala:287:{68,76}] wire _csr_io_counters_4_inc_T = csr_io_counters_4_inc_set == 2'h1; // @[package.scala:39:86] wire _csr_io_counters_4_inc_T_1 = _csr_io_counters_4_inc_T ? csr_io_counters_4_inc_sets_1 : csr_io_counters_4_inc_sets_0; // @[package.scala:39:{76,86}] wire _csr_io_counters_4_inc_T_2 = csr_io_counters_4_inc_set == 2'h2; // @[package.scala:39:86] wire _csr_io_counters_4_inc_T_3 = _csr_io_counters_4_inc_T_2 ? csr_io_counters_4_inc_sets_2 : _csr_io_counters_4_inc_T_1; // @[package.scala:39:{76,86}] wire _csr_io_counters_4_inc_T_4 = &csr_io_counters_4_inc_set; // @[package.scala:39:86] wire _csr_io_counters_4_inc_T_5 = _csr_io_counters_4_inc_T_4 ? csr_io_counters_4_inc_sets_2 : _csr_io_counters_4_inc_T_3; // @[package.scala:39:{76,86}] reg csr_io_counters_4_inc_REG; // @[core.scala:308:50] wire [1:0] csr_io_counters_5_inc_set = _csr_io_counters_5_eventSel[1:0]; // @[Events.scala:40:13] wire [55:0] csr_io_counters_5_inc_mask = _csr_io_counters_5_eventSel[63:8]; // @[Events.scala:40:44] wire [3:0] _csr_io_counters_5_inc_sets_T = {2'h0, csr_io_counters_5_inc_sets_lo}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_5_inc_sets_T_1 = {52'h0, csr_io_counters_5_inc_mask[3:0] & _csr_io_counters_5_inc_sets_T}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_5_inc_sets_0 = |_csr_io_counters_5_inc_sets_T_1; // @[core.scala:271:{68,76}] assign _csr_io_counters_5_inc_sets_T_3 = b2_mispredict & _csr_io_counters_5_inc_sets_T_2; // @[core.scala:211:18, :281:65, :282:63] assign hits_1_2 = _csr_io_counters_5_inc_sets_T_3; // @[Events.scala:13:25] wire [3:0] _csr_io_counters_5_inc_sets_T_4 = {csr_io_counters_5_inc_sets_hi_1, csr_io_counters_5_inc_sets_lo_1}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_5_inc_sets_T_5 = {52'h0, csr_io_counters_5_inc_mask[3:0] & _csr_io_counters_5_inc_sets_T_4}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_5_inc_sets_1 = |_csr_io_counters_5_inc_sets_T_5; // @[core.scala:277:{68,76}] wire [2:0] csr_io_counters_5_inc_sets_lo_2 = {csr_io_counters_5_inc_sets_lo_hi, hits_2_0}; // @[Events.scala:13:25, :16:21] wire [2:0] csr_io_counters_5_inc_sets_hi_2 = {csr_io_counters_5_inc_sets_hi_hi, hits_2_3}; // @[Events.scala:13:25, :16:21] wire [5:0] _csr_io_counters_5_inc_sets_T_6 = {csr_io_counters_5_inc_sets_hi_2, csr_io_counters_5_inc_sets_lo_2}; // @[Events.scala:16:21] wire [55:0] _csr_io_counters_5_inc_sets_T_7 = {50'h0, csr_io_counters_5_inc_mask[5:0] & _csr_io_counters_5_inc_sets_T_6}; // @[Events.scala:16:21, :40:44] wire csr_io_counters_5_inc_sets_2 = |_csr_io_counters_5_inc_sets_T_7; // @[core.scala:287:{68,76}] wire _csr_io_counters_5_inc_T = csr_io_counters_5_inc_set == 2'h1; // @[package.scala:39:86] wire _csr_io_counters_5_inc_T_1 = _csr_io_counters_5_inc_T ? csr_io_counters_5_inc_sets_1 : csr_io_counters_5_inc_sets_0; // @[package.scala:39:{76,86}] wire _csr_io_counters_5_inc_T_2 = csr_io_counters_5_inc_set == 2'h2; // @[package.scala:39:86] wire _csr_io_counters_5_inc_T_3 = _csr_io_counters_5_inc_T_2 ? csr_io_counters_5_inc_sets_2 : _csr_io_counters_5_inc_T_1; // @[package.scala:39:{76,86}] wire _csr_io_counters_5_inc_T_4 = &csr_io_counters_5_inc_set; // @[package.scala:39:86] wire _csr_io_counters_5_inc_T_5 = _csr_io_counters_5_inc_T_4 ? csr_io_counters_5_inc_sets_2 : _csr_io_counters_5_inc_T_3; // @[package.scala:39:{76,86}] reg csr_io_counters_5_inc_REG; // @[core.scala:308:50] reg [63:0] debug_tsc_reg; // @[core.scala:313:30] assign io_lsu_tsc_reg_0 = debug_tsc_reg; // @[core.scala:50:7, :313:30] reg [63:0] debug_irt_reg; // @[core.scala:314:30] reg [63:0] debug_brs_0; // @[core.scala:315:30] reg [63:0] debug_brs_1; // @[core.scala:315:30] reg [63:0] debug_brs_2; // @[core.scala:315:30] reg [63:0] debug_brs_3; // @[core.scala:315:30] reg [63:0] debug_brs_4; // @[core.scala:315:30] reg [63:0] debug_jals_0; // @[core.scala:316:30] reg [63:0] debug_jals_1; // @[core.scala:316:30] reg [63:0] debug_jals_2; // @[core.scala:316:30] reg [63:0] debug_jals_3; // @[core.scala:316:30] reg [63:0] debug_jals_4; // @[core.scala:316:30] reg [63:0] debug_jalrs_0; // @[core.scala:317:30] reg [63:0] debug_jalrs_1; // @[core.scala:317:30] reg [63:0] debug_jalrs_2; // @[core.scala:317:30] reg [63:0] debug_jalrs_3; // @[core.scala:317:30] reg [63:0] debug_jalrs_4; // @[core.scala:317:30] wire _GEN_9 = _rob_io_commit_uops_0_debug_fsrc == 3'h0; // @[core.scala:159:32, :322:41] wire _debug_brs_0_T; // @[core.scala:322:41] assign _debug_brs_0_T = _GEN_9; // @[core.scala:322:41] wire _debug_jals_0_T; // @[core.scala:327:41] assign _debug_jals_0_T = _GEN_9; // @[core.scala:322:41, :327:41] wire _debug_jalrs_0_T; // @[core.scala:332:41] assign _debug_jalrs_0_T = _GEN_9; // @[core.scala:322:41, :332:41] wire _debug_brs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_0_T; // @[core.scala:159:32, :321:36, :322:41] wire _GEN_10 = _rob_io_commit_uops_0_br_type == 4'h1; // @[package.scala:16:47] wire _debug_brs_0_T_2; // @[package.scala:16:47] assign _debug_brs_0_T_2 = _GEN_10; // @[package.scala:16:47] wire _debug_brs_1_T_2; // @[package.scala:16:47] assign _debug_brs_1_T_2 = _GEN_10; // @[package.scala:16:47] wire _debug_brs_2_T_2; // @[package.scala:16:47] assign _debug_brs_2_T_2 = _GEN_10; // @[package.scala:16:47] wire _debug_brs_3_T_2; // @[package.scala:16:47] assign _debug_brs_3_T_2 = _GEN_10; // @[package.scala:16:47] wire _debug_brs_4_T_2; // @[package.scala:16:47] assign _debug_brs_4_T_2 = _GEN_10; // @[package.scala:16:47] wire _GEN_11 = _rob_io_commit_uops_0_br_type == 4'h2; // @[package.scala:16:47] wire _debug_brs_0_T_3; // @[package.scala:16:47] assign _debug_brs_0_T_3 = _GEN_11; // @[package.scala:16:47] wire _debug_brs_1_T_3; // @[package.scala:16:47] assign _debug_brs_1_T_3 = _GEN_11; // @[package.scala:16:47] wire _debug_brs_2_T_3; // @[package.scala:16:47] assign _debug_brs_2_T_3 = _GEN_11; // @[package.scala:16:47] wire _debug_brs_3_T_3; // @[package.scala:16:47] assign _debug_brs_3_T_3 = _GEN_11; // @[package.scala:16:47] wire _debug_brs_4_T_3; // @[package.scala:16:47] assign _debug_brs_4_T_3 = _GEN_11; // @[package.scala:16:47] wire _GEN_12 = _rob_io_commit_uops_0_br_type == 4'h3; // @[package.scala:16:47] wire _debug_brs_0_T_4; // @[package.scala:16:47] assign _debug_brs_0_T_4 = _GEN_12; // @[package.scala:16:47] wire _debug_brs_1_T_4; // @[package.scala:16:47] assign _debug_brs_1_T_4 = _GEN_12; // @[package.scala:16:47] wire _debug_brs_2_T_4; // @[package.scala:16:47] assign _debug_brs_2_T_4 = _GEN_12; // @[package.scala:16:47] wire _debug_brs_3_T_4; // @[package.scala:16:47] assign _debug_brs_3_T_4 = _GEN_12; // @[package.scala:16:47] wire _debug_brs_4_T_4; // @[package.scala:16:47] assign _debug_brs_4_T_4 = _GEN_12; // @[package.scala:16:47] wire _GEN_13 = _rob_io_commit_uops_0_br_type == 4'h4; // @[package.scala:16:47] wire _debug_brs_0_T_5; // @[package.scala:16:47] assign _debug_brs_0_T_5 = _GEN_13; // @[package.scala:16:47] wire _debug_brs_1_T_5; // @[package.scala:16:47] assign _debug_brs_1_T_5 = _GEN_13; // @[package.scala:16:47] wire _debug_brs_2_T_5; // @[package.scala:16:47] assign _debug_brs_2_T_5 = _GEN_13; // @[package.scala:16:47] wire _debug_brs_3_T_5; // @[package.scala:16:47] assign _debug_brs_3_T_5 = _GEN_13; // @[package.scala:16:47] wire _debug_brs_4_T_5; // @[package.scala:16:47] assign _debug_brs_4_T_5 = _GEN_13; // @[package.scala:16:47] wire _GEN_14 = _rob_io_commit_uops_0_br_type == 4'h5; // @[package.scala:16:47] wire _debug_brs_0_T_6; // @[package.scala:16:47] assign _debug_brs_0_T_6 = _GEN_14; // @[package.scala:16:47] wire _debug_brs_1_T_6; // @[package.scala:16:47] assign _debug_brs_1_T_6 = _GEN_14; // @[package.scala:16:47] wire _debug_brs_2_T_6; // @[package.scala:16:47] assign _debug_brs_2_T_6 = _GEN_14; // @[package.scala:16:47] wire _debug_brs_3_T_6; // @[package.scala:16:47] assign _debug_brs_3_T_6 = _GEN_14; // @[package.scala:16:47] wire _debug_brs_4_T_6; // @[package.scala:16:47] assign _debug_brs_4_T_6 = _GEN_14; // @[package.scala:16:47] wire _GEN_15 = _rob_io_commit_uops_0_br_type == 4'h6; // @[package.scala:16:47] wire _debug_brs_0_T_7; // @[package.scala:16:47] assign _debug_brs_0_T_7 = _GEN_15; // @[package.scala:16:47] wire _debug_brs_1_T_7; // @[package.scala:16:47] assign _debug_brs_1_T_7 = _GEN_15; // @[package.scala:16:47] wire _debug_brs_2_T_7; // @[package.scala:16:47] assign _debug_brs_2_T_7 = _GEN_15; // @[package.scala:16:47] wire _debug_brs_3_T_7; // @[package.scala:16:47] assign _debug_brs_3_T_7 = _GEN_15; // @[package.scala:16:47] wire _debug_brs_4_T_7; // @[package.scala:16:47] assign _debug_brs_4_T_7 = _GEN_15; // @[package.scala:16:47] wire _debug_brs_0_T_8 = _debug_brs_0_T_2 | _debug_brs_0_T_3; // @[package.scala:16:47, :81:59] wire _debug_brs_0_T_9 = _debug_brs_0_T_8 | _debug_brs_0_T_4; // @[package.scala:16:47, :81:59] wire _debug_brs_0_T_10 = _debug_brs_0_T_9 | _debug_brs_0_T_5; // @[package.scala:16:47, :81:59] wire _debug_brs_0_T_11 = _debug_brs_0_T_10 | _debug_brs_0_T_6; // @[package.scala:16:47, :81:59] wire _debug_brs_0_T_12 = _debug_brs_0_T_11 | _debug_brs_0_T_7; // @[package.scala:16:47, :81:59] wire _debug_brs_0_T_13 = _debug_brs_0_T_1 & _debug_brs_0_T_12; // @[package.scala:81:59] wire _debug_brs_0_WIRE_0 = _debug_brs_0_T_13; // @[core.scala:320:52, :322:50] wire _GEN_16 = _rob_io_commit_uops_1_debug_fsrc == 3'h0; // @[core.scala:159:32, :322:41] wire _debug_brs_0_T_14; // @[core.scala:322:41] assign _debug_brs_0_T_14 = _GEN_16; // @[core.scala:322:41] wire _debug_jals_0_T_4; // @[core.scala:327:41] assign _debug_jals_0_T_4 = _GEN_16; // @[core.scala:322:41, :327:41] wire _debug_jalrs_0_T_4; // @[core.scala:332:41] assign _debug_jalrs_0_T_4 = _GEN_16; // @[core.scala:322:41, :332:41] wire _debug_brs_0_T_15 = _rob_io_commit_arch_valids_1 & _debug_brs_0_T_14; // @[core.scala:159:32, :321:36, :322:41] wire _GEN_17 = _rob_io_commit_uops_1_br_type == 4'h1; // @[package.scala:16:47] wire _debug_brs_0_T_16; // @[package.scala:16:47] assign _debug_brs_0_T_16 = _GEN_17; // @[package.scala:16:47] wire _debug_brs_1_T_16; // @[package.scala:16:47] assign _debug_brs_1_T_16 = _GEN_17; // @[package.scala:16:47] wire _debug_brs_2_T_16; // @[package.scala:16:47] assign _debug_brs_2_T_16 = _GEN_17; // @[package.scala:16:47] wire _debug_brs_3_T_16; // @[package.scala:16:47] assign _debug_brs_3_T_16 = _GEN_17; // @[package.scala:16:47] wire _debug_brs_4_T_16; // @[package.scala:16:47] assign _debug_brs_4_T_16 = _GEN_17; // @[package.scala:16:47] wire _GEN_18 = _rob_io_commit_uops_1_br_type == 4'h2; // @[package.scala:16:47] wire _debug_brs_0_T_17; // @[package.scala:16:47] assign _debug_brs_0_T_17 = _GEN_18; // @[package.scala:16:47] wire _debug_brs_1_T_17; // @[package.scala:16:47] assign _debug_brs_1_T_17 = _GEN_18; // @[package.scala:16:47] wire _debug_brs_2_T_17; // @[package.scala:16:47] assign _debug_brs_2_T_17 = _GEN_18; // @[package.scala:16:47] wire _debug_brs_3_T_17; // @[package.scala:16:47] assign _debug_brs_3_T_17 = _GEN_18; // @[package.scala:16:47] wire _debug_brs_4_T_17; // @[package.scala:16:47] assign _debug_brs_4_T_17 = _GEN_18; // @[package.scala:16:47] wire _GEN_19 = _rob_io_commit_uops_1_br_type == 4'h3; // @[package.scala:16:47] wire _debug_brs_0_T_18; // @[package.scala:16:47] assign _debug_brs_0_T_18 = _GEN_19; // @[package.scala:16:47] wire _debug_brs_1_T_18; // @[package.scala:16:47] assign _debug_brs_1_T_18 = _GEN_19; // @[package.scala:16:47] wire _debug_brs_2_T_18; // @[package.scala:16:47] assign _debug_brs_2_T_18 = _GEN_19; // @[package.scala:16:47] wire _debug_brs_3_T_18; // @[package.scala:16:47] assign _debug_brs_3_T_18 = _GEN_19; // @[package.scala:16:47] wire _debug_brs_4_T_18; // @[package.scala:16:47] assign _debug_brs_4_T_18 = _GEN_19; // @[package.scala:16:47] wire _GEN_20 = _rob_io_commit_uops_1_br_type == 4'h4; // @[package.scala:16:47] wire _debug_brs_0_T_19; // @[package.scala:16:47] assign _debug_brs_0_T_19 = _GEN_20; // @[package.scala:16:47] wire _debug_brs_1_T_19; // @[package.scala:16:47] assign _debug_brs_1_T_19 = _GEN_20; // @[package.scala:16:47] wire _debug_brs_2_T_19; // @[package.scala:16:47] assign _debug_brs_2_T_19 = _GEN_20; // @[package.scala:16:47] wire _debug_brs_3_T_19; // @[package.scala:16:47] assign _debug_brs_3_T_19 = _GEN_20; // @[package.scala:16:47] wire _debug_brs_4_T_19; // @[package.scala:16:47] assign _debug_brs_4_T_19 = _GEN_20; // @[package.scala:16:47] wire _GEN_21 = _rob_io_commit_uops_1_br_type == 4'h5; // @[package.scala:16:47] wire _debug_brs_0_T_20; // @[package.scala:16:47] assign _debug_brs_0_T_20 = _GEN_21; // @[package.scala:16:47] wire _debug_brs_1_T_20; // @[package.scala:16:47] assign _debug_brs_1_T_20 = _GEN_21; // @[package.scala:16:47] wire _debug_brs_2_T_20; // @[package.scala:16:47] assign _debug_brs_2_T_20 = _GEN_21; // @[package.scala:16:47] wire _debug_brs_3_T_20; // @[package.scala:16:47] assign _debug_brs_3_T_20 = _GEN_21; // @[package.scala:16:47] wire _debug_brs_4_T_20; // @[package.scala:16:47] assign _debug_brs_4_T_20 = _GEN_21; // @[package.scala:16:47] wire _GEN_22 = _rob_io_commit_uops_1_br_type == 4'h6; // @[package.scala:16:47] wire _debug_brs_0_T_21; // @[package.scala:16:47] assign _debug_brs_0_T_21 = _GEN_22; // @[package.scala:16:47] wire _debug_brs_1_T_21; // @[package.scala:16:47] assign _debug_brs_1_T_21 = _GEN_22; // @[package.scala:16:47] wire _debug_brs_2_T_21; // @[package.scala:16:47] assign _debug_brs_2_T_21 = _GEN_22; // @[package.scala:16:47] wire _debug_brs_3_T_21; // @[package.scala:16:47] assign _debug_brs_3_T_21 = _GEN_22; // @[package.scala:16:47] wire _debug_brs_4_T_21; // @[package.scala:16:47] assign _debug_brs_4_T_21 = _GEN_22; // @[package.scala:16:47] wire _debug_brs_0_T_22 = _debug_brs_0_T_16 | _debug_brs_0_T_17; // @[package.scala:16:47, :81:59] wire _debug_brs_0_T_23 = _debug_brs_0_T_22 | _debug_brs_0_T_18; // @[package.scala:16:47, :81:59] wire _debug_brs_0_T_24 = _debug_brs_0_T_23 | _debug_brs_0_T_19; // @[package.scala:16:47, :81:59] wire _debug_brs_0_T_25 = _debug_brs_0_T_24 | _debug_brs_0_T_20; // @[package.scala:16:47, :81:59] wire _debug_brs_0_T_26 = _debug_brs_0_T_25 | _debug_brs_0_T_21; // @[package.scala:16:47, :81:59] wire _debug_brs_0_T_27 = _debug_brs_0_T_15 & _debug_brs_0_T_26; // @[package.scala:81:59] wire _debug_brs_0_WIRE_1 = _debug_brs_0_T_27; // @[core.scala:320:52, :322:50] wire [1:0] _debug_brs_0_T_28 = {1'h0, _debug_brs_0_WIRE_0} + {1'h0, _debug_brs_0_WIRE_1}; // @[core.scala:320:{44,52}] wire [1:0] _debug_brs_0_T_29 = _debug_brs_0_T_28; // @[core.scala:320:44] wire [64:0] _debug_brs_0_T_30 = {1'h0, debug_brs_0} + {63'h0, _debug_brs_0_T_29}; // @[core.scala:315:30, :320:{34,44}] wire [63:0] _debug_brs_0_T_31 = _debug_brs_0_T_30[63:0]; // @[core.scala:320:34] wire _debug_jals_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_0_T; // @[core.scala:159:32, :326:36, :327:41] wire _GEN_23 = _rob_io_commit_uops_0_br_type == 4'h7; // @[core.scala:159:32] wire _debug_jals_0_T_2; // @[micro-op.scala:118:34] assign _debug_jals_0_T_2 = _GEN_23; // @[micro-op.scala:118:34] wire _debug_jals_1_T_2; // @[micro-op.scala:118:34] assign _debug_jals_1_T_2 = _GEN_23; // @[micro-op.scala:118:34] wire _debug_jals_2_T_2; // @[micro-op.scala:118:34] assign _debug_jals_2_T_2 = _GEN_23; // @[micro-op.scala:118:34] wire _debug_jals_3_T_2; // @[micro-op.scala:118:34] assign _debug_jals_3_T_2 = _GEN_23; // @[micro-op.scala:118:34] wire _debug_jals_4_T_2; // @[micro-op.scala:118:34] assign _debug_jals_4_T_2 = _GEN_23; // @[micro-op.scala:118:34] wire _debug_jals_0_T_3 = _debug_jals_0_T_1 & _debug_jals_0_T_2; // @[core.scala:326:36, :327:50] wire _debug_jals_0_WIRE_0 = _debug_jals_0_T_3; // @[core.scala:325:54, :327:50] wire _debug_jals_0_T_5 = _rob_io_commit_arch_valids_1 & _debug_jals_0_T_4; // @[core.scala:159:32, :326:36, :327:41] wire _GEN_24 = _rob_io_commit_uops_1_br_type == 4'h7; // @[core.scala:159:32] wire _debug_jals_0_T_6; // @[micro-op.scala:118:34] assign _debug_jals_0_T_6 = _GEN_24; // @[micro-op.scala:118:34] wire _debug_jals_1_T_6; // @[micro-op.scala:118:34] assign _debug_jals_1_T_6 = _GEN_24; // @[micro-op.scala:118:34] wire _debug_jals_2_T_6; // @[micro-op.scala:118:34] assign _debug_jals_2_T_6 = _GEN_24; // @[micro-op.scala:118:34] wire _debug_jals_3_T_6; // @[micro-op.scala:118:34] assign _debug_jals_3_T_6 = _GEN_24; // @[micro-op.scala:118:34] wire _debug_jals_4_T_6; // @[micro-op.scala:118:34] assign _debug_jals_4_T_6 = _GEN_24; // @[micro-op.scala:118:34] wire _debug_jals_0_T_7 = _debug_jals_0_T_5 & _debug_jals_0_T_6; // @[core.scala:326:36, :327:50] wire _debug_jals_0_WIRE_1 = _debug_jals_0_T_7; // @[core.scala:325:54, :327:50] wire [1:0] _debug_jals_0_T_8 = {1'h0, _debug_jals_0_WIRE_0} + {1'h0, _debug_jals_0_WIRE_1}; // @[core.scala:325:{46,54}] wire [1:0] _debug_jals_0_T_9 = _debug_jals_0_T_8; // @[core.scala:325:46] wire [64:0] _debug_jals_0_T_10 = {1'h0, debug_jals_0} + {63'h0, _debug_jals_0_T_9}; // @[core.scala:316:30, :320:34, :325:{36,46}] wire [63:0] _debug_jals_0_T_11 = _debug_jals_0_T_10[63:0]; // @[core.scala:325:36] wire _debug_jalrs_0_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_0_T; // @[core.scala:159:32, :331:36, :332:41] wire _GEN_25 = _rob_io_commit_uops_0_br_type == 4'h8; // @[core.scala:159:32] wire _debug_jalrs_0_T_2; // @[micro-op.scala:119:34] assign _debug_jalrs_0_T_2 = _GEN_25; // @[micro-op.scala:119:34] wire _debug_jalrs_1_T_2; // @[micro-op.scala:119:34] assign _debug_jalrs_1_T_2 = _GEN_25; // @[micro-op.scala:119:34] wire _debug_jalrs_2_T_2; // @[micro-op.scala:119:34] assign _debug_jalrs_2_T_2 = _GEN_25; // @[micro-op.scala:119:34] wire _debug_jalrs_3_T_2; // @[micro-op.scala:119:34] assign _debug_jalrs_3_T_2 = _GEN_25; // @[micro-op.scala:119:34] wire _debug_jalrs_4_T_2; // @[micro-op.scala:119:34] assign _debug_jalrs_4_T_2 = _GEN_25; // @[micro-op.scala:119:34] wire _debug_jalrs_0_T_3 = _debug_jalrs_0_T_1 & _debug_jalrs_0_T_2; // @[core.scala:331:36, :332:50] wire _debug_jalrs_0_WIRE_0 = _debug_jalrs_0_T_3; // @[core.scala:330:56, :332:50] wire _debug_jalrs_0_T_5 = _rob_io_commit_arch_valids_1 & _debug_jalrs_0_T_4; // @[core.scala:159:32, :331:36, :332:41] wire _GEN_26 = _rob_io_commit_uops_1_br_type == 4'h8; // @[core.scala:159:32] wire _debug_jalrs_0_T_6; // @[micro-op.scala:119:34] assign _debug_jalrs_0_T_6 = _GEN_26; // @[micro-op.scala:119:34] wire _debug_jalrs_1_T_6; // @[micro-op.scala:119:34] assign _debug_jalrs_1_T_6 = _GEN_26; // @[micro-op.scala:119:34] wire _debug_jalrs_2_T_6; // @[micro-op.scala:119:34] assign _debug_jalrs_2_T_6 = _GEN_26; // @[micro-op.scala:119:34] wire _debug_jalrs_3_T_6; // @[micro-op.scala:119:34] assign _debug_jalrs_3_T_6 = _GEN_26; // @[micro-op.scala:119:34] wire _debug_jalrs_4_T_6; // @[micro-op.scala:119:34] assign _debug_jalrs_4_T_6 = _GEN_26; // @[micro-op.scala:119:34] wire _debug_jalrs_0_T_7 = _debug_jalrs_0_T_5 & _debug_jalrs_0_T_6; // @[core.scala:331:36, :332:50] wire _debug_jalrs_0_WIRE_1 = _debug_jalrs_0_T_7; // @[core.scala:330:56, :332:50] wire [1:0] _debug_jalrs_0_T_8 = {1'h0, _debug_jalrs_0_WIRE_0} + {1'h0, _debug_jalrs_0_WIRE_1}; // @[core.scala:330:{48,56}] wire [1:0] _debug_jalrs_0_T_9 = _debug_jalrs_0_T_8; // @[core.scala:330:48] wire [64:0] _debug_jalrs_0_T_10 = {1'h0, debug_jalrs_0} + {63'h0, _debug_jalrs_0_T_9}; // @[core.scala:317:30, :320:34, :330:{38,48}] wire [63:0] _debug_jalrs_0_T_11 = _debug_jalrs_0_T_10[63:0]; // @[core.scala:330:38] wire _GEN_27 = _rob_io_commit_uops_0_debug_fsrc == 3'h1; // @[core.scala:159:32, :322:41] wire _debug_brs_1_T; // @[core.scala:322:41] assign _debug_brs_1_T = _GEN_27; // @[core.scala:322:41] wire _debug_jals_1_T; // @[core.scala:327:41] assign _debug_jals_1_T = _GEN_27; // @[core.scala:322:41, :327:41] wire _debug_jalrs_1_T; // @[core.scala:332:41] assign _debug_jalrs_1_T = _GEN_27; // @[core.scala:322:41, :332:41] wire _debug_brs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_1_T; // @[core.scala:159:32, :321:36, :322:41] wire _debug_brs_1_T_8 = _debug_brs_1_T_2 | _debug_brs_1_T_3; // @[package.scala:16:47, :81:59] wire _debug_brs_1_T_9 = _debug_brs_1_T_8 | _debug_brs_1_T_4; // @[package.scala:16:47, :81:59] wire _debug_brs_1_T_10 = _debug_brs_1_T_9 | _debug_brs_1_T_5; // @[package.scala:16:47, :81:59] wire _debug_brs_1_T_11 = _debug_brs_1_T_10 | _debug_brs_1_T_6; // @[package.scala:16:47, :81:59] wire _debug_brs_1_T_12 = _debug_brs_1_T_11 | _debug_brs_1_T_7; // @[package.scala:16:47, :81:59] wire _debug_brs_1_T_13 = _debug_brs_1_T_1 & _debug_brs_1_T_12; // @[package.scala:81:59] wire _debug_brs_1_WIRE_0 = _debug_brs_1_T_13; // @[core.scala:320:52, :322:50] wire _GEN_28 = _rob_io_commit_uops_1_debug_fsrc == 3'h1; // @[core.scala:159:32, :322:41] wire _debug_brs_1_T_14; // @[core.scala:322:41] assign _debug_brs_1_T_14 = _GEN_28; // @[core.scala:322:41] wire _debug_jals_1_T_4; // @[core.scala:327:41] assign _debug_jals_1_T_4 = _GEN_28; // @[core.scala:322:41, :327:41] wire _debug_jalrs_1_T_4; // @[core.scala:332:41] assign _debug_jalrs_1_T_4 = _GEN_28; // @[core.scala:322:41, :332:41] wire _debug_brs_1_T_15 = _rob_io_commit_arch_valids_1 & _debug_brs_1_T_14; // @[core.scala:159:32, :321:36, :322:41] wire _debug_brs_1_T_22 = _debug_brs_1_T_16 | _debug_brs_1_T_17; // @[package.scala:16:47, :81:59] wire _debug_brs_1_T_23 = _debug_brs_1_T_22 | _debug_brs_1_T_18; // @[package.scala:16:47, :81:59] wire _debug_brs_1_T_24 = _debug_brs_1_T_23 | _debug_brs_1_T_19; // @[package.scala:16:47, :81:59] wire _debug_brs_1_T_25 = _debug_brs_1_T_24 | _debug_brs_1_T_20; // @[package.scala:16:47, :81:59] wire _debug_brs_1_T_26 = _debug_brs_1_T_25 | _debug_brs_1_T_21; // @[package.scala:16:47, :81:59] wire _debug_brs_1_T_27 = _debug_brs_1_T_15 & _debug_brs_1_T_26; // @[package.scala:81:59] wire _debug_brs_1_WIRE_1 = _debug_brs_1_T_27; // @[core.scala:320:52, :322:50] wire [1:0] _debug_brs_1_T_28 = {1'h0, _debug_brs_1_WIRE_0} + {1'h0, _debug_brs_1_WIRE_1}; // @[core.scala:320:{44,52}] wire [1:0] _debug_brs_1_T_29 = _debug_brs_1_T_28; // @[core.scala:320:44] wire [64:0] _debug_brs_1_T_30 = {1'h0, debug_brs_1} + {63'h0, _debug_brs_1_T_29}; // @[core.scala:315:30, :320:{34,44}] wire [63:0] _debug_brs_1_T_31 = _debug_brs_1_T_30[63:0]; // @[core.scala:320:34] wire _debug_jals_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_1_T; // @[core.scala:159:32, :326:36, :327:41] wire _debug_jals_1_T_3 = _debug_jals_1_T_1 & _debug_jals_1_T_2; // @[core.scala:326:36, :327:50] wire _debug_jals_1_WIRE_0 = _debug_jals_1_T_3; // @[core.scala:325:54, :327:50] wire _debug_jals_1_T_5 = _rob_io_commit_arch_valids_1 & _debug_jals_1_T_4; // @[core.scala:159:32, :326:36, :327:41] wire _debug_jals_1_T_7 = _debug_jals_1_T_5 & _debug_jals_1_T_6; // @[core.scala:326:36, :327:50] wire _debug_jals_1_WIRE_1 = _debug_jals_1_T_7; // @[core.scala:325:54, :327:50] wire [1:0] _debug_jals_1_T_8 = {1'h0, _debug_jals_1_WIRE_0} + {1'h0, _debug_jals_1_WIRE_1}; // @[core.scala:325:{46,54}] wire [1:0] _debug_jals_1_T_9 = _debug_jals_1_T_8; // @[core.scala:325:46] wire [64:0] _debug_jals_1_T_10 = {1'h0, debug_jals_1} + {63'h0, _debug_jals_1_T_9}; // @[core.scala:316:30, :320:34, :325:{36,46}] wire [63:0] _debug_jals_1_T_11 = _debug_jals_1_T_10[63:0]; // @[core.scala:325:36] wire _debug_jalrs_1_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_1_T; // @[core.scala:159:32, :331:36, :332:41] wire _debug_jalrs_1_T_3 = _debug_jalrs_1_T_1 & _debug_jalrs_1_T_2; // @[core.scala:331:36, :332:50] wire _debug_jalrs_1_WIRE_0 = _debug_jalrs_1_T_3; // @[core.scala:330:56, :332:50] wire _debug_jalrs_1_T_5 = _rob_io_commit_arch_valids_1 & _debug_jalrs_1_T_4; // @[core.scala:159:32, :331:36, :332:41] wire _debug_jalrs_1_T_7 = _debug_jalrs_1_T_5 & _debug_jalrs_1_T_6; // @[core.scala:331:36, :332:50] wire _debug_jalrs_1_WIRE_1 = _debug_jalrs_1_T_7; // @[core.scala:330:56, :332:50] wire [1:0] _debug_jalrs_1_T_8 = {1'h0, _debug_jalrs_1_WIRE_0} + {1'h0, _debug_jalrs_1_WIRE_1}; // @[core.scala:330:{48,56}] wire [1:0] _debug_jalrs_1_T_9 = _debug_jalrs_1_T_8; // @[core.scala:330:48] wire [64:0] _debug_jalrs_1_T_10 = {1'h0, debug_jalrs_1} + {63'h0, _debug_jalrs_1_T_9}; // @[core.scala:317:30, :320:34, :330:{38,48}] wire [63:0] _debug_jalrs_1_T_11 = _debug_jalrs_1_T_10[63:0]; // @[core.scala:330:38] wire _GEN_29 = _rob_io_commit_uops_0_debug_fsrc == 3'h2; // @[core.scala:159:32, :322:41] wire _debug_brs_2_T; // @[core.scala:322:41] assign _debug_brs_2_T = _GEN_29; // @[core.scala:322:41] wire _debug_jals_2_T; // @[core.scala:327:41] assign _debug_jals_2_T = _GEN_29; // @[core.scala:322:41, :327:41] wire _debug_jalrs_2_T; // @[core.scala:332:41] assign _debug_jalrs_2_T = _GEN_29; // @[core.scala:322:41, :332:41] wire _debug_brs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_2_T; // @[core.scala:159:32, :321:36, :322:41] wire _debug_brs_2_T_8 = _debug_brs_2_T_2 | _debug_brs_2_T_3; // @[package.scala:16:47, :81:59] wire _debug_brs_2_T_9 = _debug_brs_2_T_8 | _debug_brs_2_T_4; // @[package.scala:16:47, :81:59] wire _debug_brs_2_T_10 = _debug_brs_2_T_9 | _debug_brs_2_T_5; // @[package.scala:16:47, :81:59] wire _debug_brs_2_T_11 = _debug_brs_2_T_10 | _debug_brs_2_T_6; // @[package.scala:16:47, :81:59] wire _debug_brs_2_T_12 = _debug_brs_2_T_11 | _debug_brs_2_T_7; // @[package.scala:16:47, :81:59] wire _debug_brs_2_T_13 = _debug_brs_2_T_1 & _debug_brs_2_T_12; // @[package.scala:81:59] wire _debug_brs_2_WIRE_0 = _debug_brs_2_T_13; // @[core.scala:320:52, :322:50] wire _GEN_30 = _rob_io_commit_uops_1_debug_fsrc == 3'h2; // @[core.scala:159:32, :322:41] wire _debug_brs_2_T_14; // @[core.scala:322:41] assign _debug_brs_2_T_14 = _GEN_30; // @[core.scala:322:41] wire _debug_jals_2_T_4; // @[core.scala:327:41] assign _debug_jals_2_T_4 = _GEN_30; // @[core.scala:322:41, :327:41] wire _debug_jalrs_2_T_4; // @[core.scala:332:41] assign _debug_jalrs_2_T_4 = _GEN_30; // @[core.scala:322:41, :332:41] wire _debug_brs_2_T_15 = _rob_io_commit_arch_valids_1 & _debug_brs_2_T_14; // @[core.scala:159:32, :321:36, :322:41] wire _debug_brs_2_T_22 = _debug_brs_2_T_16 | _debug_brs_2_T_17; // @[package.scala:16:47, :81:59] wire _debug_brs_2_T_23 = _debug_brs_2_T_22 | _debug_brs_2_T_18; // @[package.scala:16:47, :81:59] wire _debug_brs_2_T_24 = _debug_brs_2_T_23 | _debug_brs_2_T_19; // @[package.scala:16:47, :81:59] wire _debug_brs_2_T_25 = _debug_brs_2_T_24 | _debug_brs_2_T_20; // @[package.scala:16:47, :81:59] wire _debug_brs_2_T_26 = _debug_brs_2_T_25 | _debug_brs_2_T_21; // @[package.scala:16:47, :81:59] wire _debug_brs_2_T_27 = _debug_brs_2_T_15 & _debug_brs_2_T_26; // @[package.scala:81:59] wire _debug_brs_2_WIRE_1 = _debug_brs_2_T_27; // @[core.scala:320:52, :322:50] wire [1:0] _debug_brs_2_T_28 = {1'h0, _debug_brs_2_WIRE_0} + {1'h0, _debug_brs_2_WIRE_1}; // @[core.scala:320:{44,52}] wire [1:0] _debug_brs_2_T_29 = _debug_brs_2_T_28; // @[core.scala:320:44] wire [64:0] _debug_brs_2_T_30 = {1'h0, debug_brs_2} + {63'h0, _debug_brs_2_T_29}; // @[core.scala:315:30, :320:{34,44}] wire [63:0] _debug_brs_2_T_31 = _debug_brs_2_T_30[63:0]; // @[core.scala:320:34] wire _debug_jals_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_2_T; // @[core.scala:159:32, :326:36, :327:41] wire _debug_jals_2_T_3 = _debug_jals_2_T_1 & _debug_jals_2_T_2; // @[core.scala:326:36, :327:50] wire _debug_jals_2_WIRE_0 = _debug_jals_2_T_3; // @[core.scala:325:54, :327:50] wire _debug_jals_2_T_5 = _rob_io_commit_arch_valids_1 & _debug_jals_2_T_4; // @[core.scala:159:32, :326:36, :327:41] wire _debug_jals_2_T_7 = _debug_jals_2_T_5 & _debug_jals_2_T_6; // @[core.scala:326:36, :327:50] wire _debug_jals_2_WIRE_1 = _debug_jals_2_T_7; // @[core.scala:325:54, :327:50] wire [1:0] _debug_jals_2_T_8 = {1'h0, _debug_jals_2_WIRE_0} + {1'h0, _debug_jals_2_WIRE_1}; // @[core.scala:325:{46,54}] wire [1:0] _debug_jals_2_T_9 = _debug_jals_2_T_8; // @[core.scala:325:46] wire [64:0] _debug_jals_2_T_10 = {1'h0, debug_jals_2} + {63'h0, _debug_jals_2_T_9}; // @[core.scala:316:30, :320:34, :325:{36,46}] wire [63:0] _debug_jals_2_T_11 = _debug_jals_2_T_10[63:0]; // @[core.scala:325:36] wire _debug_jalrs_2_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_2_T; // @[core.scala:159:32, :331:36, :332:41] wire _debug_jalrs_2_T_3 = _debug_jalrs_2_T_1 & _debug_jalrs_2_T_2; // @[core.scala:331:36, :332:50] wire _debug_jalrs_2_WIRE_0 = _debug_jalrs_2_T_3; // @[core.scala:330:56, :332:50] wire _debug_jalrs_2_T_5 = _rob_io_commit_arch_valids_1 & _debug_jalrs_2_T_4; // @[core.scala:159:32, :331:36, :332:41] wire _debug_jalrs_2_T_7 = _debug_jalrs_2_T_5 & _debug_jalrs_2_T_6; // @[core.scala:331:36, :332:50] wire _debug_jalrs_2_WIRE_1 = _debug_jalrs_2_T_7; // @[core.scala:330:56, :332:50] wire [1:0] _debug_jalrs_2_T_8 = {1'h0, _debug_jalrs_2_WIRE_0} + {1'h0, _debug_jalrs_2_WIRE_1}; // @[core.scala:330:{48,56}] wire [1:0] _debug_jalrs_2_T_9 = _debug_jalrs_2_T_8; // @[core.scala:330:48] wire [64:0] _debug_jalrs_2_T_10 = {1'h0, debug_jalrs_2} + {63'h0, _debug_jalrs_2_T_9}; // @[core.scala:317:30, :320:34, :330:{38,48}] wire [63:0] _debug_jalrs_2_T_11 = _debug_jalrs_2_T_10[63:0]; // @[core.scala:330:38] wire _GEN_31 = _rob_io_commit_uops_0_debug_fsrc == 3'h3; // @[core.scala:159:32, :322:41] wire _debug_brs_3_T; // @[core.scala:322:41] assign _debug_brs_3_T = _GEN_31; // @[core.scala:322:41] wire _debug_jals_3_T; // @[core.scala:327:41] assign _debug_jals_3_T = _GEN_31; // @[core.scala:322:41, :327:41] wire _debug_jalrs_3_T; // @[core.scala:332:41] assign _debug_jalrs_3_T = _GEN_31; // @[core.scala:322:41, :332:41] wire _debug_brs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_3_T; // @[core.scala:159:32, :321:36, :322:41] wire _debug_brs_3_T_8 = _debug_brs_3_T_2 | _debug_brs_3_T_3; // @[package.scala:16:47, :81:59] wire _debug_brs_3_T_9 = _debug_brs_3_T_8 | _debug_brs_3_T_4; // @[package.scala:16:47, :81:59] wire _debug_brs_3_T_10 = _debug_brs_3_T_9 | _debug_brs_3_T_5; // @[package.scala:16:47, :81:59] wire _debug_brs_3_T_11 = _debug_brs_3_T_10 | _debug_brs_3_T_6; // @[package.scala:16:47, :81:59] wire _debug_brs_3_T_12 = _debug_brs_3_T_11 | _debug_brs_3_T_7; // @[package.scala:16:47, :81:59] wire _debug_brs_3_T_13 = _debug_brs_3_T_1 & _debug_brs_3_T_12; // @[package.scala:81:59] wire _debug_brs_3_WIRE_0 = _debug_brs_3_T_13; // @[core.scala:320:52, :322:50] wire _GEN_32 = _rob_io_commit_uops_1_debug_fsrc == 3'h3; // @[core.scala:159:32, :322:41] wire _debug_brs_3_T_14; // @[core.scala:322:41] assign _debug_brs_3_T_14 = _GEN_32; // @[core.scala:322:41] wire _debug_jals_3_T_4; // @[core.scala:327:41] assign _debug_jals_3_T_4 = _GEN_32; // @[core.scala:322:41, :327:41] wire _debug_jalrs_3_T_4; // @[core.scala:332:41] assign _debug_jalrs_3_T_4 = _GEN_32; // @[core.scala:322:41, :332:41] wire _debug_brs_3_T_15 = _rob_io_commit_arch_valids_1 & _debug_brs_3_T_14; // @[core.scala:159:32, :321:36, :322:41] wire _debug_brs_3_T_22 = _debug_brs_3_T_16 | _debug_brs_3_T_17; // @[package.scala:16:47, :81:59] wire _debug_brs_3_T_23 = _debug_brs_3_T_22 | _debug_brs_3_T_18; // @[package.scala:16:47, :81:59] wire _debug_brs_3_T_24 = _debug_brs_3_T_23 | _debug_brs_3_T_19; // @[package.scala:16:47, :81:59] wire _debug_brs_3_T_25 = _debug_brs_3_T_24 | _debug_brs_3_T_20; // @[package.scala:16:47, :81:59] wire _debug_brs_3_T_26 = _debug_brs_3_T_25 | _debug_brs_3_T_21; // @[package.scala:16:47, :81:59] wire _debug_brs_3_T_27 = _debug_brs_3_T_15 & _debug_brs_3_T_26; // @[package.scala:81:59] wire _debug_brs_3_WIRE_1 = _debug_brs_3_T_27; // @[core.scala:320:52, :322:50] wire [1:0] _debug_brs_3_T_28 = {1'h0, _debug_brs_3_WIRE_0} + {1'h0, _debug_brs_3_WIRE_1}; // @[core.scala:320:{44,52}] wire [1:0] _debug_brs_3_T_29 = _debug_brs_3_T_28; // @[core.scala:320:44] wire [64:0] _debug_brs_3_T_30 = {1'h0, debug_brs_3} + {63'h0, _debug_brs_3_T_29}; // @[core.scala:315:30, :320:{34,44}] wire [63:0] _debug_brs_3_T_31 = _debug_brs_3_T_30[63:0]; // @[core.scala:320:34] wire _debug_jals_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_3_T; // @[core.scala:159:32, :326:36, :327:41] wire _debug_jals_3_T_3 = _debug_jals_3_T_1 & _debug_jals_3_T_2; // @[core.scala:326:36, :327:50] wire _debug_jals_3_WIRE_0 = _debug_jals_3_T_3; // @[core.scala:325:54, :327:50] wire _debug_jals_3_T_5 = _rob_io_commit_arch_valids_1 & _debug_jals_3_T_4; // @[core.scala:159:32, :326:36, :327:41] wire _debug_jals_3_T_7 = _debug_jals_3_T_5 & _debug_jals_3_T_6; // @[core.scala:326:36, :327:50] wire _debug_jals_3_WIRE_1 = _debug_jals_3_T_7; // @[core.scala:325:54, :327:50] wire [1:0] _debug_jals_3_T_8 = {1'h0, _debug_jals_3_WIRE_0} + {1'h0, _debug_jals_3_WIRE_1}; // @[core.scala:325:{46,54}] wire [1:0] _debug_jals_3_T_9 = _debug_jals_3_T_8; // @[core.scala:325:46] wire [64:0] _debug_jals_3_T_10 = {1'h0, debug_jals_3} + {63'h0, _debug_jals_3_T_9}; // @[core.scala:316:30, :320:34, :325:{36,46}] wire [63:0] _debug_jals_3_T_11 = _debug_jals_3_T_10[63:0]; // @[core.scala:325:36] wire _debug_jalrs_3_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_3_T; // @[core.scala:159:32, :331:36, :332:41] wire _debug_jalrs_3_T_3 = _debug_jalrs_3_T_1 & _debug_jalrs_3_T_2; // @[core.scala:331:36, :332:50] wire _debug_jalrs_3_WIRE_0 = _debug_jalrs_3_T_3; // @[core.scala:330:56, :332:50] wire _debug_jalrs_3_T_5 = _rob_io_commit_arch_valids_1 & _debug_jalrs_3_T_4; // @[core.scala:159:32, :331:36, :332:41] wire _debug_jalrs_3_T_7 = _debug_jalrs_3_T_5 & _debug_jalrs_3_T_6; // @[core.scala:331:36, :332:50] wire _debug_jalrs_3_WIRE_1 = _debug_jalrs_3_T_7; // @[core.scala:330:56, :332:50] wire [1:0] _debug_jalrs_3_T_8 = {1'h0, _debug_jalrs_3_WIRE_0} + {1'h0, _debug_jalrs_3_WIRE_1}; // @[core.scala:330:{48,56}] wire [1:0] _debug_jalrs_3_T_9 = _debug_jalrs_3_T_8; // @[core.scala:330:48] wire [64:0] _debug_jalrs_3_T_10 = {1'h0, debug_jalrs_3} + {63'h0, _debug_jalrs_3_T_9}; // @[core.scala:317:30, :320:34, :330:{38,48}] wire [63:0] _debug_jalrs_3_T_11 = _debug_jalrs_3_T_10[63:0]; // @[core.scala:330:38] wire _GEN_33 = _rob_io_commit_uops_0_debug_fsrc == 3'h4; // @[core.scala:159:32, :322:41] wire _debug_brs_4_T; // @[core.scala:322:41] assign _debug_brs_4_T = _GEN_33; // @[core.scala:322:41] wire _debug_jals_4_T; // @[core.scala:327:41] assign _debug_jals_4_T = _GEN_33; // @[core.scala:322:41, :327:41] wire _debug_jalrs_4_T; // @[core.scala:332:41] assign _debug_jalrs_4_T = _GEN_33; // @[core.scala:322:41, :332:41] wire _debug_brs_4_T_1 = _rob_io_commit_arch_valids_0 & _debug_brs_4_T; // @[core.scala:159:32, :321:36, :322:41] wire _debug_brs_4_T_8 = _debug_brs_4_T_2 | _debug_brs_4_T_3; // @[package.scala:16:47, :81:59] wire _debug_brs_4_T_9 = _debug_brs_4_T_8 | _debug_brs_4_T_4; // @[package.scala:16:47, :81:59] wire _debug_brs_4_T_10 = _debug_brs_4_T_9 | _debug_brs_4_T_5; // @[package.scala:16:47, :81:59] wire _debug_brs_4_T_11 = _debug_brs_4_T_10 | _debug_brs_4_T_6; // @[package.scala:16:47, :81:59] wire _debug_brs_4_T_12 = _debug_brs_4_T_11 | _debug_brs_4_T_7; // @[package.scala:16:47, :81:59] wire _debug_brs_4_T_13 = _debug_brs_4_T_1 & _debug_brs_4_T_12; // @[package.scala:81:59] wire _debug_brs_4_WIRE_0 = _debug_brs_4_T_13; // @[core.scala:320:52, :322:50] wire _GEN_34 = _rob_io_commit_uops_1_debug_fsrc == 3'h4; // @[core.scala:159:32, :322:41] wire _debug_brs_4_T_14; // @[core.scala:322:41] assign _debug_brs_4_T_14 = _GEN_34; // @[core.scala:322:41] wire _debug_jals_4_T_4; // @[core.scala:327:41] assign _debug_jals_4_T_4 = _GEN_34; // @[core.scala:322:41, :327:41] wire _debug_jalrs_4_T_4; // @[core.scala:332:41] assign _debug_jalrs_4_T_4 = _GEN_34; // @[core.scala:322:41, :332:41] wire _debug_brs_4_T_15 = _rob_io_commit_arch_valids_1 & _debug_brs_4_T_14; // @[core.scala:159:32, :321:36, :322:41] wire _debug_brs_4_T_22 = _debug_brs_4_T_16 | _debug_brs_4_T_17; // @[package.scala:16:47, :81:59] wire _debug_brs_4_T_23 = _debug_brs_4_T_22 | _debug_brs_4_T_18; // @[package.scala:16:47, :81:59] wire _debug_brs_4_T_24 = _debug_brs_4_T_23 | _debug_brs_4_T_19; // @[package.scala:16:47, :81:59] wire _debug_brs_4_T_25 = _debug_brs_4_T_24 | _debug_brs_4_T_20; // @[package.scala:16:47, :81:59] wire _debug_brs_4_T_26 = _debug_brs_4_T_25 | _debug_brs_4_T_21; // @[package.scala:16:47, :81:59] wire _debug_brs_4_T_27 = _debug_brs_4_T_15 & _debug_brs_4_T_26; // @[package.scala:81:59] wire _debug_brs_4_WIRE_1 = _debug_brs_4_T_27; // @[core.scala:320:52, :322:50] wire [1:0] _debug_brs_4_T_28 = {1'h0, _debug_brs_4_WIRE_0} + {1'h0, _debug_brs_4_WIRE_1}; // @[core.scala:320:{44,52}] wire [1:0] _debug_brs_4_T_29 = _debug_brs_4_T_28; // @[core.scala:320:44] wire [64:0] _debug_brs_4_T_30 = {1'h0, debug_brs_4} + {63'h0, _debug_brs_4_T_29}; // @[core.scala:315:30, :320:{34,44}] wire [63:0] _debug_brs_4_T_31 = _debug_brs_4_T_30[63:0]; // @[core.scala:320:34] wire _debug_jals_4_T_1 = _rob_io_commit_arch_valids_0 & _debug_jals_4_T; // @[core.scala:159:32, :326:36, :327:41] wire _debug_jals_4_T_3 = _debug_jals_4_T_1 & _debug_jals_4_T_2; // @[core.scala:326:36, :327:50] wire _debug_jals_4_WIRE_0 = _debug_jals_4_T_3; // @[core.scala:325:54, :327:50] wire _debug_jals_4_T_5 = _rob_io_commit_arch_valids_1 & _debug_jals_4_T_4; // @[core.scala:159:32, :326:36, :327:41] wire _debug_jals_4_T_7 = _debug_jals_4_T_5 & _debug_jals_4_T_6; // @[core.scala:326:36, :327:50] wire _debug_jals_4_WIRE_1 = _debug_jals_4_T_7; // @[core.scala:325:54, :327:50] wire [1:0] _debug_jals_4_T_8 = {1'h0, _debug_jals_4_WIRE_0} + {1'h0, _debug_jals_4_WIRE_1}; // @[core.scala:325:{46,54}] wire [1:0] _debug_jals_4_T_9 = _debug_jals_4_T_8; // @[core.scala:325:46] wire [64:0] _debug_jals_4_T_10 = {1'h0, debug_jals_4} + {63'h0, _debug_jals_4_T_9}; // @[core.scala:316:30, :320:34, :325:{36,46}] wire [63:0] _debug_jals_4_T_11 = _debug_jals_4_T_10[63:0]; // @[core.scala:325:36] wire _debug_jalrs_4_T_1 = _rob_io_commit_arch_valids_0 & _debug_jalrs_4_T; // @[core.scala:159:32, :331:36, :332:41] wire _debug_jalrs_4_T_3 = _debug_jalrs_4_T_1 & _debug_jalrs_4_T_2; // @[core.scala:331:36, :332:50] wire _debug_jalrs_4_WIRE_0 = _debug_jalrs_4_T_3; // @[core.scala:330:56, :332:50] wire _debug_jalrs_4_T_5 = _rob_io_commit_arch_valids_1 & _debug_jalrs_4_T_4; // @[core.scala:159:32, :331:36, :332:41] wire _debug_jalrs_4_T_7 = _debug_jalrs_4_T_5 & _debug_jalrs_4_T_6; // @[core.scala:331:36, :332:50] wire _debug_jalrs_4_WIRE_1 = _debug_jalrs_4_T_7; // @[core.scala:330:56, :332:50] wire [1:0] _debug_jalrs_4_T_8 = {1'h0, _debug_jalrs_4_WIRE_0} + {1'h0, _debug_jalrs_4_WIRE_1}; // @[core.scala:330:{48,56}] wire [1:0] _debug_jalrs_4_T_9 = _debug_jalrs_4_T_8; // @[core.scala:330:48] wire [64:0] _debug_jalrs_4_T_10 = {1'h0, debug_jalrs_4} + {63'h0, _debug_jalrs_4_T_9}; // @[core.scala:317:30, :320:34, :330:{38,48}] wire [63:0] _debug_jalrs_4_T_11 = _debug_jalrs_4_T_10[63:0]; // @[core.scala:330:38] wire [64:0] _debug_tsc_reg_T = {1'h0, debug_tsc_reg} + 65'h1; // @[core.scala:313:30, :341:34] wire [63:0] _debug_tsc_reg_T_1 = _debug_tsc_reg_T[63:0]; // @[core.scala:341:34] wire [1:0] _GEN_35 = {_rob_io_commit_arch_valids_1, _rob_io_commit_arch_valids_0}; // @[core.scala:159:32, :342:71] wire [1:0] _debug_irt_reg_T; // @[core.scala:342:71] assign _debug_irt_reg_T = _GEN_35; // @[core.scala:342:71] wire [1:0] _csr_io_retire_T; // @[core.scala:1113:66] assign _csr_io_retire_T = _GEN_35; // @[core.scala:342:71, :1113:66] wire _debug_irt_reg_T_1 = _debug_irt_reg_T[0]; // @[core.scala:342:{44,71}] wire _debug_irt_reg_T_2 = _debug_irt_reg_T[1]; // @[core.scala:342:{44,71}] wire [1:0] _debug_irt_reg_T_3 = {1'h0, _debug_irt_reg_T_1} + {1'h0, _debug_irt_reg_T_2}; // @[core.scala:342:44] wire [1:0] _debug_irt_reg_T_4 = _debug_irt_reg_T_3; // @[core.scala:342:44] wire [64:0] _debug_irt_reg_T_5 = {1'h0, debug_irt_reg} + {63'h0, _debug_irt_reg_T_4}; // @[core.scala:314:30, :320:34, :342:{34,44}] wire [63:0] _debug_irt_reg_T_6 = _debug_irt_reg_T_5[63:0]; // @[core.scala:342:34] wire _io_ifu_flush_icache_T = _rob_io_commit_arch_valids_0 & _rob_io_commit_uops_0_is_fencei; // @[core.scala:159:32, :408:35] wire _GEN_36 = dec_uops_0_br_type == 4'h8; // @[core.scala:181:24] wire _io_ifu_flush_icache_T_1; // @[micro-op.scala:119:34] assign _io_ifu_flush_icache_T_1 = _GEN_36; // @[micro-op.scala:119:34] wire _dec_brmask_logic_io_is_branch_0_T_15; // @[micro-op.scala:119:34] assign _dec_brmask_logic_io_is_branch_0_T_15 = _GEN_36; // @[micro-op.scala:119:34] wire _dec_brmask_logic_io_will_fire_0_T_13; // @[micro-op.scala:119:34] assign _dec_brmask_logic_io_will_fire_0_T_13 = _GEN_36; // @[micro-op.scala:119:34] wire _io_ifu_flush_icache_T_2 = dec_valids_0 & _io_ifu_flush_icache_T_1; // @[core.scala:180:24, :409:28] wire _io_ifu_flush_icache_T_3 = _io_ifu_flush_icache_T_2 & _csr_io_status_debug; // @[core.scala:294:19, :409:{28,51}] reg io_ifu_flush_icache_REG; // @[core.scala:409:13] wire _io_ifu_flush_icache_T_4 = _io_ifu_flush_icache_T | io_ifu_flush_icache_REG; // @[core.scala:408:{35,71}, :409:13] wire _io_ifu_flush_icache_T_5 = _rob_io_commit_arch_valids_1 & _rob_io_commit_uops_1_is_fencei; // @[core.scala:159:32, :408:35] wire _GEN_37 = dec_uops_1_br_type == 4'h8; // @[core.scala:181:24] wire _io_ifu_flush_icache_T_6; // @[micro-op.scala:119:34] assign _io_ifu_flush_icache_T_6 = _GEN_37; // @[micro-op.scala:119:34] wire _dec_brmask_logic_io_is_branch_1_T_15; // @[micro-op.scala:119:34] assign _dec_brmask_logic_io_is_branch_1_T_15 = _GEN_37; // @[micro-op.scala:119:34] wire _dec_brmask_logic_io_will_fire_1_T_13; // @[micro-op.scala:119:34] assign _dec_brmask_logic_io_will_fire_1_T_13 = _GEN_37; // @[micro-op.scala:119:34] wire _io_ifu_flush_icache_T_7 = dec_valids_1 & _io_ifu_flush_icache_T_6; // @[core.scala:180:24, :409:28] wire _io_ifu_flush_icache_T_8 = _io_ifu_flush_icache_T_7 & _csr_io_status_debug; // @[core.scala:294:19, :409:{28,51}] reg io_ifu_flush_icache_REG_1; // @[core.scala:409:13] wire _io_ifu_flush_icache_T_9 = _io_ifu_flush_icache_T_5 | io_ifu_flush_icache_REG_1; // @[core.scala:408:{35,71}, :409:13] assign _io_ifu_flush_icache_T_10 = _io_ifu_flush_icache_T_4 | _io_ifu_flush_icache_T_9; // @[core.scala:408:71, :410:13] assign io_ifu_flush_icache_0 = _io_ifu_flush_icache_T_10; // @[core.scala:50:7, :410:13] reg REG; // @[core.scala:421:16] reg [2:0] flush_typ; // @[core.scala:424:28] wire _io_ifu_redirect_pc_T = flush_typ == 3'h3; // @[core.scala:424:28, :431:44] reg [39:0] io_ifu_redirect_pc_r; // @[core.scala:432:47] reg [39:0] io_ifu_redirect_pc_r_1; // @[core.scala:432:47] reg [39:0] io_ifu_redirect_pc_r_2; // @[core.scala:432:47] wire [39:0] _io_ifu_redirect_pc_T_1 = _io_ifu_redirect_pc_T ? io_ifu_redirect_pc_r_2 : _csr_io_evec; // @[core.scala:294:19, :431:{33,44}, :432:47] wire [39:0] _flush_pc_T = ~io_ifu_rrd_ftq_resps_0_pc_0; // @[util.scala:245:7] wire [39:0] _flush_pc_T_1 = {_flush_pc_T[39:6], 6'h3F}; // @[util.scala:245:{7,11}] wire [39:0] _flush_pc_T_2 = ~_flush_pc_T_1; // @[util.scala:245:{5,11}] reg [5:0] flush_pc_REG; // @[core.scala:436:32] wire [40:0] _flush_pc_T_3 = {1'h0, _flush_pc_T_2} + {35'h0, flush_pc_REG}; // @[util.scala:245:5] wire [39:0] _flush_pc_T_4 = _flush_pc_T_3[39:0]; // @[core.scala:436:23] reg flush_pc_REG_1; // @[core.scala:437:36] wire [1:0] _flush_pc_T_5 = {flush_pc_REG_1, 1'h0}; // @[core.scala:437:{28,36}] wire [40:0] _flush_pc_T_6 = {1'h0, _flush_pc_T_4} - {39'h0, _flush_pc_T_5}; // @[core.scala:436:23, :437:{23,28}] wire [39:0] flush_pc = _flush_pc_T_6[39:0]; // @[core.scala:437:23] reg flush_pc_next_REG; // @[core.scala:438:49] wire [2:0] _flush_pc_next_T = flush_pc_next_REG ? 3'h2 : 3'h4; // @[core.scala:438:{41,49}] wire [40:0] _flush_pc_next_T_1 = {1'h0, flush_pc} + {38'h0, _flush_pc_next_T}; // @[core.scala:437:23, :438:{36,41}] wire [39:0] flush_pc_next = _flush_pc_next_T_1[39:0]; // @[core.scala:438:36] wire _io_ifu_redirect_pc_T_2 = flush_typ == 3'h2; // @[rob.scala:155:40] wire [39:0] _io_ifu_redirect_pc_T_3 = _io_ifu_redirect_pc_T_2 ? flush_pc : flush_pc_next; // @[rob.scala:155:40] reg [4:0] io_ifu_redirect_ftq_idx_REG; // @[core.scala:443:39] reg REG_1; // @[core.scala:444:50] wire _T_15 = brupdate_b2_mispredict & ~REG_1; // @[core.scala:209:23, :444:{39,42,50}] wire [39:0] _block_pc_T = ~io_ifu_rrd_ftq_resps_0_pc_0; // @[util.scala:245:7] wire [39:0] _block_pc_T_1 = {_block_pc_T[39:6], 6'h3F}; // @[util.scala:245:{7,11}] wire [39:0] block_pc = ~_block_pc_T_1; // @[util.scala:245:{5,11}] wire [39:0] uop_maybe_pc = {block_pc[39:6], block_pc[5:0] | brupdate_b2_uop_pc_lob}; // @[util.scala:245:5] wire [39:0] _jal_br_target_T = uop_maybe_pc; // @[core.scala:446:33, :449:36] wire _npc_T = brupdate_b2_uop_is_rvc | brupdate_b2_uop_edge_inst; // @[core.scala:209:23, :447:57] wire [2:0] _npc_T_1 = _npc_T ? 3'h2 : 3'h4; // @[core.scala:447:{33,57}] wire [40:0] _npc_T_2 = {1'h0, uop_maybe_pc} + {38'h0, _npc_T_1}; // @[core.scala:438:36, :446:33, :447:{28,33}] wire [39:0] npc = _npc_T_2[39:0]; // @[core.scala:447:28] wire [39:0] _jal_br_target_T_10; // @[core.scala:450:75] wire [39:0] jal_br_target; // @[core.scala:448:29] wire [40:0] _jal_br_target_T_1 = {_jal_br_target_T[39], _jal_br_target_T} + {{20{brupdate_b2_target_offset[20]}}, brupdate_b2_target_offset}; // @[core.scala:209:23, :449:{36,43}] wire [39:0] _jal_br_target_T_2 = _jal_br_target_T_1[39:0]; // @[core.scala:449:43] wire [39:0] _jal_br_target_T_3 = _jal_br_target_T_2; // @[core.scala:449:43] wire [38:0] _jal_br_target_T_4 = {39{brupdate_b2_uop_edge_inst}}; // @[core.scala:209:23, :450:12] wire [39:0] _jal_br_target_T_5 = {_jal_br_target_T_4, 1'h0}; // @[core.scala:450:{12,61}] wire [39:0] _jal_br_target_T_6 = _jal_br_target_T_5; // @[core.scala:450:{61,67}] wire [40:0] _jal_br_target_T_7 = {_jal_br_target_T_3[39], _jal_br_target_T_3} + {_jal_br_target_T_6[39], _jal_br_target_T_6}; // @[core.scala:449:{43,71}, :450:67] wire [39:0] _jal_br_target_T_8 = _jal_br_target_T_7[39:0]; // @[core.scala:449:71] wire [39:0] _jal_br_target_T_9 = _jal_br_target_T_8; // @[core.scala:449:71] assign _jal_br_target_T_10 = _jal_br_target_T_9; // @[core.scala:449:71, :450:75] assign jal_br_target = _jal_br_target_T_10; // @[core.scala:448:29, :450:75] wire _bj_addr_T = brupdate_b2_cfi_type == 3'h3; // @[core.scala:209:23, :451:44] wire [39:0] bj_addr = _bj_addr_T ? brupdate_b2_jalr_target : jal_br_target; // @[core.scala:209:23, :448:29, :451:{22,44}] wire _mispredict_target_T = brupdate_b2_pc_sel == 2'h0; // @[core.scala:209:23, :452:52] wire [39:0] mispredict_target = _mispredict_target_T ? npc : bj_addr; // @[core.scala:447:28, :451:22, :452:{32,52}] assign io_ifu_redirect_val_0 = REG | _T_15; // @[core.scala:50:7, :421:{16,38}, :422:27, :444:{39,72}] assign io_ifu_redirect_pc_0 = REG ? (flush_typ[0] ? _io_ifu_redirect_pc_T_1 : _io_ifu_redirect_pc_T_3) : mispredict_target; // @[rob.scala:154:40] assign io_ifu_redirect_ftq_idx_0 = REG ? io_ifu_redirect_ftq_idx_REG : brupdate_b2_uop_ftq_idx; // @[core.scala:50:7, :209:23, :421:{16,38}, :443:{29,39}, :444:72] wire _GEN_38 = brupdate_b2_cfi_type == 3'h1; // @[core.scala:209:23, :457:48] wire _use_same_ghist_T; // @[core.scala:457:48] assign _use_same_ghist_T = _GEN_38; // @[core.scala:457:48] wire _next_ghist_T; // @[core.scala:467:28] assign _next_ghist_T = _GEN_38; // @[core.scala:457:48, :467:28] wire _use_same_ghist_T_1 = ~brupdate_b2_taken; // @[core.scala:209:23, :458:27] wire _use_same_ghist_T_2 = _use_same_ghist_T & _use_same_ghist_T_1; // @[core.scala:457:{48,59}, :458:27] wire [39:0] _use_same_ghist_T_3 = ~block_pc; // @[util.scala:245:5] wire [39:0] _use_same_ghist_T_4 = {_use_same_ghist_T_3[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _use_same_ghist_T_5 = ~_use_same_ghist_T_4; // @[frontend.scala:147:{31,39}] wire [39:0] _use_same_ghist_T_6 = ~npc; // @[frontend.scala:147:33] wire [39:0] _use_same_ghist_T_7 = {_use_same_ghist_T_6[39:3], 3'h7}; // @[frontend.scala:147:{33,39}] wire [39:0] _use_same_ghist_T_8 = ~_use_same_ghist_T_7; // @[frontend.scala:147:{31,39}] wire _use_same_ghist_T_9 = _use_same_ghist_T_5 == _use_same_ghist_T_8; // @[frontend.scala:147:31] wire use_same_ghist = _use_same_ghist_T_2 & _use_same_ghist_T_9; // @[core.scala:457:59, :458:46, :459:47] wire [3:0] _cfi_idx_T_2 = {_cfi_idx_T, 3'h0}; // @[core.scala:462:{10,32}] wire [5:0] _cfi_idx_T_3 = {brupdate_b2_uop_pc_lob[5:4], brupdate_b2_uop_pc_lob[3:0] ^ _cfi_idx_T_2}; // @[core.scala:209:23, :461:43, :462:10] wire [1:0] cfi_idx = _cfi_idx_T_3[2:1]; // @[core.scala:461:43, :462:74] wire [1:0] next_ghist_cfi_idx_fixed = cfi_idx; // @[frontend.scala:72:32] wire _GEN_39 = io_ifu_rrd_ftq_resps_0_entry_cfi_idx_bits_0 == cfi_idx; // @[core.scala:50:7, :462:74, :471:55] wire _next_ghist_T_1; // @[core.scala:471:55] assign _next_ghist_T_1 = _GEN_39; // @[core.scala:471:55] wire _next_ghist_T_3; // @[core.scala:472:55] assign _next_ghist_T_3 = _GEN_39; // @[core.scala:471:55, :472:55] wire _next_ghist_T_2 = io_ifu_rrd_ftq_resps_0_entry_cfi_is_call_0 & _next_ghist_T_1; // @[core.scala:50:7, :471:{29,55}] wire _next_ghist_new_history_ras_idx_T = _next_ghist_T_2; // @[frontend.scala:110:42] wire _next_ghist_T_4 = io_ifu_rrd_ftq_resps_0_entry_cfi_is_ret_0 & _next_ghist_T_3; // @[core.scala:50:7, :472:{29,55}] wire _next_ghist_new_history_ras_idx_T_4 = _next_ghist_T_4; // @[frontend.scala:111:42] wire [3:0] next_ghist_cfi_idx_oh = 4'h1 << next_ghist_cfi_idx_fixed; // @[OneHot.scala:58:35] wire [3:0] _next_ghist_not_taken_branches_T = next_ghist_cfi_idx_oh; // @[OneHot.scala:58:35] wire [4:0] _next_ghist_new_history_ras_idx_T_9; // @[frontend.scala:110:31] wire [63:0] next_ghist_old_history; // @[frontend.scala:74:27] wire [4:0] next_ghist_ras_idx; // @[frontend.scala:74:27] wire [3:0] _next_ghist_not_taken_branches_T_1 = {1'h0, next_ghist_cfi_idx_oh[3:1]}; // @[OneHot.scala:58:35] wire [3:0] _next_ghist_not_taken_branches_T_2 = {2'h0, next_ghist_cfi_idx_oh[3:2]}; // @[OneHot.scala:58:35] wire [3:0] _next_ghist_not_taken_branches_T_3 = {3'h0, next_ghist_cfi_idx_oh[3]}; // @[OneHot.scala:58:35] wire [3:0] _next_ghist_not_taken_branches_T_4 = _next_ghist_not_taken_branches_T | _next_ghist_not_taken_branches_T_1; // @[util.scala:383:{29,45}] wire [3:0] _next_ghist_not_taken_branches_T_5 = _next_ghist_not_taken_branches_T_4 | _next_ghist_not_taken_branches_T_2; // @[util.scala:383:{29,45}] wire [3:0] _next_ghist_not_taken_branches_T_6 = _next_ghist_not_taken_branches_T_5 | _next_ghist_not_taken_branches_T_3; // @[util.scala:383:{29,45}] wire _GEN_40 = _next_ghist_T & brupdate_b2_taken; // @[frontend.scala:77:84] wire _next_ghist_not_taken_branches_T_7; // @[frontend.scala:77:84] assign _next_ghist_not_taken_branches_T_7 = _GEN_40; // @[frontend.scala:77:84] wire _next_ghist_new_history_old_history_T; // @[frontend.scala:85:48] assign _next_ghist_new_history_old_history_T = _GEN_40; // @[frontend.scala:77:84, :85:48] wire [3:0] _next_ghist_not_taken_branches_T_8 = _next_ghist_not_taken_branches_T_7 ? next_ghist_cfi_idx_oh : 4'h0; // @[OneHot.scala:58:35] wire [3:0] _next_ghist_not_taken_branches_T_9 = ~_next_ghist_not_taken_branches_T_8; // @[frontend.scala:77:{69,73}] wire [3:0] _next_ghist_not_taken_branches_T_10 = _next_ghist_not_taken_branches_T_6 & _next_ghist_not_taken_branches_T_9; // @[util.scala:383:45] wire [3:0] _next_ghist_not_taken_branches_T_12 = _next_ghist_not_taken_branches_T_10; // @[frontend.scala:76:44, :77:67] wire [3:0] next_ghist_not_taken_branches = io_ifu_rrd_ftq_resps_0_entry_br_mask_0 & _next_ghist_not_taken_branches_T_12; // @[frontend.scala:76:{39,44}] wire _next_ghist_saw_not_taken_branch_T = |next_ghist_not_taken_branches; // @[frontend.scala:76:39, :84:53] wire next_ghist_saw_not_taken_branch = _next_ghist_saw_not_taken_branch_T | io_ifu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken_0; // @[frontend.scala:84:{53,61}] wire _next_ghist_new_history_old_history_T_1 = _next_ghist_new_history_old_history_T; // @[frontend.scala:85:{48,61}] wire [64:0] _GEN_41 = {io_ifu_rrd_ftq_resps_0_ghist_old_history_0, 1'h0}; // @[frontend.scala:85:91] wire [64:0] _next_ghist_new_history_old_history_T_2; // @[frontend.scala:85:91] assign _next_ghist_new_history_old_history_T_2 = _GEN_41; // @[frontend.scala:85:91] wire [64:0] _next_ghist_new_history_old_history_T_4; // @[frontend.scala:86:91] assign _next_ghist_new_history_old_history_T_4 = _GEN_41; // @[frontend.scala:85:91, :86:91] wire [64:0] _next_ghist_new_history_old_history_T_3 = {_next_ghist_new_history_old_history_T_2[64:1], 1'h1}; // @[frontend.scala:85:{91,96}] wire [64:0] _next_ghist_new_history_old_history_T_5 = next_ghist_saw_not_taken_branch ? _next_ghist_new_history_old_history_T_4 : {1'h0, io_ifu_rrd_ftq_resps_0_ghist_old_history_0}; // @[frontend.scala:84:61, :86:{37,91}] wire [64:0] _next_ghist_new_history_old_history_T_6 = _next_ghist_new_history_old_history_T_1 ? _next_ghist_new_history_old_history_T_3 : _next_ghist_new_history_old_history_T_5; // @[frontend.scala:85:{37,61,96}, :86:37] assign next_ghist_old_history = _next_ghist_new_history_old_history_T_6[63:0]; // @[frontend.scala:74:27, :85:{31,37}] wire [5:0] _GEN_42 = {1'h0, io_ifu_rrd_ftq_resps_0_ghist_ras_idx_0}; // @[util.scala:211:14] wire [5:0] _next_ghist_new_history_ras_idx_T_1 = _GEN_42 + 6'h1; // @[util.scala:211:14] wire [4:0] _next_ghist_new_history_ras_idx_T_2 = _next_ghist_new_history_ras_idx_T_1[4:0]; // @[util.scala:211:14] wire [4:0] _next_ghist_new_history_ras_idx_T_3 = _next_ghist_new_history_ras_idx_T_2; // @[util.scala:211:{14,20}] wire [5:0] _next_ghist_new_history_ras_idx_T_5 = _GEN_42 - 6'h1; // @[util.scala:211:14, :228:14] wire [4:0] _next_ghist_new_history_ras_idx_T_6 = _next_ghist_new_history_ras_idx_T_5[4:0]; // @[util.scala:228:14] wire [4:0] _next_ghist_new_history_ras_idx_T_7 = _next_ghist_new_history_ras_idx_T_6; // @[util.scala:228:{14,20}] wire [4:0] _next_ghist_new_history_ras_idx_T_8 = _next_ghist_new_history_ras_idx_T_4 ? _next_ghist_new_history_ras_idx_T_7 : io_ifu_rrd_ftq_resps_0_ghist_ras_idx_0; // @[util.scala:228:20] assign _next_ghist_new_history_ras_idx_T_9 = _next_ghist_new_history_ras_idx_T ? _next_ghist_new_history_ras_idx_T_3 : _next_ghist_new_history_ras_idx_T_8; // @[util.scala:211:20] assign next_ghist_ras_idx = _next_ghist_new_history_ras_idx_T_9; // @[frontend.scala:74:27, :110:31] wire [63:0] _io_ifu_redirect_ghist_T_old_history = use_same_ghist ? io_ifu_rrd_ftq_resps_0_ghist_old_history_0 : next_ghist_old_history; // @[frontend.scala:74:27] wire _io_ifu_redirect_ghist_T_current_saw_branch_not_taken = use_same_ghist & io_ifu_rrd_ftq_resps_0_ghist_current_saw_branch_not_taken_0; // @[core.scala:50:7, :458:46, :475:35] wire _io_ifu_redirect_ghist_T_new_saw_branch_not_taken = use_same_ghist & io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_not_taken_0; // @[core.scala:50:7, :458:46, :475:35] wire _io_ifu_redirect_ghist_T_new_saw_branch_taken = use_same_ghist & io_ifu_rrd_ftq_resps_0_ghist_new_saw_branch_taken_0; // @[core.scala:50:7, :458:46, :475:35] wire [4:0] _io_ifu_redirect_ghist_T_ras_idx = use_same_ghist ? io_ifu_rrd_ftq_resps_0_ghist_ras_idx_0 : next_ghist_ras_idx; // @[frontend.scala:74:27] assign io_ifu_redirect_ghist_old_history_0 = REG ? 64'h0 : _io_ifu_redirect_ghist_T_old_history; // @[core.scala:50:7, :421:{16,38}, :429:27, :444:72, :475:35] assign io_ifu_redirect_ghist_new_saw_branch_not_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_not_taken; // @[core.scala:50:7, :421:{16,38}, :429:27, :444:72, :475:35] assign io_ifu_redirect_ghist_new_saw_branch_taken_0 = ~REG & _io_ifu_redirect_ghist_T_new_saw_branch_taken; // @[core.scala:50:7, :421:{16,38}, :429:27, :444:72, :475:35] assign io_ifu_redirect_ghist_ras_idx_0 = REG ? new_ghist_ras_idx : _io_ifu_redirect_ghist_T_ras_idx; // @[core.scala:50:7, :421:{16,38}, :426:29, :429:27, :444:72, :475:35] assign io_ifu_redirect_ghist_current_saw_branch_not_taken_0 = REG | use_same_ghist; // @[core.scala:50:7, :421:{16,38}, :429:27, :444:72, :458:46] assign io_ifu_redirect_flush_0 = REG | _T_15 | (|{_rob_io_flush_frontend, brupdate_b1_mispredict_mask}); // @[core.scala:50:7, :159:32, :209:23, :238:42, :421:{16,38}, :423:27, :444:{39,72}, :455:29, :480:{38,78}] wire _youngest_com_idx_T = ~_rob_io_commit_valids_1; // @[Mux.scala:50:70] wire [1:0] _youngest_com_idx_T_1 = 2'h1 - {1'h0, _youngest_com_idx_T}; // @[Mux.scala:50:70] wire youngest_com_idx = _youngest_com_idx_T_1[0]; // @[core.scala:485:42] wire _io_ifu_commit_valid_T = _rob_io_commit_valids_0 | _rob_io_commit_valids_1; // @[core.scala:159:32, :486:55] wire _io_ifu_commit_valid_T_1 = _io_ifu_commit_valid_T | _rob_io_com_xcpt_valid; // @[core.scala:159:32, :486:{55,59}] wire [4:0] _io_ifu_commit_bits_T = _rob_io_com_xcpt_valid ? _rob_io_com_xcpt_bits_ftq_idx : youngest_com_idx ? _rob_io_commit_uops_1_ftq_idx : _rob_io_commit_uops_0_ftq_idx; // @[core.scala:159:32, :485:42, :487:29] reg [1:0] dec_finished_mask; // @[core.scala:507:34] wire _dec_valids_0_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_0_valid_0; // @[core.scala:50:7, :519:68] wire _dec_valids_0_T_1 = dec_finished_mask[0]; // @[core.scala:507:34, :520:61] wire _dec_brmask_logic_io_is_branch_0_T = dec_finished_mask[0]; // @[core.scala:507:34, :520:61, :641:59] wire _dec_valids_0_T_2 = ~_dec_valids_0_T_1; // @[core.scala:520:{43,61}] assign _dec_valids_0_T_3 = _dec_valids_0_T & _dec_valids_0_T_2; // @[core.scala:519:{68,97}, :520:43] assign dec_valids_0 = _dec_valids_0_T_3; // @[core.scala:180:24, :519:97] reg decode_0_io_interrupt_REG; // @[core.scala:524:50] reg [63:0] decode_0_io_interrupt_cause_REG; // @[core.scala:525:50] wire _dec_valids_1_T = io_ifu_fetchpacket_valid_0 & io_ifu_fetchpacket_bits_uops_1_valid_0; // @[core.scala:50:7, :519:68] wire _dec_valids_1_T_1 = dec_finished_mask[1]; // @[core.scala:507:34, :520:61] wire _dec_brmask_logic_io_is_branch_1_T = dec_finished_mask[1]; // @[core.scala:507:34, :520:61, :641:59] wire _dec_valids_1_T_2 = ~_dec_valids_1_T_1; // @[core.scala:520:{43,61}] assign _dec_valids_1_T_3 = _dec_valids_1_T & _dec_valids_1_T_2; // @[core.scala:519:{68,97}, :520:43] assign dec_valids_1 = _dec_valids_1_T_3; // @[core.scala:180:24, :519:97] reg decode_1_io_interrupt_REG; // @[core.scala:524:50] reg [63:0] decode_1_io_interrupt_cause_REG; // @[core.scala:525:50] wire _xcpt_pc_req_valid_T; // @[core.scala:586:45] wire xcpt_pc_req_ready; // @[core.scala:537:25] wire xcpt_pc_req_valid; // @[core.scala:537:25] wire [4:0] xcpt_pc_req_bits; // @[core.scala:537:25] wire mispredict_pc_req_ready; // @[core.scala:538:31] wire flush_pc_req_valid; // @[core.scala:539:26] wire [4:0] flush_pc_req_bits; // @[core.scala:539:26] wire [1:0] data_sel; // @[core.scala:558:30] wire issue_read; // @[core.scala:560:34] wire use_port; // @[core.scala:561:32] wire issue_read_1; // @[core.scala:560:34] wire use_port_1; // @[core.scala:561:32] wire _T_37 = ~issue_read & _alu_exe_unit_0_io_arb_ftq_reqs_0_valid; // @[core.scala:92:11, :560:34, :562:{15,51}] assign issue_read_1 = _T_37; // @[core.scala:560:34, :562:51] assign use_port_1 = _T_37; // @[core.scala:561:32, :562:51] assign data_sel = _T_37 ? 2'h2 : {1'h0, _alu_exe_unit_0_io_arb_ftq_reqs_0_valid}; // @[core.scala:92:11, :558:30, :562:{51,65}, :565:20] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T = data_sel[0]; // @[core.scala:558:30, :573:67] reg alu_exe_unit_0_io_rrd_ftq_resps_0_REG; // @[core.scala:573:58] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_valid = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_valid_0 : io_ifu_rrd_ftq_resps_2_valid_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_cfi_idx_valid = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_idx_valid_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_idx_valid_0; // @[core.scala:50:7, :573:{50,58}] wire [1:0] _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_cfi_idx_bits = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_idx_bits_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_idx_bits_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_cfi_taken = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_taken_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_taken_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_cfi_mispredicted = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_mispredicted_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_mispredicted_0; // @[core.scala:50:7, :573:{50,58}] wire [2:0] _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_cfi_type = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_type_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_type_0; // @[core.scala:50:7, :573:{50,58}] wire [3:0] _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_br_mask = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_br_mask_0 : io_ifu_rrd_ftq_resps_2_entry_br_mask_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_cfi_is_call = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_is_call_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_is_call_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_cfi_is_ret = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_is_ret_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_is_ret_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_cfi_npc_plus4 = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_npc_plus4_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_npc_plus4_0; // @[core.scala:50:7, :573:{50,58}] wire [39:0] _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_ras_top = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_ras_top_0 : io_ifu_rrd_ftq_resps_2_entry_ras_top_0; // @[core.scala:50:7, :573:{50,58}] wire [4:0] _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_ras_idx = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_ras_idx_0 : io_ifu_rrd_ftq_resps_2_entry_ras_idx_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_entry_start_bank = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_start_bank_0 : io_ifu_rrd_ftq_resps_2_entry_start_bank_0; // @[core.scala:50:7, :573:{50,58}] wire [39:0] _alu_exe_unit_0_io_rrd_ftq_resps_0_T_1_pc = alu_exe_unit_0_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_pc_0 : io_ifu_rrd_ftq_resps_2_pc_0; // @[core.scala:50:7, :573:{50,58}] wire [1:0] data_sel_1; // @[core.scala:558:30] wire issue_read_2; // @[core.scala:560:34] wire use_port_2; // @[core.scala:561:32] wire _T_47 = ~use_port & _alu_exe_unit_0_io_arb_ftq_reqs_1_valid; // @[core.scala:92:11, :561:32, :562:{31,51}] assign issue_read_2 = _T_47; // @[core.scala:560:34, :562:51] assign use_port_2 = _T_47; // @[core.scala:561:32, :562:51] wire _T_48 = use_port_2 | use_port; // @[core.scala:561:32, :568:39] wire issue_read_3; // @[core.scala:560:34] wire use_port_3; // @[core.scala:561:32] wire _T_57 = ~issue_read_2 & ~use_port_1 & _alu_exe_unit_0_io_arb_ftq_reqs_1_valid; // @[core.scala:92:11, :560:34, :561:32, :562:{15,28,31,51}] assign issue_read_3 = _T_57; // @[core.scala:560:34, :562:{28,51}] assign use_port_3 = _T_57; // @[core.scala:561:32, :562:{28,51}] assign data_sel_1 = _T_57 ? 2'h2 : {1'h0, _T_47}; // @[core.scala:558:30, :562:{28,51,65}, :565:20] wire _T_58 = use_port_3 | use_port_1; // @[core.scala:561:32, :568:39] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T = data_sel_1[0]; // @[core.scala:558:30, :573:67] reg alu_exe_unit_0_io_rrd_ftq_resps_1_REG; // @[core.scala:573:58] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_valid = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_valid_0 : io_ifu_rrd_ftq_resps_2_valid_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_cfi_idx_valid = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_idx_valid_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_idx_valid_0; // @[core.scala:50:7, :573:{50,58}] wire [1:0] _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_cfi_idx_bits = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_idx_bits_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_idx_bits_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_cfi_taken = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_taken_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_taken_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_cfi_mispredicted = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_mispredicted_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_mispredicted_0; // @[core.scala:50:7, :573:{50,58}] wire [2:0] _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_cfi_type = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_type_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_type_0; // @[core.scala:50:7, :573:{50,58}] wire [3:0] _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_br_mask = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_br_mask_0 : io_ifu_rrd_ftq_resps_2_entry_br_mask_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_cfi_is_call = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_is_call_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_is_call_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_cfi_is_ret = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_is_ret_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_is_ret_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_cfi_npc_plus4 = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_npc_plus4_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_npc_plus4_0; // @[core.scala:50:7, :573:{50,58}] wire [39:0] _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_ras_top = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_ras_top_0 : io_ifu_rrd_ftq_resps_2_entry_ras_top_0; // @[core.scala:50:7, :573:{50,58}] wire [4:0] _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_ras_idx = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_ras_idx_0 : io_ifu_rrd_ftq_resps_2_entry_ras_idx_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_entry_start_bank = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_start_bank_0 : io_ifu_rrd_ftq_resps_2_entry_start_bank_0; // @[core.scala:50:7, :573:{50,58}] wire [39:0] _alu_exe_unit_0_io_rrd_ftq_resps_1_T_1_pc = alu_exe_unit_0_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_pc_0 : io_ifu_rrd_ftq_resps_2_pc_0; // @[core.scala:50:7, :573:{50,58}] wire [1:0] data_sel_2; // @[core.scala:558:30] wire issue_read_4; // @[core.scala:560:34] wire use_port_4; // @[core.scala:561:32] wire _T_67 = ~_T_48 & _alu_exe_unit_1_io_arb_ftq_reqs_0_valid; // @[core.scala:92:11, :562:{31,51}, :568:39] assign issue_read_4 = _T_67; // @[core.scala:560:34, :562:51] assign use_port_4 = _T_67; // @[core.scala:561:32, :562:51] wire _T_68 = use_port_4 | _T_48; // @[core.scala:561:32, :568:39] wire issue_read_5; // @[core.scala:560:34] wire use_port_5; // @[core.scala:561:32] wire _T_77 = ~issue_read_4 & ~_T_58 & _alu_exe_unit_1_io_arb_ftq_reqs_0_valid; // @[core.scala:92:11, :560:34, :562:{15,28,31,51}, :568:39] assign issue_read_5 = _T_77; // @[core.scala:560:34, :562:{28,51}] assign use_port_5 = _T_77; // @[core.scala:561:32, :562:{28,51}] assign data_sel_2 = _T_77 ? 2'h2 : {1'h0, _T_67}; // @[core.scala:558:30, :562:{28,51,65}, :565:20] wire _T_78 = use_port_5 | _T_58; // @[core.scala:561:32, :568:39] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T = data_sel_2[0]; // @[core.scala:558:30, :573:67] reg alu_exe_unit_1_io_rrd_ftq_resps_0_REG; // @[core.scala:573:58] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_valid = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_valid_0 : io_ifu_rrd_ftq_resps_2_valid_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_cfi_idx_valid = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_idx_valid_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_idx_valid_0; // @[core.scala:50:7, :573:{50,58}] wire [1:0] _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_cfi_idx_bits = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_idx_bits_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_idx_bits_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_cfi_taken = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_taken_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_taken_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_cfi_mispredicted = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_mispredicted_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_mispredicted_0; // @[core.scala:50:7, :573:{50,58}] wire [2:0] _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_cfi_type = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_type_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_type_0; // @[core.scala:50:7, :573:{50,58}] wire [3:0] _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_br_mask = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_br_mask_0 : io_ifu_rrd_ftq_resps_2_entry_br_mask_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_cfi_is_call = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_is_call_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_is_call_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_cfi_is_ret = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_is_ret_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_is_ret_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_cfi_npc_plus4 = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_npc_plus4_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_npc_plus4_0; // @[core.scala:50:7, :573:{50,58}] wire [39:0] _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_ras_top = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_ras_top_0 : io_ifu_rrd_ftq_resps_2_entry_ras_top_0; // @[core.scala:50:7, :573:{50,58}] wire [4:0] _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_ras_idx = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_ras_idx_0 : io_ifu_rrd_ftq_resps_2_entry_ras_idx_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_entry_start_bank = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_entry_start_bank_0 : io_ifu_rrd_ftq_resps_2_entry_start_bank_0; // @[core.scala:50:7, :573:{50,58}] wire [39:0] _alu_exe_unit_1_io_rrd_ftq_resps_0_T_1_pc = alu_exe_unit_1_io_rrd_ftq_resps_0_REG ? io_ifu_rrd_ftq_resps_1_pc_0 : io_ifu_rrd_ftq_resps_2_pc_0; // @[core.scala:50:7, :573:{50,58}] wire [1:0] data_sel_3; // @[core.scala:558:30] wire issue_read_6; // @[core.scala:560:34] wire use_port_6; // @[core.scala:561:32] wire _T_87 = ~_T_68 & _alu_exe_unit_1_io_arb_ftq_reqs_1_valid; // @[core.scala:92:11, :562:{31,51}, :568:39] assign issue_read_6 = _T_87; // @[core.scala:560:34, :562:51] assign use_port_6 = _T_87; // @[core.scala:561:32, :562:51] assign io_ifu_arb_ftq_reqs_1_0 = (use_port ? _alu_exe_unit_0_io_arb_ftq_reqs_0_bits : 5'h0) | (use_port | ~use_port_2 ? 5'h0 : _alu_exe_unit_0_io_arb_ftq_reqs_1_bits) | (_T_48 | ~use_port_4 ? 5'h0 : _alu_exe_unit_1_io_arb_ftq_reqs_0_bits) | (_T_68 | ~use_port_6 ? 5'h0 : _alu_exe_unit_1_io_arb_ftq_reqs_1_bits); // @[core.scala:50:7, :92:11, :561:32, :568:39, :569:{47,52,73,76}] wire issue_read_7; // @[core.scala:560:34] wire use_port_7; // @[core.scala:561:32] wire _T_97 = ~issue_read_6 & ~_T_78 & _alu_exe_unit_1_io_arb_ftq_reqs_1_valid; // @[core.scala:92:11, :560:34, :562:{15,28,31,51}, :568:39] assign issue_read_7 = _T_97; // @[core.scala:560:34, :562:{28,51}] assign use_port_7 = _T_97; // @[core.scala:561:32, :562:{28,51}] assign data_sel_3 = _T_97 ? 2'h2 : {1'h0, _T_87}; // @[core.scala:558:30, :562:{28,51,65}, :565:20] assign io_ifu_arb_ftq_reqs_2_0 = (use_port_1 ? _alu_exe_unit_0_io_arb_ftq_reqs_0_bits : 5'h0) | (use_port_1 | ~use_port_3 ? 5'h0 : _alu_exe_unit_0_io_arb_ftq_reqs_1_bits) | (_T_58 | ~use_port_5 ? 5'h0 : _alu_exe_unit_1_io_arb_ftq_reqs_0_bits) | (_T_78 | ~use_port_7 ? 5'h0 : _alu_exe_unit_1_io_arb_ftq_reqs_1_bits); // @[core.scala:50:7, :92:11, :561:32, :568:39, :569:{47,52,73,76}] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T = data_sel_3[0]; // @[core.scala:558:30, :573:67] reg alu_exe_unit_1_io_rrd_ftq_resps_1_REG; // @[core.scala:573:58] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_valid = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_valid_0 : io_ifu_rrd_ftq_resps_2_valid_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_cfi_idx_valid = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_idx_valid_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_idx_valid_0; // @[core.scala:50:7, :573:{50,58}] wire [1:0] _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_cfi_idx_bits = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_idx_bits_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_idx_bits_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_cfi_taken = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_taken_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_taken_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_cfi_mispredicted = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_mispredicted_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_mispredicted_0; // @[core.scala:50:7, :573:{50,58}] wire [2:0] _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_cfi_type = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_type_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_type_0; // @[core.scala:50:7, :573:{50,58}] wire [3:0] _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_br_mask = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_br_mask_0 : io_ifu_rrd_ftq_resps_2_entry_br_mask_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_cfi_is_call = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_is_call_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_is_call_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_cfi_is_ret = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_is_ret_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_is_ret_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_cfi_npc_plus4 = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_cfi_npc_plus4_0 : io_ifu_rrd_ftq_resps_2_entry_cfi_npc_plus4_0; // @[core.scala:50:7, :573:{50,58}] wire [39:0] _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_ras_top = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_ras_top_0 : io_ifu_rrd_ftq_resps_2_entry_ras_top_0; // @[core.scala:50:7, :573:{50,58}] wire [4:0] _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_ras_idx = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_ras_idx_0 : io_ifu_rrd_ftq_resps_2_entry_ras_idx_0; // @[core.scala:50:7, :573:{50,58}] wire _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_entry_start_bank = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_entry_start_bank_0 : io_ifu_rrd_ftq_resps_2_entry_start_bank_0; // @[core.scala:50:7, :573:{50,58}] wire [39:0] _alu_exe_unit_1_io_rrd_ftq_resps_1_T_1_pc = alu_exe_unit_1_io_rrd_ftq_resps_1_REG ? io_ifu_rrd_ftq_resps_1_pc_0 : io_ifu_rrd_ftq_resps_2_pc_0; // @[core.scala:50:7, :573:{50,58}] wire xcpt_idx = ~dec_xcpts_0; // @[Mux.scala:50:70] assign _xcpt_pc_req_valid_T = dec_xcpts_0 | dec_xcpts_1; // @[core.scala:185:24, :586:45] assign xcpt_pc_req_valid = _xcpt_pc_req_valid_T; // @[core.scala:537:25, :586:45] assign xcpt_pc_req_bits = xcpt_idx ? dec_uops_1_ftq_idx : dec_uops_0_ftq_idx; // @[Mux.scala:50:70] assign dec_xcpts_0 = dec_uops_0_exception & dec_valids_0; // @[core.scala:180:24, :181:24, :185:24, :601:71] assign dec_xcpts_1 = dec_uops_1_exception & dec_valids_1; // @[core.scala:180:24, :181:24, :185:24, :601:71] wire dec_prior_slot_valid_2 = dec_prior_slot_valid_1 | dec_valids_1; // @[core.scala:180:24, :605:71] wire _dec_xcpt_stall_T = ~_rob_io_empty; // @[core.scala:159:32, :607:6] wire _dec_xcpt_stall_T_1 = ~io_lsu_fencei_rdy_0; // @[core.scala:50:7, :607:23] wire _dec_xcpt_stall_T_2 = _dec_xcpt_stall_T | _dec_xcpt_stall_T_1; // @[core.scala:607:{6,20,23}] wire _dec_xcpt_stall_T_3 = _dec_xcpt_stall_T_2; // @[core.scala:607:{20,42}] wire _GEN_43 = dis_valids_0 | dis_valids_1; // @[core.scala:189:24, :607:91] wire _dec_xcpt_stall_T_4; // @[core.scala:607:91] assign _dec_xcpt_stall_T_4 = _GEN_43; // @[core.scala:607:91] wire _dec_xcpt_stall_T_12; // @[core.scala:607:91] assign _dec_xcpt_stall_T_12 = _GEN_43; // @[core.scala:607:91] wire _dec_xcpt_stall_T_5 = _dec_xcpt_stall_T_3 | _dec_xcpt_stall_T_4; // @[core.scala:607:{42,69,91}] wire _dec_xcpt_stall_T_6 = ~xcpt_pc_req_ready; // @[core.scala:537:25, :607:99] wire _dec_xcpt_stall_T_7 = _dec_xcpt_stall_T_5 | _dec_xcpt_stall_T_6; // @[core.scala:607:{69,96,99}] wire dec_xcpt_stall_0 = dec_xcpts_0 & _dec_xcpt_stall_T_7; // @[core.scala:185:24, :606:66, :607:96] wire _dec_xcpt_stall_T_8 = ~_rob_io_empty; // @[core.scala:159:32, :607:6] wire _dec_xcpt_stall_T_9 = ~io_lsu_fencei_rdy_0; // @[core.scala:50:7, :607:23] wire _dec_xcpt_stall_T_10 = _dec_xcpt_stall_T_8 | _dec_xcpt_stall_T_9; // @[core.scala:607:{6,20,23}] wire _dec_xcpt_stall_T_11 = _dec_xcpt_stall_T_10 | dec_prior_slot_valid_1; // @[core.scala:605:71, :607:{20,42}] wire _dec_xcpt_stall_T_13 = _dec_xcpt_stall_T_11 | _dec_xcpt_stall_T_12; // @[core.scala:607:{42,69,91}] wire _dec_xcpt_stall_T_14 = ~xcpt_pc_req_ready; // @[core.scala:537:25, :607:99] wire _dec_xcpt_stall_T_15 = _dec_xcpt_stall_T_13 | _dec_xcpt_stall_T_14; // @[core.scala:607:{69,96,99}] wire dec_xcpt_stall_1 = dec_xcpts_1 & _dec_xcpt_stall_T_15; // @[core.scala:185:24, :606:66, :607:96] wire branch_mask_full_0; // @[core.scala:610:30] wire branch_mask_full_1; // @[core.scala:610:30] wire _dec_hazards_T = ~dis_ready; // @[core.scala:192:24, :614:26] wire _dec_hazards_T_1 = _dec_hazards_T | _rob_io_rollback; // @[core.scala:159:32, :614:26, :615:23] wire _dec_hazards_T_2 = _dec_hazards_T_1 | dec_xcpt_stall_0; // @[core.scala:606:66, :615:23, :616:23] wire _dec_hazards_T_3 = _dec_hazards_T_2 | branch_mask_full_0; // @[core.scala:610:30, :616:23, :617:23] wire _dec_hazards_T_4 = |brupdate_b1_mispredict_mask; // @[core.scala:209:23, :238:42, :618:54] wire _dec_hazards_T_5 = _dec_hazards_T_3 | _dec_hazards_T_4; // @[core.scala:617:23, :618:{23,54}] wire _dec_hazards_T_6 = _dec_hazards_T_5 | brupdate_b2_mispredict; // @[core.scala:209:23, :618:23, :619:23] wire _dec_hazards_T_7 = _dec_hazards_T_6 | io_ifu_redirect_flush_0; // @[core.scala:50:7, :619:23, :620:23] wire dec_hazards_0 = dec_valids_0 & _dec_hazards_T_7; // @[core.scala:180:24, :613:37, :620:23] wire dec_stalls_0 = dec_hazards_0; // @[core.scala:613:37, :622:62] wire _dec_hazards_T_8 = ~dis_ready; // @[core.scala:192:24, :614:26] wire _dec_hazards_T_9 = _dec_hazards_T_8 | _rob_io_rollback; // @[core.scala:159:32, :614:26, :615:23] wire _dec_hazards_T_10 = _dec_hazards_T_9 | dec_xcpt_stall_1; // @[core.scala:606:66, :615:23, :616:23] wire _dec_hazards_T_11 = _dec_hazards_T_10 | branch_mask_full_1; // @[core.scala:610:30, :616:23, :617:23] wire _dec_hazards_T_12 = |brupdate_b1_mispredict_mask; // @[core.scala:209:23, :238:42, :618:54] wire _dec_hazards_T_13 = _dec_hazards_T_11 | _dec_hazards_T_12; // @[core.scala:617:23, :618:{23,54}] wire _dec_hazards_T_14 = _dec_hazards_T_13 | brupdate_b2_mispredict; // @[core.scala:209:23, :618:23, :619:23] wire _dec_hazards_T_15 = _dec_hazards_T_14 | io_ifu_redirect_flush_0; // @[core.scala:50:7, :619:23, :620:23] wire dec_hazards_1 = dec_valids_1 & _dec_hazards_T_15; // @[core.scala:180:24, :613:37, :620:23] wire dec_stalls_1 = dec_stalls_0 | dec_hazards_1; // @[core.scala:613:37, :622:62] assign dec_fire_0 = dec_valids_0 & ~dec_stalls_0; // @[core.scala:180:24, :182:24, :622:62, :623:{58,61}] assign dec_fire_1 = dec_valids_1 & ~dec_stalls_1; // @[core.scala:180:24, :182:24, :622:62, :623:{58,61}] wire [1:0] _dec_finished_mask_T = {dec_fire_1, dec_fire_0}; // @[core.scala:182:24, :631:35] wire [1:0] _dec_finished_mask_T_1 = _dec_finished_mask_T | dec_finished_mask; // @[core.scala:507:34, :631:{35,42}] reg dec_brmask_logic_io_flush_pipeline_REG; // @[core.scala:638:48] wire _dec_brmask_logic_io_is_branch_0_T_1 = ~_dec_brmask_logic_io_is_branch_0_T; // @[core.scala:641:{41,59}] wire _GEN_44 = dec_uops_0_br_type == 4'h1; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_0_T_2; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_0_T_2 = _GEN_44; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_0_T; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_0_T = _GEN_44; // @[package.scala:16:47] wire _GEN_45 = dec_uops_0_br_type == 4'h2; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_0_T_3; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_0_T_3 = _GEN_45; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_0_T_1; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_0_T_1 = _GEN_45; // @[package.scala:16:47] wire _GEN_46 = dec_uops_0_br_type == 4'h3; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_0_T_4; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_0_T_4 = _GEN_46; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_0_T_2; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_0_T_2 = _GEN_46; // @[package.scala:16:47] wire _GEN_47 = dec_uops_0_br_type == 4'h4; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_0_T_5; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_0_T_5 = _GEN_47; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_0_T_3; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_0_T_3 = _GEN_47; // @[package.scala:16:47] wire _GEN_48 = dec_uops_0_br_type == 4'h5; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_0_T_6; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_0_T_6 = _GEN_48; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_0_T_4; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_0_T_4 = _GEN_48; // @[package.scala:16:47] wire _GEN_49 = dec_uops_0_br_type == 4'h6; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_0_T_7; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_0_T_7 = _GEN_49; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_0_T_5; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_0_T_5 = _GEN_49; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_0_T_8 = _dec_brmask_logic_io_is_branch_0_T_2 | _dec_brmask_logic_io_is_branch_0_T_3; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_is_branch_0_T_9 = _dec_brmask_logic_io_is_branch_0_T_8 | _dec_brmask_logic_io_is_branch_0_T_4; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_is_branch_0_T_10 = _dec_brmask_logic_io_is_branch_0_T_9 | _dec_brmask_logic_io_is_branch_0_T_5; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_is_branch_0_T_11 = _dec_brmask_logic_io_is_branch_0_T_10 | _dec_brmask_logic_io_is_branch_0_T_6; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_is_branch_0_T_12 = _dec_brmask_logic_io_is_branch_0_T_11 | _dec_brmask_logic_io_is_branch_0_T_7; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_is_branch_0_T_13 = ~dec_uops_0_is_sfb; // @[core.scala:181:24] wire _dec_brmask_logic_io_is_branch_0_T_14 = _dec_brmask_logic_io_is_branch_0_T_12 & _dec_brmask_logic_io_is_branch_0_T_13; // @[package.scala:81:59] wire _dec_brmask_logic_io_is_branch_0_T_16 = _dec_brmask_logic_io_is_branch_0_T_14 | _dec_brmask_logic_io_is_branch_0_T_15; // @[micro-op.scala:119:34, :160:{33,45}] wire _dec_brmask_logic_io_is_branch_0_T_17 = _dec_brmask_logic_io_is_branch_0_T_1 & _dec_brmask_logic_io_is_branch_0_T_16; // @[core.scala:641:{41,63}] wire _dec_brmask_logic_io_will_fire_0_T_6 = _dec_brmask_logic_io_will_fire_0_T | _dec_brmask_logic_io_will_fire_0_T_1; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_will_fire_0_T_7 = _dec_brmask_logic_io_will_fire_0_T_6 | _dec_brmask_logic_io_will_fire_0_T_2; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_will_fire_0_T_8 = _dec_brmask_logic_io_will_fire_0_T_7 | _dec_brmask_logic_io_will_fire_0_T_3; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_will_fire_0_T_9 = _dec_brmask_logic_io_will_fire_0_T_8 | _dec_brmask_logic_io_will_fire_0_T_4; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_will_fire_0_T_10 = _dec_brmask_logic_io_will_fire_0_T_9 | _dec_brmask_logic_io_will_fire_0_T_5; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_will_fire_0_T_11 = ~dec_uops_0_is_sfb; // @[core.scala:181:24] wire _dec_brmask_logic_io_will_fire_0_T_12 = _dec_brmask_logic_io_will_fire_0_T_10 & _dec_brmask_logic_io_will_fire_0_T_11; // @[package.scala:81:59] wire _dec_brmask_logic_io_will_fire_0_T_14 = _dec_brmask_logic_io_will_fire_0_T_12 | _dec_brmask_logic_io_will_fire_0_T_13; // @[micro-op.scala:119:34, :160:{33,45}] wire _dec_brmask_logic_io_will_fire_0_T_15 = dec_fire_0 & _dec_brmask_logic_io_will_fire_0_T_14; // @[core.scala:182:24, :642:54] wire _dec_brmask_logic_io_is_branch_1_T_1 = ~_dec_brmask_logic_io_is_branch_1_T; // @[core.scala:641:{41,59}] wire _GEN_50 = dec_uops_1_br_type == 4'h1; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_1_T_2; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_1_T_2 = _GEN_50; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_1_T; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_1_T = _GEN_50; // @[package.scala:16:47] wire _GEN_51 = dec_uops_1_br_type == 4'h2; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_1_T_3; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_1_T_3 = _GEN_51; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_1_T_1; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_1_T_1 = _GEN_51; // @[package.scala:16:47] wire _GEN_52 = dec_uops_1_br_type == 4'h3; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_1_T_4; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_1_T_4 = _GEN_52; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_1_T_2; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_1_T_2 = _GEN_52; // @[package.scala:16:47] wire _GEN_53 = dec_uops_1_br_type == 4'h4; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_1_T_5; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_1_T_5 = _GEN_53; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_1_T_3; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_1_T_3 = _GEN_53; // @[package.scala:16:47] wire _GEN_54 = dec_uops_1_br_type == 4'h5; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_1_T_6; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_1_T_6 = _GEN_54; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_1_T_4; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_1_T_4 = _GEN_54; // @[package.scala:16:47] wire _GEN_55 = dec_uops_1_br_type == 4'h6; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_1_T_7; // @[package.scala:16:47] assign _dec_brmask_logic_io_is_branch_1_T_7 = _GEN_55; // @[package.scala:16:47] wire _dec_brmask_logic_io_will_fire_1_T_5; // @[package.scala:16:47] assign _dec_brmask_logic_io_will_fire_1_T_5 = _GEN_55; // @[package.scala:16:47] wire _dec_brmask_logic_io_is_branch_1_T_8 = _dec_brmask_logic_io_is_branch_1_T_2 | _dec_brmask_logic_io_is_branch_1_T_3; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_is_branch_1_T_9 = _dec_brmask_logic_io_is_branch_1_T_8 | _dec_brmask_logic_io_is_branch_1_T_4; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_is_branch_1_T_10 = _dec_brmask_logic_io_is_branch_1_T_9 | _dec_brmask_logic_io_is_branch_1_T_5; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_is_branch_1_T_11 = _dec_brmask_logic_io_is_branch_1_T_10 | _dec_brmask_logic_io_is_branch_1_T_6; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_is_branch_1_T_12 = _dec_brmask_logic_io_is_branch_1_T_11 | _dec_brmask_logic_io_is_branch_1_T_7; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_is_branch_1_T_13 = ~dec_uops_1_is_sfb; // @[core.scala:181:24] wire _dec_brmask_logic_io_is_branch_1_T_14 = _dec_brmask_logic_io_is_branch_1_T_12 & _dec_brmask_logic_io_is_branch_1_T_13; // @[package.scala:81:59] wire _dec_brmask_logic_io_is_branch_1_T_16 = _dec_brmask_logic_io_is_branch_1_T_14 | _dec_brmask_logic_io_is_branch_1_T_15; // @[micro-op.scala:119:34, :160:{33,45}] wire _dec_brmask_logic_io_is_branch_1_T_17 = _dec_brmask_logic_io_is_branch_1_T_1 & _dec_brmask_logic_io_is_branch_1_T_16; // @[core.scala:641:{41,63}] wire _dec_brmask_logic_io_will_fire_1_T_6 = _dec_brmask_logic_io_will_fire_1_T | _dec_brmask_logic_io_will_fire_1_T_1; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_will_fire_1_T_7 = _dec_brmask_logic_io_will_fire_1_T_6 | _dec_brmask_logic_io_will_fire_1_T_2; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_will_fire_1_T_8 = _dec_brmask_logic_io_will_fire_1_T_7 | _dec_brmask_logic_io_will_fire_1_T_3; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_will_fire_1_T_9 = _dec_brmask_logic_io_will_fire_1_T_8 | _dec_brmask_logic_io_will_fire_1_T_4; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_will_fire_1_T_10 = _dec_brmask_logic_io_will_fire_1_T_9 | _dec_brmask_logic_io_will_fire_1_T_5; // @[package.scala:16:47, :81:59] wire _dec_brmask_logic_io_will_fire_1_T_11 = ~dec_uops_1_is_sfb; // @[core.scala:181:24] wire _dec_brmask_logic_io_will_fire_1_T_12 = _dec_brmask_logic_io_will_fire_1_T_10 & _dec_brmask_logic_io_will_fire_1_T_11; // @[package.scala:81:59] wire _dec_brmask_logic_io_will_fire_1_T_14 = _dec_brmask_logic_io_will_fire_1_T_12 | _dec_brmask_logic_io_will_fire_1_T_13; // @[micro-op.scala:119:34, :160:{33,45}] wire _dec_brmask_logic_io_will_fire_1_T_15 = dec_fire_1 & _dec_brmask_logic_io_will_fire_1_T_14; // @[core.scala:182:24, :642:54] wire _GEN_56 = dis_uops_0_lrs1_rtype == 2'h1; // @[core.scala:190:24, :697:52] wire _dis_uops_0_prs1_T; // @[core.scala:697:52] assign _dis_uops_0_prs1_T = _GEN_56; // @[core.scala:697:52] wire _dis_uops_0_prs1_busy_T_2; // @[core.scala:713:73] assign _dis_uops_0_prs1_busy_T_2 = _GEN_56; // @[core.scala:697:52, :713:73] wire _GEN_57 = dis_uops_0_lrs1_rtype == 2'h0; // @[core.scala:190:24, :698:52] wire _dis_uops_0_prs1_T_1; // @[core.scala:698:52] assign _dis_uops_0_prs1_T_1 = _GEN_57; // @[core.scala:698:52] wire _dis_uops_0_prs1_busy_T; // @[core.scala:712:73] assign _dis_uops_0_prs1_busy_T = _GEN_57; // @[core.scala:698:52, :712:73] wire [6:0] _dis_uops_0_prs1_T_2 = _dis_uops_0_prs1_T_1 ? _rename_stage_io_ren2_uops_0_prs1 : {1'h0, dis_uops_0_lrs1}; // @[core.scala:116:33, :190:24, :698:{28,52}] assign _dis_uops_0_prs1_T_3 = _dis_uops_0_prs1_T ? _fp_rename_stage_io_ren2_uops_0_prs1 : _dis_uops_0_prs1_T_2; // @[core.scala:117:33, :697:{28,52}, :698:28] assign dis_uops_0_prs1 = _dis_uops_0_prs1_T_3; // @[core.scala:190:24, :697:28] wire _GEN_58 = dis_uops_0_lrs2_rtype == 2'h1; // @[core.scala:190:24, :699:52] wire _dis_uops_0_prs2_T; // @[core.scala:699:52] assign _dis_uops_0_prs2_T = _GEN_58; // @[core.scala:699:52] wire _dis_uops_0_prs2_busy_T_2; // @[core.scala:715:73] assign _dis_uops_0_prs2_busy_T_2 = _GEN_58; // @[core.scala:699:52, :715:73] assign _dis_uops_0_prs2_T_1 = _dis_uops_0_prs2_T ? _fp_rename_stage_io_ren2_uops_0_prs2 : _rename_stage_io_ren2_uops_0_prs2; // @[core.scala:116:33, :117:33, :699:{28,52}] assign dis_uops_0_prs2 = _dis_uops_0_prs2_T_1; // @[core.scala:190:24, :699:28] wire _GEN_59 = dis_uops_0_dst_rtype == 2'h1; // @[core.scala:190:24, :702:52] wire _dis_uops_0_pdst_T; // @[core.scala:702:52] assign _dis_uops_0_pdst_T = _GEN_59; // @[core.scala:702:52] wire _dis_uops_0_stale_pdst_T; // @[core.scala:710:57] assign _dis_uops_0_stale_pdst_T = _GEN_59; // @[core.scala:702:52, :710:57] wire _dis_uops_0_pdst_T_1 = dis_uops_0_dst_rtype == 2'h0; // @[core.scala:190:24, :703:52] wire _dis_uops_0_pdst_T_2 = |dis_uops_0_br_type; // @[core.scala:190:24] wire _dis_uops_0_pdst_T_3 = _dis_uops_0_pdst_T_2 & dis_uops_0_is_sfb; // @[core.scala:190:24] wire _dis_uops_0_pdst_T_4 = _dis_uops_0_pdst_T_3; // @[micro-op.scala:120:{42,52}] wire [1:0] dis_uops_0_pdst_lo_hi = {_dis_uops_0_pdst_prng_io_out_2, _dis_uops_0_pdst_prng_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] dis_uops_0_pdst_lo = {dis_uops_0_pdst_lo_hi, _dis_uops_0_pdst_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] dis_uops_0_pdst_hi_lo = {_dis_uops_0_pdst_prng_io_out_4, _dis_uops_0_pdst_prng_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [1:0] dis_uops_0_pdst_hi_hi = {_dis_uops_0_pdst_prng_io_out_6, _dis_uops_0_pdst_prng_io_out_5}; // @[PRNG.scala:91:22, :95:17] wire [3:0] dis_uops_0_pdst_hi = {dis_uops_0_pdst_hi_hi, dis_uops_0_pdst_hi_lo}; // @[PRNG.scala:95:17] wire [6:0] _dis_uops_0_pdst_T_5 = {dis_uops_0_pdst_hi, dis_uops_0_pdst_lo}; // @[PRNG.scala:95:17] wire [6:0] _dis_uops_0_pdst_T_6 = _dis_uops_0_pdst_T_4 ? _pred_rename_stage_io_ren2_uops_0_pdst : _dis_uops_0_pdst_T_5; // @[PRNG.scala:95:17] wire [6:0] _dis_uops_0_pdst_T_7 = _dis_uops_0_pdst_T_1 ? _rename_stage_io_ren2_uops_0_pdst : _dis_uops_0_pdst_T_6; // @[core.scala:116:33, :703:{28,52}, :704:28] assign _dis_uops_0_pdst_T_8 = _dis_uops_0_pdst_T ? _fp_rename_stage_io_ren2_uops_0_pdst : _dis_uops_0_pdst_T_7; // @[core.scala:117:33, :702:{28,52}, :703:28] assign dis_uops_0_pdst = _dis_uops_0_pdst_T_8; // @[core.scala:190:24, :702:28] assign _dis_uops_0_stale_pdst_T_1 = _dis_uops_0_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_0_stale_pdst : _rename_stage_io_ren2_uops_0_stale_pdst; // @[core.scala:116:33, :117:33, :710:{34,57}] assign dis_uops_0_stale_pdst = _dis_uops_0_stale_pdst_T_1; // @[core.scala:190:24, :710:34] wire _dis_uops_0_prs1_busy_T_1 = _rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T; // @[core.scala:116:33, :712:{46,73}] wire _dis_uops_0_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs1_busy & _dis_uops_0_prs1_busy_T_2; // @[core.scala:117:33, :713:{46,73}] assign _dis_uops_0_prs1_busy_T_4 = _dis_uops_0_prs1_busy_T_1 | _dis_uops_0_prs1_busy_T_3; // @[core.scala:712:{46,85}, :713:46] assign dis_uops_0_prs1_busy = _dis_uops_0_prs1_busy_T_4; // @[core.scala:190:24, :712:85] wire _dis_uops_0_prs2_busy_T = dis_uops_0_lrs2_rtype == 2'h0; // @[core.scala:190:24, :714:73] wire _dis_uops_0_prs2_busy_T_1 = _rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T; // @[core.scala:116:33, :714:{46,73}] wire _dis_uops_0_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_0_prs2_busy & _dis_uops_0_prs2_busy_T_2; // @[core.scala:117:33, :715:{46,73}] assign _dis_uops_0_prs2_busy_T_4 = _dis_uops_0_prs2_busy_T_1 | _dis_uops_0_prs2_busy_T_3; // @[core.scala:714:{46,85}, :715:46] assign dis_uops_0_prs2_busy = _dis_uops_0_prs2_busy_T_4; // @[core.scala:190:24, :714:85] assign _dis_uops_0_prs3_busy_T = _fp_rename_stage_io_ren2_uops_0_prs3_busy & dis_uops_0_frs3_en; // @[core.scala:117:33, :190:24, :716:46] assign dis_uops_0_prs3_busy = _dis_uops_0_prs3_busy_T; // @[core.scala:190:24, :716:46] wire _dis_uops_0_ppred_busy_T = ~(|dis_uops_0_br_type); // @[core.scala:190:24] wire _dis_uops_0_ppred_busy_T_1 = _dis_uops_0_ppred_busy_T & dis_uops_0_is_sfb; // @[core.scala:190:24] wire _dis_uops_0_ppred_busy_T_2 = _dis_uops_0_ppred_busy_T_1; // @[micro-op.scala:121:{42,52}] assign _dis_uops_0_ppred_busy_T_3 = _pred_rename_stage_io_ren2_uops_0_ppred_busy & _dis_uops_0_ppred_busy_T_2; // @[core.scala:118:33, :717:48] assign dis_uops_0_ppred_busy = _dis_uops_0_ppred_busy_T_3; // @[core.scala:190:24, :717:48] wire _ren_stalls_0_T = _rename_stage_io_ren_stalls_0 | _fp_rename_stage_io_ren_stalls_0; // @[core.scala:116:33, :117:33, :719:52] wire _ren_stalls_0_T_1 = _ren_stalls_0_T; // @[core.scala:719:{52,63}] assign _ren_stalls_0_T_2 = _ren_stalls_0_T_1 | _imm_rename_stage_io_ren_stalls_0; // @[core.scala:119:33, :719:{63,74}] assign ren_stalls_0 = _ren_stalls_0_T_2; // @[core.scala:186:24, :719:74] wire _GEN_60 = dis_uops_1_lrs1_rtype == 2'h1; // @[core.scala:190:24, :697:52] wire _dis_uops_1_prs1_T; // @[core.scala:697:52] assign _dis_uops_1_prs1_T = _GEN_60; // @[core.scala:697:52] wire _dis_uops_1_prs1_busy_T_2; // @[core.scala:713:73] assign _dis_uops_1_prs1_busy_T_2 = _GEN_60; // @[core.scala:697:52, :713:73] wire _GEN_61 = dis_uops_1_lrs1_rtype == 2'h0; // @[core.scala:190:24, :698:52] wire _dis_uops_1_prs1_T_1; // @[core.scala:698:52] assign _dis_uops_1_prs1_T_1 = _GEN_61; // @[core.scala:698:52] wire _dis_uops_1_prs1_busy_T; // @[core.scala:712:73] assign _dis_uops_1_prs1_busy_T = _GEN_61; // @[core.scala:698:52, :712:73] wire [6:0] _dis_uops_1_prs1_T_2 = _dis_uops_1_prs1_T_1 ? _rename_stage_io_ren2_uops_1_prs1 : {1'h0, dis_uops_1_lrs1}; // @[core.scala:116:33, :190:24, :698:{28,52}] assign _dis_uops_1_prs1_T_3 = _dis_uops_1_prs1_T ? _fp_rename_stage_io_ren2_uops_1_prs1 : _dis_uops_1_prs1_T_2; // @[core.scala:117:33, :697:{28,52}, :698:28] assign dis_uops_1_prs1 = _dis_uops_1_prs1_T_3; // @[core.scala:190:24, :697:28] wire _GEN_62 = dis_uops_1_lrs2_rtype == 2'h1; // @[core.scala:190:24, :699:52] wire _dis_uops_1_prs2_T; // @[core.scala:699:52] assign _dis_uops_1_prs2_T = _GEN_62; // @[core.scala:699:52] wire _dis_uops_1_prs2_busy_T_2; // @[core.scala:715:73] assign _dis_uops_1_prs2_busy_T_2 = _GEN_62; // @[core.scala:699:52, :715:73] assign _dis_uops_1_prs2_T_1 = _dis_uops_1_prs2_T ? _fp_rename_stage_io_ren2_uops_1_prs2 : _rename_stage_io_ren2_uops_1_prs2; // @[core.scala:116:33, :117:33, :699:{28,52}] assign dis_uops_1_prs2 = _dis_uops_1_prs2_T_1; // @[core.scala:190:24, :699:28] wire _GEN_63 = dis_uops_1_dst_rtype == 2'h1; // @[core.scala:190:24, :702:52] wire _dis_uops_1_pdst_T; // @[core.scala:702:52] assign _dis_uops_1_pdst_T = _GEN_63; // @[core.scala:702:52] wire _dis_uops_1_stale_pdst_T; // @[core.scala:710:57] assign _dis_uops_1_stale_pdst_T = _GEN_63; // @[core.scala:702:52, :710:57] wire _dis_uops_1_pdst_T_1 = dis_uops_1_dst_rtype == 2'h0; // @[core.scala:190:24, :703:52] wire _dis_uops_1_pdst_T_2 = |dis_uops_1_br_type; // @[core.scala:190:24] wire _dis_uops_1_pdst_T_3 = _dis_uops_1_pdst_T_2 & dis_uops_1_is_sfb; // @[core.scala:190:24] wire _dis_uops_1_pdst_T_4 = _dis_uops_1_pdst_T_3; // @[micro-op.scala:120:{42,52}] wire [1:0] dis_uops_1_pdst_lo_hi = {_dis_uops_1_pdst_prng_io_out_2, _dis_uops_1_pdst_prng_io_out_1}; // @[PRNG.scala:91:22, :95:17] wire [2:0] dis_uops_1_pdst_lo = {dis_uops_1_pdst_lo_hi, _dis_uops_1_pdst_prng_io_out_0}; // @[PRNG.scala:91:22, :95:17] wire [1:0] dis_uops_1_pdst_hi_lo = {_dis_uops_1_pdst_prng_io_out_4, _dis_uops_1_pdst_prng_io_out_3}; // @[PRNG.scala:91:22, :95:17] wire [1:0] dis_uops_1_pdst_hi_hi = {_dis_uops_1_pdst_prng_io_out_6, _dis_uops_1_pdst_prng_io_out_5}; // @[PRNG.scala:91:22, :95:17] wire [3:0] dis_uops_1_pdst_hi = {dis_uops_1_pdst_hi_hi, dis_uops_1_pdst_hi_lo}; // @[PRNG.scala:95:17] wire [6:0] _dis_uops_1_pdst_T_5 = {dis_uops_1_pdst_hi, dis_uops_1_pdst_lo}; // @[PRNG.scala:95:17] wire [6:0] _dis_uops_1_pdst_T_6 = _dis_uops_1_pdst_T_4 ? _pred_rename_stage_io_ren2_uops_1_pdst : _dis_uops_1_pdst_T_5; // @[PRNG.scala:95:17] wire [6:0] _dis_uops_1_pdst_T_7 = _dis_uops_1_pdst_T_1 ? _rename_stage_io_ren2_uops_1_pdst : _dis_uops_1_pdst_T_6; // @[core.scala:116:33, :703:{28,52}, :704:28] assign _dis_uops_1_pdst_T_8 = _dis_uops_1_pdst_T ? _fp_rename_stage_io_ren2_uops_1_pdst : _dis_uops_1_pdst_T_7; // @[core.scala:117:33, :702:{28,52}, :703:28] assign dis_uops_1_pdst = _dis_uops_1_pdst_T_8; // @[core.scala:190:24, :702:28] assign _dis_uops_1_stale_pdst_T_1 = _dis_uops_1_stale_pdst_T ? _fp_rename_stage_io_ren2_uops_1_stale_pdst : _rename_stage_io_ren2_uops_1_stale_pdst; // @[core.scala:116:33, :117:33, :710:{34,57}] assign dis_uops_1_stale_pdst = _dis_uops_1_stale_pdst_T_1; // @[core.scala:190:24, :710:34] wire _dis_uops_1_prs1_busy_T_1 = _rename_stage_io_ren2_uops_1_prs1_busy & _dis_uops_1_prs1_busy_T; // @[core.scala:116:33, :712:{46,73}] wire _dis_uops_1_prs1_busy_T_3 = _fp_rename_stage_io_ren2_uops_1_prs1_busy & _dis_uops_1_prs1_busy_T_2; // @[core.scala:117:33, :713:{46,73}] assign _dis_uops_1_prs1_busy_T_4 = _dis_uops_1_prs1_busy_T_1 | _dis_uops_1_prs1_busy_T_3; // @[core.scala:712:{46,85}, :713:46] assign dis_uops_1_prs1_busy = _dis_uops_1_prs1_busy_T_4; // @[core.scala:190:24, :712:85] wire _dis_uops_1_prs2_busy_T = dis_uops_1_lrs2_rtype == 2'h0; // @[core.scala:190:24, :714:73] wire _dis_uops_1_prs2_busy_T_1 = _rename_stage_io_ren2_uops_1_prs2_busy & _dis_uops_1_prs2_busy_T; // @[core.scala:116:33, :714:{46,73}] wire _dis_uops_1_prs2_busy_T_3 = _fp_rename_stage_io_ren2_uops_1_prs2_busy & _dis_uops_1_prs2_busy_T_2; // @[core.scala:117:33, :715:{46,73}] assign _dis_uops_1_prs2_busy_T_4 = _dis_uops_1_prs2_busy_T_1 | _dis_uops_1_prs2_busy_T_3; // @[core.scala:714:{46,85}, :715:46] assign dis_uops_1_prs2_busy = _dis_uops_1_prs2_busy_T_4; // @[core.scala:190:24, :714:85] assign _dis_uops_1_prs3_busy_T = _fp_rename_stage_io_ren2_uops_1_prs3_busy & dis_uops_1_frs3_en; // @[core.scala:117:33, :190:24, :716:46] assign dis_uops_1_prs3_busy = _dis_uops_1_prs3_busy_T; // @[core.scala:190:24, :716:46] wire _dis_uops_1_ppred_busy_T = ~(|dis_uops_1_br_type); // @[core.scala:190:24] wire _dis_uops_1_ppred_busy_T_1 = _dis_uops_1_ppred_busy_T & dis_uops_1_is_sfb; // @[core.scala:190:24] wire _dis_uops_1_ppred_busy_T_2 = _dis_uops_1_ppred_busy_T_1; // @[micro-op.scala:121:{42,52}] assign _dis_uops_1_ppred_busy_T_3 = _pred_rename_stage_io_ren2_uops_1_ppred_busy & _dis_uops_1_ppred_busy_T_2; // @[core.scala:118:33, :717:48] assign dis_uops_1_ppred_busy = _dis_uops_1_ppred_busy_T_3; // @[core.scala:190:24, :717:48] wire _ren_stalls_1_T = _rename_stage_io_ren_stalls_1 | _fp_rename_stage_io_ren_stalls_1; // @[core.scala:116:33, :117:33, :719:52] wire _ren_stalls_1_T_1 = _ren_stalls_1_T; // @[core.scala:719:{52,63}] assign _ren_stalls_1_T_2 = _ren_stalls_1_T_1 | _imm_rename_stage_io_ren_stalls_1; // @[core.scala:119:33, :719:{63,74}] assign ren_stalls_1 = _ren_stalls_1_T_2; // @[core.scala:186:24, :719:74] wire dis_prior_slot_valid_2 = dis_prior_slot_valid_1 | dis_valids_1; // @[core.scala:189:24, :731:71] wire _dis_prior_slot_unique_T = dis_valids_0 & dis_uops_0_is_unique; // @[core.scala:189:24, :190:24, :732:101] wire dis_prior_slot_unique_1 = _dis_prior_slot_unique_T; // @[core.scala:732:{96,101}] wire _dis_prior_slot_unique_T_1 = dis_valids_1 & dis_uops_1_is_unique; // @[core.scala:189:24, :190:24, :732:101] wire dis_prior_slot_unique_2 = dis_prior_slot_unique_1 | _dis_prior_slot_unique_T_1; // @[core.scala:732:{96,101}] wire _wait_for_empty_pipeline_T = custom_csrs_csrs_0_value[0]; // @[core.scala:301:25] wire _wait_for_empty_pipeline_T_10 = custom_csrs_csrs_0_value[0]; // @[core.scala:301:25] wire _wait_for_empty_pipeline_T_1 = custom_csrs_csrs_2_value[3]; // @[core.scala:301:25] wire _wait_for_empty_pipeline_T_11 = custom_csrs_csrs_2_value[3]; // @[core.scala:301:25] wire _wait_for_empty_pipeline_T_2 = ~_wait_for_empty_pipeline_T_1; // @[parameters.scala:181:{66,96}] wire _wait_for_empty_pipeline_T_3 = _wait_for_empty_pipeline_T & _wait_for_empty_pipeline_T_2; // @[parameters.scala:181:{50,63,66}] wire _wait_for_empty_pipeline_T_4 = ~_wait_for_empty_pipeline_T_3; // @[core.scala:733:88] wire _wait_for_empty_pipeline_T_5 = dis_uops_0_is_unique | _wait_for_empty_pipeline_T_4; // @[core.scala:190:24, :733:{85,88}] wire _wait_for_empty_pipeline_T_6 = ~_rob_io_empty; // @[core.scala:159:32, :607:6, :734:36] wire _wait_for_empty_pipeline_T_7 = ~io_lsu_fencei_rdy_0; // @[core.scala:50:7, :607:23, :734:53] wire _wait_for_empty_pipeline_T_8 = _wait_for_empty_pipeline_T_6 | _wait_for_empty_pipeline_T_7; // @[core.scala:734:{36,50,53}] wire _wait_for_empty_pipeline_T_9 = _wait_for_empty_pipeline_T_8; // @[core.scala:734:{50,72}] wire wait_for_empty_pipeline_0 = _wait_for_empty_pipeline_T_5 & _wait_for_empty_pipeline_T_9; // @[core.scala:733:{85,112}, :734:72] wire _wait_for_empty_pipeline_T_12 = ~_wait_for_empty_pipeline_T_11; // @[parameters.scala:181:{66,96}] wire _wait_for_empty_pipeline_T_13 = _wait_for_empty_pipeline_T_10 & _wait_for_empty_pipeline_T_12; // @[parameters.scala:181:{50,63,66}] wire _wait_for_empty_pipeline_T_14 = ~_wait_for_empty_pipeline_T_13; // @[core.scala:733:88] wire _wait_for_empty_pipeline_T_15 = dis_uops_1_is_unique | _wait_for_empty_pipeline_T_14; // @[core.scala:190:24, :733:{85,88}] wire _wait_for_empty_pipeline_T_16 = ~_rob_io_empty; // @[core.scala:159:32, :607:6, :734:36] wire _wait_for_empty_pipeline_T_17 = ~io_lsu_fencei_rdy_0; // @[core.scala:50:7, :607:23, :734:53] wire _wait_for_empty_pipeline_T_18 = _wait_for_empty_pipeline_T_16 | _wait_for_empty_pipeline_T_17; // @[core.scala:734:{36,50,53}] wire _wait_for_empty_pipeline_T_19 = _wait_for_empty_pipeline_T_18 | dis_prior_slot_valid_1; // @[core.scala:731:71, :734:{50,72}] wire wait_for_empty_pipeline_1 = _wait_for_empty_pipeline_T_15 & _wait_for_empty_pipeline_T_19; // @[core.scala:733:{85,112}, :734:72] wire _wait_for_rocc_T = dis_uops_0_is_fence | dis_uops_0_is_fencei; // @[core.scala:190:24, :737:47] wire _wait_for_rocc_T_2 = dis_uops_1_is_fence | dis_uops_1_is_fencei; // @[core.scala:190:24, :737:47] wire _block_rocc_T = dis_valids_0 & dis_uops_0_is_rocc; // @[core.scala:189:24, :190:24, :739:66] wire block_rocc_1 = _block_rocc_T; // @[core.scala:739:{66,100}] wire _block_rocc_T_1 = dis_valids_1 & dis_uops_1_is_rocc; // @[core.scala:189:24, :190:24, :739:66] wire block_rocc_2 = block_rocc_1 | _block_rocc_T_1; // @[core.scala:739:{66,100}] wire _GEN_64 = dis_uops_0_br_type == 4'h1; // @[package.scala:16:47] wire _block_brtag_T; // @[package.scala:16:47] assign _block_brtag_T = _GEN_64; // @[package.scala:16:47] wire _brtag_stall_T; // @[package.scala:16:47] assign _brtag_stall_T = _GEN_64; // @[package.scala:16:47] wire _GEN_65 = dis_uops_0_br_type == 4'h2; // @[package.scala:16:47] wire _block_brtag_T_1; // @[package.scala:16:47] assign _block_brtag_T_1 = _GEN_65; // @[package.scala:16:47] wire _brtag_stall_T_1; // @[package.scala:16:47] assign _brtag_stall_T_1 = _GEN_65; // @[package.scala:16:47] wire _GEN_66 = dis_uops_0_br_type == 4'h3; // @[package.scala:16:47] wire _block_brtag_T_2; // @[package.scala:16:47] assign _block_brtag_T_2 = _GEN_66; // @[package.scala:16:47] wire _brtag_stall_T_2; // @[package.scala:16:47] assign _brtag_stall_T_2 = _GEN_66; // @[package.scala:16:47] wire _GEN_67 = dis_uops_0_br_type == 4'h4; // @[package.scala:16:47] wire _block_brtag_T_3; // @[package.scala:16:47] assign _block_brtag_T_3 = _GEN_67; // @[package.scala:16:47] wire _brtag_stall_T_3; // @[package.scala:16:47] assign _brtag_stall_T_3 = _GEN_67; // @[package.scala:16:47] wire _GEN_68 = dis_uops_0_br_type == 4'h5; // @[package.scala:16:47] wire _block_brtag_T_4; // @[package.scala:16:47] assign _block_brtag_T_4 = _GEN_68; // @[package.scala:16:47] wire _brtag_stall_T_4; // @[package.scala:16:47] assign _brtag_stall_T_4 = _GEN_68; // @[package.scala:16:47] wire _GEN_69 = dis_uops_0_br_type == 4'h6; // @[package.scala:16:47] wire _block_brtag_T_5; // @[package.scala:16:47] assign _block_brtag_T_5 = _GEN_69; // @[package.scala:16:47] wire _brtag_stall_T_5; // @[package.scala:16:47] assign _brtag_stall_T_5 = _GEN_69; // @[package.scala:16:47] wire _block_brtag_T_6 = _block_brtag_T | _block_brtag_T_1; // @[package.scala:16:47, :81:59] wire _block_brtag_T_7 = _block_brtag_T_6 | _block_brtag_T_2; // @[package.scala:16:47, :81:59] wire _block_brtag_T_8 = _block_brtag_T_7 | _block_brtag_T_3; // @[package.scala:16:47, :81:59] wire _block_brtag_T_9 = _block_brtag_T_8 | _block_brtag_T_4; // @[package.scala:16:47, :81:59] wire _block_brtag_T_10 = _block_brtag_T_9 | _block_brtag_T_5; // @[package.scala:16:47, :81:59] wire _block_brtag_T_11 = ~dis_uops_0_is_sfb; // @[core.scala:190:24] wire _block_brtag_T_12 = _block_brtag_T_10 & _block_brtag_T_11; // @[package.scala:81:59] wire _GEN_70 = dis_uops_0_br_type == 4'h8; // @[core.scala:190:24] wire _block_brtag_T_13; // @[micro-op.scala:119:34] assign _block_brtag_T_13 = _GEN_70; // @[micro-op.scala:119:34] wire _brtag_stall_T_13; // @[micro-op.scala:119:34] assign _brtag_stall_T_13 = _GEN_70; // @[micro-op.scala:119:34] wire _block_brtag_T_14 = _block_brtag_T_12 | _block_brtag_T_13; // @[micro-op.scala:119:34, :160:{33,45}] wire _block_brtag_T_15 = dis_valids_0 & _block_brtag_T_14; // @[core.scala:189:24, :745:67] wire block_brtag_1 = _block_brtag_T_15; // @[core.scala:745:{67,107}] wire _GEN_71 = dis_uops_1_br_type == 4'h1; // @[package.scala:16:47] wire _block_brtag_T_16; // @[package.scala:16:47] assign _block_brtag_T_16 = _GEN_71; // @[package.scala:16:47] wire _brtag_stall_T_15; // @[package.scala:16:47] assign _brtag_stall_T_15 = _GEN_71; // @[package.scala:16:47] wire _GEN_72 = dis_uops_1_br_type == 4'h2; // @[package.scala:16:47] wire _block_brtag_T_17; // @[package.scala:16:47] assign _block_brtag_T_17 = _GEN_72; // @[package.scala:16:47] wire _brtag_stall_T_16; // @[package.scala:16:47] assign _brtag_stall_T_16 = _GEN_72; // @[package.scala:16:47] wire _GEN_73 = dis_uops_1_br_type == 4'h3; // @[package.scala:16:47] wire _block_brtag_T_18; // @[package.scala:16:47] assign _block_brtag_T_18 = _GEN_73; // @[package.scala:16:47] wire _brtag_stall_T_17; // @[package.scala:16:47] assign _brtag_stall_T_17 = _GEN_73; // @[package.scala:16:47] wire _GEN_74 = dis_uops_1_br_type == 4'h4; // @[package.scala:16:47] wire _block_brtag_T_19; // @[package.scala:16:47] assign _block_brtag_T_19 = _GEN_74; // @[package.scala:16:47] wire _brtag_stall_T_18; // @[package.scala:16:47] assign _brtag_stall_T_18 = _GEN_74; // @[package.scala:16:47] wire _GEN_75 = dis_uops_1_br_type == 4'h5; // @[package.scala:16:47] wire _block_brtag_T_20; // @[package.scala:16:47] assign _block_brtag_T_20 = _GEN_75; // @[package.scala:16:47] wire _brtag_stall_T_19; // @[package.scala:16:47] assign _brtag_stall_T_19 = _GEN_75; // @[package.scala:16:47] wire _GEN_76 = dis_uops_1_br_type == 4'h6; // @[package.scala:16:47] wire _block_brtag_T_21; // @[package.scala:16:47] assign _block_brtag_T_21 = _GEN_76; // @[package.scala:16:47] wire _brtag_stall_T_20; // @[package.scala:16:47] assign _brtag_stall_T_20 = _GEN_76; // @[package.scala:16:47] wire _block_brtag_T_22 = _block_brtag_T_16 | _block_brtag_T_17; // @[package.scala:16:47, :81:59] wire _block_brtag_T_23 = _block_brtag_T_22 | _block_brtag_T_18; // @[package.scala:16:47, :81:59] wire _block_brtag_T_24 = _block_brtag_T_23 | _block_brtag_T_19; // @[package.scala:16:47, :81:59] wire _block_brtag_T_25 = _block_brtag_T_24 | _block_brtag_T_20; // @[package.scala:16:47, :81:59] wire _block_brtag_T_26 = _block_brtag_T_25 | _block_brtag_T_21; // @[package.scala:16:47, :81:59] wire _block_brtag_T_27 = ~dis_uops_1_is_sfb; // @[core.scala:190:24] wire _block_brtag_T_28 = _block_brtag_T_26 & _block_brtag_T_27; // @[package.scala:81:59] wire _GEN_77 = dis_uops_1_br_type == 4'h8; // @[core.scala:190:24] wire _block_brtag_T_29; // @[micro-op.scala:119:34] assign _block_brtag_T_29 = _GEN_77; // @[micro-op.scala:119:34] wire _brtag_stall_T_28; // @[micro-op.scala:119:34] assign _brtag_stall_T_28 = _GEN_77; // @[micro-op.scala:119:34] wire _block_brtag_T_30 = _block_brtag_T_28 | _block_brtag_T_29; // @[micro-op.scala:119:34, :160:{33,45}] wire _block_brtag_T_31 = dis_valids_1 & _block_brtag_T_30; // @[core.scala:189:24, :745:67] wire block_brtag_2 = block_brtag_1 | _block_brtag_T_31; // @[core.scala:745:{67,107}] wire _brtag_stall_T_6 = _brtag_stall_T | _brtag_stall_T_1; // @[package.scala:16:47, :81:59] wire _brtag_stall_T_7 = _brtag_stall_T_6 | _brtag_stall_T_2; // @[package.scala:16:47, :81:59] wire _brtag_stall_T_8 = _brtag_stall_T_7 | _brtag_stall_T_3; // @[package.scala:16:47, :81:59] wire _brtag_stall_T_9 = _brtag_stall_T_8 | _brtag_stall_T_4; // @[package.scala:16:47, :81:59] wire _brtag_stall_T_10 = _brtag_stall_T_9 | _brtag_stall_T_5; // @[package.scala:16:47, :81:59] wire _brtag_stall_T_11 = ~dis_uops_0_is_sfb; // @[core.scala:190:24] wire _brtag_stall_T_12 = _brtag_stall_T_10 & _brtag_stall_T_11; // @[package.scala:81:59] wire _brtag_stall_T_14 = _brtag_stall_T_12 | _brtag_stall_T_13; // @[micro-op.scala:119:34, :160:{33,45}] wire _brtag_stall_T_21 = _brtag_stall_T_15 | _brtag_stall_T_16; // @[package.scala:16:47, :81:59] wire _brtag_stall_T_22 = _brtag_stall_T_21 | _brtag_stall_T_17; // @[package.scala:16:47, :81:59] wire _brtag_stall_T_23 = _brtag_stall_T_22 | _brtag_stall_T_18; // @[package.scala:16:47, :81:59] wire _brtag_stall_T_24 = _brtag_stall_T_23 | _brtag_stall_T_19; // @[package.scala:16:47, :81:59] wire _brtag_stall_T_25 = _brtag_stall_T_24 | _brtag_stall_T_20; // @[package.scala:16:47, :81:59] wire _brtag_stall_T_26 = ~dis_uops_1_is_sfb; // @[core.scala:190:24] wire _brtag_stall_T_27 = _brtag_stall_T_25 & _brtag_stall_T_26; // @[package.scala:81:59] wire _brtag_stall_T_29 = _brtag_stall_T_27 | _brtag_stall_T_28; // @[micro-op.scala:119:34, :160:{33,45}] wire _dis_hazards_T = ~_rob_io_ready; // @[core.scala:159:32, :750:26] wire _dis_hazards_T_1 = _dis_hazards_T; // @[core.scala:750:26, :751:23] wire _dis_hazards_T_2 = _dis_hazards_T_1 | ren_stalls_0; // @[core.scala:186:24, :751:23, :752:23] wire _dis_hazards_T_3 = io_lsu_ldq_full_0_0 & dis_uops_0_uses_ldq; // @[core.scala:50:7, :190:24, :753:45] wire _dis_hazards_T_4 = _dis_hazards_T_2 | _dis_hazards_T_3; // @[core.scala:752:23, :753:{23,45}] wire _dis_hazards_T_5 = io_lsu_stq_full_0_0 & dis_uops_0_uses_stq; // @[core.scala:50:7, :190:24, :754:45] wire _dis_hazards_T_6 = _dis_hazards_T_4 | _dis_hazards_T_5; // @[core.scala:753:23, :754:{23,45}] wire _dis_hazards_T_7 = ~_dispatcher_io_ren_uops_0_ready; // @[core.scala:125:32, :755:26] wire _dis_hazards_T_8 = _dis_hazards_T_6 | _dis_hazards_T_7; // @[core.scala:754:23, :755:{23,26}] wire _dis_hazards_T_9 = _dis_hazards_T_8 | wait_for_empty_pipeline_0; // @[core.scala:733:112, :755:23, :756:23] wire _dis_hazards_T_10 = _dis_hazards_T_9; // @[core.scala:756:23, :757:23] wire _dis_hazards_T_11 = _dis_hazards_T_10; // @[core.scala:757:23, :758:23] wire _dis_hazards_T_12 = _dis_hazards_T_11; // @[core.scala:758:23, :759:23] wire _dis_hazards_T_13 = |brupdate_b1_mispredict_mask; // @[core.scala:209:23, :238:42, :760:54] wire _dis_hazards_T_14 = _dis_hazards_T_12 | _dis_hazards_T_13; // @[core.scala:759:23, :760:{23,54}] wire _dis_hazards_T_15 = _dis_hazards_T_14 | brupdate_b2_mispredict; // @[core.scala:209:23, :760:23, :761:23] wire _dis_hazards_T_16 = _dis_hazards_T_15 | io_ifu_redirect_flush_0; // @[core.scala:50:7, :761:23, :762:23] wire dis_hazards_0 = dis_valids_0 & _dis_hazards_T_16; // @[core.scala:189:24, :749:37, :762:23] wire dis_stalls_0 = dis_hazards_0; // @[core.scala:749:37, :767:62] wire _dis_hazards_T_17 = ~_rob_io_ready; // @[core.scala:159:32, :750:26] wire _dis_hazards_T_18 = _dis_hazards_T_17; // @[core.scala:750:26, :751:23] wire _dis_hazards_T_19 = _dis_hazards_T_18 | ren_stalls_1; // @[core.scala:186:24, :751:23, :752:23] wire _dis_hazards_T_20 = io_lsu_ldq_full_1_0 & dis_uops_1_uses_ldq; // @[core.scala:50:7, :190:24, :753:45] wire _dis_hazards_T_21 = _dis_hazards_T_19 | _dis_hazards_T_20; // @[core.scala:752:23, :753:{23,45}] wire _dis_hazards_T_22 = io_lsu_stq_full_1_0 & dis_uops_1_uses_stq; // @[core.scala:50:7, :190:24, :754:45] wire _dis_hazards_T_23 = _dis_hazards_T_21 | _dis_hazards_T_22; // @[core.scala:753:23, :754:{23,45}] wire _dis_hazards_T_24 = ~_dispatcher_io_ren_uops_1_ready; // @[core.scala:125:32, :755:26] wire _dis_hazards_T_25 = _dis_hazards_T_23 | _dis_hazards_T_24; // @[core.scala:754:23, :755:{23,26}] wire _dis_hazards_T_26 = _dis_hazards_T_25 | wait_for_empty_pipeline_1; // @[core.scala:733:112, :755:23, :756:23] wire _dis_hazards_T_27 = _dis_hazards_T_26; // @[core.scala:756:23, :757:23] wire _dis_hazards_T_28 = _dis_hazards_T_27 | dis_prior_slot_unique_1; // @[core.scala:732:96, :757:23, :758:23] wire _dis_hazards_T_29 = _dis_hazards_T_28; // @[core.scala:758:23, :759:23] wire _dis_hazards_T_30 = |brupdate_b1_mispredict_mask; // @[core.scala:209:23, :238:42, :760:54] wire _dis_hazards_T_31 = _dis_hazards_T_29 | _dis_hazards_T_30; // @[core.scala:759:23, :760:{23,54}] wire _dis_hazards_T_32 = _dis_hazards_T_31 | brupdate_b2_mispredict; // @[core.scala:209:23, :760:23, :761:23] wire _dis_hazards_T_33 = _dis_hazards_T_32 | io_ifu_redirect_flush_0; // @[core.scala:50:7, :761:23, :762:23] wire dis_hazards_1 = dis_valids_1 & _dis_hazards_T_33; // @[core.scala:189:24, :749:37, :762:23] wire _io_lsu_fence_dmem_T = dis_valids_0 & wait_for_empty_pipeline_0; // @[core.scala:189:24, :733:112, :765:86] wire _io_lsu_fence_dmem_T_1 = dis_valids_1 & wait_for_empty_pipeline_1; // @[core.scala:189:24, :733:112, :765:86] assign _io_lsu_fence_dmem_T_2 = _io_lsu_fence_dmem_T | _io_lsu_fence_dmem_T_1; // @[core.scala:765:{86,101}] assign io_lsu_fence_dmem_0 = _io_lsu_fence_dmem_T_2; // @[core.scala:50:7, :765:101] wire dis_stalls_1 = dis_stalls_0 | dis_hazards_1; // @[core.scala:749:37, :767:62] assign dis_fire_0 = dis_valids_0 & ~dis_stalls_0; // @[core.scala:189:24, :191:24, :767:62, :768:{62,65}] assign dis_fire_1 = dis_valids_1 & ~dis_stalls_1; // @[core.scala:189:24, :191:24, :767:62, :768:{62,65}] assign _dis_ready_T = ~dis_stalls_1; // @[core.scala:767:62, :768:65, :769:16] assign dis_ready = _dis_ready_T; // @[core.scala:192:24, :769:16] reg REG_2; // @[core.scala:792:16] assign io_ifu_commit_valid_0 = REG_2 | _io_ifu_commit_valid_T_1; // @[core.scala:50:7, :486:{23,59}, :792:{16,94}, :793:25] wire _io_ifu_commit_bits_T_1 = ~dis_valids_0; // @[Mux.scala:50:70] reg [4:0] io_ifu_commit_bits_REG; // @[core.scala:794:35] assign io_ifu_commit_bits_0 = {27'h0, REG_2 ? io_ifu_commit_bits_REG : _io_ifu_commit_bits_T}; // @[core.scala:50:7, :487:{23,29}, :792:{16,94}, :794:{25,35}] wire [5:0] _GEN_78 = {1'h0, _rob_io_rob_tail_idx[5:1]}; // @[core.scala:159:32, :803:54] wire [5:0] _dis_uops_0_rob_idx_T; // @[core.scala:803:54] assign _dis_uops_0_rob_idx_T = _GEN_78; // @[core.scala:803:54] wire [5:0] _dis_uops_1_rob_idx_T; // @[core.scala:803:54] assign _dis_uops_1_rob_idx_T = _GEN_78; // @[core.scala:803:54] wire [6:0] _dis_uops_0_rob_idx_T_1 = {_dis_uops_0_rob_idx_T, 1'h0}; // @[core.scala:803:{33,54}] assign dis_uops_0_rob_idx = _dis_uops_0_rob_idx_T_1[5:0]; // @[core.scala:190:24, :803:{27,33}] wire [6:0] _dis_uops_1_rob_idx_T_1 = {_dis_uops_1_rob_idx_T, 1'h1}; // @[core.scala:803:{33,54}] assign dis_uops_1_rob_idx = _dis_uops_1_rob_idx_T_1[5:0]; // @[core.scala:190:24, :803:{27,33}] reg [31:0] uop_inst; // @[core.scala:847:22] reg [31:0] uop_debug_inst; // @[core.scala:847:22] reg uop_is_rvc; // @[core.scala:847:22] reg [39:0] uop_debug_pc; // @[core.scala:847:22] reg uop_iq_type_0; // @[core.scala:847:22] reg uop_iq_type_1; // @[core.scala:847:22] reg uop_iq_type_2; // @[core.scala:847:22] reg uop_iq_type_3; // @[core.scala:847:22] reg uop_fu_code_0; // @[core.scala:847:22] reg uop_fu_code_1; // @[core.scala:847:22] reg uop_fu_code_2; // @[core.scala:847:22] reg uop_fu_code_3; // @[core.scala:847:22] reg uop_fu_code_4; // @[core.scala:847:22] reg uop_fu_code_5; // @[core.scala:847:22] reg uop_fu_code_6; // @[core.scala:847:22] reg uop_fu_code_7; // @[core.scala:847:22] reg uop_fu_code_8; // @[core.scala:847:22] reg uop_fu_code_9; // @[core.scala:847:22] reg uop_iw_issued; // @[core.scala:847:22] reg uop_iw_issued_partial_agen; // @[core.scala:847:22] reg uop_iw_issued_partial_dgen; // @[core.scala:847:22] reg [1:0] uop_iw_p1_speculative_child; // @[core.scala:847:22] reg [1:0] uop_iw_p2_speculative_child; // @[core.scala:847:22] reg uop_iw_p1_bypass_hint; // @[core.scala:847:22] reg uop_iw_p2_bypass_hint; // @[core.scala:847:22] reg uop_iw_p3_bypass_hint; // @[core.scala:847:22] reg [1:0] uop_dis_col_sel; // @[core.scala:847:22] reg [11:0] uop_br_mask; // @[core.scala:847:22] reg [3:0] uop_br_tag; // @[core.scala:847:22] reg [3:0] uop_br_type; // @[core.scala:847:22] reg uop_is_sfb; // @[core.scala:847:22] reg uop_is_fence; // @[core.scala:847:22] reg uop_is_fencei; // @[core.scala:847:22] reg uop_is_sfence; // @[core.scala:847:22] reg uop_is_amo; // @[core.scala:847:22] reg uop_is_eret; // @[core.scala:847:22] reg uop_is_sys_pc2epc; // @[core.scala:847:22] reg uop_is_rocc; // @[core.scala:847:22] reg uop_is_mov; // @[core.scala:847:22] reg [4:0] uop_ftq_idx; // @[core.scala:847:22] reg uop_edge_inst; // @[core.scala:847:22] reg [5:0] uop_pc_lob; // @[core.scala:847:22] reg uop_taken; // @[core.scala:847:22] reg uop_imm_rename; // @[core.scala:847:22] reg [2:0] uop_imm_sel; // @[core.scala:847:22] reg [4:0] uop_pimm; // @[core.scala:847:22] reg [19:0] uop_imm_packed; // @[core.scala:847:22] reg [1:0] uop_op1_sel; // @[core.scala:847:22] reg [2:0] uop_op2_sel; // @[core.scala:847:22] reg uop_fp_ctrl_ldst; // @[core.scala:847:22] reg uop_fp_ctrl_wen; // @[core.scala:847:22] reg uop_fp_ctrl_ren1; // @[core.scala:847:22] reg uop_fp_ctrl_ren2; // @[core.scala:847:22] reg uop_fp_ctrl_ren3; // @[core.scala:847:22] reg uop_fp_ctrl_swap12; // @[core.scala:847:22] reg uop_fp_ctrl_swap23; // @[core.scala:847:22] reg [1:0] uop_fp_ctrl_typeTagIn; // @[core.scala:847:22] reg [1:0] uop_fp_ctrl_typeTagOut; // @[core.scala:847:22] reg uop_fp_ctrl_fromint; // @[core.scala:847:22] reg uop_fp_ctrl_toint; // @[core.scala:847:22] reg uop_fp_ctrl_fastpipe; // @[core.scala:847:22] reg uop_fp_ctrl_fma; // @[core.scala:847:22] reg uop_fp_ctrl_div; // @[core.scala:847:22] reg uop_fp_ctrl_sqrt; // @[core.scala:847:22] reg uop_fp_ctrl_wflags; // @[core.scala:847:22] reg uop_fp_ctrl_vec; // @[core.scala:847:22] reg [5:0] uop_rob_idx; // @[core.scala:847:22] reg [3:0] uop_ldq_idx; // @[core.scala:847:22] reg [3:0] uop_stq_idx; // @[core.scala:847:22] reg [1:0] uop_rxq_idx; // @[core.scala:847:22] reg [6:0] uop_pdst; // @[core.scala:847:22] reg [6:0] uop_prs1; // @[core.scala:847:22] reg [6:0] uop_prs2; // @[core.scala:847:22] reg [6:0] uop_prs3; // @[core.scala:847:22] reg [4:0] uop_ppred; // @[core.scala:847:22] reg uop_prs1_busy; // @[core.scala:847:22] reg uop_prs2_busy; // @[core.scala:847:22] reg uop_prs3_busy; // @[core.scala:847:22] reg uop_ppred_busy; // @[core.scala:847:22] reg [6:0] uop_stale_pdst; // @[core.scala:847:22] reg uop_exception; // @[core.scala:847:22] reg [63:0] uop_exc_cause; // @[core.scala:847:22] reg [4:0] uop_mem_cmd; // @[core.scala:847:22] reg [1:0] uop_mem_size; // @[core.scala:847:22] reg uop_mem_signed; // @[core.scala:847:22] reg uop_uses_ldq; // @[core.scala:847:22] reg uop_uses_stq; // @[core.scala:847:22] reg uop_is_unique; // @[core.scala:847:22] reg uop_flush_on_commit; // @[core.scala:847:22] reg [2:0] uop_csr_cmd; // @[core.scala:847:22] reg uop_ldst_is_rs1; // @[core.scala:847:22] reg [5:0] uop_ldst; // @[core.scala:847:22] reg [5:0] uop_lrs1; // @[core.scala:847:22] reg [5:0] uop_lrs2; // @[core.scala:847:22] reg [5:0] uop_lrs3; // @[core.scala:847:22] reg [1:0] uop_dst_rtype; // @[core.scala:847:22] reg [1:0] uop_lrs1_rtype; // @[core.scala:847:22] reg [1:0] uop_lrs2_rtype; // @[core.scala:847:22] reg uop_frs3_en; // @[core.scala:847:22] reg uop_fcn_dw; // @[core.scala:847:22] reg [4:0] uop_fcn_op; // @[core.scala:847:22] reg uop_fp_val; // @[core.scala:847:22] reg [2:0] uop_fp_rm; // @[core.scala:847:22] reg [1:0] uop_fp_typ; // @[core.scala:847:22] reg uop_xcpt_pf_if; // @[core.scala:847:22] reg uop_xcpt_ae_if; // @[core.scala:847:22] reg uop_xcpt_ma_if; // @[core.scala:847:22] reg uop_bp_debug_if; // @[core.scala:847:22] reg uop_bp_xcpt_if; // @[core.scala:847:22] reg [2:0] uop_debug_fsrc; // @[core.scala:847:22] reg [2:0] uop_debug_tsrc; // @[core.scala:847:22] reg immregfile_io_write_ports_0_valid_REG; // @[core.scala:849:54] wire _immregfile_io_write_ports_0_valid_T = uop_imm_sel == 3'h6; // @[package.scala:16:47] wire _immregfile_io_write_ports_0_valid_T_1 = uop_imm_sel == 3'h5; // @[package.scala:16:47] wire _immregfile_io_write_ports_0_valid_T_2 = _immregfile_io_write_ports_0_valid_T | _immregfile_io_write_ports_0_valid_T_1; // @[package.scala:16:47, :81:59] wire _immregfile_io_write_ports_0_valid_T_3 = ~_immregfile_io_write_ports_0_valid_T_2; // @[package.scala:81:59] wire _immregfile_io_write_ports_0_valid_T_4 = immregfile_io_write_ports_0_valid_REG & _immregfile_io_write_ports_0_valid_T_3; // @[core.scala:849:{54,68,71}] reg bregfile_io_write_ports_0_valid_REG; // @[core.scala:853:62] wire _bregfile_io_write_ports_0_valid_T = uop_br_type == 4'h1; // @[package.scala:16:47] wire _bregfile_io_write_ports_0_valid_T_1 = uop_br_type == 4'h2; // @[package.scala:16:47] wire _bregfile_io_write_ports_0_valid_T_2 = uop_br_type == 4'h3; // @[package.scala:16:47] wire _bregfile_io_write_ports_0_valid_T_3 = uop_br_type == 4'h4; // @[package.scala:16:47] wire _bregfile_io_write_ports_0_valid_T_4 = uop_br_type == 4'h5; // @[package.scala:16:47] wire _bregfile_io_write_ports_0_valid_T_5 = uop_br_type == 4'h6; // @[package.scala:16:47] wire _bregfile_io_write_ports_0_valid_T_6 = _bregfile_io_write_ports_0_valid_T | _bregfile_io_write_ports_0_valid_T_1; // @[package.scala:16:47, :81:59] wire _bregfile_io_write_ports_0_valid_T_7 = _bregfile_io_write_ports_0_valid_T_6 | _bregfile_io_write_ports_0_valid_T_2; // @[package.scala:16:47, :81:59] wire _bregfile_io_write_ports_0_valid_T_8 = _bregfile_io_write_ports_0_valid_T_7 | _bregfile_io_write_ports_0_valid_T_3; // @[package.scala:16:47, :81:59] wire _bregfile_io_write_ports_0_valid_T_9 = _bregfile_io_write_ports_0_valid_T_8 | _bregfile_io_write_ports_0_valid_T_4; // @[package.scala:16:47, :81:59] wire _bregfile_io_write_ports_0_valid_T_10 = _bregfile_io_write_ports_0_valid_T_9 | _bregfile_io_write_ports_0_valid_T_5; // @[package.scala:16:47, :81:59] wire _bregfile_io_write_ports_0_valid_T_11 = ~uop_is_sfb; // @[core.scala:847:22] wire _bregfile_io_write_ports_0_valid_T_12 = _bregfile_io_write_ports_0_valid_T_10 & _bregfile_io_write_ports_0_valid_T_11; // @[package.scala:81:59] wire _bregfile_io_write_ports_0_valid_T_13 = uop_br_type == 4'h8; // @[core.scala:847:22] wire _bregfile_io_write_ports_0_valid_T_14 = _bregfile_io_write_ports_0_valid_T_12 | _bregfile_io_write_ports_0_valid_T_13; // @[micro-op.scala:119:34, :160:{33,45}] wire _bregfile_io_write_ports_0_valid_T_15 = bregfile_io_write_ports_0_valid_REG & _bregfile_io_write_ports_0_valid_T_14; // @[core.scala:853:{62,76}] reg [31:0] uop_1_inst; // @[core.scala:847:22] reg [31:0] uop_1_debug_inst; // @[core.scala:847:22] reg uop_1_is_rvc; // @[core.scala:847:22] reg [39:0] uop_1_debug_pc; // @[core.scala:847:22] reg uop_1_iq_type_0; // @[core.scala:847:22] reg uop_1_iq_type_1; // @[core.scala:847:22] reg uop_1_iq_type_2; // @[core.scala:847:22] reg uop_1_iq_type_3; // @[core.scala:847:22] reg uop_1_fu_code_0; // @[core.scala:847:22] reg uop_1_fu_code_1; // @[core.scala:847:22] reg uop_1_fu_code_2; // @[core.scala:847:22] reg uop_1_fu_code_3; // @[core.scala:847:22] reg uop_1_fu_code_4; // @[core.scala:847:22] reg uop_1_fu_code_5; // @[core.scala:847:22] reg uop_1_fu_code_6; // @[core.scala:847:22] reg uop_1_fu_code_7; // @[core.scala:847:22] reg uop_1_fu_code_8; // @[core.scala:847:22] reg uop_1_fu_code_9; // @[core.scala:847:22] reg uop_1_iw_issued; // @[core.scala:847:22] reg uop_1_iw_issued_partial_agen; // @[core.scala:847:22] reg uop_1_iw_issued_partial_dgen; // @[core.scala:847:22] reg [1:0] uop_1_iw_p1_speculative_child; // @[core.scala:847:22] reg [1:0] uop_1_iw_p2_speculative_child; // @[core.scala:847:22] reg uop_1_iw_p1_bypass_hint; // @[core.scala:847:22] reg uop_1_iw_p2_bypass_hint; // @[core.scala:847:22] reg uop_1_iw_p3_bypass_hint; // @[core.scala:847:22] reg [1:0] uop_1_dis_col_sel; // @[core.scala:847:22] reg [11:0] uop_1_br_mask; // @[core.scala:847:22] reg [3:0] uop_1_br_tag; // @[core.scala:847:22] reg [3:0] uop_1_br_type; // @[core.scala:847:22] reg uop_1_is_sfb; // @[core.scala:847:22] reg uop_1_is_fence; // @[core.scala:847:22] reg uop_1_is_fencei; // @[core.scala:847:22] reg uop_1_is_sfence; // @[core.scala:847:22] reg uop_1_is_amo; // @[core.scala:847:22] reg uop_1_is_eret; // @[core.scala:847:22] reg uop_1_is_sys_pc2epc; // @[core.scala:847:22] reg uop_1_is_rocc; // @[core.scala:847:22] reg uop_1_is_mov; // @[core.scala:847:22] reg [4:0] uop_1_ftq_idx; // @[core.scala:847:22] reg uop_1_edge_inst; // @[core.scala:847:22] reg [5:0] uop_1_pc_lob; // @[core.scala:847:22] reg uop_1_taken; // @[core.scala:847:22] reg uop_1_imm_rename; // @[core.scala:847:22] reg [2:0] uop_1_imm_sel; // @[core.scala:847:22] reg [4:0] uop_1_pimm; // @[core.scala:847:22] reg [19:0] uop_1_imm_packed; // @[core.scala:847:22] reg [1:0] uop_1_op1_sel; // @[core.scala:847:22] reg [2:0] uop_1_op2_sel; // @[core.scala:847:22] reg uop_1_fp_ctrl_ldst; // @[core.scala:847:22] reg uop_1_fp_ctrl_wen; // @[core.scala:847:22] reg uop_1_fp_ctrl_ren1; // @[core.scala:847:22] reg uop_1_fp_ctrl_ren2; // @[core.scala:847:22] reg uop_1_fp_ctrl_ren3; // @[core.scala:847:22] reg uop_1_fp_ctrl_swap12; // @[core.scala:847:22] reg uop_1_fp_ctrl_swap23; // @[core.scala:847:22] reg [1:0] uop_1_fp_ctrl_typeTagIn; // @[core.scala:847:22] reg [1:0] uop_1_fp_ctrl_typeTagOut; // @[core.scala:847:22] reg uop_1_fp_ctrl_fromint; // @[core.scala:847:22] reg uop_1_fp_ctrl_toint; // @[core.scala:847:22] reg uop_1_fp_ctrl_fastpipe; // @[core.scala:847:22] reg uop_1_fp_ctrl_fma; // @[core.scala:847:22] reg uop_1_fp_ctrl_div; // @[core.scala:847:22] reg uop_1_fp_ctrl_sqrt; // @[core.scala:847:22] reg uop_1_fp_ctrl_wflags; // @[core.scala:847:22] reg uop_1_fp_ctrl_vec; // @[core.scala:847:22] reg [5:0] uop_1_rob_idx; // @[core.scala:847:22] reg [3:0] uop_1_ldq_idx; // @[core.scala:847:22] reg [3:0] uop_1_stq_idx; // @[core.scala:847:22] reg [1:0] uop_1_rxq_idx; // @[core.scala:847:22] reg [6:0] uop_1_pdst; // @[core.scala:847:22] reg [6:0] uop_1_prs1; // @[core.scala:847:22] reg [6:0] uop_1_prs2; // @[core.scala:847:22] reg [6:0] uop_1_prs3; // @[core.scala:847:22] reg [4:0] uop_1_ppred; // @[core.scala:847:22] reg uop_1_prs1_busy; // @[core.scala:847:22] reg uop_1_prs2_busy; // @[core.scala:847:22] reg uop_1_prs3_busy; // @[core.scala:847:22] reg uop_1_ppred_busy; // @[core.scala:847:22] reg [6:0] uop_1_stale_pdst; // @[core.scala:847:22] reg uop_1_exception; // @[core.scala:847:22] reg [63:0] uop_1_exc_cause; // @[core.scala:847:22] reg [4:0] uop_1_mem_cmd; // @[core.scala:847:22] reg [1:0] uop_1_mem_size; // @[core.scala:847:22] reg uop_1_mem_signed; // @[core.scala:847:22] reg uop_1_uses_ldq; // @[core.scala:847:22] reg uop_1_uses_stq; // @[core.scala:847:22] reg uop_1_is_unique; // @[core.scala:847:22] reg uop_1_flush_on_commit; // @[core.scala:847:22] reg [2:0] uop_1_csr_cmd; // @[core.scala:847:22] reg uop_1_ldst_is_rs1; // @[core.scala:847:22] reg [5:0] uop_1_ldst; // @[core.scala:847:22] reg [5:0] uop_1_lrs1; // @[core.scala:847:22] reg [5:0] uop_1_lrs2; // @[core.scala:847:22] reg [5:0] uop_1_lrs3; // @[core.scala:847:22] reg [1:0] uop_1_dst_rtype; // @[core.scala:847:22] reg [1:0] uop_1_lrs1_rtype; // @[core.scala:847:22] reg [1:0] uop_1_lrs2_rtype; // @[core.scala:847:22] reg uop_1_frs3_en; // @[core.scala:847:22] reg uop_1_fcn_dw; // @[core.scala:847:22] reg [4:0] uop_1_fcn_op; // @[core.scala:847:22] reg uop_1_fp_val; // @[core.scala:847:22] reg [2:0] uop_1_fp_rm; // @[core.scala:847:22] reg [1:0] uop_1_fp_typ; // @[core.scala:847:22] reg uop_1_xcpt_pf_if; // @[core.scala:847:22] reg uop_1_xcpt_ae_if; // @[core.scala:847:22] reg uop_1_xcpt_ma_if; // @[core.scala:847:22] reg uop_1_bp_debug_if; // @[core.scala:847:22] reg uop_1_bp_xcpt_if; // @[core.scala:847:22] reg [2:0] uop_1_debug_fsrc; // @[core.scala:847:22] reg [2:0] uop_1_debug_tsrc; // @[core.scala:847:22] reg immregfile_io_write_ports_1_valid_REG; // @[core.scala:849:54] wire _immregfile_io_write_ports_1_valid_T = uop_1_imm_sel == 3'h6; // @[package.scala:16:47] wire _immregfile_io_write_ports_1_valid_T_1 = uop_1_imm_sel == 3'h5; // @[package.scala:16:47] wire _immregfile_io_write_ports_1_valid_T_2 = _immregfile_io_write_ports_1_valid_T | _immregfile_io_write_ports_1_valid_T_1; // @[package.scala:16:47, :81:59] wire _immregfile_io_write_ports_1_valid_T_3 = ~_immregfile_io_write_ports_1_valid_T_2; // @[package.scala:81:59] wire _immregfile_io_write_ports_1_valid_T_4 = immregfile_io_write_ports_1_valid_REG & _immregfile_io_write_ports_1_valid_T_3; // @[core.scala:849:{54,68,71}] reg bregfile_io_write_ports_1_valid_REG; // @[core.scala:853:62] wire _bregfile_io_write_ports_1_valid_T = uop_1_br_type == 4'h1; // @[package.scala:16:47] wire _bregfile_io_write_ports_1_valid_T_1 = uop_1_br_type == 4'h2; // @[package.scala:16:47] wire _bregfile_io_write_ports_1_valid_T_2 = uop_1_br_type == 4'h3; // @[package.scala:16:47] wire _bregfile_io_write_ports_1_valid_T_3 = uop_1_br_type == 4'h4; // @[package.scala:16:47] wire _bregfile_io_write_ports_1_valid_T_4 = uop_1_br_type == 4'h5; // @[package.scala:16:47] wire _bregfile_io_write_ports_1_valid_T_5 = uop_1_br_type == 4'h6; // @[package.scala:16:47] wire _bregfile_io_write_ports_1_valid_T_6 = _bregfile_io_write_ports_1_valid_T | _bregfile_io_write_ports_1_valid_T_1; // @[package.scala:16:47, :81:59] wire _bregfile_io_write_ports_1_valid_T_7 = _bregfile_io_write_ports_1_valid_T_6 | _bregfile_io_write_ports_1_valid_T_2; // @[package.scala:16:47, :81:59] wire _bregfile_io_write_ports_1_valid_T_8 = _bregfile_io_write_ports_1_valid_T_7 | _bregfile_io_write_ports_1_valid_T_3; // @[package.scala:16:47, :81:59] wire _bregfile_io_write_ports_1_valid_T_9 = _bregfile_io_write_ports_1_valid_T_8 | _bregfile_io_write_ports_1_valid_T_4; // @[package.scala:16:47, :81:59] wire _bregfile_io_write_ports_1_valid_T_10 = _bregfile_io_write_ports_1_valid_T_9 | _bregfile_io_write_ports_1_valid_T_5; // @[package.scala:16:47, :81:59] wire _bregfile_io_write_ports_1_valid_T_11 = ~uop_1_is_sfb; // @[core.scala:847:22] wire _bregfile_io_write_ports_1_valid_T_12 = _bregfile_io_write_ports_1_valid_T_10 & _bregfile_io_write_ports_1_valid_T_11; // @[package.scala:81:59] wire _bregfile_io_write_ports_1_valid_T_13 = uop_1_br_type == 4'h8; // @[core.scala:847:22] wire _bregfile_io_write_ports_1_valid_T_14 = _bregfile_io_write_ports_1_valid_T_12 | _bregfile_io_write_ports_1_valid_T_13; // @[micro-op.scala:119:34, :160:{33,45}] wire _bregfile_io_write_ports_1_valid_T_15 = bregfile_io_write_ports_1_valid_REG & _bregfile_io_write_ports_1_valid_T_14; // @[core.scala:853:{62,76}] reg rob_io_wb_resps_0_REG; // @[core.scala:872:70] wire _rob_io_wb_resps_0_out_valid_T_4; // @[util.scala:116:31] wire [11:0] _rob_io_wb_resps_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21] wire [11:0] rob_io_wb_resps_0_out_bits_uop_br_mask; // @[util.scala:114:23] wire rob_io_wb_resps_0_out_valid; // @[util.scala:114:23] wire [11:0] _rob_io_wb_resps_0_out_bits_uop_br_mask_T = ~brupdate_b1_resolve_mask; // @[util.scala:97:23] assign _rob_io_wb_resps_0_out_bits_uop_br_mask_T_1 = io_lsu_iresp_0_bits_uop_br_mask_0 & _rob_io_wb_resps_0_out_bits_uop_br_mask_T; // @[util.scala:97:{21,23}] assign rob_io_wb_resps_0_out_bits_uop_br_mask = _rob_io_wb_resps_0_out_bits_uop_br_mask_T_1; // @[util.scala:97:21, :114:23] wire [11:0] _rob_io_wb_resps_0_out_valid_T = brupdate_b1_mispredict_mask & io_lsu_iresp_0_bits_uop_br_mask_0; // @[util.scala:126:51] wire _rob_io_wb_resps_0_out_valid_T_1 = |_rob_io_wb_resps_0_out_valid_T; // @[util.scala:126:{51,59}] wire _rob_io_wb_resps_0_out_valid_T_2 = _rob_io_wb_resps_0_out_valid_T_1 | rob_io_wb_resps_0_REG; // @[util.scala:61:61, :126:59] wire _rob_io_wb_resps_0_out_valid_T_3 = ~_rob_io_wb_resps_0_out_valid_T_2; // @[util.scala:61:61, :116:34] assign _rob_io_wb_resps_0_out_valid_T_4 = io_lsu_iresp_0_valid_0 & _rob_io_wb_resps_0_out_valid_T_3; // @[util.scala:116:{31,34}] assign rob_io_wb_resps_0_out_valid = _rob_io_wb_resps_0_out_valid_T_4; // @[util.scala:114:23, :116:31] reg rob_io_wb_resps_0_REG_1_valid; // @[core.scala:872:39] reg [31:0] rob_io_wb_resps_0_REG_1_bits_uop_inst; // @[core.scala:872:39] reg [31:0] rob_io_wb_resps_0_REG_1_bits_uop_debug_inst; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_is_rvc; // @[core.scala:872:39] reg [39:0] rob_io_wb_resps_0_REG_1_bits_uop_debug_pc; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_iq_type_0; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_iq_type_1; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_iq_type_2; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_iq_type_3; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fu_code_0; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fu_code_1; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fu_code_2; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fu_code_3; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fu_code_4; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fu_code_5; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fu_code_6; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fu_code_7; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fu_code_8; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fu_code_9; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_iw_issued; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_iw_issued_partial_agen; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_iw_issued_partial_dgen; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_iw_p1_speculative_child; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_iw_p2_speculative_child; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_iw_p1_bypass_hint; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_iw_p2_bypass_hint; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_iw_p3_bypass_hint; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_dis_col_sel; // @[core.scala:872:39] reg [11:0] rob_io_wb_resps_0_REG_1_bits_uop_br_mask; // @[core.scala:872:39] reg [3:0] rob_io_wb_resps_0_REG_1_bits_uop_br_tag; // @[core.scala:872:39] reg [3:0] rob_io_wb_resps_0_REG_1_bits_uop_br_type; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_is_sfb; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_is_fence; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_is_fencei; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_is_sfence; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_is_amo; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_is_eret; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_is_sys_pc2epc; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_is_rocc; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_is_mov; // @[core.scala:872:39] reg [4:0] rob_io_wb_resps_0_REG_1_bits_uop_ftq_idx; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_edge_inst; // @[core.scala:872:39] reg [5:0] rob_io_wb_resps_0_REG_1_bits_uop_pc_lob; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_taken; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_imm_rename; // @[core.scala:872:39] reg [2:0] rob_io_wb_resps_0_REG_1_bits_uop_imm_sel; // @[core.scala:872:39] reg [4:0] rob_io_wb_resps_0_REG_1_bits_uop_pimm; // @[core.scala:872:39] reg [19:0] rob_io_wb_resps_0_REG_1_bits_uop_imm_packed; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_op1_sel; // @[core.scala:872:39] reg [2:0] rob_io_wb_resps_0_REG_1_bits_uop_op2_sel; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_ldst; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_wen; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_ren1; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_ren2; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_ren3; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_swap12; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_swap23; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_typeTagIn; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_typeTagOut; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_fromint; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_toint; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_fastpipe; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_fma; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_div; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_sqrt; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_wflags; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_ctrl_vec; // @[core.scala:872:39] reg [5:0] rob_io_wb_resps_0_REG_1_bits_uop_rob_idx; // @[core.scala:872:39] reg [3:0] rob_io_wb_resps_0_REG_1_bits_uop_ldq_idx; // @[core.scala:872:39] reg [3:0] rob_io_wb_resps_0_REG_1_bits_uop_stq_idx; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_rxq_idx; // @[core.scala:872:39] reg [6:0] rob_io_wb_resps_0_REG_1_bits_uop_pdst; // @[core.scala:872:39] reg [6:0] rob_io_wb_resps_0_REG_1_bits_uop_prs1; // @[core.scala:872:39] reg [6:0] rob_io_wb_resps_0_REG_1_bits_uop_prs2; // @[core.scala:872:39] reg [6:0] rob_io_wb_resps_0_REG_1_bits_uop_prs3; // @[core.scala:872:39] reg [4:0] rob_io_wb_resps_0_REG_1_bits_uop_ppred; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_prs1_busy; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_prs2_busy; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_prs3_busy; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_ppred_busy; // @[core.scala:872:39] reg [6:0] rob_io_wb_resps_0_REG_1_bits_uop_stale_pdst; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_exception; // @[core.scala:872:39] reg [63:0] rob_io_wb_resps_0_REG_1_bits_uop_exc_cause; // @[core.scala:872:39] reg [4:0] rob_io_wb_resps_0_REG_1_bits_uop_mem_cmd; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_mem_size; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_mem_signed; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_uses_ldq; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_uses_stq; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_is_unique; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_flush_on_commit; // @[core.scala:872:39] reg [2:0] rob_io_wb_resps_0_REG_1_bits_uop_csr_cmd; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_ldst_is_rs1; // @[core.scala:872:39] reg [5:0] rob_io_wb_resps_0_REG_1_bits_uop_ldst; // @[core.scala:872:39] reg [5:0] rob_io_wb_resps_0_REG_1_bits_uop_lrs1; // @[core.scala:872:39] reg [5:0] rob_io_wb_resps_0_REG_1_bits_uop_lrs2; // @[core.scala:872:39] reg [5:0] rob_io_wb_resps_0_REG_1_bits_uop_lrs3; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_dst_rtype; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_lrs1_rtype; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_lrs2_rtype; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_frs3_en; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fcn_dw; // @[core.scala:872:39] reg [4:0] rob_io_wb_resps_0_REG_1_bits_uop_fcn_op; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_fp_val; // @[core.scala:872:39] reg [2:0] rob_io_wb_resps_0_REG_1_bits_uop_fp_rm; // @[core.scala:872:39] reg [1:0] rob_io_wb_resps_0_REG_1_bits_uop_fp_typ; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_xcpt_pf_if; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_xcpt_ae_if; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_xcpt_ma_if; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_bp_debug_if; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_uop_bp_xcpt_if; // @[core.scala:872:39] reg [2:0] rob_io_wb_resps_0_REG_1_bits_uop_debug_fsrc; // @[core.scala:872:39] reg [2:0] rob_io_wb_resps_0_REG_1_bits_uop_debug_tsrc; // @[core.scala:872:39] reg [63:0] rob_io_wb_resps_0_REG_1_bits_data; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_predicated; // @[core.scala:872:39] reg rob_io_wb_resps_0_REG_1_bits_fflags_valid; // @[core.scala:872:39] reg [4:0] rob_io_wb_resps_0_REG_1_bits_fflags_bits; // @[core.scala:872:39] reg iregfile_io_write_ports_0_valid_REG; // @[core.scala:873:53] reg [6:0] iregfile_io_write_ports_0_bits_addr_REG; // @[core.scala:874:57] reg [63:0] iregfile_io_write_ports_0_bits_data_REG; // @[core.scala:875:57] reg int_bypasses_0_valid_REG; // @[core.scala:877:46] assign int_bypasses_0_valid = int_bypasses_0_valid_REG; // @[core.scala:174:27, :877:46] reg [31:0] int_bypasses_0_bits_REG_uop_inst; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_inst = int_bypasses_0_bits_REG_uop_inst; // @[core.scala:174:27, :878:46] reg [31:0] int_bypasses_0_bits_REG_uop_debug_inst; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_debug_inst = int_bypasses_0_bits_REG_uop_debug_inst; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_is_rvc; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_is_rvc = int_bypasses_0_bits_REG_uop_is_rvc; // @[core.scala:174:27, :878:46] reg [39:0] int_bypasses_0_bits_REG_uop_debug_pc; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_debug_pc = int_bypasses_0_bits_REG_uop_debug_pc; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_iq_type_0; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iq_type_0 = int_bypasses_0_bits_REG_uop_iq_type_0; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_iq_type_1; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iq_type_1 = int_bypasses_0_bits_REG_uop_iq_type_1; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_iq_type_2; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iq_type_2 = int_bypasses_0_bits_REG_uop_iq_type_2; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_iq_type_3; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iq_type_3 = int_bypasses_0_bits_REG_uop_iq_type_3; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fu_code_0; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fu_code_0 = int_bypasses_0_bits_REG_uop_fu_code_0; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fu_code_1; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fu_code_1 = int_bypasses_0_bits_REG_uop_fu_code_1; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fu_code_2; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fu_code_2 = int_bypasses_0_bits_REG_uop_fu_code_2; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fu_code_3; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fu_code_3 = int_bypasses_0_bits_REG_uop_fu_code_3; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fu_code_4; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fu_code_4 = int_bypasses_0_bits_REG_uop_fu_code_4; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fu_code_5; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fu_code_5 = int_bypasses_0_bits_REG_uop_fu_code_5; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fu_code_6; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fu_code_6 = int_bypasses_0_bits_REG_uop_fu_code_6; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fu_code_7; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fu_code_7 = int_bypasses_0_bits_REG_uop_fu_code_7; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fu_code_8; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fu_code_8 = int_bypasses_0_bits_REG_uop_fu_code_8; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fu_code_9; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fu_code_9 = int_bypasses_0_bits_REG_uop_fu_code_9; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_iw_issued; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iw_issued = int_bypasses_0_bits_REG_uop_iw_issued; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_iw_issued_partial_agen; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iw_issued_partial_agen = int_bypasses_0_bits_REG_uop_iw_issued_partial_agen; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_iw_issued_partial_dgen; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iw_issued_partial_dgen = int_bypasses_0_bits_REG_uop_iw_issued_partial_dgen; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_iw_p1_speculative_child; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iw_p1_speculative_child = int_bypasses_0_bits_REG_uop_iw_p1_speculative_child; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_iw_p2_speculative_child; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iw_p2_speculative_child = int_bypasses_0_bits_REG_uop_iw_p2_speculative_child; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_iw_p1_bypass_hint; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iw_p1_bypass_hint = int_bypasses_0_bits_REG_uop_iw_p1_bypass_hint; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_iw_p2_bypass_hint; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iw_p2_bypass_hint = int_bypasses_0_bits_REG_uop_iw_p2_bypass_hint; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_iw_p3_bypass_hint; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_iw_p3_bypass_hint = int_bypasses_0_bits_REG_uop_iw_p3_bypass_hint; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_dis_col_sel; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_dis_col_sel = int_bypasses_0_bits_REG_uop_dis_col_sel; // @[core.scala:174:27, :878:46] reg [11:0] int_bypasses_0_bits_REG_uop_br_mask; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_br_mask = int_bypasses_0_bits_REG_uop_br_mask; // @[core.scala:174:27, :878:46] reg [3:0] int_bypasses_0_bits_REG_uop_br_tag; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_br_tag = int_bypasses_0_bits_REG_uop_br_tag; // @[core.scala:174:27, :878:46] reg [3:0] int_bypasses_0_bits_REG_uop_br_type; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_br_type = int_bypasses_0_bits_REG_uop_br_type; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_is_sfb; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_is_sfb = int_bypasses_0_bits_REG_uop_is_sfb; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_is_fence; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_is_fence = int_bypasses_0_bits_REG_uop_is_fence; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_is_fencei; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_is_fencei = int_bypasses_0_bits_REG_uop_is_fencei; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_is_sfence; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_is_sfence = int_bypasses_0_bits_REG_uop_is_sfence; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_is_amo; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_is_amo = int_bypasses_0_bits_REG_uop_is_amo; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_is_eret; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_is_eret = int_bypasses_0_bits_REG_uop_is_eret; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_is_sys_pc2epc; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_is_sys_pc2epc = int_bypasses_0_bits_REG_uop_is_sys_pc2epc; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_is_rocc; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_is_rocc = int_bypasses_0_bits_REG_uop_is_rocc; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_is_mov; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_is_mov = int_bypasses_0_bits_REG_uop_is_mov; // @[core.scala:174:27, :878:46] reg [4:0] int_bypasses_0_bits_REG_uop_ftq_idx; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_ftq_idx = int_bypasses_0_bits_REG_uop_ftq_idx; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_edge_inst; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_edge_inst = int_bypasses_0_bits_REG_uop_edge_inst; // @[core.scala:174:27, :878:46] reg [5:0] int_bypasses_0_bits_REG_uop_pc_lob; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_pc_lob = int_bypasses_0_bits_REG_uop_pc_lob; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_taken; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_taken = int_bypasses_0_bits_REG_uop_taken; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_imm_rename; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_imm_rename = int_bypasses_0_bits_REG_uop_imm_rename; // @[core.scala:174:27, :878:46] reg [2:0] int_bypasses_0_bits_REG_uop_imm_sel; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_imm_sel = int_bypasses_0_bits_REG_uop_imm_sel; // @[core.scala:174:27, :878:46] reg [4:0] int_bypasses_0_bits_REG_uop_pimm; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_pimm = int_bypasses_0_bits_REG_uop_pimm; // @[core.scala:174:27, :878:46] reg [19:0] int_bypasses_0_bits_REG_uop_imm_packed; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_imm_packed = int_bypasses_0_bits_REG_uop_imm_packed; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_op1_sel; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_op1_sel = int_bypasses_0_bits_REG_uop_op1_sel; // @[core.scala:174:27, :878:46] reg [2:0] int_bypasses_0_bits_REG_uop_op2_sel; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_op2_sel = int_bypasses_0_bits_REG_uop_op2_sel; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_ldst; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_ldst = int_bypasses_0_bits_REG_uop_fp_ctrl_ldst; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_wen; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_wen = int_bypasses_0_bits_REG_uop_fp_ctrl_wen; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_ren1; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_ren1 = int_bypasses_0_bits_REG_uop_fp_ctrl_ren1; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_ren2; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_ren2 = int_bypasses_0_bits_REG_uop_fp_ctrl_ren2; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_ren3; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_ren3 = int_bypasses_0_bits_REG_uop_fp_ctrl_ren3; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_swap12; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_swap12 = int_bypasses_0_bits_REG_uop_fp_ctrl_swap12; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_swap23; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_swap23 = int_bypasses_0_bits_REG_uop_fp_ctrl_swap23; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_fp_ctrl_typeTagIn; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_typeTagIn = int_bypasses_0_bits_REG_uop_fp_ctrl_typeTagIn; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_fp_ctrl_typeTagOut; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_typeTagOut = int_bypasses_0_bits_REG_uop_fp_ctrl_typeTagOut; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_fromint; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_fromint = int_bypasses_0_bits_REG_uop_fp_ctrl_fromint; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_toint; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_toint = int_bypasses_0_bits_REG_uop_fp_ctrl_toint; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_fastpipe; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_fastpipe = int_bypasses_0_bits_REG_uop_fp_ctrl_fastpipe; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_fma; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_fma = int_bypasses_0_bits_REG_uop_fp_ctrl_fma; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_div; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_div = int_bypasses_0_bits_REG_uop_fp_ctrl_div; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_sqrt; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_sqrt = int_bypasses_0_bits_REG_uop_fp_ctrl_sqrt; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_wflags; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_wflags = int_bypasses_0_bits_REG_uop_fp_ctrl_wflags; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_ctrl_vec; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_ctrl_vec = int_bypasses_0_bits_REG_uop_fp_ctrl_vec; // @[core.scala:174:27, :878:46] reg [5:0] int_bypasses_0_bits_REG_uop_rob_idx; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_rob_idx = int_bypasses_0_bits_REG_uop_rob_idx; // @[core.scala:174:27, :878:46] reg [3:0] int_bypasses_0_bits_REG_uop_ldq_idx; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_ldq_idx = int_bypasses_0_bits_REG_uop_ldq_idx; // @[core.scala:174:27, :878:46] reg [3:0] int_bypasses_0_bits_REG_uop_stq_idx; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_stq_idx = int_bypasses_0_bits_REG_uop_stq_idx; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_rxq_idx; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_rxq_idx = int_bypasses_0_bits_REG_uop_rxq_idx; // @[core.scala:174:27, :878:46] reg [6:0] int_bypasses_0_bits_REG_uop_pdst; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_pdst = int_bypasses_0_bits_REG_uop_pdst; // @[core.scala:174:27, :878:46] reg [6:0] int_bypasses_0_bits_REG_uop_prs1; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_prs1 = int_bypasses_0_bits_REG_uop_prs1; // @[core.scala:174:27, :878:46] reg [6:0] int_bypasses_0_bits_REG_uop_prs2; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_prs2 = int_bypasses_0_bits_REG_uop_prs2; // @[core.scala:174:27, :878:46] reg [6:0] int_bypasses_0_bits_REG_uop_prs3; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_prs3 = int_bypasses_0_bits_REG_uop_prs3; // @[core.scala:174:27, :878:46] reg [4:0] int_bypasses_0_bits_REG_uop_ppred; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_ppred = int_bypasses_0_bits_REG_uop_ppred; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_prs1_busy; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_prs1_busy = int_bypasses_0_bits_REG_uop_prs1_busy; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_prs2_busy; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_prs2_busy = int_bypasses_0_bits_REG_uop_prs2_busy; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_prs3_busy; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_prs3_busy = int_bypasses_0_bits_REG_uop_prs3_busy; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_ppred_busy; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_ppred_busy = int_bypasses_0_bits_REG_uop_ppred_busy; // @[core.scala:174:27, :878:46] reg [6:0] int_bypasses_0_bits_REG_uop_stale_pdst; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_stale_pdst = int_bypasses_0_bits_REG_uop_stale_pdst; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_exception; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_exception = int_bypasses_0_bits_REG_uop_exception; // @[core.scala:174:27, :878:46] reg [63:0] int_bypasses_0_bits_REG_uop_exc_cause; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_exc_cause = int_bypasses_0_bits_REG_uop_exc_cause; // @[core.scala:174:27, :878:46] reg [4:0] int_bypasses_0_bits_REG_uop_mem_cmd; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_mem_cmd = int_bypasses_0_bits_REG_uop_mem_cmd; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_mem_size; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_mem_size = int_bypasses_0_bits_REG_uop_mem_size; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_mem_signed; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_mem_signed = int_bypasses_0_bits_REG_uop_mem_signed; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_uses_ldq; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_uses_ldq = int_bypasses_0_bits_REG_uop_uses_ldq; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_uses_stq; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_uses_stq = int_bypasses_0_bits_REG_uop_uses_stq; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_is_unique; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_is_unique = int_bypasses_0_bits_REG_uop_is_unique; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_flush_on_commit; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_flush_on_commit = int_bypasses_0_bits_REG_uop_flush_on_commit; // @[core.scala:174:27, :878:46] reg [2:0] int_bypasses_0_bits_REG_uop_csr_cmd; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_csr_cmd = int_bypasses_0_bits_REG_uop_csr_cmd; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_ldst_is_rs1; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_ldst_is_rs1 = int_bypasses_0_bits_REG_uop_ldst_is_rs1; // @[core.scala:174:27, :878:46] reg [5:0] int_bypasses_0_bits_REG_uop_ldst; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_ldst = int_bypasses_0_bits_REG_uop_ldst; // @[core.scala:174:27, :878:46] reg [5:0] int_bypasses_0_bits_REG_uop_lrs1; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_lrs1 = int_bypasses_0_bits_REG_uop_lrs1; // @[core.scala:174:27, :878:46] reg [5:0] int_bypasses_0_bits_REG_uop_lrs2; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_lrs2 = int_bypasses_0_bits_REG_uop_lrs2; // @[core.scala:174:27, :878:46] reg [5:0] int_bypasses_0_bits_REG_uop_lrs3; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_lrs3 = int_bypasses_0_bits_REG_uop_lrs3; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_dst_rtype; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_dst_rtype = int_bypasses_0_bits_REG_uop_dst_rtype; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_lrs1_rtype; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_lrs1_rtype = int_bypasses_0_bits_REG_uop_lrs1_rtype; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_lrs2_rtype; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_lrs2_rtype = int_bypasses_0_bits_REG_uop_lrs2_rtype; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_frs3_en; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_frs3_en = int_bypasses_0_bits_REG_uop_frs3_en; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fcn_dw; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fcn_dw = int_bypasses_0_bits_REG_uop_fcn_dw; // @[core.scala:174:27, :878:46] reg [4:0] int_bypasses_0_bits_REG_uop_fcn_op; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fcn_op = int_bypasses_0_bits_REG_uop_fcn_op; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_fp_val; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_val = int_bypasses_0_bits_REG_uop_fp_val; // @[core.scala:174:27, :878:46] reg [2:0] int_bypasses_0_bits_REG_uop_fp_rm; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_rm = int_bypasses_0_bits_REG_uop_fp_rm; // @[core.scala:174:27, :878:46] reg [1:0] int_bypasses_0_bits_REG_uop_fp_typ; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_fp_typ = int_bypasses_0_bits_REG_uop_fp_typ; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_xcpt_pf_if; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_xcpt_pf_if = int_bypasses_0_bits_REG_uop_xcpt_pf_if; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_xcpt_ae_if; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_xcpt_ae_if = int_bypasses_0_bits_REG_uop_xcpt_ae_if; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_xcpt_ma_if; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_xcpt_ma_if = int_bypasses_0_bits_REG_uop_xcpt_ma_if; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_bp_debug_if; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_bp_debug_if = int_bypasses_0_bits_REG_uop_bp_debug_if; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_uop_bp_xcpt_if; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_bp_xcpt_if = int_bypasses_0_bits_REG_uop_bp_xcpt_if; // @[core.scala:174:27, :878:46] reg [2:0] int_bypasses_0_bits_REG_uop_debug_fsrc; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_debug_fsrc = int_bypasses_0_bits_REG_uop_debug_fsrc; // @[core.scala:174:27, :878:46] reg [2:0] int_bypasses_0_bits_REG_uop_debug_tsrc; // @[core.scala:878:46] assign int_bypasses_0_bits_uop_debug_tsrc = int_bypasses_0_bits_REG_uop_debug_tsrc; // @[core.scala:174:27, :878:46] reg [63:0] int_bypasses_0_bits_REG_data; // @[core.scala:878:46] assign int_bypasses_0_bits_data = int_bypasses_0_bits_REG_data; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_predicated; // @[core.scala:878:46] assign int_bypasses_0_bits_predicated = int_bypasses_0_bits_REG_predicated; // @[core.scala:174:27, :878:46] reg int_bypasses_0_bits_REG_fflags_valid; // @[core.scala:878:46] assign int_bypasses_0_bits_fflags_valid = int_bypasses_0_bits_REG_fflags_valid; // @[core.scala:174:27, :878:46] reg [4:0] int_bypasses_0_bits_REG_fflags_bits; // @[core.scala:878:46] assign int_bypasses_0_bits_fflags_bits = int_bypasses_0_bits_REG_fflags_bits; // @[core.scala:174:27, :878:46] wire [63:0] rdata; // @[core.scala:903:25] wire _GEN_79 = _ll_arb_io_out_bits_uop_dst_rtype == 2'h0; // @[core.scala:883:22, :937:88] wire _int_wakeups_1_valid_T; // @[core.scala:937:88] assign _int_wakeups_1_valid_T = _GEN_79; // @[core.scala:937:88] wire _iregfile_io_write_ports_1_valid_T; // @[core.scala:947:104] assign _iregfile_io_write_ports_1_valid_T = _GEN_79; // @[core.scala:937:88, :947:104] assign _int_wakeups_1_valid_T_1 = _ll_arb_io_out_valid & _int_wakeups_1_valid_T; // @[core.scala:883:22, :937:{52,88}] assign int_wakeups_1_valid = _int_wakeups_1_valid_T_1; // @[core.scala:164:26, :937:52] reg rob_io_wb_resps_1_valid_REG; // @[core.scala:944:103] wire [11:0] _rob_io_wb_resps_1_valid_T = brupdate_b1_mispredict_mask & _ll_arb_io_out_bits_uop_br_mask; // @[util.scala:126:51] wire _rob_io_wb_resps_1_valid_T_1 = |_rob_io_wb_resps_1_valid_T; // @[util.scala:126:{51,59}] wire _rob_io_wb_resps_1_valid_T_2 = _rob_io_wb_resps_1_valid_T_1 | rob_io_wb_resps_1_valid_REG; // @[util.scala:61:61, :126:59] wire _rob_io_wb_resps_1_valid_T_3 = ~_rob_io_wb_resps_1_valid_T_2; // @[util.scala:61:61] wire _rob_io_wb_resps_1_valid_T_4 = _ll_arb_io_out_valid & _rob_io_wb_resps_1_valid_T_3; // @[core.scala:883:22, :944:{65,68}] reg rob_io_wb_resps_1_valid_REG_1; // @[core.scala:944:44] reg [31:0] rob_io_wb_resps_1_bits_REG_uop_inst; // @[core.scala:945:44] reg [31:0] rob_io_wb_resps_1_bits_REG_uop_debug_inst; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_is_rvc; // @[core.scala:945:44] reg [39:0] rob_io_wb_resps_1_bits_REG_uop_debug_pc; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_iq_type_0; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_iq_type_1; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_iq_type_2; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_iq_type_3; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fu_code_0; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fu_code_1; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fu_code_2; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fu_code_3; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fu_code_4; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fu_code_5; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fu_code_6; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fu_code_7; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fu_code_8; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fu_code_9; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_iw_issued; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_iw_issued_partial_agen; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_iw_issued_partial_dgen; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_iw_p1_speculative_child; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_iw_p2_speculative_child; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_iw_p1_bypass_hint; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_iw_p2_bypass_hint; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_iw_p3_bypass_hint; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_dis_col_sel; // @[core.scala:945:44] reg [11:0] rob_io_wb_resps_1_bits_REG_uop_br_mask; // @[core.scala:945:44] reg [3:0] rob_io_wb_resps_1_bits_REG_uop_br_tag; // @[core.scala:945:44] reg [3:0] rob_io_wb_resps_1_bits_REG_uop_br_type; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_is_sfb; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_is_fence; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_is_fencei; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_is_sfence; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_is_amo; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_is_eret; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_is_sys_pc2epc; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_is_rocc; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_is_mov; // @[core.scala:945:44] reg [4:0] rob_io_wb_resps_1_bits_REG_uop_ftq_idx; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_edge_inst; // @[core.scala:945:44] reg [5:0] rob_io_wb_resps_1_bits_REG_uop_pc_lob; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_taken; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_imm_rename; // @[core.scala:945:44] reg [2:0] rob_io_wb_resps_1_bits_REG_uop_imm_sel; // @[core.scala:945:44] reg [4:0] rob_io_wb_resps_1_bits_REG_uop_pimm; // @[core.scala:945:44] reg [19:0] rob_io_wb_resps_1_bits_REG_uop_imm_packed; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_op1_sel; // @[core.scala:945:44] reg [2:0] rob_io_wb_resps_1_bits_REG_uop_op2_sel; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_ldst; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_wen; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_ren1; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_ren2; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_ren3; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_swap12; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_swap23; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_typeTagIn; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_typeTagOut; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_fromint; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_toint; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_fastpipe; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_fma; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_div; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_sqrt; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_wflags; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_ctrl_vec; // @[core.scala:945:44] reg [5:0] rob_io_wb_resps_1_bits_REG_uop_rob_idx; // @[core.scala:945:44] reg [3:0] rob_io_wb_resps_1_bits_REG_uop_ldq_idx; // @[core.scala:945:44] reg [3:0] rob_io_wb_resps_1_bits_REG_uop_stq_idx; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_rxq_idx; // @[core.scala:945:44] reg [6:0] rob_io_wb_resps_1_bits_REG_uop_pdst; // @[core.scala:945:44] reg [6:0] rob_io_wb_resps_1_bits_REG_uop_prs1; // @[core.scala:945:44] reg [6:0] rob_io_wb_resps_1_bits_REG_uop_prs2; // @[core.scala:945:44] reg [6:0] rob_io_wb_resps_1_bits_REG_uop_prs3; // @[core.scala:945:44] reg [4:0] rob_io_wb_resps_1_bits_REG_uop_ppred; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_prs1_busy; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_prs2_busy; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_prs3_busy; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_ppred_busy; // @[core.scala:945:44] reg [6:0] rob_io_wb_resps_1_bits_REG_uop_stale_pdst; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_exception; // @[core.scala:945:44] reg [63:0] rob_io_wb_resps_1_bits_REG_uop_exc_cause; // @[core.scala:945:44] reg [4:0] rob_io_wb_resps_1_bits_REG_uop_mem_cmd; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_mem_size; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_mem_signed; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_uses_ldq; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_uses_stq; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_is_unique; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_flush_on_commit; // @[core.scala:945:44] reg [2:0] rob_io_wb_resps_1_bits_REG_uop_csr_cmd; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_ldst_is_rs1; // @[core.scala:945:44] reg [5:0] rob_io_wb_resps_1_bits_REG_uop_ldst; // @[core.scala:945:44] reg [5:0] rob_io_wb_resps_1_bits_REG_uop_lrs1; // @[core.scala:945:44] reg [5:0] rob_io_wb_resps_1_bits_REG_uop_lrs2; // @[core.scala:945:44] reg [5:0] rob_io_wb_resps_1_bits_REG_uop_lrs3; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_dst_rtype; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_lrs1_rtype; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_lrs2_rtype; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_frs3_en; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fcn_dw; // @[core.scala:945:44] reg [4:0] rob_io_wb_resps_1_bits_REG_uop_fcn_op; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_fp_val; // @[core.scala:945:44] reg [2:0] rob_io_wb_resps_1_bits_REG_uop_fp_rm; // @[core.scala:945:44] reg [1:0] rob_io_wb_resps_1_bits_REG_uop_fp_typ; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_xcpt_pf_if; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_xcpt_ae_if; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_xcpt_ma_if; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_bp_debug_if; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_uop_bp_xcpt_if; // @[core.scala:945:44] reg [2:0] rob_io_wb_resps_1_bits_REG_uop_debug_fsrc; // @[core.scala:945:44] reg [2:0] rob_io_wb_resps_1_bits_REG_uop_debug_tsrc; // @[core.scala:945:44] reg [63:0] rob_io_wb_resps_1_bits_REG_data; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_predicated; // @[core.scala:945:44] reg rob_io_wb_resps_1_bits_REG_fflags_valid; // @[core.scala:945:44] reg [4:0] rob_io_wb_resps_1_bits_REG_fflags_bits; // @[core.scala:945:44] wire _iregfile_io_write_ports_1_valid_T_1 = _ll_arb_io_out_valid & _iregfile_io_write_ports_1_valid_T; // @[core.scala:883:22, :947:{68,104}] wire _GEN_80 = _alu_exe_unit_0_io_alu_resp_bits_uop_dst_rtype == 2'h0; // @[core.scala:92:11, :958:101] wire _int_bypasses_1_valid_T; // @[core.scala:958:101] assign _int_bypasses_1_valid_T = _GEN_80; // @[core.scala:958:101] wire _iregfile_io_write_ports_2_valid_T; // @[core.scala:968:112] assign _iregfile_io_write_ports_2_valid_T = _GEN_80; // @[core.scala:958:101, :968:112] assign _int_bypasses_1_valid_T_1 = _alu_exe_unit_0_io_alu_resp_valid & _int_bypasses_1_valid_T; // @[core.scala:92:11, :958:{62,101}] assign int_bypasses_1_valid = _int_bypasses_1_valid_T_1; // @[core.scala:174:27, :958:62] reg rob_io_wb_resps_2_valid_REG; // @[core.scala:965:108] wire [11:0] _rob_io_wb_resps_2_valid_T = brupdate_b1_mispredict_mask & _alu_exe_unit_0_io_alu_resp_bits_uop_br_mask; // @[util.scala:126:51] wire _rob_io_wb_resps_2_valid_T_1 = |_rob_io_wb_resps_2_valid_T; // @[util.scala:126:{51,59}] wire _rob_io_wb_resps_2_valid_T_2 = _rob_io_wb_resps_2_valid_T_1 | rob_io_wb_resps_2_valid_REG; // @[util.scala:61:61, :126:59] wire _rob_io_wb_resps_2_valid_T_3 = ~_rob_io_wb_resps_2_valid_T_2; // @[util.scala:61:61] wire _rob_io_wb_resps_2_valid_T_4 = _alu_exe_unit_0_io_alu_resp_valid & _rob_io_wb_resps_2_valid_T_3; // @[core.scala:92:11, :965:{70,73}] reg rob_io_wb_resps_2_valid_REG_1; // @[core.scala:965:46] reg [31:0] rob_io_wb_resps_2_bits_REG_uop_inst; // @[core.scala:966:46] reg [31:0] rob_io_wb_resps_2_bits_REG_uop_debug_inst; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_is_rvc; // @[core.scala:966:46] reg [39:0] rob_io_wb_resps_2_bits_REG_uop_debug_pc; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_iq_type_0; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_iq_type_1; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_iq_type_2; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_iq_type_3; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fu_code_0; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fu_code_1; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fu_code_2; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fu_code_3; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fu_code_4; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fu_code_5; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fu_code_6; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fu_code_7; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fu_code_8; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fu_code_9; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_iw_issued; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_iw_issued_partial_agen; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_iw_issued_partial_dgen; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_iw_p1_speculative_child; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_iw_p2_speculative_child; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_iw_p1_bypass_hint; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_iw_p2_bypass_hint; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_iw_p3_bypass_hint; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_dis_col_sel; // @[core.scala:966:46] reg [11:0] rob_io_wb_resps_2_bits_REG_uop_br_mask; // @[core.scala:966:46] reg [3:0] rob_io_wb_resps_2_bits_REG_uop_br_tag; // @[core.scala:966:46] reg [3:0] rob_io_wb_resps_2_bits_REG_uop_br_type; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_is_sfb; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_is_fence; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_is_fencei; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_is_sfence; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_is_amo; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_is_eret; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_is_sys_pc2epc; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_is_rocc; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_is_mov; // @[core.scala:966:46] reg [4:0] rob_io_wb_resps_2_bits_REG_uop_ftq_idx; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_edge_inst; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_2_bits_REG_uop_pc_lob; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_taken; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_imm_rename; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_2_bits_REG_uop_imm_sel; // @[core.scala:966:46] reg [4:0] rob_io_wb_resps_2_bits_REG_uop_pimm; // @[core.scala:966:46] reg [19:0] rob_io_wb_resps_2_bits_REG_uop_imm_packed; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_op1_sel; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_2_bits_REG_uop_op2_sel; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_ldst; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_wen; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_ren1; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_ren2; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_ren3; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_swap12; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_swap23; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_typeTagIn; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_typeTagOut; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_fromint; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_toint; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_fastpipe; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_fma; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_div; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_sqrt; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_wflags; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_ctrl_vec; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_2_bits_REG_uop_rob_idx; // @[core.scala:966:46] reg [3:0] rob_io_wb_resps_2_bits_REG_uop_ldq_idx; // @[core.scala:966:46] reg [3:0] rob_io_wb_resps_2_bits_REG_uop_stq_idx; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_rxq_idx; // @[core.scala:966:46] reg [6:0] rob_io_wb_resps_2_bits_REG_uop_pdst; // @[core.scala:966:46] reg [6:0] rob_io_wb_resps_2_bits_REG_uop_prs1; // @[core.scala:966:46] reg [6:0] rob_io_wb_resps_2_bits_REG_uop_prs2; // @[core.scala:966:46] reg [6:0] rob_io_wb_resps_2_bits_REG_uop_prs3; // @[core.scala:966:46] reg [4:0] rob_io_wb_resps_2_bits_REG_uop_ppred; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_prs1_busy; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_prs2_busy; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_prs3_busy; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_ppred_busy; // @[core.scala:966:46] reg [6:0] rob_io_wb_resps_2_bits_REG_uop_stale_pdst; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_exception; // @[core.scala:966:46] reg [63:0] rob_io_wb_resps_2_bits_REG_uop_exc_cause; // @[core.scala:966:46] reg [4:0] rob_io_wb_resps_2_bits_REG_uop_mem_cmd; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_mem_size; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_mem_signed; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_uses_ldq; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_uses_stq; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_is_unique; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_flush_on_commit; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_2_bits_REG_uop_csr_cmd; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_ldst_is_rs1; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_2_bits_REG_uop_ldst; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_2_bits_REG_uop_lrs1; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_2_bits_REG_uop_lrs2; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_2_bits_REG_uop_lrs3; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_dst_rtype; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_lrs1_rtype; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_lrs2_rtype; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_frs3_en; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fcn_dw; // @[core.scala:966:46] reg [4:0] rob_io_wb_resps_2_bits_REG_uop_fcn_op; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_fp_val; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_2_bits_REG_uop_fp_rm; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_2_bits_REG_uop_fp_typ; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_xcpt_pf_if; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_xcpt_ae_if; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_xcpt_ma_if; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_bp_debug_if; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_uop_bp_xcpt_if; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_2_bits_REG_uop_debug_fsrc; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_2_bits_REG_uop_debug_tsrc; // @[core.scala:966:46] reg [63:0] rob_io_wb_resps_2_bits_REG_data; // @[core.scala:966:46] reg rob_io_wb_resps_2_bits_REG_predicated; // @[core.scala:966:46] wire _iregfile_io_write_ports_2_valid_T_1 = _alu_exe_unit_0_io_alu_resp_valid & _iregfile_io_write_ports_2_valid_T; // @[core.scala:92:11, :968:{73,112}] wire _GEN_81 = _alu_exe_unit_1_io_alu_resp_bits_uop_dst_rtype == 2'h0; // @[core.scala:92:11, :958:101] wire _int_bypasses_2_valid_T; // @[core.scala:958:101] assign _int_bypasses_2_valid_T = _GEN_81; // @[core.scala:958:101] wire _iregfile_io_write_ports_3_valid_T; // @[core.scala:968:112] assign _iregfile_io_write_ports_3_valid_T = _GEN_81; // @[core.scala:958:101, :968:112] assign _int_bypasses_2_valid_T_1 = _alu_exe_unit_1_io_alu_resp_valid & _int_bypasses_2_valid_T; // @[core.scala:92:11, :958:{62,101}] assign int_bypasses_2_valid = _int_bypasses_2_valid_T_1; // @[core.scala:174:27, :958:62] reg rob_io_wb_resps_3_valid_REG; // @[core.scala:965:108] wire [11:0] _rob_io_wb_resps_3_valid_T = brupdate_b1_mispredict_mask & _alu_exe_unit_1_io_alu_resp_bits_uop_br_mask; // @[util.scala:126:51] wire _rob_io_wb_resps_3_valid_T_1 = |_rob_io_wb_resps_3_valid_T; // @[util.scala:126:{51,59}] wire _rob_io_wb_resps_3_valid_T_2 = _rob_io_wb_resps_3_valid_T_1 | rob_io_wb_resps_3_valid_REG; // @[util.scala:61:61, :126:59] wire _rob_io_wb_resps_3_valid_T_3 = ~_rob_io_wb_resps_3_valid_T_2; // @[util.scala:61:61] wire _rob_io_wb_resps_3_valid_T_4 = _alu_exe_unit_1_io_alu_resp_valid & _rob_io_wb_resps_3_valid_T_3; // @[core.scala:92:11, :965:{70,73}] reg rob_io_wb_resps_3_valid_REG_1; // @[core.scala:965:46] reg [31:0] rob_io_wb_resps_3_bits_REG_uop_inst; // @[core.scala:966:46] reg [31:0] rob_io_wb_resps_3_bits_REG_uop_debug_inst; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_is_rvc; // @[core.scala:966:46] reg [39:0] rob_io_wb_resps_3_bits_REG_uop_debug_pc; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_iq_type_0; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_iq_type_1; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_iq_type_2; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_iq_type_3; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fu_code_0; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fu_code_1; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fu_code_2; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fu_code_3; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fu_code_4; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fu_code_5; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fu_code_6; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fu_code_7; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fu_code_8; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fu_code_9; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_iw_issued; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_iw_issued_partial_agen; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_iw_issued_partial_dgen; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_iw_p1_speculative_child; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_iw_p2_speculative_child; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_iw_p1_bypass_hint; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_iw_p2_bypass_hint; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_iw_p3_bypass_hint; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_dis_col_sel; // @[core.scala:966:46] reg [11:0] rob_io_wb_resps_3_bits_REG_uop_br_mask; // @[core.scala:966:46] reg [3:0] rob_io_wb_resps_3_bits_REG_uop_br_tag; // @[core.scala:966:46] reg [3:0] rob_io_wb_resps_3_bits_REG_uop_br_type; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_is_sfb; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_is_fence; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_is_fencei; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_is_sfence; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_is_amo; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_is_eret; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_is_sys_pc2epc; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_is_rocc; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_is_mov; // @[core.scala:966:46] reg [4:0] rob_io_wb_resps_3_bits_REG_uop_ftq_idx; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_edge_inst; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_3_bits_REG_uop_pc_lob; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_taken; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_imm_rename; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_3_bits_REG_uop_imm_sel; // @[core.scala:966:46] reg [4:0] rob_io_wb_resps_3_bits_REG_uop_pimm; // @[core.scala:966:46] reg [19:0] rob_io_wb_resps_3_bits_REG_uop_imm_packed; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_op1_sel; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_3_bits_REG_uop_op2_sel; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_ldst; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_wen; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_ren1; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_ren2; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_ren3; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_swap12; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_swap23; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_typeTagIn; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_typeTagOut; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_fromint; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_toint; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_fastpipe; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_fma; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_div; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_sqrt; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_wflags; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_ctrl_vec; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_3_bits_REG_uop_rob_idx; // @[core.scala:966:46] reg [3:0] rob_io_wb_resps_3_bits_REG_uop_ldq_idx; // @[core.scala:966:46] reg [3:0] rob_io_wb_resps_3_bits_REG_uop_stq_idx; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_rxq_idx; // @[core.scala:966:46] reg [6:0] rob_io_wb_resps_3_bits_REG_uop_pdst; // @[core.scala:966:46] reg [6:0] rob_io_wb_resps_3_bits_REG_uop_prs1; // @[core.scala:966:46] reg [6:0] rob_io_wb_resps_3_bits_REG_uop_prs2; // @[core.scala:966:46] reg [6:0] rob_io_wb_resps_3_bits_REG_uop_prs3; // @[core.scala:966:46] reg [4:0] rob_io_wb_resps_3_bits_REG_uop_ppred; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_prs1_busy; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_prs2_busy; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_prs3_busy; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_ppred_busy; // @[core.scala:966:46] reg [6:0] rob_io_wb_resps_3_bits_REG_uop_stale_pdst; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_exception; // @[core.scala:966:46] reg [63:0] rob_io_wb_resps_3_bits_REG_uop_exc_cause; // @[core.scala:966:46] reg [4:0] rob_io_wb_resps_3_bits_REG_uop_mem_cmd; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_mem_size; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_mem_signed; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_uses_ldq; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_uses_stq; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_is_unique; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_flush_on_commit; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_3_bits_REG_uop_csr_cmd; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_ldst_is_rs1; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_3_bits_REG_uop_ldst; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_3_bits_REG_uop_lrs1; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_3_bits_REG_uop_lrs2; // @[core.scala:966:46] reg [5:0] rob_io_wb_resps_3_bits_REG_uop_lrs3; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_dst_rtype; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_lrs1_rtype; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_lrs2_rtype; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_frs3_en; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fcn_dw; // @[core.scala:966:46] reg [4:0] rob_io_wb_resps_3_bits_REG_uop_fcn_op; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_fp_val; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_3_bits_REG_uop_fp_rm; // @[core.scala:966:46] reg [1:0] rob_io_wb_resps_3_bits_REG_uop_fp_typ; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_xcpt_pf_if; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_xcpt_ae_if; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_xcpt_ma_if; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_bp_debug_if; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_uop_bp_xcpt_if; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_3_bits_REG_uop_debug_fsrc; // @[core.scala:966:46] reg [2:0] rob_io_wb_resps_3_bits_REG_uop_debug_tsrc; // @[core.scala:966:46] reg [63:0] rob_io_wb_resps_3_bits_REG_data; // @[core.scala:966:46] reg rob_io_wb_resps_3_bits_REG_predicated; // @[core.scala:966:46] wire _iregfile_io_write_ports_3_valid_T_1 = _alu_exe_unit_1_io_alu_resp_valid & _iregfile_io_write_ports_3_valid_T; // @[core.scala:92:11, :968:{73,112}] wire _pregfile_write_valids_T = |_alu_exe_unit_0_io_alu_resp_bits_uop_br_type; // @[core.scala:92:11] wire _pregfile_write_valids_T_1 = _pregfile_write_valids_T & _alu_exe_unit_0_io_alu_resp_bits_uop_is_sfb; // @[core.scala:92:11] wire _pregfile_write_valids_T_2 = _pregfile_write_valids_T_1; // @[micro-op.scala:120:{42,52}] wire pregfile_write_valids_0 = _alu_exe_unit_0_io_alu_resp_valid & _pregfile_write_valids_T_2; // @[core.scala:92:11, :981:74] wire _pregfile_write_valids_T_3 = |_alu_exe_unit_1_io_alu_resp_bits_uop_br_type; // @[core.scala:92:11] wire _pregfile_write_valids_T_4 = _pregfile_write_valids_T_3 & _alu_exe_unit_1_io_alu_resp_bits_uop_is_sfb; // @[core.scala:92:11] wire _pregfile_write_valids_T_5 = _pregfile_write_valids_T_4; // @[micro-op.scala:120:{42,52}] wire pregfile_write_valids_1 = _alu_exe_unit_1_io_alu_resp_valid & _pregfile_write_valids_T_5; // @[core.scala:92:11, :981:74] wire _pregfile_io_write_ports_0_valid_T = pregfile_write_valids_0 | pregfile_write_valids_1; // @[core.scala:981:74, :983:69] wire [6:0] _pregfile_io_write_ports_0_bits_addr_T = pregfile_write_valids_0 ? _alu_exe_unit_0_io_alu_resp_bits_uop_pdst : 7'h0; // @[Mux.scala:30:73] wire [6:0] _pregfile_io_write_ports_0_bits_addr_T_1 = pregfile_write_valids_1 ? _alu_exe_unit_1_io_alu_resp_bits_uop_pdst : 7'h0; // @[Mux.scala:30:73] wire [6:0] _pregfile_io_write_ports_0_bits_addr_T_2 = _pregfile_io_write_ports_0_bits_addr_T | _pregfile_io_write_ports_0_bits_addr_T_1; // @[Mux.scala:30:73] wire [6:0] _pregfile_io_write_ports_0_bits_addr_WIRE = _pregfile_io_write_ports_0_bits_addr_T_2; // @[Mux.scala:30:73] wire [63:0] _pregfile_io_write_ports_0_bits_data_T = pregfile_write_valids_0 ? _alu_exe_unit_0_io_alu_resp_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _pregfile_io_write_ports_0_bits_data_T_1 = pregfile_write_valids_1 ? _alu_exe_unit_1_io_alu_resp_bits_data : 64'h0; // @[Mux.scala:30:73] wire [63:0] _pregfile_io_write_ports_0_bits_data_T_2 = _pregfile_io_write_ports_0_bits_data_T | _pregfile_io_write_ports_0_bits_data_T_1; // @[Mux.scala:30:73] wire [63:0] _pregfile_io_write_ports_0_bits_data_WIRE = _pregfile_io_write_ports_0_bits_data_T_2; // @[Mux.scala:30:73] wire [1:0] _GEN_82 = _alu_exe_unit_0_io_child_rebusy | _alu_exe_unit_1_io_child_rebusy; // @[core.scala:92:11, :1010:81] wire [1:0] _rename_stage_io_child_rebusys_T; // @[core.scala:1010:81] assign _rename_stage_io_child_rebusys_T = _GEN_82; // @[core.scala:1010:81] wire [1:0] _mem_iss_unit_io_child_rebusys_T; // @[core.scala:1025:79] assign _mem_iss_unit_io_child_rebusys_T = _GEN_82; // @[core.scala:1010:81, :1025:79] wire [1:0] _alu_iss_unit_io_child_rebusys_T; // @[core.scala:1025:79] assign _alu_iss_unit_io_child_rebusys_T = _GEN_82; // @[core.scala:1010:81, :1025:79] wire [1:0] _unq_iss_unit_io_child_rebusys_T; // @[core.scala:1025:79] assign _unq_iss_unit_io_child_rebusys_T = _GEN_82; // @[core.scala:1010:81, :1025:79] reg mem_iss_unit_io_flush_pipeline_REG; // @[core.scala:1022:42] reg alu_iss_unit_io_flush_pipeline_REG; // @[core.scala:1022:42] reg unq_iss_unit_io_flush_pipeline_REG; // @[core.scala:1022:42] wire _mem_iss_unit_io_squash_grant_T = _mem_exe_unit_0_io_squash_iss | _mem_exe_unit_1_io_squash_iss; // @[core.scala:74:11, :1031:48] wire _GEN_83 = _alu_exe_unit_0_io_squash_iss | _alu_exe_unit_1_io_squash_iss; // @[core.scala:92:11, :1032:48] wire _mem_iss_unit_io_squash_grant_T_1; // @[core.scala:1032:48] assign _mem_iss_unit_io_squash_grant_T_1 = _GEN_83; // @[core.scala:1032:48] wire _unq_iss_unit_io_squash_grant_T; // @[core.scala:1037:48] assign _unq_iss_unit_io_squash_grant_T = _GEN_83; // @[core.scala:1032:48, :1037:48] wire _alu_iss_unit_io_squash_grant_T; // @[core.scala:1041:48] assign _alu_iss_unit_io_squash_grant_T = _GEN_83; // @[core.scala:1032:48, :1041:48] wire _mem_iss_unit_io_squash_grant_T_2 = _mem_iss_unit_io_squash_grant_T | _mem_iss_unit_io_squash_grant_T_1; // @[core.scala:1031:{48,53}, :1032:48] wire _mem_iss_unit_io_squash_grant_T_3 = _mem_iss_unit_io_squash_grant_T_2 | io_lsu_iwakeups_0_bits_rebusy_0; // @[core.scala:50:7, :1031:53, :1032:53] wire _unq_iss_unit_io_squash_grant_T_1 = _unique_exe_unit_0_io_squash_iss | _unq_iss_unit_io_squash_grant_T; // @[core.scala:81:11, :1036:53, :1037:48] wire _unq_iss_unit_io_squash_grant_T_2 = _unq_iss_unit_io_squash_grant_T_1 | io_lsu_iwakeups_0_bits_rebusy_0; // @[core.scala:50:7, :1036:53, :1037:53] wire _alu_iss_unit_io_squash_grant_T_1 = _alu_iss_unit_io_squash_grant_T | io_lsu_iwakeups_0_bits_rebusy_0; // @[core.scala:50:7, :1041:{48,53}] wire [2:0] _csr_io_rw_cmd_T = {~_unique_exe_unit_0_io_csr_resp_valid, 2'h0}; // @[CSR.scala:183:15] wire [2:0] _csr_io_rw_cmd_T_1 = ~_csr_io_rw_cmd_T; // @[CSR.scala:183:{11,15}] wire [2:0] _csr_io_rw_cmd_T_2 = _unique_exe_unit_0_io_csr_resp_bits_uop_csr_cmd & _csr_io_rw_cmd_T_1; // @[CSR.scala:183:{9,11}] wire _csr_io_retire_T_1 = _csr_io_retire_T[0]; // @[core.scala:1113:{39,66}] wire _csr_io_retire_T_2 = _csr_io_retire_T[1]; // @[core.scala:1113:{39,66}] wire [1:0] _csr_io_retire_T_3 = {1'h0, _csr_io_retire_T_1} + {1'h0, _csr_io_retire_T_2}; // @[core.scala:1113:39] wire [1:0] _csr_io_retire_T_4 = _csr_io_retire_T_3; // @[core.scala:1113:39] reg [1:0] csr_io_retire_REG; // @[core.scala:1113:30] reg csr_io_exception_REG; // @[core.scala:1114:30] wire [39:0] _csr_io_pc_T = ~io_ifu_com_pc_0; // @[util.scala:245:7] wire [39:0] _csr_io_pc_T_1 = {_csr_io_pc_T[39:6], 6'h3F}; // @[util.scala:245:{7,11}] wire [39:0] _csr_io_pc_T_2 = ~_csr_io_pc_T_1; // @[util.scala:245:{5,11}] reg [5:0] csr_io_pc_REG; // @[core.scala:1118:31] wire [40:0] _csr_io_pc_T_3 = {1'h0, _csr_io_pc_T_2} + {35'h0, csr_io_pc_REG}; // @[util.scala:245:5] wire [39:0] _csr_io_pc_T_4 = _csr_io_pc_T_3[39:0]; // @[core.scala:1118:22] reg csr_io_pc_REG_1; // @[core.scala:1119:35] wire [1:0] _csr_io_pc_T_5 = {csr_io_pc_REG_1, 1'h0}; // @[core.scala:1119:{27,35}] wire [40:0] _csr_io_pc_T_6 = {1'h0, _csr_io_pc_T_4} - {39'h0, _csr_io_pc_T_5}; // @[core.scala:1118:22, :1119:{22,27}] wire [39:0] _csr_io_pc_T_7 = _csr_io_pc_T_6[39:0]; // @[core.scala:1119:22] reg [63:0] csr_io_cause_REG; // @[core.scala:1121:30] wire _tval_valid_T = csr_io_cause_REG == 64'h3; // @[package.scala:16:47] wire _tval_valid_T_1 = csr_io_cause_REG == 64'h4; // @[package.scala:16:47] wire _tval_valid_T_2 = csr_io_cause_REG == 64'h6; // @[package.scala:16:47] wire _tval_valid_T_3 = csr_io_cause_REG == 64'h5; // @[package.scala:16:47] wire _tval_valid_T_4 = csr_io_cause_REG == 64'h7; // @[package.scala:16:47] wire _tval_valid_T_5 = csr_io_cause_REG == 64'h1; // @[package.scala:16:47] wire _tval_valid_T_6 = csr_io_cause_REG == 64'hD; // @[package.scala:16:47] wire _tval_valid_T_7 = csr_io_cause_REG == 64'hF; // @[package.scala:16:47] wire _tval_valid_T_8 = csr_io_cause_REG == 64'hC; // @[package.scala:16:47] wire _tval_valid_T_9 = _tval_valid_T | _tval_valid_T_1; // @[package.scala:16:47, :81:59] wire _tval_valid_T_10 = _tval_valid_T_9 | _tval_valid_T_2; // @[package.scala:16:47, :81:59] wire _tval_valid_T_11 = _tval_valid_T_10 | _tval_valid_T_3; // @[package.scala:16:47, :81:59] wire _tval_valid_T_12 = _tval_valid_T_11 | _tval_valid_T_4; // @[package.scala:16:47, :81:59] wire _tval_valid_T_13 = _tval_valid_T_12 | _tval_valid_T_5; // @[package.scala:16:47, :81:59] wire _tval_valid_T_14 = _tval_valid_T_13 | _tval_valid_T_6; // @[package.scala:16:47, :81:59] wire _tval_valid_T_15 = _tval_valid_T_14 | _tval_valid_T_7; // @[package.scala:16:47, :81:59] wire _tval_valid_T_16 = _tval_valid_T_15 | _tval_valid_T_8; // @[package.scala:16:47, :81:59] wire tval_valid = csr_io_exception_REG & _tval_valid_T_16; // @[package.scala:81:59] wire [63:0] _csr_io_tval_a_T; // @[core.scala:1147:18] wire [24:0] csr_io_tval_a = _csr_io_tval_a_T[63:39]; // @[core.scala:1147:{18,25}] wire _csr_io_tval_msb_T = csr_io_tval_a == 25'h0; // @[core.scala:1147:25, :1148:23] wire _csr_io_tval_msb_T_1 = &csr_io_tval_a; // @[core.scala:1147:25, :1148:36] wire _csr_io_tval_msb_T_2 = _csr_io_tval_msb_T | _csr_io_tval_msb_T_1; // @[core.scala:1148:{23,31,36}] wire _csr_io_tval_msb_T_3 = _rob_io_com_xcpt_bits_badvaddr[39]; // @[core.scala:159:32, :1148:48] wire _csr_io_tval_msb_T_4 = _rob_io_com_xcpt_bits_badvaddr[38]; // @[core.scala:159:32, :1148:64] wire _csr_io_tval_msb_T_5 = ~_csr_io_tval_msb_T_4; // @[core.scala:1148:{61,64}] wire csr_io_tval_msb = _csr_io_tval_msb_T_2 ? _csr_io_tval_msb_T_3 : _csr_io_tval_msb_T_5; // @[core.scala:1148:{20,31,48,61}] wire [38:0] _csr_io_tval_T = _rob_io_com_xcpt_bits_badvaddr[38:0]; // @[core.scala:159:32, :1149:18] wire [39:0] _csr_io_tval_T_1 = {csr_io_tval_msb, _csr_io_tval_T}; // @[core.scala:1148:20, :1149:{10,18}] reg [39:0] csr_io_tval_REG; // @[core.scala:1138:12] wire [39:0] _csr_io_tval_T_2 = tval_valid ? csr_io_tval_REG : 40'h0; // @[core.scala:1124:37, :1137:21, :1138:12] reg io_lsu_exception_REG; // @[core.scala:1195:30] assign io_lsu_exception_0 = io_lsu_exception_REG; // @[core.scala:50:7, :1195:30] wire [11:0] rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp = _fp_pipeline_io_wb_0_bits_data[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isZero_T = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isZero = _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isZero_0 = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isSpecial_T = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isSpecial = &_rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isNaN_T = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isNaN_T_1 = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isSpecial & _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isNaN = _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T_1 = ~_rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T_2 = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isSpecial & _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isInf = _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sign_T = _fp_pipeline_io_wb_0_bits_data[64]; // @[rawFloatFromRecFN.scala:59:25] assign rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sign = _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sExp_T = {1'h0, rob_io_wb_resps_4_bits_data_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sExp = _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T = ~rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_1 = {1'h0, _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_2 = _fp_pipeline_io_wb_0_bits_data[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_3 = {_rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_1, _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sig = _rob_io_wb_resps_4_bits_data_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire rob_io_wb_resps_4_bits_data_unrecoded_isSubnormal = $signed(rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist_T = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist = _rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _rob_io_wb_resps_4_bits_data_unrecoded_denormFract_T = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _rob_io_wb_resps_4_bits_data_unrecoded_denormFract_T_1 = _rob_io_wb_resps_4_bits_data_unrecoded_denormFract_T >> rob_io_wb_resps_4_bits_data_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] rob_io_wb_resps_4_bits_data_unrecoded_denormFract = _rob_io_wb_resps_4_bits_data_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_1 = {1'h0, _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_2 = _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_3 = rob_io_wb_resps_4_bits_data_unrecoded_isSubnormal ? 11'h0 : _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_4 = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isNaN | rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_5 = {11{_rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] rob_io_wb_resps_4_bits_data_unrecoded_expOut = _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_3 | _rob_io_wb_resps_4_bits_data_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _rob_io_wb_resps_4_bits_data_unrecoded_fractOut_T = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _rob_io_wb_resps_4_bits_data_unrecoded_fractOut_T_1 = rob_io_wb_resps_4_bits_data_unrecoded_rawIn_isInf ? 52'h0 : _rob_io_wb_resps_4_bits_data_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] rob_io_wb_resps_4_bits_data_unrecoded_fractOut = rob_io_wb_resps_4_bits_data_unrecoded_isSubnormal ? rob_io_wb_resps_4_bits_data_unrecoded_denormFract : _rob_io_wb_resps_4_bits_data_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] rob_io_wb_resps_4_bits_data_unrecoded_hi = {rob_io_wb_resps_4_bits_data_unrecoded_rawIn_sign, rob_io_wb_resps_4_bits_data_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] rob_io_wb_resps_4_bits_data_unrecoded = {rob_io_wb_resps_4_bits_data_unrecoded_hi, rob_io_wb_resps_4_bits_data_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _rob_io_wb_resps_4_bits_data_prevRecoded_T = _fp_pipeline_io_wb_0_bits_data[31]; // @[FPU.scala:442:10] wire _rob_io_wb_resps_4_bits_data_prevRecoded_T_1 = _fp_pipeline_io_wb_0_bits_data[52]; // @[FPU.scala:443:10] wire [30:0] _rob_io_wb_resps_4_bits_data_prevRecoded_T_2 = _fp_pipeline_io_wb_0_bits_data[30:0]; // @[FPU.scala:444:10] wire [1:0] rob_io_wb_resps_4_bits_data_prevRecoded_hi = {_rob_io_wb_resps_4_bits_data_prevRecoded_T, _rob_io_wb_resps_4_bits_data_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] rob_io_wb_resps_4_bits_data_prevRecoded = {rob_io_wb_resps_4_bits_data_prevRecoded_hi, _rob_io_wb_resps_4_bits_data_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp = rob_io_wb_resps_4_bits_data_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isZero_T = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isZero = _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isZero_0 = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isSpecial_T = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isSpecial = &_rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isNaN_T = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1 = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isSpecial & _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isNaN = _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T_1 = ~_rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T_2 = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isSpecial & _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isInf = _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sign_T = rob_io_wb_resps_4_bits_data_prevRecoded[32]; // @[FPU.scala:441:28] assign rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sign = _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sExp_T = {1'h0, rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sExp = _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T = ~rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_2 = rob_io_wb_resps_4_bits_data_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_3 = {_rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_1, _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sig = _rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire rob_io_wb_resps_4_bits_data_prevUnrecoded_isSubnormal = $signed(rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist_T = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist = _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract_T = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract_T_1 = _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract_T >> rob_io_wb_resps_4_bits_data_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract = _rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_1 = {1'h0, _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_2 = _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_3 = rob_io_wb_resps_4_bits_data_prevUnrecoded_isSubnormal ? 8'h0 : _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_4 = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isNaN | rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_5 = {8{_rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut = _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_3 | _rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut_T = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut_T_1 = rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_isInf ? 23'h0 : _rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut = rob_io_wb_resps_4_bits_data_prevUnrecoded_isSubnormal ? rob_io_wb_resps_4_bits_data_prevUnrecoded_denormFract : _rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] rob_io_wb_resps_4_bits_data_prevUnrecoded_hi = {rob_io_wb_resps_4_bits_data_prevUnrecoded_rawIn_sign, rob_io_wb_resps_4_bits_data_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] rob_io_wb_resps_4_bits_data_prevUnrecoded = {rob_io_wb_resps_4_bits_data_prevUnrecoded_hi, rob_io_wb_resps_4_bits_data_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [31:0] _rob_io_wb_resps_4_bits_data_T = rob_io_wb_resps_4_bits_data_unrecoded[63:32]; // @[FPU.scala:446:21] wire [2:0] _rob_io_wb_resps_4_bits_data_T_1 = _fp_pipeline_io_wb_0_bits_data[63:61]; // @[FPU.scala:249:25] wire _rob_io_wb_resps_4_bits_data_T_2 = &_rob_io_wb_resps_4_bits_data_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _rob_io_wb_resps_4_bits_data_T_3 = rob_io_wb_resps_4_bits_data_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _rob_io_wb_resps_4_bits_data_T_4 = _rob_io_wb_resps_4_bits_data_T_2 ? rob_io_wb_resps_4_bits_data_prevUnrecoded : _rob_io_wb_resps_4_bits_data_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [63:0] _rob_io_wb_resps_4_bits_data_T_5 = {_rob_io_wb_resps_4_bits_data_T, _rob_io_wb_resps_4_bits_data_T_4}; // @[FPU.scala:446:{10,21,44}] wire [11:0] rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp = _fp_pipeline_io_wb_1_bits_data[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isZero_T = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isZero = _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isZero_0 = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isSpecial_T = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isSpecial = &_rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isNaN_T = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isNaN_T_1 = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isSpecial & _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isNaN = _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T_1 = ~_rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T_2 = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isSpecial & _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isInf = _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sign_T = _fp_pipeline_io_wb_1_bits_data[64]; // @[rawFloatFromRecFN.scala:59:25] assign rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sign = _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sExp_T = {1'h0, rob_io_wb_resps_5_bits_data_unrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sExp = _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T = ~rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_1 = {1'h0, _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_2 = _fp_pipeline_io_wb_1_bits_data[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_3 = {_rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_1, _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sig = _rob_io_wb_resps_5_bits_data_unrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire rob_io_wb_resps_5_bits_data_unrecoded_isSubnormal = $signed(rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sExp) < 13'sh402; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist_T = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sExp[5:0]; // @[rawFloatFromRecFN.scala:55:23] wire [6:0] _rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist_T_1 = 7'h1 - {1'h0, _rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [5:0] rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist = _rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist_T_1[5:0]; // @[fNFromRecFN.scala:52:35] wire [52:0] _rob_io_wb_resps_5_bits_data_unrecoded_denormFract_T = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sig[53:1]; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _rob_io_wb_resps_5_bits_data_unrecoded_denormFract_T_1 = _rob_io_wb_resps_5_bits_data_unrecoded_denormFract_T >> rob_io_wb_resps_5_bits_data_unrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [51:0] rob_io_wb_resps_5_bits_data_unrecoded_denormFract = _rob_io_wb_resps_5_bits_data_unrecoded_denormFract_T_1[51:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [10:0] _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sExp[10:0]; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_1 = {1'h0, _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T} - 12'h401; // @[fNFromRecFN.scala:58:{27,45}] wire [10:0] _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_2 = _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_1[10:0]; // @[fNFromRecFN.scala:58:45] wire [10:0] _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_3 = rob_io_wb_resps_5_bits_data_unrecoded_isSubnormal ? 11'h0 : _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_4 = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isNaN | rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_5 = {11{_rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [10:0] rob_io_wb_resps_5_bits_data_unrecoded_expOut = _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_3 | _rob_io_wb_resps_5_bits_data_unrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [51:0] _rob_io_wb_resps_5_bits_data_unrecoded_fractOut_T = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sig[51:0]; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] _rob_io_wb_resps_5_bits_data_unrecoded_fractOut_T_1 = rob_io_wb_resps_5_bits_data_unrecoded_rawIn_isInf ? 52'h0 : _rob_io_wb_resps_5_bits_data_unrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [51:0] rob_io_wb_resps_5_bits_data_unrecoded_fractOut = rob_io_wb_resps_5_bits_data_unrecoded_isSubnormal ? rob_io_wb_resps_5_bits_data_unrecoded_denormFract : _rob_io_wb_resps_5_bits_data_unrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [11:0] rob_io_wb_resps_5_bits_data_unrecoded_hi = {rob_io_wb_resps_5_bits_data_unrecoded_rawIn_sign, rob_io_wb_resps_5_bits_data_unrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [63:0] rob_io_wb_resps_5_bits_data_unrecoded = {rob_io_wb_resps_5_bits_data_unrecoded_hi, rob_io_wb_resps_5_bits_data_unrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire _rob_io_wb_resps_5_bits_data_prevRecoded_T = _fp_pipeline_io_wb_1_bits_data[31]; // @[FPU.scala:442:10] wire _rob_io_wb_resps_5_bits_data_prevRecoded_T_1 = _fp_pipeline_io_wb_1_bits_data[52]; // @[FPU.scala:443:10] wire [30:0] _rob_io_wb_resps_5_bits_data_prevRecoded_T_2 = _fp_pipeline_io_wb_1_bits_data[30:0]; // @[FPU.scala:444:10] wire [1:0] rob_io_wb_resps_5_bits_data_prevRecoded_hi = {_rob_io_wb_resps_5_bits_data_prevRecoded_T, _rob_io_wb_resps_5_bits_data_prevRecoded_T_1}; // @[FPU.scala:441:28, :442:10, :443:10] wire [32:0] rob_io_wb_resps_5_bits_data_prevRecoded = {rob_io_wb_resps_5_bits_data_prevRecoded_hi, _rob_io_wb_resps_5_bits_data_prevRecoded_T_2}; // @[FPU.scala:441:28, :444:10] wire [8:0] rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp = rob_io_wb_resps_5_bits_data_prevRecoded[31:23]; // @[FPU.scala:441:28] wire [2:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isZero_T = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isZero = _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isZero_0 = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isSpecial_T = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isSpecial = &_rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isNaN_T = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1 = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isSpecial & _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isNaN = _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T_1 = ~_rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T_2 = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isSpecial & _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isInf = _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sign_T = rob_io_wb_resps_5_bits_data_prevRecoded[32]; // @[FPU.scala:441:28] assign rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sign = _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sExp_T = {1'h0, rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sExp = _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T = ~rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_1 = {1'h0, _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_2 = rob_io_wb_resps_5_bits_data_prevRecoded[22:0]; // @[FPU.scala:441:28] assign _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_3 = {_rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_1, _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sig = _rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire rob_io_wb_resps_5_bits_data_prevUnrecoded_isSubnormal = $signed(rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sExp) < 10'sh82; // @[rawFloatFromRecFN.scala:55:23] wire [4:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist_T = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sExp[4:0]; // @[rawFloatFromRecFN.scala:55:23] wire [5:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist_T_1 = 6'h1 - {1'h0, _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist_T}; // @[fNFromRecFN.scala:52:{35,47}] wire [4:0] rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist = _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist_T_1[4:0]; // @[fNFromRecFN.scala:52:35] wire [23:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract_T = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sig[24:1]; // @[rawFloatFromRecFN.scala:55:23] wire [23:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract_T_1 = _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract_T >> rob_io_wb_resps_5_bits_data_prevUnrecoded_denormShiftDist; // @[fNFromRecFN.scala:52:35, :53:{38,42}] wire [22:0] rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract = _rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract_T_1[22:0]; // @[fNFromRecFN.scala:53:{42,60}] wire [7:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sExp[7:0]; // @[rawFloatFromRecFN.scala:55:23] wire [8:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_1 = {1'h0, _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T} - 9'h81; // @[fNFromRecFN.scala:58:{27,45}] wire [7:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_2 = _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_1[7:0]; // @[fNFromRecFN.scala:58:45] wire [7:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_3 = rob_io_wb_resps_5_bits_data_prevUnrecoded_isSubnormal ? 8'h0 : _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_2; // @[fNFromRecFN.scala:51:38, :56:16, :58:45] wire _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_4 = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isNaN | rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire [7:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_5 = {8{_rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_4}}; // @[fNFromRecFN.scala:60:{21,44}] wire [7:0] rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut = _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_3 | _rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut_T_5; // @[fNFromRecFN.scala:56:16, :60:{15,21}] wire [22:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut_T = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sig[22:0]; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] _rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut_T_1 = rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_isInf ? 23'h0 : _rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut_T; // @[rawFloatFromRecFN.scala:55:23] wire [22:0] rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut = rob_io_wb_resps_5_bits_data_prevUnrecoded_isSubnormal ? rob_io_wb_resps_5_bits_data_prevUnrecoded_denormFract : _rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut_T_1; // @[fNFromRecFN.scala:51:38, :53:60, :62:16, :64:20] wire [8:0] rob_io_wb_resps_5_bits_data_prevUnrecoded_hi = {rob_io_wb_resps_5_bits_data_prevUnrecoded_rawIn_sign, rob_io_wb_resps_5_bits_data_prevUnrecoded_expOut}; // @[rawFloatFromRecFN.scala:55:23] wire [31:0] rob_io_wb_resps_5_bits_data_prevUnrecoded = {rob_io_wb_resps_5_bits_data_prevUnrecoded_hi, rob_io_wb_resps_5_bits_data_prevUnrecoded_fractOut}; // @[fNFromRecFN.scala:62:16, :66:12] wire [31:0] _rob_io_wb_resps_5_bits_data_T = rob_io_wb_resps_5_bits_data_unrecoded[63:32]; // @[FPU.scala:446:21] wire [2:0] _rob_io_wb_resps_5_bits_data_T_1 = _fp_pipeline_io_wb_1_bits_data[63:61]; // @[FPU.scala:249:25] wire _rob_io_wb_resps_5_bits_data_T_2 = &_rob_io_wb_resps_5_bits_data_T_1; // @[FPU.scala:249:{25,56}] wire [31:0] _rob_io_wb_resps_5_bits_data_T_3 = rob_io_wb_resps_5_bits_data_unrecoded[31:0]; // @[FPU.scala:446:81] wire [31:0] _rob_io_wb_resps_5_bits_data_T_4 = _rob_io_wb_resps_5_bits_data_T_2 ? rob_io_wb_resps_5_bits_data_prevUnrecoded : _rob_io_wb_resps_5_bits_data_T_3; // @[FPU.scala:249:56, :446:{44,81}] wire [63:0] _rob_io_wb_resps_5_bits_data_T_5 = {_rob_io_wb_resps_5_bits_data_T, _rob_io_wb_resps_5_bits_data_T_4}; // @[FPU.scala:446:{10,21,44}] reg fp_pipeline_io_flush_pipeline_REG; // @[core.scala:1250:43] reg alu_exe_unit_0_io_kill_REG; // @[core.scala:1253:26] reg alu_exe_unit_1_io_kill_REG; // @[core.scala:1253:26] reg mem_exe_unit_0_io_kill_REG; // @[core.scala:1253:26] reg mem_exe_unit_1_io_kill_REG; // @[core.scala:1253:26] reg unique_exe_unit_0_io_kill_REG; // @[core.scala:1253:26] reg [4:0] small_0; // @[Counters.scala:45:41] wire [5:0] nextSmall = {1'h0, small_0} + 6'h1; // @[Counters.scala:45:41, :46:33] reg [26:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[5]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T; // @[Counters.scala:51:{20,33}] wire [27:0] _large_r_T = {1'h0, large_0} + 28'h1; // @[Counters.scala:50:31, :51:55] wire [26:0] _large_r_T_1 = _large_r_T[26:0]; // @[Counters.scala:51:55] wire [31:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30]
Generate the Verilog code corresponding to this FIRRTL code module MSHR_7 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<7>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h20)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h20)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h20)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)
module MSHR_7( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 7'h20; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 7'h20; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 7'h20; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module Pipeline_15 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, dram_addr : UInt, spad_addr : UInt, pool_dram_addr : UInt, pool_spad_addr : UInt, channels : UInt, is_pool : UInt<1>, I : UInt, J : UInt}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, dram_addr : UInt, spad_addr : UInt, pool_dram_addr : UInt, pool_spad_addr : UInt, channels : UInt, is_pool : UInt<1>, I : UInt, J : UInt}}, busy : UInt<1>} reg stages : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, dram_addr : UInt, spad_addr : UInt, pool_dram_addr : UInt, pool_spad_addr : UInt, channels : UInt, is_pool : UInt<1>, I : UInt, J : UInt}[2], clock wire _valids_WIRE : UInt<1>[2] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) regreset valids : UInt<1>[2], clock, reset, _valids_WIRE wire stalling : UInt<1>[2] connect stalling[0], UInt<1>(0h0) connect stalling[1], UInt<1>(0h0) node _io_busy_T = or(valids[0], valids[1]) node _io_busy_T_1 = or(io.in.valid, _io_busy_T) connect io.busy, _io_busy_T_1 node _io_in_ready_T = eq(stalling[0], UInt<1>(0h0)) connect io.in.ready, _io_in_ready_T node _stalling_1_T = eq(io.out.ready, UInt<1>(0h0)) node _stalling_1_T_1 = and(valids[1], _stalling_1_T) connect stalling[1], _stalling_1_T_1 node _stalling_0_T = and(valids[0], stalling[1]) connect stalling[0], _stalling_0_T connect io.out.valid, valids[1] when io.out.ready : connect valids[1], UInt<1>(0h0) node _T = eq(stalling[1], UInt<1>(0h0)) when _T : connect valids[0], UInt<1>(0h0) node _T_1 = and(io.in.ready, io.in.valid) when _T_1 : connect valids[0], UInt<1>(0h1) when valids[0] : connect valids[1], UInt<1>(0h1) node _T_2 = and(io.in.ready, io.in.valid) when _T_2 : connect stages[0], io.in.bits connect io.out.bits, stages[1] node _T_3 = eq(stalling[1], UInt<1>(0h0)) when _T_3 : connect stages[1], stages[0]
module Pipeline_15( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [6:0] io_in_bits_cmd_inst_funct, // @[Pipeline.scala:7:14] input [63:0] io_in_bits_cmd_rs1, // @[Pipeline.scala:7:14] input [63:0] io_in_bits_cmd_rs2, // @[Pipeline.scala:7:14] input [69:0] io_in_bits_dram_addr, // @[Pipeline.scala:7:14] input [67:0] io_in_bits_spad_addr, // @[Pipeline.scala:7:14] input [66:0] io_in_bits_pool_dram_addr, // @[Pipeline.scala:7:14] input [65:0] io_in_bits_pool_spad_addr, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_channels, // @[Pipeline.scala:7:14] input io_in_bits_is_pool, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_I, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_J, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [6:0] io_out_bits_cmd_inst_funct, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rs2, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rs1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xd, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xs1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xs2, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rd, // @[Pipeline.scala:7:14] output [6:0] io_out_bits_cmd_inst_opcode, // @[Pipeline.scala:7:14] output [63:0] io_out_bits_cmd_rs1, // @[Pipeline.scala:7:14] output [63:0] io_out_bits_cmd_rs2, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_debug, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_cease, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_wfi, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_cmd_status_isa, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_dprv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_dv, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_prv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_v, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sd, // @[Pipeline.scala:7:14] output [22:0] io_out_bits_cmd_status_zero2, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mpv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_gva, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mbe, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sbe, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_sxl, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_uxl, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sd_rv32, // @[Pipeline.scala:7:14] output [7:0] io_out_bits_cmd_status_zero1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tsr, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tw, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tvm, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mxr, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sum, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mprv, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_xs, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_fs, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_mpp, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_vs, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_spp, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mpie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_ube, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_spie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_upie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_hie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_uie, // @[Pipeline.scala:7:14] output [69:0] io_out_bits_dram_addr, // @[Pipeline.scala:7:14] output [67:0] io_out_bits_spad_addr, // @[Pipeline.scala:7:14] output [66:0] io_out_bits_pool_dram_addr, // @[Pipeline.scala:7:14] output [65:0] io_out_bits_pool_spad_addr, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_channels, // @[Pipeline.scala:7:14] output io_out_bits_is_pool, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_I, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_J, // @[Pipeline.scala:7:14] output io_busy // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [6:0] io_in_bits_cmd_inst_funct_0 = io_in_bits_cmd_inst_funct; // @[Pipeline.scala:6:7] wire [63:0] io_in_bits_cmd_rs1_0 = io_in_bits_cmd_rs1; // @[Pipeline.scala:6:7] wire [63:0] io_in_bits_cmd_rs2_0 = io_in_bits_cmd_rs2; // @[Pipeline.scala:6:7] wire [69:0] io_in_bits_dram_addr_0 = io_in_bits_dram_addr; // @[Pipeline.scala:6:7] wire [67:0] io_in_bits_spad_addr_0 = io_in_bits_spad_addr; // @[Pipeline.scala:6:7] wire [66:0] io_in_bits_pool_dram_addr_0 = io_in_bits_pool_dram_addr; // @[Pipeline.scala:6:7] wire [65:0] io_in_bits_pool_spad_addr_0 = io_in_bits_pool_spad_addr; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_channels_0 = io_in_bits_channels; // @[Pipeline.scala:6:7] wire io_in_bits_is_pool_0 = io_in_bits_is_pool; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_I_0 = io_in_bits_I; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_J_0 = io_in_bits_J; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire [4:0] io_in_bits_cmd_inst_rs2 = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [4:0] io_in_bits_cmd_inst_rs1 = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [4:0] io_in_bits_cmd_inst_rd = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [6:0] io_in_bits_cmd_inst_opcode = 7'h0; // @[Pipeline.scala:6:7, :7:14] wire [31:0] io_in_bits_cmd_status_isa = 32'h0; // @[Pipeline.scala:6:7, :7:14] wire [22:0] io_in_bits_cmd_status_zero2 = 23'h0; // @[Pipeline.scala:6:7, :7:14] wire [7:0] io_in_bits_cmd_status_zero1 = 8'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_dprv = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_prv = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_sxl = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_uxl = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_xs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_fs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_mpp = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_vs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire io_in_bits_cmd_inst_xd = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_inst_xs1 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_inst_xs2 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_debug = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_cease = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_wfi = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_dv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_v = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sd = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mpv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_gva = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mbe = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sbe = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sd_rv32 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tsr = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tw = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tvm = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mxr = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sum = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mprv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_spp = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mpie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_ube = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_spie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_upie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_hie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_uie = 1'h0; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_1; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [6:0] io_out_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rs2_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rs1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xd_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xs1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xs2_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rd_0; // @[Pipeline.scala:6:7] wire [6:0] io_out_bits_cmd_inst_opcode_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_debug_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_cease_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_wfi_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_cmd_status_isa_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_dprv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_dv_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_prv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_v_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sd_0; // @[Pipeline.scala:6:7] wire [22:0] io_out_bits_cmd_status_zero2_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mpv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_gva_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mbe_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sbe_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_sxl_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_uxl_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sd_rv32_0; // @[Pipeline.scala:6:7] wire [7:0] io_out_bits_cmd_status_zero1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tsr_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tw_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tvm_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mxr_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sum_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mprv_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_xs_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_fs_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_mpp_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_vs_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_spp_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mpie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_ube_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_spie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_upie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_hie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_uie_0; // @[Pipeline.scala:6:7] wire [63:0] io_out_bits_cmd_rs1_0; // @[Pipeline.scala:6:7] wire [63:0] io_out_bits_cmd_rs2_0; // @[Pipeline.scala:6:7] wire [69:0] io_out_bits_dram_addr_0; // @[Pipeline.scala:6:7] wire [67:0] io_out_bits_spad_addr_0; // @[Pipeline.scala:6:7] wire [66:0] io_out_bits_pool_dram_addr_0; // @[Pipeline.scala:6:7] wire [65:0] io_out_bits_pool_spad_addr_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_channels_0; // @[Pipeline.scala:6:7] wire io_out_bits_is_pool_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_I_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_J_0; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy_0; // @[Pipeline.scala:6:7] reg [6:0] stages_0_cmd_inst_funct; // @[Pipeline.scala:21:21] reg [63:0] stages_0_cmd_rs1; // @[Pipeline.scala:21:21] reg [63:0] stages_0_cmd_rs2; // @[Pipeline.scala:21:21] reg [69:0] stages_0_dram_addr; // @[Pipeline.scala:21:21] reg [67:0] stages_0_spad_addr; // @[Pipeline.scala:21:21] reg [66:0] stages_0_pool_dram_addr; // @[Pipeline.scala:21:21] reg [65:0] stages_0_pool_spad_addr; // @[Pipeline.scala:21:21] reg [15:0] stages_0_channels; // @[Pipeline.scala:21:21] reg stages_0_is_pool; // @[Pipeline.scala:21:21] reg [15:0] stages_0_I; // @[Pipeline.scala:21:21] reg [15:0] stages_0_J; // @[Pipeline.scala:21:21] reg [6:0] stages_1_cmd_inst_funct; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_funct_0 = stages_1_cmd_inst_funct; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rs2_0 = stages_1_cmd_inst_rs2; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rs1_0 = stages_1_cmd_inst_rs1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xd_0 = stages_1_cmd_inst_xd; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xs1_0 = stages_1_cmd_inst_xs1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xs2_0 = stages_1_cmd_inst_xs2; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rd_0 = stages_1_cmd_inst_rd; // @[Pipeline.scala:6:7, :21:21] reg [6:0] stages_1_cmd_inst_opcode; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_opcode_0 = stages_1_cmd_inst_opcode; // @[Pipeline.scala:6:7, :21:21] reg [63:0] stages_1_cmd_rs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_rs1_0 = stages_1_cmd_rs1; // @[Pipeline.scala:6:7, :21:21] reg [63:0] stages_1_cmd_rs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_rs2_0 = stages_1_cmd_rs2; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_debug; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_debug_0 = stages_1_cmd_status_debug; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_cease; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_cease_0 = stages_1_cmd_status_cease; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_wfi; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_wfi_0 = stages_1_cmd_status_wfi; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_1_cmd_status_isa; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_isa_0 = stages_1_cmd_status_isa; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_dprv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_dprv_0 = stages_1_cmd_status_dprv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_dv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_dv_0 = stages_1_cmd_status_dv; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_prv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_prv_0 = stages_1_cmd_status_prv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_v; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_v_0 = stages_1_cmd_status_v; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sd_0 = stages_1_cmd_status_sd; // @[Pipeline.scala:6:7, :21:21] reg [22:0] stages_1_cmd_status_zero2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_zero2_0 = stages_1_cmd_status_zero2; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mpv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpv_0 = stages_1_cmd_status_mpv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_gva; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_gva_0 = stages_1_cmd_status_gva; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mbe; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mbe_0 = stages_1_cmd_status_mbe; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sbe; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sbe_0 = stages_1_cmd_status_sbe; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_sxl; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sxl_0 = stages_1_cmd_status_sxl; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_uxl; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_uxl_0 = stages_1_cmd_status_uxl; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sd_rv32_0 = stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:6:7, :21:21] reg [7:0] stages_1_cmd_status_zero1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_zero1_0 = stages_1_cmd_status_zero1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tsr; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tsr_0 = stages_1_cmd_status_tsr; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tw; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tw_0 = stages_1_cmd_status_tw; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tvm; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tvm_0 = stages_1_cmd_status_tvm; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mxr; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mxr_0 = stages_1_cmd_status_mxr; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sum; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sum_0 = stages_1_cmd_status_sum; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mprv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mprv_0 = stages_1_cmd_status_mprv; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_xs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_xs_0 = stages_1_cmd_status_xs; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_fs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_fs_0 = stages_1_cmd_status_fs; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_mpp; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpp_0 = stages_1_cmd_status_mpp; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_vs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_vs_0 = stages_1_cmd_status_vs; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_spp; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_spp_0 = stages_1_cmd_status_spp; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mpie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpie_0 = stages_1_cmd_status_mpie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_ube; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_ube_0 = stages_1_cmd_status_ube; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_spie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_spie_0 = stages_1_cmd_status_spie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_upie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_upie_0 = stages_1_cmd_status_upie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mie_0 = stages_1_cmd_status_mie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_hie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_hie_0 = stages_1_cmd_status_hie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sie_0 = stages_1_cmd_status_sie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_uie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_uie_0 = stages_1_cmd_status_uie; // @[Pipeline.scala:6:7, :21:21] reg [69:0] stages_1_dram_addr; // @[Pipeline.scala:21:21] assign io_out_bits_dram_addr_0 = stages_1_dram_addr; // @[Pipeline.scala:6:7, :21:21] reg [67:0] stages_1_spad_addr; // @[Pipeline.scala:21:21] assign io_out_bits_spad_addr_0 = stages_1_spad_addr; // @[Pipeline.scala:6:7, :21:21] reg [66:0] stages_1_pool_dram_addr; // @[Pipeline.scala:21:21] assign io_out_bits_pool_dram_addr_0 = stages_1_pool_dram_addr; // @[Pipeline.scala:6:7, :21:21] reg [65:0] stages_1_pool_spad_addr; // @[Pipeline.scala:21:21] assign io_out_bits_pool_spad_addr_0 = stages_1_pool_spad_addr; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_1_channels; // @[Pipeline.scala:21:21] assign io_out_bits_channels_0 = stages_1_channels; // @[Pipeline.scala:6:7, :21:21] reg stages_1_is_pool; // @[Pipeline.scala:21:21] assign io_out_bits_is_pool_0 = stages_1_is_pool; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_1_I; // @[Pipeline.scala:21:21] assign io_out_bits_I_0 = stages_1_I; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_1_J; // @[Pipeline.scala:21:21] assign io_out_bits_J_0 = stages_1_J; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_1; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_1 = io_in_valid_0 | _io_busy_T; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy_0 = _io_busy_T_1; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_1_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_1_T_1 = valids_1 & _stalling_1_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_1 = _stalling_1_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] wire _T_2 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_2) begin // @[Decoupled.scala:51:35] stages_0_cmd_inst_funct <= io_in_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7, :21:21] stages_0_cmd_rs1 <= io_in_bits_cmd_rs1_0; // @[Pipeline.scala:6:7, :21:21] stages_0_cmd_rs2 <= io_in_bits_cmd_rs2_0; // @[Pipeline.scala:6:7, :21:21] stages_0_dram_addr <= io_in_bits_dram_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_spad_addr <= io_in_bits_spad_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_pool_dram_addr <= io_in_bits_pool_dram_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_pool_spad_addr <= io_in_bits_pool_spad_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_channels <= io_in_bits_channels_0; // @[Pipeline.scala:6:7, :21:21] stages_0_is_pool <= io_in_bits_is_pool_0; // @[Pipeline.scala:6:7, :21:21] stages_0_I <= io_in_bits_I_0; // @[Pipeline.scala:6:7, :21:21] stages_0_J <= io_in_bits_J_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_cmd_inst_funct <= stages_0_cmd_inst_funct; // @[Pipeline.scala:21:21] stages_1_cmd_inst_rs2 <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_rs1 <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_rd <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_opcode <= 7'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_rs1 <= stages_0_cmd_rs1; // @[Pipeline.scala:21:21] stages_1_cmd_rs2 <= stages_0_cmd_rs2; // @[Pipeline.scala:21:21] stages_1_cmd_status_isa <= 32'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_dprv <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_prv <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_zero2 <= 23'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_sxl <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_uxl <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_zero1 <= 8'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_xs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_fs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_mpp <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_vs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_dram_addr <= stages_0_dram_addr; // @[Pipeline.scala:21:21] stages_1_spad_addr <= stages_0_spad_addr; // @[Pipeline.scala:21:21] stages_1_pool_dram_addr <= stages_0_pool_dram_addr; // @[Pipeline.scala:21:21] stages_1_pool_spad_addr <= stages_0_pool_spad_addr; // @[Pipeline.scala:21:21] stages_1_channels <= stages_0_channels; // @[Pipeline.scala:21:21] stages_1_is_pool <= stages_0_is_pool; // @[Pipeline.scala:21:21] stages_1_I <= stages_0_I; // @[Pipeline.scala:21:21] stages_1_J <= stages_0_J; // @[Pipeline.scala:21:21] end stages_1_cmd_inst_xd <= stalling_1 & stages_1_cmd_inst_xd; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_inst_xs1 <= stalling_1 & stages_1_cmd_inst_xs1; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_inst_xs2 <= stalling_1 & stages_1_cmd_inst_xs2; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_debug <= stalling_1 & stages_1_cmd_status_debug; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_cease <= stalling_1 & stages_1_cmd_status_cease; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_wfi <= stalling_1 & stages_1_cmd_status_wfi; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_dv <= stalling_1 & stages_1_cmd_status_dv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_v <= stalling_1 & stages_1_cmd_status_v; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sd <= stalling_1 & stages_1_cmd_status_sd; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mpv <= stalling_1 & stages_1_cmd_status_mpv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_gva <= stalling_1 & stages_1_cmd_status_gva; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mbe <= stalling_1 & stages_1_cmd_status_mbe; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sbe <= stalling_1 & stages_1_cmd_status_sbe; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sd_rv32 <= stalling_1 & stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tsr <= stalling_1 & stages_1_cmd_status_tsr; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tw <= stalling_1 & stages_1_cmd_status_tw; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tvm <= stalling_1 & stages_1_cmd_status_tvm; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mxr <= stalling_1 & stages_1_cmd_status_mxr; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sum <= stalling_1 & stages_1_cmd_status_sum; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mprv <= stalling_1 & stages_1_cmd_status_mprv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_spp <= stalling_1 & stages_1_cmd_status_spp; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mpie <= stalling_1 & stages_1_cmd_status_mpie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_ube <= stalling_1 & stages_1_cmd_status_ube; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_spie <= stalling_1 & stages_1_cmd_status_spie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_upie <= stalling_1 & stages_1_cmd_status_upie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mie <= stalling_1 & stages_1_cmd_status_mie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_hie <= stalling_1 & stages_1_cmd_status_hie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sie <= stalling_1 & stages_1_cmd_status_sie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_uie <= stalling_1 & stages_1_cmd_status_uie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_2 | stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 | ~io_out_ready_0 & valids_1; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_funct = io_out_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rs2 = io_out_bits_cmd_inst_rs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rs1 = io_out_bits_cmd_inst_rs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xd = io_out_bits_cmd_inst_xd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xs1 = io_out_bits_cmd_inst_xs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xs2 = io_out_bits_cmd_inst_xs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rd = io_out_bits_cmd_inst_rd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_opcode = io_out_bits_cmd_inst_opcode_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_rs1 = io_out_bits_cmd_rs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_rs2 = io_out_bits_cmd_rs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_debug = io_out_bits_cmd_status_debug_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_cease = io_out_bits_cmd_status_cease_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_wfi = io_out_bits_cmd_status_wfi_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_isa = io_out_bits_cmd_status_isa_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_dprv = io_out_bits_cmd_status_dprv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_dv = io_out_bits_cmd_status_dv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_prv = io_out_bits_cmd_status_prv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_v = io_out_bits_cmd_status_v_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sd = io_out_bits_cmd_status_sd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_zero2 = io_out_bits_cmd_status_zero2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpv = io_out_bits_cmd_status_mpv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_gva = io_out_bits_cmd_status_gva_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mbe = io_out_bits_cmd_status_mbe_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sbe = io_out_bits_cmd_status_sbe_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sxl = io_out_bits_cmd_status_sxl_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_uxl = io_out_bits_cmd_status_uxl_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sd_rv32 = io_out_bits_cmd_status_sd_rv32_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_zero1 = io_out_bits_cmd_status_zero1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tsr = io_out_bits_cmd_status_tsr_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tw = io_out_bits_cmd_status_tw_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tvm = io_out_bits_cmd_status_tvm_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mxr = io_out_bits_cmd_status_mxr_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sum = io_out_bits_cmd_status_sum_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mprv = io_out_bits_cmd_status_mprv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_xs = io_out_bits_cmd_status_xs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_fs = io_out_bits_cmd_status_fs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpp = io_out_bits_cmd_status_mpp_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_vs = io_out_bits_cmd_status_vs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_spp = io_out_bits_cmd_status_spp_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpie = io_out_bits_cmd_status_mpie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_ube = io_out_bits_cmd_status_ube_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_spie = io_out_bits_cmd_status_spie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_upie = io_out_bits_cmd_status_upie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mie = io_out_bits_cmd_status_mie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_hie = io_out_bits_cmd_status_hie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sie = io_out_bits_cmd_status_sie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_uie = io_out_bits_cmd_status_uie_0; // @[Pipeline.scala:6:7] assign io_out_bits_dram_addr = io_out_bits_dram_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_spad_addr = io_out_bits_spad_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_pool_dram_addr = io_out_bits_pool_dram_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_pool_spad_addr = io_out_bits_pool_spad_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_channels = io_out_bits_channels_0; // @[Pipeline.scala:6:7] assign io_out_bits_is_pool = io_out_bits_is_pool_0; // @[Pipeline.scala:6:7] assign io_out_bits_I = io_out_bits_I_0; // @[Pipeline.scala:6:7] assign io_out_bits_J = io_out_bits_J_0; // @[Pipeline.scala:6:7] assign io_busy = io_busy_0; // @[Pipeline.scala:6:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_174 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_310 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_174( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_310 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<3>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<3>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<3>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<6>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<3>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<3>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<1>, clock reg probes_toN : UInt<1>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node req_clientBit = eq(request.source, UInt<6>(0h20)) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node probe_bit = eq(io.sinkc.bits.source, UInt<6>(0h20)) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node new_clientBit = eq(new_request.source, UInt<6>(0h20)) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)
module MSHR( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [2:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [2:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_source = 3'h0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_sink = 3'h0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire invalid_clients = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg meta_clients; // @[MSHR.scala:100:17] wire _meta_no_clients_T = meta_clients; // @[MSHR.scala:100:17, :220:39] wire evict_c = meta_clients; // @[MSHR.scala:100:17, :315:27] wire before_c = meta_clients; // @[MSHR.scala:100:17, :315:27] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg probes_done; // @[MSHR.scala:150:24] reg probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire after_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire prior_c = final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire req_clientBit = request_source == 6'h20; // @[Parameters.scala:46:9] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire _final_meta_writeback_clients_T_12 = meta_hit & _final_meta_writeback_clients_T_11; // @[MSHR.scala:100:17, :245:{40,64}] wire _final_meta_writeback_clients_T_13 = req_acquire & req_clientBit; // @[Parameters.scala:46:9] wire _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? meta_hit & _final_meta_writeback_clients_T_16 : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:46:9] wire _honour_BtoT_T_1 = _honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire excluded_client = _excluded_client_T_9 & req_clientBit; // @[Parameters.scala:46:9] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire probe_bit = io_sinkc_bits_source_0 == 6'h20; // @[Parameters.scala:46:9] wire _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:46:9] wire _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire _probes_toN_T = probe_toN & probe_bit; // @[Parameters.scala:46:9] wire _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire new_clientBit = new_request_source == 6'h20; // @[Parameters.scala:46:9] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire new_skipProbe = _new_skipProbe_T_7 & new_clientBit; // @[Parameters.scala:46:9] wire [3:0] prior; // @[MSHR.scala:314:26] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module Tile_112 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_368 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_112( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_368 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module EgressUnit_31 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<1>}}[1], credit_available : UInt<1>[1], channel_status : { occupied : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip allocs : { alloc : UInt<1>, flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}}[1], flip credit_alloc : { alloc : UInt<1>, tail : UInt<1>}[1], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<37>, ingress_id : UInt}}} regreset channel_empty : UInt<1>, clock, reset, UInt<1>(0h1) reg flow : { vnet_id : UInt<1>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<2>}, clock inst q of Queue2_EgressFlit_31 connect q.clock, clock connect q.reset, reset connect q.io.enq.valid, io.in[0].valid connect q.io.enq.bits.head, io.in[0].bits.head connect q.io.enq.bits.tail, io.in[0].bits.tail node _q_io_enq_bits_ingress_id_T = eq(UInt<4>(0hf), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_1 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_2 = and(_q_io_enq_bits_ingress_id_T, _q_io_enq_bits_ingress_id_T_1) node _q_io_enq_bits_ingress_id_T_3 = eq(UInt<3>(0h4), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_4 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_5 = and(_q_io_enq_bits_ingress_id_T_3, _q_io_enq_bits_ingress_id_T_4) node _q_io_enq_bits_ingress_id_T_6 = eq(UInt<4>(0he), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_7 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_8 = and(_q_io_enq_bits_ingress_id_T_6, _q_io_enq_bits_ingress_id_T_7) node _q_io_enq_bits_ingress_id_T_9 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_10 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_11 = and(_q_io_enq_bits_ingress_id_T_9, _q_io_enq_bits_ingress_id_T_10) node _q_io_enq_bits_ingress_id_T_12 = eq(UInt<4>(0hb), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_13 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_14 = and(_q_io_enq_bits_ingress_id_T_12, _q_io_enq_bits_ingress_id_T_13) node _q_io_enq_bits_ingress_id_T_15 = eq(UInt<3>(0h7), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_16 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_17 = and(_q_io_enq_bits_ingress_id_T_15, _q_io_enq_bits_ingress_id_T_16) node _q_io_enq_bits_ingress_id_T_18 = eq(UInt<4>(0hc), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_19 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_20 = and(_q_io_enq_bits_ingress_id_T_18, _q_io_enq_bits_ingress_id_T_19) node _q_io_enq_bits_ingress_id_T_21 = eq(UInt<4>(0hd), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_22 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_23 = and(_q_io_enq_bits_ingress_id_T_21, _q_io_enq_bits_ingress_id_T_22) node _q_io_enq_bits_ingress_id_T_24 = eq(UInt<1>(0h1), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_25 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_26 = and(_q_io_enq_bits_ingress_id_T_24, _q_io_enq_bits_ingress_id_T_25) node _q_io_enq_bits_ingress_id_T_27 = eq(UInt<4>(0h8), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_28 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_29 = and(_q_io_enq_bits_ingress_id_T_27, _q_io_enq_bits_ingress_id_T_28) node _q_io_enq_bits_ingress_id_T_30 = eq(UInt<2>(0h2), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_31 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_32 = and(_q_io_enq_bits_ingress_id_T_30, _q_io_enq_bits_ingress_id_T_31) node _q_io_enq_bits_ingress_id_T_33 = eq(UInt<2>(0h3), io.in[0].bits.flow.ingress_node) node _q_io_enq_bits_ingress_id_T_34 = eq(UInt<1>(0h0), io.in[0].bits.flow.ingress_node_id) node _q_io_enq_bits_ingress_id_T_35 = and(_q_io_enq_bits_ingress_id_T_33, _q_io_enq_bits_ingress_id_T_34) node _q_io_enq_bits_ingress_id_T_36 = mux(_q_io_enq_bits_ingress_id_T_2, UInt<5>(0hc), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_37 = mux(_q_io_enq_bits_ingress_id_T_5, UInt<5>(0h5), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_38 = mux(_q_io_enq_bits_ingress_id_T_8, UInt<5>(0hb), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_39 = mux(_q_io_enq_bits_ingress_id_T_11, UInt<5>(0h1), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_40 = mux(_q_io_enq_bits_ingress_id_T_14, UInt<5>(0h8), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_41 = mux(_q_io_enq_bits_ingress_id_T_17, UInt<5>(0h6), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_42 = mux(_q_io_enq_bits_ingress_id_T_20, UInt<5>(0h9), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_43 = mux(_q_io_enq_bits_ingress_id_T_23, UInt<5>(0ha), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_44 = mux(_q_io_enq_bits_ingress_id_T_26, UInt<5>(0h2), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_45 = mux(_q_io_enq_bits_ingress_id_T_29, UInt<5>(0h7), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_46 = mux(_q_io_enq_bits_ingress_id_T_32, UInt<5>(0h3), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_47 = mux(_q_io_enq_bits_ingress_id_T_35, UInt<5>(0h4), UInt<1>(0h0)) node _q_io_enq_bits_ingress_id_T_48 = or(_q_io_enq_bits_ingress_id_T_36, _q_io_enq_bits_ingress_id_T_37) node _q_io_enq_bits_ingress_id_T_49 = or(_q_io_enq_bits_ingress_id_T_48, _q_io_enq_bits_ingress_id_T_38) node _q_io_enq_bits_ingress_id_T_50 = or(_q_io_enq_bits_ingress_id_T_49, _q_io_enq_bits_ingress_id_T_39) node _q_io_enq_bits_ingress_id_T_51 = or(_q_io_enq_bits_ingress_id_T_50, _q_io_enq_bits_ingress_id_T_40) node _q_io_enq_bits_ingress_id_T_52 = or(_q_io_enq_bits_ingress_id_T_51, _q_io_enq_bits_ingress_id_T_41) node _q_io_enq_bits_ingress_id_T_53 = or(_q_io_enq_bits_ingress_id_T_52, _q_io_enq_bits_ingress_id_T_42) node _q_io_enq_bits_ingress_id_T_54 = or(_q_io_enq_bits_ingress_id_T_53, _q_io_enq_bits_ingress_id_T_43) node _q_io_enq_bits_ingress_id_T_55 = or(_q_io_enq_bits_ingress_id_T_54, _q_io_enq_bits_ingress_id_T_44) node _q_io_enq_bits_ingress_id_T_56 = or(_q_io_enq_bits_ingress_id_T_55, _q_io_enq_bits_ingress_id_T_45) node _q_io_enq_bits_ingress_id_T_57 = or(_q_io_enq_bits_ingress_id_T_56, _q_io_enq_bits_ingress_id_T_46) node _q_io_enq_bits_ingress_id_T_58 = or(_q_io_enq_bits_ingress_id_T_57, _q_io_enq_bits_ingress_id_T_47) wire _q_io_enq_bits_ingress_id_WIRE : UInt<5> connect _q_io_enq_bits_ingress_id_WIRE, _q_io_enq_bits_ingress_id_T_58 connect q.io.enq.bits.ingress_id, _q_io_enq_bits_ingress_id_WIRE connect q.io.enq.bits.payload, io.in[0].bits.payload connect io.out.bits, q.io.deq.bits connect io.out.valid, q.io.deq.valid connect q.io.deq.ready, io.out.ready node _T = eq(q.io.enq.ready, UInt<1>(0h0)) node _T_1 = and(q.io.enq.valid, _T) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at EgressUnit.scala:38 assert(!(q.io.enq.valid && !q.io.enq.ready))\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _io_credit_available_0_T = eq(q.io.count, UInt<1>(0h0)) connect io.credit_available[0], _io_credit_available_0_T node _io_channel_status_0_occupied_T = eq(channel_empty, UInt<1>(0h0)) connect io.channel_status[0].occupied, _io_channel_status_0_occupied_T connect io.channel_status[0].flow, flow node _T_6 = and(io.credit_alloc[0].alloc, io.credit_alloc[0].tail) when _T_6 : connect channel_empty, UInt<1>(0h1) when io.allocs[0].alloc : connect channel_empty, UInt<1>(0h0) connect flow, io.allocs[0].flow
module EgressUnit_31( // @[EgressUnit.scala:12:7] input clock, // @[EgressUnit.scala:12:7] input reset, // @[EgressUnit.scala:12:7] input io_in_0_valid, // @[EgressUnit.scala:18:14] input io_in_0_bits_head, // @[EgressUnit.scala:18:14] input io_in_0_bits_tail, // @[EgressUnit.scala:18:14] input [36:0] io_in_0_bits_payload, // @[EgressUnit.scala:18:14] input [3:0] io_in_0_bits_flow_ingress_node, // @[EgressUnit.scala:18:14] input [1:0] io_in_0_bits_flow_ingress_node_id, // @[EgressUnit.scala:18:14] output io_credit_available_0, // @[EgressUnit.scala:18:14] output io_channel_status_0_occupied, // @[EgressUnit.scala:18:14] input io_allocs_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_alloc, // @[EgressUnit.scala:18:14] input io_credit_alloc_0_tail, // @[EgressUnit.scala:18:14] input io_out_ready, // @[EgressUnit.scala:18:14] output io_out_valid, // @[EgressUnit.scala:18:14] output io_out_bits_head, // @[EgressUnit.scala:18:14] output io_out_bits_tail, // @[EgressUnit.scala:18:14] output [36:0] io_out_bits_payload // @[EgressUnit.scala:18:14] ); wire _q_io_enq_ready; // @[EgressUnit.scala:22:17] wire [1:0] _q_io_count; // @[EgressUnit.scala:22:17] reg channel_empty; // @[EgressUnit.scala:20:30] wire _q_io_enq_bits_ingress_id_T_34 = io_in_0_bits_flow_ingress_node_id == 2'h0; // @[EgressUnit.scala:32:27]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_51 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_20 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_21 = and(_T_19, _T_20) node _T_22 = or(UInt<1>(0h0), _T_21) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = and(_T_22, _T_27) node _T_29 = or(UInt<1>(0h0), _T_28) node _T_30 = and(_T_18, _T_29) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_30, UInt<1>(0h1), "") : assert_2 node _T_34 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_35 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_36 = and(_T_34, _T_35) node _T_37 = or(UInt<1>(0h0), _T_36) node _T_38 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = and(_T_37, _T_42) node _T_44 = or(UInt<1>(0h0), _T_43) node _T_45 = and(UInt<1>(0h0), _T_44) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_45, UInt<1>(0h1), "") : assert_3 node _T_49 = asUInt(reset) node _T_50 = eq(_T_49, UInt<1>(0h0)) when _T_50 : node _T_51 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_52 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_52, UInt<1>(0h1), "") : assert_5 node _T_56 = asUInt(reset) node _T_57 = eq(_T_56, UInt<1>(0h0)) when _T_57 : node _T_58 = eq(is_aligned, UInt<1>(0h0)) when _T_58 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_59 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_60 = asUInt(reset) node _T_61 = eq(_T_60, UInt<1>(0h0)) when _T_61 : node _T_62 = eq(_T_59, UInt<1>(0h0)) when _T_62 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_59, UInt<1>(0h1), "") : assert_7 node _T_63 = not(io.in.a.bits.mask) node _T_64 = eq(_T_63, UInt<1>(0h0)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_64, UInt<1>(0h1), "") : assert_8 node _T_68 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_68, UInt<1>(0h1), "") : assert_9 node _T_72 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_72 : node _T_73 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_74 = and(UInt<1>(0h0), _T_73) node _T_75 = or(UInt<1>(0h0), _T_74) node _T_76 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_77 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_78 = and(_T_76, _T_77) node _T_79 = or(UInt<1>(0h0), _T_78) node _T_80 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_81 = cvt(_T_80) node _T_82 = and(_T_81, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_83 = asSInt(_T_82) node _T_84 = eq(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = and(_T_79, _T_84) node _T_86 = or(UInt<1>(0h0), _T_85) node _T_87 = and(_T_75, _T_86) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_87, UInt<1>(0h1), "") : assert_10 node _T_91 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_92 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_93 = and(_T_91, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = and(_T_94, _T_99) node _T_101 = or(UInt<1>(0h0), _T_100) node _T_102 = and(UInt<1>(0h0), _T_101) node _T_103 = asUInt(reset) node _T_104 = eq(_T_103, UInt<1>(0h0)) when _T_104 : node _T_105 = eq(_T_102, UInt<1>(0h0)) when _T_105 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_102, UInt<1>(0h1), "") : assert_11 node _T_106 = asUInt(reset) node _T_107 = eq(_T_106, UInt<1>(0h0)) when _T_107 : node _T_108 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_109 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_110 = asUInt(reset) node _T_111 = eq(_T_110, UInt<1>(0h0)) when _T_111 : node _T_112 = eq(_T_109, UInt<1>(0h0)) when _T_112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_109, UInt<1>(0h1), "") : assert_13 node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(is_aligned, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_116 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_117 = asUInt(reset) node _T_118 = eq(_T_117, UInt<1>(0h0)) when _T_118 : node _T_119 = eq(_T_116, UInt<1>(0h0)) when _T_119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_116, UInt<1>(0h1), "") : assert_15 node _T_120 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_120, UInt<1>(0h1), "") : assert_16 node _T_124 = not(io.in.a.bits.mask) node _T_125 = eq(_T_124, UInt<1>(0h0)) node _T_126 = asUInt(reset) node _T_127 = eq(_T_126, UInt<1>(0h0)) when _T_127 : node _T_128 = eq(_T_125, UInt<1>(0h0)) when _T_128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_125, UInt<1>(0h1), "") : assert_17 node _T_129 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_130 = asUInt(reset) node _T_131 = eq(_T_130, UInt<1>(0h0)) when _T_131 : node _T_132 = eq(_T_129, UInt<1>(0h0)) when _T_132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_129, UInt<1>(0h1), "") : assert_18 node _T_133 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_133 : node _T_134 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_135 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_136 = and(_T_134, _T_135) node _T_137 = or(UInt<1>(0h0), _T_136) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_137, UInt<1>(0h1), "") : assert_19 node _T_141 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_142 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_143 = and(_T_141, _T_142) node _T_144 = or(UInt<1>(0h0), _T_143) node _T_145 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_146 = cvt(_T_145) node _T_147 = and(_T_146, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_148 = asSInt(_T_147) node _T_149 = eq(_T_148, asSInt(UInt<1>(0h0))) node _T_150 = and(_T_144, _T_149) node _T_151 = or(UInt<1>(0h0), _T_150) node _T_152 = asUInt(reset) node _T_153 = eq(_T_152, UInt<1>(0h0)) when _T_153 : node _T_154 = eq(_T_151, UInt<1>(0h0)) when _T_154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_151, UInt<1>(0h1), "") : assert_20 node _T_155 = asUInt(reset) node _T_156 = eq(_T_155, UInt<1>(0h0)) when _T_156 : node _T_157 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_157 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_158 = asUInt(reset) node _T_159 = eq(_T_158, UInt<1>(0h0)) when _T_159 : node _T_160 = eq(is_aligned, UInt<1>(0h0)) when _T_160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_161 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_162 = asUInt(reset) node _T_163 = eq(_T_162, UInt<1>(0h0)) when _T_163 : node _T_164 = eq(_T_161, UInt<1>(0h0)) when _T_164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_161, UInt<1>(0h1), "") : assert_23 node _T_165 = eq(io.in.a.bits.mask, mask) node _T_166 = asUInt(reset) node _T_167 = eq(_T_166, UInt<1>(0h0)) when _T_167 : node _T_168 = eq(_T_165, UInt<1>(0h0)) when _T_168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_165, UInt<1>(0h1), "") : assert_24 node _T_169 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_169, UInt<1>(0h1), "") : assert_25 node _T_173 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_173 : node _T_174 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_175 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_176 = and(_T_174, _T_175) node _T_177 = or(UInt<1>(0h0), _T_176) node _T_178 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_179 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_180 = and(_T_178, _T_179) node _T_181 = or(UInt<1>(0h0), _T_180) node _T_182 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_183 = cvt(_T_182) node _T_184 = and(_T_183, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_185 = asSInt(_T_184) node _T_186 = eq(_T_185, asSInt(UInt<1>(0h0))) node _T_187 = and(_T_181, _T_186) node _T_188 = or(UInt<1>(0h0), _T_187) node _T_189 = and(_T_177, _T_188) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_189, UInt<1>(0h1), "") : assert_26 node _T_193 = asUInt(reset) node _T_194 = eq(_T_193, UInt<1>(0h0)) when _T_194 : node _T_195 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_195 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_196 = asUInt(reset) node _T_197 = eq(_T_196, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(is_aligned, UInt<1>(0h0)) when _T_198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_199 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_199, UInt<1>(0h1), "") : assert_29 node _T_203 = eq(io.in.a.bits.mask, mask) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_203, UInt<1>(0h1), "") : assert_30 node _T_207 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_207 : node _T_208 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_209 = and(UInt<1>(0h0), _T_208) node _T_210 = or(UInt<1>(0h0), _T_209) node _T_211 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_212 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_213 = and(_T_211, _T_212) node _T_214 = or(UInt<1>(0h0), _T_213) node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = and(_T_214, _T_219) node _T_221 = or(UInt<1>(0h0), _T_220) node _T_222 = and(_T_210, _T_221) node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_T_222, UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_222, UInt<1>(0h1), "") : assert_31 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_229 = asUInt(reset) node _T_230 = eq(_T_229, UInt<1>(0h0)) when _T_230 : node _T_231 = eq(is_aligned, UInt<1>(0h0)) when _T_231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_232 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_232, UInt<1>(0h1), "") : assert_34 node _T_236 = not(mask) node _T_237 = and(io.in.a.bits.mask, _T_236) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = asUInt(reset) node _T_240 = eq(_T_239, UInt<1>(0h0)) when _T_240 : node _T_241 = eq(_T_238, UInt<1>(0h0)) when _T_241 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_238, UInt<1>(0h1), "") : assert_35 node _T_242 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_242 : node _T_243 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_244 = and(UInt<1>(0h0), _T_243) node _T_245 = or(UInt<1>(0h0), _T_244) node _T_246 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_247 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_248 = cvt(_T_247) node _T_249 = and(_T_248, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_250 = asSInt(_T_249) node _T_251 = eq(_T_250, asSInt(UInt<1>(0h0))) node _T_252 = and(_T_246, _T_251) node _T_253 = or(UInt<1>(0h0), _T_252) node _T_254 = and(_T_245, _T_253) node _T_255 = asUInt(reset) node _T_256 = eq(_T_255, UInt<1>(0h0)) when _T_256 : node _T_257 = eq(_T_254, UInt<1>(0h0)) when _T_257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_254, UInt<1>(0h1), "") : assert_36 node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(is_aligned, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_264 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(_T_264, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_264, UInt<1>(0h1), "") : assert_39 node _T_268 = eq(io.in.a.bits.mask, mask) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_268, UInt<1>(0h1), "") : assert_40 node _T_272 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_272 : node _T_273 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_274 = and(UInt<1>(0h0), _T_273) node _T_275 = or(UInt<1>(0h0), _T_274) node _T_276 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_277 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = and(_T_276, _T_281) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = and(_T_275, _T_283) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_284, UInt<1>(0h1), "") : assert_41 node _T_288 = asUInt(reset) node _T_289 = eq(_T_288, UInt<1>(0h0)) when _T_289 : node _T_290 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_291 = asUInt(reset) node _T_292 = eq(_T_291, UInt<1>(0h0)) when _T_292 : node _T_293 = eq(is_aligned, UInt<1>(0h0)) when _T_293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_294 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_294, UInt<1>(0h1), "") : assert_44 node _T_298 = eq(io.in.a.bits.mask, mask) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_298, UInt<1>(0h1), "") : assert_45 node _T_302 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_302 : node _T_303 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_304 = and(UInt<1>(0h0), _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_307 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_308 = and(_T_306, _T_307) node _T_309 = or(UInt<1>(0h0), _T_308) node _T_310 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<129>(0h100000000000000000000000000000000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = and(_T_309, _T_314) node _T_316 = or(UInt<1>(0h0), _T_315) node _T_317 = and(_T_305, _T_316) node _T_318 = asUInt(reset) node _T_319 = eq(_T_318, UInt<1>(0h0)) when _T_319 : node _T_320 = eq(_T_317, UInt<1>(0h0)) when _T_320 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_317, UInt<1>(0h1), "") : assert_46 node _T_321 = asUInt(reset) node _T_322 = eq(_T_321, UInt<1>(0h0)) when _T_322 : node _T_323 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_323 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_324 = asUInt(reset) node _T_325 = eq(_T_324, UInt<1>(0h0)) when _T_325 : node _T_326 = eq(is_aligned, UInt<1>(0h0)) when _T_326 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_327 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_328 = asUInt(reset) node _T_329 = eq(_T_328, UInt<1>(0h0)) when _T_329 : node _T_330 = eq(_T_327, UInt<1>(0h0)) when _T_330 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_327, UInt<1>(0h1), "") : assert_49 node _T_331 = eq(io.in.a.bits.mask, mask) node _T_332 = asUInt(reset) node _T_333 = eq(_T_332, UInt<1>(0h0)) when _T_333 : node _T_334 = eq(_T_331, UInt<1>(0h0)) when _T_334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_331, UInt<1>(0h1), "") : assert_50 node _T_335 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_T_335, UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_335, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_339 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_340 = asUInt(reset) node _T_341 = eq(_T_340, UInt<1>(0h0)) when _T_341 : node _T_342 = eq(_T_339, UInt<1>(0h0)) when _T_342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_339, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h1)) node _T_343 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_343 : node _T_344 = asUInt(reset) node _T_345 = eq(_T_344, UInt<1>(0h0)) when _T_345 : node _T_346 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_347 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_348 = asUInt(reset) node _T_349 = eq(_T_348, UInt<1>(0h0)) when _T_349 : node _T_350 = eq(_T_347, UInt<1>(0h0)) when _T_350 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_347, UInt<1>(0h1), "") : assert_54 node _T_351 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_352 = asUInt(reset) node _T_353 = eq(_T_352, UInt<1>(0h0)) when _T_353 : node _T_354 = eq(_T_351, UInt<1>(0h0)) when _T_354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_351, UInt<1>(0h1), "") : assert_55 node _T_355 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_355, UInt<1>(0h1), "") : assert_56 node _T_359 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_359, UInt<1>(0h1), "") : assert_57 node _T_363 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_363 : node _T_364 = asUInt(reset) node _T_365 = eq(_T_364, UInt<1>(0h0)) when _T_365 : node _T_366 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_366 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(sink_ok, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_370 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(_T_370, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_370, UInt<1>(0h1), "") : assert_60 node _T_374 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_374, UInt<1>(0h1), "") : assert_61 node _T_378 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_378, UInt<1>(0h1), "") : assert_62 node _T_382 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_382, UInt<1>(0h1), "") : assert_63 node _T_386 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_387 = or(UInt<1>(0h1), _T_386) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_387, UInt<1>(0h1), "") : assert_64 node _T_391 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_391 : node _T_392 = asUInt(reset) node _T_393 = eq(_T_392, UInt<1>(0h0)) when _T_393 : node _T_394 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_394 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(sink_ok, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_398, UInt<1>(0h1), "") : assert_67 node _T_402 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_402, UInt<1>(0h1), "") : assert_68 node _T_406 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_406, UInt<1>(0h1), "") : assert_69 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = or(_T_410, io.in.d.bits.corrupt) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_411, UInt<1>(0h1), "") : assert_70 node _T_415 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_416 = or(UInt<1>(0h1), _T_415) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_416, UInt<1>(0h1), "") : assert_71 node _T_420 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_420 : node _T_421 = asUInt(reset) node _T_422 = eq(_T_421, UInt<1>(0h0)) when _T_422 : node _T_423 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_423 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_424 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_425 = asUInt(reset) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(_T_424, UInt<1>(0h0)) when _T_427 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_424, UInt<1>(0h1), "") : assert_73 node _T_428 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_429 = asUInt(reset) node _T_430 = eq(_T_429, UInt<1>(0h0)) when _T_430 : node _T_431 = eq(_T_428, UInt<1>(0h0)) when _T_431 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_428, UInt<1>(0h1), "") : assert_74 node _T_432 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_433 = or(UInt<1>(0h1), _T_432) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_433, UInt<1>(0h1), "") : assert_75 node _T_437 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_437 : node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_441 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_441, UInt<1>(0h1), "") : assert_77 node _T_445 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_446 = or(_T_445, io.in.d.bits.corrupt) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_446, UInt<1>(0h1), "") : assert_78 node _T_450 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_451 = or(UInt<1>(0h1), _T_450) node _T_452 = asUInt(reset) node _T_453 = eq(_T_452, UInt<1>(0h0)) when _T_453 : node _T_454 = eq(_T_451, UInt<1>(0h0)) when _T_454 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_451, UInt<1>(0h1), "") : assert_79 node _T_455 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_455 : node _T_456 = asUInt(reset) node _T_457 = eq(_T_456, UInt<1>(0h0)) when _T_457 : node _T_458 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_458 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_459 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_459, UInt<1>(0h1), "") : assert_81 node _T_463 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_464 = asUInt(reset) node _T_465 = eq(_T_464, UInt<1>(0h0)) when _T_465 : node _T_466 = eq(_T_463, UInt<1>(0h0)) when _T_466 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_463, UInt<1>(0h1), "") : assert_82 node _T_467 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_468 = or(UInt<1>(0h1), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_468, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<128>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<128>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_472 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_473 = asUInt(reset) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(_T_472, UInt<1>(0h0)) when _T_475 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_472, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<128>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_476 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_477 = asUInt(reset) node _T_478 = eq(_T_477, UInt<1>(0h0)) when _T_478 : node _T_479 = eq(_T_476, UInt<1>(0h0)) when _T_479 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_476, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_480 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_481 = asUInt(reset) node _T_482 = eq(_T_481, UInt<1>(0h0)) when _T_482 : node _T_483 = eq(_T_480, UInt<1>(0h0)) when _T_483 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_480, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_484 = eq(a_first, UInt<1>(0h0)) node _T_485 = and(io.in.a.valid, _T_484) when _T_485 : node _T_486 = eq(io.in.a.bits.opcode, opcode) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_486, UInt<1>(0h1), "") : assert_87 node _T_490 = eq(io.in.a.bits.param, param) node _T_491 = asUInt(reset) node _T_492 = eq(_T_491, UInt<1>(0h0)) when _T_492 : node _T_493 = eq(_T_490, UInt<1>(0h0)) when _T_493 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_490, UInt<1>(0h1), "") : assert_88 node _T_494 = eq(io.in.a.bits.size, size) node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(_T_494, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_494, UInt<1>(0h1), "") : assert_89 node _T_498 = eq(io.in.a.bits.source, source) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_498, UInt<1>(0h1), "") : assert_90 node _T_502 = eq(io.in.a.bits.address, address) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_502, UInt<1>(0h1), "") : assert_91 node _T_506 = and(io.in.a.ready, io.in.a.valid) node _T_507 = and(_T_506, a_first) when _T_507 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_508 = eq(d_first, UInt<1>(0h0)) node _T_509 = and(io.in.d.valid, _T_508) when _T_509 : node _T_510 = eq(io.in.d.bits.opcode, opcode_1) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_510, UInt<1>(0h1), "") : assert_92 node _T_514 = eq(io.in.d.bits.param, param_1) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_514, UInt<1>(0h1), "") : assert_93 node _T_518 = eq(io.in.d.bits.size, size_1) node _T_519 = asUInt(reset) node _T_520 = eq(_T_519, UInt<1>(0h0)) when _T_520 : node _T_521 = eq(_T_518, UInt<1>(0h0)) when _T_521 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_518, UInt<1>(0h1), "") : assert_94 node _T_522 = eq(io.in.d.bits.source, source_1) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_522, UInt<1>(0h1), "") : assert_95 node _T_526 = eq(io.in.d.bits.sink, sink) node _T_527 = asUInt(reset) node _T_528 = eq(_T_527, UInt<1>(0h0)) when _T_528 : node _T_529 = eq(_T_526, UInt<1>(0h0)) when _T_529 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_526, UInt<1>(0h1), "") : assert_96 node _T_530 = eq(io.in.d.bits.denied, denied) node _T_531 = asUInt(reset) node _T_532 = eq(_T_531, UInt<1>(0h0)) when _T_532 : node _T_533 = eq(_T_530, UInt<1>(0h0)) when _T_533 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_530, UInt<1>(0h1), "") : assert_97 node _T_534 = and(io.in.d.ready, io.in.d.valid) node _T_535 = and(_T_534, d_first) when _T_535 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_536 = and(io.in.a.valid, a_first_1) node _T_537 = and(_T_536, UInt<1>(0h1)) when _T_537 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_538 = and(io.in.a.ready, io.in.a.valid) node _T_539 = and(_T_538, a_first_1) node _T_540 = and(_T_539, UInt<1>(0h1)) when _T_540 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_541 = dshr(inflight, io.in.a.bits.source) node _T_542 = bits(_T_541, 0, 0) node _T_543 = eq(_T_542, UInt<1>(0h0)) node _T_544 = asUInt(reset) node _T_545 = eq(_T_544, UInt<1>(0h0)) when _T_545 : node _T_546 = eq(_T_543, UInt<1>(0h0)) when _T_546 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_543, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_547 = and(io.in.d.valid, d_first_1) node _T_548 = and(_T_547, UInt<1>(0h1)) node _T_549 = eq(d_release_ack, UInt<1>(0h0)) node _T_550 = and(_T_548, _T_549) when _T_550 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_551 = and(io.in.d.ready, io.in.d.valid) node _T_552 = and(_T_551, d_first_1) node _T_553 = and(_T_552, UInt<1>(0h1)) node _T_554 = eq(d_release_ack, UInt<1>(0h0)) node _T_555 = and(_T_553, _T_554) when _T_555 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_556 = and(io.in.d.valid, d_first_1) node _T_557 = and(_T_556, UInt<1>(0h1)) node _T_558 = eq(d_release_ack, UInt<1>(0h0)) node _T_559 = and(_T_557, _T_558) when _T_559 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_560 = dshr(inflight, io.in.d.bits.source) node _T_561 = bits(_T_560, 0, 0) node _T_562 = or(_T_561, same_cycle_resp) node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(_T_562, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_562, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_566 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_567 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_568 = or(_T_566, _T_567) node _T_569 = asUInt(reset) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(_T_568, UInt<1>(0h0)) when _T_571 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_568, UInt<1>(0h1), "") : assert_100 node _T_572 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_572, UInt<1>(0h1), "") : assert_101 else : node _T_576 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_577 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_578 = or(_T_576, _T_577) node _T_579 = asUInt(reset) node _T_580 = eq(_T_579, UInt<1>(0h0)) when _T_580 : node _T_581 = eq(_T_578, UInt<1>(0h0)) when _T_581 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_578, UInt<1>(0h1), "") : assert_102 node _T_582 = eq(io.in.d.bits.size, a_size_lookup) node _T_583 = asUInt(reset) node _T_584 = eq(_T_583, UInt<1>(0h0)) when _T_584 : node _T_585 = eq(_T_582, UInt<1>(0h0)) when _T_585 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_582, UInt<1>(0h1), "") : assert_103 node _T_586 = and(io.in.d.valid, d_first_1) node _T_587 = and(_T_586, a_first_1) node _T_588 = and(_T_587, io.in.a.valid) node _T_589 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_590 = and(_T_588, _T_589) node _T_591 = eq(d_release_ack, UInt<1>(0h0)) node _T_592 = and(_T_590, _T_591) when _T_592 : node _T_593 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_594 = or(_T_593, io.in.a.ready) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_594, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_102 node _T_598 = orr(inflight) node _T_599 = eq(_T_598, UInt<1>(0h0)) node _T_600 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_601 = or(_T_599, _T_600) node _T_602 = lt(watchdog, plusarg_reader.out) node _T_603 = or(_T_601, _T_602) node _T_604 = asUInt(reset) node _T_605 = eq(_T_604, UInt<1>(0h0)) when _T_605 : node _T_606 = eq(_T_603, UInt<1>(0h0)) when _T_606 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_603, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_607 = and(io.in.a.ready, io.in.a.valid) node _T_608 = and(io.in.d.ready, io.in.d.valid) node _T_609 = or(_T_607, _T_608) when _T_609 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<128>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<128>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<128>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_610 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<128>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_611 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_612 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_613 = and(_T_611, _T_612) node _T_614 = and(_T_610, _T_613) when _T_614 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<128>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_615 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_616 = and(_T_615, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<128>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_617 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_618 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_619 = and(_T_617, _T_618) node _T_620 = and(_T_616, _T_619) when _T_620 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<128>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<128>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_621 = dshr(inflight_1, _WIRE_15.bits.source) node _T_622 = bits(_T_621, 0, 0) node _T_623 = eq(_T_622, UInt<1>(0h0)) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_623, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_627 = and(io.in.d.valid, d_first_2) node _T_628 = and(_T_627, UInt<1>(0h1)) node _T_629 = and(_T_628, d_release_ack_1) when _T_629 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_630 = and(io.in.d.ready, io.in.d.valid) node _T_631 = and(_T_630, d_first_2) node _T_632 = and(_T_631, UInt<1>(0h1)) node _T_633 = and(_T_632, d_release_ack_1) when _T_633 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_634 = and(io.in.d.valid, d_first_2) node _T_635 = and(_T_634, UInt<1>(0h1)) node _T_636 = and(_T_635, d_release_ack_1) when _T_636 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_637 = dshr(inflight_1, io.in.d.bits.source) node _T_638 = bits(_T_637, 0, 0) node _T_639 = or(_T_638, same_cycle_resp_1) node _T_640 = asUInt(reset) node _T_641 = eq(_T_640, UInt<1>(0h0)) when _T_641 : node _T_642 = eq(_T_639, UInt<1>(0h0)) when _T_642 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_639, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<128>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_643 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(_T_643, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_643, UInt<1>(0h1), "") : assert_108 else : node _T_647 = eq(io.in.d.bits.size, c_size_lookup) node _T_648 = asUInt(reset) node _T_649 = eq(_T_648, UInt<1>(0h0)) when _T_649 : node _T_650 = eq(_T_647, UInt<1>(0h0)) when _T_650 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_647, UInt<1>(0h1), "") : assert_109 node _T_651 = and(io.in.d.valid, d_first_2) node _T_652 = and(_T_651, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<128>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_653 = and(_T_652, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<128>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_654 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_655 = and(_T_653, _T_654) node _T_656 = and(_T_655, d_release_ack_1) node _T_657 = eq(c_probe_ack, UInt<1>(0h0)) node _T_658 = and(_T_656, _T_657) when _T_658 : node _T_659 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<128>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_660 = or(_T_659, _WIRE_23.ready) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_660, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_103 node _T_664 = orr(inflight_1) node _T_665 = eq(_T_664, UInt<1>(0h0)) node _T_666 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_667 = or(_T_665, _T_666) node _T_668 = lt(watchdog_1, plusarg_reader_1.out) node _T_669 = or(_T_667, _T_668) node _T_670 = asUInt(reset) node _T_671 = eq(_T_670, UInt<1>(0h0)) when _T_671 : node _T_672 = eq(_T_669, UInt<1>(0h0)) when _T_672 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/tilelink/BusBypass.scala:33:14)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_669, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<128>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<128>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_673 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_674 = and(io.in.d.ready, io.in.d.valid) node _T_675 = or(_T_673, _T_674) when _T_675 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_51( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] io_in_d_bits_data = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_wo_ready_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_address = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_address = 128'h0; // @[Bundles.scala:265:61] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [127:0] _is_aligned_T = {126'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 128'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_607 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_607; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_607; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [127:0] address; // @[Monitor.scala:391:22] wire _T_675 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_675; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_675; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire [4:0] _GEN = 5'h3 << io_in_d_bits_size_0; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN; // @[package.scala:243:71] wire [1:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [1:0] size_1; // @[Monitor.scala:540:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_537 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_537; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_537; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_607 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_0 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_0; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_0; // @[Monitor.scala:673:46, :783:46] wire _T_586 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_586 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_675 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_1; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_1; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] wire [1:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[1:0]; // @[package.scala:243:{71,76}] wire [1:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_651 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_651 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_675 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_2 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_2; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_28 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_28( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw = io_x_pw_0; // @[package.scala:267:30] wire io_y_px = io_x_px_0; // @[package.scala:267:30] wire io_y_pr = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff = io_x_eff_0; // @[package.scala:267:30] wire io_y_c = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_31 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_31( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_92 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}, flip out_credit_available : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<5>, flip vc_free : UInt<5>}} inst input_buffer of InputBuffer_92 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) inst route_arbiter of Arbiter5_RouteComputerReq_20 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<5>}[5], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<3>(0h5)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0hd)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_9 : connect states[1].g, UInt<3>(0h2) connect route_arbiter.io.in[2].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[2].bits.flow.egress_node_id invalidate route_arbiter.io.in[2].bits.flow.egress_node invalidate route_arbiter.io.in[2].bits.flow.ingress_node_id invalidate route_arbiter.io.in[2].bits.flow.ingress_node invalidate route_arbiter.io.in[2].bits.flow.vnet_id invalidate route_arbiter.io.in[2].bits.src_virt_id connect route_arbiter.io.in[3].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[3].bits.flow.egress_node_id invalidate route_arbiter.io.in[3].bits.flow.egress_node invalidate route_arbiter.io.in[3].bits.flow.ingress_node_id invalidate route_arbiter.io.in[3].bits.flow.ingress_node invalidate route_arbiter.io.in[3].bits.flow.vnet_id invalidate route_arbiter.io.in[3].bits.src_virt_id connect route_arbiter.io.in[4].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[4].bits.flow.egress_node_id invalidate route_arbiter.io.in[4].bits.flow.egress_node invalidate route_arbiter.io.in[4].bits.flow.ingress_node_id invalidate route_arbiter.io.in[4].bits.flow.ingress_node invalidate route_arbiter.io.in[4].bits.flow.vnet_id invalidate route_arbiter.io.in[4].bits.src_virt_id node _T_10 = and(io.router_req.ready, io.router_req.valid) when _T_10 : node _T_11 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_15 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_15 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_16 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_16 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_17 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_17 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_18 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_18 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_19 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_19 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` regreset mask : UInt<5>, clock, reset, UInt<5>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}}[5] wire vcalloc_vals : UInt<1>[5] node vcalloc_filter_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_vals[2]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[4], vcalloc_vals[3]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_vals[2]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_14, UInt<10>(0h200), UInt<10>(0h0)) node _vcalloc_filter_T_16 = mux(_vcalloc_filter_T_13, UInt<10>(0h100), _vcalloc_filter_T_15) node _vcalloc_filter_T_17 = mux(_vcalloc_filter_T_12, UInt<10>(0h80), _vcalloc_filter_T_16) node _vcalloc_filter_T_18 = mux(_vcalloc_filter_T_11, UInt<10>(0h40), _vcalloc_filter_T_17) node _vcalloc_filter_T_19 = mux(_vcalloc_filter_T_10, UInt<10>(0h20), _vcalloc_filter_T_18) node _vcalloc_filter_T_20 = mux(_vcalloc_filter_T_9, UInt<10>(0h10), _vcalloc_filter_T_19) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_8, UInt<10>(0h8), _vcalloc_filter_T_20) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_7, UInt<10>(0h4), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_6, UInt<10>(0h2), _vcalloc_filter_T_22) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<10>(0h1), _vcalloc_filter_T_23) node _vcalloc_sel_T = bits(vcalloc_filter, 4, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 5) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_20 = and(io.router_req.ready, io.router_req.valid) when _T_20 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_21 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_22 = or(_T_21, vcalloc_vals[2]) node _T_23 = or(_T_22, vcalloc_vals[3]) node _T_24 = or(_T_23, vcalloc_vals[4]) when _T_24 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = bits(vcalloc_sel, 0, 0) node _mask_T_9 = bits(vcalloc_sel, 1, 1) node _mask_T_10 = bits(vcalloc_sel, 2, 2) node _mask_T_11 = bits(vcalloc_sel, 3, 3) node _mask_T_12 = bits(vcalloc_sel, 4, 4) node _mask_T_13 = mux(_mask_T_8, _mask_T_3, UInt<1>(0h0)) node _mask_T_14 = mux(_mask_T_9, _mask_T_4, UInt<1>(0h0)) node _mask_T_15 = mux(_mask_T_10, _mask_T_5, UInt<1>(0h0)) node _mask_T_16 = mux(_mask_T_11, _mask_T_6, UInt<1>(0h0)) node _mask_T_17 = mux(_mask_T_12, _mask_T_7, UInt<1>(0h0)) node _mask_T_18 = or(_mask_T_13, _mask_T_14) node _mask_T_19 = or(_mask_T_18, _mask_T_15) node _mask_T_20 = or(_mask_T_19, _mask_T_16) node _mask_T_21 = or(_mask_T_20, _mask_T_17) wire _mask_WIRE : UInt<5> connect _mask_WIRE, _mask_T_21 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_3 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]}} wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[5] node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_7 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = or(_io_vcalloc_req_bits_T_5, _io_vcalloc_req_bits_T_6) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_10, _io_vcalloc_req_bits_T_7) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_8) node _io_vcalloc_req_bits_T_13 = or(_io_vcalloc_req_bits_T_12, _io_vcalloc_req_bits_T_9) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_13 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_17 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_14, _io_vcalloc_req_bits_T_15) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_16) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_17) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_18) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_29 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_30 = or(_io_vcalloc_req_bits_T_29, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_30, _io_vcalloc_req_bits_T_27) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_31 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_32 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_33) node _io_vcalloc_req_bits_T_38 = or(_io_vcalloc_req_bits_T_37, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_39 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_35) node _io_vcalloc_req_bits_T_40 = or(_io_vcalloc_req_bits_T_39, _io_vcalloc_req_bits_T_36) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_40 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_49 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_8 : UInt<1>[5] node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_52 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_51) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_55, _io_vcalloc_req_bits_T_52) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_53) node _io_vcalloc_req_bits_T_58 = or(_io_vcalloc_req_bits_T_57, _io_vcalloc_req_bits_T_54) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_58 connect _io_vcalloc_req_bits_WIRE_8[0], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_62 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_59, _io_vcalloc_req_bits_T_60) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_61) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_62) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_63) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_8[1], _io_vcalloc_req_bits_WIRE_10 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_74 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_75 = or(_io_vcalloc_req_bits_T_74, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_75, _io_vcalloc_req_bits_T_72) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_76 connect _io_vcalloc_req_bits_WIRE_8[2], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_77 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_78) node _io_vcalloc_req_bits_T_83 = or(_io_vcalloc_req_bits_T_82, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_84 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_80) node _io_vcalloc_req_bits_T_85 = or(_io_vcalloc_req_bits_T_84, _io_vcalloc_req_bits_T_81) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_85 connect _io_vcalloc_req_bits_WIRE_8[3], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_94 connect _io_vcalloc_req_bits_WIRE_8[4], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_8 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[5] node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_97 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_96) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_100, _io_vcalloc_req_bits_T_97) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_98) node _io_vcalloc_req_bits_T_103 = or(_io_vcalloc_req_bits_T_102, _io_vcalloc_req_bits_T_99) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_103 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_107 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_108 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_104, _io_vcalloc_req_bits_T_105) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_106) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_107) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_108) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_14[1], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_119 = or(_io_vcalloc_req_bits_T_118, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_120 = or(_io_vcalloc_req_bits_T_119, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_120, _io_vcalloc_req_bits_T_117) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_121 connect _io_vcalloc_req_bits_WIRE_14[2], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_122 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_123 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_124 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_125 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_126 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_123) node _io_vcalloc_req_bits_T_128 = or(_io_vcalloc_req_bits_T_127, _io_vcalloc_req_bits_T_124) node _io_vcalloc_req_bits_T_129 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_125) node _io_vcalloc_req_bits_T_130 = or(_io_vcalloc_req_bits_T_129, _io_vcalloc_req_bits_T_126) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_130 connect _io_vcalloc_req_bits_WIRE_14[3], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_131, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_139 connect _io_vcalloc_req_bits_WIRE_14[4], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_14 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_140 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_141 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_142 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_141) node _io_vcalloc_req_bits_T_146 = or(_io_vcalloc_req_bits_T_145, _io_vcalloc_req_bits_T_142) node _io_vcalloc_req_bits_T_147 = or(_io_vcalloc_req_bits_T_146, _io_vcalloc_req_bits_T_143) node _io_vcalloc_req_bits_T_148 = or(_io_vcalloc_req_bits_T_147, _io_vcalloc_req_bits_T_144) wire _io_vcalloc_req_bits_WIRE_20 : UInt<3> connect _io_vcalloc_req_bits_WIRE_20, _io_vcalloc_req_bits_T_148 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_20 wire _io_vcalloc_req_bits_WIRE_21 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_152 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_153 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_149, _io_vcalloc_req_bits_T_150) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_151) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_152) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_153) wire _io_vcalloc_req_bits_WIRE_22 : UInt<2> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_21.egress_node_id, _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_164 = or(_io_vcalloc_req_bits_T_163, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_165 = or(_io_vcalloc_req_bits_T_164, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_165, _io_vcalloc_req_bits_T_162) wire _io_vcalloc_req_bits_WIRE_23 : UInt<5> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_166 connect _io_vcalloc_req_bits_WIRE_21.egress_node, _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_167 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_168 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_169 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_170 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_171 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_168) node _io_vcalloc_req_bits_T_173 = or(_io_vcalloc_req_bits_T_172, _io_vcalloc_req_bits_T_169) node _io_vcalloc_req_bits_T_174 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_170) node _io_vcalloc_req_bits_T_175 = or(_io_vcalloc_req_bits_T_174, _io_vcalloc_req_bits_T_171) wire _io_vcalloc_req_bits_WIRE_24 : UInt<2> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_175 connect _io_vcalloc_req_bits_WIRE_21.ingress_node_id, _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_176, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_25 : UInt<5> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_184 connect _io_vcalloc_req_bits_WIRE_21.ingress_node, _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_185 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_186 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_187 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_186) node _io_vcalloc_req_bits_T_191 = or(_io_vcalloc_req_bits_T_190, _io_vcalloc_req_bits_T_187) node _io_vcalloc_req_bits_T_192 = or(_io_vcalloc_req_bits_T_191, _io_vcalloc_req_bits_T_188) node _io_vcalloc_req_bits_T_193 = or(_io_vcalloc_req_bits_T_192, _io_vcalloc_req_bits_T_189) wire _io_vcalloc_req_bits_WIRE_26 : UInt<3> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_193 connect _io_vcalloc_req_bits_WIRE_21.vnet_id, _io_vcalloc_req_bits_WIRE_26 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_21 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].flow, states[1].flow node _T_25 = bits(vcalloc_sel, 1, 1) node _T_26 = and(vcalloc_vals[1], _T_25) node _T_27 = and(_T_26, io.vcalloc_req.ready) when _T_27 : connect states[1].g, UInt<3>(0h3) connect vcalloc_vals[2], UInt<1>(0h0) invalidate vcalloc_reqs[2].vc_sel.`0`[0] invalidate vcalloc_reqs[2].vc_sel.`0`[1] invalidate vcalloc_reqs[2].vc_sel.`0`[2] invalidate vcalloc_reqs[2].vc_sel.`0`[3] invalidate vcalloc_reqs[2].vc_sel.`0`[4] invalidate vcalloc_reqs[2].vc_sel.`1`[0] invalidate vcalloc_reqs[2].vc_sel.`1`[1] invalidate vcalloc_reqs[2].vc_sel.`1`[2] invalidate vcalloc_reqs[2].vc_sel.`1`[3] invalidate vcalloc_reqs[2].vc_sel.`1`[4] invalidate vcalloc_reqs[2].vc_sel.`2`[0] invalidate vcalloc_reqs[2].vc_sel.`2`[1] invalidate vcalloc_reqs[2].vc_sel.`2`[2] invalidate vcalloc_reqs[2].vc_sel.`2`[3] invalidate vcalloc_reqs[2].vc_sel.`2`[4] invalidate vcalloc_reqs[2].in_vc invalidate vcalloc_reqs[2].flow.egress_node_id invalidate vcalloc_reqs[2].flow.egress_node invalidate vcalloc_reqs[2].flow.ingress_node_id invalidate vcalloc_reqs[2].flow.ingress_node invalidate vcalloc_reqs[2].flow.vnet_id connect vcalloc_vals[3], UInt<1>(0h0) invalidate vcalloc_reqs[3].vc_sel.`0`[0] invalidate vcalloc_reqs[3].vc_sel.`0`[1] invalidate vcalloc_reqs[3].vc_sel.`0`[2] invalidate vcalloc_reqs[3].vc_sel.`0`[3] invalidate vcalloc_reqs[3].vc_sel.`0`[4] invalidate vcalloc_reqs[3].vc_sel.`1`[0] invalidate vcalloc_reqs[3].vc_sel.`1`[1] invalidate vcalloc_reqs[3].vc_sel.`1`[2] invalidate vcalloc_reqs[3].vc_sel.`1`[3] invalidate vcalloc_reqs[3].vc_sel.`1`[4] invalidate vcalloc_reqs[3].vc_sel.`2`[0] invalidate vcalloc_reqs[3].vc_sel.`2`[1] invalidate vcalloc_reqs[3].vc_sel.`2`[2] invalidate vcalloc_reqs[3].vc_sel.`2`[3] invalidate vcalloc_reqs[3].vc_sel.`2`[4] invalidate vcalloc_reqs[3].in_vc invalidate vcalloc_reqs[3].flow.egress_node_id invalidate vcalloc_reqs[3].flow.egress_node invalidate vcalloc_reqs[3].flow.ingress_node_id invalidate vcalloc_reqs[3].flow.ingress_node invalidate vcalloc_reqs[3].flow.vnet_id connect vcalloc_vals[4], UInt<1>(0h0) invalidate vcalloc_reqs[4].vc_sel.`0`[0] invalidate vcalloc_reqs[4].vc_sel.`0`[1] invalidate vcalloc_reqs[4].vc_sel.`0`[2] invalidate vcalloc_reqs[4].vc_sel.`0`[3] invalidate vcalloc_reqs[4].vc_sel.`0`[4] invalidate vcalloc_reqs[4].vc_sel.`1`[0] invalidate vcalloc_reqs[4].vc_sel.`1`[1] invalidate vcalloc_reqs[4].vc_sel.`1`[2] invalidate vcalloc_reqs[4].vc_sel.`1`[3] invalidate vcalloc_reqs[4].vc_sel.`1`[4] invalidate vcalloc_reqs[4].vc_sel.`2`[0] invalidate vcalloc_reqs[4].vc_sel.`2`[1] invalidate vcalloc_reqs[4].vc_sel.`2`[2] invalidate vcalloc_reqs[4].vc_sel.`2`[3] invalidate vcalloc_reqs[4].vc_sel.`2`[4] invalidate vcalloc_reqs[4].in_vc invalidate vcalloc_reqs[4].flow.egress_node_id invalidate vcalloc_reqs[4].flow.egress_node invalidate vcalloc_reqs[4].flow.ingress_node_id invalidate vcalloc_reqs[4].flow.ingress_node invalidate vcalloc_reqs[4].flow.vnet_id node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[3], vcalloc_vals[4]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(vcalloc_vals[2], _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 1, 0) node _io_debug_va_stall_T_6 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_5) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 2, 0) node _io_debug_va_stall_T_8 = sub(_io_debug_va_stall_T_7, io.vcalloc_req.ready) node _io_debug_va_stall_T_9 = tail(_io_debug_va_stall_T_8, 1) connect io.debug.va_stall, _io_debug_va_stall_T_9 node _T_28 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_28 : node _T_29 = bits(vcalloc_sel, 0, 0) when _T_29 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].g, UInt<3>(0h3) node _T_30 = eq(states[0].g, UInt<3>(0h2)) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_30, UInt<1>(0h1), "") : assert_3 node _T_34 = bits(vcalloc_sel, 1, 1) when _T_34 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].g, UInt<3>(0h3) node _T_35 = eq(states[1].g, UInt<3>(0h2)) node _T_36 = asUInt(reset) node _T_37 = eq(_T_36, UInt<1>(0h0)) when _T_37 : node _T_38 = eq(_T_35, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_35, UInt<1>(0h1), "") : assert_4 node _T_39 = bits(vcalloc_sel, 2, 2) when _T_39 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].g, UInt<3>(0h3) node _T_40 = eq(states[2].g, UInt<3>(0h2)) node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : node _T_43 = eq(_T_40, UInt<1>(0h0)) when _T_43 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_40, UInt<1>(0h1), "") : assert_5 node _T_44 = bits(vcalloc_sel, 3, 3) when _T_44 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].g, UInt<3>(0h3) node _T_45 = eq(states[3].g, UInt<3>(0h2)) node _T_46 = asUInt(reset) node _T_47 = eq(_T_46, UInt<1>(0h0)) when _T_47 : node _T_48 = eq(_T_45, UInt<1>(0h0)) when _T_48 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_45, UInt<1>(0h1), "") : assert_6 node _T_49 = bits(vcalloc_sel, 4, 4) when _T_49 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].g, UInt<3>(0h3) node _T_50 = eq(states[4].g, UInt<3>(0h2)) node _T_51 = asUInt(reset) node _T_52 = eq(_T_51, UInt<1>(0h0)) when _T_52 : node _T_53 = eq(_T_50, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_50, UInt<1>(0h1), "") : assert_7 inst salloc_arb of SwitchArbiter_243 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] node credit_available_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_hi_hi = cat(states[1].vc_sel.`0`[4], states[1].vc_sel.`0`[3]) node credit_available_hi = cat(credit_available_hi_hi, states[1].vc_sel.`0`[2]) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[4], states[1].vc_sel.`1`[3]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, states[1].vc_sel.`1`[2]) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`2`[4], states[1].vc_sel.`2`[3]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, states[1].vc_sel.`2`[2]) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1) node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T) node credit_available_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[4], io.out_credit_available.`0`[3]) node credit_available_hi_4 = cat(credit_available_hi_hi_3, io.out_credit_available.`0`[2]) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3) node credit_available_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_hi_hi_4 = cat(io.out_credit_available.`1`[4], io.out_credit_available.`1`[3]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, io.out_credit_available.`1`[2]) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4) node credit_available_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`2`[4], io.out_credit_available.`2`[3]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, io.out_credit_available.`2`[2]) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5) node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5) node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_54 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_55 = and(_T_54, input_buffer.io.deq[1].bits.tail) when _T_55 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready connect salloc_arb.io.in[2].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[2].bits.tail invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[2].bits.vc_sel.`2`[4] connect salloc_arb.io.in[3].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[3].bits.tail invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[3].bits.vc_sel.`2`[4] connect salloc_arb.io.in[4].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[4].bits.tail invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[4].bits.vc_sel.`2`[4] node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_11 = bits(_io_debug_sa_stall_T_10, 1, 0) node _io_debug_sa_stall_T_12 = add(_io_debug_sa_stall_T_7, _io_debug_sa_stall_T_9) node _io_debug_sa_stall_T_13 = bits(_io_debug_sa_stall_T_12, 1, 0) node _io_debug_sa_stall_T_14 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_13) node _io_debug_sa_stall_T_15 = bits(_io_debug_sa_stall_T_14, 1, 0) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_11, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 2, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_17 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_8 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = or(_io_in_vc_free_T_6, _io_in_vc_free_T_7) node _io_in_vc_free_T_12 = or(_io_in_vc_free_T_11, _io_in_vc_free_T_8) node _io_in_vc_free_T_13 = or(_io_in_vc_free_T_12, _io_in_vc_free_T_9) node _io_in_vc_free_T_14 = or(_io_in_vc_free_T_13, _io_in_vc_free_T_10) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_14 node _io_in_vc_free_T_15 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_15, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_16 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 4, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire vc_sel : { `2` : UInt<1>[5], `1` : UInt<1>[5], `0` : UInt<1>[5]} wire _vc_sel_WIRE : UInt<1>[5] node _vc_sel_T_5 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_7 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_8 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = or(_vc_sel_T_5, _vc_sel_T_6) node _vc_sel_T_11 = or(_vc_sel_T_10, _vc_sel_T_7) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_8) node _vc_sel_T_13 = or(_vc_sel_T_12, _vc_sel_T_9) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_13 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_14 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_16 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_17 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_18 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_19 = or(_vc_sel_T_14, _vc_sel_T_15) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_16) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_17) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_18) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_22 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_28 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_29 = or(_vc_sel_T_28, _vc_sel_T_25) node _vc_sel_T_30 = or(_vc_sel_T_29, _vc_sel_T_26) node _vc_sel_T_31 = or(_vc_sel_T_30, _vc_sel_T_27) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_31 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_32 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_33 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_36 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_37 = or(_vc_sel_T_32, _vc_sel_T_33) node _vc_sel_T_38 = or(_vc_sel_T_37, _vc_sel_T_34) node _vc_sel_T_39 = or(_vc_sel_T_38, _vc_sel_T_35) node _vc_sel_T_40 = or(_vc_sel_T_39, _vc_sel_T_36) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_40 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_41 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_41, _vc_sel_T_42) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_43) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_44) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_45) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_49 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_6 : UInt<1>[5] node _vc_sel_T_50 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_51 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_52 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_53 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_55 = or(_vc_sel_T_50, _vc_sel_T_51) node _vc_sel_T_56 = or(_vc_sel_T_55, _vc_sel_T_52) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_53) node _vc_sel_T_58 = or(_vc_sel_T_57, _vc_sel_T_54) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_58 connect _vc_sel_WIRE_6[0], _vc_sel_WIRE_7 node _vc_sel_T_59 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_61 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_62 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_63 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_64 = or(_vc_sel_T_59, _vc_sel_T_60) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_61) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_62) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_63) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_67 connect _vc_sel_WIRE_6[1], _vc_sel_WIRE_8 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_73 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_74 = or(_vc_sel_T_73, _vc_sel_T_70) node _vc_sel_T_75 = or(_vc_sel_T_74, _vc_sel_T_71) node _vc_sel_T_76 = or(_vc_sel_T_75, _vc_sel_T_72) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_76 connect _vc_sel_WIRE_6[2], _vc_sel_WIRE_9 node _vc_sel_T_77 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_78 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_79 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_80 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_81 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_82 = or(_vc_sel_T_77, _vc_sel_T_78) node _vc_sel_T_83 = or(_vc_sel_T_82, _vc_sel_T_79) node _vc_sel_T_84 = or(_vc_sel_T_83, _vc_sel_T_80) node _vc_sel_T_85 = or(_vc_sel_T_84, _vc_sel_T_81) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_85 connect _vc_sel_WIRE_6[3], _vc_sel_WIRE_10 node _vc_sel_T_86 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_86, _vc_sel_T_87) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_88) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_89) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_90) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_94 connect _vc_sel_WIRE_6[4], _vc_sel_WIRE_11 connect vc_sel.`1`, _vc_sel_WIRE_6 wire _vc_sel_WIRE_12 : UInt<1>[5] node _vc_sel_T_95 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_96 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_97 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_98 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_100 = or(_vc_sel_T_95, _vc_sel_T_96) node _vc_sel_T_101 = or(_vc_sel_T_100, _vc_sel_T_97) node _vc_sel_T_102 = or(_vc_sel_T_101, _vc_sel_T_98) node _vc_sel_T_103 = or(_vc_sel_T_102, _vc_sel_T_99) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_103 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 node _vc_sel_T_104 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_106 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_107 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_108 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_109 = or(_vc_sel_T_104, _vc_sel_T_105) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_106) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_107) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_108) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_112 connect _vc_sel_WIRE_12[1], _vc_sel_WIRE_14 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_118 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_119 = or(_vc_sel_T_118, _vc_sel_T_115) node _vc_sel_T_120 = or(_vc_sel_T_119, _vc_sel_T_116) node _vc_sel_T_121 = or(_vc_sel_T_120, _vc_sel_T_117) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_121 connect _vc_sel_WIRE_12[2], _vc_sel_WIRE_15 node _vc_sel_T_122 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_123 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_124 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_125 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_126 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_127 = or(_vc_sel_T_122, _vc_sel_T_123) node _vc_sel_T_128 = or(_vc_sel_T_127, _vc_sel_T_124) node _vc_sel_T_129 = or(_vc_sel_T_128, _vc_sel_T_125) node _vc_sel_T_130 = or(_vc_sel_T_129, _vc_sel_T_126) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_130 connect _vc_sel_WIRE_12[3], _vc_sel_WIRE_16 node _vc_sel_T_131 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_131, _vc_sel_T_132) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_133) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_134) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_135) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_139 connect _vc_sel_WIRE_12[4], _vc_sel_WIRE_17 connect vc_sel.`2`, _vc_sel_WIRE_12 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node channel_oh_0 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_3 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`1`[2]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`1`[3]) node channel_oh_1 = or(_channel_oh_T_5, vc_sel.`1`[4]) node _channel_oh_T_6 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`2`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`2`[3]) node channel_oh_2 = or(_channel_oh_T_8, vc_sel.`2`[4]) node virt_channel_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_hi_hi = cat(vc_sel.`0`[4], vc_sel.`0`[3]) node virt_channel_hi = cat(virt_channel_hi_hi, vc_sel.`0`[2]) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 4, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_3 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[4], vc_sel.`1`[3]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, vc_sel.`1`[2]) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 4, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_6 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[4], vc_sel.`2`[3]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, vc_sel.`2`[2]) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 4, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node _virt_channel_T_24 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_25 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_26 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_27 = or(_virt_channel_T_24, _virt_channel_T_25) node _virt_channel_T_28 = or(_virt_channel_T_27, _virt_channel_T_26) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_28 node _T_56 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_56 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_7 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = or(_salloc_outs_0_flit_payload_T_5, _salloc_outs_0_flit_payload_T_6) node _salloc_outs_0_flit_payload_T_11 = or(_salloc_outs_0_flit_payload_T_10, _salloc_outs_0_flit_payload_T_7) node _salloc_outs_0_flit_payload_T_12 = or(_salloc_outs_0_flit_payload_T_11, _salloc_outs_0_flit_payload_T_8) node _salloc_outs_0_flit_payload_T_13 = or(_salloc_outs_0_flit_payload_T_12, _salloc_outs_0_flit_payload_T_9) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_13 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_7 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = or(_salloc_outs_0_flit_head_T_5, _salloc_outs_0_flit_head_T_6) node _salloc_outs_0_flit_head_T_11 = or(_salloc_outs_0_flit_head_T_10, _salloc_outs_0_flit_head_T_7) node _salloc_outs_0_flit_head_T_12 = or(_salloc_outs_0_flit_head_T_11, _salloc_outs_0_flit_head_T_8) node _salloc_outs_0_flit_head_T_13 = or(_salloc_outs_0_flit_head_T_12, _salloc_outs_0_flit_head_T_9) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_13 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_7 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = or(_salloc_outs_0_flit_tail_T_5, _salloc_outs_0_flit_tail_T_6) node _salloc_outs_0_flit_tail_T_11 = or(_salloc_outs_0_flit_tail_T_10, _salloc_outs_0_flit_tail_T_7) node _salloc_outs_0_flit_tail_T_12 = or(_salloc_outs_0_flit_tail_T_11, _salloc_outs_0_flit_tail_T_8) node _salloc_outs_0_flit_tail_T_13 = or(_salloc_outs_0_flit_tail_T_12, _salloc_outs_0_flit_tail_T_9) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_13 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_7 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = or(_salloc_outs_0_flit_flow_T_5, _salloc_outs_0_flit_flow_T_6) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_10, _salloc_outs_0_flit_flow_T_7) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_8) node _salloc_outs_0_flit_flow_T_13 = or(_salloc_outs_0_flit_flow_T_12, _salloc_outs_0_flit_flow_T_9) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_13 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_17 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_14, _salloc_outs_0_flit_flow_T_15) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_16) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_17) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_18) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_29 = or(_salloc_outs_0_flit_flow_T_28, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_30 = or(_salloc_outs_0_flit_flow_T_29, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_30, _salloc_outs_0_flit_flow_T_27) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_31 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_32 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_33 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_34 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_35 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_36 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_33) node _salloc_outs_0_flit_flow_T_38 = or(_salloc_outs_0_flit_flow_T_37, _salloc_outs_0_flit_flow_T_34) node _salloc_outs_0_flit_flow_T_39 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_35) node _salloc_outs_0_flit_flow_T_40 = or(_salloc_outs_0_flit_flow_T_39, _salloc_outs_0_flit_flow_T_36) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_40 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_41, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_49 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[1], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[3], UInt<1>(0h0) connect states[1].vc_sel.`0`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[3], UInt<1>(0h0) connect states[1].vc_sel.`2`[4], UInt<1>(0h0) invalidate states[2].fifo_deps invalidate states[2].flow.egress_node_id invalidate states[2].flow.egress_node invalidate states[2].flow.ingress_node_id invalidate states[2].flow.ingress_node invalidate states[2].flow.vnet_id invalidate states[2].vc_sel.`0`[0] invalidate states[2].vc_sel.`0`[1] invalidate states[2].vc_sel.`0`[2] invalidate states[2].vc_sel.`0`[3] invalidate states[2].vc_sel.`0`[4] invalidate states[2].vc_sel.`1`[0] invalidate states[2].vc_sel.`1`[1] invalidate states[2].vc_sel.`1`[2] invalidate states[2].vc_sel.`1`[3] invalidate states[2].vc_sel.`1`[4] invalidate states[2].vc_sel.`2`[0] invalidate states[2].vc_sel.`2`[1] invalidate states[2].vc_sel.`2`[2] invalidate states[2].vc_sel.`2`[3] invalidate states[2].vc_sel.`2`[4] invalidate states[2].g invalidate states[3].fifo_deps invalidate states[3].flow.egress_node_id invalidate states[3].flow.egress_node invalidate states[3].flow.ingress_node_id invalidate states[3].flow.ingress_node invalidate states[3].flow.vnet_id invalidate states[3].vc_sel.`0`[0] invalidate states[3].vc_sel.`0`[1] invalidate states[3].vc_sel.`0`[2] invalidate states[3].vc_sel.`0`[3] invalidate states[3].vc_sel.`0`[4] invalidate states[3].vc_sel.`1`[0] invalidate states[3].vc_sel.`1`[1] invalidate states[3].vc_sel.`1`[2] invalidate states[3].vc_sel.`1`[3] invalidate states[3].vc_sel.`1`[4] invalidate states[3].vc_sel.`2`[0] invalidate states[3].vc_sel.`2`[1] invalidate states[3].vc_sel.`2`[2] invalidate states[3].vc_sel.`2`[3] invalidate states[3].vc_sel.`2`[4] invalidate states[3].g invalidate states[4].fifo_deps invalidate states[4].flow.egress_node_id invalidate states[4].flow.egress_node invalidate states[4].flow.ingress_node_id invalidate states[4].flow.ingress_node invalidate states[4].flow.vnet_id invalidate states[4].vc_sel.`0`[0] invalidate states[4].vc_sel.`0`[1] invalidate states[4].vc_sel.`0`[2] invalidate states[4].vc_sel.`0`[3] invalidate states[4].vc_sel.`0`[4] invalidate states[4].vc_sel.`1`[0] invalidate states[4].vc_sel.`1`[1] invalidate states[4].vc_sel.`1`[2] invalidate states[4].vc_sel.`1`[3] invalidate states[4].vc_sel.`1`[4] invalidate states[4].vc_sel.`2`[0] invalidate states[4].vc_sel.`2`[1] invalidate states[4].vc_sel.`2`[2] invalidate states[4].vc_sel.`2`[3] invalidate states[4].vc_sel.`2`[4] invalidate states[4].g node _T_57 = asUInt(reset) when _T_57 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0)
module InputUnit_92( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [4:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [4:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [4:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [4:0] mask; // @[InputUnit.scala:250:21] wire [4:0] _vcalloc_filter_T_3 = {3'h0, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [9:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 10'h1 : _vcalloc_filter_T_3[1] ? 10'h2 : _vcalloc_filter_T_3[2] ? 10'h4 : _vcalloc_filter_T_3[3] ? 10'h8 : _vcalloc_filter_T_3[4] ? 10'h10 : {3'h0, vcalloc_vals_1, 6'h0}; // @[OneHot.scala:85:71] wire [4:0] vcalloc_sel = vcalloc_filter[4:0] | vcalloc_filter[9:5]; // @[Mux.scala:50:70] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & vcalloc_vals_1; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_62 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_extend of AsyncResetSynchronizerShiftReg_w1_d3_i0_75 connect io_out_source_extend.clock, clock connect io_out_source_extend.reset, reset connect io_out_source_extend.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_extend.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_62( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_75 io_out_source_extend ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_15 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T = shr(io.in.a.bits.source, 2) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 2) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h1)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_12 = shr(io.in.a.bits.source, 2) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<2>(0h2)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_18 = shr(io.in.a.bits.source, 2) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<2>(0h3)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) wire _source_ok_WIRE : UInt<1>[4] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 connect _source_ok_WIRE[2], _source_ok_T_17 connect _source_ok_WIRE[3], _source_ok_T_23 node _source_ok_T_24 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_25 = or(_source_ok_T_24, _source_ok_WIRE[2]) node source_ok = or(_source_ok_T_25, _source_ok_WIRE[3]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_4 = shr(io.in.a.bits.source, 2) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<2>(0h3)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_17 = shr(io.in.a.bits.source, 2) node _T_18 = eq(_T_17, UInt<1>(0h1)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_30 = shr(io.in.a.bits.source, 2) node _T_31 = eq(_T_30, UInt<2>(0h2)) node _T_32 = leq(UInt<1>(0h0), uncommonBits_2) node _T_33 = and(_T_31, _T_32) node _T_34 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_35 = and(_T_33, _T_34) node _T_36 = eq(_T_35, UInt<1>(0h0)) node _T_37 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_38 = cvt(_T_37) node _T_39 = and(_T_38, asSInt(UInt<1>(0h0))) node _T_40 = asSInt(_T_39) node _T_41 = eq(_T_40, asSInt(UInt<1>(0h0))) node _T_42 = or(_T_36, _T_41) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_43 = shr(io.in.a.bits.source, 2) node _T_44 = eq(_T_43, UInt<2>(0h3)) node _T_45 = leq(UInt<1>(0h0), uncommonBits_3) node _T_46 = and(_T_44, _T_45) node _T_47 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_48 = and(_T_46, _T_47) node _T_49 = eq(_T_48, UInt<1>(0h0)) node _T_50 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_51 = cvt(_T_50) node _T_52 = and(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = asSInt(_T_52) node _T_54 = eq(_T_53, asSInt(UInt<1>(0h0))) node _T_55 = or(_T_49, _T_54) node _T_56 = and(_T_16, _T_29) node _T_57 = and(_T_56, _T_42) node _T_58 = and(_T_57, _T_55) node _T_59 = asUInt(reset) node _T_60 = eq(_T_59, UInt<1>(0h0)) when _T_60 : node _T_61 = eq(_T_58, UInt<1>(0h0)) when _T_61 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_58, UInt<1>(0h1), "") : assert_1 node _T_62 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_62 : node _T_63 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_64 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_65 = and(_T_63, _T_64) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_66 = shr(io.in.a.bits.source, 2) node _T_67 = eq(_T_66, UInt<1>(0h0)) node _T_68 = leq(UInt<1>(0h0), uncommonBits_4) node _T_69 = and(_T_67, _T_68) node _T_70 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_71 = and(_T_69, _T_70) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_72 = shr(io.in.a.bits.source, 2) node _T_73 = eq(_T_72, UInt<1>(0h1)) node _T_74 = leq(UInt<1>(0h0), uncommonBits_5) node _T_75 = and(_T_73, _T_74) node _T_76 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_77 = and(_T_75, _T_76) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_78 = shr(io.in.a.bits.source, 2) node _T_79 = eq(_T_78, UInt<2>(0h2)) node _T_80 = leq(UInt<1>(0h0), uncommonBits_6) node _T_81 = and(_T_79, _T_80) node _T_82 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_83 = and(_T_81, _T_82) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_84 = shr(io.in.a.bits.source, 2) node _T_85 = eq(_T_84, UInt<2>(0h3)) node _T_86 = leq(UInt<1>(0h0), uncommonBits_7) node _T_87 = and(_T_85, _T_86) node _T_88 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_89 = and(_T_87, _T_88) node _T_90 = or(_T_71, _T_77) node _T_91 = or(_T_90, _T_83) node _T_92 = or(_T_91, _T_89) node _T_93 = and(_T_65, _T_92) node _T_94 = or(UInt<1>(0h0), _T_93) node _T_95 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_96 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_97 = cvt(_T_96) node _T_98 = and(_T_97, asSInt(UInt<14>(0h2000))) node _T_99 = asSInt(_T_98) node _T_100 = eq(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_102 = cvt(_T_101) node _T_103 = and(_T_102, asSInt(UInt<13>(0h1000))) node _T_104 = asSInt(_T_103) node _T_105 = eq(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_107 = cvt(_T_106) node _T_108 = and(_T_107, asSInt(UInt<17>(0h10000))) node _T_109 = asSInt(_T_108) node _T_110 = eq(_T_109, asSInt(UInt<1>(0h0))) node _T_111 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_112 = cvt(_T_111) node _T_113 = and(_T_112, asSInt(UInt<18>(0h2f000))) node _T_114 = asSInt(_T_113) node _T_115 = eq(_T_114, asSInt(UInt<1>(0h0))) node _T_116 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_117 = cvt(_T_116) node _T_118 = and(_T_117, asSInt(UInt<17>(0h10000))) node _T_119 = asSInt(_T_118) node _T_120 = eq(_T_119, asSInt(UInt<1>(0h0))) node _T_121 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_122 = cvt(_T_121) node _T_123 = and(_T_122, asSInt(UInt<13>(0h1000))) node _T_124 = asSInt(_T_123) node _T_125 = eq(_T_124, asSInt(UInt<1>(0h0))) node _T_126 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<27>(0h4000000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = or(_T_100, _T_105) node _T_137 = or(_T_136, _T_110) node _T_138 = or(_T_137, _T_115) node _T_139 = or(_T_138, _T_120) node _T_140 = or(_T_139, _T_125) node _T_141 = or(_T_140, _T_130) node _T_142 = or(_T_141, _T_135) node _T_143 = and(_T_95, _T_142) node _T_144 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_145 = or(UInt<1>(0h0), _T_144) node _T_146 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<29>(0h10000000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = or(_T_150, _T_155) node _T_157 = and(_T_145, _T_156) node _T_158 = or(UInt<1>(0h0), _T_143) node _T_159 = or(_T_158, _T_157) node _T_160 = and(_T_94, _T_159) node _T_161 = asUInt(reset) node _T_162 = eq(_T_161, UInt<1>(0h0)) when _T_162 : node _T_163 = eq(_T_160, UInt<1>(0h0)) when _T_163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_160, UInt<1>(0h1), "") : assert_2 node _T_164 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_165 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_166 = and(_T_164, _T_165) node _T_167 = or(UInt<1>(0h0), _T_166) node _T_168 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<14>(0h2000))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_174 = cvt(_T_173) node _T_175 = and(_T_174, asSInt(UInt<13>(0h1000))) node _T_176 = asSInt(_T_175) node _T_177 = eq(_T_176, asSInt(UInt<1>(0h0))) node _T_178 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_179 = cvt(_T_178) node _T_180 = and(_T_179, asSInt(UInt<17>(0h10000))) node _T_181 = asSInt(_T_180) node _T_182 = eq(_T_181, asSInt(UInt<1>(0h0))) node _T_183 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_184 = cvt(_T_183) node _T_185 = and(_T_184, asSInt(UInt<18>(0h2f000))) node _T_186 = asSInt(_T_185) node _T_187 = eq(_T_186, asSInt(UInt<1>(0h0))) node _T_188 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_189 = cvt(_T_188) node _T_190 = and(_T_189, asSInt(UInt<17>(0h10000))) node _T_191 = asSInt(_T_190) node _T_192 = eq(_T_191, asSInt(UInt<1>(0h0))) node _T_193 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_194 = cvt(_T_193) node _T_195 = and(_T_194, asSInt(UInt<13>(0h1000))) node _T_196 = asSInt(_T_195) node _T_197 = eq(_T_196, asSInt(UInt<1>(0h0))) node _T_198 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_199 = cvt(_T_198) node _T_200 = and(_T_199, asSInt(UInt<17>(0h10000))) node _T_201 = asSInt(_T_200) node _T_202 = eq(_T_201, asSInt(UInt<1>(0h0))) node _T_203 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_204 = cvt(_T_203) node _T_205 = and(_T_204, asSInt(UInt<27>(0h4000000))) node _T_206 = asSInt(_T_205) node _T_207 = eq(_T_206, asSInt(UInt<1>(0h0))) node _T_208 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_209 = cvt(_T_208) node _T_210 = and(_T_209, asSInt(UInt<13>(0h1000))) node _T_211 = asSInt(_T_210) node _T_212 = eq(_T_211, asSInt(UInt<1>(0h0))) node _T_213 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_214 = cvt(_T_213) node _T_215 = and(_T_214, asSInt(UInt<29>(0h10000000))) node _T_216 = asSInt(_T_215) node _T_217 = eq(_T_216, asSInt(UInt<1>(0h0))) node _T_218 = or(_T_172, _T_177) node _T_219 = or(_T_218, _T_182) node _T_220 = or(_T_219, _T_187) node _T_221 = or(_T_220, _T_192) node _T_222 = or(_T_221, _T_197) node _T_223 = or(_T_222, _T_202) node _T_224 = or(_T_223, _T_207) node _T_225 = or(_T_224, _T_212) node _T_226 = or(_T_225, _T_217) node _T_227 = and(_T_167, _T_226) node _T_228 = or(UInt<1>(0h0), _T_227) node _T_229 = and(UInt<1>(0h0), _T_228) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_229, UInt<1>(0h1), "") : assert_3 node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(source_ok, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_236 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_237 = asUInt(reset) node _T_238 = eq(_T_237, UInt<1>(0h0)) when _T_238 : node _T_239 = eq(_T_236, UInt<1>(0h0)) when _T_239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_236, UInt<1>(0h1), "") : assert_5 node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(is_aligned, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_243 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_244 = asUInt(reset) node _T_245 = eq(_T_244, UInt<1>(0h0)) when _T_245 : node _T_246 = eq(_T_243, UInt<1>(0h0)) when _T_246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_243, UInt<1>(0h1), "") : assert_7 node _T_247 = not(io.in.a.bits.mask) node _T_248 = eq(_T_247, UInt<1>(0h0)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_248, UInt<1>(0h1), "") : assert_8 node _T_252 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_253 = asUInt(reset) node _T_254 = eq(_T_253, UInt<1>(0h0)) when _T_254 : node _T_255 = eq(_T_252, UInt<1>(0h0)) when _T_255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_252, UInt<1>(0h1), "") : assert_9 node _T_256 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_256 : node _T_257 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_258 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_259 = and(_T_257, _T_258) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_260 = shr(io.in.a.bits.source, 2) node _T_261 = eq(_T_260, UInt<1>(0h0)) node _T_262 = leq(UInt<1>(0h0), uncommonBits_8) node _T_263 = and(_T_261, _T_262) node _T_264 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_265 = and(_T_263, _T_264) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h1)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_9) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<2>(0h2)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_10) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h3)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_11) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _T_284 = or(_T_265, _T_271) node _T_285 = or(_T_284, _T_277) node _T_286 = or(_T_285, _T_283) node _T_287 = and(_T_259, _T_286) node _T_288 = or(UInt<1>(0h0), _T_287) node _T_289 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_290 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_291 = cvt(_T_290) node _T_292 = and(_T_291, asSInt(UInt<14>(0h2000))) node _T_293 = asSInt(_T_292) node _T_294 = eq(_T_293, asSInt(UInt<1>(0h0))) node _T_295 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_296 = cvt(_T_295) node _T_297 = and(_T_296, asSInt(UInt<13>(0h1000))) node _T_298 = asSInt(_T_297) node _T_299 = eq(_T_298, asSInt(UInt<1>(0h0))) node _T_300 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_301 = cvt(_T_300) node _T_302 = and(_T_301, asSInt(UInt<17>(0h10000))) node _T_303 = asSInt(_T_302) node _T_304 = eq(_T_303, asSInt(UInt<1>(0h0))) node _T_305 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_306 = cvt(_T_305) node _T_307 = and(_T_306, asSInt(UInt<18>(0h2f000))) node _T_308 = asSInt(_T_307) node _T_309 = eq(_T_308, asSInt(UInt<1>(0h0))) node _T_310 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_311 = cvt(_T_310) node _T_312 = and(_T_311, asSInt(UInt<17>(0h10000))) node _T_313 = asSInt(_T_312) node _T_314 = eq(_T_313, asSInt(UInt<1>(0h0))) node _T_315 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_316 = cvt(_T_315) node _T_317 = and(_T_316, asSInt(UInt<13>(0h1000))) node _T_318 = asSInt(_T_317) node _T_319 = eq(_T_318, asSInt(UInt<1>(0h0))) node _T_320 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_321 = cvt(_T_320) node _T_322 = and(_T_321, asSInt(UInt<27>(0h4000000))) node _T_323 = asSInt(_T_322) node _T_324 = eq(_T_323, asSInt(UInt<1>(0h0))) node _T_325 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_326 = cvt(_T_325) node _T_327 = and(_T_326, asSInt(UInt<13>(0h1000))) node _T_328 = asSInt(_T_327) node _T_329 = eq(_T_328, asSInt(UInt<1>(0h0))) node _T_330 = or(_T_294, _T_299) node _T_331 = or(_T_330, _T_304) node _T_332 = or(_T_331, _T_309) node _T_333 = or(_T_332, _T_314) node _T_334 = or(_T_333, _T_319) node _T_335 = or(_T_334, _T_324) node _T_336 = or(_T_335, _T_329) node _T_337 = and(_T_289, _T_336) node _T_338 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_339 = or(UInt<1>(0h0), _T_338) node _T_340 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_341 = cvt(_T_340) node _T_342 = and(_T_341, asSInt(UInt<17>(0h10000))) node _T_343 = asSInt(_T_342) node _T_344 = eq(_T_343, asSInt(UInt<1>(0h0))) node _T_345 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_346 = cvt(_T_345) node _T_347 = and(_T_346, asSInt(UInt<29>(0h10000000))) node _T_348 = asSInt(_T_347) node _T_349 = eq(_T_348, asSInt(UInt<1>(0h0))) node _T_350 = or(_T_344, _T_349) node _T_351 = and(_T_339, _T_350) node _T_352 = or(UInt<1>(0h0), _T_337) node _T_353 = or(_T_352, _T_351) node _T_354 = and(_T_288, _T_353) node _T_355 = asUInt(reset) node _T_356 = eq(_T_355, UInt<1>(0h0)) when _T_356 : node _T_357 = eq(_T_354, UInt<1>(0h0)) when _T_357 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_354, UInt<1>(0h1), "") : assert_10 node _T_358 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_359 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_360 = and(_T_358, _T_359) node _T_361 = or(UInt<1>(0h0), _T_360) node _T_362 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_363 = cvt(_T_362) node _T_364 = and(_T_363, asSInt(UInt<14>(0h2000))) node _T_365 = asSInt(_T_364) node _T_366 = eq(_T_365, asSInt(UInt<1>(0h0))) node _T_367 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_368 = cvt(_T_367) node _T_369 = and(_T_368, asSInt(UInt<13>(0h1000))) node _T_370 = asSInt(_T_369) node _T_371 = eq(_T_370, asSInt(UInt<1>(0h0))) node _T_372 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<17>(0h10000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_378 = cvt(_T_377) node _T_379 = and(_T_378, asSInt(UInt<18>(0h2f000))) node _T_380 = asSInt(_T_379) node _T_381 = eq(_T_380, asSInt(UInt<1>(0h0))) node _T_382 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_383 = cvt(_T_382) node _T_384 = and(_T_383, asSInt(UInt<17>(0h10000))) node _T_385 = asSInt(_T_384) node _T_386 = eq(_T_385, asSInt(UInt<1>(0h0))) node _T_387 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_388 = cvt(_T_387) node _T_389 = and(_T_388, asSInt(UInt<13>(0h1000))) node _T_390 = asSInt(_T_389) node _T_391 = eq(_T_390, asSInt(UInt<1>(0h0))) node _T_392 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_393 = cvt(_T_392) node _T_394 = and(_T_393, asSInt(UInt<17>(0h10000))) node _T_395 = asSInt(_T_394) node _T_396 = eq(_T_395, asSInt(UInt<1>(0h0))) node _T_397 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<27>(0h4000000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_403 = cvt(_T_402) node _T_404 = and(_T_403, asSInt(UInt<13>(0h1000))) node _T_405 = asSInt(_T_404) node _T_406 = eq(_T_405, asSInt(UInt<1>(0h0))) node _T_407 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_408 = cvt(_T_407) node _T_409 = and(_T_408, asSInt(UInt<29>(0h10000000))) node _T_410 = asSInt(_T_409) node _T_411 = eq(_T_410, asSInt(UInt<1>(0h0))) node _T_412 = or(_T_366, _T_371) node _T_413 = or(_T_412, _T_376) node _T_414 = or(_T_413, _T_381) node _T_415 = or(_T_414, _T_386) node _T_416 = or(_T_415, _T_391) node _T_417 = or(_T_416, _T_396) node _T_418 = or(_T_417, _T_401) node _T_419 = or(_T_418, _T_406) node _T_420 = or(_T_419, _T_411) node _T_421 = and(_T_361, _T_420) node _T_422 = or(UInt<1>(0h0), _T_421) node _T_423 = and(UInt<1>(0h0), _T_422) node _T_424 = asUInt(reset) node _T_425 = eq(_T_424, UInt<1>(0h0)) when _T_425 : node _T_426 = eq(_T_423, UInt<1>(0h0)) when _T_426 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_423, UInt<1>(0h1), "") : assert_11 node _T_427 = asUInt(reset) node _T_428 = eq(_T_427, UInt<1>(0h0)) when _T_428 : node _T_429 = eq(source_ok, UInt<1>(0h0)) when _T_429 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_430 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_431 = asUInt(reset) node _T_432 = eq(_T_431, UInt<1>(0h0)) when _T_432 : node _T_433 = eq(_T_430, UInt<1>(0h0)) when _T_433 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_430, UInt<1>(0h1), "") : assert_13 node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(is_aligned, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_437 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_438 = asUInt(reset) node _T_439 = eq(_T_438, UInt<1>(0h0)) when _T_439 : node _T_440 = eq(_T_437, UInt<1>(0h0)) when _T_440 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_437, UInt<1>(0h1), "") : assert_15 node _T_441 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_442 = asUInt(reset) node _T_443 = eq(_T_442, UInt<1>(0h0)) when _T_443 : node _T_444 = eq(_T_441, UInt<1>(0h0)) when _T_444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_441, UInt<1>(0h1), "") : assert_16 node _T_445 = not(io.in.a.bits.mask) node _T_446 = eq(_T_445, UInt<1>(0h0)) node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_T_446, UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_446, UInt<1>(0h1), "") : assert_17 node _T_450 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_451 = asUInt(reset) node _T_452 = eq(_T_451, UInt<1>(0h0)) when _T_452 : node _T_453 = eq(_T_450, UInt<1>(0h0)) when _T_453 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_450, UInt<1>(0h1), "") : assert_18 node _T_454 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_454 : node _T_455 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_456 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_457 = and(_T_455, _T_456) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_458 = shr(io.in.a.bits.source, 2) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = leq(UInt<1>(0h0), uncommonBits_12) node _T_461 = and(_T_459, _T_460) node _T_462 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_463 = and(_T_461, _T_462) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_464 = shr(io.in.a.bits.source, 2) node _T_465 = eq(_T_464, UInt<1>(0h1)) node _T_466 = leq(UInt<1>(0h0), uncommonBits_13) node _T_467 = and(_T_465, _T_466) node _T_468 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_469 = and(_T_467, _T_468) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_470 = shr(io.in.a.bits.source, 2) node _T_471 = eq(_T_470, UInt<2>(0h2)) node _T_472 = leq(UInt<1>(0h0), uncommonBits_14) node _T_473 = and(_T_471, _T_472) node _T_474 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_475 = and(_T_473, _T_474) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_476 = shr(io.in.a.bits.source, 2) node _T_477 = eq(_T_476, UInt<2>(0h3)) node _T_478 = leq(UInt<1>(0h0), uncommonBits_15) node _T_479 = and(_T_477, _T_478) node _T_480 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_481 = and(_T_479, _T_480) node _T_482 = or(_T_463, _T_469) node _T_483 = or(_T_482, _T_475) node _T_484 = or(_T_483, _T_481) node _T_485 = and(_T_457, _T_484) node _T_486 = or(UInt<1>(0h0), _T_485) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_486, UInt<1>(0h1), "") : assert_19 node _T_490 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_491 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_492 = and(_T_490, _T_491) node _T_493 = or(UInt<1>(0h0), _T_492) node _T_494 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_495 = cvt(_T_494) node _T_496 = and(_T_495, asSInt(UInt<13>(0h1000))) node _T_497 = asSInt(_T_496) node _T_498 = eq(_T_497, asSInt(UInt<1>(0h0))) node _T_499 = and(_T_493, _T_498) node _T_500 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_501 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_502 = and(_T_500, _T_501) node _T_503 = or(UInt<1>(0h0), _T_502) node _T_504 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_505 = cvt(_T_504) node _T_506 = and(_T_505, asSInt(UInt<14>(0h2000))) node _T_507 = asSInt(_T_506) node _T_508 = eq(_T_507, asSInt(UInt<1>(0h0))) node _T_509 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_510 = cvt(_T_509) node _T_511 = and(_T_510, asSInt(UInt<17>(0h10000))) node _T_512 = asSInt(_T_511) node _T_513 = eq(_T_512, asSInt(UInt<1>(0h0))) node _T_514 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_515 = cvt(_T_514) node _T_516 = and(_T_515, asSInt(UInt<18>(0h2f000))) node _T_517 = asSInt(_T_516) node _T_518 = eq(_T_517, asSInt(UInt<1>(0h0))) node _T_519 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_520 = cvt(_T_519) node _T_521 = and(_T_520, asSInt(UInt<17>(0h10000))) node _T_522 = asSInt(_T_521) node _T_523 = eq(_T_522, asSInt(UInt<1>(0h0))) node _T_524 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_525 = cvt(_T_524) node _T_526 = and(_T_525, asSInt(UInt<13>(0h1000))) node _T_527 = asSInt(_T_526) node _T_528 = eq(_T_527, asSInt(UInt<1>(0h0))) node _T_529 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_530 = cvt(_T_529) node _T_531 = and(_T_530, asSInt(UInt<17>(0h10000))) node _T_532 = asSInt(_T_531) node _T_533 = eq(_T_532, asSInt(UInt<1>(0h0))) node _T_534 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<27>(0h4000000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<29>(0h10000000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = or(_T_508, _T_513) node _T_550 = or(_T_549, _T_518) node _T_551 = or(_T_550, _T_523) node _T_552 = or(_T_551, _T_528) node _T_553 = or(_T_552, _T_533) node _T_554 = or(_T_553, _T_538) node _T_555 = or(_T_554, _T_543) node _T_556 = or(_T_555, _T_548) node _T_557 = and(_T_503, _T_556) node _T_558 = or(UInt<1>(0h0), _T_499) node _T_559 = or(_T_558, _T_557) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_559, UInt<1>(0h1), "") : assert_20 node _T_563 = asUInt(reset) node _T_564 = eq(_T_563, UInt<1>(0h0)) when _T_564 : node _T_565 = eq(source_ok, UInt<1>(0h0)) when _T_565 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(is_aligned, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_569 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_569, UInt<1>(0h1), "") : assert_23 node _T_573 = eq(io.in.a.bits.mask, mask) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_573, UInt<1>(0h1), "") : assert_24 node _T_577 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_577, UInt<1>(0h1), "") : assert_25 node _T_581 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_581 : node _T_582 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_583 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_584 = and(_T_582, _T_583) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_585 = shr(io.in.a.bits.source, 2) node _T_586 = eq(_T_585, UInt<1>(0h0)) node _T_587 = leq(UInt<1>(0h0), uncommonBits_16) node _T_588 = and(_T_586, _T_587) node _T_589 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_590 = and(_T_588, _T_589) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_591 = shr(io.in.a.bits.source, 2) node _T_592 = eq(_T_591, UInt<1>(0h1)) node _T_593 = leq(UInt<1>(0h0), uncommonBits_17) node _T_594 = and(_T_592, _T_593) node _T_595 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_596 = and(_T_594, _T_595) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_597 = shr(io.in.a.bits.source, 2) node _T_598 = eq(_T_597, UInt<2>(0h2)) node _T_599 = leq(UInt<1>(0h0), uncommonBits_18) node _T_600 = and(_T_598, _T_599) node _T_601 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_602 = and(_T_600, _T_601) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_603 = shr(io.in.a.bits.source, 2) node _T_604 = eq(_T_603, UInt<2>(0h3)) node _T_605 = leq(UInt<1>(0h0), uncommonBits_19) node _T_606 = and(_T_604, _T_605) node _T_607 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_608 = and(_T_606, _T_607) node _T_609 = or(_T_590, _T_596) node _T_610 = or(_T_609, _T_602) node _T_611 = or(_T_610, _T_608) node _T_612 = and(_T_584, _T_611) node _T_613 = or(UInt<1>(0h0), _T_612) node _T_614 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_615 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_616 = and(_T_614, _T_615) node _T_617 = or(UInt<1>(0h0), _T_616) node _T_618 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_619 = cvt(_T_618) node _T_620 = and(_T_619, asSInt(UInt<13>(0h1000))) node _T_621 = asSInt(_T_620) node _T_622 = eq(_T_621, asSInt(UInt<1>(0h0))) node _T_623 = and(_T_617, _T_622) node _T_624 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_625 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_626 = and(_T_624, _T_625) node _T_627 = or(UInt<1>(0h0), _T_626) node _T_628 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_629 = cvt(_T_628) node _T_630 = and(_T_629, asSInt(UInt<14>(0h2000))) node _T_631 = asSInt(_T_630) node _T_632 = eq(_T_631, asSInt(UInt<1>(0h0))) node _T_633 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_634 = cvt(_T_633) node _T_635 = and(_T_634, asSInt(UInt<18>(0h2f000))) node _T_636 = asSInt(_T_635) node _T_637 = eq(_T_636, asSInt(UInt<1>(0h0))) node _T_638 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_639 = cvt(_T_638) node _T_640 = and(_T_639, asSInt(UInt<17>(0h10000))) node _T_641 = asSInt(_T_640) node _T_642 = eq(_T_641, asSInt(UInt<1>(0h0))) node _T_643 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_644 = cvt(_T_643) node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000))) node _T_646 = asSInt(_T_645) node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0))) node _T_648 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_649 = cvt(_T_648) node _T_650 = and(_T_649, asSInt(UInt<17>(0h10000))) node _T_651 = asSInt(_T_650) node _T_652 = eq(_T_651, asSInt(UInt<1>(0h0))) node _T_653 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<27>(0h4000000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<13>(0h1000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<29>(0h10000000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = or(_T_632, _T_637) node _T_669 = or(_T_668, _T_642) node _T_670 = or(_T_669, _T_647) node _T_671 = or(_T_670, _T_652) node _T_672 = or(_T_671, _T_657) node _T_673 = or(_T_672, _T_662) node _T_674 = or(_T_673, _T_667) node _T_675 = and(_T_627, _T_674) node _T_676 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_677 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_678 = cvt(_T_677) node _T_679 = and(_T_678, asSInt(UInt<17>(0h10000))) node _T_680 = asSInt(_T_679) node _T_681 = eq(_T_680, asSInt(UInt<1>(0h0))) node _T_682 = and(_T_676, _T_681) node _T_683 = or(UInt<1>(0h0), _T_623) node _T_684 = or(_T_683, _T_675) node _T_685 = or(_T_684, _T_682) node _T_686 = and(_T_613, _T_685) node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(_T_686, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_686, UInt<1>(0h1), "") : assert_26 node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(source_ok, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_693 = asUInt(reset) node _T_694 = eq(_T_693, UInt<1>(0h0)) when _T_694 : node _T_695 = eq(is_aligned, UInt<1>(0h0)) when _T_695 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_696 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(_T_696, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_696, UInt<1>(0h1), "") : assert_29 node _T_700 = eq(io.in.a.bits.mask, mask) node _T_701 = asUInt(reset) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(_T_700, UInt<1>(0h0)) when _T_703 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_700, UInt<1>(0h1), "") : assert_30 node _T_704 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_704 : node _T_705 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_706 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_707 = and(_T_705, _T_706) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_708 = shr(io.in.a.bits.source, 2) node _T_709 = eq(_T_708, UInt<1>(0h0)) node _T_710 = leq(UInt<1>(0h0), uncommonBits_20) node _T_711 = and(_T_709, _T_710) node _T_712 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_713 = and(_T_711, _T_712) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_714 = shr(io.in.a.bits.source, 2) node _T_715 = eq(_T_714, UInt<1>(0h1)) node _T_716 = leq(UInt<1>(0h0), uncommonBits_21) node _T_717 = and(_T_715, _T_716) node _T_718 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_719 = and(_T_717, _T_718) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_720 = shr(io.in.a.bits.source, 2) node _T_721 = eq(_T_720, UInt<2>(0h2)) node _T_722 = leq(UInt<1>(0h0), uncommonBits_22) node _T_723 = and(_T_721, _T_722) node _T_724 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_725 = and(_T_723, _T_724) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_726 = shr(io.in.a.bits.source, 2) node _T_727 = eq(_T_726, UInt<2>(0h3)) node _T_728 = leq(UInt<1>(0h0), uncommonBits_23) node _T_729 = and(_T_727, _T_728) node _T_730 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_731 = and(_T_729, _T_730) node _T_732 = or(_T_713, _T_719) node _T_733 = or(_T_732, _T_725) node _T_734 = or(_T_733, _T_731) node _T_735 = and(_T_707, _T_734) node _T_736 = or(UInt<1>(0h0), _T_735) node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_739 = and(_T_737, _T_738) node _T_740 = or(UInt<1>(0h0), _T_739) node _T_741 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_742 = cvt(_T_741) node _T_743 = and(_T_742, asSInt(UInt<13>(0h1000))) node _T_744 = asSInt(_T_743) node _T_745 = eq(_T_744, asSInt(UInt<1>(0h0))) node _T_746 = and(_T_740, _T_745) node _T_747 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_748 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_749 = and(_T_747, _T_748) node _T_750 = or(UInt<1>(0h0), _T_749) node _T_751 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_752 = cvt(_T_751) node _T_753 = and(_T_752, asSInt(UInt<14>(0h2000))) node _T_754 = asSInt(_T_753) node _T_755 = eq(_T_754, asSInt(UInt<1>(0h0))) node _T_756 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_757 = cvt(_T_756) node _T_758 = and(_T_757, asSInt(UInt<18>(0h2f000))) node _T_759 = asSInt(_T_758) node _T_760 = eq(_T_759, asSInt(UInt<1>(0h0))) node _T_761 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_762 = cvt(_T_761) node _T_763 = and(_T_762, asSInt(UInt<17>(0h10000))) node _T_764 = asSInt(_T_763) node _T_765 = eq(_T_764, asSInt(UInt<1>(0h0))) node _T_766 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_767 = cvt(_T_766) node _T_768 = and(_T_767, asSInt(UInt<13>(0h1000))) node _T_769 = asSInt(_T_768) node _T_770 = eq(_T_769, asSInt(UInt<1>(0h0))) node _T_771 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_772 = cvt(_T_771) node _T_773 = and(_T_772, asSInt(UInt<17>(0h10000))) node _T_774 = asSInt(_T_773) node _T_775 = eq(_T_774, asSInt(UInt<1>(0h0))) node _T_776 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_777 = cvt(_T_776) node _T_778 = and(_T_777, asSInt(UInt<27>(0h4000000))) node _T_779 = asSInt(_T_778) node _T_780 = eq(_T_779, asSInt(UInt<1>(0h0))) node _T_781 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_782 = cvt(_T_781) node _T_783 = and(_T_782, asSInt(UInt<13>(0h1000))) node _T_784 = asSInt(_T_783) node _T_785 = eq(_T_784, asSInt(UInt<1>(0h0))) node _T_786 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_787 = cvt(_T_786) node _T_788 = and(_T_787, asSInt(UInt<29>(0h10000000))) node _T_789 = asSInt(_T_788) node _T_790 = eq(_T_789, asSInt(UInt<1>(0h0))) node _T_791 = or(_T_755, _T_760) node _T_792 = or(_T_791, _T_765) node _T_793 = or(_T_792, _T_770) node _T_794 = or(_T_793, _T_775) node _T_795 = or(_T_794, _T_780) node _T_796 = or(_T_795, _T_785) node _T_797 = or(_T_796, _T_790) node _T_798 = and(_T_750, _T_797) node _T_799 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_800 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_801 = cvt(_T_800) node _T_802 = and(_T_801, asSInt(UInt<17>(0h10000))) node _T_803 = asSInt(_T_802) node _T_804 = eq(_T_803, asSInt(UInt<1>(0h0))) node _T_805 = and(_T_799, _T_804) node _T_806 = or(UInt<1>(0h0), _T_746) node _T_807 = or(_T_806, _T_798) node _T_808 = or(_T_807, _T_805) node _T_809 = and(_T_736, _T_808) node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(_T_809, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_809, UInt<1>(0h1), "") : assert_31 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(source_ok, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_816 = asUInt(reset) node _T_817 = eq(_T_816, UInt<1>(0h0)) when _T_817 : node _T_818 = eq(is_aligned, UInt<1>(0h0)) when _T_818 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_819 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_820 = asUInt(reset) node _T_821 = eq(_T_820, UInt<1>(0h0)) when _T_821 : node _T_822 = eq(_T_819, UInt<1>(0h0)) when _T_822 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_819, UInt<1>(0h1), "") : assert_34 node _T_823 = not(mask) node _T_824 = and(io.in.a.bits.mask, _T_823) node _T_825 = eq(_T_824, UInt<1>(0h0)) node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(_T_825, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_825, UInt<1>(0h1), "") : assert_35 node _T_829 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_829 : node _T_830 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_831 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_832 = and(_T_830, _T_831) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_833 = shr(io.in.a.bits.source, 2) node _T_834 = eq(_T_833, UInt<1>(0h0)) node _T_835 = leq(UInt<1>(0h0), uncommonBits_24) node _T_836 = and(_T_834, _T_835) node _T_837 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_838 = and(_T_836, _T_837) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_839 = shr(io.in.a.bits.source, 2) node _T_840 = eq(_T_839, UInt<1>(0h1)) node _T_841 = leq(UInt<1>(0h0), uncommonBits_25) node _T_842 = and(_T_840, _T_841) node _T_843 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_844 = and(_T_842, _T_843) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_845 = shr(io.in.a.bits.source, 2) node _T_846 = eq(_T_845, UInt<2>(0h2)) node _T_847 = leq(UInt<1>(0h0), uncommonBits_26) node _T_848 = and(_T_846, _T_847) node _T_849 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_850 = and(_T_848, _T_849) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_851 = shr(io.in.a.bits.source, 2) node _T_852 = eq(_T_851, UInt<2>(0h3)) node _T_853 = leq(UInt<1>(0h0), uncommonBits_27) node _T_854 = and(_T_852, _T_853) node _T_855 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_856 = and(_T_854, _T_855) node _T_857 = or(_T_838, _T_844) node _T_858 = or(_T_857, _T_850) node _T_859 = or(_T_858, _T_856) node _T_860 = and(_T_832, _T_859) node _T_861 = or(UInt<1>(0h0), _T_860) node _T_862 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_863 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_864 = and(_T_862, _T_863) node _T_865 = or(UInt<1>(0h0), _T_864) node _T_866 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_867 = cvt(_T_866) node _T_868 = and(_T_867, asSInt(UInt<14>(0h2000))) node _T_869 = asSInt(_T_868) node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0))) node _T_871 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_872 = cvt(_T_871) node _T_873 = and(_T_872, asSInt(UInt<13>(0h1000))) node _T_874 = asSInt(_T_873) node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0))) node _T_876 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_877 = cvt(_T_876) node _T_878 = and(_T_877, asSInt(UInt<18>(0h2f000))) node _T_879 = asSInt(_T_878) node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0))) node _T_881 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_882 = cvt(_T_881) node _T_883 = and(_T_882, asSInt(UInt<17>(0h10000))) node _T_884 = asSInt(_T_883) node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0))) node _T_886 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<13>(0h1000))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<27>(0h4000000))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = or(_T_870, _T_875) node _T_902 = or(_T_901, _T_880) node _T_903 = or(_T_902, _T_885) node _T_904 = or(_T_903, _T_890) node _T_905 = or(_T_904, _T_895) node _T_906 = or(_T_905, _T_900) node _T_907 = and(_T_865, _T_906) node _T_908 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_909 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_910 = cvt(_T_909) node _T_911 = and(_T_910, asSInt(UInt<17>(0h10000))) node _T_912 = asSInt(_T_911) node _T_913 = eq(_T_912, asSInt(UInt<1>(0h0))) node _T_914 = and(_T_908, _T_913) node _T_915 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_916 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_917 = and(_T_915, _T_916) node _T_918 = or(UInt<1>(0h0), _T_917) node _T_919 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_920 = cvt(_T_919) node _T_921 = and(_T_920, asSInt(UInt<17>(0h10000))) node _T_922 = asSInt(_T_921) node _T_923 = eq(_T_922, asSInt(UInt<1>(0h0))) node _T_924 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_925 = cvt(_T_924) node _T_926 = and(_T_925, asSInt(UInt<29>(0h10000000))) node _T_927 = asSInt(_T_926) node _T_928 = eq(_T_927, asSInt(UInt<1>(0h0))) node _T_929 = or(_T_923, _T_928) node _T_930 = and(_T_918, _T_929) node _T_931 = or(UInt<1>(0h0), _T_907) node _T_932 = or(_T_931, _T_914) node _T_933 = or(_T_932, _T_930) node _T_934 = and(_T_861, _T_933) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_934, UInt<1>(0h1), "") : assert_36 node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(source_ok, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(is_aligned, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_944 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(_T_944, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_944, UInt<1>(0h1), "") : assert_39 node _T_948 = eq(io.in.a.bits.mask, mask) node _T_949 = asUInt(reset) node _T_950 = eq(_T_949, UInt<1>(0h0)) when _T_950 : node _T_951 = eq(_T_948, UInt<1>(0h0)) when _T_951 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_948, UInt<1>(0h1), "") : assert_40 node _T_952 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_952 : node _T_953 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_954 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_955 = and(_T_953, _T_954) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_956 = shr(io.in.a.bits.source, 2) node _T_957 = eq(_T_956, UInt<1>(0h0)) node _T_958 = leq(UInt<1>(0h0), uncommonBits_28) node _T_959 = and(_T_957, _T_958) node _T_960 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_961 = and(_T_959, _T_960) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_962 = shr(io.in.a.bits.source, 2) node _T_963 = eq(_T_962, UInt<1>(0h1)) node _T_964 = leq(UInt<1>(0h0), uncommonBits_29) node _T_965 = and(_T_963, _T_964) node _T_966 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_967 = and(_T_965, _T_966) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_968 = shr(io.in.a.bits.source, 2) node _T_969 = eq(_T_968, UInt<2>(0h2)) node _T_970 = leq(UInt<1>(0h0), uncommonBits_30) node _T_971 = and(_T_969, _T_970) node _T_972 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_973 = and(_T_971, _T_972) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_974 = shr(io.in.a.bits.source, 2) node _T_975 = eq(_T_974, UInt<2>(0h3)) node _T_976 = leq(UInt<1>(0h0), uncommonBits_31) node _T_977 = and(_T_975, _T_976) node _T_978 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_979 = and(_T_977, _T_978) node _T_980 = or(_T_961, _T_967) node _T_981 = or(_T_980, _T_973) node _T_982 = or(_T_981, _T_979) node _T_983 = and(_T_955, _T_982) node _T_984 = or(UInt<1>(0h0), _T_983) node _T_985 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_986 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_987 = and(_T_985, _T_986) node _T_988 = or(UInt<1>(0h0), _T_987) node _T_989 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_990 = cvt(_T_989) node _T_991 = and(_T_990, asSInt(UInt<14>(0h2000))) node _T_992 = asSInt(_T_991) node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0))) node _T_994 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<13>(0h1000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1000 = cvt(_T_999) node _T_1001 = and(_T_1000, asSInt(UInt<18>(0h2f000))) node _T_1002 = asSInt(_T_1001) node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0))) node _T_1004 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1005 = cvt(_T_1004) node _T_1006 = and(_T_1005, asSInt(UInt<17>(0h10000))) node _T_1007 = asSInt(_T_1006) node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0))) node _T_1009 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1010 = cvt(_T_1009) node _T_1011 = and(_T_1010, asSInt(UInt<13>(0h1000))) node _T_1012 = asSInt(_T_1011) node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0))) node _T_1014 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1015 = cvt(_T_1014) node _T_1016 = and(_T_1015, asSInt(UInt<27>(0h4000000))) node _T_1017 = asSInt(_T_1016) node _T_1018 = eq(_T_1017, asSInt(UInt<1>(0h0))) node _T_1019 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1020 = cvt(_T_1019) node _T_1021 = and(_T_1020, asSInt(UInt<13>(0h1000))) node _T_1022 = asSInt(_T_1021) node _T_1023 = eq(_T_1022, asSInt(UInt<1>(0h0))) node _T_1024 = or(_T_993, _T_998) node _T_1025 = or(_T_1024, _T_1003) node _T_1026 = or(_T_1025, _T_1008) node _T_1027 = or(_T_1026, _T_1013) node _T_1028 = or(_T_1027, _T_1018) node _T_1029 = or(_T_1028, _T_1023) node _T_1030 = and(_T_988, _T_1029) node _T_1031 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1032 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1033 = cvt(_T_1032) node _T_1034 = and(_T_1033, asSInt(UInt<17>(0h10000))) node _T_1035 = asSInt(_T_1034) node _T_1036 = eq(_T_1035, asSInt(UInt<1>(0h0))) node _T_1037 = and(_T_1031, _T_1036) node _T_1038 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1039 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_1040 = and(_T_1038, _T_1039) node _T_1041 = or(UInt<1>(0h0), _T_1040) node _T_1042 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1043 = cvt(_T_1042) node _T_1044 = and(_T_1043, asSInt(UInt<17>(0h10000))) node _T_1045 = asSInt(_T_1044) node _T_1046 = eq(_T_1045, asSInt(UInt<1>(0h0))) node _T_1047 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1048 = cvt(_T_1047) node _T_1049 = and(_T_1048, asSInt(UInt<29>(0h10000000))) node _T_1050 = asSInt(_T_1049) node _T_1051 = eq(_T_1050, asSInt(UInt<1>(0h0))) node _T_1052 = or(_T_1046, _T_1051) node _T_1053 = and(_T_1041, _T_1052) node _T_1054 = or(UInt<1>(0h0), _T_1030) node _T_1055 = or(_T_1054, _T_1037) node _T_1056 = or(_T_1055, _T_1053) node _T_1057 = and(_T_984, _T_1056) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_41 node _T_1061 = asUInt(reset) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(source_ok, UInt<1>(0h0)) when _T_1063 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(is_aligned, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_1067 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_44 node _T_1071 = eq(io.in.a.bits.mask, mask) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_45 node _T_1075 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_1075 : node _T_1076 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1077 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1078 = and(_T_1076, _T_1077) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_1079 = shr(io.in.a.bits.source, 2) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) node _T_1081 = leq(UInt<1>(0h0), uncommonBits_32) node _T_1082 = and(_T_1080, _T_1081) node _T_1083 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_1084 = and(_T_1082, _T_1083) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_1085 = shr(io.in.a.bits.source, 2) node _T_1086 = eq(_T_1085, UInt<1>(0h1)) node _T_1087 = leq(UInt<1>(0h0), uncommonBits_33) node _T_1088 = and(_T_1086, _T_1087) node _T_1089 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_1090 = and(_T_1088, _T_1089) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_1091 = shr(io.in.a.bits.source, 2) node _T_1092 = eq(_T_1091, UInt<2>(0h2)) node _T_1093 = leq(UInt<1>(0h0), uncommonBits_34) node _T_1094 = and(_T_1092, _T_1093) node _T_1095 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_1096 = and(_T_1094, _T_1095) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_1097 = shr(io.in.a.bits.source, 2) node _T_1098 = eq(_T_1097, UInt<2>(0h3)) node _T_1099 = leq(UInt<1>(0h0), uncommonBits_35) node _T_1100 = and(_T_1098, _T_1099) node _T_1101 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_1102 = and(_T_1100, _T_1101) node _T_1103 = or(_T_1084, _T_1090) node _T_1104 = or(_T_1103, _T_1096) node _T_1105 = or(_T_1104, _T_1102) node _T_1106 = and(_T_1078, _T_1105) node _T_1107 = or(UInt<1>(0h0), _T_1106) node _T_1108 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1109 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_1110 = and(_T_1108, _T_1109) node _T_1111 = or(UInt<1>(0h0), _T_1110) node _T_1112 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_1113 = cvt(_T_1112) node _T_1114 = and(_T_1113, asSInt(UInt<13>(0h1000))) node _T_1115 = asSInt(_T_1114) node _T_1116 = eq(_T_1115, asSInt(UInt<1>(0h0))) node _T_1117 = and(_T_1111, _T_1116) node _T_1118 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_1119 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_1120 = cvt(_T_1119) node _T_1121 = and(_T_1120, asSInt(UInt<14>(0h2000))) node _T_1122 = asSInt(_T_1121) node _T_1123 = eq(_T_1122, asSInt(UInt<1>(0h0))) node _T_1124 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_1125 = cvt(_T_1124) node _T_1126 = and(_T_1125, asSInt(UInt<17>(0h10000))) node _T_1127 = asSInt(_T_1126) node _T_1128 = eq(_T_1127, asSInt(UInt<1>(0h0))) node _T_1129 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_1130 = cvt(_T_1129) node _T_1131 = and(_T_1130, asSInt(UInt<18>(0h2f000))) node _T_1132 = asSInt(_T_1131) node _T_1133 = eq(_T_1132, asSInt(UInt<1>(0h0))) node _T_1134 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_1135 = cvt(_T_1134) node _T_1136 = and(_T_1135, asSInt(UInt<17>(0h10000))) node _T_1137 = asSInt(_T_1136) node _T_1138 = eq(_T_1137, asSInt(UInt<1>(0h0))) node _T_1139 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1140 = cvt(_T_1139) node _T_1141 = and(_T_1140, asSInt(UInt<13>(0h1000))) node _T_1142 = asSInt(_T_1141) node _T_1143 = eq(_T_1142, asSInt(UInt<1>(0h0))) node _T_1144 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1145 = cvt(_T_1144) node _T_1146 = and(_T_1145, asSInt(UInt<27>(0h4000000))) node _T_1147 = asSInt(_T_1146) node _T_1148 = eq(_T_1147, asSInt(UInt<1>(0h0))) node _T_1149 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1150 = cvt(_T_1149) node _T_1151 = and(_T_1150, asSInt(UInt<13>(0h1000))) node _T_1152 = asSInt(_T_1151) node _T_1153 = eq(_T_1152, asSInt(UInt<1>(0h0))) node _T_1154 = or(_T_1123, _T_1128) node _T_1155 = or(_T_1154, _T_1133) node _T_1156 = or(_T_1155, _T_1138) node _T_1157 = or(_T_1156, _T_1143) node _T_1158 = or(_T_1157, _T_1148) node _T_1159 = or(_T_1158, _T_1153) node _T_1160 = and(_T_1118, _T_1159) node _T_1161 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1162 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = or(UInt<1>(0h0), _T_1163) node _T_1165 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1166 = cvt(_T_1165) node _T_1167 = and(_T_1166, asSInt(UInt<17>(0h10000))) node _T_1168 = asSInt(_T_1167) node _T_1169 = eq(_T_1168, asSInt(UInt<1>(0h0))) node _T_1170 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1171 = cvt(_T_1170) node _T_1172 = and(_T_1171, asSInt(UInt<29>(0h10000000))) node _T_1173 = asSInt(_T_1172) node _T_1174 = eq(_T_1173, asSInt(UInt<1>(0h0))) node _T_1175 = or(_T_1169, _T_1174) node _T_1176 = and(_T_1164, _T_1175) node _T_1177 = or(UInt<1>(0h0), _T_1117) node _T_1178 = or(_T_1177, _T_1160) node _T_1179 = or(_T_1178, _T_1176) node _T_1180 = and(_T_1107, _T_1179) node _T_1181 = asUInt(reset) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(_T_1180, UInt<1>(0h0)) when _T_1183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1180, UInt<1>(0h1), "") : assert_46 node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(source_ok, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(is_aligned, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1190 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_49 node _T_1194 = eq(io.in.a.bits.mask, mask) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_50 node _T_1198 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1202 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1203 = asUInt(reset) node _T_1204 = eq(_T_1203, UInt<1>(0h0)) when _T_1204 : node _T_1205 = eq(_T_1202, UInt<1>(0h0)) when _T_1205 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1202, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_26 = shr(io.in.d.bits.source, 2) node _source_ok_T_27 = eq(_source_ok_T_26, UInt<1>(0h0)) node _source_ok_T_28 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_29 = and(_source_ok_T_27, _source_ok_T_28) node _source_ok_T_30 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_31 = and(_source_ok_T_29, _source_ok_T_30) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_32 = shr(io.in.d.bits.source, 2) node _source_ok_T_33 = eq(_source_ok_T_32, UInt<1>(0h1)) node _source_ok_T_34 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_35 = and(_source_ok_T_33, _source_ok_T_34) node _source_ok_T_36 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_37 = and(_source_ok_T_35, _source_ok_T_36) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_38 = shr(io.in.d.bits.source, 2) node _source_ok_T_39 = eq(_source_ok_T_38, UInt<2>(0h2)) node _source_ok_T_40 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_41 = and(_source_ok_T_39, _source_ok_T_40) node _source_ok_T_42 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_43 = and(_source_ok_T_41, _source_ok_T_42) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_44 = shr(io.in.d.bits.source, 2) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<2>(0h3)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) wire _source_ok_WIRE_1 : UInt<1>[4] connect _source_ok_WIRE_1[0], _source_ok_T_31 connect _source_ok_WIRE_1[1], _source_ok_T_37 connect _source_ok_WIRE_1[2], _source_ok_T_43 connect _source_ok_WIRE_1[3], _source_ok_T_49 node _source_ok_T_50 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_51 = or(_source_ok_T_50, _source_ok_WIRE_1[2]) node source_ok_1 = or(_source_ok_T_51, _source_ok_WIRE_1[3]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1206 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1206 : node _T_1207 = asUInt(reset) node _T_1208 = eq(_T_1207, UInt<1>(0h0)) when _T_1208 : node _T_1209 = eq(source_ok_1, UInt<1>(0h0)) when _T_1209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1210 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1211 = asUInt(reset) node _T_1212 = eq(_T_1211, UInt<1>(0h0)) when _T_1212 : node _T_1213 = eq(_T_1210, UInt<1>(0h0)) when _T_1213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1210, UInt<1>(0h1), "") : assert_54 node _T_1214 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1215 = asUInt(reset) node _T_1216 = eq(_T_1215, UInt<1>(0h0)) when _T_1216 : node _T_1217 = eq(_T_1214, UInt<1>(0h0)) when _T_1217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1214, UInt<1>(0h1), "") : assert_55 node _T_1218 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1219 = asUInt(reset) node _T_1220 = eq(_T_1219, UInt<1>(0h0)) when _T_1220 : node _T_1221 = eq(_T_1218, UInt<1>(0h0)) when _T_1221 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1218, UInt<1>(0h1), "") : assert_56 node _T_1222 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1223 = asUInt(reset) node _T_1224 = eq(_T_1223, UInt<1>(0h0)) when _T_1224 : node _T_1225 = eq(_T_1222, UInt<1>(0h0)) when _T_1225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1222, UInt<1>(0h1), "") : assert_57 node _T_1226 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1226 : node _T_1227 = asUInt(reset) node _T_1228 = eq(_T_1227, UInt<1>(0h0)) when _T_1228 : node _T_1229 = eq(source_ok_1, UInt<1>(0h0)) when _T_1229 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1230 = asUInt(reset) node _T_1231 = eq(_T_1230, UInt<1>(0h0)) when _T_1231 : node _T_1232 = eq(sink_ok, UInt<1>(0h0)) when _T_1232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1233 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_60 node _T_1237 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_61 node _T_1241 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_62 node _T_1245 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_63 node _T_1249 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1250 = or(UInt<1>(0h1), _T_1249) node _T_1251 = asUInt(reset) node _T_1252 = eq(_T_1251, UInt<1>(0h0)) when _T_1252 : node _T_1253 = eq(_T_1250, UInt<1>(0h0)) when _T_1253 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1250, UInt<1>(0h1), "") : assert_64 node _T_1254 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1254 : node _T_1255 = asUInt(reset) node _T_1256 = eq(_T_1255, UInt<1>(0h0)) when _T_1256 : node _T_1257 = eq(source_ok_1, UInt<1>(0h0)) when _T_1257 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1258 = asUInt(reset) node _T_1259 = eq(_T_1258, UInt<1>(0h0)) when _T_1259 : node _T_1260 = eq(sink_ok, UInt<1>(0h0)) when _T_1260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1261 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_67 node _T_1265 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1266 = asUInt(reset) node _T_1267 = eq(_T_1266, UInt<1>(0h0)) when _T_1267 : node _T_1268 = eq(_T_1265, UInt<1>(0h0)) when _T_1268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1265, UInt<1>(0h1), "") : assert_68 node _T_1269 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1270 = asUInt(reset) node _T_1271 = eq(_T_1270, UInt<1>(0h0)) when _T_1271 : node _T_1272 = eq(_T_1269, UInt<1>(0h0)) when _T_1272 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1269, UInt<1>(0h1), "") : assert_69 node _T_1273 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1274 = or(_T_1273, io.in.d.bits.corrupt) node _T_1275 = asUInt(reset) node _T_1276 = eq(_T_1275, UInt<1>(0h0)) when _T_1276 : node _T_1277 = eq(_T_1274, UInt<1>(0h0)) when _T_1277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1274, UInt<1>(0h1), "") : assert_70 node _T_1278 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1279 = or(UInt<1>(0h1), _T_1278) node _T_1280 = asUInt(reset) node _T_1281 = eq(_T_1280, UInt<1>(0h0)) when _T_1281 : node _T_1282 = eq(_T_1279, UInt<1>(0h0)) when _T_1282 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1279, UInt<1>(0h1), "") : assert_71 node _T_1283 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1283 : node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(source_ok_1, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1287 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1288 = asUInt(reset) node _T_1289 = eq(_T_1288, UInt<1>(0h0)) when _T_1289 : node _T_1290 = eq(_T_1287, UInt<1>(0h0)) when _T_1290 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1287, UInt<1>(0h1), "") : assert_73 node _T_1291 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_74 node _T_1295 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1296 = or(UInt<1>(0h1), _T_1295) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_75 node _T_1300 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1300 : node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(source_ok_1, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1304 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1305 = asUInt(reset) node _T_1306 = eq(_T_1305, UInt<1>(0h0)) when _T_1306 : node _T_1307 = eq(_T_1304, UInt<1>(0h0)) when _T_1307 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1304, UInt<1>(0h1), "") : assert_77 node _T_1308 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1309 = or(_T_1308, io.in.d.bits.corrupt) node _T_1310 = asUInt(reset) node _T_1311 = eq(_T_1310, UInt<1>(0h0)) when _T_1311 : node _T_1312 = eq(_T_1309, UInt<1>(0h0)) when _T_1312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1309, UInt<1>(0h1), "") : assert_78 node _T_1313 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1314 = or(UInt<1>(0h1), _T_1313) node _T_1315 = asUInt(reset) node _T_1316 = eq(_T_1315, UInt<1>(0h0)) when _T_1316 : node _T_1317 = eq(_T_1314, UInt<1>(0h0)) when _T_1317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1314, UInt<1>(0h1), "") : assert_79 node _T_1318 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1318 : node _T_1319 = asUInt(reset) node _T_1320 = eq(_T_1319, UInt<1>(0h0)) when _T_1320 : node _T_1321 = eq(source_ok_1, UInt<1>(0h0)) when _T_1321 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1322 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_81 node _T_1326 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1327 = asUInt(reset) node _T_1328 = eq(_T_1327, UInt<1>(0h0)) when _T_1328 : node _T_1329 = eq(_T_1326, UInt<1>(0h0)) when _T_1329 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1326, UInt<1>(0h1), "") : assert_82 node _T_1330 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1331 = or(UInt<1>(0h1), _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1335 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1336 = asUInt(reset) node _T_1337 = eq(_T_1336, UInt<1>(0h0)) when _T_1337 : node _T_1338 = eq(_T_1335, UInt<1>(0h0)) when _T_1338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1335, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1339 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1340 = asUInt(reset) node _T_1341 = eq(_T_1340, UInt<1>(0h0)) when _T_1341 : node _T_1342 = eq(_T_1339, UInt<1>(0h0)) when _T_1342 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1339, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1343 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1344 = asUInt(reset) node _T_1345 = eq(_T_1344, UInt<1>(0h0)) when _T_1345 : node _T_1346 = eq(_T_1343, UInt<1>(0h0)) when _T_1346 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1343, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1347 = eq(a_first, UInt<1>(0h0)) node _T_1348 = and(io.in.a.valid, _T_1347) when _T_1348 : node _T_1349 = eq(io.in.a.bits.opcode, opcode) node _T_1350 = asUInt(reset) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) when _T_1351 : node _T_1352 = eq(_T_1349, UInt<1>(0h0)) when _T_1352 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1349, UInt<1>(0h1), "") : assert_87 node _T_1353 = eq(io.in.a.bits.param, param) node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(_T_1353, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1353, UInt<1>(0h1), "") : assert_88 node _T_1357 = eq(io.in.a.bits.size, size) node _T_1358 = asUInt(reset) node _T_1359 = eq(_T_1358, UInt<1>(0h0)) when _T_1359 : node _T_1360 = eq(_T_1357, UInt<1>(0h0)) when _T_1360 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1357, UInt<1>(0h1), "") : assert_89 node _T_1361 = eq(io.in.a.bits.source, source) node _T_1362 = asUInt(reset) node _T_1363 = eq(_T_1362, UInt<1>(0h0)) when _T_1363 : node _T_1364 = eq(_T_1361, UInt<1>(0h0)) when _T_1364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1361, UInt<1>(0h1), "") : assert_90 node _T_1365 = eq(io.in.a.bits.address, address) node _T_1366 = asUInt(reset) node _T_1367 = eq(_T_1366, UInt<1>(0h0)) when _T_1367 : node _T_1368 = eq(_T_1365, UInt<1>(0h0)) when _T_1368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1365, UInt<1>(0h1), "") : assert_91 node _T_1369 = and(io.in.a.ready, io.in.a.valid) node _T_1370 = and(_T_1369, a_first) when _T_1370 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1371 = eq(d_first, UInt<1>(0h0)) node _T_1372 = and(io.in.d.valid, _T_1371) when _T_1372 : node _T_1373 = eq(io.in.d.bits.opcode, opcode_1) node _T_1374 = asUInt(reset) node _T_1375 = eq(_T_1374, UInt<1>(0h0)) when _T_1375 : node _T_1376 = eq(_T_1373, UInt<1>(0h0)) when _T_1376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1373, UInt<1>(0h1), "") : assert_92 node _T_1377 = eq(io.in.d.bits.param, param_1) node _T_1378 = asUInt(reset) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) when _T_1379 : node _T_1380 = eq(_T_1377, UInt<1>(0h0)) when _T_1380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1377, UInt<1>(0h1), "") : assert_93 node _T_1381 = eq(io.in.d.bits.size, size_1) node _T_1382 = asUInt(reset) node _T_1383 = eq(_T_1382, UInt<1>(0h0)) when _T_1383 : node _T_1384 = eq(_T_1381, UInt<1>(0h0)) when _T_1384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1381, UInt<1>(0h1), "") : assert_94 node _T_1385 = eq(io.in.d.bits.source, source_1) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_95 node _T_1389 = eq(io.in.d.bits.sink, sink) node _T_1390 = asUInt(reset) node _T_1391 = eq(_T_1390, UInt<1>(0h0)) when _T_1391 : node _T_1392 = eq(_T_1389, UInt<1>(0h0)) when _T_1392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1389, UInt<1>(0h1), "") : assert_96 node _T_1393 = eq(io.in.d.bits.denied, denied) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_97 node _T_1397 = and(io.in.d.ready, io.in.d.valid) node _T_1398 = and(_T_1397, d_first) when _T_1398 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes : UInt<128>, clock, reset, UInt<128>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<16> connect a_set, UInt<16>(0h0) wire a_set_wo_ready : UInt<16> connect a_set_wo_ready, UInt<16>(0h0) wire a_opcodes_set : UInt<64> connect a_opcodes_set, UInt<64>(0h0) wire a_sizes_set : UInt<128> connect a_sizes_set, UInt<128>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1399 = and(io.in.a.valid, a_first_1) node _T_1400 = and(_T_1399, UInt<1>(0h1)) when _T_1400 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1401 = and(io.in.a.ready, io.in.a.valid) node _T_1402 = and(_T_1401, a_first_1) node _T_1403 = and(_T_1402, UInt<1>(0h1)) when _T_1403 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1404 = dshr(inflight, io.in.a.bits.source) node _T_1405 = bits(_T_1404, 0, 0) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) node _T_1407 = asUInt(reset) node _T_1408 = eq(_T_1407, UInt<1>(0h0)) when _T_1408 : node _T_1409 = eq(_T_1406, UInt<1>(0h0)) when _T_1409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1406, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<16> connect d_clr, UInt<16>(0h0) wire d_clr_wo_ready : UInt<16> connect d_clr_wo_ready, UInt<16>(0h0) wire d_opcodes_clr : UInt<64> connect d_opcodes_clr, UInt<64>(0h0) wire d_sizes_clr : UInt<128> connect d_sizes_clr, UInt<128>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1410 = and(io.in.d.valid, d_first_1) node _T_1411 = and(_T_1410, UInt<1>(0h1)) node _T_1412 = eq(d_release_ack, UInt<1>(0h0)) node _T_1413 = and(_T_1411, _T_1412) when _T_1413 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1414 = and(io.in.d.ready, io.in.d.valid) node _T_1415 = and(_T_1414, d_first_1) node _T_1416 = and(_T_1415, UInt<1>(0h1)) node _T_1417 = eq(d_release_ack, UInt<1>(0h0)) node _T_1418 = and(_T_1416, _T_1417) when _T_1418 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1419 = and(io.in.d.valid, d_first_1) node _T_1420 = and(_T_1419, UInt<1>(0h1)) node _T_1421 = eq(d_release_ack, UInt<1>(0h0)) node _T_1422 = and(_T_1420, _T_1421) when _T_1422 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1423 = dshr(inflight, io.in.d.bits.source) node _T_1424 = bits(_T_1423, 0, 0) node _T_1425 = or(_T_1424, same_cycle_resp) node _T_1426 = asUInt(reset) node _T_1427 = eq(_T_1426, UInt<1>(0h0)) when _T_1427 : node _T_1428 = eq(_T_1425, UInt<1>(0h0)) when _T_1428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1425, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1429 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1430 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1431 = or(_T_1429, _T_1430) node _T_1432 = asUInt(reset) node _T_1433 = eq(_T_1432, UInt<1>(0h0)) when _T_1433 : node _T_1434 = eq(_T_1431, UInt<1>(0h0)) when _T_1434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1431, UInt<1>(0h1), "") : assert_100 node _T_1435 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1436 = asUInt(reset) node _T_1437 = eq(_T_1436, UInt<1>(0h0)) when _T_1437 : node _T_1438 = eq(_T_1435, UInt<1>(0h0)) when _T_1438 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1435, UInt<1>(0h1), "") : assert_101 else : node _T_1439 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1440 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1441 = or(_T_1439, _T_1440) node _T_1442 = asUInt(reset) node _T_1443 = eq(_T_1442, UInt<1>(0h0)) when _T_1443 : node _T_1444 = eq(_T_1441, UInt<1>(0h0)) when _T_1444 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1441, UInt<1>(0h1), "") : assert_102 node _T_1445 = eq(io.in.d.bits.size, a_size_lookup) node _T_1446 = asUInt(reset) node _T_1447 = eq(_T_1446, UInt<1>(0h0)) when _T_1447 : node _T_1448 = eq(_T_1445, UInt<1>(0h0)) when _T_1448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1445, UInt<1>(0h1), "") : assert_103 node _T_1449 = and(io.in.d.valid, d_first_1) node _T_1450 = and(_T_1449, a_first_1) node _T_1451 = and(_T_1450, io.in.a.valid) node _T_1452 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1453 = and(_T_1451, _T_1452) node _T_1454 = eq(d_release_ack, UInt<1>(0h0)) node _T_1455 = and(_T_1453, _T_1454) when _T_1455 : node _T_1456 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1457 = or(_T_1456, io.in.a.ready) node _T_1458 = asUInt(reset) node _T_1459 = eq(_T_1458, UInt<1>(0h0)) when _T_1459 : node _T_1460 = eq(_T_1457, UInt<1>(0h0)) when _T_1460 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1457, UInt<1>(0h1), "") : assert_104 node _T_1461 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1462 = orr(a_set_wo_ready) node _T_1463 = eq(_T_1462, UInt<1>(0h0)) node _T_1464 = or(_T_1461, _T_1463) node _T_1465 = asUInt(reset) node _T_1466 = eq(_T_1465, UInt<1>(0h0)) when _T_1466 : node _T_1467 = eq(_T_1464, UInt<1>(0h0)) when _T_1467 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1464, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_30 node _T_1468 = orr(inflight) node _T_1469 = eq(_T_1468, UInt<1>(0h0)) node _T_1470 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1471 = or(_T_1469, _T_1470) node _T_1472 = lt(watchdog, plusarg_reader.out) node _T_1473 = or(_T_1471, _T_1472) node _T_1474 = asUInt(reset) node _T_1475 = eq(_T_1474, UInt<1>(0h0)) when _T_1475 : node _T_1476 = eq(_T_1473, UInt<1>(0h0)) when _T_1476 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1473, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1477 = and(io.in.a.ready, io.in.a.valid) node _T_1478 = and(io.in.d.ready, io.in.d.valid) node _T_1479 = or(_T_1477, _T_1478) when _T_1479 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<16>, clock, reset, UInt<16>(0h0) regreset inflight_opcodes_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset inflight_sizes_1 : UInt<128>, clock, reset, UInt<128>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<4>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<4>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<16> connect c_set, UInt<16>(0h0) wire c_set_wo_ready : UInt<16> connect c_set_wo_ready, UInt<16>(0h0) wire c_opcodes_set : UInt<64> connect c_opcodes_set, UInt<64>(0h0) wire c_sizes_set : UInt<128> connect c_sizes_set, UInt<128>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1480 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1481 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1482 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1483 = and(_T_1481, _T_1482) node _T_1484 = and(_T_1480, _T_1483) when _T_1484 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<4>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1485 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1486 = and(_T_1485, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<4>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1487 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1488 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1489 = and(_T_1487, _T_1488) node _T_1490 = and(_T_1486, _T_1489) when _T_1490 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<4>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<4>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1491 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1492 = bits(_T_1491, 0, 0) node _T_1493 = eq(_T_1492, UInt<1>(0h0)) node _T_1494 = asUInt(reset) node _T_1495 = eq(_T_1494, UInt<1>(0h0)) when _T_1495 : node _T_1496 = eq(_T_1493, UInt<1>(0h0)) when _T_1496 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1493, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<16> connect d_clr_1, UInt<16>(0h0) wire d_clr_wo_ready_1 : UInt<16> connect d_clr_wo_ready_1, UInt<16>(0h0) wire d_opcodes_clr_1 : UInt<64> connect d_opcodes_clr_1, UInt<64>(0h0) wire d_sizes_clr_1 : UInt<128> connect d_sizes_clr_1, UInt<128>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1497 = and(io.in.d.valid, d_first_2) node _T_1498 = and(_T_1497, UInt<1>(0h1)) node _T_1499 = and(_T_1498, d_release_ack_1) when _T_1499 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1500 = and(io.in.d.ready, io.in.d.valid) node _T_1501 = and(_T_1500, d_first_2) node _T_1502 = and(_T_1501, UInt<1>(0h1)) node _T_1503 = and(_T_1502, d_release_ack_1) when _T_1503 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1504 = and(io.in.d.valid, d_first_2) node _T_1505 = and(_T_1504, UInt<1>(0h1)) node _T_1506 = and(_T_1505, d_release_ack_1) when _T_1506 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1507 = dshr(inflight_1, io.in.d.bits.source) node _T_1508 = bits(_T_1507, 0, 0) node _T_1509 = or(_T_1508, same_cycle_resp_1) node _T_1510 = asUInt(reset) node _T_1511 = eq(_T_1510, UInt<1>(0h0)) when _T_1511 : node _T_1512 = eq(_T_1509, UInt<1>(0h0)) when _T_1512 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1509, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<4>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1513 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1514 = asUInt(reset) node _T_1515 = eq(_T_1514, UInt<1>(0h0)) when _T_1515 : node _T_1516 = eq(_T_1513, UInt<1>(0h0)) when _T_1516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1513, UInt<1>(0h1), "") : assert_109 else : node _T_1517 = eq(io.in.d.bits.size, c_size_lookup) node _T_1518 = asUInt(reset) node _T_1519 = eq(_T_1518, UInt<1>(0h0)) when _T_1519 : node _T_1520 = eq(_T_1517, UInt<1>(0h0)) when _T_1520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1517, UInt<1>(0h1), "") : assert_110 node _T_1521 = and(io.in.d.valid, d_first_2) node _T_1522 = and(_T_1521, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<4>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1523 = and(_T_1522, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<4>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1524 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1525 = and(_T_1523, _T_1524) node _T_1526 = and(_T_1525, d_release_ack_1) node _T_1527 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1528 = and(_T_1526, _T_1527) when _T_1528 : node _T_1529 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<4>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1530 = or(_T_1529, _WIRE_23.ready) node _T_1531 = asUInt(reset) node _T_1532 = eq(_T_1531, UInt<1>(0h0)) when _T_1532 : node _T_1533 = eq(_T_1530, UInt<1>(0h0)) when _T_1533 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1530, UInt<1>(0h1), "") : assert_111 node _T_1534 = orr(c_set_wo_ready) when _T_1534 : node _T_1535 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1536 = asUInt(reset) node _T_1537 = eq(_T_1536, UInt<1>(0h0)) when _T_1537 : node _T_1538 = eq(_T_1535, UInt<1>(0h0)) when _T_1538 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1535, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_31 node _T_1539 = orr(inflight_1) node _T_1540 = eq(_T_1539, UInt<1>(0h0)) node _T_1541 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1542 = or(_T_1540, _T_1541) node _T_1543 = lt(watchdog_1, plusarg_reader_1.out) node _T_1544 = or(_T_1542, _T_1543) node _T_1545 = asUInt(reset) node _T_1546 = eq(_T_1545, UInt<1>(0h0)) when _T_1546 : node _T_1547 = eq(_T_1544, UInt<1>(0h0)) when _T_1547 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/serdes/PeripheryTLSerial.scala:149:77)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1544, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<4>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1548 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1549 = and(io.in.d.ready, io.in.d.valid) node _T_1550 = or(_T_1548, _T_1549) when _T_1550 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_15( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [8:0] c_first_beats1_decode = 9'h0; // @[Edges.scala:220:59] wire [8:0] c_first_beats1 = 9'h0; // @[Edges.scala:221:14] wire [8:0] _c_first_count_T = 9'h0; // @[Edges.scala:234:27] wire [8:0] c_first_count = 9'h0; // @[Edges.scala:234:25] wire [8:0] _c_first_counter_T = 9'h0; // @[Edges.scala:236:21] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_28 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_30 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_34 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_36 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_40 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_42 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [8:0] c_first_counter1 = 9'h1FF; // @[Edges.scala:230:28] wire [9:0] _c_first_counter1_T = 10'h3FF; // @[Edges.scala:230:28] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] c_opcodes_set = 64'h0; // @[Monitor.scala:740:34] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_wo_ready_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_1_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_2_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_3_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_4_bits_source = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_5_bits_source = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [131:0] _c_sizes_set_T_1 = 132'h0; // @[Monitor.scala:768:52] wire [6:0] _c_opcodes_set_T = 7'h0; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T = 7'h0; // @[Monitor.scala:768:77] wire [130:0] _c_opcodes_set_T_1 = 131'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [15:0] _c_set_wo_ready_T = 16'h1; // @[OneHot.scala:58:35] wire [15:0] _c_set_T = 16'h1; // @[OneHot.scala:58:35] wire [127:0] c_sizes_set = 128'h0; // @[Monitor.scala:741:34] wire [15:0] c_set = 16'h0; // @[Monitor.scala:738:34] wire [15:0] c_set_wo_ready = 16'h0; // @[Monitor.scala:739:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_4 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_6 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_12 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_18 = io_in_a_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = _source_ok_T_6 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_13 = _source_ok_T_12 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = &_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire _source_ok_T_24 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_25 = _source_ok_T_24 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_25 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 4'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_4 = _uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_9 = _uncommonBits_T_9[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_14 = _uncommonBits_T_14[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_19 = _uncommonBits_T_19[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_24 = _uncommonBits_T_24[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_29 = _uncommonBits_T_29[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_34 = _uncommonBits_T_34[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] _source_ok_T_26 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_32 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_38 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire [1:0] _source_ok_T_44 = io_in_d_bits_source_0[3:2]; // @[Monitor.scala:36:7] wire _source_ok_T_27 = _source_ok_T_26 == 2'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_29 = _source_ok_T_27; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_31 = _source_ok_T_29; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_33 = _source_ok_T_32 == 2'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_35 = _source_ok_T_33; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_37 = _source_ok_T_35; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_37; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_39 = _source_ok_T_38 == 2'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_41 = _source_ok_T_39; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_43 = _source_ok_T_41; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_45 = &_source_ok_T_44; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire _source_ok_T_50 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_51 = _source_ok_T_50 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_51 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _T_1477 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1477; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1477; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T = {1'h0, a_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1 = _a_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1550 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1550; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1550; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1550; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [8:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T = {1'h0, d_first_counter} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1 = _d_first_counter1_T[8:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [15:0] inflight; // @[Monitor.scala:614:27] reg [63:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [127:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [8:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 9'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] a_first_counter1_1 = _a_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_1 = _d_first_counter1_T_1[8:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [15:0] a_set; // @[Monitor.scala:626:34] wire [15:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [63:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [127:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [63:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [63:0] _a_opcode_lookup_T_6 = {60'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [63:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [6:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [127:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [127:0] _a_size_lookup_T_6 = {120'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [127:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[127:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_3 = {12'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_4 = 16'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1403 = _T_1477 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1403 ? _a_set_T : 16'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1403 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1403 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1403 ? _a_opcodes_set_T_1[63:0] : 64'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [6:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [131:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1403 ? _a_sizes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [15:0] d_clr; // @[Monitor.scala:664:34] wire [15:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [63:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [127:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1449 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_6 = {12'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [15:0] _GEN_7 = 16'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1449 & ~d_release_ack ? _d_clr_wo_ready_T : 16'h0; // @[OneHot.scala:58:35] wire _T_1418 = _T_1550 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1418 ? _d_clr_T : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1418 ? _d_opcodes_clr_T_5[63:0] : 64'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1418 ? _d_sizes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [15:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [15:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [15:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [63:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [63:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [63:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [127:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [127:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [127:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [15:0] inflight_1; // @[Monitor.scala:726:35] wire [15:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [63:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [63:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [127:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [127:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [8:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:3]; // @[package.scala:243:46] wire [8:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 9'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire [9:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 10'h1; // @[Edges.scala:229:27, :230:28] wire [8:0] d_first_counter1_2 = _d_first_counter1_T_2[8:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 9'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 9'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [8:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [8:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [8:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [63:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [63:0] _c_opcode_lookup_T_6 = {60'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [63:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[63:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [127:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [127:0] _c_size_lookup_T_6 = {120'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [127:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[127:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [15:0] d_clr_1; // @[Monitor.scala:774:34] wire [15:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [63:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [127:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1521 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1521 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 16'h0; // @[OneHot.scala:58:35] wire _T_1503 = _T_1550 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1503 ? _d_clr_T_1 : 16'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1503 ? _d_opcodes_clr_T_11[63:0] : 64'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1503 ? _d_sizes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 4'h0; // @[Monitor.scala:36:7, :795:113] wire [15:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [15:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [63:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [63:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [127:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [127:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module CSRFile : input clock : Clock input reset : Reset output io : { flip ungated_clock : Clock, flip interrupts : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt<1>, rw : { flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<32>, flip wdata : UInt<32>}, decode : { flip inst : UInt<32>, fp_illegal : UInt<1>, vector_illegal : UInt<1>, fp_csr : UInt<1>, vector_csr : UInt<1>, rocc_illegal : UInt<1>, read_illegal : UInt<1>, write_illegal : UInt<1>, write_flush : UInt<1>, system_illegal : UInt<1>, virtual_access_illegal : UInt<1>, virtual_system_illegal : UInt<1>}[1], csr_stall : UInt<1>, rw_stall : UInt<1>, eret : UInt<1>, singleStep : UInt<1>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, gstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, ptbr : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, hgatp : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, vsatp : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, evec : UInt<32>, flip exception : UInt<1>, flip retire : UInt<1>, flip cause : UInt<32>, flip pc : UInt<32>, flip tval : UInt<32>, flip htval : UInt<32>, flip mhtinst_read_pseudo : UInt<1>, flip gva : UInt<1>, time : UInt<32>, fcsr_rm : UInt<3>, flip fcsr_flags : { valid : UInt<1>, bits : UInt<5>}, flip rocc_interrupt : UInt<1>, interrupt : UInt<1>, interrupt_cause : UInt<32>, bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<8>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<32>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<23>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[1], pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], counters : { eventSel : UInt<32>, flip inc : UInt<1>}[0], csrw_counter : UInt<32>, inhibit_cycle : UInt<1>, flip inst : UInt<32>[1], trace : { valid : UInt<1>, iaddr : UInt<32>, insn : UInt<32>, priv : UInt<3>, exception : UInt<1>, interrupt : UInt<1>, cause : UInt<32>, tval : UInt<32>}[1], mcontext : UInt<0>, scontext : UInt<0>, fiom : UInt<1>, customCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<32>, value : UInt<32>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<32>}[4], roccCSRs : { ren : UInt<1>, wen : UInt<1>, wdata : UInt<32>, value : UInt<32>, flip stall : UInt<1>, flip set : UInt<1>, flip sdata : UInt<32>}[0]} connect io.rw_stall, UInt<1>(0h0) wire _reset_mstatus_WIRE : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect _reset_mstatus_WIRE.uie, UInt<1>(0h0) connect _reset_mstatus_WIRE.sie, UInt<1>(0h0) connect _reset_mstatus_WIRE.hie, UInt<1>(0h0) connect _reset_mstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mstatus_WIRE.upie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spie, UInt<1>(0h0) connect _reset_mstatus_WIRE.ube, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpie, UInt<1>(0h0) connect _reset_mstatus_WIRE.spp, UInt<1>(0h0) connect _reset_mstatus_WIRE.vs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mpp, UInt<2>(0h0) connect _reset_mstatus_WIRE.fs, UInt<2>(0h0) connect _reset_mstatus_WIRE.xs, UInt<2>(0h0) connect _reset_mstatus_WIRE.mprv, UInt<1>(0h0) connect _reset_mstatus_WIRE.sum, UInt<1>(0h0) connect _reset_mstatus_WIRE.mxr, UInt<1>(0h0) connect _reset_mstatus_WIRE.tvm, UInt<1>(0h0) connect _reset_mstatus_WIRE.tw, UInt<1>(0h0) connect _reset_mstatus_WIRE.tsr, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero1, UInt<8>(0h0) connect _reset_mstatus_WIRE.sd_rv32, UInt<1>(0h0) connect _reset_mstatus_WIRE.uxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sxl, UInt<2>(0h0) connect _reset_mstatus_WIRE.sbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.mbe, UInt<1>(0h0) connect _reset_mstatus_WIRE.gva, UInt<1>(0h0) connect _reset_mstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mstatus_WIRE.zero2, UInt<23>(0h0) connect _reset_mstatus_WIRE.sd, UInt<1>(0h0) connect _reset_mstatus_WIRE.v, UInt<1>(0h0) connect _reset_mstatus_WIRE.prv, UInt<2>(0h0) connect _reset_mstatus_WIRE.dv, UInt<1>(0h0) connect _reset_mstatus_WIRE.dprv, UInt<2>(0h0) connect _reset_mstatus_WIRE.isa, UInt<32>(0h0) connect _reset_mstatus_WIRE.wfi, UInt<1>(0h0) connect _reset_mstatus_WIRE.cease, UInt<1>(0h0) connect _reset_mstatus_WIRE.debug, UInt<1>(0h0) wire reset_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} connect reset_mstatus, _reset_mstatus_WIRE connect reset_mstatus.mpp, UInt<2>(0h3) connect reset_mstatus.prv, UInt<2>(0h3) connect reset_mstatus.xs, UInt<1>(0h0) regreset reg_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock, reset, reset_mstatus wire new_prv : UInt connect new_prv, reg_mstatus.prv connect reg_mstatus.prv, UInt<2>(0h3) wire _reset_dcsr_WIRE : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect _reset_dcsr_WIRE.prv, UInt<2>(0h0) connect _reset_dcsr_WIRE.step, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero1, UInt<2>(0h0) connect _reset_dcsr_WIRE.v, UInt<1>(0h0) connect _reset_dcsr_WIRE.cause, UInt<3>(0h0) connect _reset_dcsr_WIRE.stoptime, UInt<1>(0h0) connect _reset_dcsr_WIRE.stopcycle, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero2, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaku, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreaks, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakh, UInt<1>(0h0) connect _reset_dcsr_WIRE.ebreakm, UInt<1>(0h0) connect _reset_dcsr_WIRE.zero3, UInt<12>(0h0) connect _reset_dcsr_WIRE.zero4, UInt<2>(0h0) connect _reset_dcsr_WIRE.xdebugver, UInt<2>(0h0) wire reset_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} connect reset_dcsr, _reset_dcsr_WIRE connect reset_dcsr.xdebugver, UInt<1>(0h1) connect reset_dcsr.prv, UInt<2>(0h3) regreset reg_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>}, clock, reset, reset_dcsr wire sup : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sup.usip, UInt<1>(0h0) connect sup.ssip, UInt<1>(0h0) connect sup.vssip, UInt<1>(0h0) connect sup.msip, UInt<1>(0h1) connect sup.utip, UInt<1>(0h0) connect sup.stip, UInt<1>(0h0) connect sup.vstip, UInt<1>(0h0) connect sup.mtip, UInt<1>(0h1) connect sup.ueip, UInt<1>(0h0) connect sup.seip, UInt<1>(0h0) connect sup.vseip, UInt<1>(0h0) connect sup.meip, UInt<1>(0h1) connect sup.sgeip, UInt<1>(0h0) connect sup.rocc, UInt<1>(0h0) connect sup.debug, UInt<1>(0h0) connect sup.zero1, UInt<1>(0h0) wire del : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect del, sup connect del.msip, UInt<1>(0h0) connect del.mtip, UInt<1>(0h0) connect del.meip, UInt<1>(0h0) node lo_lo_lo = cat(sup.ssip, sup.usip) node lo_lo_hi = cat(sup.msip, sup.vssip) node lo_lo = cat(lo_lo_hi, lo_lo_lo) node lo_hi_lo = cat(sup.stip, sup.utip) node lo_hi_hi = cat(sup.mtip, sup.vstip) node lo_hi = cat(lo_hi_hi, lo_hi_lo) node lo = cat(lo_hi, lo_lo) node hi_lo_lo = cat(sup.seip, sup.ueip) node hi_lo_hi = cat(sup.meip, sup.vseip) node hi_lo = cat(hi_lo_hi, hi_lo_lo) node hi_hi_lo = cat(sup.rocc, sup.sgeip) node hi_hi_hi_hi = cat(UInt<0>(0h0), sup.zero1) node hi_hi_hi = cat(hi_hi_hi_hi, sup.debug) node hi_hi = cat(hi_hi_hi, hi_hi_lo) node hi = cat(hi_hi, hi_lo) node _T = cat(hi, lo) node supported_interrupts = or(_T, UInt<1>(0h0)) node lo_lo_lo_1 = cat(del.ssip, del.usip) node lo_lo_hi_1 = cat(del.msip, del.vssip) node lo_lo_1 = cat(lo_lo_hi_1, lo_lo_lo_1) node lo_hi_lo_1 = cat(del.stip, del.utip) node lo_hi_hi_1 = cat(del.mtip, del.vstip) node lo_hi_1 = cat(lo_hi_hi_1, lo_hi_lo_1) node lo_1 = cat(lo_hi_1, lo_lo_1) node hi_lo_lo_1 = cat(del.seip, del.ueip) node hi_lo_hi_1 = cat(del.meip, del.vseip) node hi_lo_1 = cat(hi_lo_hi_1, hi_lo_lo_1) node hi_hi_lo_1 = cat(del.rocc, del.sgeip) node hi_hi_hi_hi_1 = cat(UInt<0>(0h0), del.zero1) node hi_hi_hi_1 = cat(hi_hi_hi_hi_1, del.debug) node hi_hi_1 = cat(hi_hi_hi_1, hi_hi_lo_1) node hi_1 = cat(hi_hi_1, hi_lo_1) node delegable_interrupts = cat(hi_1, lo_1) wire _always_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _always_WIRE.usip, UInt<1>(0h0) connect _always_WIRE.ssip, UInt<1>(0h0) connect _always_WIRE.vssip, UInt<1>(0h0) connect _always_WIRE.msip, UInt<1>(0h0) connect _always_WIRE.utip, UInt<1>(0h0) connect _always_WIRE.stip, UInt<1>(0h0) connect _always_WIRE.vstip, UInt<1>(0h0) connect _always_WIRE.mtip, UInt<1>(0h0) connect _always_WIRE.ueip, UInt<1>(0h0) connect _always_WIRE.seip, UInt<1>(0h0) connect _always_WIRE.vseip, UInt<1>(0h0) connect _always_WIRE.meip, UInt<1>(0h0) connect _always_WIRE.sgeip, UInt<1>(0h0) connect _always_WIRE.rocc, UInt<1>(0h0) connect _always_WIRE.debug, UInt<1>(0h0) connect _always_WIRE.zero1, UInt<1>(0h0) wire always : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect always, _always_WIRE connect always.vssip, UInt<1>(0h0) connect always.vstip, UInt<1>(0h0) connect always.vseip, UInt<1>(0h0) wire deleg : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect deleg, always node lo_lo_lo_2 = cat(deleg.ssip, deleg.usip) node lo_lo_hi_2 = cat(deleg.msip, deleg.vssip) node lo_lo_2 = cat(lo_lo_hi_2, lo_lo_lo_2) node lo_hi_lo_2 = cat(deleg.stip, deleg.utip) node lo_hi_hi_2 = cat(deleg.mtip, deleg.vstip) node lo_hi_2 = cat(lo_hi_hi_2, lo_hi_lo_2) node lo_2 = cat(lo_hi_2, lo_lo_2) node hi_lo_lo_2 = cat(deleg.seip, deleg.ueip) node hi_lo_hi_2 = cat(deleg.meip, deleg.vseip) node hi_lo_2 = cat(hi_lo_hi_2, hi_lo_lo_2) node hi_hi_lo_2 = cat(deleg.rocc, deleg.sgeip) node hi_hi_hi_hi_2 = cat(UInt<0>(0h0), deleg.zero1) node hi_hi_hi_2 = cat(hi_hi_hi_hi_2, deleg.debug) node hi_hi_2 = cat(hi_hi_hi_2, hi_hi_lo_2) node hi_2 = cat(hi_hi_2, hi_lo_2) node hs_delegable_interrupts = cat(hi_2, lo_2) node lo_lo_lo_3 = cat(always.ssip, always.usip) node lo_lo_hi_3 = cat(always.msip, always.vssip) node lo_lo_3 = cat(lo_lo_hi_3, lo_lo_lo_3) node lo_hi_lo_3 = cat(always.stip, always.utip) node lo_hi_hi_3 = cat(always.mtip, always.vstip) node lo_hi_3 = cat(lo_hi_hi_3, lo_hi_lo_3) node lo_3 = cat(lo_hi_3, lo_lo_3) node hi_lo_lo_3 = cat(always.seip, always.ueip) node hi_lo_hi_3 = cat(always.meip, always.vseip) node hi_lo_3 = cat(hi_lo_hi_3, hi_lo_lo_3) node hi_hi_lo_3 = cat(always.rocc, always.sgeip) node hi_hi_hi_hi_3 = cat(UInt<0>(0h0), always.zero1) node hi_hi_hi_3 = cat(hi_hi_hi_hi_3, always.debug) node hi_hi_3 = cat(hi_hi_hi_3, hi_hi_lo_3) node hi_3 = cat(hi_hi_3, hi_lo_3) node mideleg_always_hs = cat(hi_3, lo_3) regreset reg_debug : UInt<1>, clock, reset, UInt<1>(0h0) reg reg_dpc : UInt<32>, clock reg reg_dscratch0 : UInt<32>, clock reg reg_singleStepped : UInt<1>, clock reg reg_tselect : UInt<1>, clock reg reg_bp : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<8>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<32>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<23>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}}[2], clock reg reg_pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>}[8], clock reg reg_mie : UInt<32>, clock reg reg_mideleg : UInt<32>, clock node _T_1 = and(reg_mideleg, delegable_interrupts) node _T_2 = or(_T_1, mideleg_always_hs) node read_mideleg = mux(UInt<1>(0h0), _T_2, UInt<1>(0h0)) reg reg_medeleg : UInt<32>, clock node _T_3 = and(reg_medeleg, UInt<16>(0hb15d)) node read_medeleg = mux(UInt<1>(0h0), _T_3, UInt<1>(0h0)) reg reg_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clock reg reg_mepc : UInt<32>, clock regreset reg_mcause : UInt<32>, clock, reset, UInt<32>(0h0) reg reg_mtval : UInt<32>, clock reg reg_mtval2 : UInt<32>, clock reg reg_mscratch : UInt<32>, clock regreset reg_mtvec : UInt<32>, clock, reset, UInt<32>(0h0) wire _reset_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _reset_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mie, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _reset_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _reset_mnstatus_WIRE.mpp, UInt<2>(0h0) wire reset_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect reset_mnstatus, _reset_mnstatus_WIRE connect reset_mnstatus.mpp, UInt<2>(0h3) reg reg_mnscratch : UInt<32>, clock reg reg_mnepc : UInt<32>, clock regreset reg_mncause : UInt<32>, clock, reset, UInt<32>(0h0) regreset reg_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>}, clock, reset, reset_mnstatus regreset reg_rnmie : UInt<1>, clock, reset, UInt<1>(0h1) wire _reg_menvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_menvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_menvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_menvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_menvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_menvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_menvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_menvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_menvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_menvcfg_WIRE wire _reg_senvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_senvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_senvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_senvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_senvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_senvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_senvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_senvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_senvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_senvcfg_WIRE wire _reg_henvcfg_WIRE : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>} connect _reg_henvcfg_WIRE.fiom, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero3, UInt<3>(0h0) connect _reg_henvcfg_WIRE.cbie, UInt<2>(0h0) connect _reg_henvcfg_WIRE.cbcfe, UInt<1>(0h0) connect _reg_henvcfg_WIRE.cbze, UInt<1>(0h0) connect _reg_henvcfg_WIRE.zero54, UInt<54>(0h0) connect _reg_henvcfg_WIRE.pbmte, UInt<1>(0h0) connect _reg_henvcfg_WIRE.stce, UInt<1>(0h0) regreset reg_henvcfg : { stce : UInt<1>, pbmte : UInt<1>, zero54 : UInt<54>, cbze : UInt<1>, cbcfe : UInt<1>, cbie : UInt<2>, zero3 : UInt<3>, fiom : UInt<1>}, clock, reset, _reg_henvcfg_WIRE reg reg_mcounteren : UInt<32>, clock node _T_4 = and(reg_mcounteren, UInt<3>(0h7)) node read_mcounteren = mux(UInt<1>(0h0), _T_4, UInt<1>(0h0)) reg reg_scounteren : UInt<32>, clock node _T_5 = and(reg_scounteren, UInt<3>(0h7)) node read_scounteren = mux(UInt<1>(0h0), _T_5, UInt<1>(0h0)) reg reg_hideleg : UInt<32>, clock node _T_6 = and(reg_hideleg, hs_delegable_interrupts) node read_hideleg = mux(UInt<1>(0h0), _T_6, UInt<1>(0h0)) reg reg_hedeleg : UInt<32>, clock node _T_7 = and(reg_hedeleg, UInt<16>(0hb1ff)) node read_hedeleg = mux(UInt<1>(0h0), _T_7, UInt<1>(0h0)) reg reg_hcounteren : UInt<32>, clock node _T_8 = and(reg_hcounteren, UInt<3>(0h7)) node read_hcounteren = mux(UInt<1>(0h0), _T_8, UInt<1>(0h0)) wire _reg_hstatus_WIRE : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>} connect _reg_hstatus_WIRE.zero1, UInt<5>(0h0) connect _reg_hstatus_WIRE.vsbe, UInt<1>(0h0) connect _reg_hstatus_WIRE.gva, UInt<1>(0h0) connect _reg_hstatus_WIRE.spv, UInt<1>(0h0) connect _reg_hstatus_WIRE.spvp, UInt<1>(0h0) connect _reg_hstatus_WIRE.hu, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero2, UInt<2>(0h0) connect _reg_hstatus_WIRE.vgein, UInt<6>(0h0) connect _reg_hstatus_WIRE.zero3, UInt<2>(0h0) connect _reg_hstatus_WIRE.vtvm, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtw, UInt<1>(0h0) connect _reg_hstatus_WIRE.vtsr, UInt<1>(0h0) connect _reg_hstatus_WIRE.zero5, UInt<9>(0h0) connect _reg_hstatus_WIRE.vsxl, UInt<2>(0h0) connect _reg_hstatus_WIRE.zero6, UInt<30>(0h0) regreset reg_hstatus : { zero6 : UInt<30>, vsxl : UInt<2>, zero5 : UInt<9>, vtsr : UInt<1>, vtw : UInt<1>, vtvm : UInt<1>, zero3 : UInt<2>, vgein : UInt<6>, zero2 : UInt<2>, hu : UInt<1>, spvp : UInt<1>, spv : UInt<1>, gva : UInt<1>, vsbe : UInt<1>, zero1 : UInt<5>}, clock, reset, _reg_hstatus_WIRE reg reg_hgatp : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, clock reg reg_htval : UInt<32>, clock node read_hvip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node read_hvip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node read_hvip_lo_lo = cat(read_hvip_lo_lo_hi, read_hvip_lo_lo_lo) node read_hvip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node read_hvip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node read_hvip_lo_hi = cat(read_hvip_lo_hi_hi, read_hvip_lo_hi_lo) node read_hvip_lo = cat(read_hvip_lo_hi, read_hvip_lo_lo) node read_hvip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node read_hvip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node read_hvip_hi_lo = cat(read_hvip_hi_lo_hi, read_hvip_hi_lo_lo) node read_hvip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node read_hvip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node read_hvip_hi_hi_hi = cat(read_hvip_hi_hi_hi_hi, reg_mip.debug) node read_hvip_hi_hi = cat(read_hvip_hi_hi_hi, read_hvip_hi_hi_lo) node read_hvip_hi = cat(read_hvip_hi_hi, read_hvip_hi_lo) node _read_hvip_T = cat(read_hvip_hi, read_hvip_lo) node read_hvip = and(_read_hvip_T, hs_delegable_interrupts) node read_hie = and(reg_mie, hs_delegable_interrupts) reg reg_vstvec : UInt<32>, clock node _T_9 = bits(reg_vstvec, 0, 0) node _T_10 = mux(_T_9, UInt<7>(0h7e), UInt<2>(0h2)) node _T_11 = and(reg_vstvec, UInt<1>(0h0)) node _T_12 = or(_T_10, _T_11) node _T_13 = not(_T_12) node read_vstvec = and(reg_vstvec, _T_13) reg reg_vsstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}, clock reg reg_vsscratch : UInt<32>, clock reg reg_vsepc : UInt<32>, clock reg reg_vscause : UInt<32>, clock reg reg_vstval : UInt<32>, clock reg reg_vsatp : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, clock reg reg_sepc : UInt<32>, clock reg reg_scause : UInt<32>, clock reg reg_stval : UInt<32>, clock reg reg_sscratch : UInt<32>, clock reg reg_stvec : UInt<32>, clock reg reg_satp : { mode : UInt<1>, asid : UInt<9>, ppn : UInt<22>}, clock regreset reg_wfi : UInt<1>, io.ungated_clock, reset, UInt<1>(0h0) reg reg_fflags : UInt<5>, clock reg reg_frm : UInt<3>, clock reg reg_mtinst_read_pseudo : UInt<1>, clock reg reg_htinst_read_pseudo : UInt<1>, clock node hi_4 = cat(reg_mtinst_read_pseudo, UInt<1>(0h0)) node read_mtinst = cat(hi_4, UInt<12>(0h0)) node hi_5 = cat(reg_htinst_read_pseudo, UInt<1>(0h0)) node read_htinst = cat(hi_5, UInt<12>(0h0)) regreset reg_mcountinhibit : UInt<3>, clock, reset, UInt<3>(0h0) node _io_inhibit_cycle_T = bits(reg_mcountinhibit, 0, 0) connect io.inhibit_cycle, _io_inhibit_cycle_T node x3 = bits(reg_mcountinhibit, 2, 2) regreset small : UInt<6>, clock, reset, UInt<6>(0h0) node nextSmall = add(small, io.retire) node _T_14 = eq(x3, UInt<1>(0h0)) when _T_14 : connect small, nextSmall regreset large : UInt<58>, clock, reset, UInt<58>(0h0) node _large_T = bits(nextSmall, 6, 6) node _large_T_1 = eq(x3, UInt<1>(0h0)) node _large_T_2 = and(_large_T, _large_T_1) when _large_T_2 : node _large_r_T = add(large, UInt<1>(0h1)) node _large_r_T_1 = tail(_large_r_T, 1) connect large, _large_r_T_1 node value = cat(large, small) node x10 = eq(io.csr_stall, UInt<1>(0h0)) node x11 = bits(reg_mcountinhibit, 0, 0) regreset small_1 : UInt<6>, io.ungated_clock, reset, UInt<6>(0h0) node nextSmall_1 = add(small_1, x10) node _T_15 = eq(x11, UInt<1>(0h0)) when _T_15 : connect small_1, nextSmall_1 regreset large_1 : UInt<58>, io.ungated_clock, reset, UInt<58>(0h0) node _large_T_3 = bits(nextSmall_1, 6, 6) node _large_T_4 = eq(x11, UInt<1>(0h0)) node _large_T_5 = and(_large_T_3, _large_T_4) when _large_T_5 : node _large_r_T_2 = add(large_1, UInt<1>(0h1)) node _large_r_T_3 = tail(_large_r_T_2, 1) connect large_1, _large_r_T_3 node value_1 = cat(large_1, small_1) wire mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect mip, reg_mip connect mip.mtip, io.interrupts.mtip connect mip.msip, io.interrupts.msip connect mip.meip, io.interrupts.meip connect mip.rocc, io.rocc_interrupt node read_mip_lo_lo_lo = cat(mip.ssip, mip.usip) node read_mip_lo_lo_hi = cat(mip.msip, mip.vssip) node read_mip_lo_lo = cat(read_mip_lo_lo_hi, read_mip_lo_lo_lo) node read_mip_lo_hi_lo = cat(mip.stip, mip.utip) node read_mip_lo_hi_hi = cat(mip.mtip, mip.vstip) node read_mip_lo_hi = cat(read_mip_lo_hi_hi, read_mip_lo_hi_lo) node read_mip_lo = cat(read_mip_lo_hi, read_mip_lo_lo) node read_mip_hi_lo_lo = cat(mip.seip, mip.ueip) node read_mip_hi_lo_hi = cat(mip.meip, mip.vseip) node read_mip_hi_lo = cat(read_mip_hi_lo_hi, read_mip_hi_lo_lo) node read_mip_hi_hi_lo = cat(mip.rocc, mip.sgeip) node read_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), mip.zero1) node read_mip_hi_hi_hi = cat(read_mip_hi_hi_hi_hi, mip.debug) node read_mip_hi_hi = cat(read_mip_hi_hi_hi, read_mip_hi_hi_lo) node read_mip_hi = cat(read_mip_hi_hi, read_mip_hi_lo) node _read_mip_T = cat(read_mip_hi, read_mip_lo) node read_mip = and(_read_mip_T, supported_interrupts) node read_hip = and(read_mip, hs_delegable_interrupts) node _pending_interrupts_T = and(read_mip, reg_mie) node pending_interrupts = or(UInt<1>(0h0), _pending_interrupts_T) node d_interrupts = shl(io.interrupts.debug, 14) node _m_interrupts_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _m_interrupts_T_1 = or(_m_interrupts_T, reg_mstatus.mie) node _m_interrupts_T_2 = and(reg_rnmie, _m_interrupts_T_1) node _m_interrupts_T_3 = not(pending_interrupts) node _m_interrupts_T_4 = or(_m_interrupts_T_3, read_mideleg) node _m_interrupts_T_5 = not(_m_interrupts_T_4) node m_interrupts = mux(_m_interrupts_T_2, _m_interrupts_T_5, UInt<1>(0h0)) node _s_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_1 = or(reg_mstatus.v, _s_interrupts_T) node _s_interrupts_T_2 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _s_interrupts_T_3 = and(_s_interrupts_T_2, reg_mstatus.sie) node _s_interrupts_T_4 = or(_s_interrupts_T_1, _s_interrupts_T_3) node _s_interrupts_T_5 = and(reg_rnmie, _s_interrupts_T_4) node _s_interrupts_T_6 = and(pending_interrupts, read_mideleg) node _s_interrupts_T_7 = not(read_hideleg) node _s_interrupts_T_8 = and(_s_interrupts_T_6, _s_interrupts_T_7) node s_interrupts = mux(_s_interrupts_T_5, _s_interrupts_T_8, UInt<1>(0h0)) node _vs_interrupts_T = lt(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_1 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _vs_interrupts_T_2 = and(_vs_interrupts_T_1, reg_vsstatus.sie) node _vs_interrupts_T_3 = or(_vs_interrupts_T, _vs_interrupts_T_2) node _vs_interrupts_T_4 = and(reg_mstatus.v, _vs_interrupts_T_3) node _vs_interrupts_T_5 = and(reg_rnmie, _vs_interrupts_T_4) node _vs_interrupts_T_6 = and(pending_interrupts, read_hideleg) node vs_interrupts = mux(_vs_interrupts_T_5, _vs_interrupts_T_6, UInt<1>(0h0)) node _any_T = bits(d_interrupts, 14, 14) node _any_T_1 = bits(d_interrupts, 13, 13) node _any_T_2 = bits(d_interrupts, 12, 12) node _any_T_3 = bits(d_interrupts, 11, 11) node _any_T_4 = bits(d_interrupts, 3, 3) node _any_T_5 = bits(d_interrupts, 7, 7) node _any_T_6 = bits(d_interrupts, 9, 9) node _any_T_7 = bits(d_interrupts, 1, 1) node _any_T_8 = bits(d_interrupts, 5, 5) node _any_T_9 = bits(d_interrupts, 10, 10) node _any_T_10 = bits(d_interrupts, 2, 2) node _any_T_11 = bits(d_interrupts, 6, 6) node _any_T_12 = bits(d_interrupts, 8, 8) node _any_T_13 = bits(d_interrupts, 0, 0) node _any_T_14 = bits(d_interrupts, 4, 4) node _any_T_15 = bits(m_interrupts, 15, 15) node _any_T_16 = bits(m_interrupts, 14, 14) node _any_T_17 = bits(m_interrupts, 13, 13) node _any_T_18 = bits(m_interrupts, 12, 12) node _any_T_19 = bits(m_interrupts, 11, 11) node _any_T_20 = bits(m_interrupts, 3, 3) node _any_T_21 = bits(m_interrupts, 7, 7) node _any_T_22 = bits(m_interrupts, 9, 9) node _any_T_23 = bits(m_interrupts, 1, 1) node _any_T_24 = bits(m_interrupts, 5, 5) node _any_T_25 = bits(m_interrupts, 10, 10) node _any_T_26 = bits(m_interrupts, 2, 2) node _any_T_27 = bits(m_interrupts, 6, 6) node _any_T_28 = bits(m_interrupts, 8, 8) node _any_T_29 = bits(m_interrupts, 0, 0) node _any_T_30 = bits(m_interrupts, 4, 4) node _any_T_31 = bits(s_interrupts, 15, 15) node _any_T_32 = bits(s_interrupts, 14, 14) node _any_T_33 = bits(s_interrupts, 13, 13) node _any_T_34 = bits(s_interrupts, 12, 12) node _any_T_35 = bits(s_interrupts, 11, 11) node _any_T_36 = bits(s_interrupts, 3, 3) node _any_T_37 = bits(s_interrupts, 7, 7) node _any_T_38 = bits(s_interrupts, 9, 9) node _any_T_39 = bits(s_interrupts, 1, 1) node _any_T_40 = bits(s_interrupts, 5, 5) node _any_T_41 = bits(s_interrupts, 10, 10) node _any_T_42 = bits(s_interrupts, 2, 2) node _any_T_43 = bits(s_interrupts, 6, 6) node _any_T_44 = bits(s_interrupts, 8, 8) node _any_T_45 = bits(s_interrupts, 0, 0) node _any_T_46 = bits(s_interrupts, 4, 4) node _any_T_47 = bits(vs_interrupts, 15, 15) node _any_T_48 = bits(vs_interrupts, 14, 14) node _any_T_49 = bits(vs_interrupts, 13, 13) node _any_T_50 = bits(vs_interrupts, 12, 12) node _any_T_51 = bits(vs_interrupts, 11, 11) node _any_T_52 = bits(vs_interrupts, 3, 3) node _any_T_53 = bits(vs_interrupts, 7, 7) node _any_T_54 = bits(vs_interrupts, 9, 9) node _any_T_55 = bits(vs_interrupts, 1, 1) node _any_T_56 = bits(vs_interrupts, 5, 5) node _any_T_57 = bits(vs_interrupts, 10, 10) node _any_T_58 = bits(vs_interrupts, 2, 2) node _any_T_59 = bits(vs_interrupts, 6, 6) node _any_T_60 = bits(vs_interrupts, 8, 8) node _any_T_61 = bits(vs_interrupts, 0, 0) node _any_T_62 = bits(vs_interrupts, 4, 4) node _any_T_63 = or(_any_T, _any_T_1) node _any_T_64 = or(_any_T_63, _any_T_2) node _any_T_65 = or(_any_T_64, _any_T_3) node _any_T_66 = or(_any_T_65, _any_T_4) node _any_T_67 = or(_any_T_66, _any_T_5) node _any_T_68 = or(_any_T_67, _any_T_6) node _any_T_69 = or(_any_T_68, _any_T_7) node _any_T_70 = or(_any_T_69, _any_T_8) node _any_T_71 = or(_any_T_70, _any_T_9) node _any_T_72 = or(_any_T_71, _any_T_10) node _any_T_73 = or(_any_T_72, _any_T_11) node _any_T_74 = or(_any_T_73, _any_T_12) node _any_T_75 = or(_any_T_74, _any_T_13) node _any_T_76 = or(_any_T_75, _any_T_14) node _any_T_77 = or(_any_T_76, UInt<1>(0h0)) node _any_T_78 = or(_any_T_77, _any_T_15) node _any_T_79 = or(_any_T_78, _any_T_16) node _any_T_80 = or(_any_T_79, _any_T_17) node _any_T_81 = or(_any_T_80, _any_T_18) node _any_T_82 = or(_any_T_81, _any_T_19) node _any_T_83 = or(_any_T_82, _any_T_20) node _any_T_84 = or(_any_T_83, _any_T_21) node _any_T_85 = or(_any_T_84, _any_T_22) node _any_T_86 = or(_any_T_85, _any_T_23) node _any_T_87 = or(_any_T_86, _any_T_24) node _any_T_88 = or(_any_T_87, _any_T_25) node _any_T_89 = or(_any_T_88, _any_T_26) node _any_T_90 = or(_any_T_89, _any_T_27) node _any_T_91 = or(_any_T_90, _any_T_28) node _any_T_92 = or(_any_T_91, _any_T_29) node _any_T_93 = or(_any_T_92, _any_T_30) node _any_T_94 = or(_any_T_93, _any_T_31) node _any_T_95 = or(_any_T_94, _any_T_32) node _any_T_96 = or(_any_T_95, _any_T_33) node _any_T_97 = or(_any_T_96, _any_T_34) node _any_T_98 = or(_any_T_97, _any_T_35) node _any_T_99 = or(_any_T_98, _any_T_36) node _any_T_100 = or(_any_T_99, _any_T_37) node _any_T_101 = or(_any_T_100, _any_T_38) node _any_T_102 = or(_any_T_101, _any_T_39) node _any_T_103 = or(_any_T_102, _any_T_40) node _any_T_104 = or(_any_T_103, _any_T_41) node _any_T_105 = or(_any_T_104, _any_T_42) node _any_T_106 = or(_any_T_105, _any_T_43) node _any_T_107 = or(_any_T_106, _any_T_44) node _any_T_108 = or(_any_T_107, _any_T_45) node _any_T_109 = or(_any_T_108, _any_T_46) node _any_T_110 = or(_any_T_109, _any_T_47) node _any_T_111 = or(_any_T_110, _any_T_48) node _any_T_112 = or(_any_T_111, _any_T_49) node _any_T_113 = or(_any_T_112, _any_T_50) node _any_T_114 = or(_any_T_113, _any_T_51) node _any_T_115 = or(_any_T_114, _any_T_52) node _any_T_116 = or(_any_T_115, _any_T_53) node _any_T_117 = or(_any_T_116, _any_T_54) node _any_T_118 = or(_any_T_117, _any_T_55) node _any_T_119 = or(_any_T_118, _any_T_56) node _any_T_120 = or(_any_T_119, _any_T_57) node _any_T_121 = or(_any_T_120, _any_T_58) node _any_T_122 = or(_any_T_121, _any_T_59) node _any_T_123 = or(_any_T_122, _any_T_60) node _any_T_124 = or(_any_T_123, _any_T_61) node anyInterrupt = or(_any_T_124, _any_T_62) node _which_T = bits(d_interrupts, 14, 14) node _which_T_1 = bits(d_interrupts, 13, 13) node _which_T_2 = bits(d_interrupts, 12, 12) node _which_T_3 = bits(d_interrupts, 11, 11) node _which_T_4 = bits(d_interrupts, 3, 3) node _which_T_5 = bits(d_interrupts, 7, 7) node _which_T_6 = bits(d_interrupts, 9, 9) node _which_T_7 = bits(d_interrupts, 1, 1) node _which_T_8 = bits(d_interrupts, 5, 5) node _which_T_9 = bits(d_interrupts, 10, 10) node _which_T_10 = bits(d_interrupts, 2, 2) node _which_T_11 = bits(d_interrupts, 6, 6) node _which_T_12 = bits(d_interrupts, 8, 8) node _which_T_13 = bits(d_interrupts, 0, 0) node _which_T_14 = bits(d_interrupts, 4, 4) node _which_T_15 = bits(m_interrupts, 15, 15) node _which_T_16 = bits(m_interrupts, 14, 14) node _which_T_17 = bits(m_interrupts, 13, 13) node _which_T_18 = bits(m_interrupts, 12, 12) node _which_T_19 = bits(m_interrupts, 11, 11) node _which_T_20 = bits(m_interrupts, 3, 3) node _which_T_21 = bits(m_interrupts, 7, 7) node _which_T_22 = bits(m_interrupts, 9, 9) node _which_T_23 = bits(m_interrupts, 1, 1) node _which_T_24 = bits(m_interrupts, 5, 5) node _which_T_25 = bits(m_interrupts, 10, 10) node _which_T_26 = bits(m_interrupts, 2, 2) node _which_T_27 = bits(m_interrupts, 6, 6) node _which_T_28 = bits(m_interrupts, 8, 8) node _which_T_29 = bits(m_interrupts, 0, 0) node _which_T_30 = bits(m_interrupts, 4, 4) node _which_T_31 = bits(s_interrupts, 15, 15) node _which_T_32 = bits(s_interrupts, 14, 14) node _which_T_33 = bits(s_interrupts, 13, 13) node _which_T_34 = bits(s_interrupts, 12, 12) node _which_T_35 = bits(s_interrupts, 11, 11) node _which_T_36 = bits(s_interrupts, 3, 3) node _which_T_37 = bits(s_interrupts, 7, 7) node _which_T_38 = bits(s_interrupts, 9, 9) node _which_T_39 = bits(s_interrupts, 1, 1) node _which_T_40 = bits(s_interrupts, 5, 5) node _which_T_41 = bits(s_interrupts, 10, 10) node _which_T_42 = bits(s_interrupts, 2, 2) node _which_T_43 = bits(s_interrupts, 6, 6) node _which_T_44 = bits(s_interrupts, 8, 8) node _which_T_45 = bits(s_interrupts, 0, 0) node _which_T_46 = bits(s_interrupts, 4, 4) node _which_T_47 = bits(vs_interrupts, 15, 15) node _which_T_48 = bits(vs_interrupts, 14, 14) node _which_T_49 = bits(vs_interrupts, 13, 13) node _which_T_50 = bits(vs_interrupts, 12, 12) node _which_T_51 = bits(vs_interrupts, 11, 11) node _which_T_52 = bits(vs_interrupts, 3, 3) node _which_T_53 = bits(vs_interrupts, 7, 7) node _which_T_54 = bits(vs_interrupts, 9, 9) node _which_T_55 = bits(vs_interrupts, 1, 1) node _which_T_56 = bits(vs_interrupts, 5, 5) node _which_T_57 = bits(vs_interrupts, 10, 10) node _which_T_58 = bits(vs_interrupts, 2, 2) node _which_T_59 = bits(vs_interrupts, 6, 6) node _which_T_60 = bits(vs_interrupts, 8, 8) node _which_T_61 = bits(vs_interrupts, 0, 0) node _which_T_62 = bits(vs_interrupts, 4, 4) node _which_T_63 = mux(_which_T_61, UInt<1>(0h0), UInt<3>(0h4)) node _which_T_64 = mux(_which_T_60, UInt<4>(0h8), _which_T_63) node _which_T_65 = mux(_which_T_59, UInt<3>(0h6), _which_T_64) node _which_T_66 = mux(_which_T_58, UInt<2>(0h2), _which_T_65) node _which_T_67 = mux(_which_T_57, UInt<4>(0ha), _which_T_66) node _which_T_68 = mux(_which_T_56, UInt<3>(0h5), _which_T_67) node _which_T_69 = mux(_which_T_55, UInt<1>(0h1), _which_T_68) node _which_T_70 = mux(_which_T_54, UInt<4>(0h9), _which_T_69) node _which_T_71 = mux(_which_T_53, UInt<3>(0h7), _which_T_70) node _which_T_72 = mux(_which_T_52, UInt<2>(0h3), _which_T_71) node _which_T_73 = mux(_which_T_51, UInt<4>(0hb), _which_T_72) node _which_T_74 = mux(_which_T_50, UInt<4>(0hc), _which_T_73) node _which_T_75 = mux(_which_T_49, UInt<4>(0hd), _which_T_74) node _which_T_76 = mux(_which_T_48, UInt<4>(0he), _which_T_75) node _which_T_77 = mux(_which_T_47, UInt<4>(0hf), _which_T_76) node _which_T_78 = mux(_which_T_46, UInt<3>(0h4), _which_T_77) node _which_T_79 = mux(_which_T_45, UInt<1>(0h0), _which_T_78) node _which_T_80 = mux(_which_T_44, UInt<4>(0h8), _which_T_79) node _which_T_81 = mux(_which_T_43, UInt<3>(0h6), _which_T_80) node _which_T_82 = mux(_which_T_42, UInt<2>(0h2), _which_T_81) node _which_T_83 = mux(_which_T_41, UInt<4>(0ha), _which_T_82) node _which_T_84 = mux(_which_T_40, UInt<3>(0h5), _which_T_83) node _which_T_85 = mux(_which_T_39, UInt<1>(0h1), _which_T_84) node _which_T_86 = mux(_which_T_38, UInt<4>(0h9), _which_T_85) node _which_T_87 = mux(_which_T_37, UInt<3>(0h7), _which_T_86) node _which_T_88 = mux(_which_T_36, UInt<2>(0h3), _which_T_87) node _which_T_89 = mux(_which_T_35, UInt<4>(0hb), _which_T_88) node _which_T_90 = mux(_which_T_34, UInt<4>(0hc), _which_T_89) node _which_T_91 = mux(_which_T_33, UInt<4>(0hd), _which_T_90) node _which_T_92 = mux(_which_T_32, UInt<4>(0he), _which_T_91) node _which_T_93 = mux(_which_T_31, UInt<4>(0hf), _which_T_92) node _which_T_94 = mux(_which_T_30, UInt<3>(0h4), _which_T_93) node _which_T_95 = mux(_which_T_29, UInt<1>(0h0), _which_T_94) node _which_T_96 = mux(_which_T_28, UInt<4>(0h8), _which_T_95) node _which_T_97 = mux(_which_T_27, UInt<3>(0h6), _which_T_96) node _which_T_98 = mux(_which_T_26, UInt<2>(0h2), _which_T_97) node _which_T_99 = mux(_which_T_25, UInt<4>(0ha), _which_T_98) node _which_T_100 = mux(_which_T_24, UInt<3>(0h5), _which_T_99) node _which_T_101 = mux(_which_T_23, UInt<1>(0h1), _which_T_100) node _which_T_102 = mux(_which_T_22, UInt<4>(0h9), _which_T_101) node _which_T_103 = mux(_which_T_21, UInt<3>(0h7), _which_T_102) node _which_T_104 = mux(_which_T_20, UInt<2>(0h3), _which_T_103) node _which_T_105 = mux(_which_T_19, UInt<4>(0hb), _which_T_104) node _which_T_106 = mux(_which_T_18, UInt<4>(0hc), _which_T_105) node _which_T_107 = mux(_which_T_17, UInt<4>(0hd), _which_T_106) node _which_T_108 = mux(_which_T_16, UInt<4>(0he), _which_T_107) node _which_T_109 = mux(_which_T_15, UInt<4>(0hf), _which_T_108) node _which_T_110 = mux(UInt<1>(0h0), UInt<1>(0h0), _which_T_109) node _which_T_111 = mux(_which_T_14, UInt<3>(0h4), _which_T_110) node _which_T_112 = mux(_which_T_13, UInt<1>(0h0), _which_T_111) node _which_T_113 = mux(_which_T_12, UInt<4>(0h8), _which_T_112) node _which_T_114 = mux(_which_T_11, UInt<3>(0h6), _which_T_113) node _which_T_115 = mux(_which_T_10, UInt<2>(0h2), _which_T_114) node _which_T_116 = mux(_which_T_9, UInt<4>(0ha), _which_T_115) node _which_T_117 = mux(_which_T_8, UInt<3>(0h5), _which_T_116) node _which_T_118 = mux(_which_T_7, UInt<1>(0h1), _which_T_117) node _which_T_119 = mux(_which_T_6, UInt<4>(0h9), _which_T_118) node _which_T_120 = mux(_which_T_5, UInt<3>(0h7), _which_T_119) node _which_T_121 = mux(_which_T_4, UInt<2>(0h3), _which_T_120) node _which_T_122 = mux(_which_T_3, UInt<4>(0hb), _which_T_121) node _which_T_123 = mux(_which_T_2, UInt<4>(0hc), _which_T_122) node _which_T_124 = mux(_which_T_1, UInt<4>(0hd), _which_T_123) node whichInterrupt = mux(_which_T, UInt<4>(0he), _which_T_124) node _interruptCause_T = shl(UInt<1>(0h0), 30) node _interruptCause_T_1 = add(UInt<32>(0h80000000), _interruptCause_T) node _interruptCause_T_2 = tail(_interruptCause_T_1, 1) node _interruptCause_T_3 = add(_interruptCause_T_2, whichInterrupt) node interruptCause = tail(_interruptCause_T_3, 1) node _io_interrupt_T = eq(io.singleStep, UInt<1>(0h0)) node _io_interrupt_T_1 = and(anyInterrupt, _io_interrupt_T) node _io_interrupt_T_2 = or(_io_interrupt_T_1, reg_singleStepped) node _io_interrupt_T_3 = or(reg_debug, io.status.cease) node _io_interrupt_T_4 = eq(_io_interrupt_T_3, UInt<1>(0h0)) node _io_interrupt_T_5 = and(_io_interrupt_T_2, _io_interrupt_T_4) connect io.interrupt, _io_interrupt_T_5 connect io.interrupt_cause, interruptCause connect io.bp[0], reg_bp[0] connect io.mcontext, UInt<1>(0h0) connect io.scontext, UInt<1>(0h0) node _io_fiom_T = lt(reg_mstatus.prv, UInt<2>(0h3)) node _io_fiom_T_1 = and(_io_fiom_T, reg_menvcfg.fiom) node _io_fiom_T_2 = lt(reg_mstatus.prv, UInt<1>(0h1)) node _io_fiom_T_3 = and(_io_fiom_T_2, reg_senvcfg.fiom) node _io_fiom_T_4 = or(_io_fiom_T_1, _io_fiom_T_3) node _io_fiom_T_5 = and(reg_mstatus.v, reg_henvcfg.fiom) node _io_fiom_T_6 = or(_io_fiom_T_4, _io_fiom_T_5) connect io.fiom, _io_fiom_T_6 wire pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp.cfg, reg_pmp[0].cfg connect pmp.addr, reg_pmp[0].addr node _pmp_mask_base_T = bits(pmp.cfg.a, 0, 0) node _pmp_mask_base_T_1 = cat(pmp.addr, _pmp_mask_base_T) node _pmp_mask_base_T_2 = shr(UInt<2>(0h3), 2) node pmp_mask_base = or(_pmp_mask_base_T_1, _pmp_mask_base_T_2) node _pmp_mask_T = add(pmp_mask_base, UInt<1>(0h1)) node _pmp_mask_T_1 = tail(_pmp_mask_T, 1) node _pmp_mask_T_2 = not(_pmp_mask_T_1) node _pmp_mask_T_3 = and(pmp_mask_base, _pmp_mask_T_2) node _pmp_mask_T_4 = cat(_pmp_mask_T_3, UInt<2>(0h3)) connect pmp.mask, _pmp_mask_T_4 wire pmp_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_1.cfg, reg_pmp[1].cfg connect pmp_1.addr, reg_pmp[1].addr node _pmp_mask_base_T_3 = bits(pmp_1.cfg.a, 0, 0) node _pmp_mask_base_T_4 = cat(pmp_1.addr, _pmp_mask_base_T_3) node _pmp_mask_base_T_5 = shr(UInt<2>(0h3), 2) node pmp_mask_base_1 = or(_pmp_mask_base_T_4, _pmp_mask_base_T_5) node _pmp_mask_T_5 = add(pmp_mask_base_1, UInt<1>(0h1)) node _pmp_mask_T_6 = tail(_pmp_mask_T_5, 1) node _pmp_mask_T_7 = not(_pmp_mask_T_6) node _pmp_mask_T_8 = and(pmp_mask_base_1, _pmp_mask_T_7) node _pmp_mask_T_9 = cat(_pmp_mask_T_8, UInt<2>(0h3)) connect pmp_1.mask, _pmp_mask_T_9 wire pmp_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_2.cfg, reg_pmp[2].cfg connect pmp_2.addr, reg_pmp[2].addr node _pmp_mask_base_T_6 = bits(pmp_2.cfg.a, 0, 0) node _pmp_mask_base_T_7 = cat(pmp_2.addr, _pmp_mask_base_T_6) node _pmp_mask_base_T_8 = shr(UInt<2>(0h3), 2) node pmp_mask_base_2 = or(_pmp_mask_base_T_7, _pmp_mask_base_T_8) node _pmp_mask_T_10 = add(pmp_mask_base_2, UInt<1>(0h1)) node _pmp_mask_T_11 = tail(_pmp_mask_T_10, 1) node _pmp_mask_T_12 = not(_pmp_mask_T_11) node _pmp_mask_T_13 = and(pmp_mask_base_2, _pmp_mask_T_12) node _pmp_mask_T_14 = cat(_pmp_mask_T_13, UInt<2>(0h3)) connect pmp_2.mask, _pmp_mask_T_14 wire pmp_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_3.cfg, reg_pmp[3].cfg connect pmp_3.addr, reg_pmp[3].addr node _pmp_mask_base_T_9 = bits(pmp_3.cfg.a, 0, 0) node _pmp_mask_base_T_10 = cat(pmp_3.addr, _pmp_mask_base_T_9) node _pmp_mask_base_T_11 = shr(UInt<2>(0h3), 2) node pmp_mask_base_3 = or(_pmp_mask_base_T_10, _pmp_mask_base_T_11) node _pmp_mask_T_15 = add(pmp_mask_base_3, UInt<1>(0h1)) node _pmp_mask_T_16 = tail(_pmp_mask_T_15, 1) node _pmp_mask_T_17 = not(_pmp_mask_T_16) node _pmp_mask_T_18 = and(pmp_mask_base_3, _pmp_mask_T_17) node _pmp_mask_T_19 = cat(_pmp_mask_T_18, UInt<2>(0h3)) connect pmp_3.mask, _pmp_mask_T_19 wire pmp_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_4.cfg, reg_pmp[4].cfg connect pmp_4.addr, reg_pmp[4].addr node _pmp_mask_base_T_12 = bits(pmp_4.cfg.a, 0, 0) node _pmp_mask_base_T_13 = cat(pmp_4.addr, _pmp_mask_base_T_12) node _pmp_mask_base_T_14 = shr(UInt<2>(0h3), 2) node pmp_mask_base_4 = or(_pmp_mask_base_T_13, _pmp_mask_base_T_14) node _pmp_mask_T_20 = add(pmp_mask_base_4, UInt<1>(0h1)) node _pmp_mask_T_21 = tail(_pmp_mask_T_20, 1) node _pmp_mask_T_22 = not(_pmp_mask_T_21) node _pmp_mask_T_23 = and(pmp_mask_base_4, _pmp_mask_T_22) node _pmp_mask_T_24 = cat(_pmp_mask_T_23, UInt<2>(0h3)) connect pmp_4.mask, _pmp_mask_T_24 wire pmp_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_5.cfg, reg_pmp[5].cfg connect pmp_5.addr, reg_pmp[5].addr node _pmp_mask_base_T_15 = bits(pmp_5.cfg.a, 0, 0) node _pmp_mask_base_T_16 = cat(pmp_5.addr, _pmp_mask_base_T_15) node _pmp_mask_base_T_17 = shr(UInt<2>(0h3), 2) node pmp_mask_base_5 = or(_pmp_mask_base_T_16, _pmp_mask_base_T_17) node _pmp_mask_T_25 = add(pmp_mask_base_5, UInt<1>(0h1)) node _pmp_mask_T_26 = tail(_pmp_mask_T_25, 1) node _pmp_mask_T_27 = not(_pmp_mask_T_26) node _pmp_mask_T_28 = and(pmp_mask_base_5, _pmp_mask_T_27) node _pmp_mask_T_29 = cat(_pmp_mask_T_28, UInt<2>(0h3)) connect pmp_5.mask, _pmp_mask_T_29 wire pmp_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_6.cfg, reg_pmp[6].cfg connect pmp_6.addr, reg_pmp[6].addr node _pmp_mask_base_T_18 = bits(pmp_6.cfg.a, 0, 0) node _pmp_mask_base_T_19 = cat(pmp_6.addr, _pmp_mask_base_T_18) node _pmp_mask_base_T_20 = shr(UInt<2>(0h3), 2) node pmp_mask_base_6 = or(_pmp_mask_base_T_19, _pmp_mask_base_T_20) node _pmp_mask_T_30 = add(pmp_mask_base_6, UInt<1>(0h1)) node _pmp_mask_T_31 = tail(_pmp_mask_T_30, 1) node _pmp_mask_T_32 = not(_pmp_mask_T_31) node _pmp_mask_T_33 = and(pmp_mask_base_6, _pmp_mask_T_32) node _pmp_mask_T_34 = cat(_pmp_mask_T_33, UInt<2>(0h3)) connect pmp_6.mask, _pmp_mask_T_34 wire pmp_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp_7.cfg, reg_pmp[7].cfg connect pmp_7.addr, reg_pmp[7].addr node _pmp_mask_base_T_21 = bits(pmp_7.cfg.a, 0, 0) node _pmp_mask_base_T_22 = cat(pmp_7.addr, _pmp_mask_base_T_21) node _pmp_mask_base_T_23 = shr(UInt<2>(0h3), 2) node pmp_mask_base_7 = or(_pmp_mask_base_T_22, _pmp_mask_base_T_23) node _pmp_mask_T_35 = add(pmp_mask_base_7, UInt<1>(0h1)) node _pmp_mask_T_36 = tail(_pmp_mask_T_35, 1) node _pmp_mask_T_37 = not(_pmp_mask_T_36) node _pmp_mask_T_38 = and(pmp_mask_base_7, _pmp_mask_T_37) node _pmp_mask_T_39 = cat(_pmp_mask_T_38, UInt<2>(0h3)) connect pmp_7.mask, _pmp_mask_T_39 connect io.pmp[0], pmp connect io.pmp[1], pmp_1 connect io.pmp[2], pmp_2 connect io.pmp[3], pmp_3 connect io.pmp[4], pmp_4 connect io.pmp[5], pmp_5 connect io.pmp[6], pmp_6 connect io.pmp[7], pmp_7 regreset reg_misa : UInt, clock, reset, UInt<31>(0h40801105) node read_mstatus_lo_lo_lo_lo = cat(io.status.sie, io.status.uie) node read_mstatus_lo_lo_lo_hi = cat(io.status.mie, io.status.hie) node read_mstatus_lo_lo_lo = cat(read_mstatus_lo_lo_lo_hi, read_mstatus_lo_lo_lo_lo) node read_mstatus_lo_lo_hi_lo = cat(io.status.spie, io.status.upie) node read_mstatus_lo_lo_hi_hi_hi = cat(io.status.spp, io.status.mpie) node read_mstatus_lo_lo_hi_hi = cat(read_mstatus_lo_lo_hi_hi_hi, io.status.ube) node read_mstatus_lo_lo_hi = cat(read_mstatus_lo_lo_hi_hi, read_mstatus_lo_lo_hi_lo) node read_mstatus_lo_lo = cat(read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo) node read_mstatus_lo_hi_lo_lo = cat(io.status.mpp, io.status.vs) node read_mstatus_lo_hi_lo_hi = cat(io.status.xs, io.status.fs) node read_mstatus_lo_hi_lo = cat(read_mstatus_lo_hi_lo_hi, read_mstatus_lo_hi_lo_lo) node read_mstatus_lo_hi_hi_lo = cat(io.status.sum, io.status.mprv) node read_mstatus_lo_hi_hi_hi_hi = cat(io.status.tw, io.status.tvm) node read_mstatus_lo_hi_hi_hi = cat(read_mstatus_lo_hi_hi_hi_hi, io.status.mxr) node read_mstatus_lo_hi_hi = cat(read_mstatus_lo_hi_hi_hi, read_mstatus_lo_hi_hi_lo) node read_mstatus_lo_hi = cat(read_mstatus_lo_hi_hi, read_mstatus_lo_hi_lo) node read_mstatus_lo = cat(read_mstatus_lo_hi, read_mstatus_lo_lo) node read_mstatus_hi_lo_lo_lo = cat(io.status.zero1, io.status.tsr) node read_mstatus_hi_lo_lo_hi = cat(io.status.uxl, io.status.sd_rv32) node read_mstatus_hi_lo_lo = cat(read_mstatus_hi_lo_lo_hi, read_mstatus_hi_lo_lo_lo) node read_mstatus_hi_lo_hi_lo = cat(io.status.sbe, io.status.sxl) node read_mstatus_hi_lo_hi_hi_hi = cat(io.status.mpv, io.status.gva) node read_mstatus_hi_lo_hi_hi = cat(read_mstatus_hi_lo_hi_hi_hi, io.status.mbe) node read_mstatus_hi_lo_hi = cat(read_mstatus_hi_lo_hi_hi, read_mstatus_hi_lo_hi_lo) node read_mstatus_hi_lo = cat(read_mstatus_hi_lo_hi, read_mstatus_hi_lo_lo) node read_mstatus_hi_hi_lo_lo = cat(io.status.sd, io.status.zero2) node read_mstatus_hi_hi_lo_hi_hi = cat(io.status.dv, io.status.prv) node read_mstatus_hi_hi_lo_hi = cat(read_mstatus_hi_hi_lo_hi_hi, io.status.v) node read_mstatus_hi_hi_lo = cat(read_mstatus_hi_hi_lo_hi, read_mstatus_hi_hi_lo_lo) node read_mstatus_hi_hi_hi_lo = cat(io.status.isa, io.status.dprv) node read_mstatus_hi_hi_hi_hi_hi = cat(io.status.debug, io.status.cease) node read_mstatus_hi_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi_hi, io.status.wfi) node read_mstatus_hi_hi_hi = cat(read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo) node read_mstatus_hi_hi = cat(read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo) node read_mstatus_hi = cat(read_mstatus_hi_hi, read_mstatus_hi_lo) node _read_mstatus_T = cat(read_mstatus_hi, read_mstatus_lo) node read_mstatus = bits(_read_mstatus_T, 31, 0) node _read_mtvec_T = bits(reg_mtvec, 0, 0) node _read_mtvec_T_1 = mux(_read_mtvec_T, UInt<7>(0h7e), UInt<2>(0h2)) node _read_mtvec_T_2 = and(reg_mtvec, UInt<1>(0h0)) node _read_mtvec_T_3 = or(_read_mtvec_T_1, _read_mtvec_T_2) node _read_mtvec_T_4 = not(_read_mtvec_T_3) node read_mtvec = and(reg_mtvec, _read_mtvec_T_4) node _read_stvec_T = bits(reg_stvec, 0, 0) node _read_stvec_T_1 = mux(_read_stvec_T, UInt<7>(0h7e), UInt<2>(0h2)) node _read_stvec_T_2 = and(reg_stvec, UInt<1>(0h0)) node _read_stvec_T_3 = or(_read_stvec_T_1, _read_stvec_T_2) node _read_stvec_T_4 = not(_read_stvec_T_3) node read_stvec = and(reg_stvec, _read_stvec_T_4) node read_mapping_lo_lo_hi = cat(reg_bp[reg_tselect].control.x, reg_bp[reg_tselect].control.w) node read_mapping_lo_lo = cat(read_mapping_lo_lo_hi, reg_bp[reg_tselect].control.r) node read_mapping_lo_hi_lo = cat(reg_bp[reg_tselect].control.s, reg_bp[reg_tselect].control.u) node read_mapping_lo_hi_hi = cat(reg_bp[reg_tselect].control.m, reg_bp[reg_tselect].control.h) node read_mapping_lo_hi = cat(read_mapping_lo_hi_hi, read_mapping_lo_hi_lo) node read_mapping_lo = cat(read_mapping_lo_hi, read_mapping_lo_lo) node read_mapping_hi_lo_lo = cat(reg_bp[reg_tselect].control.zero, reg_bp[reg_tselect].control.tmatch) node read_mapping_hi_lo_hi = cat(reg_bp[reg_tselect].control.action, reg_bp[reg_tselect].control.chain) node read_mapping_hi_lo = cat(read_mapping_hi_lo_hi, read_mapping_hi_lo_lo) node read_mapping_hi_hi_lo = cat(reg_bp[reg_tselect].control.maskmax, reg_bp[reg_tselect].control.reserved) node read_mapping_hi_hi_hi = cat(reg_bp[reg_tselect].control.ttype, reg_bp[reg_tselect].control.dmode) node read_mapping_hi_hi = cat(read_mapping_hi_hi_hi, read_mapping_hi_hi_lo) node read_mapping_hi = cat(read_mapping_hi_hi, read_mapping_hi_lo) node read_mapping_1_2 = cat(read_mapping_hi, read_mapping_lo) node read_mapping_lo_hi_1 = cat(reg_bp[reg_tselect].textra.svalue, reg_bp[reg_tselect].textra.pad1) node read_mapping_lo_1 = cat(read_mapping_lo_hi_1, reg_bp[reg_tselect].textra.sselect) node read_mapping_hi_hi_1 = cat(reg_bp[reg_tselect].textra.mvalue, reg_bp[reg_tselect].textra.mselect) node read_mapping_hi_1 = cat(read_mapping_hi_hi_1, reg_bp[reg_tselect].textra.pad2) node read_mapping_3_2 = cat(read_mapping_hi_1, read_mapping_lo_1) node _read_mapping_T = not(reg_mepc) node _read_mapping_T_1 = bits(reg_misa, 2, 2) node _read_mapping_T_2 = mux(_read_mapping_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _read_mapping_T_3 = or(_read_mapping_T, _read_mapping_T_2) node read_mapping_10_2 = not(_read_mapping_T_3) node debug_csrs_lo_lo_hi = cat(reg_dcsr.zero1, reg_dcsr.step) node debug_csrs_lo_lo = cat(debug_csrs_lo_lo_hi, reg_dcsr.prv) node debug_csrs_lo_hi_lo = cat(reg_dcsr.cause, reg_dcsr.v) node debug_csrs_lo_hi_hi = cat(reg_dcsr.stopcycle, reg_dcsr.stoptime) node debug_csrs_lo_hi = cat(debug_csrs_lo_hi_hi, debug_csrs_lo_hi_lo) node debug_csrs_lo = cat(debug_csrs_lo_hi, debug_csrs_lo_lo) node debug_csrs_hi_lo_lo = cat(reg_dcsr.ebreaku, reg_dcsr.zero2) node debug_csrs_hi_lo_hi = cat(reg_dcsr.ebreakh, reg_dcsr.ebreaks) node debug_csrs_hi_lo = cat(debug_csrs_hi_lo_hi, debug_csrs_hi_lo_lo) node debug_csrs_hi_hi_lo = cat(reg_dcsr.zero3, reg_dcsr.ebreakm) node debug_csrs_hi_hi_hi = cat(reg_dcsr.xdebugver, reg_dcsr.zero4) node debug_csrs_hi_hi = cat(debug_csrs_hi_hi_hi, debug_csrs_hi_hi_lo) node debug_csrs_hi = cat(debug_csrs_hi_hi, debug_csrs_hi_lo) node debug_csrs_0_2 = cat(debug_csrs_hi, debug_csrs_lo) node _debug_csrs_T = not(reg_dpc) node _debug_csrs_T_1 = bits(reg_misa, 2, 2) node _debug_csrs_T_2 = mux(_debug_csrs_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _debug_csrs_T_3 = or(_debug_csrs_T, _debug_csrs_T_2) node debug_csrs_1_2 = not(_debug_csrs_T_3) wire _read_mnstatus_WIRE : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect _read_mnstatus_WIRE.zero1, UInt<3>(0h0) connect _read_mnstatus_WIRE.mie, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero2, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpv, UInt<1>(0h0) connect _read_mnstatus_WIRE.zero3, UInt<3>(0h0) connect _read_mnstatus_WIRE.mpp, UInt<2>(0h0) wire read_mnstatus : { mpp : UInt<2>, zero3 : UInt<3>, mpv : UInt<1>, zero2 : UInt<3>, mie : UInt<1>, zero1 : UInt<3>} connect read_mnstatus, _read_mnstatus_WIRE connect read_mnstatus.mpp, reg_mnstatus.mpp connect read_mnstatus.mpv, reg_mnstatus.mpv connect read_mnstatus.mie, reg_rnmie node read_fcsr = cat(reg_frm, reg_fflags) node read_vcsr = cat(UInt<1>(0h0), UInt<1>(0h0)) node _T_16 = shr(UInt<1>(0h0), 32) node _T_17 = shr(UInt<1>(0h0), 32) node _T_18 = shr(UInt<1>(0h0), 32) node _T_19 = shr(UInt<1>(0h0), 32) node _T_20 = shr(UInt<1>(0h0), 32) node _T_21 = shr(UInt<1>(0h0), 32) node _T_22 = shr(UInt<1>(0h0), 32) node _T_23 = shr(UInt<1>(0h0), 32) node _T_24 = shr(UInt<1>(0h0), 32) node _T_25 = shr(UInt<1>(0h0), 32) node _T_26 = shr(UInt<1>(0h0), 32) node _T_27 = shr(UInt<1>(0h0), 32) node _T_28 = shr(UInt<1>(0h0), 32) node _T_29 = shr(UInt<1>(0h0), 32) node _T_30 = shr(UInt<1>(0h0), 32) node _T_31 = shr(UInt<1>(0h0), 32) node _T_32 = shr(UInt<1>(0h0), 32) node _T_33 = shr(UInt<1>(0h0), 32) node _T_34 = shr(UInt<1>(0h0), 32) node _T_35 = shr(UInt<1>(0h0), 32) node _T_36 = shr(UInt<1>(0h0), 32) node _T_37 = shr(UInt<1>(0h0), 32) node _T_38 = shr(UInt<1>(0h0), 32) node _T_39 = shr(UInt<1>(0h0), 32) node _T_40 = shr(UInt<1>(0h0), 32) node _T_41 = shr(UInt<1>(0h0), 32) node _T_42 = shr(UInt<1>(0h0), 32) node _T_43 = shr(UInt<1>(0h0), 32) node _T_44 = shr(UInt<1>(0h0), 32) node _T_45 = shr(UInt<1>(0h0), 32) node _T_46 = shr(UInt<1>(0h0), 32) node _T_47 = shr(UInt<1>(0h0), 32) node _T_48 = shr(UInt<1>(0h0), 32) node _T_49 = shr(UInt<1>(0h0), 32) node _T_50 = shr(UInt<1>(0h0), 32) node _T_51 = shr(UInt<1>(0h0), 32) node _T_52 = shr(UInt<1>(0h0), 32) node _T_53 = shr(UInt<1>(0h0), 32) node _T_54 = shr(UInt<1>(0h0), 32) node _T_55 = shr(UInt<1>(0h0), 32) node _T_56 = shr(UInt<1>(0h0), 32) node _T_57 = shr(UInt<1>(0h0), 32) node _T_58 = shr(UInt<1>(0h0), 32) node _T_59 = shr(UInt<1>(0h0), 32) node _T_60 = shr(UInt<1>(0h0), 32) node _T_61 = shr(UInt<1>(0h0), 32) node _T_62 = shr(UInt<1>(0h0), 32) node _T_63 = shr(UInt<1>(0h0), 32) node _T_64 = shr(UInt<1>(0h0), 32) node _T_65 = shr(UInt<1>(0h0), 32) node _T_66 = shr(UInt<1>(0h0), 32) node _T_67 = shr(UInt<1>(0h0), 32) node _T_68 = shr(UInt<1>(0h0), 32) node _T_69 = shr(UInt<1>(0h0), 32) node _T_70 = shr(UInt<1>(0h0), 32) node _T_71 = shr(UInt<1>(0h0), 32) node _T_72 = shr(UInt<1>(0h0), 32) node _T_73 = shr(UInt<1>(0h0), 32) node _T_74 = shr(value_1, 32) node _T_75 = shr(value, 32) node _T_76 = shr(value_1, 32) node _T_77 = shr(value, 32) wire _sie_mask_sgeip_mask_WIRE : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect _sie_mask_sgeip_mask_WIRE.usip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vssip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.msip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.utip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.stip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vstip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.mtip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.ueip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.seip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.vseip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.meip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.sgeip, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.rocc, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.debug, UInt<1>(0h0) connect _sie_mask_sgeip_mask_WIRE.zero1, UInt<1>(0h0) wire sie_mask_sgeip_mask : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} connect sie_mask_sgeip_mask, _sie_mask_sgeip_mask_WIRE connect sie_mask_sgeip_mask.sgeip, UInt<1>(0h1) node sie_mask_lo_lo_lo = cat(sie_mask_sgeip_mask.ssip, sie_mask_sgeip_mask.usip) node sie_mask_lo_lo_hi = cat(sie_mask_sgeip_mask.msip, sie_mask_sgeip_mask.vssip) node sie_mask_lo_lo = cat(sie_mask_lo_lo_hi, sie_mask_lo_lo_lo) node sie_mask_lo_hi_lo = cat(sie_mask_sgeip_mask.stip, sie_mask_sgeip_mask.utip) node sie_mask_lo_hi_hi = cat(sie_mask_sgeip_mask.mtip, sie_mask_sgeip_mask.vstip) node sie_mask_lo_hi = cat(sie_mask_lo_hi_hi, sie_mask_lo_hi_lo) node sie_mask_lo = cat(sie_mask_lo_hi, sie_mask_lo_lo) node sie_mask_hi_lo_lo = cat(sie_mask_sgeip_mask.seip, sie_mask_sgeip_mask.ueip) node sie_mask_hi_lo_hi = cat(sie_mask_sgeip_mask.meip, sie_mask_sgeip_mask.vseip) node sie_mask_hi_lo = cat(sie_mask_hi_lo_hi, sie_mask_hi_lo_lo) node sie_mask_hi_hi_lo = cat(sie_mask_sgeip_mask.rocc, sie_mask_sgeip_mask.sgeip) node sie_mask_hi_hi_hi_hi = cat(UInt<0>(0h0), sie_mask_sgeip_mask.zero1) node sie_mask_hi_hi_hi = cat(sie_mask_hi_hi_hi_hi, sie_mask_sgeip_mask.debug) node sie_mask_hi_hi = cat(sie_mask_hi_hi_hi, sie_mask_hi_hi_lo) node sie_mask_hi = cat(sie_mask_hi_hi, sie_mask_hi_lo) node _sie_mask_T = cat(sie_mask_hi, sie_mask_lo) node _sie_mask_T_1 = or(hs_delegable_interrupts, _sie_mask_T) node _sie_mask_T_2 = not(_sie_mask_T_1) node sie_mask = and(read_mideleg, _sie_mask_T_2) wire read_pmp_15 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect read_pmp_15.mask, UInt<32>(0h0) connect read_pmp_15.addr, UInt<30>(0h0) connect read_pmp_15.cfg.r, UInt<1>(0h0) connect read_pmp_15.cfg.w, UInt<1>(0h0) connect read_pmp_15.cfg.x, UInt<1>(0h0) connect read_pmp_15.cfg.a, UInt<2>(0h0) connect read_pmp_15.cfg.res, UInt<2>(0h0) connect read_pmp_15.cfg.l, UInt<1>(0h0) node lo_hi_4 = cat(reg_pmp[0].cfg.x, reg_pmp[0].cfg.w) node lo_4 = cat(lo_hi_4, reg_pmp[0].cfg.r) node hi_hi_4 = cat(reg_pmp[0].cfg.l, reg_pmp[0].cfg.res) node hi_6 = cat(hi_hi_4, reg_pmp[0].cfg.a) node _T_78 = cat(hi_6, lo_4) node lo_hi_5 = cat(reg_pmp[1].cfg.x, reg_pmp[1].cfg.w) node lo_5 = cat(lo_hi_5, reg_pmp[1].cfg.r) node hi_hi_5 = cat(reg_pmp[1].cfg.l, reg_pmp[1].cfg.res) node hi_7 = cat(hi_hi_5, reg_pmp[1].cfg.a) node _T_79 = cat(hi_7, lo_5) node lo_hi_6 = cat(reg_pmp[2].cfg.x, reg_pmp[2].cfg.w) node lo_6 = cat(lo_hi_6, reg_pmp[2].cfg.r) node hi_hi_6 = cat(reg_pmp[2].cfg.l, reg_pmp[2].cfg.res) node hi_8 = cat(hi_hi_6, reg_pmp[2].cfg.a) node _T_80 = cat(hi_8, lo_6) node lo_hi_7 = cat(reg_pmp[3].cfg.x, reg_pmp[3].cfg.w) node lo_7 = cat(lo_hi_7, reg_pmp[3].cfg.r) node hi_hi_7 = cat(reg_pmp[3].cfg.l, reg_pmp[3].cfg.res) node hi_9 = cat(hi_hi_7, reg_pmp[3].cfg.a) node _T_81 = cat(hi_9, lo_7) node lo_8 = cat(_T_79, _T_78) node hi_10 = cat(_T_81, _T_80) node _T_82 = cat(hi_10, lo_8) node lo_hi_8 = cat(reg_pmp[4].cfg.x, reg_pmp[4].cfg.w) node lo_9 = cat(lo_hi_8, reg_pmp[4].cfg.r) node hi_hi_8 = cat(reg_pmp[4].cfg.l, reg_pmp[4].cfg.res) node hi_11 = cat(hi_hi_8, reg_pmp[4].cfg.a) node _T_83 = cat(hi_11, lo_9) node lo_hi_9 = cat(reg_pmp[5].cfg.x, reg_pmp[5].cfg.w) node lo_10 = cat(lo_hi_9, reg_pmp[5].cfg.r) node hi_hi_9 = cat(reg_pmp[5].cfg.l, reg_pmp[5].cfg.res) node hi_12 = cat(hi_hi_9, reg_pmp[5].cfg.a) node _T_84 = cat(hi_12, lo_10) node lo_hi_10 = cat(reg_pmp[6].cfg.x, reg_pmp[6].cfg.w) node lo_11 = cat(lo_hi_10, reg_pmp[6].cfg.r) node hi_hi_10 = cat(reg_pmp[6].cfg.l, reg_pmp[6].cfg.res) node hi_13 = cat(hi_hi_10, reg_pmp[6].cfg.a) node _T_85 = cat(hi_13, lo_11) node lo_hi_11 = cat(reg_pmp[7].cfg.x, reg_pmp[7].cfg.w) node lo_12 = cat(lo_hi_11, reg_pmp[7].cfg.r) node hi_hi_11 = cat(reg_pmp[7].cfg.l, reg_pmp[7].cfg.res) node hi_14 = cat(hi_hi_11, reg_pmp[7].cfg.a) node _T_86 = cat(hi_14, lo_12) node lo_13 = cat(_T_84, _T_83) node hi_15 = cat(_T_86, _T_85) node _T_87 = cat(hi_15, lo_13) node lo_hi_12 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_14 = cat(lo_hi_12, read_pmp_15.cfg.r) node hi_hi_12 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_16 = cat(hi_hi_12, read_pmp_15.cfg.a) node _T_88 = cat(hi_16, lo_14) node lo_hi_13 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_15 = cat(lo_hi_13, read_pmp_15.cfg.r) node hi_hi_13 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_17 = cat(hi_hi_13, read_pmp_15.cfg.a) node _T_89 = cat(hi_17, lo_15) node lo_hi_14 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_16 = cat(lo_hi_14, read_pmp_15.cfg.r) node hi_hi_14 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_18 = cat(hi_hi_14, read_pmp_15.cfg.a) node _T_90 = cat(hi_18, lo_16) node lo_hi_15 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_17 = cat(lo_hi_15, read_pmp_15.cfg.r) node hi_hi_15 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_19 = cat(hi_hi_15, read_pmp_15.cfg.a) node _T_91 = cat(hi_19, lo_17) node lo_18 = cat(_T_89, _T_88) node hi_20 = cat(_T_91, _T_90) node _T_92 = cat(hi_20, lo_18) node lo_hi_16 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_19 = cat(lo_hi_16, read_pmp_15.cfg.r) node hi_hi_16 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_21 = cat(hi_hi_16, read_pmp_15.cfg.a) node _T_93 = cat(hi_21, lo_19) node lo_hi_17 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_20 = cat(lo_hi_17, read_pmp_15.cfg.r) node hi_hi_17 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_22 = cat(hi_hi_17, read_pmp_15.cfg.a) node _T_94 = cat(hi_22, lo_20) node lo_hi_18 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_21 = cat(lo_hi_18, read_pmp_15.cfg.r) node hi_hi_18 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_23 = cat(hi_hi_18, read_pmp_15.cfg.a) node _T_95 = cat(hi_23, lo_21) node lo_hi_19 = cat(read_pmp_15.cfg.x, read_pmp_15.cfg.w) node lo_22 = cat(lo_hi_19, read_pmp_15.cfg.r) node hi_hi_19 = cat(read_pmp_15.cfg.l, read_pmp_15.cfg.res) node hi_24 = cat(hi_hi_19, read_pmp_15.cfg.a) node _T_96 = cat(hi_24, lo_22) node lo_23 = cat(_T_94, _T_93) node hi_25 = cat(_T_96, _T_95) node _T_97 = cat(hi_25, lo_23) regreset reg_custom_0 : UInt<32>, clock, reset, UInt<32>(0h8) node _reg_custom_read_T = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_1 = eq(io.rw.addr, UInt<11>(0h7c1)) node reg_custom_read = and(_reg_custom_read_T, _reg_custom_read_T_1) connect io.customCSRs[0].ren, reg_custom_read node _reg_custom_T = and(reg_custom_read, io.customCSRs[0].stall) when _reg_custom_T : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_1 : UInt<32>, clock, reset, UInt<32>(0h1) node _reg_custom_read_T_2 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_3 = eq(io.rw.addr, UInt<12>(0hf12)) node reg_custom_read_1 = and(_reg_custom_read_T_2, _reg_custom_read_T_3) connect io.customCSRs[1].ren, reg_custom_read_1 node _reg_custom_T_1 = and(reg_custom_read_1, io.customCSRs[1].stall) when _reg_custom_T_1 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_2 : UInt<32>, clock, reset, UInt<32>(0h0) node _reg_custom_read_T_4 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_5 = eq(io.rw.addr, UInt<12>(0hf11)) node reg_custom_read_2 = and(_reg_custom_read_T_4, _reg_custom_read_T_5) connect io.customCSRs[2].ren, reg_custom_read_2 node _reg_custom_T_2 = and(reg_custom_read_2, io.customCSRs[2].stall) when _reg_custom_T_2 : connect io.rw_stall, UInt<1>(0h1) regreset reg_custom_3 : UInt<32>, clock, reset, UInt<32>(0h20181004) node _reg_custom_read_T_6 = neq(io.rw.cmd, UInt<3>(0h0)) node _reg_custom_read_T_7 = eq(io.rw.addr, UInt<12>(0hf13)) node reg_custom_read_3 = and(_reg_custom_read_T_6, _reg_custom_read_T_7) connect io.customCSRs[3].ren, reg_custom_read_3 node _reg_custom_T_3 = and(reg_custom_read_3, io.customCSRs[3].stall) when _reg_custom_T_3 : connect io.rw_stall, UInt<1>(0h1) node decoded_addr_addr = cat(io.status.v, io.rw.addr) wire decoded_addr_decoded_decoded_plaInput : UInt<12> node decoded_addr_decoded_decoded_invInputs = not(decoded_addr_decoded_decoded_plaInput) wire decoded_addr_decoded_decoded : UInt<196> node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo) node _decoded_addr_decoded_decoded_andMatrixOutputs_T = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo) node decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1) node decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2) node decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3) node decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4) node decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5) node decoded_addr_decoded_decoded_andMatrixOutputs_179_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6) node decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7) node decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8) node decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9) node decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10) node decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11) node decoded_addr_decoded_decoded_andMatrixOutputs_189_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_11) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12) node decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_12) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13) node decoded_addr_decoded_decoded_andMatrixOutputs_154_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_13) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14) node decoded_addr_decoded_decoded_andMatrixOutputs_156_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_14) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15) node decoded_addr_decoded_decoded_andMatrixOutputs_181_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_15) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16) node decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_16) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17) node decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_17) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18) node decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_18) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19) node decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_19) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20) node decoded_addr_decoded_decoded_andMatrixOutputs_171_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_20) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21) node decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_21) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22) node decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_22) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23) node decoded_addr_decoded_decoded_andMatrixOutputs_177_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_23) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24) node decoded_addr_decoded_decoded_andMatrixOutputs_183_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_24) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25) node decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_25) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26) node decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_26) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27) node decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_27) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28) node decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_28) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29) node decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_29) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30) node decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_30) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31) node decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_31) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32) node decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_32) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33) node decoded_addr_decoded_decoded_andMatrixOutputs_185_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_33) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34) node decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_34) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35) node decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_35) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36) node decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_36) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37) node decoded_addr_decoded_decoded_andMatrixOutputs_158_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_37) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38) node decoded_addr_decoded_decoded_andMatrixOutputs_157_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_38) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39) node decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_39) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40) node decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_40) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41) node decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_41) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42) node decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_42) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43) node decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_43) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44) node decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_44) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45) node decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_45) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46) node decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_46) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47) node decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_47) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48) node decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_48) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49) node decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_49) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50) node decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_50) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51) node decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_51) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52) node decoded_addr_decoded_decoded_andMatrixOutputs_180_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_52) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53) node decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_53) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54) node decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_54) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55) node decoded_addr_decoded_decoded_andMatrixOutputs_186_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_55) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56) node decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_56) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57) node decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_57) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58) node decoded_addr_decoded_decoded_andMatrixOutputs_195_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_58) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59) node decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_59) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60) node decoded_addr_decoded_decoded_andMatrixOutputs_191_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_60) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61) node decoded_addr_decoded_decoded_andMatrixOutputs_168_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_61) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62) node decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_62) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63) node decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_63) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64) node decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_64) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = bits(decoded_addr_decoded_decoded_plaInput, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65) node decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_65) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = bits(decoded_addr_decoded_decoded_plaInput, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = bits(decoded_addr_decoded_decoded_invInputs, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_66) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_67) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_68) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_69) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_70) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_170_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_71) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_192_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_72) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_73) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_182_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_74) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_75) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_76) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_77) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_78) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_176_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_79) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_80) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_81) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_82) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_83) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_172_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_84) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_85) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_86) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_87) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_88) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_184_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_89) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_173_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_90) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_91) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_92) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_93) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_94) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_95) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_96) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_175_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_97) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_194_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_98) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_188_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_99) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_100) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_164_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_101) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_102) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_169_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_103) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_104) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_105) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_106) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_107) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_108) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_109) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_110) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_111) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_112) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_113) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_114) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_115) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_116) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_117) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_187_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_118) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_119) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_165_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_120) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_151_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_121) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_122) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_162_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_123) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_124) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_125) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_126) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_127) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = bits(decoded_addr_decoded_decoded_invInputs, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_161_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_128) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_129) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_130) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_131) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_132) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_133) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_134) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_135) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_166_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_136) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_137) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_138) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_139) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_132 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_132 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_132) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_178_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_140) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_133 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_133 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_133) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_141) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_134 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_134 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_134) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_142) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_135 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_135 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_135) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_143) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_136 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_136 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_136) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_144) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_143 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_137 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_137 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_137) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_145) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_144 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_138 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_138 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_138) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_146) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_146 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_145 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_139 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_139 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_139) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_193_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_147) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_147 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_146 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_140 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_140 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_140) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148) node decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_148) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_149 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_148 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_148 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_148 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_148 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_147 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_141 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_141 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_141) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_148) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_148) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_148) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_148) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149) node decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_149) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_150 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_150 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_150 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_150 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_150 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_150 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_149 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_149 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_149 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_149 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_148 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_142 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_142 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_148) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_142) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_149) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_149) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_149) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_150) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_150) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_150) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_150) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_149) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_lo_150) node decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_150) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_151 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_151 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_151 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_151 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_151 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_151 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_150 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_150 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_150 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_150 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_149 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_143 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_143 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_149) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_143) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_150) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_150) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_150) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_151) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_151) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_151) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_151) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_150) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_lo_151) node decoded_addr_decoded_decoded_andMatrixOutputs_163_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_151) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_152 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_152 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_152 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_152 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_152 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_152 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_151 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_151 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_151 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_151 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_150 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_144 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_144 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_150) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_144) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_151) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_152 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_151) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_152 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_151) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_152) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_152) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_152) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_152 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_152) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_152 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_151) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_152 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_lo_152) node decoded_addr_decoded_decoded_andMatrixOutputs_150_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_152) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_153 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_153 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_153 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_153 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_153 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_153 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_152 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_152 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_152 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_152 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_151 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_145 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_145 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_151) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_152 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_145) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_152 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_152) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_153 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_152) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_153 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_152) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_153) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_152 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_153) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_152 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_153) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_153 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_153) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_153 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_152) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_153 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_lo_153) node decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_153) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_154 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_154 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_154 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_154 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_154 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_154 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_153 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_153 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_153 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_153 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_152 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_146 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_146 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_152) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_153 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_146) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_153 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_153) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_154 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_153) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_154 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_153) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_152 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_154) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_153 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_154) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_153 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_154) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_154 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_154) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_154 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_153) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_154 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_lo_154) node decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_154) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_155 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_155 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_155 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_155 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_155 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_155 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_154 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_154 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_154 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_154 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_153 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_147 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_147 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_153) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_154 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_147) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_154 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_154) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_155 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_154) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_155 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_154) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_153 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_155) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_154 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_155) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_154 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_155) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_155 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_155) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_155 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_154) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_155 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_lo_155) node decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_155) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_156 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_156 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_156 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_156 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_156 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_156 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_155 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_155 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_155 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_155 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_154 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_148 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_148 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_154) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_155 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_148) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_155 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_155) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_156 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_155) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_156 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_155) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_154 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_156) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_155 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_156) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_155 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_156) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_156 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_156) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_156 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_155) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_156 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_lo_156) node decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_156) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_157 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_157 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_157 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_157 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_157 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_157 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_156 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_156 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_156 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_156 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_155 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_149 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_149 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_155) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_156 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_149) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_156 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_156) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_157 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_156) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_157 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_156) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_155 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_157) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_156 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_157) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_156 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_157) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_157 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_157) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_157 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_156) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_157 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_lo_157) node decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_157) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_158 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_158 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_158 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_158 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_158 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_158 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_157 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_157 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_157 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_157 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_156 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_150 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_150 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_156) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_157 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_150) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_157 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_157) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_158 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_157) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_158 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_157) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_156 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_158) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_157 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_158) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_157 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_158) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_158 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_158) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_158 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_157) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_158 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_lo_158) node decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_158) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_159 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_159 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_159 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_159 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_159 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_159 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_158 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_158 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_158 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_158 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_157 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_151 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_151 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_157) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_158 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_151) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_158 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_158) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_159 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_158) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_159 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_158) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_157 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_159) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_158 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_159) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_158 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_159) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_159 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_159) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_159 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_158) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_159 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_lo_159) node decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_159) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_160 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_160 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_160 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_160 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_160 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_160 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_159 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_159 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_159 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_159 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_158 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_159 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_158) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_159 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_159) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_160 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_159) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_160 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_159) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_158 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_160) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_159 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_160) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_159 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_160) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_160 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_160) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_160 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_159) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_160 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_lo_160) node decoded_addr_decoded_decoded_andMatrixOutputs_153_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_160) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_161 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_161 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_161 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_161 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_161 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_161 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_160 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_160 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_160 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_160 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_159 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_152 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_152 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_159) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_160 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_152) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_160 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_160) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_161 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_160) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_161 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_160) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_159 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_161) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_160 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_161) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_160 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_161) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_161 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_161) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_161 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_160) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_161 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_lo_161) node decoded_addr_decoded_decoded_andMatrixOutputs_160_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_161) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_162 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_162 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_162 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_162 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_162 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_162 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_161 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_161 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_161 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_161 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_160 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_153 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_153 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_160) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_161 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_153) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_161 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_161) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_162 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_161) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_162 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_161) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_160 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_162) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_161 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_162) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_161 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_162) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_162 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_162) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_162 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_161) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_162 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_lo_162) node decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_162) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_163 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_163 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_163 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_163 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_163 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_163 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_162 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_162 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_162 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_162 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_161 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_154 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_154 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_161) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_162 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_154) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_162 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_162) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_163 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_162) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_163 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_162) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_161 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_163) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_162 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_163) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_162 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_163) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_163 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_163) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_163 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_162) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_163 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_lo_163) node decoded_addr_decoded_decoded_andMatrixOutputs_152_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_163) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_164 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_164 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_164 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_164 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_164 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_164 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_163 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_163 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_163 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_163 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_162 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_155 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_155 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_162) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_163 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_155) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_163 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_163) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_164 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_163) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_164 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_163) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_162 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_164) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_163 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_164) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_163 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_164) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_164 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_164) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_164 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_163) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_164 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_lo_164) node decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_164) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_165 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_165 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_165 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_165 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_165 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_165 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_164 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_164 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_164 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_164 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_163 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_156 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_156 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_163) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_164 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_156) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_164 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_164) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_165 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_164) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_165 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_164) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_163 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_165) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_164 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_165) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_164 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_165) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_165 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_165) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_165 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_164) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_165 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_lo_165) node decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_165) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_166 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_166 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_166 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_166 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_166 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_166 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_165 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_165 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_165 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_165 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_164 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_157 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_157 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_164) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_165 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_157) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_165 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_165) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_166 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_165) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_166 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_165) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_164 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_166) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_165 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_166) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_165 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_166) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_166 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_166) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_166 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_165) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_166 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_lo_166) node decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_166) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_167 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_167 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_167 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_167 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_167 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_167 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_166 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_166 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_166 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_166 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_165 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_158 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_158 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_165) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_166 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_158) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_166 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_166) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_167 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_166) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_167 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_166) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_165 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_167) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_166 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_167) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_166 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_167) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_167 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_167) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_167 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_166) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_167 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_lo_167) node decoded_addr_decoded_decoded_andMatrixOutputs_190_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_167) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_168 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_168 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_168 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_168 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_168 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_168 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_167 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_167 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_167 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_167 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_166 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_159 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_159 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_166) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_167 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_159) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_167 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_167) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_168 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_167) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_168 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_167) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_166 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_168) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_167 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_168) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_167 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_168) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_168 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_168) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_168 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_167) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_168 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_lo_168) node decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_168) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_169 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_169 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_169 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_169 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_169 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_169 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_168 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_168 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_168 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_168 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_167 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_160 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_160 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_167) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_168 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_160) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_168 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_168) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_169 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_168) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_169 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_168) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_167 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_169) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_168 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_169) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_168 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_169) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_169 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_169) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_169 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_168) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_169 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_lo_169) node decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_169) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_170 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_170 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_170 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_170 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_170 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_170 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_169 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_169 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_169 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_169 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_168 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_161 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_161 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_168) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_169 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_161) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_169 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_169) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_170 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_169) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_170 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_169) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_168 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_170) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_169 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_170) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_169 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_170) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_170 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_170) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_170 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_169) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_170 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_lo_170) node decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_170) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_171 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_171 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_171 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_171 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_171 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_171 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_170 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_170 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_170 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_170 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_169 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_162 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_162 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_169) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_170 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_162) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_170 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_170) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_171 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_170) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_171 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_170) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_169 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_171) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_170 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_171) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_170 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_171) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_171 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_171) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_171 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_170) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_171 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_lo_171) node decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_171) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_172 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_172 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_172 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_172 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_172 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_172 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_171 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_171 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_171 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_171 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_170 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_163 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_163 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_170) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_171 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_163) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_171 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_171) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_172 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_171) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_172 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_171) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_170 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_172) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_171 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_172) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_171 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_172) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_172 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_172) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_172 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_171) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_172 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_lo_172) node decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_172) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_173 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_173 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_173 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_173 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_173 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_173 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_172 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_172 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_172 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_172 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_171 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_164 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_164 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_171) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_172 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_164) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_172 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_172) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_173 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_172) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_173 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_172) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_171 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_173) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_172 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_173) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_172 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_173) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_173 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_173) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_173 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_172) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_173 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_lo_173) node decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_173) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_174 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_174 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_174 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_174 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_174 = bits(decoded_addr_decoded_decoded_invInputs, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_174 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_173 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_173 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_173 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_173 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_172 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_165 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_165 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_172) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_173 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_165) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_173 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_173) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_174 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_173) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_174 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_173) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_172 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_174) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_173 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_174) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_173 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_174) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_174 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_174) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_174 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_173) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_174 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_lo_174) node decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_174) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_175 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_175 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_175 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_175 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_175 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_175 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_174 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_174 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_174 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_174 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_173 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_166 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_166 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_173) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_174 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_166) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_174 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_174) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_175 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_174) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_175 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_174) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_173 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_175) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_174 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_175) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_174 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_175) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_175 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_175) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_175 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_174) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_175 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_lo_175) node decoded_addr_decoded_decoded_andMatrixOutputs_174_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_175) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_176 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_176 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_176 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_176 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_176 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_176 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_175 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_175 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_175 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_175 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_174 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_167 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_167 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_174) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_175 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_167) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_175 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_175) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_176 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_175) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_176 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_175) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_174 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_176) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_175 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_176) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_175 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_176) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_176 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_176) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_176 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_175) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_176 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_lo_176) node decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_176) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_177 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_177 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_177 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_177 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_177 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_177 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_176 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_176 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_176 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_176 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_175 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_168 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_168 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_175) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_176 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_168) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_176 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_176) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_177 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_176) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_177 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_176) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_175 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_177) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_176 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_177) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_176 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_177) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_177 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_177) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_177 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_176) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_177 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_lo_177) node decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_177) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_178 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_178 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_178 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_178 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_178 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_178 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_177 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_177 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_177 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_177 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_176 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_169 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_169 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_176) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_177 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_169) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_177 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_177) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_178 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_177) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_178 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_177) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_176 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_178) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_177 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_178) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_177 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_178) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_178 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_178) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_178 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_177) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_178 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_lo_178) node decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_178) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_179 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_179 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_179 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_179 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_179 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_179 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_178 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_178 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_178 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_178 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_177 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_170 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_170 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_177) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_178 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_170) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_178 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_178) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_179 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_178) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_179 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_178) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_177 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_179) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_178 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_179) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_178 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_179) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_179 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_179) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_179 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_178) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_179 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_lo_179) node decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_179) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_180 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_180 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_180 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_180 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_180 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_180 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_179 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_179 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_179 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_179 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_178 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_171 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_171 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_178) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_179 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_171) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_179 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_179) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_180 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_179) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_180 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_179) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_178 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_180) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_179 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_180) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_179 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_180) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_180 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_180) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_180 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_179) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_180 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_lo_180) node decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_180) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_181 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_181 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_181 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_181 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_181 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_181 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_180 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_180 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_180 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_180 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_179 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_172 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_172 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_179) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_180 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_172) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_180 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_180) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_181 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_180) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_181 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_180) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_179 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_181) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_180 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_181) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_180 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_181) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_181 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_181) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_181 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_180) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_181 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_lo_181) node decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_181) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_182 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_182 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_182 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_182 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_182 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_182 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_181 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_181 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_181 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_181 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_180 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_173 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_173 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_180) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_181 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_173) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_181 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_181) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_182 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_181) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_182 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_181) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_180 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_182) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_181 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_182) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_181 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_182) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_182 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_182) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_182 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_181) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_182 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_lo_182) node decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_182) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_183 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_183 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_183 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_183 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_183 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_183 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_182 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_182 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_182 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_182 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_181 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_174 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_174 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_181) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_182 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_174) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_182 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_182) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_183 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_182) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_183 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_182) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_181 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_183) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_182 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_183) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_182 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_183) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_183 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_183) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_183 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_182) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_183 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_lo_183) node decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_183) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_184 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_184 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_184 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_184 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_184 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_184 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_183 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_183 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_183 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_183 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_182 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_175 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_175 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_182) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_183 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_175) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_183 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_183) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_184 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_183) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_184 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_183) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_182 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_184) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_183 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_184) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_183 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_184) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_184 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_184) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_184 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_183) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_184 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_lo_184) node decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_184) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_185 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_185 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_185 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_185 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_185 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_185 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_184 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_184 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_184 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_184 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_183 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_176 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_176 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_183) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_184 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_176) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_184 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_184) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_185 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_184) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_185 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_184) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_183 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_185) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_184 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_185) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_184 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_185) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_185 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_185) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_185 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_184) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_185 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_lo_185) node decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_185) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_186 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_186 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_186 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_186 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_186 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_186 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_185 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_185 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_185 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_185 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_184 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_177 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_177 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_184) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_185 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_177) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_185 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_185) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_186 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_185) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_186 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_185) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_184 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_186) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_185 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_186) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_185 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_186) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_186 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_186) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_186 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_185) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_186 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_lo_186) node decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_186) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_187 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_187 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_187 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_187 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_187 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_187 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_186 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_186 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_186 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_186 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_185 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_178 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_178 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_185) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_186 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_178) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_186 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_186) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_187 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_186) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_187 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_186) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_185 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_187) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_186 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_187) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_186 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_187) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_187 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_187) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_187 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_186) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_187 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_lo_187) node decoded_addr_decoded_decoded_andMatrixOutputs_155_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_187) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_188 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_188 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_188 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_188 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_188 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_188 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_187 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_187 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_187 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_187 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_186 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_179 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_179 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_186) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_187 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_179) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_187 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_187) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_188 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_187) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_188 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_187) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_186 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_188) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_187 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_188) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_187 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_188) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_188 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_188) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_188 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_187) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_188 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_lo_188) node decoded_addr_decoded_decoded_andMatrixOutputs_167_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_188) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_189 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_189 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_189 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_189 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_189 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_189 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_188 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_188 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_188 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_188 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_187 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_180 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_180 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_187) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_188 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_180) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_188 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_188) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_189 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_188) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_189 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_188) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_187 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_189) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_188 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_189) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_188 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_189) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_189 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_189) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_189 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_188) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_189 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_lo_189) node decoded_addr_decoded_decoded_andMatrixOutputs_159_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_189) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_190 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_190 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_190 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_190 = bits(decoded_addr_decoded_decoded_plaInput, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_190 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_190 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_189 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_189 = bits(decoded_addr_decoded_decoded_plaInput, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_189 = bits(decoded_addr_decoded_decoded_invInputs, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_189 = bits(decoded_addr_decoded_decoded_invInputs, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_188 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_181 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_181 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_188) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_189 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_181) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_189 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_189) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_190 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_189) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_190 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_189) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_188 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_190) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_189 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_190) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_189 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_190) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_190 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_190) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_190 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_189) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_190 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_lo_190) node decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_190) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_191 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_191 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_191 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_191 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_191 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_191 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_190 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_190 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_190 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_190 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_189 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_190 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_189) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_190 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_190) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_191 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_190) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_191 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_190) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_189 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_191) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_190 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_191) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_190 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_191) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_191 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_191) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_191 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_190) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_191 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_lo_191) node decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_191) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_192 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_192 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_192 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_192 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_192 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_192 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_191 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_191 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_191 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_191 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_190 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_182 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_182 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_190) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_191 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_182) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_191 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_191) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_192 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_191) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_192 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_191) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_190 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_192) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_191 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_192) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_191 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_192) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_192 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_192) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_192 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_191) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_192 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_lo_192) node decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_192) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_193 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_193 = bits(decoded_addr_decoded_decoded_plaInput, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_193 = bits(decoded_addr_decoded_decoded_invInputs, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_193 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_193 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_193 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_192 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_192 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_192 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_192 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_191 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_183 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_183 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_191) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_192 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_183) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_192 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_192) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_193 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_192) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_193 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_192) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_191 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_193) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_192 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_193) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_192 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_193) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_193 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_193) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_193 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_192) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_193 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_lo_193) node decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_193) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_194 = bits(decoded_addr_decoded_decoded_invInputs, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_194 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_194 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_194 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_194 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_194 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_193 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_193 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_193 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_193 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_192 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_184 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_184 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_192) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_193 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_184) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_193 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_193) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_194 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_193) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_194 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_194, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_193) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_192 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_194) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_193 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_194) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_193 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_194) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_194 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_194) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_194 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_194, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_193) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_194 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_194, decoded_addr_decoded_decoded_andMatrixOutputs_lo_194) node decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_194) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_195 = bits(decoded_addr_decoded_decoded_plaInput, 0, 0) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_195 = bits(decoded_addr_decoded_decoded_invInputs, 1, 1) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_195 = bits(decoded_addr_decoded_decoded_plaInput, 2, 2) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_195 = bits(decoded_addr_decoded_decoded_invInputs, 3, 3) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_195 = bits(decoded_addr_decoded_decoded_plaInput, 4, 4) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_195 = bits(decoded_addr_decoded_decoded_invInputs, 5, 5) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_194 = bits(decoded_addr_decoded_decoded_invInputs, 6, 6) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_194 = bits(decoded_addr_decoded_decoded_invInputs, 7, 7) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_194 = bits(decoded_addr_decoded_decoded_plaInput, 8, 8) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_194 = bits(decoded_addr_decoded_decoded_plaInput, 9, 9) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_193 = bits(decoded_addr_decoded_decoded_plaInput, 10, 10) node decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_185 = bits(decoded_addr_decoded_decoded_plaInput, 11, 11) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_185 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_193) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_194 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_185) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_194 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_194) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_195 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_194) node decoded_addr_decoded_decoded_andMatrixOutputs_lo_195 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_195, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_194) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_193 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_195, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_195) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_194 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_195) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_194 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_195, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_195) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_195 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_195) node decoded_addr_decoded_decoded_andMatrixOutputs_hi_195 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_195, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_194) node _decoded_addr_decoded_decoded_andMatrixOutputs_T_195 = cat(decoded_addr_decoded_decoded_andMatrixOutputs_hi_195, decoded_addr_decoded_decoded_andMatrixOutputs_lo_195) node decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = andr(_decoded_addr_decoded_decoded_andMatrixOutputs_T_195) node _decoded_addr_decoded_decoded_orMatrixOutputs_T = orr(decoded_addr_decoded_decoded_andMatrixOutputs_92_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_14_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_126_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_44_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_13_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_195_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_140_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_118_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_186_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_46_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_89_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_180_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_112_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_138_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_120_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_106_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_73_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_111_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_21_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_52_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_11_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_28_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_79_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_55_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_100_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_160_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_153_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_188_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_194_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_59_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_56_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_66_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_161_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_137_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_175_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_185_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_159_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_67_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_98_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_60_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_34_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_167_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_93_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_87_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_116_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_45_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_155_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_0_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_50_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_75_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_80_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_135_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_42_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_58_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_117_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_35_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_142_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_162_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_17_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_107_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_40_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_101_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_91_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_53_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_16_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_82_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_84_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_151_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_150_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_173_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_113_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_134_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_165_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_163_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_184_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_25_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_103_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_145_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_119_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_18_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_183_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_70_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_187_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_124_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_29_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_177_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_30_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_31_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_86_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_2_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_109_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_97_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_149_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_193_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_123_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_19_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_143_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_72_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_131_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_172_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_171_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_38_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_136_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_139_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_88_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_105_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_174_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_48_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_22_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_3_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_76_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_63_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_71_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_81_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_148_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_8_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_6_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_94_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_20_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_10_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_108_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_74_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_47_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_43_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_176_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_181_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_36_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_4_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_178_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_69_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_156_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_61_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_49_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_62_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_78_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_154_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_114_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_15_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_90_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_33_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_12_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_146_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_41_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_39_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_51_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_189_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_190_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_144_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_166_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_182_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_150 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_54_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_151 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_125_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_152 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_77_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_153 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_32_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_154 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_96_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_155 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_7_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_156 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_121_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_157 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_169_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_158 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_24_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_159 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_192_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_160 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_132_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_161 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_9_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_162 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_122_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_163 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_5_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_164 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_170_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_165 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_128_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_166 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_152_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_167 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_164_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_168 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_133_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_169 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_27_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_170 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_64_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_171 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_68_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_172 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_130_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_173 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_23_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_174 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_115_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_175 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_179_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_176 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_99_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_177 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_95_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_178 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_37_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_179 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_26_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_180 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_57_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_181 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_1_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_182 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_104_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_183 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_102_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_184 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_158_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_185 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_129_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_186 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_83_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_187 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_110_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_188 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_157_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_189 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_85_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_190 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_141_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_191 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_127_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_192 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_65_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_193 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_168_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_194 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_191_2) node _decoded_addr_decoded_decoded_orMatrixOutputs_T_195 = orr(decoded_addr_decoded_decoded_andMatrixOutputs_147_2) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_2, _decoded_addr_decoded_decoded_orMatrixOutputs_T_1) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_3) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_11, _decoded_addr_decoded_decoded_orMatrixOutputs_T_10) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_12) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_20, _decoded_addr_decoded_decoded_orMatrixOutputs_T_19) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_21) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_29, _decoded_addr_decoded_decoded_orMatrixOutputs_T_28) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_32, _decoded_addr_decoded_decoded_orMatrixOutputs_T_31) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_35, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_33) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_36) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_41, _decoded_addr_decoded_decoded_orMatrixOutputs_T_40) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_44, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_42) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_46, _decoded_addr_decoded_decoded_orMatrixOutputs_T_45) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_48, _decoded_addr_decoded_decoded_orMatrixOutputs_T_47) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_51, _decoded_addr_decoded_decoded_orMatrixOutputs_T_50) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_54, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_52) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_55) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_60, _decoded_addr_decoded_decoded_orMatrixOutputs_T_59) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_63, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_61) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_64) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_72, _decoded_addr_decoded_decoded_orMatrixOutputs_T_71) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_75, _decoded_addr_decoded_decoded_orMatrixOutputs_T_74) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_76) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_81, _decoded_addr_decoded_decoded_orMatrixOutputs_T_80) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_84, _decoded_addr_decoded_decoded_orMatrixOutputs_T_83) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_85) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_90, _decoded_addr_decoded_decoded_orMatrixOutputs_T_89) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_93, _decoded_addr_decoded_decoded_orMatrixOutputs_T_92) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_95, _decoded_addr_decoded_decoded_orMatrixOutputs_T_94) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_97, _decoded_addr_decoded_decoded_orMatrixOutputs_T_96) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_100, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_98) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_101) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_109, _decoded_addr_decoded_decoded_orMatrixOutputs_T_108) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_112, _decoded_addr_decoded_decoded_orMatrixOutputs_T_111) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_113) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_118, _decoded_addr_decoded_decoded_orMatrixOutputs_T_117) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_121, _decoded_addr_decoded_decoded_orMatrixOutputs_T_120) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_124, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_122) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_125) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_133, _decoded_addr_decoded_decoded_orMatrixOutputs_T_132) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_134) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_142, _decoded_addr_decoded_decoded_orMatrixOutputs_T_141) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_152, _decoded_addr_decoded_decoded_orMatrixOutputs_T_151) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_150) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_155, _decoded_addr_decoded_decoded_orMatrixOutputs_T_154) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_153) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_158, _decoded_addr_decoded_decoded_orMatrixOutputs_T_157) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_156) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_161, _decoded_addr_decoded_decoded_orMatrixOutputs_T_160) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_159) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_164, _decoded_addr_decoded_decoded_orMatrixOutputs_T_163) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_162) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_167, _decoded_addr_decoded_decoded_orMatrixOutputs_T_166) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_165) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_170, _decoded_addr_decoded_decoded_orMatrixOutputs_T_169) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_168) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_173, _decoded_addr_decoded_decoded_orMatrixOutputs_T_172) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_171) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_176, _decoded_addr_decoded_decoded_orMatrixOutputs_T_175) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_174) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_179, _decoded_addr_decoded_decoded_orMatrixOutputs_T_178) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_177) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_182, _decoded_addr_decoded_decoded_orMatrixOutputs_T_181) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_180) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_185, _decoded_addr_decoded_decoded_orMatrixOutputs_T_184) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_183) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_188, _decoded_addr_decoded_decoded_orMatrixOutputs_T_187) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_186) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_191, _decoded_addr_decoded_decoded_orMatrixOutputs_T_190) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_189) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_193, _decoded_addr_decoded_decoded_orMatrixOutputs_T_192) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_orMatrixOutputs_T_195, _decoded_addr_decoded_decoded_orMatrixOutputs_T_194) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_orMatrixOutputs = cat(decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo) node _decoded_addr_decoded_decoded_invMatrixOutputs_T = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 0, 0) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 1, 1) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 2, 2) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 3, 3) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 4, 4) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 5, 5) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 6, 6) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 7, 7) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 8, 8) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 9, 9) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 10, 10) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 11, 11) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 12, 12) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 13, 13) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 14, 14) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 15, 15) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 16, 16) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 17, 17) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 18, 18) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 19, 19) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 20, 20) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 21, 21) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 22, 22) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 23, 23) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 24, 24) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 25, 25) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 26, 26) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 27, 27) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 28, 28) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 29, 29) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 30, 30) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 31, 31) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 32, 32) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 33, 33) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 34, 34) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 35, 35) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 36, 36) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 37, 37) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 38, 38) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 39, 39) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 40, 40) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 41, 41) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 42, 42) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 43, 43) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 44, 44) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 45, 45) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 46, 46) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 47, 47) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 48, 48) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 49, 49) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 50, 50) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 51, 51) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 52, 52) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 53, 53) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 54, 54) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 55, 55) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 56, 56) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 57, 57) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 58, 58) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 59, 59) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 60, 60) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 61, 61) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 62, 62) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 63, 63) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 64, 64) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 65, 65) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 66, 66) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 67, 67) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 68, 68) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 69, 69) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 70, 70) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 71, 71) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 72, 72) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 73, 73) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 74, 74) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 75, 75) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 76, 76) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 77, 77) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 78, 78) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 79, 79) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 80, 80) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 81, 81) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 82, 82) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 83, 83) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 84, 84) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 85, 85) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 86, 86) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 87, 87) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 88, 88) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 89, 89) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 90, 90) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 91, 91) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 92, 92) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 93, 93) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 94, 94) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 95, 95) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 96, 96) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 97, 97) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 98, 98) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 99, 99) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 100, 100) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 101, 101) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 102, 102) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 103, 103) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 104, 104) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 105, 105) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 106, 106) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 107, 107) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 108, 108) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 109, 109) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 110, 110) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 111, 111) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 112, 112) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 113, 113) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 114, 114) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 115, 115) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 116, 116) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 117, 117) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 118, 118) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 119, 119) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 120, 120) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 121, 121) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 122, 122) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 123, 123) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 124, 124) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 125, 125) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 126, 126) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 127, 127) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 128, 128) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 129, 129) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 130, 130) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 131, 131) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 132, 132) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 133, 133) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 134, 134) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 135, 135) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 136, 136) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 137, 137) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 138, 138) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 139, 139) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 140, 140) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 141, 141) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 142, 142) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 143, 143) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 144, 144) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 145, 145) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 146, 146) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 147, 147) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 148, 148) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 149, 149) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_150 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 150, 150) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_151 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 151, 151) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_152 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 152, 152) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_153 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 153, 153) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_154 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 154, 154) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_155 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 155, 155) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_156 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 156, 156) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_157 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 157, 157) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_158 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 158, 158) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_159 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 159, 159) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_160 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 160, 160) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_161 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 161, 161) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_162 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 162, 162) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_163 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 163, 163) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_164 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 164, 164) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_165 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 165, 165) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_166 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 166, 166) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_167 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 167, 167) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_168 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 168, 168) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_169 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 169, 169) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_170 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 170, 170) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_171 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 171, 171) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_172 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 172, 172) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_173 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 173, 173) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_174 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 174, 174) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_175 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 175, 175) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_176 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 176, 176) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_177 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 177, 177) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_178 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 178, 178) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_179 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 179, 179) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_180 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 180, 180) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_181 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 181, 181) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_182 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 182, 182) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_183 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 183, 183) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_184 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 184, 184) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_185 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 185, 185) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_186 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 186, 186) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_187 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 187, 187) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_188 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 188, 188) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_189 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 189, 189) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_190 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 190, 190) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_191 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 191, 191) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_192 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 192, 192) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_193 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 193, 193) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_194 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 194, 194) node _decoded_addr_decoded_decoded_invMatrixOutputs_T_195 = bits(decoded_addr_decoded_decoded_orMatrixOutputs, 195, 195) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_2, _decoded_addr_decoded_decoded_invMatrixOutputs_T_1) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_3) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_11, _decoded_addr_decoded_decoded_invMatrixOutputs_T_10) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_12) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_20, _decoded_addr_decoded_decoded_invMatrixOutputs_T_19) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_21) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_29, _decoded_addr_decoded_decoded_invMatrixOutputs_T_28) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_32, _decoded_addr_decoded_decoded_invMatrixOutputs_T_31) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_35, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_33) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_36) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_41, _decoded_addr_decoded_decoded_invMatrixOutputs_T_40) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_44, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_42) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_46, _decoded_addr_decoded_decoded_invMatrixOutputs_T_45) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_48, _decoded_addr_decoded_decoded_invMatrixOutputs_T_47) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_51, _decoded_addr_decoded_decoded_invMatrixOutputs_T_50) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_54, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_52) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_55) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_60, _decoded_addr_decoded_decoded_invMatrixOutputs_T_59) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_63, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_61) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_64) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_72, _decoded_addr_decoded_decoded_invMatrixOutputs_T_71) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_75, _decoded_addr_decoded_decoded_invMatrixOutputs_T_74) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_76) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_81, _decoded_addr_decoded_decoded_invMatrixOutputs_T_80) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_84, _decoded_addr_decoded_decoded_invMatrixOutputs_T_83) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_85) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_90, _decoded_addr_decoded_decoded_invMatrixOutputs_T_89) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_93, _decoded_addr_decoded_decoded_invMatrixOutputs_T_92) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_95, _decoded_addr_decoded_decoded_invMatrixOutputs_T_94) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_97, _decoded_addr_decoded_decoded_invMatrixOutputs_T_96) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_100, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_98) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_101) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_109, _decoded_addr_decoded_decoded_invMatrixOutputs_T_108) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_112, _decoded_addr_decoded_decoded_invMatrixOutputs_T_111) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_113) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_118, _decoded_addr_decoded_decoded_invMatrixOutputs_T_117) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_121, _decoded_addr_decoded_decoded_invMatrixOutputs_T_120) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_124, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_122) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_125) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_133, _decoded_addr_decoded_decoded_invMatrixOutputs_T_132) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_134) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_142, _decoded_addr_decoded_decoded_invMatrixOutputs_T_141) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_152, _decoded_addr_decoded_decoded_invMatrixOutputs_T_151) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_150) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_155, _decoded_addr_decoded_decoded_invMatrixOutputs_T_154) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_153) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_158, _decoded_addr_decoded_decoded_invMatrixOutputs_T_157) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_156) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_161, _decoded_addr_decoded_decoded_invMatrixOutputs_T_160) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_159) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_164, _decoded_addr_decoded_decoded_invMatrixOutputs_T_163) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_162) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_167, _decoded_addr_decoded_decoded_invMatrixOutputs_T_166) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_165) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_170, _decoded_addr_decoded_decoded_invMatrixOutputs_T_169) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_168) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_173, _decoded_addr_decoded_decoded_invMatrixOutputs_T_172) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_171) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_176, _decoded_addr_decoded_decoded_invMatrixOutputs_T_175) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_174) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_179, _decoded_addr_decoded_decoded_invMatrixOutputs_T_178) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_177) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_182, _decoded_addr_decoded_decoded_invMatrixOutputs_T_181) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_180) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_185, _decoded_addr_decoded_decoded_invMatrixOutputs_T_184) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_183) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_188, _decoded_addr_decoded_decoded_invMatrixOutputs_T_187) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_186) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_191, _decoded_addr_decoded_decoded_invMatrixOutputs_T_190) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_189) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_lo = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_193, _decoded_addr_decoded_decoded_invMatrixOutputs_T_192) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = cat(_decoded_addr_decoded_decoded_invMatrixOutputs_T_195, _decoded_addr_decoded_decoded_invMatrixOutputs_T_194) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs_hi = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo) node decoded_addr_decoded_decoded_invMatrixOutputs = cat(decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo) connect decoded_addr_decoded_decoded, decoded_addr_decoded_decoded_invMatrixOutputs connect decoded_addr_decoded_decoded_plaInput, decoded_addr_addr node decoded_addr_decoded_0 = bits(decoded_addr_decoded_decoded, 195, 195) node decoded_addr_decoded_1 = bits(decoded_addr_decoded_decoded, 194, 194) node decoded_addr_decoded_2 = bits(decoded_addr_decoded_decoded, 193, 193) node decoded_addr_decoded_3 = bits(decoded_addr_decoded_decoded, 192, 192) node decoded_addr_decoded_4 = bits(decoded_addr_decoded_decoded, 191, 191) node decoded_addr_decoded_5 = bits(decoded_addr_decoded_decoded, 190, 190) node decoded_addr_decoded_6 = bits(decoded_addr_decoded_decoded, 189, 189) node decoded_addr_decoded_7 = bits(decoded_addr_decoded_decoded, 188, 188) node decoded_addr_decoded_8 = bits(decoded_addr_decoded_decoded, 187, 187) node decoded_addr_decoded_9 = bits(decoded_addr_decoded_decoded, 186, 186) node decoded_addr_decoded_10 = bits(decoded_addr_decoded_decoded, 185, 185) node decoded_addr_decoded_11 = bits(decoded_addr_decoded_decoded, 184, 184) node decoded_addr_decoded_12 = bits(decoded_addr_decoded_decoded, 183, 183) node decoded_addr_decoded_13 = bits(decoded_addr_decoded_decoded, 182, 182) node decoded_addr_decoded_14 = bits(decoded_addr_decoded_decoded, 181, 181) node decoded_addr_decoded_15 = bits(decoded_addr_decoded_decoded, 180, 180) node decoded_addr_decoded_16 = bits(decoded_addr_decoded_decoded, 179, 179) node decoded_addr_decoded_17 = bits(decoded_addr_decoded_decoded, 178, 178) node decoded_addr_decoded_18 = bits(decoded_addr_decoded_decoded, 177, 177) node decoded_addr_decoded_19 = bits(decoded_addr_decoded_decoded, 176, 176) node decoded_addr_decoded_20 = bits(decoded_addr_decoded_decoded, 175, 175) node decoded_addr_decoded_21 = bits(decoded_addr_decoded_decoded, 174, 174) node decoded_addr_decoded_22 = bits(decoded_addr_decoded_decoded, 173, 173) node decoded_addr_decoded_23 = bits(decoded_addr_decoded_decoded, 172, 172) node decoded_addr_decoded_24 = bits(decoded_addr_decoded_decoded, 171, 171) node decoded_addr_decoded_25 = bits(decoded_addr_decoded_decoded, 170, 170) node decoded_addr_decoded_26 = bits(decoded_addr_decoded_decoded, 169, 169) node decoded_addr_decoded_27 = bits(decoded_addr_decoded_decoded, 168, 168) node decoded_addr_decoded_28 = bits(decoded_addr_decoded_decoded, 167, 167) node decoded_addr_decoded_29 = bits(decoded_addr_decoded_decoded, 166, 166) node decoded_addr_decoded_30 = bits(decoded_addr_decoded_decoded, 165, 165) node decoded_addr_decoded_31 = bits(decoded_addr_decoded_decoded, 164, 164) node decoded_addr_decoded_32 = bits(decoded_addr_decoded_decoded, 163, 163) node decoded_addr_decoded_33 = bits(decoded_addr_decoded_decoded, 162, 162) node decoded_addr_decoded_34 = bits(decoded_addr_decoded_decoded, 161, 161) node decoded_addr_decoded_35 = bits(decoded_addr_decoded_decoded, 160, 160) node decoded_addr_decoded_36 = bits(decoded_addr_decoded_decoded, 159, 159) node decoded_addr_decoded_37 = bits(decoded_addr_decoded_decoded, 158, 158) node decoded_addr_decoded_38 = bits(decoded_addr_decoded_decoded, 157, 157) node decoded_addr_decoded_39 = bits(decoded_addr_decoded_decoded, 156, 156) node decoded_addr_decoded_40 = bits(decoded_addr_decoded_decoded, 155, 155) node decoded_addr_decoded_41 = bits(decoded_addr_decoded_decoded, 154, 154) node decoded_addr_decoded_42 = bits(decoded_addr_decoded_decoded, 153, 153) node decoded_addr_decoded_43 = bits(decoded_addr_decoded_decoded, 152, 152) node decoded_addr_decoded_44 = bits(decoded_addr_decoded_decoded, 151, 151) node decoded_addr_decoded_45 = bits(decoded_addr_decoded_decoded, 150, 150) node decoded_addr_decoded_46 = bits(decoded_addr_decoded_decoded, 149, 149) node decoded_addr_decoded_47 = bits(decoded_addr_decoded_decoded, 148, 148) node decoded_addr_decoded_48 = bits(decoded_addr_decoded_decoded, 147, 147) node decoded_addr_decoded_49 = bits(decoded_addr_decoded_decoded, 146, 146) node decoded_addr_decoded_50 = bits(decoded_addr_decoded_decoded, 145, 145) node decoded_addr_decoded_51 = bits(decoded_addr_decoded_decoded, 144, 144) node decoded_addr_decoded_52 = bits(decoded_addr_decoded_decoded, 143, 143) node decoded_addr_decoded_53 = bits(decoded_addr_decoded_decoded, 142, 142) node decoded_addr_decoded_54 = bits(decoded_addr_decoded_decoded, 141, 141) node decoded_addr_decoded_55 = bits(decoded_addr_decoded_decoded, 140, 140) node decoded_addr_decoded_56 = bits(decoded_addr_decoded_decoded, 139, 139) node decoded_addr_decoded_57 = bits(decoded_addr_decoded_decoded, 138, 138) node decoded_addr_decoded_58 = bits(decoded_addr_decoded_decoded, 137, 137) node decoded_addr_decoded_59 = bits(decoded_addr_decoded_decoded, 136, 136) node decoded_addr_decoded_60 = bits(decoded_addr_decoded_decoded, 135, 135) node decoded_addr_decoded_61 = bits(decoded_addr_decoded_decoded, 134, 134) node decoded_addr_decoded_62 = bits(decoded_addr_decoded_decoded, 133, 133) node decoded_addr_decoded_63 = bits(decoded_addr_decoded_decoded, 132, 132) node decoded_addr_decoded_64 = bits(decoded_addr_decoded_decoded, 131, 131) node decoded_addr_decoded_65 = bits(decoded_addr_decoded_decoded, 130, 130) node decoded_addr_decoded_66 = bits(decoded_addr_decoded_decoded, 129, 129) node decoded_addr_decoded_67 = bits(decoded_addr_decoded_decoded, 128, 128) node decoded_addr_decoded_68 = bits(decoded_addr_decoded_decoded, 127, 127) node decoded_addr_decoded_69 = bits(decoded_addr_decoded_decoded, 126, 126) node decoded_addr_decoded_70 = bits(decoded_addr_decoded_decoded, 125, 125) node decoded_addr_decoded_71 = bits(decoded_addr_decoded_decoded, 124, 124) node decoded_addr_decoded_72 = bits(decoded_addr_decoded_decoded, 123, 123) node decoded_addr_decoded_73 = bits(decoded_addr_decoded_decoded, 122, 122) node decoded_addr_decoded_74 = bits(decoded_addr_decoded_decoded, 121, 121) node decoded_addr_decoded_75 = bits(decoded_addr_decoded_decoded, 120, 120) node decoded_addr_decoded_76 = bits(decoded_addr_decoded_decoded, 119, 119) node decoded_addr_decoded_77 = bits(decoded_addr_decoded_decoded, 118, 118) node decoded_addr_decoded_78 = bits(decoded_addr_decoded_decoded, 117, 117) node decoded_addr_decoded_79 = bits(decoded_addr_decoded_decoded, 116, 116) node decoded_addr_decoded_80 = bits(decoded_addr_decoded_decoded, 115, 115) node decoded_addr_decoded_81 = bits(decoded_addr_decoded_decoded, 114, 114) node decoded_addr_decoded_82 = bits(decoded_addr_decoded_decoded, 113, 113) node decoded_addr_decoded_83 = bits(decoded_addr_decoded_decoded, 112, 112) node decoded_addr_decoded_84 = bits(decoded_addr_decoded_decoded, 111, 111) node decoded_addr_decoded_85 = bits(decoded_addr_decoded_decoded, 110, 110) node decoded_addr_decoded_86 = bits(decoded_addr_decoded_decoded, 109, 109) node decoded_addr_decoded_87 = bits(decoded_addr_decoded_decoded, 108, 108) node decoded_addr_decoded_88 = bits(decoded_addr_decoded_decoded, 107, 107) node decoded_addr_decoded_89 = bits(decoded_addr_decoded_decoded, 106, 106) node decoded_addr_decoded_90 = bits(decoded_addr_decoded_decoded, 105, 105) node decoded_addr_decoded_91 = bits(decoded_addr_decoded_decoded, 104, 104) node decoded_addr_decoded_92 = bits(decoded_addr_decoded_decoded, 103, 103) node decoded_addr_decoded_93 = bits(decoded_addr_decoded_decoded, 102, 102) node decoded_addr_decoded_94 = bits(decoded_addr_decoded_decoded, 101, 101) node decoded_addr_decoded_95 = bits(decoded_addr_decoded_decoded, 100, 100) node decoded_addr_decoded_96 = bits(decoded_addr_decoded_decoded, 99, 99) node decoded_addr_decoded_97 = bits(decoded_addr_decoded_decoded, 98, 98) node decoded_addr_decoded_98 = bits(decoded_addr_decoded_decoded, 97, 97) node decoded_addr_decoded_99 = bits(decoded_addr_decoded_decoded, 96, 96) node decoded_addr_decoded_100 = bits(decoded_addr_decoded_decoded, 95, 95) node decoded_addr_decoded_101 = bits(decoded_addr_decoded_decoded, 94, 94) node decoded_addr_decoded_102 = bits(decoded_addr_decoded_decoded, 93, 93) node decoded_addr_decoded_103 = bits(decoded_addr_decoded_decoded, 92, 92) node decoded_addr_decoded_104 = bits(decoded_addr_decoded_decoded, 91, 91) node decoded_addr_decoded_105 = bits(decoded_addr_decoded_decoded, 90, 90) node decoded_addr_decoded_106 = bits(decoded_addr_decoded_decoded, 89, 89) node decoded_addr_decoded_107 = bits(decoded_addr_decoded_decoded, 88, 88) node decoded_addr_decoded_108 = bits(decoded_addr_decoded_decoded, 87, 87) node decoded_addr_decoded_109 = bits(decoded_addr_decoded_decoded, 86, 86) node decoded_addr_decoded_110 = bits(decoded_addr_decoded_decoded, 85, 85) node decoded_addr_decoded_111 = bits(decoded_addr_decoded_decoded, 84, 84) node decoded_addr_decoded_112 = bits(decoded_addr_decoded_decoded, 83, 83) node decoded_addr_decoded_113 = bits(decoded_addr_decoded_decoded, 82, 82) node decoded_addr_decoded_114 = bits(decoded_addr_decoded_decoded, 81, 81) node decoded_addr_decoded_115 = bits(decoded_addr_decoded_decoded, 80, 80) node decoded_addr_decoded_116 = bits(decoded_addr_decoded_decoded, 79, 79) node decoded_addr_decoded_117 = bits(decoded_addr_decoded_decoded, 78, 78) node decoded_addr_decoded_118 = bits(decoded_addr_decoded_decoded, 77, 77) node decoded_addr_decoded_119 = bits(decoded_addr_decoded_decoded, 76, 76) node decoded_addr_decoded_120 = bits(decoded_addr_decoded_decoded, 75, 75) node decoded_addr_decoded_121 = bits(decoded_addr_decoded_decoded, 74, 74) node decoded_addr_decoded_122 = bits(decoded_addr_decoded_decoded, 73, 73) node decoded_addr_decoded_123 = bits(decoded_addr_decoded_decoded, 72, 72) node decoded_addr_decoded_124 = bits(decoded_addr_decoded_decoded, 71, 71) node decoded_addr_decoded_125 = bits(decoded_addr_decoded_decoded, 70, 70) node decoded_addr_decoded_126 = bits(decoded_addr_decoded_decoded, 69, 69) node decoded_addr_decoded_127 = bits(decoded_addr_decoded_decoded, 68, 68) node decoded_addr_decoded_128 = bits(decoded_addr_decoded_decoded, 67, 67) node decoded_addr_decoded_129 = bits(decoded_addr_decoded_decoded, 66, 66) node decoded_addr_decoded_130 = bits(decoded_addr_decoded_decoded, 65, 65) node decoded_addr_decoded_131 = bits(decoded_addr_decoded_decoded, 64, 64) node decoded_addr_decoded_132 = bits(decoded_addr_decoded_decoded, 63, 63) node decoded_addr_decoded_133 = bits(decoded_addr_decoded_decoded, 62, 62) node decoded_addr_decoded_134 = bits(decoded_addr_decoded_decoded, 61, 61) node decoded_addr_decoded_135 = bits(decoded_addr_decoded_decoded, 60, 60) node decoded_addr_decoded_136 = bits(decoded_addr_decoded_decoded, 59, 59) node decoded_addr_decoded_137 = bits(decoded_addr_decoded_decoded, 58, 58) node decoded_addr_decoded_138 = bits(decoded_addr_decoded_decoded, 57, 57) node decoded_addr_decoded_139 = bits(decoded_addr_decoded_decoded, 56, 56) node decoded_addr_decoded_140 = bits(decoded_addr_decoded_decoded, 55, 55) node decoded_addr_decoded_141 = bits(decoded_addr_decoded_decoded, 54, 54) node decoded_addr_decoded_142 = bits(decoded_addr_decoded_decoded, 53, 53) node decoded_addr_decoded_143 = bits(decoded_addr_decoded_decoded, 52, 52) node decoded_addr_decoded_144 = bits(decoded_addr_decoded_decoded, 51, 51) node decoded_addr_decoded_145 = bits(decoded_addr_decoded_decoded, 50, 50) node decoded_addr_decoded_146 = bits(decoded_addr_decoded_decoded, 49, 49) node decoded_addr_decoded_147 = bits(decoded_addr_decoded_decoded, 48, 48) node decoded_addr_decoded_148 = bits(decoded_addr_decoded_decoded, 47, 47) node decoded_addr_decoded_149 = bits(decoded_addr_decoded_decoded, 46, 46) node decoded_addr_decoded_150 = bits(decoded_addr_decoded_decoded, 45, 45) node decoded_addr_decoded_151 = bits(decoded_addr_decoded_decoded, 44, 44) node decoded_addr_decoded_152 = bits(decoded_addr_decoded_decoded, 43, 43) node decoded_addr_decoded_153 = bits(decoded_addr_decoded_decoded, 42, 42) node decoded_addr_decoded_154 = bits(decoded_addr_decoded_decoded, 41, 41) node decoded_addr_decoded_155 = bits(decoded_addr_decoded_decoded, 40, 40) node decoded_addr_decoded_156 = bits(decoded_addr_decoded_decoded, 39, 39) node decoded_addr_decoded_157 = bits(decoded_addr_decoded_decoded, 38, 38) node decoded_addr_decoded_158 = bits(decoded_addr_decoded_decoded, 37, 37) node decoded_addr_decoded_159 = bits(decoded_addr_decoded_decoded, 36, 36) node decoded_addr_decoded_160 = bits(decoded_addr_decoded_decoded, 35, 35) node decoded_addr_decoded_161 = bits(decoded_addr_decoded_decoded, 34, 34) node decoded_addr_decoded_162 = bits(decoded_addr_decoded_decoded, 33, 33) node decoded_addr_decoded_163 = bits(decoded_addr_decoded_decoded, 32, 32) node decoded_addr_decoded_164 = bits(decoded_addr_decoded_decoded, 31, 31) node decoded_addr_decoded_165 = bits(decoded_addr_decoded_decoded, 30, 30) node decoded_addr_decoded_166 = bits(decoded_addr_decoded_decoded, 29, 29) node decoded_addr_decoded_167 = bits(decoded_addr_decoded_decoded, 28, 28) node decoded_addr_decoded_168 = bits(decoded_addr_decoded_decoded, 27, 27) node decoded_addr_decoded_169 = bits(decoded_addr_decoded_decoded, 26, 26) node decoded_addr_decoded_170 = bits(decoded_addr_decoded_decoded, 25, 25) node decoded_addr_decoded_171 = bits(decoded_addr_decoded_decoded, 24, 24) node decoded_addr_decoded_172 = bits(decoded_addr_decoded_decoded, 23, 23) node decoded_addr_decoded_173 = bits(decoded_addr_decoded_decoded, 22, 22) node decoded_addr_decoded_174 = bits(decoded_addr_decoded_decoded, 21, 21) node decoded_addr_decoded_175 = bits(decoded_addr_decoded_decoded, 20, 20) node decoded_addr_decoded_176 = bits(decoded_addr_decoded_decoded, 19, 19) node decoded_addr_decoded_177 = bits(decoded_addr_decoded_decoded, 18, 18) node decoded_addr_decoded_178 = bits(decoded_addr_decoded_decoded, 17, 17) node decoded_addr_decoded_179 = bits(decoded_addr_decoded_decoded, 16, 16) node decoded_addr_decoded_180 = bits(decoded_addr_decoded_decoded, 15, 15) node decoded_addr_decoded_181 = bits(decoded_addr_decoded_decoded, 14, 14) node decoded_addr_decoded_182 = bits(decoded_addr_decoded_decoded, 13, 13) node decoded_addr_decoded_183 = bits(decoded_addr_decoded_decoded, 12, 12) node decoded_addr_decoded_184 = bits(decoded_addr_decoded_decoded, 11, 11) node decoded_addr_decoded_185 = bits(decoded_addr_decoded_decoded, 10, 10) node decoded_addr_decoded_186 = bits(decoded_addr_decoded_decoded, 9, 9) node decoded_addr_decoded_187 = bits(decoded_addr_decoded_decoded, 8, 8) node decoded_addr_decoded_188 = bits(decoded_addr_decoded_decoded, 7, 7) node decoded_addr_decoded_189 = bits(decoded_addr_decoded_decoded, 6, 6) node decoded_addr_decoded_190 = bits(decoded_addr_decoded_decoded, 5, 5) node decoded_addr_decoded_191 = bits(decoded_addr_decoded_decoded, 4, 4) node decoded_addr_decoded_192 = bits(decoded_addr_decoded_decoded, 3, 3) node decoded_addr_decoded_193 = bits(decoded_addr_decoded_decoded, 2, 2) node decoded_addr_decoded_194 = bits(decoded_addr_decoded_decoded, 1, 1) node decoded_addr_decoded_195 = bits(decoded_addr_decoded_decoded, 0, 0) node decoded_addr_121_2 = bits(decoded_addr_decoded_0, 0, 0) node decoded_addr_66_2 = bits(decoded_addr_decoded_1, 0, 0) node decoded_addr_13_2 = bits(decoded_addr_decoded_2, 0, 0) node decoded_addr_153_2 = bits(decoded_addr_decoded_3, 0, 0) node decoded_addr_115_2 = bits(decoded_addr_decoded_4, 0, 0) node decoded_addr_125_2 = bits(decoded_addr_decoded_5, 0, 0) node decoded_addr_89_2 = bits(decoded_addr_decoded_6, 0, 0) node decoded_addr_135_2 = bits(decoded_addr_decoded_7, 0, 0) node decoded_addr_94_2 = bits(decoded_addr_decoded_8, 0, 0) node decoded_addr_170_2 = bits(decoded_addr_decoded_9, 0, 0) node decoded_addr_173_2 = bits(decoded_addr_decoded_10, 0, 0) node decoded_addr_179_2 = bits(decoded_addr_decoded_11, 0, 0) node decoded_addr_35_2 = bits(decoded_addr_decoded_12, 0, 0) node decoded_addr_172_2 = bits(decoded_addr_decoded_13, 0, 0) node decoded_addr_59_2 = bits(decoded_addr_decoded_14, 0, 0) node decoded_addr_112_2 = bits(decoded_addr_decoded_15, 0, 0) node decoded_addr_69_2 = bits(decoded_addr_decoded_16, 0, 0) node decoded_addr_171_2 = bits(decoded_addr_decoded_17, 0, 0) node decoded_addr_128_2 = bits(decoded_addr_decoded_18, 0, 0) node decoded_addr_156_2 = bits(decoded_addr_decoded_19, 0, 0) node decoded_addr_189_2 = bits(decoded_addr_decoded_20, 0, 0) node decoded_addr_20_2 = bits(decoded_addr_decoded_21, 0, 0) node decoded_addr_34_2 = bits(decoded_addr_decoded_22, 0, 0) node decoded_addr_6_2 = bits(decoded_addr_decoded_23, 0, 0) node decoded_addr_177_2 = bits(decoded_addr_decoded_24, 0, 0) node decoded_addr_105_2 = bits(decoded_addr_decoded_25, 0, 0) node decoded_addr_62_2 = bits(decoded_addr_decoded_26, 0, 0) node decoded_addr_188_2 = bits(decoded_addr_decoded_27, 0, 0) node decoded_addr_148_2 = bits(decoded_addr_decoded_28, 0, 0) node decoded_addr_22_2 = bits(decoded_addr_decoded_29, 0, 0) node decoded_addr_86_2 = bits(decoded_addr_decoded_30, 0, 0) node decoded_addr_141_2 = bits(decoded_addr_decoded_31, 0, 0) node decoded_addr_103_2 = bits(decoded_addr_decoded_32, 0, 0) node decoded_addr_152_2 = bits(decoded_addr_decoded_33, 0, 0) node decoded_addr_73_2 = bits(decoded_addr_decoded_34, 0, 0) node decoded_addr_37_2 = bits(decoded_addr_decoded_35, 0, 0) node decoded_addr_0_2 = bits(decoded_addr_decoded_36, 0, 0) node decoded_addr_72_2 = bits(decoded_addr_decoded_37, 0, 0) node decoded_addr_33_2 = bits(decoded_addr_decoded_38, 0, 0) node decoded_addr_131_2 = bits(decoded_addr_decoded_39, 0, 0) node decoded_addr_180_2 = bits(decoded_addr_decoded_40, 0, 0) node decoded_addr_165_2 = bits(decoded_addr_decoded_41, 0, 0) node decoded_addr_91_2 = bits(decoded_addr_decoded_42, 0, 0) node decoded_addr_176_2 = bits(decoded_addr_decoded_43, 0, 0) node decoded_addr_56_2 = bits(decoded_addr_decoded_44, 0, 0) node decoded_addr_147_2 = bits(decoded_addr_decoded_45, 0, 0) node decoded_addr_119_2 = bits(decoded_addr_decoded_46, 0, 0) node decoded_addr_143_2 = bits(decoded_addr_decoded_47, 0, 0) node decoded_addr_129_2 = bits(decoded_addr_decoded_48, 0, 0) node decoded_addr_104_2 = bits(decoded_addr_decoded_49, 0, 0) node decoded_addr_1_2 = bits(decoded_addr_decoded_50, 0, 0) node decoded_addr_19_2 = bits(decoded_addr_decoded_51, 0, 0) node decoded_addr_96_2 = bits(decoded_addr_decoded_52, 0, 0) node decoded_addr_5_2 = bits(decoded_addr_decoded_53, 0, 0) node decoded_addr_142_2 = bits(decoded_addr_decoded_54, 0, 0) node decoded_addr_49_2 = bits(decoded_addr_decoded_55, 0, 0) node decoded_addr_61_2 = bits(decoded_addr_decoded_56, 0, 0) node decoded_addr_136_2 = bits(decoded_addr_decoded_57, 0, 0) node decoded_addr_45_2 = bits(decoded_addr_decoded_58, 0, 0) node decoded_addr_75_2 = bits(decoded_addr_decoded_59, 0, 0) node decoded_addr_113_2 = bits(decoded_addr_decoded_60, 0, 0) node decoded_addr_99_2 = bits(decoded_addr_decoded_61, 0, 0) node decoded_addr_83_2 = bits(decoded_addr_decoded_62, 0, 0) node decoded_addr_110_2 = bits(decoded_addr_decoded_63, 0, 0) node decoded_addr_44_2 = bits(decoded_addr_decoded_64, 0, 0) node decoded_addr_132_2 = bits(decoded_addr_decoded_65, 0, 0) node decoded_addr_158_2 = bits(decoded_addr_decoded_66, 0, 0) node decoded_addr_30_2 = bits(decoded_addr_decoded_67, 0, 0) node decoded_addr_168_2 = bits(decoded_addr_decoded_68, 0, 0) node decoded_addr_191_2 = bits(decoded_addr_decoded_69, 0, 0) node decoded_addr_160_2 = bits(decoded_addr_decoded_70, 0, 0) node decoded_addr_32_2 = bits(decoded_addr_decoded_71, 0, 0) node decoded_addr_164_2 = bits(decoded_addr_decoded_72, 0, 0) node decoded_addr_21_2 = bits(decoded_addr_decoded_73, 0, 0) node decoded_addr_101_2 = bits(decoded_addr_decoded_74, 0, 0) node decoded_addr_10_2 = bits(decoded_addr_decoded_75, 0, 0) node decoded_addr_76_2 = bits(decoded_addr_decoded_76, 0, 0) node decoded_addr_95_2 = bits(decoded_addr_decoded_77, 0, 0) node decoded_addr_57_2 = bits(decoded_addr_decoded_78, 0, 0) node decoded_addr_137_2 = bits(decoded_addr_decoded_79, 0, 0) node decoded_addr_55_2 = bits(decoded_addr_decoded_80, 0, 0) node decoded_addr_140_2 = bits(decoded_addr_decoded_81, 0, 0) node decoded_addr_74_2 = bits(decoded_addr_decoded_82, 0, 0) node decoded_addr_100_2 = bits(decoded_addr_decoded_83, 0, 0) node decoded_addr_84_2 = bits(decoded_addr_decoded_84, 0, 0) node decoded_addr_114_2 = bits(decoded_addr_decoded_85, 0, 0) node decoded_addr_193_2 = bits(decoded_addr_decoded_86, 0, 0) node decoded_addr_18_2 = bits(decoded_addr_decoded_87, 0, 0) node decoded_addr_159_2 = bits(decoded_addr_decoded_88, 0, 0) node decoded_addr_29_2 = bits(decoded_addr_decoded_89, 0, 0) node decoded_addr_27_2 = bits(decoded_addr_decoded_90, 0, 0) node decoded_addr_40_2 = bits(decoded_addr_decoded_91, 0, 0) node decoded_addr_25_2 = bits(decoded_addr_decoded_92, 0, 0) node decoded_addr_181_2 = bits(decoded_addr_decoded_93, 0, 0) node decoded_addr_9_2 = bits(decoded_addr_decoded_94, 0, 0) node decoded_addr_174_2 = bits(decoded_addr_decoded_95, 0, 0) node decoded_addr_194_2 = bits(decoded_addr_decoded_96, 0, 0) node decoded_addr_60_2 = bits(decoded_addr_decoded_97, 0, 0) node decoded_addr_122_2 = bits(decoded_addr_decoded_98, 0, 0) node decoded_addr_70_2 = bits(decoded_addr_decoded_99, 0, 0) node decoded_addr_92_2 = bits(decoded_addr_decoded_100, 0, 0) node decoded_addr_127_2 = bits(decoded_addr_decoded_101, 0, 0) node decoded_addr_106_2 = bits(decoded_addr_decoded_102, 0, 0) node decoded_addr_87_2 = bits(decoded_addr_decoded_103, 0, 0) node decoded_addr_118_2 = bits(decoded_addr_decoded_104, 0, 0) node decoded_addr_53_2 = bits(decoded_addr_decoded_105, 0, 0) node decoded_addr_79_2 = bits(decoded_addr_decoded_106, 0, 0) node decoded_addr_155_2 = bits(decoded_addr_decoded_107, 0, 0) node decoded_addr_39_2 = bits(decoded_addr_decoded_108, 0, 0) node decoded_addr_166_2 = bits(decoded_addr_decoded_109, 0, 0) node decoded_addr_36_2 = bits(decoded_addr_decoded_110, 0, 0) node decoded_addr_8_2 = bits(decoded_addr_decoded_111, 0, 0) node decoded_addr_38_2 = bits(decoded_addr_decoded_112, 0, 0) node decoded_addr_43_2 = bits(decoded_addr_decoded_113, 0, 0) node decoded_addr_23_2 = bits(decoded_addr_decoded_114, 0, 0) node decoded_addr_187_2 = bits(decoded_addr_decoded_115, 0, 0) node decoded_addr_149_2 = bits(decoded_addr_decoded_116, 0, 0) node decoded_addr_77_2 = bits(decoded_addr_decoded_117, 0, 0) node decoded_addr_185_2 = bits(decoded_addr_decoded_118, 0, 0) node decoded_addr_81_2 = bits(decoded_addr_decoded_119, 0, 0) node decoded_addr_134_2 = bits(decoded_addr_decoded_120, 0, 0) node decoded_addr_111_2 = bits(decoded_addr_decoded_121, 0, 0) node decoded_addr_145_2 = bits(decoded_addr_decoded_122, 0, 0) node decoded_addr_124_2 = bits(decoded_addr_decoded_123, 0, 0) node decoded_addr_102_2 = bits(decoded_addr_decoded_124, 0, 0) node decoded_addr_90_2 = bits(decoded_addr_decoded_125, 0, 0) node decoded_addr_63_2 = bits(decoded_addr_decoded_126, 0, 0) node decoded_addr_192_2 = bits(decoded_addr_decoded_127, 0, 0) node decoded_addr_78_2 = bits(decoded_addr_decoded_128, 0, 0) node decoded_addr_151_2 = bits(decoded_addr_decoded_129, 0, 0) node decoded_addr_51_2 = bits(decoded_addr_decoded_130, 0, 0) node decoded_addr_67_2 = bits(decoded_addr_decoded_131, 0, 0) node decoded_addr_46_2 = bits(decoded_addr_decoded_132, 0, 0) node decoded_addr_54_2 = bits(decoded_addr_decoded_133, 0, 0) node decoded_addr_85_2 = bits(decoded_addr_decoded_134, 0, 0) node decoded_addr_97_2 = bits(decoded_addr_decoded_135, 0, 0) node decoded_addr_120_2 = bits(decoded_addr_decoded_136, 0, 0) node decoded_addr_7_2 = bits(decoded_addr_decoded_137, 0, 0) node decoded_addr_93_2 = bits(decoded_addr_decoded_138, 0, 0) node decoded_addr_42_2 = bits(decoded_addr_decoded_139, 0, 0) node decoded_addr_126_2 = bits(decoded_addr_decoded_140, 0, 0) node decoded_addr_154_2 = bits(decoded_addr_decoded_141, 0, 0) node decoded_addr_28_2 = bits(decoded_addr_decoded_142, 0, 0) node decoded_addr_162_2 = bits(decoded_addr_decoded_143, 0, 0) node decoded_addr_190_2 = bits(decoded_addr_decoded_144, 0, 0) node decoded_addr_182_2 = bits(decoded_addr_decoded_145, 0, 0) node decoded_addr_14_2 = bits(decoded_addr_decoded_146, 0, 0) node decoded_addr_175_2 = bits(decoded_addr_decoded_147, 0, 0) node decoded_addr_17_2 = bits(decoded_addr_decoded_148, 0, 0) node decoded_addr_139_2 = bits(decoded_addr_decoded_149, 0, 0) node decoded_addr_15_2 = bits(decoded_addr_decoded_150, 0, 0) node decoded_addr_80_2 = bits(decoded_addr_decoded_151, 0, 0) node decoded_addr_108_2 = bits(decoded_addr_decoded_152, 0, 0) node decoded_addr_68_2 = bits(decoded_addr_decoded_153, 0, 0) node decoded_addr_47_2 = bits(decoded_addr_decoded_154, 0, 0) node decoded_addr_58_2 = bits(decoded_addr_decoded_155, 0, 0) node decoded_addr_133_2 = bits(decoded_addr_decoded_156, 0, 0) node decoded_addr_71_2 = bits(decoded_addr_decoded_157, 0, 0) node decoded_addr_117_2 = bits(decoded_addr_decoded_158, 0, 0) node decoded_addr_4_2 = bits(decoded_addr_decoded_159, 0, 0) node decoded_addr_109_2 = bits(decoded_addr_decoded_160, 0, 0) node decoded_addr_186_2 = bits(decoded_addr_decoded_161, 0, 0) node decoded_addr_16_2 = bits(decoded_addr_decoded_162, 0, 0) node decoded_addr_150_2 = bits(decoded_addr_decoded_163, 0, 0) node decoded_addr_31_2 = bits(decoded_addr_decoded_164, 0, 0) node decoded_addr_2_2 = bits(decoded_addr_decoded_165, 0, 0) node decoded_addr_82_2 = bits(decoded_addr_decoded_166, 0, 0) node decoded_addr_167_2 = bits(decoded_addr_decoded_167, 0, 0) node decoded_addr_64_2 = bits(decoded_addr_decoded_168, 0, 0) node decoded_addr_195_2 = bits(decoded_addr_decoded_169, 0, 0) node decoded_addr_144_2 = bits(decoded_addr_decoded_170, 0, 0) node decoded_addr_184_2 = bits(decoded_addr_decoded_171, 0, 0) node decoded_addr_169_2 = bits(decoded_addr_decoded_172, 0, 0) node decoded_addr_12_2 = bits(decoded_addr_decoded_173, 0, 0) node decoded_addr_157_2 = bits(decoded_addr_decoded_174, 0, 0) node decoded_addr_130_2 = bits(decoded_addr_decoded_175, 0, 0) node decoded_addr_11_2 = bits(decoded_addr_decoded_176, 0, 0) node decoded_addr_161_2 = bits(decoded_addr_decoded_177, 0, 0) node decoded_addr_107_2 = bits(decoded_addr_decoded_178, 0, 0) node decoded_addr_65_2 = bits(decoded_addr_decoded_179, 0, 0) node decoded_addr_26_2 = bits(decoded_addr_decoded_180, 0, 0) node decoded_addr_178_2 = bits(decoded_addr_decoded_181, 0, 0) node decoded_addr_146_2 = bits(decoded_addr_decoded_182, 0, 0) node decoded_addr_52_2 = bits(decoded_addr_decoded_183, 0, 0) node decoded_addr_88_2 = bits(decoded_addr_decoded_184, 0, 0) node decoded_addr_138_2 = bits(decoded_addr_decoded_185, 0, 0) node decoded_addr_183_2 = bits(decoded_addr_decoded_186, 0, 0) node decoded_addr_41_2 = bits(decoded_addr_decoded_187, 0, 0) node decoded_addr_50_2 = bits(decoded_addr_decoded_188, 0, 0) node decoded_addr_98_2 = bits(decoded_addr_decoded_189, 0, 0) node decoded_addr_123_2 = bits(decoded_addr_decoded_190, 0, 0) node decoded_addr_24_2 = bits(decoded_addr_decoded_191, 0, 0) node decoded_addr_3_2 = bits(decoded_addr_decoded_192, 0, 0) node decoded_addr_48_2 = bits(decoded_addr_decoded_193, 0, 0) node decoded_addr_163_2 = bits(decoded_addr_decoded_194, 0, 0) node decoded_addr_116_2 = bits(decoded_addr_decoded_195, 0, 0) node _wdata_T = bits(io.rw.cmd, 1, 1) node _wdata_T_1 = mux(_wdata_T, io.rw.rdata, UInt<1>(0h0)) node _wdata_T_2 = or(_wdata_T_1, io.rw.wdata) node _wdata_T_3 = bits(io.rw.cmd, 1, 0) node _wdata_T_4 = andr(_wdata_T_3) node _wdata_T_5 = mux(_wdata_T_4, io.rw.wdata, UInt<1>(0h0)) node _wdata_T_6 = not(_wdata_T_5) node wdata = and(_wdata_T_2, _wdata_T_6) node system_insn = eq(io.rw.cmd, UInt<3>(0h4)) node _insn_T = shl(io.rw.addr, 20) node insn = or(UInt<7>(0h73), _insn_T) wire decoded_plaInput : UInt<32> node decoded_invInputs = not(decoded_plaInput) wire decoded : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_invInputs, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_plaInput, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_plaInput, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs, 31, 31) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 31, 31) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_5) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_3_2) node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_4_2) node _decoded_orMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node _decoded_orMatrixOutputs_T_4 = orr(decoded_andMatrixOutputs_1_2) node _decoded_orMatrixOutputs_T_5 = orr(decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo = cat(_decoded_orMatrixOutputs_T_1, _decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_hi_hi_hi = cat(_decoded_orMatrixOutputs_T_5, _decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_hi = cat(_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4) node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded, decoded_invMatrixOutputs connect decoded_plaInput, insn node _T_98 = bits(decoded, 8, 8) node _T_99 = bits(decoded, 7, 7) node _T_100 = bits(decoded, 6, 6) node _T_101 = bits(decoded, 5, 5) node _T_102 = bits(decoded, 4, 4) node _T_103 = bits(decoded, 3, 3) node _T_104 = bits(decoded, 2, 2) node _T_105 = bits(decoded, 1, 1) node _T_106 = bits(decoded, 0, 0) node _T_107 = bits(_T_98, 0, 0) node insn_call = and(system_insn, _T_107) node _T_108 = bits(_T_99, 0, 0) node insn_break = and(system_insn, _T_108) node _T_109 = bits(_T_100, 0, 0) node insn_ret = and(system_insn, _T_109) node _T_110 = bits(_T_101, 0, 0) node insn_cease = and(system_insn, _T_110) node _T_111 = bits(_T_102, 0, 0) node insn_wfi = and(system_insn, _T_111) node _T_112 = bits(_T_103, 0, 0) node _T_113 = and(system_insn, _T_112) node _T_114 = bits(_T_104, 0, 0) node _T_115 = and(system_insn, _T_114) node _T_116 = bits(_T_105, 0, 0) node _T_117 = and(system_insn, _T_116) node _T_118 = bits(_T_106, 0, 0) node _T_119 = and(system_insn, _T_118) node addr = bits(io.decode[0].inst, 31, 20) wire decoded_plaInput_1 : UInt<32> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_1 : UInt<9> node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_invInputs_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_5_2_1 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_plaInput_1, 20, 20) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_1, 21, 21) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_3_2_1 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_invInputs_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_plaInput_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_8_6, decoded_andMatrixOutputs_andMatrixInput_9_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_5_6, decoded_andMatrixOutputs_andMatrixInput_6_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_8) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 22, 22) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs_1, 23, 23) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_1, 24, 24) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 25, 25) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_invInputs_1, 26, 26) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 27, 27) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_plaInput_1, 28, 28) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_plaInput_1, 29, 29) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs_1, 31, 31) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_8_7, decoded_andMatrixOutputs_andMatrixInput_9_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_andMatrixOutputs_andMatrixInput_6_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_9) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_4_2_1 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 30, 30) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs_1, 31, 31) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_11) node _decoded_orMatrixOutputs_T_6 = orr(decoded_andMatrixOutputs_3_2_1) node _decoded_orMatrixOutputs_T_7 = orr(decoded_andMatrixOutputs_4_2_1) node _decoded_orMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8) node _decoded_orMatrixOutputs_T_10 = orr(decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_11 = orr(decoded_andMatrixOutputs_5_2_1) node decoded_orMatrixOutputs_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_7, _decoded_orMatrixOutputs_T_6) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_11, _decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_9) node decoded_orMatrixOutputs_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 8, 8) node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, io.decode[0].inst node _T_120 = bits(decoded_1, 8, 8) node _T_121 = bits(decoded_1, 7, 7) node _T_122 = bits(decoded_1, 6, 6) node _T_123 = bits(decoded_1, 5, 5) node _T_124 = bits(decoded_1, 4, 4) node _T_125 = bits(decoded_1, 3, 3) node _T_126 = bits(decoded_1, 2, 2) node _T_127 = bits(decoded_1, 1, 1) node _T_128 = bits(decoded_1, 0, 0) node _T_129 = bits(_T_120, 0, 0) node is_break = bits(_T_121, 0, 0) node is_ret = bits(_T_122, 0, 0) node _T_130 = bits(_T_123, 0, 0) node is_wfi = bits(_T_124, 0, 0) node is_sfence = bits(_T_125, 0, 0) node is_hfence_vvma = bits(_T_126, 0, 0) node is_hfence_gvma = bits(_T_127, 0, 0) node is_hlsv = bits(_T_128, 0, 0) node _is_counter_T = geq(addr, UInt<12>(0hc00)) node _is_counter_T_1 = lt(addr, UInt<12>(0hc20)) node _is_counter_T_2 = and(_is_counter_T, _is_counter_T_1) node _is_counter_T_3 = geq(addr, UInt<12>(0hc80)) node _is_counter_T_4 = lt(addr, UInt<12>(0hca0)) node _is_counter_T_5 = and(_is_counter_T_3, _is_counter_T_4) node is_counter = or(_is_counter_T_2, _is_counter_T_5) node _allow_wfi_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_wfi_T_1 = or(UInt<1>(0h1), _allow_wfi_T) node _allow_wfi_T_2 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _allow_wfi_T_3 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_wfi_T_4 = eq(reg_hstatus.vtw, UInt<1>(0h0)) node _allow_wfi_T_5 = or(_allow_wfi_T_3, _allow_wfi_T_4) node _allow_wfi_T_6 = and(_allow_wfi_T_2, _allow_wfi_T_5) node allow_wfi = or(_allow_wfi_T_1, _allow_wfi_T_6) node _allow_sfence_vma_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sfence_vma_T_1 = or(UInt<1>(0h1), _allow_sfence_vma_T) node _allow_sfence_vma_T_2 = mux(reg_mstatus.v, reg_hstatus.vtvm, reg_mstatus.tvm) node _allow_sfence_vma_T_3 = eq(_allow_sfence_vma_T_2, UInt<1>(0h0)) node allow_sfence_vma = or(_allow_sfence_vma_T_1, _allow_sfence_vma_T_3) node _allow_hfence_vvma_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hfence_vvma_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hfence_vvma_T_2 = and(_allow_hfence_vvma_T, _allow_hfence_vvma_T_1) node allow_hfence_vvma = or(UInt<1>(0h1), _allow_hfence_vvma_T_2) node _allow_hlsv_T = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_hlsv_T_1 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_hlsv_T_2 = or(_allow_hlsv_T_1, reg_hstatus.hu) node _allow_hlsv_T_3 = and(_allow_hlsv_T, _allow_hlsv_T_2) node allow_hlsv = or(UInt<1>(0h1), _allow_hlsv_T_3) node _allow_sret_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_sret_T_1 = or(UInt<1>(0h1), _allow_sret_T) node _allow_sret_T_2 = mux(reg_mstatus.v, reg_hstatus.vtsr, reg_mstatus.tsr) node _allow_sret_T_3 = eq(_allow_sret_T_2, UInt<1>(0h0)) node allow_sret = or(_allow_sret_T_1, _allow_sret_T_3) node counter_addr = bits(addr, 4, 0) node _allow_counter_T = gt(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_1 = dshr(read_mcounteren, counter_addr) node _allow_counter_T_2 = bits(_allow_counter_T_1, 0, 0) node _allow_counter_T_3 = or(_allow_counter_T, _allow_counter_T_2) node _allow_counter_T_4 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _allow_counter_T_5 = geq(reg_mstatus.prv, UInt<1>(0h1)) node _allow_counter_T_6 = or(_allow_counter_T_4, _allow_counter_T_5) node _allow_counter_T_7 = dshr(read_scounteren, counter_addr) node _allow_counter_T_8 = bits(_allow_counter_T_7, 0, 0) node _allow_counter_T_9 = or(_allow_counter_T_6, _allow_counter_T_8) node _allow_counter_T_10 = and(_allow_counter_T_3, _allow_counter_T_9) node _allow_counter_T_11 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _allow_counter_T_12 = eq(reg_mstatus.v, UInt<1>(0h0)) node _allow_counter_T_13 = or(_allow_counter_T_11, _allow_counter_T_12) node _allow_counter_T_14 = dshr(read_hcounteren, counter_addr) node _allow_counter_T_15 = bits(_allow_counter_T_14, 0, 0) node _allow_counter_T_16 = or(_allow_counter_T_13, _allow_counter_T_15) node allow_counter = and(_allow_counter_T_10, _allow_counter_T_16) node _io_decode_0_fp_illegal_T = eq(io.status.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_1 = eq(reg_vsstatus.fs, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_fp_illegal_T_1) node _io_decode_0_fp_illegal_T_3 = or(_io_decode_0_fp_illegal_T, _io_decode_0_fp_illegal_T_2) node _io_decode_0_fp_illegal_T_4 = bits(reg_misa, 5, 5) node _io_decode_0_fp_illegal_T_5 = eq(_io_decode_0_fp_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_fp_illegal_T_6 = or(_io_decode_0_fp_illegal_T_3, _io_decode_0_fp_illegal_T_5) connect io.decode[0].fp_illegal, _io_decode_0_fp_illegal_T_6 node _io_decode_0_vector_illegal_T = eq(io.status.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_1 = eq(reg_vsstatus.vs, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_vector_illegal_T_1) node _io_decode_0_vector_illegal_T_3 = or(_io_decode_0_vector_illegal_T, _io_decode_0_vector_illegal_T_2) node _io_decode_0_vector_illegal_T_4 = bits(reg_misa, 21, 21) node _io_decode_0_vector_illegal_T_5 = eq(_io_decode_0_vector_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_vector_illegal_T_6 = or(_io_decode_0_vector_illegal_T_3, _io_decode_0_vector_illegal_T_5) connect io.decode[0].vector_illegal, _io_decode_0_vector_illegal_T_6 wire io_decode_0_fp_csr_plaInput : UInt<12> node io_decode_0_fp_csr_invInputs = not(io_decode_0_fp_csr_plaInput) wire io_decode_0_fp_csr_plaOutput : UInt<1> connect io_decode_0_fp_csr_plaOutput, UInt<1>(0h0) connect io_decode_0_fp_csr_plaInput, addr node _io_decode_0_fp_csr_T = bits(io_decode_0_fp_csr_plaOutput, 0, 0) connect io.decode[0].fp_csr, _io_decode_0_fp_csr_T wire io_decode_0_vector_csr_plaInput : UInt<12> node io_decode_0_vector_csr_invInputs = not(io_decode_0_vector_csr_plaInput) wire io_decode_0_vector_csr_plaOutput : UInt<1> connect io_decode_0_vector_csr_plaOutput, UInt<1>(0h0) connect io_decode_0_vector_csr_plaInput, addr node _io_decode_0_vector_csr_T = bits(io_decode_0_vector_csr_plaOutput, 0, 0) connect io.decode[0].vector_csr, _io_decode_0_vector_csr_T node _io_decode_0_rocc_illegal_T = eq(io.status.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_1 = eq(reg_vsstatus.xs, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_2 = and(reg_mstatus.v, _io_decode_0_rocc_illegal_T_1) node _io_decode_0_rocc_illegal_T_3 = or(_io_decode_0_rocc_illegal_T, _io_decode_0_rocc_illegal_T_2) node _io_decode_0_rocc_illegal_T_4 = bits(reg_misa, 23, 23) node _io_decode_0_rocc_illegal_T_5 = eq(_io_decode_0_rocc_illegal_T_4, UInt<1>(0h0)) node _io_decode_0_rocc_illegal_T_6 = or(_io_decode_0_rocc_illegal_T_3, _io_decode_0_rocc_illegal_T_5) connect io.decode[0].rocc_illegal, _io_decode_0_rocc_illegal_T_6 node _csr_addr_legal_T = bits(addr, 9, 8) node _csr_addr_legal_T_1 = geq(reg_mstatus.prv, _csr_addr_legal_T) node _csr_addr_legal_T_2 = eq(reg_mstatus.v, UInt<1>(0h0)) node _csr_addr_legal_T_3 = and(UInt<1>(0h0), _csr_addr_legal_T_2) node _csr_addr_legal_T_4 = eq(reg_mstatus.prv, UInt<1>(0h1)) node _csr_addr_legal_T_5 = and(_csr_addr_legal_T_3, _csr_addr_legal_T_4) node _csr_addr_legal_T_6 = bits(addr, 9, 8) node _csr_addr_legal_T_7 = eq(_csr_addr_legal_T_6, UInt<2>(0h2)) node _csr_addr_legal_T_8 = and(_csr_addr_legal_T_5, _csr_addr_legal_T_7) node csr_addr_legal = or(_csr_addr_legal_T_1, _csr_addr_legal_T_8) node _csr_exists_T = eq(addr, UInt<11>(0h7a0)) node _csr_exists_T_1 = eq(addr, UInt<11>(0h7a1)) node _csr_exists_T_2 = eq(addr, UInt<11>(0h7a2)) node _csr_exists_T_3 = eq(addr, UInt<11>(0h7a3)) node _csr_exists_T_4 = eq(addr, UInt<10>(0h301)) node _csr_exists_T_5 = eq(addr, UInt<10>(0h300)) node _csr_exists_T_6 = eq(addr, UInt<10>(0h305)) node _csr_exists_T_7 = eq(addr, UInt<10>(0h344)) node _csr_exists_T_8 = eq(addr, UInt<10>(0h304)) node _csr_exists_T_9 = eq(addr, UInt<10>(0h340)) node _csr_exists_T_10 = eq(addr, UInt<10>(0h341)) node _csr_exists_T_11 = eq(addr, UInt<10>(0h343)) node _csr_exists_T_12 = eq(addr, UInt<10>(0h342)) node _csr_exists_T_13 = eq(addr, UInt<12>(0hf14)) node _csr_exists_T_14 = eq(addr, UInt<11>(0h7b0)) node _csr_exists_T_15 = eq(addr, UInt<11>(0h7b1)) node _csr_exists_T_16 = eq(addr, UInt<11>(0h7b2)) node _csr_exists_T_17 = eq(addr, UInt<10>(0h320)) node _csr_exists_T_18 = eq(addr, UInt<12>(0hb00)) node _csr_exists_T_19 = eq(addr, UInt<12>(0hb02)) node _csr_exists_T_20 = eq(addr, UInt<10>(0h323)) node _csr_exists_T_21 = eq(addr, UInt<12>(0hb03)) node _csr_exists_T_22 = eq(addr, UInt<12>(0hc03)) node _csr_exists_T_23 = eq(addr, UInt<12>(0hb83)) node _csr_exists_T_24 = eq(addr, UInt<12>(0hc83)) node _csr_exists_T_25 = eq(addr, UInt<10>(0h324)) node _csr_exists_T_26 = eq(addr, UInt<12>(0hb04)) node _csr_exists_T_27 = eq(addr, UInt<12>(0hc04)) node _csr_exists_T_28 = eq(addr, UInt<12>(0hb84)) node _csr_exists_T_29 = eq(addr, UInt<12>(0hc84)) node _csr_exists_T_30 = eq(addr, UInt<10>(0h325)) node _csr_exists_T_31 = eq(addr, UInt<12>(0hb05)) node _csr_exists_T_32 = eq(addr, UInt<12>(0hc05)) node _csr_exists_T_33 = eq(addr, UInt<12>(0hb85)) node _csr_exists_T_34 = eq(addr, UInt<12>(0hc85)) node _csr_exists_T_35 = eq(addr, UInt<10>(0h326)) node _csr_exists_T_36 = eq(addr, UInt<12>(0hb06)) node _csr_exists_T_37 = eq(addr, UInt<12>(0hc06)) node _csr_exists_T_38 = eq(addr, UInt<12>(0hb86)) node _csr_exists_T_39 = eq(addr, UInt<12>(0hc86)) node _csr_exists_T_40 = eq(addr, UInt<10>(0h327)) node _csr_exists_T_41 = eq(addr, UInt<12>(0hb07)) node _csr_exists_T_42 = eq(addr, UInt<12>(0hc07)) node _csr_exists_T_43 = eq(addr, UInt<12>(0hb87)) node _csr_exists_T_44 = eq(addr, UInt<12>(0hc87)) node _csr_exists_T_45 = eq(addr, UInt<10>(0h328)) node _csr_exists_T_46 = eq(addr, UInt<12>(0hb08)) node _csr_exists_T_47 = eq(addr, UInt<12>(0hc08)) node _csr_exists_T_48 = eq(addr, UInt<12>(0hb88)) node _csr_exists_T_49 = eq(addr, UInt<12>(0hc88)) node _csr_exists_T_50 = eq(addr, UInt<10>(0h329)) node _csr_exists_T_51 = eq(addr, UInt<12>(0hb09)) node _csr_exists_T_52 = eq(addr, UInt<12>(0hc09)) node _csr_exists_T_53 = eq(addr, UInt<12>(0hb89)) node _csr_exists_T_54 = eq(addr, UInt<12>(0hc89)) node _csr_exists_T_55 = eq(addr, UInt<10>(0h32a)) node _csr_exists_T_56 = eq(addr, UInt<12>(0hb0a)) node _csr_exists_T_57 = eq(addr, UInt<12>(0hc0a)) node _csr_exists_T_58 = eq(addr, UInt<12>(0hb8a)) node _csr_exists_T_59 = eq(addr, UInt<12>(0hc8a)) node _csr_exists_T_60 = eq(addr, UInt<10>(0h32b)) node _csr_exists_T_61 = eq(addr, UInt<12>(0hb0b)) node _csr_exists_T_62 = eq(addr, UInt<12>(0hc0b)) node _csr_exists_T_63 = eq(addr, UInt<12>(0hb8b)) node _csr_exists_T_64 = eq(addr, UInt<12>(0hc8b)) node _csr_exists_T_65 = eq(addr, UInt<10>(0h32c)) node _csr_exists_T_66 = eq(addr, UInt<12>(0hb0c)) node _csr_exists_T_67 = eq(addr, UInt<12>(0hc0c)) node _csr_exists_T_68 = eq(addr, UInt<12>(0hb8c)) node _csr_exists_T_69 = eq(addr, UInt<12>(0hc8c)) node _csr_exists_T_70 = eq(addr, UInt<10>(0h32d)) node _csr_exists_T_71 = eq(addr, UInt<12>(0hb0d)) node _csr_exists_T_72 = eq(addr, UInt<12>(0hc0d)) node _csr_exists_T_73 = eq(addr, UInt<12>(0hb8d)) node _csr_exists_T_74 = eq(addr, UInt<12>(0hc8d)) node _csr_exists_T_75 = eq(addr, UInt<10>(0h32e)) node _csr_exists_T_76 = eq(addr, UInt<12>(0hb0e)) node _csr_exists_T_77 = eq(addr, UInt<12>(0hc0e)) node _csr_exists_T_78 = eq(addr, UInt<12>(0hb8e)) node _csr_exists_T_79 = eq(addr, UInt<12>(0hc8e)) node _csr_exists_T_80 = eq(addr, UInt<10>(0h32f)) node _csr_exists_T_81 = eq(addr, UInt<12>(0hb0f)) node _csr_exists_T_82 = eq(addr, UInt<12>(0hc0f)) node _csr_exists_T_83 = eq(addr, UInt<12>(0hb8f)) node _csr_exists_T_84 = eq(addr, UInt<12>(0hc8f)) node _csr_exists_T_85 = eq(addr, UInt<10>(0h330)) node _csr_exists_T_86 = eq(addr, UInt<12>(0hb10)) node _csr_exists_T_87 = eq(addr, UInt<12>(0hc10)) node _csr_exists_T_88 = eq(addr, UInt<12>(0hb90)) node _csr_exists_T_89 = eq(addr, UInt<12>(0hc90)) node _csr_exists_T_90 = eq(addr, UInt<10>(0h331)) node _csr_exists_T_91 = eq(addr, UInt<12>(0hb11)) node _csr_exists_T_92 = eq(addr, UInt<12>(0hc11)) node _csr_exists_T_93 = eq(addr, UInt<12>(0hb91)) node _csr_exists_T_94 = eq(addr, UInt<12>(0hc91)) node _csr_exists_T_95 = eq(addr, UInt<10>(0h332)) node _csr_exists_T_96 = eq(addr, UInt<12>(0hb12)) node _csr_exists_T_97 = eq(addr, UInt<12>(0hc12)) node _csr_exists_T_98 = eq(addr, UInt<12>(0hb92)) node _csr_exists_T_99 = eq(addr, UInt<12>(0hc92)) node _csr_exists_T_100 = eq(addr, UInt<10>(0h333)) node _csr_exists_T_101 = eq(addr, UInt<12>(0hb13)) node _csr_exists_T_102 = eq(addr, UInt<12>(0hc13)) node _csr_exists_T_103 = eq(addr, UInt<12>(0hb93)) node _csr_exists_T_104 = eq(addr, UInt<12>(0hc93)) node _csr_exists_T_105 = eq(addr, UInt<10>(0h334)) node _csr_exists_T_106 = eq(addr, UInt<12>(0hb14)) node _csr_exists_T_107 = eq(addr, UInt<12>(0hc14)) node _csr_exists_T_108 = eq(addr, UInt<12>(0hb94)) node _csr_exists_T_109 = eq(addr, UInt<12>(0hc94)) node _csr_exists_T_110 = eq(addr, UInt<10>(0h335)) node _csr_exists_T_111 = eq(addr, UInt<12>(0hb15)) node _csr_exists_T_112 = eq(addr, UInt<12>(0hc15)) node _csr_exists_T_113 = eq(addr, UInt<12>(0hb95)) node _csr_exists_T_114 = eq(addr, UInt<12>(0hc95)) node _csr_exists_T_115 = eq(addr, UInt<10>(0h336)) node _csr_exists_T_116 = eq(addr, UInt<12>(0hb16)) node _csr_exists_T_117 = eq(addr, UInt<12>(0hc16)) node _csr_exists_T_118 = eq(addr, UInt<12>(0hb96)) node _csr_exists_T_119 = eq(addr, UInt<12>(0hc96)) node _csr_exists_T_120 = eq(addr, UInt<10>(0h337)) node _csr_exists_T_121 = eq(addr, UInt<12>(0hb17)) node _csr_exists_T_122 = eq(addr, UInt<12>(0hc17)) node _csr_exists_T_123 = eq(addr, UInt<12>(0hb97)) node _csr_exists_T_124 = eq(addr, UInt<12>(0hc97)) node _csr_exists_T_125 = eq(addr, UInt<10>(0h338)) node _csr_exists_T_126 = eq(addr, UInt<12>(0hb18)) node _csr_exists_T_127 = eq(addr, UInt<12>(0hc18)) node _csr_exists_T_128 = eq(addr, UInt<12>(0hb98)) node _csr_exists_T_129 = eq(addr, UInt<12>(0hc98)) node _csr_exists_T_130 = eq(addr, UInt<10>(0h339)) node _csr_exists_T_131 = eq(addr, UInt<12>(0hb19)) node _csr_exists_T_132 = eq(addr, UInt<12>(0hc19)) node _csr_exists_T_133 = eq(addr, UInt<12>(0hb99)) node _csr_exists_T_134 = eq(addr, UInt<12>(0hc99)) node _csr_exists_T_135 = eq(addr, UInt<10>(0h33a)) node _csr_exists_T_136 = eq(addr, UInt<12>(0hb1a)) node _csr_exists_T_137 = eq(addr, UInt<12>(0hc1a)) node _csr_exists_T_138 = eq(addr, UInt<12>(0hb9a)) node _csr_exists_T_139 = eq(addr, UInt<12>(0hc9a)) node _csr_exists_T_140 = eq(addr, UInt<10>(0h33b)) node _csr_exists_T_141 = eq(addr, UInt<12>(0hb1b)) node _csr_exists_T_142 = eq(addr, UInt<12>(0hc1b)) node _csr_exists_T_143 = eq(addr, UInt<12>(0hb9b)) node _csr_exists_T_144 = eq(addr, UInt<12>(0hc9b)) node _csr_exists_T_145 = eq(addr, UInt<10>(0h33c)) node _csr_exists_T_146 = eq(addr, UInt<12>(0hb1c)) node _csr_exists_T_147 = eq(addr, UInt<12>(0hc1c)) node _csr_exists_T_148 = eq(addr, UInt<12>(0hb9c)) node _csr_exists_T_149 = eq(addr, UInt<12>(0hc9c)) node _csr_exists_T_150 = eq(addr, UInt<10>(0h33d)) node _csr_exists_T_151 = eq(addr, UInt<12>(0hb1d)) node _csr_exists_T_152 = eq(addr, UInt<12>(0hc1d)) node _csr_exists_T_153 = eq(addr, UInt<12>(0hb9d)) node _csr_exists_T_154 = eq(addr, UInt<12>(0hc9d)) node _csr_exists_T_155 = eq(addr, UInt<10>(0h33e)) node _csr_exists_T_156 = eq(addr, UInt<12>(0hb1e)) node _csr_exists_T_157 = eq(addr, UInt<12>(0hc1e)) node _csr_exists_T_158 = eq(addr, UInt<12>(0hb9e)) node _csr_exists_T_159 = eq(addr, UInt<12>(0hc9e)) node _csr_exists_T_160 = eq(addr, UInt<10>(0h33f)) node _csr_exists_T_161 = eq(addr, UInt<12>(0hb1f)) node _csr_exists_T_162 = eq(addr, UInt<12>(0hc1f)) node _csr_exists_T_163 = eq(addr, UInt<12>(0hb9f)) node _csr_exists_T_164 = eq(addr, UInt<12>(0hc9f)) node _csr_exists_T_165 = eq(addr, UInt<12>(0hc00)) node _csr_exists_T_166 = eq(addr, UInt<12>(0hc02)) node _csr_exists_T_167 = eq(addr, UInt<12>(0hb80)) node _csr_exists_T_168 = eq(addr, UInt<12>(0hb82)) node _csr_exists_T_169 = eq(addr, UInt<12>(0hc80)) node _csr_exists_T_170 = eq(addr, UInt<12>(0hc82)) node _csr_exists_T_171 = eq(addr, UInt<10>(0h3a0)) node _csr_exists_T_172 = eq(addr, UInt<10>(0h3a1)) node _csr_exists_T_173 = eq(addr, UInt<10>(0h3a2)) node _csr_exists_T_174 = eq(addr, UInt<10>(0h3a3)) node _csr_exists_T_175 = eq(addr, UInt<10>(0h3b0)) node _csr_exists_T_176 = eq(addr, UInt<10>(0h3b1)) node _csr_exists_T_177 = eq(addr, UInt<10>(0h3b2)) node _csr_exists_T_178 = eq(addr, UInt<10>(0h3b3)) node _csr_exists_T_179 = eq(addr, UInt<10>(0h3b4)) node _csr_exists_T_180 = eq(addr, UInt<10>(0h3b5)) node _csr_exists_T_181 = eq(addr, UInt<10>(0h3b6)) node _csr_exists_T_182 = eq(addr, UInt<10>(0h3b7)) node _csr_exists_T_183 = eq(addr, UInt<10>(0h3b8)) node _csr_exists_T_184 = eq(addr, UInt<10>(0h3b9)) node _csr_exists_T_185 = eq(addr, UInt<10>(0h3ba)) node _csr_exists_T_186 = eq(addr, UInt<10>(0h3bb)) node _csr_exists_T_187 = eq(addr, UInt<10>(0h3bc)) node _csr_exists_T_188 = eq(addr, UInt<10>(0h3bd)) node _csr_exists_T_189 = eq(addr, UInt<10>(0h3be)) node _csr_exists_T_190 = eq(addr, UInt<10>(0h3bf)) node _csr_exists_T_191 = eq(addr, UInt<11>(0h7c1)) node _csr_exists_T_192 = eq(addr, UInt<12>(0hf12)) node _csr_exists_T_193 = eq(addr, UInt<12>(0hf11)) node _csr_exists_T_194 = eq(addr, UInt<12>(0hf13)) node _csr_exists_T_195 = eq(addr, UInt<12>(0hf15)) node _csr_exists_T_196 = or(_csr_exists_T, _csr_exists_T_1) node _csr_exists_T_197 = or(_csr_exists_T_196, _csr_exists_T_2) node _csr_exists_T_198 = or(_csr_exists_T_197, _csr_exists_T_3) node _csr_exists_T_199 = or(_csr_exists_T_198, _csr_exists_T_4) node _csr_exists_T_200 = or(_csr_exists_T_199, _csr_exists_T_5) node _csr_exists_T_201 = or(_csr_exists_T_200, _csr_exists_T_6) node _csr_exists_T_202 = or(_csr_exists_T_201, _csr_exists_T_7) node _csr_exists_T_203 = or(_csr_exists_T_202, _csr_exists_T_8) node _csr_exists_T_204 = or(_csr_exists_T_203, _csr_exists_T_9) node _csr_exists_T_205 = or(_csr_exists_T_204, _csr_exists_T_10) node _csr_exists_T_206 = or(_csr_exists_T_205, _csr_exists_T_11) node _csr_exists_T_207 = or(_csr_exists_T_206, _csr_exists_T_12) node _csr_exists_T_208 = or(_csr_exists_T_207, _csr_exists_T_13) node _csr_exists_T_209 = or(_csr_exists_T_208, _csr_exists_T_14) node _csr_exists_T_210 = or(_csr_exists_T_209, _csr_exists_T_15) node _csr_exists_T_211 = or(_csr_exists_T_210, _csr_exists_T_16) node _csr_exists_T_212 = or(_csr_exists_T_211, _csr_exists_T_17) node _csr_exists_T_213 = or(_csr_exists_T_212, _csr_exists_T_18) node _csr_exists_T_214 = or(_csr_exists_T_213, _csr_exists_T_19) node _csr_exists_T_215 = or(_csr_exists_T_214, _csr_exists_T_20) node _csr_exists_T_216 = or(_csr_exists_T_215, _csr_exists_T_21) node _csr_exists_T_217 = or(_csr_exists_T_216, _csr_exists_T_22) node _csr_exists_T_218 = or(_csr_exists_T_217, _csr_exists_T_23) node _csr_exists_T_219 = or(_csr_exists_T_218, _csr_exists_T_24) node _csr_exists_T_220 = or(_csr_exists_T_219, _csr_exists_T_25) node _csr_exists_T_221 = or(_csr_exists_T_220, _csr_exists_T_26) node _csr_exists_T_222 = or(_csr_exists_T_221, _csr_exists_T_27) node _csr_exists_T_223 = or(_csr_exists_T_222, _csr_exists_T_28) node _csr_exists_T_224 = or(_csr_exists_T_223, _csr_exists_T_29) node _csr_exists_T_225 = or(_csr_exists_T_224, _csr_exists_T_30) node _csr_exists_T_226 = or(_csr_exists_T_225, _csr_exists_T_31) node _csr_exists_T_227 = or(_csr_exists_T_226, _csr_exists_T_32) node _csr_exists_T_228 = or(_csr_exists_T_227, _csr_exists_T_33) node _csr_exists_T_229 = or(_csr_exists_T_228, _csr_exists_T_34) node _csr_exists_T_230 = or(_csr_exists_T_229, _csr_exists_T_35) node _csr_exists_T_231 = or(_csr_exists_T_230, _csr_exists_T_36) node _csr_exists_T_232 = or(_csr_exists_T_231, _csr_exists_T_37) node _csr_exists_T_233 = or(_csr_exists_T_232, _csr_exists_T_38) node _csr_exists_T_234 = or(_csr_exists_T_233, _csr_exists_T_39) node _csr_exists_T_235 = or(_csr_exists_T_234, _csr_exists_T_40) node _csr_exists_T_236 = or(_csr_exists_T_235, _csr_exists_T_41) node _csr_exists_T_237 = or(_csr_exists_T_236, _csr_exists_T_42) node _csr_exists_T_238 = or(_csr_exists_T_237, _csr_exists_T_43) node _csr_exists_T_239 = or(_csr_exists_T_238, _csr_exists_T_44) node _csr_exists_T_240 = or(_csr_exists_T_239, _csr_exists_T_45) node _csr_exists_T_241 = or(_csr_exists_T_240, _csr_exists_T_46) node _csr_exists_T_242 = or(_csr_exists_T_241, _csr_exists_T_47) node _csr_exists_T_243 = or(_csr_exists_T_242, _csr_exists_T_48) node _csr_exists_T_244 = or(_csr_exists_T_243, _csr_exists_T_49) node _csr_exists_T_245 = or(_csr_exists_T_244, _csr_exists_T_50) node _csr_exists_T_246 = or(_csr_exists_T_245, _csr_exists_T_51) node _csr_exists_T_247 = or(_csr_exists_T_246, _csr_exists_T_52) node _csr_exists_T_248 = or(_csr_exists_T_247, _csr_exists_T_53) node _csr_exists_T_249 = or(_csr_exists_T_248, _csr_exists_T_54) node _csr_exists_T_250 = or(_csr_exists_T_249, _csr_exists_T_55) node _csr_exists_T_251 = or(_csr_exists_T_250, _csr_exists_T_56) node _csr_exists_T_252 = or(_csr_exists_T_251, _csr_exists_T_57) node _csr_exists_T_253 = or(_csr_exists_T_252, _csr_exists_T_58) node _csr_exists_T_254 = or(_csr_exists_T_253, _csr_exists_T_59) node _csr_exists_T_255 = or(_csr_exists_T_254, _csr_exists_T_60) node _csr_exists_T_256 = or(_csr_exists_T_255, _csr_exists_T_61) node _csr_exists_T_257 = or(_csr_exists_T_256, _csr_exists_T_62) node _csr_exists_T_258 = or(_csr_exists_T_257, _csr_exists_T_63) node _csr_exists_T_259 = or(_csr_exists_T_258, _csr_exists_T_64) node _csr_exists_T_260 = or(_csr_exists_T_259, _csr_exists_T_65) node _csr_exists_T_261 = or(_csr_exists_T_260, _csr_exists_T_66) node _csr_exists_T_262 = or(_csr_exists_T_261, _csr_exists_T_67) node _csr_exists_T_263 = or(_csr_exists_T_262, _csr_exists_T_68) node _csr_exists_T_264 = or(_csr_exists_T_263, _csr_exists_T_69) node _csr_exists_T_265 = or(_csr_exists_T_264, _csr_exists_T_70) node _csr_exists_T_266 = or(_csr_exists_T_265, _csr_exists_T_71) node _csr_exists_T_267 = or(_csr_exists_T_266, _csr_exists_T_72) node _csr_exists_T_268 = or(_csr_exists_T_267, _csr_exists_T_73) node _csr_exists_T_269 = or(_csr_exists_T_268, _csr_exists_T_74) node _csr_exists_T_270 = or(_csr_exists_T_269, _csr_exists_T_75) node _csr_exists_T_271 = or(_csr_exists_T_270, _csr_exists_T_76) node _csr_exists_T_272 = or(_csr_exists_T_271, _csr_exists_T_77) node _csr_exists_T_273 = or(_csr_exists_T_272, _csr_exists_T_78) node _csr_exists_T_274 = or(_csr_exists_T_273, _csr_exists_T_79) node _csr_exists_T_275 = or(_csr_exists_T_274, _csr_exists_T_80) node _csr_exists_T_276 = or(_csr_exists_T_275, _csr_exists_T_81) node _csr_exists_T_277 = or(_csr_exists_T_276, _csr_exists_T_82) node _csr_exists_T_278 = or(_csr_exists_T_277, _csr_exists_T_83) node _csr_exists_T_279 = or(_csr_exists_T_278, _csr_exists_T_84) node _csr_exists_T_280 = or(_csr_exists_T_279, _csr_exists_T_85) node _csr_exists_T_281 = or(_csr_exists_T_280, _csr_exists_T_86) node _csr_exists_T_282 = or(_csr_exists_T_281, _csr_exists_T_87) node _csr_exists_T_283 = or(_csr_exists_T_282, _csr_exists_T_88) node _csr_exists_T_284 = or(_csr_exists_T_283, _csr_exists_T_89) node _csr_exists_T_285 = or(_csr_exists_T_284, _csr_exists_T_90) node _csr_exists_T_286 = or(_csr_exists_T_285, _csr_exists_T_91) node _csr_exists_T_287 = or(_csr_exists_T_286, _csr_exists_T_92) node _csr_exists_T_288 = or(_csr_exists_T_287, _csr_exists_T_93) node _csr_exists_T_289 = or(_csr_exists_T_288, _csr_exists_T_94) node _csr_exists_T_290 = or(_csr_exists_T_289, _csr_exists_T_95) node _csr_exists_T_291 = or(_csr_exists_T_290, _csr_exists_T_96) node _csr_exists_T_292 = or(_csr_exists_T_291, _csr_exists_T_97) node _csr_exists_T_293 = or(_csr_exists_T_292, _csr_exists_T_98) node _csr_exists_T_294 = or(_csr_exists_T_293, _csr_exists_T_99) node _csr_exists_T_295 = or(_csr_exists_T_294, _csr_exists_T_100) node _csr_exists_T_296 = or(_csr_exists_T_295, _csr_exists_T_101) node _csr_exists_T_297 = or(_csr_exists_T_296, _csr_exists_T_102) node _csr_exists_T_298 = or(_csr_exists_T_297, _csr_exists_T_103) node _csr_exists_T_299 = or(_csr_exists_T_298, _csr_exists_T_104) node _csr_exists_T_300 = or(_csr_exists_T_299, _csr_exists_T_105) node _csr_exists_T_301 = or(_csr_exists_T_300, _csr_exists_T_106) node _csr_exists_T_302 = or(_csr_exists_T_301, _csr_exists_T_107) node _csr_exists_T_303 = or(_csr_exists_T_302, _csr_exists_T_108) node _csr_exists_T_304 = or(_csr_exists_T_303, _csr_exists_T_109) node _csr_exists_T_305 = or(_csr_exists_T_304, _csr_exists_T_110) node _csr_exists_T_306 = or(_csr_exists_T_305, _csr_exists_T_111) node _csr_exists_T_307 = or(_csr_exists_T_306, _csr_exists_T_112) node _csr_exists_T_308 = or(_csr_exists_T_307, _csr_exists_T_113) node _csr_exists_T_309 = or(_csr_exists_T_308, _csr_exists_T_114) node _csr_exists_T_310 = or(_csr_exists_T_309, _csr_exists_T_115) node _csr_exists_T_311 = or(_csr_exists_T_310, _csr_exists_T_116) node _csr_exists_T_312 = or(_csr_exists_T_311, _csr_exists_T_117) node _csr_exists_T_313 = or(_csr_exists_T_312, _csr_exists_T_118) node _csr_exists_T_314 = or(_csr_exists_T_313, _csr_exists_T_119) node _csr_exists_T_315 = or(_csr_exists_T_314, _csr_exists_T_120) node _csr_exists_T_316 = or(_csr_exists_T_315, _csr_exists_T_121) node _csr_exists_T_317 = or(_csr_exists_T_316, _csr_exists_T_122) node _csr_exists_T_318 = or(_csr_exists_T_317, _csr_exists_T_123) node _csr_exists_T_319 = or(_csr_exists_T_318, _csr_exists_T_124) node _csr_exists_T_320 = or(_csr_exists_T_319, _csr_exists_T_125) node _csr_exists_T_321 = or(_csr_exists_T_320, _csr_exists_T_126) node _csr_exists_T_322 = or(_csr_exists_T_321, _csr_exists_T_127) node _csr_exists_T_323 = or(_csr_exists_T_322, _csr_exists_T_128) node _csr_exists_T_324 = or(_csr_exists_T_323, _csr_exists_T_129) node _csr_exists_T_325 = or(_csr_exists_T_324, _csr_exists_T_130) node _csr_exists_T_326 = or(_csr_exists_T_325, _csr_exists_T_131) node _csr_exists_T_327 = or(_csr_exists_T_326, _csr_exists_T_132) node _csr_exists_T_328 = or(_csr_exists_T_327, _csr_exists_T_133) node _csr_exists_T_329 = or(_csr_exists_T_328, _csr_exists_T_134) node _csr_exists_T_330 = or(_csr_exists_T_329, _csr_exists_T_135) node _csr_exists_T_331 = or(_csr_exists_T_330, _csr_exists_T_136) node _csr_exists_T_332 = or(_csr_exists_T_331, _csr_exists_T_137) node _csr_exists_T_333 = or(_csr_exists_T_332, _csr_exists_T_138) node _csr_exists_T_334 = or(_csr_exists_T_333, _csr_exists_T_139) node _csr_exists_T_335 = or(_csr_exists_T_334, _csr_exists_T_140) node _csr_exists_T_336 = or(_csr_exists_T_335, _csr_exists_T_141) node _csr_exists_T_337 = or(_csr_exists_T_336, _csr_exists_T_142) node _csr_exists_T_338 = or(_csr_exists_T_337, _csr_exists_T_143) node _csr_exists_T_339 = or(_csr_exists_T_338, _csr_exists_T_144) node _csr_exists_T_340 = or(_csr_exists_T_339, _csr_exists_T_145) node _csr_exists_T_341 = or(_csr_exists_T_340, _csr_exists_T_146) node _csr_exists_T_342 = or(_csr_exists_T_341, _csr_exists_T_147) node _csr_exists_T_343 = or(_csr_exists_T_342, _csr_exists_T_148) node _csr_exists_T_344 = or(_csr_exists_T_343, _csr_exists_T_149) node _csr_exists_T_345 = or(_csr_exists_T_344, _csr_exists_T_150) node _csr_exists_T_346 = or(_csr_exists_T_345, _csr_exists_T_151) node _csr_exists_T_347 = or(_csr_exists_T_346, _csr_exists_T_152) node _csr_exists_T_348 = or(_csr_exists_T_347, _csr_exists_T_153) node _csr_exists_T_349 = or(_csr_exists_T_348, _csr_exists_T_154) node _csr_exists_T_350 = or(_csr_exists_T_349, _csr_exists_T_155) node _csr_exists_T_351 = or(_csr_exists_T_350, _csr_exists_T_156) node _csr_exists_T_352 = or(_csr_exists_T_351, _csr_exists_T_157) node _csr_exists_T_353 = or(_csr_exists_T_352, _csr_exists_T_158) node _csr_exists_T_354 = or(_csr_exists_T_353, _csr_exists_T_159) node _csr_exists_T_355 = or(_csr_exists_T_354, _csr_exists_T_160) node _csr_exists_T_356 = or(_csr_exists_T_355, _csr_exists_T_161) node _csr_exists_T_357 = or(_csr_exists_T_356, _csr_exists_T_162) node _csr_exists_T_358 = or(_csr_exists_T_357, _csr_exists_T_163) node _csr_exists_T_359 = or(_csr_exists_T_358, _csr_exists_T_164) node _csr_exists_T_360 = or(_csr_exists_T_359, _csr_exists_T_165) node _csr_exists_T_361 = or(_csr_exists_T_360, _csr_exists_T_166) node _csr_exists_T_362 = or(_csr_exists_T_361, _csr_exists_T_167) node _csr_exists_T_363 = or(_csr_exists_T_362, _csr_exists_T_168) node _csr_exists_T_364 = or(_csr_exists_T_363, _csr_exists_T_169) node _csr_exists_T_365 = or(_csr_exists_T_364, _csr_exists_T_170) node _csr_exists_T_366 = or(_csr_exists_T_365, _csr_exists_T_171) node _csr_exists_T_367 = or(_csr_exists_T_366, _csr_exists_T_172) node _csr_exists_T_368 = or(_csr_exists_T_367, _csr_exists_T_173) node _csr_exists_T_369 = or(_csr_exists_T_368, _csr_exists_T_174) node _csr_exists_T_370 = or(_csr_exists_T_369, _csr_exists_T_175) node _csr_exists_T_371 = or(_csr_exists_T_370, _csr_exists_T_176) node _csr_exists_T_372 = or(_csr_exists_T_371, _csr_exists_T_177) node _csr_exists_T_373 = or(_csr_exists_T_372, _csr_exists_T_178) node _csr_exists_T_374 = or(_csr_exists_T_373, _csr_exists_T_179) node _csr_exists_T_375 = or(_csr_exists_T_374, _csr_exists_T_180) node _csr_exists_T_376 = or(_csr_exists_T_375, _csr_exists_T_181) node _csr_exists_T_377 = or(_csr_exists_T_376, _csr_exists_T_182) node _csr_exists_T_378 = or(_csr_exists_T_377, _csr_exists_T_183) node _csr_exists_T_379 = or(_csr_exists_T_378, _csr_exists_T_184) node _csr_exists_T_380 = or(_csr_exists_T_379, _csr_exists_T_185) node _csr_exists_T_381 = or(_csr_exists_T_380, _csr_exists_T_186) node _csr_exists_T_382 = or(_csr_exists_T_381, _csr_exists_T_187) node _csr_exists_T_383 = or(_csr_exists_T_382, _csr_exists_T_188) node _csr_exists_T_384 = or(_csr_exists_T_383, _csr_exists_T_189) node _csr_exists_T_385 = or(_csr_exists_T_384, _csr_exists_T_190) node _csr_exists_T_386 = or(_csr_exists_T_385, _csr_exists_T_191) node _csr_exists_T_387 = or(_csr_exists_T_386, _csr_exists_T_192) node _csr_exists_T_388 = or(_csr_exists_T_387, _csr_exists_T_193) node _csr_exists_T_389 = or(_csr_exists_T_388, _csr_exists_T_194) node csr_exists = or(_csr_exists_T_389, _csr_exists_T_195) node _io_decode_0_read_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_1 = eq(csr_exists, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_2 = or(_io_decode_0_read_illegal_T, _io_decode_0_read_illegal_T_1) node _io_decode_0_read_illegal_T_3 = eq(addr, UInt<9>(0h180)) node _io_decode_0_read_illegal_T_4 = eq(addr, UInt<11>(0h680)) node _io_decode_0_read_illegal_T_5 = or(_io_decode_0_read_illegal_T_3, _io_decode_0_read_illegal_T_4) node _io_decode_0_read_illegal_T_6 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_7 = and(_io_decode_0_read_illegal_T_5, _io_decode_0_read_illegal_T_6) node _io_decode_0_read_illegal_T_8 = or(_io_decode_0_read_illegal_T_2, _io_decode_0_read_illegal_T_7) node _io_decode_0_read_illegal_T_9 = eq(allow_counter, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_10 = and(is_counter, _io_decode_0_read_illegal_T_9) node _io_decode_0_read_illegal_T_11 = or(_io_decode_0_read_illegal_T_8, _io_decode_0_read_illegal_T_10) wire io_decode_0_read_illegal_plaInput : UInt<12> node io_decode_0_read_illegal_invInputs = not(io_decode_0_read_illegal_plaInput) wire io_decode_0_read_illegal_plaOutput : UInt<1> node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = bits(io_decode_0_read_illegal_plaInput, 4, 4) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = bits(io_decode_0_read_illegal_plaInput, 5, 5) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = bits(io_decode_0_read_illegal_invInputs, 6, 6) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = bits(io_decode_0_read_illegal_plaInput, 7, 7) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = bits(io_decode_0_read_illegal_plaInput, 8, 8) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = bits(io_decode_0_read_illegal_plaInput, 9, 9) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = bits(io_decode_0_read_illegal_plaInput, 10, 10) node io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = bits(io_decode_0_read_illegal_invInputs, 11, 11) node io_decode_0_read_illegal_andMatrixOutputs_lo_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7) node io_decode_0_read_illegal_andMatrixOutputs_lo_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5) node io_decode_0_read_illegal_andMatrixOutputs_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo) node io_decode_0_read_illegal_andMatrixOutputs_hi_lo = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3) node io_decode_0_read_illegal_andMatrixOutputs_hi_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1) node io_decode_0_read_illegal_andMatrixOutputs_hi = cat(io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo) node _io_decode_0_read_illegal_andMatrixOutputs_T = cat(io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo) node io_decode_0_read_illegal_andMatrixOutputs_0_2 = andr(_io_decode_0_read_illegal_andMatrixOutputs_T) node io_decode_0_read_illegal_orMatrixOutputs = orr(io_decode_0_read_illegal_andMatrixOutputs_0_2) node io_decode_0_read_illegal_invMatrixOutputs = bits(io_decode_0_read_illegal_orMatrixOutputs, 0, 0) connect io_decode_0_read_illegal_plaOutput, io_decode_0_read_illegal_invMatrixOutputs connect io_decode_0_read_illegal_plaInput, addr node _io_decode_0_read_illegal_T_12 = bits(io_decode_0_read_illegal_plaOutput, 0, 0) node _io_decode_0_read_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_read_illegal_T_14 = and(_io_decode_0_read_illegal_T_12, _io_decode_0_read_illegal_T_13) node _io_decode_0_read_illegal_T_15 = or(_io_decode_0_read_illegal_T_11, _io_decode_0_read_illegal_T_14) wire io_decode_0_read_illegal_plaInput_1 : UInt<12> node io_decode_0_read_illegal_invInputs_1 = not(io_decode_0_read_illegal_plaInput_1) wire io_decode_0_read_illegal_plaOutput_1 : UInt<1> connect io_decode_0_read_illegal_plaOutput_1, UInt<1>(0h0) connect io_decode_0_read_illegal_plaInput_1, addr node _io_decode_0_read_illegal_T_16 = bits(io_decode_0_read_illegal_plaOutput_1, 0, 0) node _io_decode_0_read_illegal_T_17 = and(_io_decode_0_read_illegal_T_16, io.decode[0].vector_illegal) node _io_decode_0_read_illegal_T_18 = or(_io_decode_0_read_illegal_T_15, _io_decode_0_read_illegal_T_17) node _io_decode_0_read_illegal_T_19 = and(io.decode[0].fp_csr, io.decode[0].fp_illegal) node _io_decode_0_read_illegal_T_20 = or(_io_decode_0_read_illegal_T_18, _io_decode_0_read_illegal_T_19) connect io.decode[0].read_illegal, _io_decode_0_read_illegal_T_20 node _io_decode_0_write_illegal_T = bits(addr, 11, 10) node _io_decode_0_write_illegal_T_1 = andr(_io_decode_0_write_illegal_T) connect io.decode[0].write_illegal, _io_decode_0_write_illegal_T_1 node _io_decode_0_write_flush_addr_m_T = shl(UInt<2>(0h3), 8) node io_decode_0_write_flush_addr_m = or(addr, _io_decode_0_write_flush_addr_m_T) node _io_decode_0_write_flush_T = geq(io_decode_0_write_flush_addr_m, UInt<10>(0h340)) node _io_decode_0_write_flush_T_1 = leq(io_decode_0_write_flush_addr_m, UInt<10>(0h343)) node _io_decode_0_write_flush_T_2 = and(_io_decode_0_write_flush_T, _io_decode_0_write_flush_T_1) node _io_decode_0_write_flush_T_3 = eq(_io_decode_0_write_flush_T_2, UInt<1>(0h0)) connect io.decode[0].write_flush, _io_decode_0_write_flush_T_3 node _io_decode_0_system_illegal_T = eq(csr_addr_legal, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_1 = eq(is_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_2 = and(_io_decode_0_system_illegal_T, _io_decode_0_system_illegal_T_1) node _io_decode_0_system_illegal_T_3 = eq(allow_wfi, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_4 = and(is_wfi, _io_decode_0_system_illegal_T_3) node _io_decode_0_system_illegal_T_5 = or(_io_decode_0_system_illegal_T_2, _io_decode_0_system_illegal_T_4) node _io_decode_0_system_illegal_T_6 = eq(allow_sret, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_7 = and(is_ret, _io_decode_0_system_illegal_T_6) node _io_decode_0_system_illegal_T_8 = or(_io_decode_0_system_illegal_T_5, _io_decode_0_system_illegal_T_7) node _io_decode_0_system_illegal_T_9 = bits(addr, 10, 10) node _io_decode_0_system_illegal_T_10 = and(is_ret, _io_decode_0_system_illegal_T_9) node _io_decode_0_system_illegal_T_11 = bits(addr, 7, 7) node _io_decode_0_system_illegal_T_12 = and(_io_decode_0_system_illegal_T_10, _io_decode_0_system_illegal_T_11) node _io_decode_0_system_illegal_T_13 = eq(reg_debug, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_14 = and(_io_decode_0_system_illegal_T_12, _io_decode_0_system_illegal_T_13) node _io_decode_0_system_illegal_T_15 = or(_io_decode_0_system_illegal_T_8, _io_decode_0_system_illegal_T_14) node _io_decode_0_system_illegal_T_16 = or(is_sfence, is_hfence_gvma) node _io_decode_0_system_illegal_T_17 = eq(allow_sfence_vma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_18 = and(_io_decode_0_system_illegal_T_16, _io_decode_0_system_illegal_T_17) node _io_decode_0_system_illegal_T_19 = or(_io_decode_0_system_illegal_T_15, _io_decode_0_system_illegal_T_18) node _io_decode_0_system_illegal_T_20 = eq(allow_hfence_vvma, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_21 = and(is_hfence_vvma, _io_decode_0_system_illegal_T_20) node _io_decode_0_system_illegal_T_22 = or(_io_decode_0_system_illegal_T_19, _io_decode_0_system_illegal_T_21) node _io_decode_0_system_illegal_T_23 = eq(allow_hlsv, UInt<1>(0h0)) node _io_decode_0_system_illegal_T_24 = and(is_hlsv, _io_decode_0_system_illegal_T_23) node _io_decode_0_system_illegal_T_25 = or(_io_decode_0_system_illegal_T_22, _io_decode_0_system_illegal_T_24) connect io.decode[0].system_illegal, _io_decode_0_system_illegal_T_25 node _io_decode_0_virtual_access_illegal_T = and(reg_mstatus.v, csr_exists) node _io_decode_0_virtual_access_illegal_T_1 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_2 = eq(_io_decode_0_virtual_access_illegal_T_1, UInt<2>(0h2)) node _io_decode_0_virtual_access_illegal_T_3 = dshr(read_mcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_4 = bits(_io_decode_0_virtual_access_illegal_T_3, 0, 0) node _io_decode_0_virtual_access_illegal_T_5 = and(is_counter, _io_decode_0_virtual_access_illegal_T_4) node _io_decode_0_virtual_access_illegal_T_6 = dshr(read_hcounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_7 = bits(_io_decode_0_virtual_access_illegal_T_6, 0, 0) node _io_decode_0_virtual_access_illegal_T_8 = eq(_io_decode_0_virtual_access_illegal_T_7, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_9 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_10 = eq(_io_decode_0_virtual_access_illegal_T_9, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_11 = dshr(read_scounteren, counter_addr) node _io_decode_0_virtual_access_illegal_T_12 = bits(_io_decode_0_virtual_access_illegal_T_11, 0, 0) node _io_decode_0_virtual_access_illegal_T_13 = eq(_io_decode_0_virtual_access_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_14 = and(_io_decode_0_virtual_access_illegal_T_10, _io_decode_0_virtual_access_illegal_T_13) node _io_decode_0_virtual_access_illegal_T_15 = or(_io_decode_0_virtual_access_illegal_T_8, _io_decode_0_virtual_access_illegal_T_14) node _io_decode_0_virtual_access_illegal_T_16 = and(_io_decode_0_virtual_access_illegal_T_5, _io_decode_0_virtual_access_illegal_T_15) node _io_decode_0_virtual_access_illegal_T_17 = or(_io_decode_0_virtual_access_illegal_T_2, _io_decode_0_virtual_access_illegal_T_16) node _io_decode_0_virtual_access_illegal_T_18 = bits(addr, 9, 8) node _io_decode_0_virtual_access_illegal_T_19 = eq(_io_decode_0_virtual_access_illegal_T_18, UInt<1>(0h1)) node _io_decode_0_virtual_access_illegal_T_20 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_21 = eq(_io_decode_0_virtual_access_illegal_T_20, UInt<1>(0h0)) node _io_decode_0_virtual_access_illegal_T_22 = and(_io_decode_0_virtual_access_illegal_T_19, _io_decode_0_virtual_access_illegal_T_21) node _io_decode_0_virtual_access_illegal_T_23 = or(_io_decode_0_virtual_access_illegal_T_17, _io_decode_0_virtual_access_illegal_T_22) node _io_decode_0_virtual_access_illegal_T_24 = eq(addr, UInt<9>(0h180)) node _io_decode_0_virtual_access_illegal_T_25 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_access_illegal_T_26 = and(_io_decode_0_virtual_access_illegal_T_24, _io_decode_0_virtual_access_illegal_T_25) node _io_decode_0_virtual_access_illegal_T_27 = and(_io_decode_0_virtual_access_illegal_T_26, reg_hstatus.vtvm) node _io_decode_0_virtual_access_illegal_T_28 = or(_io_decode_0_virtual_access_illegal_T_23, _io_decode_0_virtual_access_illegal_T_27) node _io_decode_0_virtual_access_illegal_T_29 = and(_io_decode_0_virtual_access_illegal_T, _io_decode_0_virtual_access_illegal_T_28) connect io.decode[0].virtual_access_illegal, _io_decode_0_virtual_access_illegal_T_29 node _io_decode_0_virtual_system_illegal_T = or(is_hfence_vvma, is_hfence_gvma) node _io_decode_0_virtual_system_illegal_T_1 = or(_io_decode_0_virtual_system_illegal_T, is_hlsv) node _io_decode_0_virtual_system_illegal_T_2 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_3 = eq(_io_decode_0_virtual_system_illegal_T_2, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_4 = eq(reg_mstatus.tw, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_5 = and(_io_decode_0_virtual_system_illegal_T_4, reg_hstatus.vtw) node _io_decode_0_virtual_system_illegal_T_6 = or(_io_decode_0_virtual_system_illegal_T_3, _io_decode_0_virtual_system_illegal_T_5) node _io_decode_0_virtual_system_illegal_T_7 = and(is_wfi, _io_decode_0_virtual_system_illegal_T_6) node _io_decode_0_virtual_system_illegal_T_8 = or(_io_decode_0_virtual_system_illegal_T_1, _io_decode_0_virtual_system_illegal_T_7) node _io_decode_0_virtual_system_illegal_T_9 = bits(addr, 9, 8) node _io_decode_0_virtual_system_illegal_T_10 = eq(_io_decode_0_virtual_system_illegal_T_9, UInt<1>(0h1)) node _io_decode_0_virtual_system_illegal_T_11 = and(is_ret, _io_decode_0_virtual_system_illegal_T_10) node _io_decode_0_virtual_system_illegal_T_12 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_13 = eq(_io_decode_0_virtual_system_illegal_T_12, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_14 = or(_io_decode_0_virtual_system_illegal_T_13, reg_hstatus.vtsr) node _io_decode_0_virtual_system_illegal_T_15 = and(_io_decode_0_virtual_system_illegal_T_11, _io_decode_0_virtual_system_illegal_T_14) node _io_decode_0_virtual_system_illegal_T_16 = or(_io_decode_0_virtual_system_illegal_T_8, _io_decode_0_virtual_system_illegal_T_15) node _io_decode_0_virtual_system_illegal_T_17 = bits(reg_mstatus.prv, 0, 0) node _io_decode_0_virtual_system_illegal_T_18 = eq(_io_decode_0_virtual_system_illegal_T_17, UInt<1>(0h0)) node _io_decode_0_virtual_system_illegal_T_19 = or(_io_decode_0_virtual_system_illegal_T_18, reg_hstatus.vtvm) node _io_decode_0_virtual_system_illegal_T_20 = and(is_sfence, _io_decode_0_virtual_system_illegal_T_19) node _io_decode_0_virtual_system_illegal_T_21 = or(_io_decode_0_virtual_system_illegal_T_16, _io_decode_0_virtual_system_illegal_T_20) node _io_decode_0_virtual_system_illegal_T_22 = and(reg_mstatus.v, _io_decode_0_virtual_system_illegal_T_21) connect io.decode[0].virtual_system_illegal, _io_decode_0_virtual_system_illegal_T_22 node _cause_T = bits(reg_mstatus.prv, 0, 0) node _cause_T_1 = and(_cause_T, reg_mstatus.v) node _cause_T_2 = mux(_cause_T_1, UInt<2>(0h2), reg_mstatus.prv) node _cause_T_3 = add(UInt<4>(0h8), _cause_T_2) node _cause_T_4 = tail(_cause_T_3, 1) node _cause_T_5 = mux(insn_break, UInt<2>(0h3), io.cause) node cause = mux(insn_call, _cause_T_4, _cause_T_5) node cause_lsbs = bits(cause, 7, 0) node cause_deleg_lsbs = bits(cause, 4, 0) node _causeIsDebugInt_T = bits(cause, 31, 31) node _causeIsDebugInt_T_1 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugInt = and(_causeIsDebugInt_T, _causeIsDebugInt_T_1) node _causeIsDebugTrigger_T = bits(cause, 31, 31) node _causeIsDebugTrigger_T_1 = eq(_causeIsDebugTrigger_T, UInt<1>(0h0)) node _causeIsDebugTrigger_T_2 = eq(cause_lsbs, UInt<4>(0he)) node causeIsDebugTrigger = and(_causeIsDebugTrigger_T_1, _causeIsDebugTrigger_T_2) node _causeIsDebugBreak_T = bits(cause, 31, 31) node _causeIsDebugBreak_T_1 = eq(_causeIsDebugBreak_T, UInt<1>(0h0)) node _causeIsDebugBreak_T_2 = and(_causeIsDebugBreak_T_1, insn_break) node causeIsDebugBreak_lo = cat(reg_dcsr.ebreaks, reg_dcsr.ebreaku) node causeIsDebugBreak_hi = cat(reg_dcsr.ebreakm, reg_dcsr.ebreakh) node _causeIsDebugBreak_T_3 = cat(causeIsDebugBreak_hi, causeIsDebugBreak_lo) node _causeIsDebugBreak_T_4 = dshr(_causeIsDebugBreak_T_3, reg_mstatus.prv) node _causeIsDebugBreak_T_5 = bits(_causeIsDebugBreak_T_4, 0, 0) node causeIsDebugBreak = and(_causeIsDebugBreak_T_2, _causeIsDebugBreak_T_5) node _trapToDebug_T = or(reg_singleStepped, causeIsDebugInt) node _trapToDebug_T_1 = or(_trapToDebug_T, causeIsDebugTrigger) node _trapToDebug_T_2 = or(_trapToDebug_T_1, causeIsDebugBreak) node _trapToDebug_T_3 = or(_trapToDebug_T_2, reg_debug) node trapToDebug = and(UInt<1>(0h1), _trapToDebug_T_3) node _debugTVec_T = mux(insn_break, UInt<12>(0h800), UInt<12>(0h808)) node debugTVec = mux(reg_debug, _debugTVec_T, UInt<12>(0h800)) node _delegate_T = leq(reg_mstatus.prv, UInt<1>(0h1)) node _delegate_T_1 = and(UInt<1>(0h0), _delegate_T) node _delegate_T_2 = bits(cause, 31, 31) node _delegate_T_3 = dshr(read_mideleg, cause_deleg_lsbs) node _delegate_T_4 = bits(_delegate_T_3, 0, 0) node _delegate_T_5 = dshr(read_medeleg, cause_deleg_lsbs) node _delegate_T_6 = bits(_delegate_T_5, 0, 0) node _delegate_T_7 = mux(_delegate_T_2, _delegate_T_4, _delegate_T_6) node delegate = and(_delegate_T_1, _delegate_T_7) node _delegateVS_T = and(reg_mstatus.v, delegate) node _delegateVS_T_1 = bits(cause, 31, 31) node _delegateVS_T_2 = dshr(read_hideleg, cause_deleg_lsbs) node _delegateVS_T_3 = bits(_delegateVS_T_2, 0, 0) node _delegateVS_T_4 = dshr(read_hedeleg, cause_deleg_lsbs) node _delegateVS_T_5 = bits(_delegateVS_T_4, 0, 0) node _delegateVS_T_6 = mux(_delegateVS_T_1, _delegateVS_T_3, _delegateVS_T_5) node delegateVS = and(_delegateVS_T, _delegateVS_T_6) node _notDebugTVec_base_T = mux(delegateVS, read_vstvec, read_stvec) node notDebugTVec_base = mux(delegate, _notDebugTVec_base_T, read_mtvec) node _notDebugTVec_interruptOffset_T = bits(cause, 4, 0) node notDebugTVec_interruptOffset = shl(_notDebugTVec_interruptOffset_T, 2) node _notDebugTVec_interruptVec_T = shr(notDebugTVec_base, 7) node notDebugTVec_interruptVec = cat(_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset) node _notDebugTVec_doVector_T = bits(notDebugTVec_base, 0, 0) node _notDebugTVec_doVector_T_1 = bits(cause, 31, 31) node _notDebugTVec_doVector_T_2 = and(_notDebugTVec_doVector_T, _notDebugTVec_doVector_T_1) node _notDebugTVec_doVector_T_3 = shr(cause_lsbs, 5) node _notDebugTVec_doVector_T_4 = eq(_notDebugTVec_doVector_T_3, UInt<1>(0h0)) node notDebugTVec_doVector = and(_notDebugTVec_doVector_T_2, _notDebugTVec_doVector_T_4) node _notDebugTVec_T = shr(notDebugTVec_base, 2) node _notDebugTVec_T_1 = shl(_notDebugTVec_T, 2) node notDebugTVec = mux(notDebugTVec_doVector, notDebugTVec_interruptVec, _notDebugTVec_T_1) node _causeIsRnmiInt_T = bits(cause, 31, 31) node _causeIsRnmiInt_T_1 = bits(cause, 30, 30) node _causeIsRnmiInt_T_2 = and(_causeIsRnmiInt_T, _causeIsRnmiInt_T_1) node _causeIsRnmiInt_T_3 = eq(cause_lsbs, UInt<4>(0hd)) node _causeIsRnmiInt_T_4 = eq(cause_lsbs, UInt<4>(0hc)) node _causeIsRnmiInt_T_5 = or(_causeIsRnmiInt_T_3, _causeIsRnmiInt_T_4) node causeIsRnmiInt = and(_causeIsRnmiInt_T_2, _causeIsRnmiInt_T_5) node _causeIsRnmiBEU_T = bits(cause, 31, 31) node _causeIsRnmiBEU_T_1 = bits(cause, 30, 30) node _causeIsRnmiBEU_T_2 = and(_causeIsRnmiBEU_T, _causeIsRnmiBEU_T_1) node _causeIsRnmiBEU_T_3 = eq(cause_lsbs, UInt<4>(0hc)) node causeIsRnmiBEU = and(_causeIsRnmiBEU_T_2, _causeIsRnmiBEU_T_3) node trapToNmiInt = and(UInt<1>(0h0), causeIsRnmiInt) node _trapToNmiXcpt_T = eq(reg_rnmie, UInt<1>(0h0)) node trapToNmiXcpt = and(UInt<1>(0h0), _trapToNmiXcpt_T) node trapToNmi = or(trapToNmiInt, trapToNmiXcpt) node _nmiTVec_T = mux(causeIsRnmiInt, UInt<1>(0h0), UInt<1>(0h0)) node _nmiTVec_T_1 = shr(_nmiTVec_T, 1) node nmiTVec = shl(_nmiTVec_T_1, 1) node _tvec_T = mux(trapToNmi, nmiTVec, notDebugTVec) node tvec = mux(trapToDebug, debugTVec, _tvec_T) connect io.evec, tvec connect io.ptbr, reg_satp connect io.hgatp, reg_hgatp connect io.vsatp, reg_vsatp node _io_eret_T = or(insn_call, insn_break) node _io_eret_T_1 = or(_io_eret_T, insn_ret) connect io.eret, _io_eret_T_1 node _io_singleStep_T = eq(reg_debug, UInt<1>(0h0)) node _io_singleStep_T_1 = and(reg_dcsr.step, _io_singleStep_T) connect io.singleStep, _io_singleStep_T_1 connect io.status, reg_mstatus node _io_status_sd_T = andr(io.status.fs) node _io_status_sd_T_1 = andr(io.status.xs) node _io_status_sd_T_2 = or(_io_status_sd_T, _io_status_sd_T_1) node _io_status_sd_T_3 = andr(io.status.vs) node _io_status_sd_T_4 = or(_io_status_sd_T_2, _io_status_sd_T_3) connect io.status.sd, _io_status_sd_T_4 connect io.status.debug, reg_debug connect io.status.isa, reg_misa connect io.status.uxl, UInt<1>(0h0) connect io.status.sxl, UInt<1>(0h0) node _io_status_dprv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dprv_T_1 = and(reg_mstatus.mprv, _io_status_dprv_T) node _io_status_dprv_T_2 = mux(_io_status_dprv_T_1, reg_mstatus.mpp, reg_mstatus.prv) connect io.status.dprv, _io_status_dprv_T_2 node _io_status_dv_T = eq(reg_debug, UInt<1>(0h0)) node _io_status_dv_T_1 = and(reg_mstatus.mprv, _io_status_dv_T) node _io_status_dv_T_2 = mux(_io_status_dv_T_1, reg_mstatus.mpv, UInt<1>(0h0)) node _io_status_dv_T_3 = or(reg_mstatus.v, _io_status_dv_T_2) connect io.status.dv, _io_status_dv_T_3 node _io_status_sd_rv32_T = and(UInt<1>(0h1), io.status.sd) connect io.status.sd_rv32, _io_status_sd_rv32_T connect io.status.mpv, reg_mstatus.mpv connect io.status.gva, reg_mstatus.gva connect io.hstatus, reg_hstatus connect io.hstatus.vsxl, UInt<1>(0h0) connect io.gstatus, reg_vsstatus node _io_gstatus_sd_T = andr(io.gstatus.fs) node _io_gstatus_sd_T_1 = andr(io.gstatus.xs) node _io_gstatus_sd_T_2 = or(_io_gstatus_sd_T, _io_gstatus_sd_T_1) node _io_gstatus_sd_T_3 = andr(io.gstatus.vs) node _io_gstatus_sd_T_4 = or(_io_gstatus_sd_T_2, _io_gstatus_sd_T_3) connect io.gstatus.sd, _io_gstatus_sd_T_4 connect io.gstatus.uxl, UInt<1>(0h0) node _io_gstatus_sd_rv32_T = and(UInt<1>(0h1), io.gstatus.sd) connect io.gstatus.sd_rv32, _io_gstatus_sd_rv32_T node _exception_T = or(insn_call, insn_break) node exception = or(_exception_T, io.exception) node _T_131 = add(insn_ret, insn_call) node _T_132 = bits(_T_131, 1, 0) node _T_133 = add(insn_break, io.exception) node _T_134 = bits(_T_133, 1, 0) node _T_135 = add(_T_132, _T_134) node _T_136 = bits(_T_135, 2, 0) node _T_137 = leq(_T_136, UInt<1>(0h1)) node _T_138 = asUInt(reset) node _T_139 = eq(_T_138, UInt<1>(0h0)) when _T_139 : node _T_140 = eq(_T_137, UInt<1>(0h0)) when _T_140 : printf(clock, UInt<1>(0h1), "Assertion failed: these conditions must be mutually exclusive\n at CSR.scala:1021 assert(PopCount(insn_ret :: insn_call :: insn_break :: io.exception :: Nil) <= 1.U, \"these conditions must be mutually exclusive\")\n") : printf assert(clock, _T_137, UInt<1>(0h1), "") : assert node _T_141 = eq(io.singleStep, UInt<1>(0h0)) node _T_142 = and(insn_wfi, _T_141) node _T_143 = eq(reg_debug, UInt<1>(0h0)) node _T_144 = and(_T_142, _T_143) when _T_144 : connect reg_wfi, UInt<1>(0h1) node _T_145 = orr(pending_interrupts) node _T_146 = or(_T_145, io.interrupts.debug) node _T_147 = or(_T_146, exception) when _T_147 : connect reg_wfi, UInt<1>(0h0) node _T_148 = bits(io.retire, 0, 0) node _T_149 = or(_T_148, exception) when _T_149 : connect reg_singleStepped, UInt<1>(0h1) node _T_150 = eq(io.singleStep, UInt<1>(0h0)) when _T_150 : connect reg_singleStepped, UInt<1>(0h0) node _T_151 = eq(io.singleStep, UInt<1>(0h0)) node _T_152 = leq(io.retire, UInt<1>(0h1)) node _T_153 = or(_T_151, _T_152) node _T_154 = asUInt(reset) node _T_155 = eq(_T_154, UInt<1>(0h0)) when _T_155 : node _T_156 = eq(_T_153, UInt<1>(0h0)) when _T_156 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1029 assert(!io.singleStep || io.retire <= 1.U)\n") : printf_1 assert(clock, _T_153, UInt<1>(0h1), "") : assert_1 node _T_157 = eq(reg_singleStepped, UInt<1>(0h0)) node _T_158 = eq(io.retire, UInt<1>(0h0)) node _T_159 = or(_T_157, _T_158) node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(_T_159, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed\n at CSR.scala:1030 assert(!reg_singleStepped || io.retire === 0.U)\n") : printf_2 assert(clock, _T_159, UInt<1>(0h1), "") : assert_2 node _epc_T = not(io.pc) node _epc_T_1 = or(_epc_T, UInt<1>(0h1)) node epc = not(_epc_T_1) node tval = mux(insn_break, epc, io.tval) when exception : when trapToDebug : node _T_163 = eq(reg_debug, UInt<1>(0h0)) when _T_163 : connect reg_mstatus.v, UInt<1>(0h0) connect reg_debug, UInt<1>(0h1) connect reg_dpc, epc node _reg_dcsr_cause_T = mux(causeIsDebugTrigger, UInt<2>(0h2), UInt<1>(0h1)) node _reg_dcsr_cause_T_1 = mux(causeIsDebugInt, UInt<2>(0h3), _reg_dcsr_cause_T) node _reg_dcsr_cause_T_2 = mux(reg_singleStepped, UInt<3>(0h4), _reg_dcsr_cause_T_1) connect reg_dcsr.cause, _reg_dcsr_cause_T_2 connect reg_dcsr.prv, UInt<2>(0h3) connect reg_dcsr.v, reg_mstatus.v connect new_prv, UInt<2>(0h3) else : when trapToNmiInt : when reg_rnmie : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mnstatus.mpv, reg_mstatus.v connect reg_rnmie, UInt<1>(0h0) connect reg_mnepc, epc node _reg_mncause_T = mux(causeIsRnmiBEU, UInt<2>(0h3), UInt<2>(0h2)) node _reg_mncause_T_1 = or(UInt<32>(0h80000000), _reg_mncause_T) connect reg_mncause, _reg_mncause_T_1 connect reg_mnstatus.mpp, UInt<2>(0h3) connect new_prv, UInt<2>(0h3) else : node _T_164 = and(delegateVS, reg_rnmie) when _T_164 : connect reg_mstatus.v, UInt<1>(0h1) connect reg_vsstatus.spp, reg_mstatus.prv connect reg_vsepc, epc node _reg_vscause_T = bits(cause, 31, 31) node _reg_vscause_T_1 = bits(cause, 31, 2) node _reg_vscause_T_2 = cat(_reg_vscause_T_1, UInt<2>(0h1)) node _reg_vscause_T_3 = mux(_reg_vscause_T, _reg_vscause_T_2, cause) connect reg_vscause, _reg_vscause_T_3 connect reg_vstval, tval connect reg_vsstatus.spie, reg_vsstatus.sie connect reg_vsstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : node _T_165 = and(delegate, reg_rnmie) when _T_165 : connect reg_mstatus.v, UInt<1>(0h0) node _reg_hstatus_spvp_T = bits(reg_mstatus.prv, 0, 0) node _reg_hstatus_spvp_T_1 = mux(reg_mstatus.v, _reg_hstatus_spvp_T, reg_hstatus.spvp) connect reg_hstatus.spvp, _reg_hstatus_spvp_T_1 connect reg_hstatus.gva, io.gva connect reg_hstatus.spv, reg_mstatus.v connect reg_sepc, epc connect reg_scause, cause connect reg_stval, tval connect reg_htval, io.htval connect reg_htinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.spie, reg_mstatus.sie connect reg_mstatus.spp, reg_mstatus.prv connect reg_mstatus.sie, UInt<1>(0h0) connect new_prv, UInt<1>(0h1) else : connect reg_mstatus.v, UInt<1>(0h0) connect reg_mstatus.mpv, reg_mstatus.v connect reg_mstatus.gva, io.gva connect reg_mepc, epc connect reg_mcause, cause connect reg_mtval, tval connect reg_mtval2, io.htval connect reg_mtinst_read_pseudo, io.mhtinst_read_pseudo connect reg_mstatus.mpie, reg_mstatus.mie connect reg_mstatus.mpp, UInt<2>(0h3) connect reg_mstatus.mie, UInt<1>(0h0) connect new_prv, UInt<2>(0h3) node _en_T = and(supported_interrupts, UInt<1>(0h1)) node _en_T_1 = neq(_en_T, UInt<1>(0h0)) node _en_T_2 = and(exception, _en_T_1) node _en_T_3 = add(UInt<32>(0h80000000), UInt<1>(0h0)) node _en_T_4 = tail(_en_T_3, 1) node _en_T_5 = eq(cause, _en_T_4) node en = and(_en_T_2, _en_T_5) node _delegable_T = and(delegable_interrupts, UInt<1>(0h1)) node delegable = neq(_delegable_T, UInt<1>(0h0)) node _T_166 = eq(delegate, UInt<1>(0h0)) node _T_167 = and(en, _T_166) node _T_168 = and(en, delegable) node _T_169 = and(_T_168, delegate) node _en_T_6 = and(supported_interrupts, UInt<2>(0h2)) node _en_T_7 = neq(_en_T_6, UInt<1>(0h0)) node _en_T_8 = and(exception, _en_T_7) node _en_T_9 = add(UInt<32>(0h80000000), UInt<1>(0h1)) node _en_T_10 = tail(_en_T_9, 1) node _en_T_11 = eq(cause, _en_T_10) node en_1 = and(_en_T_8, _en_T_11) node _delegable_T_1 = and(delegable_interrupts, UInt<2>(0h2)) node delegable_1 = neq(_delegable_T_1, UInt<1>(0h0)) node _T_170 = eq(delegate, UInt<1>(0h0)) node _T_171 = and(en_1, _T_170) node _T_172 = and(en_1, delegable_1) node _T_173 = and(_T_172, delegate) node _en_T_12 = and(supported_interrupts, UInt<3>(0h4)) node _en_T_13 = neq(_en_T_12, UInt<1>(0h0)) node _en_T_14 = and(exception, _en_T_13) node _en_T_15 = add(UInt<32>(0h80000000), UInt<2>(0h2)) node _en_T_16 = tail(_en_T_15, 1) node _en_T_17 = eq(cause, _en_T_16) node en_2 = and(_en_T_14, _en_T_17) node _delegable_T_2 = and(delegable_interrupts, UInt<3>(0h4)) node delegable_2 = neq(_delegable_T_2, UInt<1>(0h0)) node _T_174 = eq(delegate, UInt<1>(0h0)) node _T_175 = and(en_2, _T_174) node _T_176 = and(en_2, delegable_2) node _T_177 = and(_T_176, delegate) node _en_T_18 = and(supported_interrupts, UInt<4>(0h8)) node _en_T_19 = neq(_en_T_18, UInt<1>(0h0)) node _en_T_20 = and(exception, _en_T_19) node _en_T_21 = add(UInt<32>(0h80000000), UInt<2>(0h3)) node _en_T_22 = tail(_en_T_21, 1) node _en_T_23 = eq(cause, _en_T_22) node en_3 = and(_en_T_20, _en_T_23) node _delegable_T_3 = and(delegable_interrupts, UInt<4>(0h8)) node delegable_3 = neq(_delegable_T_3, UInt<1>(0h0)) node _T_178 = eq(delegate, UInt<1>(0h0)) node _T_179 = and(en_3, _T_178) node _T_180 = and(en_3, delegable_3) node _T_181 = and(_T_180, delegate) node _en_T_24 = and(supported_interrupts, UInt<5>(0h10)) node _en_T_25 = neq(_en_T_24, UInt<1>(0h0)) node _en_T_26 = and(exception, _en_T_25) node _en_T_27 = add(UInt<32>(0h80000000), UInt<3>(0h4)) node _en_T_28 = tail(_en_T_27, 1) node _en_T_29 = eq(cause, _en_T_28) node en_4 = and(_en_T_26, _en_T_29) node _delegable_T_4 = and(delegable_interrupts, UInt<5>(0h10)) node delegable_4 = neq(_delegable_T_4, UInt<1>(0h0)) node _T_182 = eq(delegate, UInt<1>(0h0)) node _T_183 = and(en_4, _T_182) node _T_184 = and(en_4, delegable_4) node _T_185 = and(_T_184, delegate) node _en_T_30 = and(supported_interrupts, UInt<6>(0h20)) node _en_T_31 = neq(_en_T_30, UInt<1>(0h0)) node _en_T_32 = and(exception, _en_T_31) node _en_T_33 = add(UInt<32>(0h80000000), UInt<3>(0h5)) node _en_T_34 = tail(_en_T_33, 1) node _en_T_35 = eq(cause, _en_T_34) node en_5 = and(_en_T_32, _en_T_35) node _delegable_T_5 = and(delegable_interrupts, UInt<6>(0h20)) node delegable_5 = neq(_delegable_T_5, UInt<1>(0h0)) node _T_186 = eq(delegate, UInt<1>(0h0)) node _T_187 = and(en_5, _T_186) node _T_188 = and(en_5, delegable_5) node _T_189 = and(_T_188, delegate) node _en_T_36 = and(supported_interrupts, UInt<7>(0h40)) node _en_T_37 = neq(_en_T_36, UInt<1>(0h0)) node _en_T_38 = and(exception, _en_T_37) node _en_T_39 = add(UInt<32>(0h80000000), UInt<3>(0h6)) node _en_T_40 = tail(_en_T_39, 1) node _en_T_41 = eq(cause, _en_T_40) node en_6 = and(_en_T_38, _en_T_41) node _delegable_T_6 = and(delegable_interrupts, UInt<7>(0h40)) node delegable_6 = neq(_delegable_T_6, UInt<1>(0h0)) node _T_190 = eq(delegate, UInt<1>(0h0)) node _T_191 = and(en_6, _T_190) node _T_192 = and(en_6, delegable_6) node _T_193 = and(_T_192, delegate) node _en_T_42 = and(supported_interrupts, UInt<8>(0h80)) node _en_T_43 = neq(_en_T_42, UInt<1>(0h0)) node _en_T_44 = and(exception, _en_T_43) node _en_T_45 = add(UInt<32>(0h80000000), UInt<3>(0h7)) node _en_T_46 = tail(_en_T_45, 1) node _en_T_47 = eq(cause, _en_T_46) node en_7 = and(_en_T_44, _en_T_47) node _delegable_T_7 = and(delegable_interrupts, UInt<8>(0h80)) node delegable_7 = neq(_delegable_T_7, UInt<1>(0h0)) node _T_194 = eq(delegate, UInt<1>(0h0)) node _T_195 = and(en_7, _T_194) node _T_196 = and(en_7, delegable_7) node _T_197 = and(_T_196, delegate) node _en_T_48 = and(supported_interrupts, UInt<9>(0h100)) node _en_T_49 = neq(_en_T_48, UInt<1>(0h0)) node _en_T_50 = and(exception, _en_T_49) node _en_T_51 = add(UInt<32>(0h80000000), UInt<4>(0h8)) node _en_T_52 = tail(_en_T_51, 1) node _en_T_53 = eq(cause, _en_T_52) node en_8 = and(_en_T_50, _en_T_53) node _delegable_T_8 = and(delegable_interrupts, UInt<9>(0h100)) node delegable_8 = neq(_delegable_T_8, UInt<1>(0h0)) node _T_198 = eq(delegate, UInt<1>(0h0)) node _T_199 = and(en_8, _T_198) node _T_200 = and(en_8, delegable_8) node _T_201 = and(_T_200, delegate) node _en_T_54 = and(supported_interrupts, UInt<10>(0h200)) node _en_T_55 = neq(_en_T_54, UInt<1>(0h0)) node _en_T_56 = and(exception, _en_T_55) node _en_T_57 = add(UInt<32>(0h80000000), UInt<4>(0h9)) node _en_T_58 = tail(_en_T_57, 1) node _en_T_59 = eq(cause, _en_T_58) node en_9 = and(_en_T_56, _en_T_59) node _delegable_T_9 = and(delegable_interrupts, UInt<10>(0h200)) node delegable_9 = neq(_delegable_T_9, UInt<1>(0h0)) node _T_202 = eq(delegate, UInt<1>(0h0)) node _T_203 = and(en_9, _T_202) node _T_204 = and(en_9, delegable_9) node _T_205 = and(_T_204, delegate) node _en_T_60 = and(supported_interrupts, UInt<11>(0h400)) node _en_T_61 = neq(_en_T_60, UInt<1>(0h0)) node _en_T_62 = and(exception, _en_T_61) node _en_T_63 = add(UInt<32>(0h80000000), UInt<4>(0ha)) node _en_T_64 = tail(_en_T_63, 1) node _en_T_65 = eq(cause, _en_T_64) node en_10 = and(_en_T_62, _en_T_65) node _delegable_T_10 = and(delegable_interrupts, UInt<11>(0h400)) node delegable_10 = neq(_delegable_T_10, UInt<1>(0h0)) node _T_206 = eq(delegate, UInt<1>(0h0)) node _T_207 = and(en_10, _T_206) node _T_208 = and(en_10, delegable_10) node _T_209 = and(_T_208, delegate) node _en_T_66 = and(supported_interrupts, UInt<12>(0h800)) node _en_T_67 = neq(_en_T_66, UInt<1>(0h0)) node _en_T_68 = and(exception, _en_T_67) node _en_T_69 = add(UInt<32>(0h80000000), UInt<4>(0hb)) node _en_T_70 = tail(_en_T_69, 1) node _en_T_71 = eq(cause, _en_T_70) node en_11 = and(_en_T_68, _en_T_71) node _delegable_T_11 = and(delegable_interrupts, UInt<12>(0h800)) node delegable_11 = neq(_delegable_T_11, UInt<1>(0h0)) node _T_210 = eq(delegate, UInt<1>(0h0)) node _T_211 = and(en_11, _T_210) node _T_212 = and(en_11, delegable_11) node _T_213 = and(_T_212, delegate) node _en_T_72 = and(supported_interrupts, UInt<13>(0h1000)) node _en_T_73 = neq(_en_T_72, UInt<1>(0h0)) node _en_T_74 = and(exception, _en_T_73) node _en_T_75 = add(UInt<32>(0h80000000), UInt<4>(0hc)) node _en_T_76 = tail(_en_T_75, 1) node _en_T_77 = eq(cause, _en_T_76) node en_12 = and(_en_T_74, _en_T_77) node _delegable_T_12 = and(delegable_interrupts, UInt<13>(0h1000)) node delegable_12 = neq(_delegable_T_12, UInt<1>(0h0)) node _T_214 = eq(delegate, UInt<1>(0h0)) node _T_215 = and(en_12, _T_214) node _T_216 = and(en_12, delegable_12) node _T_217 = and(_T_216, delegate) node _en_T_78 = and(supported_interrupts, UInt<14>(0h2000)) node _en_T_79 = neq(_en_T_78, UInt<1>(0h0)) node _en_T_80 = and(exception, _en_T_79) node _en_T_81 = add(UInt<32>(0h80000000), UInt<4>(0hd)) node _en_T_82 = tail(_en_T_81, 1) node _en_T_83 = eq(cause, _en_T_82) node en_13 = and(_en_T_80, _en_T_83) node _delegable_T_13 = and(delegable_interrupts, UInt<14>(0h2000)) node delegable_13 = neq(_delegable_T_13, UInt<1>(0h0)) node _T_218 = eq(delegate, UInt<1>(0h0)) node _T_219 = and(en_13, _T_218) node _T_220 = and(en_13, delegable_13) node _T_221 = and(_T_220, delegate) node _en_T_84 = and(supported_interrupts, UInt<15>(0h4000)) node _en_T_85 = neq(_en_T_84, UInt<1>(0h0)) node _en_T_86 = and(exception, _en_T_85) node _en_T_87 = add(UInt<32>(0h80000000), UInt<4>(0he)) node _en_T_88 = tail(_en_T_87, 1) node _en_T_89 = eq(cause, _en_T_88) node en_14 = and(_en_T_86, _en_T_89) node _delegable_T_14 = and(delegable_interrupts, UInt<15>(0h4000)) node delegable_14 = neq(_delegable_T_14, UInt<1>(0h0)) node _T_222 = eq(delegate, UInt<1>(0h0)) node _T_223 = and(en_14, _T_222) node _T_224 = and(en_14, delegable_14) node _T_225 = and(_T_224, delegate) node _en_T_90 = and(supported_interrupts, UInt<16>(0h8000)) node _en_T_91 = neq(_en_T_90, UInt<1>(0h0)) node _en_T_92 = and(exception, _en_T_91) node _en_T_93 = add(UInt<32>(0h80000000), UInt<4>(0hf)) node _en_T_94 = tail(_en_T_93, 1) node _en_T_95 = eq(cause, _en_T_94) node en_15 = and(_en_T_92, _en_T_95) node _delegable_T_15 = and(delegable_interrupts, UInt<16>(0h8000)) node delegable_15 = neq(_delegable_T_15, UInt<1>(0h0)) node _T_226 = eq(delegate, UInt<1>(0h0)) node _T_227 = and(en_15, _T_226) node _T_228 = and(en_15, delegable_15) node _T_229 = and(_T_228, delegate) node _en_T_96 = eq(cause, UInt<1>(0h0)) node en_16 = and(exception, _en_T_96) node _delegable_T_16 = and(UInt<16>(0hb15d), UInt<1>(0h1)) node delegable_16 = neq(_delegable_T_16, UInt<1>(0h0)) node _T_230 = eq(delegate, UInt<1>(0h0)) node _T_231 = and(en_16, _T_230) node _T_232 = and(en_16, delegable_16) node _T_233 = and(_T_232, delegate) node _en_T_97 = eq(cause, UInt<1>(0h1)) node en_17 = and(exception, _en_T_97) node _delegable_T_17 = and(UInt<16>(0hb15d), UInt<2>(0h2)) node delegable_17 = neq(_delegable_T_17, UInt<1>(0h0)) node _T_234 = eq(delegate, UInt<1>(0h0)) node _T_235 = and(en_17, _T_234) node _T_236 = and(en_17, delegable_17) node _T_237 = and(_T_236, delegate) node _en_T_98 = eq(cause, UInt<2>(0h2)) node en_18 = and(exception, _en_T_98) node _delegable_T_18 = and(UInt<16>(0hb15d), UInt<3>(0h4)) node delegable_18 = neq(_delegable_T_18, UInt<1>(0h0)) node _T_238 = eq(delegate, UInt<1>(0h0)) node _T_239 = and(en_18, _T_238) node _T_240 = and(en_18, delegable_18) node _T_241 = and(_T_240, delegate) node _en_T_99 = eq(cause, UInt<2>(0h3)) node en_19 = and(exception, _en_T_99) node _delegable_T_19 = and(UInt<16>(0hb15d), UInt<4>(0h8)) node delegable_19 = neq(_delegable_T_19, UInt<1>(0h0)) node _T_242 = eq(delegate, UInt<1>(0h0)) node _T_243 = and(en_19, _T_242) node _T_244 = and(en_19, delegable_19) node _T_245 = and(_T_244, delegate) node _en_T_100 = eq(cause, UInt<3>(0h4)) node en_20 = and(exception, _en_T_100) node _delegable_T_20 = and(UInt<16>(0hb15d), UInt<5>(0h10)) node delegable_20 = neq(_delegable_T_20, UInt<1>(0h0)) node _T_246 = eq(delegate, UInt<1>(0h0)) node _T_247 = and(en_20, _T_246) node _T_248 = and(en_20, delegable_20) node _T_249 = and(_T_248, delegate) node _en_T_101 = eq(cause, UInt<3>(0h5)) node en_21 = and(exception, _en_T_101) node _delegable_T_21 = and(UInt<16>(0hb15d), UInt<6>(0h20)) node delegable_21 = neq(_delegable_T_21, UInt<1>(0h0)) node _T_250 = eq(delegate, UInt<1>(0h0)) node _T_251 = and(en_21, _T_250) node _T_252 = and(en_21, delegable_21) node _T_253 = and(_T_252, delegate) node _en_T_102 = eq(cause, UInt<3>(0h6)) node en_22 = and(exception, _en_T_102) node _delegable_T_22 = and(UInt<16>(0hb15d), UInt<7>(0h40)) node delegable_22 = neq(_delegable_T_22, UInt<1>(0h0)) node _T_254 = eq(delegate, UInt<1>(0h0)) node _T_255 = and(en_22, _T_254) node _T_256 = and(en_22, delegable_22) node _T_257 = and(_T_256, delegate) node _en_T_103 = eq(cause, UInt<3>(0h7)) node en_23 = and(exception, _en_T_103) node _delegable_T_23 = and(UInt<16>(0hb15d), UInt<8>(0h80)) node delegable_23 = neq(_delegable_T_23, UInt<1>(0h0)) node _T_258 = eq(delegate, UInt<1>(0h0)) node _T_259 = and(en_23, _T_258) node _T_260 = and(en_23, delegable_23) node _T_261 = and(_T_260, delegate) node _en_T_104 = eq(cause, UInt<4>(0hb)) node en_24 = and(exception, _en_T_104) node _delegable_T_24 = and(UInt<16>(0hb15d), UInt<12>(0h800)) node delegable_24 = neq(_delegable_T_24, UInt<1>(0h0)) node _T_262 = eq(delegate, UInt<1>(0h0)) node _T_263 = and(en_24, _T_262) node _T_264 = and(en_24, delegable_24) node _T_265 = and(_T_264, delegate) when insn_ret : wire ret_prv : UInt invalidate ret_prv node _T_266 = bits(io.rw.addr, 9, 9) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = and(UInt<1>(0h0), _T_267) when _T_268 : node _T_269 = eq(reg_mstatus.v, UInt<1>(0h0)) when _T_269 : connect reg_mstatus.sie, reg_mstatus.spie connect reg_mstatus.spie, UInt<1>(0h1) connect reg_mstatus.spp, UInt<1>(0h0) connect ret_prv, reg_mstatus.spp node _reg_mstatus_v_T = and(UInt<1>(0h0), reg_hstatus.spv) connect reg_mstatus.v, _reg_mstatus_v_T node _io_evec_T = not(reg_sepc) node _io_evec_T_1 = bits(reg_misa, 2, 2) node _io_evec_T_2 = mux(_io_evec_T_1, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_3 = or(_io_evec_T, _io_evec_T_2) node _io_evec_T_4 = not(_io_evec_T_3) connect io.evec, _io_evec_T_4 connect reg_hstatus.spv, UInt<1>(0h0) else : connect reg_vsstatus.sie, reg_vsstatus.spie connect reg_vsstatus.spie, UInt<1>(0h1) connect reg_vsstatus.spp, UInt<1>(0h0) connect ret_prv, reg_vsstatus.spp connect reg_mstatus.v, UInt<1>(0h0) node _io_evec_T_5 = not(reg_vsepc) node _io_evec_T_6 = bits(reg_misa, 2, 2) node _io_evec_T_7 = mux(_io_evec_T_6, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_8 = or(_io_evec_T_5, _io_evec_T_7) node _io_evec_T_9 = not(_io_evec_T_8) connect io.evec, _io_evec_T_9 else : node _T_270 = bits(io.rw.addr, 10, 10) node _T_271 = and(UInt<1>(0h1), _T_270) node _T_272 = bits(io.rw.addr, 7, 7) node _T_273 = and(_T_271, _T_272) when _T_273 : connect ret_prv, reg_dcsr.prv node _reg_mstatus_v_T_1 = and(UInt<1>(0h0), reg_dcsr.v) node _reg_mstatus_v_T_2 = leq(reg_dcsr.prv, UInt<1>(0h1)) node _reg_mstatus_v_T_3 = and(_reg_mstatus_v_T_1, _reg_mstatus_v_T_2) connect reg_mstatus.v, _reg_mstatus_v_T_3 connect reg_debug, UInt<1>(0h0) node _io_evec_T_10 = not(reg_dpc) node _io_evec_T_11 = bits(reg_misa, 2, 2) node _io_evec_T_12 = mux(_io_evec_T_11, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_13 = or(_io_evec_T_10, _io_evec_T_12) node _io_evec_T_14 = not(_io_evec_T_13) connect io.evec, _io_evec_T_14 else : node _T_274 = bits(io.rw.addr, 10, 10) node _T_275 = and(UInt<1>(0h0), _T_274) node _T_276 = bits(io.rw.addr, 7, 7) node _T_277 = eq(_T_276, UInt<1>(0h0)) node _T_278 = and(_T_275, _T_277) when _T_278 : connect ret_prv, reg_mnstatus.mpp node _reg_mstatus_v_T_4 = and(UInt<1>(0h0), reg_mnstatus.mpv) node _reg_mstatus_v_T_5 = leq(reg_mnstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_6 = and(_reg_mstatus_v_T_4, _reg_mstatus_v_T_5) connect reg_mstatus.v, _reg_mstatus_v_T_6 connect reg_rnmie, UInt<1>(0h1) node _io_evec_T_15 = not(reg_mnepc) node _io_evec_T_16 = bits(reg_misa, 2, 2) node _io_evec_T_17 = mux(_io_evec_T_16, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_18 = or(_io_evec_T_15, _io_evec_T_17) node _io_evec_T_19 = not(_io_evec_T_18) connect io.evec, _io_evec_T_19 else : connect reg_mstatus.mie, reg_mstatus.mpie connect reg_mstatus.mpie, UInt<1>(0h1) connect reg_mstatus.mpp, UInt<2>(0h3) connect reg_mstatus.mpv, UInt<1>(0h0) connect ret_prv, reg_mstatus.mpp node _reg_mstatus_v_T_7 = and(UInt<1>(0h0), reg_mstatus.mpv) node _reg_mstatus_v_T_8 = leq(reg_mstatus.mpp, UInt<1>(0h1)) node _reg_mstatus_v_T_9 = and(_reg_mstatus_v_T_7, _reg_mstatus_v_T_8) connect reg_mstatus.v, _reg_mstatus_v_T_9 node _io_evec_T_20 = not(reg_mepc) node _io_evec_T_21 = bits(reg_misa, 2, 2) node _io_evec_T_22 = mux(_io_evec_T_21, UInt<1>(0h1), UInt<2>(0h3)) node _io_evec_T_23 = or(_io_evec_T_20, _io_evec_T_22) node _io_evec_T_24 = not(_io_evec_T_23) connect io.evec, _io_evec_T_24 connect new_prv, ret_prv node _T_279 = leq(ret_prv, UInt<1>(0h1)) node _T_280 = and(UInt<1>(0h0), _T_279) when _T_280 : connect reg_mstatus.mprv, UInt<1>(0h0) connect io.time, value_1 node _io_csr_stall_T = or(reg_wfi, io.status.cease) connect io.csr_stall, _io_csr_stall_T regreset io_status_cease_r : UInt<1>, clock, reset, UInt<1>(0h0) when insn_cease : connect io_status_cease_r, UInt<1>(0h1) connect io.status.cease, io_status_cease_r connect io.status.wfi, reg_wfi connect io.customCSRs[0].wen, UInt<1>(0h0) connect io.customCSRs[0].wdata, wdata connect io.customCSRs[0].value, reg_custom_0 connect io.customCSRs[1].wen, UInt<1>(0h0) connect io.customCSRs[1].wdata, wdata connect io.customCSRs[1].value, reg_custom_1 connect io.customCSRs[2].wen, UInt<1>(0h0) connect io.customCSRs[2].wdata, wdata connect io.customCSRs[2].value, reg_custom_2 connect io.customCSRs[3].wen, UInt<1>(0h0) connect io.customCSRs[3].wdata, wdata connect io.customCSRs[3].value, reg_custom_3 node _io_rw_rdata_T = mux(decoded_addr_121_2, reg_tselect, UInt<1>(0h0)) node _io_rw_rdata_T_1 = mux(decoded_addr_66_2, read_mapping_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_2 = mux(decoded_addr_13_2, reg_bp[reg_tselect].address, UInt<1>(0h0)) node _io_rw_rdata_T_3 = mux(decoded_addr_153_2, read_mapping_3_2, UInt<1>(0h0)) node _io_rw_rdata_T_4 = mux(decoded_addr_115_2, reg_misa, UInt<1>(0h0)) node _io_rw_rdata_T_5 = mux(decoded_addr_125_2, read_mstatus, UInt<1>(0h0)) node _io_rw_rdata_T_6 = mux(decoded_addr_89_2, read_mtvec, UInt<1>(0h0)) node _io_rw_rdata_T_7 = mux(decoded_addr_135_2, read_mip, UInt<1>(0h0)) node _io_rw_rdata_T_8 = mux(decoded_addr_94_2, reg_mie, UInt<1>(0h0)) node _io_rw_rdata_T_9 = mux(decoded_addr_170_2, reg_mscratch, UInt<1>(0h0)) node _io_rw_rdata_T_10 = mux(decoded_addr_173_2, read_mapping_10_2, UInt<1>(0h0)) node _io_rw_rdata_T_11 = mux(decoded_addr_179_2, reg_mtval, UInt<1>(0h0)) node _io_rw_rdata_T_12 = mux(decoded_addr_35_2, reg_mcause, UInt<1>(0h0)) node _io_rw_rdata_T_13 = mux(decoded_addr_172_2, io.hartid, UInt<1>(0h0)) node _io_rw_rdata_T_14 = mux(decoded_addr_59_2, debug_csrs_0_2, UInt<1>(0h0)) node _io_rw_rdata_T_15 = mux(decoded_addr_112_2, debug_csrs_1_2, UInt<1>(0h0)) node _io_rw_rdata_T_16 = mux(decoded_addr_69_2, reg_dscratch0, UInt<1>(0h0)) node _io_rw_rdata_T_17 = mux(decoded_addr_171_2, reg_mcountinhibit, UInt<1>(0h0)) node _io_rw_rdata_T_18 = mux(decoded_addr_128_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_19 = mux(decoded_addr_156_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_20 = mux(decoded_addr_189_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_21 = mux(decoded_addr_20_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_22 = mux(decoded_addr_34_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_23 = mux(decoded_addr_6_2, _T_16, UInt<1>(0h0)) node _io_rw_rdata_T_24 = mux(decoded_addr_177_2, _T_17, UInt<1>(0h0)) node _io_rw_rdata_T_25 = mux(decoded_addr_105_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_26 = mux(decoded_addr_62_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_27 = mux(decoded_addr_188_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_28 = mux(decoded_addr_148_2, _T_18, UInt<1>(0h0)) node _io_rw_rdata_T_29 = mux(decoded_addr_22_2, _T_19, UInt<1>(0h0)) node _io_rw_rdata_T_30 = mux(decoded_addr_86_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_31 = mux(decoded_addr_141_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_32 = mux(decoded_addr_103_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_33 = mux(decoded_addr_152_2, _T_20, UInt<1>(0h0)) node _io_rw_rdata_T_34 = mux(decoded_addr_73_2, _T_21, UInt<1>(0h0)) node _io_rw_rdata_T_35 = mux(decoded_addr_37_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_36 = mux(decoded_addr_0_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_37 = mux(decoded_addr_72_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_38 = mux(decoded_addr_33_2, _T_22, UInt<1>(0h0)) node _io_rw_rdata_T_39 = mux(decoded_addr_131_2, _T_23, UInt<1>(0h0)) node _io_rw_rdata_T_40 = mux(decoded_addr_180_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_41 = mux(decoded_addr_165_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_42 = mux(decoded_addr_91_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_43 = mux(decoded_addr_176_2, _T_24, UInt<1>(0h0)) node _io_rw_rdata_T_44 = mux(decoded_addr_56_2, _T_25, UInt<1>(0h0)) node _io_rw_rdata_T_45 = mux(decoded_addr_147_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_46 = mux(decoded_addr_119_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_47 = mux(decoded_addr_143_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_48 = mux(decoded_addr_129_2, _T_26, UInt<1>(0h0)) node _io_rw_rdata_T_49 = mux(decoded_addr_104_2, _T_27, UInt<1>(0h0)) node _io_rw_rdata_T_50 = mux(decoded_addr_1_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_51 = mux(decoded_addr_19_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_52 = mux(decoded_addr_96_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_53 = mux(decoded_addr_5_2, _T_28, UInt<1>(0h0)) node _io_rw_rdata_T_54 = mux(decoded_addr_142_2, _T_29, UInt<1>(0h0)) node _io_rw_rdata_T_55 = mux(decoded_addr_49_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_56 = mux(decoded_addr_61_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_57 = mux(decoded_addr_136_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_58 = mux(decoded_addr_45_2, _T_30, UInt<1>(0h0)) node _io_rw_rdata_T_59 = mux(decoded_addr_75_2, _T_31, UInt<1>(0h0)) node _io_rw_rdata_T_60 = mux(decoded_addr_113_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_61 = mux(decoded_addr_99_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_62 = mux(decoded_addr_83_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_63 = mux(decoded_addr_110_2, _T_32, UInt<1>(0h0)) node _io_rw_rdata_T_64 = mux(decoded_addr_44_2, _T_33, UInt<1>(0h0)) node _io_rw_rdata_T_65 = mux(decoded_addr_132_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_66 = mux(decoded_addr_158_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_67 = mux(decoded_addr_30_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_68 = mux(decoded_addr_168_2, _T_34, UInt<1>(0h0)) node _io_rw_rdata_T_69 = mux(decoded_addr_191_2, _T_35, UInt<1>(0h0)) node _io_rw_rdata_T_70 = mux(decoded_addr_160_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_71 = mux(decoded_addr_32_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_72 = mux(decoded_addr_164_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_73 = mux(decoded_addr_21_2, _T_36, UInt<1>(0h0)) node _io_rw_rdata_T_74 = mux(decoded_addr_101_2, _T_37, UInt<1>(0h0)) node _io_rw_rdata_T_75 = mux(decoded_addr_10_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_76 = mux(decoded_addr_76_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_77 = mux(decoded_addr_95_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_78 = mux(decoded_addr_57_2, _T_38, UInt<1>(0h0)) node _io_rw_rdata_T_79 = mux(decoded_addr_137_2, _T_39, UInt<1>(0h0)) node _io_rw_rdata_T_80 = mux(decoded_addr_55_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_81 = mux(decoded_addr_140_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_82 = mux(decoded_addr_74_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_83 = mux(decoded_addr_100_2, _T_40, UInt<1>(0h0)) node _io_rw_rdata_T_84 = mux(decoded_addr_84_2, _T_41, UInt<1>(0h0)) node _io_rw_rdata_T_85 = mux(decoded_addr_114_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_86 = mux(decoded_addr_193_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_87 = mux(decoded_addr_18_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_88 = mux(decoded_addr_159_2, _T_42, UInt<1>(0h0)) node _io_rw_rdata_T_89 = mux(decoded_addr_29_2, _T_43, UInt<1>(0h0)) node _io_rw_rdata_T_90 = mux(decoded_addr_27_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_91 = mux(decoded_addr_40_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_92 = mux(decoded_addr_25_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_93 = mux(decoded_addr_181_2, _T_44, UInt<1>(0h0)) node _io_rw_rdata_T_94 = mux(decoded_addr_9_2, _T_45, UInt<1>(0h0)) node _io_rw_rdata_T_95 = mux(decoded_addr_174_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_96 = mux(decoded_addr_194_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_97 = mux(decoded_addr_60_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_98 = mux(decoded_addr_122_2, _T_46, UInt<1>(0h0)) node _io_rw_rdata_T_99 = mux(decoded_addr_70_2, _T_47, UInt<1>(0h0)) node _io_rw_rdata_T_100 = mux(decoded_addr_92_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_101 = mux(decoded_addr_127_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_102 = mux(decoded_addr_106_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_103 = mux(decoded_addr_87_2, _T_48, UInt<1>(0h0)) node _io_rw_rdata_T_104 = mux(decoded_addr_118_2, _T_49, UInt<1>(0h0)) node _io_rw_rdata_T_105 = mux(decoded_addr_53_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_106 = mux(decoded_addr_79_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_107 = mux(decoded_addr_155_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_108 = mux(decoded_addr_39_2, _T_50, UInt<1>(0h0)) node _io_rw_rdata_T_109 = mux(decoded_addr_166_2, _T_51, UInt<1>(0h0)) node _io_rw_rdata_T_110 = mux(decoded_addr_36_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_111 = mux(decoded_addr_8_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_112 = mux(decoded_addr_38_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_113 = mux(decoded_addr_43_2, _T_52, UInt<1>(0h0)) node _io_rw_rdata_T_114 = mux(decoded_addr_23_2, _T_53, UInt<1>(0h0)) node _io_rw_rdata_T_115 = mux(decoded_addr_187_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_116 = mux(decoded_addr_149_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_117 = mux(decoded_addr_77_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_118 = mux(decoded_addr_185_2, _T_54, UInt<1>(0h0)) node _io_rw_rdata_T_119 = mux(decoded_addr_81_2, _T_55, UInt<1>(0h0)) node _io_rw_rdata_T_120 = mux(decoded_addr_134_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_121 = mux(decoded_addr_111_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_122 = mux(decoded_addr_145_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_123 = mux(decoded_addr_124_2, _T_56, UInt<1>(0h0)) node _io_rw_rdata_T_124 = mux(decoded_addr_102_2, _T_57, UInt<1>(0h0)) node _io_rw_rdata_T_125 = mux(decoded_addr_90_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_126 = mux(decoded_addr_63_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_127 = mux(decoded_addr_192_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_128 = mux(decoded_addr_78_2, _T_58, UInt<1>(0h0)) node _io_rw_rdata_T_129 = mux(decoded_addr_151_2, _T_59, UInt<1>(0h0)) node _io_rw_rdata_T_130 = mux(decoded_addr_51_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_131 = mux(decoded_addr_67_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_132 = mux(decoded_addr_46_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_133 = mux(decoded_addr_54_2, _T_60, UInt<1>(0h0)) node _io_rw_rdata_T_134 = mux(decoded_addr_85_2, _T_61, UInt<1>(0h0)) node _io_rw_rdata_T_135 = mux(decoded_addr_97_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_136 = mux(decoded_addr_120_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_137 = mux(decoded_addr_7_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_138 = mux(decoded_addr_93_2, _T_62, UInt<1>(0h0)) node _io_rw_rdata_T_139 = mux(decoded_addr_42_2, _T_63, UInt<1>(0h0)) node _io_rw_rdata_T_140 = mux(decoded_addr_126_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_141 = mux(decoded_addr_154_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_142 = mux(decoded_addr_28_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_143 = mux(decoded_addr_162_2, _T_64, UInt<1>(0h0)) node _io_rw_rdata_T_144 = mux(decoded_addr_190_2, _T_65, UInt<1>(0h0)) node _io_rw_rdata_T_145 = mux(decoded_addr_182_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_146 = mux(decoded_addr_14_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_147 = mux(decoded_addr_175_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_148 = mux(decoded_addr_17_2, _T_66, UInt<1>(0h0)) node _io_rw_rdata_T_149 = mux(decoded_addr_139_2, _T_67, UInt<1>(0h0)) node _io_rw_rdata_T_150 = mux(decoded_addr_15_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_151 = mux(decoded_addr_80_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_152 = mux(decoded_addr_108_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_153 = mux(decoded_addr_68_2, _T_68, UInt<1>(0h0)) node _io_rw_rdata_T_154 = mux(decoded_addr_47_2, _T_69, UInt<1>(0h0)) node _io_rw_rdata_T_155 = mux(decoded_addr_58_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_156 = mux(decoded_addr_133_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_157 = mux(decoded_addr_71_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_158 = mux(decoded_addr_117_2, _T_70, UInt<1>(0h0)) node _io_rw_rdata_T_159 = mux(decoded_addr_4_2, _T_71, UInt<1>(0h0)) node _io_rw_rdata_T_160 = mux(decoded_addr_109_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_161 = mux(decoded_addr_186_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_162 = mux(decoded_addr_16_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_163 = mux(decoded_addr_150_2, _T_72, UInt<1>(0h0)) node _io_rw_rdata_T_164 = mux(decoded_addr_31_2, _T_73, UInt<1>(0h0)) node _io_rw_rdata_T_165 = mux(decoded_addr_2_2, value_1, UInt<1>(0h0)) node _io_rw_rdata_T_166 = mux(decoded_addr_82_2, value, UInt<1>(0h0)) node _io_rw_rdata_T_167 = mux(decoded_addr_167_2, _T_74, UInt<1>(0h0)) node _io_rw_rdata_T_168 = mux(decoded_addr_64_2, _T_75, UInt<1>(0h0)) node _io_rw_rdata_T_169 = mux(decoded_addr_195_2, _T_76, UInt<1>(0h0)) node _io_rw_rdata_T_170 = mux(decoded_addr_144_2, _T_77, UInt<1>(0h0)) node _io_rw_rdata_T_171 = mux(decoded_addr_184_2, _T_82, UInt<1>(0h0)) node _io_rw_rdata_T_172 = mux(decoded_addr_169_2, _T_87, UInt<1>(0h0)) node _io_rw_rdata_T_173 = mux(decoded_addr_12_2, _T_92, UInt<1>(0h0)) node _io_rw_rdata_T_174 = mux(decoded_addr_157_2, _T_97, UInt<1>(0h0)) node _io_rw_rdata_T_175 = mux(decoded_addr_130_2, reg_pmp[0].addr, UInt<1>(0h0)) node _io_rw_rdata_T_176 = mux(decoded_addr_11_2, reg_pmp[1].addr, UInt<1>(0h0)) node _io_rw_rdata_T_177 = mux(decoded_addr_161_2, reg_pmp[2].addr, UInt<1>(0h0)) node _io_rw_rdata_T_178 = mux(decoded_addr_107_2, reg_pmp[3].addr, UInt<1>(0h0)) node _io_rw_rdata_T_179 = mux(decoded_addr_65_2, reg_pmp[4].addr, UInt<1>(0h0)) node _io_rw_rdata_T_180 = mux(decoded_addr_26_2, reg_pmp[5].addr, UInt<1>(0h0)) node _io_rw_rdata_T_181 = mux(decoded_addr_178_2, reg_pmp[6].addr, UInt<1>(0h0)) node _io_rw_rdata_T_182 = mux(decoded_addr_146_2, reg_pmp[7].addr, UInt<1>(0h0)) node _io_rw_rdata_T_183 = mux(decoded_addr_52_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_184 = mux(decoded_addr_88_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_185 = mux(decoded_addr_138_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_186 = mux(decoded_addr_183_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_187 = mux(decoded_addr_41_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_188 = mux(decoded_addr_50_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_189 = mux(decoded_addr_98_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_190 = mux(decoded_addr_123_2, read_pmp_15.addr, UInt<1>(0h0)) node _io_rw_rdata_T_191 = mux(decoded_addr_24_2, reg_custom_0, UInt<1>(0h0)) node _io_rw_rdata_T_192 = mux(decoded_addr_3_2, reg_custom_1, UInt<1>(0h0)) node _io_rw_rdata_T_193 = mux(decoded_addr_48_2, reg_custom_2, UInt<1>(0h0)) node _io_rw_rdata_T_194 = mux(decoded_addr_163_2, reg_custom_3, UInt<1>(0h0)) node _io_rw_rdata_T_195 = mux(decoded_addr_116_2, UInt<1>(0h0), UInt<1>(0h0)) node _io_rw_rdata_T_196 = or(_io_rw_rdata_T, _io_rw_rdata_T_1) node _io_rw_rdata_T_197 = or(_io_rw_rdata_T_196, _io_rw_rdata_T_2) node _io_rw_rdata_T_198 = or(_io_rw_rdata_T_197, _io_rw_rdata_T_3) node _io_rw_rdata_T_199 = or(_io_rw_rdata_T_198, _io_rw_rdata_T_4) node _io_rw_rdata_T_200 = or(_io_rw_rdata_T_199, _io_rw_rdata_T_5) node _io_rw_rdata_T_201 = or(_io_rw_rdata_T_200, _io_rw_rdata_T_6) node _io_rw_rdata_T_202 = or(_io_rw_rdata_T_201, _io_rw_rdata_T_7) node _io_rw_rdata_T_203 = or(_io_rw_rdata_T_202, _io_rw_rdata_T_8) node _io_rw_rdata_T_204 = or(_io_rw_rdata_T_203, _io_rw_rdata_T_9) node _io_rw_rdata_T_205 = or(_io_rw_rdata_T_204, _io_rw_rdata_T_10) node _io_rw_rdata_T_206 = or(_io_rw_rdata_T_205, _io_rw_rdata_T_11) node _io_rw_rdata_T_207 = or(_io_rw_rdata_T_206, _io_rw_rdata_T_12) node _io_rw_rdata_T_208 = or(_io_rw_rdata_T_207, _io_rw_rdata_T_13) node _io_rw_rdata_T_209 = or(_io_rw_rdata_T_208, _io_rw_rdata_T_14) node _io_rw_rdata_T_210 = or(_io_rw_rdata_T_209, _io_rw_rdata_T_15) node _io_rw_rdata_T_211 = or(_io_rw_rdata_T_210, _io_rw_rdata_T_16) node _io_rw_rdata_T_212 = or(_io_rw_rdata_T_211, _io_rw_rdata_T_17) node _io_rw_rdata_T_213 = or(_io_rw_rdata_T_212, _io_rw_rdata_T_18) node _io_rw_rdata_T_214 = or(_io_rw_rdata_T_213, _io_rw_rdata_T_19) node _io_rw_rdata_T_215 = or(_io_rw_rdata_T_214, _io_rw_rdata_T_20) node _io_rw_rdata_T_216 = or(_io_rw_rdata_T_215, _io_rw_rdata_T_21) node _io_rw_rdata_T_217 = or(_io_rw_rdata_T_216, _io_rw_rdata_T_22) node _io_rw_rdata_T_218 = or(_io_rw_rdata_T_217, _io_rw_rdata_T_23) node _io_rw_rdata_T_219 = or(_io_rw_rdata_T_218, _io_rw_rdata_T_24) node _io_rw_rdata_T_220 = or(_io_rw_rdata_T_219, _io_rw_rdata_T_25) node _io_rw_rdata_T_221 = or(_io_rw_rdata_T_220, _io_rw_rdata_T_26) node _io_rw_rdata_T_222 = or(_io_rw_rdata_T_221, _io_rw_rdata_T_27) node _io_rw_rdata_T_223 = or(_io_rw_rdata_T_222, _io_rw_rdata_T_28) node _io_rw_rdata_T_224 = or(_io_rw_rdata_T_223, _io_rw_rdata_T_29) node _io_rw_rdata_T_225 = or(_io_rw_rdata_T_224, _io_rw_rdata_T_30) node _io_rw_rdata_T_226 = or(_io_rw_rdata_T_225, _io_rw_rdata_T_31) node _io_rw_rdata_T_227 = or(_io_rw_rdata_T_226, _io_rw_rdata_T_32) node _io_rw_rdata_T_228 = or(_io_rw_rdata_T_227, _io_rw_rdata_T_33) node _io_rw_rdata_T_229 = or(_io_rw_rdata_T_228, _io_rw_rdata_T_34) node _io_rw_rdata_T_230 = or(_io_rw_rdata_T_229, _io_rw_rdata_T_35) node _io_rw_rdata_T_231 = or(_io_rw_rdata_T_230, _io_rw_rdata_T_36) node _io_rw_rdata_T_232 = or(_io_rw_rdata_T_231, _io_rw_rdata_T_37) node _io_rw_rdata_T_233 = or(_io_rw_rdata_T_232, _io_rw_rdata_T_38) node _io_rw_rdata_T_234 = or(_io_rw_rdata_T_233, _io_rw_rdata_T_39) node _io_rw_rdata_T_235 = or(_io_rw_rdata_T_234, _io_rw_rdata_T_40) node _io_rw_rdata_T_236 = or(_io_rw_rdata_T_235, _io_rw_rdata_T_41) node _io_rw_rdata_T_237 = or(_io_rw_rdata_T_236, _io_rw_rdata_T_42) node _io_rw_rdata_T_238 = or(_io_rw_rdata_T_237, _io_rw_rdata_T_43) node _io_rw_rdata_T_239 = or(_io_rw_rdata_T_238, _io_rw_rdata_T_44) node _io_rw_rdata_T_240 = or(_io_rw_rdata_T_239, _io_rw_rdata_T_45) node _io_rw_rdata_T_241 = or(_io_rw_rdata_T_240, _io_rw_rdata_T_46) node _io_rw_rdata_T_242 = or(_io_rw_rdata_T_241, _io_rw_rdata_T_47) node _io_rw_rdata_T_243 = or(_io_rw_rdata_T_242, _io_rw_rdata_T_48) node _io_rw_rdata_T_244 = or(_io_rw_rdata_T_243, _io_rw_rdata_T_49) node _io_rw_rdata_T_245 = or(_io_rw_rdata_T_244, _io_rw_rdata_T_50) node _io_rw_rdata_T_246 = or(_io_rw_rdata_T_245, _io_rw_rdata_T_51) node _io_rw_rdata_T_247 = or(_io_rw_rdata_T_246, _io_rw_rdata_T_52) node _io_rw_rdata_T_248 = or(_io_rw_rdata_T_247, _io_rw_rdata_T_53) node _io_rw_rdata_T_249 = or(_io_rw_rdata_T_248, _io_rw_rdata_T_54) node _io_rw_rdata_T_250 = or(_io_rw_rdata_T_249, _io_rw_rdata_T_55) node _io_rw_rdata_T_251 = or(_io_rw_rdata_T_250, _io_rw_rdata_T_56) node _io_rw_rdata_T_252 = or(_io_rw_rdata_T_251, _io_rw_rdata_T_57) node _io_rw_rdata_T_253 = or(_io_rw_rdata_T_252, _io_rw_rdata_T_58) node _io_rw_rdata_T_254 = or(_io_rw_rdata_T_253, _io_rw_rdata_T_59) node _io_rw_rdata_T_255 = or(_io_rw_rdata_T_254, _io_rw_rdata_T_60) node _io_rw_rdata_T_256 = or(_io_rw_rdata_T_255, _io_rw_rdata_T_61) node _io_rw_rdata_T_257 = or(_io_rw_rdata_T_256, _io_rw_rdata_T_62) node _io_rw_rdata_T_258 = or(_io_rw_rdata_T_257, _io_rw_rdata_T_63) node _io_rw_rdata_T_259 = or(_io_rw_rdata_T_258, _io_rw_rdata_T_64) node _io_rw_rdata_T_260 = or(_io_rw_rdata_T_259, _io_rw_rdata_T_65) node _io_rw_rdata_T_261 = or(_io_rw_rdata_T_260, _io_rw_rdata_T_66) node _io_rw_rdata_T_262 = or(_io_rw_rdata_T_261, _io_rw_rdata_T_67) node _io_rw_rdata_T_263 = or(_io_rw_rdata_T_262, _io_rw_rdata_T_68) node _io_rw_rdata_T_264 = or(_io_rw_rdata_T_263, _io_rw_rdata_T_69) node _io_rw_rdata_T_265 = or(_io_rw_rdata_T_264, _io_rw_rdata_T_70) node _io_rw_rdata_T_266 = or(_io_rw_rdata_T_265, _io_rw_rdata_T_71) node _io_rw_rdata_T_267 = or(_io_rw_rdata_T_266, _io_rw_rdata_T_72) node _io_rw_rdata_T_268 = or(_io_rw_rdata_T_267, _io_rw_rdata_T_73) node _io_rw_rdata_T_269 = or(_io_rw_rdata_T_268, _io_rw_rdata_T_74) node _io_rw_rdata_T_270 = or(_io_rw_rdata_T_269, _io_rw_rdata_T_75) node _io_rw_rdata_T_271 = or(_io_rw_rdata_T_270, _io_rw_rdata_T_76) node _io_rw_rdata_T_272 = or(_io_rw_rdata_T_271, _io_rw_rdata_T_77) node _io_rw_rdata_T_273 = or(_io_rw_rdata_T_272, _io_rw_rdata_T_78) node _io_rw_rdata_T_274 = or(_io_rw_rdata_T_273, _io_rw_rdata_T_79) node _io_rw_rdata_T_275 = or(_io_rw_rdata_T_274, _io_rw_rdata_T_80) node _io_rw_rdata_T_276 = or(_io_rw_rdata_T_275, _io_rw_rdata_T_81) node _io_rw_rdata_T_277 = or(_io_rw_rdata_T_276, _io_rw_rdata_T_82) node _io_rw_rdata_T_278 = or(_io_rw_rdata_T_277, _io_rw_rdata_T_83) node _io_rw_rdata_T_279 = or(_io_rw_rdata_T_278, _io_rw_rdata_T_84) node _io_rw_rdata_T_280 = or(_io_rw_rdata_T_279, _io_rw_rdata_T_85) node _io_rw_rdata_T_281 = or(_io_rw_rdata_T_280, _io_rw_rdata_T_86) node _io_rw_rdata_T_282 = or(_io_rw_rdata_T_281, _io_rw_rdata_T_87) node _io_rw_rdata_T_283 = or(_io_rw_rdata_T_282, _io_rw_rdata_T_88) node _io_rw_rdata_T_284 = or(_io_rw_rdata_T_283, _io_rw_rdata_T_89) node _io_rw_rdata_T_285 = or(_io_rw_rdata_T_284, _io_rw_rdata_T_90) node _io_rw_rdata_T_286 = or(_io_rw_rdata_T_285, _io_rw_rdata_T_91) node _io_rw_rdata_T_287 = or(_io_rw_rdata_T_286, _io_rw_rdata_T_92) node _io_rw_rdata_T_288 = or(_io_rw_rdata_T_287, _io_rw_rdata_T_93) node _io_rw_rdata_T_289 = or(_io_rw_rdata_T_288, _io_rw_rdata_T_94) node _io_rw_rdata_T_290 = or(_io_rw_rdata_T_289, _io_rw_rdata_T_95) node _io_rw_rdata_T_291 = or(_io_rw_rdata_T_290, _io_rw_rdata_T_96) node _io_rw_rdata_T_292 = or(_io_rw_rdata_T_291, _io_rw_rdata_T_97) node _io_rw_rdata_T_293 = or(_io_rw_rdata_T_292, _io_rw_rdata_T_98) node _io_rw_rdata_T_294 = or(_io_rw_rdata_T_293, _io_rw_rdata_T_99) node _io_rw_rdata_T_295 = or(_io_rw_rdata_T_294, _io_rw_rdata_T_100) node _io_rw_rdata_T_296 = or(_io_rw_rdata_T_295, _io_rw_rdata_T_101) node _io_rw_rdata_T_297 = or(_io_rw_rdata_T_296, _io_rw_rdata_T_102) node _io_rw_rdata_T_298 = or(_io_rw_rdata_T_297, _io_rw_rdata_T_103) node _io_rw_rdata_T_299 = or(_io_rw_rdata_T_298, _io_rw_rdata_T_104) node _io_rw_rdata_T_300 = or(_io_rw_rdata_T_299, _io_rw_rdata_T_105) node _io_rw_rdata_T_301 = or(_io_rw_rdata_T_300, _io_rw_rdata_T_106) node _io_rw_rdata_T_302 = or(_io_rw_rdata_T_301, _io_rw_rdata_T_107) node _io_rw_rdata_T_303 = or(_io_rw_rdata_T_302, _io_rw_rdata_T_108) node _io_rw_rdata_T_304 = or(_io_rw_rdata_T_303, _io_rw_rdata_T_109) node _io_rw_rdata_T_305 = or(_io_rw_rdata_T_304, _io_rw_rdata_T_110) node _io_rw_rdata_T_306 = or(_io_rw_rdata_T_305, _io_rw_rdata_T_111) node _io_rw_rdata_T_307 = or(_io_rw_rdata_T_306, _io_rw_rdata_T_112) node _io_rw_rdata_T_308 = or(_io_rw_rdata_T_307, _io_rw_rdata_T_113) node _io_rw_rdata_T_309 = or(_io_rw_rdata_T_308, _io_rw_rdata_T_114) node _io_rw_rdata_T_310 = or(_io_rw_rdata_T_309, _io_rw_rdata_T_115) node _io_rw_rdata_T_311 = or(_io_rw_rdata_T_310, _io_rw_rdata_T_116) node _io_rw_rdata_T_312 = or(_io_rw_rdata_T_311, _io_rw_rdata_T_117) node _io_rw_rdata_T_313 = or(_io_rw_rdata_T_312, _io_rw_rdata_T_118) node _io_rw_rdata_T_314 = or(_io_rw_rdata_T_313, _io_rw_rdata_T_119) node _io_rw_rdata_T_315 = or(_io_rw_rdata_T_314, _io_rw_rdata_T_120) node _io_rw_rdata_T_316 = or(_io_rw_rdata_T_315, _io_rw_rdata_T_121) node _io_rw_rdata_T_317 = or(_io_rw_rdata_T_316, _io_rw_rdata_T_122) node _io_rw_rdata_T_318 = or(_io_rw_rdata_T_317, _io_rw_rdata_T_123) node _io_rw_rdata_T_319 = or(_io_rw_rdata_T_318, _io_rw_rdata_T_124) node _io_rw_rdata_T_320 = or(_io_rw_rdata_T_319, _io_rw_rdata_T_125) node _io_rw_rdata_T_321 = or(_io_rw_rdata_T_320, _io_rw_rdata_T_126) node _io_rw_rdata_T_322 = or(_io_rw_rdata_T_321, _io_rw_rdata_T_127) node _io_rw_rdata_T_323 = or(_io_rw_rdata_T_322, _io_rw_rdata_T_128) node _io_rw_rdata_T_324 = or(_io_rw_rdata_T_323, _io_rw_rdata_T_129) node _io_rw_rdata_T_325 = or(_io_rw_rdata_T_324, _io_rw_rdata_T_130) node _io_rw_rdata_T_326 = or(_io_rw_rdata_T_325, _io_rw_rdata_T_131) node _io_rw_rdata_T_327 = or(_io_rw_rdata_T_326, _io_rw_rdata_T_132) node _io_rw_rdata_T_328 = or(_io_rw_rdata_T_327, _io_rw_rdata_T_133) node _io_rw_rdata_T_329 = or(_io_rw_rdata_T_328, _io_rw_rdata_T_134) node _io_rw_rdata_T_330 = or(_io_rw_rdata_T_329, _io_rw_rdata_T_135) node _io_rw_rdata_T_331 = or(_io_rw_rdata_T_330, _io_rw_rdata_T_136) node _io_rw_rdata_T_332 = or(_io_rw_rdata_T_331, _io_rw_rdata_T_137) node _io_rw_rdata_T_333 = or(_io_rw_rdata_T_332, _io_rw_rdata_T_138) node _io_rw_rdata_T_334 = or(_io_rw_rdata_T_333, _io_rw_rdata_T_139) node _io_rw_rdata_T_335 = or(_io_rw_rdata_T_334, _io_rw_rdata_T_140) node _io_rw_rdata_T_336 = or(_io_rw_rdata_T_335, _io_rw_rdata_T_141) node _io_rw_rdata_T_337 = or(_io_rw_rdata_T_336, _io_rw_rdata_T_142) node _io_rw_rdata_T_338 = or(_io_rw_rdata_T_337, _io_rw_rdata_T_143) node _io_rw_rdata_T_339 = or(_io_rw_rdata_T_338, _io_rw_rdata_T_144) node _io_rw_rdata_T_340 = or(_io_rw_rdata_T_339, _io_rw_rdata_T_145) node _io_rw_rdata_T_341 = or(_io_rw_rdata_T_340, _io_rw_rdata_T_146) node _io_rw_rdata_T_342 = or(_io_rw_rdata_T_341, _io_rw_rdata_T_147) node _io_rw_rdata_T_343 = or(_io_rw_rdata_T_342, _io_rw_rdata_T_148) node _io_rw_rdata_T_344 = or(_io_rw_rdata_T_343, _io_rw_rdata_T_149) node _io_rw_rdata_T_345 = or(_io_rw_rdata_T_344, _io_rw_rdata_T_150) node _io_rw_rdata_T_346 = or(_io_rw_rdata_T_345, _io_rw_rdata_T_151) node _io_rw_rdata_T_347 = or(_io_rw_rdata_T_346, _io_rw_rdata_T_152) node _io_rw_rdata_T_348 = or(_io_rw_rdata_T_347, _io_rw_rdata_T_153) node _io_rw_rdata_T_349 = or(_io_rw_rdata_T_348, _io_rw_rdata_T_154) node _io_rw_rdata_T_350 = or(_io_rw_rdata_T_349, _io_rw_rdata_T_155) node _io_rw_rdata_T_351 = or(_io_rw_rdata_T_350, _io_rw_rdata_T_156) node _io_rw_rdata_T_352 = or(_io_rw_rdata_T_351, _io_rw_rdata_T_157) node _io_rw_rdata_T_353 = or(_io_rw_rdata_T_352, _io_rw_rdata_T_158) node _io_rw_rdata_T_354 = or(_io_rw_rdata_T_353, _io_rw_rdata_T_159) node _io_rw_rdata_T_355 = or(_io_rw_rdata_T_354, _io_rw_rdata_T_160) node _io_rw_rdata_T_356 = or(_io_rw_rdata_T_355, _io_rw_rdata_T_161) node _io_rw_rdata_T_357 = or(_io_rw_rdata_T_356, _io_rw_rdata_T_162) node _io_rw_rdata_T_358 = or(_io_rw_rdata_T_357, _io_rw_rdata_T_163) node _io_rw_rdata_T_359 = or(_io_rw_rdata_T_358, _io_rw_rdata_T_164) node _io_rw_rdata_T_360 = or(_io_rw_rdata_T_359, _io_rw_rdata_T_165) node _io_rw_rdata_T_361 = or(_io_rw_rdata_T_360, _io_rw_rdata_T_166) node _io_rw_rdata_T_362 = or(_io_rw_rdata_T_361, _io_rw_rdata_T_167) node _io_rw_rdata_T_363 = or(_io_rw_rdata_T_362, _io_rw_rdata_T_168) node _io_rw_rdata_T_364 = or(_io_rw_rdata_T_363, _io_rw_rdata_T_169) node _io_rw_rdata_T_365 = or(_io_rw_rdata_T_364, _io_rw_rdata_T_170) node _io_rw_rdata_T_366 = or(_io_rw_rdata_T_365, _io_rw_rdata_T_171) node _io_rw_rdata_T_367 = or(_io_rw_rdata_T_366, _io_rw_rdata_T_172) node _io_rw_rdata_T_368 = or(_io_rw_rdata_T_367, _io_rw_rdata_T_173) node _io_rw_rdata_T_369 = or(_io_rw_rdata_T_368, _io_rw_rdata_T_174) node _io_rw_rdata_T_370 = or(_io_rw_rdata_T_369, _io_rw_rdata_T_175) node _io_rw_rdata_T_371 = or(_io_rw_rdata_T_370, _io_rw_rdata_T_176) node _io_rw_rdata_T_372 = or(_io_rw_rdata_T_371, _io_rw_rdata_T_177) node _io_rw_rdata_T_373 = or(_io_rw_rdata_T_372, _io_rw_rdata_T_178) node _io_rw_rdata_T_374 = or(_io_rw_rdata_T_373, _io_rw_rdata_T_179) node _io_rw_rdata_T_375 = or(_io_rw_rdata_T_374, _io_rw_rdata_T_180) node _io_rw_rdata_T_376 = or(_io_rw_rdata_T_375, _io_rw_rdata_T_181) node _io_rw_rdata_T_377 = or(_io_rw_rdata_T_376, _io_rw_rdata_T_182) node _io_rw_rdata_T_378 = or(_io_rw_rdata_T_377, _io_rw_rdata_T_183) node _io_rw_rdata_T_379 = or(_io_rw_rdata_T_378, _io_rw_rdata_T_184) node _io_rw_rdata_T_380 = or(_io_rw_rdata_T_379, _io_rw_rdata_T_185) node _io_rw_rdata_T_381 = or(_io_rw_rdata_T_380, _io_rw_rdata_T_186) node _io_rw_rdata_T_382 = or(_io_rw_rdata_T_381, _io_rw_rdata_T_187) node _io_rw_rdata_T_383 = or(_io_rw_rdata_T_382, _io_rw_rdata_T_188) node _io_rw_rdata_T_384 = or(_io_rw_rdata_T_383, _io_rw_rdata_T_189) node _io_rw_rdata_T_385 = or(_io_rw_rdata_T_384, _io_rw_rdata_T_190) node _io_rw_rdata_T_386 = or(_io_rw_rdata_T_385, _io_rw_rdata_T_191) node _io_rw_rdata_T_387 = or(_io_rw_rdata_T_386, _io_rw_rdata_T_192) node _io_rw_rdata_T_388 = or(_io_rw_rdata_T_387, _io_rw_rdata_T_193) node _io_rw_rdata_T_389 = or(_io_rw_rdata_T_388, _io_rw_rdata_T_194) node _io_rw_rdata_T_390 = or(_io_rw_rdata_T_389, _io_rw_rdata_T_195) wire _io_rw_rdata_WIRE : UInt connect _io_rw_rdata_WIRE, _io_rw_rdata_T_390 connect io.rw.rdata, _io_rw_rdata_WIRE node _T_281 = andr(UInt<2>(0h1)) node _T_282 = eq(_T_281, UInt<1>(0h0)) when _T_282 : node _T_283 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_284 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_285 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_286 = or(_T_283, _T_284) node _T_287 = or(_T_286, _T_285) node _T_288 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_289 = and(_T_287, _T_288) else : node _T_290 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_291 = eq(io.rw.addr, UInt<11>(0h7a0)) node _T_292 = and(_T_290, _T_291) node _T_293 = andr(UInt<2>(0h1)) node _T_294 = eq(_T_293, UInt<1>(0h0)) when _T_294 : node _T_295 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_296 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_297 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_298 = or(_T_295, _T_296) node _T_299 = or(_T_298, _T_297) node _T_300 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_301 = and(_T_299, _T_300) else : node _T_302 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_303 = eq(io.rw.addr, UInt<11>(0h7a1)) node _T_304 = and(_T_302, _T_303) node _T_305 = andr(UInt<2>(0h1)) node _T_306 = eq(_T_305, UInt<1>(0h0)) when _T_306 : node _T_307 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_308 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_309 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_310 = or(_T_307, _T_308) node _T_311 = or(_T_310, _T_309) node _T_312 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_313 = and(_T_311, _T_312) else : node _T_314 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_315 = eq(io.rw.addr, UInt<11>(0h7a2)) node _T_316 = and(_T_314, _T_315) node _T_317 = andr(UInt<2>(0h1)) node _T_318 = eq(_T_317, UInt<1>(0h0)) when _T_318 : node _T_319 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_320 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_321 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_322 = or(_T_319, _T_320) node _T_323 = or(_T_322, _T_321) node _T_324 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_325 = and(_T_323, _T_324) else : node _T_326 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_327 = eq(io.rw.addr, UInt<11>(0h7a3)) node _T_328 = and(_T_326, _T_327) node _T_329 = andr(UInt<2>(0h0)) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_332 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_333 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_334 = or(_T_331, _T_332) node _T_335 = or(_T_334, _T_333) node _T_336 = eq(io.rw.addr, UInt<10>(0h301)) node _T_337 = and(_T_335, _T_336) else : node _T_338 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_339 = eq(io.rw.addr, UInt<10>(0h301)) node _T_340 = and(_T_338, _T_339) node _T_341 = andr(UInt<2>(0h0)) node _T_342 = eq(_T_341, UInt<1>(0h0)) when _T_342 : node _T_343 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_344 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_345 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_346 = or(_T_343, _T_344) node _T_347 = or(_T_346, _T_345) node _T_348 = eq(io.rw.addr, UInt<10>(0h300)) node _T_349 = and(_T_347, _T_348) else : node _T_350 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_351 = eq(io.rw.addr, UInt<10>(0h300)) node _T_352 = and(_T_350, _T_351) node _T_353 = andr(UInt<2>(0h0)) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_356 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_357 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_358 = or(_T_355, _T_356) node _T_359 = or(_T_358, _T_357) node _T_360 = eq(io.rw.addr, UInt<10>(0h305)) node _T_361 = and(_T_359, _T_360) else : node _T_362 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_363 = eq(io.rw.addr, UInt<10>(0h305)) node _T_364 = and(_T_362, _T_363) node _T_365 = andr(UInt<2>(0h0)) node _T_366 = eq(_T_365, UInt<1>(0h0)) when _T_366 : node _T_367 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_368 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_369 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_370 = or(_T_367, _T_368) node _T_371 = or(_T_370, _T_369) node _T_372 = eq(io.rw.addr, UInt<10>(0h344)) node _T_373 = and(_T_371, _T_372) else : node _T_374 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_375 = eq(io.rw.addr, UInt<10>(0h344)) node _T_376 = and(_T_374, _T_375) node _T_377 = andr(UInt<2>(0h0)) node _T_378 = eq(_T_377, UInt<1>(0h0)) when _T_378 : node _T_379 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_380 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_381 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_382 = or(_T_379, _T_380) node _T_383 = or(_T_382, _T_381) node _T_384 = eq(io.rw.addr, UInt<10>(0h304)) node _T_385 = and(_T_383, _T_384) else : node _T_386 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_387 = eq(io.rw.addr, UInt<10>(0h304)) node _T_388 = and(_T_386, _T_387) node _T_389 = andr(UInt<2>(0h0)) node _T_390 = eq(_T_389, UInt<1>(0h0)) when _T_390 : node _T_391 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_392 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_393 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_394 = or(_T_391, _T_392) node _T_395 = or(_T_394, _T_393) node _T_396 = eq(io.rw.addr, UInt<10>(0h340)) node _T_397 = and(_T_395, _T_396) else : node _T_398 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_399 = eq(io.rw.addr, UInt<10>(0h340)) node _T_400 = and(_T_398, _T_399) node _T_401 = andr(UInt<2>(0h0)) node _T_402 = eq(_T_401, UInt<1>(0h0)) when _T_402 : node _T_403 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_404 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_405 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_406 = or(_T_403, _T_404) node _T_407 = or(_T_406, _T_405) node _T_408 = eq(io.rw.addr, UInt<10>(0h341)) node _T_409 = and(_T_407, _T_408) else : node _T_410 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_411 = eq(io.rw.addr, UInt<10>(0h341)) node _T_412 = and(_T_410, _T_411) node _T_413 = andr(UInt<2>(0h0)) node _T_414 = eq(_T_413, UInt<1>(0h0)) when _T_414 : node _T_415 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_416 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_417 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_418 = or(_T_415, _T_416) node _T_419 = or(_T_418, _T_417) node _T_420 = eq(io.rw.addr, UInt<10>(0h343)) node _T_421 = and(_T_419, _T_420) else : node _T_422 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_423 = eq(io.rw.addr, UInt<10>(0h343)) node _T_424 = and(_T_422, _T_423) node _T_425 = andr(UInt<2>(0h0)) node _T_426 = eq(_T_425, UInt<1>(0h0)) when _T_426 : node _T_427 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_428 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_429 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_430 = or(_T_427, _T_428) node _T_431 = or(_T_430, _T_429) node _T_432 = eq(io.rw.addr, UInt<10>(0h342)) node _T_433 = and(_T_431, _T_432) else : node _T_434 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_435 = eq(io.rw.addr, UInt<10>(0h342)) node _T_436 = and(_T_434, _T_435) node _T_437 = andr(UInt<2>(0h3)) node _T_438 = eq(_T_437, UInt<1>(0h0)) when _T_438 : node _T_439 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_440 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_441 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_442 = or(_T_439, _T_440) node _T_443 = or(_T_442, _T_441) node _T_444 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_445 = and(_T_443, _T_444) else : node _T_446 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_447 = eq(io.rw.addr, UInt<12>(0hf14)) node _T_448 = and(_T_446, _T_447) node _T_449 = andr(UInt<2>(0h1)) node _T_450 = eq(_T_449, UInt<1>(0h0)) when _T_450 : node _T_451 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_452 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_453 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_454 = or(_T_451, _T_452) node _T_455 = or(_T_454, _T_453) node _T_456 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_457 = and(_T_455, _T_456) else : node _T_458 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_459 = eq(io.rw.addr, UInt<11>(0h7b0)) node _T_460 = and(_T_458, _T_459) node _T_461 = andr(UInt<2>(0h1)) node _T_462 = eq(_T_461, UInt<1>(0h0)) when _T_462 : node _T_463 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_464 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_465 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_466 = or(_T_463, _T_464) node _T_467 = or(_T_466, _T_465) node _T_468 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_469 = and(_T_467, _T_468) else : node _T_470 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_471 = eq(io.rw.addr, UInt<11>(0h7b1)) node _T_472 = and(_T_470, _T_471) node _T_473 = andr(UInt<2>(0h1)) node _T_474 = eq(_T_473, UInt<1>(0h0)) when _T_474 : node _T_475 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_476 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_477 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_478 = or(_T_475, _T_476) node _T_479 = or(_T_478, _T_477) node _T_480 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_481 = and(_T_479, _T_480) else : node _T_482 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_483 = eq(io.rw.addr, UInt<11>(0h7b2)) node _T_484 = and(_T_482, _T_483) node _T_485 = andr(UInt<2>(0h0)) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_488 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_489 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_490 = or(_T_487, _T_488) node _T_491 = or(_T_490, _T_489) node _T_492 = eq(io.rw.addr, UInt<10>(0h320)) node _T_493 = and(_T_491, _T_492) else : node _T_494 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_495 = eq(io.rw.addr, UInt<10>(0h320)) node _T_496 = and(_T_494, _T_495) node _T_497 = andr(UInt<2>(0h2)) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_500 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_501 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_502 = or(_T_499, _T_500) node _T_503 = or(_T_502, _T_501) node _T_504 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_505 = and(_T_503, _T_504) else : node _T_506 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_507 = eq(io.rw.addr, UInt<12>(0hb00)) node _T_508 = and(_T_506, _T_507) node _T_509 = andr(UInt<2>(0h2)) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_512 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_513 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_514 = or(_T_511, _T_512) node _T_515 = or(_T_514, _T_513) node _T_516 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_517 = and(_T_515, _T_516) else : node _T_518 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_519 = eq(io.rw.addr, UInt<12>(0hb02)) node _T_520 = and(_T_518, _T_519) node _T_521 = andr(UInt<2>(0h0)) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_524 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_525 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_526 = or(_T_523, _T_524) node _T_527 = or(_T_526, _T_525) node _T_528 = eq(io.rw.addr, UInt<10>(0h323)) node _T_529 = and(_T_527, _T_528) else : node _T_530 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_531 = eq(io.rw.addr, UInt<10>(0h323)) node _T_532 = and(_T_530, _T_531) node _T_533 = andr(UInt<2>(0h2)) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_536 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_537 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_538 = or(_T_535, _T_536) node _T_539 = or(_T_538, _T_537) node _T_540 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_541 = and(_T_539, _T_540) else : node _T_542 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_543 = eq(io.rw.addr, UInt<12>(0hb03)) node _T_544 = and(_T_542, _T_543) node _T_545 = andr(UInt<2>(0h2)) node _T_546 = eq(_T_545, UInt<1>(0h0)) when _T_546 : node _T_547 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_548 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_549 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_550 = or(_T_547, _T_548) node _T_551 = or(_T_550, _T_549) node _T_552 = eq(io.rw.addr, UInt<12>(0hb83)) node _T_553 = and(_T_551, _T_552) else : node _T_554 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_555 = eq(io.rw.addr, UInt<12>(0hb83)) node _T_556 = and(_T_554, _T_555) node _T_557 = andr(UInt<2>(0h3)) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_560 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_561 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_562 = or(_T_559, _T_560) node _T_563 = or(_T_562, _T_561) node _T_564 = eq(io.rw.addr, UInt<12>(0hc83)) node _T_565 = and(_T_563, _T_564) else : node _T_566 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_567 = eq(io.rw.addr, UInt<12>(0hc83)) node _T_568 = and(_T_566, _T_567) node _T_569 = andr(UInt<2>(0h0)) node _T_570 = eq(_T_569, UInt<1>(0h0)) when _T_570 : node _T_571 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_572 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_573 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_574 = or(_T_571, _T_572) node _T_575 = or(_T_574, _T_573) node _T_576 = eq(io.rw.addr, UInt<10>(0h324)) node _T_577 = and(_T_575, _T_576) else : node _T_578 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_579 = eq(io.rw.addr, UInt<10>(0h324)) node _T_580 = and(_T_578, _T_579) node _T_581 = andr(UInt<2>(0h2)) node _T_582 = eq(_T_581, UInt<1>(0h0)) when _T_582 : node _T_583 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_584 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_585 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_586 = or(_T_583, _T_584) node _T_587 = or(_T_586, _T_585) node _T_588 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_589 = and(_T_587, _T_588) else : node _T_590 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_591 = eq(io.rw.addr, UInt<12>(0hb04)) node _T_592 = and(_T_590, _T_591) node _T_593 = andr(UInt<2>(0h2)) node _T_594 = eq(_T_593, UInt<1>(0h0)) when _T_594 : node _T_595 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_596 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_597 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_598 = or(_T_595, _T_596) node _T_599 = or(_T_598, _T_597) node _T_600 = eq(io.rw.addr, UInt<12>(0hb84)) node _T_601 = and(_T_599, _T_600) else : node _T_602 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_603 = eq(io.rw.addr, UInt<12>(0hb84)) node _T_604 = and(_T_602, _T_603) node _T_605 = andr(UInt<2>(0h3)) node _T_606 = eq(_T_605, UInt<1>(0h0)) when _T_606 : node _T_607 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_608 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_609 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_610 = or(_T_607, _T_608) node _T_611 = or(_T_610, _T_609) node _T_612 = eq(io.rw.addr, UInt<12>(0hc84)) node _T_613 = and(_T_611, _T_612) else : node _T_614 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_615 = eq(io.rw.addr, UInt<12>(0hc84)) node _T_616 = and(_T_614, _T_615) node _T_617 = andr(UInt<2>(0h0)) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_620 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_621 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_622 = or(_T_619, _T_620) node _T_623 = or(_T_622, _T_621) node _T_624 = eq(io.rw.addr, UInt<10>(0h325)) node _T_625 = and(_T_623, _T_624) else : node _T_626 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_627 = eq(io.rw.addr, UInt<10>(0h325)) node _T_628 = and(_T_626, _T_627) node _T_629 = andr(UInt<2>(0h2)) node _T_630 = eq(_T_629, UInt<1>(0h0)) when _T_630 : node _T_631 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_632 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_633 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_634 = or(_T_631, _T_632) node _T_635 = or(_T_634, _T_633) node _T_636 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_637 = and(_T_635, _T_636) else : node _T_638 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_639 = eq(io.rw.addr, UInt<12>(0hb05)) node _T_640 = and(_T_638, _T_639) node _T_641 = andr(UInt<2>(0h2)) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_644 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_645 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_646 = or(_T_643, _T_644) node _T_647 = or(_T_646, _T_645) node _T_648 = eq(io.rw.addr, UInt<12>(0hb85)) node _T_649 = and(_T_647, _T_648) else : node _T_650 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_651 = eq(io.rw.addr, UInt<12>(0hb85)) node _T_652 = and(_T_650, _T_651) node _T_653 = andr(UInt<2>(0h3)) node _T_654 = eq(_T_653, UInt<1>(0h0)) when _T_654 : node _T_655 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_656 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_657 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_658 = or(_T_655, _T_656) node _T_659 = or(_T_658, _T_657) node _T_660 = eq(io.rw.addr, UInt<12>(0hc85)) node _T_661 = and(_T_659, _T_660) else : node _T_662 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_663 = eq(io.rw.addr, UInt<12>(0hc85)) node _T_664 = and(_T_662, _T_663) node _T_665 = andr(UInt<2>(0h0)) node _T_666 = eq(_T_665, UInt<1>(0h0)) when _T_666 : node _T_667 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_668 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_669 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_670 = or(_T_667, _T_668) node _T_671 = or(_T_670, _T_669) node _T_672 = eq(io.rw.addr, UInt<10>(0h326)) node _T_673 = and(_T_671, _T_672) else : node _T_674 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_675 = eq(io.rw.addr, UInt<10>(0h326)) node _T_676 = and(_T_674, _T_675) node _T_677 = andr(UInt<2>(0h2)) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_680 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_681 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_682 = or(_T_679, _T_680) node _T_683 = or(_T_682, _T_681) node _T_684 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_685 = and(_T_683, _T_684) else : node _T_686 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_687 = eq(io.rw.addr, UInt<12>(0hb06)) node _T_688 = and(_T_686, _T_687) node _T_689 = andr(UInt<2>(0h2)) node _T_690 = eq(_T_689, UInt<1>(0h0)) when _T_690 : node _T_691 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_692 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_693 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_694 = or(_T_691, _T_692) node _T_695 = or(_T_694, _T_693) node _T_696 = eq(io.rw.addr, UInt<12>(0hb86)) node _T_697 = and(_T_695, _T_696) else : node _T_698 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_699 = eq(io.rw.addr, UInt<12>(0hb86)) node _T_700 = and(_T_698, _T_699) node _T_701 = andr(UInt<2>(0h3)) node _T_702 = eq(_T_701, UInt<1>(0h0)) when _T_702 : node _T_703 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_704 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_705 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_706 = or(_T_703, _T_704) node _T_707 = or(_T_706, _T_705) node _T_708 = eq(io.rw.addr, UInt<12>(0hc86)) node _T_709 = and(_T_707, _T_708) else : node _T_710 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_711 = eq(io.rw.addr, UInt<12>(0hc86)) node _T_712 = and(_T_710, _T_711) node _T_713 = andr(UInt<2>(0h0)) node _T_714 = eq(_T_713, UInt<1>(0h0)) when _T_714 : node _T_715 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_716 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_717 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_718 = or(_T_715, _T_716) node _T_719 = or(_T_718, _T_717) node _T_720 = eq(io.rw.addr, UInt<10>(0h327)) node _T_721 = and(_T_719, _T_720) else : node _T_722 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_723 = eq(io.rw.addr, UInt<10>(0h327)) node _T_724 = and(_T_722, _T_723) node _T_725 = andr(UInt<2>(0h2)) node _T_726 = eq(_T_725, UInt<1>(0h0)) when _T_726 : node _T_727 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_728 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_729 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_730 = or(_T_727, _T_728) node _T_731 = or(_T_730, _T_729) node _T_732 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_733 = and(_T_731, _T_732) else : node _T_734 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_735 = eq(io.rw.addr, UInt<12>(0hb07)) node _T_736 = and(_T_734, _T_735) node _T_737 = andr(UInt<2>(0h2)) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_740 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_741 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_742 = or(_T_739, _T_740) node _T_743 = or(_T_742, _T_741) node _T_744 = eq(io.rw.addr, UInt<12>(0hb87)) node _T_745 = and(_T_743, _T_744) else : node _T_746 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_747 = eq(io.rw.addr, UInt<12>(0hb87)) node _T_748 = and(_T_746, _T_747) node _T_749 = andr(UInt<2>(0h3)) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_752 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_753 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_754 = or(_T_751, _T_752) node _T_755 = or(_T_754, _T_753) node _T_756 = eq(io.rw.addr, UInt<12>(0hc87)) node _T_757 = and(_T_755, _T_756) else : node _T_758 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_759 = eq(io.rw.addr, UInt<12>(0hc87)) node _T_760 = and(_T_758, _T_759) node _T_761 = andr(UInt<2>(0h0)) node _T_762 = eq(_T_761, UInt<1>(0h0)) when _T_762 : node _T_763 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_764 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_765 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_766 = or(_T_763, _T_764) node _T_767 = or(_T_766, _T_765) node _T_768 = eq(io.rw.addr, UInt<10>(0h328)) node _T_769 = and(_T_767, _T_768) else : node _T_770 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_771 = eq(io.rw.addr, UInt<10>(0h328)) node _T_772 = and(_T_770, _T_771) node _T_773 = andr(UInt<2>(0h2)) node _T_774 = eq(_T_773, UInt<1>(0h0)) when _T_774 : node _T_775 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_776 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_777 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_778 = or(_T_775, _T_776) node _T_779 = or(_T_778, _T_777) node _T_780 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_781 = and(_T_779, _T_780) else : node _T_782 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_783 = eq(io.rw.addr, UInt<12>(0hb08)) node _T_784 = and(_T_782, _T_783) node _T_785 = andr(UInt<2>(0h2)) node _T_786 = eq(_T_785, UInt<1>(0h0)) when _T_786 : node _T_787 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_788 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_789 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_790 = or(_T_787, _T_788) node _T_791 = or(_T_790, _T_789) node _T_792 = eq(io.rw.addr, UInt<12>(0hb88)) node _T_793 = and(_T_791, _T_792) else : node _T_794 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_795 = eq(io.rw.addr, UInt<12>(0hb88)) node _T_796 = and(_T_794, _T_795) node _T_797 = andr(UInt<2>(0h3)) node _T_798 = eq(_T_797, UInt<1>(0h0)) when _T_798 : node _T_799 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_800 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_801 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_802 = or(_T_799, _T_800) node _T_803 = or(_T_802, _T_801) node _T_804 = eq(io.rw.addr, UInt<12>(0hc88)) node _T_805 = and(_T_803, _T_804) else : node _T_806 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_807 = eq(io.rw.addr, UInt<12>(0hc88)) node _T_808 = and(_T_806, _T_807) node _T_809 = andr(UInt<2>(0h0)) node _T_810 = eq(_T_809, UInt<1>(0h0)) when _T_810 : node _T_811 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_812 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_813 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_814 = or(_T_811, _T_812) node _T_815 = or(_T_814, _T_813) node _T_816 = eq(io.rw.addr, UInt<10>(0h329)) node _T_817 = and(_T_815, _T_816) else : node _T_818 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_819 = eq(io.rw.addr, UInt<10>(0h329)) node _T_820 = and(_T_818, _T_819) node _T_821 = andr(UInt<2>(0h2)) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_824 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_825 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_826 = or(_T_823, _T_824) node _T_827 = or(_T_826, _T_825) node _T_828 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_829 = and(_T_827, _T_828) else : node _T_830 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_831 = eq(io.rw.addr, UInt<12>(0hb09)) node _T_832 = and(_T_830, _T_831) node _T_833 = andr(UInt<2>(0h2)) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_836 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_837 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_838 = or(_T_835, _T_836) node _T_839 = or(_T_838, _T_837) node _T_840 = eq(io.rw.addr, UInt<12>(0hb89)) node _T_841 = and(_T_839, _T_840) else : node _T_842 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_843 = eq(io.rw.addr, UInt<12>(0hb89)) node _T_844 = and(_T_842, _T_843) node _T_845 = andr(UInt<2>(0h3)) node _T_846 = eq(_T_845, UInt<1>(0h0)) when _T_846 : node _T_847 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_848 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_849 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_850 = or(_T_847, _T_848) node _T_851 = or(_T_850, _T_849) node _T_852 = eq(io.rw.addr, UInt<12>(0hc89)) node _T_853 = and(_T_851, _T_852) else : node _T_854 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_855 = eq(io.rw.addr, UInt<12>(0hc89)) node _T_856 = and(_T_854, _T_855) node _T_857 = andr(UInt<2>(0h0)) node _T_858 = eq(_T_857, UInt<1>(0h0)) when _T_858 : node _T_859 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_860 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_861 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_862 = or(_T_859, _T_860) node _T_863 = or(_T_862, _T_861) node _T_864 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_865 = and(_T_863, _T_864) else : node _T_866 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_867 = eq(io.rw.addr, UInt<10>(0h32a)) node _T_868 = and(_T_866, _T_867) node _T_869 = andr(UInt<2>(0h2)) node _T_870 = eq(_T_869, UInt<1>(0h0)) when _T_870 : node _T_871 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_872 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_873 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_874 = or(_T_871, _T_872) node _T_875 = or(_T_874, _T_873) node _T_876 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_877 = and(_T_875, _T_876) else : node _T_878 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_879 = eq(io.rw.addr, UInt<12>(0hb0a)) node _T_880 = and(_T_878, _T_879) node _T_881 = andr(UInt<2>(0h2)) node _T_882 = eq(_T_881, UInt<1>(0h0)) when _T_882 : node _T_883 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_884 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_885 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_886 = or(_T_883, _T_884) node _T_887 = or(_T_886, _T_885) node _T_888 = eq(io.rw.addr, UInt<12>(0hb8a)) node _T_889 = and(_T_887, _T_888) else : node _T_890 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_891 = eq(io.rw.addr, UInt<12>(0hb8a)) node _T_892 = and(_T_890, _T_891) node _T_893 = andr(UInt<2>(0h3)) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_896 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_897 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_898 = or(_T_895, _T_896) node _T_899 = or(_T_898, _T_897) node _T_900 = eq(io.rw.addr, UInt<12>(0hc8a)) node _T_901 = and(_T_899, _T_900) else : node _T_902 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_903 = eq(io.rw.addr, UInt<12>(0hc8a)) node _T_904 = and(_T_902, _T_903) node _T_905 = andr(UInt<2>(0h0)) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_908 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_909 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_910 = or(_T_907, _T_908) node _T_911 = or(_T_910, _T_909) node _T_912 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_913 = and(_T_911, _T_912) else : node _T_914 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_915 = eq(io.rw.addr, UInt<10>(0h32b)) node _T_916 = and(_T_914, _T_915) node _T_917 = andr(UInt<2>(0h2)) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_920 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_921 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_922 = or(_T_919, _T_920) node _T_923 = or(_T_922, _T_921) node _T_924 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_925 = and(_T_923, _T_924) else : node _T_926 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_927 = eq(io.rw.addr, UInt<12>(0hb0b)) node _T_928 = and(_T_926, _T_927) node _T_929 = andr(UInt<2>(0h2)) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_932 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_933 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_934 = or(_T_931, _T_932) node _T_935 = or(_T_934, _T_933) node _T_936 = eq(io.rw.addr, UInt<12>(0hb8b)) node _T_937 = and(_T_935, _T_936) else : node _T_938 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_939 = eq(io.rw.addr, UInt<12>(0hb8b)) node _T_940 = and(_T_938, _T_939) node _T_941 = andr(UInt<2>(0h3)) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_944 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_945 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_946 = or(_T_943, _T_944) node _T_947 = or(_T_946, _T_945) node _T_948 = eq(io.rw.addr, UInt<12>(0hc8b)) node _T_949 = and(_T_947, _T_948) else : node _T_950 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_951 = eq(io.rw.addr, UInt<12>(0hc8b)) node _T_952 = and(_T_950, _T_951) node _T_953 = andr(UInt<2>(0h0)) node _T_954 = eq(_T_953, UInt<1>(0h0)) when _T_954 : node _T_955 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_956 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_957 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_958 = or(_T_955, _T_956) node _T_959 = or(_T_958, _T_957) node _T_960 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_961 = and(_T_959, _T_960) else : node _T_962 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_963 = eq(io.rw.addr, UInt<10>(0h32c)) node _T_964 = and(_T_962, _T_963) node _T_965 = andr(UInt<2>(0h2)) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_968 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_969 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_970 = or(_T_967, _T_968) node _T_971 = or(_T_970, _T_969) node _T_972 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_973 = and(_T_971, _T_972) else : node _T_974 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_975 = eq(io.rw.addr, UInt<12>(0hb0c)) node _T_976 = and(_T_974, _T_975) node _T_977 = andr(UInt<2>(0h2)) node _T_978 = eq(_T_977, UInt<1>(0h0)) when _T_978 : node _T_979 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_980 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_981 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_982 = or(_T_979, _T_980) node _T_983 = or(_T_982, _T_981) node _T_984 = eq(io.rw.addr, UInt<12>(0hb8c)) node _T_985 = and(_T_983, _T_984) else : node _T_986 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_987 = eq(io.rw.addr, UInt<12>(0hb8c)) node _T_988 = and(_T_986, _T_987) node _T_989 = andr(UInt<2>(0h3)) node _T_990 = eq(_T_989, UInt<1>(0h0)) when _T_990 : node _T_991 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_992 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_993 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_994 = or(_T_991, _T_992) node _T_995 = or(_T_994, _T_993) node _T_996 = eq(io.rw.addr, UInt<12>(0hc8c)) node _T_997 = and(_T_995, _T_996) else : node _T_998 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_999 = eq(io.rw.addr, UInt<12>(0hc8c)) node _T_1000 = and(_T_998, _T_999) node _T_1001 = andr(UInt<2>(0h0)) node _T_1002 = eq(_T_1001, UInt<1>(0h0)) when _T_1002 : node _T_1003 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1004 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1005 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1006 = or(_T_1003, _T_1004) node _T_1007 = or(_T_1006, _T_1005) node _T_1008 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_1009 = and(_T_1007, _T_1008) else : node _T_1010 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1011 = eq(io.rw.addr, UInt<10>(0h32d)) node _T_1012 = and(_T_1010, _T_1011) node _T_1013 = andr(UInt<2>(0h2)) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1016 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1017 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1018 = or(_T_1015, _T_1016) node _T_1019 = or(_T_1018, _T_1017) node _T_1020 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_1021 = and(_T_1019, _T_1020) else : node _T_1022 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1023 = eq(io.rw.addr, UInt<12>(0hb0d)) node _T_1024 = and(_T_1022, _T_1023) node _T_1025 = andr(UInt<2>(0h2)) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1028 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1029 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1030 = or(_T_1027, _T_1028) node _T_1031 = or(_T_1030, _T_1029) node _T_1032 = eq(io.rw.addr, UInt<12>(0hb8d)) node _T_1033 = and(_T_1031, _T_1032) else : node _T_1034 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1035 = eq(io.rw.addr, UInt<12>(0hb8d)) node _T_1036 = and(_T_1034, _T_1035) node _T_1037 = andr(UInt<2>(0h3)) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1040 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1041 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1042 = or(_T_1039, _T_1040) node _T_1043 = or(_T_1042, _T_1041) node _T_1044 = eq(io.rw.addr, UInt<12>(0hc8d)) node _T_1045 = and(_T_1043, _T_1044) else : node _T_1046 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1047 = eq(io.rw.addr, UInt<12>(0hc8d)) node _T_1048 = and(_T_1046, _T_1047) node _T_1049 = andr(UInt<2>(0h0)) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1052 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1053 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1054 = or(_T_1051, _T_1052) node _T_1055 = or(_T_1054, _T_1053) node _T_1056 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_1057 = and(_T_1055, _T_1056) else : node _T_1058 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1059 = eq(io.rw.addr, UInt<10>(0h32e)) node _T_1060 = and(_T_1058, _T_1059) node _T_1061 = andr(UInt<2>(0h2)) node _T_1062 = eq(_T_1061, UInt<1>(0h0)) when _T_1062 : node _T_1063 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1064 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1065 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1066 = or(_T_1063, _T_1064) node _T_1067 = or(_T_1066, _T_1065) node _T_1068 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_1069 = and(_T_1067, _T_1068) else : node _T_1070 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1071 = eq(io.rw.addr, UInt<12>(0hb0e)) node _T_1072 = and(_T_1070, _T_1071) node _T_1073 = andr(UInt<2>(0h2)) node _T_1074 = eq(_T_1073, UInt<1>(0h0)) when _T_1074 : node _T_1075 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1076 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1077 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1078 = or(_T_1075, _T_1076) node _T_1079 = or(_T_1078, _T_1077) node _T_1080 = eq(io.rw.addr, UInt<12>(0hb8e)) node _T_1081 = and(_T_1079, _T_1080) else : node _T_1082 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1083 = eq(io.rw.addr, UInt<12>(0hb8e)) node _T_1084 = and(_T_1082, _T_1083) node _T_1085 = andr(UInt<2>(0h3)) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1088 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1089 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1090 = or(_T_1087, _T_1088) node _T_1091 = or(_T_1090, _T_1089) node _T_1092 = eq(io.rw.addr, UInt<12>(0hc8e)) node _T_1093 = and(_T_1091, _T_1092) else : node _T_1094 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1095 = eq(io.rw.addr, UInt<12>(0hc8e)) node _T_1096 = and(_T_1094, _T_1095) node _T_1097 = andr(UInt<2>(0h0)) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1100 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1101 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1102 = or(_T_1099, _T_1100) node _T_1103 = or(_T_1102, _T_1101) node _T_1104 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_1105 = and(_T_1103, _T_1104) else : node _T_1106 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1107 = eq(io.rw.addr, UInt<10>(0h32f)) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = andr(UInt<2>(0h2)) node _T_1110 = eq(_T_1109, UInt<1>(0h0)) when _T_1110 : node _T_1111 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1112 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1113 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1114 = or(_T_1111, _T_1112) node _T_1115 = or(_T_1114, _T_1113) node _T_1116 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_1117 = and(_T_1115, _T_1116) else : node _T_1118 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1119 = eq(io.rw.addr, UInt<12>(0hb0f)) node _T_1120 = and(_T_1118, _T_1119) node _T_1121 = andr(UInt<2>(0h2)) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1124 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1125 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1126 = or(_T_1123, _T_1124) node _T_1127 = or(_T_1126, _T_1125) node _T_1128 = eq(io.rw.addr, UInt<12>(0hb8f)) node _T_1129 = and(_T_1127, _T_1128) else : node _T_1130 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1131 = eq(io.rw.addr, UInt<12>(0hb8f)) node _T_1132 = and(_T_1130, _T_1131) node _T_1133 = andr(UInt<2>(0h3)) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1136 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1137 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1138 = or(_T_1135, _T_1136) node _T_1139 = or(_T_1138, _T_1137) node _T_1140 = eq(io.rw.addr, UInt<12>(0hc8f)) node _T_1141 = and(_T_1139, _T_1140) else : node _T_1142 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1143 = eq(io.rw.addr, UInt<12>(0hc8f)) node _T_1144 = and(_T_1142, _T_1143) node _T_1145 = andr(UInt<2>(0h0)) node _T_1146 = eq(_T_1145, UInt<1>(0h0)) when _T_1146 : node _T_1147 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1148 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1149 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1150 = or(_T_1147, _T_1148) node _T_1151 = or(_T_1150, _T_1149) node _T_1152 = eq(io.rw.addr, UInt<10>(0h330)) node _T_1153 = and(_T_1151, _T_1152) else : node _T_1154 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1155 = eq(io.rw.addr, UInt<10>(0h330)) node _T_1156 = and(_T_1154, _T_1155) node _T_1157 = andr(UInt<2>(0h2)) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1160 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1161 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1162 = or(_T_1159, _T_1160) node _T_1163 = or(_T_1162, _T_1161) node _T_1164 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_1165 = and(_T_1163, _T_1164) else : node _T_1166 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1167 = eq(io.rw.addr, UInt<12>(0hb10)) node _T_1168 = and(_T_1166, _T_1167) node _T_1169 = andr(UInt<2>(0h2)) node _T_1170 = eq(_T_1169, UInt<1>(0h0)) when _T_1170 : node _T_1171 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1172 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1173 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1174 = or(_T_1171, _T_1172) node _T_1175 = or(_T_1174, _T_1173) node _T_1176 = eq(io.rw.addr, UInt<12>(0hb90)) node _T_1177 = and(_T_1175, _T_1176) else : node _T_1178 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1179 = eq(io.rw.addr, UInt<12>(0hb90)) node _T_1180 = and(_T_1178, _T_1179) node _T_1181 = andr(UInt<2>(0h3)) node _T_1182 = eq(_T_1181, UInt<1>(0h0)) when _T_1182 : node _T_1183 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1184 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1185 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1186 = or(_T_1183, _T_1184) node _T_1187 = or(_T_1186, _T_1185) node _T_1188 = eq(io.rw.addr, UInt<12>(0hc90)) node _T_1189 = and(_T_1187, _T_1188) else : node _T_1190 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1191 = eq(io.rw.addr, UInt<12>(0hc90)) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = andr(UInt<2>(0h0)) node _T_1194 = eq(_T_1193, UInt<1>(0h0)) when _T_1194 : node _T_1195 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1196 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1197 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1198 = or(_T_1195, _T_1196) node _T_1199 = or(_T_1198, _T_1197) node _T_1200 = eq(io.rw.addr, UInt<10>(0h331)) node _T_1201 = and(_T_1199, _T_1200) else : node _T_1202 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1203 = eq(io.rw.addr, UInt<10>(0h331)) node _T_1204 = and(_T_1202, _T_1203) node _T_1205 = andr(UInt<2>(0h2)) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1208 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1209 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1210 = or(_T_1207, _T_1208) node _T_1211 = or(_T_1210, _T_1209) node _T_1212 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_1213 = and(_T_1211, _T_1212) else : node _T_1214 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1215 = eq(io.rw.addr, UInt<12>(0hb11)) node _T_1216 = and(_T_1214, _T_1215) node _T_1217 = andr(UInt<2>(0h2)) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1220 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1221 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1222 = or(_T_1219, _T_1220) node _T_1223 = or(_T_1222, _T_1221) node _T_1224 = eq(io.rw.addr, UInt<12>(0hb91)) node _T_1225 = and(_T_1223, _T_1224) else : node _T_1226 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1227 = eq(io.rw.addr, UInt<12>(0hb91)) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = andr(UInt<2>(0h3)) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1232 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1233 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1234 = or(_T_1231, _T_1232) node _T_1235 = or(_T_1234, _T_1233) node _T_1236 = eq(io.rw.addr, UInt<12>(0hc91)) node _T_1237 = and(_T_1235, _T_1236) else : node _T_1238 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1239 = eq(io.rw.addr, UInt<12>(0hc91)) node _T_1240 = and(_T_1238, _T_1239) node _T_1241 = andr(UInt<2>(0h0)) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1244 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1245 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1246 = or(_T_1243, _T_1244) node _T_1247 = or(_T_1246, _T_1245) node _T_1248 = eq(io.rw.addr, UInt<10>(0h332)) node _T_1249 = and(_T_1247, _T_1248) else : node _T_1250 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1251 = eq(io.rw.addr, UInt<10>(0h332)) node _T_1252 = and(_T_1250, _T_1251) node _T_1253 = andr(UInt<2>(0h2)) node _T_1254 = eq(_T_1253, UInt<1>(0h0)) when _T_1254 : node _T_1255 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1256 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1257 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1258 = or(_T_1255, _T_1256) node _T_1259 = or(_T_1258, _T_1257) node _T_1260 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_1261 = and(_T_1259, _T_1260) else : node _T_1262 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1263 = eq(io.rw.addr, UInt<12>(0hb12)) node _T_1264 = and(_T_1262, _T_1263) node _T_1265 = andr(UInt<2>(0h2)) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1268 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1269 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1270 = or(_T_1267, _T_1268) node _T_1271 = or(_T_1270, _T_1269) node _T_1272 = eq(io.rw.addr, UInt<12>(0hb92)) node _T_1273 = and(_T_1271, _T_1272) else : node _T_1274 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1275 = eq(io.rw.addr, UInt<12>(0hb92)) node _T_1276 = and(_T_1274, _T_1275) node _T_1277 = andr(UInt<2>(0h3)) node _T_1278 = eq(_T_1277, UInt<1>(0h0)) when _T_1278 : node _T_1279 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1280 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1281 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1282 = or(_T_1279, _T_1280) node _T_1283 = or(_T_1282, _T_1281) node _T_1284 = eq(io.rw.addr, UInt<12>(0hc92)) node _T_1285 = and(_T_1283, _T_1284) else : node _T_1286 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1287 = eq(io.rw.addr, UInt<12>(0hc92)) node _T_1288 = and(_T_1286, _T_1287) node _T_1289 = andr(UInt<2>(0h0)) node _T_1290 = eq(_T_1289, UInt<1>(0h0)) when _T_1290 : node _T_1291 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1292 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1293 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1294 = or(_T_1291, _T_1292) node _T_1295 = or(_T_1294, _T_1293) node _T_1296 = eq(io.rw.addr, UInt<10>(0h333)) node _T_1297 = and(_T_1295, _T_1296) else : node _T_1298 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1299 = eq(io.rw.addr, UInt<10>(0h333)) node _T_1300 = and(_T_1298, _T_1299) node _T_1301 = andr(UInt<2>(0h2)) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1304 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1305 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1306 = or(_T_1303, _T_1304) node _T_1307 = or(_T_1306, _T_1305) node _T_1308 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_1309 = and(_T_1307, _T_1308) else : node _T_1310 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1311 = eq(io.rw.addr, UInt<12>(0hb13)) node _T_1312 = and(_T_1310, _T_1311) node _T_1313 = andr(UInt<2>(0h2)) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1316 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1317 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1318 = or(_T_1315, _T_1316) node _T_1319 = or(_T_1318, _T_1317) node _T_1320 = eq(io.rw.addr, UInt<12>(0hb93)) node _T_1321 = and(_T_1319, _T_1320) else : node _T_1322 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1323 = eq(io.rw.addr, UInt<12>(0hb93)) node _T_1324 = and(_T_1322, _T_1323) node _T_1325 = andr(UInt<2>(0h3)) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1328 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1329 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1330 = or(_T_1327, _T_1328) node _T_1331 = or(_T_1330, _T_1329) node _T_1332 = eq(io.rw.addr, UInt<12>(0hc93)) node _T_1333 = and(_T_1331, _T_1332) else : node _T_1334 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1335 = eq(io.rw.addr, UInt<12>(0hc93)) node _T_1336 = and(_T_1334, _T_1335) node _T_1337 = andr(UInt<2>(0h0)) node _T_1338 = eq(_T_1337, UInt<1>(0h0)) when _T_1338 : node _T_1339 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1340 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1341 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1342 = or(_T_1339, _T_1340) node _T_1343 = or(_T_1342, _T_1341) node _T_1344 = eq(io.rw.addr, UInt<10>(0h334)) node _T_1345 = and(_T_1343, _T_1344) else : node _T_1346 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1347 = eq(io.rw.addr, UInt<10>(0h334)) node _T_1348 = and(_T_1346, _T_1347) node _T_1349 = andr(UInt<2>(0h2)) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1352 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1353 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1354 = or(_T_1351, _T_1352) node _T_1355 = or(_T_1354, _T_1353) node _T_1356 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_1357 = and(_T_1355, _T_1356) else : node _T_1358 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1359 = eq(io.rw.addr, UInt<12>(0hb14)) node _T_1360 = and(_T_1358, _T_1359) node _T_1361 = andr(UInt<2>(0h2)) node _T_1362 = eq(_T_1361, UInt<1>(0h0)) when _T_1362 : node _T_1363 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1364 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1365 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1366 = or(_T_1363, _T_1364) node _T_1367 = or(_T_1366, _T_1365) node _T_1368 = eq(io.rw.addr, UInt<12>(0hb94)) node _T_1369 = and(_T_1367, _T_1368) else : node _T_1370 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1371 = eq(io.rw.addr, UInt<12>(0hb94)) node _T_1372 = and(_T_1370, _T_1371) node _T_1373 = andr(UInt<2>(0h3)) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1376 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1377 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1378 = or(_T_1375, _T_1376) node _T_1379 = or(_T_1378, _T_1377) node _T_1380 = eq(io.rw.addr, UInt<12>(0hc94)) node _T_1381 = and(_T_1379, _T_1380) else : node _T_1382 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1383 = eq(io.rw.addr, UInt<12>(0hc94)) node _T_1384 = and(_T_1382, _T_1383) node _T_1385 = andr(UInt<2>(0h0)) node _T_1386 = eq(_T_1385, UInt<1>(0h0)) when _T_1386 : node _T_1387 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1388 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1389 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1390 = or(_T_1387, _T_1388) node _T_1391 = or(_T_1390, _T_1389) node _T_1392 = eq(io.rw.addr, UInt<10>(0h335)) node _T_1393 = and(_T_1391, _T_1392) else : node _T_1394 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1395 = eq(io.rw.addr, UInt<10>(0h335)) node _T_1396 = and(_T_1394, _T_1395) node _T_1397 = andr(UInt<2>(0h2)) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) when _T_1398 : node _T_1399 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1400 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1401 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1402 = or(_T_1399, _T_1400) node _T_1403 = or(_T_1402, _T_1401) node _T_1404 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_1405 = and(_T_1403, _T_1404) else : node _T_1406 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1407 = eq(io.rw.addr, UInt<12>(0hb15)) node _T_1408 = and(_T_1406, _T_1407) node _T_1409 = andr(UInt<2>(0h2)) node _T_1410 = eq(_T_1409, UInt<1>(0h0)) when _T_1410 : node _T_1411 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1412 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1413 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1414 = or(_T_1411, _T_1412) node _T_1415 = or(_T_1414, _T_1413) node _T_1416 = eq(io.rw.addr, UInt<12>(0hb95)) node _T_1417 = and(_T_1415, _T_1416) else : node _T_1418 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1419 = eq(io.rw.addr, UInt<12>(0hb95)) node _T_1420 = and(_T_1418, _T_1419) node _T_1421 = andr(UInt<2>(0h3)) node _T_1422 = eq(_T_1421, UInt<1>(0h0)) when _T_1422 : node _T_1423 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1424 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1425 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1426 = or(_T_1423, _T_1424) node _T_1427 = or(_T_1426, _T_1425) node _T_1428 = eq(io.rw.addr, UInt<12>(0hc95)) node _T_1429 = and(_T_1427, _T_1428) else : node _T_1430 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1431 = eq(io.rw.addr, UInt<12>(0hc95)) node _T_1432 = and(_T_1430, _T_1431) node _T_1433 = andr(UInt<2>(0h0)) node _T_1434 = eq(_T_1433, UInt<1>(0h0)) when _T_1434 : node _T_1435 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1436 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1437 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1438 = or(_T_1435, _T_1436) node _T_1439 = or(_T_1438, _T_1437) node _T_1440 = eq(io.rw.addr, UInt<10>(0h336)) node _T_1441 = and(_T_1439, _T_1440) else : node _T_1442 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1443 = eq(io.rw.addr, UInt<10>(0h336)) node _T_1444 = and(_T_1442, _T_1443) node _T_1445 = andr(UInt<2>(0h2)) node _T_1446 = eq(_T_1445, UInt<1>(0h0)) when _T_1446 : node _T_1447 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1448 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1449 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1450 = or(_T_1447, _T_1448) node _T_1451 = or(_T_1450, _T_1449) node _T_1452 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1453 = and(_T_1451, _T_1452) else : node _T_1454 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1455 = eq(io.rw.addr, UInt<12>(0hb16)) node _T_1456 = and(_T_1454, _T_1455) node _T_1457 = andr(UInt<2>(0h2)) node _T_1458 = eq(_T_1457, UInt<1>(0h0)) when _T_1458 : node _T_1459 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1460 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1461 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1462 = or(_T_1459, _T_1460) node _T_1463 = or(_T_1462, _T_1461) node _T_1464 = eq(io.rw.addr, UInt<12>(0hb96)) node _T_1465 = and(_T_1463, _T_1464) else : node _T_1466 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1467 = eq(io.rw.addr, UInt<12>(0hb96)) node _T_1468 = and(_T_1466, _T_1467) node _T_1469 = andr(UInt<2>(0h3)) node _T_1470 = eq(_T_1469, UInt<1>(0h0)) when _T_1470 : node _T_1471 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1472 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1473 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1474 = or(_T_1471, _T_1472) node _T_1475 = or(_T_1474, _T_1473) node _T_1476 = eq(io.rw.addr, UInt<12>(0hc96)) node _T_1477 = and(_T_1475, _T_1476) else : node _T_1478 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1479 = eq(io.rw.addr, UInt<12>(0hc96)) node _T_1480 = and(_T_1478, _T_1479) node _T_1481 = andr(UInt<2>(0h0)) node _T_1482 = eq(_T_1481, UInt<1>(0h0)) when _T_1482 : node _T_1483 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1484 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1485 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1486 = or(_T_1483, _T_1484) node _T_1487 = or(_T_1486, _T_1485) node _T_1488 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1489 = and(_T_1487, _T_1488) else : node _T_1490 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1491 = eq(io.rw.addr, UInt<10>(0h337)) node _T_1492 = and(_T_1490, _T_1491) node _T_1493 = andr(UInt<2>(0h2)) node _T_1494 = eq(_T_1493, UInt<1>(0h0)) when _T_1494 : node _T_1495 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1496 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1497 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1498 = or(_T_1495, _T_1496) node _T_1499 = or(_T_1498, _T_1497) node _T_1500 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1501 = and(_T_1499, _T_1500) else : node _T_1502 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1503 = eq(io.rw.addr, UInt<12>(0hb17)) node _T_1504 = and(_T_1502, _T_1503) node _T_1505 = andr(UInt<2>(0h2)) node _T_1506 = eq(_T_1505, UInt<1>(0h0)) when _T_1506 : node _T_1507 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1508 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1509 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1510 = or(_T_1507, _T_1508) node _T_1511 = or(_T_1510, _T_1509) node _T_1512 = eq(io.rw.addr, UInt<12>(0hb97)) node _T_1513 = and(_T_1511, _T_1512) else : node _T_1514 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1515 = eq(io.rw.addr, UInt<12>(0hb97)) node _T_1516 = and(_T_1514, _T_1515) node _T_1517 = andr(UInt<2>(0h3)) node _T_1518 = eq(_T_1517, UInt<1>(0h0)) when _T_1518 : node _T_1519 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1520 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1521 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1522 = or(_T_1519, _T_1520) node _T_1523 = or(_T_1522, _T_1521) node _T_1524 = eq(io.rw.addr, UInt<12>(0hc97)) node _T_1525 = and(_T_1523, _T_1524) else : node _T_1526 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1527 = eq(io.rw.addr, UInt<12>(0hc97)) node _T_1528 = and(_T_1526, _T_1527) node _T_1529 = andr(UInt<2>(0h0)) node _T_1530 = eq(_T_1529, UInt<1>(0h0)) when _T_1530 : node _T_1531 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1532 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1533 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1534 = or(_T_1531, _T_1532) node _T_1535 = or(_T_1534, _T_1533) node _T_1536 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1537 = and(_T_1535, _T_1536) else : node _T_1538 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1539 = eq(io.rw.addr, UInt<10>(0h338)) node _T_1540 = and(_T_1538, _T_1539) node _T_1541 = andr(UInt<2>(0h2)) node _T_1542 = eq(_T_1541, UInt<1>(0h0)) when _T_1542 : node _T_1543 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1544 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1545 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1546 = or(_T_1543, _T_1544) node _T_1547 = or(_T_1546, _T_1545) node _T_1548 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1549 = and(_T_1547, _T_1548) else : node _T_1550 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1551 = eq(io.rw.addr, UInt<12>(0hb18)) node _T_1552 = and(_T_1550, _T_1551) node _T_1553 = andr(UInt<2>(0h2)) node _T_1554 = eq(_T_1553, UInt<1>(0h0)) when _T_1554 : node _T_1555 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1556 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1557 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1558 = or(_T_1555, _T_1556) node _T_1559 = or(_T_1558, _T_1557) node _T_1560 = eq(io.rw.addr, UInt<12>(0hb98)) node _T_1561 = and(_T_1559, _T_1560) else : node _T_1562 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1563 = eq(io.rw.addr, UInt<12>(0hb98)) node _T_1564 = and(_T_1562, _T_1563) node _T_1565 = andr(UInt<2>(0h3)) node _T_1566 = eq(_T_1565, UInt<1>(0h0)) when _T_1566 : node _T_1567 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1568 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1569 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1570 = or(_T_1567, _T_1568) node _T_1571 = or(_T_1570, _T_1569) node _T_1572 = eq(io.rw.addr, UInt<12>(0hc98)) node _T_1573 = and(_T_1571, _T_1572) else : node _T_1574 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1575 = eq(io.rw.addr, UInt<12>(0hc98)) node _T_1576 = and(_T_1574, _T_1575) node _T_1577 = andr(UInt<2>(0h0)) node _T_1578 = eq(_T_1577, UInt<1>(0h0)) when _T_1578 : node _T_1579 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1580 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1581 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1582 = or(_T_1579, _T_1580) node _T_1583 = or(_T_1582, _T_1581) node _T_1584 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1585 = and(_T_1583, _T_1584) else : node _T_1586 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1587 = eq(io.rw.addr, UInt<10>(0h339)) node _T_1588 = and(_T_1586, _T_1587) node _T_1589 = andr(UInt<2>(0h2)) node _T_1590 = eq(_T_1589, UInt<1>(0h0)) when _T_1590 : node _T_1591 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1592 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1593 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1594 = or(_T_1591, _T_1592) node _T_1595 = or(_T_1594, _T_1593) node _T_1596 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1597 = and(_T_1595, _T_1596) else : node _T_1598 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1599 = eq(io.rw.addr, UInt<12>(0hb19)) node _T_1600 = and(_T_1598, _T_1599) node _T_1601 = andr(UInt<2>(0h2)) node _T_1602 = eq(_T_1601, UInt<1>(0h0)) when _T_1602 : node _T_1603 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1604 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1605 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1606 = or(_T_1603, _T_1604) node _T_1607 = or(_T_1606, _T_1605) node _T_1608 = eq(io.rw.addr, UInt<12>(0hb99)) node _T_1609 = and(_T_1607, _T_1608) else : node _T_1610 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1611 = eq(io.rw.addr, UInt<12>(0hb99)) node _T_1612 = and(_T_1610, _T_1611) node _T_1613 = andr(UInt<2>(0h3)) node _T_1614 = eq(_T_1613, UInt<1>(0h0)) when _T_1614 : node _T_1615 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1616 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1617 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1618 = or(_T_1615, _T_1616) node _T_1619 = or(_T_1618, _T_1617) node _T_1620 = eq(io.rw.addr, UInt<12>(0hc99)) node _T_1621 = and(_T_1619, _T_1620) else : node _T_1622 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1623 = eq(io.rw.addr, UInt<12>(0hc99)) node _T_1624 = and(_T_1622, _T_1623) node _T_1625 = andr(UInt<2>(0h0)) node _T_1626 = eq(_T_1625, UInt<1>(0h0)) when _T_1626 : node _T_1627 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1628 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1629 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1630 = or(_T_1627, _T_1628) node _T_1631 = or(_T_1630, _T_1629) node _T_1632 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1633 = and(_T_1631, _T_1632) else : node _T_1634 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1635 = eq(io.rw.addr, UInt<10>(0h33a)) node _T_1636 = and(_T_1634, _T_1635) node _T_1637 = andr(UInt<2>(0h2)) node _T_1638 = eq(_T_1637, UInt<1>(0h0)) when _T_1638 : node _T_1639 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1640 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1641 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1642 = or(_T_1639, _T_1640) node _T_1643 = or(_T_1642, _T_1641) node _T_1644 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1645 = and(_T_1643, _T_1644) else : node _T_1646 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1647 = eq(io.rw.addr, UInt<12>(0hb1a)) node _T_1648 = and(_T_1646, _T_1647) node _T_1649 = andr(UInt<2>(0h2)) node _T_1650 = eq(_T_1649, UInt<1>(0h0)) when _T_1650 : node _T_1651 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1652 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1653 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1654 = or(_T_1651, _T_1652) node _T_1655 = or(_T_1654, _T_1653) node _T_1656 = eq(io.rw.addr, UInt<12>(0hb9a)) node _T_1657 = and(_T_1655, _T_1656) else : node _T_1658 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1659 = eq(io.rw.addr, UInt<12>(0hb9a)) node _T_1660 = and(_T_1658, _T_1659) node _T_1661 = andr(UInt<2>(0h3)) node _T_1662 = eq(_T_1661, UInt<1>(0h0)) when _T_1662 : node _T_1663 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1664 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1665 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1666 = or(_T_1663, _T_1664) node _T_1667 = or(_T_1666, _T_1665) node _T_1668 = eq(io.rw.addr, UInt<12>(0hc9a)) node _T_1669 = and(_T_1667, _T_1668) else : node _T_1670 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1671 = eq(io.rw.addr, UInt<12>(0hc9a)) node _T_1672 = and(_T_1670, _T_1671) node _T_1673 = andr(UInt<2>(0h0)) node _T_1674 = eq(_T_1673, UInt<1>(0h0)) when _T_1674 : node _T_1675 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1676 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1677 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1678 = or(_T_1675, _T_1676) node _T_1679 = or(_T_1678, _T_1677) node _T_1680 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1681 = and(_T_1679, _T_1680) else : node _T_1682 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1683 = eq(io.rw.addr, UInt<10>(0h33b)) node _T_1684 = and(_T_1682, _T_1683) node _T_1685 = andr(UInt<2>(0h2)) node _T_1686 = eq(_T_1685, UInt<1>(0h0)) when _T_1686 : node _T_1687 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1688 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1689 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1690 = or(_T_1687, _T_1688) node _T_1691 = or(_T_1690, _T_1689) node _T_1692 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1693 = and(_T_1691, _T_1692) else : node _T_1694 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1695 = eq(io.rw.addr, UInt<12>(0hb1b)) node _T_1696 = and(_T_1694, _T_1695) node _T_1697 = andr(UInt<2>(0h2)) node _T_1698 = eq(_T_1697, UInt<1>(0h0)) when _T_1698 : node _T_1699 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1700 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1701 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1702 = or(_T_1699, _T_1700) node _T_1703 = or(_T_1702, _T_1701) node _T_1704 = eq(io.rw.addr, UInt<12>(0hb9b)) node _T_1705 = and(_T_1703, _T_1704) else : node _T_1706 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1707 = eq(io.rw.addr, UInt<12>(0hb9b)) node _T_1708 = and(_T_1706, _T_1707) node _T_1709 = andr(UInt<2>(0h3)) node _T_1710 = eq(_T_1709, UInt<1>(0h0)) when _T_1710 : node _T_1711 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1712 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1713 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1714 = or(_T_1711, _T_1712) node _T_1715 = or(_T_1714, _T_1713) node _T_1716 = eq(io.rw.addr, UInt<12>(0hc9b)) node _T_1717 = and(_T_1715, _T_1716) else : node _T_1718 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1719 = eq(io.rw.addr, UInt<12>(0hc9b)) node _T_1720 = and(_T_1718, _T_1719) node _T_1721 = andr(UInt<2>(0h0)) node _T_1722 = eq(_T_1721, UInt<1>(0h0)) when _T_1722 : node _T_1723 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1724 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1725 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1726 = or(_T_1723, _T_1724) node _T_1727 = or(_T_1726, _T_1725) node _T_1728 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1729 = and(_T_1727, _T_1728) else : node _T_1730 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1731 = eq(io.rw.addr, UInt<10>(0h33c)) node _T_1732 = and(_T_1730, _T_1731) node _T_1733 = andr(UInt<2>(0h2)) node _T_1734 = eq(_T_1733, UInt<1>(0h0)) when _T_1734 : node _T_1735 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1736 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1737 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1738 = or(_T_1735, _T_1736) node _T_1739 = or(_T_1738, _T_1737) node _T_1740 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1741 = and(_T_1739, _T_1740) else : node _T_1742 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1743 = eq(io.rw.addr, UInt<12>(0hb1c)) node _T_1744 = and(_T_1742, _T_1743) node _T_1745 = andr(UInt<2>(0h2)) node _T_1746 = eq(_T_1745, UInt<1>(0h0)) when _T_1746 : node _T_1747 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1748 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1749 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1750 = or(_T_1747, _T_1748) node _T_1751 = or(_T_1750, _T_1749) node _T_1752 = eq(io.rw.addr, UInt<12>(0hb9c)) node _T_1753 = and(_T_1751, _T_1752) else : node _T_1754 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1755 = eq(io.rw.addr, UInt<12>(0hb9c)) node _T_1756 = and(_T_1754, _T_1755) node _T_1757 = andr(UInt<2>(0h3)) node _T_1758 = eq(_T_1757, UInt<1>(0h0)) when _T_1758 : node _T_1759 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1760 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1761 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1762 = or(_T_1759, _T_1760) node _T_1763 = or(_T_1762, _T_1761) node _T_1764 = eq(io.rw.addr, UInt<12>(0hc9c)) node _T_1765 = and(_T_1763, _T_1764) else : node _T_1766 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1767 = eq(io.rw.addr, UInt<12>(0hc9c)) node _T_1768 = and(_T_1766, _T_1767) node _T_1769 = andr(UInt<2>(0h0)) node _T_1770 = eq(_T_1769, UInt<1>(0h0)) when _T_1770 : node _T_1771 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1772 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1773 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1774 = or(_T_1771, _T_1772) node _T_1775 = or(_T_1774, _T_1773) node _T_1776 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1777 = and(_T_1775, _T_1776) else : node _T_1778 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1779 = eq(io.rw.addr, UInt<10>(0h33d)) node _T_1780 = and(_T_1778, _T_1779) node _T_1781 = andr(UInt<2>(0h2)) node _T_1782 = eq(_T_1781, UInt<1>(0h0)) when _T_1782 : node _T_1783 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1784 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1785 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1786 = or(_T_1783, _T_1784) node _T_1787 = or(_T_1786, _T_1785) node _T_1788 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1789 = and(_T_1787, _T_1788) else : node _T_1790 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1791 = eq(io.rw.addr, UInt<12>(0hb1d)) node _T_1792 = and(_T_1790, _T_1791) node _T_1793 = andr(UInt<2>(0h2)) node _T_1794 = eq(_T_1793, UInt<1>(0h0)) when _T_1794 : node _T_1795 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1796 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1797 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1798 = or(_T_1795, _T_1796) node _T_1799 = or(_T_1798, _T_1797) node _T_1800 = eq(io.rw.addr, UInt<12>(0hb9d)) node _T_1801 = and(_T_1799, _T_1800) else : node _T_1802 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1803 = eq(io.rw.addr, UInt<12>(0hb9d)) node _T_1804 = and(_T_1802, _T_1803) node _T_1805 = andr(UInt<2>(0h3)) node _T_1806 = eq(_T_1805, UInt<1>(0h0)) when _T_1806 : node _T_1807 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1808 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1809 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1810 = or(_T_1807, _T_1808) node _T_1811 = or(_T_1810, _T_1809) node _T_1812 = eq(io.rw.addr, UInt<12>(0hc9d)) node _T_1813 = and(_T_1811, _T_1812) else : node _T_1814 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1815 = eq(io.rw.addr, UInt<12>(0hc9d)) node _T_1816 = and(_T_1814, _T_1815) node _T_1817 = andr(UInt<2>(0h0)) node _T_1818 = eq(_T_1817, UInt<1>(0h0)) when _T_1818 : node _T_1819 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1820 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1821 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1822 = or(_T_1819, _T_1820) node _T_1823 = or(_T_1822, _T_1821) node _T_1824 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1825 = and(_T_1823, _T_1824) else : node _T_1826 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1827 = eq(io.rw.addr, UInt<10>(0h33e)) node _T_1828 = and(_T_1826, _T_1827) node _T_1829 = andr(UInt<2>(0h2)) node _T_1830 = eq(_T_1829, UInt<1>(0h0)) when _T_1830 : node _T_1831 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1832 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1833 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1834 = or(_T_1831, _T_1832) node _T_1835 = or(_T_1834, _T_1833) node _T_1836 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1837 = and(_T_1835, _T_1836) else : node _T_1838 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1839 = eq(io.rw.addr, UInt<12>(0hb1e)) node _T_1840 = and(_T_1838, _T_1839) node _T_1841 = andr(UInt<2>(0h2)) node _T_1842 = eq(_T_1841, UInt<1>(0h0)) when _T_1842 : node _T_1843 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1844 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1845 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1846 = or(_T_1843, _T_1844) node _T_1847 = or(_T_1846, _T_1845) node _T_1848 = eq(io.rw.addr, UInt<12>(0hb9e)) node _T_1849 = and(_T_1847, _T_1848) else : node _T_1850 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1851 = eq(io.rw.addr, UInt<12>(0hb9e)) node _T_1852 = and(_T_1850, _T_1851) node _T_1853 = andr(UInt<2>(0h3)) node _T_1854 = eq(_T_1853, UInt<1>(0h0)) when _T_1854 : node _T_1855 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1856 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1857 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1858 = or(_T_1855, _T_1856) node _T_1859 = or(_T_1858, _T_1857) node _T_1860 = eq(io.rw.addr, UInt<12>(0hc9e)) node _T_1861 = and(_T_1859, _T_1860) else : node _T_1862 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1863 = eq(io.rw.addr, UInt<12>(0hc9e)) node _T_1864 = and(_T_1862, _T_1863) node _T_1865 = andr(UInt<2>(0h0)) node _T_1866 = eq(_T_1865, UInt<1>(0h0)) when _T_1866 : node _T_1867 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1868 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1869 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1870 = or(_T_1867, _T_1868) node _T_1871 = or(_T_1870, _T_1869) node _T_1872 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1873 = and(_T_1871, _T_1872) else : node _T_1874 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1875 = eq(io.rw.addr, UInt<10>(0h33f)) node _T_1876 = and(_T_1874, _T_1875) node _T_1877 = andr(UInt<2>(0h2)) node _T_1878 = eq(_T_1877, UInt<1>(0h0)) when _T_1878 : node _T_1879 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1880 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1881 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1882 = or(_T_1879, _T_1880) node _T_1883 = or(_T_1882, _T_1881) node _T_1884 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1885 = and(_T_1883, _T_1884) else : node _T_1886 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1887 = eq(io.rw.addr, UInt<12>(0hb1f)) node _T_1888 = and(_T_1886, _T_1887) node _T_1889 = andr(UInt<2>(0h2)) node _T_1890 = eq(_T_1889, UInt<1>(0h0)) when _T_1890 : node _T_1891 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1892 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1893 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1894 = or(_T_1891, _T_1892) node _T_1895 = or(_T_1894, _T_1893) node _T_1896 = eq(io.rw.addr, UInt<12>(0hb9f)) node _T_1897 = and(_T_1895, _T_1896) else : node _T_1898 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1899 = eq(io.rw.addr, UInt<12>(0hb9f)) node _T_1900 = and(_T_1898, _T_1899) node _T_1901 = andr(UInt<2>(0h3)) node _T_1902 = eq(_T_1901, UInt<1>(0h0)) when _T_1902 : node _T_1903 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1904 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1905 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1906 = or(_T_1903, _T_1904) node _T_1907 = or(_T_1906, _T_1905) node _T_1908 = eq(io.rw.addr, UInt<12>(0hc9f)) node _T_1909 = and(_T_1907, _T_1908) else : node _T_1910 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1911 = eq(io.rw.addr, UInt<12>(0hc9f)) node _T_1912 = and(_T_1910, _T_1911) node _T_1913 = andr(UInt<2>(0h3)) node _T_1914 = eq(_T_1913, UInt<1>(0h0)) when _T_1914 : node _T_1915 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1916 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1917 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1918 = or(_T_1915, _T_1916) node _T_1919 = or(_T_1918, _T_1917) node _T_1920 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1921 = and(_T_1919, _T_1920) else : node _T_1922 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1923 = eq(io.rw.addr, UInt<12>(0hc00)) node _T_1924 = and(_T_1922, _T_1923) node _T_1925 = andr(UInt<2>(0h3)) node _T_1926 = eq(_T_1925, UInt<1>(0h0)) when _T_1926 : node _T_1927 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1928 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1929 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1930 = or(_T_1927, _T_1928) node _T_1931 = or(_T_1930, _T_1929) node _T_1932 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1933 = and(_T_1931, _T_1932) else : node _T_1934 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1935 = eq(io.rw.addr, UInt<12>(0hc02)) node _T_1936 = and(_T_1934, _T_1935) node _T_1937 = andr(UInt<2>(0h2)) node _T_1938 = eq(_T_1937, UInt<1>(0h0)) when _T_1938 : node _T_1939 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1940 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1941 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1942 = or(_T_1939, _T_1940) node _T_1943 = or(_T_1942, _T_1941) node _T_1944 = eq(io.rw.addr, UInt<12>(0hb80)) node _T_1945 = and(_T_1943, _T_1944) else : node _T_1946 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1947 = eq(io.rw.addr, UInt<12>(0hb80)) node _T_1948 = and(_T_1946, _T_1947) node _T_1949 = andr(UInt<2>(0h2)) node _T_1950 = eq(_T_1949, UInt<1>(0h0)) when _T_1950 : node _T_1951 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1952 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1953 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1954 = or(_T_1951, _T_1952) node _T_1955 = or(_T_1954, _T_1953) node _T_1956 = eq(io.rw.addr, UInt<12>(0hb82)) node _T_1957 = and(_T_1955, _T_1956) else : node _T_1958 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1959 = eq(io.rw.addr, UInt<12>(0hb82)) node _T_1960 = and(_T_1958, _T_1959) node _T_1961 = andr(UInt<2>(0h3)) node _T_1962 = eq(_T_1961, UInt<1>(0h0)) when _T_1962 : node _T_1963 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1964 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1965 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1966 = or(_T_1963, _T_1964) node _T_1967 = or(_T_1966, _T_1965) node _T_1968 = eq(io.rw.addr, UInt<12>(0hc80)) node _T_1969 = and(_T_1967, _T_1968) else : node _T_1970 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1971 = eq(io.rw.addr, UInt<12>(0hc80)) node _T_1972 = and(_T_1970, _T_1971) node _T_1973 = andr(UInt<2>(0h3)) node _T_1974 = eq(_T_1973, UInt<1>(0h0)) when _T_1974 : node _T_1975 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1976 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1977 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1978 = or(_T_1975, _T_1976) node _T_1979 = or(_T_1978, _T_1977) node _T_1980 = eq(io.rw.addr, UInt<12>(0hc82)) node _T_1981 = and(_T_1979, _T_1980) else : node _T_1982 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1983 = eq(io.rw.addr, UInt<12>(0hc82)) node _T_1984 = and(_T_1982, _T_1983) node _T_1985 = andr(UInt<2>(0h0)) node _T_1986 = eq(_T_1985, UInt<1>(0h0)) when _T_1986 : node _T_1987 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_1988 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_1989 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_1990 = or(_T_1987, _T_1988) node _T_1991 = or(_T_1990, _T_1989) node _T_1992 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1993 = and(_T_1991, _T_1992) else : node _T_1994 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_1995 = eq(io.rw.addr, UInt<10>(0h3a0)) node _T_1996 = and(_T_1994, _T_1995) node _T_1997 = andr(UInt<2>(0h0)) node _T_1998 = eq(_T_1997, UInt<1>(0h0)) when _T_1998 : node _T_1999 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2000 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2001 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2002 = or(_T_1999, _T_2000) node _T_2003 = or(_T_2002, _T_2001) node _T_2004 = eq(io.rw.addr, UInt<10>(0h3a1)) node _T_2005 = and(_T_2003, _T_2004) else : node _T_2006 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2007 = eq(io.rw.addr, UInt<10>(0h3a1)) node _T_2008 = and(_T_2006, _T_2007) node _T_2009 = andr(UInt<2>(0h0)) node _T_2010 = eq(_T_2009, UInt<1>(0h0)) when _T_2010 : node _T_2011 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2012 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2013 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2014 = or(_T_2011, _T_2012) node _T_2015 = or(_T_2014, _T_2013) node _T_2016 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_2017 = and(_T_2015, _T_2016) else : node _T_2018 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2019 = eq(io.rw.addr, UInt<10>(0h3a2)) node _T_2020 = and(_T_2018, _T_2019) node _T_2021 = andr(UInt<2>(0h0)) node _T_2022 = eq(_T_2021, UInt<1>(0h0)) when _T_2022 : node _T_2023 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2024 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2025 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2026 = or(_T_2023, _T_2024) node _T_2027 = or(_T_2026, _T_2025) node _T_2028 = eq(io.rw.addr, UInt<10>(0h3a3)) node _T_2029 = and(_T_2027, _T_2028) else : node _T_2030 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2031 = eq(io.rw.addr, UInt<10>(0h3a3)) node _T_2032 = and(_T_2030, _T_2031) node _T_2033 = andr(UInt<2>(0h0)) node _T_2034 = eq(_T_2033, UInt<1>(0h0)) when _T_2034 : node _T_2035 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2036 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2037 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2038 = or(_T_2035, _T_2036) node _T_2039 = or(_T_2038, _T_2037) node _T_2040 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_2041 = and(_T_2039, _T_2040) else : node _T_2042 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2043 = eq(io.rw.addr, UInt<10>(0h3b0)) node _T_2044 = and(_T_2042, _T_2043) node _T_2045 = andr(UInt<2>(0h0)) node _T_2046 = eq(_T_2045, UInt<1>(0h0)) when _T_2046 : node _T_2047 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2048 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2049 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2050 = or(_T_2047, _T_2048) node _T_2051 = or(_T_2050, _T_2049) node _T_2052 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_2053 = and(_T_2051, _T_2052) else : node _T_2054 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2055 = eq(io.rw.addr, UInt<10>(0h3b1)) node _T_2056 = and(_T_2054, _T_2055) node _T_2057 = andr(UInt<2>(0h0)) node _T_2058 = eq(_T_2057, UInt<1>(0h0)) when _T_2058 : node _T_2059 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2060 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2061 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2062 = or(_T_2059, _T_2060) node _T_2063 = or(_T_2062, _T_2061) node _T_2064 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_2065 = and(_T_2063, _T_2064) else : node _T_2066 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2067 = eq(io.rw.addr, UInt<10>(0h3b2)) node _T_2068 = and(_T_2066, _T_2067) node _T_2069 = andr(UInt<2>(0h0)) node _T_2070 = eq(_T_2069, UInt<1>(0h0)) when _T_2070 : node _T_2071 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2072 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2073 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2074 = or(_T_2071, _T_2072) node _T_2075 = or(_T_2074, _T_2073) node _T_2076 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_2077 = and(_T_2075, _T_2076) else : node _T_2078 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2079 = eq(io.rw.addr, UInt<10>(0h3b3)) node _T_2080 = and(_T_2078, _T_2079) node _T_2081 = andr(UInt<2>(0h0)) node _T_2082 = eq(_T_2081, UInt<1>(0h0)) when _T_2082 : node _T_2083 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2084 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2085 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2086 = or(_T_2083, _T_2084) node _T_2087 = or(_T_2086, _T_2085) node _T_2088 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_2089 = and(_T_2087, _T_2088) else : node _T_2090 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2091 = eq(io.rw.addr, UInt<10>(0h3b4)) node _T_2092 = and(_T_2090, _T_2091) node _T_2093 = andr(UInt<2>(0h0)) node _T_2094 = eq(_T_2093, UInt<1>(0h0)) when _T_2094 : node _T_2095 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2096 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2097 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2098 = or(_T_2095, _T_2096) node _T_2099 = or(_T_2098, _T_2097) node _T_2100 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_2101 = and(_T_2099, _T_2100) else : node _T_2102 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2103 = eq(io.rw.addr, UInt<10>(0h3b5)) node _T_2104 = and(_T_2102, _T_2103) node _T_2105 = andr(UInt<2>(0h0)) node _T_2106 = eq(_T_2105, UInt<1>(0h0)) when _T_2106 : node _T_2107 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2108 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2109 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2110 = or(_T_2107, _T_2108) node _T_2111 = or(_T_2110, _T_2109) node _T_2112 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_2113 = and(_T_2111, _T_2112) else : node _T_2114 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2115 = eq(io.rw.addr, UInt<10>(0h3b6)) node _T_2116 = and(_T_2114, _T_2115) node _T_2117 = andr(UInt<2>(0h0)) node _T_2118 = eq(_T_2117, UInt<1>(0h0)) when _T_2118 : node _T_2119 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2120 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2121 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2122 = or(_T_2119, _T_2120) node _T_2123 = or(_T_2122, _T_2121) node _T_2124 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_2125 = and(_T_2123, _T_2124) else : node _T_2126 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2127 = eq(io.rw.addr, UInt<10>(0h3b7)) node _T_2128 = and(_T_2126, _T_2127) node _T_2129 = andr(UInt<2>(0h0)) node _T_2130 = eq(_T_2129, UInt<1>(0h0)) when _T_2130 : node _T_2131 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2132 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2133 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2134 = or(_T_2131, _T_2132) node _T_2135 = or(_T_2134, _T_2133) node _T_2136 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_2137 = and(_T_2135, _T_2136) else : node _T_2138 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2139 = eq(io.rw.addr, UInt<10>(0h3b8)) node _T_2140 = and(_T_2138, _T_2139) node _T_2141 = andr(UInt<2>(0h0)) node _T_2142 = eq(_T_2141, UInt<1>(0h0)) when _T_2142 : node _T_2143 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2144 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2145 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2146 = or(_T_2143, _T_2144) node _T_2147 = or(_T_2146, _T_2145) node _T_2148 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_2149 = and(_T_2147, _T_2148) else : node _T_2150 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2151 = eq(io.rw.addr, UInt<10>(0h3b9)) node _T_2152 = and(_T_2150, _T_2151) node _T_2153 = andr(UInt<2>(0h0)) node _T_2154 = eq(_T_2153, UInt<1>(0h0)) when _T_2154 : node _T_2155 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2156 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2157 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2158 = or(_T_2155, _T_2156) node _T_2159 = or(_T_2158, _T_2157) node _T_2160 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_2161 = and(_T_2159, _T_2160) else : node _T_2162 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2163 = eq(io.rw.addr, UInt<10>(0h3ba)) node _T_2164 = and(_T_2162, _T_2163) node _T_2165 = andr(UInt<2>(0h0)) node _T_2166 = eq(_T_2165, UInt<1>(0h0)) when _T_2166 : node _T_2167 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2168 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2169 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2170 = or(_T_2167, _T_2168) node _T_2171 = or(_T_2170, _T_2169) node _T_2172 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_2173 = and(_T_2171, _T_2172) else : node _T_2174 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2175 = eq(io.rw.addr, UInt<10>(0h3bb)) node _T_2176 = and(_T_2174, _T_2175) node _T_2177 = andr(UInt<2>(0h0)) node _T_2178 = eq(_T_2177, UInt<1>(0h0)) when _T_2178 : node _T_2179 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2180 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2181 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2182 = or(_T_2179, _T_2180) node _T_2183 = or(_T_2182, _T_2181) node _T_2184 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_2185 = and(_T_2183, _T_2184) else : node _T_2186 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2187 = eq(io.rw.addr, UInt<10>(0h3bc)) node _T_2188 = and(_T_2186, _T_2187) node _T_2189 = andr(UInt<2>(0h0)) node _T_2190 = eq(_T_2189, UInt<1>(0h0)) when _T_2190 : node _T_2191 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2192 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2193 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2194 = or(_T_2191, _T_2192) node _T_2195 = or(_T_2194, _T_2193) node _T_2196 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_2197 = and(_T_2195, _T_2196) else : node _T_2198 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2199 = eq(io.rw.addr, UInt<10>(0h3bd)) node _T_2200 = and(_T_2198, _T_2199) node _T_2201 = andr(UInt<2>(0h0)) node _T_2202 = eq(_T_2201, UInt<1>(0h0)) when _T_2202 : node _T_2203 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2204 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2205 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2206 = or(_T_2203, _T_2204) node _T_2207 = or(_T_2206, _T_2205) node _T_2208 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_2209 = and(_T_2207, _T_2208) else : node _T_2210 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2211 = eq(io.rw.addr, UInt<10>(0h3be)) node _T_2212 = and(_T_2210, _T_2211) node _T_2213 = andr(UInt<2>(0h0)) node _T_2214 = eq(_T_2213, UInt<1>(0h0)) when _T_2214 : node _T_2215 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2216 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2217 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2218 = or(_T_2215, _T_2216) node _T_2219 = or(_T_2218, _T_2217) node _T_2220 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_2221 = and(_T_2219, _T_2220) else : node _T_2222 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2223 = eq(io.rw.addr, UInt<10>(0h3bf)) node _T_2224 = and(_T_2222, _T_2223) node _T_2225 = andr(UInt<2>(0h1)) node _T_2226 = eq(_T_2225, UInt<1>(0h0)) when _T_2226 : node _T_2227 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2228 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2229 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2230 = or(_T_2227, _T_2228) node _T_2231 = or(_T_2230, _T_2229) node _T_2232 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_2233 = and(_T_2231, _T_2232) else : node _T_2234 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2235 = eq(io.rw.addr, UInt<11>(0h7c1)) node _T_2236 = and(_T_2234, _T_2235) node _T_2237 = andr(UInt<2>(0h3)) node _T_2238 = eq(_T_2237, UInt<1>(0h0)) when _T_2238 : node _T_2239 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2240 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2241 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2242 = or(_T_2239, _T_2240) node _T_2243 = or(_T_2242, _T_2241) node _T_2244 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_2245 = and(_T_2243, _T_2244) else : node _T_2246 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2247 = eq(io.rw.addr, UInt<12>(0hf12)) node _T_2248 = and(_T_2246, _T_2247) node _T_2249 = andr(UInt<2>(0h3)) node _T_2250 = eq(_T_2249, UInt<1>(0h0)) when _T_2250 : node _T_2251 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2252 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2253 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2254 = or(_T_2251, _T_2252) node _T_2255 = or(_T_2254, _T_2253) node _T_2256 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_2257 = and(_T_2255, _T_2256) else : node _T_2258 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2259 = eq(io.rw.addr, UInt<12>(0hf11)) node _T_2260 = and(_T_2258, _T_2259) node _T_2261 = andr(UInt<2>(0h3)) node _T_2262 = eq(_T_2261, UInt<1>(0h0)) when _T_2262 : node _T_2263 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2264 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2265 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2266 = or(_T_2263, _T_2264) node _T_2267 = or(_T_2266, _T_2265) node _T_2268 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_2269 = and(_T_2267, _T_2268) else : node _T_2270 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2271 = eq(io.rw.addr, UInt<12>(0hf13)) node _T_2272 = and(_T_2270, _T_2271) node _T_2273 = andr(UInt<2>(0h3)) node _T_2274 = eq(_T_2273, UInt<1>(0h0)) when _T_2274 : node _T_2275 = eq(io.rw.cmd, UInt<3>(0h5)) node _T_2276 = eq(io.rw.cmd, UInt<3>(0h6)) node _T_2277 = eq(io.rw.cmd, UInt<3>(0h7)) node _T_2278 = or(_T_2275, _T_2276) node _T_2279 = or(_T_2278, _T_2277) node _T_2280 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_2281 = and(_T_2279, _T_2280) else : node _T_2282 = eq(io.rw.cmd, UInt<3>(0h2)) node _T_2283 = eq(io.rw.addr, UInt<12>(0hf15)) node _T_2284 = and(_T_2282, _T_2283) wire set_vs_dirty : UInt<1> connect set_vs_dirty, UInt<1>(0h0) wire set_fs_dirty : UInt<1> connect set_fs_dirty, UInt<1>(0h0) connect io.fcsr_rm, reg_frm when io.fcsr_flags.valid : node _reg_fflags_T = or(reg_fflags, io.fcsr_flags.bits) connect reg_fflags, _reg_fflags_T connect set_fs_dirty, UInt<1>(0h1) node _csr_wen_T = eq(io.rw.cmd, UInt<3>(0h6)) node _csr_wen_T_1 = eq(io.rw.cmd, UInt<3>(0h7)) node _csr_wen_T_2 = eq(io.rw.cmd, UInt<3>(0h5)) node _csr_wen_T_3 = or(_csr_wen_T, _csr_wen_T_1) node _csr_wen_T_4 = or(_csr_wen_T_3, _csr_wen_T_2) node _csr_wen_T_5 = eq(io.rw_stall, UInt<1>(0h0)) node csr_wen = and(_csr_wen_T_4, _csr_wen_T_5) node _io_csrw_counter_T = and(UInt<1>(0h1), csr_wen) node _io_csrw_counter_T_1 = geq(io.rw.addr, UInt<12>(0hb00)) node _io_csrw_counter_T_2 = lt(io.rw.addr, UInt<12>(0hb20)) node _io_csrw_counter_T_3 = and(_io_csrw_counter_T_1, _io_csrw_counter_T_2) node _io_csrw_counter_T_4 = geq(io.rw.addr, UInt<12>(0hb80)) node _io_csrw_counter_T_5 = lt(io.rw.addr, UInt<12>(0hba0)) node _io_csrw_counter_T_6 = and(_io_csrw_counter_T_4, _io_csrw_counter_T_5) node _io_csrw_counter_T_7 = or(_io_csrw_counter_T_3, _io_csrw_counter_T_6) node _io_csrw_counter_T_8 = and(_io_csrw_counter_T, _io_csrw_counter_T_7) node _io_csrw_counter_T_9 = bits(io.rw.addr, 4, 0) node _io_csrw_counter_T_10 = dshl(UInt<1>(0h1), _io_csrw_counter_T_9) node _io_csrw_counter_T_11 = mux(_io_csrw_counter_T_8, _io_csrw_counter_T_10, UInt<1>(0h0)) connect io.csrw_counter, _io_csrw_counter_T_11 when csr_wen : when decoded_addr_125_2 : wire new_mstatus : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>} wire _new_mstatus_WIRE : UInt<105> connect _new_mstatus_WIRE, wdata node _new_mstatus_T = bits(_new_mstatus_WIRE, 0, 0) connect new_mstatus.uie, _new_mstatus_T node _new_mstatus_T_1 = bits(_new_mstatus_WIRE, 1, 1) connect new_mstatus.sie, _new_mstatus_T_1 node _new_mstatus_T_2 = bits(_new_mstatus_WIRE, 2, 2) connect new_mstatus.hie, _new_mstatus_T_2 node _new_mstatus_T_3 = bits(_new_mstatus_WIRE, 3, 3) connect new_mstatus.mie, _new_mstatus_T_3 node _new_mstatus_T_4 = bits(_new_mstatus_WIRE, 4, 4) connect new_mstatus.upie, _new_mstatus_T_4 node _new_mstatus_T_5 = bits(_new_mstatus_WIRE, 5, 5) connect new_mstatus.spie, _new_mstatus_T_5 node _new_mstatus_T_6 = bits(_new_mstatus_WIRE, 6, 6) connect new_mstatus.ube, _new_mstatus_T_6 node _new_mstatus_T_7 = bits(_new_mstatus_WIRE, 7, 7) connect new_mstatus.mpie, _new_mstatus_T_7 node _new_mstatus_T_8 = bits(_new_mstatus_WIRE, 8, 8) connect new_mstatus.spp, _new_mstatus_T_8 node _new_mstatus_T_9 = bits(_new_mstatus_WIRE, 10, 9) connect new_mstatus.vs, _new_mstatus_T_9 node _new_mstatus_T_10 = bits(_new_mstatus_WIRE, 12, 11) connect new_mstatus.mpp, _new_mstatus_T_10 node _new_mstatus_T_11 = bits(_new_mstatus_WIRE, 14, 13) connect new_mstatus.fs, _new_mstatus_T_11 node _new_mstatus_T_12 = bits(_new_mstatus_WIRE, 16, 15) connect new_mstatus.xs, _new_mstatus_T_12 node _new_mstatus_T_13 = bits(_new_mstatus_WIRE, 17, 17) connect new_mstatus.mprv, _new_mstatus_T_13 node _new_mstatus_T_14 = bits(_new_mstatus_WIRE, 18, 18) connect new_mstatus.sum, _new_mstatus_T_14 node _new_mstatus_T_15 = bits(_new_mstatus_WIRE, 19, 19) connect new_mstatus.mxr, _new_mstatus_T_15 node _new_mstatus_T_16 = bits(_new_mstatus_WIRE, 20, 20) connect new_mstatus.tvm, _new_mstatus_T_16 node _new_mstatus_T_17 = bits(_new_mstatus_WIRE, 21, 21) connect new_mstatus.tw, _new_mstatus_T_17 node _new_mstatus_T_18 = bits(_new_mstatus_WIRE, 22, 22) connect new_mstatus.tsr, _new_mstatus_T_18 node _new_mstatus_T_19 = bits(_new_mstatus_WIRE, 30, 23) connect new_mstatus.zero1, _new_mstatus_T_19 node _new_mstatus_T_20 = bits(_new_mstatus_WIRE, 31, 31) connect new_mstatus.sd_rv32, _new_mstatus_T_20 node _new_mstatus_T_21 = bits(_new_mstatus_WIRE, 33, 32) connect new_mstatus.uxl, _new_mstatus_T_21 node _new_mstatus_T_22 = bits(_new_mstatus_WIRE, 35, 34) connect new_mstatus.sxl, _new_mstatus_T_22 node _new_mstatus_T_23 = bits(_new_mstatus_WIRE, 36, 36) connect new_mstatus.sbe, _new_mstatus_T_23 node _new_mstatus_T_24 = bits(_new_mstatus_WIRE, 37, 37) connect new_mstatus.mbe, _new_mstatus_T_24 node _new_mstatus_T_25 = bits(_new_mstatus_WIRE, 38, 38) connect new_mstatus.gva, _new_mstatus_T_25 node _new_mstatus_T_26 = bits(_new_mstatus_WIRE, 39, 39) connect new_mstatus.mpv, _new_mstatus_T_26 node _new_mstatus_T_27 = bits(_new_mstatus_WIRE, 62, 40) connect new_mstatus.zero2, _new_mstatus_T_27 node _new_mstatus_T_28 = bits(_new_mstatus_WIRE, 63, 63) connect new_mstatus.sd, _new_mstatus_T_28 node _new_mstatus_T_29 = bits(_new_mstatus_WIRE, 64, 64) connect new_mstatus.v, _new_mstatus_T_29 node _new_mstatus_T_30 = bits(_new_mstatus_WIRE, 66, 65) connect new_mstatus.prv, _new_mstatus_T_30 node _new_mstatus_T_31 = bits(_new_mstatus_WIRE, 67, 67) connect new_mstatus.dv, _new_mstatus_T_31 node _new_mstatus_T_32 = bits(_new_mstatus_WIRE, 69, 68) connect new_mstatus.dprv, _new_mstatus_T_32 node _new_mstatus_T_33 = bits(_new_mstatus_WIRE, 101, 70) connect new_mstatus.isa, _new_mstatus_T_33 node _new_mstatus_T_34 = bits(_new_mstatus_WIRE, 102, 102) connect new_mstatus.wfi, _new_mstatus_T_34 node _new_mstatus_T_35 = bits(_new_mstatus_WIRE, 103, 103) connect new_mstatus.cease, _new_mstatus_T_35 node _new_mstatus_T_36 = bits(_new_mstatus_WIRE, 104, 104) connect new_mstatus.debug, _new_mstatus_T_36 connect reg_mstatus.mie, new_mstatus.mie connect reg_mstatus.mpie, new_mstatus.mpie connect reg_mstatus.vs, UInt<1>(0h0) when decoded_addr_115_2 : node f = bits(wdata, 5, 5) node _T_2285 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _T_2286 = bits(io.pc, 1, 1) node _T_2287 = eq(_T_2286, UInt<1>(0h0)) node _T_2288 = or(_T_2285, _T_2287) node _T_2289 = bits(wdata, 2, 2) node _T_2290 = or(_T_2288, _T_2289) when _T_2290 : node _reg_misa_T = not(wdata) node _reg_misa_T_1 = eq(f, UInt<1>(0h0)) node _reg_misa_T_2 = shl(_reg_misa_T_1, 3) node _reg_misa_T_3 = or(_reg_misa_T, _reg_misa_T_2) node _reg_misa_T_4 = not(_reg_misa_T_3) node _reg_misa_T_5 = and(_reg_misa_T_4, UInt<32>(0h1005)) node _reg_misa_T_6 = not(UInt<32>(0h1005)) node _reg_misa_T_7 = and(reg_misa, _reg_misa_T_6) node _reg_misa_T_8 = or(_reg_misa_T_5, _reg_misa_T_7) connect reg_misa, _reg_misa_T_8 when decoded_addr_135_2 : node new_mip_lo_lo_lo = cat(reg_mip.ssip, reg_mip.usip) node new_mip_lo_lo_hi = cat(reg_mip.msip, reg_mip.vssip) node new_mip_lo_lo = cat(new_mip_lo_lo_hi, new_mip_lo_lo_lo) node new_mip_lo_hi_lo = cat(reg_mip.stip, reg_mip.utip) node new_mip_lo_hi_hi = cat(reg_mip.mtip, reg_mip.vstip) node new_mip_lo_hi = cat(new_mip_lo_hi_hi, new_mip_lo_hi_lo) node new_mip_lo = cat(new_mip_lo_hi, new_mip_lo_lo) node new_mip_hi_lo_lo = cat(reg_mip.seip, reg_mip.ueip) node new_mip_hi_lo_hi = cat(reg_mip.meip, reg_mip.vseip) node new_mip_hi_lo = cat(new_mip_hi_lo_hi, new_mip_hi_lo_lo) node new_mip_hi_hi_lo = cat(reg_mip.rocc, reg_mip.sgeip) node new_mip_hi_hi_hi_hi = cat(UInt<0>(0h0), reg_mip.zero1) node new_mip_hi_hi_hi = cat(new_mip_hi_hi_hi_hi, reg_mip.debug) node new_mip_hi_hi = cat(new_mip_hi_hi_hi, new_mip_hi_hi_lo) node new_mip_hi = cat(new_mip_hi_hi, new_mip_hi_lo) node _new_mip_T = cat(new_mip_hi, new_mip_lo) node _new_mip_T_1 = bits(io.rw.cmd, 1, 1) node _new_mip_T_2 = mux(_new_mip_T_1, _new_mip_T, UInt<1>(0h0)) node _new_mip_T_3 = or(_new_mip_T_2, io.rw.wdata) node _new_mip_T_4 = bits(io.rw.cmd, 1, 0) node _new_mip_T_5 = andr(_new_mip_T_4) node _new_mip_T_6 = mux(_new_mip_T_5, io.rw.wdata, UInt<1>(0h0)) node _new_mip_T_7 = not(_new_mip_T_6) node _new_mip_T_8 = and(_new_mip_T_3, _new_mip_T_7) wire new_mip : { lip : UInt<1>[0], zero1 : UInt<1>, debug : UInt<1>, rocc : UInt<1>, sgeip : UInt<1>, meip : UInt<1>, vseip : UInt<1>, seip : UInt<1>, ueip : UInt<1>, mtip : UInt<1>, vstip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, vssip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} wire _new_mip_WIRE : UInt<16> connect _new_mip_WIRE, _new_mip_T_8 node _new_mip_T_9 = bits(_new_mip_WIRE, 0, 0) connect new_mip.usip, _new_mip_T_9 node _new_mip_T_10 = bits(_new_mip_WIRE, 1, 1) connect new_mip.ssip, _new_mip_T_10 node _new_mip_T_11 = bits(_new_mip_WIRE, 2, 2) connect new_mip.vssip, _new_mip_T_11 node _new_mip_T_12 = bits(_new_mip_WIRE, 3, 3) connect new_mip.msip, _new_mip_T_12 node _new_mip_T_13 = bits(_new_mip_WIRE, 4, 4) connect new_mip.utip, _new_mip_T_13 node _new_mip_T_14 = bits(_new_mip_WIRE, 5, 5) connect new_mip.stip, _new_mip_T_14 node _new_mip_T_15 = bits(_new_mip_WIRE, 6, 6) connect new_mip.vstip, _new_mip_T_15 node _new_mip_T_16 = bits(_new_mip_WIRE, 7, 7) connect new_mip.mtip, _new_mip_T_16 node _new_mip_T_17 = bits(_new_mip_WIRE, 8, 8) connect new_mip.ueip, _new_mip_T_17 node _new_mip_T_18 = bits(_new_mip_WIRE, 9, 9) connect new_mip.seip, _new_mip_T_18 node _new_mip_T_19 = bits(_new_mip_WIRE, 10, 10) connect new_mip.vseip, _new_mip_T_19 node _new_mip_T_20 = bits(_new_mip_WIRE, 11, 11) connect new_mip.meip, _new_mip_T_20 node _new_mip_T_21 = bits(_new_mip_WIRE, 12, 12) connect new_mip.sgeip, _new_mip_T_21 node _new_mip_T_22 = bits(_new_mip_WIRE, 13, 13) connect new_mip.rocc, _new_mip_T_22 node _new_mip_T_23 = bits(_new_mip_WIRE, 14, 14) connect new_mip.debug, _new_mip_T_23 node _new_mip_T_24 = bits(_new_mip_WIRE, 15, 15) connect new_mip.zero1, _new_mip_T_24 when decoded_addr_94_2 : node _reg_mie_T = and(wdata, supported_interrupts) connect reg_mie, _reg_mie_T when decoded_addr_173_2 : node _reg_mepc_T = not(wdata) node _reg_mepc_T_1 = or(_reg_mepc_T, UInt<1>(0h1)) node _reg_mepc_T_2 = not(_reg_mepc_T_1) connect reg_mepc, _reg_mepc_T_2 when decoded_addr_170_2 : connect reg_mscratch, wdata when decoded_addr_89_2 : connect reg_mtvec, wdata when decoded_addr_35_2 : node _reg_mcause_T = and(wdata, UInt<32>(0h8000000f)) connect reg_mcause, _reg_mcause_T when decoded_addr_179_2 : connect reg_mtval, wdata when decoded_addr_171_2 : node _reg_mcountinhibit_T = not(UInt<32>(0h2)) node _reg_mcountinhibit_T_1 = and(wdata, _reg_mcountinhibit_T) connect reg_mcountinhibit, _reg_mcountinhibit_T_1 when decoded_addr_128_2 : node _T_2291 = bits(value_1, 63, 32) node _T_2292 = cat(_T_2291, wdata) connect small_1, _T_2292 node _large_T_6 = shr(_T_2292, 6) connect large_1, _large_T_6 when decoded_addr_167_2 : node _T_2293 = bits(wdata, 31, 0) node _T_2294 = bits(value_1, 31, 0) node _T_2295 = cat(_T_2293, _T_2294) connect small_1, _T_2295 node _large_T_7 = shr(_T_2295, 6) connect large_1, _large_T_7 when decoded_addr_156_2 : node _T_2296 = bits(value, 63, 32) node _T_2297 = cat(_T_2296, wdata) connect small, _T_2297 node _large_T_8 = shr(_T_2297, 6) connect large, _large_T_8 when decoded_addr_64_2 : node _T_2298 = bits(wdata, 31, 0) node _T_2299 = bits(value, 31, 0) node _T_2300 = cat(_T_2298, _T_2299) connect small, _T_2300 node _large_T_9 = shr(_T_2300, 6) connect large, _large_T_9 when decoded_addr_59_2 : wire new_dcsr : { xdebugver : UInt<2>, zero4 : UInt<2>, zero3 : UInt<12>, ebreakm : UInt<1>, ebreakh : UInt<1>, ebreaks : UInt<1>, ebreaku : UInt<1>, zero2 : UInt<1>, stopcycle : UInt<1>, stoptime : UInt<1>, cause : UInt<3>, v : UInt<1>, zero1 : UInt<2>, step : UInt<1>, prv : UInt<2>} wire _new_dcsr_WIRE : UInt<32> connect _new_dcsr_WIRE, wdata node _new_dcsr_T = bits(_new_dcsr_WIRE, 1, 0) connect new_dcsr.prv, _new_dcsr_T node _new_dcsr_T_1 = bits(_new_dcsr_WIRE, 2, 2) connect new_dcsr.step, _new_dcsr_T_1 node _new_dcsr_T_2 = bits(_new_dcsr_WIRE, 4, 3) connect new_dcsr.zero1, _new_dcsr_T_2 node _new_dcsr_T_3 = bits(_new_dcsr_WIRE, 5, 5) connect new_dcsr.v, _new_dcsr_T_3 node _new_dcsr_T_4 = bits(_new_dcsr_WIRE, 8, 6) connect new_dcsr.cause, _new_dcsr_T_4 node _new_dcsr_T_5 = bits(_new_dcsr_WIRE, 9, 9) connect new_dcsr.stoptime, _new_dcsr_T_5 node _new_dcsr_T_6 = bits(_new_dcsr_WIRE, 10, 10) connect new_dcsr.stopcycle, _new_dcsr_T_6 node _new_dcsr_T_7 = bits(_new_dcsr_WIRE, 11, 11) connect new_dcsr.zero2, _new_dcsr_T_7 node _new_dcsr_T_8 = bits(_new_dcsr_WIRE, 12, 12) connect new_dcsr.ebreaku, _new_dcsr_T_8 node _new_dcsr_T_9 = bits(_new_dcsr_WIRE, 13, 13) connect new_dcsr.ebreaks, _new_dcsr_T_9 node _new_dcsr_T_10 = bits(_new_dcsr_WIRE, 14, 14) connect new_dcsr.ebreakh, _new_dcsr_T_10 node _new_dcsr_T_11 = bits(_new_dcsr_WIRE, 15, 15) connect new_dcsr.ebreakm, _new_dcsr_T_11 node _new_dcsr_T_12 = bits(_new_dcsr_WIRE, 27, 16) connect new_dcsr.zero3, _new_dcsr_T_12 node _new_dcsr_T_13 = bits(_new_dcsr_WIRE, 29, 28) connect new_dcsr.zero4, _new_dcsr_T_13 node _new_dcsr_T_14 = bits(_new_dcsr_WIRE, 31, 30) connect new_dcsr.xdebugver, _new_dcsr_T_14 connect reg_dcsr.step, new_dcsr.step connect reg_dcsr.ebreakm, new_dcsr.ebreakm when decoded_addr_112_2 : node _reg_dpc_T = not(wdata) node _reg_dpc_T_1 = or(_reg_dpc_T, UInt<1>(0h1)) node _reg_dpc_T_2 = not(_reg_dpc_T_1) connect reg_dpc, _reg_dpc_T_2 when decoded_addr_69_2 : connect reg_dscratch0, wdata when decoded_addr_121_2 : connect reg_tselect, wdata node _T_2301 = eq(UInt<1>(0h0), reg_tselect) node _T_2302 = eq(reg_bp[0].control.dmode, UInt<1>(0h0)) node _T_2303 = or(_T_2302, reg_debug) node _T_2304 = and(_T_2301, _T_2303) when _T_2304 : when decoded_addr_13_2 : connect reg_bp[0].address, wdata when decoded_addr_153_2 : skip when decoded_addr_66_2 : wire _reg_bp_0_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<8>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_0_control_WIRE_1 : UInt<32> connect _reg_bp_0_control_WIRE_1, wdata node _reg_bp_0_control_T = bits(_reg_bp_0_control_WIRE_1, 0, 0) connect _reg_bp_0_control_WIRE.r, _reg_bp_0_control_T node _reg_bp_0_control_T_1 = bits(_reg_bp_0_control_WIRE_1, 1, 1) connect _reg_bp_0_control_WIRE.w, _reg_bp_0_control_T_1 node _reg_bp_0_control_T_2 = bits(_reg_bp_0_control_WIRE_1, 2, 2) connect _reg_bp_0_control_WIRE.x, _reg_bp_0_control_T_2 node _reg_bp_0_control_T_3 = bits(_reg_bp_0_control_WIRE_1, 3, 3) connect _reg_bp_0_control_WIRE.u, _reg_bp_0_control_T_3 node _reg_bp_0_control_T_4 = bits(_reg_bp_0_control_WIRE_1, 4, 4) connect _reg_bp_0_control_WIRE.s, _reg_bp_0_control_T_4 node _reg_bp_0_control_T_5 = bits(_reg_bp_0_control_WIRE_1, 5, 5) connect _reg_bp_0_control_WIRE.h, _reg_bp_0_control_T_5 node _reg_bp_0_control_T_6 = bits(_reg_bp_0_control_WIRE_1, 6, 6) connect _reg_bp_0_control_WIRE.m, _reg_bp_0_control_T_6 node _reg_bp_0_control_T_7 = bits(_reg_bp_0_control_WIRE_1, 8, 7) connect _reg_bp_0_control_WIRE.tmatch, _reg_bp_0_control_T_7 node _reg_bp_0_control_T_8 = bits(_reg_bp_0_control_WIRE_1, 10, 9) connect _reg_bp_0_control_WIRE.zero, _reg_bp_0_control_T_8 node _reg_bp_0_control_T_9 = bits(_reg_bp_0_control_WIRE_1, 11, 11) connect _reg_bp_0_control_WIRE.chain, _reg_bp_0_control_T_9 node _reg_bp_0_control_T_10 = bits(_reg_bp_0_control_WIRE_1, 12, 12) connect _reg_bp_0_control_WIRE.action, _reg_bp_0_control_T_10 node _reg_bp_0_control_T_11 = bits(_reg_bp_0_control_WIRE_1, 20, 13) connect _reg_bp_0_control_WIRE.reserved, _reg_bp_0_control_T_11 node _reg_bp_0_control_T_12 = bits(_reg_bp_0_control_WIRE_1, 26, 21) connect _reg_bp_0_control_WIRE.maskmax, _reg_bp_0_control_T_12 node _reg_bp_0_control_T_13 = bits(_reg_bp_0_control_WIRE_1, 27, 27) connect _reg_bp_0_control_WIRE.dmode, _reg_bp_0_control_T_13 node _reg_bp_0_control_T_14 = bits(_reg_bp_0_control_WIRE_1, 31, 28) connect _reg_bp_0_control_WIRE.ttype, _reg_bp_0_control_T_14 connect reg_bp[0].control, _reg_bp_0_control_WIRE node newBPC_lo_lo_hi = cat(reg_bp[0].control.x, reg_bp[0].control.w) node newBPC_lo_lo = cat(newBPC_lo_lo_hi, reg_bp[0].control.r) node newBPC_lo_hi_lo = cat(reg_bp[0].control.s, reg_bp[0].control.u) node newBPC_lo_hi_hi = cat(reg_bp[0].control.m, reg_bp[0].control.h) node newBPC_lo_hi = cat(newBPC_lo_hi_hi, newBPC_lo_hi_lo) node newBPC_lo = cat(newBPC_lo_hi, newBPC_lo_lo) node newBPC_hi_lo_lo = cat(reg_bp[0].control.zero, reg_bp[0].control.tmatch) node newBPC_hi_lo_hi = cat(reg_bp[0].control.action, reg_bp[0].control.chain) node newBPC_hi_lo = cat(newBPC_hi_lo_hi, newBPC_hi_lo_lo) node newBPC_hi_hi_lo = cat(reg_bp[0].control.maskmax, reg_bp[0].control.reserved) node newBPC_hi_hi_hi = cat(reg_bp[0].control.ttype, reg_bp[0].control.dmode) node newBPC_hi_hi = cat(newBPC_hi_hi_hi, newBPC_hi_hi_lo) node newBPC_hi = cat(newBPC_hi_hi, newBPC_hi_lo) node _newBPC_T = cat(newBPC_hi, newBPC_lo) node _newBPC_T_1 = bits(io.rw.cmd, 1, 1) node _newBPC_T_2 = mux(_newBPC_T_1, _newBPC_T, UInt<1>(0h0)) node _newBPC_T_3 = or(_newBPC_T_2, io.rw.wdata) node _newBPC_T_4 = bits(io.rw.cmd, 1, 0) node _newBPC_T_5 = andr(_newBPC_T_4) node _newBPC_T_6 = mux(_newBPC_T_5, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_7 = not(_newBPC_T_6) node _newBPC_T_8 = and(_newBPC_T_3, _newBPC_T_7) wire newBPC : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<8>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE : UInt<32> connect _newBPC_WIRE, _newBPC_T_8 node _newBPC_T_9 = bits(_newBPC_WIRE, 0, 0) connect newBPC.r, _newBPC_T_9 node _newBPC_T_10 = bits(_newBPC_WIRE, 1, 1) connect newBPC.w, _newBPC_T_10 node _newBPC_T_11 = bits(_newBPC_WIRE, 2, 2) connect newBPC.x, _newBPC_T_11 node _newBPC_T_12 = bits(_newBPC_WIRE, 3, 3) connect newBPC.u, _newBPC_T_12 node _newBPC_T_13 = bits(_newBPC_WIRE, 4, 4) connect newBPC.s, _newBPC_T_13 node _newBPC_T_14 = bits(_newBPC_WIRE, 5, 5) connect newBPC.h, _newBPC_T_14 node _newBPC_T_15 = bits(_newBPC_WIRE, 6, 6) connect newBPC.m, _newBPC_T_15 node _newBPC_T_16 = bits(_newBPC_WIRE, 8, 7) connect newBPC.tmatch, _newBPC_T_16 node _newBPC_T_17 = bits(_newBPC_WIRE, 10, 9) connect newBPC.zero, _newBPC_T_17 node _newBPC_T_18 = bits(_newBPC_WIRE, 11, 11) connect newBPC.chain, _newBPC_T_18 node _newBPC_T_19 = bits(_newBPC_WIRE, 12, 12) connect newBPC.action, _newBPC_T_19 node _newBPC_T_20 = bits(_newBPC_WIRE, 20, 13) connect newBPC.reserved, _newBPC_T_20 node _newBPC_T_21 = bits(_newBPC_WIRE, 26, 21) connect newBPC.maskmax, _newBPC_T_21 node _newBPC_T_22 = bits(_newBPC_WIRE, 27, 27) connect newBPC.dmode, _newBPC_T_22 node _newBPC_T_23 = bits(_newBPC_WIRE, 31, 28) connect newBPC.ttype, _newBPC_T_23 node _dMode_T = and(newBPC.dmode, reg_debug) node _dMode_T_1 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _dMode_T_2 = or(UInt<1>(0h0), _dMode_T_1) node dMode = and(_dMode_T, _dMode_T_2) connect reg_bp[0].control.dmode, dMode node _T_2305 = gt(newBPC.action, UInt<1>(0h1)) node _T_2306 = or(dMode, _T_2305) when _T_2306 : connect reg_bp[0].control.action, newBPC.action else : connect reg_bp[0].control.action, UInt<1>(0h0) node _reg_bp_0_control_chain_T = or(UInt<1>(0h0), UInt<1>(0h1)) node _reg_bp_0_control_chain_T_1 = eq(_reg_bp_0_control_chain_T, UInt<1>(0h0)) node _reg_bp_0_control_chain_T_2 = and(newBPC.chain, _reg_bp_0_control_chain_T_1) node _reg_bp_0_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_0_control_chain_T_4 = or(dMode, _reg_bp_0_control_chain_T_3) node _reg_bp_0_control_chain_T_5 = and(_reg_bp_0_control_chain_T_2, _reg_bp_0_control_chain_T_4) connect reg_bp[0].control.chain, _reg_bp_0_control_chain_T_5 node _T_2307 = eq(UInt<1>(0h1), reg_tselect) node _T_2308 = eq(reg_bp[1].control.dmode, UInt<1>(0h0)) node _T_2309 = or(_T_2308, reg_debug) node _T_2310 = and(_T_2307, _T_2309) when _T_2310 : when decoded_addr_13_2 : connect reg_bp[1].address, wdata when decoded_addr_153_2 : skip when decoded_addr_66_2 : wire _reg_bp_1_control_WIRE : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<8>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _reg_bp_1_control_WIRE_1 : UInt<32> connect _reg_bp_1_control_WIRE_1, wdata node _reg_bp_1_control_T = bits(_reg_bp_1_control_WIRE_1, 0, 0) connect _reg_bp_1_control_WIRE.r, _reg_bp_1_control_T node _reg_bp_1_control_T_1 = bits(_reg_bp_1_control_WIRE_1, 1, 1) connect _reg_bp_1_control_WIRE.w, _reg_bp_1_control_T_1 node _reg_bp_1_control_T_2 = bits(_reg_bp_1_control_WIRE_1, 2, 2) connect _reg_bp_1_control_WIRE.x, _reg_bp_1_control_T_2 node _reg_bp_1_control_T_3 = bits(_reg_bp_1_control_WIRE_1, 3, 3) connect _reg_bp_1_control_WIRE.u, _reg_bp_1_control_T_3 node _reg_bp_1_control_T_4 = bits(_reg_bp_1_control_WIRE_1, 4, 4) connect _reg_bp_1_control_WIRE.s, _reg_bp_1_control_T_4 node _reg_bp_1_control_T_5 = bits(_reg_bp_1_control_WIRE_1, 5, 5) connect _reg_bp_1_control_WIRE.h, _reg_bp_1_control_T_5 node _reg_bp_1_control_T_6 = bits(_reg_bp_1_control_WIRE_1, 6, 6) connect _reg_bp_1_control_WIRE.m, _reg_bp_1_control_T_6 node _reg_bp_1_control_T_7 = bits(_reg_bp_1_control_WIRE_1, 8, 7) connect _reg_bp_1_control_WIRE.tmatch, _reg_bp_1_control_T_7 node _reg_bp_1_control_T_8 = bits(_reg_bp_1_control_WIRE_1, 10, 9) connect _reg_bp_1_control_WIRE.zero, _reg_bp_1_control_T_8 node _reg_bp_1_control_T_9 = bits(_reg_bp_1_control_WIRE_1, 11, 11) connect _reg_bp_1_control_WIRE.chain, _reg_bp_1_control_T_9 node _reg_bp_1_control_T_10 = bits(_reg_bp_1_control_WIRE_1, 12, 12) connect _reg_bp_1_control_WIRE.action, _reg_bp_1_control_T_10 node _reg_bp_1_control_T_11 = bits(_reg_bp_1_control_WIRE_1, 20, 13) connect _reg_bp_1_control_WIRE.reserved, _reg_bp_1_control_T_11 node _reg_bp_1_control_T_12 = bits(_reg_bp_1_control_WIRE_1, 26, 21) connect _reg_bp_1_control_WIRE.maskmax, _reg_bp_1_control_T_12 node _reg_bp_1_control_T_13 = bits(_reg_bp_1_control_WIRE_1, 27, 27) connect _reg_bp_1_control_WIRE.dmode, _reg_bp_1_control_T_13 node _reg_bp_1_control_T_14 = bits(_reg_bp_1_control_WIRE_1, 31, 28) connect _reg_bp_1_control_WIRE.ttype, _reg_bp_1_control_T_14 connect reg_bp[1].control, _reg_bp_1_control_WIRE node newBPC_lo_lo_hi_1 = cat(reg_bp[1].control.x, reg_bp[1].control.w) node newBPC_lo_lo_1 = cat(newBPC_lo_lo_hi_1, reg_bp[1].control.r) node newBPC_lo_hi_lo_1 = cat(reg_bp[1].control.s, reg_bp[1].control.u) node newBPC_lo_hi_hi_1 = cat(reg_bp[1].control.m, reg_bp[1].control.h) node newBPC_lo_hi_1 = cat(newBPC_lo_hi_hi_1, newBPC_lo_hi_lo_1) node newBPC_lo_1 = cat(newBPC_lo_hi_1, newBPC_lo_lo_1) node newBPC_hi_lo_lo_1 = cat(reg_bp[1].control.zero, reg_bp[1].control.tmatch) node newBPC_hi_lo_hi_1 = cat(reg_bp[1].control.action, reg_bp[1].control.chain) node newBPC_hi_lo_1 = cat(newBPC_hi_lo_hi_1, newBPC_hi_lo_lo_1) node newBPC_hi_hi_lo_1 = cat(reg_bp[1].control.maskmax, reg_bp[1].control.reserved) node newBPC_hi_hi_hi_1 = cat(reg_bp[1].control.ttype, reg_bp[1].control.dmode) node newBPC_hi_hi_1 = cat(newBPC_hi_hi_hi_1, newBPC_hi_hi_lo_1) node newBPC_hi_1 = cat(newBPC_hi_hi_1, newBPC_hi_lo_1) node _newBPC_T_24 = cat(newBPC_hi_1, newBPC_lo_1) node _newBPC_T_25 = bits(io.rw.cmd, 1, 1) node _newBPC_T_26 = mux(_newBPC_T_25, _newBPC_T_24, UInt<1>(0h0)) node _newBPC_T_27 = or(_newBPC_T_26, io.rw.wdata) node _newBPC_T_28 = bits(io.rw.cmd, 1, 0) node _newBPC_T_29 = andr(_newBPC_T_28) node _newBPC_T_30 = mux(_newBPC_T_29, io.rw.wdata, UInt<1>(0h0)) node _newBPC_T_31 = not(_newBPC_T_30) node _newBPC_T_32 = and(_newBPC_T_27, _newBPC_T_31) wire newBPC_1 : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<8>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newBPC_WIRE_1 : UInt<32> connect _newBPC_WIRE_1, _newBPC_T_32 node _newBPC_T_33 = bits(_newBPC_WIRE_1, 0, 0) connect newBPC_1.r, _newBPC_T_33 node _newBPC_T_34 = bits(_newBPC_WIRE_1, 1, 1) connect newBPC_1.w, _newBPC_T_34 node _newBPC_T_35 = bits(_newBPC_WIRE_1, 2, 2) connect newBPC_1.x, _newBPC_T_35 node _newBPC_T_36 = bits(_newBPC_WIRE_1, 3, 3) connect newBPC_1.u, _newBPC_T_36 node _newBPC_T_37 = bits(_newBPC_WIRE_1, 4, 4) connect newBPC_1.s, _newBPC_T_37 node _newBPC_T_38 = bits(_newBPC_WIRE_1, 5, 5) connect newBPC_1.h, _newBPC_T_38 node _newBPC_T_39 = bits(_newBPC_WIRE_1, 6, 6) connect newBPC_1.m, _newBPC_T_39 node _newBPC_T_40 = bits(_newBPC_WIRE_1, 8, 7) connect newBPC_1.tmatch, _newBPC_T_40 node _newBPC_T_41 = bits(_newBPC_WIRE_1, 10, 9) connect newBPC_1.zero, _newBPC_T_41 node _newBPC_T_42 = bits(_newBPC_WIRE_1, 11, 11) connect newBPC_1.chain, _newBPC_T_42 node _newBPC_T_43 = bits(_newBPC_WIRE_1, 12, 12) connect newBPC_1.action, _newBPC_T_43 node _newBPC_T_44 = bits(_newBPC_WIRE_1, 20, 13) connect newBPC_1.reserved, _newBPC_T_44 node _newBPC_T_45 = bits(_newBPC_WIRE_1, 26, 21) connect newBPC_1.maskmax, _newBPC_T_45 node _newBPC_T_46 = bits(_newBPC_WIRE_1, 27, 27) connect newBPC_1.dmode, _newBPC_T_46 node _newBPC_T_47 = bits(_newBPC_WIRE_1, 31, 28) connect newBPC_1.ttype, _newBPC_T_47 node _dMode_T_3 = and(newBPC_1.dmode, reg_debug) node _dMode_T_4 = eq(reg_bp[0].control.chain, UInt<1>(0h0)) node _dMode_T_5 = or(reg_bp[0].control.dmode, _dMode_T_4) node dMode_1 = and(_dMode_T_3, _dMode_T_5) connect reg_bp[1].control.dmode, dMode_1 node _T_2311 = gt(newBPC_1.action, UInt<1>(0h1)) node _T_2312 = or(dMode_1, _T_2311) when _T_2312 : connect reg_bp[1].control.action, newBPC_1.action else : connect reg_bp[1].control.action, UInt<1>(0h0) node _reg_bp_1_control_chain_T = or(reg_bp[0].control.chain, UInt<1>(0h1)) node _reg_bp_1_control_chain_T_1 = eq(_reg_bp_1_control_chain_T, UInt<1>(0h0)) node _reg_bp_1_control_chain_T_2 = and(newBPC_1.chain, _reg_bp_1_control_chain_T_1) node _reg_bp_1_control_chain_T_3 = eq(UInt<1>(0h1), UInt<1>(0h0)) node _reg_bp_1_control_chain_T_4 = or(dMode_1, _reg_bp_1_control_chain_T_3) node _reg_bp_1_control_chain_T_5 = and(_reg_bp_1_control_chain_T_2, _reg_bp_1_control_chain_T_4) connect reg_bp[1].control.chain, _reg_bp_1_control_chain_T_5 node _T_2313 = eq(reg_pmp[0].cfg.l, UInt<1>(0h0)) node _T_2314 = and(decoded_addr_184_2, _T_2313) when _T_2314 : node _newCfg_T = shr(wdata, 0) wire newCfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE : UInt<8> connect _newCfg_WIRE, _newCfg_T node _newCfg_T_1 = bits(_newCfg_WIRE, 0, 0) connect newCfg.r, _newCfg_T_1 node _newCfg_T_2 = bits(_newCfg_WIRE, 1, 1) connect newCfg.w, _newCfg_T_2 node _newCfg_T_3 = bits(_newCfg_WIRE, 2, 2) connect newCfg.x, _newCfg_T_3 node _newCfg_T_4 = bits(_newCfg_WIRE, 4, 3) connect newCfg.a, _newCfg_T_4 node _newCfg_T_5 = bits(_newCfg_WIRE, 6, 5) connect newCfg.res, _newCfg_T_5 node _newCfg_T_6 = bits(_newCfg_WIRE, 7, 7) connect newCfg.l, _newCfg_T_6 connect reg_pmp[0].cfg, newCfg node _reg_pmp_0_cfg_w_T = and(newCfg.w, newCfg.r) connect reg_pmp[0].cfg.w, _reg_pmp_0_cfg_w_T node _T_2315 = bits(reg_pmp[1].cfg.a, 1, 1) node _T_2316 = eq(_T_2315, UInt<1>(0h0)) node _T_2317 = bits(reg_pmp[1].cfg.a, 0, 0) node _T_2318 = and(_T_2316, _T_2317) node _T_2319 = and(reg_pmp[1].cfg.l, _T_2318) node _T_2320 = or(reg_pmp[0].cfg.l, _T_2319) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) node _T_2322 = and(decoded_addr_130_2, _T_2321) when _T_2322 : connect reg_pmp[0].addr, wdata node _T_2323 = eq(reg_pmp[1].cfg.l, UInt<1>(0h0)) node _T_2324 = and(decoded_addr_184_2, _T_2323) when _T_2324 : node _newCfg_T_7 = shr(wdata, 8) wire newCfg_1 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_1 : UInt<8> connect _newCfg_WIRE_1, _newCfg_T_7 node _newCfg_T_8 = bits(_newCfg_WIRE_1, 0, 0) connect newCfg_1.r, _newCfg_T_8 node _newCfg_T_9 = bits(_newCfg_WIRE_1, 1, 1) connect newCfg_1.w, _newCfg_T_9 node _newCfg_T_10 = bits(_newCfg_WIRE_1, 2, 2) connect newCfg_1.x, _newCfg_T_10 node _newCfg_T_11 = bits(_newCfg_WIRE_1, 4, 3) connect newCfg_1.a, _newCfg_T_11 node _newCfg_T_12 = bits(_newCfg_WIRE_1, 6, 5) connect newCfg_1.res, _newCfg_T_12 node _newCfg_T_13 = bits(_newCfg_WIRE_1, 7, 7) connect newCfg_1.l, _newCfg_T_13 connect reg_pmp[1].cfg, newCfg_1 node _reg_pmp_1_cfg_w_T = and(newCfg_1.w, newCfg_1.r) connect reg_pmp[1].cfg.w, _reg_pmp_1_cfg_w_T node _T_2325 = bits(reg_pmp[2].cfg.a, 1, 1) node _T_2326 = eq(_T_2325, UInt<1>(0h0)) node _T_2327 = bits(reg_pmp[2].cfg.a, 0, 0) node _T_2328 = and(_T_2326, _T_2327) node _T_2329 = and(reg_pmp[2].cfg.l, _T_2328) node _T_2330 = or(reg_pmp[1].cfg.l, _T_2329) node _T_2331 = eq(_T_2330, UInt<1>(0h0)) node _T_2332 = and(decoded_addr_11_2, _T_2331) when _T_2332 : connect reg_pmp[1].addr, wdata node _T_2333 = eq(reg_pmp[2].cfg.l, UInt<1>(0h0)) node _T_2334 = and(decoded_addr_184_2, _T_2333) when _T_2334 : node _newCfg_T_14 = shr(wdata, 16) wire newCfg_2 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_2 : UInt<8> connect _newCfg_WIRE_2, _newCfg_T_14 node _newCfg_T_15 = bits(_newCfg_WIRE_2, 0, 0) connect newCfg_2.r, _newCfg_T_15 node _newCfg_T_16 = bits(_newCfg_WIRE_2, 1, 1) connect newCfg_2.w, _newCfg_T_16 node _newCfg_T_17 = bits(_newCfg_WIRE_2, 2, 2) connect newCfg_2.x, _newCfg_T_17 node _newCfg_T_18 = bits(_newCfg_WIRE_2, 4, 3) connect newCfg_2.a, _newCfg_T_18 node _newCfg_T_19 = bits(_newCfg_WIRE_2, 6, 5) connect newCfg_2.res, _newCfg_T_19 node _newCfg_T_20 = bits(_newCfg_WIRE_2, 7, 7) connect newCfg_2.l, _newCfg_T_20 connect reg_pmp[2].cfg, newCfg_2 node _reg_pmp_2_cfg_w_T = and(newCfg_2.w, newCfg_2.r) connect reg_pmp[2].cfg.w, _reg_pmp_2_cfg_w_T node _T_2335 = bits(reg_pmp[3].cfg.a, 1, 1) node _T_2336 = eq(_T_2335, UInt<1>(0h0)) node _T_2337 = bits(reg_pmp[3].cfg.a, 0, 0) node _T_2338 = and(_T_2336, _T_2337) node _T_2339 = and(reg_pmp[3].cfg.l, _T_2338) node _T_2340 = or(reg_pmp[2].cfg.l, _T_2339) node _T_2341 = eq(_T_2340, UInt<1>(0h0)) node _T_2342 = and(decoded_addr_161_2, _T_2341) when _T_2342 : connect reg_pmp[2].addr, wdata node _T_2343 = eq(reg_pmp[3].cfg.l, UInt<1>(0h0)) node _T_2344 = and(decoded_addr_184_2, _T_2343) when _T_2344 : node _newCfg_T_21 = shr(wdata, 24) wire newCfg_3 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_3 : UInt<8> connect _newCfg_WIRE_3, _newCfg_T_21 node _newCfg_T_22 = bits(_newCfg_WIRE_3, 0, 0) connect newCfg_3.r, _newCfg_T_22 node _newCfg_T_23 = bits(_newCfg_WIRE_3, 1, 1) connect newCfg_3.w, _newCfg_T_23 node _newCfg_T_24 = bits(_newCfg_WIRE_3, 2, 2) connect newCfg_3.x, _newCfg_T_24 node _newCfg_T_25 = bits(_newCfg_WIRE_3, 4, 3) connect newCfg_3.a, _newCfg_T_25 node _newCfg_T_26 = bits(_newCfg_WIRE_3, 6, 5) connect newCfg_3.res, _newCfg_T_26 node _newCfg_T_27 = bits(_newCfg_WIRE_3, 7, 7) connect newCfg_3.l, _newCfg_T_27 connect reg_pmp[3].cfg, newCfg_3 node _reg_pmp_3_cfg_w_T = and(newCfg_3.w, newCfg_3.r) connect reg_pmp[3].cfg.w, _reg_pmp_3_cfg_w_T node _T_2345 = bits(reg_pmp[4].cfg.a, 1, 1) node _T_2346 = eq(_T_2345, UInt<1>(0h0)) node _T_2347 = bits(reg_pmp[4].cfg.a, 0, 0) node _T_2348 = and(_T_2346, _T_2347) node _T_2349 = and(reg_pmp[4].cfg.l, _T_2348) node _T_2350 = or(reg_pmp[3].cfg.l, _T_2349) node _T_2351 = eq(_T_2350, UInt<1>(0h0)) node _T_2352 = and(decoded_addr_107_2, _T_2351) when _T_2352 : connect reg_pmp[3].addr, wdata node _T_2353 = eq(reg_pmp[4].cfg.l, UInt<1>(0h0)) node _T_2354 = and(decoded_addr_169_2, _T_2353) when _T_2354 : node _newCfg_T_28 = shr(wdata, 0) wire newCfg_4 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_4 : UInt<8> connect _newCfg_WIRE_4, _newCfg_T_28 node _newCfg_T_29 = bits(_newCfg_WIRE_4, 0, 0) connect newCfg_4.r, _newCfg_T_29 node _newCfg_T_30 = bits(_newCfg_WIRE_4, 1, 1) connect newCfg_4.w, _newCfg_T_30 node _newCfg_T_31 = bits(_newCfg_WIRE_4, 2, 2) connect newCfg_4.x, _newCfg_T_31 node _newCfg_T_32 = bits(_newCfg_WIRE_4, 4, 3) connect newCfg_4.a, _newCfg_T_32 node _newCfg_T_33 = bits(_newCfg_WIRE_4, 6, 5) connect newCfg_4.res, _newCfg_T_33 node _newCfg_T_34 = bits(_newCfg_WIRE_4, 7, 7) connect newCfg_4.l, _newCfg_T_34 connect reg_pmp[4].cfg, newCfg_4 node _reg_pmp_4_cfg_w_T = and(newCfg_4.w, newCfg_4.r) connect reg_pmp[4].cfg.w, _reg_pmp_4_cfg_w_T node _T_2355 = bits(reg_pmp[5].cfg.a, 1, 1) node _T_2356 = eq(_T_2355, UInt<1>(0h0)) node _T_2357 = bits(reg_pmp[5].cfg.a, 0, 0) node _T_2358 = and(_T_2356, _T_2357) node _T_2359 = and(reg_pmp[5].cfg.l, _T_2358) node _T_2360 = or(reg_pmp[4].cfg.l, _T_2359) node _T_2361 = eq(_T_2360, UInt<1>(0h0)) node _T_2362 = and(decoded_addr_65_2, _T_2361) when _T_2362 : connect reg_pmp[4].addr, wdata node _T_2363 = eq(reg_pmp[5].cfg.l, UInt<1>(0h0)) node _T_2364 = and(decoded_addr_169_2, _T_2363) when _T_2364 : node _newCfg_T_35 = shr(wdata, 8) wire newCfg_5 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_5 : UInt<8> connect _newCfg_WIRE_5, _newCfg_T_35 node _newCfg_T_36 = bits(_newCfg_WIRE_5, 0, 0) connect newCfg_5.r, _newCfg_T_36 node _newCfg_T_37 = bits(_newCfg_WIRE_5, 1, 1) connect newCfg_5.w, _newCfg_T_37 node _newCfg_T_38 = bits(_newCfg_WIRE_5, 2, 2) connect newCfg_5.x, _newCfg_T_38 node _newCfg_T_39 = bits(_newCfg_WIRE_5, 4, 3) connect newCfg_5.a, _newCfg_T_39 node _newCfg_T_40 = bits(_newCfg_WIRE_5, 6, 5) connect newCfg_5.res, _newCfg_T_40 node _newCfg_T_41 = bits(_newCfg_WIRE_5, 7, 7) connect newCfg_5.l, _newCfg_T_41 connect reg_pmp[5].cfg, newCfg_5 node _reg_pmp_5_cfg_w_T = and(newCfg_5.w, newCfg_5.r) connect reg_pmp[5].cfg.w, _reg_pmp_5_cfg_w_T node _T_2365 = bits(reg_pmp[6].cfg.a, 1, 1) node _T_2366 = eq(_T_2365, UInt<1>(0h0)) node _T_2367 = bits(reg_pmp[6].cfg.a, 0, 0) node _T_2368 = and(_T_2366, _T_2367) node _T_2369 = and(reg_pmp[6].cfg.l, _T_2368) node _T_2370 = or(reg_pmp[5].cfg.l, _T_2369) node _T_2371 = eq(_T_2370, UInt<1>(0h0)) node _T_2372 = and(decoded_addr_26_2, _T_2371) when _T_2372 : connect reg_pmp[5].addr, wdata node _T_2373 = eq(reg_pmp[6].cfg.l, UInt<1>(0h0)) node _T_2374 = and(decoded_addr_169_2, _T_2373) when _T_2374 : node _newCfg_T_42 = shr(wdata, 16) wire newCfg_6 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_6 : UInt<8> connect _newCfg_WIRE_6, _newCfg_T_42 node _newCfg_T_43 = bits(_newCfg_WIRE_6, 0, 0) connect newCfg_6.r, _newCfg_T_43 node _newCfg_T_44 = bits(_newCfg_WIRE_6, 1, 1) connect newCfg_6.w, _newCfg_T_44 node _newCfg_T_45 = bits(_newCfg_WIRE_6, 2, 2) connect newCfg_6.x, _newCfg_T_45 node _newCfg_T_46 = bits(_newCfg_WIRE_6, 4, 3) connect newCfg_6.a, _newCfg_T_46 node _newCfg_T_47 = bits(_newCfg_WIRE_6, 6, 5) connect newCfg_6.res, _newCfg_T_47 node _newCfg_T_48 = bits(_newCfg_WIRE_6, 7, 7) connect newCfg_6.l, _newCfg_T_48 connect reg_pmp[6].cfg, newCfg_6 node _reg_pmp_6_cfg_w_T = and(newCfg_6.w, newCfg_6.r) connect reg_pmp[6].cfg.w, _reg_pmp_6_cfg_w_T node _T_2375 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_2376 = eq(_T_2375, UInt<1>(0h0)) node _T_2377 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_2378 = and(_T_2376, _T_2377) node _T_2379 = and(reg_pmp[7].cfg.l, _T_2378) node _T_2380 = or(reg_pmp[6].cfg.l, _T_2379) node _T_2381 = eq(_T_2380, UInt<1>(0h0)) node _T_2382 = and(decoded_addr_178_2, _T_2381) when _T_2382 : connect reg_pmp[6].addr, wdata node _T_2383 = eq(reg_pmp[7].cfg.l, UInt<1>(0h0)) node _T_2384 = and(decoded_addr_169_2, _T_2383) when _T_2384 : node _newCfg_T_49 = shr(wdata, 24) wire newCfg_7 : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>} wire _newCfg_WIRE_7 : UInt<8> connect _newCfg_WIRE_7, _newCfg_T_49 node _newCfg_T_50 = bits(_newCfg_WIRE_7, 0, 0) connect newCfg_7.r, _newCfg_T_50 node _newCfg_T_51 = bits(_newCfg_WIRE_7, 1, 1) connect newCfg_7.w, _newCfg_T_51 node _newCfg_T_52 = bits(_newCfg_WIRE_7, 2, 2) connect newCfg_7.x, _newCfg_T_52 node _newCfg_T_53 = bits(_newCfg_WIRE_7, 4, 3) connect newCfg_7.a, _newCfg_T_53 node _newCfg_T_54 = bits(_newCfg_WIRE_7, 6, 5) connect newCfg_7.res, _newCfg_T_54 node _newCfg_T_55 = bits(_newCfg_WIRE_7, 7, 7) connect newCfg_7.l, _newCfg_T_55 connect reg_pmp[7].cfg, newCfg_7 node _reg_pmp_7_cfg_w_T = and(newCfg_7.w, newCfg_7.r) connect reg_pmp[7].cfg.w, _reg_pmp_7_cfg_w_T node _T_2385 = bits(reg_pmp[7].cfg.a, 1, 1) node _T_2386 = eq(_T_2385, UInt<1>(0h0)) node _T_2387 = bits(reg_pmp[7].cfg.a, 0, 0) node _T_2388 = and(_T_2386, _T_2387) node _T_2389 = and(reg_pmp[7].cfg.l, _T_2388) node _T_2390 = or(reg_pmp[7].cfg.l, _T_2389) node _T_2391 = eq(_T_2390, UInt<1>(0h0)) node _T_2392 = and(decoded_addr_146_2, _T_2391) when _T_2392 : connect reg_pmp[7].addr, wdata when decoded_addr_24_2 : node _reg_custom_0_T = and(wdata, UInt<32>(0h8)) node _reg_custom_0_T_1 = not(UInt<32>(0h8)) node _reg_custom_0_T_2 = and(reg_custom_0, _reg_custom_0_T_1) node _reg_custom_0_T_3 = or(_reg_custom_0_T, _reg_custom_0_T_2) connect reg_custom_0, _reg_custom_0_T_3 connect io.customCSRs[0].wen, UInt<1>(0h1) when decoded_addr_3_2 : node _reg_custom_1_T = and(wdata, UInt<32>(0h0)) node _reg_custom_1_T_1 = not(UInt<32>(0h0)) node _reg_custom_1_T_2 = and(reg_custom_1, _reg_custom_1_T_1) node _reg_custom_1_T_3 = or(_reg_custom_1_T, _reg_custom_1_T_2) connect reg_custom_1, _reg_custom_1_T_3 connect io.customCSRs[1].wen, UInt<1>(0h1) when decoded_addr_48_2 : node _reg_custom_2_T = and(wdata, UInt<32>(0h0)) node _reg_custom_2_T_1 = not(UInt<32>(0h0)) node _reg_custom_2_T_2 = and(reg_custom_2, _reg_custom_2_T_1) node _reg_custom_2_T_3 = or(_reg_custom_2_T, _reg_custom_2_T_2) connect reg_custom_2, _reg_custom_2_T_3 connect io.customCSRs[2].wen, UInt<1>(0h1) when decoded_addr_163_2 : node _reg_custom_3_T = and(wdata, UInt<32>(0h0)) node _reg_custom_3_T_1 = not(UInt<32>(0h0)) node _reg_custom_3_T_2 = and(reg_custom_3, _reg_custom_3_T_1) node _reg_custom_3_T_3 = or(_reg_custom_3_T, _reg_custom_3_T_2) connect reg_custom_3, _reg_custom_3_T_3 connect io.customCSRs[3].wen, UInt<1>(0h1) when io.customCSRs[0].set : node _reg_custom_0_T_4 = and(io.customCSRs[0].sdata, UInt<32>(0h8)) node _reg_custom_0_T_5 = not(UInt<32>(0h8)) node _reg_custom_0_T_6 = and(reg_custom_0, _reg_custom_0_T_5) node _reg_custom_0_T_7 = or(_reg_custom_0_T_4, _reg_custom_0_T_6) connect reg_custom_0, _reg_custom_0_T_7 when io.customCSRs[1].set : node _reg_custom_1_T_4 = and(io.customCSRs[1].sdata, UInt<32>(0h0)) node _reg_custom_1_T_5 = not(UInt<32>(0h0)) node _reg_custom_1_T_6 = and(reg_custom_1, _reg_custom_1_T_5) node _reg_custom_1_T_7 = or(_reg_custom_1_T_4, _reg_custom_1_T_6) connect reg_custom_1, _reg_custom_1_T_7 when io.customCSRs[2].set : node _reg_custom_2_T_4 = and(io.customCSRs[2].sdata, UInt<32>(0h0)) node _reg_custom_2_T_5 = not(UInt<32>(0h0)) node _reg_custom_2_T_6 = and(reg_custom_2, _reg_custom_2_T_5) node _reg_custom_2_T_7 = or(_reg_custom_2_T_4, _reg_custom_2_T_6) connect reg_custom_2, _reg_custom_2_T_7 when io.customCSRs[3].set : node _reg_custom_3_T_4 = and(io.customCSRs[3].sdata, UInt<32>(0h0)) node _reg_custom_3_T_5 = not(UInt<32>(0h0)) node _reg_custom_3_T_6 = and(reg_custom_3, _reg_custom_3_T_5) node _reg_custom_3_T_7 = or(_reg_custom_3_T_4, _reg_custom_3_T_6) connect reg_custom_3, _reg_custom_3_T_7 node _T_2393 = asUInt(reset) when _T_2393 : connect reg_satp.mode, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_satp.mode, UInt<1>(0h0) connect reg_satp.ppn, UInt<1>(0h0) connect reg_satp.asid, UInt<1>(0h0) connect reg_vsatp.mode, UInt<1>(0h0) connect reg_vsatp.ppn, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.mode, UInt<1>(0h0) connect reg_hgatp.ppn, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_satp.asid, UInt<1>(0h0) connect reg_vsatp.asid, UInt<1>(0h0) connect reg_hgatp.asid, UInt<1>(0h0) connect reg_vsstatus.xs, UInt<1>(0h0) connect reg_tselect, UInt<1>(0h0) connect reg_bp[0].control.ttype, UInt<2>(0h2) connect reg_bp[0].control.maskmax, UInt<3>(0h4) connect reg_bp[0].control.reserved, UInt<1>(0h0) connect reg_bp[0].control.zero, UInt<1>(0h0) connect reg_bp[0].control.h, UInt<1>(0h0) connect reg_bp[0].control.s, UInt<1>(0h0) connect reg_bp[0].control.u, UInt<1>(0h0) connect reg_bp[0].control.m, UInt<1>(0h1) node _T_2394 = asUInt(reset) when _T_2394 : connect reg_bp[0].control.action, UInt<1>(0h0) connect reg_bp[0].control.dmode, UInt<1>(0h0) connect reg_bp[0].control.chain, UInt<1>(0h0) connect reg_bp[0].control.r, UInt<1>(0h0) connect reg_bp[0].control.w, UInt<1>(0h0) connect reg_bp[0].control.x, UInt<1>(0h0) connect reg_bp[1].control.ttype, UInt<2>(0h2) connect reg_bp[1].control.maskmax, UInt<3>(0h4) connect reg_bp[1].control.reserved, UInt<1>(0h0) connect reg_bp[1].control.zero, UInt<1>(0h0) connect reg_bp[1].control.h, UInt<1>(0h0) connect reg_bp[1].control.s, UInt<1>(0h0) connect reg_bp[1].control.u, UInt<1>(0h0) connect reg_bp[1].control.m, UInt<1>(0h1) node _T_2395 = asUInt(reset) when _T_2395 : connect reg_bp[1].control.action, UInt<1>(0h0) connect reg_bp[1].control.dmode, UInt<1>(0h0) connect reg_bp[1].control.chain, UInt<1>(0h0) connect reg_bp[1].control.r, UInt<1>(0h0) connect reg_bp[1].control.w, UInt<1>(0h0) connect reg_bp[1].control.x, UInt<1>(0h0) connect reg_bp[0].textra.mselect, UInt<1>(0h0) connect reg_bp[0].textra.sselect, UInt<1>(0h0) connect reg_bp[1].textra.mselect, UInt<1>(0h0) connect reg_bp[1].textra.sselect, UInt<1>(0h0) wire _reg_bp_1_WIRE : { control : { ttype : UInt<4>, dmode : UInt<1>, maskmax : UInt<6>, reserved : UInt<8>, action : UInt<1>, chain : UInt<1>, zero : UInt<2>, tmatch : UInt<2>, m : UInt<1>, h : UInt<1>, s : UInt<1>, u : UInt<1>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, address : UInt<32>, textra : { mvalue : UInt<0>, mselect : UInt<1>, pad2 : UInt<23>, svalue : UInt<0>, pad1 : UInt<1>, sselect : UInt<1>}} connect _reg_bp_1_WIRE.textra.sselect, UInt<1>(0h0) connect _reg_bp_1_WIRE.textra.pad1, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.svalue connect _reg_bp_1_WIRE.textra.pad2, UInt<23>(0h0) connect _reg_bp_1_WIRE.textra.mselect, UInt<1>(0h0) invalidate _reg_bp_1_WIRE.textra.mvalue connect _reg_bp_1_WIRE.address, UInt<32>(0h0) connect _reg_bp_1_WIRE.control.r, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.w, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.x, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.u, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.s, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.h, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.m, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.tmatch, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.zero, UInt<2>(0h0) connect _reg_bp_1_WIRE.control.chain, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.action, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.reserved, UInt<8>(0h0) connect _reg_bp_1_WIRE.control.maskmax, UInt<6>(0h0) connect _reg_bp_1_WIRE.control.dmode, UInt<1>(0h0) connect _reg_bp_1_WIRE.control.ttype, UInt<4>(0h0) connect reg_bp[1], _reg_bp_1_WIRE connect reg_pmp[0].cfg.res, UInt<1>(0h0) node _T_2396 = asUInt(reset) when _T_2396 : connect reg_pmp[0].cfg.a, UInt<1>(0h0) connect reg_pmp[0].cfg.l, UInt<1>(0h0) connect reg_pmp[1].cfg.res, UInt<1>(0h0) node _T_2397 = asUInt(reset) when _T_2397 : connect reg_pmp[1].cfg.a, UInt<1>(0h0) connect reg_pmp[1].cfg.l, UInt<1>(0h0) connect reg_pmp[2].cfg.res, UInt<1>(0h0) node _T_2398 = asUInt(reset) when _T_2398 : connect reg_pmp[2].cfg.a, UInt<1>(0h0) connect reg_pmp[2].cfg.l, UInt<1>(0h0) connect reg_pmp[3].cfg.res, UInt<1>(0h0) node _T_2399 = asUInt(reset) when _T_2399 : connect reg_pmp[3].cfg.a, UInt<1>(0h0) connect reg_pmp[3].cfg.l, UInt<1>(0h0) connect reg_pmp[4].cfg.res, UInt<1>(0h0) node _T_2400 = asUInt(reset) when _T_2400 : connect reg_pmp[4].cfg.a, UInt<1>(0h0) connect reg_pmp[4].cfg.l, UInt<1>(0h0) connect reg_pmp[5].cfg.res, UInt<1>(0h0) node _T_2401 = asUInt(reset) when _T_2401 : connect reg_pmp[5].cfg.a, UInt<1>(0h0) connect reg_pmp[5].cfg.l, UInt<1>(0h0) connect reg_pmp[6].cfg.res, UInt<1>(0h0) node _T_2402 = asUInt(reset) when _T_2402 : connect reg_pmp[6].cfg.a, UInt<1>(0h0) connect reg_pmp[6].cfg.l, UInt<1>(0h0) connect reg_pmp[7].cfg.res, UInt<1>(0h0) node _T_2403 = asUInt(reset) when _T_2403 : connect reg_pmp[7].cfg.a, UInt<1>(0h0) connect reg_pmp[7].cfg.l, UInt<1>(0h0) node _io_trace_0_exception_T = geq(io.retire, UInt<1>(0h0)) node _io_trace_0_exception_T_1 = and(_io_trace_0_exception_T, exception) connect io.trace[0].exception, _io_trace_0_exception_T_1 node _io_trace_0_valid_T = gt(io.retire, UInt<1>(0h0)) node _io_trace_0_valid_T_1 = or(_io_trace_0_valid_T, io.trace[0].exception) connect io.trace[0].valid, _io_trace_0_valid_T_1 connect io.trace[0].insn, io.inst[0] connect io.trace[0].iaddr, io.pc node _io_trace_0_priv_T = cat(reg_debug, reg_mstatus.prv) connect io.trace[0].priv, _io_trace_0_priv_T connect io.trace[0].cause, cause node _io_trace_0_interrupt_T = bits(cause, 31, 31) connect io.trace[0].interrupt, _io_trace_0_interrupt_T connect io.trace[0].tval, io.tval
module CSRFile( // @[CSR.scala:377:7] input clock, // @[CSR.scala:377:7] input reset, // @[CSR.scala:377:7] input io_ungated_clock, // @[CSR.scala:384:14] input io_interrupts_debug, // @[CSR.scala:384:14] input io_interrupts_mtip, // @[CSR.scala:384:14] input io_interrupts_msip, // @[CSR.scala:384:14] input io_interrupts_meip, // @[CSR.scala:384:14] input io_hartid, // @[CSR.scala:384:14] input [11:0] io_rw_addr, // @[CSR.scala:384:14] input [2:0] io_rw_cmd, // @[CSR.scala:384:14] output [31:0] io_rw_rdata, // @[CSR.scala:384:14] input [31:0] io_rw_wdata, // @[CSR.scala:384:14] input [31:0] io_decode_0_inst, // @[CSR.scala:384:14] output io_decode_0_read_illegal, // @[CSR.scala:384:14] output io_decode_0_write_illegal, // @[CSR.scala:384:14] output io_decode_0_write_flush, // @[CSR.scala:384:14] output io_decode_0_system_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_access_illegal, // @[CSR.scala:384:14] output io_decode_0_virtual_system_illegal, // @[CSR.scala:384:14] output io_csr_stall, // @[CSR.scala:384:14] output io_eret, // @[CSR.scala:384:14] output io_singleStep, // @[CSR.scala:384:14] output io_status_debug, // @[CSR.scala:384:14] output io_status_cease, // @[CSR.scala:384:14] output io_status_wfi, // @[CSR.scala:384:14] output [31:0] io_status_isa, // @[CSR.scala:384:14] output io_status_dv, // @[CSR.scala:384:14] output io_status_v, // @[CSR.scala:384:14] output io_status_mpv, // @[CSR.scala:384:14] output io_status_gva, // @[CSR.scala:384:14] output [1:0] io_status_mpp, // @[CSR.scala:384:14] output io_status_mpie, // @[CSR.scala:384:14] output io_status_mie, // @[CSR.scala:384:14] output io_gstatus_debug, // @[CSR.scala:384:14] output io_gstatus_cease, // @[CSR.scala:384:14] output io_gstatus_wfi, // @[CSR.scala:384:14] output [31:0] io_gstatus_isa, // @[CSR.scala:384:14] output [1:0] io_gstatus_dprv, // @[CSR.scala:384:14] output io_gstatus_dv, // @[CSR.scala:384:14] output [1:0] io_gstatus_prv, // @[CSR.scala:384:14] output io_gstatus_v, // @[CSR.scala:384:14] output io_gstatus_sd, // @[CSR.scala:384:14] output [22:0] io_gstatus_zero2, // @[CSR.scala:384:14] output io_gstatus_mpv, // @[CSR.scala:384:14] output io_gstatus_gva, // @[CSR.scala:384:14] output io_gstatus_mbe, // @[CSR.scala:384:14] output io_gstatus_sbe, // @[CSR.scala:384:14] output [1:0] io_gstatus_sxl, // @[CSR.scala:384:14] output io_gstatus_sd_rv32, // @[CSR.scala:384:14] output [7:0] io_gstatus_zero1, // @[CSR.scala:384:14] output io_gstatus_tsr, // @[CSR.scala:384:14] output io_gstatus_tw, // @[CSR.scala:384:14] output io_gstatus_tvm, // @[CSR.scala:384:14] output io_gstatus_mxr, // @[CSR.scala:384:14] output io_gstatus_sum, // @[CSR.scala:384:14] output io_gstatus_mprv, // @[CSR.scala:384:14] output [1:0] io_gstatus_fs, // @[CSR.scala:384:14] output [1:0] io_gstatus_mpp, // @[CSR.scala:384:14] output [1:0] io_gstatus_vs, // @[CSR.scala:384:14] output io_gstatus_spp, // @[CSR.scala:384:14] output io_gstatus_mpie, // @[CSR.scala:384:14] output io_gstatus_ube, // @[CSR.scala:384:14] output io_gstatus_spie, // @[CSR.scala:384:14] output io_gstatus_upie, // @[CSR.scala:384:14] output io_gstatus_mie, // @[CSR.scala:384:14] output io_gstatus_hie, // @[CSR.scala:384:14] output io_gstatus_sie, // @[CSR.scala:384:14] output io_gstatus_uie, // @[CSR.scala:384:14] output [31:0] io_evec, // @[CSR.scala:384:14] input io_exception, // @[CSR.scala:384:14] input io_retire, // @[CSR.scala:384:14] input [31:0] io_cause, // @[CSR.scala:384:14] input [31:0] io_pc, // @[CSR.scala:384:14] input [31:0] io_tval, // @[CSR.scala:384:14] input [31:0] io_htval, // @[CSR.scala:384:14] input io_mhtinst_read_pseudo, // @[CSR.scala:384:14] input io_gva, // @[CSR.scala:384:14] output [31:0] io_time, // @[CSR.scala:384:14] output [2:0] io_fcsr_rm, // @[CSR.scala:384:14] output io_interrupt, // @[CSR.scala:384:14] output [31:0] io_interrupt_cause, // @[CSR.scala:384:14] output io_bp_0_control_dmode, // @[CSR.scala:384:14] output io_bp_0_control_action, // @[CSR.scala:384:14] output [1:0] io_bp_0_control_tmatch, // @[CSR.scala:384:14] output io_bp_0_control_x, // @[CSR.scala:384:14] output io_bp_0_control_w, // @[CSR.scala:384:14] output io_bp_0_control_r, // @[CSR.scala:384:14] output [31:0] io_bp_0_address, // @[CSR.scala:384:14] output [22:0] io_bp_0_textra_pad2, // @[CSR.scala:384:14] output io_bp_0_textra_pad1, // @[CSR.scala:384:14] output io_pmp_0_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_0_cfg_a, // @[CSR.scala:384:14] output io_pmp_0_cfg_x, // @[CSR.scala:384:14] output io_pmp_0_cfg_w, // @[CSR.scala:384:14] output io_pmp_0_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_0_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_0_mask, // @[CSR.scala:384:14] output io_pmp_1_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_1_cfg_a, // @[CSR.scala:384:14] output io_pmp_1_cfg_x, // @[CSR.scala:384:14] output io_pmp_1_cfg_w, // @[CSR.scala:384:14] output io_pmp_1_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_1_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_1_mask, // @[CSR.scala:384:14] output io_pmp_2_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_2_cfg_a, // @[CSR.scala:384:14] output io_pmp_2_cfg_x, // @[CSR.scala:384:14] output io_pmp_2_cfg_w, // @[CSR.scala:384:14] output io_pmp_2_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_2_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_2_mask, // @[CSR.scala:384:14] output io_pmp_3_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_3_cfg_a, // @[CSR.scala:384:14] output io_pmp_3_cfg_x, // @[CSR.scala:384:14] output io_pmp_3_cfg_w, // @[CSR.scala:384:14] output io_pmp_3_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_3_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_3_mask, // @[CSR.scala:384:14] output io_pmp_4_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_4_cfg_a, // @[CSR.scala:384:14] output io_pmp_4_cfg_x, // @[CSR.scala:384:14] output io_pmp_4_cfg_w, // @[CSR.scala:384:14] output io_pmp_4_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_4_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_4_mask, // @[CSR.scala:384:14] output io_pmp_5_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_5_cfg_a, // @[CSR.scala:384:14] output io_pmp_5_cfg_x, // @[CSR.scala:384:14] output io_pmp_5_cfg_w, // @[CSR.scala:384:14] output io_pmp_5_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_5_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_5_mask, // @[CSR.scala:384:14] output io_pmp_6_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_6_cfg_a, // @[CSR.scala:384:14] output io_pmp_6_cfg_x, // @[CSR.scala:384:14] output io_pmp_6_cfg_w, // @[CSR.scala:384:14] output io_pmp_6_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_6_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_6_mask, // @[CSR.scala:384:14] output io_pmp_7_cfg_l, // @[CSR.scala:384:14] output [1:0] io_pmp_7_cfg_a, // @[CSR.scala:384:14] output io_pmp_7_cfg_x, // @[CSR.scala:384:14] output io_pmp_7_cfg_w, // @[CSR.scala:384:14] output io_pmp_7_cfg_r, // @[CSR.scala:384:14] output [29:0] io_pmp_7_addr, // @[CSR.scala:384:14] output [31:0] io_pmp_7_mask, // @[CSR.scala:384:14] output io_inhibit_cycle, // @[CSR.scala:384:14] input [31:0] io_inst_0, // @[CSR.scala:384:14] output io_trace_0_valid, // @[CSR.scala:384:14] output [31:0] io_trace_0_iaddr, // @[CSR.scala:384:14] output [31:0] io_trace_0_insn, // @[CSR.scala:384:14] output [2:0] io_trace_0_priv, // @[CSR.scala:384:14] output io_trace_0_exception, // @[CSR.scala:384:14] output io_trace_0_interrupt, // @[CSR.scala:384:14] output [31:0] io_trace_0_cause, // @[CSR.scala:384:14] output [31:0] io_trace_0_tval, // @[CSR.scala:384:14] output io_customCSRs_0_ren, // @[CSR.scala:384:14] output io_customCSRs_0_wen, // @[CSR.scala:384:14] output [31:0] io_customCSRs_0_wdata, // @[CSR.scala:384:14] output [31:0] io_customCSRs_0_value, // @[CSR.scala:384:14] output io_customCSRs_1_ren, // @[CSR.scala:384:14] output io_customCSRs_1_wen, // @[CSR.scala:384:14] output [31:0] io_customCSRs_1_wdata, // @[CSR.scala:384:14] output [31:0] io_customCSRs_1_value, // @[CSR.scala:384:14] output io_customCSRs_2_ren, // @[CSR.scala:384:14] output io_customCSRs_2_wen, // @[CSR.scala:384:14] output [31:0] io_customCSRs_2_wdata, // @[CSR.scala:384:14] output [31:0] io_customCSRs_2_value, // @[CSR.scala:384:14] output io_customCSRs_3_ren, // @[CSR.scala:384:14] output io_customCSRs_3_wen, // @[CSR.scala:384:14] output [31:0] io_customCSRs_3_wdata, // @[CSR.scala:384:14] output [31:0] io_customCSRs_3_value // @[CSR.scala:384:14] ); wire io_gstatus_sd_0; // @[CSR.scala:377:7] wire io_ungated_clock_0 = io_ungated_clock; // @[CSR.scala:377:7] wire io_interrupts_debug_0 = io_interrupts_debug; // @[CSR.scala:377:7] wire io_interrupts_mtip_0 = io_interrupts_mtip; // @[CSR.scala:377:7] wire io_interrupts_msip_0 = io_interrupts_msip; // @[CSR.scala:377:7] wire io_interrupts_meip_0 = io_interrupts_meip; // @[CSR.scala:377:7] wire io_hartid_0 = io_hartid; // @[CSR.scala:377:7] wire [11:0] io_rw_addr_0 = io_rw_addr; // @[CSR.scala:377:7] wire [2:0] io_rw_cmd_0 = io_rw_cmd; // @[CSR.scala:377:7] wire [31:0] io_rw_wdata_0 = io_rw_wdata; // @[CSR.scala:377:7] wire [31:0] io_decode_0_inst_0 = io_decode_0_inst; // @[CSR.scala:377:7] wire io_exception_0 = io_exception; // @[CSR.scala:377:7] wire io_retire_0 = io_retire; // @[CSR.scala:377:7] wire [31:0] io_cause_0 = io_cause; // @[CSR.scala:377:7] wire [31:0] io_pc_0 = io_pc; // @[CSR.scala:377:7] wire [31:0] io_tval_0 = io_tval; // @[CSR.scala:377:7] wire [31:0] io_htval_0 = io_htval; // @[CSR.scala:377:7] wire io_mhtinst_read_pseudo_0 = io_mhtinst_read_pseudo; // @[CSR.scala:377:7] wire io_gva_0 = io_gva; // @[CSR.scala:377:7] wire [31:0] io_inst_0_0 = io_inst_0; // @[CSR.scala:377:7] wire io_decode_0_fp_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_0_vector_illegal = 1'h1; // @[CSR.scala:377:7] wire io_decode_0_rocc_illegal = 1'h1; // @[CSR.scala:377:7] wire io_bp_0_control_m = 1'h1; // @[CSR.scala:377:7] wire sup_meip = 1'h1; // @[CSR.scala:406:19] wire sup_mtip = 1'h1; // @[CSR.scala:406:19] wire sup_msip = 1'h1; // @[CSR.scala:406:19] wire read_mnstatus_mie = 1'h1; // @[CSR.scala:675:31] wire sie_mask_sgeip_mask_sgeip = 1'h1; // @[CSR.scala:748:30] wire _allow_wfi_T = 1'h1; // @[CSR.scala:906:61] wire _allow_wfi_T_1 = 1'h1; // @[CSR.scala:906:42] wire _allow_wfi_T_2 = 1'h1; // @[CSR.scala:906:74] wire _allow_wfi_T_4 = 1'h1; // @[CSR.scala:906:112] wire _allow_wfi_T_5 = 1'h1; // @[CSR.scala:906:109] wire _allow_wfi_T_6 = 1'h1; // @[CSR.scala:906:90] wire allow_wfi = 1'h1; // @[CSR.scala:906:71] wire _allow_sfence_vma_T = 1'h1; // @[CSR.scala:907:60] wire _allow_sfence_vma_T_1 = 1'h1; // @[CSR.scala:907:41] wire _allow_sfence_vma_T_3 = 1'h1; // @[CSR.scala:907:73] wire allow_sfence_vma = 1'h1; // @[CSR.scala:907:70] wire _allow_hfence_vvma_T_1 = 1'h1; // @[CSR.scala:908:88] wire allow_hfence_vvma = 1'h1; // @[CSR.scala:908:50] wire _allow_hlsv_T_1 = 1'h1; // @[CSR.scala:909:81] wire _allow_hlsv_T_2 = 1'h1; // @[CSR.scala:909:92] wire allow_hlsv = 1'h1; // @[CSR.scala:909:43] wire _allow_sret_T = 1'h1; // @[CSR.scala:910:62] wire _allow_sret_T_1 = 1'h1; // @[CSR.scala:910:43] wire _allow_sret_T_3 = 1'h1; // @[CSR.scala:910:75] wire allow_sret = 1'h1; // @[CSR.scala:910:72] wire _allow_counter_T = 1'h1; // @[CSR.scala:912:42] wire _allow_counter_T_3 = 1'h1; // @[CSR.scala:912:52] wire _allow_counter_T_4 = 1'h1; // @[CSR.scala:913:8] wire _allow_counter_T_5 = 1'h1; // @[CSR.scala:913:46] wire _allow_counter_T_6 = 1'h1; // @[CSR.scala:913:27] wire _allow_counter_T_9 = 1'h1; // @[CSR.scala:913:57] wire _allow_counter_T_10 = 1'h1; // @[CSR.scala:912:86] wire _allow_counter_T_11 = 1'h1; // @[CSR.scala:914:8] wire _allow_counter_T_13 = 1'h1; // @[CSR.scala:914:27] wire _allow_counter_T_16 = 1'h1; // @[CSR.scala:914:45] wire allow_counter = 1'h1; // @[CSR.scala:913:91] wire _io_decode_0_fp_illegal_T = 1'h1; // @[CSR.scala:915:39] wire _io_decode_0_fp_illegal_T_1 = 1'h1; // @[CSR.scala:915:83] wire _io_decode_0_fp_illegal_T_3 = 1'h1; // @[CSR.scala:915:47] wire _io_decode_0_fp_illegal_T_6 = 1'h1; // @[CSR.scala:915:91] wire _io_decode_0_vector_illegal_T = 1'h1; // @[CSR.scala:916:43] wire _io_decode_0_vector_illegal_T_1 = 1'h1; // @[CSR.scala:916:87] wire _io_decode_0_vector_illegal_T_3 = 1'h1; // @[CSR.scala:916:51] wire _io_decode_0_vector_illegal_T_6 = 1'h1; // @[CSR.scala:916:95] wire _io_decode_0_rocc_illegal_T = 1'h1; // @[CSR.scala:919:41] wire _io_decode_0_rocc_illegal_T_1 = 1'h1; // @[CSR.scala:919:85] wire _io_decode_0_rocc_illegal_T_3 = 1'h1; // @[CSR.scala:919:49] wire _io_decode_0_rocc_illegal_T_6 = 1'h1; // @[CSR.scala:919:93] wire _csr_addr_legal_T_1 = 1'h1; // @[CSR.scala:920:42] wire _io_decode_0_virtual_access_illegal_T_9 = 1'h1; // @[CSR.scala:945:105] wire _io_decode_0_virtual_access_illegal_T_20 = 1'h1; // @[CSR.scala:946:53] wire _io_decode_0_virtual_access_illegal_T_25 = 1'h1; // @[CSR.scala:947:46] wire _io_decode_0_virtual_system_illegal_T_2 = 1'h1; // @[CSR.scala:953:34] wire _io_decode_0_virtual_system_illegal_T_4 = 1'h1; // @[CSR.scala:953:41] wire _io_decode_0_virtual_system_illegal_T_12 = 1'h1; // @[CSR.scala:954:64] wire _io_decode_0_virtual_system_illegal_T_17 = 1'h1; // @[CSR.scala:955:37] wire _cause_T = 1'h1; // @[CSR.scala:959:61] wire _reg_hstatus_spvp_T = 1'h1; // @[CSR.scala:1067:61] wire _en_T_19 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_43 = 1'h1; // @[CSR.scala:1096:71] wire _en_T_67 = 1'h1; // @[CSR.scala:1096:71] wire delegable_16 = 1'h1; // @[CSR.scala:1109:67] wire delegable_18 = 1'h1; // @[CSR.scala:1109:67] wire delegable_19 = 1'h1; // @[CSR.scala:1109:67] wire delegable_20 = 1'h1; // @[CSR.scala:1109:67] wire delegable_22 = 1'h1; // @[CSR.scala:1109:67] wire _csr_wen_T_5 = 1'h1; // @[CSR.scala:1222:59] wire _dMode_T_1 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_2 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_0_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _dMode_T_4 = 1'h1; // @[CSR.scala:1478:68] wire _dMode_T_5 = 1'h1; // @[CSR.scala:1478:65] wire _reg_bp_1_control_chain_T = 1'h1; // @[CSR.scala:1481:61] wire _io_trace_0_exception_T = 1'h1; // @[CSR.scala:1620:30] wire [1:0] io_status_dprv = 2'h3; // @[CSR.scala:377:7] wire [1:0] io_status_prv = 2'h3; // @[CSR.scala:377:7] wire [1:0] reset_mstatus_prv = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_mpp = 2'h3; // @[CSR.scala:391:34] wire [1:0] reset_dcsr_prv = 2'h3; // @[CSR.scala:400:31] wire [1:0] reset_mnstatus_mpp = 2'h3; // @[CSR.scala:516:35] wire [1:0] read_mnstatus_mpp = 2'h3; // @[CSR.scala:675:31] wire [1:0] _io_status_dprv_T_2 = 2'h3; // @[CSR.scala:1008:24] wire io_decode_0_fp_csr = 1'h0; // @[CSR.scala:377:7] wire io_decode_0_vector_csr = 1'h0; // @[CSR.scala:377:7] wire io_rw_stall = 1'h0; // @[CSR.scala:377:7] wire io_status_sd = 1'h0; // @[CSR.scala:377:7] wire io_status_mbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sbe = 1'h0; // @[CSR.scala:377:7] wire io_status_sd_rv32 = 1'h0; // @[CSR.scala:377:7] wire io_status_tsr = 1'h0; // @[CSR.scala:377:7] wire io_status_tw = 1'h0; // @[CSR.scala:377:7] wire io_status_tvm = 1'h0; // @[CSR.scala:377:7] wire io_status_mxr = 1'h0; // @[CSR.scala:377:7] wire io_status_sum = 1'h0; // @[CSR.scala:377:7] wire io_status_mprv = 1'h0; // @[CSR.scala:377:7] wire io_status_spp = 1'h0; // @[CSR.scala:377:7] wire io_status_ube = 1'h0; // @[CSR.scala:377:7] wire io_status_spie = 1'h0; // @[CSR.scala:377:7] wire io_status_upie = 1'h0; // @[CSR.scala:377:7] wire io_status_hie = 1'h0; // @[CSR.scala:377:7] wire io_status_sie = 1'h0; // @[CSR.scala:377:7] wire io_status_uie = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtsr = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtw = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vtvm = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_hu = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_spvp = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_spv = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_gva = 1'h0; // @[CSR.scala:377:7] wire io_hstatus_vsbe = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_debug_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_cease_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_wfi_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_dv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_v_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_gva_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sbe_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tsr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tw_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_tvm_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mxr_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sum_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mprv_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_spp_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mpie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_ube_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_spie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_upie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_mie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_hie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_sie_0 = 1'h0; // @[CSR.scala:377:7] wire io_gstatus_uie_0 = 1'h0; // @[CSR.scala:377:7] wire io_ptbr_mode = 1'h0; // @[CSR.scala:377:7] wire io_hgatp_mode = 1'h0; // @[CSR.scala:377:7] wire io_vsatp_mode = 1'h0; // @[CSR.scala:377:7] wire io_fcsr_flags_valid = 1'h0; // @[CSR.scala:377:7] wire io_rocc_interrupt = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_chain = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_h = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_s = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_control_u = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_mselect = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_pad1_0 = 1'h0; // @[CSR.scala:377:7] wire io_bp_0_textra_sselect = 1'h0; // @[CSR.scala:377:7] wire io_fiom = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_0_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_1_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_2_set = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_stall = 1'h0; // @[CSR.scala:377:7] wire io_customCSRs_3_set = 1'h0; // @[CSR.scala:377:7] wire _reset_mstatus_WIRE_debug = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_cease = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_wfi = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_dv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_v = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_gva = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sbe = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sd_rv32 = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tsr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tw = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_tvm = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mxr = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sum = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mprv = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spp = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mpie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_ube = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_spie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_upie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_mie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_hie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_sie = 1'h0; // @[CSR.scala:391:47] wire _reset_mstatus_WIRE_uie = 1'h0; // @[CSR.scala:391:47] wire reset_mstatus_debug = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_cease = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_wfi = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_dv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_v = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_gva = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sbe = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sd_rv32 = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tsr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tw = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_tvm = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mxr = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sum = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mprv = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spp = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mpie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_ube = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_spie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_upie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_mie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_hie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_sie = 1'h0; // @[CSR.scala:391:34] wire reset_mstatus_uie = 1'h0; // @[CSR.scala:391:34] wire _reset_dcsr_WIRE_ebreakm = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreakh = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaks = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_ebreaku = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_zero2 = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stopcycle = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_stoptime = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_v = 1'h0; // @[CSR.scala:400:44] wire _reset_dcsr_WIRE_step = 1'h0; // @[CSR.scala:400:44] wire reset_dcsr_ebreakm = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreakh = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaks = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_ebreaku = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_zero2 = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stopcycle = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_stoptime = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_v = 1'h0; // @[CSR.scala:400:31] wire reset_dcsr_step = 1'h0; // @[CSR.scala:400:31] wire sup_zero1 = 1'h0; // @[CSR.scala:406:19] wire sup_debug = 1'h0; // @[CSR.scala:406:19] wire sup_rocc = 1'h0; // @[CSR.scala:406:19] wire sup_sgeip = 1'h0; // @[CSR.scala:406:19] wire sup_vseip = 1'h0; // @[CSR.scala:406:19] wire sup_seip = 1'h0; // @[CSR.scala:406:19] wire sup_ueip = 1'h0; // @[CSR.scala:406:19] wire sup_vstip = 1'h0; // @[CSR.scala:406:19] wire sup_stip = 1'h0; // @[CSR.scala:406:19] wire sup_utip = 1'h0; // @[CSR.scala:406:19] wire sup_vssip = 1'h0; // @[CSR.scala:406:19] wire sup_ssip = 1'h0; // @[CSR.scala:406:19] wire sup_usip = 1'h0; // @[CSR.scala:406:19] wire del_zero1 = 1'h0; // @[CSR.scala:426:26] wire del_debug = 1'h0; // @[CSR.scala:426:26] wire del_rocc = 1'h0; // @[CSR.scala:426:26] wire del_sgeip = 1'h0; // @[CSR.scala:426:26] wire del_meip = 1'h0; // @[CSR.scala:426:26] wire del_vseip = 1'h0; // @[CSR.scala:426:26] wire del_seip = 1'h0; // @[CSR.scala:426:26] wire del_ueip = 1'h0; // @[CSR.scala:426:26] wire del_mtip = 1'h0; // @[CSR.scala:426:26] wire del_vstip = 1'h0; // @[CSR.scala:426:26] wire del_stip = 1'h0; // @[CSR.scala:426:26] wire del_utip = 1'h0; // @[CSR.scala:426:26] wire del_msip = 1'h0; // @[CSR.scala:426:26] wire del_vssip = 1'h0; // @[CSR.scala:426:26] wire del_ssip = 1'h0; // @[CSR.scala:426:26] wire del_usip = 1'h0; // @[CSR.scala:426:26] wire hi_hi_hi_hi = 1'h0; // @[CSR.scala:431:10] wire hi_hi_hi_hi_1 = 1'h0; // @[CSR.scala:431:50] wire _always_WIRE_zero1 = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_debug = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_rocc = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_sgeip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_meip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vseip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_seip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ueip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_mtip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vstip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_stip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_utip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_msip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_vssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_ssip = 1'h0; // @[CSR.scala:471:42] wire _always_WIRE_usip = 1'h0; // @[CSR.scala:471:42] wire always_zero1 = 1'h0; // @[CSR.scala:471:29] wire always_debug = 1'h0; // @[CSR.scala:471:29] wire always_rocc = 1'h0; // @[CSR.scala:471:29] wire always_sgeip = 1'h0; // @[CSR.scala:471:29] wire always_meip = 1'h0; // @[CSR.scala:471:29] wire always_vseip = 1'h0; // @[CSR.scala:471:29] wire always_seip = 1'h0; // @[CSR.scala:471:29] wire always_ueip = 1'h0; // @[CSR.scala:471:29] wire always_mtip = 1'h0; // @[CSR.scala:471:29] wire always_vstip = 1'h0; // @[CSR.scala:471:29] wire always_stip = 1'h0; // @[CSR.scala:471:29] wire always_utip = 1'h0; // @[CSR.scala:471:29] wire always_msip = 1'h0; // @[CSR.scala:471:29] wire always_vssip = 1'h0; // @[CSR.scala:471:29] wire always_ssip = 1'h0; // @[CSR.scala:471:29] wire always_usip = 1'h0; // @[CSR.scala:471:29] wire deleg_zero1 = 1'h0; // @[CSR.scala:476:28] wire deleg_debug = 1'h0; // @[CSR.scala:476:28] wire deleg_rocc = 1'h0; // @[CSR.scala:476:28] wire deleg_sgeip = 1'h0; // @[CSR.scala:476:28] wire deleg_meip = 1'h0; // @[CSR.scala:476:28] wire deleg_vseip = 1'h0; // @[CSR.scala:476:28] wire deleg_seip = 1'h0; // @[CSR.scala:476:28] wire deleg_ueip = 1'h0; // @[CSR.scala:476:28] wire deleg_mtip = 1'h0; // @[CSR.scala:476:28] wire deleg_vstip = 1'h0; // @[CSR.scala:476:28] wire deleg_stip = 1'h0; // @[CSR.scala:476:28] wire deleg_utip = 1'h0; // @[CSR.scala:476:28] wire deleg_msip = 1'h0; // @[CSR.scala:476:28] wire deleg_vssip = 1'h0; // @[CSR.scala:476:28] wire deleg_ssip = 1'h0; // @[CSR.scala:476:28] wire deleg_usip = 1'h0; // @[CSR.scala:476:28] wire hi_hi_hi_hi_2 = 1'h0; // @[CSR.scala:479:12] wire hi_hi_hi_hi_3 = 1'h0; // @[CSR.scala:479:27] wire _reset_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:516:48] wire _reset_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:516:48] wire reset_mnstatus_mpv = 1'h0; // @[CSR.scala:516:35] wire reset_mnstatus_mie = 1'h0; // @[CSR.scala:516:35] wire _reg_menvcfg_WIRE_stce = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:525:41] wire _reg_menvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:525:41] wire _reg_senvcfg_WIRE_stce = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:526:41] wire _reg_senvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:526:41] wire _reg_henvcfg_WIRE_stce = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_pbmte = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbze = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_cbcfe = 1'h0; // @[CSR.scala:527:41] wire _reg_henvcfg_WIRE_fiom = 1'h0; // @[CSR.scala:527:41] wire _reg_hstatus_WIRE_vtsr = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtw = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vtvm = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_hu = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spvp = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_spv = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_gva = 1'h0; // @[CSR.scala:552:41] wire _reg_hstatus_WIRE_vsbe = 1'h0; // @[CSR.scala:552:41] wire read_hvip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:555:27] wire mip_zero1 = 1'h0; // @[CSR.scala:600:24] wire mip_debug = 1'h0; // @[CSR.scala:600:24] wire mip_rocc = 1'h0; // @[CSR.scala:600:24] wire mip_sgeip = 1'h0; // @[CSR.scala:600:24] wire mip_vseip = 1'h0; // @[CSR.scala:600:24] wire mip_seip = 1'h0; // @[CSR.scala:600:24] wire mip_ueip = 1'h0; // @[CSR.scala:600:24] wire mip_vstip = 1'h0; // @[CSR.scala:600:24] wire mip_stip = 1'h0; // @[CSR.scala:600:24] wire mip_utip = 1'h0; // @[CSR.scala:600:24] wire mip_vssip = 1'h0; // @[CSR.scala:600:24] wire mip_ssip = 1'h0; // @[CSR.scala:600:24] wire mip_usip = 1'h0; // @[CSR.scala:600:24] wire _m_interrupts_T = 1'h0; // @[CSR.scala:620:51] wire _s_interrupts_T = 1'h0; // @[CSR.scala:621:68] wire _s_interrupts_T_2 = 1'h0; // @[CSR.scala:621:98] wire _s_interrupts_T_3 = 1'h0; // @[CSR.scala:621:110] wire _vs_interrupts_T = 1'h0; // @[CSR.scala:622:70] wire _vs_interrupts_T_1 = 1'h0; // @[CSR.scala:622:99] wire _vs_interrupts_T_2 = 1'h0; // @[CSR.scala:622:111] wire _vs_interrupts_T_3 = 1'h0; // @[CSR.scala:622:80] wire _vs_interrupts_T_4 = 1'h0; // @[CSR.scala:622:50] wire _vs_interrupts_T_5 = 1'h0; // @[CSR.scala:622:32] wire _any_T_31 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_32 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_33 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_34 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_35 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_36 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_37 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_38 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_39 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_40 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_41 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_42 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_43 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_44 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_45 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_46 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_47 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_48 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_49 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_50 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_51 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_52 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_53 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_54 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_55 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_56 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_57 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_58 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_59 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_60 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_61 = 1'h0; // @[CSR.scala:1637:76] wire _any_T_62 = 1'h0; // @[CSR.scala:1637:76] wire _which_T_31 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_32 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_33 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_34 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_35 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_36 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_37 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_38 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_39 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_40 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_41 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_42 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_43 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_44 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_45 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_46 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_47 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_48 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_49 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_50 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_51 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_52 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_53 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_54 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_55 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_56 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_57 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_58 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_59 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_60 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_61 = 1'h0; // @[CSR.scala:1638:91] wire _which_T_62 = 1'h0; // @[CSR.scala:1638:91] wire _io_fiom_T = 1'h0; // @[CSR.scala:631:31] wire _io_fiom_T_1 = 1'h0; // @[CSR.scala:631:41] wire _io_fiom_T_2 = 1'h0; // @[CSR.scala:631:82] wire _io_fiom_T_3 = 1'h0; // @[CSR.scala:631:92] wire _io_fiom_T_4 = 1'h0; // @[CSR.scala:631:62] wire _io_fiom_T_5 = 1'h0; // @[CSR.scala:631:131] wire _io_fiom_T_6 = 1'h0; // @[CSR.scala:631:113] wire _pmp_mask_base_T_2 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_5 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_8 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_11 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_14 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_17 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_20 = 1'h0; // @[PMP.scala:57:62] wire _pmp_mask_base_T_23 = 1'h0; // @[PMP.scala:57:62] wire _read_stvec_T = 1'h0; // @[CSR.scala:1666:41] wire read_mapping_lo_hi_1 = 1'h0; // @[CSR.scala:657:47] wire read_mapping_hi_hi_1 = 1'h0; // @[CSR.scala:657:47] wire _read_mnstatus_WIRE_mpv = 1'h0; // @[CSR.scala:675:44] wire _read_mnstatus_WIRE_mie = 1'h0; // @[CSR.scala:675:44] wire read_mnstatus_mpv = 1'h0; // @[CSR.scala:675:31] wire _sie_mask_sgeip_mask_WIRE_zero1 = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_debug = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_rocc = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_sgeip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_meip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vseip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_seip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ueip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_mtip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vstip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_stip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_utip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_msip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_vssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_ssip = 1'h0; // @[CSR.scala:748:43] wire _sie_mask_sgeip_mask_WIRE_usip = 1'h0; // @[CSR.scala:748:43] wire sie_mask_sgeip_mask_zero1 = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_debug = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_rocc = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_meip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vseip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_seip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ueip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_mtip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vstip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_stip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_utip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_msip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_vssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_ssip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_sgeip_mask_usip = 1'h0; // @[CSR.scala:748:30] wire sie_mask_hi_hi_hi_hi = 1'h0; // @[CSR.scala:750:59] wire read_pmp_15_cfg_l = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_x = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_w = 1'h0; // @[CSR.scala:787:59] wire read_pmp_15_cfg_r = 1'h0; // @[CSR.scala:787:59] wire _reg_custom_T = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_1 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_2 = 1'h0; // @[CSR.scala:801:16] wire _reg_custom_T_3 = 1'h0; // @[CSR.scala:801:16] wire _allow_sfence_vma_T_2 = 1'h0; // @[CSR.scala:907:77] wire _allow_sret_T_2 = 1'h0; // @[CSR.scala:910:79] wire io_decode_0_fp_csr_plaOutput = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_fp_csr_T = 1'h0; // @[Decode.scala:55:116] wire io_decode_0_vector_csr_plaOutput = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_vector_csr_T = 1'h0; // @[Decode.scala:55:116] wire _csr_addr_legal_T_3 = 1'h0; // @[CSR.scala:921:25] wire _csr_addr_legal_T_4 = 1'h0; // @[CSR.scala:921:62] wire _csr_addr_legal_T_5 = 1'h0; // @[CSR.scala:921:43] wire _csr_addr_legal_T_8 = 1'h0; // @[CSR.scala:921:74] wire _io_decode_0_read_illegal_T_6 = 1'h0; // @[CSR.scala:925:59] wire _io_decode_0_read_illegal_T_7 = 1'h0; // @[CSR.scala:925:56] wire _io_decode_0_read_illegal_T_9 = 1'h0; // @[CSR.scala:926:21] wire _io_decode_0_read_illegal_T_10 = 1'h0; // @[CSR.scala:926:18] wire io_decode_0_read_illegal_plaOutput_1 = 1'h0; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_16 = 1'h0; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_17 = 1'h0; // @[CSR.scala:928:43] wire _io_decode_0_read_illegal_T_19 = 1'h0; // @[CSR.scala:929:21] wire _io_decode_0_system_illegal_T_3 = 1'h0; // @[CSR.scala:936:17] wire _io_decode_0_system_illegal_T_4 = 1'h0; // @[CSR.scala:936:14] wire _io_decode_0_system_illegal_T_6 = 1'h0; // @[CSR.scala:937:17] wire _io_decode_0_system_illegal_T_7 = 1'h0; // @[CSR.scala:937:14] wire _io_decode_0_system_illegal_T_17 = 1'h0; // @[CSR.scala:939:40] wire _io_decode_0_system_illegal_T_18 = 1'h0; // @[CSR.scala:939:37] wire _io_decode_0_system_illegal_T_20 = 1'h0; // @[CSR.scala:940:25] wire _io_decode_0_system_illegal_T_21 = 1'h0; // @[CSR.scala:940:22] wire _io_decode_0_system_illegal_T_23 = 1'h0; // @[CSR.scala:941:18] wire _io_decode_0_system_illegal_T_24 = 1'h0; // @[CSR.scala:941:15] wire _io_decode_0_virtual_access_illegal_T_10 = 1'h0; // @[CSR.scala:945:89] wire _io_decode_0_virtual_access_illegal_T_14 = 1'h0; // @[CSR.scala:945:109] wire _io_decode_0_virtual_access_illegal_T_21 = 1'h0; // @[CSR.scala:946:37] wire _io_decode_0_virtual_access_illegal_T_22 = 1'h0; // @[CSR.scala:946:34] wire _io_decode_0_virtual_access_illegal_T_27 = 1'h0; // @[CSR.scala:947:50] wire _io_decode_0_virtual_system_illegal_T_3 = 1'h0; // @[CSR.scala:953:18] wire _io_decode_0_virtual_system_illegal_T_5 = 1'h0; // @[CSR.scala:953:57] wire _io_decode_0_virtual_system_illegal_T_6 = 1'h0; // @[CSR.scala:953:38] wire _io_decode_0_virtual_system_illegal_T_7 = 1'h0; // @[CSR.scala:953:14] wire _io_decode_0_virtual_system_illegal_T_13 = 1'h0; // @[CSR.scala:954:48] wire _io_decode_0_virtual_system_illegal_T_14 = 1'h0; // @[CSR.scala:954:68] wire _io_decode_0_virtual_system_illegal_T_15 = 1'h0; // @[CSR.scala:954:44] wire _io_decode_0_virtual_system_illegal_T_18 = 1'h0; // @[CSR.scala:955:21] wire _io_decode_0_virtual_system_illegal_T_19 = 1'h0; // @[CSR.scala:955:41] wire _io_decode_0_virtual_system_illegal_T_20 = 1'h0; // @[CSR.scala:955:17] wire _delegate_T = 1'h0; // @[CSR.scala:970:55] wire _delegate_T_1 = 1'h0; // @[CSR.scala:970:36] wire delegate = 1'h0; // @[CSR.scala:970:66] wire _delegateVS_T = 1'h0; // @[CSR.scala:971:34] wire delegateVS = 1'h0; // @[CSR.scala:971:46] wire trapToNmiInt = 1'h0; // @[CSR.scala:990:33] wire _trapToNmiXcpt_T = 1'h0; // @[CSR.scala:991:37] wire trapToNmiXcpt = 1'h0; // @[CSR.scala:991:34] wire trapToNmi = 1'h0; // @[CSR.scala:992:32] wire _nmiTVec_T = 1'h0; // @[CSR.scala:993:21] wire _nmiTVec_T_1 = 1'h0; // @[CSR.scala:993:58] wire _io_status_sd_T = 1'h0; // @[CSR.scala:1003:32] wire _io_status_sd_T_1 = 1'h0; // @[CSR.scala:1003:53] wire _io_status_sd_T_2 = 1'h0; // @[CSR.scala:1003:37] wire _io_status_sd_T_3 = 1'h0; // @[CSR.scala:1003:74] wire _io_status_sd_T_4 = 1'h0; // @[CSR.scala:1003:58] wire _io_status_dprv_T_1 = 1'h0; // @[CSR.scala:1008:42] wire _io_status_dv_T_1 = 1'h0; // @[CSR.scala:1009:57] wire _io_status_dv_T_2 = 1'h0; // @[CSR.scala:1009:39] wire _io_status_sd_rv32_T = 1'h0; // @[CSR.scala:1010:39] wire _io_gstatus_sd_T_1 = 1'h0; // @[CSR.scala:1016:56] wire _en_T_1 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_2 = 1'h0; // @[CSR.scala:1096:24] wire en = 1'h0; // @[CSR.scala:1096:79] wire delegable = 1'h0; // @[CSR.scala:1097:65] wire _en_T_7 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_8 = 1'h0; // @[CSR.scala:1096:24] wire en_1 = 1'h0; // @[CSR.scala:1096:79] wire delegable_1 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_13 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_14 = 1'h0; // @[CSR.scala:1096:24] wire en_2 = 1'h0; // @[CSR.scala:1096:79] wire delegable_2 = 1'h0; // @[CSR.scala:1097:65] wire delegable_3 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_25 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_26 = 1'h0; // @[CSR.scala:1096:24] wire en_4 = 1'h0; // @[CSR.scala:1096:79] wire delegable_4 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_31 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_32 = 1'h0; // @[CSR.scala:1096:24] wire en_5 = 1'h0; // @[CSR.scala:1096:79] wire delegable_5 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_37 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_38 = 1'h0; // @[CSR.scala:1096:24] wire en_6 = 1'h0; // @[CSR.scala:1096:79] wire delegable_6 = 1'h0; // @[CSR.scala:1097:65] wire delegable_7 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_49 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_50 = 1'h0; // @[CSR.scala:1096:24] wire en_8 = 1'h0; // @[CSR.scala:1096:79] wire delegable_8 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_55 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_56 = 1'h0; // @[CSR.scala:1096:24] wire en_9 = 1'h0; // @[CSR.scala:1096:79] wire delegable_9 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_61 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_62 = 1'h0; // @[CSR.scala:1096:24] wire en_10 = 1'h0; // @[CSR.scala:1096:79] wire delegable_10 = 1'h0; // @[CSR.scala:1097:65] wire delegable_11 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_73 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_74 = 1'h0; // @[CSR.scala:1096:24] wire en_12 = 1'h0; // @[CSR.scala:1096:79] wire delegable_12 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_79 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_80 = 1'h0; // @[CSR.scala:1096:24] wire en_13 = 1'h0; // @[CSR.scala:1096:79] wire delegable_13 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_85 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_86 = 1'h0; // @[CSR.scala:1096:24] wire en_14 = 1'h0; // @[CSR.scala:1096:79] wire delegable_14 = 1'h0; // @[CSR.scala:1097:65] wire _en_T_91 = 1'h0; // @[CSR.scala:1096:71] wire _en_T_92 = 1'h0; // @[CSR.scala:1096:24] wire en_15 = 1'h0; // @[CSR.scala:1096:79] wire delegable_15 = 1'h0; // @[CSR.scala:1097:65] wire delegable_17 = 1'h0; // @[CSR.scala:1109:67] wire delegable_21 = 1'h0; // @[CSR.scala:1109:67] wire delegable_23 = 1'h0; // @[CSR.scala:1109:67] wire delegable_24 = 1'h0; // @[CSR.scala:1109:67] wire _reg_mstatus_v_T = 1'h0; // @[CSR.scala:1123:44] wire _reg_mstatus_v_T_1 = 1'h0; // @[CSR.scala:1136:42] wire _reg_mstatus_v_T_2 = 1'h0; // @[CSR.scala:1136:72] wire _reg_mstatus_v_T_3 = 1'h0; // @[CSR.scala:1136:56] wire _reg_mstatus_v_T_4 = 1'h0; // @[CSR.scala:1141:42] wire _reg_mstatus_v_T_5 = 1'h0; // @[CSR.scala:1141:82] wire _reg_mstatus_v_T_6 = 1'h0; // @[CSR.scala:1141:62] wire _reg_mstatus_v_T_7 = 1'h0; // @[CSR.scala:1150:42] wire _reg_mstatus_v_T_9 = 1'h0; // @[CSR.scala:1150:61] wire _io_rw_rdata_T = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_20 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_21 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_22 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_23 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_24 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_25 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_26 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_27 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_29 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_30 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_31 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_32 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_33 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_34 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_35 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_36 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_37 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_38 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_39 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_40 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_41 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_42 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_43 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_44 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_45 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_46 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_48 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_49 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_50 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_51 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_52 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_53 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_54 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_55 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_56 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_57 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_58 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_59 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_60 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_61 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_62 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_63 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_64 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_66 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_67 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_68 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_69 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_70 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_71 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_72 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_73 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_74 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_75 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_76 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_77 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_78 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_79 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_80 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_81 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_82 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_83 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_84 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_85 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_86 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_87 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_88 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_89 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_90 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_91 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_92 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_93 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_94 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_95 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_96 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_97 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_98 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_99 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_100 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_101 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_102 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_103 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_104 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_105 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_106 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_107 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_108 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_109 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_110 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_111 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_112 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_113 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_114 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_115 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_116 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_117 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_118 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_119 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_120 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_121 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_122 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_123 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_124 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_125 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_126 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_127 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_128 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_129 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_130 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_131 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_132 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_133 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_134 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_135 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_136 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_137 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_138 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_139 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_140 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_141 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_142 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_143 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_144 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_145 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_146 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_147 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_148 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_149 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_150 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_151 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_152 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_153 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_154 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_155 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_156 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_157 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_158 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_159 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_160 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_161 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_162 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_163 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_164 = 1'h0; // @[Mux.scala:30:73] wire _io_rw_rdata_T_195 = 1'h0; // @[Mux.scala:30:73] wire set_vs_dirty = 1'h0; // @[CSR.scala:1191:33] wire set_fs_dirty = 1'h0; // @[CSR.scala:1200:33] wire new_mip_hi_hi_hi_hi = 1'h0; // @[CSR.scala:1271:59] wire _reg_bp_0_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_0_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_0_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_0_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_bp_1_control_chain_T_1 = 1'h0; // @[CSR.scala:1481:49] wire _reg_bp_1_control_chain_T_2 = 1'h0; // @[CSR.scala:1481:46] wire _reg_bp_1_control_chain_T_3 = 1'h0; // @[CSR.scala:1481:88] wire _reg_bp_1_control_chain_T_5 = 1'h0; // @[CSR.scala:1481:75] wire _reg_bp_1_WIRE_control_dmode = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_action = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_chain = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_m = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_h = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_s = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_u = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_x = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_w = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_control_r = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_mselect = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_pad1 = 1'h0; // @[CSR.scala:1613:23] wire _reg_bp_1_WIRE_textra_sselect = 1'h0; // @[CSR.scala:1613:23] wire [22:0] io_status_zero2 = 23'h0; // @[CSR.scala:377:7] wire [22:0] io_gstatus_zero2_0 = 23'h0; // @[CSR.scala:377:7] wire [22:0] io_bp_0_textra_pad2_0 = 23'h0; // @[CSR.scala:377:7] wire [22:0] _reset_mstatus_WIRE_zero2 = 23'h0; // @[CSR.scala:391:47] wire [22:0] reset_mstatus_zero2 = 23'h0; // @[CSR.scala:391:34] wire [22:0] _reg_bp_1_WIRE_textra_pad2 = 23'h0; // @[CSR.scala:1613:23] wire [7:0] io_status_zero1 = 8'h0; // @[CSR.scala:377:7] wire [7:0] io_gstatus_zero1_0 = 8'h0; // @[CSR.scala:377:7] wire [7:0] io_bp_0_control_reserved = 8'h0; // @[CSR.scala:377:7] wire [7:0] _reset_mstatus_WIRE_zero1 = 8'h0; // @[CSR.scala:391:47] wire [7:0] reset_mstatus_zero1 = 8'h0; // @[CSR.scala:391:34] wire [7:0] lo_1 = 8'h0; // @[CSR.scala:431:50] wire [7:0] hi_1 = 8'h0; // @[CSR.scala:431:50] wire [7:0] lo_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] hi_2 = 8'h0; // @[CSR.scala:479:12] wire [7:0] lo_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] hi_3 = 8'h0; // @[CSR.scala:479:27] wire [7:0] read_fcsr = 8'h0; // @[CSR.scala:689:22] wire [7:0] sie_mask_lo = 8'h0; // @[CSR.scala:750:59] wire [7:0] _reg_bp_1_WIRE_control_reserved = 8'h0; // @[CSR.scala:1613:23] wire [1:0] io_status_sxl = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_status_uxl = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_status_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_status_fs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_status_vs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_vsxl = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero3 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_hstatus_zero2 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_dprv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_prv_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_sxl_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_uxl = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_xs = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_fs_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_mpp_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_gstatus_vs_0 = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_zero = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[CSR.scala:377:7] wire [1:0] _reset_mstatus_WIRE_dprv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_prv = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_sxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_uxl = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_xs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_fs = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_mpp = 2'h0; // @[CSR.scala:391:47] wire [1:0] _reset_mstatus_WIRE_vs = 2'h0; // @[CSR.scala:391:47] wire [1:0] reset_mstatus_dprv = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_sxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_uxl = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_xs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_fs = 2'h0; // @[CSR.scala:391:34] wire [1:0] reset_mstatus_vs = 2'h0; // @[CSR.scala:391:34] wire [1:0] _reset_dcsr_WIRE_xdebugver = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero4 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_zero1 = 2'h0; // @[CSR.scala:400:44] wire [1:0] _reset_dcsr_WIRE_prv = 2'h0; // @[CSR.scala:400:44] wire [1:0] reset_dcsr_zero4 = 2'h0; // @[CSR.scala:400:31] wire [1:0] reset_dcsr_zero1 = 2'h0; // @[CSR.scala:400:31] wire [1:0] lo_lo_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] lo_hi_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] hi_lo_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] hi_hi_lo = 2'h0; // @[CSR.scala:431:10] wire [1:0] hi_hi_hi = 2'h0; // @[CSR.scala:431:10] wire [1:0] lo_lo_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_hi_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_lo_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_lo_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_lo_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] hi_hi_hi_1 = 2'h0; // @[CSR.scala:431:50] wire [1:0] lo_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_lo_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_lo_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] hi_hi_hi_2 = 2'h0; // @[CSR.scala:479:12] wire [1:0] lo_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] lo_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_lo_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_lo_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] hi_hi_hi_3 = 2'h0; // @[CSR.scala:479:27] wire [1:0] _reset_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:516:48] wire [1:0] _reg_menvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:525:41] wire [1:0] _reg_senvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:526:41] wire [1:0] _reg_henvcfg_WIRE_cbie = 2'h0; // @[CSR.scala:527:41] wire [1:0] _reg_hstatus_WIRE_vsxl = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero3 = 2'h0; // @[CSR.scala:552:41] wire [1:0] _reg_hstatus_WIRE_zero2 = 2'h0; // @[CSR.scala:552:41] wire [1:0] read_hvip_lo_lo_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_lo_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_lo_hi_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_lo_hi_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_lo_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_lo_hi = 2'h0; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_lo = 2'h0; // @[CSR.scala:555:27] wire [1:0] hi_5 = 2'h0; // @[CSR.scala:588:103] wire [1:0] pmp_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_res = 2'h0; // @[PMP.scala:24:19] wire [1:0] read_mstatus_lo_lo_lo_lo = 2'h0; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_lo_hi_lo = 2'h0; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_hi_hi_lo = 2'h0; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_hi_hi_hi_hi = 2'h0; // @[CSR.scala:649:32] wire [1:0] read_mapping_lo_hi_lo = 2'h0; // @[CSR.scala:655:48] wire [1:0] debug_csrs_lo_hi_hi = 2'h0; // @[CSR.scala:670:27] wire [1:0] debug_csrs_hi_lo_lo = 2'h0; // @[CSR.scala:670:27] wire [1:0] debug_csrs_hi_lo_hi = 2'h0; // @[CSR.scala:670:27] wire [1:0] _read_mnstatus_WIRE_mpp = 2'h0; // @[CSR.scala:675:44] wire [1:0] read_vcsr = 2'h0; // @[CSR.scala:695:22] wire [1:0] sie_mask_lo_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_lo_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_lo = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_lo_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] sie_mask_hi_hi_hi = 2'h0; // @[CSR.scala:750:59] wire [1:0] read_pmp_15_cfg_res = 2'h0; // @[CSR.scala:787:59] wire [1:0] read_pmp_15_cfg_a = 2'h0; // @[CSR.scala:787:59] wire [1:0] lo_hi_12 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_13 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_14 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_15 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_16 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_17 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_18 = 2'h0; // @[package.scala:45:36] wire [1:0] lo_hi_19 = 2'h0; // @[package.scala:45:36] wire [1:0] decoded_orMatrixOutputs_lo_lo = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_hi = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_lo_1 = 2'h0; // @[pla.scala:102:36] wire [1:0] decoded_orMatrixOutputs_lo_hi_1 = 2'h0; // @[pla.scala:102:36] wire [1:0] causeIsDebugBreak_lo = 2'h0; // @[CSR.scala:965:62] wire [1:0] nmiTVec = 2'h0; // @[CSR.scala:993:62] wire [1:0] new_mip_lo_lo_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_lo_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_lo_hi_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_lo_hi_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_lo_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_lo_hi = 2'h0; // @[CSR.scala:1271:59] wire [1:0] new_mip_hi_hi_lo = 2'h0; // @[CSR.scala:1271:59] wire [1:0] newBPC_lo_hi_lo = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_lo_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_lo_hi_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] newBPC_hi_lo_hi_1 = 2'h0; // @[CSR.scala:1477:67] wire [1:0] _reg_bp_1_WIRE_control_zero = 2'h0; // @[CSR.scala:1613:23] wire [1:0] _reg_bp_1_WIRE_control_tmatch = 2'h0; // @[CSR.scala:1613:23] wire [29:0] io_hstatus_zero6 = 30'h0; // @[CSR.scala:377:7] wire [29:0] _reg_hstatus_WIRE_zero6 = 30'h0; // @[CSR.scala:552:41] wire [29:0] read_pmp_15_addr = 30'h0; // @[CSR.scala:787:59] wire [29:0] _io_rw_rdata_T_183 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_184 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_185 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_186 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_187 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_188 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_189 = 30'h0; // @[Mux.scala:30:73] wire [29:0] _io_rw_rdata_T_190 = 30'h0; // @[Mux.scala:30:73] wire [8:0] io_hstatus_zero5 = 9'h0; // @[CSR.scala:377:7] wire [8:0] io_ptbr_asid = 9'h0; // @[CSR.scala:377:7] wire [8:0] io_hgatp_asid = 9'h0; // @[CSR.scala:377:7] wire [8:0] io_vsatp_asid = 9'h0; // @[CSR.scala:377:7] wire [8:0] _reg_hstatus_WIRE_zero5 = 9'h0; // @[CSR.scala:552:41] wire [8:0] read_mstatus_hi_lo_lo_lo = 9'h0; // @[CSR.scala:649:32] wire [5:0] io_hstatus_vgein = 6'h0; // @[CSR.scala:377:7] wire [5:0] _reg_hstatus_WIRE_vgein = 6'h0; // @[CSR.scala:552:41] wire [5:0] newBPC_hi_lo_1 = 6'h0; // @[CSR.scala:1477:67] wire [5:0] _reg_bp_1_WIRE_control_maskmax = 6'h0; // @[CSR.scala:1613:23] wire [4:0] io_hstatus_zero1 = 5'h0; // @[CSR.scala:377:7] wire [4:0] io_fcsr_flags_bits = 5'h0; // @[CSR.scala:377:7] wire [4:0] _reg_hstatus_WIRE_zero1 = 5'h0; // @[CSR.scala:552:41] wire [4:0] read_mstatus_lo_hi_hi = 5'h0; // @[CSR.scala:649:32] wire [4:0] hi_16 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_17 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_18 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_19 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_21 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_22 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_23 = 5'h0; // @[package.scala:45:36] wire [4:0] hi_24 = 5'h0; // @[package.scala:45:36] wire [4:0] _reg_fflags_T = 5'h0; // @[CSR.scala:1211:30] wire [4:0] newBPC_hi_hi_hi_1 = 5'h0; // @[CSR.scala:1477:67] wire [21:0] io_ptbr_ppn = 22'h0; // @[CSR.scala:377:7] wire [21:0] io_hgatp_ppn = 22'h0; // @[CSR.scala:377:7] wire [21:0] io_vsatp_ppn = 22'h0; // @[CSR.scala:377:7] wire [3:0] io_bp_0_control_ttype = 4'h2; // @[CSR.scala:377:7] wire [5:0] io_bp_0_control_maskmax = 6'h4; // @[CSR.scala:377:7] wire [31:0] io_gstatus_isa_0 = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_0_sdata = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_1_sdata = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_2_sdata = 32'h0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_3_sdata = 32'h0; // @[CSR.scala:377:7] wire [31:0] _reset_mstatus_WIRE_isa = 32'h0; // @[CSR.scala:391:47] wire [31:0] reset_mstatus_isa = 32'h0; // @[CSR.scala:391:34] wire [31:0] read_mideleg = 32'h0; // @[CSR.scala:498:14] wire [31:0] read_medeleg = 32'h0; // @[CSR.scala:502:14] wire [31:0] read_mcounteren = 32'h0; // @[CSR.scala:532:14] wire [31:0] read_scounteren = 32'h0; // @[CSR.scala:536:14] wire [31:0] read_hideleg = 32'h0; // @[CSR.scala:541:14] wire [31:0] read_hedeleg = 32'h0; // @[CSR.scala:545:14] wire [31:0] read_hcounteren = 32'h0; // @[CSR.scala:550:14] wire [31:0] read_hie = 32'h0; // @[CSR.scala:556:26] wire [31:0] read_vstvec = 32'h0; // @[package.scala:174:35] wire [31:0] _s_interrupts_T_6 = 32'h0; // @[CSR.scala:621:151] wire [31:0] _s_interrupts_T_8 = 32'h0; // @[CSR.scala:621:166] wire [31:0] s_interrupts = 32'h0; // @[CSR.scala:621:25] wire [31:0] _vs_interrupts_T_6 = 32'h0; // @[CSR.scala:622:153] wire [31:0] vs_interrupts = 32'h0; // @[CSR.scala:622:26] wire [31:0] _read_mtvec_T_2 = 32'h0; // @[package.scala:174:46] wire [31:0] _read_stvec_T_2 = 32'h0; // @[package.scala:174:46] wire [31:0] read_stvec = 32'h0; // @[package.scala:174:35] wire [31:0] sie_mask = 32'h0; // @[CSR.scala:750:18] wire [31:0] read_pmp_15_mask = 32'h0; // @[CSR.scala:787:59] wire [31:0] _io_rw_rdata_T_173 = 32'h0; // @[Mux.scala:30:73] wire [31:0] _io_rw_rdata_T_174 = 32'h0; // @[Mux.scala:30:73] wire [31:0] _newBPC_T_24 = 32'h0; // @[CSR.scala:1477:67] wire [31:0] _newBPC_T_26 = 32'h0; // @[CSR.scala:1643:9] wire [31:0] _reg_custom_1_T = 32'h0; // @[CSR.scala:1506:23] wire [31:0] _reg_custom_2_T = 32'h0; // @[CSR.scala:1506:23] wire [31:0] _reg_custom_3_T = 32'h0; // @[CSR.scala:1506:23] wire [31:0] _reg_custom_0_T_4 = 32'h0; // @[CSR.scala:1531:24] wire [31:0] _reg_custom_1_T_4 = 32'h0; // @[CSR.scala:1531:24] wire [31:0] _reg_custom_2_T_4 = 32'h0; // @[CSR.scala:1531:24] wire [31:0] _reg_custom_3_T_4 = 32'h0; // @[CSR.scala:1531:24] wire [31:0] _reg_bp_1_WIRE_address = 32'h0; // @[CSR.scala:1613:23] wire [3:0] hi_hi = 4'h0; // @[CSR.scala:431:10] wire [3:0] lo_lo_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] lo_hi_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] hi_lo_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] hi_hi_1 = 4'h0; // @[CSR.scala:431:50] wire [3:0] lo_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_lo_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] hi_hi_2 = 4'h0; // @[CSR.scala:479:12] wire [3:0] lo_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] lo_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_lo_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] hi_hi_3 = 4'h0; // @[CSR.scala:479:27] wire [3:0] read_mstatus_lo_hi_lo_hi = 4'h0; // @[CSR.scala:649:32] wire [3:0] debug_csrs_hi_lo = 4'h0; // @[CSR.scala:670:27] wire [3:0] sie_mask_lo_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_lo_hi = 4'h0; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_lo = 4'h0; // @[CSR.scala:750:59] wire [3:0] decoded_orMatrixOutputs_lo = 4'h0; // @[pla.scala:102:36] wire [3:0] decoded_orMatrixOutputs_lo_1 = 4'h0; // @[pla.scala:102:36] wire [3:0] newBPC_lo_hi_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] newBPC_hi_lo_lo_1 = 4'h0; // @[CSR.scala:1477:67] wire [3:0] _reg_bp_1_WIRE_control_ttype = 4'h0; // @[CSR.scala:1613:23] wire [24:0] newBPC_hi_1 = 25'h0; // @[CSR.scala:1477:67] wire [18:0] newBPC_hi_hi_1 = 19'h0; // @[CSR.scala:1477:67] wire [13:0] newBPC_hi_hi_lo_1 = 14'h0; // @[CSR.scala:1477:67] wire [6:0] newBPC_lo_1 = 7'h0; // @[CSR.scala:1477:67] wire [2:0] io_fcsr_rm_0 = 3'h0; // @[CSR.scala:377:7] wire [2:0] _reset_dcsr_WIRE_cause = 3'h0; // @[CSR.scala:400:44] wire [2:0] reset_dcsr_cause = 3'h0; // @[CSR.scala:400:31] wire [2:0] _reset_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:516:48] wire [2:0] _reset_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:516:48] wire [2:0] reset_mnstatus_zero3 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero2 = 3'h0; // @[CSR.scala:516:35] wire [2:0] reset_mnstatus_zero1 = 3'h0; // @[CSR.scala:516:35] wire [2:0] _reg_menvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:525:41] wire [2:0] _reg_senvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:526:41] wire [2:0] _reg_henvcfg_WIRE_zero3 = 3'h0; // @[CSR.scala:527:41] wire [2:0] read_mstatus_lo_hi_hi_hi = 3'h0; // @[CSR.scala:649:32] wire [2:0] read_mstatus_hi_lo_lo_hi = 3'h0; // @[CSR.scala:649:32] wire [2:0] read_mstatus_hi_lo_hi_lo = 3'h0; // @[CSR.scala:649:32] wire [2:0] _read_mnstatus_WIRE_zero3 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero2 = 3'h0; // @[CSR.scala:675:44] wire [2:0] _read_mnstatus_WIRE_zero1 = 3'h0; // @[CSR.scala:675:44] wire [2:0] read_mnstatus_zero3 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero2 = 3'h0; // @[CSR.scala:675:31] wire [2:0] read_mnstatus_zero1 = 3'h0; // @[CSR.scala:675:31] wire [2:0] lo_14 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_12 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_15 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_13 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_16 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_14 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_17 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_15 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_19 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_16 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_20 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_17 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_21 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_18 = 3'h0; // @[package.scala:45:36] wire [2:0] lo_22 = 3'h0; // @[package.scala:45:36] wire [2:0] hi_hi_19 = 3'h0; // @[package.scala:45:36] wire [2:0] newBPC_lo_lo_1 = 3'h0; // @[CSR.scala:1477:67] wire [13:0] read_mapping_hi_hi_lo = 14'h400; // @[CSR.scala:655:48] wire [13:0] newBPC_hi_hi_lo = 14'h400; // @[CSR.scala:1477:67] wire [3:0] lo_lo = 4'h8; // @[CSR.scala:431:10] wire [3:0] lo_hi = 4'h8; // @[CSR.scala:431:10] wire [3:0] hi_lo = 4'h8; // @[CSR.scala:431:10] wire [3:0] read_mapping_lo_hi = 4'h8; // @[CSR.scala:655:48] wire [3:0] newBPC_lo_hi = 4'h8; // @[CSR.scala:1477:67] wire [1:0] lo_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] lo_hi_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] hi_lo_hi = 2'h2; // @[CSR.scala:431:10] wire [1:0] read_mapping_lo_hi_hi = 2'h2; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_hi_hi = 2'h2; // @[CSR.scala:1477:67] wire [3:0] _which_T_64 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_65 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_66 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_67 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_68 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_69 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_70 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_71 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_72 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_73 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_74 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_75 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_76 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_77 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_78 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_79 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_80 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_81 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_82 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_83 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_84 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_85 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_86 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_87 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_88 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_89 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_90 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_91 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_92 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_93 = 4'h4; // @[Mux.scala:50:70] wire [3:0] _which_T_94 = 4'h4; // @[Mux.scala:50:70] wire [3:0] debug_csrs_hi_hi_hi = 4'h4; // @[CSR.scala:670:27] wire [23:0] read_mstatus_hi_hi_lo_lo = 24'h0; // @[CSR.scala:649:32] wire [23:0] read_mapping_hi_1 = 24'h0; // @[CSR.scala:657:47] wire [11:0] _reset_dcsr_WIRE_zero3 = 12'h0; // @[CSR.scala:400:44] wire [11:0] reset_dcsr_zero3 = 12'h0; // @[CSR.scala:400:31] wire [11:0] read_mstatus_hi_lo_lo = 12'h0; // @[CSR.scala:649:32] wire [31:0] _s_interrupts_T_7 = 32'hFFFFFFFF; // @[CSR.scala:621:168] wire [31:0] _io_evec_T = 32'hFFFFFFFF; // @[CSR.scala:1665:28] wire [31:0] _io_evec_T_5 = 32'hFFFFFFFF; // @[CSR.scala:1665:28] wire [31:0] _io_evec_T_15 = 32'hFFFFFFFF; // @[CSR.scala:1665:28] wire [31:0] _reg_custom_1_T_1 = 32'hFFFFFFFF; // @[CSR.scala:1506:40] wire [31:0] _reg_custom_2_T_1 = 32'hFFFFFFFF; // @[CSR.scala:1506:40] wire [31:0] _reg_custom_3_T_1 = 32'hFFFFFFFF; // @[CSR.scala:1506:40] wire [31:0] _reg_custom_1_T_5 = 32'hFFFFFFFF; // @[CSR.scala:1531:41] wire [31:0] _reg_custom_2_T_5 = 32'hFFFFFFFF; // @[CSR.scala:1531:41] wire [31:0] _reg_custom_3_T_5 = 32'hFFFFFFFF; // @[CSR.scala:1531:41] wire [31:0] _reg_custom_0_T_1 = 32'hFFFFFFF7; // @[CSR.scala:1506:40] wire [31:0] _reg_custom_0_T_5 = 32'hFFFFFFF7; // @[CSR.scala:1531:41] wire [31:0] _reg_mcountinhibit_T = 32'hFFFFFFFD; // @[CSR.scala:1306:78] wire [31:0] _reg_misa_T_6 = 32'hFFFFEFFA; // @[CSR.scala:1263:75] wire [15:0] delegable_interrupts = 16'h0; // @[CSR.scala:431:50] wire [15:0] hs_delegable_interrupts = 16'h0; // @[CSR.scala:479:12] wire [15:0] mideleg_always_hs = 16'h0; // @[CSR.scala:479:27] wire [15:0] read_hvip = 16'h0; // @[CSR.scala:555:34] wire [15:0] read_hip = 16'h0; // @[CSR.scala:611:27] wire [15:0] lo_18 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_20 = 16'h0; // @[package.scala:45:27] wire [15:0] lo_23 = 16'h0; // @[package.scala:45:27] wire [15:0] hi_25 = 16'h0; // @[package.scala:45:27] wire [15:0] _en_T = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_6 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_1 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_12 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_2 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_3 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_24 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_4 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_30 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_5 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_36 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_6 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_7 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_48 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_8 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_54 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_9 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_60 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_10 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_11 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_72 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_12 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_78 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_13 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_84 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_14 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _en_T_90 = 16'h0; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_15 = 16'h0; // @[CSR.scala:1097:43] wire [15:0] _delegable_T_17 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_21 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_23 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_24 = 16'h0; // @[CSR.scala:1109:45] wire [15:0] _en_T_18 = 16'h8; // @[CSR.scala:1096:49] wire [15:0] _delegable_T_19 = 16'h8; // @[CSR.scala:1109:45] wire [31:0] _en_T_94 = 32'h8000000F; // @[CSR.scala:1096:120] wire [31:0] _en_T_88 = 32'h8000000E; // @[CSR.scala:1096:120] wire [31:0] _en_T_82 = 32'h8000000D; // @[CSR.scala:1096:120] wire [31:0] _en_T_76 = 32'h8000000C; // @[CSR.scala:1096:120] wire [31:0] _en_T_70 = 32'h8000000B; // @[CSR.scala:1096:120] wire [15:0] _en_T_66 = 16'h800; // @[CSR.scala:1096:49] wire [31:0] _en_T_64 = 32'h8000000A; // @[CSR.scala:1096:120] wire [31:0] _en_T_58 = 32'h80000009; // @[CSR.scala:1096:120] wire [31:0] _en_T_52 = 32'h80000008; // @[CSR.scala:1096:120] wire [31:0] _en_T_46 = 32'h80000007; // @[CSR.scala:1096:120] wire [15:0] _en_T_42 = 16'h80; // @[CSR.scala:1096:49] wire [31:0] _en_T_40 = 32'h80000006; // @[CSR.scala:1096:120] wire [31:0] _en_T_34 = 32'h80000005; // @[CSR.scala:1096:120] wire [31:0] _en_T_28 = 32'h80000004; // @[CSR.scala:1096:120] wire [31:0] _en_T_22 = 32'h80000003; // @[CSR.scala:1096:120] wire [31:0] _en_T_16 = 32'h80000002; // @[CSR.scala:1096:120] wire [31:0] _en_T_10 = 32'h80000001; // @[CSR.scala:1096:120] wire [31:0] _interruptCause_T_2 = 32'h80000000; // @[CSR.scala:625:39] wire [31:0] _en_T_4 = 32'h80000000; // @[CSR.scala:1096:120] wire [32:0] _interruptCause_T_1 = 33'h80000000; // @[CSR.scala:625:39] wire [32:0] _en_T_3 = 33'h80000000; // @[CSR.scala:1096:120] wire [9:0] _io_decode_0_write_flush_addr_m_T = 10'h300; // @[CSR.scala:932:36] wire [15:0] _sie_mask_T_2 = 16'hEFFF; // @[CSR.scala:750:20] wire [15:0] _sie_mask_T = 16'h1000; // @[CSR.scala:750:59] wire [15:0] _sie_mask_T_1 = 16'h1000; // @[CSR.scala:750:46] wire [7:0] sie_mask_hi = 8'h10; // @[CSR.scala:750:59] wire [3:0] sie_mask_hi_hi = 4'h1; // @[CSR.scala:750:59] wire [1:0] reset_dcsr_xdebugver = 2'h1; // @[CSR.scala:400:31] wire [1:0] sie_mask_hi_hi_lo = 2'h1; // @[CSR.scala:750:59] wire [2:0] _which_T_63 = 3'h4; // @[Mux.scala:50:70] wire [53:0] _reg_menvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:525:41] wire [53:0] _reg_senvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:526:41] wire [53:0] _reg_henvcfg_WIRE_zero54 = 54'h0; // @[CSR.scala:527:41] wire [15:0] supported_interrupts = 16'h888; // @[CSR.scala:431:17] wire [7:0] hi = 8'h8; // @[CSR.scala:431:10] wire [7:0] lo = 8'h88; // @[CSR.scala:431:10] wire [15:0] _delegable_T_22 = 16'h40; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_20 = 16'h10; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_18 = 16'h4; // @[CSR.scala:1109:45] wire [15:0] _delegable_T_16 = 16'h1; // @[CSR.scala:1109:45] wire [32:0] _en_T_93 = 33'h8000000F; // @[CSR.scala:1096:120] wire [32:0] _en_T_87 = 33'h8000000E; // @[CSR.scala:1096:120] wire [32:0] _en_T_81 = 33'h8000000D; // @[CSR.scala:1096:120] wire [32:0] _en_T_75 = 33'h8000000C; // @[CSR.scala:1096:120] wire [32:0] _en_T_69 = 33'h8000000B; // @[CSR.scala:1096:120] wire [32:0] _en_T_63 = 33'h8000000A; // @[CSR.scala:1096:120] wire [32:0] _en_T_57 = 33'h80000009; // @[CSR.scala:1096:120] wire [32:0] _en_T_51 = 33'h80000008; // @[CSR.scala:1096:120] wire [32:0] _en_T_45 = 33'h80000007; // @[CSR.scala:1096:120] wire [32:0] _en_T_39 = 33'h80000006; // @[CSR.scala:1096:120] wire [32:0] _en_T_33 = 33'h80000005; // @[CSR.scala:1096:120] wire [32:0] _en_T_27 = 33'h80000004; // @[CSR.scala:1096:120] wire [32:0] _en_T_21 = 33'h80000003; // @[CSR.scala:1096:120] wire [32:0] _en_T_15 = 33'h80000002; // @[CSR.scala:1096:120] wire [32:0] _en_T_9 = 33'h80000001; // @[CSR.scala:1096:120] wire [30:0] _interruptCause_T = 31'h0; // @[CSR.scala:625:50] wire mip_mtip = io_interrupts_mtip_0; // @[CSR.scala:377:7, :600:24] wire mip_msip = io_interrupts_msip_0; // @[CSR.scala:377:7, :600:24] wire mip_meip = io_interrupts_meip_0; // @[CSR.scala:377:7, :600:24] wire [31:0] _newBPC_T_27 = io_rw_wdata_0; // @[CSR.scala:377:7, :1643:30] wire [31:0] decoded_plaInput_1 = io_decode_0_inst_0; // @[pla.scala:77:22] wire _io_decode_0_read_illegal_T_20; // @[CSR.scala:928:68] wire _io_decode_0_write_illegal_T_1; // @[CSR.scala:930:41] wire _io_decode_0_write_flush_T_3; // @[CSR.scala:933:7] wire _io_decode_0_system_illegal_T_25; // @[CSR.scala:940:44] wire _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:943:66] wire _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:949:52] wire _io_csr_stall_T; // @[CSR.scala:1161:27] wire _io_eret_T_1; // @[CSR.scala:1000:38] wire _io_singleStep_T_1; // @[CSR.scala:1001:34] wire _io_status_dv_T_3; // @[CSR.scala:1009:33] wire _io_gstatus_sd_T_4; // @[CSR.scala:1016:61] wire _io_gstatus_sd_rv32_T = io_gstatus_sd_0; // @[CSR.scala:377:7, :1018:40] wire _io_trace_0_valid_T = io_retire_0; // @[CSR.scala:377:7, :1621:26] wire [31:0] io_trace_0_iaddr_0 = io_pc_0; // @[CSR.scala:377:7] wire [31:0] io_trace_0_tval_0 = io_tval_0; // @[CSR.scala:377:7] wire _io_interrupt_T_5; // @[CSR.scala:626:73] wire [31:0] interruptCause; // @[CSR.scala:625:63] wire pmp_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_cfg_a; // @[PMP.scala:24:19] wire pmp_cfg_x; // @[PMP.scala:24:19] wire pmp_cfg_w; // @[PMP.scala:24:19] wire pmp_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_addr; // @[PMP.scala:24:19] wire [31:0] pmp_mask; // @[PMP.scala:24:19] wire pmp_1_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_1_cfg_a; // @[PMP.scala:24:19] wire pmp_1_cfg_x; // @[PMP.scala:24:19] wire pmp_1_cfg_w; // @[PMP.scala:24:19] wire pmp_1_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_1_addr; // @[PMP.scala:24:19] wire [31:0] pmp_1_mask; // @[PMP.scala:24:19] wire pmp_2_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_2_cfg_a; // @[PMP.scala:24:19] wire pmp_2_cfg_x; // @[PMP.scala:24:19] wire pmp_2_cfg_w; // @[PMP.scala:24:19] wire pmp_2_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_2_addr; // @[PMP.scala:24:19] wire [31:0] pmp_2_mask; // @[PMP.scala:24:19] wire pmp_3_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_3_cfg_a; // @[PMP.scala:24:19] wire pmp_3_cfg_x; // @[PMP.scala:24:19] wire pmp_3_cfg_w; // @[PMP.scala:24:19] wire pmp_3_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_3_addr; // @[PMP.scala:24:19] wire [31:0] pmp_3_mask; // @[PMP.scala:24:19] wire pmp_4_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_4_cfg_a; // @[PMP.scala:24:19] wire pmp_4_cfg_x; // @[PMP.scala:24:19] wire pmp_4_cfg_w; // @[PMP.scala:24:19] wire pmp_4_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_4_addr; // @[PMP.scala:24:19] wire [31:0] pmp_4_mask; // @[PMP.scala:24:19] wire pmp_5_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_5_cfg_a; // @[PMP.scala:24:19] wire pmp_5_cfg_x; // @[PMP.scala:24:19] wire pmp_5_cfg_w; // @[PMP.scala:24:19] wire pmp_5_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_5_addr; // @[PMP.scala:24:19] wire [31:0] pmp_5_mask; // @[PMP.scala:24:19] wire pmp_6_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_6_cfg_a; // @[PMP.scala:24:19] wire pmp_6_cfg_x; // @[PMP.scala:24:19] wire pmp_6_cfg_w; // @[PMP.scala:24:19] wire pmp_6_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_6_addr; // @[PMP.scala:24:19] wire [31:0] pmp_6_mask; // @[PMP.scala:24:19] wire pmp_7_cfg_l; // @[PMP.scala:24:19] wire [1:0] pmp_7_cfg_a; // @[PMP.scala:24:19] wire pmp_7_cfg_x; // @[PMP.scala:24:19] wire pmp_7_cfg_w; // @[PMP.scala:24:19] wire pmp_7_cfg_r; // @[PMP.scala:24:19] wire [29:0] pmp_7_addr; // @[PMP.scala:24:19] wire [31:0] pmp_7_mask; // @[PMP.scala:24:19] wire [31:0] _io_csrw_counter_T_11; // @[CSR.scala:1223:25] wire _io_inhibit_cycle_T; // @[CSR.scala:591:40] wire [31:0] io_trace_0_insn_0 = io_inst_0_0; // @[CSR.scala:377:7] wire _io_trace_0_valid_T_1; // @[CSR.scala:1621:32] wire [2:0] _io_trace_0_priv_T; // @[CSR.scala:1624:18] wire _io_trace_0_exception_T_1; // @[CSR.scala:1620:37] wire _io_trace_0_interrupt_T; // @[CSR.scala:1626:25] wire [31:0] cause; // @[CSR.scala:959:8] wire reg_custom_read; // @[CSR.scala:799:36] wire [31:0] wdata; // @[CSR.scala:1643:39] wire reg_custom_read_1; // @[CSR.scala:799:36] wire reg_custom_read_2; // @[CSR.scala:799:36] wire reg_custom_read_3; // @[CSR.scala:799:36] wire [31:0] io_rw_rdata_0; // @[CSR.scala:377:7] wire io_decode_0_read_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_write_flush_0; // @[CSR.scala:377:7] wire io_decode_0_system_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_access_illegal_0; // @[CSR.scala:377:7] wire io_decode_0_virtual_system_illegal_0; // @[CSR.scala:377:7] wire io_status_debug_0; // @[CSR.scala:377:7] wire io_status_cease_0; // @[CSR.scala:377:7] wire io_status_wfi_0; // @[CSR.scala:377:7] wire [31:0] io_status_isa_0; // @[CSR.scala:377:7] wire io_status_dv_0; // @[CSR.scala:377:7] wire io_status_v_0; // @[CSR.scala:377:7] wire io_status_mpv_0; // @[CSR.scala:377:7] wire io_status_gva_0; // @[CSR.scala:377:7] wire [1:0] io_status_mpp_0; // @[CSR.scala:377:7] wire io_status_mpie_0; // @[CSR.scala:377:7] wire io_status_mie_0; // @[CSR.scala:377:7] wire io_gstatus_sd_rv32_0; // @[CSR.scala:377:7] wire io_bp_0_control_dmode_0; // @[CSR.scala:377:7] wire io_bp_0_control_action_0; // @[CSR.scala:377:7] wire [1:0] io_bp_0_control_tmatch_0; // @[CSR.scala:377:7] wire io_bp_0_control_x_0; // @[CSR.scala:377:7] wire io_bp_0_control_w_0; // @[CSR.scala:377:7] wire io_bp_0_control_r_0; // @[CSR.scala:377:7] wire [31:0] io_bp_0_address_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_0_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_0_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_0_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_0_mask_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_1_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_1_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_1_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_1_mask_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_2_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_2_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_2_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_2_mask_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_3_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_3_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_3_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_3_mask_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_4_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_4_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_4_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_4_mask_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_5_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_5_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_5_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_5_mask_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_6_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_6_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_6_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_6_mask_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_l_0; // @[CSR.scala:377:7] wire [1:0] io_pmp_7_cfg_a_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_x_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_w_0; // @[CSR.scala:377:7] wire io_pmp_7_cfg_r_0; // @[CSR.scala:377:7] wire [29:0] io_pmp_7_addr_0; // @[CSR.scala:377:7] wire [31:0] io_pmp_7_mask_0; // @[CSR.scala:377:7] wire io_trace_0_valid_0; // @[CSR.scala:377:7] wire [2:0] io_trace_0_priv_0; // @[CSR.scala:377:7] wire io_trace_0_exception_0; // @[CSR.scala:377:7] wire io_trace_0_interrupt_0; // @[CSR.scala:377:7] wire [31:0] io_trace_0_cause_0; // @[CSR.scala:377:7] wire io_customCSRs_0_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_0_wen_0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_0_wdata_0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_0_value_0; // @[CSR.scala:377:7] wire io_customCSRs_1_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_1_wen_0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_1_wdata_0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_1_value_0; // @[CSR.scala:377:7] wire io_customCSRs_2_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_2_wen_0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_2_wdata_0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_2_value_0; // @[CSR.scala:377:7] wire io_customCSRs_3_ren_0; // @[CSR.scala:377:7] wire io_customCSRs_3_wen_0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_3_wdata_0; // @[CSR.scala:377:7] wire [31:0] io_customCSRs_3_value_0; // @[CSR.scala:377:7] wire io_csr_stall_0; // @[CSR.scala:377:7] wire io_eret_0; // @[CSR.scala:377:7] wire io_singleStep_0; // @[CSR.scala:377:7] wire [31:0] io_evec_0; // @[CSR.scala:377:7] wire [31:0] io_time_0; // @[CSR.scala:377:7] wire io_interrupt_0; // @[CSR.scala:377:7] wire [31:0] io_interrupt_cause_0; // @[CSR.scala:377:7] wire [31:0] io_csrw_counter; // @[CSR.scala:377:7] wire io_inhibit_cycle_0; // @[CSR.scala:377:7] reg reg_mstatus_v; // @[CSR.scala:395:28] assign io_status_v_0 = reg_mstatus_v; // @[CSR.scala:377:7, :395:28] wire _s_interrupts_T_1 = reg_mstatus_v; // @[CSR.scala:395:28, :621:49] wire _io_decode_0_rocc_illegal_T_2 = reg_mstatus_v; // @[CSR.scala:395:28, :919:66] wire _cause_T_1 = reg_mstatus_v; // @[CSR.scala:395:28, :959:65] assign _io_status_dv_T_3 = reg_mstatus_v; // @[CSR.scala:395:28, :1009:33] wire _reg_hstatus_spvp_T_1 = reg_mstatus_v; // @[CSR.scala:395:28, :1067:30] reg reg_mstatus_mpv; // @[CSR.scala:395:28] assign io_status_mpv_0 = reg_mstatus_mpv; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_gva; // @[CSR.scala:395:28] assign io_status_gva_0 = reg_mstatus_gva; // @[CSR.scala:377:7, :395:28] reg [1:0] reg_mstatus_mpp; // @[CSR.scala:395:28] assign io_status_mpp_0 = reg_mstatus_mpp; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mpie; // @[CSR.scala:395:28] assign io_status_mpie_0 = reg_mstatus_mpie; // @[CSR.scala:377:7, :395:28] reg reg_mstatus_mie; // @[CSR.scala:395:28] assign io_status_mie_0 = reg_mstatus_mie; // @[CSR.scala:377:7, :395:28] wire _m_interrupts_T_1 = reg_mstatus_mie; // @[CSR.scala:395:28, :620:62] wire [1:0] new_prv; // @[CSR.scala:397:28] reg reg_dcsr_ebreakm; // @[CSR.scala:403:25] reg [2:0] reg_dcsr_cause; // @[CSR.scala:403:25] reg reg_dcsr_v; // @[CSR.scala:403:25] reg reg_dcsr_step; // @[CSR.scala:403:25] reg reg_debug; // @[CSR.scala:482:26] assign io_status_debug_0 = reg_debug; // @[CSR.scala:377:7, :482:26] reg [31:0] reg_dpc; // @[CSR.scala:483:20] reg [31:0] reg_dscratch0; // @[CSR.scala:484:26] reg reg_singleStepped; // @[CSR.scala:486:30] reg reg_bp_0_control_dmode; // @[CSR.scala:492:19] assign io_bp_0_control_dmode_0 = reg_bp_0_control_dmode; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_action; // @[CSR.scala:492:19] assign io_bp_0_control_action_0 = reg_bp_0_control_action; // @[CSR.scala:377:7, :492:19] reg [1:0] reg_bp_0_control_tmatch; // @[CSR.scala:492:19] assign io_bp_0_control_tmatch_0 = reg_bp_0_control_tmatch; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_x; // @[CSR.scala:492:19] assign io_bp_0_control_x_0 = reg_bp_0_control_x; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_w; // @[CSR.scala:492:19] assign io_bp_0_control_w_0 = reg_bp_0_control_w; // @[CSR.scala:377:7, :492:19] reg reg_bp_0_control_r; // @[CSR.scala:492:19] assign io_bp_0_control_r_0 = reg_bp_0_control_r; // @[CSR.scala:377:7, :492:19] reg [31:0] reg_bp_0_address; // @[CSR.scala:492:19] assign io_bp_0_address_0 = reg_bp_0_address; // @[CSR.scala:377:7, :492:19] reg reg_pmp_0_cfg_l; // @[CSR.scala:493:20] assign pmp_cfg_l = reg_pmp_0_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_0_cfg_a; // @[CSR.scala:493:20] assign pmp_cfg_a = reg_pmp_0_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_x; // @[CSR.scala:493:20] assign pmp_cfg_x = reg_pmp_0_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_w; // @[CSR.scala:493:20] assign pmp_cfg_w = reg_pmp_0_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_0_cfg_r; // @[CSR.scala:493:20] assign pmp_cfg_r = reg_pmp_0_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_0_addr; // @[CSR.scala:493:20] assign pmp_addr = reg_pmp_0_addr; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_l; // @[CSR.scala:493:20] assign pmp_1_cfg_l = reg_pmp_1_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_1_cfg_a; // @[CSR.scala:493:20] assign pmp_1_cfg_a = reg_pmp_1_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_x; // @[CSR.scala:493:20] assign pmp_1_cfg_x = reg_pmp_1_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_w; // @[CSR.scala:493:20] assign pmp_1_cfg_w = reg_pmp_1_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_1_cfg_r; // @[CSR.scala:493:20] assign pmp_1_cfg_r = reg_pmp_1_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_1_addr; // @[CSR.scala:493:20] assign pmp_1_addr = reg_pmp_1_addr; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_l; // @[CSR.scala:493:20] assign pmp_2_cfg_l = reg_pmp_2_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_2_cfg_a; // @[CSR.scala:493:20] assign pmp_2_cfg_a = reg_pmp_2_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_x; // @[CSR.scala:493:20] assign pmp_2_cfg_x = reg_pmp_2_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_w; // @[CSR.scala:493:20] assign pmp_2_cfg_w = reg_pmp_2_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_2_cfg_r; // @[CSR.scala:493:20] assign pmp_2_cfg_r = reg_pmp_2_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_2_addr; // @[CSR.scala:493:20] assign pmp_2_addr = reg_pmp_2_addr; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_l; // @[CSR.scala:493:20] assign pmp_3_cfg_l = reg_pmp_3_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_3_cfg_a; // @[CSR.scala:493:20] assign pmp_3_cfg_a = reg_pmp_3_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_x; // @[CSR.scala:493:20] assign pmp_3_cfg_x = reg_pmp_3_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_w; // @[CSR.scala:493:20] assign pmp_3_cfg_w = reg_pmp_3_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_3_cfg_r; // @[CSR.scala:493:20] assign pmp_3_cfg_r = reg_pmp_3_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_3_addr; // @[CSR.scala:493:20] assign pmp_3_addr = reg_pmp_3_addr; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_l; // @[CSR.scala:493:20] assign pmp_4_cfg_l = reg_pmp_4_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_4_cfg_a; // @[CSR.scala:493:20] assign pmp_4_cfg_a = reg_pmp_4_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_x; // @[CSR.scala:493:20] assign pmp_4_cfg_x = reg_pmp_4_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_w; // @[CSR.scala:493:20] assign pmp_4_cfg_w = reg_pmp_4_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_4_cfg_r; // @[CSR.scala:493:20] assign pmp_4_cfg_r = reg_pmp_4_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_4_addr; // @[CSR.scala:493:20] assign pmp_4_addr = reg_pmp_4_addr; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_l; // @[CSR.scala:493:20] assign pmp_5_cfg_l = reg_pmp_5_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_5_cfg_a; // @[CSR.scala:493:20] assign pmp_5_cfg_a = reg_pmp_5_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_x; // @[CSR.scala:493:20] assign pmp_5_cfg_x = reg_pmp_5_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_w; // @[CSR.scala:493:20] assign pmp_5_cfg_w = reg_pmp_5_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_5_cfg_r; // @[CSR.scala:493:20] assign pmp_5_cfg_r = reg_pmp_5_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_5_addr; // @[CSR.scala:493:20] assign pmp_5_addr = reg_pmp_5_addr; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_l; // @[CSR.scala:493:20] assign pmp_6_cfg_l = reg_pmp_6_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_6_cfg_a; // @[CSR.scala:493:20] assign pmp_6_cfg_a = reg_pmp_6_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_x; // @[CSR.scala:493:20] assign pmp_6_cfg_x = reg_pmp_6_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_w; // @[CSR.scala:493:20] assign pmp_6_cfg_w = reg_pmp_6_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_6_cfg_r; // @[CSR.scala:493:20] assign pmp_6_cfg_r = reg_pmp_6_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_6_addr; // @[CSR.scala:493:20] assign pmp_6_addr = reg_pmp_6_addr; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_l; // @[CSR.scala:493:20] assign pmp_7_cfg_l = reg_pmp_7_cfg_l; // @[PMP.scala:24:19] reg [1:0] reg_pmp_7_cfg_a; // @[CSR.scala:493:20] assign pmp_7_cfg_a = reg_pmp_7_cfg_a; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_x; // @[CSR.scala:493:20] assign pmp_7_cfg_x = reg_pmp_7_cfg_x; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_w; // @[CSR.scala:493:20] assign pmp_7_cfg_w = reg_pmp_7_cfg_w; // @[PMP.scala:24:19] reg reg_pmp_7_cfg_r; // @[CSR.scala:493:20] assign pmp_7_cfg_r = reg_pmp_7_cfg_r; // @[PMP.scala:24:19] reg [29:0] reg_pmp_7_addr; // @[CSR.scala:493:20] assign pmp_7_addr = reg_pmp_7_addr; // @[PMP.scala:24:19] reg [31:0] reg_mie; // @[CSR.scala:495:20] reg [31:0] reg_mepc; // @[CSR.scala:505:21] reg [31:0] reg_mcause; // @[CSR.scala:506:27] reg [31:0] reg_mtval; // @[CSR.scala:507:22] reg [31:0] reg_mtval2; // @[CSR.scala:508:23] reg [31:0] reg_mscratch; // @[CSR.scala:509:25] reg [31:0] reg_mtvec; // @[CSR.scala:512:31] wire [3:0] read_hvip_lo_lo = {read_hvip_lo_lo_hi, read_hvip_lo_lo_lo}; // @[CSR.scala:555:27] wire [3:0] read_hvip_lo_hi = {read_hvip_lo_hi_hi, read_hvip_lo_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_lo = {read_hvip_lo_hi, read_hvip_lo_lo}; // @[CSR.scala:555:27] wire [3:0] read_hvip_hi_lo = {read_hvip_hi_lo_hi, read_hvip_hi_lo_lo}; // @[CSR.scala:555:27] wire [1:0] read_hvip_hi_hi_hi = {read_hvip_hi_hi_hi_hi, 1'h0}; // @[CSR.scala:555:27] wire [3:0] read_hvip_hi_hi = {read_hvip_hi_hi_hi, read_hvip_hi_hi_lo}; // @[CSR.scala:555:27] wire [7:0] read_hvip_hi = {read_hvip_hi_hi, read_hvip_hi_lo}; // @[CSR.scala:555:27] wire [15:0] _read_hvip_T = {read_hvip_hi, read_hvip_lo}; // @[CSR.scala:555:27] reg reg_wfi; // @[CSR.scala:575:54] assign io_status_wfi_0 = reg_wfi; // @[CSR.scala:377:7, :575:54] reg reg_mtinst_read_pseudo; // @[CSR.scala:584:35] wire [1:0] hi_4 = {reg_mtinst_read_pseudo, 1'h0}; // @[CSR.scala:584:35, :588:103] wire [13:0] read_mtinst = {hi_4, 12'h0}; // @[CSR.scala:588:103] wire [13:0] read_htinst = {hi_5, 12'h0}; // @[CSR.scala:588:103] reg [2:0] reg_mcountinhibit; // @[CSR.scala:590:34] assign _io_inhibit_cycle_T = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40] wire x11 = reg_mcountinhibit[0]; // @[CSR.scala:590:34, :591:40, :594:98] assign io_inhibit_cycle_0 = _io_inhibit_cycle_T; // @[CSR.scala:377:7, :591:40] wire x3 = reg_mcountinhibit[2]; // @[CSR.scala:590:34, :592:75] reg [5:0] small_0; // @[Counters.scala:45:41] wire [6:0] nextSmall = {1'h0, small_0} + {6'h0, io_retire_0}; // @[Counters.scala:45:41, :46:33] wire _large_T_1 = ~x3; // @[Counters.scala:47:9, :51:36] reg [57:0] large_0; // @[Counters.scala:50:31] wire _large_T = nextSmall[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_2 = _large_T & _large_T_1; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T = {1'h0, large_0} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_1 = _large_r_T[57:0]; // @[Counters.scala:51:55] wire [63:0] value = {large_0, small_0}; // @[Counters.scala:45:41, :50:31, :55:30] wire x10 = ~io_csr_stall_0; // @[CSR.scala:377:7, :594:56] reg [5:0] small_1; // @[Counters.scala:45:41] wire [6:0] nextSmall_1 = {1'h0, small_1} + {6'h0, x10}; // @[Counters.scala:45:41, :46:33] wire _large_T_4 = ~x11; // @[Counters.scala:47:9, :51:36] reg [57:0] large_1; // @[Counters.scala:50:31] wire _large_T_3 = nextSmall_1[6]; // @[Counters.scala:46:33, :51:20] wire _large_T_5 = _large_T_3 & _large_T_4; // @[Counters.scala:51:{20,33,36}] wire [58:0] _large_r_T_2 = {1'h0, large_1} + 59'h1; // @[Counters.scala:50:31, :51:55] wire [57:0] _large_r_T_3 = _large_r_T_2[57:0]; // @[Counters.scala:51:55] wire [63:0] value_1 = {large_1, small_1}; // @[Counters.scala:45:41, :50:31, :55:30] wire read_mip_hi_hi_hi_hi = mip_zero1; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_lo_lo = {mip_ssip, mip_usip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_lo_hi = {mip_msip, mip_vssip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_lo = {read_mip_lo_lo_hi, read_mip_lo_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_lo_hi_lo = {mip_stip, mip_utip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_lo_hi_hi = {mip_mtip, mip_vstip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_lo_hi = {read_mip_lo_hi_hi, read_mip_lo_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_lo = {read_mip_lo_hi, read_mip_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_lo_lo = {mip_seip, mip_ueip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_lo_hi = {mip_meip, mip_vseip}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_lo = {read_mip_hi_lo_hi, read_mip_hi_lo_lo}; // @[CSR.scala:610:22] wire [1:0] read_mip_hi_hi_lo = {1'h0, mip_sgeip}; // @[CSR.scala:600:24, :610:22] wire [1:0] read_mip_hi_hi_hi = {read_mip_hi_hi_hi_hi, mip_debug}; // @[CSR.scala:600:24, :610:22] wire [3:0] read_mip_hi_hi = {read_mip_hi_hi_hi, read_mip_hi_hi_lo}; // @[CSR.scala:610:22] wire [7:0] read_mip_hi = {read_mip_hi_hi, read_mip_hi_lo}; // @[CSR.scala:610:22] wire [15:0] _read_mip_T = {read_mip_hi, read_mip_lo}; // @[CSR.scala:610:22] wire [15:0] read_mip = _read_mip_T & 16'h888; // @[CSR.scala:610:{22,29}] wire [31:0] _pending_interrupts_T = {16'h0, reg_mie[15:0] & read_mip}; // @[CSR.scala:495:20, :610:29, :614:56] wire [31:0] pending_interrupts = _pending_interrupts_T; // @[CSR.scala:614:{44,56}] wire [14:0] d_interrupts = {io_interrupts_debug_0, 14'h0}; // @[CSR.scala:377:7, :615:42] wire _m_interrupts_T_2 = _m_interrupts_T_1; // @[CSR.scala:620:{31,62}] wire [31:0] _m_interrupts_T_3 = ~pending_interrupts; // @[CSR.scala:614:44, :620:85] wire [31:0] _m_interrupts_T_4 = _m_interrupts_T_3; // @[CSR.scala:620:{85,105}] wire [31:0] _m_interrupts_T_5 = ~_m_interrupts_T_4; // @[CSR.scala:620:{83,105}] wire [31:0] m_interrupts = _m_interrupts_T_2 ? _m_interrupts_T_5 : 32'h0; // @[CSR.scala:620:{25,31,83}] wire _s_interrupts_T_4 = _s_interrupts_T_1; // @[CSR.scala:621:{49,78}] wire _s_interrupts_T_5 = _s_interrupts_T_4; // @[CSR.scala:621:{31,78}] wire _any_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76] wire _which_T = d_interrupts[14]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76] wire _which_T_1 = d_interrupts[13]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76] wire _which_T_2 = d_interrupts[12]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76] wire _which_T_3 = d_interrupts[11]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76] wire _which_T_4 = d_interrupts[3]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76] wire _which_T_5 = d_interrupts[7]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76] wire _which_T_6 = d_interrupts[9]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76] wire _which_T_7 = d_interrupts[1]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76] wire _which_T_8 = d_interrupts[5]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76] wire _which_T_9 = d_interrupts[10]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76] wire _which_T_10 = d_interrupts[2]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76] wire _which_T_11 = d_interrupts[6]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76] wire _which_T_12 = d_interrupts[8]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76] wire _which_T_13 = d_interrupts[0]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76] wire _which_T_14 = d_interrupts[4]; // @[CSR.scala:615:42, :1637:76, :1638:91] wire _any_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76] wire _which_T_15 = m_interrupts[15]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76] wire _which_T_16 = m_interrupts[14]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76] wire _which_T_17 = m_interrupts[13]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76] wire _which_T_18 = m_interrupts[12]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76] wire _which_T_19 = m_interrupts[11]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76] wire _which_T_20 = m_interrupts[3]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76] wire _which_T_21 = m_interrupts[7]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76] wire _which_T_22 = m_interrupts[9]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76] wire _which_T_23 = m_interrupts[1]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76] wire _which_T_24 = m_interrupts[5]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76] wire _which_T_25 = m_interrupts[10]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76] wire _which_T_26 = m_interrupts[2]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76] wire _which_T_27 = m_interrupts[6]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76] wire _which_T_28 = m_interrupts[8]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76] wire _which_T_29 = m_interrupts[0]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76] wire _which_T_30 = m_interrupts[4]; // @[CSR.scala:620:25, :1637:76, :1638:91] wire _any_T_63 = _any_T | _any_T_1; // @[CSR.scala:1637:{76,90}] wire _any_T_64 = _any_T_63 | _any_T_2; // @[CSR.scala:1637:{76,90}] wire _any_T_65 = _any_T_64 | _any_T_3; // @[CSR.scala:1637:{76,90}] wire _any_T_66 = _any_T_65 | _any_T_4; // @[CSR.scala:1637:{76,90}] wire _any_T_67 = _any_T_66 | _any_T_5; // @[CSR.scala:1637:{76,90}] wire _any_T_68 = _any_T_67 | _any_T_6; // @[CSR.scala:1637:{76,90}] wire _any_T_69 = _any_T_68 | _any_T_7; // @[CSR.scala:1637:{76,90}] wire _any_T_70 = _any_T_69 | _any_T_8; // @[CSR.scala:1637:{76,90}] wire _any_T_71 = _any_T_70 | _any_T_9; // @[CSR.scala:1637:{76,90}] wire _any_T_72 = _any_T_71 | _any_T_10; // @[CSR.scala:1637:{76,90}] wire _any_T_73 = _any_T_72 | _any_T_11; // @[CSR.scala:1637:{76,90}] wire _any_T_74 = _any_T_73 | _any_T_12; // @[CSR.scala:1637:{76,90}] wire _any_T_75 = _any_T_74 | _any_T_13; // @[CSR.scala:1637:{76,90}] wire _any_T_76 = _any_T_75 | _any_T_14; // @[CSR.scala:1637:{76,90}] wire _any_T_77 = _any_T_76; // @[CSR.scala:1637:90] wire _any_T_78 = _any_T_77 | _any_T_15; // @[CSR.scala:1637:{76,90}] wire _any_T_79 = _any_T_78 | _any_T_16; // @[CSR.scala:1637:{76,90}] wire _any_T_80 = _any_T_79 | _any_T_17; // @[CSR.scala:1637:{76,90}] wire _any_T_81 = _any_T_80 | _any_T_18; // @[CSR.scala:1637:{76,90}] wire _any_T_82 = _any_T_81 | _any_T_19; // @[CSR.scala:1637:{76,90}] wire _any_T_83 = _any_T_82 | _any_T_20; // @[CSR.scala:1637:{76,90}] wire _any_T_84 = _any_T_83 | _any_T_21; // @[CSR.scala:1637:{76,90}] wire _any_T_85 = _any_T_84 | _any_T_22; // @[CSR.scala:1637:{76,90}] wire _any_T_86 = _any_T_85 | _any_T_23; // @[CSR.scala:1637:{76,90}] wire _any_T_87 = _any_T_86 | _any_T_24; // @[CSR.scala:1637:{76,90}] wire _any_T_88 = _any_T_87 | _any_T_25; // @[CSR.scala:1637:{76,90}] wire _any_T_89 = _any_T_88 | _any_T_26; // @[CSR.scala:1637:{76,90}] wire _any_T_90 = _any_T_89 | _any_T_27; // @[CSR.scala:1637:{76,90}] wire _any_T_91 = _any_T_90 | _any_T_28; // @[CSR.scala:1637:{76,90}] wire _any_T_92 = _any_T_91 | _any_T_29; // @[CSR.scala:1637:{76,90}] wire _any_T_93 = _any_T_92 | _any_T_30; // @[CSR.scala:1637:{76,90}] wire _any_T_94 = _any_T_93; // @[CSR.scala:1637:90] wire _any_T_95 = _any_T_94; // @[CSR.scala:1637:90] wire _any_T_96 = _any_T_95; // @[CSR.scala:1637:90] wire _any_T_97 = _any_T_96; // @[CSR.scala:1637:90] wire _any_T_98 = _any_T_97; // @[CSR.scala:1637:90] wire _any_T_99 = _any_T_98; // @[CSR.scala:1637:90] wire _any_T_100 = _any_T_99; // @[CSR.scala:1637:90] wire _any_T_101 = _any_T_100; // @[CSR.scala:1637:90] wire _any_T_102 = _any_T_101; // @[CSR.scala:1637:90] wire _any_T_103 = _any_T_102; // @[CSR.scala:1637:90] wire _any_T_104 = _any_T_103; // @[CSR.scala:1637:90] wire _any_T_105 = _any_T_104; // @[CSR.scala:1637:90] wire _any_T_106 = _any_T_105; // @[CSR.scala:1637:90] wire _any_T_107 = _any_T_106; // @[CSR.scala:1637:90] wire _any_T_108 = _any_T_107; // @[CSR.scala:1637:90] wire _any_T_109 = _any_T_108; // @[CSR.scala:1637:90] wire _any_T_110 = _any_T_109; // @[CSR.scala:1637:90] wire _any_T_111 = _any_T_110; // @[CSR.scala:1637:90] wire _any_T_112 = _any_T_111; // @[CSR.scala:1637:90] wire _any_T_113 = _any_T_112; // @[CSR.scala:1637:90] wire _any_T_114 = _any_T_113; // @[CSR.scala:1637:90] wire _any_T_115 = _any_T_114; // @[CSR.scala:1637:90] wire _any_T_116 = _any_T_115; // @[CSR.scala:1637:90] wire _any_T_117 = _any_T_116; // @[CSR.scala:1637:90] wire _any_T_118 = _any_T_117; // @[CSR.scala:1637:90] wire _any_T_119 = _any_T_118; // @[CSR.scala:1637:90] wire _any_T_120 = _any_T_119; // @[CSR.scala:1637:90] wire _any_T_121 = _any_T_120; // @[CSR.scala:1637:90] wire _any_T_122 = _any_T_121; // @[CSR.scala:1637:90] wire _any_T_123 = _any_T_122; // @[CSR.scala:1637:90] wire _any_T_124 = _any_T_123; // @[CSR.scala:1637:90] wire anyInterrupt = _any_T_124; // @[CSR.scala:1637:90] wire [3:0] _which_T_95 = {1'h0, ~_which_T_29, 2'h0}; // @[Mux.scala:50:70] wire [3:0] _which_T_96 = _which_T_28 ? 4'h8 : _which_T_95; // @[Mux.scala:50:70] wire [3:0] _which_T_97 = _which_T_27 ? 4'h6 : _which_T_96; // @[Mux.scala:50:70] wire [3:0] _which_T_98 = _which_T_26 ? 4'h2 : _which_T_97; // @[Mux.scala:50:70] wire [3:0] _which_T_99 = _which_T_25 ? 4'hA : _which_T_98; // @[Mux.scala:50:70] wire [3:0] _which_T_100 = _which_T_24 ? 4'h5 : _which_T_99; // @[Mux.scala:50:70] wire [3:0] _which_T_101 = _which_T_23 ? 4'h1 : _which_T_100; // @[Mux.scala:50:70] wire [3:0] _which_T_102 = _which_T_22 ? 4'h9 : _which_T_101; // @[Mux.scala:50:70] wire [3:0] _which_T_103 = _which_T_21 ? 4'h7 : _which_T_102; // @[Mux.scala:50:70] wire [3:0] _which_T_104 = _which_T_20 ? 4'h3 : _which_T_103; // @[Mux.scala:50:70] wire [3:0] _which_T_105 = _which_T_19 ? 4'hB : _which_T_104; // @[Mux.scala:50:70] wire [3:0] _which_T_106 = _which_T_18 ? 4'hC : _which_T_105; // @[Mux.scala:50:70] wire [3:0] _which_T_107 = _which_T_17 ? 4'hD : _which_T_106; // @[Mux.scala:50:70] wire [3:0] _which_T_108 = _which_T_16 ? 4'hE : _which_T_107; // @[Mux.scala:50:70] wire [3:0] _which_T_109 = _which_T_15 ? 4'hF : _which_T_108; // @[Mux.scala:50:70] wire [3:0] _which_T_110 = _which_T_109; // @[Mux.scala:50:70] wire [3:0] _which_T_111 = _which_T_14 ? 4'h4 : _which_T_110; // @[Mux.scala:50:70] wire [3:0] _which_T_112 = _which_T_13 ? 4'h0 : _which_T_111; // @[Mux.scala:50:70] wire [3:0] _which_T_113 = _which_T_12 ? 4'h8 : _which_T_112; // @[Mux.scala:50:70] wire [3:0] _which_T_114 = _which_T_11 ? 4'h6 : _which_T_113; // @[Mux.scala:50:70] wire [3:0] _which_T_115 = _which_T_10 ? 4'h2 : _which_T_114; // @[Mux.scala:50:70] wire [3:0] _which_T_116 = _which_T_9 ? 4'hA : _which_T_115; // @[Mux.scala:50:70] wire [3:0] _which_T_117 = _which_T_8 ? 4'h5 : _which_T_116; // @[Mux.scala:50:70] wire [3:0] _which_T_118 = _which_T_7 ? 4'h1 : _which_T_117; // @[Mux.scala:50:70] wire [3:0] _which_T_119 = _which_T_6 ? 4'h9 : _which_T_118; // @[Mux.scala:50:70] wire [3:0] _which_T_120 = _which_T_5 ? 4'h7 : _which_T_119; // @[Mux.scala:50:70] wire [3:0] _which_T_121 = _which_T_4 ? 4'h3 : _which_T_120; // @[Mux.scala:50:70] wire [3:0] _which_T_122 = _which_T_3 ? 4'hB : _which_T_121; // @[Mux.scala:50:70] wire [3:0] _which_T_123 = _which_T_2 ? 4'hC : _which_T_122; // @[Mux.scala:50:70] wire [3:0] _which_T_124 = _which_T_1 ? 4'hD : _which_T_123; // @[Mux.scala:50:70] wire [3:0] whichInterrupt = _which_T ? 4'hE : _which_T_124; // @[Mux.scala:50:70] wire [32:0] _interruptCause_T_3 = {29'h0, whichInterrupt} + 33'h80000000; // @[Mux.scala:50:70] assign interruptCause = _interruptCause_T_3[31:0]; // @[CSR.scala:625:63] assign io_interrupt_cause_0 = interruptCause; // @[CSR.scala:377:7, :625:63] wire _io_interrupt_T = ~io_singleStep_0; // @[CSR.scala:377:7, :626:36] wire _io_interrupt_T_1 = anyInterrupt & _io_interrupt_T; // @[CSR.scala:626:{33,36}, :1637:90] wire _io_interrupt_T_2 = _io_interrupt_T_1 | reg_singleStepped; // @[CSR.scala:486:30, :626:{33,51}] wire _io_interrupt_T_3 = reg_debug | io_status_cease_0; // @[CSR.scala:377:7, :482:26, :626:88] wire _io_interrupt_T_4 = ~_io_interrupt_T_3; // @[CSR.scala:626:{76,88}] assign _io_interrupt_T_5 = _io_interrupt_T_2 & _io_interrupt_T_4; // @[CSR.scala:626:{51,73,76}] assign io_interrupt_0 = _io_interrupt_T_5; // @[CSR.scala:377:7, :626:73] assign io_pmp_0_cfg_l_0 = pmp_cfg_l; // @[PMP.scala:24:19] assign io_pmp_0_cfg_a_0 = pmp_cfg_a; // @[PMP.scala:24:19] assign io_pmp_0_cfg_x_0 = pmp_cfg_x; // @[PMP.scala:24:19] assign io_pmp_0_cfg_w_0 = pmp_cfg_w; // @[PMP.scala:24:19] assign io_pmp_0_cfg_r_0 = pmp_cfg_r; // @[PMP.scala:24:19] assign io_pmp_0_addr_0 = pmp_addr; // @[PMP.scala:24:19] assign io_pmp_0_mask_0 = pmp_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T = pmp_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_1 = {pmp_addr, _pmp_mask_base_T}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base = _pmp_mask_base_T_1; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T = {1'h0, pmp_mask_base} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_1 = _pmp_mask_T[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_2 = ~_pmp_mask_T_1; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_3 = pmp_mask_base & _pmp_mask_T_2; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_4 = {_pmp_mask_T_3, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_mask = _pmp_mask_T_4[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_1_cfg_l_0 = pmp_1_cfg_l; // @[PMP.scala:24:19] assign io_pmp_1_cfg_a_0 = pmp_1_cfg_a; // @[PMP.scala:24:19] assign io_pmp_1_cfg_x_0 = pmp_1_cfg_x; // @[PMP.scala:24:19] assign io_pmp_1_cfg_w_0 = pmp_1_cfg_w; // @[PMP.scala:24:19] assign io_pmp_1_cfg_r_0 = pmp_1_cfg_r; // @[PMP.scala:24:19] assign io_pmp_1_addr_0 = pmp_1_addr; // @[PMP.scala:24:19] assign io_pmp_1_mask_0 = pmp_1_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_3 = pmp_1_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_4 = {pmp_1_addr, _pmp_mask_base_T_3}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_1 = _pmp_mask_base_T_4; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_5 = {1'h0, pmp_mask_base_1} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_6 = _pmp_mask_T_5[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_7 = ~_pmp_mask_T_6; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_8 = pmp_mask_base_1 & _pmp_mask_T_7; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_9 = {_pmp_mask_T_8, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_1_mask = _pmp_mask_T_9[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_2_cfg_l_0 = pmp_2_cfg_l; // @[PMP.scala:24:19] assign io_pmp_2_cfg_a_0 = pmp_2_cfg_a; // @[PMP.scala:24:19] assign io_pmp_2_cfg_x_0 = pmp_2_cfg_x; // @[PMP.scala:24:19] assign io_pmp_2_cfg_w_0 = pmp_2_cfg_w; // @[PMP.scala:24:19] assign io_pmp_2_cfg_r_0 = pmp_2_cfg_r; // @[PMP.scala:24:19] assign io_pmp_2_addr_0 = pmp_2_addr; // @[PMP.scala:24:19] assign io_pmp_2_mask_0 = pmp_2_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_6 = pmp_2_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_7 = {pmp_2_addr, _pmp_mask_base_T_6}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_2 = _pmp_mask_base_T_7; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_10 = {1'h0, pmp_mask_base_2} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_11 = _pmp_mask_T_10[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_12 = ~_pmp_mask_T_11; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_13 = pmp_mask_base_2 & _pmp_mask_T_12; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_14 = {_pmp_mask_T_13, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_2_mask = _pmp_mask_T_14[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_3_cfg_l_0 = pmp_3_cfg_l; // @[PMP.scala:24:19] assign io_pmp_3_cfg_a_0 = pmp_3_cfg_a; // @[PMP.scala:24:19] assign io_pmp_3_cfg_x_0 = pmp_3_cfg_x; // @[PMP.scala:24:19] assign io_pmp_3_cfg_w_0 = pmp_3_cfg_w; // @[PMP.scala:24:19] assign io_pmp_3_cfg_r_0 = pmp_3_cfg_r; // @[PMP.scala:24:19] assign io_pmp_3_addr_0 = pmp_3_addr; // @[PMP.scala:24:19] assign io_pmp_3_mask_0 = pmp_3_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_9 = pmp_3_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_10 = {pmp_3_addr, _pmp_mask_base_T_9}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_3 = _pmp_mask_base_T_10; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_15 = {1'h0, pmp_mask_base_3} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_16 = _pmp_mask_T_15[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_17 = ~_pmp_mask_T_16; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_18 = pmp_mask_base_3 & _pmp_mask_T_17; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_19 = {_pmp_mask_T_18, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_3_mask = _pmp_mask_T_19[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_4_cfg_l_0 = pmp_4_cfg_l; // @[PMP.scala:24:19] assign io_pmp_4_cfg_a_0 = pmp_4_cfg_a; // @[PMP.scala:24:19] assign io_pmp_4_cfg_x_0 = pmp_4_cfg_x; // @[PMP.scala:24:19] assign io_pmp_4_cfg_w_0 = pmp_4_cfg_w; // @[PMP.scala:24:19] assign io_pmp_4_cfg_r_0 = pmp_4_cfg_r; // @[PMP.scala:24:19] assign io_pmp_4_addr_0 = pmp_4_addr; // @[PMP.scala:24:19] assign io_pmp_4_mask_0 = pmp_4_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_12 = pmp_4_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_13 = {pmp_4_addr, _pmp_mask_base_T_12}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_4 = _pmp_mask_base_T_13; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_20 = {1'h0, pmp_mask_base_4} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_21 = _pmp_mask_T_20[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_22 = ~_pmp_mask_T_21; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_23 = pmp_mask_base_4 & _pmp_mask_T_22; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_24 = {_pmp_mask_T_23, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_4_mask = _pmp_mask_T_24[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_5_cfg_l_0 = pmp_5_cfg_l; // @[PMP.scala:24:19] assign io_pmp_5_cfg_a_0 = pmp_5_cfg_a; // @[PMP.scala:24:19] assign io_pmp_5_cfg_x_0 = pmp_5_cfg_x; // @[PMP.scala:24:19] assign io_pmp_5_cfg_w_0 = pmp_5_cfg_w; // @[PMP.scala:24:19] assign io_pmp_5_cfg_r_0 = pmp_5_cfg_r; // @[PMP.scala:24:19] assign io_pmp_5_addr_0 = pmp_5_addr; // @[PMP.scala:24:19] assign io_pmp_5_mask_0 = pmp_5_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_15 = pmp_5_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_16 = {pmp_5_addr, _pmp_mask_base_T_15}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_5 = _pmp_mask_base_T_16; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_25 = {1'h0, pmp_mask_base_5} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_26 = _pmp_mask_T_25[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_27 = ~_pmp_mask_T_26; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_28 = pmp_mask_base_5 & _pmp_mask_T_27; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_29 = {_pmp_mask_T_28, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_5_mask = _pmp_mask_T_29[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_6_cfg_l_0 = pmp_6_cfg_l; // @[PMP.scala:24:19] assign io_pmp_6_cfg_a_0 = pmp_6_cfg_a; // @[PMP.scala:24:19] assign io_pmp_6_cfg_x_0 = pmp_6_cfg_x; // @[PMP.scala:24:19] assign io_pmp_6_cfg_w_0 = pmp_6_cfg_w; // @[PMP.scala:24:19] assign io_pmp_6_cfg_r_0 = pmp_6_cfg_r; // @[PMP.scala:24:19] assign io_pmp_6_addr_0 = pmp_6_addr; // @[PMP.scala:24:19] assign io_pmp_6_mask_0 = pmp_6_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_18 = pmp_6_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_19 = {pmp_6_addr, _pmp_mask_base_T_18}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_6 = _pmp_mask_base_T_19; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_30 = {1'h0, pmp_mask_base_6} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_31 = _pmp_mask_T_30[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_32 = ~_pmp_mask_T_31; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_33 = pmp_mask_base_6 & _pmp_mask_T_32; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_34 = {_pmp_mask_T_33, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_6_mask = _pmp_mask_T_34[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] assign io_pmp_7_cfg_l_0 = pmp_7_cfg_l; // @[PMP.scala:24:19] assign io_pmp_7_cfg_a_0 = pmp_7_cfg_a; // @[PMP.scala:24:19] assign io_pmp_7_cfg_x_0 = pmp_7_cfg_x; // @[PMP.scala:24:19] assign io_pmp_7_cfg_w_0 = pmp_7_cfg_w; // @[PMP.scala:24:19] assign io_pmp_7_cfg_r_0 = pmp_7_cfg_r; // @[PMP.scala:24:19] assign io_pmp_7_addr_0 = pmp_7_addr; // @[PMP.scala:24:19] assign io_pmp_7_mask_0 = pmp_7_mask; // @[PMP.scala:24:19] wire _pmp_mask_base_T_21 = pmp_7_cfg_a[0]; // @[PMP.scala:24:19, :57:31] wire [30:0] _pmp_mask_base_T_22 = {pmp_7_addr, _pmp_mask_base_T_21}; // @[PMP.scala:24:19, :57:{19,31}] wire [30:0] pmp_mask_base_7 = _pmp_mask_base_T_22; // @[PMP.scala:57:{19,36}] wire [31:0] _pmp_mask_T_35 = {1'h0, pmp_mask_base_7} + 32'h1; // @[PMP.scala:57:36, :58:23] wire [30:0] _pmp_mask_T_36 = _pmp_mask_T_35[30:0]; // @[PMP.scala:58:23] wire [30:0] _pmp_mask_T_37 = ~_pmp_mask_T_36; // @[PMP.scala:58:{16,23}] wire [30:0] _pmp_mask_T_38 = pmp_mask_base_7 & _pmp_mask_T_37; // @[PMP.scala:57:36, :58:{14,16}] wire [32:0] _pmp_mask_T_39 = {_pmp_mask_T_38, 2'h3}; // @[PMP.scala:58:{8,14}] assign pmp_7_mask = _pmp_mask_T_39[31:0]; // @[PMP.scala:24:19, :27:14, :58:8] reg [31:0] reg_misa; // @[CSR.scala:648:25] assign io_status_isa_0 = reg_misa; // @[CSR.scala:377:7, :648:25] wire [1:0] read_mstatus_lo_lo_lo_hi = {io_status_mie_0, 1'h0}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_lo_lo_lo = {read_mstatus_lo_lo_lo_hi, 2'h0}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_lo_lo_hi_hi_hi = {1'h0, io_status_mpie_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_lo_lo_hi_hi = {read_mstatus_lo_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [4:0] read_mstatus_lo_lo_hi = {read_mstatus_lo_lo_hi_hi, 2'h0}; // @[CSR.scala:649:32] wire [8:0] read_mstatus_lo_lo = {read_mstatus_lo_lo_hi, read_mstatus_lo_lo_lo}; // @[CSR.scala:649:32] wire [3:0] read_mstatus_lo_hi_lo_lo = {io_status_mpp_0, 2'h0}; // @[CSR.scala:377:7, :649:32] wire [7:0] read_mstatus_lo_hi_lo = {4'h0, read_mstatus_lo_hi_lo_lo}; // @[CSR.scala:649:32] wire [12:0] read_mstatus_lo_hi = {5'h0, read_mstatus_lo_hi_lo}; // @[CSR.scala:649:32] wire [21:0] read_mstatus_lo = {read_mstatus_lo_hi, read_mstatus_lo_lo}; // @[CSR.scala:649:32] wire [1:0] read_mstatus_hi_lo_hi_hi_hi = {io_status_mpv_0, io_status_gva_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_lo_hi_hi = {read_mstatus_hi_lo_hi_hi_hi, 1'h0}; // @[CSR.scala:649:32] wire [5:0] read_mstatus_hi_lo_hi = {read_mstatus_hi_lo_hi_hi, 3'h0}; // @[CSR.scala:649:32] wire [17:0] read_mstatus_hi_lo = {read_mstatus_hi_lo_hi, 12'h0}; // @[CSR.scala:649:32] wire [2:0] read_mstatus_hi_hi_lo_hi_hi = {io_status_dv_0, 2'h3}; // @[CSR.scala:377:7, :649:32] wire [3:0] read_mstatus_hi_hi_lo_hi = {read_mstatus_hi_hi_lo_hi_hi, io_status_v_0}; // @[CSR.scala:377:7, :649:32] wire [27:0] read_mstatus_hi_hi_lo = {read_mstatus_hi_hi_lo_hi, 24'h0}; // @[CSR.scala:649:32] wire [33:0] read_mstatus_hi_hi_hi_lo = {io_status_isa_0, 2'h3}; // @[CSR.scala:377:7, :649:32] wire [1:0] read_mstatus_hi_hi_hi_hi_hi = {io_status_debug_0, io_status_cease_0}; // @[CSR.scala:377:7, :649:32] wire [2:0] read_mstatus_hi_hi_hi_hi = {read_mstatus_hi_hi_hi_hi_hi, io_status_wfi_0}; // @[CSR.scala:377:7, :649:32] wire [36:0] read_mstatus_hi_hi_hi = {read_mstatus_hi_hi_hi_hi, read_mstatus_hi_hi_hi_lo}; // @[CSR.scala:649:32] wire [64:0] read_mstatus_hi_hi = {read_mstatus_hi_hi_hi, read_mstatus_hi_hi_lo}; // @[CSR.scala:649:32] wire [82:0] read_mstatus_hi = {read_mstatus_hi_hi, read_mstatus_hi_lo}; // @[CSR.scala:649:32] wire [104:0] _read_mstatus_T = {read_mstatus_hi, read_mstatus_lo}; // @[CSR.scala:649:32] wire [31:0] read_mstatus = _read_mstatus_T[31:0]; // @[package.scala:163:13] wire _read_mtvec_T = reg_mtvec[0]; // @[CSR.scala:512:31, :1666:41] wire [6:0] _read_mtvec_T_1 = _read_mtvec_T ? 7'h7E : 7'h2; // @[CSR.scala:1666:{39,41}] wire [31:0] _read_mtvec_T_3 = {25'h0, _read_mtvec_T_1}; // @[package.scala:174:41] wire [31:0] _read_mtvec_T_4 = ~_read_mtvec_T_3; // @[package.scala:174:{37,41}] wire [31:0] read_mtvec = reg_mtvec & _read_mtvec_T_4; // @[package.scala:174:{35,37}] wire [31:0] notDebugTVec_base = read_mtvec; // @[package.scala:174:35] wire [6:0] _read_stvec_T_1 = _read_stvec_T ? 7'h7E : 7'h2; // @[CSR.scala:1666:{39,41}] wire [31:0] _read_stvec_T_3 = {25'h0, _read_stvec_T_1}; // @[package.scala:174:41] wire [31:0] _read_stvec_T_4 = ~_read_stvec_T_3; // @[package.scala:174:{37,41}] wire [31:0] _notDebugTVec_base_T = read_stvec; // @[package.scala:174:35] wire [1:0] _GEN = {reg_bp_0_control_x, reg_bp_0_control_w}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_lo_lo_hi; // @[CSR.scala:655:48] assign read_mapping_lo_lo_hi = _GEN; // @[CSR.scala:655:48] wire [1:0] newBPC_lo_lo_hi; // @[CSR.scala:1477:67] assign newBPC_lo_lo_hi = _GEN; // @[CSR.scala:655:48, :1477:67] wire [2:0] read_mapping_lo_lo = {read_mapping_lo_lo_hi, reg_bp_0_control_r}; // @[CSR.scala:492:19, :655:48] wire [6:0] read_mapping_lo = {4'h8, read_mapping_lo_lo}; // @[CSR.scala:655:48] wire [3:0] _GEN_0 = {2'h0, reg_bp_0_control_tmatch}; // @[CSR.scala:492:19, :655:48] wire [3:0] read_mapping_hi_lo_lo; // @[CSR.scala:655:48] assign read_mapping_hi_lo_lo = _GEN_0; // @[CSR.scala:655:48] wire [3:0] newBPC_hi_lo_lo; // @[CSR.scala:1477:67] assign newBPC_hi_lo_lo = _GEN_0; // @[CSR.scala:655:48, :1477:67] wire [1:0] _GEN_1 = {reg_bp_0_control_action, 1'h0}; // @[CSR.scala:492:19, :655:48] wire [1:0] read_mapping_hi_lo_hi; // @[CSR.scala:655:48] assign read_mapping_hi_lo_hi = _GEN_1; // @[CSR.scala:655:48] wire [1:0] newBPC_hi_lo_hi; // @[CSR.scala:1477:67] assign newBPC_hi_lo_hi = _GEN_1; // @[CSR.scala:655:48, :1477:67] wire [5:0] read_mapping_hi_lo = {read_mapping_hi_lo_hi, read_mapping_hi_lo_lo}; // @[CSR.scala:655:48] wire [4:0] _GEN_2 = {4'h2, reg_bp_0_control_dmode}; // @[CSR.scala:492:19, :655:48] wire [4:0] read_mapping_hi_hi_hi; // @[CSR.scala:655:48] assign read_mapping_hi_hi_hi = _GEN_2; // @[CSR.scala:655:48] wire [4:0] newBPC_hi_hi_hi; // @[CSR.scala:1477:67] assign newBPC_hi_hi_hi = _GEN_2; // @[CSR.scala:655:48, :1477:67] wire [18:0] read_mapping_hi_hi = {read_mapping_hi_hi_hi, 14'h400}; // @[CSR.scala:655:48] wire [24:0] read_mapping_hi = {read_mapping_hi_hi, read_mapping_hi_lo}; // @[CSR.scala:655:48] wire [31:0] read_mapping_1_2 = {read_mapping_hi, read_mapping_lo}; // @[CSR.scala:655:48] wire [1:0] read_mapping_lo_1 = {read_mapping_lo_hi_1, 1'h0}; // @[CSR.scala:657:47] wire [25:0] read_mapping_3_2 = {read_mapping_hi_1, read_mapping_lo_1}; // @[CSR.scala:657:47] wire [31:0] _read_mapping_T = ~reg_mepc; // @[CSR.scala:505:21, :1665:28] wire _read_mapping_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _debug_csrs_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_1 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_6 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_11 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_16 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire _io_evec_T_21 = reg_misa[2]; // @[CSR.scala:648:25, :1665:45] wire [1:0] _read_mapping_T_2 = {~_read_mapping_T_1, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [31:0] _read_mapping_T_3 = {_read_mapping_T[31:2], _read_mapping_T[1:0] | _read_mapping_T_2}; // @[CSR.scala:1665:{28,31,36}] wire [31:0] read_mapping_10_2 = ~_read_mapping_T_3; // @[CSR.scala:1665:{26,31}] wire [2:0] debug_csrs_lo_lo_hi = {2'h0, reg_dcsr_step}; // @[CSR.scala:403:25, :670:27] wire [4:0] debug_csrs_lo_lo = {debug_csrs_lo_lo_hi, 2'h3}; // @[CSR.scala:670:27] wire [3:0] debug_csrs_lo_hi_lo = {reg_dcsr_cause, reg_dcsr_v}; // @[CSR.scala:403:25, :670:27] wire [5:0] debug_csrs_lo_hi = {2'h0, debug_csrs_lo_hi_lo}; // @[CSR.scala:670:27] wire [10:0] debug_csrs_lo = {debug_csrs_lo_hi, debug_csrs_lo_lo}; // @[CSR.scala:670:27] wire [12:0] debug_csrs_hi_hi_lo = {12'h0, reg_dcsr_ebreakm}; // @[CSR.scala:403:25, :670:27] wire [16:0] debug_csrs_hi_hi = {4'h4, debug_csrs_hi_hi_lo}; // @[CSR.scala:670:27] wire [20:0] debug_csrs_hi = {debug_csrs_hi_hi, 4'h0}; // @[CSR.scala:670:27] wire [31:0] debug_csrs_0_2 = {debug_csrs_hi, debug_csrs_lo}; // @[CSR.scala:670:27] wire [31:0] _debug_csrs_T = ~reg_dpc; // @[CSR.scala:483:20, :1665:28] wire [1:0] _debug_csrs_T_2 = {~_debug_csrs_T_1, 1'h1}; // @[CSR.scala:1665:{36,45}] wire [31:0] _debug_csrs_T_3 = {_debug_csrs_T[31:2], _debug_csrs_T[1:0] | _debug_csrs_T_2}; // @[CSR.scala:1665:{28,31,36}] wire [31:0] debug_csrs_1_2 = ~_debug_csrs_T_3; // @[CSR.scala:1665:{26,31}] wire [1:0] lo_hi_4 = {reg_pmp_0_cfg_x, reg_pmp_0_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_4 = {lo_hi_4, reg_pmp_0_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_4 = {reg_pmp_0_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_6 = {hi_hi_4, reg_pmp_0_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_5 = {reg_pmp_1_cfg_x, reg_pmp_1_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_5 = {lo_hi_5, reg_pmp_1_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_5 = {reg_pmp_1_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_7 = {hi_hi_5, reg_pmp_1_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_6 = {reg_pmp_2_cfg_x, reg_pmp_2_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_6 = {lo_hi_6, reg_pmp_2_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_6 = {reg_pmp_2_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_8 = {hi_hi_6, reg_pmp_2_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_7 = {reg_pmp_3_cfg_x, reg_pmp_3_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_7 = {lo_hi_7, reg_pmp_3_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_7 = {reg_pmp_3_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_9 = {hi_hi_7, reg_pmp_3_cfg_a}; // @[package.scala:45:36] wire [15:0] lo_8 = {hi_7, lo_5, hi_6, lo_4}; // @[package.scala:45:{27,36}] wire [15:0] hi_10 = {hi_9, lo_7, hi_8, lo_6}; // @[package.scala:45:{27,36}] wire [1:0] lo_hi_8 = {reg_pmp_4_cfg_x, reg_pmp_4_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_9 = {lo_hi_8, reg_pmp_4_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_8 = {reg_pmp_4_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_11 = {hi_hi_8, reg_pmp_4_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_9 = {reg_pmp_5_cfg_x, reg_pmp_5_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_10 = {lo_hi_9, reg_pmp_5_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_9 = {reg_pmp_5_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_12 = {hi_hi_9, reg_pmp_5_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_10 = {reg_pmp_6_cfg_x, reg_pmp_6_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_11 = {lo_hi_10, reg_pmp_6_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_10 = {reg_pmp_6_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_13 = {hi_hi_10, reg_pmp_6_cfg_a}; // @[package.scala:45:36] wire [1:0] lo_hi_11 = {reg_pmp_7_cfg_x, reg_pmp_7_cfg_w}; // @[package.scala:45:36] wire [2:0] lo_12 = {lo_hi_11, reg_pmp_7_cfg_r}; // @[package.scala:45:36] wire [2:0] hi_hi_11 = {reg_pmp_7_cfg_l, 2'h0}; // @[package.scala:45:36] wire [4:0] hi_14 = {hi_hi_11, reg_pmp_7_cfg_a}; // @[package.scala:45:36] wire [15:0] lo_13 = {hi_12, lo_10, hi_11, lo_9}; // @[package.scala:45:{27,36}] wire [15:0] hi_15 = {hi_14, lo_12, hi_13, lo_11}; // @[package.scala:45:{27,36}] reg [31:0] reg_custom_0; // @[CSR.scala:798:43] assign io_customCSRs_0_value_0 = reg_custom_0; // @[CSR.scala:377:7, :798:43] wire _reg_custom_read_T = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_1 = io_rw_addr_0 == 12'h7C1; // @[CSR.scala:377:7, :799:50] assign reg_custom_read = _reg_custom_read_T & _reg_custom_read_T_1; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_0_ren_0 = reg_custom_read; // @[CSR.scala:377:7, :799:36] reg [31:0] reg_custom_1; // @[CSR.scala:798:43] assign io_customCSRs_1_value_0 = reg_custom_1; // @[CSR.scala:377:7, :798:43] wire [31:0] _reg_custom_1_T_2 = reg_custom_1; // @[CSR.scala:798:43, :1506:38] wire [31:0] _reg_custom_1_T_6 = reg_custom_1; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_2 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_3 = io_rw_addr_0 == 12'hF12; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_1 = _reg_custom_read_T_2 & _reg_custom_read_T_3; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_1_ren_0 = reg_custom_read_1; // @[CSR.scala:377:7, :799:36] reg [31:0] reg_custom_2; // @[CSR.scala:798:43] assign io_customCSRs_2_value_0 = reg_custom_2; // @[CSR.scala:377:7, :798:43] wire [31:0] _reg_custom_2_T_2 = reg_custom_2; // @[CSR.scala:798:43, :1506:38] wire [31:0] _reg_custom_2_T_6 = reg_custom_2; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_4 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_5 = io_rw_addr_0 == 12'hF11; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_2 = _reg_custom_read_T_4 & _reg_custom_read_T_5; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_2_ren_0 = reg_custom_read_2; // @[CSR.scala:377:7, :799:36] reg [31:0] reg_custom_3; // @[CSR.scala:798:43] assign io_customCSRs_3_value_0 = reg_custom_3; // @[CSR.scala:377:7, :798:43] wire [31:0] _reg_custom_3_T_2 = reg_custom_3; // @[CSR.scala:798:43, :1506:38] wire [31:0] _reg_custom_3_T_6 = reg_custom_3; // @[CSR.scala:798:43, :1531:39] wire _reg_custom_read_T_6 = |io_rw_cmd_0; // @[CSR.scala:377:7, :799:26] wire _reg_custom_read_T_7 = io_rw_addr_0 == 12'hF13; // @[CSR.scala:377:7, :799:50] assign reg_custom_read_3 = _reg_custom_read_T_6 & _reg_custom_read_T_7; // @[CSR.scala:799:{26,36,50}] assign io_customCSRs_3_ren_0 = reg_custom_read_3; // @[CSR.scala:377:7, :799:36] wire [12:0] decoded_addr_addr = {io_status_v_0, io_rw_addr_0}; // @[CSR.scala:377:7, :851:19] wire [11:0] decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22] wire [11:0] decoded_addr_decoded_decoded_invInputs = ~decoded_addr_decoded_decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [195:0] decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [195:0] decoded_addr_decoded_decoded; // @[pla.scala:81:23] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_150 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_152 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_154 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_156 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_158 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_161 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_163 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_165 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_167 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_169 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_171 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_173 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_175 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_177 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_179 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_181 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_183 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_185 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_187 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_189 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_192 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_194 = decoded_addr_decoded_decoded_invInputs[0]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_152 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_153 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_156 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_157 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_160 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_163 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_164 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_167 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_168 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_171 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_172 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_175 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_176 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_179 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_180 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_183 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_184 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_187 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_188 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_191 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_194 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_195 = decoded_addr_decoded_decoded_invInputs[1]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_152 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_153 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_154 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_155 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_160 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_161 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_162 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_167 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_168 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_169 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_170 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_175 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_176 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_177 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_178 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_183 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_184 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_185 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_186 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_191 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_192 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_193 = decoded_addr_decoded_decoded_invInputs[2]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_150 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_151 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_160 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_161 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_162 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_163 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_164 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_165 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_166 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_175 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_176 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_177 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_178 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_179 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_180 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_181 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_182 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_191 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_192 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_193 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_194 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_195 = decoded_addr_decoded_decoded_invInputs[3]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_160 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_161 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_162 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_163 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_164 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_165 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_166 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_167 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_168 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_169 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_170 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_171 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_172 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_173 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_174 = decoded_addr_decoded_decoded_invInputs[4]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_149 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_150 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_151 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_152 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_153 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_154 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_155 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_156 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_157 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_158 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_159 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_160 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_161 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_162 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_163 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_164 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_165 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_166 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_167 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_168 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_169 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_170 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_171 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_172 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_173 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_174 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_175 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_176 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_177 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_178 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_179 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_180 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_181 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_182 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_183 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_184 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_185 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_186 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_187 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_188 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_189 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_190 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_191 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_192 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_193 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_194 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_195 = decoded_addr_decoded_decoded_invInputs[5]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_148 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_149 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_150 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_151 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_152 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_153 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_154 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_155 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_156 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_157 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_158 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_160 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_160 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_161 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_162 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_163 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_164 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_165 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_166 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_167 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_168 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_169 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_170 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_171 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_172 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_173 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_174 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_175 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_176 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_177 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_178 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_179 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_180 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_181 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_182 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_183 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_184 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_185 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_186 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_187 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_188 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_189 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_191 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_191 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_192 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_193 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_194 = decoded_addr_decoded_decoded_invInputs[6]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_148 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_149 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_150 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_151 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_152 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_153 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_154 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_155 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_156 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_157 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_158 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_190 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_191 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_192 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_193 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_194 = decoded_addr_decoded_decoded_invInputs[7]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_190 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_191 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_192 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_193 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_194 = decoded_addr_decoded_decoded_plaInput[8]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_190 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_191 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_192 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_193 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_194 = decoded_addr_decoded_decoded_plaInput[9]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126 = decoded_addr_decoded_decoded_invInputs[10]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66 = decoded_addr_decoded_decoded_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T = {decoded_addr_decoded_decoded_andMatrixOutputs_hi, decoded_addr_decoded_decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_141_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_190 = decoded_addr_decoded_decoded_andMatrixOutputs_141_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_151 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_153 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_155 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_157 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_159 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_162 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_164 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_166 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_168 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_170 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_172 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_174 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_176 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_178 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_180 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_182 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_184 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_186 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_188 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_190 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_193 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_195 = decoded_addr_decoded_decoded_plaInput[0]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_1 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_1, decoded_addr_decoded_decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_127_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_191 = decoded_addr_decoded_decoded_andMatrixOutputs_127_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_150 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_151 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_156 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_157 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_158 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_159 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_163 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_164 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_165 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_166 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_171 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_172 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_173 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_174 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_179 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_180 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_181 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_182 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_187 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_188 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_189 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_190 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_194 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_195 = decoded_addr_decoded_decoded_plaInput[2]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_2}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_2}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_2 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_2, decoded_addr_decoded_decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_110_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_187 = decoded_addr_decoded_decoded_andMatrixOutputs_110_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_3}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_3 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_3, decoded_addr_decoded_decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_85_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_189 = decoded_addr_decoded_decoded_andMatrixOutputs_85_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65 = decoded_addr_decoded_decoded_plaInput[5]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_37_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_178 = decoded_addr_decoded_decoded_andMatrixOutputs_37_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_150 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_151 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_154 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_155 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_158 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_159 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_161 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_162 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_165 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_166 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_169 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_170 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_173 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_174 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_177 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_178 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_181 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_182 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_185 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_186 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_189 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_190 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_192 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_193 = decoded_addr_decoded_decoded_plaInput[1]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_179_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_175 = decoded_addr_decoded_decoded_andMatrixOutputs_179_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_4, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_6}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_6}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_64_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_170 = decoded_addr_decoded_decoded_andMatrixOutputs_64_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_5, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_7}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_7}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_7}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_128_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_165 = decoded_addr_decoded_decoded_andMatrixOutputs_128_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_6, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_8}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_8}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_8}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_8}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_132_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_160 = decoded_addr_decoded_decoded_andMatrixOutputs_132_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_9}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_7, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_9}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_9}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_9}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_9}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_7_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_155 = decoded_addr_decoded_decoded_andMatrixOutputs_7_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_152 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_153 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_154 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_155 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_156 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_157 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_158 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_159 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_167 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_168 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_169 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_170 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_171 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_172 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_173 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_174 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_183 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_184 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_185 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_186 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_187 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_188 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_189 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_190 = decoded_addr_decoded_decoded_plaInput[3]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_8, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_8}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_10}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_10}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_10}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_10}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_10}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_lo_10}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_54_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_150 = decoded_addr_decoded_decoded_andMatrixOutputs_54_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_9, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_9}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_11}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_11}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_11}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_11}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_11}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_11}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_lo_11}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_189_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_145 = decoded_addr_decoded_decoded_andMatrixOutputs_189_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_10, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_10}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_12}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_12}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_12}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_12}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_12}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_12}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_12}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_lo_12}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_12_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_12; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_140 = decoded_addr_decoded_decoded_andMatrixOutputs_12_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_11, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_13}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_13}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_13}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_13}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_13}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_13}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_13}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_13}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_lo_13}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_154_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_13; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_135 = decoded_addr_decoded_decoded_andMatrixOutputs_154_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_12, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_12}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_14}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_14}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_14}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_14}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_14}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_14}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_14}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_lo_14}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_156_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_14; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_130 = decoded_addr_decoded_decoded_andMatrixOutputs_156_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_13, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_13}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_15}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_15}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_15}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_15}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_15}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_15}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_15}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_lo_15}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_181_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_15; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_125 = decoded_addr_decoded_decoded_andMatrixOutputs_181_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_14, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_14}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_16}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_16}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_16}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_16}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_16}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_16}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_16}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_lo_16}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_108_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_16; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_120 = decoded_addr_decoded_decoded_andMatrixOutputs_108_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_15, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_15}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_17}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_17}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_17}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_17}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_17}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_17}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_17}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_17}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_lo_17}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_8_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_17; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_115 = decoded_addr_decoded_decoded_andMatrixOutputs_8_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_150 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_151 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_152 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_153 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_154 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_155 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_156 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_157 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_158 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_159 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_175 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_176 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_177 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_178 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_179 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_180 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_181 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_182 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_183 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_184 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_185 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_186 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_187 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_188 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_189 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_190 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_191 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_192 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_193 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_194 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_195 = decoded_addr_decoded_decoded_plaInput[4]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_16, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_16}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_18}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_18}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_18}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_18}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_18}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_18}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_18}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_lo_18}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_76_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_18; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_110 = decoded_addr_decoded_decoded_andMatrixOutputs_76_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_17, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_17}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_19}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_19}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_19}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_19}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_19}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_19}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_19}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_lo_19}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_105_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_19; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_105 = decoded_addr_decoded_decoded_andMatrixOutputs_105_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_18, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_18}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_20}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_20}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_20}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_20}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_20}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_20}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_20}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_lo_20}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_171_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_20; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_100 = decoded_addr_decoded_decoded_andMatrixOutputs_171_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_19, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_19}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_21}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_21}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_21}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_21}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_21}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_21}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_21}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_21}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_lo_21}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_19_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_21; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_95 = decoded_addr_decoded_decoded_andMatrixOutputs_19_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_20, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_20}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_22}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_22}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_22}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_22}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_22}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_22}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_22}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_lo_22}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_109_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_22; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_90 = decoded_addr_decoded_decoded_andMatrixOutputs_109_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_21, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_21}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_23}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_23}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_23}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_23}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_23}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_23}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_23}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_lo_23}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_177_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_23; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_85 = decoded_addr_decoded_decoded_andMatrixOutputs_177_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_22, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_22}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_24}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_24}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_24}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_24}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_24}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_24}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_lo_24}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_183_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_24; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_80 = decoded_addr_decoded_decoded_andMatrixOutputs_183_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_23, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_23}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_25}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_25}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_25}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_25}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_25}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_25}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_25}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_lo_25}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_25_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_25; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_75 = decoded_addr_decoded_decoded_andMatrixOutputs_25_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_26}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_24, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_24}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_26}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_26}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_26}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_26}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_26}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_26}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_26}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_lo_26}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_113_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_26; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_70 = decoded_addr_decoded_decoded_andMatrixOutputs_113_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_25, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_25}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_27}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_27}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_27}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_27}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_27}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_27}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_27}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_27}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_lo_27}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_82_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_27; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_65 = decoded_addr_decoded_decoded_andMatrixOutputs_82_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_26, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_26}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_28}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_28}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_28}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_28}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_28}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_28}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_28}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_28}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_lo_28}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_40_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_28; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_60 = decoded_addr_decoded_decoded_andMatrixOutputs_40_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_29}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_27, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_27}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_29}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_29}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_29}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_29}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_29}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_29}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_29}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_29}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_lo_29}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_35_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_29; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_55 = decoded_addr_decoded_decoded_andMatrixOutputs_35_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_30}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_28, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_28}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_30}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_30}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_30}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_30}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_30}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_30}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_30}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_lo_30}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_80_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_30; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_50 = decoded_addr_decoded_decoded_andMatrixOutputs_80_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_29, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_29}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_31}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_31}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_31}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_31}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_31}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_31}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_31}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_31}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_lo_31}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_45_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_31; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_45 = decoded_addr_decoded_decoded_andMatrixOutputs_45_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_30, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_30}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_32}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_32}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_32}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_32}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_32}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_32}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_32}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_lo_32}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_34_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_32; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_40 = decoded_addr_decoded_decoded_andMatrixOutputs_34_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_33}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_31, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_31}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_33}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_33}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_33}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_33}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_33}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_33}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_33}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_lo_33}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_185_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_33; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_35 = decoded_addr_decoded_decoded_andMatrixOutputs_185_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66 = decoded_addr_decoded_decoded_plaInput[6]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_32, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_32}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_34}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_34}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_34}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_34}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_34}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_34}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_lo_34}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_83_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_34; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_186 = decoded_addr_decoded_decoded_andMatrixOutputs_83_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_33, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_33}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_35}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_35}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_35}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_35}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_35}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_35}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_lo_35}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_129_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_35; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_185 = decoded_addr_decoded_decoded_andMatrixOutputs_129_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_34, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_34}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_36}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_36}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_36}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_36}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_36}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_36}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_lo_36}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_102_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_36; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_183 = decoded_addr_decoded_decoded_andMatrixOutputs_102_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_35, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_35}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_37}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_37}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_37}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_37}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_37}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_37}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_37}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_37}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_lo_37}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_158_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_37; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_184 = decoded_addr_decoded_decoded_andMatrixOutputs_158_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_38}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_38}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_38}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_38}; // @[pla.scala:98:53] wire [9:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_lo_38}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_157_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_38; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_188 = decoded_addr_decoded_decoded_andMatrixOutputs_157_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_159 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_160 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_161 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_162 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_163 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_164 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_165 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_166 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_167 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_168 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_169 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_170 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_171 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_172 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_173 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_174 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_175 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_176 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_177 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_178 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_179 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_180 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_181 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_182 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_183 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_184 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_185 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_186 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_187 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_188 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_189 = decoded_addr_decoded_decoded_plaInput[7]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_38}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_36, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_36}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_39}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_39}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_39}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_39}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_39}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_39}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_lo_39}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_100_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_39; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_24 = decoded_addr_decoded_decoded_andMatrixOutputs_100_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_39}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_37, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_37}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_40}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_40}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_40}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_40}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_40}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_40}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_lo_40}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_55_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_40; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_23 = decoded_addr_decoded_decoded_andMatrixOutputs_55_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_40}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_38, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_38}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_41}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_41}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_41}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_41}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_41}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_41}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_lo_41}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_79_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_41; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_22 = decoded_addr_decoded_decoded_andMatrixOutputs_79_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_41}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_39, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_39}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_42}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_42}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_42}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_42}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_42}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_42}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_42}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_lo_42}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_28_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_42; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_21 = decoded_addr_decoded_decoded_andMatrixOutputs_28_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_42}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_40, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_40}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_43}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_43}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_43}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_43}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_43}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_43}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_lo_43}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_11_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_43; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_20 = decoded_addr_decoded_decoded_andMatrixOutputs_11_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_43}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_41, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_41}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_44}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_44}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_44}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_44}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_44}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_lo_44}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_52_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_44; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_19 = decoded_addr_decoded_decoded_andMatrixOutputs_52_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_44}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_42, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_42}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_45}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_45}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_45}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_45}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_45}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_lo_45}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_21_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_45; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_18 = decoded_addr_decoded_decoded_andMatrixOutputs_21_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_45}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_43, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_43}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_46}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_46}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_46}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_46}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_46}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_46}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_lo_46}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_111_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_46; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_17 = decoded_addr_decoded_decoded_andMatrixOutputs_111_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_46}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_44, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_44}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_47}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_47}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_47}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_47}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_47}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_47}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_lo_47}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_73_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_47; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_16 = decoded_addr_decoded_decoded_andMatrixOutputs_73_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_47}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_45, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_45}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_48}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_48}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_48}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_48}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_lo_48}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_106_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_48; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_15 = decoded_addr_decoded_decoded_andMatrixOutputs_106_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_48}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_46, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_46}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_49}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_49}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_49}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_49}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_lo_49}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_120_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_49; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_14 = decoded_addr_decoded_decoded_andMatrixOutputs_120_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_49}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_47, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_47}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_50}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_50}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_50}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_50}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_50}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_lo_50}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_138_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_50; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_13 = decoded_addr_decoded_decoded_andMatrixOutputs_138_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_50}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_48, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_48}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_51}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_51}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_51}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_51}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_51}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_51}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_51}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_lo_51}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_112_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_51; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_12 = decoded_addr_decoded_decoded_andMatrixOutputs_112_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_51}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_49, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_49}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_52}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_52}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_52}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_52}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_52}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_52}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_lo_52}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_180_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_52; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_11 = decoded_addr_decoded_decoded_andMatrixOutputs_180_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_52}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_50, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_50}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_53}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_53}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_53}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_53}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_53}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_53}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_lo_53}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_89_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_53; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_10 = decoded_addr_decoded_decoded_andMatrixOutputs_89_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_53}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_51, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_51}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_54}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_54}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_54}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_54}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_54}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_54}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_54}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_lo_54}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_46_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_54; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_9 = decoded_addr_decoded_decoded_andMatrixOutputs_46_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_54}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_52, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_52}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_55}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_55}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_55}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_55}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_55}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_55}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_55}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_lo_55}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_186_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_55; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_8 = decoded_addr_decoded_decoded_andMatrixOutputs_186_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_55}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_53, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_53}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_56}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_56}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_56}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_56}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_56}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_56}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_lo_56}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_118_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_56; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_7 = decoded_addr_decoded_decoded_andMatrixOutputs_118_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_56}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_54, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_54}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_57}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_57}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_57}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_57}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_57}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_57}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_lo_57}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_140_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_57; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_6 = decoded_addr_decoded_decoded_andMatrixOutputs_140_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_57}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_55, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_55}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_58}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_58}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_58}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_58}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_58}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_58}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_58}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_58}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_lo_58}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_195_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_58; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_5 = decoded_addr_decoded_decoded_andMatrixOutputs_195_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_143 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_144 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_145 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_146 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_147 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_148 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_149 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_150 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_151 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_152 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_153 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_154 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_155 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_156 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_157 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_159 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_159 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_160 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_161 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_162 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_163 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_164 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_165 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_166 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_167 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_168 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_169 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_170 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_171 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_172 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_173 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_174 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_175 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_176 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_177 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_178 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_179 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_180 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_181 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_182 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_183 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_184 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_185 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_186 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_187 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_188 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_190 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_190 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_191 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_192 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_193 = decoded_addr_decoded_decoded_plaInput[10]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_58}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_56, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_56}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_59}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_59}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_59}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_59}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_59}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_59}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_59}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_59}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_lo_59}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_147_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_59; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_195 = decoded_addr_decoded_decoded_andMatrixOutputs_147_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_59}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_57, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_57}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_60}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_60}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_60}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_60}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_60}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_60}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_60}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_lo_60}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_191_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_60; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_194 = decoded_addr_decoded_decoded_andMatrixOutputs_191_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_60}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_58, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_58}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_61}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_61}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_61}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_61}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_61}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_61}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_61}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_lo_61}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_168_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_61; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_193 = decoded_addr_decoded_decoded_andMatrixOutputs_168_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_61}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_59, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_59}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_62}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_62}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_62}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_62}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_62}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_62}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_62}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_62}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_lo_62}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_65_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_62; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_192 = decoded_addr_decoded_decoded_andMatrixOutputs_65_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_62}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_60, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_60}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_63}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_63}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_63}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_63}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_63}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_63}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_63}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_lo_63}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_1_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_63; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_181 = decoded_addr_decoded_decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_63}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_61, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_61}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_64}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_64}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_64}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_64}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_lo_64}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_57_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_64; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_180 = decoded_addr_decoded_decoded_andMatrixOutputs_57_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_64}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_65}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_65}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_65}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_65}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_65}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_65}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_65}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_lo_65}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_26_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_65; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_179 = decoded_addr_decoded_decoded_andMatrixOutputs_26_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_66}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_66}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_66}; // @[pla.scala:90:45, :98:53] wire [5:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_lo_66}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_13_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_66; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_4 = decoded_addr_decoded_decoded_andMatrixOutputs_13_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_132 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_133 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_134 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_135 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_136 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_137 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_138 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_139 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_140 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_141 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_142 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_143 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_144 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_145 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_146 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_147 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_148 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_149 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_150 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_151 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_158 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_152 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_153 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_154 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_155 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_156 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_157 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_158 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_159 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_160 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_161 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_162 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_163 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_164 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_165 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_166 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_167 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_168 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_169 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_170 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_171 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_172 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_173 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_174 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_175 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_176 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_177 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_178 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_179 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_180 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_181 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_189 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_182 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_183 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_184 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_185 = decoded_addr_decoded_decoded_plaInput[11]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_65}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_66}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_66}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_67}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_67}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_67}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_67}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_66}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_lo_67}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_95_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_67; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_177 = decoded_addr_decoded_decoded_andMatrixOutputs_95_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_66}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_62, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_62}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_67}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_67}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_67}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_68}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_68}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_68}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_67}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_lo_68}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_99_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_68; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_176 = decoded_addr_decoded_decoded_andMatrixOutputs_99_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_67}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_63, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_63}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_68}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_68}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_68}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_69}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_69}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_69}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_69}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_68}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_lo_69}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_115_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_69; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_174 = decoded_addr_decoded_decoded_andMatrixOutputs_115_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_68}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_64, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_64}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_69}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_69}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_69}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_70}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_70}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_70}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_70}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_69}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_lo_70}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_27_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_70; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_169 = decoded_addr_decoded_decoded_andMatrixOutputs_27_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_69}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_65, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_65}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_70}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_70}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_70}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_71}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_71}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_70}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_lo_71}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_170_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_71; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_164 = decoded_addr_decoded_decoded_andMatrixOutputs_170_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_70}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_66, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_66}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_71}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_71}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_71}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_72}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_72}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_71}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_lo_72}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_192_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_72; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_159 = decoded_addr_decoded_decoded_andMatrixOutputs_192_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_71}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_67, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_67}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_72}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_72}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_72}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_73}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_73}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_73}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_72}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_lo_73}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_96_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_73; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_154 = decoded_addr_decoded_decoded_andMatrixOutputs_96_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_72}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_68, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_68}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_73}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_73}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_73}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_74}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_74}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_74}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_73}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_lo_74}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_182_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_74; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_149 = decoded_addr_decoded_decoded_andMatrixOutputs_182_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_73}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_69, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_69}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_74}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_74}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_74}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_75}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_75}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_74}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_lo_75}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_51_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_75; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_144 = decoded_addr_decoded_decoded_andMatrixOutputs_51_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_74}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_70, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_70}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_75}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_75}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_75}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_76}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_76}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_75}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_lo_76}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_33_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_76; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_139 = decoded_addr_decoded_decoded_andMatrixOutputs_33_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_75}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_71, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_71}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_76}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_76}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_76}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_77}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_77}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_77}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_76}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_lo_77}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_78_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_77; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_134 = decoded_addr_decoded_decoded_andMatrixOutputs_78_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_76}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_72, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_72}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_77}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_77}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_77}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_78}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_78}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_78}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_77}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_lo_78}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_69_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_78; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_129 = decoded_addr_decoded_decoded_andMatrixOutputs_69_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_77}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_73, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_73}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_78}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_78}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_78}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_79}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_79}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_78}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_lo_79}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_176_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_79; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_124 = decoded_addr_decoded_decoded_andMatrixOutputs_176_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_78}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_74, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_74}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_79}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_79}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_79}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_80}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_80}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_79}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_lo_80}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_10_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_80; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_119 = decoded_addr_decoded_decoded_andMatrixOutputs_10_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_79}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_75, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_75}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_80}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_80}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_80}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_81}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_81}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_81}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_80}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_lo_81}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_148_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_81; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_114 = decoded_addr_decoded_decoded_andMatrixOutputs_148_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_80}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_76, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_76}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_81}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_81}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_81}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_82}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_82}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_82}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_81}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_lo_82}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_3_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_82; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_109 = decoded_addr_decoded_decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_81}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_77, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_77}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_82}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_82}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_82}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_83}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_83}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_82}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_lo_83}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_88_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_83; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_104 = decoded_addr_decoded_decoded_andMatrixOutputs_88_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_82}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_78, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_78}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_83}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_83}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_83}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_84}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_84}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_83}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_lo_84}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_172_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_84; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_99 = decoded_addr_decoded_decoded_andMatrixOutputs_172_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_83}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_79, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_79}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_84}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_84}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_84}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_85}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_85}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_85}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_84}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_lo_85}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_123_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_85; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_94 = decoded_addr_decoded_decoded_andMatrixOutputs_123_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_84}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_80, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_80}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_85}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_85}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_85}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_86}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_85}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_lo_86}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_2_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_86; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_89 = decoded_addr_decoded_decoded_andMatrixOutputs_2_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_85}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_81, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_81}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_86}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_86}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_86}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_87}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_86}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_lo_87}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_29_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_87; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_84 = decoded_addr_decoded_decoded_andMatrixOutputs_29_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_86}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_82, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_82}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_87}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_87}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_87}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_88}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_87}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_lo_88}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_18_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_88; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_79 = decoded_addr_decoded_decoded_andMatrixOutputs_18_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_87}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_83, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_83}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_88}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_88}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_88}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_89}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_89}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_88}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_lo_89}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_184_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_89; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_74 = decoded_addr_decoded_decoded_andMatrixOutputs_184_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_88}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_84, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_84}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_89}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_89}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_89}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_90}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_90}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_90}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_89}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_lo_90}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_173_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_90; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_69 = decoded_addr_decoded_decoded_andMatrixOutputs_173_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_89}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_85, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_85}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_90}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_90}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_90}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_91}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_91}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_91}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_90}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_lo_91}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_16_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_91; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_64 = decoded_addr_decoded_decoded_andMatrixOutputs_16_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_90}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_86, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_86}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_91}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_91}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_91}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_92}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_92}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_92}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_91}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_lo_92}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_107_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_92; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_59 = decoded_addr_decoded_decoded_andMatrixOutputs_107_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_91}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_87, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_87}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_92}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_92}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_92}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_93}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_93}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_93}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_93}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_92}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_lo_93}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_117_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_93; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_54 = decoded_addr_decoded_decoded_andMatrixOutputs_117_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_92}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_88, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_88}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_93}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_93}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_93}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_94}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_94}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_93}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_lo_94}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_75_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_94; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_49 = decoded_addr_decoded_decoded_andMatrixOutputs_75_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_93}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_89, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_89}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_94}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_94}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_94}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_95}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_95}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_94}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_lo_95}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_116_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_95; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_44 = decoded_addr_decoded_decoded_andMatrixOutputs_116_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_94}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_90, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_90}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_95}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_95}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_95}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_96}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_96}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_95}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_lo_96}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_60_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_96; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_39 = decoded_addr_decoded_decoded_andMatrixOutputs_60_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_95}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_91, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_91}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_96}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_96}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_96}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_97}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_97}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_97}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_97}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_96}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_lo_97}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_175_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_97; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_34 = decoded_addr_decoded_decoded_andMatrixOutputs_175_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_96}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_97}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_97}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_97}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_98}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_98}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_98}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_97}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_lo_98}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_194_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_98; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_28 = decoded_addr_decoded_decoded_andMatrixOutputs_194_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_97}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_92, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_92}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_98}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_98}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_99}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_99}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_99}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_98}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_lo_99}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_188_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_99; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_27 = decoded_addr_decoded_decoded_andMatrixOutputs_188_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_98}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_93, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_93}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_99}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_99}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_100}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_100}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_100}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_100}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_99}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_lo_100}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_130_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_100; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_172 = decoded_addr_decoded_decoded_andMatrixOutputs_130_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_99}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_94, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_94}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_100}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_100}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_101}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_101}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_101}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_101}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_100}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_lo_101}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_164_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_101; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_167 = decoded_addr_decoded_decoded_andMatrixOutputs_164_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_100}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_95, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_95}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_101}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_101}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_102}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_102}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_101}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_lo_102}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_122_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_102; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_162 = decoded_addr_decoded_decoded_andMatrixOutputs_122_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_101}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_96, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_96}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_102}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_102}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_103}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_103}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_102}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_lo_103}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_169_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_103; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_157 = decoded_addr_decoded_decoded_andMatrixOutputs_169_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_102}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_97, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_97}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_103}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_103}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_104}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_104}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_104}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_103}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_lo_104}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_77_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_104; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_152 = decoded_addr_decoded_decoded_andMatrixOutputs_77_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_103}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_98, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_98}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_104}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_104}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_105}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_105}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_105}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_104}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_lo_105}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_144_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_105; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_147 = decoded_addr_decoded_decoded_andMatrixOutputs_144_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_104}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_99, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_99}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_105}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_105}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_106}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_106}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_105}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_lo_106}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_41_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_106; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_142 = decoded_addr_decoded_decoded_andMatrixOutputs_41_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_105}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_100, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_100}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_106}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_106}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_107}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_107}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_106}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_lo_107}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_15_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_107; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_137 = decoded_addr_decoded_decoded_andMatrixOutputs_15_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_106}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_101, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_101}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_107}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_107}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_108}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_108}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_108}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_107}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_lo_108}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_49_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_108; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_132 = decoded_addr_decoded_decoded_andMatrixOutputs_49_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_107}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_102, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_102}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_108}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_108}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_109}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_109}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_109}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_108}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_lo_109}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_4_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_109; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_127 = decoded_addr_decoded_decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_108}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_103, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_103}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_109}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_109}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_110}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_109}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_lo_110}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_47_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_110; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_122 = decoded_addr_decoded_decoded_andMatrixOutputs_47_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_109}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_104, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_104}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_110}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_110}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_111}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_110}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_lo_111}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_94_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_111; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_117 = decoded_addr_decoded_decoded_andMatrixOutputs_94_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_110}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_105, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_105}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_111}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_111}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_112}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_112}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_112}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_111}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_lo_112}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_71_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_112; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_112 = decoded_addr_decoded_decoded_andMatrixOutputs_71_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_111}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_106, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_106}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_112}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_112}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_113}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_113}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_113}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_112}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_lo_113}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_48_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_113; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_107 = decoded_addr_decoded_decoded_andMatrixOutputs_48_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_112}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_107, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_107}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_113}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_113}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_114}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_114}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_113}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_lo_114}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_136_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_114; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_102 = decoded_addr_decoded_decoded_andMatrixOutputs_136_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_113}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_108, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_108}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_114}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_114}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_115}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_115}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_114}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_lo_115}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_72_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_115; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_97 = decoded_addr_decoded_decoded_andMatrixOutputs_72_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_114}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_109, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_109}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_115}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_115}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_116}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_116}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_116}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_115}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_lo_116}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_149_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_116; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_92 = decoded_addr_decoded_decoded_andMatrixOutputs_149_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_115}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_110, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_110}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_116}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_116}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_117}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_117}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_117}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_116}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_lo_117}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_31_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_117; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_87 = decoded_addr_decoded_decoded_andMatrixOutputs_31_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_116}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_111, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_111}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_117}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_117}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_118}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_118}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_117}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_lo_118}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_187_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_118; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_82 = decoded_addr_decoded_decoded_andMatrixOutputs_187_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_117}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_112, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_112}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_118}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_118}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_119}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_119}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_118}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_lo_119}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_145_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_119; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_77 = decoded_addr_decoded_decoded_andMatrixOutputs_145_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_118}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_113, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_113}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_119}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_119}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_120}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_120}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_120}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_119}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_lo_120}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_165_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_120; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_72 = decoded_addr_decoded_decoded_andMatrixOutputs_165_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_119}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_114, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_114}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_120}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_120}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_121}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_121}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_121}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_121}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_120}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_lo_121}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_151_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_121; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_67 = decoded_addr_decoded_decoded_andMatrixOutputs_151_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_120}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_115, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_115}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_121}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_121}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_122}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_122}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_122}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_121}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_lo_122}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_91_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_122; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_62 = decoded_addr_decoded_decoded_andMatrixOutputs_91_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_121}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_116, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_116}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_122}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_122}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_123}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_123}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_123}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_122}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_lo_123}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_162_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_123; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_57 = decoded_addr_decoded_decoded_andMatrixOutputs_162_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_122}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_117, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_117}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_123}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_123}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_124}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_124}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_124}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_124}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_123}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_lo_124}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_42_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_124; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_52 = decoded_addr_decoded_decoded_andMatrixOutputs_42_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_123}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_118, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_118}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_124}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_124}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_125}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_125}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_125}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_125}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_124}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_lo_125}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_0_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_125; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_47 = decoded_addr_decoded_decoded_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_124}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_119, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_119}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_125}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_125}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_126}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_126}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_126}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_125}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_lo_126}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_93_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_126; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_42 = decoded_addr_decoded_decoded_andMatrixOutputs_93_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_125}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_120, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_120}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_126}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_126}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_127}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_127}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_127}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_126}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_lo_127}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_67_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_127; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_37 = decoded_addr_decoded_decoded_andMatrixOutputs_67_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_126}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_121, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_121}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_127}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_127}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_127}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_128}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_128}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_128}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_128}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_127}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_lo_128}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_161_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_128; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_32 = decoded_addr_decoded_decoded_andMatrixOutputs_161_2; // @[pla.scala:98:70, :114:36] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_148 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_149 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_150 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_151 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_152 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_153 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_154 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_155 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_156 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_157 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_158 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_159 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_160 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_161 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_162 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_163 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_164 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_165 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_166 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_167 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_168 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_169 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_170 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_171 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_172 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_173 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_174 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_175 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_176 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_177 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_178 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_179 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_180 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_181 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_182 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_183 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_184 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_185 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_186 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_187 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_188 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_189 = decoded_addr_decoded_decoded_invInputs[8]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_146 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_147 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_148 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_149 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_150 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_151 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_152 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_153 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_154 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_155 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_156 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_157 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_158 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_159 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_160 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_161 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_162 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_163 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_164 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_165 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_166 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_167 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_168 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_169 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_170 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_171 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_172 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_173 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_174 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_175 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_176 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_177 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_178 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_179 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_180 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_181 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_182 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_183 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_184 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_185 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_186 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_187 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_188 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_189 = decoded_addr_decoded_decoded_invInputs[9]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_127}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_128}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_128}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_128}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_129}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_128}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_lo_129}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_56_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_129; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_30 = decoded_addr_decoded_decoded_andMatrixOutputs_56_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_128}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_122, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_122}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_129}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_129}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_129}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_130}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_129}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_lo_130}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_59_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_130; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_29 = decoded_addr_decoded_decoded_andMatrixOutputs_59_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_129}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_123, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_123}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_130}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_130}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_130}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_131}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_131}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_130}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_lo_131}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_23_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_131; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_173 = decoded_addr_decoded_decoded_andMatrixOutputs_23_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_130}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_124, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_124}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_131}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_131}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_131}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_132}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_132}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_131}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_lo_132}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_133_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_132; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_168 = decoded_addr_decoded_decoded_andMatrixOutputs_133_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_131}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_125, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_125}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_132}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_132}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_132}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_133}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_133}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_132}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_lo_133}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_5_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_133; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_163 = decoded_addr_decoded_decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_132}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_126, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_126}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_133}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_133}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_133}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_134}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_134}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_134}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_133}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_lo_134}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_24_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_134; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_158 = decoded_addr_decoded_decoded_andMatrixOutputs_24_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_133}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_127, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_127}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_134}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_134}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_134}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_135}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_135}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_135}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_135}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_134}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_lo_135}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_32_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_135; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_153 = decoded_addr_decoded_decoded_andMatrixOutputs_32_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_134}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_128, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_128}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_135}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_135}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_135}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_136}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_136}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_136}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_135}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_lo_136}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_166_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_136; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_148 = decoded_addr_decoded_decoded_andMatrixOutputs_166_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_135}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_129, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_129}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_136}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_136}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_136}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_137}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_136}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_lo_137}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_39_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_137; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_143 = decoded_addr_decoded_decoded_andMatrixOutputs_39_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_136}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_130, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_130}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_137}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_137}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_137}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_138}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_137}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_lo_138}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_90_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_138; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_138 = decoded_addr_decoded_decoded_andMatrixOutputs_90_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_137}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_131, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_131}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_138}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_138}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_138}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_139}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_139}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_138}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_lo_139}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_62_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_139; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_133 = decoded_addr_decoded_decoded_andMatrixOutputs_62_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_132 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_138}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_132, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_132}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_139}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_139}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_139}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_140}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_140}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_139}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_lo_140}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_178_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_140; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_128 = decoded_addr_decoded_decoded_andMatrixOutputs_178_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_133 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_139}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_133, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_133}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_140}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_140}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_140}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_141}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_141}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_140}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_lo_141}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_43_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_141; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_123 = decoded_addr_decoded_decoded_andMatrixOutputs_43_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_134 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_140}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_134, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_134}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_141}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_141}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_141}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_142}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_142}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_141}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_lo_142}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_20_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_142; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_118 = decoded_addr_decoded_decoded_andMatrixOutputs_20_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_135 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_141}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_135, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_135}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_142}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_142}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_142}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_143}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_143}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_143}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_142}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_lo_143}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_81_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_143; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_113 = decoded_addr_decoded_decoded_andMatrixOutputs_81_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_136 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_142}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_136, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_136}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_143}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_143}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_143}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_144}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_144}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_144}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_143}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_lo_144}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_22_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_144; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_108 = decoded_addr_decoded_decoded_andMatrixOutputs_22_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_137 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_143}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_137, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_137}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_144}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_144}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_144}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_145}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_145}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_144}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_lo_145}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_139_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_145; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_103 = decoded_addr_decoded_decoded_andMatrixOutputs_139_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_138 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_144}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_138, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_138}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_145}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_145}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_145}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_146}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_146}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_145}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_lo_146}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_131_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_146; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_98 = decoded_addr_decoded_decoded_andMatrixOutputs_131_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_139 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_145}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_139, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_139}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_146}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_146}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_146}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_147}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_147}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_147}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_146}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_lo_147}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_193_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_147; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_93 = decoded_addr_decoded_decoded_andMatrixOutputs_193_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_140 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_146}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_140, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_140}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_147}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_147}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_147}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_148}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_148}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_148}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_147}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_lo_148}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_86_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_148; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_88 = decoded_addr_decoded_decoded_andMatrixOutputs_86_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_141 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_147}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_141, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_141}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_148}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_148}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_148}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_149}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_149}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_148}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_lo_149}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_124_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_149; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_83 = decoded_addr_decoded_decoded_andMatrixOutputs_124_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_142 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_148}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_142, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_142}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_149}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_149}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_149}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_150}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_150}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_149}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_lo_150}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_119_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_150; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_78 = decoded_addr_decoded_decoded_andMatrixOutputs_119_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_143 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_149}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_143, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_143}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_150}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_150}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_150}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_151}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_151}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_151}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_150}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_lo_151}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_163_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_151; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_73 = decoded_addr_decoded_decoded_andMatrixOutputs_163_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_144 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_150}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_144, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_144}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_151}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_151}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_151}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_152}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_152}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_152}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_152}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_151}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_lo_152}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_150_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_152; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_68 = decoded_addr_decoded_decoded_andMatrixOutputs_150_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_145 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_151}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_145, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_145}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_152}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_152}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_152}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_153}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_153}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_153}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_152}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_lo_153}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_53_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_153; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_63 = decoded_addr_decoded_decoded_andMatrixOutputs_53_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_146 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_152}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_146, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_146}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_153}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_153}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_153}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_154}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_154}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_154}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_153}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_lo_154}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_17_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_154; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_58 = decoded_addr_decoded_decoded_andMatrixOutputs_17_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_147 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_153}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_147, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_147}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_154}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_154}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_154}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_155}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_155}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_155}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_155}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_154}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_lo_155}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_58_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_155; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_53 = decoded_addr_decoded_decoded_andMatrixOutputs_58_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_148 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_154}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_148, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_148}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_155}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_155}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_155}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_156}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_156}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_156}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_156}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_155}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_lo_156}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_50_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_156; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_48 = decoded_addr_decoded_decoded_andMatrixOutputs_50_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_149 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_155}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_149, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_149}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_156}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_157 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_156}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_157 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_156}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_157}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_157}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_157 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_157}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_157 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_156}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_157 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_lo_157}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_87_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_157; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_43 = decoded_addr_decoded_decoded_andMatrixOutputs_87_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_150 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_156}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_157 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_150, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_150}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_157 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_157}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_158 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_157}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_158 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_157}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_158}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_157 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_158}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_157 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_158}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_158 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_158}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_158 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_157}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_158 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_lo_158}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_98_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_158; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_38 = decoded_addr_decoded_decoded_andMatrixOutputs_98_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_151 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_157}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_158 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_151, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_151}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_158 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_158}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_159 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_158}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_159 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_158}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_157 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_159}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_158 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_159}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_158 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_159}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_159 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_159}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_159 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_158}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_159 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_lo_159}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_137_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_159; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_33 = decoded_addr_decoded_decoded_andMatrixOutputs_137_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_159 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_158}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_159 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_160 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_159}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_160 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_159}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_158 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_160}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_159 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_160}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_159 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_160}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_160 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_160}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_160 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_159}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_160 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_lo_160}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_153_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_160; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_26 = decoded_addr_decoded_decoded_andMatrixOutputs_153_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_152 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_159}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_160 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_152, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_152}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_160 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_161 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_160}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_161 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_160}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_159 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_161}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_160 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_161}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_160 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_161 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_161}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_161 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_160}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_161 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_lo_161}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_160_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_161; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_25 = decoded_addr_decoded_decoded_andMatrixOutputs_160_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_153 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_160}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_161 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_153, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_153}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_161 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_162 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_161}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_162 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_161}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_160 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_162}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_161 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_162}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_161 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_162}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_162 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_162}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_162 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_161}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_162 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_lo_162}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_68_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_162; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_171 = decoded_addr_decoded_decoded_andMatrixOutputs_68_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_154 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_161}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_162 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_154, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_154}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_162 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_163 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_162}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_163 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_162}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_161 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_163}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_162 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_163}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_162 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_163}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_163 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_163}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_163 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_162}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_163 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_lo_163}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_152_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_163; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_166 = decoded_addr_decoded_decoded_andMatrixOutputs_152_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_155 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_162}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_163 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_155, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_155}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_163 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_164 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_163}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_164 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_163}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_162 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_164}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_163 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_164}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_163 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_164 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_164}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_164 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_163}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_164 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_lo_164}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_9_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_164; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_161 = decoded_addr_decoded_decoded_andMatrixOutputs_9_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_156 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_163}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_164 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_156, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_156}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_164 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_165 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_164}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_165 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_164}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_163 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_165}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_164 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_165}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_164 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_165 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_165}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_165 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_164}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_165 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_lo_165}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_121_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_165; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_156 = decoded_addr_decoded_decoded_andMatrixOutputs_121_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_157 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_164}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_165 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_157, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_157}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_165 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_166 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_165}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_166 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_165}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_164 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_166}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_165 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_166}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_165 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_166}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_166 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_166}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_166 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_165}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_166 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_lo_166}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_125_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_166; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_151 = decoded_addr_decoded_decoded_andMatrixOutputs_125_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_158 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_165}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_166 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_158, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_158}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_166 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_167 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_166}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_167 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_166}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_165 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_166 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_167}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_166 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_167}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_167 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_167}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_167 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_166}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_167 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_lo_167}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_190_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_167; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_146 = decoded_addr_decoded_decoded_andMatrixOutputs_190_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_159 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_166}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_167 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_159, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_159}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_167 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_168 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_167}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_168 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_167}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_166 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_167 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_168}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_167 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_168 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_168}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_168 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_167}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_168 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_lo_168}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_146_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_168; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_141 = decoded_addr_decoded_decoded_andMatrixOutputs_146_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_160 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_167}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_168 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_160, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_160}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_168 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_169 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_168}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_169 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_168}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_167 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_168 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_169}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_168 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_169 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_169}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_169 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_168}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_169 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_lo_169}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_114_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_169; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_136 = decoded_addr_decoded_decoded_andMatrixOutputs_114_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_161 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_168}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_169 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_161, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_161}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_169 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_170 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_169}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_170 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_169}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_168 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_169 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_170}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_169 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_170}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_170 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_170}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_170 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_169}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_170 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_lo_170}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_61_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_170; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_131 = decoded_addr_decoded_decoded_andMatrixOutputs_61_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_162 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_169}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_170 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_162, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_162}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_170 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_171 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_170}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_171 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_170}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_169 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_170 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_171}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_170 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_171}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_171 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_171}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_171 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_170}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_171 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_lo_171}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_36_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_171; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_126 = decoded_addr_decoded_decoded_andMatrixOutputs_36_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_163 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_170}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_171 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_163, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_163}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_171 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_172 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_171}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_172 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_171}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_170 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_171 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_172}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_171 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_172 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_172}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_172 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_171}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_172 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_lo_172}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_74_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_172; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_121 = decoded_addr_decoded_decoded_andMatrixOutputs_74_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_164 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_171}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_172 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_164, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_164}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_172 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_173 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_172}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_173 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_172}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_171 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_172 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_173}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_172 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_173 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_173}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_173 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_172}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_173 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_lo_173}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_6_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_173; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_116 = decoded_addr_decoded_decoded_andMatrixOutputs_6_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_165 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_172}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_173 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_165, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_165}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_173 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_174 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_173}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_174 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_173}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_172 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_173 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_174}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_173 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_174}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_174 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_174}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_174 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_173}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_174 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_lo_174}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_63_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_174; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_111 = decoded_addr_decoded_decoded_andMatrixOutputs_63_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_166 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_173}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_174 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_166, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_166}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_174 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_175 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_174}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_175 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_174}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_173 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_174 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_175}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_174 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_175}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_175 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_175}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_175 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_174}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_175 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_lo_175}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_174_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_175; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_106 = decoded_addr_decoded_decoded_andMatrixOutputs_174_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_167 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_174}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_175 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_167, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_167}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_175 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_176 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_175}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_176 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_175}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_174 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_175 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_176}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_175 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_176 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_176}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_176 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_175}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_176 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_lo_176}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_38_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_176; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_101 = decoded_addr_decoded_decoded_andMatrixOutputs_38_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_168 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_175}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_176 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_168, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_168}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_176 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_177 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_176}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_177 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_176}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_175 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_176 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_177}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_176 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_177 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_177}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_177 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_176}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_177 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_lo_177}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_143_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_177; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_96 = decoded_addr_decoded_decoded_andMatrixOutputs_143_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_169 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_176}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_177 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_169, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_169}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_177 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_178 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_177}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_178 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_177}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_176 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_178}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_177 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_178}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_177 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_178}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_178 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_178}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_178 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_177}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_178 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_lo_178}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_97_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_178; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_91 = decoded_addr_decoded_decoded_andMatrixOutputs_97_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_170 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_177}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_178 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_170, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_170}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_178 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_178}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_179 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_178}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_179 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_178}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_177 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_178 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_179}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_178 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_179}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_179 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_179}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_179 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_178}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_179 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_lo_179}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_30_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_179; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_86 = decoded_addr_decoded_decoded_andMatrixOutputs_30_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_171 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_178}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_179 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_171, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_171}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_179 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_180 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_179}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_180 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_179}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_178 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_179 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_180}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_179 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_180 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_180}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_180 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_179}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_180 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_lo_180}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_70_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_180; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_81 = decoded_addr_decoded_decoded_andMatrixOutputs_70_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_172 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_179}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_180 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_172, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_172}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_180 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_181 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_180}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_181 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_180}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_179 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_180 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_181}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_180 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_181 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_181}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_181 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_180}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_181 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_lo_181}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_103_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_181; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_76 = decoded_addr_decoded_decoded_andMatrixOutputs_103_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_173 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_180}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_181 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_173, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_173}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_181 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_182 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_181}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_182 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_181}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_180 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_181 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_182}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_181 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_182}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_182 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_182}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_182 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_181}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_182 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_lo_182}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_134_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_182; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_71 = decoded_addr_decoded_decoded_andMatrixOutputs_134_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_174 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_181}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_182 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_174, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_174}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_182 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_183 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_182}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_183 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_182}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_181 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_183}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_182 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_183}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_182 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_183}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_183 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_183}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_183 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_182}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_183 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_lo_183}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_84_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_183; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_66 = decoded_addr_decoded_decoded_andMatrixOutputs_84_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_175 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_182}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_183 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_175, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_175}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_183 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_184 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_183}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_184 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_183}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_182 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_184}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_183 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_184}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_183 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_184 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_184}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_184 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_183}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_184 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_lo_184}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_101_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_184; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_61 = decoded_addr_decoded_decoded_andMatrixOutputs_101_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_176 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_183}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_184 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_176, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_176}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_184 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_185 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_184}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_185 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_184}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_183 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_185}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_184 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_185}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_184 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_185 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_185}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_185 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_184}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_185 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_lo_185}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_142_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_185; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_56 = decoded_addr_decoded_decoded_andMatrixOutputs_142_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_177 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_184}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_185 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_177, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_177}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_185 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_186 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_185}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_186 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_185}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_184 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_186}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_185 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_186}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_185 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_186}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_186 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_186}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_186 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_185}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_186 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_lo_186}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_135_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_186; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_51 = decoded_addr_decoded_decoded_andMatrixOutputs_135_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_178 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_185}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_186 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_178, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_178}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_186 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_187 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_186}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_187 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_186}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_185 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_187}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_186 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_187}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_186 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_187}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_187 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_187}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_187 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_186}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_187 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_lo_187}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_155_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_187; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_46 = decoded_addr_decoded_decoded_andMatrixOutputs_155_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_179 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_186}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_187 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_179, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_179}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_187 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_188 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_187}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_188 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_187}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_186 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_188}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_187 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_186, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_188}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_187 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_188 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_188}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_188 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_187}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_188 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_lo_188}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_167_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_188; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_41 = decoded_addr_decoded_decoded_andMatrixOutputs_167_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_180 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_187}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_188 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_180, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_180}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_188 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_189 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_188}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_189 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_188}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_187 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_189}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_188 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_187, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_189}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_188 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_189 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_189}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_189 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_188}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_189 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_lo_189}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_159_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_189; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_36 = decoded_addr_decoded_decoded_andMatrixOutputs_159_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_181 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_188}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_189 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_181, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_181}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_189 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_189}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_190 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_189}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_190 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_189}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_188 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_190}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_189 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_188, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_190}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_189 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_190}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_190 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_190}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_190 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_189}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_190 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_lo_190}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_66_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_190; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_31 = decoded_addr_decoded_decoded_andMatrixOutputs_66_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_190 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_189}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_190 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_190}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_191 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_190}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_191 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_190}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_189 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_191}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_190 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_189, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_191}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_190 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_191}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_191 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_191}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_191 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_190}; // @[pla.scala:98:53] wire [10:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_191 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_lo_191}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_126_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_191; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_2 = decoded_addr_decoded_decoded_andMatrixOutputs_126_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_182 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_190}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_191 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_182, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_182}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_191 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_191}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_192 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_191}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_192 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_191}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_190 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_192}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_191 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_190, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_192}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_191 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_192}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_192 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_192}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_192 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_191}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_192 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_lo_192}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_44_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_192; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_3 = decoded_addr_decoded_decoded_andMatrixOutputs_44_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_183 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_191}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_192 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_183, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_183}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_192 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_192}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_193 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_192}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_193 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_192}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_191 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_193}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_192 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_191, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_193}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_192 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_193}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_193 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_193}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_193 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_192}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_193 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_lo_193}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_14_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_193; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_1 = decoded_addr_decoded_decoded_andMatrixOutputs_14_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_184 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_192}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_193 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_184, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_184}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_193 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_193}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_194 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_193}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_194 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_194, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_193}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_192 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_194}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_193 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_192, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_194}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_193 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_194}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_194 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_194}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_194 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_194, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_193}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_194 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_194, decoded_addr_decoded_decoded_andMatrixOutputs_lo_194}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_104_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_194; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T_182 = decoded_addr_decoded_decoded_andMatrixOutputs_104_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_185 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_9_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_10_193}; // @[pla.scala:90:45, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_194 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_hi_185, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_11_185}; // @[pla.scala:90:45, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_194 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_6_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_7_194}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_195 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_hi_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_8_194}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_lo_195 = {decoded_addr_decoded_decoded_andMatrixOutputs_lo_hi_195, decoded_addr_decoded_decoded_andMatrixOutputs_lo_lo_194}; // @[pla.scala:98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_193 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_3_195, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_4_195}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_194 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_hi_193, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_5_195}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_194 = {decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_0_195, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_1_195}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_195 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_hi_194, decoded_addr_decoded_decoded_andMatrixOutputs_andMatrixInput_2_195}; // @[pla.scala:90:45, :98:53] wire [5:0] decoded_addr_decoded_decoded_andMatrixOutputs_hi_195 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_hi_195, decoded_addr_decoded_decoded_andMatrixOutputs_hi_lo_194}; // @[pla.scala:98:53] wire [11:0] _decoded_addr_decoded_decoded_andMatrixOutputs_T_195 = {decoded_addr_decoded_decoded_andMatrixOutputs_hi_195, decoded_addr_decoded_decoded_andMatrixOutputs_lo_195}; // @[pla.scala:98:53] wire decoded_addr_decoded_decoded_andMatrixOutputs_92_2 = &_decoded_addr_decoded_decoded_andMatrixOutputs_T_195; // @[pla.scala:98:{53,70}] wire _decoded_addr_decoded_decoded_orMatrixOutputs_T = decoded_addr_decoded_decoded_andMatrixOutputs_92_2; // @[pla.scala:98:70, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_2, _decoded_addr_decoded_decoded_orMatrixOutputs_T_1}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_5, _decoded_addr_decoded_decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_3}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_8, _decoded_addr_decoded_decoded_orMatrixOutputs_T_7}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_11, _decoded_addr_decoded_decoded_orMatrixOutputs_T_10}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_14, _decoded_addr_decoded_decoded_orMatrixOutputs_T_13}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_12}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_17, _decoded_addr_decoded_decoded_orMatrixOutputs_T_16}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_15}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_20, _decoded_addr_decoded_decoded_orMatrixOutputs_T_19}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_18}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_23, _decoded_addr_decoded_decoded_orMatrixOutputs_T_22}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_21}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [23:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_26, _decoded_addr_decoded_decoded_orMatrixOutputs_T_25}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_24}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_29, _decoded_addr_decoded_decoded_orMatrixOutputs_T_28}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_27}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_32, _decoded_addr_decoded_decoded_orMatrixOutputs_T_31}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_30}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_35, _decoded_addr_decoded_decoded_orMatrixOutputs_T_34}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_33}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_38, _decoded_addr_decoded_decoded_orMatrixOutputs_T_37}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_36}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_41, _decoded_addr_decoded_decoded_orMatrixOutputs_T_40}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_39}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_44, _decoded_addr_decoded_decoded_orMatrixOutputs_T_43}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_42}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_46, _decoded_addr_decoded_decoded_orMatrixOutputs_T_45}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_48, _decoded_addr_decoded_decoded_orMatrixOutputs_T_47}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [12:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [24:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [48:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_51, _decoded_addr_decoded_decoded_orMatrixOutputs_T_50}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_49}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_54, _decoded_addr_decoded_decoded_orMatrixOutputs_T_53}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_52}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_57, _decoded_addr_decoded_decoded_orMatrixOutputs_T_56}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_55}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_60, _decoded_addr_decoded_decoded_orMatrixOutputs_T_59}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_58}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_63, _decoded_addr_decoded_decoded_orMatrixOutputs_T_62}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_61}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_66, _decoded_addr_decoded_decoded_orMatrixOutputs_T_65}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_64}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_69, _decoded_addr_decoded_decoded_orMatrixOutputs_T_68}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_67}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_72, _decoded_addr_decoded_decoded_orMatrixOutputs_T_71}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_70}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [23:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_75, _decoded_addr_decoded_decoded_orMatrixOutputs_T_74}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_73}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_78, _decoded_addr_decoded_decoded_orMatrixOutputs_T_77}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_76}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_81, _decoded_addr_decoded_decoded_orMatrixOutputs_T_80}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_79}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_84, _decoded_addr_decoded_decoded_orMatrixOutputs_T_83}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_82}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_87, _decoded_addr_decoded_decoded_orMatrixOutputs_T_86}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_85}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_90, _decoded_addr_decoded_decoded_orMatrixOutputs_T_89}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_88}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_93, _decoded_addr_decoded_decoded_orMatrixOutputs_T_92}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_91}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_95, _decoded_addr_decoded_decoded_orMatrixOutputs_T_94}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_97, _decoded_addr_decoded_decoded_orMatrixOutputs_T_96}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [12:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [24:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [48:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi_lo}; // @[pla.scala:102:36] wire [97:0] decoded_addr_decoded_decoded_orMatrixOutputs_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_100, _decoded_addr_decoded_decoded_orMatrixOutputs_T_99}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_98}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_103, _decoded_addr_decoded_decoded_orMatrixOutputs_T_102}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_101}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_106, _decoded_addr_decoded_decoded_orMatrixOutputs_T_105}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_104}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_109, _decoded_addr_decoded_decoded_orMatrixOutputs_T_108}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_107}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_112, _decoded_addr_decoded_decoded_orMatrixOutputs_T_111}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_110}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_115, _decoded_addr_decoded_decoded_orMatrixOutputs_T_114}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_113}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_118, _decoded_addr_decoded_decoded_orMatrixOutputs_T_117}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_116}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_121, _decoded_addr_decoded_decoded_orMatrixOutputs_T_120}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_119}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [23:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_124, _decoded_addr_decoded_decoded_orMatrixOutputs_T_123}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_122}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_127, _decoded_addr_decoded_decoded_orMatrixOutputs_T_126}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_125}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_130, _decoded_addr_decoded_decoded_orMatrixOutputs_T_129}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_128}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_133, _decoded_addr_decoded_decoded_orMatrixOutputs_T_132}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_131}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_136, _decoded_addr_decoded_decoded_orMatrixOutputs_T_135}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_134}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_139, _decoded_addr_decoded_decoded_orMatrixOutputs_T_138}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_137}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_142, _decoded_addr_decoded_decoded_orMatrixOutputs_T_141}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_140}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_144, _decoded_addr_decoded_decoded_orMatrixOutputs_T_143}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_146, _decoded_addr_decoded_decoded_orMatrixOutputs_T_145}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [12:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [24:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [48:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_149, _decoded_addr_decoded_decoded_orMatrixOutputs_T_148}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_147}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_152, _decoded_addr_decoded_decoded_orMatrixOutputs_T_151}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_150}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_155, _decoded_addr_decoded_decoded_orMatrixOutputs_T_154}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_153}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_158, _decoded_addr_decoded_decoded_orMatrixOutputs_T_157}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_156}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_161, _decoded_addr_decoded_decoded_orMatrixOutputs_T_160}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_159}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_164, _decoded_addr_decoded_decoded_orMatrixOutputs_T_163}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_162}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_167, _decoded_addr_decoded_decoded_orMatrixOutputs_T_166}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_165}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_170, _decoded_addr_decoded_decoded_orMatrixOutputs_T_169}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_168}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [23:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_173, _decoded_addr_decoded_decoded_orMatrixOutputs_T_172}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_171}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_176, _decoded_addr_decoded_decoded_orMatrixOutputs_T_175}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_174}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_179, _decoded_addr_decoded_decoded_orMatrixOutputs_T_178}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_177}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_182, _decoded_addr_decoded_decoded_orMatrixOutputs_T_181}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_180}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:102:36] wire [11:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_185, _decoded_addr_decoded_decoded_orMatrixOutputs_T_184}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_183}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_188, _decoded_addr_decoded_decoded_orMatrixOutputs_T_187}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_186}; // @[pla.scala:102:36, :114:36] wire [5:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:102:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_191, _decoded_addr_decoded_decoded_orMatrixOutputs_T_190}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_orMatrixOutputs_T_189}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_193, _decoded_addr_decoded_decoded_orMatrixOutputs_T_192}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_orMatrixOutputs_T_195, _decoded_addr_decoded_decoded_orMatrixOutputs_T_194}; // @[pla.scala:102:36, :114:36] wire [3:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [6:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [12:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [24:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:102:36] wire [48:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi_lo}; // @[pla.scala:102:36] wire [97:0] decoded_addr_decoded_decoded_orMatrixOutputs_hi = {decoded_addr_decoded_decoded_orMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [195:0] decoded_addr_decoded_decoded_orMatrixOutputs = {decoded_addr_decoded_decoded_orMatrixOutputs_hi, decoded_addr_decoded_decoded_orMatrixOutputs_lo}; // @[pla.scala:102:36] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T = decoded_addr_decoded_decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_1 = decoded_addr_decoded_decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_2 = decoded_addr_decoded_decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_3 = decoded_addr_decoded_decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_4 = decoded_addr_decoded_decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_5 = decoded_addr_decoded_decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_6 = decoded_addr_decoded_decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_7 = decoded_addr_decoded_decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_8 = decoded_addr_decoded_decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_9 = decoded_addr_decoded_decoded_orMatrixOutputs[9]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_10 = decoded_addr_decoded_decoded_orMatrixOutputs[10]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_11 = decoded_addr_decoded_decoded_orMatrixOutputs[11]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_12 = decoded_addr_decoded_decoded_orMatrixOutputs[12]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_13 = decoded_addr_decoded_decoded_orMatrixOutputs[13]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_14 = decoded_addr_decoded_decoded_orMatrixOutputs[14]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_15 = decoded_addr_decoded_decoded_orMatrixOutputs[15]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_16 = decoded_addr_decoded_decoded_orMatrixOutputs[16]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_17 = decoded_addr_decoded_decoded_orMatrixOutputs[17]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_18 = decoded_addr_decoded_decoded_orMatrixOutputs[18]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_19 = decoded_addr_decoded_decoded_orMatrixOutputs[19]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_20 = decoded_addr_decoded_decoded_orMatrixOutputs[20]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_21 = decoded_addr_decoded_decoded_orMatrixOutputs[21]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_22 = decoded_addr_decoded_decoded_orMatrixOutputs[22]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_23 = decoded_addr_decoded_decoded_orMatrixOutputs[23]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_24 = decoded_addr_decoded_decoded_orMatrixOutputs[24]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_25 = decoded_addr_decoded_decoded_orMatrixOutputs[25]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_26 = decoded_addr_decoded_decoded_orMatrixOutputs[26]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_27 = decoded_addr_decoded_decoded_orMatrixOutputs[27]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_28 = decoded_addr_decoded_decoded_orMatrixOutputs[28]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_29 = decoded_addr_decoded_decoded_orMatrixOutputs[29]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_30 = decoded_addr_decoded_decoded_orMatrixOutputs[30]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_31 = decoded_addr_decoded_decoded_orMatrixOutputs[31]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_32 = decoded_addr_decoded_decoded_orMatrixOutputs[32]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_33 = decoded_addr_decoded_decoded_orMatrixOutputs[33]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_34 = decoded_addr_decoded_decoded_orMatrixOutputs[34]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_35 = decoded_addr_decoded_decoded_orMatrixOutputs[35]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_36 = decoded_addr_decoded_decoded_orMatrixOutputs[36]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_37 = decoded_addr_decoded_decoded_orMatrixOutputs[37]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_38 = decoded_addr_decoded_decoded_orMatrixOutputs[38]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_39 = decoded_addr_decoded_decoded_orMatrixOutputs[39]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_40 = decoded_addr_decoded_decoded_orMatrixOutputs[40]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_41 = decoded_addr_decoded_decoded_orMatrixOutputs[41]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_42 = decoded_addr_decoded_decoded_orMatrixOutputs[42]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_43 = decoded_addr_decoded_decoded_orMatrixOutputs[43]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_44 = decoded_addr_decoded_decoded_orMatrixOutputs[44]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_45 = decoded_addr_decoded_decoded_orMatrixOutputs[45]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_46 = decoded_addr_decoded_decoded_orMatrixOutputs[46]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_47 = decoded_addr_decoded_decoded_orMatrixOutputs[47]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_48 = decoded_addr_decoded_decoded_orMatrixOutputs[48]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_49 = decoded_addr_decoded_decoded_orMatrixOutputs[49]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_50 = decoded_addr_decoded_decoded_orMatrixOutputs[50]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_51 = decoded_addr_decoded_decoded_orMatrixOutputs[51]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_52 = decoded_addr_decoded_decoded_orMatrixOutputs[52]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_53 = decoded_addr_decoded_decoded_orMatrixOutputs[53]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_54 = decoded_addr_decoded_decoded_orMatrixOutputs[54]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_55 = decoded_addr_decoded_decoded_orMatrixOutputs[55]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_56 = decoded_addr_decoded_decoded_orMatrixOutputs[56]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_57 = decoded_addr_decoded_decoded_orMatrixOutputs[57]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_58 = decoded_addr_decoded_decoded_orMatrixOutputs[58]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_59 = decoded_addr_decoded_decoded_orMatrixOutputs[59]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_60 = decoded_addr_decoded_decoded_orMatrixOutputs[60]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_61 = decoded_addr_decoded_decoded_orMatrixOutputs[61]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_62 = decoded_addr_decoded_decoded_orMatrixOutputs[62]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_63 = decoded_addr_decoded_decoded_orMatrixOutputs[63]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_64 = decoded_addr_decoded_decoded_orMatrixOutputs[64]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_65 = decoded_addr_decoded_decoded_orMatrixOutputs[65]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_66 = decoded_addr_decoded_decoded_orMatrixOutputs[66]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_67 = decoded_addr_decoded_decoded_orMatrixOutputs[67]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_68 = decoded_addr_decoded_decoded_orMatrixOutputs[68]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_69 = decoded_addr_decoded_decoded_orMatrixOutputs[69]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_70 = decoded_addr_decoded_decoded_orMatrixOutputs[70]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_71 = decoded_addr_decoded_decoded_orMatrixOutputs[71]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_72 = decoded_addr_decoded_decoded_orMatrixOutputs[72]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_73 = decoded_addr_decoded_decoded_orMatrixOutputs[73]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_74 = decoded_addr_decoded_decoded_orMatrixOutputs[74]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_75 = decoded_addr_decoded_decoded_orMatrixOutputs[75]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_76 = decoded_addr_decoded_decoded_orMatrixOutputs[76]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_77 = decoded_addr_decoded_decoded_orMatrixOutputs[77]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_78 = decoded_addr_decoded_decoded_orMatrixOutputs[78]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_79 = decoded_addr_decoded_decoded_orMatrixOutputs[79]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_80 = decoded_addr_decoded_decoded_orMatrixOutputs[80]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_81 = decoded_addr_decoded_decoded_orMatrixOutputs[81]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_82 = decoded_addr_decoded_decoded_orMatrixOutputs[82]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_83 = decoded_addr_decoded_decoded_orMatrixOutputs[83]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_84 = decoded_addr_decoded_decoded_orMatrixOutputs[84]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_85 = decoded_addr_decoded_decoded_orMatrixOutputs[85]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_86 = decoded_addr_decoded_decoded_orMatrixOutputs[86]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_87 = decoded_addr_decoded_decoded_orMatrixOutputs[87]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_88 = decoded_addr_decoded_decoded_orMatrixOutputs[88]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_89 = decoded_addr_decoded_decoded_orMatrixOutputs[89]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_90 = decoded_addr_decoded_decoded_orMatrixOutputs[90]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_91 = decoded_addr_decoded_decoded_orMatrixOutputs[91]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_92 = decoded_addr_decoded_decoded_orMatrixOutputs[92]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_93 = decoded_addr_decoded_decoded_orMatrixOutputs[93]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_94 = decoded_addr_decoded_decoded_orMatrixOutputs[94]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_95 = decoded_addr_decoded_decoded_orMatrixOutputs[95]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_96 = decoded_addr_decoded_decoded_orMatrixOutputs[96]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_97 = decoded_addr_decoded_decoded_orMatrixOutputs[97]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_98 = decoded_addr_decoded_decoded_orMatrixOutputs[98]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_99 = decoded_addr_decoded_decoded_orMatrixOutputs[99]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_100 = decoded_addr_decoded_decoded_orMatrixOutputs[100]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_101 = decoded_addr_decoded_decoded_orMatrixOutputs[101]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_102 = decoded_addr_decoded_decoded_orMatrixOutputs[102]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_103 = decoded_addr_decoded_decoded_orMatrixOutputs[103]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_104 = decoded_addr_decoded_decoded_orMatrixOutputs[104]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_105 = decoded_addr_decoded_decoded_orMatrixOutputs[105]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_106 = decoded_addr_decoded_decoded_orMatrixOutputs[106]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_107 = decoded_addr_decoded_decoded_orMatrixOutputs[107]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_108 = decoded_addr_decoded_decoded_orMatrixOutputs[108]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_109 = decoded_addr_decoded_decoded_orMatrixOutputs[109]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_110 = decoded_addr_decoded_decoded_orMatrixOutputs[110]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_111 = decoded_addr_decoded_decoded_orMatrixOutputs[111]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_112 = decoded_addr_decoded_decoded_orMatrixOutputs[112]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_113 = decoded_addr_decoded_decoded_orMatrixOutputs[113]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_114 = decoded_addr_decoded_decoded_orMatrixOutputs[114]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_115 = decoded_addr_decoded_decoded_orMatrixOutputs[115]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_116 = decoded_addr_decoded_decoded_orMatrixOutputs[116]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_117 = decoded_addr_decoded_decoded_orMatrixOutputs[117]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_118 = decoded_addr_decoded_decoded_orMatrixOutputs[118]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_119 = decoded_addr_decoded_decoded_orMatrixOutputs[119]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_120 = decoded_addr_decoded_decoded_orMatrixOutputs[120]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_121 = decoded_addr_decoded_decoded_orMatrixOutputs[121]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_122 = decoded_addr_decoded_decoded_orMatrixOutputs[122]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_123 = decoded_addr_decoded_decoded_orMatrixOutputs[123]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_124 = decoded_addr_decoded_decoded_orMatrixOutputs[124]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_125 = decoded_addr_decoded_decoded_orMatrixOutputs[125]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_126 = decoded_addr_decoded_decoded_orMatrixOutputs[126]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_127 = decoded_addr_decoded_decoded_orMatrixOutputs[127]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_128 = decoded_addr_decoded_decoded_orMatrixOutputs[128]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_129 = decoded_addr_decoded_decoded_orMatrixOutputs[129]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_130 = decoded_addr_decoded_decoded_orMatrixOutputs[130]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_131 = decoded_addr_decoded_decoded_orMatrixOutputs[131]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_132 = decoded_addr_decoded_decoded_orMatrixOutputs[132]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_133 = decoded_addr_decoded_decoded_orMatrixOutputs[133]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_134 = decoded_addr_decoded_decoded_orMatrixOutputs[134]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_135 = decoded_addr_decoded_decoded_orMatrixOutputs[135]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_136 = decoded_addr_decoded_decoded_orMatrixOutputs[136]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_137 = decoded_addr_decoded_decoded_orMatrixOutputs[137]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_138 = decoded_addr_decoded_decoded_orMatrixOutputs[138]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_139 = decoded_addr_decoded_decoded_orMatrixOutputs[139]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_140 = decoded_addr_decoded_decoded_orMatrixOutputs[140]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_141 = decoded_addr_decoded_decoded_orMatrixOutputs[141]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_142 = decoded_addr_decoded_decoded_orMatrixOutputs[142]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_143 = decoded_addr_decoded_decoded_orMatrixOutputs[143]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_144 = decoded_addr_decoded_decoded_orMatrixOutputs[144]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_145 = decoded_addr_decoded_decoded_orMatrixOutputs[145]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_146 = decoded_addr_decoded_decoded_orMatrixOutputs[146]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_147 = decoded_addr_decoded_decoded_orMatrixOutputs[147]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_148 = decoded_addr_decoded_decoded_orMatrixOutputs[148]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_149 = decoded_addr_decoded_decoded_orMatrixOutputs[149]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_150 = decoded_addr_decoded_decoded_orMatrixOutputs[150]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_151 = decoded_addr_decoded_decoded_orMatrixOutputs[151]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_152 = decoded_addr_decoded_decoded_orMatrixOutputs[152]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_153 = decoded_addr_decoded_decoded_orMatrixOutputs[153]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_154 = decoded_addr_decoded_decoded_orMatrixOutputs[154]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_155 = decoded_addr_decoded_decoded_orMatrixOutputs[155]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_156 = decoded_addr_decoded_decoded_orMatrixOutputs[156]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_157 = decoded_addr_decoded_decoded_orMatrixOutputs[157]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_158 = decoded_addr_decoded_decoded_orMatrixOutputs[158]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_159 = decoded_addr_decoded_decoded_orMatrixOutputs[159]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_160 = decoded_addr_decoded_decoded_orMatrixOutputs[160]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_161 = decoded_addr_decoded_decoded_orMatrixOutputs[161]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_162 = decoded_addr_decoded_decoded_orMatrixOutputs[162]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_163 = decoded_addr_decoded_decoded_orMatrixOutputs[163]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_164 = decoded_addr_decoded_decoded_orMatrixOutputs[164]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_165 = decoded_addr_decoded_decoded_orMatrixOutputs[165]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_166 = decoded_addr_decoded_decoded_orMatrixOutputs[166]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_167 = decoded_addr_decoded_decoded_orMatrixOutputs[167]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_168 = decoded_addr_decoded_decoded_orMatrixOutputs[168]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_169 = decoded_addr_decoded_decoded_orMatrixOutputs[169]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_170 = decoded_addr_decoded_decoded_orMatrixOutputs[170]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_171 = decoded_addr_decoded_decoded_orMatrixOutputs[171]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_172 = decoded_addr_decoded_decoded_orMatrixOutputs[172]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_173 = decoded_addr_decoded_decoded_orMatrixOutputs[173]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_174 = decoded_addr_decoded_decoded_orMatrixOutputs[174]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_175 = decoded_addr_decoded_decoded_orMatrixOutputs[175]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_176 = decoded_addr_decoded_decoded_orMatrixOutputs[176]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_177 = decoded_addr_decoded_decoded_orMatrixOutputs[177]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_178 = decoded_addr_decoded_decoded_orMatrixOutputs[178]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_179 = decoded_addr_decoded_decoded_orMatrixOutputs[179]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_180 = decoded_addr_decoded_decoded_orMatrixOutputs[180]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_181 = decoded_addr_decoded_decoded_orMatrixOutputs[181]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_182 = decoded_addr_decoded_decoded_orMatrixOutputs[182]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_183 = decoded_addr_decoded_decoded_orMatrixOutputs[183]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_184 = decoded_addr_decoded_decoded_orMatrixOutputs[184]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_185 = decoded_addr_decoded_decoded_orMatrixOutputs[185]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_186 = decoded_addr_decoded_decoded_orMatrixOutputs[186]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_187 = decoded_addr_decoded_decoded_orMatrixOutputs[187]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_188 = decoded_addr_decoded_decoded_orMatrixOutputs[188]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_189 = decoded_addr_decoded_decoded_orMatrixOutputs[189]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_190 = decoded_addr_decoded_decoded_orMatrixOutputs[190]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_191 = decoded_addr_decoded_decoded_orMatrixOutputs[191]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_192 = decoded_addr_decoded_decoded_orMatrixOutputs[192]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_193 = decoded_addr_decoded_decoded_orMatrixOutputs[193]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_194 = decoded_addr_decoded_decoded_orMatrixOutputs[194]; // @[pla.scala:102:36, :124:31] wire _decoded_addr_decoded_decoded_invMatrixOutputs_T_195 = decoded_addr_decoded_decoded_orMatrixOutputs[195]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_2, _decoded_addr_decoded_decoded_invMatrixOutputs_T_1}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_5, _decoded_addr_decoded_decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_3}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_8, _decoded_addr_decoded_decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_11, _decoded_addr_decoded_decoded_invMatrixOutputs_T_10}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_14, _decoded_addr_decoded_decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_12}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_17, _decoded_addr_decoded_decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_20, _decoded_addr_decoded_decoded_invMatrixOutputs_T_19}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_18}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_23, _decoded_addr_decoded_decoded_invMatrixOutputs_T_22}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_21}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [23:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_26, _decoded_addr_decoded_decoded_invMatrixOutputs_T_25}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_24}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_29, _decoded_addr_decoded_decoded_invMatrixOutputs_T_28}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_27}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_32, _decoded_addr_decoded_decoded_invMatrixOutputs_T_31}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_30}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_35, _decoded_addr_decoded_decoded_invMatrixOutputs_T_34}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_33}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_38, _decoded_addr_decoded_decoded_invMatrixOutputs_T_37}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_36}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_41, _decoded_addr_decoded_decoded_invMatrixOutputs_T_40}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_39}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_44, _decoded_addr_decoded_decoded_invMatrixOutputs_T_43}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_42}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_46, _decoded_addr_decoded_decoded_invMatrixOutputs_T_45}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_48, _decoded_addr_decoded_decoded_invMatrixOutputs_T_47}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [12:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [24:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [48:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_51, _decoded_addr_decoded_decoded_invMatrixOutputs_T_50}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_49}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_54, _decoded_addr_decoded_decoded_invMatrixOutputs_T_53}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_52}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_57, _decoded_addr_decoded_decoded_invMatrixOutputs_T_56}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_55}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_60, _decoded_addr_decoded_decoded_invMatrixOutputs_T_59}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_58}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_63, _decoded_addr_decoded_decoded_invMatrixOutputs_T_62}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_61}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_66, _decoded_addr_decoded_decoded_invMatrixOutputs_T_65}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_64}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_69, _decoded_addr_decoded_decoded_invMatrixOutputs_T_68}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_67}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_72, _decoded_addr_decoded_decoded_invMatrixOutputs_T_71}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_70}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [23:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_75, _decoded_addr_decoded_decoded_invMatrixOutputs_T_74}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_73}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_78, _decoded_addr_decoded_decoded_invMatrixOutputs_T_77}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_76}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_81, _decoded_addr_decoded_decoded_invMatrixOutputs_T_80}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_79}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_84, _decoded_addr_decoded_decoded_invMatrixOutputs_T_83}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_82}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_87, _decoded_addr_decoded_decoded_invMatrixOutputs_T_86}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_85}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_90, _decoded_addr_decoded_decoded_invMatrixOutputs_T_89}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_88}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_93, _decoded_addr_decoded_decoded_invMatrixOutputs_T_92}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_91}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_95, _decoded_addr_decoded_decoded_invMatrixOutputs_T_94}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_97, _decoded_addr_decoded_decoded_invMatrixOutputs_T_96}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [12:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [24:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [48:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi_lo}; // @[pla.scala:120:37] wire [97:0] decoded_addr_decoded_decoded_invMatrixOutputs_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_100, _decoded_addr_decoded_decoded_invMatrixOutputs_T_99}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_98}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_103, _decoded_addr_decoded_decoded_invMatrixOutputs_T_102}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_101}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_106, _decoded_addr_decoded_decoded_invMatrixOutputs_T_105}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_104}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_109, _decoded_addr_decoded_decoded_invMatrixOutputs_T_108}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_107}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_112, _decoded_addr_decoded_decoded_invMatrixOutputs_T_111}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_110}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_115, _decoded_addr_decoded_decoded_invMatrixOutputs_T_114}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_113}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_118, _decoded_addr_decoded_decoded_invMatrixOutputs_T_117}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_116}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_121, _decoded_addr_decoded_decoded_invMatrixOutputs_T_120}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_119}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [23:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_124, _decoded_addr_decoded_decoded_invMatrixOutputs_T_123}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_122}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_127, _decoded_addr_decoded_decoded_invMatrixOutputs_T_126}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_125}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_130, _decoded_addr_decoded_decoded_invMatrixOutputs_T_129}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_128}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_133, _decoded_addr_decoded_decoded_invMatrixOutputs_T_132}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_131}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_136, _decoded_addr_decoded_decoded_invMatrixOutputs_T_135}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_134}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_139, _decoded_addr_decoded_decoded_invMatrixOutputs_T_138}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_137}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_142, _decoded_addr_decoded_decoded_invMatrixOutputs_T_141}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_140}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_144, _decoded_addr_decoded_decoded_invMatrixOutputs_T_143}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_146, _decoded_addr_decoded_decoded_invMatrixOutputs_T_145}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [12:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [24:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [48:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_149, _decoded_addr_decoded_decoded_invMatrixOutputs_T_148}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_147}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_152, _decoded_addr_decoded_decoded_invMatrixOutputs_T_151}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_150}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_155, _decoded_addr_decoded_decoded_invMatrixOutputs_T_154}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_153}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_158, _decoded_addr_decoded_decoded_invMatrixOutputs_T_157}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_156}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_161, _decoded_addr_decoded_decoded_invMatrixOutputs_T_160}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_159}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_164, _decoded_addr_decoded_decoded_invMatrixOutputs_T_163}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_162}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_167, _decoded_addr_decoded_decoded_invMatrixOutputs_T_166}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_165}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_170, _decoded_addr_decoded_decoded_invMatrixOutputs_T_169}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_168}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [23:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_173, _decoded_addr_decoded_decoded_invMatrixOutputs_T_172}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_171}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_176, _decoded_addr_decoded_decoded_invMatrixOutputs_T_175}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_174}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_179, _decoded_addr_decoded_decoded_invMatrixOutputs_T_178}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_177}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_182, _decoded_addr_decoded_decoded_invMatrixOutputs_T_181}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_180}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi_lo}; // @[pla.scala:120:37] wire [11:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_185, _decoded_addr_decoded_decoded_invMatrixOutputs_T_184}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_183}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_188, _decoded_addr_decoded_decoded_invMatrixOutputs_T_187}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_186}; // @[pla.scala:120:37, :124:31] wire [5:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_191, _decoded_addr_decoded_decoded_invMatrixOutputs_T_190}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo_hi, _decoded_addr_decoded_decoded_invMatrixOutputs_T_189}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_lo = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_193, _decoded_addr_decoded_decoded_invMatrixOutputs_T_192}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi = {_decoded_addr_decoded_decoded_invMatrixOutputs_T_195, _decoded_addr_decoded_decoded_invMatrixOutputs_T_194}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [6:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [12:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [24:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi_lo}; // @[pla.scala:120:37] wire [48:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi_lo}; // @[pla.scala:120:37] wire [97:0] decoded_addr_decoded_decoded_invMatrixOutputs_hi = {decoded_addr_decoded_decoded_invMatrixOutputs_hi_hi, decoded_addr_decoded_decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded_invMatrixOutputs = {decoded_addr_decoded_decoded_invMatrixOutputs_hi, decoded_addr_decoded_decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded_addr_decoded_decoded = decoded_addr_decoded_decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] assign decoded_addr_decoded_decoded_plaInput = decoded_addr_addr[11:0]; // @[pla.scala:77:22] wire decoded_addr_decoded_0 = decoded_addr_decoded_decoded[195]; // @[pla.scala:81:23] wire decoded_addr_121_2 = decoded_addr_decoded_0; // @[Decode.scala:50:77] wire decoded_addr_decoded_1 = decoded_addr_decoded_decoded[194]; // @[pla.scala:81:23] wire decoded_addr_66_2 = decoded_addr_decoded_1; // @[Decode.scala:50:77] wire decoded_addr_decoded_2 = decoded_addr_decoded_decoded[193]; // @[pla.scala:81:23] wire decoded_addr_13_2 = decoded_addr_decoded_2; // @[Decode.scala:50:77] wire decoded_addr_decoded_3 = decoded_addr_decoded_decoded[192]; // @[pla.scala:81:23] wire decoded_addr_153_2 = decoded_addr_decoded_3; // @[Decode.scala:50:77] wire decoded_addr_decoded_4 = decoded_addr_decoded_decoded[191]; // @[pla.scala:81:23] wire decoded_addr_115_2 = decoded_addr_decoded_4; // @[Decode.scala:50:77] wire decoded_addr_decoded_5 = decoded_addr_decoded_decoded[190]; // @[pla.scala:81:23] wire decoded_addr_125_2 = decoded_addr_decoded_5; // @[Decode.scala:50:77] wire decoded_addr_decoded_6 = decoded_addr_decoded_decoded[189]; // @[pla.scala:81:23] wire decoded_addr_89_2 = decoded_addr_decoded_6; // @[Decode.scala:50:77] wire decoded_addr_decoded_7 = decoded_addr_decoded_decoded[188]; // @[pla.scala:81:23] wire decoded_addr_135_2 = decoded_addr_decoded_7; // @[Decode.scala:50:77] wire decoded_addr_decoded_8 = decoded_addr_decoded_decoded[187]; // @[pla.scala:81:23] wire decoded_addr_94_2 = decoded_addr_decoded_8; // @[Decode.scala:50:77] wire decoded_addr_decoded_9 = decoded_addr_decoded_decoded[186]; // @[pla.scala:81:23] wire decoded_addr_170_2 = decoded_addr_decoded_9; // @[Decode.scala:50:77] wire decoded_addr_decoded_10 = decoded_addr_decoded_decoded[185]; // @[pla.scala:81:23] wire decoded_addr_173_2 = decoded_addr_decoded_10; // @[Decode.scala:50:77] wire decoded_addr_decoded_11 = decoded_addr_decoded_decoded[184]; // @[pla.scala:81:23] wire decoded_addr_179_2 = decoded_addr_decoded_11; // @[Decode.scala:50:77] wire decoded_addr_decoded_12 = decoded_addr_decoded_decoded[183]; // @[pla.scala:81:23] wire decoded_addr_35_2 = decoded_addr_decoded_12; // @[Decode.scala:50:77] wire decoded_addr_decoded_13 = decoded_addr_decoded_decoded[182]; // @[pla.scala:81:23] wire decoded_addr_172_2 = decoded_addr_decoded_13; // @[Decode.scala:50:77] wire decoded_addr_decoded_14 = decoded_addr_decoded_decoded[181]; // @[pla.scala:81:23] wire decoded_addr_59_2 = decoded_addr_decoded_14; // @[Decode.scala:50:77] wire decoded_addr_decoded_15 = decoded_addr_decoded_decoded[180]; // @[pla.scala:81:23] wire decoded_addr_112_2 = decoded_addr_decoded_15; // @[Decode.scala:50:77] wire decoded_addr_decoded_16 = decoded_addr_decoded_decoded[179]; // @[pla.scala:81:23] wire decoded_addr_69_2 = decoded_addr_decoded_16; // @[Decode.scala:50:77] wire decoded_addr_decoded_17 = decoded_addr_decoded_decoded[178]; // @[pla.scala:81:23] wire decoded_addr_171_2 = decoded_addr_decoded_17; // @[Decode.scala:50:77] wire decoded_addr_decoded_18 = decoded_addr_decoded_decoded[177]; // @[pla.scala:81:23] wire decoded_addr_128_2 = decoded_addr_decoded_18; // @[Decode.scala:50:77] wire decoded_addr_decoded_19 = decoded_addr_decoded_decoded[176]; // @[pla.scala:81:23] wire decoded_addr_156_2 = decoded_addr_decoded_19; // @[Decode.scala:50:77] wire decoded_addr_decoded_20 = decoded_addr_decoded_decoded[175]; // @[pla.scala:81:23] wire decoded_addr_189_2 = decoded_addr_decoded_20; // @[Decode.scala:50:77] wire decoded_addr_decoded_21 = decoded_addr_decoded_decoded[174]; // @[pla.scala:81:23] wire decoded_addr_20_2 = decoded_addr_decoded_21; // @[Decode.scala:50:77] wire decoded_addr_decoded_22 = decoded_addr_decoded_decoded[173]; // @[pla.scala:81:23] wire decoded_addr_34_2 = decoded_addr_decoded_22; // @[Decode.scala:50:77] wire decoded_addr_decoded_23 = decoded_addr_decoded_decoded[172]; // @[pla.scala:81:23] wire decoded_addr_6_2 = decoded_addr_decoded_23; // @[Decode.scala:50:77] wire decoded_addr_decoded_24 = decoded_addr_decoded_decoded[171]; // @[pla.scala:81:23] wire decoded_addr_177_2 = decoded_addr_decoded_24; // @[Decode.scala:50:77] wire decoded_addr_decoded_25 = decoded_addr_decoded_decoded[170]; // @[pla.scala:81:23] wire decoded_addr_105_2 = decoded_addr_decoded_25; // @[Decode.scala:50:77] wire decoded_addr_decoded_26 = decoded_addr_decoded_decoded[169]; // @[pla.scala:81:23] wire decoded_addr_62_2 = decoded_addr_decoded_26; // @[Decode.scala:50:77] wire decoded_addr_decoded_27 = decoded_addr_decoded_decoded[168]; // @[pla.scala:81:23] wire decoded_addr_188_2 = decoded_addr_decoded_27; // @[Decode.scala:50:77] wire decoded_addr_decoded_28 = decoded_addr_decoded_decoded[167]; // @[pla.scala:81:23] wire decoded_addr_148_2 = decoded_addr_decoded_28; // @[Decode.scala:50:77] wire decoded_addr_decoded_29 = decoded_addr_decoded_decoded[166]; // @[pla.scala:81:23] wire decoded_addr_22_2 = decoded_addr_decoded_29; // @[Decode.scala:50:77] wire decoded_addr_decoded_30 = decoded_addr_decoded_decoded[165]; // @[pla.scala:81:23] wire decoded_addr_86_2 = decoded_addr_decoded_30; // @[Decode.scala:50:77] wire decoded_addr_decoded_31 = decoded_addr_decoded_decoded[164]; // @[pla.scala:81:23] wire decoded_addr_141_2 = decoded_addr_decoded_31; // @[Decode.scala:50:77] wire decoded_addr_decoded_32 = decoded_addr_decoded_decoded[163]; // @[pla.scala:81:23] wire decoded_addr_103_2 = decoded_addr_decoded_32; // @[Decode.scala:50:77] wire decoded_addr_decoded_33 = decoded_addr_decoded_decoded[162]; // @[pla.scala:81:23] wire decoded_addr_152_2 = decoded_addr_decoded_33; // @[Decode.scala:50:77] wire decoded_addr_decoded_34 = decoded_addr_decoded_decoded[161]; // @[pla.scala:81:23] wire decoded_addr_73_2 = decoded_addr_decoded_34; // @[Decode.scala:50:77] wire decoded_addr_decoded_35 = decoded_addr_decoded_decoded[160]; // @[pla.scala:81:23] wire decoded_addr_37_2 = decoded_addr_decoded_35; // @[Decode.scala:50:77] wire decoded_addr_decoded_36 = decoded_addr_decoded_decoded[159]; // @[pla.scala:81:23] wire decoded_addr_0_2 = decoded_addr_decoded_36; // @[Decode.scala:50:77] wire decoded_addr_decoded_37 = decoded_addr_decoded_decoded[158]; // @[pla.scala:81:23] wire decoded_addr_72_2 = decoded_addr_decoded_37; // @[Decode.scala:50:77] wire decoded_addr_decoded_38 = decoded_addr_decoded_decoded[157]; // @[pla.scala:81:23] wire decoded_addr_33_2 = decoded_addr_decoded_38; // @[Decode.scala:50:77] wire decoded_addr_decoded_39 = decoded_addr_decoded_decoded[156]; // @[pla.scala:81:23] wire decoded_addr_131_2 = decoded_addr_decoded_39; // @[Decode.scala:50:77] wire decoded_addr_decoded_40 = decoded_addr_decoded_decoded[155]; // @[pla.scala:81:23] wire decoded_addr_180_2 = decoded_addr_decoded_40; // @[Decode.scala:50:77] wire decoded_addr_decoded_41 = decoded_addr_decoded_decoded[154]; // @[pla.scala:81:23] wire decoded_addr_165_2 = decoded_addr_decoded_41; // @[Decode.scala:50:77] wire decoded_addr_decoded_42 = decoded_addr_decoded_decoded[153]; // @[pla.scala:81:23] wire decoded_addr_91_2 = decoded_addr_decoded_42; // @[Decode.scala:50:77] wire decoded_addr_decoded_43 = decoded_addr_decoded_decoded[152]; // @[pla.scala:81:23] wire decoded_addr_176_2 = decoded_addr_decoded_43; // @[Decode.scala:50:77] wire decoded_addr_decoded_44 = decoded_addr_decoded_decoded[151]; // @[pla.scala:81:23] wire decoded_addr_56_2 = decoded_addr_decoded_44; // @[Decode.scala:50:77] wire decoded_addr_decoded_45 = decoded_addr_decoded_decoded[150]; // @[pla.scala:81:23] wire decoded_addr_147_2 = decoded_addr_decoded_45; // @[Decode.scala:50:77] wire decoded_addr_decoded_46 = decoded_addr_decoded_decoded[149]; // @[pla.scala:81:23] wire decoded_addr_119_2 = decoded_addr_decoded_46; // @[Decode.scala:50:77] wire decoded_addr_decoded_47 = decoded_addr_decoded_decoded[148]; // @[pla.scala:81:23] wire decoded_addr_143_2 = decoded_addr_decoded_47; // @[Decode.scala:50:77] wire decoded_addr_decoded_48 = decoded_addr_decoded_decoded[147]; // @[pla.scala:81:23] wire decoded_addr_129_2 = decoded_addr_decoded_48; // @[Decode.scala:50:77] wire decoded_addr_decoded_49 = decoded_addr_decoded_decoded[146]; // @[pla.scala:81:23] wire decoded_addr_104_2 = decoded_addr_decoded_49; // @[Decode.scala:50:77] wire decoded_addr_decoded_50 = decoded_addr_decoded_decoded[145]; // @[pla.scala:81:23] wire decoded_addr_1_2 = decoded_addr_decoded_50; // @[Decode.scala:50:77] wire decoded_addr_decoded_51 = decoded_addr_decoded_decoded[144]; // @[pla.scala:81:23] wire decoded_addr_19_2 = decoded_addr_decoded_51; // @[Decode.scala:50:77] wire decoded_addr_decoded_52 = decoded_addr_decoded_decoded[143]; // @[pla.scala:81:23] wire decoded_addr_96_2 = decoded_addr_decoded_52; // @[Decode.scala:50:77] wire decoded_addr_decoded_53 = decoded_addr_decoded_decoded[142]; // @[pla.scala:81:23] wire decoded_addr_5_2 = decoded_addr_decoded_53; // @[Decode.scala:50:77] wire decoded_addr_decoded_54 = decoded_addr_decoded_decoded[141]; // @[pla.scala:81:23] wire decoded_addr_142_2 = decoded_addr_decoded_54; // @[Decode.scala:50:77] wire decoded_addr_decoded_55 = decoded_addr_decoded_decoded[140]; // @[pla.scala:81:23] wire decoded_addr_49_2 = decoded_addr_decoded_55; // @[Decode.scala:50:77] wire decoded_addr_decoded_56 = decoded_addr_decoded_decoded[139]; // @[pla.scala:81:23] wire decoded_addr_61_2 = decoded_addr_decoded_56; // @[Decode.scala:50:77] wire decoded_addr_decoded_57 = decoded_addr_decoded_decoded[138]; // @[pla.scala:81:23] wire decoded_addr_136_2 = decoded_addr_decoded_57; // @[Decode.scala:50:77] wire decoded_addr_decoded_58 = decoded_addr_decoded_decoded[137]; // @[pla.scala:81:23] wire decoded_addr_45_2 = decoded_addr_decoded_58; // @[Decode.scala:50:77] wire decoded_addr_decoded_59 = decoded_addr_decoded_decoded[136]; // @[pla.scala:81:23] wire decoded_addr_75_2 = decoded_addr_decoded_59; // @[Decode.scala:50:77] wire decoded_addr_decoded_60 = decoded_addr_decoded_decoded[135]; // @[pla.scala:81:23] wire decoded_addr_113_2 = decoded_addr_decoded_60; // @[Decode.scala:50:77] wire decoded_addr_decoded_61 = decoded_addr_decoded_decoded[134]; // @[pla.scala:81:23] wire decoded_addr_99_2 = decoded_addr_decoded_61; // @[Decode.scala:50:77] wire decoded_addr_decoded_62 = decoded_addr_decoded_decoded[133]; // @[pla.scala:81:23] wire decoded_addr_83_2 = decoded_addr_decoded_62; // @[Decode.scala:50:77] wire decoded_addr_decoded_63 = decoded_addr_decoded_decoded[132]; // @[pla.scala:81:23] wire decoded_addr_110_2 = decoded_addr_decoded_63; // @[Decode.scala:50:77] wire decoded_addr_decoded_64 = decoded_addr_decoded_decoded[131]; // @[pla.scala:81:23] wire decoded_addr_44_2 = decoded_addr_decoded_64; // @[Decode.scala:50:77] wire decoded_addr_decoded_65 = decoded_addr_decoded_decoded[130]; // @[pla.scala:81:23] wire decoded_addr_132_2 = decoded_addr_decoded_65; // @[Decode.scala:50:77] wire decoded_addr_decoded_66 = decoded_addr_decoded_decoded[129]; // @[pla.scala:81:23] wire decoded_addr_158_2 = decoded_addr_decoded_66; // @[Decode.scala:50:77] wire decoded_addr_decoded_67 = decoded_addr_decoded_decoded[128]; // @[pla.scala:81:23] wire decoded_addr_30_2 = decoded_addr_decoded_67; // @[Decode.scala:50:77] wire decoded_addr_decoded_68 = decoded_addr_decoded_decoded[127]; // @[pla.scala:81:23] wire decoded_addr_168_2 = decoded_addr_decoded_68; // @[Decode.scala:50:77] wire decoded_addr_decoded_69 = decoded_addr_decoded_decoded[126]; // @[pla.scala:81:23] wire decoded_addr_191_2 = decoded_addr_decoded_69; // @[Decode.scala:50:77] wire decoded_addr_decoded_70 = decoded_addr_decoded_decoded[125]; // @[pla.scala:81:23] wire decoded_addr_160_2 = decoded_addr_decoded_70; // @[Decode.scala:50:77] wire decoded_addr_decoded_71 = decoded_addr_decoded_decoded[124]; // @[pla.scala:81:23] wire decoded_addr_32_2 = decoded_addr_decoded_71; // @[Decode.scala:50:77] wire decoded_addr_decoded_72 = decoded_addr_decoded_decoded[123]; // @[pla.scala:81:23] wire decoded_addr_164_2 = decoded_addr_decoded_72; // @[Decode.scala:50:77] wire decoded_addr_decoded_73 = decoded_addr_decoded_decoded[122]; // @[pla.scala:81:23] wire decoded_addr_21_2 = decoded_addr_decoded_73; // @[Decode.scala:50:77] wire decoded_addr_decoded_74 = decoded_addr_decoded_decoded[121]; // @[pla.scala:81:23] wire decoded_addr_101_2 = decoded_addr_decoded_74; // @[Decode.scala:50:77] wire decoded_addr_decoded_75 = decoded_addr_decoded_decoded[120]; // @[pla.scala:81:23] wire decoded_addr_10_2 = decoded_addr_decoded_75; // @[Decode.scala:50:77] wire decoded_addr_decoded_76 = decoded_addr_decoded_decoded[119]; // @[pla.scala:81:23] wire decoded_addr_76_2 = decoded_addr_decoded_76; // @[Decode.scala:50:77] wire decoded_addr_decoded_77 = decoded_addr_decoded_decoded[118]; // @[pla.scala:81:23] wire decoded_addr_95_2 = decoded_addr_decoded_77; // @[Decode.scala:50:77] wire decoded_addr_decoded_78 = decoded_addr_decoded_decoded[117]; // @[pla.scala:81:23] wire decoded_addr_57_2 = decoded_addr_decoded_78; // @[Decode.scala:50:77] wire decoded_addr_decoded_79 = decoded_addr_decoded_decoded[116]; // @[pla.scala:81:23] wire decoded_addr_137_2 = decoded_addr_decoded_79; // @[Decode.scala:50:77] wire decoded_addr_decoded_80 = decoded_addr_decoded_decoded[115]; // @[pla.scala:81:23] wire decoded_addr_55_2 = decoded_addr_decoded_80; // @[Decode.scala:50:77] wire decoded_addr_decoded_81 = decoded_addr_decoded_decoded[114]; // @[pla.scala:81:23] wire decoded_addr_140_2 = decoded_addr_decoded_81; // @[Decode.scala:50:77] wire decoded_addr_decoded_82 = decoded_addr_decoded_decoded[113]; // @[pla.scala:81:23] wire decoded_addr_74_2 = decoded_addr_decoded_82; // @[Decode.scala:50:77] wire decoded_addr_decoded_83 = decoded_addr_decoded_decoded[112]; // @[pla.scala:81:23] wire decoded_addr_100_2 = decoded_addr_decoded_83; // @[Decode.scala:50:77] wire decoded_addr_decoded_84 = decoded_addr_decoded_decoded[111]; // @[pla.scala:81:23] wire decoded_addr_84_2 = decoded_addr_decoded_84; // @[Decode.scala:50:77] wire decoded_addr_decoded_85 = decoded_addr_decoded_decoded[110]; // @[pla.scala:81:23] wire decoded_addr_114_2 = decoded_addr_decoded_85; // @[Decode.scala:50:77] wire decoded_addr_decoded_86 = decoded_addr_decoded_decoded[109]; // @[pla.scala:81:23] wire decoded_addr_193_2 = decoded_addr_decoded_86; // @[Decode.scala:50:77] wire decoded_addr_decoded_87 = decoded_addr_decoded_decoded[108]; // @[pla.scala:81:23] wire decoded_addr_18_2 = decoded_addr_decoded_87; // @[Decode.scala:50:77] wire decoded_addr_decoded_88 = decoded_addr_decoded_decoded[107]; // @[pla.scala:81:23] wire decoded_addr_159_2 = decoded_addr_decoded_88; // @[Decode.scala:50:77] wire decoded_addr_decoded_89 = decoded_addr_decoded_decoded[106]; // @[pla.scala:81:23] wire decoded_addr_29_2 = decoded_addr_decoded_89; // @[Decode.scala:50:77] wire decoded_addr_decoded_90 = decoded_addr_decoded_decoded[105]; // @[pla.scala:81:23] wire decoded_addr_27_2 = decoded_addr_decoded_90; // @[Decode.scala:50:77] wire decoded_addr_decoded_91 = decoded_addr_decoded_decoded[104]; // @[pla.scala:81:23] wire decoded_addr_40_2 = decoded_addr_decoded_91; // @[Decode.scala:50:77] wire decoded_addr_decoded_92 = decoded_addr_decoded_decoded[103]; // @[pla.scala:81:23] wire decoded_addr_25_2 = decoded_addr_decoded_92; // @[Decode.scala:50:77] wire decoded_addr_decoded_93 = decoded_addr_decoded_decoded[102]; // @[pla.scala:81:23] wire decoded_addr_181_2 = decoded_addr_decoded_93; // @[Decode.scala:50:77] wire decoded_addr_decoded_94 = decoded_addr_decoded_decoded[101]; // @[pla.scala:81:23] wire decoded_addr_9_2 = decoded_addr_decoded_94; // @[Decode.scala:50:77] wire decoded_addr_decoded_95 = decoded_addr_decoded_decoded[100]; // @[pla.scala:81:23] wire decoded_addr_174_2 = decoded_addr_decoded_95; // @[Decode.scala:50:77] wire decoded_addr_decoded_96 = decoded_addr_decoded_decoded[99]; // @[pla.scala:81:23] wire decoded_addr_194_2 = decoded_addr_decoded_96; // @[Decode.scala:50:77] wire decoded_addr_decoded_97 = decoded_addr_decoded_decoded[98]; // @[pla.scala:81:23] wire decoded_addr_60_2 = decoded_addr_decoded_97; // @[Decode.scala:50:77] wire decoded_addr_decoded_98 = decoded_addr_decoded_decoded[97]; // @[pla.scala:81:23] wire decoded_addr_122_2 = decoded_addr_decoded_98; // @[Decode.scala:50:77] wire decoded_addr_decoded_99 = decoded_addr_decoded_decoded[96]; // @[pla.scala:81:23] wire decoded_addr_70_2 = decoded_addr_decoded_99; // @[Decode.scala:50:77] wire decoded_addr_decoded_100 = decoded_addr_decoded_decoded[95]; // @[pla.scala:81:23] wire decoded_addr_92_2 = decoded_addr_decoded_100; // @[Decode.scala:50:77] wire decoded_addr_decoded_101 = decoded_addr_decoded_decoded[94]; // @[pla.scala:81:23] wire decoded_addr_127_2 = decoded_addr_decoded_101; // @[Decode.scala:50:77] wire decoded_addr_decoded_102 = decoded_addr_decoded_decoded[93]; // @[pla.scala:81:23] wire decoded_addr_106_2 = decoded_addr_decoded_102; // @[Decode.scala:50:77] wire decoded_addr_decoded_103 = decoded_addr_decoded_decoded[92]; // @[pla.scala:81:23] wire decoded_addr_87_2 = decoded_addr_decoded_103; // @[Decode.scala:50:77] wire decoded_addr_decoded_104 = decoded_addr_decoded_decoded[91]; // @[pla.scala:81:23] wire decoded_addr_118_2 = decoded_addr_decoded_104; // @[Decode.scala:50:77] wire decoded_addr_decoded_105 = decoded_addr_decoded_decoded[90]; // @[pla.scala:81:23] wire decoded_addr_53_2 = decoded_addr_decoded_105; // @[Decode.scala:50:77] wire decoded_addr_decoded_106 = decoded_addr_decoded_decoded[89]; // @[pla.scala:81:23] wire decoded_addr_79_2 = decoded_addr_decoded_106; // @[Decode.scala:50:77] wire decoded_addr_decoded_107 = decoded_addr_decoded_decoded[88]; // @[pla.scala:81:23] wire decoded_addr_155_2 = decoded_addr_decoded_107; // @[Decode.scala:50:77] wire decoded_addr_decoded_108 = decoded_addr_decoded_decoded[87]; // @[pla.scala:81:23] wire decoded_addr_39_2 = decoded_addr_decoded_108; // @[Decode.scala:50:77] wire decoded_addr_decoded_109 = decoded_addr_decoded_decoded[86]; // @[pla.scala:81:23] wire decoded_addr_166_2 = decoded_addr_decoded_109; // @[Decode.scala:50:77] wire decoded_addr_decoded_110 = decoded_addr_decoded_decoded[85]; // @[pla.scala:81:23] wire decoded_addr_36_2 = decoded_addr_decoded_110; // @[Decode.scala:50:77] wire decoded_addr_decoded_111 = decoded_addr_decoded_decoded[84]; // @[pla.scala:81:23] wire decoded_addr_8_2 = decoded_addr_decoded_111; // @[Decode.scala:50:77] wire decoded_addr_decoded_112 = decoded_addr_decoded_decoded[83]; // @[pla.scala:81:23] wire decoded_addr_38_2 = decoded_addr_decoded_112; // @[Decode.scala:50:77] wire decoded_addr_decoded_113 = decoded_addr_decoded_decoded[82]; // @[pla.scala:81:23] wire decoded_addr_43_2 = decoded_addr_decoded_113; // @[Decode.scala:50:77] wire decoded_addr_decoded_114 = decoded_addr_decoded_decoded[81]; // @[pla.scala:81:23] wire decoded_addr_23_2 = decoded_addr_decoded_114; // @[Decode.scala:50:77] wire decoded_addr_decoded_115 = decoded_addr_decoded_decoded[80]; // @[pla.scala:81:23] wire decoded_addr_187_2 = decoded_addr_decoded_115; // @[Decode.scala:50:77] wire decoded_addr_decoded_116 = decoded_addr_decoded_decoded[79]; // @[pla.scala:81:23] wire decoded_addr_149_2 = decoded_addr_decoded_116; // @[Decode.scala:50:77] wire decoded_addr_decoded_117 = decoded_addr_decoded_decoded[78]; // @[pla.scala:81:23] wire decoded_addr_77_2 = decoded_addr_decoded_117; // @[Decode.scala:50:77] wire decoded_addr_decoded_118 = decoded_addr_decoded_decoded[77]; // @[pla.scala:81:23] wire decoded_addr_185_2 = decoded_addr_decoded_118; // @[Decode.scala:50:77] wire decoded_addr_decoded_119 = decoded_addr_decoded_decoded[76]; // @[pla.scala:81:23] wire decoded_addr_81_2 = decoded_addr_decoded_119; // @[Decode.scala:50:77] wire decoded_addr_decoded_120 = decoded_addr_decoded_decoded[75]; // @[pla.scala:81:23] wire decoded_addr_134_2 = decoded_addr_decoded_120; // @[Decode.scala:50:77] wire decoded_addr_decoded_121 = decoded_addr_decoded_decoded[74]; // @[pla.scala:81:23] wire decoded_addr_111_2 = decoded_addr_decoded_121; // @[Decode.scala:50:77] wire decoded_addr_decoded_122 = decoded_addr_decoded_decoded[73]; // @[pla.scala:81:23] wire decoded_addr_145_2 = decoded_addr_decoded_122; // @[Decode.scala:50:77] wire decoded_addr_decoded_123 = decoded_addr_decoded_decoded[72]; // @[pla.scala:81:23] wire decoded_addr_124_2 = decoded_addr_decoded_123; // @[Decode.scala:50:77] wire decoded_addr_decoded_124 = decoded_addr_decoded_decoded[71]; // @[pla.scala:81:23] wire decoded_addr_102_2 = decoded_addr_decoded_124; // @[Decode.scala:50:77] wire decoded_addr_decoded_125 = decoded_addr_decoded_decoded[70]; // @[pla.scala:81:23] wire decoded_addr_90_2 = decoded_addr_decoded_125; // @[Decode.scala:50:77] wire decoded_addr_decoded_126 = decoded_addr_decoded_decoded[69]; // @[pla.scala:81:23] wire decoded_addr_63_2 = decoded_addr_decoded_126; // @[Decode.scala:50:77] wire decoded_addr_decoded_127 = decoded_addr_decoded_decoded[68]; // @[pla.scala:81:23] wire decoded_addr_192_2 = decoded_addr_decoded_127; // @[Decode.scala:50:77] wire decoded_addr_decoded_128 = decoded_addr_decoded_decoded[67]; // @[pla.scala:81:23] wire decoded_addr_78_2 = decoded_addr_decoded_128; // @[Decode.scala:50:77] wire decoded_addr_decoded_129 = decoded_addr_decoded_decoded[66]; // @[pla.scala:81:23] wire decoded_addr_151_2 = decoded_addr_decoded_129; // @[Decode.scala:50:77] wire decoded_addr_decoded_130 = decoded_addr_decoded_decoded[65]; // @[pla.scala:81:23] wire decoded_addr_51_2 = decoded_addr_decoded_130; // @[Decode.scala:50:77] wire decoded_addr_decoded_131 = decoded_addr_decoded_decoded[64]; // @[pla.scala:81:23] wire decoded_addr_67_2 = decoded_addr_decoded_131; // @[Decode.scala:50:77] wire decoded_addr_decoded_132 = decoded_addr_decoded_decoded[63]; // @[pla.scala:81:23] wire decoded_addr_46_2 = decoded_addr_decoded_132; // @[Decode.scala:50:77] wire decoded_addr_decoded_133 = decoded_addr_decoded_decoded[62]; // @[pla.scala:81:23] wire decoded_addr_54_2 = decoded_addr_decoded_133; // @[Decode.scala:50:77] wire decoded_addr_decoded_134 = decoded_addr_decoded_decoded[61]; // @[pla.scala:81:23] wire decoded_addr_85_2 = decoded_addr_decoded_134; // @[Decode.scala:50:77] wire decoded_addr_decoded_135 = decoded_addr_decoded_decoded[60]; // @[pla.scala:81:23] wire decoded_addr_97_2 = decoded_addr_decoded_135; // @[Decode.scala:50:77] wire decoded_addr_decoded_136 = decoded_addr_decoded_decoded[59]; // @[pla.scala:81:23] wire decoded_addr_120_2 = decoded_addr_decoded_136; // @[Decode.scala:50:77] wire decoded_addr_decoded_137 = decoded_addr_decoded_decoded[58]; // @[pla.scala:81:23] wire decoded_addr_7_2 = decoded_addr_decoded_137; // @[Decode.scala:50:77] wire decoded_addr_decoded_138 = decoded_addr_decoded_decoded[57]; // @[pla.scala:81:23] wire decoded_addr_93_2 = decoded_addr_decoded_138; // @[Decode.scala:50:77] wire decoded_addr_decoded_139 = decoded_addr_decoded_decoded[56]; // @[pla.scala:81:23] wire decoded_addr_42_2 = decoded_addr_decoded_139; // @[Decode.scala:50:77] wire decoded_addr_decoded_140 = decoded_addr_decoded_decoded[55]; // @[pla.scala:81:23] wire decoded_addr_126_2 = decoded_addr_decoded_140; // @[Decode.scala:50:77] wire decoded_addr_decoded_141 = decoded_addr_decoded_decoded[54]; // @[pla.scala:81:23] wire decoded_addr_154_2 = decoded_addr_decoded_141; // @[Decode.scala:50:77] wire decoded_addr_decoded_142 = decoded_addr_decoded_decoded[53]; // @[pla.scala:81:23] wire decoded_addr_28_2 = decoded_addr_decoded_142; // @[Decode.scala:50:77] wire decoded_addr_decoded_143 = decoded_addr_decoded_decoded[52]; // @[pla.scala:81:23] wire decoded_addr_162_2 = decoded_addr_decoded_143; // @[Decode.scala:50:77] wire decoded_addr_decoded_144 = decoded_addr_decoded_decoded[51]; // @[pla.scala:81:23] wire decoded_addr_190_2 = decoded_addr_decoded_144; // @[Decode.scala:50:77] wire decoded_addr_decoded_145 = decoded_addr_decoded_decoded[50]; // @[pla.scala:81:23] wire decoded_addr_182_2 = decoded_addr_decoded_145; // @[Decode.scala:50:77] wire decoded_addr_decoded_146 = decoded_addr_decoded_decoded[49]; // @[pla.scala:81:23] wire decoded_addr_14_2 = decoded_addr_decoded_146; // @[Decode.scala:50:77] wire decoded_addr_decoded_147 = decoded_addr_decoded_decoded[48]; // @[pla.scala:81:23] wire decoded_addr_175_2 = decoded_addr_decoded_147; // @[Decode.scala:50:77] wire decoded_addr_decoded_148 = decoded_addr_decoded_decoded[47]; // @[pla.scala:81:23] wire decoded_addr_17_2 = decoded_addr_decoded_148; // @[Decode.scala:50:77] wire decoded_addr_decoded_149 = decoded_addr_decoded_decoded[46]; // @[pla.scala:81:23] wire decoded_addr_139_2 = decoded_addr_decoded_149; // @[Decode.scala:50:77] wire decoded_addr_decoded_150 = decoded_addr_decoded_decoded[45]; // @[pla.scala:81:23] wire decoded_addr_15_2 = decoded_addr_decoded_150; // @[Decode.scala:50:77] wire decoded_addr_decoded_151 = decoded_addr_decoded_decoded[44]; // @[pla.scala:81:23] wire decoded_addr_80_2 = decoded_addr_decoded_151; // @[Decode.scala:50:77] wire decoded_addr_decoded_152 = decoded_addr_decoded_decoded[43]; // @[pla.scala:81:23] wire decoded_addr_108_2 = decoded_addr_decoded_152; // @[Decode.scala:50:77] wire decoded_addr_decoded_153 = decoded_addr_decoded_decoded[42]; // @[pla.scala:81:23] wire decoded_addr_68_2 = decoded_addr_decoded_153; // @[Decode.scala:50:77] wire decoded_addr_decoded_154 = decoded_addr_decoded_decoded[41]; // @[pla.scala:81:23] wire decoded_addr_47_2 = decoded_addr_decoded_154; // @[Decode.scala:50:77] wire decoded_addr_decoded_155 = decoded_addr_decoded_decoded[40]; // @[pla.scala:81:23] wire decoded_addr_58_2 = decoded_addr_decoded_155; // @[Decode.scala:50:77] wire decoded_addr_decoded_156 = decoded_addr_decoded_decoded[39]; // @[pla.scala:81:23] wire decoded_addr_133_2 = decoded_addr_decoded_156; // @[Decode.scala:50:77] wire decoded_addr_decoded_157 = decoded_addr_decoded_decoded[38]; // @[pla.scala:81:23] wire decoded_addr_71_2 = decoded_addr_decoded_157; // @[Decode.scala:50:77] wire decoded_addr_decoded_158 = decoded_addr_decoded_decoded[37]; // @[pla.scala:81:23] wire decoded_addr_117_2 = decoded_addr_decoded_158; // @[Decode.scala:50:77] wire decoded_addr_decoded_159 = decoded_addr_decoded_decoded[36]; // @[pla.scala:81:23] wire decoded_addr_4_2 = decoded_addr_decoded_159; // @[Decode.scala:50:77] wire decoded_addr_decoded_160 = decoded_addr_decoded_decoded[35]; // @[pla.scala:81:23] wire decoded_addr_109_2 = decoded_addr_decoded_160; // @[Decode.scala:50:77] wire decoded_addr_decoded_161 = decoded_addr_decoded_decoded[34]; // @[pla.scala:81:23] wire decoded_addr_186_2 = decoded_addr_decoded_161; // @[Decode.scala:50:77] wire decoded_addr_decoded_162 = decoded_addr_decoded_decoded[33]; // @[pla.scala:81:23] wire decoded_addr_16_2 = decoded_addr_decoded_162; // @[Decode.scala:50:77] wire decoded_addr_decoded_163 = decoded_addr_decoded_decoded[32]; // @[pla.scala:81:23] wire decoded_addr_150_2 = decoded_addr_decoded_163; // @[Decode.scala:50:77] wire decoded_addr_decoded_164 = decoded_addr_decoded_decoded[31]; // @[pla.scala:81:23] wire decoded_addr_31_2 = decoded_addr_decoded_164; // @[Decode.scala:50:77] wire decoded_addr_decoded_165 = decoded_addr_decoded_decoded[30]; // @[pla.scala:81:23] wire decoded_addr_2_2 = decoded_addr_decoded_165; // @[Decode.scala:50:77] wire decoded_addr_decoded_166 = decoded_addr_decoded_decoded[29]; // @[pla.scala:81:23] wire decoded_addr_82_2 = decoded_addr_decoded_166; // @[Decode.scala:50:77] wire decoded_addr_decoded_167 = decoded_addr_decoded_decoded[28]; // @[pla.scala:81:23] wire decoded_addr_167_2 = decoded_addr_decoded_167; // @[Decode.scala:50:77] wire decoded_addr_decoded_168 = decoded_addr_decoded_decoded[27]; // @[pla.scala:81:23] wire decoded_addr_64_2 = decoded_addr_decoded_168; // @[Decode.scala:50:77] wire decoded_addr_decoded_169 = decoded_addr_decoded_decoded[26]; // @[pla.scala:81:23] wire decoded_addr_195_2 = decoded_addr_decoded_169; // @[Decode.scala:50:77] wire decoded_addr_decoded_170 = decoded_addr_decoded_decoded[25]; // @[pla.scala:81:23] wire decoded_addr_144_2 = decoded_addr_decoded_170; // @[Decode.scala:50:77] wire decoded_addr_decoded_171 = decoded_addr_decoded_decoded[24]; // @[pla.scala:81:23] wire decoded_addr_184_2 = decoded_addr_decoded_171; // @[Decode.scala:50:77] wire decoded_addr_decoded_172 = decoded_addr_decoded_decoded[23]; // @[pla.scala:81:23] wire decoded_addr_169_2 = decoded_addr_decoded_172; // @[Decode.scala:50:77] wire decoded_addr_decoded_173 = decoded_addr_decoded_decoded[22]; // @[pla.scala:81:23] wire decoded_addr_12_2 = decoded_addr_decoded_173; // @[Decode.scala:50:77] wire decoded_addr_decoded_174 = decoded_addr_decoded_decoded[21]; // @[pla.scala:81:23] wire decoded_addr_157_2 = decoded_addr_decoded_174; // @[Decode.scala:50:77] wire decoded_addr_decoded_175 = decoded_addr_decoded_decoded[20]; // @[pla.scala:81:23] wire decoded_addr_130_2 = decoded_addr_decoded_175; // @[Decode.scala:50:77] wire decoded_addr_decoded_176 = decoded_addr_decoded_decoded[19]; // @[pla.scala:81:23] wire decoded_addr_11_2 = decoded_addr_decoded_176; // @[Decode.scala:50:77] wire decoded_addr_decoded_177 = decoded_addr_decoded_decoded[18]; // @[pla.scala:81:23] wire decoded_addr_161_2 = decoded_addr_decoded_177; // @[Decode.scala:50:77] wire decoded_addr_decoded_178 = decoded_addr_decoded_decoded[17]; // @[pla.scala:81:23] wire decoded_addr_107_2 = decoded_addr_decoded_178; // @[Decode.scala:50:77] wire decoded_addr_decoded_179 = decoded_addr_decoded_decoded[16]; // @[pla.scala:81:23] wire decoded_addr_65_2 = decoded_addr_decoded_179; // @[Decode.scala:50:77] wire decoded_addr_decoded_180 = decoded_addr_decoded_decoded[15]; // @[pla.scala:81:23] wire decoded_addr_26_2 = decoded_addr_decoded_180; // @[Decode.scala:50:77] wire decoded_addr_decoded_181 = decoded_addr_decoded_decoded[14]; // @[pla.scala:81:23] wire decoded_addr_178_2 = decoded_addr_decoded_181; // @[Decode.scala:50:77] wire decoded_addr_decoded_182 = decoded_addr_decoded_decoded[13]; // @[pla.scala:81:23] wire decoded_addr_146_2 = decoded_addr_decoded_182; // @[Decode.scala:50:77] wire decoded_addr_decoded_183 = decoded_addr_decoded_decoded[12]; // @[pla.scala:81:23] wire decoded_addr_52_2 = decoded_addr_decoded_183; // @[Decode.scala:50:77] wire decoded_addr_decoded_184 = decoded_addr_decoded_decoded[11]; // @[pla.scala:81:23] wire decoded_addr_88_2 = decoded_addr_decoded_184; // @[Decode.scala:50:77] wire decoded_addr_decoded_185 = decoded_addr_decoded_decoded[10]; // @[pla.scala:81:23] wire decoded_addr_138_2 = decoded_addr_decoded_185; // @[Decode.scala:50:77] wire decoded_addr_decoded_186 = decoded_addr_decoded_decoded[9]; // @[pla.scala:81:23] wire decoded_addr_183_2 = decoded_addr_decoded_186; // @[Decode.scala:50:77] wire decoded_addr_decoded_187 = decoded_addr_decoded_decoded[8]; // @[pla.scala:81:23] wire decoded_addr_41_2 = decoded_addr_decoded_187; // @[Decode.scala:50:77] wire decoded_addr_decoded_188 = decoded_addr_decoded_decoded[7]; // @[pla.scala:81:23] wire decoded_addr_50_2 = decoded_addr_decoded_188; // @[Decode.scala:50:77] wire decoded_addr_decoded_189 = decoded_addr_decoded_decoded[6]; // @[pla.scala:81:23] wire decoded_addr_98_2 = decoded_addr_decoded_189; // @[Decode.scala:50:77] wire decoded_addr_decoded_190 = decoded_addr_decoded_decoded[5]; // @[pla.scala:81:23] wire decoded_addr_123_2 = decoded_addr_decoded_190; // @[Decode.scala:50:77] wire decoded_addr_decoded_191 = decoded_addr_decoded_decoded[4]; // @[pla.scala:81:23] wire decoded_addr_24_2 = decoded_addr_decoded_191; // @[Decode.scala:50:77] wire decoded_addr_decoded_192 = decoded_addr_decoded_decoded[3]; // @[pla.scala:81:23] wire decoded_addr_3_2 = decoded_addr_decoded_192; // @[Decode.scala:50:77] wire decoded_addr_decoded_193 = decoded_addr_decoded_decoded[2]; // @[pla.scala:81:23] wire decoded_addr_48_2 = decoded_addr_decoded_193; // @[Decode.scala:50:77] wire decoded_addr_decoded_194 = decoded_addr_decoded_decoded[1]; // @[pla.scala:81:23] wire decoded_addr_163_2 = decoded_addr_decoded_194; // @[Decode.scala:50:77] wire decoded_addr_decoded_195 = decoded_addr_decoded_decoded[0]; // @[pla.scala:81:23] wire decoded_addr_116_2 = decoded_addr_decoded_195; // @[Decode.scala:50:77] wire _wdata_T = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _new_mip_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_1 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire _newBPC_T_25 = io_rw_cmd_0[1]; // @[CSR.scala:377:7, :1643:13] wire [31:0] _wdata_T_1 = _wdata_T ? io_rw_rdata_0 : 32'h0; // @[CSR.scala:377:7, :1643:{9,13}] wire [31:0] _wdata_T_2 = _wdata_T_1 | io_rw_wdata_0; // @[CSR.scala:377:7, :1643:{9,30}] wire [1:0] _wdata_T_3 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _new_mip_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_4 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire [1:0] _newBPC_T_28 = io_rw_cmd_0[1:0]; // @[CSR.scala:377:7, :1643:49] wire _wdata_T_4 = &_wdata_T_3; // @[CSR.scala:1643:{49,55}] wire [31:0] _wdata_T_5 = _wdata_T_4 ? io_rw_wdata_0 : 32'h0; // @[CSR.scala:377:7, :1643:{45,55}] wire [31:0] _wdata_T_6 = ~_wdata_T_5; // @[CSR.scala:1643:{41,45}] assign wdata = _wdata_T_2 & _wdata_T_6; // @[CSR.scala:1643:{30,39,41}] assign io_customCSRs_0_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_1_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_2_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] assign io_customCSRs_3_wdata_0 = wdata; // @[CSR.scala:377:7, :1643:39] wire [31:0] _new_dcsr_WIRE = wdata; // @[CSR.scala:1322:38, :1643:39] wire [31:0] _reg_bp_0_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [31:0] _reg_bp_1_control_WIRE_1 = wdata; // @[CSR.scala:1471:41, :1643:39] wire [31:0] _newCfg_T = wdata; // @[CSR.scala:1491:29, :1643:39] wire [31:0] _newCfg_T_28 = wdata; // @[CSR.scala:1491:29, :1643:39] wire system_insn = io_rw_cmd_0 == 3'h4; // @[CSR.scala:377:7, :876:31] wire [31:0] _insn_T = {io_rw_addr_0, 20'h0}; // @[CSR.scala:377:7, :892:44] wire [31:0] insn = {_insn_T[31:7], _insn_T[6:0] | 7'h73}; // @[CSR.scala:892:{30,44}] wire [31:0] decoded_plaInput = insn; // @[pla.scala:77:22] wire [31:0] decoded_invInputs = ~decoded_plaInput; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs; // @[pla.scala:120:37] wire [8:0] decoded; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0 = decoded_invInputs[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_1 = decoded_invInputs[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_1 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_0_3 = decoded_invInputs[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_1 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_3 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_4 = decoded_invInputs[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_1 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_3 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_4 = decoded_invInputs[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_1 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_3 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_4 = decoded_invInputs[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_1 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_2 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_3 = decoded_invInputs[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_1 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_2 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_3 = decoded_invInputs[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_1 = decoded_invInputs[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_1 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_2 = decoded_invInputs[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_1 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_2 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_3 = decoded_invInputs[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_1 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_2 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_3 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_5 = decoded_invInputs[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo = {decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_andMatrixInput_11}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi = {decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo = {decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi = {decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo = {decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi = {decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi = {decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi = {decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T = {decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2 = &_decoded_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_5 = decoded_andMatrixOutputs_5_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_1 = decoded_plaInput[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_1 = {decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_1 = {decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_1 = {decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_1 = {decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_1 = {decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_1 = {decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_1 = {decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_1 = {decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2 = &_decoded_andMatrixOutputs_T_1; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_4 = decoded_andMatrixOutputs_1_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_2 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_3 = decoded_plaInput[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _decoded_andMatrixOutputs_T_2 = {decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2 = &_decoded_andMatrixOutputs_T_2; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T = decoded_andMatrixOutputs_3_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_2 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_3 = decoded_plaInput[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_2 = {decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_3 = {decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_2 = {decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_2 = {decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_3}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_3 = {decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_3 = {decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2 = &_decoded_andMatrixOutputs_T_3; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_4 = decoded_plaInput[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_3 = {decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_4 = {decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_3 = {decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_3 = {decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_4}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_4 = {decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_4 = {decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2 = &_decoded_andMatrixOutputs_T_4; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_1 = decoded_andMatrixOutputs_4_2; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_5 = decoded_plaInput[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_5 = {decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2 = &_decoded_andMatrixOutputs_T_5; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_2 = {decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_2_2}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_3 = |_decoded_orMatrixOutputs_T_2; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_hi_lo = {_decoded_orMatrixOutputs_T_1, _decoded_orMatrixOutputs_T}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi = {_decoded_orMatrixOutputs_T_5, _decoded_orMatrixOutputs_T_4}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi = {decoded_orMatrixOutputs_hi_hi_hi, _decoded_orMatrixOutputs_T_3}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi = {decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs = {decoded_orMatrixOutputs_hi, 4'h0}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T = decoded_orMatrixOutputs[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_1 = decoded_orMatrixOutputs[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_2 = decoded_orMatrixOutputs[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_3 = decoded_orMatrixOutputs[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_4 = decoded_orMatrixOutputs[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_5 = decoded_orMatrixOutputs[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_6 = decoded_orMatrixOutputs[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_7 = decoded_orMatrixOutputs[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_8 = decoded_orMatrixOutputs[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo = {_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi = {_decoded_invMatrixOutputs_T_3, _decoded_invMatrixOutputs_T_2}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo = {decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo = {_decoded_invMatrixOutputs_T_5, _decoded_invMatrixOutputs_T_4}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi = {_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi = {decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_6}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi = {decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs = {decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo}; // @[pla.scala:120:37] assign decoded = decoded_invMatrixOutputs; // @[pla.scala:81:23, :120:37] wire insn_call = system_insn & decoded[8]; // @[pla.scala:81:23] wire insn_break = system_insn & decoded[7]; // @[pla.scala:81:23] wire insn_ret = system_insn & decoded[6]; // @[pla.scala:81:23] wire insn_cease = system_insn & decoded[5]; // @[pla.scala:81:23] wire insn_wfi = system_insn & decoded[4]; // @[pla.scala:81:23] wire [11:0] addr = io_decode_0_inst_0[31:20]; // @[CSR.scala:377:7, :897:27] wire [11:0] io_decode_0_fp_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_vector_csr_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput = addr; // @[pla.scala:77:22] wire [11:0] io_decode_0_read_illegal_plaInput_1 = addr; // @[pla.scala:77:22] wire [31:0] decoded_invInputs_1 = ~decoded_plaInput_1; // @[pla.scala:77:22, :78:21] wire [8:0] decoded_invMatrixOutputs_1; // @[pla.scala:120:37] wire [8:0] decoded_1; // @[pla.scala:81:23] wire decoded_andMatrixOutputs_andMatrixInput_0_6 = decoded_invInputs_1[20]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_6 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_7 = decoded_invInputs_1[21]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_5 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_6 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_0_9 = decoded_invInputs_1[22]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_5 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_6 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_9 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_10 = decoded_invInputs_1[23]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_4 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_5 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_8 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_9 = decoded_invInputs_1[24]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_4 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_5 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_8 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_9 = decoded_invInputs_1[25]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_4 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_6_5 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_6 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_4_7 = decoded_invInputs_1[26]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_4 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_7_5 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_6 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_5_7 = decoded_invInputs_1[27]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_4 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_5 = decoded_invInputs_1[28]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_4 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_5 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_8 = decoded_invInputs_1[29]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_2 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_10_3 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_2_7 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_6 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_8_7 = decoded_invInputs_1[30]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_2 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_11_3 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_3_7 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_6 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_9_7 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire decoded_andMatrixOutputs_andMatrixInput_1_11 = decoded_invInputs_1[31]; // @[pla.scala:78:21, :91:29] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_4 = {decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_11_2}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_andMatrixOutputs_andMatrixInput_7_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_4 = {decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_8_4}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_5 = {decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_2 = {decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_4}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_4 = {decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_andMatrixInput_5_4}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_4 = {decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_4 = {decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_2_5}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_5 = {decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_6 = {decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_5_2_1 = &_decoded_andMatrixOutputs_T_6; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_11 = decoded_andMatrixOutputs_5_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_7 = decoded_plaInput_1[20]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_3}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_lo_5 = {decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_andMatrixOutputs_andMatrixInput_7_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_5 = {decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_8_5}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_lo_6 = {decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_hi_3 = {decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_5}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_lo_5 = {decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_andMatrixInput_5_5}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_5 = {decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_5 = {decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_6}; // @[pla.scala:91:29, :98:53] wire [5:0] decoded_andMatrixOutputs_hi_6 = {decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5}; // @[pla.scala:98:53] wire [11:0] _decoded_andMatrixOutputs_T_7 = {decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_1_2_1 = &_decoded_andMatrixOutputs_T_7; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_10 = decoded_andMatrixOutputs_1_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_8 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_6 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_6_7 = decoded_plaInput_1[28]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_7 = {decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8}; // @[pla.scala:90:45, :91:29, :98:53] wire [3:0] _decoded_andMatrixOutputs_T_8 = {decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_3_2_1 = &_decoded_andMatrixOutputs_T_8; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_6 = decoded_andMatrixOutputs_3_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_7_6 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire decoded_andMatrixOutputs_andMatrixInput_7_7 = decoded_plaInput_1[29]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_6 = {decoded_andMatrixOutputs_andMatrixInput_8_6, decoded_andMatrixOutputs_andMatrixInput_9_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_5_6, decoded_andMatrixOutputs_andMatrixInput_6_6}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_6 = {decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_7_6}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_8 = {decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_6 = {decoded_andMatrixOutputs_andMatrixInput_3_8, decoded_andMatrixOutputs_andMatrixInput_4_6}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_6 = {decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9}; // @[pla.scala:91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_6 = {decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_8}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_8 = {decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_9 = {decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_0_2_1 = &_decoded_andMatrixOutputs_T_9; // @[pla.scala:98:{53,70}] wire decoded_andMatrixOutputs_andMatrixInput_0_10 = decoded_plaInput_1[22]; // @[pla.scala:77:22, :90:45] wire [1:0] decoded_andMatrixOutputs_lo_lo_7 = {decoded_andMatrixOutputs_andMatrixInput_8_7, decoded_andMatrixOutputs_andMatrixInput_9_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_lo_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_andMatrixOutputs_andMatrixInput_6_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_lo_hi_7 = {decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_7_7}; // @[pla.scala:90:45, :98:53] wire [4:0] decoded_andMatrixOutputs_lo_9 = {decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7}; // @[pla.scala:98:53] wire [1:0] decoded_andMatrixOutputs_hi_lo_7 = {decoded_andMatrixOutputs_andMatrixInput_3_9, decoded_andMatrixOutputs_andMatrixInput_4_7}; // @[pla.scala:91:29, :98:53] wire [1:0] decoded_andMatrixOutputs_hi_hi_hi_7 = {decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10}; // @[pla.scala:90:45, :91:29, :98:53] wire [2:0] decoded_andMatrixOutputs_hi_hi_7 = {decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_9}; // @[pla.scala:91:29, :98:53] wire [4:0] decoded_andMatrixOutputs_hi_9 = {decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7}; // @[pla.scala:98:53] wire [9:0] _decoded_andMatrixOutputs_T_10 = {decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9}; // @[pla.scala:98:53] wire decoded_andMatrixOutputs_4_2_1 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] wire _decoded_orMatrixOutputs_T_7 = decoded_andMatrixOutputs_4_2_1; // @[pla.scala:98:70, :114:36] wire decoded_andMatrixOutputs_andMatrixInput_0_11 = decoded_plaInput_1[30]; // @[pla.scala:77:22, :90:45] wire [1:0] _decoded_andMatrixOutputs_T_11 = {decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11}; // @[pla.scala:90:45, :91:29, :98:53] wire decoded_andMatrixOutputs_2_2_1 = &_decoded_andMatrixOutputs_T_11; // @[pla.scala:98:{53,70}] wire [1:0] _decoded_orMatrixOutputs_T_8 = {decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_2_2_1}; // @[pla.scala:98:70, :114:19] wire _decoded_orMatrixOutputs_T_9 = |_decoded_orMatrixOutputs_T_8; // @[pla.scala:114:{19,36}] wire [1:0] decoded_orMatrixOutputs_hi_lo_1 = {_decoded_orMatrixOutputs_T_7, _decoded_orMatrixOutputs_T_6}; // @[pla.scala:102:36, :114:36] wire [1:0] decoded_orMatrixOutputs_hi_hi_hi_1 = {_decoded_orMatrixOutputs_T_11, _decoded_orMatrixOutputs_T_10}; // @[pla.scala:102:36, :114:36] wire [2:0] decoded_orMatrixOutputs_hi_hi_1 = {decoded_orMatrixOutputs_hi_hi_hi_1, _decoded_orMatrixOutputs_T_9}; // @[pla.scala:102:36, :114:36] wire [4:0] decoded_orMatrixOutputs_hi_1 = {decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1}; // @[pla.scala:102:36] wire [8:0] decoded_orMatrixOutputs_1 = {decoded_orMatrixOutputs_hi_1, 4'h0}; // @[pla.scala:102:36] wire _decoded_invMatrixOutputs_T_9 = decoded_orMatrixOutputs_1[0]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_10 = decoded_orMatrixOutputs_1[1]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_11 = decoded_orMatrixOutputs_1[2]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_12 = decoded_orMatrixOutputs_1[3]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_13 = decoded_orMatrixOutputs_1[4]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_14 = decoded_orMatrixOutputs_1[5]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_15 = decoded_orMatrixOutputs_1[6]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_16 = decoded_orMatrixOutputs_1[7]; // @[pla.scala:102:36, :124:31] wire _decoded_invMatrixOutputs_T_17 = decoded_orMatrixOutputs_1[8]; // @[pla.scala:102:36, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_lo_1 = {_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_lo_hi_1 = {_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11}; // @[pla.scala:120:37, :124:31] wire [3:0] decoded_invMatrixOutputs_lo_1 = {decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1}; // @[pla.scala:120:37] wire [1:0] decoded_invMatrixOutputs_hi_lo_1 = {_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13}; // @[pla.scala:120:37, :124:31] wire [1:0] decoded_invMatrixOutputs_hi_hi_hi_1 = {_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16}; // @[pla.scala:120:37, :124:31] wire [2:0] decoded_invMatrixOutputs_hi_hi_1 = {decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_15}; // @[pla.scala:120:37, :124:31] wire [4:0] decoded_invMatrixOutputs_hi_1 = {decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1}; // @[pla.scala:120:37] assign decoded_invMatrixOutputs_1 = {decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1}; // @[pla.scala:120:37] assign decoded_1 = decoded_invMatrixOutputs_1; // @[pla.scala:81:23, :120:37] wire is_break = decoded_1[7]; // @[pla.scala:81:23] wire is_ret = decoded_1[6]; // @[pla.scala:81:23] wire is_wfi = decoded_1[4]; // @[pla.scala:81:23] wire is_sfence = decoded_1[3]; // @[pla.scala:81:23] wire is_hfence_vvma = decoded_1[2]; // @[pla.scala:81:23] wire is_hfence_gvma = decoded_1[1]; // @[pla.scala:81:23] wire is_hlsv = decoded_1[0]; // @[pla.scala:81:23] wire _is_counter_T = addr > 12'hBFF; // @[package.scala:213:47] wire _is_counter_T_1 = addr < 12'hC20; // @[package.scala:213:60] wire _is_counter_T_2 = _is_counter_T & _is_counter_T_1; // @[package.scala:213:{47,55,60}] wire _is_counter_T_3 = addr > 12'hC7F; // @[package.scala:213:47] wire _is_counter_T_4 = addr < 12'hCA0; // @[package.scala:213:60] wire _is_counter_T_5 = _is_counter_T_3 & _is_counter_T_4; // @[package.scala:213:{47,55,60}] wire is_counter = _is_counter_T_2 | _is_counter_T_5; // @[package.scala:213:55] wire _allow_wfi_T_3 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94] wire _allow_hfence_vvma_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :908:53] wire _allow_hfence_vvma_T_2 = _allow_hfence_vvma_T; // @[CSR.scala:908:{53,68}] wire _allow_hlsv_T = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :909:46] wire _allow_hlsv_T_3 = _allow_hlsv_T; // @[CSR.scala:909:{46,61}] wire [4:0] counter_addr = addr[4:0]; // @[CSR.scala:897:27, :911:28] wire [31:0] _GEN_3 = 32'h0 >> counter_addr; // @[CSR.scala:911:28, :912:70] wire [31:0] _allow_counter_T_1; // @[CSR.scala:912:70] assign _allow_counter_T_1 = _GEN_3; // @[CSR.scala:912:70] wire [31:0] _allow_counter_T_7; // @[CSR.scala:913:75] assign _allow_counter_T_7 = _GEN_3; // @[CSR.scala:912:70, :913:75] wire [31:0] _allow_counter_T_14; // @[CSR.scala:914:63] assign _allow_counter_T_14 = _GEN_3; // @[CSR.scala:912:70, :914:63] wire [31:0] _io_decode_0_virtual_access_illegal_T_3; // @[CSR.scala:945:36] assign _io_decode_0_virtual_access_illegal_T_3 = _GEN_3; // @[CSR.scala:912:70, :945:36] wire [31:0] _io_decode_0_virtual_access_illegal_T_6; // @[CSR.scala:945:71] assign _io_decode_0_virtual_access_illegal_T_6 = _GEN_3; // @[CSR.scala:912:70, :945:71] wire [31:0] _io_decode_0_virtual_access_illegal_T_11; // @[CSR.scala:945:128] assign _io_decode_0_virtual_access_illegal_T_11 = _GEN_3; // @[CSR.scala:912:70, :945:128] wire _allow_counter_T_2 = _allow_counter_T_1[0]; // @[CSR.scala:912:70] wire _allow_counter_T_8 = _allow_counter_T_7[0]; // @[CSR.scala:913:75] wire _allow_counter_T_12 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :914:30] wire _allow_counter_T_15 = _allow_counter_T_14[0]; // @[CSR.scala:914:63] wire _io_decode_0_fp_illegal_T_2 = reg_mstatus_v & _io_decode_0_fp_illegal_T_1; // @[CSR.scala:395:28, :915:{64,83}] wire _io_decode_0_fp_illegal_T_4 = reg_misa[5]; // @[CSR.scala:648:25, :915:103] wire _io_decode_0_fp_illegal_T_5 = ~_io_decode_0_fp_illegal_T_4; // @[CSR.scala:915:{94,103}] wire _io_decode_0_vector_illegal_T_2 = reg_mstatus_v & _io_decode_0_vector_illegal_T_1; // @[CSR.scala:395:28, :916:{68,87}] wire _io_decode_0_vector_illegal_T_4 = reg_misa[21]; // @[CSR.scala:648:25, :916:107] wire _io_decode_0_vector_illegal_T_5 = ~_io_decode_0_vector_illegal_T_4; // @[CSR.scala:916:{98,107}] wire [11:0] io_decode_0_fp_csr_invInputs = ~io_decode_0_fp_csr_plaInput; // @[pla.scala:77:22, :78:21] wire [11:0] io_decode_0_vector_csr_invInputs = ~io_decode_0_vector_csr_plaInput; // @[pla.scala:77:22, :78:21] wire _io_decode_0_rocc_illegal_T_4 = reg_misa[23]; // @[CSR.scala:648:25, :919:105] wire _io_decode_0_rocc_illegal_T_5 = ~_io_decode_0_rocc_illegal_T_4; // @[CSR.scala:919:{96,105}] wire [1:0] _csr_addr_legal_T = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _csr_addr_legal_T_6 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_1 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_access_illegal_T_18 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire [1:0] _io_decode_0_virtual_system_illegal_T_9 = addr[9:8]; // @[CSR.scala:190:36, :897:27] wire csr_addr_legal = _csr_addr_legal_T_1; // @[CSR.scala:920:{42,60}] wire _csr_addr_legal_T_2 = ~reg_mstatus_v; // @[CSR.scala:395:28, :906:94, :921:28] wire _csr_addr_legal_T_7 = _csr_addr_legal_T_6 == 2'h2; // @[CSR.scala:190:36, :921:92] wire _csr_exists_T = addr == 12'h7A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_1 = addr == 12'h7A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_2 = addr == 12'h7A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_3 = addr == 12'h7A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_4 = addr == 12'h301; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_5 = addr == 12'h300; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_6 = addr == 12'h305; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_7 = addr == 12'h344; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_8 = addr == 12'h304; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_9 = addr == 12'h340; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_10 = addr == 12'h341; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_11 = addr == 12'h343; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_12 = addr == 12'h342; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_13 = addr == 12'hF14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_14 = addr == 12'h7B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_15 = addr == 12'h7B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_16 = addr == 12'h7B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_17 = addr == 12'h320; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_18 = addr == 12'hB00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_19 = addr == 12'hB02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_20 = addr == 12'h323; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_21 = addr == 12'hB03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_22 = addr == 12'hC03; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_23 = addr == 12'hB83; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_24 = addr == 12'hC83; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_25 = addr == 12'h324; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_26 = addr == 12'hB04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_27 = addr == 12'hC04; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_28 = addr == 12'hB84; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_29 = addr == 12'hC84; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_30 = addr == 12'h325; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_31 = addr == 12'hB05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_32 = addr == 12'hC05; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_33 = addr == 12'hB85; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_34 = addr == 12'hC85; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_35 = addr == 12'h326; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_36 = addr == 12'hB06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_37 = addr == 12'hC06; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_38 = addr == 12'hB86; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_39 = addr == 12'hC86; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_40 = addr == 12'h327; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_41 = addr == 12'hB07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_42 = addr == 12'hC07; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_43 = addr == 12'hB87; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_44 = addr == 12'hC87; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_45 = addr == 12'h328; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_46 = addr == 12'hB08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_47 = addr == 12'hC08; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_48 = addr == 12'hB88; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_49 = addr == 12'hC88; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_50 = addr == 12'h329; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_51 = addr == 12'hB09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_52 = addr == 12'hC09; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_53 = addr == 12'hB89; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_54 = addr == 12'hC89; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_55 = addr == 12'h32A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_56 = addr == 12'hB0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_57 = addr == 12'hC0A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_58 = addr == 12'hB8A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_59 = addr == 12'hC8A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_60 = addr == 12'h32B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_61 = addr == 12'hB0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_62 = addr == 12'hC0B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_63 = addr == 12'hB8B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_64 = addr == 12'hC8B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_65 = addr == 12'h32C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_66 = addr == 12'hB0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_67 = addr == 12'hC0C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_68 = addr == 12'hB8C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_69 = addr == 12'hC8C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_70 = addr == 12'h32D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_71 = addr == 12'hB0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_72 = addr == 12'hC0D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_73 = addr == 12'hB8D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_74 = addr == 12'hC8D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_75 = addr == 12'h32E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_76 = addr == 12'hB0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_77 = addr == 12'hC0E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_78 = addr == 12'hB8E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_79 = addr == 12'hC8E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_80 = addr == 12'h32F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_81 = addr == 12'hB0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_82 = addr == 12'hC0F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_83 = addr == 12'hB8F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_84 = addr == 12'hC8F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_85 = addr == 12'h330; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_86 = addr == 12'hB10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_87 = addr == 12'hC10; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_88 = addr == 12'hB90; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_89 = addr == 12'hC90; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_90 = addr == 12'h331; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_91 = addr == 12'hB11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_92 = addr == 12'hC11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_93 = addr == 12'hB91; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_94 = addr == 12'hC91; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_95 = addr == 12'h332; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_96 = addr == 12'hB12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_97 = addr == 12'hC12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_98 = addr == 12'hB92; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_99 = addr == 12'hC92; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_100 = addr == 12'h333; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_101 = addr == 12'hB13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_102 = addr == 12'hC13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_103 = addr == 12'hB93; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_104 = addr == 12'hC93; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_105 = addr == 12'h334; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_106 = addr == 12'hB14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_107 = addr == 12'hC14; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_108 = addr == 12'hB94; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_109 = addr == 12'hC94; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_110 = addr == 12'h335; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_111 = addr == 12'hB15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_112 = addr == 12'hC15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_113 = addr == 12'hB95; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_114 = addr == 12'hC95; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_115 = addr == 12'h336; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_116 = addr == 12'hB16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_117 = addr == 12'hC16; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_118 = addr == 12'hB96; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_119 = addr == 12'hC96; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_120 = addr == 12'h337; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_121 = addr == 12'hB17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_122 = addr == 12'hC17; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_123 = addr == 12'hB97; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_124 = addr == 12'hC97; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_125 = addr == 12'h338; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_126 = addr == 12'hB18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_127 = addr == 12'hC18; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_128 = addr == 12'hB98; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_129 = addr == 12'hC98; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_130 = addr == 12'h339; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_131 = addr == 12'hB19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_132 = addr == 12'hC19; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_133 = addr == 12'hB99; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_134 = addr == 12'hC99; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_135 = addr == 12'h33A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_136 = addr == 12'hB1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_137 = addr == 12'hC1A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_138 = addr == 12'hB9A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_139 = addr == 12'hC9A; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_140 = addr == 12'h33B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_141 = addr == 12'hB1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_142 = addr == 12'hC1B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_143 = addr == 12'hB9B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_144 = addr == 12'hC9B; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_145 = addr == 12'h33C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_146 = addr == 12'hB1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_147 = addr == 12'hC1C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_148 = addr == 12'hB9C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_149 = addr == 12'hC9C; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_150 = addr == 12'h33D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_151 = addr == 12'hB1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_152 = addr == 12'hC1D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_153 = addr == 12'hB9D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_154 = addr == 12'hC9D; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_155 = addr == 12'h33E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_156 = addr == 12'hB1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_157 = addr == 12'hC1E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_158 = addr == 12'hB9E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_159 = addr == 12'hC9E; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_160 = addr == 12'h33F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_161 = addr == 12'hB1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_162 = addr == 12'hC1F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_163 = addr == 12'hB9F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_164 = addr == 12'hC9F; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_165 = addr == 12'hC00; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_166 = addr == 12'hC02; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_167 = addr == 12'hB80; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_168 = addr == 12'hB82; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_169 = addr == 12'hC80; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_170 = addr == 12'hC82; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_171 = addr == 12'h3A0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_172 = addr == 12'h3A1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_173 = addr == 12'h3A2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_174 = addr == 12'h3A3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_175 = addr == 12'h3B0; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_176 = addr == 12'h3B1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_177 = addr == 12'h3B2; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_178 = addr == 12'h3B3; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_179 = addr == 12'h3B4; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_180 = addr == 12'h3B5; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_181 = addr == 12'h3B6; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_182 = addr == 12'h3B7; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_183 = addr == 12'h3B8; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_184 = addr == 12'h3B9; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_185 = addr == 12'h3BA; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_186 = addr == 12'h3BB; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_187 = addr == 12'h3BC; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_188 = addr == 12'h3BD; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_189 = addr == 12'h3BE; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_190 = addr == 12'h3BF; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_191 = addr == 12'h7C1; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_192 = addr == 12'hF12; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_193 = addr == 12'hF11; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_194 = addr == 12'hF13; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_195 = addr == 12'hF15; // @[CSR.scala:897:27, :899:93] wire _csr_exists_T_196 = _csr_exists_T | _csr_exists_T_1; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_197 = _csr_exists_T_196 | _csr_exists_T_2; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_198 = _csr_exists_T_197 | _csr_exists_T_3; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_199 = _csr_exists_T_198 | _csr_exists_T_4; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_200 = _csr_exists_T_199 | _csr_exists_T_5; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_201 = _csr_exists_T_200 | _csr_exists_T_6; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_202 = _csr_exists_T_201 | _csr_exists_T_7; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_203 = _csr_exists_T_202 | _csr_exists_T_8; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_204 = _csr_exists_T_203 | _csr_exists_T_9; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_205 = _csr_exists_T_204 | _csr_exists_T_10; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_206 = _csr_exists_T_205 | _csr_exists_T_11; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_207 = _csr_exists_T_206 | _csr_exists_T_12; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_208 = _csr_exists_T_207 | _csr_exists_T_13; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_209 = _csr_exists_T_208 | _csr_exists_T_14; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_210 = _csr_exists_T_209 | _csr_exists_T_15; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_211 = _csr_exists_T_210 | _csr_exists_T_16; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_212 = _csr_exists_T_211 | _csr_exists_T_17; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_213 = _csr_exists_T_212 | _csr_exists_T_18; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_214 = _csr_exists_T_213 | _csr_exists_T_19; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_215 = _csr_exists_T_214 | _csr_exists_T_20; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_216 = _csr_exists_T_215 | _csr_exists_T_21; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_217 = _csr_exists_T_216 | _csr_exists_T_22; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_218 = _csr_exists_T_217 | _csr_exists_T_23; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_219 = _csr_exists_T_218 | _csr_exists_T_24; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_220 = _csr_exists_T_219 | _csr_exists_T_25; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_221 = _csr_exists_T_220 | _csr_exists_T_26; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_222 = _csr_exists_T_221 | _csr_exists_T_27; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_223 = _csr_exists_T_222 | _csr_exists_T_28; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_224 = _csr_exists_T_223 | _csr_exists_T_29; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_225 = _csr_exists_T_224 | _csr_exists_T_30; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_226 = _csr_exists_T_225 | _csr_exists_T_31; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_227 = _csr_exists_T_226 | _csr_exists_T_32; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_228 = _csr_exists_T_227 | _csr_exists_T_33; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_229 = _csr_exists_T_228 | _csr_exists_T_34; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_230 = _csr_exists_T_229 | _csr_exists_T_35; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_231 = _csr_exists_T_230 | _csr_exists_T_36; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_232 = _csr_exists_T_231 | _csr_exists_T_37; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_233 = _csr_exists_T_232 | _csr_exists_T_38; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_234 = _csr_exists_T_233 | _csr_exists_T_39; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_235 = _csr_exists_T_234 | _csr_exists_T_40; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_236 = _csr_exists_T_235 | _csr_exists_T_41; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_237 = _csr_exists_T_236 | _csr_exists_T_42; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_238 = _csr_exists_T_237 | _csr_exists_T_43; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_239 = _csr_exists_T_238 | _csr_exists_T_44; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_240 = _csr_exists_T_239 | _csr_exists_T_45; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_241 = _csr_exists_T_240 | _csr_exists_T_46; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_242 = _csr_exists_T_241 | _csr_exists_T_47; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_243 = _csr_exists_T_242 | _csr_exists_T_48; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_244 = _csr_exists_T_243 | _csr_exists_T_49; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_245 = _csr_exists_T_244 | _csr_exists_T_50; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_246 = _csr_exists_T_245 | _csr_exists_T_51; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_247 = _csr_exists_T_246 | _csr_exists_T_52; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_248 = _csr_exists_T_247 | _csr_exists_T_53; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_249 = _csr_exists_T_248 | _csr_exists_T_54; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_250 = _csr_exists_T_249 | _csr_exists_T_55; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_251 = _csr_exists_T_250 | _csr_exists_T_56; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_252 = _csr_exists_T_251 | _csr_exists_T_57; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_253 = _csr_exists_T_252 | _csr_exists_T_58; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_254 = _csr_exists_T_253 | _csr_exists_T_59; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_255 = _csr_exists_T_254 | _csr_exists_T_60; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_256 = _csr_exists_T_255 | _csr_exists_T_61; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_257 = _csr_exists_T_256 | _csr_exists_T_62; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_258 = _csr_exists_T_257 | _csr_exists_T_63; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_259 = _csr_exists_T_258 | _csr_exists_T_64; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_260 = _csr_exists_T_259 | _csr_exists_T_65; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_261 = _csr_exists_T_260 | _csr_exists_T_66; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_262 = _csr_exists_T_261 | _csr_exists_T_67; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_263 = _csr_exists_T_262 | _csr_exists_T_68; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_264 = _csr_exists_T_263 | _csr_exists_T_69; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_265 = _csr_exists_T_264 | _csr_exists_T_70; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_266 = _csr_exists_T_265 | _csr_exists_T_71; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_267 = _csr_exists_T_266 | _csr_exists_T_72; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_268 = _csr_exists_T_267 | _csr_exists_T_73; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_269 = _csr_exists_T_268 | _csr_exists_T_74; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_270 = _csr_exists_T_269 | _csr_exists_T_75; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_271 = _csr_exists_T_270 | _csr_exists_T_76; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_272 = _csr_exists_T_271 | _csr_exists_T_77; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_273 = _csr_exists_T_272 | _csr_exists_T_78; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_274 = _csr_exists_T_273 | _csr_exists_T_79; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_275 = _csr_exists_T_274 | _csr_exists_T_80; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_276 = _csr_exists_T_275 | _csr_exists_T_81; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_277 = _csr_exists_T_276 | _csr_exists_T_82; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_278 = _csr_exists_T_277 | _csr_exists_T_83; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_279 = _csr_exists_T_278 | _csr_exists_T_84; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_280 = _csr_exists_T_279 | _csr_exists_T_85; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_281 = _csr_exists_T_280 | _csr_exists_T_86; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_282 = _csr_exists_T_281 | _csr_exists_T_87; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_283 = _csr_exists_T_282 | _csr_exists_T_88; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_284 = _csr_exists_T_283 | _csr_exists_T_89; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_285 = _csr_exists_T_284 | _csr_exists_T_90; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_286 = _csr_exists_T_285 | _csr_exists_T_91; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_287 = _csr_exists_T_286 | _csr_exists_T_92; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_288 = _csr_exists_T_287 | _csr_exists_T_93; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_289 = _csr_exists_T_288 | _csr_exists_T_94; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_290 = _csr_exists_T_289 | _csr_exists_T_95; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_291 = _csr_exists_T_290 | _csr_exists_T_96; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_292 = _csr_exists_T_291 | _csr_exists_T_97; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_293 = _csr_exists_T_292 | _csr_exists_T_98; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_294 = _csr_exists_T_293 | _csr_exists_T_99; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_295 = _csr_exists_T_294 | _csr_exists_T_100; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_296 = _csr_exists_T_295 | _csr_exists_T_101; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_297 = _csr_exists_T_296 | _csr_exists_T_102; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_298 = _csr_exists_T_297 | _csr_exists_T_103; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_299 = _csr_exists_T_298 | _csr_exists_T_104; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_300 = _csr_exists_T_299 | _csr_exists_T_105; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_301 = _csr_exists_T_300 | _csr_exists_T_106; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_302 = _csr_exists_T_301 | _csr_exists_T_107; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_303 = _csr_exists_T_302 | _csr_exists_T_108; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_304 = _csr_exists_T_303 | _csr_exists_T_109; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_305 = _csr_exists_T_304 | _csr_exists_T_110; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_306 = _csr_exists_T_305 | _csr_exists_T_111; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_307 = _csr_exists_T_306 | _csr_exists_T_112; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_308 = _csr_exists_T_307 | _csr_exists_T_113; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_309 = _csr_exists_T_308 | _csr_exists_T_114; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_310 = _csr_exists_T_309 | _csr_exists_T_115; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_311 = _csr_exists_T_310 | _csr_exists_T_116; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_312 = _csr_exists_T_311 | _csr_exists_T_117; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_313 = _csr_exists_T_312 | _csr_exists_T_118; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_314 = _csr_exists_T_313 | _csr_exists_T_119; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_315 = _csr_exists_T_314 | _csr_exists_T_120; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_316 = _csr_exists_T_315 | _csr_exists_T_121; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_317 = _csr_exists_T_316 | _csr_exists_T_122; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_318 = _csr_exists_T_317 | _csr_exists_T_123; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_319 = _csr_exists_T_318 | _csr_exists_T_124; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_320 = _csr_exists_T_319 | _csr_exists_T_125; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_321 = _csr_exists_T_320 | _csr_exists_T_126; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_322 = _csr_exists_T_321 | _csr_exists_T_127; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_323 = _csr_exists_T_322 | _csr_exists_T_128; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_324 = _csr_exists_T_323 | _csr_exists_T_129; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_325 = _csr_exists_T_324 | _csr_exists_T_130; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_326 = _csr_exists_T_325 | _csr_exists_T_131; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_327 = _csr_exists_T_326 | _csr_exists_T_132; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_328 = _csr_exists_T_327 | _csr_exists_T_133; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_329 = _csr_exists_T_328 | _csr_exists_T_134; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_330 = _csr_exists_T_329 | _csr_exists_T_135; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_331 = _csr_exists_T_330 | _csr_exists_T_136; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_332 = _csr_exists_T_331 | _csr_exists_T_137; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_333 = _csr_exists_T_332 | _csr_exists_T_138; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_334 = _csr_exists_T_333 | _csr_exists_T_139; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_335 = _csr_exists_T_334 | _csr_exists_T_140; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_336 = _csr_exists_T_335 | _csr_exists_T_141; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_337 = _csr_exists_T_336 | _csr_exists_T_142; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_338 = _csr_exists_T_337 | _csr_exists_T_143; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_339 = _csr_exists_T_338 | _csr_exists_T_144; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_340 = _csr_exists_T_339 | _csr_exists_T_145; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_341 = _csr_exists_T_340 | _csr_exists_T_146; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_342 = _csr_exists_T_341 | _csr_exists_T_147; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_343 = _csr_exists_T_342 | _csr_exists_T_148; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_344 = _csr_exists_T_343 | _csr_exists_T_149; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_345 = _csr_exists_T_344 | _csr_exists_T_150; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_346 = _csr_exists_T_345 | _csr_exists_T_151; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_347 = _csr_exists_T_346 | _csr_exists_T_152; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_348 = _csr_exists_T_347 | _csr_exists_T_153; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_349 = _csr_exists_T_348 | _csr_exists_T_154; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_350 = _csr_exists_T_349 | _csr_exists_T_155; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_351 = _csr_exists_T_350 | _csr_exists_T_156; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_352 = _csr_exists_T_351 | _csr_exists_T_157; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_353 = _csr_exists_T_352 | _csr_exists_T_158; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_354 = _csr_exists_T_353 | _csr_exists_T_159; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_355 = _csr_exists_T_354 | _csr_exists_T_160; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_356 = _csr_exists_T_355 | _csr_exists_T_161; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_357 = _csr_exists_T_356 | _csr_exists_T_162; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_358 = _csr_exists_T_357 | _csr_exists_T_163; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_359 = _csr_exists_T_358 | _csr_exists_T_164; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_360 = _csr_exists_T_359 | _csr_exists_T_165; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_361 = _csr_exists_T_360 | _csr_exists_T_166; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_362 = _csr_exists_T_361 | _csr_exists_T_167; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_363 = _csr_exists_T_362 | _csr_exists_T_168; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_364 = _csr_exists_T_363 | _csr_exists_T_169; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_365 = _csr_exists_T_364 | _csr_exists_T_170; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_366 = _csr_exists_T_365 | _csr_exists_T_171; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_367 = _csr_exists_T_366 | _csr_exists_T_172; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_368 = _csr_exists_T_367 | _csr_exists_T_173; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_369 = _csr_exists_T_368 | _csr_exists_T_174; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_370 = _csr_exists_T_369 | _csr_exists_T_175; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_371 = _csr_exists_T_370 | _csr_exists_T_176; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_372 = _csr_exists_T_371 | _csr_exists_T_177; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_373 = _csr_exists_T_372 | _csr_exists_T_178; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_374 = _csr_exists_T_373 | _csr_exists_T_179; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_375 = _csr_exists_T_374 | _csr_exists_T_180; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_376 = _csr_exists_T_375 | _csr_exists_T_181; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_377 = _csr_exists_T_376 | _csr_exists_T_182; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_378 = _csr_exists_T_377 | _csr_exists_T_183; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_379 = _csr_exists_T_378 | _csr_exists_T_184; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_380 = _csr_exists_T_379 | _csr_exists_T_185; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_381 = _csr_exists_T_380 | _csr_exists_T_186; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_382 = _csr_exists_T_381 | _csr_exists_T_187; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_383 = _csr_exists_T_382 | _csr_exists_T_188; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_384 = _csr_exists_T_383 | _csr_exists_T_189; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_385 = _csr_exists_T_384 | _csr_exists_T_190; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_386 = _csr_exists_T_385 | _csr_exists_T_191; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_387 = _csr_exists_T_386 | _csr_exists_T_192; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_388 = _csr_exists_T_387 | _csr_exists_T_193; // @[CSR.scala:899:{93,111}] wire _csr_exists_T_389 = _csr_exists_T_388 | _csr_exists_T_194; // @[CSR.scala:899:{93,111}] wire csr_exists = _csr_exists_T_389 | _csr_exists_T_195; // @[CSR.scala:899:{93,111}] wire _io_decode_0_read_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28] wire _io_decode_0_read_illegal_T_1 = ~csr_exists; // @[CSR.scala:899:111, :924:7] wire _io_decode_0_read_illegal_T_2 = _io_decode_0_read_illegal_T | _io_decode_0_read_illegal_T_1; // @[CSR.scala:923:{28,44}, :924:7] wire _io_decode_0_read_illegal_T_8 = _io_decode_0_read_illegal_T_2; // @[CSR.scala:923:44, :924:19] wire _GEN_4 = addr == 12'h180; // @[CSR.scala:897:27, :925:14] wire _io_decode_0_read_illegal_T_3; // @[CSR.scala:925:14] assign _io_decode_0_read_illegal_T_3 = _GEN_4; // @[CSR.scala:925:14] wire _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:12] assign _io_decode_0_virtual_access_illegal_T_24 = _GEN_4; // @[CSR.scala:925:14, :947:12] wire _io_decode_0_read_illegal_T_4 = addr == 12'h680; // @[CSR.scala:897:27, :925:38] wire _io_decode_0_read_illegal_T_5 = _io_decode_0_read_illegal_T_3 | _io_decode_0_read_illegal_T_4; // @[CSR.scala:925:{14,30,38}] wire _io_decode_0_read_illegal_T_11 = _io_decode_0_read_illegal_T_8; // @[CSR.scala:924:19, :925:78] wire [11:0] io_decode_0_read_illegal_invInputs = ~io_decode_0_read_illegal_plaInput; // @[pla.scala:77:22, :78:21] wire io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:124:31] wire io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire _io_decode_0_read_illegal_T_12 = io_decode_0_read_illegal_plaOutput; // @[pla.scala:81:23] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0 = io_decode_0_read_illegal_plaInput[4]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1 = io_decode_0_read_illegal_plaInput[5]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2 = io_decode_0_read_illegal_invInputs[6]; // @[pla.scala:78:21, :91:29] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3 = io_decode_0_read_illegal_plaInput[7]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4 = io_decode_0_read_illegal_plaInput[8]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5 = io_decode_0_read_illegal_plaInput[9]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6 = io_decode_0_read_illegal_plaInput[10]; // @[pla.scala:77:22, :90:45] wire io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7 = io_decode_0_read_illegal_invInputs[11]; // @[pla.scala:78:21, :91:29] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_6, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_7}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_lo_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_4, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_5}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_lo = {io_decode_0_read_illegal_andMatrixOutputs_lo_hi, io_decode_0_read_illegal_andMatrixOutputs_lo_lo}; // @[pla.scala:98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_lo = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_2, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_3}; // @[pla.scala:90:45, :91:29, :98:53] wire [1:0] io_decode_0_read_illegal_andMatrixOutputs_hi_hi = {io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_0, io_decode_0_read_illegal_andMatrixOutputs_andMatrixInput_1}; // @[pla.scala:90:45, :98:53] wire [3:0] io_decode_0_read_illegal_andMatrixOutputs_hi = {io_decode_0_read_illegal_andMatrixOutputs_hi_hi, io_decode_0_read_illegal_andMatrixOutputs_hi_lo}; // @[pla.scala:98:53] wire [7:0] _io_decode_0_read_illegal_andMatrixOutputs_T = {io_decode_0_read_illegal_andMatrixOutputs_hi, io_decode_0_read_illegal_andMatrixOutputs_lo}; // @[pla.scala:98:53] wire io_decode_0_read_illegal_andMatrixOutputs_0_2 = &_io_decode_0_read_illegal_andMatrixOutputs_T; // @[pla.scala:98:{53,70}] wire io_decode_0_read_illegal_orMatrixOutputs = io_decode_0_read_illegal_andMatrixOutputs_0_2; // @[pla.scala:98:70, :114:36] assign io_decode_0_read_illegal_invMatrixOutputs = io_decode_0_read_illegal_orMatrixOutputs; // @[pla.scala:114:36, :124:31] assign io_decode_0_read_illegal_plaOutput = io_decode_0_read_illegal_invMatrixOutputs; // @[pla.scala:81:23, :124:31] wire _io_decode_0_read_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45] wire _io_decode_0_read_illegal_T_14 = _io_decode_0_read_illegal_T_12 & _io_decode_0_read_illegal_T_13; // @[Decode.scala:55:116] wire _io_decode_0_read_illegal_T_15 = _io_decode_0_read_illegal_T_11 | _io_decode_0_read_illegal_T_14; // @[CSR.scala:925:78, :926:36, :927:42] wire _io_decode_0_read_illegal_T_18 = _io_decode_0_read_illegal_T_15; // @[CSR.scala:926:36, :927:56] wire [11:0] io_decode_0_read_illegal_invInputs_1 = ~io_decode_0_read_illegal_plaInput_1; // @[pla.scala:77:22, :78:21] assign _io_decode_0_read_illegal_T_20 = _io_decode_0_read_illegal_T_18; // @[CSR.scala:927:56, :928:68] assign io_decode_0_read_illegal_0 = _io_decode_0_read_illegal_T_20; // @[CSR.scala:377:7, :928:68] wire [1:0] _io_decode_0_write_illegal_T = addr[11:10]; // @[CSR.scala:897:27, :930:33] assign _io_decode_0_write_illegal_T_1 = &_io_decode_0_write_illegal_T; // @[CSR.scala:930:{33,41}] assign io_decode_0_write_illegal_0 = _io_decode_0_write_illegal_T_1; // @[CSR.scala:377:7, :930:41] wire [11:0] io_decode_0_write_flush_addr_m = {_io_decode_0_write_illegal_T, addr[9:0] | 10'h300}; // @[CSR.scala:897:27, :930:33, :932:25] wire _io_decode_0_write_flush_T = io_decode_0_write_flush_addr_m > 12'h33F; // @[CSR.scala:932:25, :933:16] wire _io_decode_0_write_flush_T_1 = io_decode_0_write_flush_addr_m < 12'h344; // @[CSR.scala:932:25, :933:45] wire _io_decode_0_write_flush_T_2 = _io_decode_0_write_flush_T & _io_decode_0_write_flush_T_1; // @[CSR.scala:933:{16,35,45}] assign _io_decode_0_write_flush_T_3 = ~_io_decode_0_write_flush_T_2; // @[CSR.scala:933:{7,35}] assign io_decode_0_write_flush_0 = _io_decode_0_write_flush_T_3; // @[CSR.scala:377:7, :933:7] wire _io_decode_0_system_illegal_T = ~csr_addr_legal; // @[CSR.scala:920:60, :923:28, :935:30] wire _io_decode_0_system_illegal_T_1 = ~is_hlsv; // @[CSR.scala:903:82, :935:49] wire _io_decode_0_system_illegal_T_2 = _io_decode_0_system_illegal_T & _io_decode_0_system_illegal_T_1; // @[CSR.scala:935:{30,46,49}] wire _io_decode_0_system_illegal_T_5 = _io_decode_0_system_illegal_T_2; // @[CSR.scala:935:{46,58}] wire _io_decode_0_system_illegal_T_8 = _io_decode_0_system_illegal_T_5; // @[CSR.scala:935:58, :936:28] wire _io_decode_0_system_illegal_T_9 = addr[10]; // @[CSR.scala:897:27, :938:21] wire _io_decode_0_system_illegal_T_10 = is_ret & _io_decode_0_system_illegal_T_9; // @[CSR.scala:903:82, :938:{14,21}] wire _io_decode_0_system_illegal_T_11 = addr[7]; // @[CSR.scala:897:27, :938:33] wire _io_decode_0_system_illegal_T_12 = _io_decode_0_system_illegal_T_10 & _io_decode_0_system_illegal_T_11; // @[CSR.scala:938:{14,26,33}] wire _io_decode_0_system_illegal_T_13 = ~reg_debug; // @[CSR.scala:482:26, :927:45, :938:40] wire _io_decode_0_system_illegal_T_14 = _io_decode_0_system_illegal_T_12 & _io_decode_0_system_illegal_T_13; // @[CSR.scala:938:{26,37,40}] wire _io_decode_0_system_illegal_T_15 = _io_decode_0_system_illegal_T_8 | _io_decode_0_system_illegal_T_14; // @[CSR.scala:936:28, :937:29, :938:37] wire _io_decode_0_system_illegal_T_19 = _io_decode_0_system_illegal_T_15; // @[CSR.scala:937:29, :938:51] wire _io_decode_0_system_illegal_T_16 = is_sfence | is_hfence_gvma; // @[CSR.scala:903:82, :939:18] wire _io_decode_0_system_illegal_T_22 = _io_decode_0_system_illegal_T_19; // @[CSR.scala:938:51, :939:58] assign _io_decode_0_system_illegal_T_25 = _io_decode_0_system_illegal_T_22; // @[CSR.scala:939:58, :940:44] assign io_decode_0_system_illegal_0 = _io_decode_0_system_illegal_T_25; // @[CSR.scala:377:7, :940:44] wire _io_decode_0_virtual_access_illegal_T = reg_mstatus_v & csr_exists; // @[CSR.scala:395:28, :899:111, :943:52] wire _io_decode_0_virtual_access_illegal_T_2 = _io_decode_0_virtual_access_illegal_T_1 == 2'h2; // @[CSR.scala:190:36, :944:22] wire _io_decode_0_virtual_access_illegal_T_4 = _io_decode_0_virtual_access_illegal_T_3[0]; // @[CSR.scala:945:36] wire _io_decode_0_virtual_access_illegal_T_5 = is_counter & _io_decode_0_virtual_access_illegal_T_4; // @[CSR.scala:904:81, :945:{18,36}] wire _io_decode_0_virtual_access_illegal_T_7 = _io_decode_0_virtual_access_illegal_T_6[0]; // @[CSR.scala:945:71] wire _io_decode_0_virtual_access_illegal_T_8 = ~_io_decode_0_virtual_access_illegal_T_7; // @[CSR.scala:945:{55,71}] wire _io_decode_0_virtual_access_illegal_T_15 = _io_decode_0_virtual_access_illegal_T_8; // @[CSR.scala:945:{55,86}] wire _io_decode_0_virtual_access_illegal_T_12 = _io_decode_0_virtual_access_illegal_T_11[0]; // @[CSR.scala:945:128] wire _io_decode_0_virtual_access_illegal_T_13 = ~_io_decode_0_virtual_access_illegal_T_12; // @[CSR.scala:945:{112,128}] wire _io_decode_0_virtual_access_illegal_T_16 = _io_decode_0_virtual_access_illegal_T_5 & _io_decode_0_virtual_access_illegal_T_15; // @[CSR.scala:945:{18,51,86}] wire _io_decode_0_virtual_access_illegal_T_17 = _io_decode_0_virtual_access_illegal_T_2 | _io_decode_0_virtual_access_illegal_T_16; // @[CSR.scala:944:{22,34}, :945:51] wire _io_decode_0_virtual_access_illegal_T_23 = _io_decode_0_virtual_access_illegal_T_17; // @[CSR.scala:944:34, :945:144] wire _io_decode_0_virtual_access_illegal_T_19 = _io_decode_0_virtual_access_illegal_T_18 == 2'h1; // @[CSR.scala:190:36, :946:22] wire _io_decode_0_virtual_access_illegal_T_28 = _io_decode_0_virtual_access_illegal_T_23; // @[CSR.scala:945:144, :946:57] wire _io_decode_0_virtual_access_illegal_T_26 = _io_decode_0_virtual_access_illegal_T_24; // @[CSR.scala:947:{12,28}] assign _io_decode_0_virtual_access_illegal_T_29 = _io_decode_0_virtual_access_illegal_T & _io_decode_0_virtual_access_illegal_T_28; // @[CSR.scala:943:{52,66}, :946:57] assign io_decode_0_virtual_access_illegal_0 = _io_decode_0_virtual_access_illegal_T_29; // @[CSR.scala:377:7, :943:66] wire _io_decode_0_virtual_system_illegal_T = is_hfence_vvma | is_hfence_gvma; // @[CSR.scala:903:82, :950:22] wire _io_decode_0_virtual_system_illegal_T_1 = _io_decode_0_virtual_system_illegal_T | is_hlsv; // @[CSR.scala:903:82, :950:22, :951:22] wire _io_decode_0_virtual_system_illegal_T_8 = _io_decode_0_virtual_system_illegal_T_1; // @[CSR.scala:951:22, :952:15] wire _io_decode_0_virtual_system_illegal_T_16 = _io_decode_0_virtual_system_illegal_T_8; // @[CSR.scala:952:15, :953:77] wire _io_decode_0_virtual_system_illegal_T_10 = _io_decode_0_virtual_system_illegal_T_9 == 2'h1; // @[CSR.scala:190:36, :954:32] wire _io_decode_0_virtual_system_illegal_T_11 = is_ret & _io_decode_0_virtual_system_illegal_T_10; // @[CSR.scala:903:82, :954:{14,32}] wire _io_decode_0_virtual_system_illegal_T_21 = _io_decode_0_virtual_system_illegal_T_16; // @[CSR.scala:953:77, :954:89] assign _io_decode_0_virtual_system_illegal_T_22 = reg_mstatus_v & _io_decode_0_virtual_system_illegal_T_21; // @[CSR.scala:395:28, :949:52, :954:89] assign io_decode_0_virtual_system_illegal_0 = _io_decode_0_virtual_system_illegal_T_22; // @[CSR.scala:377:7, :949:52] wire [1:0] _cause_T_2 = {1'h1, ~_cause_T_1}; // @[CSR.scala:959:{45,65}] wire [4:0] _cause_T_3 = {3'h0, _cause_T_2} + 5'h8; // @[CSR.scala:959:{40,45}] wire [3:0] _cause_T_4 = _cause_T_3[3:0]; // @[CSR.scala:959:40] wire [31:0] _cause_T_5 = insn_break ? 32'h3 : io_cause_0; // @[CSR.scala:377:7, :893:83, :960:14] assign cause = insn_call ? {28'h0, _cause_T_4} : _cause_T_5; // @[CSR.scala:893:83, :959:{8,40}, :960:14] assign io_trace_0_cause_0 = cause; // @[CSR.scala:377:7, :959:8] wire [7:0] cause_lsbs = cause[7:0]; // @[CSR.scala:959:8, :961:25] wire [4:0] cause_deleg_lsbs = cause[4:0]; // @[CSR.scala:959:8, :962:31] wire [4:0] _notDebugTVec_interruptOffset_T = cause[4:0]; // @[CSR.scala:959:8, :962:31, :979:32] wire _causeIsDebugInt_T = cause[31]; // @[CSR.scala:959:8, :963:30] wire _causeIsDebugTrigger_T = cause[31]; // @[CSR.scala:959:8, :963:30, :964:35] wire _causeIsDebugBreak_T = cause[31]; // @[CSR.scala:959:8, :963:30, :965:33] wire _delegate_T_2 = cause[31]; // @[CSR.scala:959:8, :963:30, :970:78] wire _delegateVS_T_1 = cause[31]; // @[CSR.scala:959:8, :963:30, :971:58] wire _notDebugTVec_doVector_T_1 = cause[31]; // @[CSR.scala:959:8, :963:30, :981:36] wire _causeIsRnmiInt_T = cause[31]; // @[CSR.scala:959:8, :963:30, :985:29] wire _causeIsRnmiBEU_T = cause[31]; // @[CSR.scala:959:8, :963:30, :986:29] wire _reg_vscause_T = cause[31]; // @[CSR.scala:959:8, :963:30, :1060:31] assign _io_trace_0_interrupt_T = cause[31]; // @[CSR.scala:959:8, :963:30, :1626:25] wire _GEN_5 = cause_lsbs == 8'hE; // @[CSR.scala:961:25, :963:53] wire _causeIsDebugInt_T_1; // @[CSR.scala:963:53] assign _causeIsDebugInt_T_1 = _GEN_5; // @[CSR.scala:963:53] wire _causeIsDebugTrigger_T_2; // @[CSR.scala:964:58] assign _causeIsDebugTrigger_T_2 = _GEN_5; // @[CSR.scala:963:53, :964:58] wire causeIsDebugInt = _causeIsDebugInt_T & _causeIsDebugInt_T_1; // @[CSR.scala:963:{30,39,53}] wire _causeIsDebugTrigger_T_1 = ~_causeIsDebugTrigger_T; // @[CSR.scala:964:{29,35}] wire causeIsDebugTrigger = _causeIsDebugTrigger_T_1 & _causeIsDebugTrigger_T_2; // @[CSR.scala:964:{29,44,58}] wire _causeIsDebugBreak_T_1 = ~_causeIsDebugBreak_T; // @[CSR.scala:965:{27,33}] wire _causeIsDebugBreak_T_2 = _causeIsDebugBreak_T_1 & insn_break; // @[CSR.scala:893:83, :965:{27,42}] wire [1:0] causeIsDebugBreak_hi = {reg_dcsr_ebreakm, 1'h0}; // @[CSR.scala:403:25, :965:62] wire [3:0] _causeIsDebugBreak_T_3 = {causeIsDebugBreak_hi, 2'h0}; // @[CSR.scala:965:62] wire [3:0] _causeIsDebugBreak_T_4 = {3'h0, _causeIsDebugBreak_T_3[3]}; // @[CSR.scala:965:{62,134}] wire _causeIsDebugBreak_T_5 = _causeIsDebugBreak_T_4[0]; // @[CSR.scala:965:134] wire causeIsDebugBreak = _causeIsDebugBreak_T_2 & _causeIsDebugBreak_T_5; // @[CSR.scala:965:{42,56,134}] wire _trapToDebug_T = reg_singleStepped | causeIsDebugInt; // @[CSR.scala:486:30, :963:39, :966:56] wire _trapToDebug_T_1 = _trapToDebug_T | causeIsDebugTrigger; // @[CSR.scala:964:44, :966:{56,75}] wire _trapToDebug_T_2 = _trapToDebug_T_1 | causeIsDebugBreak; // @[CSR.scala:965:56, :966:{75,98}] wire _trapToDebug_T_3 = _trapToDebug_T_2 | reg_debug; // @[CSR.scala:482:26, :966:{98,119}] wire trapToDebug = _trapToDebug_T_3; // @[CSR.scala:966:{34,119}] wire [11:0] _debugTVec_T = {8'h80, ~insn_break, 3'h0}; // @[CSR.scala:893:83, :969:37] wire [11:0] debugTVec = reg_debug ? _debugTVec_T : 12'h800; // @[CSR.scala:482:26, :969:{22,37}] wire [31:0] _GEN_6 = 32'h0 >> cause_deleg_lsbs; // @[CSR.scala:962:31, :970:100] wire [31:0] _delegate_T_3; // @[CSR.scala:970:100] assign _delegate_T_3 = _GEN_6; // @[CSR.scala:970:100] wire [31:0] _delegate_T_5; // @[CSR.scala:970:132] assign _delegate_T_5 = _GEN_6; // @[CSR.scala:970:{100,132}] wire [31:0] _delegateVS_T_2; // @[CSR.scala:971:80] assign _delegateVS_T_2 = _GEN_6; // @[CSR.scala:970:100, :971:80] wire [31:0] _delegateVS_T_4; // @[CSR.scala:971:112] assign _delegateVS_T_4 = _GEN_6; // @[CSR.scala:970:100, :971:112] wire _delegate_T_4 = _delegate_T_3[0]; // @[CSR.scala:970:100] wire _delegate_T_6 = _delegate_T_5[0]; // @[CSR.scala:970:132] wire _delegate_T_7 = _delegate_T_2 ? _delegate_T_4 : _delegate_T_6; // @[CSR.scala:970:{72,78,100,132}] wire _delegateVS_T_3 = _delegateVS_T_2[0]; // @[CSR.scala:971:80] wire _delegateVS_T_5 = _delegateVS_T_4[0]; // @[CSR.scala:971:112] wire _delegateVS_T_6 = _delegateVS_T_1 ? _delegateVS_T_3 : _delegateVS_T_5; // @[CSR.scala:971:{52,58,80,112}] wire [6:0] notDebugTVec_interruptOffset = {_notDebugTVec_interruptOffset_T, 2'h0}; // @[CSR.scala:979:{32,59}] wire [24:0] _notDebugTVec_interruptVec_T = notDebugTVec_base[31:7]; // @[CSR.scala:978:19, :980:33] wire [31:0] notDebugTVec_interruptVec = {_notDebugTVec_interruptVec_T, notDebugTVec_interruptOffset}; // @[CSR.scala:979:59, :980:{27,33}] wire _notDebugTVec_doVector_T = notDebugTVec_base[0]; // @[CSR.scala:978:19, :981:24] wire _notDebugTVec_doVector_T_2 = _notDebugTVec_doVector_T & _notDebugTVec_doVector_T_1; // @[CSR.scala:981:{24,28,36}] wire [2:0] _notDebugTVec_doVector_T_3 = cause_lsbs[7:5]; // @[CSR.scala:961:25, :981:70] wire _notDebugTVec_doVector_T_4 = _notDebugTVec_doVector_T_3 == 3'h0; // @[CSR.scala:981:{70,94}] wire notDebugTVec_doVector = _notDebugTVec_doVector_T_2 & _notDebugTVec_doVector_T_4; // @[CSR.scala:981:{28,55,94}] wire [29:0] _notDebugTVec_T = notDebugTVec_base[31:2]; // @[CSR.scala:978:19, :982:38] wire [31:0] _notDebugTVec_T_1 = {_notDebugTVec_T, 2'h0}; // @[CSR.scala:982:{38,56}] wire [31:0] notDebugTVec = notDebugTVec_doVector ? notDebugTVec_interruptVec : _notDebugTVec_T_1; // @[CSR.scala:980:27, :981:55, :982:{8,56}] wire [31:0] _tvec_T = notDebugTVec; // @[CSR.scala:982:8, :995:45] wire _causeIsRnmiInt_T_1 = cause[30]; // @[CSR.scala:959:8, :985:46] wire _causeIsRnmiBEU_T_1 = cause[30]; // @[CSR.scala:959:8, :985:46, :986:46] wire _causeIsRnmiInt_T_2 = _causeIsRnmiInt_T & _causeIsRnmiInt_T_1; // @[CSR.scala:985:{29,38,46}] wire _causeIsRnmiInt_T_3 = cause_lsbs == 8'hD; // @[CSR.scala:961:25, :985:70] wire _GEN_7 = cause_lsbs == 8'hC; // @[CSR.scala:961:25, :985:107] wire _causeIsRnmiInt_T_4; // @[CSR.scala:985:107] assign _causeIsRnmiInt_T_4 = _GEN_7; // @[CSR.scala:985:107] wire _causeIsRnmiBEU_T_3; // @[CSR.scala:986:69] assign _causeIsRnmiBEU_T_3 = _GEN_7; // @[CSR.scala:985:107, :986:69] wire _causeIsRnmiInt_T_5 = _causeIsRnmiInt_T_3 | _causeIsRnmiInt_T_4; // @[CSR.scala:985:{70,93,107}] wire causeIsRnmiInt = _causeIsRnmiInt_T_2 & _causeIsRnmiInt_T_5; // @[CSR.scala:985:{38,55,93}] wire _causeIsRnmiBEU_T_2 = _causeIsRnmiBEU_T & _causeIsRnmiBEU_T_1; // @[CSR.scala:986:{29,38,46}] wire causeIsRnmiBEU = _causeIsRnmiBEU_T_2 & _causeIsRnmiBEU_T_3; // @[CSR.scala:986:{38,55,69}] wire [31:0] tvec = trapToDebug ? {20'h0, debugTVec} : _tvec_T; // @[CSR.scala:966:34, :969:22, :995:{17,45}] wire _GEN_8 = insn_call | insn_break; // @[CSR.scala:893:83, :1000:24] wire _io_eret_T; // @[CSR.scala:1000:24] assign _io_eret_T = _GEN_8; // @[CSR.scala:1000:24] wire _exception_T; // @[CSR.scala:1020:29] assign _exception_T = _GEN_8; // @[CSR.scala:1000:24, :1020:29] assign _io_eret_T_1 = _io_eret_T | insn_ret; // @[CSR.scala:893:83, :1000:{24,38}] assign io_eret_0 = _io_eret_T_1; // @[CSR.scala:377:7, :1000:38] wire _io_singleStep_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1001:37] assign _io_singleStep_T_1 = reg_dcsr_step & _io_singleStep_T; // @[CSR.scala:403:25, :1001:{34,37}] assign io_singleStep_0 = _io_singleStep_T_1; // @[CSR.scala:377:7, :1001:34] wire _io_status_dprv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1008:45] wire _io_status_dv_T = ~reg_debug; // @[CSR.scala:482:26, :927:45, :1009:60] assign io_status_dv_0 = _io_status_dv_T_3; // @[CSR.scala:377:7, :1009:33] wire _io_gstatus_sd_T = &io_gstatus_fs_0; // @[CSR.scala:377:7, :1016:34] wire _io_gstatus_sd_T_2 = _io_gstatus_sd_T; // @[CSR.scala:1016:{34,39}] wire _io_gstatus_sd_T_3 = &io_gstatus_vs_0; // @[CSR.scala:377:7, :1016:78] assign _io_gstatus_sd_T_4 = _io_gstatus_sd_T_2 | _io_gstatus_sd_T_3; // @[CSR.scala:1016:{39,61,78}] assign io_gstatus_sd_0 = _io_gstatus_sd_T_4; // @[CSR.scala:377:7, :1016:61] assign io_gstatus_sd_rv32_0 = _io_gstatus_sd_rv32_T; // @[CSR.scala:377:7, :1018:40] wire exception = _exception_T | io_exception_0; // @[CSR.scala:377:7, :1020:{29,43}] wire _en_T_20 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_44 = exception; // @[CSR.scala:1020:43, :1096:24] wire _en_T_68 = exception; // @[CSR.scala:1020:43, :1096:24] assign _io_trace_0_exception_T_1 = exception; // @[CSR.scala:1020:43, :1620:37]
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_322 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_322( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11_1 : output io : { flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<9>, sig : UInt<65>}, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<17>, exceptionFlags : UInt<5>} node roundingMode_near_even = eq(io.roundingMode, UInt<3>(0h0)) node roundingMode_minMag = eq(io.roundingMode, UInt<3>(0h1)) node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node roundingMode_max = eq(io.roundingMode, UInt<3>(0h3)) node roundingMode_near_maxMag = eq(io.roundingMode, UInt<3>(0h4)) node roundingMode_odd = eq(io.roundingMode, UInt<3>(0h6)) node _roundMagUp_T = and(roundingMode_min, io.in.sign) node _roundMagUp_T_1 = eq(io.in.sign, UInt<1>(0h0)) node _roundMagUp_T_2 = and(roundingMode_max, _roundMagUp_T_1) node roundMagUp = or(_roundMagUp_T, _roundMagUp_T_2) node sAdjustedExp = add(io.in.sExp, asSInt(UInt<8>(0ha0))) node _adjustedSig_T = bits(io.in.sig, 64, 52) node _adjustedSig_T_1 = bits(io.in.sig, 51, 0) node _adjustedSig_T_2 = orr(_adjustedSig_T_1) node adjustedSig = cat(_adjustedSig_T, _adjustedSig_T_2) wire common_expOut : UInt<6> wire common_fractOut : UInt<10> wire common_overflow : UInt<1> wire common_totalUnderflow : UInt<1> wire common_underflow : UInt<1> wire common_inexact : UInt<1> node _roundMask_T = cat(UInt<11>(0h0), UInt<1>(0h0)) node roundMask = cat(_roundMask_T, UInt<2>(0h3)) node _shiftedRoundMask_T = cat(UInt<1>(0h0), roundMask) node shiftedRoundMask = shr(_shiftedRoundMask_T, 1) node _roundPosMask_T = not(shiftedRoundMask) node roundPosMask = and(_roundPosMask_T, roundMask) node _roundPosBit_T = and(adjustedSig, roundPosMask) node roundPosBit = orr(_roundPosBit_T) node _anyRoundExtra_T = and(adjustedSig, shiftedRoundMask) node anyRoundExtra = orr(_anyRoundExtra_T) node anyRound = or(roundPosBit, anyRoundExtra) node _roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _roundIncr_T_1 = and(_roundIncr_T, roundPosBit) node _roundIncr_T_2 = and(roundMagUp, anyRound) node roundIncr = or(_roundIncr_T_1, _roundIncr_T_2) node _roundedSig_T = or(adjustedSig, roundMask) node _roundedSig_T_1 = shr(_roundedSig_T, 2) node _roundedSig_T_2 = add(_roundedSig_T_1, UInt<1>(0h1)) node _roundedSig_T_3 = and(roundingMode_near_even, roundPosBit) node _roundedSig_T_4 = eq(anyRoundExtra, UInt<1>(0h0)) node _roundedSig_T_5 = and(_roundedSig_T_3, _roundedSig_T_4) node _roundedSig_T_6 = shr(roundMask, 1) node _roundedSig_T_7 = mux(_roundedSig_T_5, _roundedSig_T_6, UInt<13>(0h0)) node _roundedSig_T_8 = not(_roundedSig_T_7) node _roundedSig_T_9 = and(_roundedSig_T_2, _roundedSig_T_8) node _roundedSig_T_10 = not(roundMask) node _roundedSig_T_11 = and(adjustedSig, _roundedSig_T_10) node _roundedSig_T_12 = shr(_roundedSig_T_11, 2) node _roundedSig_T_13 = and(roundingMode_odd, anyRound) node _roundedSig_T_14 = shr(roundPosMask, 1) node _roundedSig_T_15 = mux(_roundedSig_T_13, _roundedSig_T_14, UInt<1>(0h0)) node _roundedSig_T_16 = or(_roundedSig_T_12, _roundedSig_T_15) node roundedSig = mux(roundIncr, _roundedSig_T_9, _roundedSig_T_16) node _sRoundedExp_T = shr(roundedSig, 11) node _sRoundedExp_T_1 = cvt(_sRoundedExp_T) node sRoundedExp = add(sAdjustedExp, _sRoundedExp_T_1) node _common_expOut_T = bits(sRoundedExp, 5, 0) connect common_expOut, _common_expOut_T node _common_fractOut_T = bits(roundedSig, 10, 1) node _common_fractOut_T_1 = bits(roundedSig, 9, 0) node _common_fractOut_T_2 = mux(UInt<1>(0h0), _common_fractOut_T, _common_fractOut_T_1) connect common_fractOut, _common_fractOut_T_2 node _common_overflow_T = shr(sRoundedExp, 4) node _common_overflow_T_1 = geq(_common_overflow_T, asSInt(UInt<3>(0h3))) connect common_overflow, _common_overflow_T_1 connect common_totalUnderflow, UInt<1>(0h0) node _unboundedRange_roundPosBit_T = bits(adjustedSig, 2, 2) node _unboundedRange_roundPosBit_T_1 = bits(adjustedSig, 1, 1) node unboundedRange_roundPosBit = mux(UInt<1>(0h0), _unboundedRange_roundPosBit_T, _unboundedRange_roundPosBit_T_1) node _unboundedRange_anyRound_T = bits(adjustedSig, 2, 2) node _unboundedRange_anyRound_T_1 = and(UInt<1>(0h0), _unboundedRange_anyRound_T) node _unboundedRange_anyRound_T_2 = bits(adjustedSig, 1, 0) node _unboundedRange_anyRound_T_3 = orr(_unboundedRange_anyRound_T_2) node unboundedRange_anyRound = or(_unboundedRange_anyRound_T_1, _unboundedRange_anyRound_T_3) node _unboundedRange_roundIncr_T = or(roundingMode_near_even, roundingMode_near_maxMag) node _unboundedRange_roundIncr_T_1 = and(_unboundedRange_roundIncr_T, unboundedRange_roundPosBit) node _unboundedRange_roundIncr_T_2 = and(roundMagUp, unboundedRange_anyRound) node unboundedRange_roundIncr = or(_unboundedRange_roundIncr_T_1, _unboundedRange_roundIncr_T_2) node _roundCarry_T = bits(roundedSig, 12, 12) node _roundCarry_T_1 = bits(roundedSig, 11, 11) node roundCarry = mux(UInt<1>(0h0), _roundCarry_T, _roundCarry_T_1) connect common_underflow, UInt<1>(0h0) node _common_inexact_T = or(common_totalUnderflow, anyRound) connect common_inexact, _common_inexact_T node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) node _commonCase_T = eq(isNaNOut, UInt<1>(0h0)) node _commonCase_T_1 = eq(notNaN_isSpecialInfOut, UInt<1>(0h0)) node _commonCase_T_2 = and(_commonCase_T, _commonCase_T_1) node _commonCase_T_3 = eq(io.in.isZero, UInt<1>(0h0)) node commonCase = and(_commonCase_T_2, _commonCase_T_3) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) node _inexact_T = and(commonCase, common_inexact) node inexact = or(overflow, _inexact_T) node _overflow_roundMagUp_T = or(roundingMode_near_even, roundingMode_near_maxMag) node overflow_roundMagUp = or(_overflow_roundMagUp_T, roundMagUp) node _pegMinNonzeroMagOut_T = and(commonCase, common_totalUnderflow) node _pegMinNonzeroMagOut_T_1 = or(roundMagUp, roundingMode_odd) node pegMinNonzeroMagOut = and(_pegMinNonzeroMagOut_T, _pegMinNonzeroMagOut_T_1) node _pegMaxFiniteMagOut_T = eq(overflow_roundMagUp, UInt<1>(0h0)) node pegMaxFiniteMagOut = and(overflow, _pegMaxFiniteMagOut_T) node _notNaN_isInfOut_T = and(overflow, overflow_roundMagUp) node notNaN_isInfOut = or(notNaN_isSpecialInfOut, _notNaN_isInfOut_T) node signOut = mux(isNaNOut, UInt<1>(0h0), io.in.sign) node _expOut_T = or(io.in.isZero, common_totalUnderflow) node _expOut_T_1 = mux(_expOut_T, UInt<6>(0h38), UInt<1>(0h0)) node _expOut_T_2 = not(_expOut_T_1) node _expOut_T_3 = and(common_expOut, _expOut_T_2) node _expOut_T_4 = not(UInt<6>(0h8)) node _expOut_T_5 = mux(pegMinNonzeroMagOut, _expOut_T_4, UInt<1>(0h0)) node _expOut_T_6 = not(_expOut_T_5) node _expOut_T_7 = and(_expOut_T_3, _expOut_T_6) node _expOut_T_8 = mux(pegMaxFiniteMagOut, UInt<6>(0h10), UInt<1>(0h0)) node _expOut_T_9 = not(_expOut_T_8) node _expOut_T_10 = and(_expOut_T_7, _expOut_T_9) node _expOut_T_11 = mux(notNaN_isInfOut, UInt<6>(0h8), UInt<1>(0h0)) node _expOut_T_12 = not(_expOut_T_11) node _expOut_T_13 = and(_expOut_T_10, _expOut_T_12) node _expOut_T_14 = mux(pegMinNonzeroMagOut, UInt<6>(0h8), UInt<1>(0h0)) node _expOut_T_15 = or(_expOut_T_13, _expOut_T_14) node _expOut_T_16 = mux(pegMaxFiniteMagOut, UInt<6>(0h2f), UInt<1>(0h0)) node _expOut_T_17 = or(_expOut_T_15, _expOut_T_16) node _expOut_T_18 = mux(notNaN_isInfOut, UInt<6>(0h30), UInt<1>(0h0)) node _expOut_T_19 = or(_expOut_T_17, _expOut_T_18) node _expOut_T_20 = mux(isNaNOut, UInt<6>(0h38), UInt<1>(0h0)) node expOut = or(_expOut_T_19, _expOut_T_20) node _fractOut_T = or(isNaNOut, io.in.isZero) node _fractOut_T_1 = or(_fractOut_T, common_totalUnderflow) node _fractOut_T_2 = mux(isNaNOut, UInt<10>(0h200), UInt<1>(0h0)) node _fractOut_T_3 = mux(_fractOut_T_1, _fractOut_T_2, common_fractOut) node _fractOut_T_4 = mux(pegMaxFiniteMagOut, UInt<10>(0h3ff), UInt<10>(0h0)) node fractOut = or(_fractOut_T_3, _fractOut_T_4) node _io_out_T = cat(signOut, expOut) node _io_out_T_1 = cat(_io_out_T, fractOut) connect io.out, _io_out_T_1 node _io_exceptionFlags_T = cat(io.invalidExc, io.infiniteExc) node _io_exceptionFlags_T_1 = cat(_io_exceptionFlags_T, overflow) node _io_exceptionFlags_T_2 = cat(_io_exceptionFlags_T_1, underflow) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, inexact) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RoundAnyRawFNToRecFN_ie7_is64_oe5_os11_1( // @[RoundAnyRawFNToRecFN.scala:48:5] input io_in_isZero, // @[RoundAnyRawFNToRecFN.scala:58:16] input io_in_sign, // @[RoundAnyRawFNToRecFN.scala:58:16] input [8:0] io_in_sExp, // @[RoundAnyRawFNToRecFN.scala:58:16] input [64:0] io_in_sig, // @[RoundAnyRawFNToRecFN.scala:58:16] input [2:0] io_roundingMode, // @[RoundAnyRawFNToRecFN.scala:58:16] output [16:0] io_out, // @[RoundAnyRawFNToRecFN.scala:58:16] output [4:0] io_exceptionFlags // @[RoundAnyRawFNToRecFN.scala:58:16] ); wire io_in_isZero_0 = io_in_isZero; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_sign_0 = io_in_sign; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [8:0] io_in_sExp_0 = io_in_sExp; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [64:0] io_in_sig_0 = io_in_sig; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [2:0] io_roundingMode_0 = io_roundingMode; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [11:0] _roundMask_T = 12'h0; // @[RoundAnyRawFNToRecFN.scala:153:36] wire [5:0] _expOut_T_4 = 6'h37; // @[RoundAnyRawFNToRecFN.scala:258:19] wire [13:0] roundMask = 14'h3; // @[RoundAnyRawFNToRecFN.scala:153:55] wire [14:0] _shiftedRoundMask_T = 15'h3; // @[RoundAnyRawFNToRecFN.scala:162:41] wire [13:0] shiftedRoundMask = 14'h1; // @[RoundAnyRawFNToRecFN.scala:162:53] wire [13:0] _roundPosMask_T = 14'h3FFE; // @[RoundAnyRawFNToRecFN.scala:163:28] wire [13:0] roundPosMask = 14'h2; // @[RoundAnyRawFNToRecFN.scala:163:46] wire [13:0] _roundedSig_T_10 = 14'h3FFC; // @[RoundAnyRawFNToRecFN.scala:180:32] wire [12:0] _roundedSig_T_6 = 13'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [12:0] _roundedSig_T_14 = 13'h1; // @[RoundAnyRawFNToRecFN.scala:177:35, :181:67] wire [5:0] _expOut_T_6 = 6'h3F; // @[RoundAnyRawFNToRecFN.scala:257:14] wire [5:0] _expOut_T_5 = 6'h0; // @[RoundAnyRawFNToRecFN.scala:257:18] wire [5:0] _expOut_T_14 = 6'h0; // @[RoundAnyRawFNToRecFN.scala:269:16] wire [5:0] _expOut_T_20 = 6'h0; // @[RoundAnyRawFNToRecFN.scala:278:16] wire [9:0] _fractOut_T_2 = 10'h0; // @[RoundAnyRawFNToRecFN.scala:281:16] wire [1:0] _io_exceptionFlags_T = 2'h0; // @[RoundAnyRawFNToRecFN.scala:288:23] wire io_detectTininess = 1'h1; // @[RoundAnyRawFNToRecFN.scala:48:5] wire _commonCase_T = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:22] wire _commonCase_T_1 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:36] wire _commonCase_T_2 = 1'h1; // @[RoundAnyRawFNToRecFN.scala:237:33] wire io_invalidExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_infiniteExc = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isNaN = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire io_in_isInf = 1'h0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire common_totalUnderflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:125:37] wire common_underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:126:37] wire _unboundedRange_anyRound_T_1 = 1'h0; // @[RoundAnyRawFNToRecFN.scala:205:30] wire isNaNOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:235:34] wire notNaN_isSpecialInfOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:236:49] wire underflow = 1'h0; // @[RoundAnyRawFNToRecFN.scala:239:32] wire _pegMinNonzeroMagOut_T = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:20] wire pegMinNonzeroMagOut = 1'h0; // @[RoundAnyRawFNToRecFN.scala:245:45] wire _expOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :253:32] wire _fractOut_T = io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :280:22] wire signOut = io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :250:22] wire [16:0] _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:286:33] wire [4:0] _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:288:66] wire [16:0] io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire [4:0] io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] wire roundingMode_near_even = io_roundingMode_0 == 3'h0; // @[RoundAnyRawFNToRecFN.scala:48:5, :90:53] wire roundingMode_minMag = io_roundingMode_0 == 3'h1; // @[RoundAnyRawFNToRecFN.scala:48:5, :91:53] wire roundingMode_min = io_roundingMode_0 == 3'h2; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53] wire roundingMode_max = io_roundingMode_0 == 3'h3; // @[RoundAnyRawFNToRecFN.scala:48:5, :93:53] wire roundingMode_near_maxMag = io_roundingMode_0 == 3'h4; // @[RoundAnyRawFNToRecFN.scala:48:5, :94:53] wire roundingMode_odd = io_roundingMode_0 == 3'h6; // @[RoundAnyRawFNToRecFN.scala:48:5, :95:53] wire _roundMagUp_T = roundingMode_min & io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :92:53, :98:27] wire _roundMagUp_T_1 = ~io_in_sign_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :98:66] wire _roundMagUp_T_2 = roundingMode_max & _roundMagUp_T_1; // @[RoundAnyRawFNToRecFN.scala:93:53, :98:{63,66}] wire roundMagUp = _roundMagUp_T | _roundMagUp_T_2; // @[RoundAnyRawFNToRecFN.scala:98:{27,42,63}] wire [9:0] sAdjustedExp = {io_in_sExp_0[8], io_in_sExp_0} - 10'h60; // @[RoundAnyRawFNToRecFN.scala:48:5, :110:24] wire [12:0] _adjustedSig_T = io_in_sig_0[64:52]; // @[RoundAnyRawFNToRecFN.scala:48:5, :116:23] wire [51:0] _adjustedSig_T_1 = io_in_sig_0[51:0]; // @[RoundAnyRawFNToRecFN.scala:48:5, :117:26] wire _adjustedSig_T_2 = |_adjustedSig_T_1; // @[RoundAnyRawFNToRecFN.scala:117:{26,60}] wire [13:0] adjustedSig = {_adjustedSig_T, _adjustedSig_T_2}; // @[RoundAnyRawFNToRecFN.scala:116:{23,66}, :117:60] wire [5:0] _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:187:37] wire [5:0] common_expOut; // @[RoundAnyRawFNToRecFN.scala:122:31] wire [9:0] _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:189:16] wire [9:0] common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31] wire _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:196:50] wire common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37] wire _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:230:49] wire common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37] wire [13:0] _roundPosBit_T = adjustedSig & 14'h2; // @[RoundAnyRawFNToRecFN.scala:116:66, :163:46, :164:40] wire roundPosBit = |_roundPosBit_T; // @[RoundAnyRawFNToRecFN.scala:164:{40,56}] wire [13:0] _anyRoundExtra_T = adjustedSig & 14'h1; // @[RoundAnyRawFNToRecFN.scala:116:66, :162:53, :165:42] wire anyRoundExtra = |_anyRoundExtra_T; // @[RoundAnyRawFNToRecFN.scala:165:{42,62}] wire anyRound = roundPosBit | anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:164:56, :165:62, :166:36] assign _common_inexact_T = anyRound; // @[RoundAnyRawFNToRecFN.scala:166:36, :230:49] wire _GEN = roundingMode_near_even | roundingMode_near_maxMag; // @[RoundAnyRawFNToRecFN.scala:90:53, :94:53, :169:38] wire _roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:169:38] assign _roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38] wire _unboundedRange_roundIncr_T; // @[RoundAnyRawFNToRecFN.scala:207:38] assign _unboundedRange_roundIncr_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :207:38] wire _overflow_roundMagUp_T; // @[RoundAnyRawFNToRecFN.scala:243:32] assign _overflow_roundMagUp_T = _GEN; // @[RoundAnyRawFNToRecFN.scala:169:38, :243:32] wire _roundIncr_T_1 = _roundIncr_T & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:164:56, :169:{38,67}] wire _roundIncr_T_2 = roundMagUp & anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :166:36, :171:29] wire roundIncr = _roundIncr_T_1 | _roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:169:67, :170:31, :171:29] wire [13:0] _roundedSig_T = adjustedSig | 14'h3; // @[RoundAnyRawFNToRecFN.scala:116:66, :153:55, :174:32] wire [11:0] _roundedSig_T_1 = _roundedSig_T[13:2]; // @[RoundAnyRawFNToRecFN.scala:174:{32,44}] wire [12:0] _roundedSig_T_2 = {1'h0, _roundedSig_T_1} + 13'h1; // @[RoundAnyRawFNToRecFN.scala:174:{44,49}, :177:35, :181:67] wire _roundedSig_T_3 = roundingMode_near_even & roundPosBit; // @[RoundAnyRawFNToRecFN.scala:90:53, :164:56, :175:49] wire _roundedSig_T_4 = ~anyRoundExtra; // @[RoundAnyRawFNToRecFN.scala:165:62, :176:30] wire _roundedSig_T_5 = _roundedSig_T_3 & _roundedSig_T_4; // @[RoundAnyRawFNToRecFN.scala:175:{49,64}, :176:30] wire [12:0] _roundedSig_T_7 = {12'h0, _roundedSig_T_5}; // @[RoundAnyRawFNToRecFN.scala:175:{25,64}] wire [12:0] _roundedSig_T_8 = ~_roundedSig_T_7; // @[RoundAnyRawFNToRecFN.scala:175:{21,25}] wire [12:0] _roundedSig_T_9 = _roundedSig_T_2 & _roundedSig_T_8; // @[RoundAnyRawFNToRecFN.scala:174:{49,57}, :175:21] wire [13:0] _roundedSig_T_11 = adjustedSig & 14'h3FFC; // @[RoundAnyRawFNToRecFN.scala:116:66, :180:{30,32}] wire [11:0] _roundedSig_T_12 = _roundedSig_T_11[13:2]; // @[RoundAnyRawFNToRecFN.scala:180:{30,43}] wire _roundedSig_T_13 = roundingMode_odd & anyRound; // @[RoundAnyRawFNToRecFN.scala:95:53, :166:36, :181:42] wire [12:0] _roundedSig_T_15 = {12'h0, _roundedSig_T_13}; // @[RoundAnyRawFNToRecFN.scala:181:{24,42}] wire [12:0] _roundedSig_T_16 = {1'h0, _roundedSig_T_12} | _roundedSig_T_15; // @[RoundAnyRawFNToRecFN.scala:180:{43,47}, :181:24] wire [12:0] roundedSig = roundIncr ? _roundedSig_T_9 : _roundedSig_T_16; // @[RoundAnyRawFNToRecFN.scala:170:31, :173:16, :174:57, :180:47] wire [1:0] _sRoundedExp_T = roundedSig[12:11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :185:54] wire [2:0] _sRoundedExp_T_1 = {1'h0, _sRoundedExp_T}; // @[RoundAnyRawFNToRecFN.scala:185:{54,76}] wire [10:0] sRoundedExp = {sAdjustedExp[9], sAdjustedExp} + {{8{_sRoundedExp_T_1[2]}}, _sRoundedExp_T_1}; // @[RoundAnyRawFNToRecFN.scala:110:24, :185:{40,76}] assign _common_expOut_T = sRoundedExp[5:0]; // @[RoundAnyRawFNToRecFN.scala:185:40, :187:37] assign common_expOut = _common_expOut_T; // @[RoundAnyRawFNToRecFN.scala:122:31, :187:37] wire [9:0] _common_fractOut_T = roundedSig[10:1]; // @[RoundAnyRawFNToRecFN.scala:173:16, :190:27] wire [9:0] _common_fractOut_T_1 = roundedSig[9:0]; // @[RoundAnyRawFNToRecFN.scala:173:16, :191:27] assign _common_fractOut_T_2 = _common_fractOut_T_1; // @[RoundAnyRawFNToRecFN.scala:189:16, :191:27] assign common_fractOut = _common_fractOut_T_2; // @[RoundAnyRawFNToRecFN.scala:123:31, :189:16] wire [6:0] _common_overflow_T = sRoundedExp[10:4]; // @[RoundAnyRawFNToRecFN.scala:185:40, :196:30] assign _common_overflow_T_1 = $signed(_common_overflow_T) > 7'sh2; // @[RoundAnyRawFNToRecFN.scala:196:{30,50}] assign common_overflow = _common_overflow_T_1; // @[RoundAnyRawFNToRecFN.scala:124:37, :196:50] wire _unboundedRange_roundPosBit_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45] wire _unboundedRange_anyRound_T = adjustedSig[2]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:45, :205:44] wire _unboundedRange_roundPosBit_T_1 = adjustedSig[1]; // @[RoundAnyRawFNToRecFN.scala:116:66, :203:61] wire unboundedRange_roundPosBit = _unboundedRange_roundPosBit_T_1; // @[RoundAnyRawFNToRecFN.scala:203:{16,61}] wire [1:0] _unboundedRange_anyRound_T_2 = adjustedSig[1:0]; // @[RoundAnyRawFNToRecFN.scala:116:66, :205:63] wire _unboundedRange_anyRound_T_3 = |_unboundedRange_anyRound_T_2; // @[RoundAnyRawFNToRecFN.scala:205:{63,70}] wire unboundedRange_anyRound = _unboundedRange_anyRound_T_3; // @[RoundAnyRawFNToRecFN.scala:205:{49,70}] wire _unboundedRange_roundIncr_T_1 = _unboundedRange_roundIncr_T & unboundedRange_roundPosBit; // @[RoundAnyRawFNToRecFN.scala:203:16, :207:{38,67}] wire _unboundedRange_roundIncr_T_2 = roundMagUp & unboundedRange_anyRound; // @[RoundAnyRawFNToRecFN.scala:98:42, :205:49, :209:29] wire unboundedRange_roundIncr = _unboundedRange_roundIncr_T_1 | _unboundedRange_roundIncr_T_2; // @[RoundAnyRawFNToRecFN.scala:207:67, :208:46, :209:29] wire _roundCarry_T = roundedSig[12]; // @[RoundAnyRawFNToRecFN.scala:173:16, :212:27] wire _roundCarry_T_1 = roundedSig[11]; // @[RoundAnyRawFNToRecFN.scala:173:16, :213:27] wire roundCarry = _roundCarry_T_1; // @[RoundAnyRawFNToRecFN.scala:211:16, :213:27] assign common_inexact = _common_inexact_T; // @[RoundAnyRawFNToRecFN.scala:127:37, :230:49] wire _commonCase_T_3 = ~io_in_isZero_0; // @[RoundAnyRawFNToRecFN.scala:48:5, :237:64] wire commonCase = _commonCase_T_3; // @[RoundAnyRawFNToRecFN.scala:237:{61,64}] wire overflow = commonCase & common_overflow; // @[RoundAnyRawFNToRecFN.scala:124:37, :237:61, :238:32] wire _inexact_T = commonCase & common_inexact; // @[RoundAnyRawFNToRecFN.scala:127:37, :237:61, :240:43] wire inexact = overflow | _inexact_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :240:{28,43}] wire overflow_roundMagUp = _overflow_roundMagUp_T | roundMagUp; // @[RoundAnyRawFNToRecFN.scala:98:42, :243:{32,60}] wire _pegMinNonzeroMagOut_T_1 = roundMagUp | roundingMode_odd; // @[RoundAnyRawFNToRecFN.scala:95:53, :98:42, :245:60] wire _pegMaxFiniteMagOut_T = ~overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:243:60, :246:42] wire pegMaxFiniteMagOut = overflow & _pegMaxFiniteMagOut_T; // @[RoundAnyRawFNToRecFN.scala:238:32, :246:{39,42}] wire _notNaN_isInfOut_T = overflow & overflow_roundMagUp; // @[RoundAnyRawFNToRecFN.scala:238:32, :243:60, :248:45] wire notNaN_isInfOut = _notNaN_isInfOut_T; // @[RoundAnyRawFNToRecFN.scala:248:{32,45}] wire [5:0] _expOut_T_1 = _expOut_T ? 6'h38 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:253:{18,32}] wire [5:0] _expOut_T_2 = ~_expOut_T_1; // @[RoundAnyRawFNToRecFN.scala:253:{14,18}] wire [5:0] _expOut_T_3 = common_expOut & _expOut_T_2; // @[RoundAnyRawFNToRecFN.scala:122:31, :252:24, :253:14] wire [5:0] _expOut_T_7 = _expOut_T_3; // @[RoundAnyRawFNToRecFN.scala:252:24, :256:17] wire [5:0] _expOut_T_8 = {1'h0, pegMaxFiniteMagOut, 4'h0}; // @[RoundAnyRawFNToRecFN.scala:246:39, :261:18] wire [5:0] _expOut_T_9 = ~_expOut_T_8; // @[RoundAnyRawFNToRecFN.scala:261:{14,18}] wire [5:0] _expOut_T_10 = _expOut_T_7 & _expOut_T_9; // @[RoundAnyRawFNToRecFN.scala:256:17, :260:17, :261:14] wire [5:0] _expOut_T_11 = {2'h0, notNaN_isInfOut, 3'h0}; // @[RoundAnyRawFNToRecFN.scala:248:32, :265:18] wire [5:0] _expOut_T_12 = ~_expOut_T_11; // @[RoundAnyRawFNToRecFN.scala:265:{14,18}] wire [5:0] _expOut_T_13 = _expOut_T_10 & _expOut_T_12; // @[RoundAnyRawFNToRecFN.scala:260:17, :264:17, :265:14] wire [5:0] _expOut_T_15 = _expOut_T_13; // @[RoundAnyRawFNToRecFN.scala:264:17, :268:18] wire [5:0] _expOut_T_16 = pegMaxFiniteMagOut ? 6'h2F : 6'h0; // @[RoundAnyRawFNToRecFN.scala:246:39, :273:16] wire [5:0] _expOut_T_17 = _expOut_T_15 | _expOut_T_16; // @[RoundAnyRawFNToRecFN.scala:268:18, :272:15, :273:16] wire [5:0] _expOut_T_18 = notNaN_isInfOut ? 6'h30 : 6'h0; // @[RoundAnyRawFNToRecFN.scala:248:32, :277:16] wire [5:0] _expOut_T_19 = _expOut_T_17 | _expOut_T_18; // @[RoundAnyRawFNToRecFN.scala:272:15, :276:15, :277:16] wire [5:0] expOut = _expOut_T_19; // @[RoundAnyRawFNToRecFN.scala:276:15, :277:73] wire _fractOut_T_1 = _fractOut_T; // @[RoundAnyRawFNToRecFN.scala:280:{22,38}] wire [9:0] _fractOut_T_3 = _fractOut_T_1 ? 10'h0 : common_fractOut; // @[RoundAnyRawFNToRecFN.scala:123:31, :280:{12,38}] wire [9:0] _fractOut_T_4 = {10{pegMaxFiniteMagOut}}; // @[RoundAnyRawFNToRecFN.scala:246:39, :284:13] wire [9:0] fractOut = _fractOut_T_3 | _fractOut_T_4; // @[RoundAnyRawFNToRecFN.scala:280:12, :283:11, :284:13] wire [6:0] _io_out_T = {signOut, expOut}; // @[RoundAnyRawFNToRecFN.scala:250:22, :277:73, :286:23] assign _io_out_T_1 = {_io_out_T, fractOut}; // @[RoundAnyRawFNToRecFN.scala:283:11, :286:{23,33}] assign io_out_0 = _io_out_T_1; // @[RoundAnyRawFNToRecFN.scala:48:5, :286:33] wire [2:0] _io_exceptionFlags_T_1 = {2'h0, overflow}; // @[RoundAnyRawFNToRecFN.scala:238:32, :288:41] wire [3:0] _io_exceptionFlags_T_2 = {_io_exceptionFlags_T_1, 1'h0}; // @[RoundAnyRawFNToRecFN.scala:288:{41,53}] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, inexact}; // @[RoundAnyRawFNToRecFN.scala:240:28, :288:{53,66}] assign io_exceptionFlags_0 = _io_exceptionFlags_T_3; // @[RoundAnyRawFNToRecFN.scala:48:5, :288:66] assign io_out = io_out_0; // @[RoundAnyRawFNToRecFN.scala:48:5] assign io_exceptionFlags = io_exceptionFlags_0; // @[RoundAnyRawFNToRecFN.scala:48:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_351 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_95 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_351( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_95 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Pipeline_14 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, a_addr : UInt, b_addr : UInt, c_addr : UInt, I : UInt, J : UInt, K : UInt, new_weights : UInt<1>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, a_addr : UInt, b_addr : UInt, c_addr : UInt, I : UInt, J : UInt, K : UInt, new_weights : UInt<1>}}, busy : UInt<1>} reg stages : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, a_addr : UInt, b_addr : UInt, c_addr : UInt, I : UInt, J : UInt, K : UInt, new_weights : UInt<1>}[2], clock wire _valids_WIRE : UInt<1>[2] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) regreset valids : UInt<1>[2], clock, reset, _valids_WIRE wire stalling : UInt<1>[2] connect stalling[0], UInt<1>(0h0) connect stalling[1], UInt<1>(0h0) node _io_busy_T = or(valids[0], valids[1]) node _io_busy_T_1 = or(io.in.valid, _io_busy_T) connect io.busy, _io_busy_T_1 node _io_in_ready_T = eq(stalling[0], UInt<1>(0h0)) connect io.in.ready, _io_in_ready_T node _stalling_1_T = eq(io.out.ready, UInt<1>(0h0)) node _stalling_1_T_1 = and(valids[1], _stalling_1_T) connect stalling[1], _stalling_1_T_1 node _stalling_0_T = and(valids[0], stalling[1]) connect stalling[0], _stalling_0_T connect io.out.valid, valids[1] when io.out.ready : connect valids[1], UInt<1>(0h0) node _T = eq(stalling[1], UInt<1>(0h0)) when _T : connect valids[0], UInt<1>(0h0) node _T_1 = and(io.in.ready, io.in.valid) when _T_1 : connect valids[0], UInt<1>(0h1) when valids[0] : connect valids[1], UInt<1>(0h1) node _T_2 = and(io.in.ready, io.in.valid) when _T_2 : connect stages[0], io.in.bits connect io.out.bits, stages[1] node _T_3 = eq(stalling[1], UInt<1>(0h0)) when _T_3 : connect stages[1], stages[0]
module Pipeline_14( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [6:0] io_in_bits_cmd_inst_funct, // @[Pipeline.scala:7:14] input [63:0] io_in_bits_cmd_rs1, // @[Pipeline.scala:7:14] input [63:0] io_in_bits_cmd_rs2, // @[Pipeline.scala:7:14] input [51:0] io_in_bits_a_addr, // @[Pipeline.scala:7:14] input [67:0] io_in_bits_b_addr, // @[Pipeline.scala:7:14] input [67:0] io_in_bits_c_addr, // @[Pipeline.scala:7:14] input [16:0] io_in_bits_I, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_J, // @[Pipeline.scala:7:14] input [31:0] io_in_bits_K, // @[Pipeline.scala:7:14] input io_in_bits_new_weights, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [6:0] io_out_bits_cmd_inst_funct, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rs2, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rs1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xd, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xs1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xs2, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rd, // @[Pipeline.scala:7:14] output [6:0] io_out_bits_cmd_inst_opcode, // @[Pipeline.scala:7:14] output [63:0] io_out_bits_cmd_rs1, // @[Pipeline.scala:7:14] output [63:0] io_out_bits_cmd_rs2, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_debug, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_cease, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_wfi, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_cmd_status_isa, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_dprv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_dv, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_prv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_v, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sd, // @[Pipeline.scala:7:14] output [22:0] io_out_bits_cmd_status_zero2, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mpv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_gva, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mbe, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sbe, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_sxl, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_uxl, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sd_rv32, // @[Pipeline.scala:7:14] output [7:0] io_out_bits_cmd_status_zero1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tsr, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tw, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tvm, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mxr, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sum, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mprv, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_xs, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_fs, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_mpp, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_vs, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_spp, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mpie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_ube, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_spie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_upie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_hie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_uie, // @[Pipeline.scala:7:14] output [51:0] io_out_bits_a_addr, // @[Pipeline.scala:7:14] output [67:0] io_out_bits_b_addr, // @[Pipeline.scala:7:14] output [67:0] io_out_bits_c_addr, // @[Pipeline.scala:7:14] output [16:0] io_out_bits_I, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_J, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_K, // @[Pipeline.scala:7:14] output io_out_bits_new_weights, // @[Pipeline.scala:7:14] output io_busy // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [6:0] io_in_bits_cmd_inst_funct_0 = io_in_bits_cmd_inst_funct; // @[Pipeline.scala:6:7] wire [63:0] io_in_bits_cmd_rs1_0 = io_in_bits_cmd_rs1; // @[Pipeline.scala:6:7] wire [63:0] io_in_bits_cmd_rs2_0 = io_in_bits_cmd_rs2; // @[Pipeline.scala:6:7] wire [51:0] io_in_bits_a_addr_0 = io_in_bits_a_addr; // @[Pipeline.scala:6:7] wire [67:0] io_in_bits_b_addr_0 = io_in_bits_b_addr; // @[Pipeline.scala:6:7] wire [67:0] io_in_bits_c_addr_0 = io_in_bits_c_addr; // @[Pipeline.scala:6:7] wire [16:0] io_in_bits_I_0 = io_in_bits_I; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_J_0 = io_in_bits_J; // @[Pipeline.scala:6:7] wire [31:0] io_in_bits_K_0 = io_in_bits_K; // @[Pipeline.scala:6:7] wire io_in_bits_new_weights_0 = io_in_bits_new_weights; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire [4:0] io_in_bits_cmd_inst_rs2 = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [4:0] io_in_bits_cmd_inst_rs1 = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [4:0] io_in_bits_cmd_inst_rd = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [6:0] io_in_bits_cmd_inst_opcode = 7'h0; // @[Pipeline.scala:6:7, :7:14] wire [31:0] io_in_bits_cmd_status_isa = 32'h0; // @[Pipeline.scala:6:7, :7:14] wire [22:0] io_in_bits_cmd_status_zero2 = 23'h0; // @[Pipeline.scala:6:7, :7:14] wire [7:0] io_in_bits_cmd_status_zero1 = 8'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_dprv = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_prv = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_sxl = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_uxl = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_xs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_fs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_mpp = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_vs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire io_in_bits_cmd_inst_xd = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_inst_xs1 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_inst_xs2 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_debug = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_cease = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_wfi = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_dv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_v = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sd = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mpv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_gva = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mbe = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sbe = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sd_rv32 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tsr = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tw = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tvm = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mxr = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sum = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mprv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_spp = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mpie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_ube = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_spie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_upie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_hie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_uie = 1'h0; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_1; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [6:0] io_out_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rs2_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rs1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xd_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xs1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xs2_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rd_0; // @[Pipeline.scala:6:7] wire [6:0] io_out_bits_cmd_inst_opcode_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_debug_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_cease_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_wfi_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_cmd_status_isa_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_dprv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_dv_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_prv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_v_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sd_0; // @[Pipeline.scala:6:7] wire [22:0] io_out_bits_cmd_status_zero2_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mpv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_gva_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mbe_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sbe_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_sxl_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_uxl_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sd_rv32_0; // @[Pipeline.scala:6:7] wire [7:0] io_out_bits_cmd_status_zero1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tsr_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tw_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tvm_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mxr_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sum_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mprv_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_xs_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_fs_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_mpp_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_vs_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_spp_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mpie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_ube_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_spie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_upie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_hie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_uie_0; // @[Pipeline.scala:6:7] wire [63:0] io_out_bits_cmd_rs1_0; // @[Pipeline.scala:6:7] wire [63:0] io_out_bits_cmd_rs2_0; // @[Pipeline.scala:6:7] wire [51:0] io_out_bits_a_addr_0; // @[Pipeline.scala:6:7] wire [67:0] io_out_bits_b_addr_0; // @[Pipeline.scala:6:7] wire [67:0] io_out_bits_c_addr_0; // @[Pipeline.scala:6:7] wire [16:0] io_out_bits_I_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_J_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_K_0; // @[Pipeline.scala:6:7] wire io_out_bits_new_weights_0; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy_0; // @[Pipeline.scala:6:7] reg [6:0] stages_0_cmd_inst_funct; // @[Pipeline.scala:21:21] reg [63:0] stages_0_cmd_rs1; // @[Pipeline.scala:21:21] reg [63:0] stages_0_cmd_rs2; // @[Pipeline.scala:21:21] reg [51:0] stages_0_a_addr; // @[Pipeline.scala:21:21] reg [67:0] stages_0_b_addr; // @[Pipeline.scala:21:21] reg [67:0] stages_0_c_addr; // @[Pipeline.scala:21:21] reg [16:0] stages_0_I; // @[Pipeline.scala:21:21] reg [15:0] stages_0_J; // @[Pipeline.scala:21:21] reg [31:0] stages_0_K; // @[Pipeline.scala:21:21] reg stages_0_new_weights; // @[Pipeline.scala:21:21] reg [6:0] stages_1_cmd_inst_funct; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_funct_0 = stages_1_cmd_inst_funct; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rs2_0 = stages_1_cmd_inst_rs2; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rs1_0 = stages_1_cmd_inst_rs1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xd_0 = stages_1_cmd_inst_xd; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xs1_0 = stages_1_cmd_inst_xs1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xs2_0 = stages_1_cmd_inst_xs2; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rd_0 = stages_1_cmd_inst_rd; // @[Pipeline.scala:6:7, :21:21] reg [6:0] stages_1_cmd_inst_opcode; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_opcode_0 = stages_1_cmd_inst_opcode; // @[Pipeline.scala:6:7, :21:21] reg [63:0] stages_1_cmd_rs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_rs1_0 = stages_1_cmd_rs1; // @[Pipeline.scala:6:7, :21:21] reg [63:0] stages_1_cmd_rs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_rs2_0 = stages_1_cmd_rs2; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_debug; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_debug_0 = stages_1_cmd_status_debug; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_cease; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_cease_0 = stages_1_cmd_status_cease; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_wfi; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_wfi_0 = stages_1_cmd_status_wfi; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_1_cmd_status_isa; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_isa_0 = stages_1_cmd_status_isa; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_dprv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_dprv_0 = stages_1_cmd_status_dprv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_dv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_dv_0 = stages_1_cmd_status_dv; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_prv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_prv_0 = stages_1_cmd_status_prv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_v; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_v_0 = stages_1_cmd_status_v; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sd_0 = stages_1_cmd_status_sd; // @[Pipeline.scala:6:7, :21:21] reg [22:0] stages_1_cmd_status_zero2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_zero2_0 = stages_1_cmd_status_zero2; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mpv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpv_0 = stages_1_cmd_status_mpv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_gva; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_gva_0 = stages_1_cmd_status_gva; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mbe; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mbe_0 = stages_1_cmd_status_mbe; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sbe; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sbe_0 = stages_1_cmd_status_sbe; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_sxl; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sxl_0 = stages_1_cmd_status_sxl; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_uxl; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_uxl_0 = stages_1_cmd_status_uxl; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sd_rv32_0 = stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:6:7, :21:21] reg [7:0] stages_1_cmd_status_zero1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_zero1_0 = stages_1_cmd_status_zero1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tsr; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tsr_0 = stages_1_cmd_status_tsr; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tw; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tw_0 = stages_1_cmd_status_tw; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tvm; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tvm_0 = stages_1_cmd_status_tvm; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mxr; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mxr_0 = stages_1_cmd_status_mxr; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sum; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sum_0 = stages_1_cmd_status_sum; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mprv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mprv_0 = stages_1_cmd_status_mprv; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_xs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_xs_0 = stages_1_cmd_status_xs; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_fs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_fs_0 = stages_1_cmd_status_fs; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_mpp; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpp_0 = stages_1_cmd_status_mpp; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_vs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_vs_0 = stages_1_cmd_status_vs; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_spp; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_spp_0 = stages_1_cmd_status_spp; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mpie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpie_0 = stages_1_cmd_status_mpie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_ube; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_ube_0 = stages_1_cmd_status_ube; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_spie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_spie_0 = stages_1_cmd_status_spie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_upie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_upie_0 = stages_1_cmd_status_upie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mie_0 = stages_1_cmd_status_mie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_hie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_hie_0 = stages_1_cmd_status_hie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sie_0 = stages_1_cmd_status_sie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_uie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_uie_0 = stages_1_cmd_status_uie; // @[Pipeline.scala:6:7, :21:21] reg [51:0] stages_1_a_addr; // @[Pipeline.scala:21:21] assign io_out_bits_a_addr_0 = stages_1_a_addr; // @[Pipeline.scala:6:7, :21:21] reg [67:0] stages_1_b_addr; // @[Pipeline.scala:21:21] assign io_out_bits_b_addr_0 = stages_1_b_addr; // @[Pipeline.scala:6:7, :21:21] reg [67:0] stages_1_c_addr; // @[Pipeline.scala:21:21] assign io_out_bits_c_addr_0 = stages_1_c_addr; // @[Pipeline.scala:6:7, :21:21] reg [16:0] stages_1_I; // @[Pipeline.scala:21:21] assign io_out_bits_I_0 = stages_1_I; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_1_J; // @[Pipeline.scala:21:21] assign io_out_bits_J_0 = stages_1_J; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_1_K; // @[Pipeline.scala:21:21] assign io_out_bits_K_0 = stages_1_K; // @[Pipeline.scala:6:7, :21:21] reg stages_1_new_weights; // @[Pipeline.scala:21:21] assign io_out_bits_new_weights_0 = stages_1_new_weights; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_1; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_1 = io_in_valid_0 | _io_busy_T; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy_0 = _io_busy_T_1; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_1_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_1_T_1 = valids_1 & _stalling_1_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_1 = _stalling_1_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] wire _T_2 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_2) begin // @[Decoupled.scala:51:35] stages_0_cmd_inst_funct <= io_in_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7, :21:21] stages_0_cmd_rs1 <= io_in_bits_cmd_rs1_0; // @[Pipeline.scala:6:7, :21:21] stages_0_cmd_rs2 <= io_in_bits_cmd_rs2_0; // @[Pipeline.scala:6:7, :21:21] stages_0_a_addr <= io_in_bits_a_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_b_addr <= io_in_bits_b_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_c_addr <= io_in_bits_c_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_I <= io_in_bits_I_0; // @[Pipeline.scala:6:7, :21:21] stages_0_J <= io_in_bits_J_0; // @[Pipeline.scala:6:7, :21:21] stages_0_K <= io_in_bits_K_0; // @[Pipeline.scala:6:7, :21:21] stages_0_new_weights <= io_in_bits_new_weights_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_cmd_inst_funct <= stages_0_cmd_inst_funct; // @[Pipeline.scala:21:21] stages_1_cmd_inst_rs2 <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_rs1 <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_rd <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_opcode <= 7'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_rs1 <= stages_0_cmd_rs1; // @[Pipeline.scala:21:21] stages_1_cmd_rs2 <= stages_0_cmd_rs2; // @[Pipeline.scala:21:21] stages_1_cmd_status_isa <= 32'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_dprv <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_prv <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_zero2 <= 23'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_sxl <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_uxl <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_zero1 <= 8'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_xs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_fs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_mpp <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_vs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_a_addr <= stages_0_a_addr; // @[Pipeline.scala:21:21] stages_1_b_addr <= stages_0_b_addr; // @[Pipeline.scala:21:21] stages_1_c_addr <= stages_0_c_addr; // @[Pipeline.scala:21:21] stages_1_I <= stages_0_I; // @[Pipeline.scala:21:21] stages_1_J <= stages_0_J; // @[Pipeline.scala:21:21] stages_1_K <= stages_0_K; // @[Pipeline.scala:21:21] stages_1_new_weights <= stages_0_new_weights; // @[Pipeline.scala:21:21] end stages_1_cmd_inst_xd <= stalling_1 & stages_1_cmd_inst_xd; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_inst_xs1 <= stalling_1 & stages_1_cmd_inst_xs1; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_inst_xs2 <= stalling_1 & stages_1_cmd_inst_xs2; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_debug <= stalling_1 & stages_1_cmd_status_debug; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_cease <= stalling_1 & stages_1_cmd_status_cease; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_wfi <= stalling_1 & stages_1_cmd_status_wfi; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_dv <= stalling_1 & stages_1_cmd_status_dv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_v <= stalling_1 & stages_1_cmd_status_v; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sd <= stalling_1 & stages_1_cmd_status_sd; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mpv <= stalling_1 & stages_1_cmd_status_mpv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_gva <= stalling_1 & stages_1_cmd_status_gva; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mbe <= stalling_1 & stages_1_cmd_status_mbe; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sbe <= stalling_1 & stages_1_cmd_status_sbe; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sd_rv32 <= stalling_1 & stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tsr <= stalling_1 & stages_1_cmd_status_tsr; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tw <= stalling_1 & stages_1_cmd_status_tw; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tvm <= stalling_1 & stages_1_cmd_status_tvm; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mxr <= stalling_1 & stages_1_cmd_status_mxr; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sum <= stalling_1 & stages_1_cmd_status_sum; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mprv <= stalling_1 & stages_1_cmd_status_mprv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_spp <= stalling_1 & stages_1_cmd_status_spp; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mpie <= stalling_1 & stages_1_cmd_status_mpie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_ube <= stalling_1 & stages_1_cmd_status_ube; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_spie <= stalling_1 & stages_1_cmd_status_spie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_upie <= stalling_1 & stages_1_cmd_status_upie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mie <= stalling_1 & stages_1_cmd_status_mie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_hie <= stalling_1 & stages_1_cmd_status_hie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sie <= stalling_1 & stages_1_cmd_status_sie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_uie <= stalling_1 & stages_1_cmd_status_uie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_2 | stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 | ~io_out_ready_0 & valids_1; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_funct = io_out_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rs2 = io_out_bits_cmd_inst_rs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rs1 = io_out_bits_cmd_inst_rs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xd = io_out_bits_cmd_inst_xd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xs1 = io_out_bits_cmd_inst_xs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xs2 = io_out_bits_cmd_inst_xs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rd = io_out_bits_cmd_inst_rd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_opcode = io_out_bits_cmd_inst_opcode_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_rs1 = io_out_bits_cmd_rs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_rs2 = io_out_bits_cmd_rs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_debug = io_out_bits_cmd_status_debug_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_cease = io_out_bits_cmd_status_cease_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_wfi = io_out_bits_cmd_status_wfi_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_isa = io_out_bits_cmd_status_isa_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_dprv = io_out_bits_cmd_status_dprv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_dv = io_out_bits_cmd_status_dv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_prv = io_out_bits_cmd_status_prv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_v = io_out_bits_cmd_status_v_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sd = io_out_bits_cmd_status_sd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_zero2 = io_out_bits_cmd_status_zero2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpv = io_out_bits_cmd_status_mpv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_gva = io_out_bits_cmd_status_gva_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mbe = io_out_bits_cmd_status_mbe_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sbe = io_out_bits_cmd_status_sbe_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sxl = io_out_bits_cmd_status_sxl_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_uxl = io_out_bits_cmd_status_uxl_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sd_rv32 = io_out_bits_cmd_status_sd_rv32_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_zero1 = io_out_bits_cmd_status_zero1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tsr = io_out_bits_cmd_status_tsr_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tw = io_out_bits_cmd_status_tw_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tvm = io_out_bits_cmd_status_tvm_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mxr = io_out_bits_cmd_status_mxr_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sum = io_out_bits_cmd_status_sum_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mprv = io_out_bits_cmd_status_mprv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_xs = io_out_bits_cmd_status_xs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_fs = io_out_bits_cmd_status_fs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpp = io_out_bits_cmd_status_mpp_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_vs = io_out_bits_cmd_status_vs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_spp = io_out_bits_cmd_status_spp_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpie = io_out_bits_cmd_status_mpie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_ube = io_out_bits_cmd_status_ube_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_spie = io_out_bits_cmd_status_spie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_upie = io_out_bits_cmd_status_upie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mie = io_out_bits_cmd_status_mie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_hie = io_out_bits_cmd_status_hie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sie = io_out_bits_cmd_status_sie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_uie = io_out_bits_cmd_status_uie_0; // @[Pipeline.scala:6:7] assign io_out_bits_a_addr = io_out_bits_a_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_b_addr = io_out_bits_b_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_c_addr = io_out_bits_c_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_I = io_out_bits_I_0; // @[Pipeline.scala:6:7] assign io_out_bits_J = io_out_bits_J_0; // @[Pipeline.scala:6:7] assign io_out_bits_K = io_out_bits_K_0; // @[Pipeline.scala:6:7] assign io_out_bits_new_weights = io_out_bits_new_weights_0; // @[Pipeline.scala:6:7] assign io_busy = io_busy_0; // @[Pipeline.scala:6:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_133 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_133( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_180 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_328 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_180( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_328 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_45 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<5>(0h14))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<4>(0h8))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = or(_T_24, _T_29) node _T_31 = and(_T_19, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = and(_T_18, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_38 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_39 = and(_T_37, _T_38) node _T_40 = or(UInt<1>(0h0), _T_39) node _T_41 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<5>(0h14))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_47 = cvt(_T_46) node _T_48 = and(_T_47, asSInt(UInt<4>(0h8))) node _T_49 = asSInt(_T_48) node _T_50 = eq(_T_49, asSInt(UInt<1>(0h0))) node _T_51 = or(_T_45, _T_50) node _T_52 = and(_T_40, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = and(UInt<1>(0h0), _T_53) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_61 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_61, UInt<1>(0h1), "") : assert_5 node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(is_aligned, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_68 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_68, UInt<1>(0h1), "") : assert_7 node _T_72 = not(io.in.a.bits.mask) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_73, UInt<1>(0h1), "") : assert_8 node _T_77 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(_T_77, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_77, UInt<1>(0h1), "") : assert_9 node _T_81 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_81 : node _T_82 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_83 = and(UInt<1>(0h0), _T_82) node _T_84 = or(UInt<1>(0h0), _T_83) node _T_85 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_86 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_87 = cvt(_T_86) node _T_88 = and(_T_87, asSInt(UInt<5>(0h14))) node _T_89 = asSInt(_T_88) node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0))) node _T_91 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_92 = cvt(_T_91) node _T_93 = and(_T_92, asSInt(UInt<4>(0h8))) node _T_94 = asSInt(_T_93) node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0))) node _T_96 = or(_T_90, _T_95) node _T_97 = and(_T_85, _T_96) node _T_98 = or(UInt<1>(0h0), _T_97) node _T_99 = and(_T_84, _T_98) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_105 = and(_T_103, _T_104) node _T_106 = or(UInt<1>(0h0), _T_105) node _T_107 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<5>(0h14))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<4>(0h8))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(UInt<1>(0h0), _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_120, UInt<1>(0h1), "") : assert_11 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_127 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_127, UInt<1>(0h1), "") : assert_13 node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(is_aligned, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_134 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_134, UInt<1>(0h1), "") : assert_15 node _T_138 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_139 = asUInt(reset) node _T_140 = eq(_T_139, UInt<1>(0h0)) when _T_140 : node _T_141 = eq(_T_138, UInt<1>(0h0)) when _T_141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_138, UInt<1>(0h1), "") : assert_16 node _T_142 = not(io.in.a.bits.mask) node _T_143 = eq(_T_142, UInt<1>(0h0)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_143, UInt<1>(0h1), "") : assert_17 node _T_147 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_147, UInt<1>(0h1), "") : assert_18 node _T_151 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_151 : node _T_152 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_153 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_154 = and(_T_152, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_160 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_164 = cvt(_T_163) node _T_165 = and(_T_164, asSInt(UInt<5>(0h14))) node _T_166 = asSInt(_T_165) node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0))) node _T_168 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<4>(0h8))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = or(_T_167, _T_172) node _T_174 = and(_T_162, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_175, UInt<1>(0h1), "") : assert_20 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(is_aligned, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_185 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_185, UInt<1>(0h1), "") : assert_23 node _T_189 = eq(io.in.a.bits.mask, mask) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_189, UInt<1>(0h1), "") : assert_24 node _T_193 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_193, UInt<1>(0h1), "") : assert_25 node _T_197 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_203 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_204 = and(_T_202, _T_203) node _T_205 = or(UInt<1>(0h0), _T_204) node _T_206 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<5>(0h14))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<4>(0h8))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = or(_T_210, _T_215) node _T_217 = and(_T_205, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = and(_T_201, _T_218) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_219, UInt<1>(0h1), "") : assert_26 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(is_aligned, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_229 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_229, UInt<1>(0h1), "") : assert_29 node _T_233 = eq(io.in.a.bits.mask, mask) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_233, UInt<1>(0h1), "") : assert_30 node _T_237 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_237 : node _T_238 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_239 = and(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_242 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_243 = and(_T_241, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<5>(0h14))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<4>(0h8))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = and(_T_244, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = and(_T_240, _T_257) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_258, UInt<1>(0h1), "") : assert_31 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(is_aligned, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_268 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_268, UInt<1>(0h1), "") : assert_34 node _T_272 = not(mask) node _T_273 = and(io.in.a.bits.mask, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_274, UInt<1>(0h1), "") : assert_35 node _T_278 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_278 : node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_280 = and(UInt<1>(0h0), _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<5>(0h14))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<4>(0h8))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = or(_T_287, _T_292) node _T_294 = and(_T_282, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = and(_T_281, _T_295) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_296, UInt<1>(0h1), "") : assert_36 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(is_aligned, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_306 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_306, UInt<1>(0h1), "") : assert_39 node _T_310 = eq(io.in.a.bits.mask, mask) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_310, UInt<1>(0h1), "") : assert_40 node _T_314 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_314 : node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_316 = and(UInt<1>(0h0), _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<5>(0h14))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<4>(0h8))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = or(_T_323, _T_328) node _T_330 = and(_T_318, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = and(_T_317, _T_331) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_332, UInt<1>(0h1), "") : assert_41 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(is_aligned, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_342 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_342, UInt<1>(0h1), "") : assert_44 node _T_346 = eq(io.in.a.bits.mask, mask) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_346, UInt<1>(0h1), "") : assert_45 node _T_350 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_350 : node _T_351 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_352 = and(UInt<1>(0h0), _T_351) node _T_353 = or(UInt<1>(0h0), _T_352) node _T_354 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<5>(0h14))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<4>(0h8))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = or(_T_359, _T_364) node _T_366 = and(_T_354, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_T_353, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_368, UInt<1>(0h1), "") : assert_46 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_378 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_378, UInt<1>(0h1), "") : assert_49 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_382, UInt<1>(0h1), "") : assert_50 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_386, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_390 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_390, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_394 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_394 : node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_398, UInt<1>(0h1), "") : assert_54 node _T_402 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_402, UInt<1>(0h1), "") : assert_55 node _T_406 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_406, UInt<1>(0h1), "") : assert_56 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_410, UInt<1>(0h1), "") : assert_57 node _T_414 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_414 : node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(sink_ok, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_421 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_421, UInt<1>(0h1), "") : assert_60 node _T_425 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_425, UInt<1>(0h1), "") : assert_61 node _T_429 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_T_429, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_429, UInt<1>(0h1), "") : assert_62 node _T_433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_433, UInt<1>(0h1), "") : assert_63 node _T_437 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_438 = or(UInt<1>(0h0), _T_437) node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_T_438, UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_438, UInt<1>(0h1), "") : assert_64 node _T_442 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_442 : node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(sink_ok, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_449 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_449, UInt<1>(0h1), "") : assert_67 node _T_453 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_453, UInt<1>(0h1), "") : assert_68 node _T_457 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_457, UInt<1>(0h1), "") : assert_69 node _T_461 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_462 = or(_T_461, io.in.d.bits.corrupt) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_462, UInt<1>(0h1), "") : assert_70 node _T_466 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_467, UInt<1>(0h1), "") : assert_71 node _T_471 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_471 : node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_475 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_475, UInt<1>(0h1), "") : assert_73 node _T_479 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_479, UInt<1>(0h1), "") : assert_74 node _T_483 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_484, UInt<1>(0h1), "") : assert_75 node _T_488 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_488 : node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_492 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_492, UInt<1>(0h1), "") : assert_77 node _T_496 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_497 = or(_T_496, io.in.d.bits.corrupt) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_497, UInt<1>(0h1), "") : assert_78 node _T_501 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_502 = or(UInt<1>(0h0), _T_501) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_502, UInt<1>(0h1), "") : assert_79 node _T_506 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_506 : node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_510 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_510, UInt<1>(0h1), "") : assert_81 node _T_514 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_514, UInt<1>(0h1), "") : assert_82 node _T_518 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_519 = or(UInt<1>(0h0), _T_518) node _T_520 = asUInt(reset) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(_T_519, UInt<1>(0h0)) when _T_522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_519, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<7>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_523 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_523, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<7>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_527 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(_T_527, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_527, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_531 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(_T_531, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_531, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_535 = eq(a_first, UInt<1>(0h0)) node _T_536 = and(io.in.a.valid, _T_535) when _T_536 : node _T_537 = eq(io.in.a.bits.opcode, opcode) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_537, UInt<1>(0h1), "") : assert_87 node _T_541 = eq(io.in.a.bits.param, param) node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(_T_541, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_541, UInt<1>(0h1), "") : assert_88 node _T_545 = eq(io.in.a.bits.size, size) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_545, UInt<1>(0h1), "") : assert_89 node _T_549 = eq(io.in.a.bits.source, source) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_549, UInt<1>(0h1), "") : assert_90 node _T_553 = eq(io.in.a.bits.address, address) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_553, UInt<1>(0h1), "") : assert_91 node _T_557 = and(io.in.a.ready, io.in.a.valid) node _T_558 = and(_T_557, a_first) when _T_558 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_559 = eq(d_first, UInt<1>(0h0)) node _T_560 = and(io.in.d.valid, _T_559) when _T_560 : node _T_561 = eq(io.in.d.bits.opcode, opcode_1) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_561, UInt<1>(0h1), "") : assert_92 node _T_565 = eq(io.in.d.bits.param, param_1) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_565, UInt<1>(0h1), "") : assert_93 node _T_569 = eq(io.in.d.bits.size, size_1) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_569, UInt<1>(0h1), "") : assert_94 node _T_573 = eq(io.in.d.bits.source, source_1) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_573, UInt<1>(0h1), "") : assert_95 node _T_577 = eq(io.in.d.bits.sink, sink) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_577, UInt<1>(0h1), "") : assert_96 node _T_581 = eq(io.in.d.bits.denied, denied) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_581, UInt<1>(0h1), "") : assert_97 node _T_585 = and(io.in.d.ready, io.in.d.valid) node _T_586 = and(_T_585, d_first) when _T_586 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_587 = and(io.in.a.valid, a_first_1) node _T_588 = and(_T_587, UInt<1>(0h1)) when _T_588 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_589 = and(io.in.a.ready, io.in.a.valid) node _T_590 = and(_T_589, a_first_1) node _T_591 = and(_T_590, UInt<1>(0h1)) when _T_591 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_592 = dshr(inflight, io.in.a.bits.source) node _T_593 = bits(_T_592, 0, 0) node _T_594 = eq(_T_593, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_594, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_598 = and(io.in.d.valid, d_first_1) node _T_599 = and(_T_598, UInt<1>(0h1)) node _T_600 = eq(d_release_ack, UInt<1>(0h0)) node _T_601 = and(_T_599, _T_600) when _T_601 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_602 = and(io.in.d.ready, io.in.d.valid) node _T_603 = and(_T_602, d_first_1) node _T_604 = and(_T_603, UInt<1>(0h1)) node _T_605 = eq(d_release_ack, UInt<1>(0h0)) node _T_606 = and(_T_604, _T_605) when _T_606 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_607 = and(io.in.d.valid, d_first_1) node _T_608 = and(_T_607, UInt<1>(0h1)) node _T_609 = eq(d_release_ack, UInt<1>(0h0)) node _T_610 = and(_T_608, _T_609) when _T_610 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_611 = dshr(inflight, io.in.d.bits.source) node _T_612 = bits(_T_611, 0, 0) node _T_613 = or(_T_612, same_cycle_resp) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_613, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_617 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_618 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_619 = or(_T_617, _T_618) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_619, UInt<1>(0h1), "") : assert_100 node _T_623 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_623, UInt<1>(0h1), "") : assert_101 else : node _T_627 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_628 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_629 = or(_T_627, _T_628) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_629, UInt<1>(0h1), "") : assert_102 node _T_633 = eq(io.in.d.bits.size, a_size_lookup) node _T_634 = asUInt(reset) node _T_635 = eq(_T_634, UInt<1>(0h0)) when _T_635 : node _T_636 = eq(_T_633, UInt<1>(0h0)) when _T_636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_633, UInt<1>(0h1), "") : assert_103 node _T_637 = and(io.in.d.valid, d_first_1) node _T_638 = and(_T_637, a_first_1) node _T_639 = and(_T_638, io.in.a.valid) node _T_640 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_641 = and(_T_639, _T_640) node _T_642 = eq(d_release_ack, UInt<1>(0h0)) node _T_643 = and(_T_641, _T_642) when _T_643 : node _T_644 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_645 = or(_T_644, io.in.a.ready) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_645, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_91 node _T_649 = orr(inflight) node _T_650 = eq(_T_649, UInt<1>(0h0)) node _T_651 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_652 = or(_T_650, _T_651) node _T_653 = lt(watchdog, plusarg_reader.out) node _T_654 = or(_T_652, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_654, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_658 = and(io.in.a.ready, io.in.a.valid) node _T_659 = and(io.in.d.ready, io.in.d.valid) node _T_660 = or(_T_658, _T_659) when _T_660 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<7>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<7>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<7>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_661 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<7>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_662 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_663 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_664 = and(_T_662, _T_663) node _T_665 = and(_T_661, _T_664) when _T_665 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<7>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_666 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_667 = and(_T_666, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<7>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_668 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_669 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_670 = and(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) when _T_671 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<7>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<7>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_672 = dshr(inflight_1, _WIRE_15.bits.source) node _T_673 = bits(_T_672, 0, 0) node _T_674 = eq(_T_673, UInt<1>(0h0)) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_674, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_678 = and(io.in.d.valid, d_first_2) node _T_679 = and(_T_678, UInt<1>(0h1)) node _T_680 = and(_T_679, d_release_ack_1) when _T_680 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_681 = and(io.in.d.ready, io.in.d.valid) node _T_682 = and(_T_681, d_first_2) node _T_683 = and(_T_682, UInt<1>(0h1)) node _T_684 = and(_T_683, d_release_ack_1) when _T_684 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_688 = dshr(inflight_1, io.in.d.bits.source) node _T_689 = bits(_T_688, 0, 0) node _T_690 = or(_T_689, same_cycle_resp_1) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_690, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<7>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_694 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(_T_694, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_694, UInt<1>(0h1), "") : assert_108 else : node _T_698 = eq(io.in.d.bits.size, c_size_lookup) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_698, UInt<1>(0h1), "") : assert_109 node _T_702 = and(io.in.d.valid, d_first_2) node _T_703 = and(_T_702, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<7>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_704 = and(_T_703, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<7>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_705 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_706 = and(_T_704, _T_705) node _T_707 = and(_T_706, d_release_ack_1) node _T_708 = eq(c_probe_ack, UInt<1>(0h0)) node _T_709 = and(_T_707, _T_708) when _T_709 : node _T_710 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<7>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_711 = or(_T_710, _WIRE_23.ready) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_711, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_92 node _T_715 = orr(inflight_1) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_718 = or(_T_716, _T_717) node _T_719 = lt(watchdog_1, plusarg_reader_1.out) node _T_720 = or(_T_718, _T_719) node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(_T_720, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_720, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<7>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_724 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_725 = and(io.in.d.ready, io.in.d.valid) node _T_726 = or(_T_724, _T_725) when _T_726 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_45( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire a_first_done = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] reg d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] reg a_first_counter_1; // @[Edges.scala:229:27] reg d_first_counter_1; // @[Edges.scala:229:27] wire a_set = a_first_done & ~a_first_counter_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg d_first_counter_2; // @[Edges.scala:229:27] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_255 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_511 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_255( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_511 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_67 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} inst input_buffer of InputBuffer_67 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) inst route_arbiter of Arbiter8_RouteComputerReq_67 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h1e)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_9 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_10 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_10 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_11 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_11 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_12 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_12 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_13 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_13 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_14 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_14 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_15 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_15 : connect states[7].g, UInt<3>(0h2) node _T_16 = and(io.router_req.ready, io.router_req.valid) when _T_16 : node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_21 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_22 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_23 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_24 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_25 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_26 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_27 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_28 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8] wire vcalloc_vals : UInt<1>[8] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0)) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35) node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_29 = and(io.router_req.ready, io.router_req.valid) when _T_29 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_31 = or(_T_30, vcalloc_vals[2]) node _T_32 = or(_T_31, vcalloc_vals[3]) node _T_33 = or(_T_32, vcalloc_vals[4]) node _T_34 = or(_T_33, vcalloc_vals[5]) node _T_35 = or(_T_34, vcalloc_vals[6]) node _T_36 = or(_T_35, vcalloc_vals[7]) when _T_36 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = bits(vcalloc_sel, 0, 0) node _mask_T_12 = bits(vcalloc_sel, 1, 1) node _mask_T_13 = bits(vcalloc_sel, 2, 2) node _mask_T_14 = bits(vcalloc_sel, 3, 3) node _mask_T_15 = bits(vcalloc_sel, 4, 4) node _mask_T_16 = bits(vcalloc_sel, 5, 5) node _mask_T_17 = bits(vcalloc_sel, 6, 6) node _mask_T_18 = bits(vcalloc_sel, 7, 7) node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0)) node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0)) node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0)) node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0)) node _mask_T_27 = or(_mask_T_19, _mask_T_20) node _mask_T_28 = or(_mask_T_27, _mask_T_21) node _mask_T_29 = or(_mask_T_28, _mask_T_22) node _mask_T_30 = or(_mask_T_29, _mask_T_23) node _mask_T_31 = or(_mask_T_30, _mask_T_24) node _mask_T_32 = or(_mask_T_31, _mask_T_25) node _mask_T_33 = or(_mask_T_32, _mask_T_26) wire _mask_WIRE : UInt<8> connect _mask_WIRE, _mask_T_33 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}} wire _io_vcalloc_req_bits_WIRE_1 : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100) node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8] node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172 connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187 connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192) node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193) node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194) node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202 connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217 connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219) node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232 connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234) node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235) node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236) node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237) node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238) node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247 connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8] node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249) node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250) node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251) node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252) node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253) node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254) node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268) node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269) node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277 connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292 connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294) node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295) node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300) wire _io_vcalloc_req_bits_WIRE_24 : UInt<1> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307 connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309) node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310) node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311) node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312) node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313) node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314) node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322 connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325) node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326) node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327) node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328) node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329) node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337 connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344) node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352 connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367 connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20 wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8] node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369) node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370) node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371) node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382 connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384) node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385) node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386) node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387) node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388) node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389) node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397 connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401) node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402) node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403) node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404) node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412 connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442 connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34 node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444) node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445) node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446) node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447) node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450) wire _io_vcalloc_req_bits_WIRE_35 : UInt<1> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457 connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35 node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459) node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460) node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461) node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462) node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463) node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464) node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465) wire _io_vcalloc_req_bits_WIRE_36 : UInt<1> connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472 connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36 node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477) node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478) node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479) node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480) wire _io_vcalloc_req_bits_WIRE_37 : UInt<1> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487 connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495) wire _io_vcalloc_req_bits_WIRE_38 : UInt<3> connect _io_vcalloc_req_bits_WIRE_38, _io_vcalloc_req_bits_T_502 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_38 wire _io_vcalloc_req_bits_WIRE_39 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504) node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510) wire _io_vcalloc_req_bits_WIRE_40 : UInt<2> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517 connect _io_vcalloc_req_bits_WIRE_39.egress_node_id, _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519) node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520) node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521) node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522) node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523) node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525) wire _io_vcalloc_req_bits_WIRE_41 : UInt<5> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532 connect _io_vcalloc_req_bits_WIRE_39.egress_node, _io_vcalloc_req_bits_WIRE_41 node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534) node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535) node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536) node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537) node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538) node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539) node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540) wire _io_vcalloc_req_bits_WIRE_42 : UInt<2> connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547 connect _io_vcalloc_req_bits_WIRE_39.ingress_node_id, _io_vcalloc_req_bits_WIRE_42 node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553) node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554) node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555) wire _io_vcalloc_req_bits_WIRE_43 : UInt<5> connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562 connect _io_vcalloc_req_bits_WIRE_39.ingress_node, _io_vcalloc_req_bits_WIRE_43 node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_44 : UInt<3> connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577 connect _io_vcalloc_req_bits_WIRE_39.vnet_id, _io_vcalloc_req_bits_WIRE_44 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_39 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[6] invalidate vcalloc_reqs[0].vc_sel.`1`[7] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[5] invalidate vcalloc_reqs[0].vc_sel.`2`[6] invalidate vcalloc_reqs[0].vc_sel.`2`[7] invalidate vcalloc_reqs[0].vc_sel.`3`[0] invalidate vcalloc_reqs[0].vc_sel.`3`[1] invalidate vcalloc_reqs[0].vc_sel.`3`[2] invalidate vcalloc_reqs[0].vc_sel.`3`[3] invalidate vcalloc_reqs[0].vc_sel.`3`[4] invalidate vcalloc_reqs[0].vc_sel.`3`[5] invalidate vcalloc_reqs[0].vc_sel.`3`[6] invalidate vcalloc_reqs[0].vc_sel.`3`[7] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].flow, states[1].flow node _T_37 = bits(vcalloc_sel, 1, 1) node _T_38 = and(vcalloc_vals[1], _T_37) node _T_39 = and(_T_38, io.vcalloc_req.ready) when _T_39 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].flow, states[2].flow node _T_40 = bits(vcalloc_sel, 2, 2) node _T_41 = and(vcalloc_vals[2], _T_40) node _T_42 = and(_T_41, io.vcalloc_req.ready) when _T_42 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].flow, states[3].flow node _T_43 = bits(vcalloc_sel, 3, 3) node _T_44 = and(vcalloc_vals[3], _T_43) node _T_45 = and(_T_44, io.vcalloc_req.ready) when _T_45 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].flow, states[4].flow node _T_46 = bits(vcalloc_sel, 4, 4) node _T_47 = and(vcalloc_vals[4], _T_46) node _T_48 = and(_T_47, io.vcalloc_req.ready) when _T_48 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].flow, states[5].flow node _T_49 = bits(vcalloc_sel, 5, 5) node _T_50 = and(vcalloc_vals[5], _T_49) node _T_51 = and(_T_50, io.vcalloc_req.ready) when _T_51 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3` connect vcalloc_reqs[6].flow, states[6].flow node _T_52 = bits(vcalloc_sel, 6, 6) node _T_53 = and(vcalloc_vals[6], _T_52) node _T_54 = and(_T_53, io.vcalloc_req.ready) when _T_54 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3` connect vcalloc_reqs[7].flow, states[7].flow node _T_55 = bits(vcalloc_sel, 7, 7) node _T_56 = and(vcalloc_vals[7], _T_55) node _T_57 = and(_T_56, io.vcalloc_req.ready) when _T_57 : connect states[7].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0) node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0) node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready) node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1) connect io.debug.va_stall, _io_debug_va_stall_T_15 node _T_58 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_58 : node _T_59 = bits(vcalloc_sel, 0, 0) when _T_59 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].g, UInt<3>(0h3) node _T_60 = eq(states[0].g, UInt<3>(0h2)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_60, UInt<1>(0h1), "") : assert_3 node _T_64 = bits(vcalloc_sel, 1, 1) when _T_64 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].g, UInt<3>(0h3) node _T_65 = eq(states[1].g, UInt<3>(0h2)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_65, UInt<1>(0h1), "") : assert_4 node _T_69 = bits(vcalloc_sel, 2, 2) when _T_69 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].g, UInt<3>(0h3) node _T_70 = eq(states[2].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _T_74 = bits(vcalloc_sel, 3, 3) when _T_74 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].g, UInt<3>(0h3) node _T_75 = eq(states[3].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_75, UInt<1>(0h1), "") : assert_6 node _T_79 = bits(vcalloc_sel, 4, 4) when _T_79 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].g, UInt<3>(0h3) node _T_80 = eq(states[4].g, UInt<3>(0h2)) node _T_81 = asUInt(reset) node _T_82 = eq(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = eq(_T_80, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_80, UInt<1>(0h1), "") : assert_7 node _T_84 = bits(vcalloc_sel, 5, 5) when _T_84 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].g, UInt<3>(0h3) node _T_85 = eq(states[5].g, UInt<3>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_85, UInt<1>(0h1), "") : assert_8 node _T_89 = bits(vcalloc_sel, 6, 6) when _T_89 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].g, UInt<3>(0h3) node _T_90 = eq(states[6].g, UInt<3>(0h2)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_90, UInt<1>(0h1), "") : assert_9 node _T_94 = bits(vcalloc_sel, 7, 7) when _T_94 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].g, UInt<3>(0h3) node _T_95 = eq(states[7].g, UInt<3>(0h2)) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_95, UInt<1>(0h1), "") : assert_10 inst salloc_arb of SwitchArbiter_166 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`3`[7] node credit_available_lo_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_hi = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_lo_hi_1 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4]) node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo_hi_2 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4]) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_lo_3 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0]) node credit_available_lo_hi_3 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4]) node credit_available_hi_hi_3 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node credit_available_lo_4 = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_4 = cat(_credit_available_T_3, _credit_available_T_2) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_lo_4 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_4 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_4 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_5 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_5 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_lo_6 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_6 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_6 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_7 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7) node credit_available_lo_lo_7 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_7 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_8 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_9 = cat(_credit_available_T_6, _credit_available_T_5) node credit_available_hi_9 = cat(_credit_available_T_8, _credit_available_T_7) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9) node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9) node credit_available = neq(_credit_available_T_10, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6] connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5] connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6] connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3] connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4] connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5] connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6] connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_99 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_100 = and(_T_99, input_buffer.io.deq[1].bits.tail) when _T_100 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_8 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_8 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_hi_8 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6]) node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_lo_9 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) node credit_available_lo_hi_9 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2]) node credit_available_lo_11 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4]) node credit_available_hi_hi_9 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6]) node credit_available_hi_11 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) node _credit_available_T_12 = cat(credit_available_hi_11, credit_available_lo_11) node credit_available_lo_lo_10 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) node credit_available_lo_hi_10 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4]) node credit_available_hi_hi_10 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6]) node credit_available_hi_12 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_lo_11 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0]) node credit_available_lo_hi_11 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4]) node credit_available_hi_hi_11 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6]) node credit_available_hi_13 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_14 = cat(_credit_available_T_12, _credit_available_T_11) node credit_available_hi_14 = cat(_credit_available_T_14, _credit_available_T_13) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_lo_12 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_12 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_12 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_15 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15) node credit_available_lo_lo_13 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_13 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_13 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_16 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_lo_14 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_14 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_17 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_14 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_17 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_15 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_15 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_15 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_18 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_19 = cat(_credit_available_T_17, _credit_available_T_16) node credit_available_hi_19 = cat(_credit_available_T_19, _credit_available_T_18) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19) node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20) node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3] connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4] connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5] connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6] connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_101 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_102 = and(_T_101, input_buffer.io.deq[2].bits.tail) when _T_102 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_16 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_16 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_hi_16 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6]) node credit_available_hi_20 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16) node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_lo_17 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_17 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4]) node credit_available_hi_hi_17 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6]) node credit_available_hi_21 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17) node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_18 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_18 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4]) node credit_available_hi_hi_18 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6]) node credit_available_hi_22 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18) node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_lo_19 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0]) node credit_available_lo_hi_19 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2]) node credit_available_lo_23 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4]) node credit_available_hi_hi_19 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6]) node credit_available_hi_23 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19) node _credit_available_T_25 = cat(credit_available_hi_23, credit_available_lo_23) node credit_available_lo_24 = cat(_credit_available_T_23, _credit_available_T_22) node credit_available_hi_24 = cat(_credit_available_T_25, _credit_available_T_24) node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_lo_20 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_20 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_20 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_25 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20) node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_21 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_21 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_21 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_26 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21) node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_lo_22 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_22 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_22 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_27 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22) node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27) node credit_available_lo_lo_23 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_23 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_23 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_28 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23) node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_29 = cat(_credit_available_T_28, _credit_available_T_27) node credit_available_hi_29 = cat(_credit_available_T_30, _credit_available_T_29) node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29) node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31) node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1] connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2] connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3] connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4] connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5] connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6] connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_103 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_104 = and(_T_103, input_buffer.io.deq[3].bits.tail) when _T_104 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_24 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_24 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_hi_24 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6]) node credit_available_hi_30 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24) node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_lo_25 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_25 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4]) node credit_available_hi_hi_25 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6]) node credit_available_hi_31 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25) node _credit_available_T_34 = cat(credit_available_hi_31, credit_available_lo_31) node credit_available_lo_lo_26 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_26 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4]) node credit_available_hi_hi_26 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6]) node credit_available_hi_32 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26) node _credit_available_T_35 = cat(credit_available_hi_32, credit_available_lo_32) node credit_available_lo_lo_27 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0]) node credit_available_lo_hi_27 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4]) node credit_available_hi_hi_27 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6]) node credit_available_hi_33 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27) node _credit_available_T_36 = cat(credit_available_hi_33, credit_available_lo_33) node credit_available_lo_34 = cat(_credit_available_T_34, _credit_available_T_33) node credit_available_hi_34 = cat(_credit_available_T_36, _credit_available_T_35) node _credit_available_T_37 = cat(credit_available_hi_34, credit_available_lo_34) node credit_available_lo_lo_28 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_28 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_35 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_28 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_35 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28) node _credit_available_T_38 = cat(credit_available_hi_35, credit_available_lo_35) node credit_available_lo_lo_29 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_29 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_29 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_36 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29) node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36) node credit_available_lo_lo_30 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_30 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_30 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_37 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30) node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37) node credit_available_lo_lo_31 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_31 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_31 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_38 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31) node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38) node credit_available_lo_39 = cat(_credit_available_T_39, _credit_available_T_38) node credit_available_hi_39 = cat(_credit_available_T_41, _credit_available_T_40) node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39) node _credit_available_T_43 = and(_credit_available_T_37, _credit_available_T_42) node credit_available_3 = neq(_credit_available_T_43, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1] connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2] connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3] connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4] connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5] connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6] connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_105 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_106 = and(_T_105, input_buffer.io.deq[4].bits.tail) when _T_106 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_32 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_32 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_hi_32 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6]) node credit_available_hi_40 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32) node _credit_available_T_44 = cat(credit_available_hi_40, credit_available_lo_40) node credit_available_lo_lo_33 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_33 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2]) node credit_available_lo_41 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4]) node credit_available_hi_hi_33 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6]) node credit_available_hi_41 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33) node _credit_available_T_45 = cat(credit_available_hi_41, credit_available_lo_41) node credit_available_lo_lo_34 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_34 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2]) node credit_available_lo_42 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4]) node credit_available_hi_hi_34 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6]) node credit_available_hi_42 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34) node _credit_available_T_46 = cat(credit_available_hi_42, credit_available_lo_42) node credit_available_lo_lo_35 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0]) node credit_available_lo_hi_35 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2]) node credit_available_lo_43 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4]) node credit_available_hi_hi_35 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6]) node credit_available_hi_43 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35) node _credit_available_T_47 = cat(credit_available_hi_43, credit_available_lo_43) node credit_available_lo_44 = cat(_credit_available_T_45, _credit_available_T_44) node credit_available_hi_44 = cat(_credit_available_T_47, _credit_available_T_46) node _credit_available_T_48 = cat(credit_available_hi_44, credit_available_lo_44) node credit_available_lo_lo_36 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_36 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_45 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_36 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_45 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36) node _credit_available_T_49 = cat(credit_available_hi_45, credit_available_lo_45) node credit_available_lo_lo_37 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_37 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_46 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_37 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_46 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37) node _credit_available_T_50 = cat(credit_available_hi_46, credit_available_lo_46) node credit_available_lo_lo_38 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_38 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_47 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_38 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_47 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38) node _credit_available_T_51 = cat(credit_available_hi_47, credit_available_lo_47) node credit_available_lo_lo_39 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_39 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_48 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_39 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_48 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39) node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48) node credit_available_lo_49 = cat(_credit_available_T_50, _credit_available_T_49) node credit_available_hi_49 = cat(_credit_available_T_52, _credit_available_T_51) node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49) node _credit_available_T_54 = and(_credit_available_T_48, _credit_available_T_53) node credit_available_4 = neq(_credit_available_T_54, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1] connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2] connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3] connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4] connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5] connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6] connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_107 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_108 = and(_T_107, input_buffer.io.deq[5].bits.tail) when _T_108 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_40 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_40 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2]) node credit_available_lo_50 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4]) node credit_available_hi_hi_40 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6]) node credit_available_hi_50 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40) node _credit_available_T_55 = cat(credit_available_hi_50, credit_available_lo_50) node credit_available_lo_lo_41 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_41 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2]) node credit_available_lo_51 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4]) node credit_available_hi_hi_41 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6]) node credit_available_hi_51 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41) node _credit_available_T_56 = cat(credit_available_hi_51, credit_available_lo_51) node credit_available_lo_lo_42 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_42 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2]) node credit_available_lo_52 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42) node credit_available_hi_lo_42 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4]) node credit_available_hi_hi_42 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6]) node credit_available_hi_52 = cat(credit_available_hi_hi_42, credit_available_hi_lo_42) node _credit_available_T_57 = cat(credit_available_hi_52, credit_available_lo_52) node credit_available_lo_lo_43 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0]) node credit_available_lo_hi_43 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2]) node credit_available_lo_53 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43) node credit_available_hi_lo_43 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4]) node credit_available_hi_hi_43 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6]) node credit_available_hi_53 = cat(credit_available_hi_hi_43, credit_available_hi_lo_43) node _credit_available_T_58 = cat(credit_available_hi_53, credit_available_lo_53) node credit_available_lo_54 = cat(_credit_available_T_56, _credit_available_T_55) node credit_available_hi_54 = cat(_credit_available_T_58, _credit_available_T_57) node _credit_available_T_59 = cat(credit_available_hi_54, credit_available_lo_54) node credit_available_lo_lo_44 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_44 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_55 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44) node credit_available_hi_lo_44 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_44 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_55 = cat(credit_available_hi_hi_44, credit_available_hi_lo_44) node _credit_available_T_60 = cat(credit_available_hi_55, credit_available_lo_55) node credit_available_lo_lo_45 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_45 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_56 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45) node credit_available_hi_lo_45 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_45 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_56 = cat(credit_available_hi_hi_45, credit_available_hi_lo_45) node _credit_available_T_61 = cat(credit_available_hi_56, credit_available_lo_56) node credit_available_lo_lo_46 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_46 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_57 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46) node credit_available_hi_lo_46 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_46 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_57 = cat(credit_available_hi_hi_46, credit_available_hi_lo_46) node _credit_available_T_62 = cat(credit_available_hi_57, credit_available_lo_57) node credit_available_lo_lo_47 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_47 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_58 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47) node credit_available_hi_lo_47 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_47 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_58 = cat(credit_available_hi_hi_47, credit_available_hi_lo_47) node _credit_available_T_63 = cat(credit_available_hi_58, credit_available_lo_58) node credit_available_lo_59 = cat(_credit_available_T_61, _credit_available_T_60) node credit_available_hi_59 = cat(_credit_available_T_63, _credit_available_T_62) node _credit_available_T_64 = cat(credit_available_hi_59, credit_available_lo_59) node _credit_available_T_65 = and(_credit_available_T_59, _credit_available_T_64) node credit_available_5 = neq(_credit_available_T_65, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_5) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0] connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1] connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2] connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3] connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4] connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5] connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6] connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_109 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_110 = and(_T_109, input_buffer.io.deq[6].bits.tail) when _T_110 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_48 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_48 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2]) node credit_available_lo_60 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48) node credit_available_hi_lo_48 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4]) node credit_available_hi_hi_48 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6]) node credit_available_hi_60 = cat(credit_available_hi_hi_48, credit_available_hi_lo_48) node _credit_available_T_66 = cat(credit_available_hi_60, credit_available_lo_60) node credit_available_lo_lo_49 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_49 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2]) node credit_available_lo_61 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49) node credit_available_hi_lo_49 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4]) node credit_available_hi_hi_49 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6]) node credit_available_hi_61 = cat(credit_available_hi_hi_49, credit_available_hi_lo_49) node _credit_available_T_67 = cat(credit_available_hi_61, credit_available_lo_61) node credit_available_lo_lo_50 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_50 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2]) node credit_available_lo_62 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50) node credit_available_hi_lo_50 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4]) node credit_available_hi_hi_50 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6]) node credit_available_hi_62 = cat(credit_available_hi_hi_50, credit_available_hi_lo_50) node _credit_available_T_68 = cat(credit_available_hi_62, credit_available_lo_62) node credit_available_lo_lo_51 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0]) node credit_available_lo_hi_51 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2]) node credit_available_lo_63 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51) node credit_available_hi_lo_51 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4]) node credit_available_hi_hi_51 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6]) node credit_available_hi_63 = cat(credit_available_hi_hi_51, credit_available_hi_lo_51) node _credit_available_T_69 = cat(credit_available_hi_63, credit_available_lo_63) node credit_available_lo_64 = cat(_credit_available_T_67, _credit_available_T_66) node credit_available_hi_64 = cat(_credit_available_T_69, _credit_available_T_68) node _credit_available_T_70 = cat(credit_available_hi_64, credit_available_lo_64) node credit_available_lo_lo_52 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_52 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_65 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52) node credit_available_hi_lo_52 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_52 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_65 = cat(credit_available_hi_hi_52, credit_available_hi_lo_52) node _credit_available_T_71 = cat(credit_available_hi_65, credit_available_lo_65) node credit_available_lo_lo_53 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_53 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_66 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53) node credit_available_hi_lo_53 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_53 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_66 = cat(credit_available_hi_hi_53, credit_available_hi_lo_53) node _credit_available_T_72 = cat(credit_available_hi_66, credit_available_lo_66) node credit_available_lo_lo_54 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_54 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_67 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54) node credit_available_hi_lo_54 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_54 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_67 = cat(credit_available_hi_hi_54, credit_available_hi_lo_54) node _credit_available_T_73 = cat(credit_available_hi_67, credit_available_lo_67) node credit_available_lo_lo_55 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_55 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_68 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55) node credit_available_hi_lo_55 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_55 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_68 = cat(credit_available_hi_hi_55, credit_available_hi_lo_55) node _credit_available_T_74 = cat(credit_available_hi_68, credit_available_lo_68) node credit_available_lo_69 = cat(_credit_available_T_72, _credit_available_T_71) node credit_available_hi_69 = cat(_credit_available_T_74, _credit_available_T_73) node _credit_available_T_75 = cat(credit_available_hi_69, credit_available_lo_69) node _credit_available_T_76 = and(_credit_available_T_70, _credit_available_T_75) node credit_available_6 = neq(_credit_available_T_76, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_6) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0] connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1] connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2] connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3] connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4] connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5] connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6] connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_111 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_112 = and(_T_111, input_buffer.io.deq[7].bits.tail) when _T_112 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_29 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10) node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11) node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12) node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23 node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_25 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire vc_sel : { `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _vc_sel_WIRE : UInt<1>[8] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10) node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11) node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_22 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25) node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26) node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_37 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42) node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43) node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_52 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_67 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_82 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87) node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88) node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_97 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99) node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100) node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101) node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_112 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116) node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117) node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118) node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119) node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_127 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_9 : UInt<1>[8] node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_142 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145) node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_157 connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159) node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160) node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161) node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162) node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163) node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164) node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_172 connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12 node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174) node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175) node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176) node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177) node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178) node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179) node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_187 connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13 node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192) node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193) node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194) node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_202 connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14 node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_217 connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15 node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219) node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220) node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221) node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_232 connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16 node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234) node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235) node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236) node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237) node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238) node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239) node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_247 connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17 connect vc_sel.`1`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_18 : UInt<1>[8] node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249) node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250) node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251) node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252) node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253) node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254) node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_262 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268) node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269) node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_277 connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20 node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_292 connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21 node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294) node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295) node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296) node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297) node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300) wire _vc_sel_WIRE_22 : UInt<1> connect _vc_sel_WIRE_22, _vc_sel_T_307 connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22 node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309) node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310) node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311) node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312) node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313) node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314) node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_322 connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23 node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325) node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326) node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327) node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328) node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329) node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_337 connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24 node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344) node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_352 connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25 node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354) node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_367 connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26 connect vc_sel.`2`, _vc_sel_WIRE_18 wire _vc_sel_WIRE_27 : UInt<1>[8] node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369) node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370) node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371) node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372) node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373) node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_382 connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28 node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384) node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385) node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386) node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387) node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388) node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389) node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_397 connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29 node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401) node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402) node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403) node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404) node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_412 connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30 node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_427 connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430) node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_442 connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32 node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444) node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445) node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446) node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447) node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448) node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449) node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450) wire _vc_sel_WIRE_33 : UInt<1> connect _vc_sel_WIRE_33, _vc_sel_T_457 connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33 node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459) node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460) node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461) node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462) node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463) node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464) node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465) wire _vc_sel_WIRE_34 : UInt<1> connect _vc_sel_WIRE_34, _vc_sel_T_472 connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34 node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477) node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478) node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479) node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480) wire _vc_sel_WIRE_35 : UInt<1> connect _vc_sel_WIRE_35, _vc_sel_T_487 connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35 connect vc_sel.`3`, _vc_sel_WIRE_27 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6]) node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7]) node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4]) node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6]) node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7]) node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6]) node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2]) node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2]) node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0]) node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2]) node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3) node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4]) node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6]) node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3) node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node _virt_channel_T_32 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_33 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_34 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_35 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0)) node _virt_channel_T_36 = or(_virt_channel_T_32, _virt_channel_T_33) node _virt_channel_T_37 = or(_virt_channel_T_36, _virt_channel_T_34) node _virt_channel_T_38 = or(_virt_channel_T_37, _virt_channel_T_35) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_38 node _T_113 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_113 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59) node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`1`[5] invalidate states[0].vc_sel.`1`[6] invalidate states[0].vc_sel.`1`[7] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].vc_sel.`2`[5] invalidate states[0].vc_sel.`2`[6] invalidate states[0].vc_sel.`2`[7] invalidate states[0].vc_sel.`3`[0] invalidate states[0].vc_sel.`3`[1] invalidate states[0].vc_sel.`3`[2] invalidate states[0].vc_sel.`3`[3] invalidate states[0].vc_sel.`3`[4] invalidate states[0].vc_sel.`3`[5] invalidate states[0].vc_sel.`3`[6] invalidate states[0].vc_sel.`3`[7] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[5], UInt<1>(0h0) connect states[1].vc_sel.`1`[6], UInt<1>(0h0) connect states[1].vc_sel.`1`[7], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[3], UInt<1>(0h0) connect states[1].vc_sel.`2`[4], UInt<1>(0h0) connect states[1].vc_sel.`2`[5], UInt<1>(0h0) connect states[1].vc_sel.`2`[6], UInt<1>(0h0) connect states[1].vc_sel.`2`[7], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) connect states[1].vc_sel.`3`[1], UInt<1>(0h0) connect states[1].vc_sel.`3`[2], UInt<1>(0h0) connect states[1].vc_sel.`3`[3], UInt<1>(0h0) connect states[1].vc_sel.`3`[4], UInt<1>(0h0) connect states[1].vc_sel.`3`[5], UInt<1>(0h0) connect states[1].vc_sel.`3`[6], UInt<1>(0h0) connect states[1].vc_sel.`3`[7], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[2], UInt<1>(0h0) connect states[2].vc_sel.`1`[3], UInt<1>(0h0) connect states[2].vc_sel.`1`[4], UInt<1>(0h0) connect states[2].vc_sel.`1`[5], UInt<1>(0h0) connect states[2].vc_sel.`1`[6], UInt<1>(0h0) connect states[2].vc_sel.`1`[7], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[1], UInt<1>(0h0) connect states[2].vc_sel.`3`[2], UInt<1>(0h0) connect states[2].vc_sel.`3`[3], UInt<1>(0h0) connect states[2].vc_sel.`3`[4], UInt<1>(0h0) connect states[2].vc_sel.`3`[5], UInt<1>(0h0) connect states[2].vc_sel.`3`[6], UInt<1>(0h0) connect states[2].vc_sel.`3`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[1], UInt<1>(0h0) connect states[3].vc_sel.`1`[2], UInt<1>(0h0) connect states[3].vc_sel.`1`[3], UInt<1>(0h0) connect states[3].vc_sel.`1`[4], UInt<1>(0h0) connect states[3].vc_sel.`1`[5], UInt<1>(0h0) connect states[3].vc_sel.`1`[6], UInt<1>(0h0) connect states[3].vc_sel.`1`[7], UInt<1>(0h0) connect states[3].vc_sel.`2`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[1], UInt<1>(0h0) connect states[3].vc_sel.`3`[2], UInt<1>(0h0) connect states[3].vc_sel.`3`[3], UInt<1>(0h0) connect states[3].vc_sel.`3`[4], UInt<1>(0h0) connect states[3].vc_sel.`3`[5], UInt<1>(0h0) connect states[3].vc_sel.`3`[6], UInt<1>(0h0) connect states[3].vc_sel.`3`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[1], UInt<1>(0h0) connect states[4].vc_sel.`1`[2], UInt<1>(0h0) connect states[4].vc_sel.`1`[3], UInt<1>(0h0) connect states[4].vc_sel.`1`[4], UInt<1>(0h0) connect states[4].vc_sel.`1`[5], UInt<1>(0h0) connect states[4].vc_sel.`1`[6], UInt<1>(0h0) connect states[4].vc_sel.`1`[7], UInt<1>(0h0) connect states[4].vc_sel.`2`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[1], UInt<1>(0h0) connect states[4].vc_sel.`3`[2], UInt<1>(0h0) connect states[4].vc_sel.`3`[3], UInt<1>(0h0) connect states[4].vc_sel.`3`[4], UInt<1>(0h0) connect states[4].vc_sel.`3`[5], UInt<1>(0h0) connect states[4].vc_sel.`3`[6], UInt<1>(0h0) connect states[4].vc_sel.`3`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[1], UInt<1>(0h0) connect states[5].vc_sel.`1`[2], UInt<1>(0h0) connect states[5].vc_sel.`1`[3], UInt<1>(0h0) connect states[5].vc_sel.`1`[4], UInt<1>(0h0) connect states[5].vc_sel.`1`[5], UInt<1>(0h0) connect states[5].vc_sel.`1`[6], UInt<1>(0h0) connect states[5].vc_sel.`1`[7], UInt<1>(0h0) connect states[5].vc_sel.`2`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[1], UInt<1>(0h0) connect states[5].vc_sel.`3`[2], UInt<1>(0h0) connect states[5].vc_sel.`3`[3], UInt<1>(0h0) connect states[5].vc_sel.`3`[4], UInt<1>(0h0) connect states[5].vc_sel.`3`[5], UInt<1>(0h0) connect states[5].vc_sel.`3`[6], UInt<1>(0h0) connect states[5].vc_sel.`3`[7], UInt<1>(0h0) connect states[6].vc_sel.`0`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[1], UInt<1>(0h0) connect states[6].vc_sel.`1`[2], UInt<1>(0h0) connect states[6].vc_sel.`1`[3], UInt<1>(0h0) connect states[6].vc_sel.`1`[4], UInt<1>(0h0) connect states[6].vc_sel.`1`[5], UInt<1>(0h0) connect states[6].vc_sel.`1`[6], UInt<1>(0h0) connect states[6].vc_sel.`1`[7], UInt<1>(0h0) connect states[6].vc_sel.`2`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[1], UInt<1>(0h0) connect states[6].vc_sel.`3`[2], UInt<1>(0h0) connect states[6].vc_sel.`3`[3], UInt<1>(0h0) connect states[6].vc_sel.`3`[4], UInt<1>(0h0) connect states[6].vc_sel.`3`[5], UInt<1>(0h0) connect states[6].vc_sel.`3`[6], UInt<1>(0h0) connect states[6].vc_sel.`3`[7], UInt<1>(0h0) connect states[7].vc_sel.`0`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[1], UInt<1>(0h0) connect states[7].vc_sel.`1`[2], UInt<1>(0h0) connect states[7].vc_sel.`1`[3], UInt<1>(0h0) connect states[7].vc_sel.`1`[4], UInt<1>(0h0) connect states[7].vc_sel.`1`[5], UInt<1>(0h0) connect states[7].vc_sel.`1`[6], UInt<1>(0h0) connect states[7].vc_sel.`1`[7], UInt<1>(0h0) connect states[7].vc_sel.`2`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[1], UInt<1>(0h0) connect states[7].vc_sel.`3`[2], UInt<1>(0h0) connect states[7].vc_sel.`3`[3], UInt<1>(0h0) connect states[7].vc_sel.`3`[4], UInt<1>(0h0) connect states[7].vc_sel.`3`[5], UInt<1>(0h0) connect states[7].vc_sel.`3`[6], UInt<1>(0h0) connect states[7].vc_sel.`3`[7], UInt<1>(0h0) node _T_114 = asUInt(reset) when _T_114 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0)
module InputUnit_67( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_3_4, // @[InputUnit.scala:170:14] input io_out_credit_available_3_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_6, // @[InputUnit.scala:170:14] input io_out_credit_available_3_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e8_s24_5 : output io : { flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<10>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<5>, highAlignedSigC : UInt<26>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 31, 23) node _rawA_isZero_T = bits(rawA_exp, 8, 6) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 8, 7) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawA_out_isNaN_T = bits(rawA_exp, 6, 6) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 6, 6) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 32, 32) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 22, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 31, 23) node _rawB_isZero_T = bits(rawB_exp, 8, 6) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 8, 7) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawB_out_isNaN_T = bits(rawB_exp, 6, 6) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 6, 6) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 32, 32) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 22, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 31, 23) node _rawC_isZero_T = bits(rawC_exp, 8, 6) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 8, 7) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawC_out_isNaN_T = bits(rawC_exp, 6, 6) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 6, 6) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 32, 32) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 22, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<9>(0h11b))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 9, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<5>(0h18)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<7>(0h4a)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 6, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<7>(0h4a)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<53>(0h1fffffffffffff), UInt<53>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 2) wire reduced4CExtra_reducedVec : UInt<1>[7] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 26, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node reduced4CExtra_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 19, 14) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 3, 0) node _reduced4CExtra_T_5 = bits(_reduced4CExtra_T_4, 1, 0) node _reduced4CExtra_T_6 = bits(_reduced4CExtra_T_5, 0, 0) node _reduced4CExtra_T_7 = bits(_reduced4CExtra_T_5, 1, 1) node _reduced4CExtra_T_8 = cat(_reduced4CExtra_T_6, _reduced4CExtra_T_7) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 2) node _reduced4CExtra_T_10 = bits(_reduced4CExtra_T_9, 0, 0) node _reduced4CExtra_T_11 = bits(_reduced4CExtra_T_9, 1, 1) node _reduced4CExtra_T_12 = cat(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = cat(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_3, 5, 4) node _reduced4CExtra_T_15 = bits(_reduced4CExtra_T_14, 0, 0) node _reduced4CExtra_T_16 = bits(_reduced4CExtra_T_14, 1, 1) node _reduced4CExtra_T_17 = cat(_reduced4CExtra_T_15, _reduced4CExtra_T_16) node _reduced4CExtra_T_18 = cat(_reduced4CExtra_T_13, _reduced4CExtra_T_17) node _reduced4CExtra_T_19 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_18) node reduced4CExtra = orr(_reduced4CExtra_T_19) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 48, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 22, 22) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<6>(0h18))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 4, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 74, 49) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T
module MulAddRecFNToRaw_preMul_e8_s24_5( // @[MulAddRecFN.scala:71:7] input [1:0] io_op, // @[MulAddRecFN.scala:74:16] input [32:0] io_a, // @[MulAddRecFN.scala:74:16] input [32:0] io_b, // @[MulAddRecFN.scala:74:16] input [32:0] io_c, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [23:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [47:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [9:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [4:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [25:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7] wire [32:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [32:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [32:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire [47:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [4:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [25:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [9:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [4:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [25:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [23:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [47:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [8:0] rawA_exp = io_a_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawA_out_sig_T_2 = io_a_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawB_exp = io_b_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawB_out_sig_T_2 = io_b_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [8:0] rawC_exp = io_c_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawC_out_sig_T_2 = io_c_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49] assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [10:0] _sExpAlignedProd_T = {rawA_sExp[9], rawA_sExp} + {rawB_sExp[9], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [11:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[10], _sExpAlignedProd_T} - 12'hE5; // @[MulAddRecFN.scala:100:{19,32}] wire [10:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[10:0]; // @[MulAddRecFN.scala:100:32] wire [10:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49] assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [11:0] _GEN = {sExpAlignedProd[10], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [11:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[9]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [10:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[10:0]; // @[MulAddRecFN.scala:106:42] wire [10:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [9:0] posNatCAlignDist = sNatCAlignDist[9:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 11'sh0; // @[MulAddRecFN.scala:106:42, :108:69] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 10'h19; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 10'h4A; // @[MulAddRecFN.scala:107:42, :114:34] wire [6:0] _CAlignDist_T_1 = posNatCAlignDist[6:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [6:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 7'h4A; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [6:0] CAlignDist = isMinCAlign ? 7'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [24:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [52:0] _mainAlignedSigC_T_2 = {53{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [77:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [77:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [77:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire [26:0] _reduced4CExtra_T = {rawC_sig, 2'h0}; // @[rawFloatFromRecFN.scala:55:23] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [2:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[26:24]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [6:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [4:0] _reduced4CExtra_T_2 = CAlignDist[6:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [32:0] reduced4CExtra_shift = $signed(33'sh100000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [5:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[19:14]; // @[primitives.scala:76:56, :78:22] wire [3:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[3:0]; // @[primitives.scala:77:20, :78:22] wire [1:0] _reduced4CExtra_T_5 = _reduced4CExtra_T_4[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_6 = _reduced4CExtra_T_5[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_7 = _reduced4CExtra_T_5[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_8 = {_reduced4CExtra_T_6, _reduced4CExtra_T_7}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_10 = _reduced4CExtra_T_9[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_11 = _reduced4CExtra_T_9[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_12 = {_reduced4CExtra_T_10, _reduced4CExtra_T_11}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_13 = {_reduced4CExtra_T_8, _reduced4CExtra_T_12}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_14 = _reduced4CExtra_T_3[5:4]; // @[primitives.scala:77:20, :78:22] wire _reduced4CExtra_T_15 = _reduced4CExtra_T_14[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_16 = _reduced4CExtra_T_14[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_17 = {_reduced4CExtra_T_15, _reduced4CExtra_T_16}; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_18 = {_reduced4CExtra_T_13, _reduced4CExtra_T_17}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_19 = {1'h0, _reduced4CExtra_T_1[5:0] & _reduced4CExtra_T_18}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = |_reduced4CExtra_T_19; // @[MulAddRecFN.scala:122:68, :130:11] wire [74:0] _alignedSigC_T = mainAlignedSigC[77:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [74:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [75:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[23:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[48:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [11:0] _io_toPostMul_sExpSum_T = _GEN - 12'h18; // @[MulAddRecFN.scala:106:42, :158:53] wire [10:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[10:0]; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [10:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[9], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[9:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[4:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[74:49]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_343 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>, flip in_b : SInt<20>, flip in_d : SInt<20>, out_a : SInt<8>, out_b : SInt<20>, out_c : SInt<20>, flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}, flip in_id : UInt<3>, out_id : UInt<3>, flip in_last : UInt<1>, out_last : UInt<1>, flip in_valid : UInt<1>, out_valid : UInt<1>, bad_dataflow : UInt<1>} inst mac_unit of MacUnit_87 connect mac_unit.clock, clock connect mac_unit.reset, reset reg c1 : SInt<8>, clock reg c2 : SInt<8>, clock connect io.out_a, io.in_a connect io.out_control.dataflow, io.in_control.dataflow connect io.out_control.propagate, io.in_control.propagate connect io.out_control.shift, io.in_control.shift connect io.out_id, io.in_id connect io.out_last, io.in_last connect io.out_valid, io.in_valid connect mac_unit.io.in_a, io.in_a reg last_s : UInt<1>, clock when io.in_valid : connect last_s, io.in_control.propagate node flip = neq(last_s, io.in_control.propagate) node shift_offset = mux(flip, io.in_control.shift, UInt<1>(0h0)) connect io.bad_dataflow, UInt<1>(0h0) node _T = eq(io.in_control.dataflow, UInt<1>(0h0)) node _T_1 = and(UInt<1>(0h0), _T) node _T_2 = or(UInt<1>(0h0), _T_1) when _T_2 : node _T_3 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_3 : node _io_out_c_point_five_T = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_1 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_2 = tail(_io_out_c_point_five_T_1, 1) node _io_out_c_point_five_T_3 = dshr(c1, _io_out_c_point_five_T_2) node _io_out_c_point_five_T_4 = bits(_io_out_c_point_five_T_3, 0, 0) node io_out_c_point_five = mux(_io_out_c_point_five_T, UInt<1>(0h0), _io_out_c_point_five_T_4) node _io_out_c_zeros_T = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_1 = asUInt(c1) node _io_out_c_zeros_T_2 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_3 = tail(_io_out_c_zeros_T_2, 1) node _io_out_c_zeros_T_4 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_3) node _io_out_c_zeros_T_5 = sub(_io_out_c_zeros_T_4, UInt<1>(0h1)) node _io_out_c_zeros_T_6 = tail(_io_out_c_zeros_T_5, 1) node _io_out_c_zeros_T_7 = and(_io_out_c_zeros_T_1, _io_out_c_zeros_T_6) node _io_out_c_zeros_T_8 = mux(_io_out_c_zeros_T, UInt<1>(0h0), _io_out_c_zeros_T_7) node io_out_c_zeros = neq(_io_out_c_zeros_T_8, UInt<1>(0h0)) node _io_out_c_ones_digit_T = dshr(c1, shift_offset) node io_out_c_ones_digit = bits(_io_out_c_ones_digit_T, 0, 0) node _io_out_c_r_T = or(io_out_c_zeros, io_out_c_ones_digit) node _io_out_c_r_T_1 = and(io_out_c_point_five, _io_out_c_r_T) node io_out_c_r = bits(_io_out_c_r_T_1, 0, 0) node _io_out_c_T = dshr(c1, shift_offset) node _io_out_c_T_1 = mux(io_out_c_r, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_2 = add(_io_out_c_T, _io_out_c_T_1) node _io_out_c_T_3 = tail(_io_out_c_T_2, 1) node _io_out_c_T_4 = asSInt(_io_out_c_T_3) node _io_out_c_T_5 = gt(_io_out_c_T_4, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_6 = lt(_io_out_c_T_4, asSInt(UInt<20>(0h80000))) node _io_out_c_T_7 = mux(_io_out_c_T_6, asSInt(UInt<20>(0h80000)), _io_out_c_T_4) node _io_out_c_T_8 = mux(_io_out_c_T_5, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_7) node _io_out_c_T_9 = bits(_io_out_c_T_8, 19, 0) node _io_out_c_T_10 = asSInt(_io_out_c_T_9) connect io.out_c, _io_out_c_T_10 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE : SInt<8> node _mac_unit_io_in_b_T = asUInt(io.in_b) node _mac_unit_io_in_b_T_1 = asSInt(_mac_unit_io_in_b_T) connect _mac_unit_io_in_b_WIRE, _mac_unit_io_in_b_T_1 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE connect mac_unit.io.in_c, c2 connect c2, mac_unit.io.out_d node _c1_T = bits(io.in_d, 7, 0) node _c1_T_1 = asSInt(_c1_T) connect c1, _c1_T_1 else : node _io_out_c_point_five_T_5 = eq(shift_offset, UInt<1>(0h0)) node _io_out_c_point_five_T_6 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_point_five_T_7 = tail(_io_out_c_point_five_T_6, 1) node _io_out_c_point_five_T_8 = dshr(c2, _io_out_c_point_five_T_7) node _io_out_c_point_five_T_9 = bits(_io_out_c_point_five_T_8, 0, 0) node io_out_c_point_five_1 = mux(_io_out_c_point_five_T_5, UInt<1>(0h0), _io_out_c_point_five_T_9) node _io_out_c_zeros_T_9 = leq(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_10 = asUInt(c2) node _io_out_c_zeros_T_11 = sub(shift_offset, UInt<1>(0h1)) node _io_out_c_zeros_T_12 = tail(_io_out_c_zeros_T_11, 1) node _io_out_c_zeros_T_13 = dshl(UInt<1>(0h1), _io_out_c_zeros_T_12) node _io_out_c_zeros_T_14 = sub(_io_out_c_zeros_T_13, UInt<1>(0h1)) node _io_out_c_zeros_T_15 = tail(_io_out_c_zeros_T_14, 1) node _io_out_c_zeros_T_16 = and(_io_out_c_zeros_T_10, _io_out_c_zeros_T_15) node _io_out_c_zeros_T_17 = mux(_io_out_c_zeros_T_9, UInt<1>(0h0), _io_out_c_zeros_T_16) node io_out_c_zeros_1 = neq(_io_out_c_zeros_T_17, UInt<1>(0h0)) node _io_out_c_ones_digit_T_1 = dshr(c2, shift_offset) node io_out_c_ones_digit_1 = bits(_io_out_c_ones_digit_T_1, 0, 0) node _io_out_c_r_T_2 = or(io_out_c_zeros_1, io_out_c_ones_digit_1) node _io_out_c_r_T_3 = and(io_out_c_point_five_1, _io_out_c_r_T_2) node io_out_c_r_1 = bits(_io_out_c_r_T_3, 0, 0) node _io_out_c_T_11 = dshr(c2, shift_offset) node _io_out_c_T_12 = mux(io_out_c_r_1, asSInt(UInt<2>(0h1)), asSInt(UInt<1>(0h0))) node _io_out_c_T_13 = add(_io_out_c_T_11, _io_out_c_T_12) node _io_out_c_T_14 = tail(_io_out_c_T_13, 1) node _io_out_c_T_15 = asSInt(_io_out_c_T_14) node _io_out_c_T_16 = gt(_io_out_c_T_15, asSInt(UInt<20>(0h7ffff))) node _io_out_c_T_17 = lt(_io_out_c_T_15, asSInt(UInt<20>(0h80000))) node _io_out_c_T_18 = mux(_io_out_c_T_17, asSInt(UInt<20>(0h80000)), _io_out_c_T_15) node _io_out_c_T_19 = mux(_io_out_c_T_16, asSInt(UInt<20>(0h7ffff)), _io_out_c_T_18) node _io_out_c_T_20 = bits(_io_out_c_T_19, 19, 0) node _io_out_c_T_21 = asSInt(_io_out_c_T_20) connect io.out_c, _io_out_c_T_21 connect io.out_b, io.in_b wire _mac_unit_io_in_b_WIRE_1 : SInt<8> node _mac_unit_io_in_b_T_2 = asUInt(io.in_b) node _mac_unit_io_in_b_T_3 = asSInt(_mac_unit_io_in_b_T_2) connect _mac_unit_io_in_b_WIRE_1, _mac_unit_io_in_b_T_3 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_1 connect mac_unit.io.in_c, c1 connect c1, mac_unit.io.out_d node _c2_T = bits(io.in_d, 7, 0) node _c2_T_1 = asSInt(_c2_T) connect c2, _c2_T_1 else : node _T_4 = eq(io.in_control.dataflow, UInt<1>(0h1)) node _T_5 = and(UInt<1>(0h0), _T_4) node _T_6 = or(UInt<1>(0h1), _T_5) when _T_6 : node _T_7 = eq(io.in_control.propagate, UInt<1>(0h1)) when _T_7 : connect io.out_c, c1 wire _mac_unit_io_in_b_WIRE_2 : SInt<8> node _mac_unit_io_in_b_T_4 = asUInt(c2) node _mac_unit_io_in_b_T_5 = asSInt(_mac_unit_io_in_b_T_4) connect _mac_unit_io_in_b_WIRE_2, _mac_unit_io_in_b_T_5 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_2 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c1, io.in_d else : connect io.out_c, c2 wire _mac_unit_io_in_b_WIRE_3 : SInt<8> node _mac_unit_io_in_b_T_6 = asUInt(c1) node _mac_unit_io_in_b_T_7 = asSInt(_mac_unit_io_in_b_T_6) connect _mac_unit_io_in_b_WIRE_3, _mac_unit_io_in_b_T_7 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_3 connect mac_unit.io.in_c, io.in_b connect io.out_b, mac_unit.io.out_d connect c2, io.in_d else : connect io.bad_dataflow, UInt<1>(0h1) invalidate io.out_c invalidate io.out_b wire _mac_unit_io_in_b_WIRE_4 : SInt<8> node _mac_unit_io_in_b_T_8 = asUInt(io.in_b) node _mac_unit_io_in_b_T_9 = asSInt(_mac_unit_io_in_b_T_8) connect _mac_unit_io_in_b_WIRE_4, _mac_unit_io_in_b_T_9 connect mac_unit.io.in_b, _mac_unit_io_in_b_WIRE_4 connect mac_unit.io.in_c, c2 node _T_8 = eq(io.in_valid, UInt<1>(0h0)) when _T_8 : connect c1, c1 connect c2, c2 invalidate mac_unit.io.in_b invalidate mac_unit.io.in_c
module PE_343( // @[PE.scala:31:7] input clock, // @[PE.scala:31:7] input reset, // @[PE.scala:31:7] input [7:0] io_in_a, // @[PE.scala:35:14] input [19:0] io_in_b, // @[PE.scala:35:14] input [19:0] io_in_d, // @[PE.scala:35:14] output [7:0] io_out_a, // @[PE.scala:35:14] output [19:0] io_out_b, // @[PE.scala:35:14] output [19:0] io_out_c, // @[PE.scala:35:14] input io_in_control_dataflow, // @[PE.scala:35:14] input io_in_control_propagate, // @[PE.scala:35:14] input [4:0] io_in_control_shift, // @[PE.scala:35:14] output io_out_control_dataflow, // @[PE.scala:35:14] output io_out_control_propagate, // @[PE.scala:35:14] output [4:0] io_out_control_shift, // @[PE.scala:35:14] input [2:0] io_in_id, // @[PE.scala:35:14] output [2:0] io_out_id, // @[PE.scala:35:14] input io_in_last, // @[PE.scala:35:14] output io_out_last, // @[PE.scala:35:14] input io_in_valid, // @[PE.scala:35:14] output io_out_valid // @[PE.scala:35:14] ); wire [7:0] io_in_a_0 = io_in_a; // @[PE.scala:31:7] wire [19:0] io_in_b_0 = io_in_b; // @[PE.scala:31:7] wire [19:0] io_in_d_0 = io_in_d; // @[PE.scala:31:7] wire io_in_control_dataflow_0 = io_in_control_dataflow; // @[PE.scala:31:7] wire io_in_control_propagate_0 = io_in_control_propagate; // @[PE.scala:31:7] wire [4:0] io_in_control_shift_0 = io_in_control_shift; // @[PE.scala:31:7] wire [2:0] io_in_id_0 = io_in_id; // @[PE.scala:31:7] wire io_in_last_0 = io_in_last; // @[PE.scala:31:7] wire io_in_valid_0 = io_in_valid; // @[PE.scala:31:7] wire io_bad_dataflow = 1'h0; // @[PE.scala:31:7] wire _io_out_c_T_5 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_6 = 1'h0; // @[Arithmetic.scala:125:60] wire _io_out_c_T_16 = 1'h0; // @[Arithmetic.scala:125:33] wire _io_out_c_T_17 = 1'h0; // @[Arithmetic.scala:125:60] wire [7:0] io_out_a_0 = io_in_a_0; // @[PE.scala:31:7] wire [19:0] _mac_unit_io_in_b_T = io_in_b_0; // @[PE.scala:31:7, :106:37] wire [19:0] _mac_unit_io_in_b_T_2 = io_in_b_0; // @[PE.scala:31:7, :113:37] wire [19:0] _mac_unit_io_in_b_T_8 = io_in_b_0; // @[PE.scala:31:7, :137:35] wire io_out_control_dataflow_0 = io_in_control_dataflow_0; // @[PE.scala:31:7] wire io_out_control_propagate_0 = io_in_control_propagate_0; // @[PE.scala:31:7] wire [4:0] io_out_control_shift_0 = io_in_control_shift_0; // @[PE.scala:31:7] wire [2:0] io_out_id_0 = io_in_id_0; // @[PE.scala:31:7] wire io_out_last_0 = io_in_last_0; // @[PE.scala:31:7] wire io_out_valid_0 = io_in_valid_0; // @[PE.scala:31:7] wire [19:0] io_out_b_0; // @[PE.scala:31:7] wire [19:0] io_out_c_0; // @[PE.scala:31:7] reg [7:0] c1; // @[PE.scala:70:15] wire [7:0] _io_out_c_zeros_T_1 = c1; // @[PE.scala:70:15] wire [7:0] _mac_unit_io_in_b_T_6 = c1; // @[PE.scala:70:15, :127:38] reg [7:0] c2; // @[PE.scala:71:15] wire [7:0] _io_out_c_zeros_T_10 = c2; // @[PE.scala:71:15] wire [7:0] _mac_unit_io_in_b_T_4 = c2; // @[PE.scala:71:15, :121:38] reg last_s; // @[PE.scala:89:25] wire flip = last_s != io_in_control_propagate_0; // @[PE.scala:31:7, :89:25, :90:21] wire [4:0] shift_offset = flip ? io_in_control_shift_0 : 5'h0; // @[PE.scala:31:7, :90:21, :91:25] wire _GEN = shift_offset == 5'h0; // @[PE.scala:91:25] wire _io_out_c_point_five_T; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T = _GEN; // @[Arithmetic.scala:101:32] wire _io_out_c_point_five_T_5; // @[Arithmetic.scala:101:32] assign _io_out_c_point_five_T_5 = _GEN; // @[Arithmetic.scala:101:32] wire [5:0] _GEN_0 = {1'h0, shift_offset} - 6'h1; // @[PE.scala:91:25] wire [5:0] _io_out_c_point_five_T_1; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_1 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_2; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_2 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [5:0] _io_out_c_point_five_T_6; // @[Arithmetic.scala:101:53] assign _io_out_c_point_five_T_6 = _GEN_0; // @[Arithmetic.scala:101:53] wire [5:0] _io_out_c_zeros_T_11; // @[Arithmetic.scala:102:66] assign _io_out_c_zeros_T_11 = _GEN_0; // @[Arithmetic.scala:101:53, :102:66] wire [4:0] _io_out_c_point_five_T_2 = _io_out_c_point_five_T_1[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_3 = $signed($signed(c1) >>> _io_out_c_point_five_T_2); // @[PE.scala:70:15] wire _io_out_c_point_five_T_4 = _io_out_c_point_five_T_3[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five = ~_io_out_c_point_five_T & _io_out_c_point_five_T_4; // @[Arithmetic.scala:101:{29,32,50}] wire _GEN_1 = shift_offset < 5'h2; // @[PE.scala:91:25] wire _io_out_c_zeros_T; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T = _GEN_1; // @[Arithmetic.scala:102:27] wire _io_out_c_zeros_T_9; // @[Arithmetic.scala:102:27] assign _io_out_c_zeros_T_9 = _GEN_1; // @[Arithmetic.scala:102:27] wire [4:0] _io_out_c_zeros_T_3 = _io_out_c_zeros_T_2[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_4 = 32'h1 << _io_out_c_zeros_T_3; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_5 = {1'h0, _io_out_c_zeros_T_4} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_6 = _io_out_c_zeros_T_5[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_7 = {24'h0, _io_out_c_zeros_T_6[7:0] & _io_out_c_zeros_T_1}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_8 = _io_out_c_zeros_T ? 32'h0 : _io_out_c_zeros_T_7; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros = |_io_out_c_zeros_T_8; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_2 = {3'h0, shift_offset}; // @[PE.scala:91:25] wire [7:0] _GEN_3 = $signed($signed(c1) >>> _GEN_2); // @[PE.scala:70:15] wire [7:0] _io_out_c_ones_digit_T; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T = _GEN_3; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T; // @[Arithmetic.scala:107:15] assign _io_out_c_T = _GEN_3; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit = _io_out_c_ones_digit_T[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T = io_out_c_zeros | io_out_c_ones_digit; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_1 = io_out_c_point_five & _io_out_c_r_T; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r = _io_out_c_r_T_1; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_1 = {1'h0, io_out_c_r}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_2 = {_io_out_c_T[7], _io_out_c_T} + {{7{_io_out_c_T_1[1]}}, _io_out_c_T_1}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_3 = _io_out_c_T_2[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_4 = _io_out_c_T_3; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_7 = {{12{_io_out_c_T_4[7]}}, _io_out_c_T_4}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_8 = _io_out_c_T_7; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_9 = _io_out_c_T_8; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_10 = _io_out_c_T_9; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_1 = _mac_unit_io_in_b_T; // @[PE.scala:106:37] wire [7:0] _mac_unit_io_in_b_WIRE = _mac_unit_io_in_b_T_1[7:0]; // @[PE.scala:106:37] wire [7:0] _c1_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c2_T = io_in_d_0[7:0]; // @[PE.scala:31:7] wire [7:0] _c1_T_1 = _c1_T; // @[Arithmetic.scala:114:{15,33}] wire [4:0] _io_out_c_point_five_T_7 = _io_out_c_point_five_T_6[4:0]; // @[Arithmetic.scala:101:53] wire [7:0] _io_out_c_point_five_T_8 = $signed($signed(c2) >>> _io_out_c_point_five_T_7); // @[PE.scala:71:15] wire _io_out_c_point_five_T_9 = _io_out_c_point_five_T_8[0]; // @[Arithmetic.scala:101:50] wire io_out_c_point_five_1 = ~_io_out_c_point_five_T_5 & _io_out_c_point_five_T_9; // @[Arithmetic.scala:101:{29,32,50}] wire [4:0] _io_out_c_zeros_T_12 = _io_out_c_zeros_T_11[4:0]; // @[Arithmetic.scala:102:66] wire [31:0] _io_out_c_zeros_T_13 = 32'h1 << _io_out_c_zeros_T_12; // @[Arithmetic.scala:102:{60,66}] wire [32:0] _io_out_c_zeros_T_14 = {1'h0, _io_out_c_zeros_T_13} - 33'h1; // @[Arithmetic.scala:102:{60,81}] wire [31:0] _io_out_c_zeros_T_15 = _io_out_c_zeros_T_14[31:0]; // @[Arithmetic.scala:102:81] wire [31:0] _io_out_c_zeros_T_16 = {24'h0, _io_out_c_zeros_T_15[7:0] & _io_out_c_zeros_T_10}; // @[Arithmetic.scala:102:{45,52,81}] wire [31:0] _io_out_c_zeros_T_17 = _io_out_c_zeros_T_9 ? 32'h0 : _io_out_c_zeros_T_16; // @[Arithmetic.scala:102:{24,27,52}] wire io_out_c_zeros_1 = |_io_out_c_zeros_T_17; // @[Arithmetic.scala:102:{24,89}] wire [7:0] _GEN_4 = $signed($signed(c2) >>> _GEN_2); // @[PE.scala:71:15] wire [7:0] _io_out_c_ones_digit_T_1; // @[Arithmetic.scala:103:30] assign _io_out_c_ones_digit_T_1 = _GEN_4; // @[Arithmetic.scala:103:30] wire [7:0] _io_out_c_T_11; // @[Arithmetic.scala:107:15] assign _io_out_c_T_11 = _GEN_4; // @[Arithmetic.scala:103:30, :107:15] wire io_out_c_ones_digit_1 = _io_out_c_ones_digit_T_1[0]; // @[Arithmetic.scala:103:30] wire _io_out_c_r_T_2 = io_out_c_zeros_1 | io_out_c_ones_digit_1; // @[Arithmetic.scala:102:89, :103:30, :105:38] wire _io_out_c_r_T_3 = io_out_c_point_five_1 & _io_out_c_r_T_2; // @[Arithmetic.scala:101:29, :105:{29,38}] wire io_out_c_r_1 = _io_out_c_r_T_3; // @[Arithmetic.scala:105:{29,53}] wire [1:0] _io_out_c_T_12 = {1'h0, io_out_c_r_1}; // @[Arithmetic.scala:105:53, :107:33] wire [8:0] _io_out_c_T_13 = {_io_out_c_T_11[7], _io_out_c_T_11} + {{7{_io_out_c_T_12[1]}}, _io_out_c_T_12}; // @[Arithmetic.scala:107:{15,28,33}] wire [7:0] _io_out_c_T_14 = _io_out_c_T_13[7:0]; // @[Arithmetic.scala:107:28] wire [7:0] _io_out_c_T_15 = _io_out_c_T_14; // @[Arithmetic.scala:107:28] wire [19:0] _io_out_c_T_18 = {{12{_io_out_c_T_15[7]}}, _io_out_c_T_15}; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_19 = _io_out_c_T_18; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_20 = _io_out_c_T_19; // @[Mux.scala:126:16] wire [19:0] _io_out_c_T_21 = _io_out_c_T_20; // @[Arithmetic.scala:125:{81,99}] wire [19:0] _mac_unit_io_in_b_T_3 = _mac_unit_io_in_b_T_2; // @[PE.scala:113:37] wire [7:0] _mac_unit_io_in_b_WIRE_1 = _mac_unit_io_in_b_T_3[7:0]; // @[PE.scala:113:37] wire [7:0] _c2_T_1 = _c2_T; // @[Arithmetic.scala:114:{15,33}] wire [7:0] _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign _mac_unit_io_in_b_T_5 = _mac_unit_io_in_b_T_4; // @[PE.scala:121:38] wire [7:0] _mac_unit_io_in_b_WIRE_2 = _mac_unit_io_in_b_T_5; // @[PE.scala:121:38] assign io_out_c_0 = io_in_control_propagate_0 ? {{12{c1[7]}}, c1} : {{12{c2[7]}}, c2}; // @[PE.scala:31:7, :70:15, :71:15, :119:30, :120:16, :126:16] wire [7:0] _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] assign _mac_unit_io_in_b_T_7 = _mac_unit_io_in_b_T_6; // @[PE.scala:127:38] wire [7:0] _mac_unit_io_in_b_WIRE_3 = _mac_unit_io_in_b_T_7; // @[PE.scala:127:38] wire [19:0] _mac_unit_io_in_b_T_9 = _mac_unit_io_in_b_T_8; // @[PE.scala:137:35] wire [7:0] _mac_unit_io_in_b_WIRE_4 = _mac_unit_io_in_b_T_9[7:0]; // @[PE.scala:137:35] always @(posedge clock) begin // @[PE.scala:31:7] if (io_in_valid_0 & io_in_control_propagate_0) // @[PE.scala:31:7, :102:95, :141:17, :142:8] c1 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :70:15] if (~(~io_in_valid_0 | io_in_control_propagate_0)) // @[PE.scala:31:7, :71:15, :102:95, :119:30, :130:10, :141:{9,17}, :143:8] c2 <= io_in_d_0[7:0]; // @[PE.scala:31:7, :71:15] if (io_in_valid_0) // @[PE.scala:31:7] last_s <= io_in_control_propagate_0; // @[PE.scala:31:7, :89:25] always @(posedge) MacUnit_87 mac_unit ( // @[PE.scala:64:24] .clock (clock), .reset (reset), .io_in_a (io_in_a_0), // @[PE.scala:31:7] .io_in_b (io_in_control_propagate_0 ? _mac_unit_io_in_b_WIRE_2 : _mac_unit_io_in_b_WIRE_3), // @[PE.scala:31:7, :119:30, :121:{24,38}, :127:{24,38}] .io_in_c (io_in_b_0), // @[PE.scala:31:7] .io_out_d (io_out_b_0) ); // @[PE.scala:64:24] assign io_out_a = io_out_a_0; // @[PE.scala:31:7] assign io_out_b = io_out_b_0; // @[PE.scala:31:7] assign io_out_c = io_out_c_0; // @[PE.scala:31:7] assign io_out_control_dataflow = io_out_control_dataflow_0; // @[PE.scala:31:7] assign io_out_control_propagate = io_out_control_propagate_0; // @[PE.scala:31:7] assign io_out_control_shift = io_out_control_shift_0; // @[PE.scala:31:7] assign io_out_id = io_out_id_0; // @[PE.scala:31:7] assign io_out_last = io_out_last_0; // @[PE.scala:31:7] assign io_out_valid = io_out_valid_0; // @[PE.scala:31:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BundleBridgeNexus_UInt1_1 : output auto : { out : UInt<1>} wire childClock : Clock wire childReset : Reset node _childClock_T = asClock(UInt<1>(0h0)) connect childClock, _childClock_T invalidate childReset wire nodeOut : UInt<1> invalidate nodeOut connect auto.out, nodeOut node outputs_0 = or(UInt<1>(0h0), UInt<1>(0h0)) connect nodeOut, outputs_0
module BundleBridgeNexus_UInt1_1( // @[BundleBridgeNexus.scala:20:9] output auto_out // @[LazyModuleImp.scala:107:25] ); wire childClock = 1'h0; // @[LazyModuleImp.scala:155:31] wire childReset = 1'h0; // @[LazyModuleImp.scala:158:31] wire _childClock_T = 1'h0; // @[LazyModuleImp.scala:160:25] wire nodeOut; // @[MixedNode.scala:542:17] wire outputs_0 = 1'h0; // @[HasTiles.scala:78:32] assign nodeOut = outputs_0; // @[HasTiles.scala:78:32] assign auto_out = nodeOut; // @[MixedNode.scala:542:17] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MSHR_1 : input clock : Clock input reset : Reset output io : { flip allocate : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, repeat : UInt<1>}}, flip directory : { valid : UInt<1>, bits : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}}, status : { valid : UInt<1>, bits : { set : UInt<10>, tag : UInt<13>, way : UInt<3>, blockB : UInt<1>, nestB : UInt<1>, blockC : UInt<1>, nestC : UInt<1>}}, schedule : { flip ready : UInt<1>, valid : UInt<1>, bits : { a : { valid : UInt<1>, bits : { tag : UInt<13>, set : UInt<10>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<13>, set : UInt<10>, clients : UInt<4>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<13>, set : UInt<10>, way : UInt<3>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>, sink : UInt<4>, way : UInt<3>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<10>, way : UInt<3>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>}}}, reload : UInt<1>}}, flip sinkc : { valid : UInt<1>, bits : { last : UInt<1>, set : UInt<10>, tag : UInt<13>, source : UInt<7>, param : UInt<3>, data : UInt<1>}}, flip sinkd : { valid : UInt<1>, bits : { last : UInt<1>, opcode : UInt<3>, param : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>}}, flip sinke : { valid : UInt<1>, bits : { sink : UInt<4>}}, flip nestedwb : { set : UInt<10>, tag : UInt<13>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>}} regreset request_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg request : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>}, clock regreset meta_valid : UInt<1>, clock, reset, UInt<1>(0h0) reg meta : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>}, clock when meta_valid : node _T = eq(meta.state, UInt<2>(0h0)) when _T : node _T_1 = orr(meta.clients) node _T_2 = eq(_T_1, UInt<1>(0h0)) node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : node _T_5 = eq(_T_2, UInt<1>(0h0)) when _T_5 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:105 assert (!meta.clients.orR)\n") : printf assert(clock, _T_2, UInt<1>(0h1), "") : assert node _T_6 = eq(meta.dirty, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:106 assert (!meta.dirty)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = eq(meta.state, UInt<2>(0h1)) when _T_10 : node _T_11 = eq(meta.dirty, UInt<1>(0h0)) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:109 assert (!meta.dirty)\n") : printf_2 assert(clock, _T_11, UInt<1>(0h1), "") : assert_2 node _T_15 = eq(meta.state, UInt<2>(0h2)) when _T_15 : node _T_16 = orr(meta.clients) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:112 assert (meta.clients.orR)\n") : printf_3 assert(clock, _T_16, UInt<1>(0h1), "") : assert_3 node _T_20 = sub(meta.clients, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = and(meta.clients, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = asUInt(reset) node _T_25 = eq(_T_24, UInt<1>(0h0)) when _T_25 : node _T_26 = eq(_T_23, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:113 assert ((meta.clients & (meta.clients - 1.U)) === 0.U) // at most one\n") : printf_4 assert(clock, _T_23, UInt<1>(0h1), "") : assert_4 node _T_27 = eq(meta.state, UInt<2>(0h3)) when _T_27 : skip regreset s_rprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_rprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_release : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_releaseack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_pprobe : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_acquire : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_flush : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantlast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grant : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeackfirst : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeacklast : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_pprobeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_probeack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_execute : UInt<1>, clock, reset, UInt<1>(0h1) regreset w_grantack : UInt<1>, clock, reset, UInt<1>(0h1) regreset s_writeback : UInt<1>, clock, reset, UInt<1>(0h1) reg sink : UInt<3>, clock reg gotT : UInt<1>, clock reg bad_grant : UInt<1>, clock reg probes_done : UInt<4>, clock reg probes_toN : UInt<4>, clock reg probes_noT : UInt<1>, clock node _T_28 = neq(meta.state, UInt<2>(0h0)) node _T_29 = and(meta_valid, _T_28) node _T_30 = eq(io.nestedwb.set, request.set) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.nestedwb.tag, meta.tag) node _T_33 = and(_T_31, _T_32) when _T_33 : when io.nestedwb.b_clr_dirty : connect meta.dirty, UInt<1>(0h0) when io.nestedwb.c_set_dirty : connect meta.dirty, UInt<1>(0h1) when io.nestedwb.b_toB : connect meta.state, UInt<2>(0h1) when io.nestedwb.b_toN : connect meta.hit, UInt<1>(0h0) connect io.status.valid, request_valid connect io.status.bits.set, request.set connect io.status.bits.tag, request.tag connect io.status.bits.way, meta.way node _io_status_bits_blockB_T = eq(meta_valid, UInt<1>(0h0)) node _io_status_bits_blockB_T_1 = eq(w_releaseack, UInt<1>(0h0)) node _io_status_bits_blockB_T_2 = eq(w_rprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_3 = or(_io_status_bits_blockB_T_1, _io_status_bits_blockB_T_2) node _io_status_bits_blockB_T_4 = eq(w_pprobeacklast, UInt<1>(0h0)) node _io_status_bits_blockB_T_5 = or(_io_status_bits_blockB_T_3, _io_status_bits_blockB_T_4) node _io_status_bits_blockB_T_6 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_blockB_T_7 = and(_io_status_bits_blockB_T_5, _io_status_bits_blockB_T_6) node _io_status_bits_blockB_T_8 = or(_io_status_bits_blockB_T, _io_status_bits_blockB_T_7) connect io.status.bits.blockB, _io_status_bits_blockB_T_8 node _io_status_bits_nestB_T = and(meta_valid, w_releaseack) node _io_status_bits_nestB_T_1 = and(_io_status_bits_nestB_T, w_rprobeacklast) node _io_status_bits_nestB_T_2 = and(_io_status_bits_nestB_T_1, w_pprobeacklast) node _io_status_bits_nestB_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestB_T_4 = and(_io_status_bits_nestB_T_2, _io_status_bits_nestB_T_3) connect io.status.bits.nestB, _io_status_bits_nestB_T_4 node _io_status_bits_blockC_T = eq(meta_valid, UInt<1>(0h0)) connect io.status.bits.blockC, _io_status_bits_blockC_T node _io_status_bits_nestC_T = eq(w_rprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_1 = eq(w_pprobeackfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_2 = or(_io_status_bits_nestC_T, _io_status_bits_nestC_T_1) node _io_status_bits_nestC_T_3 = eq(w_grantfirst, UInt<1>(0h0)) node _io_status_bits_nestC_T_4 = or(_io_status_bits_nestC_T_2, _io_status_bits_nestC_T_3) node _io_status_bits_nestC_T_5 = and(meta_valid, _io_status_bits_nestC_T_4) connect io.status.bits.nestC, _io_status_bits_nestC_T_5 node _T_34 = eq(io.status.bits.nestB, UInt<1>(0h0)) node _T_35 = eq(io.status.bits.blockB, UInt<1>(0h0)) node _T_36 = or(_T_34, _T_35) node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : node _T_39 = eq(_T_36, UInt<1>(0h0)) when _T_39 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:179 assert (!io.status.bits.nestB || !io.status.bits.blockB)\n") : printf_5 assert(clock, _T_36, UInt<1>(0h1), "") : assert_5 node _T_40 = eq(io.status.bits.nestC, UInt<1>(0h0)) node _T_41 = eq(io.status.bits.blockC, UInt<1>(0h0)) node _T_42 = or(_T_40, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:180 assert (!io.status.bits.nestC || !io.status.bits.blockC)\n") : printf_6 assert(clock, _T_42, UInt<1>(0h1), "") : assert_6 node _no_wait_T = and(w_rprobeacklast, w_releaseack) node _no_wait_T_1 = and(_no_wait_T, w_grantlast) node _no_wait_T_2 = and(_no_wait_T_1, w_pprobeacklast) node no_wait = and(_no_wait_T_2, w_grantack) node _io_schedule_bits_a_valid_T = eq(s_acquire, UInt<1>(0h0)) node _io_schedule_bits_a_valid_T_1 = and(_io_schedule_bits_a_valid_T, s_release) node _io_schedule_bits_a_valid_T_2 = and(_io_schedule_bits_a_valid_T_1, s_pprobe) connect io.schedule.bits.a.valid, _io_schedule_bits_a_valid_T_2 node _io_schedule_bits_b_valid_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_1 = eq(s_pprobe, UInt<1>(0h0)) node _io_schedule_bits_b_valid_T_2 = or(_io_schedule_bits_b_valid_T, _io_schedule_bits_b_valid_T_1) connect io.schedule.bits.b.valid, _io_schedule_bits_b_valid_T_2 node _io_schedule_bits_c_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_1 = and(_io_schedule_bits_c_valid_T, w_rprobeackfirst) node _io_schedule_bits_c_valid_T_2 = eq(s_probeack, UInt<1>(0h0)) node _io_schedule_bits_c_valid_T_3 = and(_io_schedule_bits_c_valid_T_2, w_pprobeackfirst) node _io_schedule_bits_c_valid_T_4 = or(_io_schedule_bits_c_valid_T_1, _io_schedule_bits_c_valid_T_3) connect io.schedule.bits.c.valid, _io_schedule_bits_c_valid_T_4 node _io_schedule_bits_d_valid_T = eq(s_execute, UInt<1>(0h0)) node _io_schedule_bits_d_valid_T_1 = and(_io_schedule_bits_d_valid_T, w_pprobeack) node _io_schedule_bits_d_valid_T_2 = and(_io_schedule_bits_d_valid_T_1, w_grant) connect io.schedule.bits.d.valid, _io_schedule_bits_d_valid_T_2 node _io_schedule_bits_e_valid_T = eq(s_grantack, UInt<1>(0h0)) node _io_schedule_bits_e_valid_T_1 = and(_io_schedule_bits_e_valid_T, w_grantfirst) connect io.schedule.bits.e.valid, _io_schedule_bits_e_valid_T_1 node _io_schedule_bits_x_valid_T = eq(s_flush, UInt<1>(0h0)) node _io_schedule_bits_x_valid_T_1 = and(_io_schedule_bits_x_valid_T, w_releaseack) connect io.schedule.bits.x.valid, _io_schedule_bits_x_valid_T_1 node _io_schedule_bits_dir_valid_T = eq(s_release, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_1 = and(_io_schedule_bits_dir_valid_T, w_rprobeackfirst) node _io_schedule_bits_dir_valid_T_2 = eq(s_writeback, UInt<1>(0h0)) node _io_schedule_bits_dir_valid_T_3 = and(_io_schedule_bits_dir_valid_T_2, no_wait) node _io_schedule_bits_dir_valid_T_4 = or(_io_schedule_bits_dir_valid_T_1, _io_schedule_bits_dir_valid_T_3) connect io.schedule.bits.dir.valid, _io_schedule_bits_dir_valid_T_4 connect io.schedule.bits.reload, no_wait node _io_schedule_valid_T = or(io.schedule.bits.a.valid, io.schedule.bits.b.valid) node _io_schedule_valid_T_1 = or(_io_schedule_valid_T, io.schedule.bits.c.valid) node _io_schedule_valid_T_2 = or(_io_schedule_valid_T_1, io.schedule.bits.d.valid) node _io_schedule_valid_T_3 = or(_io_schedule_valid_T_2, io.schedule.bits.e.valid) node _io_schedule_valid_T_4 = or(_io_schedule_valid_T_3, io.schedule.bits.x.valid) node _io_schedule_valid_T_5 = or(_io_schedule_valid_T_4, io.schedule.bits.dir.valid) connect io.schedule.valid, _io_schedule_valid_T_5 when io.schedule.ready : connect s_rprobe, UInt<1>(0h1) when w_rprobeackfirst : connect s_release, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) node _T_46 = and(s_release, s_pprobe) when _T_46 : connect s_acquire, UInt<1>(0h1) when w_releaseack : connect s_flush, UInt<1>(0h1) when w_pprobeackfirst : connect s_probeack, UInt<1>(0h1) when w_grantfirst : connect s_grantack, UInt<1>(0h1) node _T_47 = and(w_pprobeack, w_grant) when _T_47 : connect s_execute, UInt<1>(0h1) when no_wait : connect s_writeback, UInt<1>(0h1) when no_wait : connect request_valid, UInt<1>(0h0) connect meta_valid, UInt<1>(0h0) wire final_meta_writeback : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>, hit : UInt<1>, way : UInt<3>} connect final_meta_writeback, meta node _req_clientBit_T = eq(request.source, UInt<7>(0h44)) node _req_clientBit_T_1 = eq(request.source, UInt<7>(0h40)) node _req_clientBit_uncommonBits_T = or(request.source, UInt<3>(0h0)) node req_clientBit_uncommonBits = bits(_req_clientBit_uncommonBits_T, 2, 0) node _req_clientBit_T_2 = shr(request.source, 3) node _req_clientBit_T_3 = eq(_req_clientBit_T_2, UInt<3>(0h6)) node _req_clientBit_T_4 = leq(UInt<1>(0h0), req_clientBit_uncommonBits) node _req_clientBit_T_5 = and(_req_clientBit_T_3, _req_clientBit_T_4) node _req_clientBit_T_6 = leq(req_clientBit_uncommonBits, UInt<3>(0h4)) node _req_clientBit_T_7 = and(_req_clientBit_T_5, _req_clientBit_T_6) node _req_clientBit_uncommonBits_T_1 = or(request.source, UInt<3>(0h0)) node req_clientBit_uncommonBits_1 = bits(_req_clientBit_uncommonBits_T_1, 2, 0) node _req_clientBit_T_8 = shr(request.source, 3) node _req_clientBit_T_9 = eq(_req_clientBit_T_8, UInt<3>(0h4)) node _req_clientBit_T_10 = leq(UInt<1>(0h0), req_clientBit_uncommonBits_1) node _req_clientBit_T_11 = and(_req_clientBit_T_9, _req_clientBit_T_10) node _req_clientBit_T_12 = leq(req_clientBit_uncommonBits_1, UInt<3>(0h4)) node _req_clientBit_T_13 = and(_req_clientBit_T_11, _req_clientBit_T_12) node req_clientBit_lo = cat(_req_clientBit_T_1, _req_clientBit_T) node req_clientBit_hi = cat(_req_clientBit_T_13, _req_clientBit_T_7) node req_clientBit = cat(req_clientBit_hi, req_clientBit_lo) node _req_needT_T = bits(request.opcode, 2, 2) node _req_needT_T_1 = eq(_req_needT_T, UInt<1>(0h0)) node _req_needT_T_2 = eq(request.opcode, UInt<3>(0h5)) node _req_needT_T_3 = eq(request.param, UInt<1>(0h1)) node _req_needT_T_4 = and(_req_needT_T_2, _req_needT_T_3) node _req_needT_T_5 = or(_req_needT_T_1, _req_needT_T_4) node _req_needT_T_6 = eq(request.opcode, UInt<3>(0h6)) node _req_needT_T_7 = eq(request.opcode, UInt<3>(0h7)) node _req_needT_T_8 = or(_req_needT_T_6, _req_needT_T_7) node _req_needT_T_9 = neq(request.param, UInt<2>(0h0)) node _req_needT_T_10 = and(_req_needT_T_8, _req_needT_T_9) node req_needT = or(_req_needT_T_5, _req_needT_T_10) node _req_acquire_T = eq(request.opcode, UInt<3>(0h6)) node _req_acquire_T_1 = eq(request.opcode, UInt<3>(0h7)) node req_acquire = or(_req_acquire_T, _req_acquire_T_1) node _meta_no_clients_T = orr(meta.clients) node meta_no_clients = eq(_meta_no_clients_T, UInt<1>(0h0)) node _req_promoteT_T = eq(meta.state, UInt<2>(0h3)) node _req_promoteT_T_1 = and(meta_no_clients, _req_promoteT_T) node _req_promoteT_T_2 = mux(meta.hit, _req_promoteT_T_1, gotT) node req_promoteT = and(req_acquire, _req_promoteT_T_2) node _T_48 = and(request.prio[2], UInt<1>(0h1)) when _T_48 : node _final_meta_writeback_dirty_T = bits(request.opcode, 0, 0) node _final_meta_writeback_dirty_T_1 = or(meta.dirty, _final_meta_writeback_dirty_T) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_1 node _final_meta_writeback_state_T = neq(request.param, UInt<3>(0h3)) node _final_meta_writeback_state_T_1 = eq(meta.state, UInt<2>(0h2)) node _final_meta_writeback_state_T_2 = and(_final_meta_writeback_state_T, _final_meta_writeback_state_T_1) node _final_meta_writeback_state_T_3 = mux(_final_meta_writeback_state_T_2, UInt<2>(0h3), meta.state) connect final_meta_writeback.state, _final_meta_writeback_state_T_3 node _final_meta_writeback_clients_T = eq(request.param, UInt<3>(0h1)) node _final_meta_writeback_clients_T_1 = eq(request.param, UInt<3>(0h2)) node _final_meta_writeback_clients_T_2 = or(_final_meta_writeback_clients_T, _final_meta_writeback_clients_T_1) node _final_meta_writeback_clients_T_3 = eq(request.param, UInt<3>(0h5)) node _final_meta_writeback_clients_T_4 = or(_final_meta_writeback_clients_T_2, _final_meta_writeback_clients_T_3) node _final_meta_writeback_clients_T_5 = mux(_final_meta_writeback_clients_T_4, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_6 = not(_final_meta_writeback_clients_T_5) node _final_meta_writeback_clients_T_7 = and(meta.clients, _final_meta_writeback_clients_T_6) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_7 connect final_meta_writeback.hit, UInt<1>(0h1) else : node _T_49 = and(request.control, UInt<1>(0h1)) when _T_49 : when meta.hit : connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) node _final_meta_writeback_clients_T_8 = not(probes_toN) node _final_meta_writeback_clients_T_9 = and(meta.clients, _final_meta_writeback_clients_T_8) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_9 connect final_meta_writeback.hit, UInt<1>(0h0) else : node _final_meta_writeback_dirty_T_2 = and(meta.hit, meta.dirty) node _final_meta_writeback_dirty_T_3 = bits(request.opcode, 2, 2) node _final_meta_writeback_dirty_T_4 = eq(_final_meta_writeback_dirty_T_3, UInt<1>(0h0)) node _final_meta_writeback_dirty_T_5 = or(_final_meta_writeback_dirty_T_2, _final_meta_writeback_dirty_T_4) connect final_meta_writeback.dirty, _final_meta_writeback_dirty_T_5 node _final_meta_writeback_state_T_4 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_5 = eq(meta.hit, UInt<1>(0h0)) node _final_meta_writeback_state_T_6 = mux(req_acquire, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_7 = mux(gotT, _final_meta_writeback_state_T_6, UInt<2>(0h1)) node _final_meta_writeback_state_T_8 = and(meta_no_clients, req_acquire) node _final_meta_writeback_state_T_9 = mux(_final_meta_writeback_state_T_8, UInt<2>(0h2), UInt<2>(0h3)) node _final_meta_writeback_state_T_10 = eq(UInt<2>(0h1), meta.state) node _final_meta_writeback_state_T_11 = mux(_final_meta_writeback_state_T_10, UInt<2>(0h1), UInt<2>(0h1)) node _final_meta_writeback_state_T_12 = eq(UInt<2>(0h2), meta.state) node _final_meta_writeback_state_T_13 = mux(_final_meta_writeback_state_T_12, UInt<2>(0h3), _final_meta_writeback_state_T_11) node _final_meta_writeback_state_T_14 = eq(UInt<2>(0h3), meta.state) node _final_meta_writeback_state_T_15 = mux(_final_meta_writeback_state_T_14, _final_meta_writeback_state_T_9, _final_meta_writeback_state_T_13) node _final_meta_writeback_state_T_16 = mux(_final_meta_writeback_state_T_5, _final_meta_writeback_state_T_7, _final_meta_writeback_state_T_15) node _final_meta_writeback_state_T_17 = mux(req_needT, _final_meta_writeback_state_T_4, _final_meta_writeback_state_T_16) connect final_meta_writeback.state, _final_meta_writeback_state_T_17 node _final_meta_writeback_clients_T_10 = not(probes_toN) node _final_meta_writeback_clients_T_11 = and(meta.clients, _final_meta_writeback_clients_T_10) node _final_meta_writeback_clients_T_12 = mux(meta.hit, _final_meta_writeback_clients_T_11, UInt<1>(0h0)) node _final_meta_writeback_clients_T_13 = mux(req_acquire, req_clientBit, UInt<1>(0h0)) node _final_meta_writeback_clients_T_14 = or(_final_meta_writeback_clients_T_12, _final_meta_writeback_clients_T_13) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_14 connect final_meta_writeback.tag, request.tag connect final_meta_writeback.hit, UInt<1>(0h1) when bad_grant : when meta.hit : node _T_50 = eq(meta_valid, UInt<1>(0h0)) node _T_51 = eq(meta.state, UInt<2>(0h1)) node _T_52 = or(_T_50, _T_51) node _T_53 = asUInt(reset) node _T_54 = eq(_T_53, UInt<1>(0h0)) when _T_54 : node _T_55 = eq(_T_52, UInt<1>(0h0)) when _T_55 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:254 assert (!meta_valid || meta.state === BRANCH)\n") : printf_7 assert(clock, _T_52, UInt<1>(0h1), "") : assert_7 connect final_meta_writeback.hit, UInt<1>(0h1) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h1) node _final_meta_writeback_clients_T_15 = not(probes_toN) node _final_meta_writeback_clients_T_16 = and(meta.clients, _final_meta_writeback_clients_T_15) connect final_meta_writeback.clients, _final_meta_writeback_clients_T_16 else : connect final_meta_writeback.hit, UInt<1>(0h0) connect final_meta_writeback.dirty, UInt<1>(0h0) connect final_meta_writeback.state, UInt<2>(0h0) connect final_meta_writeback.clients, UInt<1>(0h0) wire invalid : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>} connect invalid.dirty, UInt<1>(0h0) connect invalid.state, UInt<2>(0h0) connect invalid.clients, UInt<1>(0h0) connect invalid.tag, UInt<1>(0h0) node _honour_BtoT_T = and(meta.clients, req_clientBit) node _honour_BtoT_T_1 = orr(_honour_BtoT_T) node honour_BtoT = and(meta.hit, _honour_BtoT_T_1) node _excluded_client_T = and(meta.hit, request.prio[0]) node _excluded_client_T_1 = eq(request.opcode, UInt<3>(0h6)) node _excluded_client_T_2 = eq(request.opcode, UInt<3>(0h7)) node _excluded_client_T_3 = or(_excluded_client_T_1, _excluded_client_T_2) node _excluded_client_T_4 = eq(request.opcode, UInt<3>(0h4)) node _excluded_client_T_5 = or(_excluded_client_T_3, _excluded_client_T_4) node _excluded_client_T_6 = eq(request.opcode, UInt<3>(0h5)) node _excluded_client_T_7 = and(_excluded_client_T_6, UInt<1>(0h0)) node _excluded_client_T_8 = or(_excluded_client_T_5, _excluded_client_T_7) node _excluded_client_T_9 = and(_excluded_client_T, _excluded_client_T_8) node excluded_client = mux(_excluded_client_T_9, req_clientBit, UInt<1>(0h0)) connect io.schedule.bits.a.bits.tag, request.tag connect io.schedule.bits.a.bits.set, request.set node _io_schedule_bits_a_bits_param_T = mux(meta.hit, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_a_bits_param_T_1 = mux(req_needT, _io_schedule_bits_a_bits_param_T, UInt<2>(0h0)) connect io.schedule.bits.a.bits.param, _io_schedule_bits_a_bits_param_T_1 node _io_schedule_bits_a_bits_block_T = neq(request.size, UInt<3>(0h6)) node _io_schedule_bits_a_bits_block_T_1 = eq(request.opcode, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_2 = eq(request.opcode, UInt<3>(0h7)) node _io_schedule_bits_a_bits_block_T_3 = or(_io_schedule_bits_a_bits_block_T_1, _io_schedule_bits_a_bits_block_T_2) node _io_schedule_bits_a_bits_block_T_4 = eq(_io_schedule_bits_a_bits_block_T_3, UInt<1>(0h0)) node _io_schedule_bits_a_bits_block_T_5 = or(_io_schedule_bits_a_bits_block_T, _io_schedule_bits_a_bits_block_T_4) connect io.schedule.bits.a.bits.block, _io_schedule_bits_a_bits_block_T_5 connect io.schedule.bits.a.bits.source, UInt<1>(0h0) node _io_schedule_bits_b_bits_param_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_param_T_1 = mux(req_needT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_b_bits_param_T_2 = mux(request.prio[1], request.param, _io_schedule_bits_b_bits_param_T_1) node _io_schedule_bits_b_bits_param_T_3 = mux(_io_schedule_bits_b_bits_param_T, UInt<2>(0h2), _io_schedule_bits_b_bits_param_T_2) connect io.schedule.bits.b.bits.param, _io_schedule_bits_b_bits_param_T_3 node _io_schedule_bits_b_bits_tag_T = eq(s_rprobe, UInt<1>(0h0)) node _io_schedule_bits_b_bits_tag_T_1 = mux(_io_schedule_bits_b_bits_tag_T, meta.tag, request.tag) connect io.schedule.bits.b.bits.tag, _io_schedule_bits_b_bits_tag_T_1 connect io.schedule.bits.b.bits.set, request.set node _io_schedule_bits_b_bits_clients_T = not(excluded_client) node _io_schedule_bits_b_bits_clients_T_1 = and(meta.clients, _io_schedule_bits_b_bits_clients_T) connect io.schedule.bits.b.bits.clients, _io_schedule_bits_b_bits_clients_T_1 node _io_schedule_bits_c_bits_opcode_T = mux(meta.dirty, UInt<3>(0h7), UInt<3>(0h6)) connect io.schedule.bits.c.bits.opcode, _io_schedule_bits_c_bits_opcode_T node _io_schedule_bits_c_bits_param_T = eq(meta.state, UInt<2>(0h1)) node _io_schedule_bits_c_bits_param_T_1 = mux(_io_schedule_bits_c_bits_param_T, UInt<3>(0h2), UInt<3>(0h1)) connect io.schedule.bits.c.bits.param, _io_schedule_bits_c_bits_param_T_1 connect io.schedule.bits.c.bits.source, UInt<1>(0h0) connect io.schedule.bits.c.bits.tag, meta.tag connect io.schedule.bits.c.bits.set, request.set connect io.schedule.bits.c.bits.way, meta.way connect io.schedule.bits.c.bits.dirty, meta.dirty connect io.schedule.bits.d.bits.set, request.set connect io.schedule.bits.d.bits.put, request.put connect io.schedule.bits.d.bits.offset, request.offset connect io.schedule.bits.d.bits.tag, request.tag connect io.schedule.bits.d.bits.source, request.source connect io.schedule.bits.d.bits.size, request.size connect io.schedule.bits.d.bits.param, request.param connect io.schedule.bits.d.bits.opcode, request.opcode connect io.schedule.bits.d.bits.control, request.control connect io.schedule.bits.d.bits.prio, request.prio node _io_schedule_bits_d_bits_param_T = eq(req_acquire, UInt<1>(0h0)) node _io_schedule_bits_d_bits_param_T_1 = mux(req_promoteT, UInt<2>(0h1), UInt<2>(0h0)) node _io_schedule_bits_d_bits_param_T_2 = mux(honour_BtoT, UInt<2>(0h2), UInt<2>(0h1)) node _io_schedule_bits_d_bits_param_T_3 = eq(UInt<2>(0h0), request.param) node _io_schedule_bits_d_bits_param_T_4 = mux(_io_schedule_bits_d_bits_param_T_3, _io_schedule_bits_d_bits_param_T_1, request.param) node _io_schedule_bits_d_bits_param_T_5 = eq(UInt<2>(0h2), request.param) node _io_schedule_bits_d_bits_param_T_6 = mux(_io_schedule_bits_d_bits_param_T_5, _io_schedule_bits_d_bits_param_T_2, _io_schedule_bits_d_bits_param_T_4) node _io_schedule_bits_d_bits_param_T_7 = eq(UInt<2>(0h1), request.param) node _io_schedule_bits_d_bits_param_T_8 = mux(_io_schedule_bits_d_bits_param_T_7, UInt<2>(0h1), _io_schedule_bits_d_bits_param_T_6) node _io_schedule_bits_d_bits_param_T_9 = mux(_io_schedule_bits_d_bits_param_T, request.param, _io_schedule_bits_d_bits_param_T_8) connect io.schedule.bits.d.bits.param, _io_schedule_bits_d_bits_param_T_9 connect io.schedule.bits.d.bits.sink, UInt<1>(0h0) connect io.schedule.bits.d.bits.way, meta.way connect io.schedule.bits.d.bits.bad, bad_grant connect io.schedule.bits.e.bits.sink, sink connect io.schedule.bits.x.bits.fail, UInt<1>(0h0) connect io.schedule.bits.dir.bits.set, request.set connect io.schedule.bits.dir.bits.way, meta.way node _io_schedule_bits_dir_bits_data_T = eq(s_release, UInt<1>(0h0)) wire _io_schedule_bits_dir_bits_data_WIRE : { dirty : UInt<1>, state : UInt<2>, clients : UInt<4>, tag : UInt<13>} connect _io_schedule_bits_dir_bits_data_WIRE.tag, final_meta_writeback.tag connect _io_schedule_bits_dir_bits_data_WIRE.clients, final_meta_writeback.clients connect _io_schedule_bits_dir_bits_data_WIRE.state, final_meta_writeback.state connect _io_schedule_bits_dir_bits_data_WIRE.dirty, final_meta_writeback.dirty node _io_schedule_bits_dir_bits_data_T_1 = mux(_io_schedule_bits_dir_bits_data_T, invalid, _io_schedule_bits_dir_bits_data_WIRE) connect io.schedule.bits.dir.bits.data, _io_schedule_bits_dir_bits_data_T_1 node _evict_T = eq(meta.hit, UInt<1>(0h0)) wire evict : UInt connect evict, UInt<1>(0h0) node evict_c = orr(meta.clients) node _evict_T_1 = eq(UInt<2>(0h1), meta.state) when _evict_T_1 : node _evict_out_T = mux(evict_c, UInt<1>(0h0), UInt<1>(0h1)) connect evict, _evict_out_T else : node _evict_T_2 = eq(UInt<2>(0h2), meta.state) when _evict_T_2 : node _evict_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect evict, _evict_out_T_1 else : node _evict_T_3 = eq(UInt<2>(0h3), meta.state) when _evict_T_3 : node _evict_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _evict_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _evict_out_T_4 = mux(evict_c, _evict_out_T_2, _evict_out_T_3) connect evict, _evict_out_T_4 else : node _evict_T_4 = eq(UInt<2>(0h0), meta.state) when _evict_T_4 : connect evict, UInt<4>(0h8) node _evict_T_5 = eq(_evict_T, UInt<1>(0h0)) when _evict_T_5 : connect evict, UInt<4>(0h8) wire before : UInt connect before, UInt<1>(0h0) node before_c = orr(meta.clients) node _before_T = eq(UInt<2>(0h1), meta.state) when _before_T : node _before_out_T = mux(before_c, UInt<1>(0h0), UInt<1>(0h1)) connect before, _before_out_T else : node _before_T_1 = eq(UInt<2>(0h2), meta.state) when _before_T_1 : node _before_out_T_1 = mux(meta.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect before, _before_out_T_1 else : node _before_T_2 = eq(UInt<2>(0h3), meta.state) when _before_T_2 : node _before_out_T_2 = mux(meta.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _before_out_T_3 = mux(meta.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _before_out_T_4 = mux(before_c, _before_out_T_2, _before_out_T_3) connect before, _before_out_T_4 else : node _before_T_3 = eq(UInt<2>(0h0), meta.state) when _before_T_3 : connect before, UInt<4>(0h8) node _before_T_4 = eq(meta.hit, UInt<1>(0h0)) when _before_T_4 : connect before, UInt<4>(0h8) wire after : UInt connect after, UInt<1>(0h0) node after_c = orr(final_meta_writeback.clients) node _after_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _after_T : node _after_out_T = mux(after_c, UInt<1>(0h0), UInt<1>(0h1)) connect after, _after_out_T else : node _after_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _after_T_1 : node _after_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect after, _after_out_T_1 else : node _after_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _after_T_2 : node _after_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _after_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _after_out_T_4 = mux(after_c, _after_out_T_2, _after_out_T_3) connect after, _after_out_T_4 else : node _after_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _after_T_3 : connect after, UInt<4>(0h8) node _after_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _after_T_4 : connect after, UInt<4>(0h8) node _T_56 = eq(s_release, UInt<1>(0h0)) node _T_57 = and(_T_56, w_rprobeackfirst) node _T_58 = and(_T_57, io.schedule.ready) when _T_58 : node _T_59 = eq(evict, UInt<1>(0h1)) node _T_60 = eq(_T_59, UInt<1>(0h0)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_8 assert(clock, _T_60, UInt<1>(0h1), "") : assert_8 node _T_64 = eq(before, UInt<1>(0h1)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_9 assert(clock, _T_65, UInt<1>(0h1), "") : assert_9 node _T_69 = eq(evict, UInt<1>(0h0)) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to evicted should be impossible (false,true,true,false,true)\n at MSHR.scala:346 assert(!(evict === from.code), cf\"State transition from ${from} to evicted should be impossible ${cfg}\")\n") : printf_10 assert(clock, _T_70, UInt<1>(0h1), "") : assert_10 node _T_74 = eq(before, UInt<1>(0h0)) node _T_75 = eq(_T_74, UInt<1>(0h0)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to flushed should be impossible (false,true,true,false,true)\n at MSHR.scala:351 assert(!(before === from.code), cf\"State transition from ${from} to flushed should be impossible ${cfg}\")\n") : printf_11 assert(clock, _T_75, UInt<1>(0h1), "") : assert_11 node _T_79 = eq(evict, UInt<3>(0h7)) node _T_80 = eq(before, UInt<3>(0h7)) node _T_81 = eq(evict, UInt<3>(0h5)) node _T_82 = eq(before, UInt<3>(0h5)) node _T_83 = eq(evict, UInt<3>(0h4)) node _T_84 = eq(before, UInt<3>(0h4)) node _T_85 = eq(evict, UInt<3>(0h6)) node _T_86 = eq(before, UInt<3>(0h6)) node _T_87 = eq(evict, UInt<2>(0h3)) node _T_88 = eq(before, UInt<2>(0h3)) node _T_89 = eq(evict, UInt<2>(0h2)) node _T_90 = eq(before, UInt<2>(0h2)) node _T_91 = eq(s_writeback, UInt<1>(0h0)) node _T_92 = and(_T_91, no_wait) node _T_93 = and(_T_92, io.schedule.ready) when _T_93 : node _T_94 = eq(before, UInt<4>(0h8)) node _T_95 = eq(after, UInt<1>(0h1)) node _T_96 = and(_T_94, _T_95) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = asUInt(reset) node _T_99 = eq(_T_98, UInt<1>(0h0)) when _T_99 : node _T_100 = eq(_T_97, UInt<1>(0h0)) when _T_100 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_12 assert(clock, _T_97, UInt<1>(0h1), "") : assert_12 node _T_101 = eq(before, UInt<4>(0h8)) node _T_102 = eq(after, UInt<1>(0h0)) node _T_103 = and(_T_101, _T_102) node _T_104 = eq(_T_103, UInt<1>(0h0)) node _T_105 = asUInt(reset) node _T_106 = eq(_T_105, UInt<1>(0h0)) when _T_106 : node _T_107 = eq(_T_104, UInt<1>(0h0)) when _T_107 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_13 assert(clock, _T_104, UInt<1>(0h1), "") : assert_13 node _T_108 = eq(before, UInt<4>(0h8)) node _T_109 = eq(after, UInt<3>(0h7)) node _T_110 = and(_T_108, _T_109) node _T_111 = eq(before, UInt<4>(0h8)) node _T_112 = eq(after, UInt<3>(0h5)) node _T_113 = and(_T_111, _T_112) node _T_114 = eq(_T_113, UInt<1>(0h0)) node _T_115 = asUInt(reset) node _T_116 = eq(_T_115, UInt<1>(0h0)) when _T_116 : node _T_117 = eq(_T_114, UInt<1>(0h0)) when _T_117 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_14 assert(clock, _T_114, UInt<1>(0h1), "") : assert_14 node _T_118 = eq(before, UInt<4>(0h8)) node _T_119 = eq(after, UInt<3>(0h4)) node _T_120 = and(_T_118, _T_119) node _T_121 = eq(_T_120, UInt<1>(0h0)) node _T_122 = asUInt(reset) node _T_123 = eq(_T_122, UInt<1>(0h0)) when _T_123 : node _T_124 = eq(_T_121, UInt<1>(0h0)) when _T_124 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_15 assert(clock, _T_121, UInt<1>(0h1), "") : assert_15 node _T_125 = eq(before, UInt<4>(0h8)) node _T_126 = eq(after, UInt<3>(0h6)) node _T_127 = and(_T_125, _T_126) node _T_128 = eq(before, UInt<4>(0h8)) node _T_129 = eq(after, UInt<2>(0h3)) node _T_130 = and(_T_128, _T_129) node _T_131 = eq(before, UInt<4>(0h8)) node _T_132 = eq(after, UInt<2>(0h2)) node _T_133 = and(_T_131, _T_132) node _T_134 = eq(_T_133, UInt<1>(0h0)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_INVALID to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_16 assert(clock, _T_134, UInt<1>(0h1), "") : assert_16 node _T_138 = eq(before, UInt<1>(0h1)) node _T_139 = eq(after, UInt<4>(0h8)) node _T_140 = and(_T_138, _T_139) node _T_141 = eq(_T_140, UInt<1>(0h0)) node _T_142 = asUInt(reset) node _T_143 = eq(_T_142, UInt<1>(0h0)) when _T_143 : node _T_144 = eq(_T_141, UInt<1>(0h0)) when _T_144 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_17 assert(clock, _T_141, UInt<1>(0h1), "") : assert_17 node _T_145 = eq(before, UInt<1>(0h1)) node _T_146 = eq(after, UInt<1>(0h0)) node _T_147 = and(_T_145, _T_146) node _T_148 = eq(_T_147, UInt<1>(0h0)) node _T_149 = asUInt(reset) node _T_150 = eq(_T_149, UInt<1>(0h0)) when _T_150 : node _T_151 = eq(_T_148, UInt<1>(0h0)) when _T_151 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_18 assert(clock, _T_148, UInt<1>(0h1), "") : assert_18 node _T_152 = eq(before, UInt<1>(0h1)) node _T_153 = eq(after, UInt<3>(0h7)) node _T_154 = and(_T_152, _T_153) node _T_155 = eq(_T_154, UInt<1>(0h0)) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = eq(before, UInt<1>(0h1)) node _T_160 = eq(after, UInt<3>(0h5)) node _T_161 = and(_T_159, _T_160) node _T_162 = eq(_T_161, UInt<1>(0h0)) node _T_163 = asUInt(reset) node _T_164 = eq(_T_163, UInt<1>(0h0)) when _T_164 : node _T_165 = eq(_T_162, UInt<1>(0h0)) when _T_165 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_20 assert(clock, _T_162, UInt<1>(0h1), "") : assert_20 node _T_166 = eq(before, UInt<1>(0h1)) node _T_167 = eq(after, UInt<3>(0h4)) node _T_168 = and(_T_166, _T_167) node _T_169 = eq(_T_168, UInt<1>(0h0)) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_21 assert(clock, _T_169, UInt<1>(0h1), "") : assert_21 node _T_173 = eq(before, UInt<1>(0h1)) node _T_174 = eq(after, UInt<3>(0h6)) node _T_175 = and(_T_173, _T_174) node _T_176 = eq(_T_175, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_22 assert(clock, _T_176, UInt<1>(0h1), "") : assert_22 node _T_180 = eq(before, UInt<1>(0h1)) node _T_181 = eq(after, UInt<2>(0h3)) node _T_182 = and(_T_180, _T_181) node _T_183 = eq(_T_182, UInt<1>(0h0)) node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_T_183, UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_23 assert(clock, _T_183, UInt<1>(0h1), "") : assert_23 node _T_187 = eq(before, UInt<1>(0h1)) node _T_188 = eq(after, UInt<2>(0h2)) node _T_189 = and(_T_187, _T_188) node _T_190 = eq(_T_189, UInt<1>(0h0)) node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(_T_190, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_24 assert(clock, _T_190, UInt<1>(0h1), "") : assert_24 node _T_194 = eq(before, UInt<1>(0h0)) node _T_195 = eq(after, UInt<4>(0h8)) node _T_196 = and(_T_194, _T_195) node _T_197 = eq(_T_196, UInt<1>(0h0)) node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(_T_197, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_25 assert(clock, _T_197, UInt<1>(0h1), "") : assert_25 node _T_201 = eq(before, UInt<1>(0h0)) node _T_202 = eq(after, UInt<1>(0h1)) node _T_203 = and(_T_201, _T_202) node _T_204 = eq(_T_203, UInt<1>(0h0)) node _T_205 = asUInt(reset) node _T_206 = eq(_T_205, UInt<1>(0h0)) when _T_206 : node _T_207 = eq(_T_204, UInt<1>(0h0)) when _T_207 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_26 assert(clock, _T_204, UInt<1>(0h1), "") : assert_26 node _T_208 = eq(before, UInt<1>(0h0)) node _T_209 = eq(after, UInt<3>(0h7)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(_T_210, UInt<1>(0h0)) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_27 assert(clock, _T_211, UInt<1>(0h1), "") : assert_27 node _T_215 = eq(before, UInt<1>(0h0)) node _T_216 = eq(after, UInt<3>(0h5)) node _T_217 = and(_T_215, _T_216) node _T_218 = eq(_T_217, UInt<1>(0h0)) node _T_219 = asUInt(reset) node _T_220 = eq(_T_219, UInt<1>(0h0)) when _T_220 : node _T_221 = eq(_T_218, UInt<1>(0h0)) when _T_221 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_28 assert(clock, _T_218, UInt<1>(0h1), "") : assert_28 node _T_222 = eq(before, UInt<1>(0h0)) node _T_223 = eq(after, UInt<3>(0h6)) node _T_224 = and(_T_222, _T_223) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_D should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_29 assert(clock, _T_225, UInt<1>(0h1), "") : assert_29 node _T_229 = eq(before, UInt<1>(0h0)) node _T_230 = eq(after, UInt<3>(0h4)) node _T_231 = and(_T_229, _T_230) node _T_232 = eq(_T_231, UInt<1>(0h0)) node _T_233 = asUInt(reset) node _T_234 = eq(_T_233, UInt<1>(0h0)) when _T_234 : node _T_235 = eq(_T_232, UInt<1>(0h0)) when _T_235 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_30 assert(clock, _T_232, UInt<1>(0h1), "") : assert_30 node _T_236 = eq(before, UInt<1>(0h0)) node _T_237 = eq(after, UInt<2>(0h3)) node _T_238 = and(_T_236, _T_237) node _T_239 = eq(_T_238, UInt<1>(0h0)) node _T_240 = asUInt(reset) node _T_241 = eq(_T_240, UInt<1>(0h0)) when _T_241 : node _T_242 = eq(_T_239, UInt<1>(0h0)) when _T_242 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_31 assert(clock, _T_239, UInt<1>(0h1), "") : assert_31 node _T_243 = eq(before, UInt<1>(0h0)) node _T_244 = eq(after, UInt<2>(0h2)) node _T_245 = and(_T_243, _T_244) node _T_246 = eq(_T_245, UInt<1>(0h0)) node _T_247 = asUInt(reset) node _T_248 = eq(_T_247, UInt<1>(0h0)) when _T_248 : node _T_249 = eq(_T_246, UInt<1>(0h0)) when _T_249 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_BRANCH_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_32 assert(clock, _T_246, UInt<1>(0h1), "") : assert_32 node _T_250 = eq(before, UInt<3>(0h7)) node _T_251 = eq(after, UInt<4>(0h8)) node _T_252 = and(_T_250, _T_251) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_33 assert(clock, _T_253, UInt<1>(0h1), "") : assert_33 node _T_257 = eq(before, UInt<3>(0h7)) node _T_258 = eq(after, UInt<1>(0h1)) node _T_259 = and(_T_257, _T_258) node _T_260 = eq(_T_259, UInt<1>(0h0)) node _T_261 = asUInt(reset) node _T_262 = eq(_T_261, UInt<1>(0h0)) when _T_262 : node _T_263 = eq(_T_260, UInt<1>(0h0)) when _T_263 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_34 assert(clock, _T_260, UInt<1>(0h1), "") : assert_34 node _T_264 = eq(before, UInt<3>(0h7)) node _T_265 = eq(after, UInt<1>(0h0)) node _T_266 = and(_T_264, _T_265) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = asUInt(reset) node _T_269 = eq(_T_268, UInt<1>(0h0)) when _T_269 : node _T_270 = eq(_T_267, UInt<1>(0h0)) when _T_270 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_35 assert(clock, _T_267, UInt<1>(0h1), "") : assert_35 node _T_271 = eq(before, UInt<3>(0h7)) node _T_272 = eq(after, UInt<3>(0h5)) node _T_273 = and(_T_271, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_36 assert(clock, _T_274, UInt<1>(0h1), "") : assert_36 node _T_278 = eq(before, UInt<3>(0h7)) node _T_279 = eq(after, UInt<3>(0h6)) node _T_280 = and(_T_278, _T_279) node _T_281 = eq(before, UInt<3>(0h7)) node _T_282 = eq(after, UInt<3>(0h4)) node _T_283 = and(_T_281, _T_282) node _T_284 = eq(_T_283, UInt<1>(0h0)) node _T_285 = asUInt(reset) node _T_286 = eq(_T_285, UInt<1>(0h0)) when _T_286 : node _T_287 = eq(_T_284, UInt<1>(0h0)) when _T_287 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_37 assert(clock, _T_284, UInt<1>(0h1), "") : assert_37 node _T_288 = eq(before, UInt<3>(0h7)) node _T_289 = eq(after, UInt<2>(0h3)) node _T_290 = and(_T_288, _T_289) node _T_291 = eq(before, UInt<3>(0h7)) node _T_292 = eq(after, UInt<2>(0h2)) node _T_293 = and(_T_291, _T_292) node _T_294 = eq(_T_293, UInt<1>(0h0)) node _T_295 = asUInt(reset) node _T_296 = eq(_T_295, UInt<1>(0h0)) when _T_296 : node _T_297 = eq(_T_294, UInt<1>(0h0)) when _T_297 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_38 assert(clock, _T_294, UInt<1>(0h1), "") : assert_38 node _T_298 = eq(before, UInt<3>(0h5)) node _T_299 = eq(after, UInt<4>(0h8)) node _T_300 = and(_T_298, _T_299) node _T_301 = eq(_T_300, UInt<1>(0h0)) node _T_302 = asUInt(reset) node _T_303 = eq(_T_302, UInt<1>(0h0)) when _T_303 : node _T_304 = eq(_T_301, UInt<1>(0h0)) when _T_304 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_39 assert(clock, _T_301, UInt<1>(0h1), "") : assert_39 node _T_305 = eq(before, UInt<3>(0h5)) node _T_306 = eq(after, UInt<1>(0h1)) node _T_307 = and(_T_305, _T_306) node _T_308 = eq(_T_307, UInt<1>(0h0)) node _T_309 = asUInt(reset) node _T_310 = eq(_T_309, UInt<1>(0h0)) when _T_310 : node _T_311 = eq(_T_308, UInt<1>(0h0)) when _T_311 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_40 assert(clock, _T_308, UInt<1>(0h1), "") : assert_40 node _T_312 = eq(before, UInt<3>(0h5)) node _T_313 = eq(after, UInt<1>(0h0)) node _T_314 = and(_T_312, _T_313) node _T_315 = eq(_T_314, UInt<1>(0h0)) node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(_T_315, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_41 assert(clock, _T_315, UInt<1>(0h1), "") : assert_41 node _T_319 = eq(before, UInt<3>(0h5)) node _T_320 = eq(after, UInt<3>(0h7)) node _T_321 = and(_T_319, _T_320) node _T_322 = eq(before, UInt<3>(0h5)) node _T_323 = eq(after, UInt<3>(0h6)) node _T_324 = and(_T_322, _T_323) node _T_325 = eq(before, UInt<3>(0h5)) node _T_326 = eq(after, UInt<3>(0h4)) node _T_327 = and(_T_325, _T_326) node _T_328 = eq(_T_327, UInt<1>(0h0)) node _T_329 = asUInt(reset) node _T_330 = eq(_T_329, UInt<1>(0h0)) when _T_330 : node _T_331 = eq(_T_328, UInt<1>(0h0)) when _T_331 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_42 assert(clock, _T_328, UInt<1>(0h1), "") : assert_42 node _T_332 = eq(before, UInt<3>(0h5)) node _T_333 = eq(after, UInt<2>(0h3)) node _T_334 = and(_T_332, _T_333) node _T_335 = eq(before, UInt<3>(0h5)) node _T_336 = eq(after, UInt<2>(0h2)) node _T_337 = and(_T_335, _T_336) node _T_338 = eq(_T_337, UInt<1>(0h0)) node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(_T_338, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_C to S_TRUNK_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_43 assert(clock, _T_338, UInt<1>(0h1), "") : assert_43 node _T_342 = eq(before, UInt<3>(0h6)) node _T_343 = eq(after, UInt<4>(0h8)) node _T_344 = and(_T_342, _T_343) node _T_345 = eq(_T_344, UInt<1>(0h0)) node _T_346 = asUInt(reset) node _T_347 = eq(_T_346, UInt<1>(0h0)) when _T_347 : node _T_348 = eq(_T_345, UInt<1>(0h0)) when _T_348 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_44 assert(clock, _T_345, UInt<1>(0h1), "") : assert_44 node _T_349 = eq(before, UInt<3>(0h6)) node _T_350 = eq(after, UInt<1>(0h1)) node _T_351 = and(_T_349, _T_350) node _T_352 = eq(_T_351, UInt<1>(0h0)) node _T_353 = asUInt(reset) node _T_354 = eq(_T_353, UInt<1>(0h0)) when _T_354 : node _T_355 = eq(_T_352, UInt<1>(0h0)) when _T_355 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_45 assert(clock, _T_352, UInt<1>(0h1), "") : assert_45 node _T_356 = eq(before, UInt<3>(0h6)) node _T_357 = eq(after, UInt<1>(0h0)) node _T_358 = and(_T_356, _T_357) node _T_359 = eq(_T_358, UInt<1>(0h0)) node _T_360 = asUInt(reset) node _T_361 = eq(_T_360, UInt<1>(0h0)) when _T_361 : node _T_362 = eq(_T_359, UInt<1>(0h0)) when _T_362 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_46 assert(clock, _T_359, UInt<1>(0h1), "") : assert_46 node _T_363 = eq(before, UInt<3>(0h6)) node _T_364 = eq(after, UInt<3>(0h7)) node _T_365 = and(_T_363, _T_364) node _T_366 = eq(_T_365, UInt<1>(0h0)) node _T_367 = asUInt(reset) node _T_368 = eq(_T_367, UInt<1>(0h0)) when _T_368 : node _T_369 = eq(_T_366, UInt<1>(0h0)) when _T_369 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_47 assert(clock, _T_366, UInt<1>(0h1), "") : assert_47 node _T_370 = eq(before, UInt<3>(0h6)) node _T_371 = eq(after, UInt<3>(0h5)) node _T_372 = and(_T_370, _T_371) node _T_373 = eq(_T_372, UInt<1>(0h0)) node _T_374 = asUInt(reset) node _T_375 = eq(_T_374, UInt<1>(0h0)) when _T_375 : node _T_376 = eq(_T_373, UInt<1>(0h0)) when _T_376 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_48 assert(clock, _T_373, UInt<1>(0h1), "") : assert_48 node _T_377 = eq(before, UInt<3>(0h6)) node _T_378 = eq(after, UInt<3>(0h4)) node _T_379 = and(_T_377, _T_378) node _T_380 = eq(_T_379, UInt<1>(0h0)) node _T_381 = asUInt(reset) node _T_382 = eq(_T_381, UInt<1>(0h0)) when _T_382 : node _T_383 = eq(_T_380, UInt<1>(0h0)) when _T_383 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TIP_CD should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_49 assert(clock, _T_380, UInt<1>(0h1), "") : assert_49 node _T_384 = eq(before, UInt<3>(0h6)) node _T_385 = eq(after, UInt<2>(0h3)) node _T_386 = and(_T_384, _T_385) node _T_387 = eq(_T_386, UInt<1>(0h0)) node _T_388 = asUInt(reset) node _T_389 = eq(_T_388, UInt<1>(0h0)) when _T_389 : node _T_390 = eq(_T_387, UInt<1>(0h0)) when _T_390 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_D to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_50 assert(clock, _T_387, UInt<1>(0h1), "") : assert_50 node _T_391 = eq(before, UInt<3>(0h6)) node _T_392 = eq(after, UInt<2>(0h2)) node _T_393 = and(_T_391, _T_392) node _T_394 = eq(before, UInt<3>(0h4)) node _T_395 = eq(after, UInt<4>(0h8)) node _T_396 = and(_T_394, _T_395) node _T_397 = eq(_T_396, UInt<1>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_51 assert(clock, _T_397, UInt<1>(0h1), "") : assert_51 node _T_401 = eq(before, UInt<3>(0h4)) node _T_402 = eq(after, UInt<1>(0h1)) node _T_403 = and(_T_401, _T_402) node _T_404 = eq(_T_403, UInt<1>(0h0)) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_52 assert(clock, _T_404, UInt<1>(0h1), "") : assert_52 node _T_408 = eq(before, UInt<3>(0h4)) node _T_409 = eq(after, UInt<1>(0h0)) node _T_410 = and(_T_408, _T_409) node _T_411 = eq(_T_410, UInt<1>(0h0)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_53 assert(clock, _T_411, UInt<1>(0h1), "") : assert_53 node _T_415 = eq(before, UInt<3>(0h4)) node _T_416 = eq(after, UInt<3>(0h7)) node _T_417 = and(_T_415, _T_416) node _T_418 = eq(_T_417, UInt<1>(0h0)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_54 assert(clock, _T_418, UInt<1>(0h1), "") : assert_54 node _T_422 = eq(before, UInt<3>(0h4)) node _T_423 = eq(after, UInt<3>(0h5)) node _T_424 = and(_T_422, _T_423) node _T_425 = eq(_T_424, UInt<1>(0h0)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_55 assert(clock, _T_425, UInt<1>(0h1), "") : assert_55 node _T_429 = eq(before, UInt<3>(0h4)) node _T_430 = eq(after, UInt<3>(0h6)) node _T_431 = and(_T_429, _T_430) node _T_432 = eq(before, UInt<3>(0h4)) node _T_433 = eq(after, UInt<2>(0h3)) node _T_434 = and(_T_432, _T_433) node _T_435 = eq(_T_434, UInt<1>(0h0)) node _T_436 = asUInt(reset) node _T_437 = eq(_T_436, UInt<1>(0h0)) when _T_437 : node _T_438 = eq(_T_435, UInt<1>(0h0)) when _T_438 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TIP_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_56 assert(clock, _T_435, UInt<1>(0h1), "") : assert_56 node _T_439 = eq(before, UInt<3>(0h4)) node _T_440 = eq(after, UInt<2>(0h2)) node _T_441 = and(_T_439, _T_440) node _T_442 = eq(before, UInt<2>(0h3)) node _T_443 = eq(after, UInt<4>(0h8)) node _T_444 = and(_T_442, _T_443) node _T_445 = eq(_T_444, UInt<1>(0h0)) node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(_T_445, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_57 assert(clock, _T_445, UInt<1>(0h1), "") : assert_57 node _T_449 = eq(before, UInt<2>(0h3)) node _T_450 = eq(after, UInt<1>(0h1)) node _T_451 = and(_T_449, _T_450) node _T_452 = eq(_T_451, UInt<1>(0h0)) node _T_453 = asUInt(reset) node _T_454 = eq(_T_453, UInt<1>(0h0)) when _T_454 : node _T_455 = eq(_T_452, UInt<1>(0h0)) when _T_455 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_58 assert(clock, _T_452, UInt<1>(0h1), "") : assert_58 node _T_456 = eq(before, UInt<2>(0h3)) node _T_457 = eq(after, UInt<1>(0h0)) node _T_458 = and(_T_456, _T_457) node _T_459 = eq(_T_458, UInt<1>(0h0)) node _T_460 = asUInt(reset) node _T_461 = eq(_T_460, UInt<1>(0h0)) when _T_461 : node _T_462 = eq(_T_459, UInt<1>(0h0)) when _T_462 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_C to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_59 assert(clock, _T_459, UInt<1>(0h1), "") : assert_59 node _T_463 = eq(before, UInt<2>(0h3)) node _T_464 = eq(after, UInt<3>(0h7)) node _T_465 = and(_T_463, _T_464) node _T_466 = eq(before, UInt<2>(0h3)) node _T_467 = eq(after, UInt<3>(0h5)) node _T_468 = and(_T_466, _T_467) node _T_469 = eq(before, UInt<2>(0h3)) node _T_470 = eq(after, UInt<3>(0h6)) node _T_471 = and(_T_469, _T_470) node _T_472 = eq(before, UInt<2>(0h3)) node _T_473 = eq(after, UInt<3>(0h4)) node _T_474 = and(_T_472, _T_473) node _T_475 = eq(before, UInt<2>(0h3)) node _T_476 = eq(after, UInt<2>(0h2)) node _T_477 = and(_T_475, _T_476) node _T_478 = eq(before, UInt<2>(0h2)) node _T_479 = eq(after, UInt<4>(0h8)) node _T_480 = and(_T_478, _T_479) node _T_481 = eq(_T_480, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_INVALID should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_60 assert(clock, _T_481, UInt<1>(0h1), "") : assert_60 node _T_485 = eq(before, UInt<2>(0h2)) node _T_486 = eq(after, UInt<1>(0h1)) node _T_487 = and(_T_485, _T_486) node _T_488 = eq(_T_487, UInt<1>(0h0)) node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_T_488, UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_61 assert(clock, _T_488, UInt<1>(0h1), "") : assert_61 node _T_492 = eq(before, UInt<2>(0h2)) node _T_493 = eq(after, UInt<1>(0h0)) node _T_494 = and(_T_492, _T_493) node _T_495 = eq(_T_494, UInt<1>(0h0)) node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(_T_495, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_62 assert(clock, _T_495, UInt<1>(0h1), "") : assert_62 node _T_499 = eq(before, UInt<2>(0h2)) node _T_500 = eq(after, UInt<3>(0h7)) node _T_501 = and(_T_499, _T_500) node _T_502 = eq(_T_501, UInt<1>(0h0)) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_63 assert(clock, _T_502, UInt<1>(0h1), "") : assert_63 node _T_506 = eq(before, UInt<2>(0h2)) node _T_507 = eq(after, UInt<3>(0h5)) node _T_508 = and(_T_506, _T_507) node _T_509 = eq(_T_508, UInt<1>(0h0)) node _T_510 = asUInt(reset) node _T_511 = eq(_T_510, UInt<1>(0h0)) when _T_511 : node _T_512 = eq(_T_509, UInt<1>(0h0)) when _T_512 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TIP_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_64 assert(clock, _T_509, UInt<1>(0h1), "") : assert_64 node _T_513 = eq(before, UInt<2>(0h2)) node _T_514 = eq(after, UInt<3>(0h6)) node _T_515 = and(_T_513, _T_514) node _T_516 = eq(before, UInt<2>(0h2)) node _T_517 = eq(after, UInt<3>(0h4)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(before, UInt<2>(0h2)) node _T_520 = eq(after, UInt<2>(0h3)) node _T_521 = and(_T_519, _T_520) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = asUInt(reset) node _T_524 = eq(_T_523, UInt<1>(0h0)) when _T_524 : node _T_525 = eq(_T_522, UInt<1>(0h0)) when _T_525 : printf(clock, UInt<1>(0h1), "Assertion failed: State transition from S_TRUNK_CD to S_TRUNK_C should be impossible (false,true,true,false,true)\n at MSHR.scala:359 assert(!(before === from.code && after === to.code), cf\"State transition from ${from} to ${to} should be impossible ${cfg}\")\n") : printf_65 assert(clock, _T_522, UInt<1>(0h1), "") : assert_65 node _probe_bit_T = eq(io.sinkc.bits.source, UInt<7>(0h44)) node _probe_bit_T_1 = eq(io.sinkc.bits.source, UInt<7>(0h40)) node _probe_bit_uncommonBits_T = or(io.sinkc.bits.source, UInt<3>(0h0)) node probe_bit_uncommonBits = bits(_probe_bit_uncommonBits_T, 2, 0) node _probe_bit_T_2 = shr(io.sinkc.bits.source, 3) node _probe_bit_T_3 = eq(_probe_bit_T_2, UInt<3>(0h6)) node _probe_bit_T_4 = leq(UInt<1>(0h0), probe_bit_uncommonBits) node _probe_bit_T_5 = and(_probe_bit_T_3, _probe_bit_T_4) node _probe_bit_T_6 = leq(probe_bit_uncommonBits, UInt<3>(0h4)) node _probe_bit_T_7 = and(_probe_bit_T_5, _probe_bit_T_6) node _probe_bit_uncommonBits_T_1 = or(io.sinkc.bits.source, UInt<3>(0h0)) node probe_bit_uncommonBits_1 = bits(_probe_bit_uncommonBits_T_1, 2, 0) node _probe_bit_T_8 = shr(io.sinkc.bits.source, 3) node _probe_bit_T_9 = eq(_probe_bit_T_8, UInt<3>(0h4)) node _probe_bit_T_10 = leq(UInt<1>(0h0), probe_bit_uncommonBits_1) node _probe_bit_T_11 = and(_probe_bit_T_9, _probe_bit_T_10) node _probe_bit_T_12 = leq(probe_bit_uncommonBits_1, UInt<3>(0h4)) node _probe_bit_T_13 = and(_probe_bit_T_11, _probe_bit_T_12) node probe_bit_lo = cat(_probe_bit_T_1, _probe_bit_T) node probe_bit_hi = cat(_probe_bit_T_13, _probe_bit_T_7) node probe_bit = cat(probe_bit_hi, probe_bit_lo) node _last_probe_T = or(probes_done, probe_bit) node _last_probe_T_1 = not(excluded_client) node _last_probe_T_2 = and(meta.clients, _last_probe_T_1) node last_probe = eq(_last_probe_T, _last_probe_T_2) node _probe_toN_T = eq(io.sinkc.bits.param, UInt<3>(0h1)) node _probe_toN_T_1 = eq(io.sinkc.bits.param, UInt<3>(0h2)) node _probe_toN_T_2 = or(_probe_toN_T, _probe_toN_T_1) node _probe_toN_T_3 = eq(io.sinkc.bits.param, UInt<3>(0h5)) node probe_toN = or(_probe_toN_T_2, _probe_toN_T_3) when io.sinkc.valid : node _T_526 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_527 = and(probe_toN, _T_526) node _T_528 = eq(probe_toN, UInt<1>(0h0)) node _T_529 = eq(io.schedule.bits.b.bits.param, UInt<2>(0h1)) node _T_530 = and(_T_528, _T_529) node _probes_done_T = or(probes_done, probe_bit) connect probes_done, _probes_done_T node _probes_toN_T = mux(probe_toN, probe_bit, UInt<1>(0h0)) node _probes_toN_T_1 = or(probes_toN, _probes_toN_T) connect probes_toN, _probes_toN_T_1 node _probes_noT_T = neq(io.sinkc.bits.param, UInt<3>(0h3)) node _probes_noT_T_1 = or(probes_noT, _probes_noT_T) connect probes_noT, _probes_noT_T_1 node _w_rprobeackfirst_T = or(w_rprobeackfirst, last_probe) connect w_rprobeackfirst, _w_rprobeackfirst_T node _w_rprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_rprobeacklast_T_1 = or(w_rprobeacklast, _w_rprobeacklast_T) connect w_rprobeacklast, _w_rprobeacklast_T_1 node _w_pprobeackfirst_T = or(w_pprobeackfirst, last_probe) connect w_pprobeackfirst, _w_pprobeackfirst_T node _w_pprobeacklast_T = and(last_probe, io.sinkc.bits.last) node _w_pprobeacklast_T_1 = or(w_pprobeacklast, _w_pprobeacklast_T) connect w_pprobeacklast, _w_pprobeacklast_T_1 node _set_pprobeack_T = eq(request.offset, UInt<1>(0h0)) node _set_pprobeack_T_1 = or(io.sinkc.bits.last, _set_pprobeack_T) node set_pprobeack = and(last_probe, _set_pprobeack_T_1) node _w_pprobeack_T = or(w_pprobeack, set_pprobeack) connect w_pprobeack, _w_pprobeack_T node _T_531 = eq(set_pprobeack, UInt<1>(0h0)) node _T_532 = and(_T_531, w_rprobeackfirst) node _T_533 = and(set_pprobeack, w_rprobeackfirst) node _T_534 = neq(meta.state, UInt<2>(0h0)) node _T_535 = eq(io.sinkc.bits.tag, meta.tag) node _T_536 = and(_T_534, _T_535) node _T_537 = and(_T_536, io.sinkc.bits.data) when _T_537 : connect meta.dirty, UInt<1>(0h1) when io.sinkd.valid : node _T_538 = eq(io.sinkd.bits.opcode, UInt<3>(0h4)) node _T_539 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_540 = or(_T_538, _T_539) when _T_540 : connect sink, io.sinkd.bits.sink connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, io.sinkd.bits.last connect bad_grant, io.sinkd.bits.denied node _w_grant_T = eq(request.offset, UInt<1>(0h0)) node _w_grant_T_1 = or(_w_grant_T, io.sinkd.bits.last) connect w_grant, _w_grant_T_1 node _T_541 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_542 = eq(request.offset, UInt<1>(0h0)) node _T_543 = and(_T_541, _T_542) node _T_544 = eq(io.sinkd.bits.opcode, UInt<3>(0h5)) node _T_545 = neq(request.offset, UInt<1>(0h0)) node _T_546 = and(_T_544, _T_545) node _gotT_T = eq(io.sinkd.bits.param, UInt<2>(0h0)) connect gotT, _gotT_T else : node _T_547 = eq(io.sinkd.bits.opcode, UInt<3>(0h6)) when _T_547 : connect w_releaseack, UInt<1>(0h1) when io.sinke.valid : connect w_grantack, UInt<1>(0h1) wire allocate_as_full : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, tag : UInt<13>, offset : UInt<6>, put : UInt<6>, set : UInt<10>} connect allocate_as_full.set, io.allocate.bits.set connect allocate_as_full.put, io.allocate.bits.put connect allocate_as_full.offset, io.allocate.bits.offset connect allocate_as_full.tag, io.allocate.bits.tag connect allocate_as_full.source, io.allocate.bits.source connect allocate_as_full.size, io.allocate.bits.size connect allocate_as_full.param, io.allocate.bits.param connect allocate_as_full.opcode, io.allocate.bits.opcode connect allocate_as_full.control, io.allocate.bits.control connect allocate_as_full.prio, io.allocate.bits.prio node _new_meta_T = and(io.allocate.valid, io.allocate.bits.repeat) node new_meta = mux(_new_meta_T, final_meta_writeback, io.directory.bits) node new_request = mux(io.allocate.valid, allocate_as_full, request) node _new_needT_T = bits(new_request.opcode, 2, 2) node _new_needT_T_1 = eq(_new_needT_T, UInt<1>(0h0)) node _new_needT_T_2 = eq(new_request.opcode, UInt<3>(0h5)) node _new_needT_T_3 = eq(new_request.param, UInt<1>(0h1)) node _new_needT_T_4 = and(_new_needT_T_2, _new_needT_T_3) node _new_needT_T_5 = or(_new_needT_T_1, _new_needT_T_4) node _new_needT_T_6 = eq(new_request.opcode, UInt<3>(0h6)) node _new_needT_T_7 = eq(new_request.opcode, UInt<3>(0h7)) node _new_needT_T_8 = or(_new_needT_T_6, _new_needT_T_7) node _new_needT_T_9 = neq(new_request.param, UInt<2>(0h0)) node _new_needT_T_10 = and(_new_needT_T_8, _new_needT_T_9) node new_needT = or(_new_needT_T_5, _new_needT_T_10) node _new_clientBit_T = eq(new_request.source, UInt<7>(0h44)) node _new_clientBit_T_1 = eq(new_request.source, UInt<7>(0h40)) node _new_clientBit_uncommonBits_T = or(new_request.source, UInt<3>(0h0)) node new_clientBit_uncommonBits = bits(_new_clientBit_uncommonBits_T, 2, 0) node _new_clientBit_T_2 = shr(new_request.source, 3) node _new_clientBit_T_3 = eq(_new_clientBit_T_2, UInt<3>(0h6)) node _new_clientBit_T_4 = leq(UInt<1>(0h0), new_clientBit_uncommonBits) node _new_clientBit_T_5 = and(_new_clientBit_T_3, _new_clientBit_T_4) node _new_clientBit_T_6 = leq(new_clientBit_uncommonBits, UInt<3>(0h4)) node _new_clientBit_T_7 = and(_new_clientBit_T_5, _new_clientBit_T_6) node _new_clientBit_uncommonBits_T_1 = or(new_request.source, UInt<3>(0h0)) node new_clientBit_uncommonBits_1 = bits(_new_clientBit_uncommonBits_T_1, 2, 0) node _new_clientBit_T_8 = shr(new_request.source, 3) node _new_clientBit_T_9 = eq(_new_clientBit_T_8, UInt<3>(0h4)) node _new_clientBit_T_10 = leq(UInt<1>(0h0), new_clientBit_uncommonBits_1) node _new_clientBit_T_11 = and(_new_clientBit_T_9, _new_clientBit_T_10) node _new_clientBit_T_12 = leq(new_clientBit_uncommonBits_1, UInt<3>(0h4)) node _new_clientBit_T_13 = and(_new_clientBit_T_11, _new_clientBit_T_12) node new_clientBit_lo = cat(_new_clientBit_T_1, _new_clientBit_T) node new_clientBit_hi = cat(_new_clientBit_T_13, _new_clientBit_T_7) node new_clientBit = cat(new_clientBit_hi, new_clientBit_lo) node _new_skipProbe_T = eq(new_request.opcode, UInt<3>(0h6)) node _new_skipProbe_T_1 = eq(new_request.opcode, UInt<3>(0h7)) node _new_skipProbe_T_2 = or(_new_skipProbe_T, _new_skipProbe_T_1) node _new_skipProbe_T_3 = eq(new_request.opcode, UInt<3>(0h4)) node _new_skipProbe_T_4 = or(_new_skipProbe_T_2, _new_skipProbe_T_3) node _new_skipProbe_T_5 = eq(new_request.opcode, UInt<3>(0h5)) node _new_skipProbe_T_6 = and(_new_skipProbe_T_5, UInt<1>(0h0)) node _new_skipProbe_T_7 = or(_new_skipProbe_T_4, _new_skipProbe_T_6) node new_skipProbe = mux(_new_skipProbe_T_7, new_clientBit, UInt<1>(0h0)) wire prior : UInt connect prior, UInt<1>(0h0) node prior_c = orr(final_meta_writeback.clients) node _prior_T = eq(UInt<2>(0h1), final_meta_writeback.state) when _prior_T : node _prior_out_T = mux(prior_c, UInt<1>(0h0), UInt<1>(0h1)) connect prior, _prior_out_T else : node _prior_T_1 = eq(UInt<2>(0h2), final_meta_writeback.state) when _prior_T_1 : node _prior_out_T_1 = mux(final_meta_writeback.dirty, UInt<2>(0h2), UInt<2>(0h3)) connect prior, _prior_out_T_1 else : node _prior_T_2 = eq(UInt<2>(0h3), final_meta_writeback.state) when _prior_T_2 : node _prior_out_T_2 = mux(final_meta_writeback.dirty, UInt<3>(0h4), UInt<3>(0h5)) node _prior_out_T_3 = mux(final_meta_writeback.dirty, UInt<3>(0h6), UInt<3>(0h7)) node _prior_out_T_4 = mux(prior_c, _prior_out_T_2, _prior_out_T_3) connect prior, _prior_out_T_4 else : node _prior_T_3 = eq(UInt<2>(0h0), final_meta_writeback.state) when _prior_T_3 : connect prior, UInt<4>(0h8) node _prior_T_4 = eq(UInt<1>(0h1), UInt<1>(0h0)) when _prior_T_4 : connect prior, UInt<4>(0h8) node _T_548 = and(io.allocate.valid, io.allocate.bits.repeat) when _T_548 : node _T_549 = eq(prior, UInt<4>(0h8)) node _T_550 = eq(prior, UInt<1>(0h1)) node _T_551 = eq(_T_550, UInt<1>(0h0)) node _T_552 = asUInt(reset) node _T_553 = eq(_T_552, UInt<1>(0h0)) when _T_553 : node _T_554 = eq(_T_551, UInt<1>(0h0)) when _T_554 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_66 assert(clock, _T_551, UInt<1>(0h1), "") : assert_66 node _T_555 = eq(prior, UInt<1>(0h0)) node _T_556 = eq(_T_555, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: State bypass from S_BRANCH_C should be impossible (false,true,true,false,true)\n at MSHR.scala:516 assert(!(prior === from.code), cf\"State bypass from ${from} should be impossible ${cfg}\")\n") : printf_67 assert(clock, _T_556, UInt<1>(0h1), "") : assert_67 node _T_560 = eq(prior, UInt<3>(0h7)) node _T_561 = eq(prior, UInt<3>(0h5)) node _T_562 = eq(prior, UInt<3>(0h4)) node _T_563 = eq(prior, UInt<3>(0h6)) node _T_564 = eq(prior, UInt<2>(0h3)) node _T_565 = eq(prior, UInt<2>(0h2)) when io.allocate.valid : node _T_566 = eq(request_valid, UInt<1>(0h0)) node _T_567 = and(io.schedule.ready, io.schedule.valid) node _T_568 = and(no_wait, _T_567) node _T_569 = or(_T_566, _T_568) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:533 assert (!request_valid || (no_wait && io.schedule.fire))\n") : printf_68 assert(clock, _T_569, UInt<1>(0h1), "") : assert_68 connect request_valid, UInt<1>(0h1) connect request.set, io.allocate.bits.set connect request.put, io.allocate.bits.put connect request.offset, io.allocate.bits.offset connect request.tag, io.allocate.bits.tag connect request.source, io.allocate.bits.source connect request.size, io.allocate.bits.size connect request.param, io.allocate.bits.param connect request.opcode, io.allocate.bits.opcode connect request.control, io.allocate.bits.control connect request.prio, io.allocate.bits.prio node _T_573 = and(io.allocate.valid, io.allocate.bits.repeat) node _T_574 = or(io.directory.valid, _T_573) when _T_574 : connect meta_valid, UInt<1>(0h1) connect meta, new_meta connect probes_done, UInt<1>(0h0) connect probes_toN, UInt<1>(0h0) connect probes_noT, UInt<1>(0h0) connect gotT, UInt<1>(0h0) connect bad_grant, UInt<1>(0h0) connect s_rprobe, UInt<1>(0h1) connect w_rprobeackfirst, UInt<1>(0h1) connect w_rprobeacklast, UInt<1>(0h1) connect s_release, UInt<1>(0h1) connect w_releaseack, UInt<1>(0h1) connect s_pprobe, UInt<1>(0h1) connect s_acquire, UInt<1>(0h1) connect s_flush, UInt<1>(0h1) connect w_grantfirst, UInt<1>(0h1) connect w_grantlast, UInt<1>(0h1) connect w_grant, UInt<1>(0h1) connect w_pprobeackfirst, UInt<1>(0h1) connect w_pprobeacklast, UInt<1>(0h1) connect w_pprobeack, UInt<1>(0h1) connect s_probeack, UInt<1>(0h1) connect s_grantack, UInt<1>(0h1) connect s_execute, UInt<1>(0h1) connect w_grantack, UInt<1>(0h1) connect s_writeback, UInt<1>(0h1) node _T_575 = and(new_request.prio[2], UInt<1>(0h1)) when _T_575 : connect s_execute, UInt<1>(0h0) node _T_576 = bits(new_request.opcode, 0, 0) node _T_577 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_578 = and(_T_576, _T_577) when _T_578 : connect s_writeback, UInt<1>(0h0) node _T_579 = eq(new_request.param, UInt<3>(0h0)) node _T_580 = eq(new_request.param, UInt<3>(0h4)) node _T_581 = or(_T_579, _T_580) node _T_582 = eq(new_meta.state, UInt<2>(0h2)) node _T_583 = and(_T_581, _T_582) when _T_583 : connect s_writeback, UInt<1>(0h0) node _T_584 = eq(new_request.param, UInt<3>(0h1)) node _T_585 = eq(new_request.param, UInt<3>(0h2)) node _T_586 = or(_T_584, _T_585) node _T_587 = eq(new_request.param, UInt<3>(0h5)) node _T_588 = or(_T_586, _T_587) node _T_589 = and(new_meta.clients, new_clientBit) node _T_590 = neq(_T_589, UInt<1>(0h0)) node _T_591 = and(_T_588, _T_590) when _T_591 : connect s_writeback, UInt<1>(0h0) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(new_meta.hit, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed\n at MSHR.scala:585 assert (new_meta.hit)\n") : printf_69 assert(clock, new_meta.hit, UInt<1>(0h1), "") : assert_69 else : node _T_595 = and(new_request.control, UInt<1>(0h1)) when _T_595 : connect s_flush, UInt<1>(0h0) when new_meta.hit : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_596 = neq(new_meta.clients, UInt<1>(0h0)) node _T_597 = and(UInt<1>(0h1), _T_596) when _T_597 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) else : connect s_execute, UInt<1>(0h0) node _T_598 = eq(new_meta.hit, UInt<1>(0h0)) node _T_599 = neq(new_meta.state, UInt<2>(0h0)) node _T_600 = and(_T_598, _T_599) when _T_600 : connect s_release, UInt<1>(0h0) connect w_releaseack, UInt<1>(0h0) node _T_601 = neq(new_meta.clients, UInt<1>(0h0)) node _T_602 = and(UInt<1>(0h1), _T_601) when _T_602 : connect s_rprobe, UInt<1>(0h0) connect w_rprobeackfirst, UInt<1>(0h0) connect w_rprobeacklast, UInt<1>(0h0) node _T_603 = eq(new_meta.hit, UInt<1>(0h0)) node _T_604 = eq(new_meta.state, UInt<2>(0h1)) node _T_605 = and(_T_604, new_needT) node _T_606 = or(_T_603, _T_605) when _T_606 : connect s_acquire, UInt<1>(0h0) connect w_grantfirst, UInt<1>(0h0) connect w_grantlast, UInt<1>(0h0) connect w_grant, UInt<1>(0h0) connect s_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_607 = eq(new_meta.state, UInt<2>(0h2)) node _T_608 = or(new_needT, _T_607) node _T_609 = and(new_meta.hit, _T_608) node _T_610 = not(new_skipProbe) node _T_611 = and(new_meta.clients, _T_610) node _T_612 = neq(_T_611, UInt<1>(0h0)) node _T_613 = and(_T_609, _T_612) node _T_614 = and(UInt<1>(0h1), _T_613) when _T_614 : connect s_pprobe, UInt<1>(0h0) connect w_pprobeackfirst, UInt<1>(0h0) connect w_pprobeacklast, UInt<1>(0h0) connect w_pprobeack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_615 = eq(new_request.opcode, UInt<3>(0h6)) node _T_616 = eq(new_request.opcode, UInt<3>(0h7)) node _T_617 = or(_T_615, _T_616) when _T_617 : connect w_grantack, UInt<1>(0h0) connect s_writeback, UInt<1>(0h0) node _T_618 = bits(new_request.opcode, 2, 2) node _T_619 = eq(_T_618, UInt<1>(0h0)) node _T_620 = and(_T_619, new_meta.hit) node _T_621 = eq(new_meta.dirty, UInt<1>(0h0)) node _T_622 = and(_T_620, _T_621) when _T_622 : connect s_writeback, UInt<1>(0h0)
module MSHR_1( // @[MSHR.scala:84:7] input clock, // @[MSHR.scala:84:7] input reset, // @[MSHR.scala:84:7] input io_allocate_valid, // @[MSHR.scala:86:14] input io_allocate_bits_prio_0, // @[MSHR.scala:86:14] input io_allocate_bits_prio_1, // @[MSHR.scala:86:14] input io_allocate_bits_prio_2, // @[MSHR.scala:86:14] input io_allocate_bits_control, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_param, // @[MSHR.scala:86:14] input [2:0] io_allocate_bits_size, // @[MSHR.scala:86:14] input [6:0] io_allocate_bits_source, // @[MSHR.scala:86:14] input [12:0] io_allocate_bits_tag, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_offset, // @[MSHR.scala:86:14] input [5:0] io_allocate_bits_put, // @[MSHR.scala:86:14] input [9:0] io_allocate_bits_set, // @[MSHR.scala:86:14] input io_allocate_bits_repeat, // @[MSHR.scala:86:14] input io_directory_valid, // @[MSHR.scala:86:14] input io_directory_bits_dirty, // @[MSHR.scala:86:14] input [1:0] io_directory_bits_state, // @[MSHR.scala:86:14] input [3:0] io_directory_bits_clients, // @[MSHR.scala:86:14] input [12:0] io_directory_bits_tag, // @[MSHR.scala:86:14] input io_directory_bits_hit, // @[MSHR.scala:86:14] input [2:0] io_directory_bits_way, // @[MSHR.scala:86:14] output io_status_valid, // @[MSHR.scala:86:14] output [9:0] io_status_bits_set, // @[MSHR.scala:86:14] output [12:0] io_status_bits_tag, // @[MSHR.scala:86:14] output [2:0] io_status_bits_way, // @[MSHR.scala:86:14] output io_status_bits_blockB, // @[MSHR.scala:86:14] output io_status_bits_nestB, // @[MSHR.scala:86:14] output io_status_bits_blockC, // @[MSHR.scala:86:14] output io_status_bits_nestC, // @[MSHR.scala:86:14] input io_schedule_ready, // @[MSHR.scala:86:14] output io_schedule_valid, // @[MSHR.scala:86:14] output io_schedule_bits_a_valid, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_a_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_a_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_a_bits_param, // @[MSHR.scala:86:14] output io_schedule_bits_a_bits_block, // @[MSHR.scala:86:14] output io_schedule_bits_b_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_b_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_b_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_b_bits_set, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_b_bits_clients, // @[MSHR.scala:86:14] output io_schedule_bits_c_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_param, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_c_bits_tag, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_c_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_c_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_c_bits_dirty, // @[MSHR.scala:86:14] output io_schedule_bits_d_valid, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_0, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_1, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_prio_2, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_control, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_opcode, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_param, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_size, // @[MSHR.scala:86:14] output [6:0] io_schedule_bits_d_bits_source, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_d_bits_tag, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_offset, // @[MSHR.scala:86:14] output [5:0] io_schedule_bits_d_bits_put, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_d_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_d_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_d_bits_bad, // @[MSHR.scala:86:14] output io_schedule_bits_e_valid, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_e_bits_sink, // @[MSHR.scala:86:14] output io_schedule_bits_x_valid, // @[MSHR.scala:86:14] output io_schedule_bits_dir_valid, // @[MSHR.scala:86:14] output [9:0] io_schedule_bits_dir_bits_set, // @[MSHR.scala:86:14] output [2:0] io_schedule_bits_dir_bits_way, // @[MSHR.scala:86:14] output io_schedule_bits_dir_bits_data_dirty, // @[MSHR.scala:86:14] output [1:0] io_schedule_bits_dir_bits_data_state, // @[MSHR.scala:86:14] output [3:0] io_schedule_bits_dir_bits_data_clients, // @[MSHR.scala:86:14] output [12:0] io_schedule_bits_dir_bits_data_tag, // @[MSHR.scala:86:14] output io_schedule_bits_reload, // @[MSHR.scala:86:14] input io_sinkc_valid, // @[MSHR.scala:86:14] input io_sinkc_bits_last, // @[MSHR.scala:86:14] input [9:0] io_sinkc_bits_set, // @[MSHR.scala:86:14] input [12:0] io_sinkc_bits_tag, // @[MSHR.scala:86:14] input [6:0] io_sinkc_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkc_bits_param, // @[MSHR.scala:86:14] input io_sinkc_bits_data, // @[MSHR.scala:86:14] input io_sinkd_valid, // @[MSHR.scala:86:14] input io_sinkd_bits_last, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_opcode, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_param, // @[MSHR.scala:86:14] input [3:0] io_sinkd_bits_source, // @[MSHR.scala:86:14] input [2:0] io_sinkd_bits_sink, // @[MSHR.scala:86:14] input io_sinkd_bits_denied, // @[MSHR.scala:86:14] input io_sinke_valid, // @[MSHR.scala:86:14] input [3:0] io_sinke_bits_sink, // @[MSHR.scala:86:14] input [9:0] io_nestedwb_set, // @[MSHR.scala:86:14] input [12:0] io_nestedwb_tag, // @[MSHR.scala:86:14] input io_nestedwb_b_toN, // @[MSHR.scala:86:14] input io_nestedwb_b_toB, // @[MSHR.scala:86:14] input io_nestedwb_b_clr_dirty, // @[MSHR.scala:86:14] input io_nestedwb_c_set_dirty // @[MSHR.scala:86:14] ); wire [12:0] final_meta_writeback_tag; // @[MSHR.scala:215:38] wire [3:0] final_meta_writeback_clients; // @[MSHR.scala:215:38] wire [1:0] final_meta_writeback_state; // @[MSHR.scala:215:38] wire final_meta_writeback_dirty; // @[MSHR.scala:215:38] wire io_allocate_valid_0 = io_allocate_valid; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_0_0 = io_allocate_bits_prio_0; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_1_0 = io_allocate_bits_prio_1; // @[MSHR.scala:84:7] wire io_allocate_bits_prio_2_0 = io_allocate_bits_prio_2; // @[MSHR.scala:84:7] wire io_allocate_bits_control_0 = io_allocate_bits_control; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_opcode_0 = io_allocate_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_param_0 = io_allocate_bits_param; // @[MSHR.scala:84:7] wire [2:0] io_allocate_bits_size_0 = io_allocate_bits_size; // @[MSHR.scala:84:7] wire [6:0] io_allocate_bits_source_0 = io_allocate_bits_source; // @[MSHR.scala:84:7] wire [12:0] io_allocate_bits_tag_0 = io_allocate_bits_tag; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_offset_0 = io_allocate_bits_offset; // @[MSHR.scala:84:7] wire [5:0] io_allocate_bits_put_0 = io_allocate_bits_put; // @[MSHR.scala:84:7] wire [9:0] io_allocate_bits_set_0 = io_allocate_bits_set; // @[MSHR.scala:84:7] wire io_allocate_bits_repeat_0 = io_allocate_bits_repeat; // @[MSHR.scala:84:7] wire io_directory_valid_0 = io_directory_valid; // @[MSHR.scala:84:7] wire io_directory_bits_dirty_0 = io_directory_bits_dirty; // @[MSHR.scala:84:7] wire [1:0] io_directory_bits_state_0 = io_directory_bits_state; // @[MSHR.scala:84:7] wire [3:0] io_directory_bits_clients_0 = io_directory_bits_clients; // @[MSHR.scala:84:7] wire [12:0] io_directory_bits_tag_0 = io_directory_bits_tag; // @[MSHR.scala:84:7] wire io_directory_bits_hit_0 = io_directory_bits_hit; // @[MSHR.scala:84:7] wire [2:0] io_directory_bits_way_0 = io_directory_bits_way; // @[MSHR.scala:84:7] wire io_schedule_ready_0 = io_schedule_ready; // @[MSHR.scala:84:7] wire io_sinkc_valid_0 = io_sinkc_valid; // @[MSHR.scala:84:7] wire io_sinkc_bits_last_0 = io_sinkc_bits_last; // @[MSHR.scala:84:7] wire [9:0] io_sinkc_bits_set_0 = io_sinkc_bits_set; // @[MSHR.scala:84:7] wire [12:0] io_sinkc_bits_tag_0 = io_sinkc_bits_tag; // @[MSHR.scala:84:7] wire [6:0] io_sinkc_bits_source_0 = io_sinkc_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkc_bits_param_0 = io_sinkc_bits_param; // @[MSHR.scala:84:7] wire io_sinkc_bits_data_0 = io_sinkc_bits_data; // @[MSHR.scala:84:7] wire io_sinkd_valid_0 = io_sinkd_valid; // @[MSHR.scala:84:7] wire io_sinkd_bits_last_0 = io_sinkd_bits_last; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_opcode_0 = io_sinkd_bits_opcode; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_param_0 = io_sinkd_bits_param; // @[MSHR.scala:84:7] wire [3:0] io_sinkd_bits_source_0 = io_sinkd_bits_source; // @[MSHR.scala:84:7] wire [2:0] io_sinkd_bits_sink_0 = io_sinkd_bits_sink; // @[MSHR.scala:84:7] wire io_sinkd_bits_denied_0 = io_sinkd_bits_denied; // @[MSHR.scala:84:7] wire io_sinke_valid_0 = io_sinke_valid; // @[MSHR.scala:84:7] wire [3:0] io_sinke_bits_sink_0 = io_sinke_bits_sink; // @[MSHR.scala:84:7] wire [9:0] io_nestedwb_set_0 = io_nestedwb_set; // @[MSHR.scala:84:7] wire [12:0] io_nestedwb_tag_0 = io_nestedwb_tag; // @[MSHR.scala:84:7] wire io_nestedwb_b_toN_0 = io_nestedwb_b_toN; // @[MSHR.scala:84:7] wire io_nestedwb_b_toB_0 = io_nestedwb_b_toB; // @[MSHR.scala:84:7] wire io_nestedwb_b_clr_dirty_0 = io_nestedwb_b_clr_dirty; // @[MSHR.scala:84:7] wire io_nestedwb_c_set_dirty_0 = io_nestedwb_c_set_dirty; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_a_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_c_bits_source = 4'h0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_d_bits_sink = 4'h0; // @[MSHR.scala:84:7] wire [3:0] invalid_clients = 4'h0; // @[MSHR.scala:268:21] wire io_schedule_bits_x_bits_fail = 1'h0; // @[MSHR.scala:84:7] wire _io_schedule_bits_c_valid_T_2 = 1'h0; // @[MSHR.scala:186:68] wire _io_schedule_bits_c_valid_T_3 = 1'h0; // @[MSHR.scala:186:80] wire invalid_dirty = 1'h0; // @[MSHR.scala:268:21] wire _excluded_client_T_7 = 1'h0; // @[Parameters.scala:279:137] wire _after_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _new_skipProbe_T_6 = 1'h0; // @[Parameters.scala:279:137] wire _prior_T_4 = 1'h0; // @[MSHR.scala:323:11] wire _req_clientBit_T_4 = 1'h1; // @[Parameters.scala:56:32] wire _req_clientBit_T_10 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_4 = 1'h1; // @[Parameters.scala:56:32] wire _probe_bit_T_10 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_4 = 1'h1; // @[Parameters.scala:56:32] wire _new_clientBit_T_10 = 1'h1; // @[Parameters.scala:56:32] wire [12:0] invalid_tag = 13'h0; // @[MSHR.scala:268:21] wire [1:0] invalid_state = 2'h0; // @[MSHR.scala:268:21] wire [1:0] _final_meta_writeback_state_T_11 = 2'h1; // @[MSHR.scala:240:70] wire allocate_as_full_prio_0 = io_allocate_bits_prio_0_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_1 = io_allocate_bits_prio_1_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_prio_2 = io_allocate_bits_prio_2_0; // @[MSHR.scala:84:7, :504:34] wire allocate_as_full_control = io_allocate_bits_control_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_opcode = io_allocate_bits_opcode_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_param = io_allocate_bits_param_0; // @[MSHR.scala:84:7, :504:34] wire [2:0] allocate_as_full_size = io_allocate_bits_size_0; // @[MSHR.scala:84:7, :504:34] wire [6:0] allocate_as_full_source = io_allocate_bits_source_0; // @[MSHR.scala:84:7, :504:34] wire [12:0] allocate_as_full_tag = io_allocate_bits_tag_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_offset = io_allocate_bits_offset_0; // @[MSHR.scala:84:7, :504:34] wire [5:0] allocate_as_full_put = io_allocate_bits_put_0; // @[MSHR.scala:84:7, :504:34] wire [9:0] allocate_as_full_set = io_allocate_bits_set_0; // @[MSHR.scala:84:7, :504:34] wire _io_status_bits_blockB_T_8; // @[MSHR.scala:168:40] wire _io_status_bits_nestB_T_4; // @[MSHR.scala:169:93] wire _io_status_bits_blockC_T; // @[MSHR.scala:172:28] wire _io_status_bits_nestC_T_5; // @[MSHR.scala:173:39] wire _io_schedule_valid_T_5; // @[MSHR.scala:193:105] wire _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:184:55] wire _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:283:91] wire _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:185:41] wire [2:0] _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:286:41] wire [12:0] _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:287:41] wire [3:0] _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:289:51] wire _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:186:64] wire [2:0] _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:290:41] wire [2:0] _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:291:41] wire _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:187:57] wire [2:0] _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:298:41] wire _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:188:43] wire _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:189:40] wire _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:190:66] wire _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:310:41] wire [1:0] _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:310:41] wire [3:0] _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:310:41] wire [12:0] _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:310:41] wire no_wait; // @[MSHR.scala:183:83] wire [6:0] _probe_bit_uncommonBits_T = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [6:0] _probe_bit_uncommonBits_T_1 = io_sinkc_bits_source_0; // @[Parameters.scala:52:29] wire [9:0] io_status_bits_set_0; // @[MSHR.scala:84:7] wire [12:0] io_status_bits_tag_0; // @[MSHR.scala:84:7] wire [2:0] io_status_bits_way_0; // @[MSHR.scala:84:7] wire io_status_bits_blockB_0; // @[MSHR.scala:84:7] wire io_status_bits_nestB_0; // @[MSHR.scala:84:7] wire io_status_bits_blockC_0; // @[MSHR.scala:84:7] wire io_status_bits_nestC_0; // @[MSHR.scala:84:7] wire io_status_valid_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_a_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_a_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_a_bits_param_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_bits_block_0; // @[MSHR.scala:84:7] wire io_schedule_bits_a_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_b_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_b_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_b_bits_set_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_b_bits_clients_0; // @[MSHR.scala:84:7] wire io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_param_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_c_bits_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_c_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_c_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_bits_dirty_0; // @[MSHR.scala:84:7] wire io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_0_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_1_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_prio_2_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_control_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_opcode_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_param_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_size_0; // @[MSHR.scala:84:7] wire [6:0] io_schedule_bits_d_bits_source_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_d_bits_tag_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_offset_0; // @[MSHR.scala:84:7] wire [5:0] io_schedule_bits_d_bits_put_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_d_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_d_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_bits_bad_0; // @[MSHR.scala:84:7] wire io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_e_bits_sink_0; // @[MSHR.scala:84:7] wire io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_bits_data_dirty_0; // @[MSHR.scala:84:7] wire [1:0] io_schedule_bits_dir_bits_data_state_0; // @[MSHR.scala:84:7] wire [3:0] io_schedule_bits_dir_bits_data_clients_0; // @[MSHR.scala:84:7] wire [12:0] io_schedule_bits_dir_bits_data_tag_0; // @[MSHR.scala:84:7] wire [9:0] io_schedule_bits_dir_bits_set_0; // @[MSHR.scala:84:7] wire [2:0] io_schedule_bits_dir_bits_way_0; // @[MSHR.scala:84:7] wire io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7] wire io_schedule_bits_reload_0; // @[MSHR.scala:84:7] wire io_schedule_valid_0; // @[MSHR.scala:84:7] reg request_valid; // @[MSHR.scala:97:30] assign io_status_valid_0 = request_valid; // @[MSHR.scala:84:7, :97:30] reg request_prio_0; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_0_0 = request_prio_0; // @[MSHR.scala:84:7, :98:20] reg request_prio_1; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_1_0 = request_prio_1; // @[MSHR.scala:84:7, :98:20] reg request_prio_2; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_prio_2_0 = request_prio_2; // @[MSHR.scala:84:7, :98:20] reg request_control; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_control_0 = request_control; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_opcode; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_opcode_0 = request_opcode; // @[MSHR.scala:84:7, :98:20] reg [2:0] request_param; // @[MSHR.scala:98:20] reg [2:0] request_size; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_size_0 = request_size; // @[MSHR.scala:84:7, :98:20] reg [6:0] request_source; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_source_0 = request_source; // @[MSHR.scala:84:7, :98:20] wire [6:0] _req_clientBit_uncommonBits_T = request_source; // @[Parameters.scala:52:29] wire [6:0] _req_clientBit_uncommonBits_T_1 = request_source; // @[Parameters.scala:52:29] reg [12:0] request_tag; // @[MSHR.scala:98:20] assign io_status_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_tag_0 = request_tag; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_offset; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_offset_0 = request_offset; // @[MSHR.scala:84:7, :98:20] reg [5:0] request_put; // @[MSHR.scala:98:20] assign io_schedule_bits_d_bits_put_0 = request_put; // @[MSHR.scala:84:7, :98:20] reg [9:0] request_set; // @[MSHR.scala:98:20] assign io_status_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_a_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_b_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_c_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_d_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] assign io_schedule_bits_dir_bits_set_0 = request_set; // @[MSHR.scala:84:7, :98:20] reg meta_valid; // @[MSHR.scala:99:27] reg meta_dirty; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_dirty_0 = meta_dirty; // @[MSHR.scala:84:7, :100:17] reg [1:0] meta_state; // @[MSHR.scala:100:17] reg [3:0] meta_clients; // @[MSHR.scala:100:17] reg [12:0] meta_tag; // @[MSHR.scala:100:17] assign io_schedule_bits_c_bits_tag_0 = meta_tag; // @[MSHR.scala:84:7, :100:17] reg meta_hit; // @[MSHR.scala:100:17] reg [2:0] meta_way; // @[MSHR.scala:100:17] assign io_status_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_c_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_d_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] assign io_schedule_bits_dir_bits_way_0 = meta_way; // @[MSHR.scala:84:7, :100:17] wire [2:0] final_meta_writeback_way = meta_way; // @[MSHR.scala:100:17, :215:38] reg s_rprobe; // @[MSHR.scala:121:33] reg w_rprobeackfirst; // @[MSHR.scala:122:33] reg w_rprobeacklast; // @[MSHR.scala:123:33] reg s_release; // @[MSHR.scala:124:33] reg w_releaseack; // @[MSHR.scala:125:33] reg s_pprobe; // @[MSHR.scala:126:33] reg s_acquire; // @[MSHR.scala:127:33] reg s_flush; // @[MSHR.scala:128:33] reg w_grantfirst; // @[MSHR.scala:129:33] reg w_grantlast; // @[MSHR.scala:130:33] reg w_grant; // @[MSHR.scala:131:33] reg w_pprobeackfirst; // @[MSHR.scala:132:33] reg w_pprobeacklast; // @[MSHR.scala:133:33] reg w_pprobeack; // @[MSHR.scala:134:33] reg s_grantack; // @[MSHR.scala:136:33] reg s_execute; // @[MSHR.scala:137:33] reg w_grantack; // @[MSHR.scala:138:33] reg s_writeback; // @[MSHR.scala:139:33] reg [2:0] sink; // @[MSHR.scala:147:17] assign io_schedule_bits_e_bits_sink_0 = sink; // @[MSHR.scala:84:7, :147:17] reg gotT; // @[MSHR.scala:148:17] reg bad_grant; // @[MSHR.scala:149:22] assign io_schedule_bits_d_bits_bad_0 = bad_grant; // @[MSHR.scala:84:7, :149:22] reg [3:0] probes_done; // @[MSHR.scala:150:24] reg [3:0] probes_toN; // @[MSHR.scala:151:23] reg probes_noT; // @[MSHR.scala:152:23] wire _io_status_bits_blockB_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28] wire _io_status_bits_blockB_T_1 = ~w_releaseack; // @[MSHR.scala:125:33, :168:45] wire _io_status_bits_blockB_T_2 = ~w_rprobeacklast; // @[MSHR.scala:123:33, :168:62] wire _io_status_bits_blockB_T_3 = _io_status_bits_blockB_T_1 | _io_status_bits_blockB_T_2; // @[MSHR.scala:168:{45,59,62}] wire _io_status_bits_blockB_T_4 = ~w_pprobeacklast; // @[MSHR.scala:133:33, :168:82] wire _io_status_bits_blockB_T_5 = _io_status_bits_blockB_T_3 | _io_status_bits_blockB_T_4; // @[MSHR.scala:168:{59,79,82}] wire _io_status_bits_blockB_T_6 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103] wire _io_status_bits_blockB_T_7 = _io_status_bits_blockB_T_5 & _io_status_bits_blockB_T_6; // @[MSHR.scala:168:{79,100,103}] assign _io_status_bits_blockB_T_8 = _io_status_bits_blockB_T | _io_status_bits_blockB_T_7; // @[MSHR.scala:168:{28,40,100}] assign io_status_bits_blockB_0 = _io_status_bits_blockB_T_8; // @[MSHR.scala:84:7, :168:40] wire _io_status_bits_nestB_T = meta_valid & w_releaseack; // @[MSHR.scala:99:27, :125:33, :169:39] wire _io_status_bits_nestB_T_1 = _io_status_bits_nestB_T & w_rprobeacklast; // @[MSHR.scala:123:33, :169:{39,55}] wire _io_status_bits_nestB_T_2 = _io_status_bits_nestB_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :169:{55,74}] wire _io_status_bits_nestB_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :169:96] assign _io_status_bits_nestB_T_4 = _io_status_bits_nestB_T_2 & _io_status_bits_nestB_T_3; // @[MSHR.scala:169:{74,93,96}] assign io_status_bits_nestB_0 = _io_status_bits_nestB_T_4; // @[MSHR.scala:84:7, :169:93] assign _io_status_bits_blockC_T = ~meta_valid; // @[MSHR.scala:99:27, :168:28, :172:28] assign io_status_bits_blockC_0 = _io_status_bits_blockC_T; // @[MSHR.scala:84:7, :172:28] wire _io_status_bits_nestC_T = ~w_rprobeackfirst; // @[MSHR.scala:122:33, :173:43] wire _io_status_bits_nestC_T_1 = ~w_pprobeackfirst; // @[MSHR.scala:132:33, :173:64] wire _io_status_bits_nestC_T_2 = _io_status_bits_nestC_T | _io_status_bits_nestC_T_1; // @[MSHR.scala:173:{43,61,64}] wire _io_status_bits_nestC_T_3 = ~w_grantfirst; // @[MSHR.scala:129:33, :168:103, :173:85] wire _io_status_bits_nestC_T_4 = _io_status_bits_nestC_T_2 | _io_status_bits_nestC_T_3; // @[MSHR.scala:173:{61,82,85}] assign _io_status_bits_nestC_T_5 = meta_valid & _io_status_bits_nestC_T_4; // @[MSHR.scala:99:27, :173:{39,82}] assign io_status_bits_nestC_0 = _io_status_bits_nestC_T_5; // @[MSHR.scala:84:7, :173:39] wire _no_wait_T = w_rprobeacklast & w_releaseack; // @[MSHR.scala:123:33, :125:33, :183:33] wire _no_wait_T_1 = _no_wait_T & w_grantlast; // @[MSHR.scala:130:33, :183:{33,49}] wire _no_wait_T_2 = _no_wait_T_1 & w_pprobeacklast; // @[MSHR.scala:133:33, :183:{49,64}] assign no_wait = _no_wait_T_2 & w_grantack; // @[MSHR.scala:138:33, :183:{64,83}] assign io_schedule_bits_reload_0 = no_wait; // @[MSHR.scala:84:7, :183:83] wire _io_schedule_bits_a_valid_T = ~s_acquire; // @[MSHR.scala:127:33, :184:31] wire _io_schedule_bits_a_valid_T_1 = _io_schedule_bits_a_valid_T & s_release; // @[MSHR.scala:124:33, :184:{31,42}] assign _io_schedule_bits_a_valid_T_2 = _io_schedule_bits_a_valid_T_1 & s_pprobe; // @[MSHR.scala:126:33, :184:{42,55}] assign io_schedule_bits_a_valid_0 = _io_schedule_bits_a_valid_T_2; // @[MSHR.scala:84:7, :184:55] wire _io_schedule_bits_b_valid_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31] wire _io_schedule_bits_b_valid_T_1 = ~s_pprobe; // @[MSHR.scala:126:33, :185:44] assign _io_schedule_bits_b_valid_T_2 = _io_schedule_bits_b_valid_T | _io_schedule_bits_b_valid_T_1; // @[MSHR.scala:185:{31,41,44}] assign io_schedule_bits_b_valid_0 = _io_schedule_bits_b_valid_T_2; // @[MSHR.scala:84:7, :185:41] wire _io_schedule_bits_c_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32] wire _io_schedule_bits_c_valid_T_1 = _io_schedule_bits_c_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :186:{32,43}] assign _io_schedule_bits_c_valid_T_4 = _io_schedule_bits_c_valid_T_1; // @[MSHR.scala:186:{43,64}] assign io_schedule_bits_c_valid_0 = _io_schedule_bits_c_valid_T_4; // @[MSHR.scala:84:7, :186:64] wire _io_schedule_bits_d_valid_T = ~s_execute; // @[MSHR.scala:137:33, :187:31] wire _io_schedule_bits_d_valid_T_1 = _io_schedule_bits_d_valid_T & w_pprobeack; // @[MSHR.scala:134:33, :187:{31,42}] assign _io_schedule_bits_d_valid_T_2 = _io_schedule_bits_d_valid_T_1 & w_grant; // @[MSHR.scala:131:33, :187:{42,57}] assign io_schedule_bits_d_valid_0 = _io_schedule_bits_d_valid_T_2; // @[MSHR.scala:84:7, :187:57] wire _io_schedule_bits_e_valid_T = ~s_grantack; // @[MSHR.scala:136:33, :188:31] assign _io_schedule_bits_e_valid_T_1 = _io_schedule_bits_e_valid_T & w_grantfirst; // @[MSHR.scala:129:33, :188:{31,43}] assign io_schedule_bits_e_valid_0 = _io_schedule_bits_e_valid_T_1; // @[MSHR.scala:84:7, :188:43] wire _io_schedule_bits_x_valid_T = ~s_flush; // @[MSHR.scala:128:33, :189:31] assign _io_schedule_bits_x_valid_T_1 = _io_schedule_bits_x_valid_T & w_releaseack; // @[MSHR.scala:125:33, :189:{31,40}] assign io_schedule_bits_x_valid_0 = _io_schedule_bits_x_valid_T_1; // @[MSHR.scala:84:7, :189:40] wire _io_schedule_bits_dir_valid_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :190:34] wire _io_schedule_bits_dir_valid_T_1 = _io_schedule_bits_dir_valid_T & w_rprobeackfirst; // @[MSHR.scala:122:33, :190:{34,45}] wire _io_schedule_bits_dir_valid_T_2 = ~s_writeback; // @[MSHR.scala:139:33, :190:70] wire _io_schedule_bits_dir_valid_T_3 = _io_schedule_bits_dir_valid_T_2 & no_wait; // @[MSHR.scala:183:83, :190:{70,83}] assign _io_schedule_bits_dir_valid_T_4 = _io_schedule_bits_dir_valid_T_1 | _io_schedule_bits_dir_valid_T_3; // @[MSHR.scala:190:{45,66,83}] assign io_schedule_bits_dir_valid_0 = _io_schedule_bits_dir_valid_T_4; // @[MSHR.scala:84:7, :190:66] wire _io_schedule_valid_T = io_schedule_bits_a_valid_0 | io_schedule_bits_b_valid_0; // @[MSHR.scala:84:7, :192:49] wire _io_schedule_valid_T_1 = _io_schedule_valid_T | io_schedule_bits_c_valid_0; // @[MSHR.scala:84:7, :192:{49,77}] wire _io_schedule_valid_T_2 = _io_schedule_valid_T_1 | io_schedule_bits_d_valid_0; // @[MSHR.scala:84:7, :192:{77,105}] wire _io_schedule_valid_T_3 = _io_schedule_valid_T_2 | io_schedule_bits_e_valid_0; // @[MSHR.scala:84:7, :192:105, :193:49] wire _io_schedule_valid_T_4 = _io_schedule_valid_T_3 | io_schedule_bits_x_valid_0; // @[MSHR.scala:84:7, :193:{49,77}] assign _io_schedule_valid_T_5 = _io_schedule_valid_T_4 | io_schedule_bits_dir_valid_0; // @[MSHR.scala:84:7, :193:{77,105}] assign io_schedule_valid_0 = _io_schedule_valid_T_5; // @[MSHR.scala:84:7, :193:105] wire _io_schedule_bits_dir_bits_data_WIRE_dirty = final_meta_writeback_dirty; // @[MSHR.scala:215:38, :310:71] wire [1:0] _io_schedule_bits_dir_bits_data_WIRE_state = final_meta_writeback_state; // @[MSHR.scala:215:38, :310:71] wire [3:0] _io_schedule_bits_dir_bits_data_WIRE_clients = final_meta_writeback_clients; // @[MSHR.scala:215:38, :310:71] wire [12:0] _io_schedule_bits_dir_bits_data_WIRE_tag = final_meta_writeback_tag; // @[MSHR.scala:215:38, :310:71] wire final_meta_writeback_hit; // @[MSHR.scala:215:38] wire _req_clientBit_T = request_source == 7'h44; // @[Parameters.scala:46:9] wire _req_clientBit_T_1 = request_source == 7'h40; // @[Parameters.scala:46:9] wire [2:0] req_clientBit_uncommonBits = _req_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _req_clientBit_T_2 = request_source[6:3]; // @[Parameters.scala:54:10] wire [3:0] _req_clientBit_T_8 = request_source[6:3]; // @[Parameters.scala:54:10] wire _req_clientBit_T_3 = _req_clientBit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_5 = _req_clientBit_T_3; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_6 = req_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_7 = _req_clientBit_T_5 & _req_clientBit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20] wire [2:0] req_clientBit_uncommonBits_1 = _req_clientBit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _req_clientBit_T_9 = _req_clientBit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _req_clientBit_T_11 = _req_clientBit_T_9; // @[Parameters.scala:54:{32,67}] wire _req_clientBit_T_12 = req_clientBit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _req_clientBit_T_13 = _req_clientBit_T_11 & _req_clientBit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] req_clientBit_lo = {_req_clientBit_T_1, _req_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] req_clientBit_hi = {_req_clientBit_T_13, _req_clientBit_T_7}; // @[Parameters.scala:56:48] wire [3:0] req_clientBit = {req_clientBit_hi, req_clientBit_lo}; // @[Parameters.scala:201:10] wire _req_needT_T = request_opcode[2]; // @[Parameters.scala:269:12] wire _final_meta_writeback_dirty_T_3 = request_opcode[2]; // @[Parameters.scala:269:12] wire _req_needT_T_1 = ~_req_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN = request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _req_needT_T_2; // @[Parameters.scala:270:13] assign _req_needT_T_2 = _GEN; // @[Parameters.scala:270:13] wire _excluded_client_T_6; // @[Parameters.scala:279:117] assign _excluded_client_T_6 = _GEN; // @[Parameters.scala:270:13, :279:117] wire _GEN_0 = request_param == 3'h1; // @[Parameters.scala:270:42] wire _req_needT_T_3; // @[Parameters.scala:270:42] assign _req_needT_T_3 = _GEN_0; // @[Parameters.scala:270:42] wire _final_meta_writeback_clients_T; // @[Parameters.scala:282:11] assign _final_meta_writeback_clients_T = _GEN_0; // @[Parameters.scala:270:42, :282:11] wire _io_schedule_bits_d_bits_param_T_7; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_7 = _GEN_0; // @[Parameters.scala:270:42] wire _req_needT_T_4 = _req_needT_T_2 & _req_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _req_needT_T_5 = _req_needT_T_1 | _req_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _GEN_1 = request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _req_needT_T_6; // @[Parameters.scala:271:14] assign _req_needT_T_6 = _GEN_1; // @[Parameters.scala:271:14] wire _req_acquire_T; // @[MSHR.scala:219:36] assign _req_acquire_T = _GEN_1; // @[Parameters.scala:271:14] wire _excluded_client_T_1; // @[Parameters.scala:279:12] assign _excluded_client_T_1 = _GEN_1; // @[Parameters.scala:271:14, :279:12] wire _req_needT_T_7 = &request_opcode; // @[Parameters.scala:271:52] wire _req_needT_T_8 = _req_needT_T_6 | _req_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _req_needT_T_9 = |request_param; // @[Parameters.scala:271:89] wire _req_needT_T_10 = _req_needT_T_8 & _req_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire req_needT = _req_needT_T_5 | _req_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _req_acquire_T_1 = &request_opcode; // @[Parameters.scala:271:52] wire req_acquire = _req_acquire_T | _req_acquire_T_1; // @[MSHR.scala:219:{36,53,71}] wire _meta_no_clients_T = |meta_clients; // @[MSHR.scala:100:17, :220:39] wire meta_no_clients = ~_meta_no_clients_T; // @[MSHR.scala:220:{25,39}] wire _req_promoteT_T = &meta_state; // @[MSHR.scala:100:17, :221:81] wire _req_promoteT_T_1 = meta_no_clients & _req_promoteT_T; // @[MSHR.scala:220:25, :221:{67,81}] wire _req_promoteT_T_2 = meta_hit ? _req_promoteT_T_1 : gotT; // @[MSHR.scala:100:17, :148:17, :221:{40,67}] wire req_promoteT = req_acquire & _req_promoteT_T_2; // @[MSHR.scala:219:53, :221:{34,40}] wire _final_meta_writeback_dirty_T = request_opcode[0]; // @[MSHR.scala:98:20, :224:65] wire _final_meta_writeback_dirty_T_1 = meta_dirty | _final_meta_writeback_dirty_T; // @[MSHR.scala:100:17, :224:{48,65}] wire _final_meta_writeback_state_T = request_param != 3'h3; // @[MSHR.scala:98:20, :225:55] wire _GEN_2 = meta_state == 2'h2; // @[MSHR.scala:100:17, :225:78] wire _final_meta_writeback_state_T_1; // @[MSHR.scala:225:78] assign _final_meta_writeback_state_T_1 = _GEN_2; // @[MSHR.scala:225:78] wire _final_meta_writeback_state_T_12; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_12 = _GEN_2; // @[MSHR.scala:225:78, :240:70] wire _evict_T_2; // @[MSHR.scala:317:26] assign _evict_T_2 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _before_T_1; // @[MSHR.scala:317:26] assign _before_T_1 = _GEN_2; // @[MSHR.scala:225:78, :317:26] wire _final_meta_writeback_state_T_2 = _final_meta_writeback_state_T & _final_meta_writeback_state_T_1; // @[MSHR.scala:225:{55,64,78}] wire [1:0] _final_meta_writeback_state_T_3 = _final_meta_writeback_state_T_2 ? 2'h3 : meta_state; // @[MSHR.scala:100:17, :225:{40,64}] wire _GEN_3 = request_param == 3'h2; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:43] assign _final_meta_writeback_clients_T_1 = _GEN_3; // @[Parameters.scala:282:43] wire _io_schedule_bits_d_bits_param_T_5; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_5 = _GEN_3; // @[Parameters.scala:282:43] wire _final_meta_writeback_clients_T_2 = _final_meta_writeback_clients_T | _final_meta_writeback_clients_T_1; // @[Parameters.scala:282:{11,34,43}] wire _final_meta_writeback_clients_T_3 = request_param == 3'h5; // @[Parameters.scala:282:75] wire _final_meta_writeback_clients_T_4 = _final_meta_writeback_clients_T_2 | _final_meta_writeback_clients_T_3; // @[Parameters.scala:282:{34,66,75}] wire [3:0] _final_meta_writeback_clients_T_5 = _final_meta_writeback_clients_T_4 ? req_clientBit : 4'h0; // @[Parameters.scala:201:10, :282:66] wire [3:0] _final_meta_writeback_clients_T_6 = ~_final_meta_writeback_clients_T_5; // @[MSHR.scala:226:{52,56}] wire [3:0] _final_meta_writeback_clients_T_7 = meta_clients & _final_meta_writeback_clients_T_6; // @[MSHR.scala:100:17, :226:{50,52}] wire [3:0] _final_meta_writeback_clients_T_8 = ~probes_toN; // @[MSHR.scala:151:23, :232:54] wire [3:0] _final_meta_writeback_clients_T_9 = meta_clients & _final_meta_writeback_clients_T_8; // @[MSHR.scala:100:17, :232:{52,54}] wire _final_meta_writeback_dirty_T_2 = meta_hit & meta_dirty; // @[MSHR.scala:100:17, :236:45] wire _final_meta_writeback_dirty_T_4 = ~_final_meta_writeback_dirty_T_3; // @[MSHR.scala:236:{63,78}] wire _final_meta_writeback_dirty_T_5 = _final_meta_writeback_dirty_T_2 | _final_meta_writeback_dirty_T_4; // @[MSHR.scala:236:{45,60,63}] wire [1:0] _GEN_4 = {1'h1, ~req_acquire}; // @[MSHR.scala:219:53, :238:40] wire [1:0] _final_meta_writeback_state_T_4; // @[MSHR.scala:238:40] assign _final_meta_writeback_state_T_4 = _GEN_4; // @[MSHR.scala:238:40] wire [1:0] _final_meta_writeback_state_T_6; // @[MSHR.scala:239:65] assign _final_meta_writeback_state_T_6 = _GEN_4; // @[MSHR.scala:238:40, :239:65] wire _final_meta_writeback_state_T_5 = ~meta_hit; // @[MSHR.scala:100:17, :239:41] wire [1:0] _final_meta_writeback_state_T_7 = gotT ? _final_meta_writeback_state_T_6 : 2'h1; // @[MSHR.scala:148:17, :239:{55,65}] wire _final_meta_writeback_state_T_8 = meta_no_clients & req_acquire; // @[MSHR.scala:219:53, :220:25, :244:72] wire [1:0] _final_meta_writeback_state_T_9 = {1'h1, ~_final_meta_writeback_state_T_8}; // @[MSHR.scala:244:{55,72}] wire _GEN_5 = meta_state == 2'h1; // @[MSHR.scala:100:17, :240:70] wire _final_meta_writeback_state_T_10; // @[MSHR.scala:240:70] assign _final_meta_writeback_state_T_10 = _GEN_5; // @[MSHR.scala:240:70] wire _io_schedule_bits_c_bits_param_T; // @[MSHR.scala:291:53] assign _io_schedule_bits_c_bits_param_T = _GEN_5; // @[MSHR.scala:240:70, :291:53] wire _evict_T_1; // @[MSHR.scala:317:26] assign _evict_T_1 = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire _before_T; // @[MSHR.scala:317:26] assign _before_T = _GEN_5; // @[MSHR.scala:240:70, :317:26] wire [1:0] _final_meta_writeback_state_T_13 = {_final_meta_writeback_state_T_12, 1'h1}; // @[MSHR.scala:240:70] wire _final_meta_writeback_state_T_14 = &meta_state; // @[MSHR.scala:100:17, :221:81, :240:70] wire [1:0] _final_meta_writeback_state_T_15 = _final_meta_writeback_state_T_14 ? _final_meta_writeback_state_T_9 : _final_meta_writeback_state_T_13; // @[MSHR.scala:240:70, :244:55] wire [1:0] _final_meta_writeback_state_T_16 = _final_meta_writeback_state_T_5 ? _final_meta_writeback_state_T_7 : _final_meta_writeback_state_T_15; // @[MSHR.scala:239:{40,41,55}, :240:70] wire [1:0] _final_meta_writeback_state_T_17 = req_needT ? _final_meta_writeback_state_T_4 : _final_meta_writeback_state_T_16; // @[Parameters.scala:270:70] wire [3:0] _final_meta_writeback_clients_T_10 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :245:66] wire [3:0] _final_meta_writeback_clients_T_11 = meta_clients & _final_meta_writeback_clients_T_10; // @[MSHR.scala:100:17, :245:{64,66}] wire [3:0] _final_meta_writeback_clients_T_12 = meta_hit ? _final_meta_writeback_clients_T_11 : 4'h0; // @[MSHR.scala:100:17, :245:{40,64}] wire [3:0] _final_meta_writeback_clients_T_13 = req_acquire ? req_clientBit : 4'h0; // @[Parameters.scala:201:10] wire [3:0] _final_meta_writeback_clients_T_14 = _final_meta_writeback_clients_T_12 | _final_meta_writeback_clients_T_13; // @[MSHR.scala:245:{40,84}, :246:40] assign final_meta_writeback_tag = request_prio_2 | request_control ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :215:38, :223:52, :228:53, :247:30] wire [3:0] _final_meta_writeback_clients_T_15 = ~probes_toN; // @[MSHR.scala:151:23, :232:54, :258:54] wire [3:0] _final_meta_writeback_clients_T_16 = meta_clients & _final_meta_writeback_clients_T_15; // @[MSHR.scala:100:17, :258:{52,54}] assign final_meta_writeback_hit = bad_grant ? meta_hit : request_prio_2 | ~request_control; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :227:34, :228:53, :234:30, :248:30, :251:20, :252:21] assign final_meta_writeback_dirty = ~bad_grant & (request_prio_2 ? _final_meta_writeback_dirty_T_1 : request_control ? ~meta_hit & meta_dirty : _final_meta_writeback_dirty_T_5); // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :224:{34,48}, :228:53, :229:21, :230:36, :236:{32,60}, :251:20, :252:21] assign final_meta_writeback_state = bad_grant ? {1'h0, meta_hit} : request_prio_2 ? _final_meta_writeback_state_T_3 : request_control ? (meta_hit ? 2'h0 : meta_state) : _final_meta_writeback_state_T_17; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :225:{34,40}, :228:53, :229:21, :231:36, :237:{32,38}, :251:20, :252:21, :257:36, :263:36] assign final_meta_writeback_clients = bad_grant ? (meta_hit ? _final_meta_writeback_clients_T_16 : 4'h0) : request_prio_2 ? _final_meta_writeback_clients_T_7 : request_control ? (meta_hit ? _final_meta_writeback_clients_T_9 : meta_clients) : _final_meta_writeback_clients_T_14; // @[MSHR.scala:98:20, :100:17, :149:22, :215:38, :223:52, :226:{34,50}, :228:53, :229:21, :232:{36,52}, :245:{34,84}, :251:20, :252:21, :258:{36,52}, :264:36] wire [3:0] _honour_BtoT_T = meta_clients & req_clientBit; // @[Parameters.scala:201:10] wire _honour_BtoT_T_1 = |_honour_BtoT_T; // @[MSHR.scala:276:{47,64}] wire honour_BtoT = meta_hit & _honour_BtoT_T_1; // @[MSHR.scala:100:17, :276:{30,64}] wire _excluded_client_T = meta_hit & request_prio_0; // @[MSHR.scala:98:20, :100:17, :279:38] wire _excluded_client_T_2 = &request_opcode; // @[Parameters.scala:271:52, :279:50] wire _excluded_client_T_3 = _excluded_client_T_1 | _excluded_client_T_2; // @[Parameters.scala:279:{12,40,50}] wire _excluded_client_T_4 = request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _excluded_client_T_5 = _excluded_client_T_3 | _excluded_client_T_4; // @[Parameters.scala:279:{40,77,87}] wire _excluded_client_T_8 = _excluded_client_T_5; // @[Parameters.scala:279:{77,106}] wire _excluded_client_T_9 = _excluded_client_T & _excluded_client_T_8; // @[Parameters.scala:279:106] wire [3:0] excluded_client = _excluded_client_T_9 ? req_clientBit : 4'h0; // @[Parameters.scala:201:10] wire [1:0] _io_schedule_bits_a_bits_param_T = meta_hit ? 2'h2 : 2'h1; // @[MSHR.scala:100:17, :282:56] wire [1:0] _io_schedule_bits_a_bits_param_T_1 = req_needT ? _io_schedule_bits_a_bits_param_T : 2'h0; // @[Parameters.scala:270:70] assign io_schedule_bits_a_bits_param_0 = {1'h0, _io_schedule_bits_a_bits_param_T_1}; // @[MSHR.scala:84:7, :282:{35,41}] wire _io_schedule_bits_a_bits_block_T = request_size != 3'h6; // @[MSHR.scala:98:20, :283:51] wire _io_schedule_bits_a_bits_block_T_1 = request_opcode == 3'h0; // @[MSHR.scala:98:20, :284:55] wire _io_schedule_bits_a_bits_block_T_2 = &request_opcode; // @[Parameters.scala:271:52] wire _io_schedule_bits_a_bits_block_T_3 = _io_schedule_bits_a_bits_block_T_1 | _io_schedule_bits_a_bits_block_T_2; // @[MSHR.scala:284:{55,71,89}] wire _io_schedule_bits_a_bits_block_T_4 = ~_io_schedule_bits_a_bits_block_T_3; // @[MSHR.scala:284:{38,71}] assign _io_schedule_bits_a_bits_block_T_5 = _io_schedule_bits_a_bits_block_T | _io_schedule_bits_a_bits_block_T_4; // @[MSHR.scala:283:{51,91}, :284:38] assign io_schedule_bits_a_bits_block_0 = _io_schedule_bits_a_bits_block_T_5; // @[MSHR.scala:84:7, :283:91] wire _io_schedule_bits_b_bits_param_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :286:42] wire [1:0] _io_schedule_bits_b_bits_param_T_1 = req_needT ? 2'h2 : 2'h1; // @[Parameters.scala:270:70] wire [2:0] _io_schedule_bits_b_bits_param_T_2 = request_prio_1 ? request_param : {1'h0, _io_schedule_bits_b_bits_param_T_1}; // @[MSHR.scala:98:20, :286:{61,97}] assign _io_schedule_bits_b_bits_param_T_3 = _io_schedule_bits_b_bits_param_T ? 3'h2 : _io_schedule_bits_b_bits_param_T_2; // @[MSHR.scala:286:{41,42,61}] assign io_schedule_bits_b_bits_param_0 = _io_schedule_bits_b_bits_param_T_3; // @[MSHR.scala:84:7, :286:41] wire _io_schedule_bits_b_bits_tag_T = ~s_rprobe; // @[MSHR.scala:121:33, :185:31, :287:42] assign _io_schedule_bits_b_bits_tag_T_1 = _io_schedule_bits_b_bits_tag_T ? meta_tag : request_tag; // @[MSHR.scala:98:20, :100:17, :287:{41,42}] assign io_schedule_bits_b_bits_tag_0 = _io_schedule_bits_b_bits_tag_T_1; // @[MSHR.scala:84:7, :287:41] wire [3:0] _io_schedule_bits_b_bits_clients_T = ~excluded_client; // @[MSHR.scala:279:28, :289:53] assign _io_schedule_bits_b_bits_clients_T_1 = meta_clients & _io_schedule_bits_b_bits_clients_T; // @[MSHR.scala:100:17, :289:{51,53}] assign io_schedule_bits_b_bits_clients_0 = _io_schedule_bits_b_bits_clients_T_1; // @[MSHR.scala:84:7, :289:51] assign _io_schedule_bits_c_bits_opcode_T = {2'h3, meta_dirty}; // @[MSHR.scala:100:17, :290:41] assign io_schedule_bits_c_bits_opcode_0 = _io_schedule_bits_c_bits_opcode_T; // @[MSHR.scala:84:7, :290:41] assign _io_schedule_bits_c_bits_param_T_1 = _io_schedule_bits_c_bits_param_T ? 3'h2 : 3'h1; // @[MSHR.scala:291:{41,53}] assign io_schedule_bits_c_bits_param_0 = _io_schedule_bits_c_bits_param_T_1; // @[MSHR.scala:84:7, :291:41] wire _io_schedule_bits_d_bits_param_T = ~req_acquire; // @[MSHR.scala:219:53, :298:42] wire [1:0] _io_schedule_bits_d_bits_param_T_1 = {1'h0, req_promoteT}; // @[MSHR.scala:221:34, :300:53] wire [1:0] _io_schedule_bits_d_bits_param_T_2 = honour_BtoT ? 2'h2 : 2'h1; // @[MSHR.scala:276:30, :301:53] wire _io_schedule_bits_d_bits_param_T_3 = ~(|request_param); // @[Parameters.scala:271:89] wire [2:0] _io_schedule_bits_d_bits_param_T_4 = _io_schedule_bits_d_bits_param_T_3 ? {1'h0, _io_schedule_bits_d_bits_param_T_1} : request_param; // @[MSHR.scala:98:20, :299:79, :300:53] wire [2:0] _io_schedule_bits_d_bits_param_T_6 = _io_schedule_bits_d_bits_param_T_5 ? {1'h0, _io_schedule_bits_d_bits_param_T_2} : _io_schedule_bits_d_bits_param_T_4; // @[MSHR.scala:299:79, :301:53] wire [2:0] _io_schedule_bits_d_bits_param_T_8 = _io_schedule_bits_d_bits_param_T_7 ? 3'h1 : _io_schedule_bits_d_bits_param_T_6; // @[MSHR.scala:299:79] assign _io_schedule_bits_d_bits_param_T_9 = _io_schedule_bits_d_bits_param_T ? request_param : _io_schedule_bits_d_bits_param_T_8; // @[MSHR.scala:98:20, :298:{41,42}, :299:79] assign io_schedule_bits_d_bits_param_0 = _io_schedule_bits_d_bits_param_T_9; // @[MSHR.scala:84:7, :298:41] wire _io_schedule_bits_dir_bits_data_T = ~s_release; // @[MSHR.scala:124:33, :186:32, :310:42] assign _io_schedule_bits_dir_bits_data_T_1_dirty = ~_io_schedule_bits_dir_bits_data_T & _io_schedule_bits_dir_bits_data_WIRE_dirty; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_state = _io_schedule_bits_dir_bits_data_T ? 2'h0 : _io_schedule_bits_dir_bits_data_WIRE_state; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_clients = _io_schedule_bits_dir_bits_data_T ? 4'h0 : _io_schedule_bits_dir_bits_data_WIRE_clients; // @[MSHR.scala:310:{41,42,71}] assign _io_schedule_bits_dir_bits_data_T_1_tag = _io_schedule_bits_dir_bits_data_T ? 13'h0 : _io_schedule_bits_dir_bits_data_WIRE_tag; // @[MSHR.scala:310:{41,42,71}] assign io_schedule_bits_dir_bits_data_dirty_0 = _io_schedule_bits_dir_bits_data_T_1_dirty; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_state_0 = _io_schedule_bits_dir_bits_data_T_1_state; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_clients_0 = _io_schedule_bits_dir_bits_data_T_1_clients; // @[MSHR.scala:84:7, :310:41] assign io_schedule_bits_dir_bits_data_tag_0 = _io_schedule_bits_dir_bits_data_T_1_tag; // @[MSHR.scala:84:7, :310:41] wire _evict_T = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :338:32] wire [3:0] evict; // @[MSHR.scala:314:26] wire evict_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _evict_out_T = ~evict_c; // @[MSHR.scala:315:27, :318:32] wire [1:0] _GEN_6 = {1'h1, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32] wire [1:0] _evict_out_T_1; // @[MSHR.scala:319:32] assign _evict_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire [1:0] _before_out_T_1; // @[MSHR.scala:319:32] assign _before_out_T_1 = _GEN_6; // @[MSHR.scala:319:32] wire _evict_T_3 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _GEN_7 = {2'h2, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:39] wire [2:0] _evict_out_T_2; // @[MSHR.scala:320:39] assign _evict_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _before_out_T_2; // @[MSHR.scala:320:39] assign _before_out_T_2 = _GEN_7; // @[MSHR.scala:320:39] wire [2:0] _GEN_8 = {2'h3, ~meta_dirty}; // @[MSHR.scala:100:17, :319:32, :320:76] wire [2:0] _evict_out_T_3; // @[MSHR.scala:320:76] assign _evict_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _before_out_T_3; // @[MSHR.scala:320:76] assign _before_out_T_3 = _GEN_8; // @[MSHR.scala:320:76] wire [2:0] _evict_out_T_4 = evict_c ? _evict_out_T_2 : _evict_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _evict_T_4 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _evict_T_5 = ~_evict_T; // @[MSHR.scala:323:11, :338:32] assign evict = _evict_T_5 ? 4'h8 : _evict_T_1 ? {3'h0, _evict_out_T} : _evict_T_2 ? {2'h0, _evict_out_T_1} : _evict_T_3 ? {1'h0, _evict_out_T_4} : {_evict_T_4, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] before_0; // @[MSHR.scala:314:26] wire before_c = |meta_clients; // @[MSHR.scala:100:17, :220:39, :315:27] wire _before_out_T = ~before_c; // @[MSHR.scala:315:27, :318:32] wire _before_T_2 = &meta_state; // @[MSHR.scala:100:17, :221:81, :317:26] wire [2:0] _before_out_T_4 = before_c ? _before_out_T_2 : _before_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _before_T_3 = ~(|meta_state); // @[MSHR.scala:100:17, :104:22, :317:26] wire _before_T_4 = ~meta_hit; // @[MSHR.scala:100:17, :239:41, :323:11] assign before_0 = _before_T_4 ? 4'h8 : _before_T ? {3'h0, _before_out_T} : _before_T_1 ? {2'h0, _before_out_T_1} : _before_T_2 ? {1'h0, _before_out_T_4} : {_before_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26, :323:{11,17,23}] wire [3:0] after; // @[MSHR.scala:314:26] wire after_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _GEN_9 = final_meta_writeback_state == 2'h1; // @[MSHR.scala:215:38, :317:26] wire _after_T; // @[MSHR.scala:317:26] assign _after_T = _GEN_9; // @[MSHR.scala:317:26] wire _prior_T; // @[MSHR.scala:317:26] assign _prior_T = _GEN_9; // @[MSHR.scala:317:26] wire _after_out_T = ~after_c; // @[MSHR.scala:315:27, :318:32] wire _GEN_10 = final_meta_writeback_state == 2'h2; // @[MSHR.scala:215:38, :317:26] wire _after_T_1; // @[MSHR.scala:317:26] assign _after_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire _prior_T_1; // @[MSHR.scala:317:26] assign _prior_T_1 = _GEN_10; // @[MSHR.scala:317:26] wire [1:0] _GEN_11 = {1'h1, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32] wire [1:0] _after_out_T_1; // @[MSHR.scala:319:32] assign _after_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire [1:0] _prior_out_T_1; // @[MSHR.scala:319:32] assign _prior_out_T_1 = _GEN_11; // @[MSHR.scala:319:32] wire _after_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _GEN_12 = {2'h2, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:39] wire [2:0] _after_out_T_2; // @[MSHR.scala:320:39] assign _after_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _prior_out_T_2; // @[MSHR.scala:320:39] assign _prior_out_T_2 = _GEN_12; // @[MSHR.scala:320:39] wire [2:0] _GEN_13 = {2'h3, ~final_meta_writeback_dirty}; // @[MSHR.scala:215:38, :319:32, :320:76] wire [2:0] _after_out_T_3; // @[MSHR.scala:320:76] assign _after_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _prior_out_T_3; // @[MSHR.scala:320:76] assign _prior_out_T_3 = _GEN_13; // @[MSHR.scala:320:76] wire [2:0] _after_out_T_4 = after_c ? _after_out_T_2 : _after_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] wire _GEN_14 = final_meta_writeback_state == 2'h0; // @[MSHR.scala:215:38, :317:26] wire _after_T_3; // @[MSHR.scala:317:26] assign _after_T_3 = _GEN_14; // @[MSHR.scala:317:26] wire _prior_T_3; // @[MSHR.scala:317:26] assign _prior_T_3 = _GEN_14; // @[MSHR.scala:317:26] assign after = _after_T ? {3'h0, _after_out_T} : _after_T_1 ? {2'h0, _after_out_T_1} : _after_T_2 ? {1'h0, _after_out_T_4} : {_after_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _probe_bit_T = io_sinkc_bits_source_0 == 7'h44; // @[Parameters.scala:46:9] wire _probe_bit_T_1 = io_sinkc_bits_source_0 == 7'h40; // @[Parameters.scala:46:9] wire [2:0] probe_bit_uncommonBits = _probe_bit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _probe_bit_T_2 = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10] wire [3:0] _probe_bit_T_8 = io_sinkc_bits_source_0[6:3]; // @[Parameters.scala:54:10] wire _probe_bit_T_3 = _probe_bit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_5 = _probe_bit_T_3; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_6 = probe_bit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_7 = _probe_bit_T_5 & _probe_bit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20] wire [2:0] probe_bit_uncommonBits_1 = _probe_bit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _probe_bit_T_9 = _probe_bit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _probe_bit_T_11 = _probe_bit_T_9; // @[Parameters.scala:54:{32,67}] wire _probe_bit_T_12 = probe_bit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _probe_bit_T_13 = _probe_bit_T_11 & _probe_bit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] probe_bit_lo = {_probe_bit_T_1, _probe_bit_T}; // @[Parameters.scala:46:9] wire [1:0] probe_bit_hi = {_probe_bit_T_13, _probe_bit_T_7}; // @[Parameters.scala:56:48] wire [3:0] probe_bit = {probe_bit_hi, probe_bit_lo}; // @[Parameters.scala:201:10] wire [3:0] _GEN_15 = probes_done | probe_bit; // @[Parameters.scala:201:10] wire [3:0] _last_probe_T; // @[MSHR.scala:459:33] assign _last_probe_T = _GEN_15; // @[MSHR.scala:459:33] wire [3:0] _probes_done_T; // @[MSHR.scala:467:32] assign _probes_done_T = _GEN_15; // @[MSHR.scala:459:33, :467:32] wire [3:0] _last_probe_T_1 = ~excluded_client; // @[MSHR.scala:279:28, :289:53, :459:66] wire [3:0] _last_probe_T_2 = meta_clients & _last_probe_T_1; // @[MSHR.scala:100:17, :459:{64,66}] wire last_probe = _last_probe_T == _last_probe_T_2; // @[MSHR.scala:459:{33,46,64}] wire _probe_toN_T = io_sinkc_bits_param_0 == 3'h1; // @[Parameters.scala:282:11] wire _probe_toN_T_1 = io_sinkc_bits_param_0 == 3'h2; // @[Parameters.scala:282:43] wire _probe_toN_T_2 = _probe_toN_T | _probe_toN_T_1; // @[Parameters.scala:282:{11,34,43}] wire _probe_toN_T_3 = io_sinkc_bits_param_0 == 3'h5; // @[Parameters.scala:282:75] wire probe_toN = _probe_toN_T_2 | _probe_toN_T_3; // @[Parameters.scala:282:{34,66,75}] wire [3:0] _probes_toN_T = probe_toN ? probe_bit : 4'h0; // @[Parameters.scala:201:10, :282:66] wire [3:0] _probes_toN_T_1 = probes_toN | _probes_toN_T; // @[MSHR.scala:151:23, :468:{30,35}] wire _probes_noT_T = io_sinkc_bits_param_0 != 3'h3; // @[MSHR.scala:84:7, :469:53] wire _probes_noT_T_1 = probes_noT | _probes_noT_T; // @[MSHR.scala:152:23, :469:{30,53}] wire _w_rprobeackfirst_T = w_rprobeackfirst | last_probe; // @[MSHR.scala:122:33, :459:46, :470:42] wire _GEN_16 = last_probe & io_sinkc_bits_last_0; // @[MSHR.scala:84:7, :459:46, :471:55] wire _w_rprobeacklast_T; // @[MSHR.scala:471:55] assign _w_rprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55] wire _w_pprobeacklast_T; // @[MSHR.scala:473:55] assign _w_pprobeacklast_T = _GEN_16; // @[MSHR.scala:471:55, :473:55] wire _w_rprobeacklast_T_1 = w_rprobeacklast | _w_rprobeacklast_T; // @[MSHR.scala:123:33, :471:{40,55}] wire _w_pprobeackfirst_T = w_pprobeackfirst | last_probe; // @[MSHR.scala:132:33, :459:46, :472:42] wire _w_pprobeacklast_T_1 = w_pprobeacklast | _w_pprobeacklast_T; // @[MSHR.scala:133:33, :473:{40,55}] wire _set_pprobeack_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77] wire _set_pprobeack_T_1 = io_sinkc_bits_last_0 | _set_pprobeack_T; // @[MSHR.scala:84:7, :475:{59,77}] wire set_pprobeack = last_probe & _set_pprobeack_T_1; // @[MSHR.scala:459:46, :475:{36,59}] wire _w_pprobeack_T = w_pprobeack | set_pprobeack; // @[MSHR.scala:134:33, :475:36, :476:32] wire _w_grant_T = ~(|request_offset); // @[MSHR.scala:98:20, :475:77, :490:33] wire _w_grant_T_1 = _w_grant_T | io_sinkd_bits_last_0; // @[MSHR.scala:84:7, :490:{33,41}] wire _gotT_T = io_sinkd_bits_param_0 == 3'h0; // @[MSHR.scala:84:7, :493:35] wire _new_meta_T = io_allocate_valid_0 & io_allocate_bits_repeat_0; // @[MSHR.scala:84:7, :505:40] wire new_meta_dirty = _new_meta_T ? final_meta_writeback_dirty : io_directory_bits_dirty_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [1:0] new_meta_state = _new_meta_T ? final_meta_writeback_state : io_directory_bits_state_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [3:0] new_meta_clients = _new_meta_T ? final_meta_writeback_clients : io_directory_bits_clients_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [12:0] new_meta_tag = _new_meta_T ? final_meta_writeback_tag : io_directory_bits_tag_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_meta_hit = _new_meta_T ? final_meta_writeback_hit : io_directory_bits_hit_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire [2:0] new_meta_way = _new_meta_T ? final_meta_writeback_way : io_directory_bits_way_0; // @[MSHR.scala:84:7, :215:38, :505:{21,40}] wire new_request_prio_0 = io_allocate_valid_0 ? allocate_as_full_prio_0 : request_prio_0; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_1 = io_allocate_valid_0 ? allocate_as_full_prio_1 : request_prio_1; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_prio_2 = io_allocate_valid_0 ? allocate_as_full_prio_2 : request_prio_2; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire new_request_control = io_allocate_valid_0 ? allocate_as_full_control : request_control; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_opcode = io_allocate_valid_0 ? allocate_as_full_opcode : request_opcode; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_param = io_allocate_valid_0 ? allocate_as_full_param : request_param; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [2:0] new_request_size = io_allocate_valid_0 ? allocate_as_full_size : request_size; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] new_request_source = io_allocate_valid_0 ? allocate_as_full_source : request_source; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [12:0] new_request_tag = io_allocate_valid_0 ? allocate_as_full_tag : request_tag; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_offset = io_allocate_valid_0 ? allocate_as_full_offset : request_offset; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [5:0] new_request_put = io_allocate_valid_0 ? allocate_as_full_put : request_put; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [9:0] new_request_set = io_allocate_valid_0 ? allocate_as_full_set : request_set; // @[MSHR.scala:84:7, :98:20, :504:34, :506:24] wire [6:0] _new_clientBit_uncommonBits_T = new_request_source; // @[Parameters.scala:52:29] wire [6:0] _new_clientBit_uncommonBits_T_1 = new_request_source; // @[Parameters.scala:52:29] wire _new_needT_T = new_request_opcode[2]; // @[Parameters.scala:269:12] wire _new_needT_T_1 = ~_new_needT_T; // @[Parameters.scala:269:{5,12}] wire _GEN_17 = new_request_opcode == 3'h5; // @[Parameters.scala:270:13] wire _new_needT_T_2; // @[Parameters.scala:270:13] assign _new_needT_T_2 = _GEN_17; // @[Parameters.scala:270:13] wire _new_skipProbe_T_5; // @[Parameters.scala:279:117] assign _new_skipProbe_T_5 = _GEN_17; // @[Parameters.scala:270:13, :279:117] wire _new_needT_T_3 = new_request_param == 3'h1; // @[Parameters.scala:270:42] wire _new_needT_T_4 = _new_needT_T_2 & _new_needT_T_3; // @[Parameters.scala:270:{13,33,42}] wire _new_needT_T_5 = _new_needT_T_1 | _new_needT_T_4; // @[Parameters.scala:269:{5,16}, :270:33] wire _T_615 = new_request_opcode == 3'h6; // @[Parameters.scala:271:14] wire _new_needT_T_6; // @[Parameters.scala:271:14] assign _new_needT_T_6 = _T_615; // @[Parameters.scala:271:14] wire _new_skipProbe_T; // @[Parameters.scala:279:12] assign _new_skipProbe_T = _T_615; // @[Parameters.scala:271:14, :279:12] wire _new_needT_T_7 = &new_request_opcode; // @[Parameters.scala:271:52] wire _new_needT_T_8 = _new_needT_T_6 | _new_needT_T_7; // @[Parameters.scala:271:{14,42,52}] wire _new_needT_T_9 = |new_request_param; // @[Parameters.scala:271:89] wire _new_needT_T_10 = _new_needT_T_8 & _new_needT_T_9; // @[Parameters.scala:271:{42,80,89}] wire new_needT = _new_needT_T_5 | _new_needT_T_10; // @[Parameters.scala:269:16, :270:70, :271:80] wire _new_clientBit_T = new_request_source == 7'h44; // @[Parameters.scala:46:9] wire _new_clientBit_T_1 = new_request_source == 7'h40; // @[Parameters.scala:46:9] wire [2:0] new_clientBit_uncommonBits = _new_clientBit_uncommonBits_T[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _new_clientBit_T_2 = new_request_source[6:3]; // @[Parameters.scala:54:10] wire [3:0] _new_clientBit_T_8 = new_request_source[6:3]; // @[Parameters.scala:54:10] wire _new_clientBit_T_3 = _new_clientBit_T_2 == 4'h6; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_5 = _new_clientBit_T_3; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_6 = new_clientBit_uncommonBits < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_7 = _new_clientBit_T_5 & _new_clientBit_T_6; // @[Parameters.scala:54:67, :56:48, :57:20] wire [2:0] new_clientBit_uncommonBits_1 = _new_clientBit_uncommonBits_T_1[2:0]; // @[Parameters.scala:52:{29,56}] wire _new_clientBit_T_9 = _new_clientBit_T_8 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _new_clientBit_T_11 = _new_clientBit_T_9; // @[Parameters.scala:54:{32,67}] wire _new_clientBit_T_12 = new_clientBit_uncommonBits_1 < 3'h5; // @[Parameters.scala:52:56, :57:20] wire _new_clientBit_T_13 = _new_clientBit_T_11 & _new_clientBit_T_12; // @[Parameters.scala:54:67, :56:48, :57:20] wire [1:0] new_clientBit_lo = {_new_clientBit_T_1, _new_clientBit_T}; // @[Parameters.scala:46:9] wire [1:0] new_clientBit_hi = {_new_clientBit_T_13, _new_clientBit_T_7}; // @[Parameters.scala:56:48] wire [3:0] new_clientBit = {new_clientBit_hi, new_clientBit_lo}; // @[Parameters.scala:201:10] wire _new_skipProbe_T_1 = &new_request_opcode; // @[Parameters.scala:271:52, :279:50] wire _new_skipProbe_T_2 = _new_skipProbe_T | _new_skipProbe_T_1; // @[Parameters.scala:279:{12,40,50}] wire _new_skipProbe_T_3 = new_request_opcode == 3'h4; // @[Parameters.scala:279:87] wire _new_skipProbe_T_4 = _new_skipProbe_T_2 | _new_skipProbe_T_3; // @[Parameters.scala:279:{40,77,87}] wire _new_skipProbe_T_7 = _new_skipProbe_T_4; // @[Parameters.scala:279:{77,106}] wire [3:0] new_skipProbe = _new_skipProbe_T_7 ? new_clientBit : 4'h0; // @[Parameters.scala:201:10, :279:106] wire [3:0] prior; // @[MSHR.scala:314:26] wire prior_c = |final_meta_writeback_clients; // @[MSHR.scala:215:38, :315:27] wire _prior_out_T = ~prior_c; // @[MSHR.scala:315:27, :318:32] wire _prior_T_2 = &final_meta_writeback_state; // @[MSHR.scala:215:38, :317:26] wire [2:0] _prior_out_T_4 = prior_c ? _prior_out_T_2 : _prior_out_T_3; // @[MSHR.scala:315:27, :320:{32,39,76}] assign prior = _prior_T ? {3'h0, _prior_out_T} : _prior_T_1 ? {2'h0, _prior_out_T_1} : _prior_T_2 ? {1'h0, _prior_out_T_4} : {_prior_T_3, 3'h0}; // @[MSHR.scala:314:26, :317:26, :318:{26,32}, :319:{26,32}, :320:{26,32}, :321:26] wire _T_574 = io_directory_valid_0 | _new_meta_T; // @[MSHR.scala:84:7, :505:40, :539:28]
Generate the Verilog code corresponding to this FIRRTL code module TLSlaveToNoC_4 : input clock : Clock input reset : Reset output io : { tilelink : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<6>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}}}, flits : { flip a : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, b : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip c : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}, d : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, egress_id : UInt}}, flip e : { flip ready : UInt<1>, valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, ingress_id : UInt}}}} inst a of TLAFromNoC_4 connect a.clock, clock connect a.reset, reset inst b of TLBToNoC_4 connect b.clock, clock connect b.reset, reset inst c of TLCFromNoC_4 connect c.clock, clock connect c.reset, reset inst d of TLDToNoC_4 connect d.clock, clock connect d.reset, reset inst e of TLEFromNoC_4 connect e.clock, clock connect e.reset, reset connect io.tilelink.a.bits, a.io.protocol.bits connect io.tilelink.a.valid, a.io.protocol.valid connect a.io.protocol.ready, io.tilelink.a.ready connect b.io.protocol, io.tilelink.b connect io.tilelink.c.bits, c.io.protocol.bits connect io.tilelink.c.valid, c.io.protocol.valid connect c.io.protocol.ready, io.tilelink.c.ready connect d.io.protocol, io.tilelink.d connect io.tilelink.e.bits, e.io.protocol.bits connect io.tilelink.e.valid, e.io.protocol.valid connect e.io.protocol.ready, io.tilelink.e.ready connect a.io.flit, io.flits.a connect io.flits.b.bits, b.io.flit.bits connect io.flits.b.valid, b.io.flit.valid connect b.io.flit.ready, io.flits.b.ready connect c.io.flit, io.flits.c connect io.flits.d.bits, d.io.flit.bits connect io.flits.d.valid, d.io.flit.valid connect d.io.flit.ready, io.flits.d.ready connect e.io.flit, io.flits.e
module TLSlaveToNoC_4( // @[Tilelink.scala:125:7] input clock, // @[Tilelink.scala:125:7] input reset, // @[Tilelink.scala:125:7] input io_tilelink_a_ready, // @[Tilelink.scala:132:14] output io_tilelink_a_valid, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_a_bits_opcode, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_a_bits_param, // @[Tilelink.scala:132:14] output [3:0] io_tilelink_a_bits_size, // @[Tilelink.scala:132:14] output [5:0] io_tilelink_a_bits_source, // @[Tilelink.scala:132:14] output [31:0] io_tilelink_a_bits_address, // @[Tilelink.scala:132:14] output [7:0] io_tilelink_a_bits_mask, // @[Tilelink.scala:132:14] output [63:0] io_tilelink_a_bits_data, // @[Tilelink.scala:132:14] output io_tilelink_a_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_b_ready, // @[Tilelink.scala:132:14] input io_tilelink_b_valid, // @[Tilelink.scala:132:14] input [1:0] io_tilelink_b_bits_param, // @[Tilelink.scala:132:14] input [5:0] io_tilelink_b_bits_source, // @[Tilelink.scala:132:14] input [31:0] io_tilelink_b_bits_address, // @[Tilelink.scala:132:14] input io_tilelink_c_ready, // @[Tilelink.scala:132:14] output io_tilelink_c_valid, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_c_bits_opcode, // @[Tilelink.scala:132:14] output [2:0] io_tilelink_c_bits_param, // @[Tilelink.scala:132:14] output [3:0] io_tilelink_c_bits_size, // @[Tilelink.scala:132:14] output [5:0] io_tilelink_c_bits_source, // @[Tilelink.scala:132:14] output [31:0] io_tilelink_c_bits_address, // @[Tilelink.scala:132:14] output [63:0] io_tilelink_c_bits_data, // @[Tilelink.scala:132:14] output io_tilelink_c_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_d_ready, // @[Tilelink.scala:132:14] input io_tilelink_d_valid, // @[Tilelink.scala:132:14] input [2:0] io_tilelink_d_bits_opcode, // @[Tilelink.scala:132:14] input [1:0] io_tilelink_d_bits_param, // @[Tilelink.scala:132:14] input [3:0] io_tilelink_d_bits_size, // @[Tilelink.scala:132:14] input [5:0] io_tilelink_d_bits_source, // @[Tilelink.scala:132:14] input [4:0] io_tilelink_d_bits_sink, // @[Tilelink.scala:132:14] input io_tilelink_d_bits_denied, // @[Tilelink.scala:132:14] input [63:0] io_tilelink_d_bits_data, // @[Tilelink.scala:132:14] input io_tilelink_d_bits_corrupt, // @[Tilelink.scala:132:14] output io_tilelink_e_valid, // @[Tilelink.scala:132:14] output [4:0] io_tilelink_e_bits_sink, // @[Tilelink.scala:132:14] output io_flits_a_ready, // @[Tilelink.scala:132:14] input io_flits_a_valid, // @[Tilelink.scala:132:14] input io_flits_a_bits_head, // @[Tilelink.scala:132:14] input io_flits_a_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_a_bits_payload, // @[Tilelink.scala:132:14] input io_flits_b_ready, // @[Tilelink.scala:132:14] output io_flits_b_valid, // @[Tilelink.scala:132:14] output io_flits_b_bits_head, // @[Tilelink.scala:132:14] output io_flits_b_bits_tail, // @[Tilelink.scala:132:14] output [72:0] io_flits_b_bits_payload, // @[Tilelink.scala:132:14] output [4:0] io_flits_b_bits_egress_id, // @[Tilelink.scala:132:14] output io_flits_c_ready, // @[Tilelink.scala:132:14] input io_flits_c_valid, // @[Tilelink.scala:132:14] input io_flits_c_bits_head, // @[Tilelink.scala:132:14] input io_flits_c_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_c_bits_payload, // @[Tilelink.scala:132:14] input io_flits_d_ready, // @[Tilelink.scala:132:14] output io_flits_d_valid, // @[Tilelink.scala:132:14] output io_flits_d_bits_head, // @[Tilelink.scala:132:14] output io_flits_d_bits_tail, // @[Tilelink.scala:132:14] output [72:0] io_flits_d_bits_payload, // @[Tilelink.scala:132:14] output [4:0] io_flits_d_bits_egress_id, // @[Tilelink.scala:132:14] input io_flits_e_valid, // @[Tilelink.scala:132:14] input io_flits_e_bits_head, // @[Tilelink.scala:132:14] input io_flits_e_bits_tail, // @[Tilelink.scala:132:14] input [72:0] io_flits_e_bits_payload // @[Tilelink.scala:132:14] ); wire [64:0] _d_io_flit_bits_payload; // @[Tilelink.scala:146:17] TLAFromNoC a ( // @[Tilelink.scala:143:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_a_ready), .io_protocol_valid (io_tilelink_a_valid), .io_protocol_bits_opcode (io_tilelink_a_bits_opcode), .io_protocol_bits_param (io_tilelink_a_bits_param), .io_protocol_bits_size (io_tilelink_a_bits_size), .io_protocol_bits_source (io_tilelink_a_bits_source), .io_protocol_bits_address (io_tilelink_a_bits_address), .io_protocol_bits_mask (io_tilelink_a_bits_mask), .io_protocol_bits_data (io_tilelink_a_bits_data), .io_protocol_bits_corrupt (io_tilelink_a_bits_corrupt), .io_flit_ready (io_flits_a_ready), .io_flit_valid (io_flits_a_valid), .io_flit_bits_head (io_flits_a_bits_head), .io_flit_bits_tail (io_flits_a_bits_tail), .io_flit_bits_payload (io_flits_a_bits_payload) ); // @[Tilelink.scala:143:17] TLBToNoC_1 b ( // @[Tilelink.scala:144:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_b_ready), .io_protocol_valid (io_tilelink_b_valid), .io_protocol_bits_param (io_tilelink_b_bits_param), .io_protocol_bits_source (io_tilelink_b_bits_source), .io_protocol_bits_address (io_tilelink_b_bits_address), .io_flit_ready (io_flits_b_ready), .io_flit_valid (io_flits_b_valid), .io_flit_bits_head (io_flits_b_bits_head), .io_flit_bits_tail (io_flits_b_bits_tail), .io_flit_bits_payload (io_flits_b_bits_payload), .io_flit_bits_egress_id (io_flits_b_bits_egress_id) ); // @[Tilelink.scala:144:17] TLCFromNoC_1 c ( // @[Tilelink.scala:145:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_c_ready), .io_protocol_valid (io_tilelink_c_valid), .io_protocol_bits_opcode (io_tilelink_c_bits_opcode), .io_protocol_bits_param (io_tilelink_c_bits_param), .io_protocol_bits_size (io_tilelink_c_bits_size), .io_protocol_bits_source (io_tilelink_c_bits_source), .io_protocol_bits_address (io_tilelink_c_bits_address), .io_protocol_bits_data (io_tilelink_c_bits_data), .io_protocol_bits_corrupt (io_tilelink_c_bits_corrupt), .io_flit_ready (io_flits_c_ready), .io_flit_valid (io_flits_c_valid), .io_flit_bits_head (io_flits_c_bits_head), .io_flit_bits_tail (io_flits_c_bits_tail), .io_flit_bits_payload (io_flits_c_bits_payload[64:0]) // @[Tilelink.scala:156:14] ); // @[Tilelink.scala:145:17] TLDToNoC_4 d ( // @[Tilelink.scala:146:17] .clock (clock), .reset (reset), .io_protocol_ready (io_tilelink_d_ready), .io_protocol_valid (io_tilelink_d_valid), .io_protocol_bits_opcode (io_tilelink_d_bits_opcode), .io_protocol_bits_param (io_tilelink_d_bits_param), .io_protocol_bits_size (io_tilelink_d_bits_size), .io_protocol_bits_source (io_tilelink_d_bits_source), .io_protocol_bits_sink (io_tilelink_d_bits_sink), .io_protocol_bits_denied (io_tilelink_d_bits_denied), .io_protocol_bits_data (io_tilelink_d_bits_data), .io_protocol_bits_corrupt (io_tilelink_d_bits_corrupt), .io_flit_ready (io_flits_d_ready), .io_flit_valid (io_flits_d_valid), .io_flit_bits_head (io_flits_d_bits_head), .io_flit_bits_tail (io_flits_d_bits_tail), .io_flit_bits_payload (_d_io_flit_bits_payload), .io_flit_bits_egress_id (io_flits_d_bits_egress_id) ); // @[Tilelink.scala:146:17] TLEFromNoC_1 e ( // @[Tilelink.scala:147:17] .clock (clock), .reset (reset), .io_protocol_valid (io_tilelink_e_valid), .io_protocol_bits_sink (io_tilelink_e_bits_sink), .io_flit_valid (io_flits_e_valid), .io_flit_bits_head (io_flits_e_bits_head), .io_flit_bits_tail (io_flits_e_bits_tail), .io_flit_bits_payload (io_flits_e_bits_payload[4:0]) // @[Tilelink.scala:158:14] ); // @[Tilelink.scala:147:17] assign io_flits_d_bits_payload = {8'h0, _d_io_flit_bits_payload}; // @[Tilelink.scala:125:7, :146:17, :157:14] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PMAChecker_14 : input clock : Clock input reset : Reset output io : { flip paddr : UInt, resp : { cacheable : UInt<1>, r : UInt<1>, w : UInt<1>, pp : UInt<1>, al : UInt<1>, aa : UInt<1>, x : UInt<1>, eff : UInt<1>}} node _legal_address_T = xor(io.paddr, UInt<1>(0h0)) node _legal_address_T_1 = cvt(_legal_address_T) node _legal_address_T_2 = and(_legal_address_T_1, asSInt(UInt<13>(0h1000))) node _legal_address_T_3 = asSInt(_legal_address_T_2) node _legal_address_T_4 = eq(_legal_address_T_3, asSInt(UInt<1>(0h0))) node _legal_address_T_5 = xor(io.paddr, UInt<13>(0h1000)) node _legal_address_T_6 = cvt(_legal_address_T_5) node _legal_address_T_7 = and(_legal_address_T_6, asSInt(UInt<13>(0h1000))) node _legal_address_T_8 = asSInt(_legal_address_T_7) node _legal_address_T_9 = eq(_legal_address_T_8, asSInt(UInt<1>(0h0))) node _legal_address_T_10 = xor(io.paddr, UInt<14>(0h3000)) node _legal_address_T_11 = cvt(_legal_address_T_10) node _legal_address_T_12 = and(_legal_address_T_11, asSInt(UInt<13>(0h1000))) node _legal_address_T_13 = asSInt(_legal_address_T_12) node _legal_address_T_14 = eq(_legal_address_T_13, asSInt(UInt<1>(0h0))) node _legal_address_T_15 = xor(io.paddr, UInt<17>(0h10000)) node _legal_address_T_16 = cvt(_legal_address_T_15) node _legal_address_T_17 = and(_legal_address_T_16, asSInt(UInt<17>(0h10000))) node _legal_address_T_18 = asSInt(_legal_address_T_17) node _legal_address_T_19 = eq(_legal_address_T_18, asSInt(UInt<1>(0h0))) node _legal_address_T_20 = xor(io.paddr, UInt<21>(0h100000)) node _legal_address_T_21 = cvt(_legal_address_T_20) node _legal_address_T_22 = and(_legal_address_T_21, asSInt(UInt<13>(0h1000))) node _legal_address_T_23 = asSInt(_legal_address_T_22) node _legal_address_T_24 = eq(_legal_address_T_23, asSInt(UInt<1>(0h0))) node _legal_address_T_25 = xor(io.paddr, UInt<21>(0h110000)) node _legal_address_T_26 = cvt(_legal_address_T_25) node _legal_address_T_27 = and(_legal_address_T_26, asSInt(UInt<13>(0h1000))) node _legal_address_T_28 = asSInt(_legal_address_T_27) node _legal_address_T_29 = eq(_legal_address_T_28, asSInt(UInt<1>(0h0))) node _legal_address_T_30 = xor(io.paddr, UInt<26>(0h2000000)) node _legal_address_T_31 = cvt(_legal_address_T_30) node _legal_address_T_32 = and(_legal_address_T_31, asSInt(UInt<17>(0h10000))) node _legal_address_T_33 = asSInt(_legal_address_T_32) node _legal_address_T_34 = eq(_legal_address_T_33, asSInt(UInt<1>(0h0))) node _legal_address_T_35 = xor(io.paddr, UInt<26>(0h2010000)) node _legal_address_T_36 = cvt(_legal_address_T_35) node _legal_address_T_37 = and(_legal_address_T_36, asSInt(UInt<13>(0h1000))) node _legal_address_T_38 = asSInt(_legal_address_T_37) node _legal_address_T_39 = eq(_legal_address_T_38, asSInt(UInt<1>(0h0))) node _legal_address_T_40 = xor(io.paddr, UInt<28>(0h8000000)) node _legal_address_T_41 = cvt(_legal_address_T_40) node _legal_address_T_42 = and(_legal_address_T_41, asSInt(UInt<17>(0h10000))) node _legal_address_T_43 = asSInt(_legal_address_T_42) node _legal_address_T_44 = eq(_legal_address_T_43, asSInt(UInt<1>(0h0))) node _legal_address_T_45 = xor(io.paddr, UInt<28>(0hc000000)) node _legal_address_T_46 = cvt(_legal_address_T_45) node _legal_address_T_47 = and(_legal_address_T_46, asSInt(UInt<27>(0h4000000))) node _legal_address_T_48 = asSInt(_legal_address_T_47) node _legal_address_T_49 = eq(_legal_address_T_48, asSInt(UInt<1>(0h0))) node _legal_address_T_50 = xor(io.paddr, UInt<29>(0h10020000)) node _legal_address_T_51 = cvt(_legal_address_T_50) node _legal_address_T_52 = and(_legal_address_T_51, asSInt(UInt<13>(0h1000))) node _legal_address_T_53 = asSInt(_legal_address_T_52) node _legal_address_T_54 = eq(_legal_address_T_53, asSInt(UInt<1>(0h0))) node _legal_address_T_55 = xor(io.paddr, UInt<32>(0h80000000)) node _legal_address_T_56 = cvt(_legal_address_T_55) node _legal_address_T_57 = and(_legal_address_T_56, asSInt(UInt<29>(0h10000000))) node _legal_address_T_58 = asSInt(_legal_address_T_57) node _legal_address_T_59 = eq(_legal_address_T_58, asSInt(UInt<1>(0h0))) wire _legal_address_WIRE : UInt<1>[12] connect _legal_address_WIRE[0], _legal_address_T_4 connect _legal_address_WIRE[1], _legal_address_T_9 connect _legal_address_WIRE[2], _legal_address_T_14 connect _legal_address_WIRE[3], _legal_address_T_19 connect _legal_address_WIRE[4], _legal_address_T_24 connect _legal_address_WIRE[5], _legal_address_T_29 connect _legal_address_WIRE[6], _legal_address_T_34 connect _legal_address_WIRE[7], _legal_address_T_39 connect _legal_address_WIRE[8], _legal_address_T_44 connect _legal_address_WIRE[9], _legal_address_T_49 connect _legal_address_WIRE[10], _legal_address_T_54 connect _legal_address_WIRE[11], _legal_address_T_59 node _legal_address_T_60 = or(_legal_address_WIRE[0], _legal_address_WIRE[1]) node _legal_address_T_61 = or(_legal_address_T_60, _legal_address_WIRE[2]) node _legal_address_T_62 = or(_legal_address_T_61, _legal_address_WIRE[3]) node _legal_address_T_63 = or(_legal_address_T_62, _legal_address_WIRE[4]) node _legal_address_T_64 = or(_legal_address_T_63, _legal_address_WIRE[5]) node _legal_address_T_65 = or(_legal_address_T_64, _legal_address_WIRE[6]) node _legal_address_T_66 = or(_legal_address_T_65, _legal_address_WIRE[7]) node _legal_address_T_67 = or(_legal_address_T_66, _legal_address_WIRE[8]) node _legal_address_T_68 = or(_legal_address_T_67, _legal_address_WIRE[9]) node _legal_address_T_69 = or(_legal_address_T_68, _legal_address_WIRE[10]) node legal_address = or(_legal_address_T_69, _legal_address_WIRE[11]) node _io_resp_cacheable_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_cacheable_T_1 = cvt(_io_resp_cacheable_T) node _io_resp_cacheable_T_2 = and(_io_resp_cacheable_T_1, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_3 = asSInt(_io_resp_cacheable_T_2) node _io_resp_cacheable_T_4 = eq(_io_resp_cacheable_T_3, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_5 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_cacheable_T_6 = cvt(_io_resp_cacheable_T_5) node _io_resp_cacheable_T_7 = and(_io_resp_cacheable_T_6, asSInt(UInt<33>(0h8c011000))) node _io_resp_cacheable_T_8 = asSInt(_io_resp_cacheable_T_7) node _io_resp_cacheable_T_9 = eq(_io_resp_cacheable_T_8, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_10 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_cacheable_T_11 = cvt(_io_resp_cacheable_T_10) node _io_resp_cacheable_T_12 = and(_io_resp_cacheable_T_11, asSInt(UInt<33>(0h8c000000))) node _io_resp_cacheable_T_13 = asSInt(_io_resp_cacheable_T_12) node _io_resp_cacheable_T_14 = eq(_io_resp_cacheable_T_13, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_15 = or(_io_resp_cacheable_T_4, _io_resp_cacheable_T_9) node _io_resp_cacheable_T_16 = or(_io_resp_cacheable_T_15, _io_resp_cacheable_T_14) node _io_resp_cacheable_T_17 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_cacheable_T_18 = cvt(_io_resp_cacheable_T_17) node _io_resp_cacheable_T_19 = and(_io_resp_cacheable_T_18, asSInt(UInt<33>(0h8c010000))) node _io_resp_cacheable_T_20 = asSInt(_io_resp_cacheable_T_19) node _io_resp_cacheable_T_21 = eq(_io_resp_cacheable_T_20, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_22 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_cacheable_T_23 = cvt(_io_resp_cacheable_T_22) node _io_resp_cacheable_T_24 = and(_io_resp_cacheable_T_23, asSInt(UInt<33>(0h80000000))) node _io_resp_cacheable_T_25 = asSInt(_io_resp_cacheable_T_24) node _io_resp_cacheable_T_26 = eq(_io_resp_cacheable_T_25, asSInt(UInt<1>(0h0))) node _io_resp_cacheable_T_27 = or(_io_resp_cacheable_T_21, _io_resp_cacheable_T_26) node _io_resp_cacheable_T_28 = mux(_io_resp_cacheable_T_16, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_cacheable_T_29 = mux(_io_resp_cacheable_T_27, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_cacheable_T_30 = or(_io_resp_cacheable_T_28, _io_resp_cacheable_T_29) wire _io_resp_cacheable_WIRE : UInt<1> connect _io_resp_cacheable_WIRE, _io_resp_cacheable_T_30 node _io_resp_cacheable_T_31 = and(legal_address, _io_resp_cacheable_WIRE) connect io.resp.cacheable, _io_resp_cacheable_T_31 node _io_resp_r_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_r_T_1 = cvt(_io_resp_r_T) node _io_resp_r_T_2 = and(_io_resp_r_T_1, asSInt(UInt<1>(0h0))) node _io_resp_r_T_3 = asSInt(_io_resp_r_T_2) node _io_resp_r_T_4 = eq(_io_resp_r_T_3, asSInt(UInt<1>(0h0))) node _io_resp_r_T_5 = and(legal_address, UInt<1>(0h1)) connect io.resp.r, _io_resp_r_T_5 node _io_resp_w_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_w_T_1 = cvt(_io_resp_w_T) node _io_resp_w_T_2 = and(_io_resp_w_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_w_T_3 = asSInt(_io_resp_w_T_2) node _io_resp_w_T_4 = eq(_io_resp_w_T_3, asSInt(UInt<1>(0h0))) node _io_resp_w_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_w_T_6 = cvt(_io_resp_w_T_5) node _io_resp_w_T_7 = and(_io_resp_w_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_w_T_8 = asSInt(_io_resp_w_T_7) node _io_resp_w_T_9 = eq(_io_resp_w_T_8, asSInt(UInt<1>(0h0))) node _io_resp_w_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_w_T_11 = cvt(_io_resp_w_T_10) node _io_resp_w_T_12 = and(_io_resp_w_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_13 = asSInt(_io_resp_w_T_12) node _io_resp_w_T_14 = eq(_io_resp_w_T_13, asSInt(UInt<1>(0h0))) node _io_resp_w_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_16 = cvt(_io_resp_w_T_15) node _io_resp_w_T_17 = and(_io_resp_w_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_w_T_18 = asSInt(_io_resp_w_T_17) node _io_resp_w_T_19 = eq(_io_resp_w_T_18, asSInt(UInt<1>(0h0))) node _io_resp_w_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_w_T_21 = cvt(_io_resp_w_T_20) node _io_resp_w_T_22 = and(_io_resp_w_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_23 = asSInt(_io_resp_w_T_22) node _io_resp_w_T_24 = eq(_io_resp_w_T_23, asSInt(UInt<1>(0h0))) node _io_resp_w_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_w_T_26 = cvt(_io_resp_w_T_25) node _io_resp_w_T_27 = and(_io_resp_w_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_w_T_28 = asSInt(_io_resp_w_T_27) node _io_resp_w_T_29 = eq(_io_resp_w_T_28, asSInt(UInt<1>(0h0))) node _io_resp_w_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_w_T_31 = cvt(_io_resp_w_T_30) node _io_resp_w_T_32 = and(_io_resp_w_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_w_T_33 = asSInt(_io_resp_w_T_32) node _io_resp_w_T_34 = eq(_io_resp_w_T_33, asSInt(UInt<1>(0h0))) node _io_resp_w_T_35 = or(_io_resp_w_T_4, _io_resp_w_T_9) node _io_resp_w_T_36 = or(_io_resp_w_T_35, _io_resp_w_T_14) node _io_resp_w_T_37 = or(_io_resp_w_T_36, _io_resp_w_T_19) node _io_resp_w_T_38 = or(_io_resp_w_T_37, _io_resp_w_T_24) node _io_resp_w_T_39 = or(_io_resp_w_T_38, _io_resp_w_T_29) node _io_resp_w_T_40 = or(_io_resp_w_T_39, _io_resp_w_T_34) node _io_resp_w_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_w_T_42 = cvt(_io_resp_w_T_41) node _io_resp_w_T_43 = and(_io_resp_w_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_w_T_44 = asSInt(_io_resp_w_T_43) node _io_resp_w_T_45 = eq(_io_resp_w_T_44, asSInt(UInt<1>(0h0))) node _io_resp_w_T_46 = mux(_io_resp_w_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_w_T_47 = mux(_io_resp_w_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_w_T_48 = or(_io_resp_w_T_46, _io_resp_w_T_47) wire _io_resp_w_WIRE : UInt<1> connect _io_resp_w_WIRE, _io_resp_w_T_48 node _io_resp_w_T_49 = and(legal_address, _io_resp_w_WIRE) connect io.resp.w, _io_resp_w_T_49 node _io_resp_pp_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_pp_T_1 = cvt(_io_resp_pp_T) node _io_resp_pp_T_2 = and(_io_resp_pp_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_pp_T_3 = asSInt(_io_resp_pp_T_2) node _io_resp_pp_T_4 = eq(_io_resp_pp_T_3, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_pp_T_6 = cvt(_io_resp_pp_T_5) node _io_resp_pp_T_7 = and(_io_resp_pp_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_pp_T_8 = asSInt(_io_resp_pp_T_7) node _io_resp_pp_T_9 = eq(_io_resp_pp_T_8, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_pp_T_11 = cvt(_io_resp_pp_T_10) node _io_resp_pp_T_12 = and(_io_resp_pp_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_13 = asSInt(_io_resp_pp_T_12) node _io_resp_pp_T_14 = eq(_io_resp_pp_T_13, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_16 = cvt(_io_resp_pp_T_15) node _io_resp_pp_T_17 = and(_io_resp_pp_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_pp_T_18 = asSInt(_io_resp_pp_T_17) node _io_resp_pp_T_19 = eq(_io_resp_pp_T_18, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_pp_T_21 = cvt(_io_resp_pp_T_20) node _io_resp_pp_T_22 = and(_io_resp_pp_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_23 = asSInt(_io_resp_pp_T_22) node _io_resp_pp_T_24 = eq(_io_resp_pp_T_23, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_pp_T_26 = cvt(_io_resp_pp_T_25) node _io_resp_pp_T_27 = and(_io_resp_pp_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_pp_T_28 = asSInt(_io_resp_pp_T_27) node _io_resp_pp_T_29 = eq(_io_resp_pp_T_28, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_pp_T_31 = cvt(_io_resp_pp_T_30) node _io_resp_pp_T_32 = and(_io_resp_pp_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_pp_T_33 = asSInt(_io_resp_pp_T_32) node _io_resp_pp_T_34 = eq(_io_resp_pp_T_33, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_35 = or(_io_resp_pp_T_4, _io_resp_pp_T_9) node _io_resp_pp_T_36 = or(_io_resp_pp_T_35, _io_resp_pp_T_14) node _io_resp_pp_T_37 = or(_io_resp_pp_T_36, _io_resp_pp_T_19) node _io_resp_pp_T_38 = or(_io_resp_pp_T_37, _io_resp_pp_T_24) node _io_resp_pp_T_39 = or(_io_resp_pp_T_38, _io_resp_pp_T_29) node _io_resp_pp_T_40 = or(_io_resp_pp_T_39, _io_resp_pp_T_34) node _io_resp_pp_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_pp_T_42 = cvt(_io_resp_pp_T_41) node _io_resp_pp_T_43 = and(_io_resp_pp_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_pp_T_44 = asSInt(_io_resp_pp_T_43) node _io_resp_pp_T_45 = eq(_io_resp_pp_T_44, asSInt(UInt<1>(0h0))) node _io_resp_pp_T_46 = mux(_io_resp_pp_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_pp_T_47 = mux(_io_resp_pp_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_pp_T_48 = or(_io_resp_pp_T_46, _io_resp_pp_T_47) wire _io_resp_pp_WIRE : UInt<1> connect _io_resp_pp_WIRE, _io_resp_pp_T_48 node _io_resp_pp_T_49 = and(legal_address, _io_resp_pp_WIRE) connect io.resp.pp, _io_resp_pp_T_49 node _io_resp_al_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_al_T_1 = cvt(_io_resp_al_T) node _io_resp_al_T_2 = and(_io_resp_al_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_al_T_3 = asSInt(_io_resp_al_T_2) node _io_resp_al_T_4 = eq(_io_resp_al_T_3, asSInt(UInt<1>(0h0))) node _io_resp_al_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_al_T_6 = cvt(_io_resp_al_T_5) node _io_resp_al_T_7 = and(_io_resp_al_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_al_T_8 = asSInt(_io_resp_al_T_7) node _io_resp_al_T_9 = eq(_io_resp_al_T_8, asSInt(UInt<1>(0h0))) node _io_resp_al_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_al_T_11 = cvt(_io_resp_al_T_10) node _io_resp_al_T_12 = and(_io_resp_al_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_13 = asSInt(_io_resp_al_T_12) node _io_resp_al_T_14 = eq(_io_resp_al_T_13, asSInt(UInt<1>(0h0))) node _io_resp_al_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_16 = cvt(_io_resp_al_T_15) node _io_resp_al_T_17 = and(_io_resp_al_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_al_T_18 = asSInt(_io_resp_al_T_17) node _io_resp_al_T_19 = eq(_io_resp_al_T_18, asSInt(UInt<1>(0h0))) node _io_resp_al_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_al_T_21 = cvt(_io_resp_al_T_20) node _io_resp_al_T_22 = and(_io_resp_al_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_23 = asSInt(_io_resp_al_T_22) node _io_resp_al_T_24 = eq(_io_resp_al_T_23, asSInt(UInt<1>(0h0))) node _io_resp_al_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_al_T_26 = cvt(_io_resp_al_T_25) node _io_resp_al_T_27 = and(_io_resp_al_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_al_T_28 = asSInt(_io_resp_al_T_27) node _io_resp_al_T_29 = eq(_io_resp_al_T_28, asSInt(UInt<1>(0h0))) node _io_resp_al_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_al_T_31 = cvt(_io_resp_al_T_30) node _io_resp_al_T_32 = and(_io_resp_al_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_al_T_33 = asSInt(_io_resp_al_T_32) node _io_resp_al_T_34 = eq(_io_resp_al_T_33, asSInt(UInt<1>(0h0))) node _io_resp_al_T_35 = or(_io_resp_al_T_4, _io_resp_al_T_9) node _io_resp_al_T_36 = or(_io_resp_al_T_35, _io_resp_al_T_14) node _io_resp_al_T_37 = or(_io_resp_al_T_36, _io_resp_al_T_19) node _io_resp_al_T_38 = or(_io_resp_al_T_37, _io_resp_al_T_24) node _io_resp_al_T_39 = or(_io_resp_al_T_38, _io_resp_al_T_29) node _io_resp_al_T_40 = or(_io_resp_al_T_39, _io_resp_al_T_34) node _io_resp_al_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_al_T_42 = cvt(_io_resp_al_T_41) node _io_resp_al_T_43 = and(_io_resp_al_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_al_T_44 = asSInt(_io_resp_al_T_43) node _io_resp_al_T_45 = eq(_io_resp_al_T_44, asSInt(UInt<1>(0h0))) node _io_resp_al_T_46 = mux(_io_resp_al_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_al_T_47 = mux(_io_resp_al_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_al_T_48 = or(_io_resp_al_T_46, _io_resp_al_T_47) wire _io_resp_al_WIRE : UInt<1> connect _io_resp_al_WIRE, _io_resp_al_T_48 node _io_resp_al_T_49 = and(legal_address, _io_resp_al_WIRE) connect io.resp.al, _io_resp_al_T_49 node _io_resp_aa_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_aa_T_1 = cvt(_io_resp_aa_T) node _io_resp_aa_T_2 = and(_io_resp_aa_T_1, asSInt(UInt<33>(0h98110000))) node _io_resp_aa_T_3 = asSInt(_io_resp_aa_T_2) node _io_resp_aa_T_4 = eq(_io_resp_aa_T_3, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_aa_T_6 = cvt(_io_resp_aa_T_5) node _io_resp_aa_T_7 = and(_io_resp_aa_T_6, asSInt(UInt<33>(0h9a101000))) node _io_resp_aa_T_8 = asSInt(_io_resp_aa_T_7) node _io_resp_aa_T_9 = eq(_io_resp_aa_T_8, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_10 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_aa_T_11 = cvt(_io_resp_aa_T_10) node _io_resp_aa_T_12 = and(_io_resp_aa_T_11, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_13 = asSInt(_io_resp_aa_T_12) node _io_resp_aa_T_14 = eq(_io_resp_aa_T_13, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_16 = cvt(_io_resp_aa_T_15) node _io_resp_aa_T_17 = and(_io_resp_aa_T_16, asSInt(UInt<33>(0h98000000))) node _io_resp_aa_T_18 = asSInt(_io_resp_aa_T_17) node _io_resp_aa_T_19 = eq(_io_resp_aa_T_18, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_20 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_aa_T_21 = cvt(_io_resp_aa_T_20) node _io_resp_aa_T_22 = and(_io_resp_aa_T_21, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_23 = asSInt(_io_resp_aa_T_22) node _io_resp_aa_T_24 = eq(_io_resp_aa_T_23, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_aa_T_26 = cvt(_io_resp_aa_T_25) node _io_resp_aa_T_27 = and(_io_resp_aa_T_26, asSInt(UInt<33>(0h9a111000))) node _io_resp_aa_T_28 = asSInt(_io_resp_aa_T_27) node _io_resp_aa_T_29 = eq(_io_resp_aa_T_28, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_30 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_aa_T_31 = cvt(_io_resp_aa_T_30) node _io_resp_aa_T_32 = and(_io_resp_aa_T_31, asSInt(UInt<33>(0h90000000))) node _io_resp_aa_T_33 = asSInt(_io_resp_aa_T_32) node _io_resp_aa_T_34 = eq(_io_resp_aa_T_33, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_35 = or(_io_resp_aa_T_4, _io_resp_aa_T_9) node _io_resp_aa_T_36 = or(_io_resp_aa_T_35, _io_resp_aa_T_14) node _io_resp_aa_T_37 = or(_io_resp_aa_T_36, _io_resp_aa_T_19) node _io_resp_aa_T_38 = or(_io_resp_aa_T_37, _io_resp_aa_T_24) node _io_resp_aa_T_39 = or(_io_resp_aa_T_38, _io_resp_aa_T_29) node _io_resp_aa_T_40 = or(_io_resp_aa_T_39, _io_resp_aa_T_34) node _io_resp_aa_T_41 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_aa_T_42 = cvt(_io_resp_aa_T_41) node _io_resp_aa_T_43 = and(_io_resp_aa_T_42, asSInt(UInt<33>(0h9a110000))) node _io_resp_aa_T_44 = asSInt(_io_resp_aa_T_43) node _io_resp_aa_T_45 = eq(_io_resp_aa_T_44, asSInt(UInt<1>(0h0))) node _io_resp_aa_T_46 = mux(_io_resp_aa_T_40, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_aa_T_47 = mux(_io_resp_aa_T_45, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_aa_T_48 = or(_io_resp_aa_T_46, _io_resp_aa_T_47) wire _io_resp_aa_WIRE : UInt<1> connect _io_resp_aa_WIRE, _io_resp_aa_T_48 node _io_resp_aa_T_49 = and(legal_address, _io_resp_aa_WIRE) connect io.resp.aa, _io_resp_aa_T_49 node _io_resp_x_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_x_T_1 = cvt(_io_resp_x_T) node _io_resp_x_T_2 = and(_io_resp_x_T_1, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_3 = asSInt(_io_resp_x_T_2) node _io_resp_x_T_4 = eq(_io_resp_x_T_3, asSInt(UInt<1>(0h0))) node _io_resp_x_T_5 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_x_T_6 = cvt(_io_resp_x_T_5) node _io_resp_x_T_7 = and(_io_resp_x_T_6, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_8 = asSInt(_io_resp_x_T_7) node _io_resp_x_T_9 = eq(_io_resp_x_T_8, asSInt(UInt<1>(0h0))) node _io_resp_x_T_10 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_x_T_11 = cvt(_io_resp_x_T_10) node _io_resp_x_T_12 = and(_io_resp_x_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_13 = asSInt(_io_resp_x_T_12) node _io_resp_x_T_14 = eq(_io_resp_x_T_13, asSInt(UInt<1>(0h0))) node _io_resp_x_T_15 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_x_T_16 = cvt(_io_resp_x_T_15) node _io_resp_x_T_17 = and(_io_resp_x_T_16, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_18 = asSInt(_io_resp_x_T_17) node _io_resp_x_T_19 = eq(_io_resp_x_T_18, asSInt(UInt<1>(0h0))) node _io_resp_x_T_20 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_x_T_21 = cvt(_io_resp_x_T_20) node _io_resp_x_T_22 = and(_io_resp_x_T_21, asSInt(UInt<33>(0h90000000))) node _io_resp_x_T_23 = asSInt(_io_resp_x_T_22) node _io_resp_x_T_24 = eq(_io_resp_x_T_23, asSInt(UInt<1>(0h0))) node _io_resp_x_T_25 = or(_io_resp_x_T_4, _io_resp_x_T_9) node _io_resp_x_T_26 = or(_io_resp_x_T_25, _io_resp_x_T_14) node _io_resp_x_T_27 = or(_io_resp_x_T_26, _io_resp_x_T_19) node _io_resp_x_T_28 = or(_io_resp_x_T_27, _io_resp_x_T_24) node _io_resp_x_T_29 = xor(io.paddr, UInt<13>(0h1000)) node _io_resp_x_T_30 = cvt(_io_resp_x_T_29) node _io_resp_x_T_31 = and(_io_resp_x_T_30, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_32 = asSInt(_io_resp_x_T_31) node _io_resp_x_T_33 = eq(_io_resp_x_T_32, asSInt(UInt<1>(0h0))) node _io_resp_x_T_34 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_x_T_35 = cvt(_io_resp_x_T_34) node _io_resp_x_T_36 = and(_io_resp_x_T_35, asSInt(UInt<33>(0h9e103000))) node _io_resp_x_T_37 = asSInt(_io_resp_x_T_36) node _io_resp_x_T_38 = eq(_io_resp_x_T_37, asSInt(UInt<1>(0h0))) node _io_resp_x_T_39 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_x_T_40 = cvt(_io_resp_x_T_39) node _io_resp_x_T_41 = and(_io_resp_x_T_40, asSInt(UInt<33>(0h9e110000))) node _io_resp_x_T_42 = asSInt(_io_resp_x_T_41) node _io_resp_x_T_43 = eq(_io_resp_x_T_42, asSInt(UInt<1>(0h0))) node _io_resp_x_T_44 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_x_T_45 = cvt(_io_resp_x_T_44) node _io_resp_x_T_46 = and(_io_resp_x_T_45, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_47 = asSInt(_io_resp_x_T_46) node _io_resp_x_T_48 = eq(_io_resp_x_T_47, asSInt(UInt<1>(0h0))) node _io_resp_x_T_49 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_x_T_50 = cvt(_io_resp_x_T_49) node _io_resp_x_T_51 = and(_io_resp_x_T_50, asSInt(UInt<33>(0h9c000000))) node _io_resp_x_T_52 = asSInt(_io_resp_x_T_51) node _io_resp_x_T_53 = eq(_io_resp_x_T_52, asSInt(UInt<1>(0h0))) node _io_resp_x_T_54 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_x_T_55 = cvt(_io_resp_x_T_54) node _io_resp_x_T_56 = and(_io_resp_x_T_55, asSInt(UInt<33>(0h9e113000))) node _io_resp_x_T_57 = asSInt(_io_resp_x_T_56) node _io_resp_x_T_58 = eq(_io_resp_x_T_57, asSInt(UInt<1>(0h0))) node _io_resp_x_T_59 = or(_io_resp_x_T_33, _io_resp_x_T_38) node _io_resp_x_T_60 = or(_io_resp_x_T_59, _io_resp_x_T_43) node _io_resp_x_T_61 = or(_io_resp_x_T_60, _io_resp_x_T_48) node _io_resp_x_T_62 = or(_io_resp_x_T_61, _io_resp_x_T_53) node _io_resp_x_T_63 = or(_io_resp_x_T_62, _io_resp_x_T_58) node _io_resp_x_T_64 = mux(_io_resp_x_T_28, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_x_T_65 = mux(_io_resp_x_T_63, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_x_T_66 = or(_io_resp_x_T_64, _io_resp_x_T_65) wire _io_resp_x_WIRE : UInt<1> connect _io_resp_x_WIRE, _io_resp_x_T_66 node _io_resp_x_T_67 = and(legal_address, _io_resp_x_WIRE) connect io.resp.x, _io_resp_x_T_67 node _io_resp_eff_T = xor(io.paddr, UInt<1>(0h0)) node _io_resp_eff_T_1 = cvt(_io_resp_eff_T) node _io_resp_eff_T_2 = and(_io_resp_eff_T_1, asSInt(UInt<33>(0h9e112000))) node _io_resp_eff_T_3 = asSInt(_io_resp_eff_T_2) node _io_resp_eff_T_4 = eq(_io_resp_eff_T_3, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_5 = xor(io.paddr, UInt<21>(0h100000)) node _io_resp_eff_T_6 = cvt(_io_resp_eff_T_5) node _io_resp_eff_T_7 = and(_io_resp_eff_T_6, asSInt(UInt<33>(0h9e103000))) node _io_resp_eff_T_8 = asSInt(_io_resp_eff_T_7) node _io_resp_eff_T_9 = eq(_io_resp_eff_T_8, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_10 = xor(io.paddr, UInt<26>(0h2000000)) node _io_resp_eff_T_11 = cvt(_io_resp_eff_T_10) node _io_resp_eff_T_12 = and(_io_resp_eff_T_11, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_13 = asSInt(_io_resp_eff_T_12) node _io_resp_eff_T_14 = eq(_io_resp_eff_T_13, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_15 = xor(io.paddr, UInt<26>(0h2010000)) node _io_resp_eff_T_16 = cvt(_io_resp_eff_T_15) node _io_resp_eff_T_17 = and(_io_resp_eff_T_16, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_18 = asSInt(_io_resp_eff_T_17) node _io_resp_eff_T_19 = eq(_io_resp_eff_T_18, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_20 = xor(io.paddr, UInt<28>(0hc000000)) node _io_resp_eff_T_21 = cvt(_io_resp_eff_T_20) node _io_resp_eff_T_22 = and(_io_resp_eff_T_21, asSInt(UInt<33>(0h9c000000))) node _io_resp_eff_T_23 = asSInt(_io_resp_eff_T_22) node _io_resp_eff_T_24 = eq(_io_resp_eff_T_23, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_25 = xor(io.paddr, UInt<29>(0h10000000)) node _io_resp_eff_T_26 = cvt(_io_resp_eff_T_25) node _io_resp_eff_T_27 = and(_io_resp_eff_T_26, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_28 = asSInt(_io_resp_eff_T_27) node _io_resp_eff_T_29 = eq(_io_resp_eff_T_28, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_30 = or(_io_resp_eff_T_4, _io_resp_eff_T_9) node _io_resp_eff_T_31 = or(_io_resp_eff_T_30, _io_resp_eff_T_14) node _io_resp_eff_T_32 = or(_io_resp_eff_T_31, _io_resp_eff_T_19) node _io_resp_eff_T_33 = or(_io_resp_eff_T_32, _io_resp_eff_T_24) node _io_resp_eff_T_34 = or(_io_resp_eff_T_33, _io_resp_eff_T_29) node _io_resp_eff_T_35 = xor(io.paddr, UInt<14>(0h3000)) node _io_resp_eff_T_36 = cvt(_io_resp_eff_T_35) node _io_resp_eff_T_37 = and(_io_resp_eff_T_36, asSInt(UInt<33>(0h9e113000))) node _io_resp_eff_T_38 = asSInt(_io_resp_eff_T_37) node _io_resp_eff_T_39 = eq(_io_resp_eff_T_38, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_40 = xor(io.paddr, UInt<17>(0h10000)) node _io_resp_eff_T_41 = cvt(_io_resp_eff_T_40) node _io_resp_eff_T_42 = and(_io_resp_eff_T_41, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_43 = asSInt(_io_resp_eff_T_42) node _io_resp_eff_T_44 = eq(_io_resp_eff_T_43, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_45 = xor(io.paddr, UInt<28>(0h8000000)) node _io_resp_eff_T_46 = cvt(_io_resp_eff_T_45) node _io_resp_eff_T_47 = and(_io_resp_eff_T_46, asSInt(UInt<33>(0h9e110000))) node _io_resp_eff_T_48 = asSInt(_io_resp_eff_T_47) node _io_resp_eff_T_49 = eq(_io_resp_eff_T_48, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_50 = xor(io.paddr, UInt<32>(0h80000000)) node _io_resp_eff_T_51 = cvt(_io_resp_eff_T_50) node _io_resp_eff_T_52 = and(_io_resp_eff_T_51, asSInt(UInt<33>(0h90000000))) node _io_resp_eff_T_53 = asSInt(_io_resp_eff_T_52) node _io_resp_eff_T_54 = eq(_io_resp_eff_T_53, asSInt(UInt<1>(0h0))) node _io_resp_eff_T_55 = or(_io_resp_eff_T_39, _io_resp_eff_T_44) node _io_resp_eff_T_56 = or(_io_resp_eff_T_55, _io_resp_eff_T_49) node _io_resp_eff_T_57 = or(_io_resp_eff_T_56, _io_resp_eff_T_54) node _io_resp_eff_T_58 = mux(_io_resp_eff_T_34, UInt<1>(0h1), UInt<1>(0h0)) node _io_resp_eff_T_59 = mux(_io_resp_eff_T_57, UInt<1>(0h0), UInt<1>(0h0)) node _io_resp_eff_T_60 = or(_io_resp_eff_T_58, _io_resp_eff_T_59) wire _io_resp_eff_WIRE : UInt<1> connect _io_resp_eff_WIRE, _io_resp_eff_T_60 node _io_resp_eff_T_61 = and(legal_address, _io_resp_eff_WIRE) connect io.resp.eff, _io_resp_eff_T_61
module PMAChecker_14( // @[PMA.scala:18:7] input clock, // @[PMA.scala:18:7] input reset, // @[PMA.scala:18:7] input [39:0] io_paddr, // @[PMA.scala:19:14] output io_resp_cacheable, // @[PMA.scala:19:14] output io_resp_r, // @[PMA.scala:19:14] output io_resp_w, // @[PMA.scala:19:14] output io_resp_pp, // @[PMA.scala:19:14] output io_resp_al, // @[PMA.scala:19:14] output io_resp_aa, // @[PMA.scala:19:14] output io_resp_x, // @[PMA.scala:19:14] output io_resp_eff // @[PMA.scala:19:14] ); wire [39:0] io_paddr_0 = io_paddr; // @[PMA.scala:18:7] wire [40:0] _io_resp_r_T_2 = 41'h0; // @[Parameters.scala:137:46] wire [40:0] _io_resp_r_T_3 = 41'h0; // @[Parameters.scala:137:46] wire _io_resp_r_T_4 = 1'h1; // @[Parameters.scala:137:59] wire _io_resp_cacheable_T_28 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_w_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_pp_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_al_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_aa_T_47 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_x_T_65 = 1'h0; // @[Mux.scala:30:73] wire _io_resp_eff_T_59 = 1'h0; // @[Mux.scala:30:73] wire [39:0] _legal_address_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_cacheable_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_cacheable_T_31; // @[PMA.scala:39:19] wire [39:0] _io_resp_r_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_pp_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_al_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_aa_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_x_T = io_paddr_0; // @[PMA.scala:18:7] wire [39:0] _io_resp_eff_T = io_paddr_0; // @[PMA.scala:18:7] wire _io_resp_r_T_5; // @[PMA.scala:39:19] wire _io_resp_w_T_49; // @[PMA.scala:39:19] wire _io_resp_pp_T_49; // @[PMA.scala:39:19] wire _io_resp_al_T_49; // @[PMA.scala:39:19] wire _io_resp_aa_T_49; // @[PMA.scala:39:19] wire _io_resp_x_T_67; // @[PMA.scala:39:19] wire _io_resp_eff_T_61; // @[PMA.scala:39:19] wire io_resp_cacheable_0; // @[PMA.scala:18:7] wire io_resp_r_0; // @[PMA.scala:18:7] wire io_resp_w_0; // @[PMA.scala:18:7] wire io_resp_pp_0; // @[PMA.scala:18:7] wire io_resp_al_0; // @[PMA.scala:18:7] wire io_resp_aa_0; // @[PMA.scala:18:7] wire io_resp_x_0; // @[PMA.scala:18:7] wire io_resp_eff_0; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_1 = {1'h0, _legal_address_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_2 = _legal_address_T_1 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_3 = _legal_address_T_2; // @[Parameters.scala:137:46] wire _legal_address_T_4 = _legal_address_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_0 = _legal_address_T_4; // @[Parameters.scala:612:40] wire [39:0] _GEN = {io_paddr_0[39:13], io_paddr_0[12:0] ^ 13'h1000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_5; // @[Parameters.scala:137:31] assign _legal_address_T_5 = _GEN; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_29; // @[Parameters.scala:137:31] assign _io_resp_x_T_29 = _GEN; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_6 = {1'h0, _legal_address_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_7 = _legal_address_T_6 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_8 = _legal_address_T_7; // @[Parameters.scala:137:46] wire _legal_address_T_9 = _legal_address_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_1 = _legal_address_T_9; // @[Parameters.scala:612:40] wire [39:0] _GEN_0 = {io_paddr_0[39:14], io_paddr_0[13:0] ^ 14'h3000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_10; // @[Parameters.scala:137:31] assign _legal_address_T_10 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_5; // @[Parameters.scala:137:31] assign _io_resp_x_T_5 = _GEN_0; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_35; // @[Parameters.scala:137:31] assign _io_resp_eff_T_35 = _GEN_0; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_11 = {1'h0, _legal_address_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_12 = _legal_address_T_11 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_13 = _legal_address_T_12; // @[Parameters.scala:137:46] wire _legal_address_T_14 = _legal_address_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_2 = _legal_address_T_14; // @[Parameters.scala:612:40] wire [39:0] _GEN_1 = {io_paddr_0[39:17], io_paddr_0[16:0] ^ 17'h10000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_15; // @[Parameters.scala:137:31] assign _legal_address_T_15 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_5; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_5 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_41; // @[Parameters.scala:137:31] assign _io_resp_w_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_41; // @[Parameters.scala:137:31] assign _io_resp_pp_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_41; // @[Parameters.scala:137:31] assign _io_resp_al_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_41; // @[Parameters.scala:137:31] assign _io_resp_aa_T_41 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_10; // @[Parameters.scala:137:31] assign _io_resp_x_T_10 = _GEN_1; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_40; // @[Parameters.scala:137:31] assign _io_resp_eff_T_40 = _GEN_1; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_16 = {1'h0, _legal_address_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_17 = _legal_address_T_16 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_18 = _legal_address_T_17; // @[Parameters.scala:137:46] wire _legal_address_T_19 = _legal_address_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_3 = _legal_address_T_19; // @[Parameters.scala:612:40] wire [39:0] _GEN_2 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h100000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_20; // @[Parameters.scala:137:31] assign _legal_address_T_20 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_5; // @[Parameters.scala:137:31] assign _io_resp_w_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_5; // @[Parameters.scala:137:31] assign _io_resp_pp_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_5; // @[Parameters.scala:137:31] assign _io_resp_al_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_5; // @[Parameters.scala:137:31] assign _io_resp_aa_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_34; // @[Parameters.scala:137:31] assign _io_resp_x_T_34 = _GEN_2; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_5; // @[Parameters.scala:137:31] assign _io_resp_eff_T_5 = _GEN_2; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_21 = {1'h0, _legal_address_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_22 = _legal_address_T_21 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_23 = _legal_address_T_22; // @[Parameters.scala:137:46] wire _legal_address_T_24 = _legal_address_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_4 = _legal_address_T_24; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_25 = {io_paddr_0[39:21], io_paddr_0[20:0] ^ 21'h110000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_26 = {1'h0, _legal_address_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_27 = _legal_address_T_26 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_28 = _legal_address_T_27; // @[Parameters.scala:137:46] wire _legal_address_T_29 = _legal_address_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_5 = _legal_address_T_29; // @[Parameters.scala:612:40] wire [39:0] _GEN_3 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_30; // @[Parameters.scala:137:31] assign _legal_address_T_30 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_39; // @[Parameters.scala:137:31] assign _io_resp_x_T_39 = _GEN_3; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_10; // @[Parameters.scala:137:31] assign _io_resp_eff_T_10 = _GEN_3; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_31 = {1'h0, _legal_address_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_32 = _legal_address_T_31 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_33 = _legal_address_T_32; // @[Parameters.scala:137:46] wire _legal_address_T_34 = _legal_address_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_6 = _legal_address_T_34; // @[Parameters.scala:612:40] wire [39:0] _GEN_4 = {io_paddr_0[39:26], io_paddr_0[25:0] ^ 26'h2010000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_35; // @[Parameters.scala:137:31] assign _legal_address_T_35 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_10; // @[Parameters.scala:137:31] assign _io_resp_w_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_10; // @[Parameters.scala:137:31] assign _io_resp_pp_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_10; // @[Parameters.scala:137:31] assign _io_resp_al_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_10; // @[Parameters.scala:137:31] assign _io_resp_aa_T_10 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_44; // @[Parameters.scala:137:31] assign _io_resp_x_T_44 = _GEN_4; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_15; // @[Parameters.scala:137:31] assign _io_resp_eff_T_15 = _GEN_4; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_36 = {1'h0, _legal_address_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_37 = _legal_address_T_36 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_38 = _legal_address_T_37; // @[Parameters.scala:137:46] wire _legal_address_T_39 = _legal_address_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_7 = _legal_address_T_39; // @[Parameters.scala:612:40] wire [39:0] _GEN_5 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'h8000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_40; // @[Parameters.scala:137:31] assign _legal_address_T_40 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_17; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_17 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_15; // @[Parameters.scala:137:31] assign _io_resp_w_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_20; // @[Parameters.scala:137:31] assign _io_resp_w_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_15; // @[Parameters.scala:137:31] assign _io_resp_pp_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_20; // @[Parameters.scala:137:31] assign _io_resp_pp_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_15; // @[Parameters.scala:137:31] assign _io_resp_al_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_20; // @[Parameters.scala:137:31] assign _io_resp_al_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_15; // @[Parameters.scala:137:31] assign _io_resp_aa_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_20; // @[Parameters.scala:137:31] assign _io_resp_aa_T_20 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_15; // @[Parameters.scala:137:31] assign _io_resp_x_T_15 = _GEN_5; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_45; // @[Parameters.scala:137:31] assign _io_resp_eff_T_45 = _GEN_5; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_41 = {1'h0, _legal_address_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_42 = _legal_address_T_41 & 41'h1FFFFFF0000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_43 = _legal_address_T_42; // @[Parameters.scala:137:46] wire _legal_address_T_44 = _legal_address_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_8 = _legal_address_T_44; // @[Parameters.scala:612:40] wire [39:0] _GEN_6 = {io_paddr_0[39:28], io_paddr_0[27:0] ^ 28'hC000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_45; // @[Parameters.scala:137:31] assign _legal_address_T_45 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_10; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_10 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_49; // @[Parameters.scala:137:31] assign _io_resp_x_T_49 = _GEN_6; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_20; // @[Parameters.scala:137:31] assign _io_resp_eff_T_20 = _GEN_6; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_46 = {1'h0, _legal_address_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_47 = _legal_address_T_46 & 41'h1FFFC000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_48 = _legal_address_T_47; // @[Parameters.scala:137:46] wire _legal_address_T_49 = _legal_address_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_9 = _legal_address_T_49; // @[Parameters.scala:612:40] wire [39:0] _legal_address_T_50 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10020000}; // @[PMA.scala:18:7] wire [40:0] _legal_address_T_51 = {1'h0, _legal_address_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_52 = _legal_address_T_51 & 41'h1FFFFFFF000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_53 = _legal_address_T_52; // @[Parameters.scala:137:46] wire _legal_address_T_54 = _legal_address_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_10 = _legal_address_T_54; // @[Parameters.scala:612:40] wire [39:0] _GEN_7 = {io_paddr_0[39:32], io_paddr_0[31:0] ^ 32'h80000000}; // @[PMA.scala:18:7] wire [39:0] _legal_address_T_55; // @[Parameters.scala:137:31] assign _legal_address_T_55 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_cacheable_T_22; // @[Parameters.scala:137:31] assign _io_resp_cacheable_T_22 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_w_T_30; // @[Parameters.scala:137:31] assign _io_resp_w_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_30; // @[Parameters.scala:137:31] assign _io_resp_pp_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_30; // @[Parameters.scala:137:31] assign _io_resp_al_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_30; // @[Parameters.scala:137:31] assign _io_resp_aa_T_30 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_20; // @[Parameters.scala:137:31] assign _io_resp_x_T_20 = _GEN_7; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_50; // @[Parameters.scala:137:31] assign _io_resp_eff_T_50 = _GEN_7; // @[Parameters.scala:137:31] wire [40:0] _legal_address_T_56 = {1'h0, _legal_address_T_55}; // @[Parameters.scala:137:{31,41}] wire [40:0] _legal_address_T_57 = _legal_address_T_56 & 41'h1FFF0000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _legal_address_T_58 = _legal_address_T_57; // @[Parameters.scala:137:46] wire _legal_address_T_59 = _legal_address_T_58 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _legal_address_WIRE_11 = _legal_address_T_59; // @[Parameters.scala:612:40] wire _legal_address_T_60 = _legal_address_WIRE_0 | _legal_address_WIRE_1; // @[Parameters.scala:612:40] wire _legal_address_T_61 = _legal_address_T_60 | _legal_address_WIRE_2; // @[Parameters.scala:612:40] wire _legal_address_T_62 = _legal_address_T_61 | _legal_address_WIRE_3; // @[Parameters.scala:612:40] wire _legal_address_T_63 = _legal_address_T_62 | _legal_address_WIRE_4; // @[Parameters.scala:612:40] wire _legal_address_T_64 = _legal_address_T_63 | _legal_address_WIRE_5; // @[Parameters.scala:612:40] wire _legal_address_T_65 = _legal_address_T_64 | _legal_address_WIRE_6; // @[Parameters.scala:612:40] wire _legal_address_T_66 = _legal_address_T_65 | _legal_address_WIRE_7; // @[Parameters.scala:612:40] wire _legal_address_T_67 = _legal_address_T_66 | _legal_address_WIRE_8; // @[Parameters.scala:612:40] wire _legal_address_T_68 = _legal_address_T_67 | _legal_address_WIRE_9; // @[Parameters.scala:612:40] wire _legal_address_T_69 = _legal_address_T_68 | _legal_address_WIRE_10; // @[Parameters.scala:612:40] wire legal_address = _legal_address_T_69 | _legal_address_WIRE_11; // @[Parameters.scala:612:40] assign _io_resp_r_T_5 = legal_address; // @[PMA.scala:36:58, :39:19] wire [40:0] _io_resp_cacheable_T_1 = {1'h0, _io_resp_cacheable_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_2 = _io_resp_cacheable_T_1 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_3 = _io_resp_cacheable_T_2; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_4 = _io_resp_cacheable_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_6 = {1'h0, _io_resp_cacheable_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_7 = _io_resp_cacheable_T_6 & 41'h8C011000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_8 = _io_resp_cacheable_T_7; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_9 = _io_resp_cacheable_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_11 = {1'h0, _io_resp_cacheable_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_12 = _io_resp_cacheable_T_11 & 41'h8C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_13 = _io_resp_cacheable_T_12; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_14 = _io_resp_cacheable_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_15 = _io_resp_cacheable_T_4 | _io_resp_cacheable_T_9; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_16 = _io_resp_cacheable_T_15 | _io_resp_cacheable_T_14; // @[Parameters.scala:629:89] wire [40:0] _io_resp_cacheable_T_18 = {1'h0, _io_resp_cacheable_T_17}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_19 = _io_resp_cacheable_T_18 & 41'h8C010000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_20 = _io_resp_cacheable_T_19; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_21 = _io_resp_cacheable_T_20 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_cacheable_T_23 = {1'h0, _io_resp_cacheable_T_22}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_cacheable_T_24 = _io_resp_cacheable_T_23 & 41'h80000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_cacheable_T_25 = _io_resp_cacheable_T_24; // @[Parameters.scala:137:46] wire _io_resp_cacheable_T_26 = _io_resp_cacheable_T_25 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_cacheable_T_27 = _io_resp_cacheable_T_21 | _io_resp_cacheable_T_26; // @[Parameters.scala:629:89] wire _io_resp_cacheable_T_29 = _io_resp_cacheable_T_27; // @[Mux.scala:30:73] wire _io_resp_cacheable_T_30 = _io_resp_cacheable_T_29; // @[Mux.scala:30:73] wire _io_resp_cacheable_WIRE = _io_resp_cacheable_T_30; // @[Mux.scala:30:73] assign _io_resp_cacheable_T_31 = legal_address & _io_resp_cacheable_WIRE; // @[Mux.scala:30:73] assign io_resp_cacheable_0 = _io_resp_cacheable_T_31; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_r_T_1 = {1'h0, _io_resp_r_T}; // @[Parameters.scala:137:{31,41}] assign io_resp_r_0 = _io_resp_r_T_5; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_w_T_1 = {1'h0, _io_resp_w_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_2 = _io_resp_w_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_3 = _io_resp_w_T_2; // @[Parameters.scala:137:46] wire _io_resp_w_T_4 = _io_resp_w_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_6 = {1'h0, _io_resp_w_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_7 = _io_resp_w_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_8 = _io_resp_w_T_7; // @[Parameters.scala:137:46] wire _io_resp_w_T_9 = _io_resp_w_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_11 = {1'h0, _io_resp_w_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_12 = _io_resp_w_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_13 = _io_resp_w_T_12; // @[Parameters.scala:137:46] wire _io_resp_w_T_14 = _io_resp_w_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_16 = {1'h0, _io_resp_w_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_17 = _io_resp_w_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_18 = _io_resp_w_T_17; // @[Parameters.scala:137:46] wire _io_resp_w_T_19 = _io_resp_w_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_21 = {1'h0, _io_resp_w_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_22 = _io_resp_w_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_23 = _io_resp_w_T_22; // @[Parameters.scala:137:46] wire _io_resp_w_T_24 = _io_resp_w_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [39:0] _GEN_8 = {io_paddr_0[39:29], io_paddr_0[28:0] ^ 29'h10000000}; // @[PMA.scala:18:7] wire [39:0] _io_resp_w_T_25; // @[Parameters.scala:137:31] assign _io_resp_w_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_pp_T_25; // @[Parameters.scala:137:31] assign _io_resp_pp_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_al_T_25; // @[Parameters.scala:137:31] assign _io_resp_al_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_aa_T_25; // @[Parameters.scala:137:31] assign _io_resp_aa_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_x_T_54; // @[Parameters.scala:137:31] assign _io_resp_x_T_54 = _GEN_8; // @[Parameters.scala:137:31] wire [39:0] _io_resp_eff_T_25; // @[Parameters.scala:137:31] assign _io_resp_eff_T_25 = _GEN_8; // @[Parameters.scala:137:31] wire [40:0] _io_resp_w_T_26 = {1'h0, _io_resp_w_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_27 = _io_resp_w_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_28 = _io_resp_w_T_27; // @[Parameters.scala:137:46] wire _io_resp_w_T_29 = _io_resp_w_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_w_T_31 = {1'h0, _io_resp_w_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_32 = _io_resp_w_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_33 = _io_resp_w_T_32; // @[Parameters.scala:137:46] wire _io_resp_w_T_34 = _io_resp_w_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_35 = _io_resp_w_T_4 | _io_resp_w_T_9; // @[Parameters.scala:629:89] wire _io_resp_w_T_36 = _io_resp_w_T_35 | _io_resp_w_T_14; // @[Parameters.scala:629:89] wire _io_resp_w_T_37 = _io_resp_w_T_36 | _io_resp_w_T_19; // @[Parameters.scala:629:89] wire _io_resp_w_T_38 = _io_resp_w_T_37 | _io_resp_w_T_24; // @[Parameters.scala:629:89] wire _io_resp_w_T_39 = _io_resp_w_T_38 | _io_resp_w_T_29; // @[Parameters.scala:629:89] wire _io_resp_w_T_40 = _io_resp_w_T_39 | _io_resp_w_T_34; // @[Parameters.scala:629:89] wire _io_resp_w_T_46 = _io_resp_w_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_w_T_42 = {1'h0, _io_resp_w_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_w_T_43 = _io_resp_w_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_w_T_44 = _io_resp_w_T_43; // @[Parameters.scala:137:46] wire _io_resp_w_T_45 = _io_resp_w_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_w_T_48 = _io_resp_w_T_46; // @[Mux.scala:30:73] wire _io_resp_w_WIRE = _io_resp_w_T_48; // @[Mux.scala:30:73] assign _io_resp_w_T_49 = legal_address & _io_resp_w_WIRE; // @[Mux.scala:30:73] assign io_resp_w_0 = _io_resp_w_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_pp_T_1 = {1'h0, _io_resp_pp_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_2 = _io_resp_pp_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_3 = _io_resp_pp_T_2; // @[Parameters.scala:137:46] wire _io_resp_pp_T_4 = _io_resp_pp_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_6 = {1'h0, _io_resp_pp_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_7 = _io_resp_pp_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_8 = _io_resp_pp_T_7; // @[Parameters.scala:137:46] wire _io_resp_pp_T_9 = _io_resp_pp_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_11 = {1'h0, _io_resp_pp_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_12 = _io_resp_pp_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_13 = _io_resp_pp_T_12; // @[Parameters.scala:137:46] wire _io_resp_pp_T_14 = _io_resp_pp_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_16 = {1'h0, _io_resp_pp_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_17 = _io_resp_pp_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_18 = _io_resp_pp_T_17; // @[Parameters.scala:137:46] wire _io_resp_pp_T_19 = _io_resp_pp_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_21 = {1'h0, _io_resp_pp_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_22 = _io_resp_pp_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_23 = _io_resp_pp_T_22; // @[Parameters.scala:137:46] wire _io_resp_pp_T_24 = _io_resp_pp_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_26 = {1'h0, _io_resp_pp_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_27 = _io_resp_pp_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_28 = _io_resp_pp_T_27; // @[Parameters.scala:137:46] wire _io_resp_pp_T_29 = _io_resp_pp_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_pp_T_31 = {1'h0, _io_resp_pp_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_32 = _io_resp_pp_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_33 = _io_resp_pp_T_32; // @[Parameters.scala:137:46] wire _io_resp_pp_T_34 = _io_resp_pp_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_35 = _io_resp_pp_T_4 | _io_resp_pp_T_9; // @[Parameters.scala:629:89] wire _io_resp_pp_T_36 = _io_resp_pp_T_35 | _io_resp_pp_T_14; // @[Parameters.scala:629:89] wire _io_resp_pp_T_37 = _io_resp_pp_T_36 | _io_resp_pp_T_19; // @[Parameters.scala:629:89] wire _io_resp_pp_T_38 = _io_resp_pp_T_37 | _io_resp_pp_T_24; // @[Parameters.scala:629:89] wire _io_resp_pp_T_39 = _io_resp_pp_T_38 | _io_resp_pp_T_29; // @[Parameters.scala:629:89] wire _io_resp_pp_T_40 = _io_resp_pp_T_39 | _io_resp_pp_T_34; // @[Parameters.scala:629:89] wire _io_resp_pp_T_46 = _io_resp_pp_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_pp_T_42 = {1'h0, _io_resp_pp_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_pp_T_43 = _io_resp_pp_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_pp_T_44 = _io_resp_pp_T_43; // @[Parameters.scala:137:46] wire _io_resp_pp_T_45 = _io_resp_pp_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_pp_T_48 = _io_resp_pp_T_46; // @[Mux.scala:30:73] wire _io_resp_pp_WIRE = _io_resp_pp_T_48; // @[Mux.scala:30:73] assign _io_resp_pp_T_49 = legal_address & _io_resp_pp_WIRE; // @[Mux.scala:30:73] assign io_resp_pp_0 = _io_resp_pp_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_al_T_1 = {1'h0, _io_resp_al_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_2 = _io_resp_al_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_3 = _io_resp_al_T_2; // @[Parameters.scala:137:46] wire _io_resp_al_T_4 = _io_resp_al_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_6 = {1'h0, _io_resp_al_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_7 = _io_resp_al_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_8 = _io_resp_al_T_7; // @[Parameters.scala:137:46] wire _io_resp_al_T_9 = _io_resp_al_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_11 = {1'h0, _io_resp_al_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_12 = _io_resp_al_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_13 = _io_resp_al_T_12; // @[Parameters.scala:137:46] wire _io_resp_al_T_14 = _io_resp_al_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_16 = {1'h0, _io_resp_al_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_17 = _io_resp_al_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_18 = _io_resp_al_T_17; // @[Parameters.scala:137:46] wire _io_resp_al_T_19 = _io_resp_al_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_21 = {1'h0, _io_resp_al_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_22 = _io_resp_al_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_23 = _io_resp_al_T_22; // @[Parameters.scala:137:46] wire _io_resp_al_T_24 = _io_resp_al_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_26 = {1'h0, _io_resp_al_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_27 = _io_resp_al_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_28 = _io_resp_al_T_27; // @[Parameters.scala:137:46] wire _io_resp_al_T_29 = _io_resp_al_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_al_T_31 = {1'h0, _io_resp_al_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_32 = _io_resp_al_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_33 = _io_resp_al_T_32; // @[Parameters.scala:137:46] wire _io_resp_al_T_34 = _io_resp_al_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_35 = _io_resp_al_T_4 | _io_resp_al_T_9; // @[Parameters.scala:629:89] wire _io_resp_al_T_36 = _io_resp_al_T_35 | _io_resp_al_T_14; // @[Parameters.scala:629:89] wire _io_resp_al_T_37 = _io_resp_al_T_36 | _io_resp_al_T_19; // @[Parameters.scala:629:89] wire _io_resp_al_T_38 = _io_resp_al_T_37 | _io_resp_al_T_24; // @[Parameters.scala:629:89] wire _io_resp_al_T_39 = _io_resp_al_T_38 | _io_resp_al_T_29; // @[Parameters.scala:629:89] wire _io_resp_al_T_40 = _io_resp_al_T_39 | _io_resp_al_T_34; // @[Parameters.scala:629:89] wire _io_resp_al_T_46 = _io_resp_al_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_al_T_42 = {1'h0, _io_resp_al_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_al_T_43 = _io_resp_al_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_al_T_44 = _io_resp_al_T_43; // @[Parameters.scala:137:46] wire _io_resp_al_T_45 = _io_resp_al_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_al_T_48 = _io_resp_al_T_46; // @[Mux.scala:30:73] wire _io_resp_al_WIRE = _io_resp_al_T_48; // @[Mux.scala:30:73] assign _io_resp_al_T_49 = legal_address & _io_resp_al_WIRE; // @[Mux.scala:30:73] assign io_resp_al_0 = _io_resp_al_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_aa_T_1 = {1'h0, _io_resp_aa_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_2 = _io_resp_aa_T_1 & 41'h98110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_3 = _io_resp_aa_T_2; // @[Parameters.scala:137:46] wire _io_resp_aa_T_4 = _io_resp_aa_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_6 = {1'h0, _io_resp_aa_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_7 = _io_resp_aa_T_6 & 41'h9A101000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_8 = _io_resp_aa_T_7; // @[Parameters.scala:137:46] wire _io_resp_aa_T_9 = _io_resp_aa_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_11 = {1'h0, _io_resp_aa_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_12 = _io_resp_aa_T_11 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_13 = _io_resp_aa_T_12; // @[Parameters.scala:137:46] wire _io_resp_aa_T_14 = _io_resp_aa_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_16 = {1'h0, _io_resp_aa_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_17 = _io_resp_aa_T_16 & 41'h98000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_18 = _io_resp_aa_T_17; // @[Parameters.scala:137:46] wire _io_resp_aa_T_19 = _io_resp_aa_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_21 = {1'h0, _io_resp_aa_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_22 = _io_resp_aa_T_21 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_23 = _io_resp_aa_T_22; // @[Parameters.scala:137:46] wire _io_resp_aa_T_24 = _io_resp_aa_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_26 = {1'h0, _io_resp_aa_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_27 = _io_resp_aa_T_26 & 41'h9A111000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_28 = _io_resp_aa_T_27; // @[Parameters.scala:137:46] wire _io_resp_aa_T_29 = _io_resp_aa_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_aa_T_31 = {1'h0, _io_resp_aa_T_30}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_32 = _io_resp_aa_T_31 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_33 = _io_resp_aa_T_32; // @[Parameters.scala:137:46] wire _io_resp_aa_T_34 = _io_resp_aa_T_33 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_35 = _io_resp_aa_T_4 | _io_resp_aa_T_9; // @[Parameters.scala:629:89] wire _io_resp_aa_T_36 = _io_resp_aa_T_35 | _io_resp_aa_T_14; // @[Parameters.scala:629:89] wire _io_resp_aa_T_37 = _io_resp_aa_T_36 | _io_resp_aa_T_19; // @[Parameters.scala:629:89] wire _io_resp_aa_T_38 = _io_resp_aa_T_37 | _io_resp_aa_T_24; // @[Parameters.scala:629:89] wire _io_resp_aa_T_39 = _io_resp_aa_T_38 | _io_resp_aa_T_29; // @[Parameters.scala:629:89] wire _io_resp_aa_T_40 = _io_resp_aa_T_39 | _io_resp_aa_T_34; // @[Parameters.scala:629:89] wire _io_resp_aa_T_46 = _io_resp_aa_T_40; // @[Mux.scala:30:73] wire [40:0] _io_resp_aa_T_42 = {1'h0, _io_resp_aa_T_41}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_aa_T_43 = _io_resp_aa_T_42 & 41'h9A110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_aa_T_44 = _io_resp_aa_T_43; // @[Parameters.scala:137:46] wire _io_resp_aa_T_45 = _io_resp_aa_T_44 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_aa_T_48 = _io_resp_aa_T_46; // @[Mux.scala:30:73] wire _io_resp_aa_WIRE = _io_resp_aa_T_48; // @[Mux.scala:30:73] assign _io_resp_aa_T_49 = legal_address & _io_resp_aa_WIRE; // @[Mux.scala:30:73] assign io_resp_aa_0 = _io_resp_aa_T_49; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_x_T_1 = {1'h0, _io_resp_x_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_2 = _io_resp_x_T_1 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_3 = _io_resp_x_T_2; // @[Parameters.scala:137:46] wire _io_resp_x_T_4 = _io_resp_x_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_6 = {1'h0, _io_resp_x_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_7 = _io_resp_x_T_6 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_8 = _io_resp_x_T_7; // @[Parameters.scala:137:46] wire _io_resp_x_T_9 = _io_resp_x_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_11 = {1'h0, _io_resp_x_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_12 = _io_resp_x_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_13 = _io_resp_x_T_12; // @[Parameters.scala:137:46] wire _io_resp_x_T_14 = _io_resp_x_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_16 = {1'h0, _io_resp_x_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_17 = _io_resp_x_T_16 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_18 = _io_resp_x_T_17; // @[Parameters.scala:137:46] wire _io_resp_x_T_19 = _io_resp_x_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_21 = {1'h0, _io_resp_x_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_22 = _io_resp_x_T_21 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_23 = _io_resp_x_T_22; // @[Parameters.scala:137:46] wire _io_resp_x_T_24 = _io_resp_x_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_25 = _io_resp_x_T_4 | _io_resp_x_T_9; // @[Parameters.scala:629:89] wire _io_resp_x_T_26 = _io_resp_x_T_25 | _io_resp_x_T_14; // @[Parameters.scala:629:89] wire _io_resp_x_T_27 = _io_resp_x_T_26 | _io_resp_x_T_19; // @[Parameters.scala:629:89] wire _io_resp_x_T_28 = _io_resp_x_T_27 | _io_resp_x_T_24; // @[Parameters.scala:629:89] wire _io_resp_x_T_64 = _io_resp_x_T_28; // @[Mux.scala:30:73] wire [40:0] _io_resp_x_T_30 = {1'h0, _io_resp_x_T_29}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_31 = _io_resp_x_T_30 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_32 = _io_resp_x_T_31; // @[Parameters.scala:137:46] wire _io_resp_x_T_33 = _io_resp_x_T_32 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_35 = {1'h0, _io_resp_x_T_34}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_36 = _io_resp_x_T_35 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_37 = _io_resp_x_T_36; // @[Parameters.scala:137:46] wire _io_resp_x_T_38 = _io_resp_x_T_37 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_40 = {1'h0, _io_resp_x_T_39}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_41 = _io_resp_x_T_40 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_42 = _io_resp_x_T_41; // @[Parameters.scala:137:46] wire _io_resp_x_T_43 = _io_resp_x_T_42 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_45 = {1'h0, _io_resp_x_T_44}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_46 = _io_resp_x_T_45 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_47 = _io_resp_x_T_46; // @[Parameters.scala:137:46] wire _io_resp_x_T_48 = _io_resp_x_T_47 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_50 = {1'h0, _io_resp_x_T_49}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_51 = _io_resp_x_T_50 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_52 = _io_resp_x_T_51; // @[Parameters.scala:137:46] wire _io_resp_x_T_53 = _io_resp_x_T_52 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_x_T_55 = {1'h0, _io_resp_x_T_54}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_x_T_56 = _io_resp_x_T_55 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_x_T_57 = _io_resp_x_T_56; // @[Parameters.scala:137:46] wire _io_resp_x_T_58 = _io_resp_x_T_57 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_x_T_59 = _io_resp_x_T_33 | _io_resp_x_T_38; // @[Parameters.scala:629:89] wire _io_resp_x_T_60 = _io_resp_x_T_59 | _io_resp_x_T_43; // @[Parameters.scala:629:89] wire _io_resp_x_T_61 = _io_resp_x_T_60 | _io_resp_x_T_48; // @[Parameters.scala:629:89] wire _io_resp_x_T_62 = _io_resp_x_T_61 | _io_resp_x_T_53; // @[Parameters.scala:629:89] wire _io_resp_x_T_63 = _io_resp_x_T_62 | _io_resp_x_T_58; // @[Parameters.scala:629:89] wire _io_resp_x_T_66 = _io_resp_x_T_64; // @[Mux.scala:30:73] wire _io_resp_x_WIRE = _io_resp_x_T_66; // @[Mux.scala:30:73] assign _io_resp_x_T_67 = legal_address & _io_resp_x_WIRE; // @[Mux.scala:30:73] assign io_resp_x_0 = _io_resp_x_T_67; // @[PMA.scala:18:7, :39:19] wire [40:0] _io_resp_eff_T_1 = {1'h0, _io_resp_eff_T}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_2 = _io_resp_eff_T_1 & 41'h9E112000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_3 = _io_resp_eff_T_2; // @[Parameters.scala:137:46] wire _io_resp_eff_T_4 = _io_resp_eff_T_3 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_6 = {1'h0, _io_resp_eff_T_5}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_7 = _io_resp_eff_T_6 & 41'h9E103000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_8 = _io_resp_eff_T_7; // @[Parameters.scala:137:46] wire _io_resp_eff_T_9 = _io_resp_eff_T_8 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_11 = {1'h0, _io_resp_eff_T_10}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_12 = _io_resp_eff_T_11 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_13 = _io_resp_eff_T_12; // @[Parameters.scala:137:46] wire _io_resp_eff_T_14 = _io_resp_eff_T_13 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_16 = {1'h0, _io_resp_eff_T_15}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_17 = _io_resp_eff_T_16 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_18 = _io_resp_eff_T_17; // @[Parameters.scala:137:46] wire _io_resp_eff_T_19 = _io_resp_eff_T_18 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_21 = {1'h0, _io_resp_eff_T_20}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_22 = _io_resp_eff_T_21 & 41'h9C000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_23 = _io_resp_eff_T_22; // @[Parameters.scala:137:46] wire _io_resp_eff_T_24 = _io_resp_eff_T_23 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_26 = {1'h0, _io_resp_eff_T_25}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_27 = _io_resp_eff_T_26 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_28 = _io_resp_eff_T_27; // @[Parameters.scala:137:46] wire _io_resp_eff_T_29 = _io_resp_eff_T_28 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_30 = _io_resp_eff_T_4 | _io_resp_eff_T_9; // @[Parameters.scala:629:89] wire _io_resp_eff_T_31 = _io_resp_eff_T_30 | _io_resp_eff_T_14; // @[Parameters.scala:629:89] wire _io_resp_eff_T_32 = _io_resp_eff_T_31 | _io_resp_eff_T_19; // @[Parameters.scala:629:89] wire _io_resp_eff_T_33 = _io_resp_eff_T_32 | _io_resp_eff_T_24; // @[Parameters.scala:629:89] wire _io_resp_eff_T_34 = _io_resp_eff_T_33 | _io_resp_eff_T_29; // @[Parameters.scala:629:89] wire _io_resp_eff_T_58 = _io_resp_eff_T_34; // @[Mux.scala:30:73] wire [40:0] _io_resp_eff_T_36 = {1'h0, _io_resp_eff_T_35}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_37 = _io_resp_eff_T_36 & 41'h9E113000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_38 = _io_resp_eff_T_37; // @[Parameters.scala:137:46] wire _io_resp_eff_T_39 = _io_resp_eff_T_38 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_41 = {1'h0, _io_resp_eff_T_40}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_42 = _io_resp_eff_T_41 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_43 = _io_resp_eff_T_42; // @[Parameters.scala:137:46] wire _io_resp_eff_T_44 = _io_resp_eff_T_43 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_46 = {1'h0, _io_resp_eff_T_45}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_47 = _io_resp_eff_T_46 & 41'h9E110000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_48 = _io_resp_eff_T_47; // @[Parameters.scala:137:46] wire _io_resp_eff_T_49 = _io_resp_eff_T_48 == 41'h0; // @[Parameters.scala:137:{46,59}] wire [40:0] _io_resp_eff_T_51 = {1'h0, _io_resp_eff_T_50}; // @[Parameters.scala:137:{31,41}] wire [40:0] _io_resp_eff_T_52 = _io_resp_eff_T_51 & 41'h90000000; // @[Parameters.scala:137:{41,46}] wire [40:0] _io_resp_eff_T_53 = _io_resp_eff_T_52; // @[Parameters.scala:137:46] wire _io_resp_eff_T_54 = _io_resp_eff_T_53 == 41'h0; // @[Parameters.scala:137:{46,59}] wire _io_resp_eff_T_55 = _io_resp_eff_T_39 | _io_resp_eff_T_44; // @[Parameters.scala:629:89] wire _io_resp_eff_T_56 = _io_resp_eff_T_55 | _io_resp_eff_T_49; // @[Parameters.scala:629:89] wire _io_resp_eff_T_57 = _io_resp_eff_T_56 | _io_resp_eff_T_54; // @[Parameters.scala:629:89] wire _io_resp_eff_T_60 = _io_resp_eff_T_58; // @[Mux.scala:30:73] wire _io_resp_eff_WIRE = _io_resp_eff_T_60; // @[Mux.scala:30:73] assign _io_resp_eff_T_61 = legal_address & _io_resp_eff_WIRE; // @[Mux.scala:30:73] assign io_resp_eff_0 = _io_resp_eff_T_61; // @[PMA.scala:18:7, :39:19] assign io_resp_cacheable = io_resp_cacheable_0; // @[PMA.scala:18:7] assign io_resp_r = io_resp_r_0; // @[PMA.scala:18:7] assign io_resp_w = io_resp_w_0; // @[PMA.scala:18:7] assign io_resp_pp = io_resp_pp_0; // @[PMA.scala:18:7] assign io_resp_al = io_resp_al_0; // @[PMA.scala:18:7] assign io_resp_aa = io_resp_aa_0; // @[PMA.scala:18:7] assign io_resp_x = io_resp_x_0; // @[PMA.scala:18:7] assign io_resp_eff = io_resp_eff_0; // @[PMA.scala:18:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_11 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_23 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_11( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_23 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_70 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h11)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_T_25 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_T_26 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _source_ok_T_27 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _source_ok_T_28 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _source_ok_T_29 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_25 connect _source_ok_WIRE[6], _source_ok_T_26 connect _source_ok_WIRE[7], _source_ok_T_27 connect _source_ok_WIRE[8], _source_ok_T_28 connect _source_ok_WIRE[9], _source_ok_T_29 node _source_ok_T_30 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_31 = or(_source_ok_T_30, _source_ok_WIRE[2]) node _source_ok_T_32 = or(_source_ok_T_31, _source_ok_WIRE[3]) node _source_ok_T_33 = or(_source_ok_T_32, _source_ok_WIRE[4]) node _source_ok_T_34 = or(_source_ok_T_33, _source_ok_WIRE[5]) node _source_ok_T_35 = or(_source_ok_T_34, _source_ok_WIRE[6]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[7]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_37, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _T_64 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_65 = eq(_T_64, UInt<1>(0h0)) node _T_66 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_67 = cvt(_T_66) node _T_68 = and(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = asSInt(_T_68) node _T_70 = eq(_T_69, asSInt(UInt<1>(0h0))) node _T_71 = or(_T_65, _T_70) node _T_72 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<1>(0h0))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = or(_T_73, _T_78) node _T_80 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_81 = eq(_T_80, UInt<1>(0h0)) node _T_82 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_83 = cvt(_T_82) node _T_84 = and(_T_83, asSInt(UInt<1>(0h0))) node _T_85 = asSInt(_T_84) node _T_86 = eq(_T_85, asSInt(UInt<1>(0h0))) node _T_87 = or(_T_81, _T_86) node _T_88 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_89 = eq(_T_88, UInt<1>(0h0)) node _T_90 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<1>(0h0))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_97 = eq(_T_96, UInt<1>(0h0)) node _T_98 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_99 = cvt(_T_98) node _T_100 = and(_T_99, asSInt(UInt<1>(0h0))) node _T_101 = asSInt(_T_100) node _T_102 = eq(_T_101, asSInt(UInt<1>(0h0))) node _T_103 = or(_T_97, _T_102) node _T_104 = and(_T_11, _T_24) node _T_105 = and(_T_104, _T_37) node _T_106 = and(_T_105, _T_50) node _T_107 = and(_T_106, _T_63) node _T_108 = and(_T_107, _T_71) node _T_109 = and(_T_108, _T_79) node _T_110 = and(_T_109, _T_87) node _T_111 = and(_T_110, _T_95) node _T_112 = and(_T_111, _T_103) node _T_113 = asUInt(reset) node _T_114 = eq(_T_113, UInt<1>(0h0)) when _T_114 : node _T_115 = eq(_T_112, UInt<1>(0h0)) when _T_115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_112, UInt<1>(0h1), "") : assert_1 node _T_116 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_116 : node _T_117 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_118 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_119 = and(_T_117, _T_118) node _T_120 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 1, 0) node _T_121 = shr(io.in.a.bits.source, 2) node _T_122 = eq(_T_121, UInt<1>(0h0)) node _T_123 = leq(UInt<1>(0h0), uncommonBits_4) node _T_124 = and(_T_122, _T_123) node _T_125 = leq(uncommonBits_4, UInt<2>(0h3)) node _T_126 = and(_T_124, _T_125) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_127 = shr(io.in.a.bits.source, 2) node _T_128 = eq(_T_127, UInt<1>(0h1)) node _T_129 = leq(UInt<1>(0h0), uncommonBits_5) node _T_130 = and(_T_128, _T_129) node _T_131 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_132 = and(_T_130, _T_131) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_133 = shr(io.in.a.bits.source, 2) node _T_134 = eq(_T_133, UInt<2>(0h2)) node _T_135 = leq(UInt<1>(0h0), uncommonBits_6) node _T_136 = and(_T_134, _T_135) node _T_137 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_138 = and(_T_136, _T_137) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_139 = shr(io.in.a.bits.source, 2) node _T_140 = eq(_T_139, UInt<2>(0h3)) node _T_141 = leq(UInt<1>(0h0), uncommonBits_7) node _T_142 = and(_T_140, _T_141) node _T_143 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_144 = and(_T_142, _T_143) node _T_145 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_146 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_147 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_148 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_149 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_150 = or(_T_120, _T_126) node _T_151 = or(_T_150, _T_132) node _T_152 = or(_T_151, _T_138) node _T_153 = or(_T_152, _T_144) node _T_154 = or(_T_153, _T_145) node _T_155 = or(_T_154, _T_146) node _T_156 = or(_T_155, _T_147) node _T_157 = or(_T_156, _T_148) node _T_158 = or(_T_157, _T_149) node _T_159 = and(_T_119, _T_158) node _T_160 = or(UInt<1>(0h0), _T_159) node _T_161 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_162 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<13>(0h1000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = and(_T_161, _T_166) node _T_168 = or(UInt<1>(0h0), _T_167) node _T_169 = and(_T_160, _T_168) node _T_170 = asUInt(reset) node _T_171 = eq(_T_170, UInt<1>(0h0)) when _T_171 : node _T_172 = eq(_T_169, UInt<1>(0h0)) when _T_172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_169, UInt<1>(0h1), "") : assert_2 node _T_173 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_174 = shr(io.in.a.bits.source, 2) node _T_175 = eq(_T_174, UInt<1>(0h0)) node _T_176 = leq(UInt<1>(0h0), uncommonBits_8) node _T_177 = and(_T_175, _T_176) node _T_178 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_179 = and(_T_177, _T_178) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 1, 0) node _T_180 = shr(io.in.a.bits.source, 2) node _T_181 = eq(_T_180, UInt<1>(0h1)) node _T_182 = leq(UInt<1>(0h0), uncommonBits_9) node _T_183 = and(_T_181, _T_182) node _T_184 = leq(uncommonBits_9, UInt<2>(0h3)) node _T_185 = and(_T_183, _T_184) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_186 = shr(io.in.a.bits.source, 2) node _T_187 = eq(_T_186, UInt<2>(0h2)) node _T_188 = leq(UInt<1>(0h0), uncommonBits_10) node _T_189 = and(_T_187, _T_188) node _T_190 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_191 = and(_T_189, _T_190) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_192 = shr(io.in.a.bits.source, 2) node _T_193 = eq(_T_192, UInt<2>(0h3)) node _T_194 = leq(UInt<1>(0h0), uncommonBits_11) node _T_195 = and(_T_193, _T_194) node _T_196 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_197 = and(_T_195, _T_196) node _T_198 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_199 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_200 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_201 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_202 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_173 connect _WIRE[1], _T_179 connect _WIRE[2], _T_185 connect _WIRE[3], _T_191 connect _WIRE[4], _T_197 connect _WIRE[5], _T_198 connect _WIRE[6], _T_199 connect _WIRE[7], _T_200 connect _WIRE[8], _T_201 connect _WIRE[9], _T_202 node _T_203 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_204 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_205 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_206 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_207 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_208 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_209 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_210 = mux(_WIRE[6], _T_203, UInt<1>(0h0)) node _T_211 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_212 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_213 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_214 = or(_T_204, _T_205) node _T_215 = or(_T_214, _T_206) node _T_216 = or(_T_215, _T_207) node _T_217 = or(_T_216, _T_208) node _T_218 = or(_T_217, _T_209) node _T_219 = or(_T_218, _T_210) node _T_220 = or(_T_219, _T_211) node _T_221 = or(_T_220, _T_212) node _T_222 = or(_T_221, _T_213) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_222 node _T_223 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_224 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_225 = and(_T_223, _T_224) node _T_226 = or(UInt<1>(0h0), _T_225) node _T_227 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_228 = cvt(_T_227) node _T_229 = and(_T_228, asSInt(UInt<13>(0h1000))) node _T_230 = asSInt(_T_229) node _T_231 = eq(_T_230, asSInt(UInt<1>(0h0))) node _T_232 = and(_T_226, _T_231) node _T_233 = or(UInt<1>(0h0), _T_232) node _T_234 = and(_WIRE_1, _T_233) node _T_235 = asUInt(reset) node _T_236 = eq(_T_235, UInt<1>(0h0)) when _T_236 : node _T_237 = eq(_T_234, UInt<1>(0h0)) when _T_237 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_234, UInt<1>(0h1), "") : assert_3 node _T_238 = asUInt(reset) node _T_239 = eq(_T_238, UInt<1>(0h0)) when _T_239 : node _T_240 = eq(source_ok, UInt<1>(0h0)) when _T_240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_241 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_242 = asUInt(reset) node _T_243 = eq(_T_242, UInt<1>(0h0)) when _T_243 : node _T_244 = eq(_T_241, UInt<1>(0h0)) when _T_244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_241, UInt<1>(0h1), "") : assert_5 node _T_245 = asUInt(reset) node _T_246 = eq(_T_245, UInt<1>(0h0)) when _T_246 : node _T_247 = eq(is_aligned, UInt<1>(0h0)) when _T_247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_248 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_249 = asUInt(reset) node _T_250 = eq(_T_249, UInt<1>(0h0)) when _T_250 : node _T_251 = eq(_T_248, UInt<1>(0h0)) when _T_251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_248, UInt<1>(0h1), "") : assert_7 node _T_252 = not(io.in.a.bits.mask) node _T_253 = eq(_T_252, UInt<1>(0h0)) node _T_254 = asUInt(reset) node _T_255 = eq(_T_254, UInt<1>(0h0)) when _T_255 : node _T_256 = eq(_T_253, UInt<1>(0h0)) when _T_256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_253, UInt<1>(0h1), "") : assert_8 node _T_257 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_258 = asUInt(reset) node _T_259 = eq(_T_258, UInt<1>(0h0)) when _T_259 : node _T_260 = eq(_T_257, UInt<1>(0h0)) when _T_260 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_257, UInt<1>(0h1), "") : assert_9 node _T_261 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_261 : node _T_262 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_263 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_264 = and(_T_262, _T_263) node _T_265 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_266 = shr(io.in.a.bits.source, 2) node _T_267 = eq(_T_266, UInt<1>(0h0)) node _T_268 = leq(UInt<1>(0h0), uncommonBits_12) node _T_269 = and(_T_267, _T_268) node _T_270 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_271 = and(_T_269, _T_270) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_272 = shr(io.in.a.bits.source, 2) node _T_273 = eq(_T_272, UInt<1>(0h1)) node _T_274 = leq(UInt<1>(0h0), uncommonBits_13) node _T_275 = and(_T_273, _T_274) node _T_276 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_277 = and(_T_275, _T_276) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 1, 0) node _T_278 = shr(io.in.a.bits.source, 2) node _T_279 = eq(_T_278, UInt<2>(0h2)) node _T_280 = leq(UInt<1>(0h0), uncommonBits_14) node _T_281 = and(_T_279, _T_280) node _T_282 = leq(uncommonBits_14, UInt<2>(0h3)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_284 = shr(io.in.a.bits.source, 2) node _T_285 = eq(_T_284, UInt<2>(0h3)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_15) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_289 = and(_T_287, _T_288) node _T_290 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_291 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_292 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_293 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_294 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_295 = or(_T_265, _T_271) node _T_296 = or(_T_295, _T_277) node _T_297 = or(_T_296, _T_283) node _T_298 = or(_T_297, _T_289) node _T_299 = or(_T_298, _T_290) node _T_300 = or(_T_299, _T_291) node _T_301 = or(_T_300, _T_292) node _T_302 = or(_T_301, _T_293) node _T_303 = or(_T_302, _T_294) node _T_304 = and(_T_264, _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_307 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_308 = cvt(_T_307) node _T_309 = and(_T_308, asSInt(UInt<13>(0h1000))) node _T_310 = asSInt(_T_309) node _T_311 = eq(_T_310, asSInt(UInt<1>(0h0))) node _T_312 = and(_T_306, _T_311) node _T_313 = or(UInt<1>(0h0), _T_312) node _T_314 = and(_T_305, _T_313) node _T_315 = asUInt(reset) node _T_316 = eq(_T_315, UInt<1>(0h0)) when _T_316 : node _T_317 = eq(_T_314, UInt<1>(0h0)) when _T_317 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_314, UInt<1>(0h1), "") : assert_10 node _T_318 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_319 = shr(io.in.a.bits.source, 2) node _T_320 = eq(_T_319, UInt<1>(0h0)) node _T_321 = leq(UInt<1>(0h0), uncommonBits_16) node _T_322 = and(_T_320, _T_321) node _T_323 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_324 = and(_T_322, _T_323) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_325 = shr(io.in.a.bits.source, 2) node _T_326 = eq(_T_325, UInt<1>(0h1)) node _T_327 = leq(UInt<1>(0h0), uncommonBits_17) node _T_328 = and(_T_326, _T_327) node _T_329 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_330 = and(_T_328, _T_329) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_331 = shr(io.in.a.bits.source, 2) node _T_332 = eq(_T_331, UInt<2>(0h2)) node _T_333 = leq(UInt<1>(0h0), uncommonBits_18) node _T_334 = and(_T_332, _T_333) node _T_335 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_336 = and(_T_334, _T_335) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 1, 0) node _T_337 = shr(io.in.a.bits.source, 2) node _T_338 = eq(_T_337, UInt<2>(0h3)) node _T_339 = leq(UInt<1>(0h0), uncommonBits_19) node _T_340 = and(_T_338, _T_339) node _T_341 = leq(uncommonBits_19, UInt<2>(0h3)) node _T_342 = and(_T_340, _T_341) node _T_343 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_344 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_345 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_346 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_347 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_318 connect _WIRE_2[1], _T_324 connect _WIRE_2[2], _T_330 connect _WIRE_2[3], _T_336 connect _WIRE_2[4], _T_342 connect _WIRE_2[5], _T_343 connect _WIRE_2[6], _T_344 connect _WIRE_2[7], _T_345 connect _WIRE_2[8], _T_346 connect _WIRE_2[9], _T_347 node _T_348 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_349 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_350 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_351 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_352 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_353 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_354 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = mux(_WIRE_2[6], _T_348, UInt<1>(0h0)) node _T_356 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_357 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_358 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_359 = or(_T_349, _T_350) node _T_360 = or(_T_359, _T_351) node _T_361 = or(_T_360, _T_352) node _T_362 = or(_T_361, _T_353) node _T_363 = or(_T_362, _T_354) node _T_364 = or(_T_363, _T_355) node _T_365 = or(_T_364, _T_356) node _T_366 = or(_T_365, _T_357) node _T_367 = or(_T_366, _T_358) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_367 node _T_368 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_369 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_370 = and(_T_368, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_373 = cvt(_T_372) node _T_374 = and(_T_373, asSInt(UInt<13>(0h1000))) node _T_375 = asSInt(_T_374) node _T_376 = eq(_T_375, asSInt(UInt<1>(0h0))) node _T_377 = and(_T_371, _T_376) node _T_378 = or(UInt<1>(0h0), _T_377) node _T_379 = and(_WIRE_3, _T_378) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_379, UInt<1>(0h1), "") : assert_11 node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(source_ok, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_386 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_386, UInt<1>(0h1), "") : assert_13 node _T_390 = asUInt(reset) node _T_391 = eq(_T_390, UInt<1>(0h0)) when _T_391 : node _T_392 = eq(is_aligned, UInt<1>(0h0)) when _T_392 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_393 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_394 = asUInt(reset) node _T_395 = eq(_T_394, UInt<1>(0h0)) when _T_395 : node _T_396 = eq(_T_393, UInt<1>(0h0)) when _T_396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_393, UInt<1>(0h1), "") : assert_15 node _T_397 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_398 = asUInt(reset) node _T_399 = eq(_T_398, UInt<1>(0h0)) when _T_399 : node _T_400 = eq(_T_397, UInt<1>(0h0)) when _T_400 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_397, UInt<1>(0h1), "") : assert_16 node _T_401 = not(io.in.a.bits.mask) node _T_402 = eq(_T_401, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_402, UInt<1>(0h1), "") : assert_17 node _T_406 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_406, UInt<1>(0h1), "") : assert_18 node _T_410 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_410 : node _T_411 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_412 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_413 = and(_T_411, _T_412) node _T_414 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_415 = shr(io.in.a.bits.source, 2) node _T_416 = eq(_T_415, UInt<1>(0h0)) node _T_417 = leq(UInt<1>(0h0), uncommonBits_20) node _T_418 = and(_T_416, _T_417) node _T_419 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_421 = shr(io.in.a.bits.source, 2) node _T_422 = eq(_T_421, UInt<1>(0h1)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_21) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_426 = and(_T_424, _T_425) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_427 = shr(io.in.a.bits.source, 2) node _T_428 = eq(_T_427, UInt<2>(0h2)) node _T_429 = leq(UInt<1>(0h0), uncommonBits_22) node _T_430 = and(_T_428, _T_429) node _T_431 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_432 = and(_T_430, _T_431) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_433 = shr(io.in.a.bits.source, 2) node _T_434 = eq(_T_433, UInt<2>(0h3)) node _T_435 = leq(UInt<1>(0h0), uncommonBits_23) node _T_436 = and(_T_434, _T_435) node _T_437 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_440 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_441 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_442 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_443 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_444 = or(_T_414, _T_420) node _T_445 = or(_T_444, _T_426) node _T_446 = or(_T_445, _T_432) node _T_447 = or(_T_446, _T_438) node _T_448 = or(_T_447, _T_439) node _T_449 = or(_T_448, _T_440) node _T_450 = or(_T_449, _T_441) node _T_451 = or(_T_450, _T_442) node _T_452 = or(_T_451, _T_443) node _T_453 = and(_T_413, _T_452) node _T_454 = or(UInt<1>(0h0), _T_453) node _T_455 = asUInt(reset) node _T_456 = eq(_T_455, UInt<1>(0h0)) when _T_456 : node _T_457 = eq(_T_454, UInt<1>(0h0)) when _T_457 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_454, UInt<1>(0h1), "") : assert_19 node _T_458 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_459 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_460 = and(_T_458, _T_459) node _T_461 = or(UInt<1>(0h0), _T_460) node _T_462 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<13>(0h1000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = and(_T_461, _T_466) node _T_468 = or(UInt<1>(0h0), _T_467) node _T_469 = asUInt(reset) node _T_470 = eq(_T_469, UInt<1>(0h0)) when _T_470 : node _T_471 = eq(_T_468, UInt<1>(0h0)) when _T_471 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_468, UInt<1>(0h1), "") : assert_20 node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(source_ok, UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_475 = asUInt(reset) node _T_476 = eq(_T_475, UInt<1>(0h0)) when _T_476 : node _T_477 = eq(is_aligned, UInt<1>(0h0)) when _T_477 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_478 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_479 = asUInt(reset) node _T_480 = eq(_T_479, UInt<1>(0h0)) when _T_480 : node _T_481 = eq(_T_478, UInt<1>(0h0)) when _T_481 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_478, UInt<1>(0h1), "") : assert_23 node _T_482 = eq(io.in.a.bits.mask, mask) node _T_483 = asUInt(reset) node _T_484 = eq(_T_483, UInt<1>(0h0)) when _T_484 : node _T_485 = eq(_T_482, UInt<1>(0h0)) when _T_485 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_482, UInt<1>(0h1), "") : assert_24 node _T_486 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_487 = asUInt(reset) node _T_488 = eq(_T_487, UInt<1>(0h0)) when _T_488 : node _T_489 = eq(_T_486, UInt<1>(0h0)) when _T_489 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_486, UInt<1>(0h1), "") : assert_25 node _T_490 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_490 : node _T_491 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_492 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_493 = and(_T_491, _T_492) node _T_494 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 1, 0) node _T_495 = shr(io.in.a.bits.source, 2) node _T_496 = eq(_T_495, UInt<1>(0h0)) node _T_497 = leq(UInt<1>(0h0), uncommonBits_24) node _T_498 = and(_T_496, _T_497) node _T_499 = leq(uncommonBits_24, UInt<2>(0h3)) node _T_500 = and(_T_498, _T_499) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_501 = shr(io.in.a.bits.source, 2) node _T_502 = eq(_T_501, UInt<1>(0h1)) node _T_503 = leq(UInt<1>(0h0), uncommonBits_25) node _T_504 = and(_T_502, _T_503) node _T_505 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_506 = and(_T_504, _T_505) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_507 = shr(io.in.a.bits.source, 2) node _T_508 = eq(_T_507, UInt<2>(0h2)) node _T_509 = leq(UInt<1>(0h0), uncommonBits_26) node _T_510 = and(_T_508, _T_509) node _T_511 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_512 = and(_T_510, _T_511) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_513 = shr(io.in.a.bits.source, 2) node _T_514 = eq(_T_513, UInt<2>(0h3)) node _T_515 = leq(UInt<1>(0h0), uncommonBits_27) node _T_516 = and(_T_514, _T_515) node _T_517 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_518 = and(_T_516, _T_517) node _T_519 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_520 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_521 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_522 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_523 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_524 = or(_T_494, _T_500) node _T_525 = or(_T_524, _T_506) node _T_526 = or(_T_525, _T_512) node _T_527 = or(_T_526, _T_518) node _T_528 = or(_T_527, _T_519) node _T_529 = or(_T_528, _T_520) node _T_530 = or(_T_529, _T_521) node _T_531 = or(_T_530, _T_522) node _T_532 = or(_T_531, _T_523) node _T_533 = and(_T_493, _T_532) node _T_534 = or(UInt<1>(0h0), _T_533) node _T_535 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_536 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_537 = and(_T_535, _T_536) node _T_538 = or(UInt<1>(0h0), _T_537) node _T_539 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_540 = cvt(_T_539) node _T_541 = and(_T_540, asSInt(UInt<13>(0h1000))) node _T_542 = asSInt(_T_541) node _T_543 = eq(_T_542, asSInt(UInt<1>(0h0))) node _T_544 = and(_T_538, _T_543) node _T_545 = or(UInt<1>(0h0), _T_544) node _T_546 = and(_T_534, _T_545) node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_T_546, UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_546, UInt<1>(0h1), "") : assert_26 node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(source_ok, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_553 = asUInt(reset) node _T_554 = eq(_T_553, UInt<1>(0h0)) when _T_554 : node _T_555 = eq(is_aligned, UInt<1>(0h0)) when _T_555 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_556 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_557 = asUInt(reset) node _T_558 = eq(_T_557, UInt<1>(0h0)) when _T_558 : node _T_559 = eq(_T_556, UInt<1>(0h0)) when _T_559 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_556, UInt<1>(0h1), "") : assert_29 node _T_560 = eq(io.in.a.bits.mask, mask) node _T_561 = asUInt(reset) node _T_562 = eq(_T_561, UInt<1>(0h0)) when _T_562 : node _T_563 = eq(_T_560, UInt<1>(0h0)) when _T_563 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_560, UInt<1>(0h1), "") : assert_30 node _T_564 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_564 : node _T_565 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_566 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_567 = and(_T_565, _T_566) node _T_568 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_569 = shr(io.in.a.bits.source, 2) node _T_570 = eq(_T_569, UInt<1>(0h0)) node _T_571 = leq(UInt<1>(0h0), uncommonBits_28) node _T_572 = and(_T_570, _T_571) node _T_573 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_574 = and(_T_572, _T_573) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 1, 0) node _T_575 = shr(io.in.a.bits.source, 2) node _T_576 = eq(_T_575, UInt<1>(0h1)) node _T_577 = leq(UInt<1>(0h0), uncommonBits_29) node _T_578 = and(_T_576, _T_577) node _T_579 = leq(uncommonBits_29, UInt<2>(0h3)) node _T_580 = and(_T_578, _T_579) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_581 = shr(io.in.a.bits.source, 2) node _T_582 = eq(_T_581, UInt<2>(0h2)) node _T_583 = leq(UInt<1>(0h0), uncommonBits_30) node _T_584 = and(_T_582, _T_583) node _T_585 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_586 = and(_T_584, _T_585) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_587 = shr(io.in.a.bits.source, 2) node _T_588 = eq(_T_587, UInt<2>(0h3)) node _T_589 = leq(UInt<1>(0h0), uncommonBits_31) node _T_590 = and(_T_588, _T_589) node _T_591 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_592 = and(_T_590, _T_591) node _T_593 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_594 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_595 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_596 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_597 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_598 = or(_T_568, _T_574) node _T_599 = or(_T_598, _T_580) node _T_600 = or(_T_599, _T_586) node _T_601 = or(_T_600, _T_592) node _T_602 = or(_T_601, _T_593) node _T_603 = or(_T_602, _T_594) node _T_604 = or(_T_603, _T_595) node _T_605 = or(_T_604, _T_596) node _T_606 = or(_T_605, _T_597) node _T_607 = and(_T_567, _T_606) node _T_608 = or(UInt<1>(0h0), _T_607) node _T_609 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_610 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_611 = and(_T_609, _T_610) node _T_612 = or(UInt<1>(0h0), _T_611) node _T_613 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_614 = cvt(_T_613) node _T_615 = and(_T_614, asSInt(UInt<13>(0h1000))) node _T_616 = asSInt(_T_615) node _T_617 = eq(_T_616, asSInt(UInt<1>(0h0))) node _T_618 = and(_T_612, _T_617) node _T_619 = or(UInt<1>(0h0), _T_618) node _T_620 = and(_T_608, _T_619) node _T_621 = asUInt(reset) node _T_622 = eq(_T_621, UInt<1>(0h0)) when _T_622 : node _T_623 = eq(_T_620, UInt<1>(0h0)) when _T_623 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_620, UInt<1>(0h1), "") : assert_31 node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(source_ok, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_627 = asUInt(reset) node _T_628 = eq(_T_627, UInt<1>(0h0)) when _T_628 : node _T_629 = eq(is_aligned, UInt<1>(0h0)) when _T_629 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_630 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_631 = asUInt(reset) node _T_632 = eq(_T_631, UInt<1>(0h0)) when _T_632 : node _T_633 = eq(_T_630, UInt<1>(0h0)) when _T_633 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_630, UInt<1>(0h1), "") : assert_34 node _T_634 = not(mask) node _T_635 = and(io.in.a.bits.mask, _T_634) node _T_636 = eq(_T_635, UInt<1>(0h0)) node _T_637 = asUInt(reset) node _T_638 = eq(_T_637, UInt<1>(0h0)) when _T_638 : node _T_639 = eq(_T_636, UInt<1>(0h0)) when _T_639 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_636, UInt<1>(0h1), "") : assert_35 node _T_640 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_640 : node _T_641 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_642 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_643 = and(_T_641, _T_642) node _T_644 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_645 = shr(io.in.a.bits.source, 2) node _T_646 = eq(_T_645, UInt<1>(0h0)) node _T_647 = leq(UInt<1>(0h0), uncommonBits_32) node _T_648 = and(_T_646, _T_647) node _T_649 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_650 = and(_T_648, _T_649) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_651 = shr(io.in.a.bits.source, 2) node _T_652 = eq(_T_651, UInt<1>(0h1)) node _T_653 = leq(UInt<1>(0h0), uncommonBits_33) node _T_654 = and(_T_652, _T_653) node _T_655 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_656 = and(_T_654, _T_655) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 1, 0) node _T_657 = shr(io.in.a.bits.source, 2) node _T_658 = eq(_T_657, UInt<2>(0h2)) node _T_659 = leq(UInt<1>(0h0), uncommonBits_34) node _T_660 = and(_T_658, _T_659) node _T_661 = leq(uncommonBits_34, UInt<2>(0h3)) node _T_662 = and(_T_660, _T_661) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_663 = shr(io.in.a.bits.source, 2) node _T_664 = eq(_T_663, UInt<2>(0h3)) node _T_665 = leq(UInt<1>(0h0), uncommonBits_35) node _T_666 = and(_T_664, _T_665) node _T_667 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_668 = and(_T_666, _T_667) node _T_669 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_670 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_671 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_672 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_673 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_674 = or(_T_644, _T_650) node _T_675 = or(_T_674, _T_656) node _T_676 = or(_T_675, _T_662) node _T_677 = or(_T_676, _T_668) node _T_678 = or(_T_677, _T_669) node _T_679 = or(_T_678, _T_670) node _T_680 = or(_T_679, _T_671) node _T_681 = or(_T_680, _T_672) node _T_682 = or(_T_681, _T_673) node _T_683 = and(_T_643, _T_682) node _T_684 = or(UInt<1>(0h0), _T_683) node _T_685 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_686 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = and(_T_685, _T_690) node _T_692 = or(UInt<1>(0h0), _T_691) node _T_693 = and(_T_684, _T_692) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_693, UInt<1>(0h1), "") : assert_36 node _T_697 = asUInt(reset) node _T_698 = eq(_T_697, UInt<1>(0h0)) when _T_698 : node _T_699 = eq(source_ok, UInt<1>(0h0)) when _T_699 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_700 = asUInt(reset) node _T_701 = eq(_T_700, UInt<1>(0h0)) when _T_701 : node _T_702 = eq(is_aligned, UInt<1>(0h0)) when _T_702 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_703 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_704 = asUInt(reset) node _T_705 = eq(_T_704, UInt<1>(0h0)) when _T_705 : node _T_706 = eq(_T_703, UInt<1>(0h0)) when _T_706 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_703, UInt<1>(0h1), "") : assert_39 node _T_707 = eq(io.in.a.bits.mask, mask) node _T_708 = asUInt(reset) node _T_709 = eq(_T_708, UInt<1>(0h0)) when _T_709 : node _T_710 = eq(_T_707, UInt<1>(0h0)) when _T_710 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_707, UInt<1>(0h1), "") : assert_40 node _T_711 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_711 : node _T_712 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_713 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_714 = and(_T_712, _T_713) node _T_715 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_716 = shr(io.in.a.bits.source, 2) node _T_717 = eq(_T_716, UInt<1>(0h0)) node _T_718 = leq(UInt<1>(0h0), uncommonBits_36) node _T_719 = and(_T_717, _T_718) node _T_720 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_721 = and(_T_719, _T_720) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_722 = shr(io.in.a.bits.source, 2) node _T_723 = eq(_T_722, UInt<1>(0h1)) node _T_724 = leq(UInt<1>(0h0), uncommonBits_37) node _T_725 = and(_T_723, _T_724) node _T_726 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_727 = and(_T_725, _T_726) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_728 = shr(io.in.a.bits.source, 2) node _T_729 = eq(_T_728, UInt<2>(0h2)) node _T_730 = leq(UInt<1>(0h0), uncommonBits_38) node _T_731 = and(_T_729, _T_730) node _T_732 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_733 = and(_T_731, _T_732) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 1, 0) node _T_734 = shr(io.in.a.bits.source, 2) node _T_735 = eq(_T_734, UInt<2>(0h3)) node _T_736 = leq(UInt<1>(0h0), uncommonBits_39) node _T_737 = and(_T_735, _T_736) node _T_738 = leq(uncommonBits_39, UInt<2>(0h3)) node _T_739 = and(_T_737, _T_738) node _T_740 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_741 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_742 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_743 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_744 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_745 = or(_T_715, _T_721) node _T_746 = or(_T_745, _T_727) node _T_747 = or(_T_746, _T_733) node _T_748 = or(_T_747, _T_739) node _T_749 = or(_T_748, _T_740) node _T_750 = or(_T_749, _T_741) node _T_751 = or(_T_750, _T_742) node _T_752 = or(_T_751, _T_743) node _T_753 = or(_T_752, _T_744) node _T_754 = and(_T_714, _T_753) node _T_755 = or(UInt<1>(0h0), _T_754) node _T_756 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_757 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_758 = cvt(_T_757) node _T_759 = and(_T_758, asSInt(UInt<13>(0h1000))) node _T_760 = asSInt(_T_759) node _T_761 = eq(_T_760, asSInt(UInt<1>(0h0))) node _T_762 = and(_T_756, _T_761) node _T_763 = or(UInt<1>(0h0), _T_762) node _T_764 = and(_T_755, _T_763) node _T_765 = asUInt(reset) node _T_766 = eq(_T_765, UInt<1>(0h0)) when _T_766 : node _T_767 = eq(_T_764, UInt<1>(0h0)) when _T_767 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_764, UInt<1>(0h1), "") : assert_41 node _T_768 = asUInt(reset) node _T_769 = eq(_T_768, UInt<1>(0h0)) when _T_769 : node _T_770 = eq(source_ok, UInt<1>(0h0)) when _T_770 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_771 = asUInt(reset) node _T_772 = eq(_T_771, UInt<1>(0h0)) when _T_772 : node _T_773 = eq(is_aligned, UInt<1>(0h0)) when _T_773 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_774 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_775 = asUInt(reset) node _T_776 = eq(_T_775, UInt<1>(0h0)) when _T_776 : node _T_777 = eq(_T_774, UInt<1>(0h0)) when _T_777 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_774, UInt<1>(0h1), "") : assert_44 node _T_778 = eq(io.in.a.bits.mask, mask) node _T_779 = asUInt(reset) node _T_780 = eq(_T_779, UInt<1>(0h0)) when _T_780 : node _T_781 = eq(_T_778, UInt<1>(0h0)) when _T_781 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_778, UInt<1>(0h1), "") : assert_45 node _T_782 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_782 : node _T_783 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_784 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_785 = and(_T_783, _T_784) node _T_786 = eq(io.in.a.bits.source, UInt<5>(0h11)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_787 = shr(io.in.a.bits.source, 2) node _T_788 = eq(_T_787, UInt<1>(0h0)) node _T_789 = leq(UInt<1>(0h0), uncommonBits_40) node _T_790 = and(_T_788, _T_789) node _T_791 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_792 = and(_T_790, _T_791) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_793 = shr(io.in.a.bits.source, 2) node _T_794 = eq(_T_793, UInt<1>(0h1)) node _T_795 = leq(UInt<1>(0h0), uncommonBits_41) node _T_796 = and(_T_794, _T_795) node _T_797 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_798 = and(_T_796, _T_797) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_799 = shr(io.in.a.bits.source, 2) node _T_800 = eq(_T_799, UInt<2>(0h2)) node _T_801 = leq(UInt<1>(0h0), uncommonBits_42) node _T_802 = and(_T_800, _T_801) node _T_803 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_804 = and(_T_802, _T_803) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_805 = shr(io.in.a.bits.source, 2) node _T_806 = eq(_T_805, UInt<2>(0h3)) node _T_807 = leq(UInt<1>(0h0), uncommonBits_43) node _T_808 = and(_T_806, _T_807) node _T_809 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_810 = and(_T_808, _T_809) node _T_811 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_812 = eq(io.in.a.bits.source, UInt<6>(0h20)) node _T_813 = eq(io.in.a.bits.source, UInt<6>(0h21)) node _T_814 = eq(io.in.a.bits.source, UInt<6>(0h22)) node _T_815 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_816 = or(_T_786, _T_792) node _T_817 = or(_T_816, _T_798) node _T_818 = or(_T_817, _T_804) node _T_819 = or(_T_818, _T_810) node _T_820 = or(_T_819, _T_811) node _T_821 = or(_T_820, _T_812) node _T_822 = or(_T_821, _T_813) node _T_823 = or(_T_822, _T_814) node _T_824 = or(_T_823, _T_815) node _T_825 = and(_T_785, _T_824) node _T_826 = or(UInt<1>(0h0), _T_825) node _T_827 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_828 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_829 = cvt(_T_828) node _T_830 = and(_T_829, asSInt(UInt<13>(0h1000))) node _T_831 = asSInt(_T_830) node _T_832 = eq(_T_831, asSInt(UInt<1>(0h0))) node _T_833 = and(_T_827, _T_832) node _T_834 = or(UInt<1>(0h0), _T_833) node _T_835 = and(_T_826, _T_834) node _T_836 = asUInt(reset) node _T_837 = eq(_T_836, UInt<1>(0h0)) when _T_837 : node _T_838 = eq(_T_835, UInt<1>(0h0)) when _T_838 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_835, UInt<1>(0h1), "") : assert_46 node _T_839 = asUInt(reset) node _T_840 = eq(_T_839, UInt<1>(0h0)) when _T_840 : node _T_841 = eq(source_ok, UInt<1>(0h0)) when _T_841 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_842 = asUInt(reset) node _T_843 = eq(_T_842, UInt<1>(0h0)) when _T_843 : node _T_844 = eq(is_aligned, UInt<1>(0h0)) when _T_844 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_845 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(_T_845, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_845, UInt<1>(0h1), "") : assert_49 node _T_849 = eq(io.in.a.bits.mask, mask) node _T_850 = asUInt(reset) node _T_851 = eq(_T_850, UInt<1>(0h0)) when _T_851 : node _T_852 = eq(_T_849, UInt<1>(0h0)) when _T_852 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_849, UInt<1>(0h1), "") : assert_50 node _T_853 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_854 = asUInt(reset) node _T_855 = eq(_T_854, UInt<1>(0h0)) when _T_855 : node _T_856 = eq(_T_853, UInt<1>(0h0)) when _T_856 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_853, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_857 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_858 = asUInt(reset) node _T_859 = eq(_T_858, UInt<1>(0h0)) when _T_859 : node _T_860 = eq(_T_857, UInt<1>(0h0)) when _T_860 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_857, UInt<1>(0h1), "") : assert_52 node _source_ok_T_38 = eq(io.in.d.bits.source, UInt<5>(0h11)) node _source_ok_uncommonBits_T_4 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 1, 0) node _source_ok_T_39 = shr(io.in.d.bits.source, 2) node _source_ok_T_40 = eq(_source_ok_T_39, UInt<1>(0h0)) node _source_ok_T_41 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_42 = and(_source_ok_T_40, _source_ok_T_41) node _source_ok_T_43 = leq(source_ok_uncommonBits_4, UInt<2>(0h3)) node _source_ok_T_44 = and(_source_ok_T_42, _source_ok_T_43) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_45 = shr(io.in.d.bits.source, 2) node _source_ok_T_46 = eq(_source_ok_T_45, UInt<1>(0h1)) node _source_ok_T_47 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_48 = and(_source_ok_T_46, _source_ok_T_47) node _source_ok_T_49 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_50 = and(_source_ok_T_48, _source_ok_T_49) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_51 = shr(io.in.d.bits.source, 2) node _source_ok_T_52 = eq(_source_ok_T_51, UInt<2>(0h2)) node _source_ok_T_53 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_54 = and(_source_ok_T_52, _source_ok_T_53) node _source_ok_T_55 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_56 = and(_source_ok_T_54, _source_ok_T_55) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_57 = shr(io.in.d.bits.source, 2) node _source_ok_T_58 = eq(_source_ok_T_57, UInt<2>(0h3)) node _source_ok_T_59 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_60 = and(_source_ok_T_58, _source_ok_T_59) node _source_ok_T_61 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_62 = and(_source_ok_T_60, _source_ok_T_61) node _source_ok_T_63 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_T_64 = eq(io.in.d.bits.source, UInt<6>(0h20)) node _source_ok_T_65 = eq(io.in.d.bits.source, UInt<6>(0h21)) node _source_ok_T_66 = eq(io.in.d.bits.source, UInt<6>(0h22)) node _source_ok_T_67 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_38 connect _source_ok_WIRE_1[1], _source_ok_T_44 connect _source_ok_WIRE_1[2], _source_ok_T_50 connect _source_ok_WIRE_1[3], _source_ok_T_56 connect _source_ok_WIRE_1[4], _source_ok_T_62 connect _source_ok_WIRE_1[5], _source_ok_T_63 connect _source_ok_WIRE_1[6], _source_ok_T_64 connect _source_ok_WIRE_1[7], _source_ok_T_65 connect _source_ok_WIRE_1[8], _source_ok_T_66 connect _source_ok_WIRE_1[9], _source_ok_T_67 node _source_ok_T_68 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_69 = or(_source_ok_T_68, _source_ok_WIRE_1[2]) node _source_ok_T_70 = or(_source_ok_T_69, _source_ok_WIRE_1[3]) node _source_ok_T_71 = or(_source_ok_T_70, _source_ok_WIRE_1[4]) node _source_ok_T_72 = or(_source_ok_T_71, _source_ok_WIRE_1[5]) node _source_ok_T_73 = or(_source_ok_T_72, _source_ok_WIRE_1[6]) node _source_ok_T_74 = or(_source_ok_T_73, _source_ok_WIRE_1[7]) node _source_ok_T_75 = or(_source_ok_T_74, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_75, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_861 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_861 : node _T_862 = asUInt(reset) node _T_863 = eq(_T_862, UInt<1>(0h0)) when _T_863 : node _T_864 = eq(source_ok_1, UInt<1>(0h0)) when _T_864 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_865 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_866 = asUInt(reset) node _T_867 = eq(_T_866, UInt<1>(0h0)) when _T_867 : node _T_868 = eq(_T_865, UInt<1>(0h0)) when _T_868 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_865, UInt<1>(0h1), "") : assert_54 node _T_869 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_870 = asUInt(reset) node _T_871 = eq(_T_870, UInt<1>(0h0)) when _T_871 : node _T_872 = eq(_T_869, UInt<1>(0h0)) when _T_872 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_869, UInt<1>(0h1), "") : assert_55 node _T_873 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_874 = asUInt(reset) node _T_875 = eq(_T_874, UInt<1>(0h0)) when _T_875 : node _T_876 = eq(_T_873, UInt<1>(0h0)) when _T_876 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_873, UInt<1>(0h1), "") : assert_56 node _T_877 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_878 = asUInt(reset) node _T_879 = eq(_T_878, UInt<1>(0h0)) when _T_879 : node _T_880 = eq(_T_877, UInt<1>(0h0)) when _T_880 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_877, UInt<1>(0h1), "") : assert_57 node _T_881 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_881 : node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(source_ok_1, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(sink_ok, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_888 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_889 = asUInt(reset) node _T_890 = eq(_T_889, UInt<1>(0h0)) when _T_890 : node _T_891 = eq(_T_888, UInt<1>(0h0)) when _T_891 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_888, UInt<1>(0h1), "") : assert_60 node _T_892 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_893 = asUInt(reset) node _T_894 = eq(_T_893, UInt<1>(0h0)) when _T_894 : node _T_895 = eq(_T_892, UInt<1>(0h0)) when _T_895 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_892, UInt<1>(0h1), "") : assert_61 node _T_896 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(_T_896, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_896, UInt<1>(0h1), "") : assert_62 node _T_900 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_900, UInt<1>(0h1), "") : assert_63 node _T_904 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_905 = or(UInt<1>(0h0), _T_904) node _T_906 = asUInt(reset) node _T_907 = eq(_T_906, UInt<1>(0h0)) when _T_907 : node _T_908 = eq(_T_905, UInt<1>(0h0)) when _T_908 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_905, UInt<1>(0h1), "") : assert_64 node _T_909 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_909 : node _T_910 = asUInt(reset) node _T_911 = eq(_T_910, UInt<1>(0h0)) when _T_911 : node _T_912 = eq(source_ok_1, UInt<1>(0h0)) when _T_912 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(sink_ok, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_916 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(_T_916, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_916, UInt<1>(0h1), "") : assert_67 node _T_920 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_920, UInt<1>(0h1), "") : assert_68 node _T_924 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_924, UInt<1>(0h1), "") : assert_69 node _T_928 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_929 = or(_T_928, io.in.d.bits.corrupt) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_929, UInt<1>(0h1), "") : assert_70 node _T_933 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_934 = or(UInt<1>(0h0), _T_933) node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(_T_934, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_934, UInt<1>(0h1), "") : assert_71 node _T_938 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_938 : node _T_939 = asUInt(reset) node _T_940 = eq(_T_939, UInt<1>(0h0)) when _T_940 : node _T_941 = eq(source_ok_1, UInt<1>(0h0)) when _T_941 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_942 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_943 = asUInt(reset) node _T_944 = eq(_T_943, UInt<1>(0h0)) when _T_944 : node _T_945 = eq(_T_942, UInt<1>(0h0)) when _T_945 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_942, UInt<1>(0h1), "") : assert_73 node _T_946 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_947 = asUInt(reset) node _T_948 = eq(_T_947, UInt<1>(0h0)) when _T_948 : node _T_949 = eq(_T_946, UInt<1>(0h0)) when _T_949 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_946, UInt<1>(0h1), "") : assert_74 node _T_950 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_951 = or(UInt<1>(0h0), _T_950) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_951, UInt<1>(0h1), "") : assert_75 node _T_955 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_955 : node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(source_ok_1, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_959 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_960 = asUInt(reset) node _T_961 = eq(_T_960, UInt<1>(0h0)) when _T_961 : node _T_962 = eq(_T_959, UInt<1>(0h0)) when _T_962 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_959, UInt<1>(0h1), "") : assert_77 node _T_963 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_964 = or(_T_963, io.in.d.bits.corrupt) node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(_T_964, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_964, UInt<1>(0h1), "") : assert_78 node _T_968 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_969 = or(UInt<1>(0h0), _T_968) node _T_970 = asUInt(reset) node _T_971 = eq(_T_970, UInt<1>(0h0)) when _T_971 : node _T_972 = eq(_T_969, UInt<1>(0h0)) when _T_972 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_969, UInt<1>(0h1), "") : assert_79 node _T_973 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_973 : node _T_974 = asUInt(reset) node _T_975 = eq(_T_974, UInt<1>(0h0)) when _T_975 : node _T_976 = eq(source_ok_1, UInt<1>(0h0)) when _T_976 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_977 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_978 = asUInt(reset) node _T_979 = eq(_T_978, UInt<1>(0h0)) when _T_979 : node _T_980 = eq(_T_977, UInt<1>(0h0)) when _T_980 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_977, UInt<1>(0h1), "") : assert_81 node _T_981 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_982 = asUInt(reset) node _T_983 = eq(_T_982, UInt<1>(0h0)) when _T_983 : node _T_984 = eq(_T_981, UInt<1>(0h0)) when _T_984 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_981, UInt<1>(0h1), "") : assert_82 node _T_985 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_986 = or(UInt<1>(0h0), _T_985) node _T_987 = asUInt(reset) node _T_988 = eq(_T_987, UInt<1>(0h0)) when _T_988 : node _T_989 = eq(_T_986, UInt<1>(0h0)) when _T_989 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_986, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_990 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_991 = asUInt(reset) node _T_992 = eq(_T_991, UInt<1>(0h0)) when _T_992 : node _T_993 = eq(_T_990, UInt<1>(0h0)) when _T_993 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_990, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_994 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_995 = asUInt(reset) node _T_996 = eq(_T_995, UInt<1>(0h0)) when _T_996 : node _T_997 = eq(_T_994, UInt<1>(0h0)) when _T_997 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_994, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_998 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_999 = asUInt(reset) node _T_1000 = eq(_T_999, UInt<1>(0h0)) when _T_1000 : node _T_1001 = eq(_T_998, UInt<1>(0h0)) when _T_1001 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_998, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1002 = eq(a_first, UInt<1>(0h0)) node _T_1003 = and(io.in.a.valid, _T_1002) when _T_1003 : node _T_1004 = eq(io.in.a.bits.opcode, opcode) node _T_1005 = asUInt(reset) node _T_1006 = eq(_T_1005, UInt<1>(0h0)) when _T_1006 : node _T_1007 = eq(_T_1004, UInt<1>(0h0)) when _T_1007 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1004, UInt<1>(0h1), "") : assert_87 node _T_1008 = eq(io.in.a.bits.param, param) node _T_1009 = asUInt(reset) node _T_1010 = eq(_T_1009, UInt<1>(0h0)) when _T_1010 : node _T_1011 = eq(_T_1008, UInt<1>(0h0)) when _T_1011 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1008, UInt<1>(0h1), "") : assert_88 node _T_1012 = eq(io.in.a.bits.size, size) node _T_1013 = asUInt(reset) node _T_1014 = eq(_T_1013, UInt<1>(0h0)) when _T_1014 : node _T_1015 = eq(_T_1012, UInt<1>(0h0)) when _T_1015 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1012, UInt<1>(0h1), "") : assert_89 node _T_1016 = eq(io.in.a.bits.source, source) node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_T_1016, UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1016, UInt<1>(0h1), "") : assert_90 node _T_1020 = eq(io.in.a.bits.address, address) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_91 node _T_1024 = and(io.in.a.ready, io.in.a.valid) node _T_1025 = and(_T_1024, a_first) when _T_1025 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1026 = eq(d_first, UInt<1>(0h0)) node _T_1027 = and(io.in.d.valid, _T_1026) when _T_1027 : node _T_1028 = eq(io.in.d.bits.opcode, opcode_1) node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(_T_1028, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1028, UInt<1>(0h1), "") : assert_92 node _T_1032 = eq(io.in.d.bits.param, param_1) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_93 node _T_1036 = eq(io.in.d.bits.size, size_1) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_94 node _T_1040 = eq(io.in.d.bits.source, source_1) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_95 node _T_1044 = eq(io.in.d.bits.sink, sink) node _T_1045 = asUInt(reset) node _T_1046 = eq(_T_1045, UInt<1>(0h0)) when _T_1046 : node _T_1047 = eq(_T_1044, UInt<1>(0h0)) when _T_1047 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1044, UInt<1>(0h1), "") : assert_96 node _T_1048 = eq(io.in.d.bits.denied, denied) node _T_1049 = asUInt(reset) node _T_1050 = eq(_T_1049, UInt<1>(0h0)) when _T_1050 : node _T_1051 = eq(_T_1048, UInt<1>(0h0)) when _T_1051 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1048, UInt<1>(0h1), "") : assert_97 node _T_1052 = and(io.in.d.ready, io.in.d.valid) node _T_1053 = and(_T_1052, d_first) when _T_1053 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1054 = and(io.in.a.valid, a_first_1) node _T_1055 = and(_T_1054, UInt<1>(0h1)) when _T_1055 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1056 = and(io.in.a.ready, io.in.a.valid) node _T_1057 = and(_T_1056, a_first_1) node _T_1058 = and(_T_1057, UInt<1>(0h1)) when _T_1058 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1059 = dshr(inflight, io.in.a.bits.source) node _T_1060 = bits(_T_1059, 0, 0) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_T_1061, UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1061, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1065 = and(io.in.d.valid, d_first_1) node _T_1066 = and(_T_1065, UInt<1>(0h1)) node _T_1067 = eq(d_release_ack, UInt<1>(0h0)) node _T_1068 = and(_T_1066, _T_1067) when _T_1068 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1069 = and(io.in.d.ready, io.in.d.valid) node _T_1070 = and(_T_1069, d_first_1) node _T_1071 = and(_T_1070, UInt<1>(0h1)) node _T_1072 = eq(d_release_ack, UInt<1>(0h0)) node _T_1073 = and(_T_1071, _T_1072) when _T_1073 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1074 = and(io.in.d.valid, d_first_1) node _T_1075 = and(_T_1074, UInt<1>(0h1)) node _T_1076 = eq(d_release_ack, UInt<1>(0h0)) node _T_1077 = and(_T_1075, _T_1076) when _T_1077 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1078 = dshr(inflight, io.in.d.bits.source) node _T_1079 = bits(_T_1078, 0, 0) node _T_1080 = or(_T_1079, same_cycle_resp) node _T_1081 = asUInt(reset) node _T_1082 = eq(_T_1081, UInt<1>(0h0)) when _T_1082 : node _T_1083 = eq(_T_1080, UInt<1>(0h0)) when _T_1083 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1080, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1084 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1085 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1086 = or(_T_1084, _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_100 node _T_1090 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1091 = asUInt(reset) node _T_1092 = eq(_T_1091, UInt<1>(0h0)) when _T_1092 : node _T_1093 = eq(_T_1090, UInt<1>(0h0)) when _T_1093 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1090, UInt<1>(0h1), "") : assert_101 else : node _T_1094 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1095 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1096 = or(_T_1094, _T_1095) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_102 node _T_1100 = eq(io.in.d.bits.size, a_size_lookup) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_103 node _T_1104 = and(io.in.d.valid, d_first_1) node _T_1105 = and(_T_1104, a_first_1) node _T_1106 = and(_T_1105, io.in.a.valid) node _T_1107 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1108 = and(_T_1106, _T_1107) node _T_1109 = eq(d_release_ack, UInt<1>(0h0)) node _T_1110 = and(_T_1108, _T_1109) when _T_1110 : node _T_1111 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1112 = or(_T_1111, io.in.a.ready) node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(_T_1112, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1112, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_143 node _T_1116 = orr(inflight) node _T_1117 = eq(_T_1116, UInt<1>(0h0)) node _T_1118 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1119 = or(_T_1117, _T_1118) node _T_1120 = lt(watchdog, plusarg_reader.out) node _T_1121 = or(_T_1119, _T_1120) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1125 = and(io.in.a.ready, io.in.a.valid) node _T_1126 = and(io.in.d.ready, io.in.d.valid) node _T_1127 = or(_T_1125, _T_1126) when _T_1127 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1128 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1129 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1130 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1131 = and(_T_1129, _T_1130) node _T_1132 = and(_T_1128, _T_1131) when _T_1132 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1133 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1134 = and(_T_1133, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1135 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1136 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1137 = and(_T_1135, _T_1136) node _T_1138 = and(_T_1134, _T_1137) when _T_1138 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1139 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1140 = bits(_T_1139, 0, 0) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1145 = and(io.in.d.valid, d_first_2) node _T_1146 = and(_T_1145, UInt<1>(0h1)) node _T_1147 = and(_T_1146, d_release_ack_1) when _T_1147 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1148 = and(io.in.d.ready, io.in.d.valid) node _T_1149 = and(_T_1148, d_first_2) node _T_1150 = and(_T_1149, UInt<1>(0h1)) node _T_1151 = and(_T_1150, d_release_ack_1) when _T_1151 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1152 = and(io.in.d.valid, d_first_2) node _T_1153 = and(_T_1152, UInt<1>(0h1)) node _T_1154 = and(_T_1153, d_release_ack_1) when _T_1154 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1155 = dshr(inflight_1, io.in.d.bits.source) node _T_1156 = bits(_T_1155, 0, 0) node _T_1157 = or(_T_1156, same_cycle_resp_1) node _T_1158 = asUInt(reset) node _T_1159 = eq(_T_1158, UInt<1>(0h0)) when _T_1159 : node _T_1160 = eq(_T_1157, UInt<1>(0h0)) when _T_1160 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1157, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1161 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1162 = asUInt(reset) node _T_1163 = eq(_T_1162, UInt<1>(0h0)) when _T_1163 : node _T_1164 = eq(_T_1161, UInt<1>(0h0)) when _T_1164 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1161, UInt<1>(0h1), "") : assert_108 else : node _T_1165 = eq(io.in.d.bits.size, c_size_lookup) node _T_1166 = asUInt(reset) node _T_1167 = eq(_T_1166, UInt<1>(0h0)) when _T_1167 : node _T_1168 = eq(_T_1165, UInt<1>(0h0)) when _T_1168 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1165, UInt<1>(0h1), "") : assert_109 node _T_1169 = and(io.in.d.valid, d_first_2) node _T_1170 = and(_T_1169, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1171 = and(_T_1170, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1172 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1173 = and(_T_1171, _T_1172) node _T_1174 = and(_T_1173, d_release_ack_1) node _T_1175 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1176 = and(_T_1174, _T_1175) when _T_1176 : node _T_1177 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1178 = or(_T_1177, _WIRE_27.ready) node _T_1179 = asUInt(reset) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) when _T_1180 : node _T_1181 = eq(_T_1178, UInt<1>(0h0)) when _T_1181 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1178, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_144 node _T_1182 = orr(inflight_1) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) node _T_1184 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1185 = or(_T_1183, _T_1184) node _T_1186 = lt(watchdog_1, plusarg_reader_1.out) node _T_1187 = or(_T_1185, _T_1186) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1191 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1192 = and(io.in.d.ready, io.in.d.valid) node _T_1193 = or(_T_1191, _T_1192) when _T_1193 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_70( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [12:0] _GEN = {10'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [2:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] reg [2:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _GEN_0 = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:673:46] wire _GEN_1 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [64:0] inflight_1; // @[Monitor.scala:726:35] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_19 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_29 connect io_out_sink_valid.clock, clock connect io_out_sink_valid.reset, reset connect io_out_sink_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_19( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_29 io_out_sink_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module NoCMonitor_14 : input clock : Clock input reset : Reset output io : { flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], credit_return : UInt<3>, vc_free : UInt<3>}} wire _in_flight_WIRE : UInt<1>[3] connect _in_flight_WIRE[0], UInt<1>(0h0) connect _in_flight_WIRE[1], UInt<1>(0h0) connect _in_flight_WIRE[2], UInt<1>(0h0) regreset in_flight : UInt<1>[3], clock, reset, _in_flight_WIRE when io.in.flit[0].valid : when io.in.flit[0].bits.head : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h1) node _T = eq(in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: Flit head/tail sequencing is broken\n at Monitor.scala:22 assert (!in_flight(flit.bits.virt_channel_id), \"Flit head/tail sequencing is broken\")\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert when io.in.flit[0].bits.tail : connect in_flight[io.in.flit[0].bits.virt_channel_id], UInt<1>(0h0) node _T_4 = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T_4 : node _T_5 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h0)) node _T_6 = or(_T_5, UInt<1>(0h0)) node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : node _T_9 = eq(_T_6, UInt<1>(0h0)) when _T_9 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_1 assert(clock, _T_6, UInt<1>(0h1), "") : assert_1 node _T_10 = neq(io.in.flit[0].bits.virt_channel_id, UInt<1>(0h1)) node _T_11 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_12 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_13 = and(_T_11, _T_12) node _T_14 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_15 = and(_T_13, _T_14) node _T_16 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_19 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_20 = and(_T_18, _T_19) node _T_21 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_24 = and(_T_22, _T_23) node _T_25 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_26 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_27 = and(_T_25, _T_26) node _T_28 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_29 = and(_T_27, _T_28) node _T_30 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_31 = and(_T_29, _T_30) node _T_32 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_33 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_34 = and(_T_32, _T_33) node _T_35 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h1)) node _T_36 = and(_T_34, _T_35) node _T_37 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h1)) node _T_38 = and(_T_36, _T_37) node _T_39 = or(_T_17, _T_24) node _T_40 = or(_T_39, _T_31) node _T_41 = or(_T_40, _T_38) node _T_42 = or(_T_10, _T_41) node _T_43 = asUInt(reset) node _T_44 = eq(_T_43, UInt<1>(0h0)) when _T_44 : node _T_45 = eq(_T_42, UInt<1>(0h0)) when _T_45 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_2 assert(clock, _T_42, UInt<1>(0h1), "") : assert_2 node _T_46 = neq(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h2)) node _T_47 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_48 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h6)) node _T_49 = and(_T_47, _T_48) node _T_50 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) node _T_52 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_53 = and(_T_51, _T_52) node _T_54 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_55 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_58 = and(_T_56, _T_57) node _T_59 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_60 = and(_T_58, _T_59) node _T_61 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_62 = eq(io.in.flit[0].bits.flow.egress_node, UInt<3>(0h5)) node _T_63 = and(_T_61, _T_62) node _T_64 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_65 = and(_T_63, _T_64) node _T_66 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) node _T_68 = eq(io.in.flit[0].bits.flow.ingress_node, UInt<3>(0h4)) node _T_69 = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0ha)) node _T_70 = and(_T_68, _T_69) node _T_71 = eq(io.in.flit[0].bits.flow.ingress_node_id, UInt<1>(0h0)) node _T_72 = and(_T_70, _T_71) node _T_73 = eq(io.in.flit[0].bits.flow.egress_node_id, UInt<1>(0h0)) node _T_74 = and(_T_72, _T_73) node _T_75 = or(_T_53, _T_60) node _T_76 = or(_T_75, _T_67) node _T_77 = or(_T_76, _T_74) node _T_78 = or(_T_46, _T_77) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Monitor.scala:32 assert(flit.bits.virt_channel_id =/= i.U || v.possibleFlows.toSeq.map(_.isFlow(flit.bits.flow)).orR)\n") : printf_3 assert(clock, _T_78, UInt<1>(0h1), "") : assert_3
module NoCMonitor_14( // @[Monitor.scala:11:7] input clock, // @[Monitor.scala:11:7] input reset, // @[Monitor.scala:11:7] input io_in_flit_0_valid, // @[Monitor.scala:12:14] input io_in_flit_0_bits_head, // @[Monitor.scala:12:14] input io_in_flit_0_bits_tail, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[Monitor.scala:12:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[Monitor.scala:12:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[Monitor.scala:12:14] input [1:0] io_in_flit_0_bits_virt_channel_id // @[Monitor.scala:12:14] ); reg in_flight_0; // @[Monitor.scala:16:26] reg in_flight_1; // @[Monitor.scala:16:26] reg in_flight_2; // @[Monitor.scala:16:26] wire _GEN = io_in_flit_0_bits_virt_channel_id == 2'h0; // @[Monitor.scala:21:46]
Generate the Verilog code corresponding to this FIRRTL code module Router_19 : input clock : Clock input reset : Reset output auto : { debug_out : { va_stall : UInt[5], sa_stall : UInt[5]}, source_nodes_out_4 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, source_nodes_out_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, source_nodes_out_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, source_nodes_out_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, source_nodes_out_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in_4 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}, flip dest_nodes_in_0 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} wire destNodesIn : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate destNodesIn.vc_free invalidate destNodesIn.credit_return invalidate destNodesIn.flit[0].bits.virt_channel_id invalidate destNodesIn.flit[0].bits.flow.egress_node_id invalidate destNodesIn.flit[0].bits.flow.egress_node invalidate destNodesIn.flit[0].bits.flow.ingress_node_id invalidate destNodesIn.flit[0].bits.flow.ingress_node invalidate destNodesIn.flit[0].bits.flow.vnet_id invalidate destNodesIn.flit[0].bits.payload invalidate destNodesIn.flit[0].bits.tail invalidate destNodesIn.flit[0].bits.head invalidate destNodesIn.flit[0].valid inst monitor of NoCMonitor_32 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.vc_free, destNodesIn.vc_free connect monitor.io.in.credit_return, destNodesIn.credit_return connect monitor.io.in.flit[0].bits.virt_channel_id, destNodesIn.flit[0].bits.virt_channel_id connect monitor.io.in.flit[0].bits.flow.egress_node_id, destNodesIn.flit[0].bits.flow.egress_node_id connect monitor.io.in.flit[0].bits.flow.egress_node, destNodesIn.flit[0].bits.flow.egress_node connect monitor.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn.flit[0].bits.flow.ingress_node_id connect monitor.io.in.flit[0].bits.flow.ingress_node, destNodesIn.flit[0].bits.flow.ingress_node connect monitor.io.in.flit[0].bits.flow.vnet_id, destNodesIn.flit[0].bits.flow.vnet_id connect monitor.io.in.flit[0].bits.payload, destNodesIn.flit[0].bits.payload connect monitor.io.in.flit[0].bits.tail, destNodesIn.flit[0].bits.tail connect monitor.io.in.flit[0].bits.head, destNodesIn.flit[0].bits.head connect monitor.io.in.flit[0].valid, destNodesIn.flit[0].valid wire destNodesIn_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate destNodesIn_1.vc_free invalidate destNodesIn_1.credit_return invalidate destNodesIn_1.flit[0].bits.virt_channel_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node_id invalidate destNodesIn_1.flit[0].bits.flow.egress_node invalidate destNodesIn_1.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_1.flit[0].bits.flow.ingress_node invalidate destNodesIn_1.flit[0].bits.flow.vnet_id invalidate destNodesIn_1.flit[0].bits.payload invalidate destNodesIn_1.flit[0].bits.tail invalidate destNodesIn_1.flit[0].bits.head invalidate destNodesIn_1.flit[0].valid inst monitor_1 of NoCMonitor_33 connect monitor_1.clock, clock connect monitor_1.reset, reset connect monitor_1.io.in.vc_free, destNodesIn_1.vc_free connect monitor_1.io.in.credit_return, destNodesIn_1.credit_return connect monitor_1.io.in.flit[0].bits.virt_channel_id, destNodesIn_1.flit[0].bits.virt_channel_id connect monitor_1.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_1.flit[0].bits.flow.egress_node_id connect monitor_1.io.in.flit[0].bits.flow.egress_node, destNodesIn_1.flit[0].bits.flow.egress_node connect monitor_1.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_1.flit[0].bits.flow.ingress_node_id connect monitor_1.io.in.flit[0].bits.flow.ingress_node, destNodesIn_1.flit[0].bits.flow.ingress_node connect monitor_1.io.in.flit[0].bits.flow.vnet_id, destNodesIn_1.flit[0].bits.flow.vnet_id connect monitor_1.io.in.flit[0].bits.payload, destNodesIn_1.flit[0].bits.payload connect monitor_1.io.in.flit[0].bits.tail, destNodesIn_1.flit[0].bits.tail connect monitor_1.io.in.flit[0].bits.head, destNodesIn_1.flit[0].bits.head connect monitor_1.io.in.flit[0].valid, destNodesIn_1.flit[0].valid wire destNodesIn_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate destNodesIn_2.vc_free invalidate destNodesIn_2.credit_return invalidate destNodesIn_2.flit[0].bits.virt_channel_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node_id invalidate destNodesIn_2.flit[0].bits.flow.egress_node invalidate destNodesIn_2.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_2.flit[0].bits.flow.ingress_node invalidate destNodesIn_2.flit[0].bits.flow.vnet_id invalidate destNodesIn_2.flit[0].bits.payload invalidate destNodesIn_2.flit[0].bits.tail invalidate destNodesIn_2.flit[0].bits.head invalidate destNodesIn_2.flit[0].valid inst monitor_2 of NoCMonitor_34 connect monitor_2.clock, clock connect monitor_2.reset, reset connect monitor_2.io.in.vc_free, destNodesIn_2.vc_free connect monitor_2.io.in.credit_return, destNodesIn_2.credit_return connect monitor_2.io.in.flit[0].bits.virt_channel_id, destNodesIn_2.flit[0].bits.virt_channel_id connect monitor_2.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_2.flit[0].bits.flow.egress_node_id connect monitor_2.io.in.flit[0].bits.flow.egress_node, destNodesIn_2.flit[0].bits.flow.egress_node connect monitor_2.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_2.flit[0].bits.flow.ingress_node_id connect monitor_2.io.in.flit[0].bits.flow.ingress_node, destNodesIn_2.flit[0].bits.flow.ingress_node connect monitor_2.io.in.flit[0].bits.flow.vnet_id, destNodesIn_2.flit[0].bits.flow.vnet_id connect monitor_2.io.in.flit[0].bits.payload, destNodesIn_2.flit[0].bits.payload connect monitor_2.io.in.flit[0].bits.tail, destNodesIn_2.flit[0].bits.tail connect monitor_2.io.in.flit[0].bits.head, destNodesIn_2.flit[0].bits.head connect monitor_2.io.in.flit[0].valid, destNodesIn_2.flit[0].valid wire destNodesIn_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate destNodesIn_3.vc_free invalidate destNodesIn_3.credit_return invalidate destNodesIn_3.flit[0].bits.virt_channel_id invalidate destNodesIn_3.flit[0].bits.flow.egress_node_id invalidate destNodesIn_3.flit[0].bits.flow.egress_node invalidate destNodesIn_3.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_3.flit[0].bits.flow.ingress_node invalidate destNodesIn_3.flit[0].bits.flow.vnet_id invalidate destNodesIn_3.flit[0].bits.payload invalidate destNodesIn_3.flit[0].bits.tail invalidate destNodesIn_3.flit[0].bits.head invalidate destNodesIn_3.flit[0].valid inst monitor_3 of NoCMonitor_35 connect monitor_3.clock, clock connect monitor_3.reset, reset connect monitor_3.io.in.vc_free, destNodesIn_3.vc_free connect monitor_3.io.in.credit_return, destNodesIn_3.credit_return connect monitor_3.io.in.flit[0].bits.virt_channel_id, destNodesIn_3.flit[0].bits.virt_channel_id connect monitor_3.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_3.flit[0].bits.flow.egress_node_id connect monitor_3.io.in.flit[0].bits.flow.egress_node, destNodesIn_3.flit[0].bits.flow.egress_node connect monitor_3.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_3.flit[0].bits.flow.ingress_node_id connect monitor_3.io.in.flit[0].bits.flow.ingress_node, destNodesIn_3.flit[0].bits.flow.ingress_node connect monitor_3.io.in.flit[0].bits.flow.vnet_id, destNodesIn_3.flit[0].bits.flow.vnet_id connect monitor_3.io.in.flit[0].bits.payload, destNodesIn_3.flit[0].bits.payload connect monitor_3.io.in.flit[0].bits.tail, destNodesIn_3.flit[0].bits.tail connect monitor_3.io.in.flit[0].bits.head, destNodesIn_3.flit[0].bits.head connect monitor_3.io.in.flit[0].valid, destNodesIn_3.flit[0].valid wire destNodesIn_4 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate destNodesIn_4.vc_free invalidate destNodesIn_4.credit_return invalidate destNodesIn_4.flit[0].bits.virt_channel_id invalidate destNodesIn_4.flit[0].bits.flow.egress_node_id invalidate destNodesIn_4.flit[0].bits.flow.egress_node invalidate destNodesIn_4.flit[0].bits.flow.ingress_node_id invalidate destNodesIn_4.flit[0].bits.flow.ingress_node invalidate destNodesIn_4.flit[0].bits.flow.vnet_id invalidate destNodesIn_4.flit[0].bits.payload invalidate destNodesIn_4.flit[0].bits.tail invalidate destNodesIn_4.flit[0].bits.head invalidate destNodesIn_4.flit[0].valid inst monitor_4 of NoCMonitor_36 connect monitor_4.clock, clock connect monitor_4.reset, reset connect monitor_4.io.in.vc_free, destNodesIn_4.vc_free connect monitor_4.io.in.credit_return, destNodesIn_4.credit_return connect monitor_4.io.in.flit[0].bits.virt_channel_id, destNodesIn_4.flit[0].bits.virt_channel_id connect monitor_4.io.in.flit[0].bits.flow.egress_node_id, destNodesIn_4.flit[0].bits.flow.egress_node_id connect monitor_4.io.in.flit[0].bits.flow.egress_node, destNodesIn_4.flit[0].bits.flow.egress_node connect monitor_4.io.in.flit[0].bits.flow.ingress_node_id, destNodesIn_4.flit[0].bits.flow.ingress_node_id connect monitor_4.io.in.flit[0].bits.flow.ingress_node, destNodesIn_4.flit[0].bits.flow.ingress_node connect monitor_4.io.in.flit[0].bits.flow.vnet_id, destNodesIn_4.flit[0].bits.flow.vnet_id connect monitor_4.io.in.flit[0].bits.payload, destNodesIn_4.flit[0].bits.payload connect monitor_4.io.in.flit[0].bits.tail, destNodesIn_4.flit[0].bits.tail connect monitor_4.io.in.flit[0].bits.head, destNodesIn_4.flit[0].bits.head connect monitor_4.io.in.flit[0].valid, destNodesIn_4.flit[0].valid wire sourceNodesOut : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate sourceNodesOut.vc_free invalidate sourceNodesOut.credit_return invalidate sourceNodesOut.flit[0].bits.virt_channel_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut.flit[0].bits.flow.egress_node invalidate sourceNodesOut.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut.flit[0].bits.flow.ingress_node invalidate sourceNodesOut.flit[0].bits.flow.vnet_id invalidate sourceNodesOut.flit[0].bits.payload invalidate sourceNodesOut.flit[0].bits.tail invalidate sourceNodesOut.flit[0].bits.head invalidate sourceNodesOut.flit[0].valid wire sourceNodesOut_1 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate sourceNodesOut_1.vc_free invalidate sourceNodesOut_1.credit_return invalidate sourceNodesOut_1.flit[0].bits.virt_channel_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.egress_node invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_1.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_1.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_1.flit[0].bits.payload invalidate sourceNodesOut_1.flit[0].bits.tail invalidate sourceNodesOut_1.flit[0].bits.head invalidate sourceNodesOut_1.flit[0].valid wire sourceNodesOut_2 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate sourceNodesOut_2.vc_free invalidate sourceNodesOut_2.credit_return invalidate sourceNodesOut_2.flit[0].bits.virt_channel_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.egress_node invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_2.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_2.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_2.flit[0].bits.payload invalidate sourceNodesOut_2.flit[0].bits.tail invalidate sourceNodesOut_2.flit[0].bits.head invalidate sourceNodesOut_2.flit[0].valid wire sourceNodesOut_3 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate sourceNodesOut_3.vc_free invalidate sourceNodesOut_3.credit_return invalidate sourceNodesOut_3.flit[0].bits.virt_channel_id invalidate sourceNodesOut_3.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_3.flit[0].bits.flow.egress_node invalidate sourceNodesOut_3.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_3.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_3.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_3.flit[0].bits.payload invalidate sourceNodesOut_3.flit[0].bits.tail invalidate sourceNodesOut_3.flit[0].bits.head invalidate sourceNodesOut_3.flit[0].valid wire sourceNodesOut_4 : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>} invalidate sourceNodesOut_4.vc_free invalidate sourceNodesOut_4.credit_return invalidate sourceNodesOut_4.flit[0].bits.virt_channel_id invalidate sourceNodesOut_4.flit[0].bits.flow.egress_node_id invalidate sourceNodesOut_4.flit[0].bits.flow.egress_node invalidate sourceNodesOut_4.flit[0].bits.flow.ingress_node_id invalidate sourceNodesOut_4.flit[0].bits.flow.ingress_node invalidate sourceNodesOut_4.flit[0].bits.flow.vnet_id invalidate sourceNodesOut_4.flit[0].bits.payload invalidate sourceNodesOut_4.flit[0].bits.tail invalidate sourceNodesOut_4.flit[0].bits.head invalidate sourceNodesOut_4.flit[0].valid wire debugNodeOut : { va_stall : UInt[5], sa_stall : UInt[5]} invalidate debugNodeOut.sa_stall[0] invalidate debugNodeOut.sa_stall[1] invalidate debugNodeOut.sa_stall[2] invalidate debugNodeOut.sa_stall[3] invalidate debugNodeOut.sa_stall[4] invalidate debugNodeOut.va_stall[0] invalidate debugNodeOut.va_stall[1] invalidate debugNodeOut.va_stall[2] invalidate debugNodeOut.va_stall[3] invalidate debugNodeOut.va_stall[4] connect destNodesIn, auto.dest_nodes_in_0 connect destNodesIn_1, auto.dest_nodes_in_1 connect destNodesIn_2, auto.dest_nodes_in_2 connect destNodesIn_3, auto.dest_nodes_in_3 connect destNodesIn_4, auto.dest_nodes_in_4 connect auto.source_nodes_out_0, sourceNodesOut connect auto.source_nodes_out_1, sourceNodesOut_1 connect auto.source_nodes_out_2, sourceNodesOut_2 connect auto.source_nodes_out_3, sourceNodesOut_3 connect auto.source_nodes_out_4, sourceNodesOut_4 connect auto.debug_out, debugNodeOut inst input_unit_0_from_5 of InputUnit_32 connect input_unit_0_from_5.clock, clock connect input_unit_0_from_5.reset, reset inst input_unit_1_from_17 of InputUnit_33 connect input_unit_1_from_17.clock, clock connect input_unit_1_from_17.reset, reset inst input_unit_2_from_20 of InputUnit_34 connect input_unit_2_from_20.clock, clock connect input_unit_2_from_20.reset, reset inst input_unit_3_from_22 of InputUnit_35 connect input_unit_3_from_22.clock, clock connect input_unit_3_from_22.reset, reset inst input_unit_4_from_25 of InputUnit_36 connect input_unit_4_from_25.clock, clock connect input_unit_4_from_25.reset, reset inst output_unit_0_to_5 of OutputUnit_32 connect output_unit_0_to_5.clock, clock connect output_unit_0_to_5.reset, reset inst output_unit_1_to_17 of OutputUnit_33 connect output_unit_1_to_17.clock, clock connect output_unit_1_to_17.reset, reset inst output_unit_2_to_20 of OutputUnit_34 connect output_unit_2_to_20.clock, clock connect output_unit_2_to_20.reset, reset inst output_unit_3_to_22 of OutputUnit_35 connect output_unit_3_to_22.clock, clock connect output_unit_3_to_22.reset, reset inst output_unit_4_to_25 of OutputUnit_36 connect output_unit_4_to_25.clock, clock connect output_unit_4_to_25.reset, reset inst switch of Switch_19 connect switch.clock, clock connect switch.reset, reset inst switch_allocator of SwitchAllocator_19 connect switch_allocator.clock, clock connect switch_allocator.reset, reset inst vc_allocator of RotatingSingleVCAllocator_19 connect vc_allocator.clock, clock connect vc_allocator.reset, reset inst route_computer of RouteComputer_19 connect route_computer.clock, clock connect route_computer.reset, reset node _fires_count_T = and(vc_allocator.io.req.`0`.ready, vc_allocator.io.req.`0`.valid) node _fires_count_T_1 = and(vc_allocator.io.req.`1`.ready, vc_allocator.io.req.`1`.valid) node _fires_count_T_2 = and(vc_allocator.io.req.`2`.ready, vc_allocator.io.req.`2`.valid) node _fires_count_T_3 = and(vc_allocator.io.req.`3`.ready, vc_allocator.io.req.`3`.valid) node _fires_count_T_4 = and(vc_allocator.io.req.`4`.ready, vc_allocator.io.req.`4`.valid) node _fires_count_T_5 = add(_fires_count_T, _fires_count_T_1) node _fires_count_T_6 = bits(_fires_count_T_5, 1, 0) node _fires_count_T_7 = add(_fires_count_T_3, _fires_count_T_4) node _fires_count_T_8 = bits(_fires_count_T_7, 1, 0) node _fires_count_T_9 = add(_fires_count_T_2, _fires_count_T_8) node _fires_count_T_10 = bits(_fires_count_T_9, 1, 0) node _fires_count_T_11 = add(_fires_count_T_6, _fires_count_T_10) node _fires_count_T_12 = bits(_fires_count_T_11, 2, 0) wire fires_count : UInt connect fires_count, _fires_count_T_12 connect input_unit_0_from_5.io.in, destNodesIn connect input_unit_1_from_17.io.in, destNodesIn_1 connect input_unit_2_from_20.io.in, destNodesIn_2 connect input_unit_3_from_22.io.in, destNodesIn_3 connect input_unit_4_from_25.io.in, destNodesIn_4 connect output_unit_0_to_5.io.out.vc_free, sourceNodesOut.vc_free connect output_unit_0_to_5.io.out.credit_return, sourceNodesOut.credit_return connect sourceNodesOut.flit, output_unit_0_to_5.io.out.flit connect output_unit_1_to_17.io.out.vc_free, sourceNodesOut_1.vc_free connect output_unit_1_to_17.io.out.credit_return, sourceNodesOut_1.credit_return connect sourceNodesOut_1.flit, output_unit_1_to_17.io.out.flit connect output_unit_2_to_20.io.out.vc_free, sourceNodesOut_2.vc_free connect output_unit_2_to_20.io.out.credit_return, sourceNodesOut_2.credit_return connect sourceNodesOut_2.flit, output_unit_2_to_20.io.out.flit connect output_unit_3_to_22.io.out.vc_free, sourceNodesOut_3.vc_free connect output_unit_3_to_22.io.out.credit_return, sourceNodesOut_3.credit_return connect sourceNodesOut_3.flit, output_unit_3_to_22.io.out.flit connect output_unit_4_to_25.io.out.vc_free, sourceNodesOut_4.vc_free connect output_unit_4_to_25.io.out.credit_return, sourceNodesOut_4.credit_return connect sourceNodesOut_4.flit, output_unit_4_to_25.io.out.flit connect route_computer.io.req.`0`, input_unit_0_from_5.io.router_req connect route_computer.io.req.`1`, input_unit_1_from_17.io.router_req connect route_computer.io.req.`2`, input_unit_2_from_20.io.router_req connect route_computer.io.req.`3`, input_unit_3_from_22.io.router_req connect route_computer.io.req.`4`, input_unit_4_from_25.io.router_req connect input_unit_0_from_5.io.router_resp, route_computer.io.resp.`0` connect input_unit_1_from_17.io.router_resp, route_computer.io.resp.`1` connect input_unit_2_from_20.io.router_resp, route_computer.io.resp.`2` connect input_unit_3_from_22.io.router_resp, route_computer.io.resp.`3` connect input_unit_4_from_25.io.router_resp, route_computer.io.resp.`4` connect vc_allocator.io.req.`0`, input_unit_0_from_5.io.vcalloc_req connect vc_allocator.io.req.`1`, input_unit_1_from_17.io.vcalloc_req connect vc_allocator.io.req.`2`, input_unit_2_from_20.io.vcalloc_req connect vc_allocator.io.req.`3`, input_unit_3_from_22.io.vcalloc_req connect vc_allocator.io.req.`4`, input_unit_4_from_25.io.vcalloc_req connect input_unit_0_from_5.io.vcalloc_resp, vc_allocator.io.resp.`0` connect input_unit_1_from_17.io.vcalloc_resp, vc_allocator.io.resp.`1` connect input_unit_2_from_20.io.vcalloc_resp, vc_allocator.io.resp.`2` connect input_unit_3_from_22.io.vcalloc_resp, vc_allocator.io.resp.`3` connect input_unit_4_from_25.io.vcalloc_resp, vc_allocator.io.resp.`4` connect output_unit_0_to_5.io.allocs, vc_allocator.io.out_allocs.`0` connect output_unit_1_to_17.io.allocs, vc_allocator.io.out_allocs.`1` connect output_unit_2_to_20.io.allocs, vc_allocator.io.out_allocs.`2` connect output_unit_3_to_22.io.allocs, vc_allocator.io.out_allocs.`3` connect output_unit_4_to_25.io.allocs, vc_allocator.io.out_allocs.`4` connect vc_allocator.io.channel_status.`0`[0].flow.egress_node_id, output_unit_0_to_5.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.egress_node, output_unit_0_to_5.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[0].flow.ingress_node, output_unit_0_to_5.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`0`[0].flow.vnet_id, output_unit_0_to_5.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`0`[0].occupied, output_unit_0_to_5.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`0`[1].flow.egress_node_id, output_unit_0_to_5.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.egress_node, output_unit_0_to_5.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[1].flow.ingress_node, output_unit_0_to_5.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`0`[1].flow.vnet_id, output_unit_0_to_5.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`0`[1].occupied, output_unit_0_to_5.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`0`[2].flow.egress_node_id, output_unit_0_to_5.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.egress_node, output_unit_0_to_5.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[2].flow.ingress_node, output_unit_0_to_5.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`0`[2].flow.vnet_id, output_unit_0_to_5.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`0`[2].occupied, output_unit_0_to_5.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`0`[3].flow.egress_node_id, output_unit_0_to_5.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.egress_node, output_unit_0_to_5.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[3].flow.ingress_node, output_unit_0_to_5.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`0`[3].flow.vnet_id, output_unit_0_to_5.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`0`[3].occupied, output_unit_0_to_5.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`0`[4].flow.egress_node_id, output_unit_0_to_5.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.egress_node, output_unit_0_to_5.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[4].flow.ingress_node, output_unit_0_to_5.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`0`[4].flow.vnet_id, output_unit_0_to_5.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`0`[4].occupied, output_unit_0_to_5.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`0`[5].flow.egress_node_id, output_unit_0_to_5.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.egress_node, output_unit_0_to_5.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[5].flow.ingress_node, output_unit_0_to_5.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`0`[5].flow.vnet_id, output_unit_0_to_5.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`0`[5].occupied, output_unit_0_to_5.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`0`[6].flow.egress_node_id, output_unit_0_to_5.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.egress_node, output_unit_0_to_5.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[6].flow.ingress_node, output_unit_0_to_5.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`0`[6].flow.vnet_id, output_unit_0_to_5.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`0`[6].occupied, output_unit_0_to_5.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`0`[7].flow.egress_node_id, output_unit_0_to_5.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.egress_node, output_unit_0_to_5.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node_id, output_unit_0_to_5.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`0`[7].flow.ingress_node, output_unit_0_to_5.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`0`[7].flow.vnet_id, output_unit_0_to_5.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`0`[7].occupied, output_unit_0_to_5.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`1`[0].flow.egress_node_id, output_unit_1_to_17.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.egress_node, output_unit_1_to_17.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node_id, output_unit_1_to_17.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[0].flow.ingress_node, output_unit_1_to_17.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`1`[0].flow.vnet_id, output_unit_1_to_17.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`1`[0].occupied, output_unit_1_to_17.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`1`[1].flow.egress_node_id, output_unit_1_to_17.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.egress_node, output_unit_1_to_17.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node_id, output_unit_1_to_17.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[1].flow.ingress_node, output_unit_1_to_17.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`1`[1].flow.vnet_id, output_unit_1_to_17.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`1`[1].occupied, output_unit_1_to_17.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`1`[2].flow.egress_node_id, output_unit_1_to_17.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.egress_node, output_unit_1_to_17.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node_id, output_unit_1_to_17.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[2].flow.ingress_node, output_unit_1_to_17.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`1`[2].flow.vnet_id, output_unit_1_to_17.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`1`[2].occupied, output_unit_1_to_17.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`1`[3].flow.egress_node_id, output_unit_1_to_17.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.egress_node, output_unit_1_to_17.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node_id, output_unit_1_to_17.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[3].flow.ingress_node, output_unit_1_to_17.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`1`[3].flow.vnet_id, output_unit_1_to_17.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`1`[3].occupied, output_unit_1_to_17.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`1`[4].flow.egress_node_id, output_unit_1_to_17.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.egress_node, output_unit_1_to_17.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node_id, output_unit_1_to_17.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[4].flow.ingress_node, output_unit_1_to_17.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`1`[4].flow.vnet_id, output_unit_1_to_17.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`1`[4].occupied, output_unit_1_to_17.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`1`[5].flow.egress_node_id, output_unit_1_to_17.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[5].flow.egress_node, output_unit_1_to_17.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node_id, output_unit_1_to_17.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[5].flow.ingress_node, output_unit_1_to_17.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`1`[5].flow.vnet_id, output_unit_1_to_17.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`1`[5].occupied, output_unit_1_to_17.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`1`[6].flow.egress_node_id, output_unit_1_to_17.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[6].flow.egress_node, output_unit_1_to_17.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node_id, output_unit_1_to_17.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[6].flow.ingress_node, output_unit_1_to_17.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`1`[6].flow.vnet_id, output_unit_1_to_17.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`1`[6].occupied, output_unit_1_to_17.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`1`[7].flow.egress_node_id, output_unit_1_to_17.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`1`[7].flow.egress_node, output_unit_1_to_17.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node_id, output_unit_1_to_17.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`1`[7].flow.ingress_node, output_unit_1_to_17.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`1`[7].flow.vnet_id, output_unit_1_to_17.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`1`[7].occupied, output_unit_1_to_17.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`2`[0].flow.egress_node_id, output_unit_2_to_20.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.egress_node, output_unit_2_to_20.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node_id, output_unit_2_to_20.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[0].flow.ingress_node, output_unit_2_to_20.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`2`[0].flow.vnet_id, output_unit_2_to_20.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`2`[0].occupied, output_unit_2_to_20.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`2`[1].flow.egress_node_id, output_unit_2_to_20.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.egress_node, output_unit_2_to_20.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node_id, output_unit_2_to_20.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[1].flow.ingress_node, output_unit_2_to_20.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`2`[1].flow.vnet_id, output_unit_2_to_20.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`2`[1].occupied, output_unit_2_to_20.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`2`[2].flow.egress_node_id, output_unit_2_to_20.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.egress_node, output_unit_2_to_20.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node_id, output_unit_2_to_20.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[2].flow.ingress_node, output_unit_2_to_20.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`2`[2].flow.vnet_id, output_unit_2_to_20.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`2`[2].occupied, output_unit_2_to_20.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`2`[3].flow.egress_node_id, output_unit_2_to_20.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.egress_node, output_unit_2_to_20.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node_id, output_unit_2_to_20.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[3].flow.ingress_node, output_unit_2_to_20.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`2`[3].flow.vnet_id, output_unit_2_to_20.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`2`[3].occupied, output_unit_2_to_20.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`2`[4].flow.egress_node_id, output_unit_2_to_20.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.egress_node, output_unit_2_to_20.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node_id, output_unit_2_to_20.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[4].flow.ingress_node, output_unit_2_to_20.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`2`[4].flow.vnet_id, output_unit_2_to_20.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`2`[4].occupied, output_unit_2_to_20.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`2`[5].flow.egress_node_id, output_unit_2_to_20.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[5].flow.egress_node, output_unit_2_to_20.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`2`[5].flow.ingress_node_id, output_unit_2_to_20.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[5].flow.ingress_node, output_unit_2_to_20.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`2`[5].flow.vnet_id, output_unit_2_to_20.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`2`[5].occupied, output_unit_2_to_20.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`2`[6].flow.egress_node_id, output_unit_2_to_20.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[6].flow.egress_node, output_unit_2_to_20.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`2`[6].flow.ingress_node_id, output_unit_2_to_20.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[6].flow.ingress_node, output_unit_2_to_20.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`2`[6].flow.vnet_id, output_unit_2_to_20.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`2`[6].occupied, output_unit_2_to_20.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`2`[7].flow.egress_node_id, output_unit_2_to_20.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`2`[7].flow.egress_node, output_unit_2_to_20.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`2`[7].flow.ingress_node_id, output_unit_2_to_20.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`2`[7].flow.ingress_node, output_unit_2_to_20.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`2`[7].flow.vnet_id, output_unit_2_to_20.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`2`[7].occupied, output_unit_2_to_20.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`3`[0].flow.egress_node_id, output_unit_3_to_22.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.egress_node, output_unit_3_to_22.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node_id, output_unit_3_to_22.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[0].flow.ingress_node, output_unit_3_to_22.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`3`[0].flow.vnet_id, output_unit_3_to_22.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`3`[0].occupied, output_unit_3_to_22.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`3`[1].flow.egress_node_id, output_unit_3_to_22.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[1].flow.egress_node, output_unit_3_to_22.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`3`[1].flow.ingress_node_id, output_unit_3_to_22.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[1].flow.ingress_node, output_unit_3_to_22.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`3`[1].flow.vnet_id, output_unit_3_to_22.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`3`[1].occupied, output_unit_3_to_22.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`3`[2].flow.egress_node_id, output_unit_3_to_22.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[2].flow.egress_node, output_unit_3_to_22.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`3`[2].flow.ingress_node_id, output_unit_3_to_22.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[2].flow.ingress_node, output_unit_3_to_22.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`3`[2].flow.vnet_id, output_unit_3_to_22.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`3`[2].occupied, output_unit_3_to_22.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`3`[3].flow.egress_node_id, output_unit_3_to_22.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[3].flow.egress_node, output_unit_3_to_22.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`3`[3].flow.ingress_node_id, output_unit_3_to_22.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[3].flow.ingress_node, output_unit_3_to_22.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`3`[3].flow.vnet_id, output_unit_3_to_22.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`3`[3].occupied, output_unit_3_to_22.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`3`[4].flow.egress_node_id, output_unit_3_to_22.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[4].flow.egress_node, output_unit_3_to_22.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`3`[4].flow.ingress_node_id, output_unit_3_to_22.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[4].flow.ingress_node, output_unit_3_to_22.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`3`[4].flow.vnet_id, output_unit_3_to_22.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`3`[4].occupied, output_unit_3_to_22.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`3`[5].flow.egress_node_id, output_unit_3_to_22.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[5].flow.egress_node, output_unit_3_to_22.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`3`[5].flow.ingress_node_id, output_unit_3_to_22.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[5].flow.ingress_node, output_unit_3_to_22.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`3`[5].flow.vnet_id, output_unit_3_to_22.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`3`[5].occupied, output_unit_3_to_22.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`3`[6].flow.egress_node_id, output_unit_3_to_22.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[6].flow.egress_node, output_unit_3_to_22.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`3`[6].flow.ingress_node_id, output_unit_3_to_22.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[6].flow.ingress_node, output_unit_3_to_22.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`3`[6].flow.vnet_id, output_unit_3_to_22.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`3`[6].occupied, output_unit_3_to_22.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`3`[7].flow.egress_node_id, output_unit_3_to_22.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`3`[7].flow.egress_node, output_unit_3_to_22.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`3`[7].flow.ingress_node_id, output_unit_3_to_22.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`3`[7].flow.ingress_node, output_unit_3_to_22.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`3`[7].flow.vnet_id, output_unit_3_to_22.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`3`[7].occupied, output_unit_3_to_22.io.channel_status[7].occupied connect vc_allocator.io.channel_status.`4`[0].flow.egress_node_id, output_unit_4_to_25.io.channel_status[0].flow.egress_node_id connect vc_allocator.io.channel_status.`4`[0].flow.egress_node, output_unit_4_to_25.io.channel_status[0].flow.egress_node connect vc_allocator.io.channel_status.`4`[0].flow.ingress_node_id, output_unit_4_to_25.io.channel_status[0].flow.ingress_node_id connect vc_allocator.io.channel_status.`4`[0].flow.ingress_node, output_unit_4_to_25.io.channel_status[0].flow.ingress_node connect vc_allocator.io.channel_status.`4`[0].flow.vnet_id, output_unit_4_to_25.io.channel_status[0].flow.vnet_id connect vc_allocator.io.channel_status.`4`[0].occupied, output_unit_4_to_25.io.channel_status[0].occupied connect vc_allocator.io.channel_status.`4`[1].flow.egress_node_id, output_unit_4_to_25.io.channel_status[1].flow.egress_node_id connect vc_allocator.io.channel_status.`4`[1].flow.egress_node, output_unit_4_to_25.io.channel_status[1].flow.egress_node connect vc_allocator.io.channel_status.`4`[1].flow.ingress_node_id, output_unit_4_to_25.io.channel_status[1].flow.ingress_node_id connect vc_allocator.io.channel_status.`4`[1].flow.ingress_node, output_unit_4_to_25.io.channel_status[1].flow.ingress_node connect vc_allocator.io.channel_status.`4`[1].flow.vnet_id, output_unit_4_to_25.io.channel_status[1].flow.vnet_id connect vc_allocator.io.channel_status.`4`[1].occupied, output_unit_4_to_25.io.channel_status[1].occupied connect vc_allocator.io.channel_status.`4`[2].flow.egress_node_id, output_unit_4_to_25.io.channel_status[2].flow.egress_node_id connect vc_allocator.io.channel_status.`4`[2].flow.egress_node, output_unit_4_to_25.io.channel_status[2].flow.egress_node connect vc_allocator.io.channel_status.`4`[2].flow.ingress_node_id, output_unit_4_to_25.io.channel_status[2].flow.ingress_node_id connect vc_allocator.io.channel_status.`4`[2].flow.ingress_node, output_unit_4_to_25.io.channel_status[2].flow.ingress_node connect vc_allocator.io.channel_status.`4`[2].flow.vnet_id, output_unit_4_to_25.io.channel_status[2].flow.vnet_id connect vc_allocator.io.channel_status.`4`[2].occupied, output_unit_4_to_25.io.channel_status[2].occupied connect vc_allocator.io.channel_status.`4`[3].flow.egress_node_id, output_unit_4_to_25.io.channel_status[3].flow.egress_node_id connect vc_allocator.io.channel_status.`4`[3].flow.egress_node, output_unit_4_to_25.io.channel_status[3].flow.egress_node connect vc_allocator.io.channel_status.`4`[3].flow.ingress_node_id, output_unit_4_to_25.io.channel_status[3].flow.ingress_node_id connect vc_allocator.io.channel_status.`4`[3].flow.ingress_node, output_unit_4_to_25.io.channel_status[3].flow.ingress_node connect vc_allocator.io.channel_status.`4`[3].flow.vnet_id, output_unit_4_to_25.io.channel_status[3].flow.vnet_id connect vc_allocator.io.channel_status.`4`[3].occupied, output_unit_4_to_25.io.channel_status[3].occupied connect vc_allocator.io.channel_status.`4`[4].flow.egress_node_id, output_unit_4_to_25.io.channel_status[4].flow.egress_node_id connect vc_allocator.io.channel_status.`4`[4].flow.egress_node, output_unit_4_to_25.io.channel_status[4].flow.egress_node connect vc_allocator.io.channel_status.`4`[4].flow.ingress_node_id, output_unit_4_to_25.io.channel_status[4].flow.ingress_node_id connect vc_allocator.io.channel_status.`4`[4].flow.ingress_node, output_unit_4_to_25.io.channel_status[4].flow.ingress_node connect vc_allocator.io.channel_status.`4`[4].flow.vnet_id, output_unit_4_to_25.io.channel_status[4].flow.vnet_id connect vc_allocator.io.channel_status.`4`[4].occupied, output_unit_4_to_25.io.channel_status[4].occupied connect vc_allocator.io.channel_status.`4`[5].flow.egress_node_id, output_unit_4_to_25.io.channel_status[5].flow.egress_node_id connect vc_allocator.io.channel_status.`4`[5].flow.egress_node, output_unit_4_to_25.io.channel_status[5].flow.egress_node connect vc_allocator.io.channel_status.`4`[5].flow.ingress_node_id, output_unit_4_to_25.io.channel_status[5].flow.ingress_node_id connect vc_allocator.io.channel_status.`4`[5].flow.ingress_node, output_unit_4_to_25.io.channel_status[5].flow.ingress_node connect vc_allocator.io.channel_status.`4`[5].flow.vnet_id, output_unit_4_to_25.io.channel_status[5].flow.vnet_id connect vc_allocator.io.channel_status.`4`[5].occupied, output_unit_4_to_25.io.channel_status[5].occupied connect vc_allocator.io.channel_status.`4`[6].flow.egress_node_id, output_unit_4_to_25.io.channel_status[6].flow.egress_node_id connect vc_allocator.io.channel_status.`4`[6].flow.egress_node, output_unit_4_to_25.io.channel_status[6].flow.egress_node connect vc_allocator.io.channel_status.`4`[6].flow.ingress_node_id, output_unit_4_to_25.io.channel_status[6].flow.ingress_node_id connect vc_allocator.io.channel_status.`4`[6].flow.ingress_node, output_unit_4_to_25.io.channel_status[6].flow.ingress_node connect vc_allocator.io.channel_status.`4`[6].flow.vnet_id, output_unit_4_to_25.io.channel_status[6].flow.vnet_id connect vc_allocator.io.channel_status.`4`[6].occupied, output_unit_4_to_25.io.channel_status[6].occupied connect vc_allocator.io.channel_status.`4`[7].flow.egress_node_id, output_unit_4_to_25.io.channel_status[7].flow.egress_node_id connect vc_allocator.io.channel_status.`4`[7].flow.egress_node, output_unit_4_to_25.io.channel_status[7].flow.egress_node connect vc_allocator.io.channel_status.`4`[7].flow.ingress_node_id, output_unit_4_to_25.io.channel_status[7].flow.ingress_node_id connect vc_allocator.io.channel_status.`4`[7].flow.ingress_node, output_unit_4_to_25.io.channel_status[7].flow.ingress_node connect vc_allocator.io.channel_status.`4`[7].flow.vnet_id, output_unit_4_to_25.io.channel_status[7].flow.vnet_id connect vc_allocator.io.channel_status.`4`[7].occupied, output_unit_4_to_25.io.channel_status[7].occupied connect input_unit_0_from_5.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_0_from_5.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_0_from_5.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_0_from_5.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_0_from_5.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4] connect input_unit_0_from_5.io.out_credit_available.`0`[5], output_unit_0_to_5.io.credit_available[5] connect input_unit_0_from_5.io.out_credit_available.`0`[6], output_unit_0_to_5.io.credit_available[6] connect input_unit_0_from_5.io.out_credit_available.`0`[7], output_unit_0_to_5.io.credit_available[7] connect input_unit_0_from_5.io.out_credit_available.`1`[0], output_unit_1_to_17.io.credit_available[0] connect input_unit_0_from_5.io.out_credit_available.`1`[1], output_unit_1_to_17.io.credit_available[1] connect input_unit_0_from_5.io.out_credit_available.`1`[2], output_unit_1_to_17.io.credit_available[2] connect input_unit_0_from_5.io.out_credit_available.`1`[3], output_unit_1_to_17.io.credit_available[3] connect input_unit_0_from_5.io.out_credit_available.`1`[4], output_unit_1_to_17.io.credit_available[4] connect input_unit_0_from_5.io.out_credit_available.`1`[5], output_unit_1_to_17.io.credit_available[5] connect input_unit_0_from_5.io.out_credit_available.`1`[6], output_unit_1_to_17.io.credit_available[6] connect input_unit_0_from_5.io.out_credit_available.`1`[7], output_unit_1_to_17.io.credit_available[7] connect input_unit_0_from_5.io.out_credit_available.`2`[0], output_unit_2_to_20.io.credit_available[0] connect input_unit_0_from_5.io.out_credit_available.`2`[1], output_unit_2_to_20.io.credit_available[1] connect input_unit_0_from_5.io.out_credit_available.`2`[2], output_unit_2_to_20.io.credit_available[2] connect input_unit_0_from_5.io.out_credit_available.`2`[3], output_unit_2_to_20.io.credit_available[3] connect input_unit_0_from_5.io.out_credit_available.`2`[4], output_unit_2_to_20.io.credit_available[4] connect input_unit_0_from_5.io.out_credit_available.`2`[5], output_unit_2_to_20.io.credit_available[5] connect input_unit_0_from_5.io.out_credit_available.`2`[6], output_unit_2_to_20.io.credit_available[6] connect input_unit_0_from_5.io.out_credit_available.`2`[7], output_unit_2_to_20.io.credit_available[7] connect input_unit_0_from_5.io.out_credit_available.`3`[0], output_unit_3_to_22.io.credit_available[0] connect input_unit_0_from_5.io.out_credit_available.`3`[1], output_unit_3_to_22.io.credit_available[1] connect input_unit_0_from_5.io.out_credit_available.`3`[2], output_unit_3_to_22.io.credit_available[2] connect input_unit_0_from_5.io.out_credit_available.`3`[3], output_unit_3_to_22.io.credit_available[3] connect input_unit_0_from_5.io.out_credit_available.`3`[4], output_unit_3_to_22.io.credit_available[4] connect input_unit_0_from_5.io.out_credit_available.`3`[5], output_unit_3_to_22.io.credit_available[5] connect input_unit_0_from_5.io.out_credit_available.`3`[6], output_unit_3_to_22.io.credit_available[6] connect input_unit_0_from_5.io.out_credit_available.`3`[7], output_unit_3_to_22.io.credit_available[7] connect input_unit_0_from_5.io.out_credit_available.`4`[0], output_unit_4_to_25.io.credit_available[0] connect input_unit_0_from_5.io.out_credit_available.`4`[1], output_unit_4_to_25.io.credit_available[1] connect input_unit_0_from_5.io.out_credit_available.`4`[2], output_unit_4_to_25.io.credit_available[2] connect input_unit_0_from_5.io.out_credit_available.`4`[3], output_unit_4_to_25.io.credit_available[3] connect input_unit_0_from_5.io.out_credit_available.`4`[4], output_unit_4_to_25.io.credit_available[4] connect input_unit_0_from_5.io.out_credit_available.`4`[5], output_unit_4_to_25.io.credit_available[5] connect input_unit_0_from_5.io.out_credit_available.`4`[6], output_unit_4_to_25.io.credit_available[6] connect input_unit_0_from_5.io.out_credit_available.`4`[7], output_unit_4_to_25.io.credit_available[7] connect input_unit_1_from_17.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_1_from_17.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_1_from_17.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_1_from_17.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_1_from_17.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4] connect input_unit_1_from_17.io.out_credit_available.`0`[5], output_unit_0_to_5.io.credit_available[5] connect input_unit_1_from_17.io.out_credit_available.`0`[6], output_unit_0_to_5.io.credit_available[6] connect input_unit_1_from_17.io.out_credit_available.`0`[7], output_unit_0_to_5.io.credit_available[7] connect input_unit_1_from_17.io.out_credit_available.`1`[0], output_unit_1_to_17.io.credit_available[0] connect input_unit_1_from_17.io.out_credit_available.`1`[1], output_unit_1_to_17.io.credit_available[1] connect input_unit_1_from_17.io.out_credit_available.`1`[2], output_unit_1_to_17.io.credit_available[2] connect input_unit_1_from_17.io.out_credit_available.`1`[3], output_unit_1_to_17.io.credit_available[3] connect input_unit_1_from_17.io.out_credit_available.`1`[4], output_unit_1_to_17.io.credit_available[4] connect input_unit_1_from_17.io.out_credit_available.`1`[5], output_unit_1_to_17.io.credit_available[5] connect input_unit_1_from_17.io.out_credit_available.`1`[6], output_unit_1_to_17.io.credit_available[6] connect input_unit_1_from_17.io.out_credit_available.`1`[7], output_unit_1_to_17.io.credit_available[7] connect input_unit_1_from_17.io.out_credit_available.`2`[0], output_unit_2_to_20.io.credit_available[0] connect input_unit_1_from_17.io.out_credit_available.`2`[1], output_unit_2_to_20.io.credit_available[1] connect input_unit_1_from_17.io.out_credit_available.`2`[2], output_unit_2_to_20.io.credit_available[2] connect input_unit_1_from_17.io.out_credit_available.`2`[3], output_unit_2_to_20.io.credit_available[3] connect input_unit_1_from_17.io.out_credit_available.`2`[4], output_unit_2_to_20.io.credit_available[4] connect input_unit_1_from_17.io.out_credit_available.`2`[5], output_unit_2_to_20.io.credit_available[5] connect input_unit_1_from_17.io.out_credit_available.`2`[6], output_unit_2_to_20.io.credit_available[6] connect input_unit_1_from_17.io.out_credit_available.`2`[7], output_unit_2_to_20.io.credit_available[7] connect input_unit_1_from_17.io.out_credit_available.`3`[0], output_unit_3_to_22.io.credit_available[0] connect input_unit_1_from_17.io.out_credit_available.`3`[1], output_unit_3_to_22.io.credit_available[1] connect input_unit_1_from_17.io.out_credit_available.`3`[2], output_unit_3_to_22.io.credit_available[2] connect input_unit_1_from_17.io.out_credit_available.`3`[3], output_unit_3_to_22.io.credit_available[3] connect input_unit_1_from_17.io.out_credit_available.`3`[4], output_unit_3_to_22.io.credit_available[4] connect input_unit_1_from_17.io.out_credit_available.`3`[5], output_unit_3_to_22.io.credit_available[5] connect input_unit_1_from_17.io.out_credit_available.`3`[6], output_unit_3_to_22.io.credit_available[6] connect input_unit_1_from_17.io.out_credit_available.`3`[7], output_unit_3_to_22.io.credit_available[7] connect input_unit_1_from_17.io.out_credit_available.`4`[0], output_unit_4_to_25.io.credit_available[0] connect input_unit_1_from_17.io.out_credit_available.`4`[1], output_unit_4_to_25.io.credit_available[1] connect input_unit_1_from_17.io.out_credit_available.`4`[2], output_unit_4_to_25.io.credit_available[2] connect input_unit_1_from_17.io.out_credit_available.`4`[3], output_unit_4_to_25.io.credit_available[3] connect input_unit_1_from_17.io.out_credit_available.`4`[4], output_unit_4_to_25.io.credit_available[4] connect input_unit_1_from_17.io.out_credit_available.`4`[5], output_unit_4_to_25.io.credit_available[5] connect input_unit_1_from_17.io.out_credit_available.`4`[6], output_unit_4_to_25.io.credit_available[6] connect input_unit_1_from_17.io.out_credit_available.`4`[7], output_unit_4_to_25.io.credit_available[7] connect input_unit_2_from_20.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_2_from_20.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_2_from_20.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_2_from_20.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_2_from_20.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4] connect input_unit_2_from_20.io.out_credit_available.`0`[5], output_unit_0_to_5.io.credit_available[5] connect input_unit_2_from_20.io.out_credit_available.`0`[6], output_unit_0_to_5.io.credit_available[6] connect input_unit_2_from_20.io.out_credit_available.`0`[7], output_unit_0_to_5.io.credit_available[7] connect input_unit_2_from_20.io.out_credit_available.`1`[0], output_unit_1_to_17.io.credit_available[0] connect input_unit_2_from_20.io.out_credit_available.`1`[1], output_unit_1_to_17.io.credit_available[1] connect input_unit_2_from_20.io.out_credit_available.`1`[2], output_unit_1_to_17.io.credit_available[2] connect input_unit_2_from_20.io.out_credit_available.`1`[3], output_unit_1_to_17.io.credit_available[3] connect input_unit_2_from_20.io.out_credit_available.`1`[4], output_unit_1_to_17.io.credit_available[4] connect input_unit_2_from_20.io.out_credit_available.`1`[5], output_unit_1_to_17.io.credit_available[5] connect input_unit_2_from_20.io.out_credit_available.`1`[6], output_unit_1_to_17.io.credit_available[6] connect input_unit_2_from_20.io.out_credit_available.`1`[7], output_unit_1_to_17.io.credit_available[7] connect input_unit_2_from_20.io.out_credit_available.`2`[0], output_unit_2_to_20.io.credit_available[0] connect input_unit_2_from_20.io.out_credit_available.`2`[1], output_unit_2_to_20.io.credit_available[1] connect input_unit_2_from_20.io.out_credit_available.`2`[2], output_unit_2_to_20.io.credit_available[2] connect input_unit_2_from_20.io.out_credit_available.`2`[3], output_unit_2_to_20.io.credit_available[3] connect input_unit_2_from_20.io.out_credit_available.`2`[4], output_unit_2_to_20.io.credit_available[4] connect input_unit_2_from_20.io.out_credit_available.`2`[5], output_unit_2_to_20.io.credit_available[5] connect input_unit_2_from_20.io.out_credit_available.`2`[6], output_unit_2_to_20.io.credit_available[6] connect input_unit_2_from_20.io.out_credit_available.`2`[7], output_unit_2_to_20.io.credit_available[7] connect input_unit_2_from_20.io.out_credit_available.`3`[0], output_unit_3_to_22.io.credit_available[0] connect input_unit_2_from_20.io.out_credit_available.`3`[1], output_unit_3_to_22.io.credit_available[1] connect input_unit_2_from_20.io.out_credit_available.`3`[2], output_unit_3_to_22.io.credit_available[2] connect input_unit_2_from_20.io.out_credit_available.`3`[3], output_unit_3_to_22.io.credit_available[3] connect input_unit_2_from_20.io.out_credit_available.`3`[4], output_unit_3_to_22.io.credit_available[4] connect input_unit_2_from_20.io.out_credit_available.`3`[5], output_unit_3_to_22.io.credit_available[5] connect input_unit_2_from_20.io.out_credit_available.`3`[6], output_unit_3_to_22.io.credit_available[6] connect input_unit_2_from_20.io.out_credit_available.`3`[7], output_unit_3_to_22.io.credit_available[7] connect input_unit_2_from_20.io.out_credit_available.`4`[0], output_unit_4_to_25.io.credit_available[0] connect input_unit_2_from_20.io.out_credit_available.`4`[1], output_unit_4_to_25.io.credit_available[1] connect input_unit_2_from_20.io.out_credit_available.`4`[2], output_unit_4_to_25.io.credit_available[2] connect input_unit_2_from_20.io.out_credit_available.`4`[3], output_unit_4_to_25.io.credit_available[3] connect input_unit_2_from_20.io.out_credit_available.`4`[4], output_unit_4_to_25.io.credit_available[4] connect input_unit_2_from_20.io.out_credit_available.`4`[5], output_unit_4_to_25.io.credit_available[5] connect input_unit_2_from_20.io.out_credit_available.`4`[6], output_unit_4_to_25.io.credit_available[6] connect input_unit_2_from_20.io.out_credit_available.`4`[7], output_unit_4_to_25.io.credit_available[7] connect input_unit_3_from_22.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_3_from_22.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_3_from_22.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_3_from_22.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_3_from_22.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4] connect input_unit_3_from_22.io.out_credit_available.`0`[5], output_unit_0_to_5.io.credit_available[5] connect input_unit_3_from_22.io.out_credit_available.`0`[6], output_unit_0_to_5.io.credit_available[6] connect input_unit_3_from_22.io.out_credit_available.`0`[7], output_unit_0_to_5.io.credit_available[7] connect input_unit_3_from_22.io.out_credit_available.`1`[0], output_unit_1_to_17.io.credit_available[0] connect input_unit_3_from_22.io.out_credit_available.`1`[1], output_unit_1_to_17.io.credit_available[1] connect input_unit_3_from_22.io.out_credit_available.`1`[2], output_unit_1_to_17.io.credit_available[2] connect input_unit_3_from_22.io.out_credit_available.`1`[3], output_unit_1_to_17.io.credit_available[3] connect input_unit_3_from_22.io.out_credit_available.`1`[4], output_unit_1_to_17.io.credit_available[4] connect input_unit_3_from_22.io.out_credit_available.`1`[5], output_unit_1_to_17.io.credit_available[5] connect input_unit_3_from_22.io.out_credit_available.`1`[6], output_unit_1_to_17.io.credit_available[6] connect input_unit_3_from_22.io.out_credit_available.`1`[7], output_unit_1_to_17.io.credit_available[7] connect input_unit_3_from_22.io.out_credit_available.`2`[0], output_unit_2_to_20.io.credit_available[0] connect input_unit_3_from_22.io.out_credit_available.`2`[1], output_unit_2_to_20.io.credit_available[1] connect input_unit_3_from_22.io.out_credit_available.`2`[2], output_unit_2_to_20.io.credit_available[2] connect input_unit_3_from_22.io.out_credit_available.`2`[3], output_unit_2_to_20.io.credit_available[3] connect input_unit_3_from_22.io.out_credit_available.`2`[4], output_unit_2_to_20.io.credit_available[4] connect input_unit_3_from_22.io.out_credit_available.`2`[5], output_unit_2_to_20.io.credit_available[5] connect input_unit_3_from_22.io.out_credit_available.`2`[6], output_unit_2_to_20.io.credit_available[6] connect input_unit_3_from_22.io.out_credit_available.`2`[7], output_unit_2_to_20.io.credit_available[7] connect input_unit_3_from_22.io.out_credit_available.`3`[0], output_unit_3_to_22.io.credit_available[0] connect input_unit_3_from_22.io.out_credit_available.`3`[1], output_unit_3_to_22.io.credit_available[1] connect input_unit_3_from_22.io.out_credit_available.`3`[2], output_unit_3_to_22.io.credit_available[2] connect input_unit_3_from_22.io.out_credit_available.`3`[3], output_unit_3_to_22.io.credit_available[3] connect input_unit_3_from_22.io.out_credit_available.`3`[4], output_unit_3_to_22.io.credit_available[4] connect input_unit_3_from_22.io.out_credit_available.`3`[5], output_unit_3_to_22.io.credit_available[5] connect input_unit_3_from_22.io.out_credit_available.`3`[6], output_unit_3_to_22.io.credit_available[6] connect input_unit_3_from_22.io.out_credit_available.`3`[7], output_unit_3_to_22.io.credit_available[7] connect input_unit_3_from_22.io.out_credit_available.`4`[0], output_unit_4_to_25.io.credit_available[0] connect input_unit_3_from_22.io.out_credit_available.`4`[1], output_unit_4_to_25.io.credit_available[1] connect input_unit_3_from_22.io.out_credit_available.`4`[2], output_unit_4_to_25.io.credit_available[2] connect input_unit_3_from_22.io.out_credit_available.`4`[3], output_unit_4_to_25.io.credit_available[3] connect input_unit_3_from_22.io.out_credit_available.`4`[4], output_unit_4_to_25.io.credit_available[4] connect input_unit_3_from_22.io.out_credit_available.`4`[5], output_unit_4_to_25.io.credit_available[5] connect input_unit_3_from_22.io.out_credit_available.`4`[6], output_unit_4_to_25.io.credit_available[6] connect input_unit_3_from_22.io.out_credit_available.`4`[7], output_unit_4_to_25.io.credit_available[7] connect input_unit_4_from_25.io.out_credit_available.`0`[0], output_unit_0_to_5.io.credit_available[0] connect input_unit_4_from_25.io.out_credit_available.`0`[1], output_unit_0_to_5.io.credit_available[1] connect input_unit_4_from_25.io.out_credit_available.`0`[2], output_unit_0_to_5.io.credit_available[2] connect input_unit_4_from_25.io.out_credit_available.`0`[3], output_unit_0_to_5.io.credit_available[3] connect input_unit_4_from_25.io.out_credit_available.`0`[4], output_unit_0_to_5.io.credit_available[4] connect input_unit_4_from_25.io.out_credit_available.`0`[5], output_unit_0_to_5.io.credit_available[5] connect input_unit_4_from_25.io.out_credit_available.`0`[6], output_unit_0_to_5.io.credit_available[6] connect input_unit_4_from_25.io.out_credit_available.`0`[7], output_unit_0_to_5.io.credit_available[7] connect input_unit_4_from_25.io.out_credit_available.`1`[0], output_unit_1_to_17.io.credit_available[0] connect input_unit_4_from_25.io.out_credit_available.`1`[1], output_unit_1_to_17.io.credit_available[1] connect input_unit_4_from_25.io.out_credit_available.`1`[2], output_unit_1_to_17.io.credit_available[2] connect input_unit_4_from_25.io.out_credit_available.`1`[3], output_unit_1_to_17.io.credit_available[3] connect input_unit_4_from_25.io.out_credit_available.`1`[4], output_unit_1_to_17.io.credit_available[4] connect input_unit_4_from_25.io.out_credit_available.`1`[5], output_unit_1_to_17.io.credit_available[5] connect input_unit_4_from_25.io.out_credit_available.`1`[6], output_unit_1_to_17.io.credit_available[6] connect input_unit_4_from_25.io.out_credit_available.`1`[7], output_unit_1_to_17.io.credit_available[7] connect input_unit_4_from_25.io.out_credit_available.`2`[0], output_unit_2_to_20.io.credit_available[0] connect input_unit_4_from_25.io.out_credit_available.`2`[1], output_unit_2_to_20.io.credit_available[1] connect input_unit_4_from_25.io.out_credit_available.`2`[2], output_unit_2_to_20.io.credit_available[2] connect input_unit_4_from_25.io.out_credit_available.`2`[3], output_unit_2_to_20.io.credit_available[3] connect input_unit_4_from_25.io.out_credit_available.`2`[4], output_unit_2_to_20.io.credit_available[4] connect input_unit_4_from_25.io.out_credit_available.`2`[5], output_unit_2_to_20.io.credit_available[5] connect input_unit_4_from_25.io.out_credit_available.`2`[6], output_unit_2_to_20.io.credit_available[6] connect input_unit_4_from_25.io.out_credit_available.`2`[7], output_unit_2_to_20.io.credit_available[7] connect input_unit_4_from_25.io.out_credit_available.`3`[0], output_unit_3_to_22.io.credit_available[0] connect input_unit_4_from_25.io.out_credit_available.`3`[1], output_unit_3_to_22.io.credit_available[1] connect input_unit_4_from_25.io.out_credit_available.`3`[2], output_unit_3_to_22.io.credit_available[2] connect input_unit_4_from_25.io.out_credit_available.`3`[3], output_unit_3_to_22.io.credit_available[3] connect input_unit_4_from_25.io.out_credit_available.`3`[4], output_unit_3_to_22.io.credit_available[4] connect input_unit_4_from_25.io.out_credit_available.`3`[5], output_unit_3_to_22.io.credit_available[5] connect input_unit_4_from_25.io.out_credit_available.`3`[6], output_unit_3_to_22.io.credit_available[6] connect input_unit_4_from_25.io.out_credit_available.`3`[7], output_unit_3_to_22.io.credit_available[7] connect input_unit_4_from_25.io.out_credit_available.`4`[0], output_unit_4_to_25.io.credit_available[0] connect input_unit_4_from_25.io.out_credit_available.`4`[1], output_unit_4_to_25.io.credit_available[1] connect input_unit_4_from_25.io.out_credit_available.`4`[2], output_unit_4_to_25.io.credit_available[2] connect input_unit_4_from_25.io.out_credit_available.`4`[3], output_unit_4_to_25.io.credit_available[3] connect input_unit_4_from_25.io.out_credit_available.`4`[4], output_unit_4_to_25.io.credit_available[4] connect input_unit_4_from_25.io.out_credit_available.`4`[5], output_unit_4_to_25.io.credit_available[5] connect input_unit_4_from_25.io.out_credit_available.`4`[6], output_unit_4_to_25.io.credit_available[6] connect input_unit_4_from_25.io.out_credit_available.`4`[7], output_unit_4_to_25.io.credit_available[7] connect switch_allocator.io.req.`0`[0], input_unit_0_from_5.io.salloc_req[0] connect switch_allocator.io.req.`1`[0], input_unit_1_from_17.io.salloc_req[0] connect switch_allocator.io.req.`2`[0], input_unit_2_from_20.io.salloc_req[0] connect switch_allocator.io.req.`3`[0], input_unit_3_from_22.io.salloc_req[0] connect switch_allocator.io.req.`4`[0], input_unit_4_from_25.io.salloc_req[0] connect output_unit_0_to_5.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`0`[0].tail connect output_unit_0_to_5.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`0`[0].alloc connect output_unit_0_to_5.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`0`[1].tail connect output_unit_0_to_5.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`0`[1].alloc connect output_unit_0_to_5.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`0`[2].tail connect output_unit_0_to_5.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`0`[2].alloc connect output_unit_0_to_5.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`0`[3].tail connect output_unit_0_to_5.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`0`[3].alloc connect output_unit_0_to_5.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`0`[4].tail connect output_unit_0_to_5.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`0`[4].alloc connect output_unit_0_to_5.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`0`[5].tail connect output_unit_0_to_5.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`0`[5].alloc connect output_unit_0_to_5.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`0`[6].tail connect output_unit_0_to_5.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`0`[6].alloc connect output_unit_0_to_5.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`0`[7].tail connect output_unit_0_to_5.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`0`[7].alloc connect output_unit_1_to_17.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`1`[0].tail connect output_unit_1_to_17.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`1`[0].alloc connect output_unit_1_to_17.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`1`[1].tail connect output_unit_1_to_17.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`1`[1].alloc connect output_unit_1_to_17.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`1`[2].tail connect output_unit_1_to_17.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`1`[2].alloc connect output_unit_1_to_17.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`1`[3].tail connect output_unit_1_to_17.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`1`[3].alloc connect output_unit_1_to_17.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`1`[4].tail connect output_unit_1_to_17.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`1`[4].alloc connect output_unit_1_to_17.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`1`[5].tail connect output_unit_1_to_17.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`1`[5].alloc connect output_unit_1_to_17.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`1`[6].tail connect output_unit_1_to_17.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`1`[6].alloc connect output_unit_1_to_17.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`1`[7].tail connect output_unit_1_to_17.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`1`[7].alloc connect output_unit_2_to_20.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`2`[0].tail connect output_unit_2_to_20.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`2`[0].alloc connect output_unit_2_to_20.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`2`[1].tail connect output_unit_2_to_20.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`2`[1].alloc connect output_unit_2_to_20.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`2`[2].tail connect output_unit_2_to_20.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`2`[2].alloc connect output_unit_2_to_20.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`2`[3].tail connect output_unit_2_to_20.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`2`[3].alloc connect output_unit_2_to_20.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`2`[4].tail connect output_unit_2_to_20.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`2`[4].alloc connect output_unit_2_to_20.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`2`[5].tail connect output_unit_2_to_20.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`2`[5].alloc connect output_unit_2_to_20.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`2`[6].tail connect output_unit_2_to_20.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`2`[6].alloc connect output_unit_2_to_20.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`2`[7].tail connect output_unit_2_to_20.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`2`[7].alloc connect output_unit_3_to_22.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`3`[0].tail connect output_unit_3_to_22.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`3`[0].alloc connect output_unit_3_to_22.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`3`[1].tail connect output_unit_3_to_22.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`3`[1].alloc connect output_unit_3_to_22.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`3`[2].tail connect output_unit_3_to_22.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`3`[2].alloc connect output_unit_3_to_22.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`3`[3].tail connect output_unit_3_to_22.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`3`[3].alloc connect output_unit_3_to_22.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`3`[4].tail connect output_unit_3_to_22.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`3`[4].alloc connect output_unit_3_to_22.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`3`[5].tail connect output_unit_3_to_22.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`3`[5].alloc connect output_unit_3_to_22.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`3`[6].tail connect output_unit_3_to_22.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`3`[6].alloc connect output_unit_3_to_22.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`3`[7].tail connect output_unit_3_to_22.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`3`[7].alloc connect output_unit_4_to_25.io.credit_alloc[0].tail, switch_allocator.io.credit_alloc.`4`[0].tail connect output_unit_4_to_25.io.credit_alloc[0].alloc, switch_allocator.io.credit_alloc.`4`[0].alloc connect output_unit_4_to_25.io.credit_alloc[1].tail, switch_allocator.io.credit_alloc.`4`[1].tail connect output_unit_4_to_25.io.credit_alloc[1].alloc, switch_allocator.io.credit_alloc.`4`[1].alloc connect output_unit_4_to_25.io.credit_alloc[2].tail, switch_allocator.io.credit_alloc.`4`[2].tail connect output_unit_4_to_25.io.credit_alloc[2].alloc, switch_allocator.io.credit_alloc.`4`[2].alloc connect output_unit_4_to_25.io.credit_alloc[3].tail, switch_allocator.io.credit_alloc.`4`[3].tail connect output_unit_4_to_25.io.credit_alloc[3].alloc, switch_allocator.io.credit_alloc.`4`[3].alloc connect output_unit_4_to_25.io.credit_alloc[4].tail, switch_allocator.io.credit_alloc.`4`[4].tail connect output_unit_4_to_25.io.credit_alloc[4].alloc, switch_allocator.io.credit_alloc.`4`[4].alloc connect output_unit_4_to_25.io.credit_alloc[5].tail, switch_allocator.io.credit_alloc.`4`[5].tail connect output_unit_4_to_25.io.credit_alloc[5].alloc, switch_allocator.io.credit_alloc.`4`[5].alloc connect output_unit_4_to_25.io.credit_alloc[6].tail, switch_allocator.io.credit_alloc.`4`[6].tail connect output_unit_4_to_25.io.credit_alloc[6].alloc, switch_allocator.io.credit_alloc.`4`[6].alloc connect output_unit_4_to_25.io.credit_alloc[7].tail, switch_allocator.io.credit_alloc.`4`[7].tail connect output_unit_4_to_25.io.credit_alloc[7].alloc, switch_allocator.io.credit_alloc.`4`[7].alloc connect switch.io.in.`0`[0], input_unit_0_from_5.io.out[0] connect switch.io.in.`1`[0], input_unit_1_from_17.io.out[0] connect switch.io.in.`2`[0], input_unit_2_from_20.io.out[0] connect switch.io.in.`3`[0], input_unit_3_from_22.io.out[0] connect switch.io.in.`4`[0], input_unit_4_from_25.io.out[0] connect output_unit_0_to_5.io.in, switch.io.out.`0` connect output_unit_1_to_17.io.in, switch.io.out.`1` connect output_unit_2_to_20.io.in, switch.io.out.`2` connect output_unit_3_to_22.io.in, switch.io.out.`3` connect output_unit_4_to_25.io.in, switch.io.out.`4` reg REG : { `4` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `3` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `2` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `1` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1], `0` : { `4` : UInt<1>[1], `3` : UInt<1>[1], `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[1]}[1]}, clock connect REG, switch_allocator.io.switch_sel connect switch.io.sel.`0`[0].`0`[0], REG.`0`[0].`0`[0] connect switch.io.sel.`0`[0].`1`[0], REG.`0`[0].`1`[0] connect switch.io.sel.`0`[0].`2`[0], REG.`0`[0].`2`[0] connect switch.io.sel.`0`[0].`3`[0], REG.`0`[0].`3`[0] connect switch.io.sel.`0`[0].`4`[0], REG.`0`[0].`4`[0] connect switch.io.sel.`1`[0].`0`[0], REG.`1`[0].`0`[0] connect switch.io.sel.`1`[0].`1`[0], REG.`1`[0].`1`[0] connect switch.io.sel.`1`[0].`2`[0], REG.`1`[0].`2`[0] connect switch.io.sel.`1`[0].`3`[0], REG.`1`[0].`3`[0] connect switch.io.sel.`1`[0].`4`[0], REG.`1`[0].`4`[0] connect switch.io.sel.`2`[0].`0`[0], REG.`2`[0].`0`[0] connect switch.io.sel.`2`[0].`1`[0], REG.`2`[0].`1`[0] connect switch.io.sel.`2`[0].`2`[0], REG.`2`[0].`2`[0] connect switch.io.sel.`2`[0].`3`[0], REG.`2`[0].`3`[0] connect switch.io.sel.`2`[0].`4`[0], REG.`2`[0].`4`[0] connect switch.io.sel.`3`[0].`0`[0], REG.`3`[0].`0`[0] connect switch.io.sel.`3`[0].`1`[0], REG.`3`[0].`1`[0] connect switch.io.sel.`3`[0].`2`[0], REG.`3`[0].`2`[0] connect switch.io.sel.`3`[0].`3`[0], REG.`3`[0].`3`[0] connect switch.io.sel.`3`[0].`4`[0], REG.`3`[0].`4`[0] connect switch.io.sel.`4`[0].`0`[0], REG.`4`[0].`0`[0] connect switch.io.sel.`4`[0].`1`[0], REG.`4`[0].`1`[0] connect switch.io.sel.`4`[0].`2`[0], REG.`4`[0].`2`[0] connect switch.io.sel.`4`[0].`3`[0], REG.`4`[0].`3`[0] connect switch.io.sel.`4`[0].`4`[0], REG.`4`[0].`4`[0] connect input_unit_0_from_5.io.block, UInt<1>(0h0) connect input_unit_1_from_17.io.block, UInt<1>(0h0) connect input_unit_2_from_20.io.block, UInt<1>(0h0) connect input_unit_3_from_22.io.block, UInt<1>(0h0) connect input_unit_4_from_25.io.block, UInt<1>(0h0) connect debugNodeOut.va_stall[0], input_unit_0_from_5.io.debug.va_stall connect debugNodeOut.va_stall[1], input_unit_1_from_17.io.debug.va_stall connect debugNodeOut.va_stall[2], input_unit_2_from_20.io.debug.va_stall connect debugNodeOut.va_stall[3], input_unit_3_from_22.io.debug.va_stall connect debugNodeOut.va_stall[4], input_unit_4_from_25.io.debug.va_stall connect debugNodeOut.sa_stall[0], input_unit_0_from_5.io.debug.sa_stall connect debugNodeOut.sa_stall[1], input_unit_1_from_17.io.debug.sa_stall connect debugNodeOut.sa_stall[2], input_unit_2_from_20.io.debug.sa_stall connect debugNodeOut.sa_stall[3], input_unit_3_from_22.io.debug.sa_stall connect debugNodeOut.sa_stall[4], input_unit_4_from_25.io.debug.sa_stall regreset debug_tsc : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_tsc_T = add(debug_tsc, UInt<1>(0h1)) node _debug_tsc_T_1 = tail(_debug_tsc_T, 1) connect debug_tsc, _debug_tsc_T_1 regreset debug_sample : UInt<64>, clock, reset, UInt<64>(0h0) node _debug_sample_T = add(debug_sample, UInt<1>(0h1)) node _debug_sample_T_1 = tail(_debug_sample_T, 1) connect debug_sample, _debug_sample_T_1 inst plusarg_reader of plusarg_reader_37 node _T = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_1 = tail(_T, 1) node _T_2 = eq(debug_sample, _T_1) when _T_2 : connect debug_sample, UInt<1>(0h0) regreset util_ctr : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T = add(util_ctr, destNodesIn.flit[0].valid) node _util_ctr_T_1 = tail(_util_ctr_T, 1) connect util_ctr, _util_ctr_T_1 node _fired_T = or(fired, destNodesIn.flit[0].valid) connect fired, _fired_T node _T_3 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_4 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_5 = tail(_T_4, 1) node _T_6 = eq(debug_sample, _T_5) node _T_7 = and(_T_3, _T_6) node _T_8 = and(_T_7, fired) when _T_8 : node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "nocsample %d 5 21 %d\n", debug_tsc, util_ctr) : printf connect fired, destNodesIn.flit[0].valid regreset util_ctr_1 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_2 = add(util_ctr_1, destNodesIn_1.flit[0].valid) node _util_ctr_T_3 = tail(_util_ctr_T_2, 1) connect util_ctr_1, _util_ctr_T_3 node _fired_T_1 = or(fired_1, destNodesIn_1.flit[0].valid) connect fired_1, _fired_T_1 node _T_11 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_12 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_13 = tail(_T_12, 1) node _T_14 = eq(debug_sample, _T_13) node _T_15 = and(_T_11, _T_14) node _T_16 = and(_T_15, fired_1) when _T_16 : node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "nocsample %d 17 21 %d\n", debug_tsc, util_ctr_1) : printf_1 connect fired_1, destNodesIn_1.flit[0].valid regreset util_ctr_2 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_4 = add(util_ctr_2, destNodesIn_2.flit[0].valid) node _util_ctr_T_5 = tail(_util_ctr_T_4, 1) connect util_ctr_2, _util_ctr_T_5 node _fired_T_2 = or(fired_2, destNodesIn_2.flit[0].valid) connect fired_2, _fired_T_2 node _T_19 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_20 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_21 = tail(_T_20, 1) node _T_22 = eq(debug_sample, _T_21) node _T_23 = and(_T_19, _T_22) node _T_24 = and(_T_23, fired_2) when _T_24 : node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "nocsample %d 20 21 %d\n", debug_tsc, util_ctr_2) : printf_2 connect fired_2, destNodesIn_2.flit[0].valid regreset util_ctr_3 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_3 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_6 = add(util_ctr_3, destNodesIn_3.flit[0].valid) node _util_ctr_T_7 = tail(_util_ctr_T_6, 1) connect util_ctr_3, _util_ctr_T_7 node _fired_T_3 = or(fired_3, destNodesIn_3.flit[0].valid) connect fired_3, _fired_T_3 node _T_27 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_28 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_29 = tail(_T_28, 1) node _T_30 = eq(debug_sample, _T_29) node _T_31 = and(_T_27, _T_30) node _T_32 = and(_T_31, fired_3) when _T_32 : node _T_33 = asUInt(reset) node _T_34 = eq(_T_33, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "nocsample %d 22 21 %d\n", debug_tsc, util_ctr_3) : printf_3 connect fired_3, destNodesIn_3.flit[0].valid regreset util_ctr_4 : UInt<64>, clock, reset, UInt<64>(0h0) regreset fired_4 : UInt<1>, clock, reset, UInt<1>(0h0) node _util_ctr_T_8 = add(util_ctr_4, destNodesIn_4.flit[0].valid) node _util_ctr_T_9 = tail(_util_ctr_T_8, 1) connect util_ctr_4, _util_ctr_T_9 node _fired_T_4 = or(fired_4, destNodesIn_4.flit[0].valid) connect fired_4, _fired_T_4 node _T_35 = neq(plusarg_reader.out, UInt<1>(0h0)) node _T_36 = sub(plusarg_reader.out, UInt<1>(0h1)) node _T_37 = tail(_T_36, 1) node _T_38 = eq(debug_sample, _T_37) node _T_39 = and(_T_35, _T_38) node _T_40 = and(_T_39, fired_4) when _T_40 : node _T_41 = asUInt(reset) node _T_42 = eq(_T_41, UInt<1>(0h0)) when _T_42 : printf(clock, UInt<1>(0h1), "nocsample %d 25 21 %d\n", debug_tsc, util_ctr_4) : printf_4 connect fired_4, destNodesIn_4.flit[0].valid
module Router_19( // @[Router.scala:89:25] input clock, // @[Router.scala:89:25] input reset, // @[Router.scala:89:25] output [2:0] auto_debug_out_va_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_va_stall_4, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_0, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_1, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_2, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_3, // @[LazyModuleImp.scala:107:25] output [2:0] auto_debug_out_sa_stall_4, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_4_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_4_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_4_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_4_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_4_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_4_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_4_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_4_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_4_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_4_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_4_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_4_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_3_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_3_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_2_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_1_vc_free, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] output auto_source_nodes_out_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] output [72:0] auto_source_nodes_out_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] output [4:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] output [1:0] auto_source_nodes_out_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] output [2:0] auto_source_nodes_out_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_credit_return, // @[LazyModuleImp.scala:107:25] input [7:0] auto_source_nodes_out_0_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_4_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_4_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_4_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_4_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_4_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_4_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_4_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_4_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_4_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_4_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_4_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_4_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_3_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_3_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_3_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_3_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_3_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_3_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_3_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_2_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_2_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_2_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_2_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_2_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_1_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_1_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_1_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_1_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_1_vc_free, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_valid, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_head, // @[LazyModuleImp.scala:107:25] input auto_dest_nodes_in_0_flit_0_bits_tail, // @[LazyModuleImp.scala:107:25] input [72:0] auto_dest_nodes_in_0_flit_0_bits_payload, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_flow_vnet_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_ingress_node_id, // @[LazyModuleImp.scala:107:25] input [4:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node, // @[LazyModuleImp.scala:107:25] input [1:0] auto_dest_nodes_in_0_flit_0_bits_flow_egress_node_id, // @[LazyModuleImp.scala:107:25] input [2:0] auto_dest_nodes_in_0_flit_0_bits_virt_channel_id, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_credit_return, // @[LazyModuleImp.scala:107:25] output [7:0] auto_dest_nodes_in_0_vc_free // @[LazyModuleImp.scala:107:25] ); wire [19:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire _route_computer_io_resp_4_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_3; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_4_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_4_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_3_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_4_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_1_7; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_2_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_4_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_0; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_1; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_2; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_3; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_4; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_5; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_6; // @[Router.scala:136:32] wire _route_computer_io_resp_1_vc_sel_0_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_4_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_3_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_2_7; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_1; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_2; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_3; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_4; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_5; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_6; // @[Router.scala:136:32] wire _route_computer_io_resp_0_vc_sel_1_7; // @[Router.scala:136:32] wire _vc_allocator_io_req_4_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_3_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_2_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_1_ready; // @[Router.scala:133:30] wire _vc_allocator_io_req_0_ready; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_4_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_4_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_3_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_4_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_2_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_4_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_0; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_1_vc_sel_0_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_4_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_3_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_2_7; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_1; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_2; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_3; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_4; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_5; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_6; // @[Router.scala:133:30] wire _vc_allocator_io_resp_0_vc_sel_1_7; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_4_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_3_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_2_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_1_7_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_0_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_1_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_2_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_3_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_4_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_5_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_6_alloc; // @[Router.scala:133:30] wire _vc_allocator_io_out_allocs_0_7_alloc; // @[Router.scala:133:30] wire _switch_allocator_io_req_4_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_3_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_2_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_1_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_req_0_0_ready; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_4_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_3_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_2_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_1_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_0_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_1_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_2_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_3_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_4_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_5_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_6_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_credit_alloc_0_7_alloc; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_4_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_3_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_2_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_1_0_0_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_4_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_3_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_2_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_1_0; // @[Router.scala:132:34] wire _switch_allocator_io_switch_sel_0_0_0_0; // @[Router.scala:132:34] wire _switch_io_out_4_0_valid; // @[Router.scala:131:24] wire _switch_io_out_4_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_4_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_4_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_4_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_4_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_4_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_4_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_4_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_4_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_3_0_valid; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_3_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_3_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_3_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_3_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_3_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_3_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_2_0_valid; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_2_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_2_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_2_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_2_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_2_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_1_0_valid; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_1_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_1_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_1_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_1_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_1_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _switch_io_out_0_0_valid; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_head; // @[Router.scala:131:24] wire _switch_io_out_0_0_bits_tail; // @[Router.scala:131:24] wire [72:0] _switch_io_out_0_0_bits_payload; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_flow_vnet_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_ingress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_ingress_node_id; // @[Router.scala:131:24] wire [4:0] _switch_io_out_0_0_bits_flow_egress_node; // @[Router.scala:131:24] wire [1:0] _switch_io_out_0_0_bits_flow_egress_node_id; // @[Router.scala:131:24] wire [2:0] _switch_io_out_0_0_bits_virt_channel_id; // @[Router.scala:131:24] wire _output_unit_4_to_25_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_4_to_25_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_3_to_22_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_2_to_20_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_1_to_17_io_channel_status_7_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_0; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_1; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_2; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_3; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_4; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_5; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_6; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_credit_available_7; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_0_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_1_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_2_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_3_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_4_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_5_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_6_occupied; // @[Router.scala:122:13] wire _output_unit_0_to_5_io_channel_status_7_occupied; // @[Router.scala:122:13] wire [2:0] _input_unit_4_from_25_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_4_from_25_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_4_from_25_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_4_from_25_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_4_from_25_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_4_from_25_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_4_from_25_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_4_from_25_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_4_from_25_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_4_from_25_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_4_from_25_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_4_from_25_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_4_from_25_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_4_from_25_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_22_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_22_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_22_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_22_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_22_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_22_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_3_from_22_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_3_from_22_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_22_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_22_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_22_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_3_from_22_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_3_from_22_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_3_from_22_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_20_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_20_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_2_from_20_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_2_from_20_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_2_from_20_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_2_from_20_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_vcalloc_req_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_1_from_17_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_1_from_17_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_1_from_17_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_1_from_17_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_router_req_bits_src_virt_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_router_req_bits_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_router_req_bits_flow_egress_node_id; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_vcalloc_req_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_4_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_4_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_4_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_4_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_4_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_4_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_4_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_4_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_3_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_2_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_1_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_0; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_1; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_2; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_3; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_4; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_5; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_6; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_vc_sel_0_7; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_salloc_req_0_bits_tail; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_valid; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_head; // @[Router.scala:112:13] wire _input_unit_0_from_5_io_out_0_bits_flit_tail; // @[Router.scala:112:13] wire [72:0] _input_unit_0_from_5_io_out_0_bits_flit_payload; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_vnet_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_ingress_node_id; // @[Router.scala:112:13] wire [4:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node; // @[Router.scala:112:13] wire [1:0] _input_unit_0_from_5_io_out_0_bits_flit_flow_egress_node_id; // @[Router.scala:112:13] wire [2:0] _input_unit_0_from_5_io_out_0_bits_out_virt_channel; // @[Router.scala:112:13] wire [2:0] fires_count = {1'h0, {1'h0, _vc_allocator_io_req_0_ready & _input_unit_0_from_5_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_1_ready & _input_unit_1_from_17_io_vcalloc_req_valid}} + {1'h0, {1'h0, _vc_allocator_io_req_2_ready & _input_unit_2_from_20_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_3_ready & _input_unit_3_from_22_io_vcalloc_req_valid} + {1'h0, _vc_allocator_io_req_4_ready & _input_unit_4_from_25_io_vcalloc_req_valid}}; // @[Decoupled.scala:51:35] reg REG_4_0_4_0; // @[Router.scala:178:14] reg REG_4_0_3_0; // @[Router.scala:178:14] reg REG_4_0_2_0; // @[Router.scala:178:14] reg REG_4_0_1_0; // @[Router.scala:178:14] reg REG_4_0_0_0; // @[Router.scala:178:14] reg REG_3_0_4_0; // @[Router.scala:178:14] reg REG_3_0_3_0; // @[Router.scala:178:14] reg REG_3_0_2_0; // @[Router.scala:178:14] reg REG_3_0_1_0; // @[Router.scala:178:14] reg REG_3_0_0_0; // @[Router.scala:178:14] reg REG_2_0_4_0; // @[Router.scala:178:14] reg REG_2_0_3_0; // @[Router.scala:178:14] reg REG_2_0_2_0; // @[Router.scala:178:14] reg REG_2_0_1_0; // @[Router.scala:178:14] reg REG_2_0_0_0; // @[Router.scala:178:14] reg REG_1_0_4_0; // @[Router.scala:178:14] reg REG_1_0_3_0; // @[Router.scala:178:14] reg REG_1_0_2_0; // @[Router.scala:178:14] reg REG_1_0_1_0; // @[Router.scala:178:14] reg REG_1_0_0_0; // @[Router.scala:178:14] reg REG_0_0_4_0; // @[Router.scala:178:14] reg REG_0_0_3_0; // @[Router.scala:178:14] reg REG_0_0_2_0; // @[Router.scala:178:14] reg REG_0_0_1_0; // @[Router.scala:178:14] reg REG_0_0_0_0; // @[Router.scala:178:14] reg [63:0] debug_tsc; // @[Router.scala:195:28] reg [63:0] debug_sample; // @[Router.scala:197:31] wire _GEN = debug_sample == {44'h0, _plusarg_reader_out - 20'h1}; // @[PlusArg.scala:80:11] reg [63:0] util_ctr; // @[Router.scala:203:29] reg fired; // @[Router.scala:204:26] wire _GEN_0 = (|_plusarg_reader_out) & _GEN; // @[PlusArg.scala:80:11] wire _GEN_1 = _GEN_0 & fired; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_1; // @[Router.scala:203:29] reg fired_1; // @[Router.scala:204:26] wire _GEN_2 = _GEN_0 & fired_1; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_2; // @[Router.scala:203:29] reg fired_2; // @[Router.scala:204:26] wire _GEN_3 = _GEN_0 & fired_2; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_3; // @[Router.scala:203:29] reg fired_3; // @[Router.scala:204:26] wire _GEN_4 = _GEN_0 & fired_3; // @[Router.scala:204:26, :207:{33,71}] reg [63:0] util_ctr_4; // @[Router.scala:203:29] reg fired_4; // @[Router.scala:204:26] wire _GEN_5 = _GEN_0 & fired_4; // @[Router.scala:204:26, :207:{33,71}]
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a29d128s7k1z4u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<7>, address : UInt<29>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)
module Repeater_TLBundleA_a29d128s7k1z4u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [3:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [6:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [28:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [15:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [127:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [3:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [6:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [28:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [15:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output [127:0] io_deq_bits_data, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [3:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [6:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [28:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [15:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [127:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [3:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [6:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [28:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [15:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [127:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [3:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [6:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [28:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [15:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [127:0] io_deq_bits_data_0; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [3:0] saved_size; // @[Repeater.scala:21:18] reg [6:0] saved_source; // @[Repeater.scala:21:18] reg [28:0] saved_address; // @[Repeater.scala:21:18] reg [15:0] saved_mask; // @[Repeater.scala:21:18] reg [127:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data_0 = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_79 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_119 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_79( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_119 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_40 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} inst input_buffer of InputBuffer_40 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) inst route_arbiter of Arbiter8_RouteComputerReq_40 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h16)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_9 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_9 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_10 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_10 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_11 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_11 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_12 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_12 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_13 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_13 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_14 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_14 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_15 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_15 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_16 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_16 : connect states[7].g, UInt<3>(0h2) node _T_17 = and(io.router_req.ready, io.router_req.valid) when _T_17 : node _T_18 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : node _T_21 = eq(_T_18, UInt<1>(0h0)) when _T_21 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_18, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_22 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_22 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_23 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_23 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_24 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_24 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_25 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_25 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_26 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_26 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_27 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_27 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_28 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_28 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.router_resp.vc_sel.`4` node _T_29 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_29 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.router_resp.vc_sel.`4` regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8] wire vcalloc_vals : UInt<1>[8] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0)) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35) node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_30 = and(io.router_req.ready, io.router_req.valid) when _T_30 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_31 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_32 = or(_T_31, vcalloc_vals[2]) node _T_33 = or(_T_32, vcalloc_vals[3]) node _T_34 = or(_T_33, vcalloc_vals[4]) node _T_35 = or(_T_34, vcalloc_vals[5]) node _T_36 = or(_T_35, vcalloc_vals[6]) node _T_37 = or(_T_36, vcalloc_vals[7]) when _T_37 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = bits(vcalloc_sel, 0, 0) node _mask_T_12 = bits(vcalloc_sel, 1, 1) node _mask_T_13 = bits(vcalloc_sel, 2, 2) node _mask_T_14 = bits(vcalloc_sel, 3, 3) node _mask_T_15 = bits(vcalloc_sel, 4, 4) node _mask_T_16 = bits(vcalloc_sel, 5, 5) node _mask_T_17 = bits(vcalloc_sel, 6, 6) node _mask_T_18 = bits(vcalloc_sel, 7, 7) node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0)) node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0)) node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0)) node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0)) node _mask_T_27 = or(_mask_T_19, _mask_T_20) node _mask_T_28 = or(_mask_T_27, _mask_T_21) node _mask_T_29 = or(_mask_T_28, _mask_T_22) node _mask_T_30 = or(_mask_T_29, _mask_T_23) node _mask_T_31 = or(_mask_T_30, _mask_T_24) node _mask_T_32 = or(_mask_T_31, _mask_T_25) node _mask_T_33 = or(_mask_T_32, _mask_T_26) wire _mask_WIRE : UInt<8> connect _mask_WIRE, _mask_T_33 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}} wire _io_vcalloc_req_bits_WIRE_1 : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100) node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8] node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172 connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187 connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192) node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193) node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194) node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202 connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217 connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219) node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232 connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234) node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235) node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236) node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237) node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238) node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247 connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8] node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249) node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250) node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251) node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252) node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253) node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254) node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268) node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269) node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277 connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292 connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294) node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295) node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300) wire _io_vcalloc_req_bits_WIRE_24 : UInt<1> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307 connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309) node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310) node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311) node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312) node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313) node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314) node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322 connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325) node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326) node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327) node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328) node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329) node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337 connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344) node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352 connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367 connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20 wire _io_vcalloc_req_bits_WIRE_29 : UInt<1>[8] node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369) node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370) node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371) node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375) wire _io_vcalloc_req_bits_WIRE_30 : UInt<1> connect _io_vcalloc_req_bits_WIRE_30, _io_vcalloc_req_bits_T_382 connect _io_vcalloc_req_bits_WIRE_29[0], _io_vcalloc_req_bits_WIRE_30 node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384) node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385) node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386) node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387) node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388) node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389) node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390) wire _io_vcalloc_req_bits_WIRE_31 : UInt<1> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397 connect _io_vcalloc_req_bits_WIRE_29[1], _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401) node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402) node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403) node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404) node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405) wire _io_vcalloc_req_bits_WIRE_32 : UInt<1> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412 connect _io_vcalloc_req_bits_WIRE_29[2], _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420) wire _io_vcalloc_req_bits_WIRE_33 : UInt<1> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_29[3], _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435) wire _io_vcalloc_req_bits_WIRE_34 : UInt<1> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442 connect _io_vcalloc_req_bits_WIRE_29[4], _io_vcalloc_req_bits_WIRE_34 node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444) node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445) node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446) node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447) node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450) wire _io_vcalloc_req_bits_WIRE_35 : UInt<1> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457 connect _io_vcalloc_req_bits_WIRE_29[5], _io_vcalloc_req_bits_WIRE_35 node _io_vcalloc_req_bits_T_458 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_459 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_460 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_461 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_462 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_463 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_464 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_465 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_466 = or(_io_vcalloc_req_bits_T_458, _io_vcalloc_req_bits_T_459) node _io_vcalloc_req_bits_T_467 = or(_io_vcalloc_req_bits_T_466, _io_vcalloc_req_bits_T_460) node _io_vcalloc_req_bits_T_468 = or(_io_vcalloc_req_bits_T_467, _io_vcalloc_req_bits_T_461) node _io_vcalloc_req_bits_T_469 = or(_io_vcalloc_req_bits_T_468, _io_vcalloc_req_bits_T_462) node _io_vcalloc_req_bits_T_470 = or(_io_vcalloc_req_bits_T_469, _io_vcalloc_req_bits_T_463) node _io_vcalloc_req_bits_T_471 = or(_io_vcalloc_req_bits_T_470, _io_vcalloc_req_bits_T_464) node _io_vcalloc_req_bits_T_472 = or(_io_vcalloc_req_bits_T_471, _io_vcalloc_req_bits_T_465) wire _io_vcalloc_req_bits_WIRE_36 : UInt<1> connect _io_vcalloc_req_bits_WIRE_36, _io_vcalloc_req_bits_T_472 connect _io_vcalloc_req_bits_WIRE_29[6], _io_vcalloc_req_bits_WIRE_36 node _io_vcalloc_req_bits_T_473 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_474 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_475 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_476 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_477 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_478 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_479 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_480 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`3`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_481 = or(_io_vcalloc_req_bits_T_473, _io_vcalloc_req_bits_T_474) node _io_vcalloc_req_bits_T_482 = or(_io_vcalloc_req_bits_T_481, _io_vcalloc_req_bits_T_475) node _io_vcalloc_req_bits_T_483 = or(_io_vcalloc_req_bits_T_482, _io_vcalloc_req_bits_T_476) node _io_vcalloc_req_bits_T_484 = or(_io_vcalloc_req_bits_T_483, _io_vcalloc_req_bits_T_477) node _io_vcalloc_req_bits_T_485 = or(_io_vcalloc_req_bits_T_484, _io_vcalloc_req_bits_T_478) node _io_vcalloc_req_bits_T_486 = or(_io_vcalloc_req_bits_T_485, _io_vcalloc_req_bits_T_479) node _io_vcalloc_req_bits_T_487 = or(_io_vcalloc_req_bits_T_486, _io_vcalloc_req_bits_T_480) wire _io_vcalloc_req_bits_WIRE_37 : UInt<1> connect _io_vcalloc_req_bits_WIRE_37, _io_vcalloc_req_bits_T_487 connect _io_vcalloc_req_bits_WIRE_29[7], _io_vcalloc_req_bits_WIRE_37 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_29 wire _io_vcalloc_req_bits_WIRE_38 : UInt<1>[8] node _io_vcalloc_req_bits_T_488 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_489 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_490 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_491 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_492 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_493 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_494 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_495 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_496 = or(_io_vcalloc_req_bits_T_488, _io_vcalloc_req_bits_T_489) node _io_vcalloc_req_bits_T_497 = or(_io_vcalloc_req_bits_T_496, _io_vcalloc_req_bits_T_490) node _io_vcalloc_req_bits_T_498 = or(_io_vcalloc_req_bits_T_497, _io_vcalloc_req_bits_T_491) node _io_vcalloc_req_bits_T_499 = or(_io_vcalloc_req_bits_T_498, _io_vcalloc_req_bits_T_492) node _io_vcalloc_req_bits_T_500 = or(_io_vcalloc_req_bits_T_499, _io_vcalloc_req_bits_T_493) node _io_vcalloc_req_bits_T_501 = or(_io_vcalloc_req_bits_T_500, _io_vcalloc_req_bits_T_494) node _io_vcalloc_req_bits_T_502 = or(_io_vcalloc_req_bits_T_501, _io_vcalloc_req_bits_T_495) wire _io_vcalloc_req_bits_WIRE_39 : UInt<1> connect _io_vcalloc_req_bits_WIRE_39, _io_vcalloc_req_bits_T_502 connect _io_vcalloc_req_bits_WIRE_38[0], _io_vcalloc_req_bits_WIRE_39 node _io_vcalloc_req_bits_T_503 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_504 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_505 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_506 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_507 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_508 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_509 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_510 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_511 = or(_io_vcalloc_req_bits_T_503, _io_vcalloc_req_bits_T_504) node _io_vcalloc_req_bits_T_512 = or(_io_vcalloc_req_bits_T_511, _io_vcalloc_req_bits_T_505) node _io_vcalloc_req_bits_T_513 = or(_io_vcalloc_req_bits_T_512, _io_vcalloc_req_bits_T_506) node _io_vcalloc_req_bits_T_514 = or(_io_vcalloc_req_bits_T_513, _io_vcalloc_req_bits_T_507) node _io_vcalloc_req_bits_T_515 = or(_io_vcalloc_req_bits_T_514, _io_vcalloc_req_bits_T_508) node _io_vcalloc_req_bits_T_516 = or(_io_vcalloc_req_bits_T_515, _io_vcalloc_req_bits_T_509) node _io_vcalloc_req_bits_T_517 = or(_io_vcalloc_req_bits_T_516, _io_vcalloc_req_bits_T_510) wire _io_vcalloc_req_bits_WIRE_40 : UInt<1> connect _io_vcalloc_req_bits_WIRE_40, _io_vcalloc_req_bits_T_517 connect _io_vcalloc_req_bits_WIRE_38[1], _io_vcalloc_req_bits_WIRE_40 node _io_vcalloc_req_bits_T_518 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_519 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_520 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_521 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_522 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_523 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_524 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_525 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_526 = or(_io_vcalloc_req_bits_T_518, _io_vcalloc_req_bits_T_519) node _io_vcalloc_req_bits_T_527 = or(_io_vcalloc_req_bits_T_526, _io_vcalloc_req_bits_T_520) node _io_vcalloc_req_bits_T_528 = or(_io_vcalloc_req_bits_T_527, _io_vcalloc_req_bits_T_521) node _io_vcalloc_req_bits_T_529 = or(_io_vcalloc_req_bits_T_528, _io_vcalloc_req_bits_T_522) node _io_vcalloc_req_bits_T_530 = or(_io_vcalloc_req_bits_T_529, _io_vcalloc_req_bits_T_523) node _io_vcalloc_req_bits_T_531 = or(_io_vcalloc_req_bits_T_530, _io_vcalloc_req_bits_T_524) node _io_vcalloc_req_bits_T_532 = or(_io_vcalloc_req_bits_T_531, _io_vcalloc_req_bits_T_525) wire _io_vcalloc_req_bits_WIRE_41 : UInt<1> connect _io_vcalloc_req_bits_WIRE_41, _io_vcalloc_req_bits_T_532 connect _io_vcalloc_req_bits_WIRE_38[2], _io_vcalloc_req_bits_WIRE_41 node _io_vcalloc_req_bits_T_533 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_534 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_535 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_536 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_537 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_538 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_539 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_540 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_541 = or(_io_vcalloc_req_bits_T_533, _io_vcalloc_req_bits_T_534) node _io_vcalloc_req_bits_T_542 = or(_io_vcalloc_req_bits_T_541, _io_vcalloc_req_bits_T_535) node _io_vcalloc_req_bits_T_543 = or(_io_vcalloc_req_bits_T_542, _io_vcalloc_req_bits_T_536) node _io_vcalloc_req_bits_T_544 = or(_io_vcalloc_req_bits_T_543, _io_vcalloc_req_bits_T_537) node _io_vcalloc_req_bits_T_545 = or(_io_vcalloc_req_bits_T_544, _io_vcalloc_req_bits_T_538) node _io_vcalloc_req_bits_T_546 = or(_io_vcalloc_req_bits_T_545, _io_vcalloc_req_bits_T_539) node _io_vcalloc_req_bits_T_547 = or(_io_vcalloc_req_bits_T_546, _io_vcalloc_req_bits_T_540) wire _io_vcalloc_req_bits_WIRE_42 : UInt<1> connect _io_vcalloc_req_bits_WIRE_42, _io_vcalloc_req_bits_T_547 connect _io_vcalloc_req_bits_WIRE_38[3], _io_vcalloc_req_bits_WIRE_42 node _io_vcalloc_req_bits_T_548 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_549 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_550 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_551 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_552 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_553 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_554 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_555 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_556 = or(_io_vcalloc_req_bits_T_548, _io_vcalloc_req_bits_T_549) node _io_vcalloc_req_bits_T_557 = or(_io_vcalloc_req_bits_T_556, _io_vcalloc_req_bits_T_550) node _io_vcalloc_req_bits_T_558 = or(_io_vcalloc_req_bits_T_557, _io_vcalloc_req_bits_T_551) node _io_vcalloc_req_bits_T_559 = or(_io_vcalloc_req_bits_T_558, _io_vcalloc_req_bits_T_552) node _io_vcalloc_req_bits_T_560 = or(_io_vcalloc_req_bits_T_559, _io_vcalloc_req_bits_T_553) node _io_vcalloc_req_bits_T_561 = or(_io_vcalloc_req_bits_T_560, _io_vcalloc_req_bits_T_554) node _io_vcalloc_req_bits_T_562 = or(_io_vcalloc_req_bits_T_561, _io_vcalloc_req_bits_T_555) wire _io_vcalloc_req_bits_WIRE_43 : UInt<1> connect _io_vcalloc_req_bits_WIRE_43, _io_vcalloc_req_bits_T_562 connect _io_vcalloc_req_bits_WIRE_38[4], _io_vcalloc_req_bits_WIRE_43 node _io_vcalloc_req_bits_T_563 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_564 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_565 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_566 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_567 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_568 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_569 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_570 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_571 = or(_io_vcalloc_req_bits_T_563, _io_vcalloc_req_bits_T_564) node _io_vcalloc_req_bits_T_572 = or(_io_vcalloc_req_bits_T_571, _io_vcalloc_req_bits_T_565) node _io_vcalloc_req_bits_T_573 = or(_io_vcalloc_req_bits_T_572, _io_vcalloc_req_bits_T_566) node _io_vcalloc_req_bits_T_574 = or(_io_vcalloc_req_bits_T_573, _io_vcalloc_req_bits_T_567) node _io_vcalloc_req_bits_T_575 = or(_io_vcalloc_req_bits_T_574, _io_vcalloc_req_bits_T_568) node _io_vcalloc_req_bits_T_576 = or(_io_vcalloc_req_bits_T_575, _io_vcalloc_req_bits_T_569) node _io_vcalloc_req_bits_T_577 = or(_io_vcalloc_req_bits_T_576, _io_vcalloc_req_bits_T_570) wire _io_vcalloc_req_bits_WIRE_44 : UInt<1> connect _io_vcalloc_req_bits_WIRE_44, _io_vcalloc_req_bits_T_577 connect _io_vcalloc_req_bits_WIRE_38[5], _io_vcalloc_req_bits_WIRE_44 node _io_vcalloc_req_bits_T_578 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_579 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_580 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_581 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_582 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_583 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_584 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_585 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_586 = or(_io_vcalloc_req_bits_T_578, _io_vcalloc_req_bits_T_579) node _io_vcalloc_req_bits_T_587 = or(_io_vcalloc_req_bits_T_586, _io_vcalloc_req_bits_T_580) node _io_vcalloc_req_bits_T_588 = or(_io_vcalloc_req_bits_T_587, _io_vcalloc_req_bits_T_581) node _io_vcalloc_req_bits_T_589 = or(_io_vcalloc_req_bits_T_588, _io_vcalloc_req_bits_T_582) node _io_vcalloc_req_bits_T_590 = or(_io_vcalloc_req_bits_T_589, _io_vcalloc_req_bits_T_583) node _io_vcalloc_req_bits_T_591 = or(_io_vcalloc_req_bits_T_590, _io_vcalloc_req_bits_T_584) node _io_vcalloc_req_bits_T_592 = or(_io_vcalloc_req_bits_T_591, _io_vcalloc_req_bits_T_585) wire _io_vcalloc_req_bits_WIRE_45 : UInt<1> connect _io_vcalloc_req_bits_WIRE_45, _io_vcalloc_req_bits_T_592 connect _io_vcalloc_req_bits_WIRE_38[6], _io_vcalloc_req_bits_WIRE_45 node _io_vcalloc_req_bits_T_593 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_594 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_595 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_596 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_597 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_598 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_599 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_600 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`4`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_601 = or(_io_vcalloc_req_bits_T_593, _io_vcalloc_req_bits_T_594) node _io_vcalloc_req_bits_T_602 = or(_io_vcalloc_req_bits_T_601, _io_vcalloc_req_bits_T_595) node _io_vcalloc_req_bits_T_603 = or(_io_vcalloc_req_bits_T_602, _io_vcalloc_req_bits_T_596) node _io_vcalloc_req_bits_T_604 = or(_io_vcalloc_req_bits_T_603, _io_vcalloc_req_bits_T_597) node _io_vcalloc_req_bits_T_605 = or(_io_vcalloc_req_bits_T_604, _io_vcalloc_req_bits_T_598) node _io_vcalloc_req_bits_T_606 = or(_io_vcalloc_req_bits_T_605, _io_vcalloc_req_bits_T_599) node _io_vcalloc_req_bits_T_607 = or(_io_vcalloc_req_bits_T_606, _io_vcalloc_req_bits_T_600) wire _io_vcalloc_req_bits_WIRE_46 : UInt<1> connect _io_vcalloc_req_bits_WIRE_46, _io_vcalloc_req_bits_T_607 connect _io_vcalloc_req_bits_WIRE_38[7], _io_vcalloc_req_bits_WIRE_46 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_38 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_608 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_609 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_610 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_611 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_612 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_613 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_614 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_615 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_616 = or(_io_vcalloc_req_bits_T_608, _io_vcalloc_req_bits_T_609) node _io_vcalloc_req_bits_T_617 = or(_io_vcalloc_req_bits_T_616, _io_vcalloc_req_bits_T_610) node _io_vcalloc_req_bits_T_618 = or(_io_vcalloc_req_bits_T_617, _io_vcalloc_req_bits_T_611) node _io_vcalloc_req_bits_T_619 = or(_io_vcalloc_req_bits_T_618, _io_vcalloc_req_bits_T_612) node _io_vcalloc_req_bits_T_620 = or(_io_vcalloc_req_bits_T_619, _io_vcalloc_req_bits_T_613) node _io_vcalloc_req_bits_T_621 = or(_io_vcalloc_req_bits_T_620, _io_vcalloc_req_bits_T_614) node _io_vcalloc_req_bits_T_622 = or(_io_vcalloc_req_bits_T_621, _io_vcalloc_req_bits_T_615) wire _io_vcalloc_req_bits_WIRE_47 : UInt<3> connect _io_vcalloc_req_bits_WIRE_47, _io_vcalloc_req_bits_T_622 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_47 wire _io_vcalloc_req_bits_WIRE_48 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_623 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_624 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_625 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_626 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_627 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_628 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_629 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_630 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_631 = or(_io_vcalloc_req_bits_T_623, _io_vcalloc_req_bits_T_624) node _io_vcalloc_req_bits_T_632 = or(_io_vcalloc_req_bits_T_631, _io_vcalloc_req_bits_T_625) node _io_vcalloc_req_bits_T_633 = or(_io_vcalloc_req_bits_T_632, _io_vcalloc_req_bits_T_626) node _io_vcalloc_req_bits_T_634 = or(_io_vcalloc_req_bits_T_633, _io_vcalloc_req_bits_T_627) node _io_vcalloc_req_bits_T_635 = or(_io_vcalloc_req_bits_T_634, _io_vcalloc_req_bits_T_628) node _io_vcalloc_req_bits_T_636 = or(_io_vcalloc_req_bits_T_635, _io_vcalloc_req_bits_T_629) node _io_vcalloc_req_bits_T_637 = or(_io_vcalloc_req_bits_T_636, _io_vcalloc_req_bits_T_630) wire _io_vcalloc_req_bits_WIRE_49 : UInt<2> connect _io_vcalloc_req_bits_WIRE_49, _io_vcalloc_req_bits_T_637 connect _io_vcalloc_req_bits_WIRE_48.egress_node_id, _io_vcalloc_req_bits_WIRE_49 node _io_vcalloc_req_bits_T_638 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_639 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_640 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_641 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_642 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_643 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_644 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_645 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_646 = or(_io_vcalloc_req_bits_T_638, _io_vcalloc_req_bits_T_639) node _io_vcalloc_req_bits_T_647 = or(_io_vcalloc_req_bits_T_646, _io_vcalloc_req_bits_T_640) node _io_vcalloc_req_bits_T_648 = or(_io_vcalloc_req_bits_T_647, _io_vcalloc_req_bits_T_641) node _io_vcalloc_req_bits_T_649 = or(_io_vcalloc_req_bits_T_648, _io_vcalloc_req_bits_T_642) node _io_vcalloc_req_bits_T_650 = or(_io_vcalloc_req_bits_T_649, _io_vcalloc_req_bits_T_643) node _io_vcalloc_req_bits_T_651 = or(_io_vcalloc_req_bits_T_650, _io_vcalloc_req_bits_T_644) node _io_vcalloc_req_bits_T_652 = or(_io_vcalloc_req_bits_T_651, _io_vcalloc_req_bits_T_645) wire _io_vcalloc_req_bits_WIRE_50 : UInt<5> connect _io_vcalloc_req_bits_WIRE_50, _io_vcalloc_req_bits_T_652 connect _io_vcalloc_req_bits_WIRE_48.egress_node, _io_vcalloc_req_bits_WIRE_50 node _io_vcalloc_req_bits_T_653 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_654 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_655 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_656 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_657 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_658 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_659 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_660 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_661 = or(_io_vcalloc_req_bits_T_653, _io_vcalloc_req_bits_T_654) node _io_vcalloc_req_bits_T_662 = or(_io_vcalloc_req_bits_T_661, _io_vcalloc_req_bits_T_655) node _io_vcalloc_req_bits_T_663 = or(_io_vcalloc_req_bits_T_662, _io_vcalloc_req_bits_T_656) node _io_vcalloc_req_bits_T_664 = or(_io_vcalloc_req_bits_T_663, _io_vcalloc_req_bits_T_657) node _io_vcalloc_req_bits_T_665 = or(_io_vcalloc_req_bits_T_664, _io_vcalloc_req_bits_T_658) node _io_vcalloc_req_bits_T_666 = or(_io_vcalloc_req_bits_T_665, _io_vcalloc_req_bits_T_659) node _io_vcalloc_req_bits_T_667 = or(_io_vcalloc_req_bits_T_666, _io_vcalloc_req_bits_T_660) wire _io_vcalloc_req_bits_WIRE_51 : UInt<2> connect _io_vcalloc_req_bits_WIRE_51, _io_vcalloc_req_bits_T_667 connect _io_vcalloc_req_bits_WIRE_48.ingress_node_id, _io_vcalloc_req_bits_WIRE_51 node _io_vcalloc_req_bits_T_668 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_669 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_670 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_671 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_672 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_673 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_674 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_675 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_676 = or(_io_vcalloc_req_bits_T_668, _io_vcalloc_req_bits_T_669) node _io_vcalloc_req_bits_T_677 = or(_io_vcalloc_req_bits_T_676, _io_vcalloc_req_bits_T_670) node _io_vcalloc_req_bits_T_678 = or(_io_vcalloc_req_bits_T_677, _io_vcalloc_req_bits_T_671) node _io_vcalloc_req_bits_T_679 = or(_io_vcalloc_req_bits_T_678, _io_vcalloc_req_bits_T_672) node _io_vcalloc_req_bits_T_680 = or(_io_vcalloc_req_bits_T_679, _io_vcalloc_req_bits_T_673) node _io_vcalloc_req_bits_T_681 = or(_io_vcalloc_req_bits_T_680, _io_vcalloc_req_bits_T_674) node _io_vcalloc_req_bits_T_682 = or(_io_vcalloc_req_bits_T_681, _io_vcalloc_req_bits_T_675) wire _io_vcalloc_req_bits_WIRE_52 : UInt<5> connect _io_vcalloc_req_bits_WIRE_52, _io_vcalloc_req_bits_T_682 connect _io_vcalloc_req_bits_WIRE_48.ingress_node, _io_vcalloc_req_bits_WIRE_52 node _io_vcalloc_req_bits_T_683 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_684 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_685 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_686 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_687 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_688 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_689 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_690 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_691 = or(_io_vcalloc_req_bits_T_683, _io_vcalloc_req_bits_T_684) node _io_vcalloc_req_bits_T_692 = or(_io_vcalloc_req_bits_T_691, _io_vcalloc_req_bits_T_685) node _io_vcalloc_req_bits_T_693 = or(_io_vcalloc_req_bits_T_692, _io_vcalloc_req_bits_T_686) node _io_vcalloc_req_bits_T_694 = or(_io_vcalloc_req_bits_T_693, _io_vcalloc_req_bits_T_687) node _io_vcalloc_req_bits_T_695 = or(_io_vcalloc_req_bits_T_694, _io_vcalloc_req_bits_T_688) node _io_vcalloc_req_bits_T_696 = or(_io_vcalloc_req_bits_T_695, _io_vcalloc_req_bits_T_689) node _io_vcalloc_req_bits_T_697 = or(_io_vcalloc_req_bits_T_696, _io_vcalloc_req_bits_T_690) wire _io_vcalloc_req_bits_WIRE_53 : UInt<3> connect _io_vcalloc_req_bits_WIRE_53, _io_vcalloc_req_bits_T_697 connect _io_vcalloc_req_bits_WIRE_48.vnet_id, _io_vcalloc_req_bits_WIRE_53 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_48 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4` connect vcalloc_reqs[0].flow, states[0].flow node _T_38 = bits(vcalloc_sel, 0, 0) node _T_39 = and(vcalloc_vals[0], _T_38) node _T_40 = and(_T_39, io.vcalloc_req.ready) when _T_40 : connect states[0].g, UInt<3>(0h3) node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4` connect vcalloc_reqs[1].flow, states[1].flow node _T_41 = bits(vcalloc_sel, 1, 1) node _T_42 = and(vcalloc_vals[1], _T_41) node _T_43 = and(_T_42, io.vcalloc_req.ready) when _T_43 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, states[2].vc_sel.`4` connect vcalloc_reqs[2].flow, states[2].flow node _T_44 = bits(vcalloc_sel, 2, 2) node _T_45 = and(vcalloc_vals[2], _T_44) node _T_46 = and(_T_45, io.vcalloc_req.ready) when _T_46 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].vc_sel.`3`, states[3].vc_sel.`3` connect vcalloc_reqs[3].vc_sel.`4`, states[3].vc_sel.`4` connect vcalloc_reqs[3].flow, states[3].flow node _T_47 = bits(vcalloc_sel, 3, 3) node _T_48 = and(vcalloc_vals[3], _T_47) node _T_49 = and(_T_48, io.vcalloc_req.ready) when _T_49 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].vc_sel.`3`, states[4].vc_sel.`3` connect vcalloc_reqs[4].vc_sel.`4`, states[4].vc_sel.`4` connect vcalloc_reqs[4].flow, states[4].flow node _T_50 = bits(vcalloc_sel, 4, 4) node _T_51 = and(vcalloc_vals[4], _T_50) node _T_52 = and(_T_51, io.vcalloc_req.ready) when _T_52 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].vc_sel.`3`, states[5].vc_sel.`3` connect vcalloc_reqs[5].vc_sel.`4`, states[5].vc_sel.`4` connect vcalloc_reqs[5].flow, states[5].flow node _T_53 = bits(vcalloc_sel, 5, 5) node _T_54 = and(vcalloc_vals[5], _T_53) node _T_55 = and(_T_54, io.vcalloc_req.ready) when _T_55 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].vc_sel.`3`, states[6].vc_sel.`3` connect vcalloc_reqs[6].vc_sel.`4`, states[6].vc_sel.`4` connect vcalloc_reqs[6].flow, states[6].flow node _T_56 = bits(vcalloc_sel, 6, 6) node _T_57 = and(vcalloc_vals[6], _T_56) node _T_58 = and(_T_57, io.vcalloc_req.ready) when _T_58 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].vc_sel.`3`, states[7].vc_sel.`3` connect vcalloc_reqs[7].vc_sel.`4`, states[7].vc_sel.`4` connect vcalloc_reqs[7].flow, states[7].flow node _T_59 = bits(vcalloc_sel, 7, 7) node _T_60 = and(vcalloc_vals[7], _T_59) node _T_61 = and(_T_60, io.vcalloc_req.ready) when _T_61 : connect states[7].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0) node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0) node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready) node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1) connect io.debug.va_stall, _io_debug_va_stall_T_15 node _T_62 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_62 : node _T_63 = bits(vcalloc_sel, 0, 0) when _T_63 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].g, UInt<3>(0h3) node _T_64 = eq(states[0].g, UInt<3>(0h2)) node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(_T_64, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_64, UInt<1>(0h1), "") : assert_3 node _T_68 = bits(vcalloc_sel, 1, 1) when _T_68 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].g, UInt<3>(0h3) node _T_69 = eq(states[1].g, UInt<3>(0h2)) node _T_70 = asUInt(reset) node _T_71 = eq(_T_70, UInt<1>(0h0)) when _T_71 : node _T_72 = eq(_T_69, UInt<1>(0h0)) when _T_72 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_69, UInt<1>(0h1), "") : assert_4 node _T_73 = bits(vcalloc_sel, 2, 2) when _T_73 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[2].g, UInt<3>(0h3) node _T_74 = eq(states[2].g, UInt<3>(0h2)) node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_T_74, UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_74, UInt<1>(0h1), "") : assert_5 node _T_78 = bits(vcalloc_sel, 3, 3) when _T_78 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[3].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[3].g, UInt<3>(0h3) node _T_79 = eq(states[3].g, UInt<3>(0h2)) node _T_80 = asUInt(reset) node _T_81 = eq(_T_80, UInt<1>(0h0)) when _T_81 : node _T_82 = eq(_T_79, UInt<1>(0h0)) when _T_82 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_79, UInt<1>(0h1), "") : assert_6 node _T_83 = bits(vcalloc_sel, 4, 4) when _T_83 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[4].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[4].g, UInt<3>(0h3) node _T_84 = eq(states[4].g, UInt<3>(0h2)) node _T_85 = asUInt(reset) node _T_86 = eq(_T_85, UInt<1>(0h0)) when _T_86 : node _T_87 = eq(_T_84, UInt<1>(0h0)) when _T_87 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_84, UInt<1>(0h1), "") : assert_7 node _T_88 = bits(vcalloc_sel, 5, 5) when _T_88 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[5].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[5].g, UInt<3>(0h3) node _T_89 = eq(states[5].g, UInt<3>(0h2)) node _T_90 = asUInt(reset) node _T_91 = eq(_T_90, UInt<1>(0h0)) when _T_91 : node _T_92 = eq(_T_89, UInt<1>(0h0)) when _T_92 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_89, UInt<1>(0h1), "") : assert_8 node _T_93 = bits(vcalloc_sel, 6, 6) when _T_93 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[6].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[6].g, UInt<3>(0h3) node _T_94 = eq(states[6].g, UInt<3>(0h2)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = bits(vcalloc_sel, 7, 7) when _T_98 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[7].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[7].g, UInt<3>(0h3) node _T_99 = eq(states[7].g, UInt<3>(0h2)) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 inst salloc_arb of SwitchArbiter_110 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_lo_lo = cat(states[0].vc_sel.`0`[1], states[0].vc_sel.`0`[0]) node credit_available_lo_hi = cat(states[0].vc_sel.`0`[3], states[0].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[0].vc_sel.`0`[5], states[0].vc_sel.`0`[4]) node credit_available_hi_hi = cat(states[0].vc_sel.`0`[7], states[0].vc_sel.`0`[6]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[0].vc_sel.`1`[1], states[0].vc_sel.`1`[0]) node credit_available_lo_hi_1 = cat(states[0].vc_sel.`1`[3], states[0].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[0].vc_sel.`1`[5], states[0].vc_sel.`1`[4]) node credit_available_hi_hi_1 = cat(states[0].vc_sel.`1`[7], states[0].vc_sel.`1`[6]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[0].vc_sel.`2`[1], states[0].vc_sel.`2`[0]) node credit_available_lo_hi_2 = cat(states[0].vc_sel.`2`[3], states[0].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[0].vc_sel.`2`[5], states[0].vc_sel.`2`[4]) node credit_available_hi_hi_2 = cat(states[0].vc_sel.`2`[7], states[0].vc_sel.`2`[6]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_lo_lo_3 = cat(states[0].vc_sel.`3`[1], states[0].vc_sel.`3`[0]) node credit_available_lo_hi_3 = cat(states[0].vc_sel.`3`[3], states[0].vc_sel.`3`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(states[0].vc_sel.`3`[5], states[0].vc_sel.`3`[4]) node credit_available_hi_hi_3 = cat(states[0].vc_sel.`3`[7], states[0].vc_sel.`3`[6]) node credit_available_hi_3 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_3 = cat(credit_available_hi_3, credit_available_lo_3) node credit_available_lo_lo_4 = cat(states[0].vc_sel.`4`[1], states[0].vc_sel.`4`[0]) node credit_available_lo_hi_4 = cat(states[0].vc_sel.`4`[3], states[0].vc_sel.`4`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(states[0].vc_sel.`4`[5], states[0].vc_sel.`4`[4]) node credit_available_hi_hi_4 = cat(states[0].vc_sel.`4`[7], states[0].vc_sel.`4`[6]) node credit_available_hi_4 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_4) node credit_available_lo_5 = cat(_credit_available_T_1, _credit_available_T) node credit_available_hi_hi_5 = cat(_credit_available_T_4, _credit_available_T_3) node credit_available_hi_5 = cat(credit_available_hi_hi_5, _credit_available_T_2) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_5) node credit_available_lo_lo_5 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_5 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_6 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_6 = cat(credit_available_hi_hi_6, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_6) node credit_available_lo_lo_6 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_6 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_7 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_7 = cat(credit_available_hi_hi_7, credit_available_hi_lo_6) node _credit_available_T_7 = cat(credit_available_hi_7, credit_available_lo_7) node credit_available_lo_lo_7 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_7 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_8 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_8 = cat(credit_available_hi_hi_8, credit_available_hi_lo_7) node _credit_available_T_8 = cat(credit_available_hi_8, credit_available_lo_8) node credit_available_lo_lo_8 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_8 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_9 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_9 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_9 = cat(credit_available_hi_hi_9, credit_available_hi_lo_8) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_9) node credit_available_lo_lo_9 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_9 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_10 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_10 = cat(credit_available_hi_hi_10, credit_available_hi_lo_9) node _credit_available_T_10 = cat(credit_available_hi_10, credit_available_lo_10) node credit_available_lo_11 = cat(_credit_available_T_7, _credit_available_T_6) node credit_available_hi_hi_11 = cat(_credit_available_T_10, _credit_available_T_9) node credit_available_hi_11 = cat(credit_available_hi_hi_11, _credit_available_T_8) node _credit_available_T_11 = cat(credit_available_hi_11, credit_available_lo_11) node _credit_available_T_12 = and(_credit_available_T_5, _credit_available_T_11) node credit_available = neq(_credit_available_T_12, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`0`[3], states[0].vc_sel.`0`[3] connect salloc_arb.io.in[0].bits.vc_sel.`0`[4], states[0].vc_sel.`0`[4] connect salloc_arb.io.in[0].bits.vc_sel.`0`[5], states[0].vc_sel.`0`[5] connect salloc_arb.io.in[0].bits.vc_sel.`0`[6], states[0].vc_sel.`0`[6] connect salloc_arb.io.in[0].bits.vc_sel.`0`[7], states[0].vc_sel.`0`[7] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2] connect salloc_arb.io.in[0].bits.vc_sel.`1`[3], states[0].vc_sel.`1`[3] connect salloc_arb.io.in[0].bits.vc_sel.`1`[4], states[0].vc_sel.`1`[4] connect salloc_arb.io.in[0].bits.vc_sel.`1`[5], states[0].vc_sel.`1`[5] connect salloc_arb.io.in[0].bits.vc_sel.`1`[6], states[0].vc_sel.`1`[6] connect salloc_arb.io.in[0].bits.vc_sel.`1`[7], states[0].vc_sel.`1`[7] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1] connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2] connect salloc_arb.io.in[0].bits.vc_sel.`2`[3], states[0].vc_sel.`2`[3] connect salloc_arb.io.in[0].bits.vc_sel.`2`[4], states[0].vc_sel.`2`[4] connect salloc_arb.io.in[0].bits.vc_sel.`2`[5], states[0].vc_sel.`2`[5] connect salloc_arb.io.in[0].bits.vc_sel.`2`[6], states[0].vc_sel.`2`[6] connect salloc_arb.io.in[0].bits.vc_sel.`2`[7], states[0].vc_sel.`2`[7] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1] connect salloc_arb.io.in[0].bits.vc_sel.`3`[2], states[0].vc_sel.`3`[2] connect salloc_arb.io.in[0].bits.vc_sel.`3`[3], states[0].vc_sel.`3`[3] connect salloc_arb.io.in[0].bits.vc_sel.`3`[4], states[0].vc_sel.`3`[4] connect salloc_arb.io.in[0].bits.vc_sel.`3`[5], states[0].vc_sel.`3`[5] connect salloc_arb.io.in[0].bits.vc_sel.`3`[6], states[0].vc_sel.`3`[6] connect salloc_arb.io.in[0].bits.vc_sel.`3`[7], states[0].vc_sel.`3`[7] connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0] connect salloc_arb.io.in[0].bits.vc_sel.`4`[1], states[0].vc_sel.`4`[1] connect salloc_arb.io.in[0].bits.vc_sel.`4`[2], states[0].vc_sel.`4`[2] connect salloc_arb.io.in[0].bits.vc_sel.`4`[3], states[0].vc_sel.`4`[3] connect salloc_arb.io.in[0].bits.vc_sel.`4`[4], states[0].vc_sel.`4`[4] connect salloc_arb.io.in[0].bits.vc_sel.`4`[5], states[0].vc_sel.`4`[5] connect salloc_arb.io.in[0].bits.vc_sel.`4`[6], states[0].vc_sel.`4`[6] connect salloc_arb.io.in[0].bits.vc_sel.`4`[7], states[0].vc_sel.`4`[7] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_103 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_104 = and(_T_103, input_buffer.io.deq[0].bits.tail) when _T_104 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_lo_lo_10 = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi_10 = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_hi_12 = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6]) node credit_available_hi_12 = cat(credit_available_hi_hi_12, credit_available_hi_lo_10) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_12) node credit_available_lo_lo_11 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_lo_hi_11 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4]) node credit_available_hi_hi_13 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6]) node credit_available_hi_13 = cat(credit_available_hi_hi_13, credit_available_hi_lo_11) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_13) node credit_available_lo_lo_12 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo_hi_12 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4]) node credit_available_hi_hi_14 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6]) node credit_available_hi_14 = cat(credit_available_hi_hi_14, credit_available_hi_lo_12) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_14) node credit_available_lo_lo_13 = cat(states[1].vc_sel.`3`[1], states[1].vc_sel.`3`[0]) node credit_available_lo_hi_13 = cat(states[1].vc_sel.`3`[3], states[1].vc_sel.`3`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(states[1].vc_sel.`3`[5], states[1].vc_sel.`3`[4]) node credit_available_hi_hi_15 = cat(states[1].vc_sel.`3`[7], states[1].vc_sel.`3`[6]) node credit_available_hi_15 = cat(credit_available_hi_hi_15, credit_available_hi_lo_13) node _credit_available_T_16 = cat(credit_available_hi_15, credit_available_lo_15) node credit_available_lo_lo_14 = cat(states[1].vc_sel.`4`[1], states[1].vc_sel.`4`[0]) node credit_available_lo_hi_14 = cat(states[1].vc_sel.`4`[3], states[1].vc_sel.`4`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[1].vc_sel.`4`[5], states[1].vc_sel.`4`[4]) node credit_available_hi_hi_16 = cat(states[1].vc_sel.`4`[7], states[1].vc_sel.`4`[6]) node credit_available_hi_16 = cat(credit_available_hi_hi_16, credit_available_hi_lo_14) node _credit_available_T_17 = cat(credit_available_hi_16, credit_available_lo_16) node credit_available_lo_17 = cat(_credit_available_T_14, _credit_available_T_13) node credit_available_hi_hi_17 = cat(_credit_available_T_17, _credit_available_T_16) node credit_available_hi_17 = cat(credit_available_hi_hi_17, _credit_available_T_15) node _credit_available_T_18 = cat(credit_available_hi_17, credit_available_lo_17) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_15 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_18 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_18 = cat(credit_available_hi_hi_18, credit_available_hi_lo_15) node _credit_available_T_19 = cat(credit_available_hi_18, credit_available_lo_18) node credit_available_lo_lo_16 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_16 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_19 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_19 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_19 = cat(credit_available_hi_hi_19, credit_available_hi_lo_16) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_19) node credit_available_lo_lo_17 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_17 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_20 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_20 = cat(credit_available_hi_hi_20, credit_available_hi_lo_17) node _credit_available_T_21 = cat(credit_available_hi_20, credit_available_lo_20) node credit_available_lo_lo_18 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_18 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_21 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_21 = cat(credit_available_hi_hi_21, credit_available_hi_lo_18) node _credit_available_T_22 = cat(credit_available_hi_21, credit_available_lo_21) node credit_available_lo_lo_19 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_19 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_22 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_22 = cat(credit_available_hi_hi_22, credit_available_hi_lo_19) node _credit_available_T_23 = cat(credit_available_hi_22, credit_available_lo_22) node credit_available_lo_23 = cat(_credit_available_T_20, _credit_available_T_19) node credit_available_hi_hi_23 = cat(_credit_available_T_23, _credit_available_T_22) node credit_available_hi_23 = cat(credit_available_hi_hi_23, _credit_available_T_21) node _credit_available_T_24 = cat(credit_available_hi_23, credit_available_lo_23) node _credit_available_T_25 = and(_credit_available_T_18, _credit_available_T_24) node credit_available_1 = neq(_credit_available_T_25, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6] connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5] connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6] connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[3], states[1].vc_sel.`3`[3] connect salloc_arb.io.in[1].bits.vc_sel.`3`[4], states[1].vc_sel.`3`[4] connect salloc_arb.io.in[1].bits.vc_sel.`3`[5], states[1].vc_sel.`3`[5] connect salloc_arb.io.in[1].bits.vc_sel.`3`[6], states[1].vc_sel.`3`[6] connect salloc_arb.io.in[1].bits.vc_sel.`3`[7], states[1].vc_sel.`3`[7] connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0] connect salloc_arb.io.in[1].bits.vc_sel.`4`[1], states[1].vc_sel.`4`[1] connect salloc_arb.io.in[1].bits.vc_sel.`4`[2], states[1].vc_sel.`4`[2] connect salloc_arb.io.in[1].bits.vc_sel.`4`[3], states[1].vc_sel.`4`[3] connect salloc_arb.io.in[1].bits.vc_sel.`4`[4], states[1].vc_sel.`4`[4] connect salloc_arb.io.in[1].bits.vc_sel.`4`[5], states[1].vc_sel.`4`[5] connect salloc_arb.io.in[1].bits.vc_sel.`4`[6], states[1].vc_sel.`4`[6] connect salloc_arb.io.in[1].bits.vc_sel.`4`[7], states[1].vc_sel.`4`[7] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_105 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_106 = and(_T_105, input_buffer.io.deq[1].bits.tail) when _T_106 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_20 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_20 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2]) node credit_available_lo_24 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_hi_24 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6]) node credit_available_hi_24 = cat(credit_available_hi_hi_24, credit_available_hi_lo_20) node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_24) node credit_available_lo_lo_21 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) node credit_available_lo_hi_21 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4]) node credit_available_hi_hi_25 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6]) node credit_available_hi_25 = cat(credit_available_hi_hi_25, credit_available_hi_lo_21) node _credit_available_T_27 = cat(credit_available_hi_25, credit_available_lo_25) node credit_available_lo_lo_22 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) node credit_available_lo_hi_22 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4]) node credit_available_hi_hi_26 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6]) node credit_available_hi_26 = cat(credit_available_hi_hi_26, credit_available_hi_lo_22) node _credit_available_T_28 = cat(credit_available_hi_26, credit_available_lo_26) node credit_available_lo_lo_23 = cat(states[2].vc_sel.`3`[1], states[2].vc_sel.`3`[0]) node credit_available_lo_hi_23 = cat(states[2].vc_sel.`3`[3], states[2].vc_sel.`3`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(states[2].vc_sel.`3`[5], states[2].vc_sel.`3`[4]) node credit_available_hi_hi_27 = cat(states[2].vc_sel.`3`[7], states[2].vc_sel.`3`[6]) node credit_available_hi_27 = cat(credit_available_hi_hi_27, credit_available_hi_lo_23) node _credit_available_T_29 = cat(credit_available_hi_27, credit_available_lo_27) node credit_available_lo_lo_24 = cat(states[2].vc_sel.`4`[1], states[2].vc_sel.`4`[0]) node credit_available_lo_hi_24 = cat(states[2].vc_sel.`4`[3], states[2].vc_sel.`4`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[2].vc_sel.`4`[5], states[2].vc_sel.`4`[4]) node credit_available_hi_hi_28 = cat(states[2].vc_sel.`4`[7], states[2].vc_sel.`4`[6]) node credit_available_hi_28 = cat(credit_available_hi_hi_28, credit_available_hi_lo_24) node _credit_available_T_30 = cat(credit_available_hi_28, credit_available_lo_28) node credit_available_lo_29 = cat(_credit_available_T_27, _credit_available_T_26) node credit_available_hi_hi_29 = cat(_credit_available_T_30, _credit_available_T_29) node credit_available_hi_29 = cat(credit_available_hi_hi_29, _credit_available_T_28) node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_29) node credit_available_lo_lo_25 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_25 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_30 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_30 = cat(credit_available_hi_hi_30, credit_available_hi_lo_25) node _credit_available_T_32 = cat(credit_available_hi_30, credit_available_lo_30) node credit_available_lo_lo_26 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_26 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_31 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_31 = cat(credit_available_hi_hi_31, credit_available_hi_lo_26) node _credit_available_T_33 = cat(credit_available_hi_31, credit_available_lo_31) node credit_available_lo_lo_27 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_27 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_32 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_32 = cat(credit_available_hi_hi_32, credit_available_hi_lo_27) node _credit_available_T_34 = cat(credit_available_hi_32, credit_available_lo_32) node credit_available_lo_lo_28 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_28 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_33 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_33 = cat(credit_available_hi_hi_33, credit_available_hi_lo_28) node _credit_available_T_35 = cat(credit_available_hi_33, credit_available_lo_33) node credit_available_lo_lo_29 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_29 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_34 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_34 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_34 = cat(credit_available_hi_hi_34, credit_available_hi_lo_29) node _credit_available_T_36 = cat(credit_available_hi_34, credit_available_lo_34) node credit_available_lo_35 = cat(_credit_available_T_33, _credit_available_T_32) node credit_available_hi_hi_35 = cat(_credit_available_T_36, _credit_available_T_35) node credit_available_hi_35 = cat(credit_available_hi_hi_35, _credit_available_T_34) node _credit_available_T_37 = cat(credit_available_hi_35, credit_available_lo_35) node _credit_available_T_38 = and(_credit_available_T_31, _credit_available_T_37) node credit_available_2 = neq(_credit_available_T_38, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[3], states[2].vc_sel.`3`[3] connect salloc_arb.io.in[2].bits.vc_sel.`3`[4], states[2].vc_sel.`3`[4] connect salloc_arb.io.in[2].bits.vc_sel.`3`[5], states[2].vc_sel.`3`[5] connect salloc_arb.io.in[2].bits.vc_sel.`3`[6], states[2].vc_sel.`3`[6] connect salloc_arb.io.in[2].bits.vc_sel.`3`[7], states[2].vc_sel.`3`[7] connect salloc_arb.io.in[2].bits.vc_sel.`4`[0], states[2].vc_sel.`4`[0] connect salloc_arb.io.in[2].bits.vc_sel.`4`[1], states[2].vc_sel.`4`[1] connect salloc_arb.io.in[2].bits.vc_sel.`4`[2], states[2].vc_sel.`4`[2] connect salloc_arb.io.in[2].bits.vc_sel.`4`[3], states[2].vc_sel.`4`[3] connect salloc_arb.io.in[2].bits.vc_sel.`4`[4], states[2].vc_sel.`4`[4] connect salloc_arb.io.in[2].bits.vc_sel.`4`[5], states[2].vc_sel.`4`[5] connect salloc_arb.io.in[2].bits.vc_sel.`4`[6], states[2].vc_sel.`4`[6] connect salloc_arb.io.in[2].bits.vc_sel.`4`[7], states[2].vc_sel.`4`[7] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_107 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_108 = and(_T_107, input_buffer.io.deq[2].bits.tail) when _T_108 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_30 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_30 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_hi_36 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6]) node credit_available_hi_36 = cat(credit_available_hi_hi_36, credit_available_hi_lo_30) node _credit_available_T_39 = cat(credit_available_hi_36, credit_available_lo_36) node credit_available_lo_lo_31 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_31 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4]) node credit_available_hi_hi_37 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6]) node credit_available_hi_37 = cat(credit_available_hi_hi_37, credit_available_hi_lo_31) node _credit_available_T_40 = cat(credit_available_hi_37, credit_available_lo_37) node credit_available_lo_lo_32 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_32 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4]) node credit_available_hi_hi_38 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6]) node credit_available_hi_38 = cat(credit_available_hi_hi_38, credit_available_hi_lo_32) node _credit_available_T_41 = cat(credit_available_hi_38, credit_available_lo_38) node credit_available_lo_lo_33 = cat(states[3].vc_sel.`3`[1], states[3].vc_sel.`3`[0]) node credit_available_lo_hi_33 = cat(states[3].vc_sel.`3`[3], states[3].vc_sel.`3`[2]) node credit_available_lo_39 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(states[3].vc_sel.`3`[5], states[3].vc_sel.`3`[4]) node credit_available_hi_hi_39 = cat(states[3].vc_sel.`3`[7], states[3].vc_sel.`3`[6]) node credit_available_hi_39 = cat(credit_available_hi_hi_39, credit_available_hi_lo_33) node _credit_available_T_42 = cat(credit_available_hi_39, credit_available_lo_39) node credit_available_lo_lo_34 = cat(states[3].vc_sel.`4`[1], states[3].vc_sel.`4`[0]) node credit_available_lo_hi_34 = cat(states[3].vc_sel.`4`[3], states[3].vc_sel.`4`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(states[3].vc_sel.`4`[5], states[3].vc_sel.`4`[4]) node credit_available_hi_hi_40 = cat(states[3].vc_sel.`4`[7], states[3].vc_sel.`4`[6]) node credit_available_hi_40 = cat(credit_available_hi_hi_40, credit_available_hi_lo_34) node _credit_available_T_43 = cat(credit_available_hi_40, credit_available_lo_40) node credit_available_lo_41 = cat(_credit_available_T_40, _credit_available_T_39) node credit_available_hi_hi_41 = cat(_credit_available_T_43, _credit_available_T_42) node credit_available_hi_41 = cat(credit_available_hi_hi_41, _credit_available_T_41) node _credit_available_T_44 = cat(credit_available_hi_41, credit_available_lo_41) node credit_available_lo_lo_35 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_35 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_42 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_42 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_42 = cat(credit_available_hi_hi_42, credit_available_hi_lo_35) node _credit_available_T_45 = cat(credit_available_hi_42, credit_available_lo_42) node credit_available_lo_lo_36 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_36 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_43 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_43 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_43 = cat(credit_available_hi_hi_43, credit_available_hi_lo_36) node _credit_available_T_46 = cat(credit_available_hi_43, credit_available_lo_43) node credit_available_lo_lo_37 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_37 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_44 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_44 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_44 = cat(credit_available_hi_hi_44, credit_available_hi_lo_37) node _credit_available_T_47 = cat(credit_available_hi_44, credit_available_lo_44) node credit_available_lo_lo_38 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_38 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_45 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_45 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_45 = cat(credit_available_hi_hi_45, credit_available_hi_lo_38) node _credit_available_T_48 = cat(credit_available_hi_45, credit_available_lo_45) node credit_available_lo_lo_39 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_39 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_46 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_46 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_46 = cat(credit_available_hi_hi_46, credit_available_hi_lo_39) node _credit_available_T_49 = cat(credit_available_hi_46, credit_available_lo_46) node credit_available_lo_47 = cat(_credit_available_T_46, _credit_available_T_45) node credit_available_hi_hi_47 = cat(_credit_available_T_49, _credit_available_T_48) node credit_available_hi_47 = cat(credit_available_hi_hi_47, _credit_available_T_47) node _credit_available_T_50 = cat(credit_available_hi_47, credit_available_lo_47) node _credit_available_T_51 = and(_credit_available_T_44, _credit_available_T_50) node credit_available_3 = neq(_credit_available_T_51, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_3) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.vc_sel.`3`[0], states[3].vc_sel.`3`[0] connect salloc_arb.io.in[3].bits.vc_sel.`3`[1], states[3].vc_sel.`3`[1] connect salloc_arb.io.in[3].bits.vc_sel.`3`[2], states[3].vc_sel.`3`[2] connect salloc_arb.io.in[3].bits.vc_sel.`3`[3], states[3].vc_sel.`3`[3] connect salloc_arb.io.in[3].bits.vc_sel.`3`[4], states[3].vc_sel.`3`[4] connect salloc_arb.io.in[3].bits.vc_sel.`3`[5], states[3].vc_sel.`3`[5] connect salloc_arb.io.in[3].bits.vc_sel.`3`[6], states[3].vc_sel.`3`[6] connect salloc_arb.io.in[3].bits.vc_sel.`3`[7], states[3].vc_sel.`3`[7] connect salloc_arb.io.in[3].bits.vc_sel.`4`[0], states[3].vc_sel.`4`[0] connect salloc_arb.io.in[3].bits.vc_sel.`4`[1], states[3].vc_sel.`4`[1] connect salloc_arb.io.in[3].bits.vc_sel.`4`[2], states[3].vc_sel.`4`[2] connect salloc_arb.io.in[3].bits.vc_sel.`4`[3], states[3].vc_sel.`4`[3] connect salloc_arb.io.in[3].bits.vc_sel.`4`[4], states[3].vc_sel.`4`[4] connect salloc_arb.io.in[3].bits.vc_sel.`4`[5], states[3].vc_sel.`4`[5] connect salloc_arb.io.in[3].bits.vc_sel.`4`[6], states[3].vc_sel.`4`[6] connect salloc_arb.io.in[3].bits.vc_sel.`4`[7], states[3].vc_sel.`4`[7] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_109 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_110 = and(_T_109, input_buffer.io.deq[3].bits.tail) when _T_110 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_40 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_40 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2]) node credit_available_lo_48 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_hi_48 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6]) node credit_available_hi_48 = cat(credit_available_hi_hi_48, credit_available_hi_lo_40) node _credit_available_T_52 = cat(credit_available_hi_48, credit_available_lo_48) node credit_available_lo_lo_41 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_41 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2]) node credit_available_lo_49 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4]) node credit_available_hi_hi_49 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6]) node credit_available_hi_49 = cat(credit_available_hi_hi_49, credit_available_hi_lo_41) node _credit_available_T_53 = cat(credit_available_hi_49, credit_available_lo_49) node credit_available_lo_lo_42 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_42 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2]) node credit_available_lo_50 = cat(credit_available_lo_hi_42, credit_available_lo_lo_42) node credit_available_hi_lo_42 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4]) node credit_available_hi_hi_50 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6]) node credit_available_hi_50 = cat(credit_available_hi_hi_50, credit_available_hi_lo_42) node _credit_available_T_54 = cat(credit_available_hi_50, credit_available_lo_50) node credit_available_lo_lo_43 = cat(states[4].vc_sel.`3`[1], states[4].vc_sel.`3`[0]) node credit_available_lo_hi_43 = cat(states[4].vc_sel.`3`[3], states[4].vc_sel.`3`[2]) node credit_available_lo_51 = cat(credit_available_lo_hi_43, credit_available_lo_lo_43) node credit_available_hi_lo_43 = cat(states[4].vc_sel.`3`[5], states[4].vc_sel.`3`[4]) node credit_available_hi_hi_51 = cat(states[4].vc_sel.`3`[7], states[4].vc_sel.`3`[6]) node credit_available_hi_51 = cat(credit_available_hi_hi_51, credit_available_hi_lo_43) node _credit_available_T_55 = cat(credit_available_hi_51, credit_available_lo_51) node credit_available_lo_lo_44 = cat(states[4].vc_sel.`4`[1], states[4].vc_sel.`4`[0]) node credit_available_lo_hi_44 = cat(states[4].vc_sel.`4`[3], states[4].vc_sel.`4`[2]) node credit_available_lo_52 = cat(credit_available_lo_hi_44, credit_available_lo_lo_44) node credit_available_hi_lo_44 = cat(states[4].vc_sel.`4`[5], states[4].vc_sel.`4`[4]) node credit_available_hi_hi_52 = cat(states[4].vc_sel.`4`[7], states[4].vc_sel.`4`[6]) node credit_available_hi_52 = cat(credit_available_hi_hi_52, credit_available_hi_lo_44) node _credit_available_T_56 = cat(credit_available_hi_52, credit_available_lo_52) node credit_available_lo_53 = cat(_credit_available_T_53, _credit_available_T_52) node credit_available_hi_hi_53 = cat(_credit_available_T_56, _credit_available_T_55) node credit_available_hi_53 = cat(credit_available_hi_hi_53, _credit_available_T_54) node _credit_available_T_57 = cat(credit_available_hi_53, credit_available_lo_53) node credit_available_lo_lo_45 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_45 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_54 = cat(credit_available_lo_hi_45, credit_available_lo_lo_45) node credit_available_hi_lo_45 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_54 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_54 = cat(credit_available_hi_hi_54, credit_available_hi_lo_45) node _credit_available_T_58 = cat(credit_available_hi_54, credit_available_lo_54) node credit_available_lo_lo_46 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_46 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_55 = cat(credit_available_lo_hi_46, credit_available_lo_lo_46) node credit_available_hi_lo_46 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_55 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_55 = cat(credit_available_hi_hi_55, credit_available_hi_lo_46) node _credit_available_T_59 = cat(credit_available_hi_55, credit_available_lo_55) node credit_available_lo_lo_47 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_47 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_56 = cat(credit_available_lo_hi_47, credit_available_lo_lo_47) node credit_available_hi_lo_47 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_56 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_56 = cat(credit_available_hi_hi_56, credit_available_hi_lo_47) node _credit_available_T_60 = cat(credit_available_hi_56, credit_available_lo_56) node credit_available_lo_lo_48 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_48 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_57 = cat(credit_available_lo_hi_48, credit_available_lo_lo_48) node credit_available_hi_lo_48 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_57 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_57 = cat(credit_available_hi_hi_57, credit_available_hi_lo_48) node _credit_available_T_61 = cat(credit_available_hi_57, credit_available_lo_57) node credit_available_lo_lo_49 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_49 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_58 = cat(credit_available_lo_hi_49, credit_available_lo_lo_49) node credit_available_hi_lo_49 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_58 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_58 = cat(credit_available_hi_hi_58, credit_available_hi_lo_49) node _credit_available_T_62 = cat(credit_available_hi_58, credit_available_lo_58) node credit_available_lo_59 = cat(_credit_available_T_59, _credit_available_T_58) node credit_available_hi_hi_59 = cat(_credit_available_T_62, _credit_available_T_61) node credit_available_hi_59 = cat(credit_available_hi_hi_59, _credit_available_T_60) node _credit_available_T_63 = cat(credit_available_hi_59, credit_available_lo_59) node _credit_available_T_64 = and(_credit_available_T_57, _credit_available_T_63) node credit_available_4 = neq(_credit_available_T_64, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_4) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.vc_sel.`3`[0], states[4].vc_sel.`3`[0] connect salloc_arb.io.in[4].bits.vc_sel.`3`[1], states[4].vc_sel.`3`[1] connect salloc_arb.io.in[4].bits.vc_sel.`3`[2], states[4].vc_sel.`3`[2] connect salloc_arb.io.in[4].bits.vc_sel.`3`[3], states[4].vc_sel.`3`[3] connect salloc_arb.io.in[4].bits.vc_sel.`3`[4], states[4].vc_sel.`3`[4] connect salloc_arb.io.in[4].bits.vc_sel.`3`[5], states[4].vc_sel.`3`[5] connect salloc_arb.io.in[4].bits.vc_sel.`3`[6], states[4].vc_sel.`3`[6] connect salloc_arb.io.in[4].bits.vc_sel.`3`[7], states[4].vc_sel.`3`[7] connect salloc_arb.io.in[4].bits.vc_sel.`4`[0], states[4].vc_sel.`4`[0] connect salloc_arb.io.in[4].bits.vc_sel.`4`[1], states[4].vc_sel.`4`[1] connect salloc_arb.io.in[4].bits.vc_sel.`4`[2], states[4].vc_sel.`4`[2] connect salloc_arb.io.in[4].bits.vc_sel.`4`[3], states[4].vc_sel.`4`[3] connect salloc_arb.io.in[4].bits.vc_sel.`4`[4], states[4].vc_sel.`4`[4] connect salloc_arb.io.in[4].bits.vc_sel.`4`[5], states[4].vc_sel.`4`[5] connect salloc_arb.io.in[4].bits.vc_sel.`4`[6], states[4].vc_sel.`4`[6] connect salloc_arb.io.in[4].bits.vc_sel.`4`[7], states[4].vc_sel.`4`[7] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_111 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_112 = and(_T_111, input_buffer.io.deq[4].bits.tail) when _T_112 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_50 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_50 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2]) node credit_available_lo_60 = cat(credit_available_lo_hi_50, credit_available_lo_lo_50) node credit_available_hi_lo_50 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_hi_60 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6]) node credit_available_hi_60 = cat(credit_available_hi_hi_60, credit_available_hi_lo_50) node _credit_available_T_65 = cat(credit_available_hi_60, credit_available_lo_60) node credit_available_lo_lo_51 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_51 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2]) node credit_available_lo_61 = cat(credit_available_lo_hi_51, credit_available_lo_lo_51) node credit_available_hi_lo_51 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4]) node credit_available_hi_hi_61 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6]) node credit_available_hi_61 = cat(credit_available_hi_hi_61, credit_available_hi_lo_51) node _credit_available_T_66 = cat(credit_available_hi_61, credit_available_lo_61) node credit_available_lo_lo_52 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_52 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2]) node credit_available_lo_62 = cat(credit_available_lo_hi_52, credit_available_lo_lo_52) node credit_available_hi_lo_52 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4]) node credit_available_hi_hi_62 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6]) node credit_available_hi_62 = cat(credit_available_hi_hi_62, credit_available_hi_lo_52) node _credit_available_T_67 = cat(credit_available_hi_62, credit_available_lo_62) node credit_available_lo_lo_53 = cat(states[5].vc_sel.`3`[1], states[5].vc_sel.`3`[0]) node credit_available_lo_hi_53 = cat(states[5].vc_sel.`3`[3], states[5].vc_sel.`3`[2]) node credit_available_lo_63 = cat(credit_available_lo_hi_53, credit_available_lo_lo_53) node credit_available_hi_lo_53 = cat(states[5].vc_sel.`3`[5], states[5].vc_sel.`3`[4]) node credit_available_hi_hi_63 = cat(states[5].vc_sel.`3`[7], states[5].vc_sel.`3`[6]) node credit_available_hi_63 = cat(credit_available_hi_hi_63, credit_available_hi_lo_53) node _credit_available_T_68 = cat(credit_available_hi_63, credit_available_lo_63) node credit_available_lo_lo_54 = cat(states[5].vc_sel.`4`[1], states[5].vc_sel.`4`[0]) node credit_available_lo_hi_54 = cat(states[5].vc_sel.`4`[3], states[5].vc_sel.`4`[2]) node credit_available_lo_64 = cat(credit_available_lo_hi_54, credit_available_lo_lo_54) node credit_available_hi_lo_54 = cat(states[5].vc_sel.`4`[5], states[5].vc_sel.`4`[4]) node credit_available_hi_hi_64 = cat(states[5].vc_sel.`4`[7], states[5].vc_sel.`4`[6]) node credit_available_hi_64 = cat(credit_available_hi_hi_64, credit_available_hi_lo_54) node _credit_available_T_69 = cat(credit_available_hi_64, credit_available_lo_64) node credit_available_lo_65 = cat(_credit_available_T_66, _credit_available_T_65) node credit_available_hi_hi_65 = cat(_credit_available_T_69, _credit_available_T_68) node credit_available_hi_65 = cat(credit_available_hi_hi_65, _credit_available_T_67) node _credit_available_T_70 = cat(credit_available_hi_65, credit_available_lo_65) node credit_available_lo_lo_55 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_55 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_66 = cat(credit_available_lo_hi_55, credit_available_lo_lo_55) node credit_available_hi_lo_55 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_66 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_66 = cat(credit_available_hi_hi_66, credit_available_hi_lo_55) node _credit_available_T_71 = cat(credit_available_hi_66, credit_available_lo_66) node credit_available_lo_lo_56 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_56 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_67 = cat(credit_available_lo_hi_56, credit_available_lo_lo_56) node credit_available_hi_lo_56 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_67 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_67 = cat(credit_available_hi_hi_67, credit_available_hi_lo_56) node _credit_available_T_72 = cat(credit_available_hi_67, credit_available_lo_67) node credit_available_lo_lo_57 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_57 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_68 = cat(credit_available_lo_hi_57, credit_available_lo_lo_57) node credit_available_hi_lo_57 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_68 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_68 = cat(credit_available_hi_hi_68, credit_available_hi_lo_57) node _credit_available_T_73 = cat(credit_available_hi_68, credit_available_lo_68) node credit_available_lo_lo_58 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_58 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_69 = cat(credit_available_lo_hi_58, credit_available_lo_lo_58) node credit_available_hi_lo_58 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_69 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_69 = cat(credit_available_hi_hi_69, credit_available_hi_lo_58) node _credit_available_T_74 = cat(credit_available_hi_69, credit_available_lo_69) node credit_available_lo_lo_59 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_59 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_70 = cat(credit_available_lo_hi_59, credit_available_lo_lo_59) node credit_available_hi_lo_59 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_70 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_70 = cat(credit_available_hi_hi_70, credit_available_hi_lo_59) node _credit_available_T_75 = cat(credit_available_hi_70, credit_available_lo_70) node credit_available_lo_71 = cat(_credit_available_T_72, _credit_available_T_71) node credit_available_hi_hi_71 = cat(_credit_available_T_75, _credit_available_T_74) node credit_available_hi_71 = cat(credit_available_hi_hi_71, _credit_available_T_73) node _credit_available_T_76 = cat(credit_available_hi_71, credit_available_lo_71) node _credit_available_T_77 = and(_credit_available_T_70, _credit_available_T_76) node credit_available_5 = neq(_credit_available_T_77, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_5) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.vc_sel.`3`[0], states[5].vc_sel.`3`[0] connect salloc_arb.io.in[5].bits.vc_sel.`3`[1], states[5].vc_sel.`3`[1] connect salloc_arb.io.in[5].bits.vc_sel.`3`[2], states[5].vc_sel.`3`[2] connect salloc_arb.io.in[5].bits.vc_sel.`3`[3], states[5].vc_sel.`3`[3] connect salloc_arb.io.in[5].bits.vc_sel.`3`[4], states[5].vc_sel.`3`[4] connect salloc_arb.io.in[5].bits.vc_sel.`3`[5], states[5].vc_sel.`3`[5] connect salloc_arb.io.in[5].bits.vc_sel.`3`[6], states[5].vc_sel.`3`[6] connect salloc_arb.io.in[5].bits.vc_sel.`3`[7], states[5].vc_sel.`3`[7] connect salloc_arb.io.in[5].bits.vc_sel.`4`[0], states[5].vc_sel.`4`[0] connect salloc_arb.io.in[5].bits.vc_sel.`4`[1], states[5].vc_sel.`4`[1] connect salloc_arb.io.in[5].bits.vc_sel.`4`[2], states[5].vc_sel.`4`[2] connect salloc_arb.io.in[5].bits.vc_sel.`4`[3], states[5].vc_sel.`4`[3] connect salloc_arb.io.in[5].bits.vc_sel.`4`[4], states[5].vc_sel.`4`[4] connect salloc_arb.io.in[5].bits.vc_sel.`4`[5], states[5].vc_sel.`4`[5] connect salloc_arb.io.in[5].bits.vc_sel.`4`[6], states[5].vc_sel.`4`[6] connect salloc_arb.io.in[5].bits.vc_sel.`4`[7], states[5].vc_sel.`4`[7] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_113 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_114 = and(_T_113, input_buffer.io.deq[5].bits.tail) when _T_114 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_60 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_60 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2]) node credit_available_lo_72 = cat(credit_available_lo_hi_60, credit_available_lo_lo_60) node credit_available_hi_lo_60 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4]) node credit_available_hi_hi_72 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6]) node credit_available_hi_72 = cat(credit_available_hi_hi_72, credit_available_hi_lo_60) node _credit_available_T_78 = cat(credit_available_hi_72, credit_available_lo_72) node credit_available_lo_lo_61 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_61 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2]) node credit_available_lo_73 = cat(credit_available_lo_hi_61, credit_available_lo_lo_61) node credit_available_hi_lo_61 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4]) node credit_available_hi_hi_73 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6]) node credit_available_hi_73 = cat(credit_available_hi_hi_73, credit_available_hi_lo_61) node _credit_available_T_79 = cat(credit_available_hi_73, credit_available_lo_73) node credit_available_lo_lo_62 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_62 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2]) node credit_available_lo_74 = cat(credit_available_lo_hi_62, credit_available_lo_lo_62) node credit_available_hi_lo_62 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4]) node credit_available_hi_hi_74 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6]) node credit_available_hi_74 = cat(credit_available_hi_hi_74, credit_available_hi_lo_62) node _credit_available_T_80 = cat(credit_available_hi_74, credit_available_lo_74) node credit_available_lo_lo_63 = cat(states[6].vc_sel.`3`[1], states[6].vc_sel.`3`[0]) node credit_available_lo_hi_63 = cat(states[6].vc_sel.`3`[3], states[6].vc_sel.`3`[2]) node credit_available_lo_75 = cat(credit_available_lo_hi_63, credit_available_lo_lo_63) node credit_available_hi_lo_63 = cat(states[6].vc_sel.`3`[5], states[6].vc_sel.`3`[4]) node credit_available_hi_hi_75 = cat(states[6].vc_sel.`3`[7], states[6].vc_sel.`3`[6]) node credit_available_hi_75 = cat(credit_available_hi_hi_75, credit_available_hi_lo_63) node _credit_available_T_81 = cat(credit_available_hi_75, credit_available_lo_75) node credit_available_lo_lo_64 = cat(states[6].vc_sel.`4`[1], states[6].vc_sel.`4`[0]) node credit_available_lo_hi_64 = cat(states[6].vc_sel.`4`[3], states[6].vc_sel.`4`[2]) node credit_available_lo_76 = cat(credit_available_lo_hi_64, credit_available_lo_lo_64) node credit_available_hi_lo_64 = cat(states[6].vc_sel.`4`[5], states[6].vc_sel.`4`[4]) node credit_available_hi_hi_76 = cat(states[6].vc_sel.`4`[7], states[6].vc_sel.`4`[6]) node credit_available_hi_76 = cat(credit_available_hi_hi_76, credit_available_hi_lo_64) node _credit_available_T_82 = cat(credit_available_hi_76, credit_available_lo_76) node credit_available_lo_77 = cat(_credit_available_T_79, _credit_available_T_78) node credit_available_hi_hi_77 = cat(_credit_available_T_82, _credit_available_T_81) node credit_available_hi_77 = cat(credit_available_hi_hi_77, _credit_available_T_80) node _credit_available_T_83 = cat(credit_available_hi_77, credit_available_lo_77) node credit_available_lo_lo_65 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_65 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_78 = cat(credit_available_lo_hi_65, credit_available_lo_lo_65) node credit_available_hi_lo_65 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_78 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_78 = cat(credit_available_hi_hi_78, credit_available_hi_lo_65) node _credit_available_T_84 = cat(credit_available_hi_78, credit_available_lo_78) node credit_available_lo_lo_66 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_66 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_79 = cat(credit_available_lo_hi_66, credit_available_lo_lo_66) node credit_available_hi_lo_66 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_79 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_79 = cat(credit_available_hi_hi_79, credit_available_hi_lo_66) node _credit_available_T_85 = cat(credit_available_hi_79, credit_available_lo_79) node credit_available_lo_lo_67 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_67 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_80 = cat(credit_available_lo_hi_67, credit_available_lo_lo_67) node credit_available_hi_lo_67 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_80 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_80 = cat(credit_available_hi_hi_80, credit_available_hi_lo_67) node _credit_available_T_86 = cat(credit_available_hi_80, credit_available_lo_80) node credit_available_lo_lo_68 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_68 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_81 = cat(credit_available_lo_hi_68, credit_available_lo_lo_68) node credit_available_hi_lo_68 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_81 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_81 = cat(credit_available_hi_hi_81, credit_available_hi_lo_68) node _credit_available_T_87 = cat(credit_available_hi_81, credit_available_lo_81) node credit_available_lo_lo_69 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_69 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_82 = cat(credit_available_lo_hi_69, credit_available_lo_lo_69) node credit_available_hi_lo_69 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_82 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_82 = cat(credit_available_hi_hi_82, credit_available_hi_lo_69) node _credit_available_T_88 = cat(credit_available_hi_82, credit_available_lo_82) node credit_available_lo_83 = cat(_credit_available_T_85, _credit_available_T_84) node credit_available_hi_hi_83 = cat(_credit_available_T_88, _credit_available_T_87) node credit_available_hi_83 = cat(credit_available_hi_hi_83, _credit_available_T_86) node _credit_available_T_89 = cat(credit_available_hi_83, credit_available_lo_83) node _credit_available_T_90 = and(_credit_available_T_83, _credit_available_T_89) node credit_available_6 = neq(_credit_available_T_90, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_6) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.vc_sel.`3`[0], states[6].vc_sel.`3`[0] connect salloc_arb.io.in[6].bits.vc_sel.`3`[1], states[6].vc_sel.`3`[1] connect salloc_arb.io.in[6].bits.vc_sel.`3`[2], states[6].vc_sel.`3`[2] connect salloc_arb.io.in[6].bits.vc_sel.`3`[3], states[6].vc_sel.`3`[3] connect salloc_arb.io.in[6].bits.vc_sel.`3`[4], states[6].vc_sel.`3`[4] connect salloc_arb.io.in[6].bits.vc_sel.`3`[5], states[6].vc_sel.`3`[5] connect salloc_arb.io.in[6].bits.vc_sel.`3`[6], states[6].vc_sel.`3`[6] connect salloc_arb.io.in[6].bits.vc_sel.`3`[7], states[6].vc_sel.`3`[7] connect salloc_arb.io.in[6].bits.vc_sel.`4`[0], states[6].vc_sel.`4`[0] connect salloc_arb.io.in[6].bits.vc_sel.`4`[1], states[6].vc_sel.`4`[1] connect salloc_arb.io.in[6].bits.vc_sel.`4`[2], states[6].vc_sel.`4`[2] connect salloc_arb.io.in[6].bits.vc_sel.`4`[3], states[6].vc_sel.`4`[3] connect salloc_arb.io.in[6].bits.vc_sel.`4`[4], states[6].vc_sel.`4`[4] connect salloc_arb.io.in[6].bits.vc_sel.`4`[5], states[6].vc_sel.`4`[5] connect salloc_arb.io.in[6].bits.vc_sel.`4`[6], states[6].vc_sel.`4`[6] connect salloc_arb.io.in[6].bits.vc_sel.`4`[7], states[6].vc_sel.`4`[7] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_115 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_116 = and(_T_115, input_buffer.io.deq[6].bits.tail) when _T_116 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_70 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_70 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2]) node credit_available_lo_84 = cat(credit_available_lo_hi_70, credit_available_lo_lo_70) node credit_available_hi_lo_70 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4]) node credit_available_hi_hi_84 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6]) node credit_available_hi_84 = cat(credit_available_hi_hi_84, credit_available_hi_lo_70) node _credit_available_T_91 = cat(credit_available_hi_84, credit_available_lo_84) node credit_available_lo_lo_71 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_71 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2]) node credit_available_lo_85 = cat(credit_available_lo_hi_71, credit_available_lo_lo_71) node credit_available_hi_lo_71 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4]) node credit_available_hi_hi_85 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6]) node credit_available_hi_85 = cat(credit_available_hi_hi_85, credit_available_hi_lo_71) node _credit_available_T_92 = cat(credit_available_hi_85, credit_available_lo_85) node credit_available_lo_lo_72 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_72 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2]) node credit_available_lo_86 = cat(credit_available_lo_hi_72, credit_available_lo_lo_72) node credit_available_hi_lo_72 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4]) node credit_available_hi_hi_86 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6]) node credit_available_hi_86 = cat(credit_available_hi_hi_86, credit_available_hi_lo_72) node _credit_available_T_93 = cat(credit_available_hi_86, credit_available_lo_86) node credit_available_lo_lo_73 = cat(states[7].vc_sel.`3`[1], states[7].vc_sel.`3`[0]) node credit_available_lo_hi_73 = cat(states[7].vc_sel.`3`[3], states[7].vc_sel.`3`[2]) node credit_available_lo_87 = cat(credit_available_lo_hi_73, credit_available_lo_lo_73) node credit_available_hi_lo_73 = cat(states[7].vc_sel.`3`[5], states[7].vc_sel.`3`[4]) node credit_available_hi_hi_87 = cat(states[7].vc_sel.`3`[7], states[7].vc_sel.`3`[6]) node credit_available_hi_87 = cat(credit_available_hi_hi_87, credit_available_hi_lo_73) node _credit_available_T_94 = cat(credit_available_hi_87, credit_available_lo_87) node credit_available_lo_lo_74 = cat(states[7].vc_sel.`4`[1], states[7].vc_sel.`4`[0]) node credit_available_lo_hi_74 = cat(states[7].vc_sel.`4`[3], states[7].vc_sel.`4`[2]) node credit_available_lo_88 = cat(credit_available_lo_hi_74, credit_available_lo_lo_74) node credit_available_hi_lo_74 = cat(states[7].vc_sel.`4`[5], states[7].vc_sel.`4`[4]) node credit_available_hi_hi_88 = cat(states[7].vc_sel.`4`[7], states[7].vc_sel.`4`[6]) node credit_available_hi_88 = cat(credit_available_hi_hi_88, credit_available_hi_lo_74) node _credit_available_T_95 = cat(credit_available_hi_88, credit_available_lo_88) node credit_available_lo_89 = cat(_credit_available_T_92, _credit_available_T_91) node credit_available_hi_hi_89 = cat(_credit_available_T_95, _credit_available_T_94) node credit_available_hi_89 = cat(credit_available_hi_hi_89, _credit_available_T_93) node _credit_available_T_96 = cat(credit_available_hi_89, credit_available_lo_89) node credit_available_lo_lo_75 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_75 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_90 = cat(credit_available_lo_hi_75, credit_available_lo_lo_75) node credit_available_hi_lo_75 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_90 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_90 = cat(credit_available_hi_hi_90, credit_available_hi_lo_75) node _credit_available_T_97 = cat(credit_available_hi_90, credit_available_lo_90) node credit_available_lo_lo_76 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_76 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_91 = cat(credit_available_lo_hi_76, credit_available_lo_lo_76) node credit_available_hi_lo_76 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_91 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_91 = cat(credit_available_hi_hi_91, credit_available_hi_lo_76) node _credit_available_T_98 = cat(credit_available_hi_91, credit_available_lo_91) node credit_available_lo_lo_77 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_77 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_92 = cat(credit_available_lo_hi_77, credit_available_lo_lo_77) node credit_available_hi_lo_77 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_92 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_92 = cat(credit_available_hi_hi_92, credit_available_hi_lo_77) node _credit_available_T_99 = cat(credit_available_hi_92, credit_available_lo_92) node credit_available_lo_lo_78 = cat(io.out_credit_available.`3`[1], io.out_credit_available.`3`[0]) node credit_available_lo_hi_78 = cat(io.out_credit_available.`3`[3], io.out_credit_available.`3`[2]) node credit_available_lo_93 = cat(credit_available_lo_hi_78, credit_available_lo_lo_78) node credit_available_hi_lo_78 = cat(io.out_credit_available.`3`[5], io.out_credit_available.`3`[4]) node credit_available_hi_hi_93 = cat(io.out_credit_available.`3`[7], io.out_credit_available.`3`[6]) node credit_available_hi_93 = cat(credit_available_hi_hi_93, credit_available_hi_lo_78) node _credit_available_T_100 = cat(credit_available_hi_93, credit_available_lo_93) node credit_available_lo_lo_79 = cat(io.out_credit_available.`4`[1], io.out_credit_available.`4`[0]) node credit_available_lo_hi_79 = cat(io.out_credit_available.`4`[3], io.out_credit_available.`4`[2]) node credit_available_lo_94 = cat(credit_available_lo_hi_79, credit_available_lo_lo_79) node credit_available_hi_lo_79 = cat(io.out_credit_available.`4`[5], io.out_credit_available.`4`[4]) node credit_available_hi_hi_94 = cat(io.out_credit_available.`4`[7], io.out_credit_available.`4`[6]) node credit_available_hi_94 = cat(credit_available_hi_hi_94, credit_available_hi_lo_79) node _credit_available_T_101 = cat(credit_available_hi_94, credit_available_lo_94) node credit_available_lo_95 = cat(_credit_available_T_98, _credit_available_T_97) node credit_available_hi_hi_95 = cat(_credit_available_T_101, _credit_available_T_100) node credit_available_hi_95 = cat(credit_available_hi_hi_95, _credit_available_T_99) node _credit_available_T_102 = cat(credit_available_hi_95, credit_available_lo_95) node _credit_available_T_103 = and(_credit_available_T_96, _credit_available_T_102) node credit_available_7 = neq(_credit_available_T_103, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_7) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.vc_sel.`3`[0], states[7].vc_sel.`3`[0] connect salloc_arb.io.in[7].bits.vc_sel.`3`[1], states[7].vc_sel.`3`[1] connect salloc_arb.io.in[7].bits.vc_sel.`3`[2], states[7].vc_sel.`3`[2] connect salloc_arb.io.in[7].bits.vc_sel.`3`[3], states[7].vc_sel.`3`[3] connect salloc_arb.io.in[7].bits.vc_sel.`3`[4], states[7].vc_sel.`3`[4] connect salloc_arb.io.in[7].bits.vc_sel.`3`[5], states[7].vc_sel.`3`[5] connect salloc_arb.io.in[7].bits.vc_sel.`3`[6], states[7].vc_sel.`3`[6] connect salloc_arb.io.in[7].bits.vc_sel.`3`[7], states[7].vc_sel.`3`[7] connect salloc_arb.io.in[7].bits.vc_sel.`4`[0], states[7].vc_sel.`4`[0] connect salloc_arb.io.in[7].bits.vc_sel.`4`[1], states[7].vc_sel.`4`[1] connect salloc_arb.io.in[7].bits.vc_sel.`4`[2], states[7].vc_sel.`4`[2] connect salloc_arb.io.in[7].bits.vc_sel.`4`[3], states[7].vc_sel.`4`[3] connect salloc_arb.io.in[7].bits.vc_sel.`4`[4], states[7].vc_sel.`4`[4] connect salloc_arb.io.in[7].bits.vc_sel.`4`[5], states[7].vc_sel.`4`[5] connect salloc_arb.io.in[7].bits.vc_sel.`4`[6], states[7].vc_sel.`4`[6] connect salloc_arb.io.in[7].bits.vc_sel.`4`[7], states[7].vc_sel.`4`[7] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_117 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_118 = and(_T_117, input_buffer.io.deq[7].bits.tail) when _T_118 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_29 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10) node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11) node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12) node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23 node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_25 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire vc_sel : { `4` : UInt<1>[8], `3` : UInt<1>[8], `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _vc_sel_WIRE : UInt<1>[8] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10) node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11) node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_22 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25) node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26) node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_37 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42) node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43) node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_52 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_67 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_82 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87) node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88) node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_97 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99) node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100) node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101) node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_112 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116) node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117) node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118) node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119) node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_127 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_9 : UInt<1>[8] node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_142 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145) node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_157 connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159) node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160) node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161) node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162) node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163) node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164) node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_172 connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12 node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174) node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175) node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176) node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177) node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178) node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179) node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_187 connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13 node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192) node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193) node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194) node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_202 connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14 node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_217 connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15 node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219) node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220) node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221) node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_232 connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16 node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234) node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235) node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236) node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237) node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238) node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239) node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_247 connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17 connect vc_sel.`1`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_18 : UInt<1>[8] node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249) node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250) node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251) node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252) node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253) node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254) node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_262 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268) node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269) node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_277 connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20 node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_292 connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21 node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294) node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295) node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296) node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297) node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300) wire _vc_sel_WIRE_22 : UInt<1> connect _vc_sel_WIRE_22, _vc_sel_T_307 connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22 node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309) node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310) node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311) node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312) node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313) node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314) node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_322 connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23 node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325) node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326) node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327) node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328) node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329) node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_337 connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24 node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344) node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_352 connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25 node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354) node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_367 connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26 connect vc_sel.`2`, _vc_sel_WIRE_18 wire _vc_sel_WIRE_27 : UInt<1>[8] node _vc_sel_T_368 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_369 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_370 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_371 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_372 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_373 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_374 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_375 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_376 = or(_vc_sel_T_368, _vc_sel_T_369) node _vc_sel_T_377 = or(_vc_sel_T_376, _vc_sel_T_370) node _vc_sel_T_378 = or(_vc_sel_T_377, _vc_sel_T_371) node _vc_sel_T_379 = or(_vc_sel_T_378, _vc_sel_T_372) node _vc_sel_T_380 = or(_vc_sel_T_379, _vc_sel_T_373) node _vc_sel_T_381 = or(_vc_sel_T_380, _vc_sel_T_374) node _vc_sel_T_382 = or(_vc_sel_T_381, _vc_sel_T_375) wire _vc_sel_WIRE_28 : UInt<1> connect _vc_sel_WIRE_28, _vc_sel_T_382 connect _vc_sel_WIRE_27[0], _vc_sel_WIRE_28 node _vc_sel_T_383 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_384 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_385 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_386 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_387 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_388 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_389 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_390 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_391 = or(_vc_sel_T_383, _vc_sel_T_384) node _vc_sel_T_392 = or(_vc_sel_T_391, _vc_sel_T_385) node _vc_sel_T_393 = or(_vc_sel_T_392, _vc_sel_T_386) node _vc_sel_T_394 = or(_vc_sel_T_393, _vc_sel_T_387) node _vc_sel_T_395 = or(_vc_sel_T_394, _vc_sel_T_388) node _vc_sel_T_396 = or(_vc_sel_T_395, _vc_sel_T_389) node _vc_sel_T_397 = or(_vc_sel_T_396, _vc_sel_T_390) wire _vc_sel_WIRE_29 : UInt<1> connect _vc_sel_WIRE_29, _vc_sel_T_397 connect _vc_sel_WIRE_27[1], _vc_sel_WIRE_29 node _vc_sel_T_398 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_399 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_400 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_401 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_402 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_403 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_404 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_405 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_406 = or(_vc_sel_T_398, _vc_sel_T_399) node _vc_sel_T_407 = or(_vc_sel_T_406, _vc_sel_T_400) node _vc_sel_T_408 = or(_vc_sel_T_407, _vc_sel_T_401) node _vc_sel_T_409 = or(_vc_sel_T_408, _vc_sel_T_402) node _vc_sel_T_410 = or(_vc_sel_T_409, _vc_sel_T_403) node _vc_sel_T_411 = or(_vc_sel_T_410, _vc_sel_T_404) node _vc_sel_T_412 = or(_vc_sel_T_411, _vc_sel_T_405) wire _vc_sel_WIRE_30 : UInt<1> connect _vc_sel_WIRE_30, _vc_sel_T_412 connect _vc_sel_WIRE_27[2], _vc_sel_WIRE_30 node _vc_sel_T_413 = mux(_vc_sel_T, states[0].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_414 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_415 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_416 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_417 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_418 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_419 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_420 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[3], UInt<1>(0h0)) node _vc_sel_T_421 = or(_vc_sel_T_413, _vc_sel_T_414) node _vc_sel_T_422 = or(_vc_sel_T_421, _vc_sel_T_415) node _vc_sel_T_423 = or(_vc_sel_T_422, _vc_sel_T_416) node _vc_sel_T_424 = or(_vc_sel_T_423, _vc_sel_T_417) node _vc_sel_T_425 = or(_vc_sel_T_424, _vc_sel_T_418) node _vc_sel_T_426 = or(_vc_sel_T_425, _vc_sel_T_419) node _vc_sel_T_427 = or(_vc_sel_T_426, _vc_sel_T_420) wire _vc_sel_WIRE_31 : UInt<1> connect _vc_sel_WIRE_31, _vc_sel_T_427 connect _vc_sel_WIRE_27[3], _vc_sel_WIRE_31 node _vc_sel_T_428 = mux(_vc_sel_T, states[0].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_429 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_430 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_431 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_432 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_433 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_434 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_435 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[4], UInt<1>(0h0)) node _vc_sel_T_436 = or(_vc_sel_T_428, _vc_sel_T_429) node _vc_sel_T_437 = or(_vc_sel_T_436, _vc_sel_T_430) node _vc_sel_T_438 = or(_vc_sel_T_437, _vc_sel_T_431) node _vc_sel_T_439 = or(_vc_sel_T_438, _vc_sel_T_432) node _vc_sel_T_440 = or(_vc_sel_T_439, _vc_sel_T_433) node _vc_sel_T_441 = or(_vc_sel_T_440, _vc_sel_T_434) node _vc_sel_T_442 = or(_vc_sel_T_441, _vc_sel_T_435) wire _vc_sel_WIRE_32 : UInt<1> connect _vc_sel_WIRE_32, _vc_sel_T_442 connect _vc_sel_WIRE_27[4], _vc_sel_WIRE_32 node _vc_sel_T_443 = mux(_vc_sel_T, states[0].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_444 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_445 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_446 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_447 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_448 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_449 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_450 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[5], UInt<1>(0h0)) node _vc_sel_T_451 = or(_vc_sel_T_443, _vc_sel_T_444) node _vc_sel_T_452 = or(_vc_sel_T_451, _vc_sel_T_445) node _vc_sel_T_453 = or(_vc_sel_T_452, _vc_sel_T_446) node _vc_sel_T_454 = or(_vc_sel_T_453, _vc_sel_T_447) node _vc_sel_T_455 = or(_vc_sel_T_454, _vc_sel_T_448) node _vc_sel_T_456 = or(_vc_sel_T_455, _vc_sel_T_449) node _vc_sel_T_457 = or(_vc_sel_T_456, _vc_sel_T_450) wire _vc_sel_WIRE_33 : UInt<1> connect _vc_sel_WIRE_33, _vc_sel_T_457 connect _vc_sel_WIRE_27[5], _vc_sel_WIRE_33 node _vc_sel_T_458 = mux(_vc_sel_T, states[0].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_459 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_460 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_461 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_462 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_463 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_464 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_465 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[6], UInt<1>(0h0)) node _vc_sel_T_466 = or(_vc_sel_T_458, _vc_sel_T_459) node _vc_sel_T_467 = or(_vc_sel_T_466, _vc_sel_T_460) node _vc_sel_T_468 = or(_vc_sel_T_467, _vc_sel_T_461) node _vc_sel_T_469 = or(_vc_sel_T_468, _vc_sel_T_462) node _vc_sel_T_470 = or(_vc_sel_T_469, _vc_sel_T_463) node _vc_sel_T_471 = or(_vc_sel_T_470, _vc_sel_T_464) node _vc_sel_T_472 = or(_vc_sel_T_471, _vc_sel_T_465) wire _vc_sel_WIRE_34 : UInt<1> connect _vc_sel_WIRE_34, _vc_sel_T_472 connect _vc_sel_WIRE_27[6], _vc_sel_WIRE_34 node _vc_sel_T_473 = mux(_vc_sel_T, states[0].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_474 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_475 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_476 = mux(_vc_sel_T_3, states[3].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_477 = mux(_vc_sel_T_4, states[4].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_478 = mux(_vc_sel_T_5, states[5].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_479 = mux(_vc_sel_T_6, states[6].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_480 = mux(_vc_sel_T_7, states[7].vc_sel.`3`[7], UInt<1>(0h0)) node _vc_sel_T_481 = or(_vc_sel_T_473, _vc_sel_T_474) node _vc_sel_T_482 = or(_vc_sel_T_481, _vc_sel_T_475) node _vc_sel_T_483 = or(_vc_sel_T_482, _vc_sel_T_476) node _vc_sel_T_484 = or(_vc_sel_T_483, _vc_sel_T_477) node _vc_sel_T_485 = or(_vc_sel_T_484, _vc_sel_T_478) node _vc_sel_T_486 = or(_vc_sel_T_485, _vc_sel_T_479) node _vc_sel_T_487 = or(_vc_sel_T_486, _vc_sel_T_480) wire _vc_sel_WIRE_35 : UInt<1> connect _vc_sel_WIRE_35, _vc_sel_T_487 connect _vc_sel_WIRE_27[7], _vc_sel_WIRE_35 connect vc_sel.`3`, _vc_sel_WIRE_27 wire _vc_sel_WIRE_36 : UInt<1>[8] node _vc_sel_T_488 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_489 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_490 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_491 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_492 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_493 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_494 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_495 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_496 = or(_vc_sel_T_488, _vc_sel_T_489) node _vc_sel_T_497 = or(_vc_sel_T_496, _vc_sel_T_490) node _vc_sel_T_498 = or(_vc_sel_T_497, _vc_sel_T_491) node _vc_sel_T_499 = or(_vc_sel_T_498, _vc_sel_T_492) node _vc_sel_T_500 = or(_vc_sel_T_499, _vc_sel_T_493) node _vc_sel_T_501 = or(_vc_sel_T_500, _vc_sel_T_494) node _vc_sel_T_502 = or(_vc_sel_T_501, _vc_sel_T_495) wire _vc_sel_WIRE_37 : UInt<1> connect _vc_sel_WIRE_37, _vc_sel_T_502 connect _vc_sel_WIRE_36[0], _vc_sel_WIRE_37 node _vc_sel_T_503 = mux(_vc_sel_T, states[0].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_504 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_505 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_506 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_507 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_508 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_509 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_510 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[1], UInt<1>(0h0)) node _vc_sel_T_511 = or(_vc_sel_T_503, _vc_sel_T_504) node _vc_sel_T_512 = or(_vc_sel_T_511, _vc_sel_T_505) node _vc_sel_T_513 = or(_vc_sel_T_512, _vc_sel_T_506) node _vc_sel_T_514 = or(_vc_sel_T_513, _vc_sel_T_507) node _vc_sel_T_515 = or(_vc_sel_T_514, _vc_sel_T_508) node _vc_sel_T_516 = or(_vc_sel_T_515, _vc_sel_T_509) node _vc_sel_T_517 = or(_vc_sel_T_516, _vc_sel_T_510) wire _vc_sel_WIRE_38 : UInt<1> connect _vc_sel_WIRE_38, _vc_sel_T_517 connect _vc_sel_WIRE_36[1], _vc_sel_WIRE_38 node _vc_sel_T_518 = mux(_vc_sel_T, states[0].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_519 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_520 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_521 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_522 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_523 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_524 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_525 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[2], UInt<1>(0h0)) node _vc_sel_T_526 = or(_vc_sel_T_518, _vc_sel_T_519) node _vc_sel_T_527 = or(_vc_sel_T_526, _vc_sel_T_520) node _vc_sel_T_528 = or(_vc_sel_T_527, _vc_sel_T_521) node _vc_sel_T_529 = or(_vc_sel_T_528, _vc_sel_T_522) node _vc_sel_T_530 = or(_vc_sel_T_529, _vc_sel_T_523) node _vc_sel_T_531 = or(_vc_sel_T_530, _vc_sel_T_524) node _vc_sel_T_532 = or(_vc_sel_T_531, _vc_sel_T_525) wire _vc_sel_WIRE_39 : UInt<1> connect _vc_sel_WIRE_39, _vc_sel_T_532 connect _vc_sel_WIRE_36[2], _vc_sel_WIRE_39 node _vc_sel_T_533 = mux(_vc_sel_T, states[0].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_534 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_535 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_536 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_537 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_538 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_539 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_540 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[3], UInt<1>(0h0)) node _vc_sel_T_541 = or(_vc_sel_T_533, _vc_sel_T_534) node _vc_sel_T_542 = or(_vc_sel_T_541, _vc_sel_T_535) node _vc_sel_T_543 = or(_vc_sel_T_542, _vc_sel_T_536) node _vc_sel_T_544 = or(_vc_sel_T_543, _vc_sel_T_537) node _vc_sel_T_545 = or(_vc_sel_T_544, _vc_sel_T_538) node _vc_sel_T_546 = or(_vc_sel_T_545, _vc_sel_T_539) node _vc_sel_T_547 = or(_vc_sel_T_546, _vc_sel_T_540) wire _vc_sel_WIRE_40 : UInt<1> connect _vc_sel_WIRE_40, _vc_sel_T_547 connect _vc_sel_WIRE_36[3], _vc_sel_WIRE_40 node _vc_sel_T_548 = mux(_vc_sel_T, states[0].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_549 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_550 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_551 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_552 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_553 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_554 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_555 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[4], UInt<1>(0h0)) node _vc_sel_T_556 = or(_vc_sel_T_548, _vc_sel_T_549) node _vc_sel_T_557 = or(_vc_sel_T_556, _vc_sel_T_550) node _vc_sel_T_558 = or(_vc_sel_T_557, _vc_sel_T_551) node _vc_sel_T_559 = or(_vc_sel_T_558, _vc_sel_T_552) node _vc_sel_T_560 = or(_vc_sel_T_559, _vc_sel_T_553) node _vc_sel_T_561 = or(_vc_sel_T_560, _vc_sel_T_554) node _vc_sel_T_562 = or(_vc_sel_T_561, _vc_sel_T_555) wire _vc_sel_WIRE_41 : UInt<1> connect _vc_sel_WIRE_41, _vc_sel_T_562 connect _vc_sel_WIRE_36[4], _vc_sel_WIRE_41 node _vc_sel_T_563 = mux(_vc_sel_T, states[0].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_564 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_565 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_566 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_567 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_568 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_569 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_570 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[5], UInt<1>(0h0)) node _vc_sel_T_571 = or(_vc_sel_T_563, _vc_sel_T_564) node _vc_sel_T_572 = or(_vc_sel_T_571, _vc_sel_T_565) node _vc_sel_T_573 = or(_vc_sel_T_572, _vc_sel_T_566) node _vc_sel_T_574 = or(_vc_sel_T_573, _vc_sel_T_567) node _vc_sel_T_575 = or(_vc_sel_T_574, _vc_sel_T_568) node _vc_sel_T_576 = or(_vc_sel_T_575, _vc_sel_T_569) node _vc_sel_T_577 = or(_vc_sel_T_576, _vc_sel_T_570) wire _vc_sel_WIRE_42 : UInt<1> connect _vc_sel_WIRE_42, _vc_sel_T_577 connect _vc_sel_WIRE_36[5], _vc_sel_WIRE_42 node _vc_sel_T_578 = mux(_vc_sel_T, states[0].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_579 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_580 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_581 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_582 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_583 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_584 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_585 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[6], UInt<1>(0h0)) node _vc_sel_T_586 = or(_vc_sel_T_578, _vc_sel_T_579) node _vc_sel_T_587 = or(_vc_sel_T_586, _vc_sel_T_580) node _vc_sel_T_588 = or(_vc_sel_T_587, _vc_sel_T_581) node _vc_sel_T_589 = or(_vc_sel_T_588, _vc_sel_T_582) node _vc_sel_T_590 = or(_vc_sel_T_589, _vc_sel_T_583) node _vc_sel_T_591 = or(_vc_sel_T_590, _vc_sel_T_584) node _vc_sel_T_592 = or(_vc_sel_T_591, _vc_sel_T_585) wire _vc_sel_WIRE_43 : UInt<1> connect _vc_sel_WIRE_43, _vc_sel_T_592 connect _vc_sel_WIRE_36[6], _vc_sel_WIRE_43 node _vc_sel_T_593 = mux(_vc_sel_T, states[0].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_594 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_595 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_596 = mux(_vc_sel_T_3, states[3].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_597 = mux(_vc_sel_T_4, states[4].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_598 = mux(_vc_sel_T_5, states[5].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_599 = mux(_vc_sel_T_6, states[6].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_600 = mux(_vc_sel_T_7, states[7].vc_sel.`4`[7], UInt<1>(0h0)) node _vc_sel_T_601 = or(_vc_sel_T_593, _vc_sel_T_594) node _vc_sel_T_602 = or(_vc_sel_T_601, _vc_sel_T_595) node _vc_sel_T_603 = or(_vc_sel_T_602, _vc_sel_T_596) node _vc_sel_T_604 = or(_vc_sel_T_603, _vc_sel_T_597) node _vc_sel_T_605 = or(_vc_sel_T_604, _vc_sel_T_598) node _vc_sel_T_606 = or(_vc_sel_T_605, _vc_sel_T_599) node _vc_sel_T_607 = or(_vc_sel_T_606, _vc_sel_T_600) wire _vc_sel_WIRE_44 : UInt<1> connect _vc_sel_WIRE_44, _vc_sel_T_607 connect _vc_sel_WIRE_36[7], _vc_sel_WIRE_44 connect vc_sel.`4`, _vc_sel_WIRE_36 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6]) node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7]) node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4]) node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6]) node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7]) node _channel_oh_T_18 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node _channel_oh_T_19 = or(_channel_oh_T_18, vc_sel.`3`[2]) node _channel_oh_T_20 = or(_channel_oh_T_19, vc_sel.`3`[3]) node _channel_oh_T_21 = or(_channel_oh_T_20, vc_sel.`3`[4]) node _channel_oh_T_22 = or(_channel_oh_T_21, vc_sel.`3`[5]) node _channel_oh_T_23 = or(_channel_oh_T_22, vc_sel.`3`[6]) node channel_oh_3 = or(_channel_oh_T_23, vc_sel.`3`[7]) node _channel_oh_T_24 = or(vc_sel.`4`[0], vc_sel.`4`[1]) node _channel_oh_T_25 = or(_channel_oh_T_24, vc_sel.`4`[2]) node _channel_oh_T_26 = or(_channel_oh_T_25, vc_sel.`4`[3]) node _channel_oh_T_27 = or(_channel_oh_T_26, vc_sel.`4`[4]) node _channel_oh_T_28 = or(_channel_oh_T_27, vc_sel.`4`[5]) node _channel_oh_T_29 = or(_channel_oh_T_28, vc_sel.`4`[6]) node channel_oh_4 = or(_channel_oh_T_29, vc_sel.`4`[7]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2]) node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2]) node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node virt_channel_lo_lo_3 = cat(vc_sel.`3`[1], vc_sel.`3`[0]) node virt_channel_lo_hi_3 = cat(vc_sel.`3`[3], vc_sel.`3`[2]) node virt_channel_lo_9 = cat(virt_channel_lo_hi_3, virt_channel_lo_lo_3) node virt_channel_hi_lo_3 = cat(vc_sel.`3`[5], vc_sel.`3`[4]) node virt_channel_hi_hi_3 = cat(vc_sel.`3`[7], vc_sel.`3`[6]) node virt_channel_hi_9 = cat(virt_channel_hi_hi_3, virt_channel_hi_lo_3) node _virt_channel_T_24 = cat(virt_channel_hi_9, virt_channel_lo_9) node virt_channel_hi_10 = bits(_virt_channel_T_24, 7, 4) node virt_channel_lo_10 = bits(_virt_channel_T_24, 3, 0) node _virt_channel_T_25 = orr(virt_channel_hi_10) node _virt_channel_T_26 = or(virt_channel_hi_10, virt_channel_lo_10) node virt_channel_hi_11 = bits(_virt_channel_T_26, 3, 2) node virt_channel_lo_11 = bits(_virt_channel_T_26, 1, 0) node _virt_channel_T_27 = orr(virt_channel_hi_11) node _virt_channel_T_28 = or(virt_channel_hi_11, virt_channel_lo_11) node _virt_channel_T_29 = bits(_virt_channel_T_28, 1, 1) node _virt_channel_T_30 = cat(_virt_channel_T_27, _virt_channel_T_29) node _virt_channel_T_31 = cat(_virt_channel_T_25, _virt_channel_T_30) node virt_channel_lo_lo_4 = cat(vc_sel.`4`[1], vc_sel.`4`[0]) node virt_channel_lo_hi_4 = cat(vc_sel.`4`[3], vc_sel.`4`[2]) node virt_channel_lo_12 = cat(virt_channel_lo_hi_4, virt_channel_lo_lo_4) node virt_channel_hi_lo_4 = cat(vc_sel.`4`[5], vc_sel.`4`[4]) node virt_channel_hi_hi_4 = cat(vc_sel.`4`[7], vc_sel.`4`[6]) node virt_channel_hi_12 = cat(virt_channel_hi_hi_4, virt_channel_hi_lo_4) node _virt_channel_T_32 = cat(virt_channel_hi_12, virt_channel_lo_12) node virt_channel_hi_13 = bits(_virt_channel_T_32, 7, 4) node virt_channel_lo_13 = bits(_virt_channel_T_32, 3, 0) node _virt_channel_T_33 = orr(virt_channel_hi_13) node _virt_channel_T_34 = or(virt_channel_hi_13, virt_channel_lo_13) node virt_channel_hi_14 = bits(_virt_channel_T_34, 3, 2) node virt_channel_lo_14 = bits(_virt_channel_T_34, 1, 0) node _virt_channel_T_35 = orr(virt_channel_hi_14) node _virt_channel_T_36 = or(virt_channel_hi_14, virt_channel_lo_14) node _virt_channel_T_37 = bits(_virt_channel_T_36, 1, 1) node _virt_channel_T_38 = cat(_virt_channel_T_35, _virt_channel_T_37) node _virt_channel_T_39 = cat(_virt_channel_T_33, _virt_channel_T_38) node _virt_channel_T_40 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_41 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_42 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_43 = mux(channel_oh_3, _virt_channel_T_31, UInt<1>(0h0)) node _virt_channel_T_44 = mux(channel_oh_4, _virt_channel_T_39, UInt<1>(0h0)) node _virt_channel_T_45 = or(_virt_channel_T_40, _virt_channel_T_41) node _virt_channel_T_46 = or(_virt_channel_T_45, _virt_channel_T_42) node _virt_channel_T_47 = or(_virt_channel_T_46, _virt_channel_T_43) node _virt_channel_T_48 = or(_virt_channel_T_47, _virt_channel_T_44) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_48 node _T_119 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_119 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59) node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`1`[0], UInt<1>(0h0) connect states[0].vc_sel.`1`[1], UInt<1>(0h0) connect states[0].vc_sel.`1`[2], UInt<1>(0h0) connect states[0].vc_sel.`1`[3], UInt<1>(0h0) connect states[0].vc_sel.`1`[4], UInt<1>(0h0) connect states[0].vc_sel.`1`[5], UInt<1>(0h0) connect states[0].vc_sel.`1`[6], UInt<1>(0h0) connect states[0].vc_sel.`1`[7], UInt<1>(0h0) connect states[0].vc_sel.`2`[1], UInt<1>(0h0) connect states[0].vc_sel.`2`[2], UInt<1>(0h0) connect states[0].vc_sel.`2`[3], UInt<1>(0h0) connect states[0].vc_sel.`2`[4], UInt<1>(0h0) connect states[0].vc_sel.`2`[5], UInt<1>(0h0) connect states[0].vc_sel.`2`[6], UInt<1>(0h0) connect states[0].vc_sel.`2`[7], UInt<1>(0h0) connect states[0].vc_sel.`3`[0], UInt<1>(0h0) connect states[0].vc_sel.`3`[1], UInt<1>(0h0) connect states[0].vc_sel.`3`[2], UInt<1>(0h0) connect states[0].vc_sel.`3`[3], UInt<1>(0h0) connect states[0].vc_sel.`3`[4], UInt<1>(0h0) connect states[0].vc_sel.`3`[5], UInt<1>(0h0) connect states[0].vc_sel.`3`[6], UInt<1>(0h0) connect states[0].vc_sel.`3`[7], UInt<1>(0h0) connect states[0].vc_sel.`4`[1], UInt<1>(0h0) connect states[0].vc_sel.`4`[2], UInt<1>(0h0) connect states[0].vc_sel.`4`[3], UInt<1>(0h0) connect states[0].vc_sel.`4`[4], UInt<1>(0h0) connect states[0].vc_sel.`4`[5], UInt<1>(0h0) connect states[0].vc_sel.`4`[6], UInt<1>(0h0) connect states[0].vc_sel.`4`[7], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[5], UInt<1>(0h0) connect states[1].vc_sel.`1`[6], UInt<1>(0h0) connect states[1].vc_sel.`1`[7], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) connect states[1].vc_sel.`3`[1], UInt<1>(0h0) connect states[1].vc_sel.`3`[2], UInt<1>(0h0) connect states[1].vc_sel.`3`[3], UInt<1>(0h0) connect states[1].vc_sel.`3`[4], UInt<1>(0h0) connect states[1].vc_sel.`3`[5], UInt<1>(0h0) connect states[1].vc_sel.`3`[6], UInt<1>(0h0) connect states[1].vc_sel.`3`[7], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[2], UInt<1>(0h0) connect states[2].vc_sel.`1`[3], UInt<1>(0h0) connect states[2].vc_sel.`1`[4], UInt<1>(0h0) connect states[2].vc_sel.`1`[5], UInt<1>(0h0) connect states[2].vc_sel.`1`[6], UInt<1>(0h0) connect states[2].vc_sel.`1`[7], UInt<1>(0h0) connect states[2].vc_sel.`3`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[1], UInt<1>(0h0) connect states[2].vc_sel.`3`[2], UInt<1>(0h0) connect states[2].vc_sel.`3`[3], UInt<1>(0h0) connect states[2].vc_sel.`3`[4], UInt<1>(0h0) connect states[2].vc_sel.`3`[5], UInt<1>(0h0) connect states[2].vc_sel.`3`[6], UInt<1>(0h0) connect states[2].vc_sel.`3`[7], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[1], UInt<1>(0h0) connect states[3].vc_sel.`1`[2], UInt<1>(0h0) connect states[3].vc_sel.`1`[3], UInt<1>(0h0) connect states[3].vc_sel.`1`[4], UInt<1>(0h0) connect states[3].vc_sel.`1`[5], UInt<1>(0h0) connect states[3].vc_sel.`1`[6], UInt<1>(0h0) connect states[3].vc_sel.`1`[7], UInt<1>(0h0) connect states[3].vc_sel.`3`[0], UInt<1>(0h0) connect states[3].vc_sel.`3`[1], UInt<1>(0h0) connect states[3].vc_sel.`3`[2], UInt<1>(0h0) connect states[3].vc_sel.`3`[3], UInt<1>(0h0) connect states[3].vc_sel.`3`[4], UInt<1>(0h0) connect states[3].vc_sel.`3`[5], UInt<1>(0h0) connect states[3].vc_sel.`3`[6], UInt<1>(0h0) connect states[3].vc_sel.`3`[7], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[1], UInt<1>(0h0) connect states[4].vc_sel.`1`[2], UInt<1>(0h0) connect states[4].vc_sel.`1`[3], UInt<1>(0h0) connect states[4].vc_sel.`1`[4], UInt<1>(0h0) connect states[4].vc_sel.`1`[5], UInt<1>(0h0) connect states[4].vc_sel.`1`[6], UInt<1>(0h0) connect states[4].vc_sel.`1`[7], UInt<1>(0h0) connect states[4].vc_sel.`3`[0], UInt<1>(0h0) connect states[4].vc_sel.`3`[1], UInt<1>(0h0) connect states[4].vc_sel.`3`[2], UInt<1>(0h0) connect states[4].vc_sel.`3`[3], UInt<1>(0h0) connect states[4].vc_sel.`3`[4], UInt<1>(0h0) connect states[4].vc_sel.`3`[5], UInt<1>(0h0) connect states[4].vc_sel.`3`[6], UInt<1>(0h0) connect states[4].vc_sel.`3`[7], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[1], UInt<1>(0h0) connect states[5].vc_sel.`1`[2], UInt<1>(0h0) connect states[5].vc_sel.`1`[3], UInt<1>(0h0) connect states[5].vc_sel.`1`[4], UInt<1>(0h0) connect states[5].vc_sel.`1`[5], UInt<1>(0h0) connect states[5].vc_sel.`1`[6], UInt<1>(0h0) connect states[5].vc_sel.`1`[7], UInt<1>(0h0) connect states[5].vc_sel.`3`[0], UInt<1>(0h0) connect states[5].vc_sel.`3`[1], UInt<1>(0h0) connect states[5].vc_sel.`3`[2], UInt<1>(0h0) connect states[5].vc_sel.`3`[3], UInt<1>(0h0) connect states[5].vc_sel.`3`[4], UInt<1>(0h0) connect states[5].vc_sel.`3`[5], UInt<1>(0h0) connect states[5].vc_sel.`3`[6], UInt<1>(0h0) connect states[5].vc_sel.`3`[7], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[1], UInt<1>(0h0) connect states[6].vc_sel.`1`[2], UInt<1>(0h0) connect states[6].vc_sel.`1`[3], UInt<1>(0h0) connect states[6].vc_sel.`1`[4], UInt<1>(0h0) connect states[6].vc_sel.`1`[5], UInt<1>(0h0) connect states[6].vc_sel.`1`[6], UInt<1>(0h0) connect states[6].vc_sel.`1`[7], UInt<1>(0h0) connect states[6].vc_sel.`3`[0], UInt<1>(0h0) connect states[6].vc_sel.`3`[1], UInt<1>(0h0) connect states[6].vc_sel.`3`[2], UInt<1>(0h0) connect states[6].vc_sel.`3`[3], UInt<1>(0h0) connect states[6].vc_sel.`3`[4], UInt<1>(0h0) connect states[6].vc_sel.`3`[5], UInt<1>(0h0) connect states[6].vc_sel.`3`[6], UInt<1>(0h0) connect states[6].vc_sel.`3`[7], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[1], UInt<1>(0h0) connect states[7].vc_sel.`1`[2], UInt<1>(0h0) connect states[7].vc_sel.`1`[3], UInt<1>(0h0) connect states[7].vc_sel.`1`[4], UInt<1>(0h0) connect states[7].vc_sel.`1`[5], UInt<1>(0h0) connect states[7].vc_sel.`1`[6], UInt<1>(0h0) connect states[7].vc_sel.`1`[7], UInt<1>(0h0) connect states[7].vc_sel.`3`[0], UInt<1>(0h0) connect states[7].vc_sel.`3`[1], UInt<1>(0h0) connect states[7].vc_sel.`3`[2], UInt<1>(0h0) connect states[7].vc_sel.`3`[3], UInt<1>(0h0) connect states[7].vc_sel.`3`[4], UInt<1>(0h0) connect states[7].vc_sel.`3`[5], UInt<1>(0h0) connect states[7].vc_sel.`3`[6], UInt<1>(0h0) connect states[7].vc_sel.`3`[7], UInt<1>(0h0) node _T_120 = asUInt(reset) when _T_120 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0)
module InputUnit_40( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_2_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_1, // @[InputUnit.scala:170:14] input io_out_credit_available_4_2, // @[InputUnit.scala:170:14] input io_out_credit_available_4_3, // @[InputUnit.scala:170:14] input io_out_credit_available_4_4, // @[InputUnit.scala:170:14] input io_out_credit_available_4_5, // @[InputUnit.scala:170:14] input io_out_credit_available_4_6, // @[InputUnit.scala:170:14] input io_out_credit_available_4_7, // @[InputUnit.scala:170:14] input io_out_credit_available_3_1, // @[InputUnit.scala:170:14] input io_out_credit_available_3_2, // @[InputUnit.scala:170:14] input io_out_credit_available_3_3, // @[InputUnit.scala:170:14] input io_out_credit_available_3_4, // @[InputUnit.scala:170:14] input io_out_credit_available_3_5, // @[InputUnit.scala:170:14] input io_out_credit_available_3_6, // @[InputUnit.scala:170:14] input io_out_credit_available_3_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire vcalloc_vals_0; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_4_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_2_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_0; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, vcalloc_vals_0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_0 ? 16'h100 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_0 | vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_0 = states_0_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[0]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_8 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module Pipeline_10 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, dram_addr : UInt, spad_addr : UInt, I : UInt, J : UInt}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, dram_addr : UInt, spad_addr : UInt, I : UInt, J : UInt}}, busy : UInt<1>} reg stages : { cmd : { inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>, status : { debug : UInt<1>, cease : UInt<1>, wfi : UInt<1>, isa : UInt<32>, dprv : UInt<2>, dv : UInt<1>, prv : UInt<2>, v : UInt<1>, sd : UInt<1>, zero2 : UInt<23>, mpv : UInt<1>, gva : UInt<1>, mbe : UInt<1>, sbe : UInt<1>, sxl : UInt<2>, uxl : UInt<2>, sd_rv32 : UInt<1>, zero1 : UInt<8>, tsr : UInt<1>, tw : UInt<1>, tvm : UInt<1>, mxr : UInt<1>, sum : UInt<1>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, mpp : UInt<2>, vs : UInt<2>, spp : UInt<1>, mpie : UInt<1>, ube : UInt<1>, spie : UInt<1>, upie : UInt<1>, mie : UInt<1>, hie : UInt<1>, sie : UInt<1>, uie : UInt<1>}}, dram_addr : UInt, spad_addr : UInt, I : UInt, J : UInt}[2], clock wire _valids_WIRE : UInt<1>[2] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) regreset valids : UInt<1>[2], clock, reset, _valids_WIRE wire stalling : UInt<1>[2] connect stalling[0], UInt<1>(0h0) connect stalling[1], UInt<1>(0h0) node _io_busy_T = or(valids[0], valids[1]) node _io_busy_T_1 = or(io.in.valid, _io_busy_T) connect io.busy, _io_busy_T_1 node _io_in_ready_T = eq(stalling[0], UInt<1>(0h0)) connect io.in.ready, _io_in_ready_T node _stalling_1_T = eq(io.out.ready, UInt<1>(0h0)) node _stalling_1_T_1 = and(valids[1], _stalling_1_T) connect stalling[1], _stalling_1_T_1 node _stalling_0_T = and(valids[0], stalling[1]) connect stalling[0], _stalling_0_T connect io.out.valid, valids[1] when io.out.ready : connect valids[1], UInt<1>(0h0) node _T = eq(stalling[1], UInt<1>(0h0)) when _T : connect valids[0], UInt<1>(0h0) node _T_1 = and(io.in.ready, io.in.valid) when _T_1 : connect valids[0], UInt<1>(0h1) when valids[0] : connect valids[1], UInt<1>(0h1) node _T_2 = and(io.in.ready, io.in.valid) when _T_2 : connect stages[0], io.in.bits connect io.out.bits, stages[1] node _T_3 = eq(stalling[1], UInt<1>(0h0)) when _T_3 : connect stages[1], stages[0]
module Pipeline_10( // @[Pipeline.scala:6:7] input clock, // @[Pipeline.scala:6:7] input reset, // @[Pipeline.scala:6:7] output io_in_ready, // @[Pipeline.scala:7:14] input io_in_valid, // @[Pipeline.scala:7:14] input [6:0] io_in_bits_cmd_inst_funct, // @[Pipeline.scala:7:14] input [63:0] io_in_bits_cmd_rs1, // @[Pipeline.scala:7:14] input [39:0] io_in_bits_dram_addr, // @[Pipeline.scala:7:14] input [67:0] io_in_bits_spad_addr, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_I, // @[Pipeline.scala:7:14] input [15:0] io_in_bits_J, // @[Pipeline.scala:7:14] input io_out_ready, // @[Pipeline.scala:7:14] output io_out_valid, // @[Pipeline.scala:7:14] output [6:0] io_out_bits_cmd_inst_funct, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rs2, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rs1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xd, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xs1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_inst_xs2, // @[Pipeline.scala:7:14] output [4:0] io_out_bits_cmd_inst_rd, // @[Pipeline.scala:7:14] output [6:0] io_out_bits_cmd_inst_opcode, // @[Pipeline.scala:7:14] output [63:0] io_out_bits_cmd_rs1, // @[Pipeline.scala:7:14] output [63:0] io_out_bits_cmd_rs2, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_debug, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_cease, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_wfi, // @[Pipeline.scala:7:14] output [31:0] io_out_bits_cmd_status_isa, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_dprv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_dv, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_prv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_v, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sd, // @[Pipeline.scala:7:14] output [22:0] io_out_bits_cmd_status_zero2, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mpv, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_gva, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mbe, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sbe, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_sxl, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_uxl, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sd_rv32, // @[Pipeline.scala:7:14] output [7:0] io_out_bits_cmd_status_zero1, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tsr, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tw, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_tvm, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mxr, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sum, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mprv, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_xs, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_fs, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_mpp, // @[Pipeline.scala:7:14] output [1:0] io_out_bits_cmd_status_vs, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_spp, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mpie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_ube, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_spie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_upie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_mie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_hie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_sie, // @[Pipeline.scala:7:14] output io_out_bits_cmd_status_uie, // @[Pipeline.scala:7:14] output [39:0] io_out_bits_dram_addr, // @[Pipeline.scala:7:14] output [67:0] io_out_bits_spad_addr, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_I, // @[Pipeline.scala:7:14] output [15:0] io_out_bits_J, // @[Pipeline.scala:7:14] output io_busy // @[Pipeline.scala:7:14] ); wire io_in_valid_0 = io_in_valid; // @[Pipeline.scala:6:7] wire [6:0] io_in_bits_cmd_inst_funct_0 = io_in_bits_cmd_inst_funct; // @[Pipeline.scala:6:7] wire [63:0] io_in_bits_cmd_rs1_0 = io_in_bits_cmd_rs1; // @[Pipeline.scala:6:7] wire [39:0] io_in_bits_dram_addr_0 = io_in_bits_dram_addr; // @[Pipeline.scala:6:7] wire [67:0] io_in_bits_spad_addr_0 = io_in_bits_spad_addr; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_I_0 = io_in_bits_I; // @[Pipeline.scala:6:7] wire [15:0] io_in_bits_J_0 = io_in_bits_J; // @[Pipeline.scala:6:7] wire io_out_ready_0 = io_out_ready; // @[Pipeline.scala:6:7] wire [4:0] io_in_bits_cmd_inst_rs2 = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [4:0] io_in_bits_cmd_inst_rs1 = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [4:0] io_in_bits_cmd_inst_rd = 5'h0; // @[Pipeline.scala:6:7, :7:14] wire [6:0] io_in_bits_cmd_inst_opcode = 7'h0; // @[Pipeline.scala:6:7, :7:14] wire [63:0] io_in_bits_cmd_rs2 = 64'h0; // @[Pipeline.scala:6:7, :7:14] wire [31:0] io_in_bits_cmd_status_isa = 32'h0; // @[Pipeline.scala:6:7, :7:14] wire [22:0] io_in_bits_cmd_status_zero2 = 23'h0; // @[Pipeline.scala:6:7, :7:14] wire [7:0] io_in_bits_cmd_status_zero1 = 8'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_dprv = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_prv = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_sxl = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_uxl = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_xs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_fs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_mpp = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire [1:0] io_in_bits_cmd_status_vs = 2'h0; // @[Pipeline.scala:6:7, :7:14] wire io_in_bits_cmd_inst_xd = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_inst_xs1 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_inst_xs2 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_debug = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_cease = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_wfi = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_dv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_v = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sd = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mpv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_gva = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mbe = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sbe = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sd_rv32 = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tsr = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tw = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_tvm = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mxr = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sum = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mprv = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_spp = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mpie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_ube = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_spie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_upie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_mie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_hie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_sie = 1'h0; // @[Pipeline.scala:6:7] wire io_in_bits_cmd_status_uie = 1'h0; // @[Pipeline.scala:6:7] wire _valids_WIRE_0 = 1'h0; // @[Pipeline.scala:22:33] wire _valids_WIRE_1 = 1'h0; // @[Pipeline.scala:22:33] wire _io_in_ready_T; // @[Pipeline.scala:27:20] wire _io_busy_T_1; // @[Pipeline.scala:24:28] wire io_in_ready_0; // @[Pipeline.scala:6:7] wire [6:0] io_out_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rs2_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rs1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xd_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xs1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_inst_xs2_0; // @[Pipeline.scala:6:7] wire [4:0] io_out_bits_cmd_inst_rd_0; // @[Pipeline.scala:6:7] wire [6:0] io_out_bits_cmd_inst_opcode_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_debug_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_cease_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_wfi_0; // @[Pipeline.scala:6:7] wire [31:0] io_out_bits_cmd_status_isa_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_dprv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_dv_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_prv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_v_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sd_0; // @[Pipeline.scala:6:7] wire [22:0] io_out_bits_cmd_status_zero2_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mpv_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_gva_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mbe_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sbe_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_sxl_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_uxl_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sd_rv32_0; // @[Pipeline.scala:6:7] wire [7:0] io_out_bits_cmd_status_zero1_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tsr_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tw_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_tvm_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mxr_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sum_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mprv_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_xs_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_fs_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_mpp_0; // @[Pipeline.scala:6:7] wire [1:0] io_out_bits_cmd_status_vs_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_spp_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mpie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_ube_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_spie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_upie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_mie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_hie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_sie_0; // @[Pipeline.scala:6:7] wire io_out_bits_cmd_status_uie_0; // @[Pipeline.scala:6:7] wire [63:0] io_out_bits_cmd_rs1_0; // @[Pipeline.scala:6:7] wire [63:0] io_out_bits_cmd_rs2_0; // @[Pipeline.scala:6:7] wire [39:0] io_out_bits_dram_addr_0; // @[Pipeline.scala:6:7] wire [67:0] io_out_bits_spad_addr_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_I_0; // @[Pipeline.scala:6:7] wire [15:0] io_out_bits_J_0; // @[Pipeline.scala:6:7] wire io_out_valid_0; // @[Pipeline.scala:6:7] wire io_busy_0; // @[Pipeline.scala:6:7] reg [6:0] stages_0_cmd_inst_funct; // @[Pipeline.scala:21:21] reg [63:0] stages_0_cmd_rs1; // @[Pipeline.scala:21:21] reg [39:0] stages_0_dram_addr; // @[Pipeline.scala:21:21] reg [67:0] stages_0_spad_addr; // @[Pipeline.scala:21:21] reg [15:0] stages_0_I; // @[Pipeline.scala:21:21] reg [15:0] stages_0_J; // @[Pipeline.scala:21:21] reg [6:0] stages_1_cmd_inst_funct; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_funct_0 = stages_1_cmd_inst_funct; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rs2_0 = stages_1_cmd_inst_rs2; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rs1_0 = stages_1_cmd_inst_rs1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xd_0 = stages_1_cmd_inst_xd; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xs1_0 = stages_1_cmd_inst_xs1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_inst_xs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_xs2_0 = stages_1_cmd_inst_xs2; // @[Pipeline.scala:6:7, :21:21] reg [4:0] stages_1_cmd_inst_rd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_rd_0 = stages_1_cmd_inst_rd; // @[Pipeline.scala:6:7, :21:21] reg [6:0] stages_1_cmd_inst_opcode; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_inst_opcode_0 = stages_1_cmd_inst_opcode; // @[Pipeline.scala:6:7, :21:21] reg [63:0] stages_1_cmd_rs1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_rs1_0 = stages_1_cmd_rs1; // @[Pipeline.scala:6:7, :21:21] reg [63:0] stages_1_cmd_rs2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_rs2_0 = stages_1_cmd_rs2; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_debug; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_debug_0 = stages_1_cmd_status_debug; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_cease; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_cease_0 = stages_1_cmd_status_cease; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_wfi; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_wfi_0 = stages_1_cmd_status_wfi; // @[Pipeline.scala:6:7, :21:21] reg [31:0] stages_1_cmd_status_isa; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_isa_0 = stages_1_cmd_status_isa; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_dprv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_dprv_0 = stages_1_cmd_status_dprv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_dv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_dv_0 = stages_1_cmd_status_dv; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_prv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_prv_0 = stages_1_cmd_status_prv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_v; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_v_0 = stages_1_cmd_status_v; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sd; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sd_0 = stages_1_cmd_status_sd; // @[Pipeline.scala:6:7, :21:21] reg [22:0] stages_1_cmd_status_zero2; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_zero2_0 = stages_1_cmd_status_zero2; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mpv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpv_0 = stages_1_cmd_status_mpv; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_gva; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_gva_0 = stages_1_cmd_status_gva; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mbe; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mbe_0 = stages_1_cmd_status_mbe; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sbe; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sbe_0 = stages_1_cmd_status_sbe; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_sxl; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sxl_0 = stages_1_cmd_status_sxl; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_uxl; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_uxl_0 = stages_1_cmd_status_uxl; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sd_rv32_0 = stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:6:7, :21:21] reg [7:0] stages_1_cmd_status_zero1; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_zero1_0 = stages_1_cmd_status_zero1; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tsr; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tsr_0 = stages_1_cmd_status_tsr; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tw; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tw_0 = stages_1_cmd_status_tw; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_tvm; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_tvm_0 = stages_1_cmd_status_tvm; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mxr; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mxr_0 = stages_1_cmd_status_mxr; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sum; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sum_0 = stages_1_cmd_status_sum; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mprv; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mprv_0 = stages_1_cmd_status_mprv; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_xs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_xs_0 = stages_1_cmd_status_xs; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_fs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_fs_0 = stages_1_cmd_status_fs; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_mpp; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpp_0 = stages_1_cmd_status_mpp; // @[Pipeline.scala:6:7, :21:21] reg [1:0] stages_1_cmd_status_vs; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_vs_0 = stages_1_cmd_status_vs; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_spp; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_spp_0 = stages_1_cmd_status_spp; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mpie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mpie_0 = stages_1_cmd_status_mpie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_ube; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_ube_0 = stages_1_cmd_status_ube; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_spie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_spie_0 = stages_1_cmd_status_spie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_upie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_upie_0 = stages_1_cmd_status_upie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_mie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_mie_0 = stages_1_cmd_status_mie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_hie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_hie_0 = stages_1_cmd_status_hie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_sie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_sie_0 = stages_1_cmd_status_sie; // @[Pipeline.scala:6:7, :21:21] reg stages_1_cmd_status_uie; // @[Pipeline.scala:21:21] assign io_out_bits_cmd_status_uie_0 = stages_1_cmd_status_uie; // @[Pipeline.scala:6:7, :21:21] reg [39:0] stages_1_dram_addr; // @[Pipeline.scala:21:21] assign io_out_bits_dram_addr_0 = stages_1_dram_addr; // @[Pipeline.scala:6:7, :21:21] reg [67:0] stages_1_spad_addr; // @[Pipeline.scala:21:21] assign io_out_bits_spad_addr_0 = stages_1_spad_addr; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_1_I; // @[Pipeline.scala:21:21] assign io_out_bits_I_0 = stages_1_I; // @[Pipeline.scala:6:7, :21:21] reg [15:0] stages_1_J; // @[Pipeline.scala:21:21] assign io_out_bits_J_0 = stages_1_J; // @[Pipeline.scala:6:7, :21:21] reg valids_0; // @[Pipeline.scala:22:25] reg valids_1; // @[Pipeline.scala:22:25] assign io_out_valid_0 = valids_1; // @[Pipeline.scala:6:7, :22:25] wire _stalling_0_T; // @[Pipeline.scala:30:16] wire _stalling_1_T_1; // @[Pipeline.scala:28:34] wire stalling_0; // @[Pipeline.scala:23:27] wire stalling_1; // @[Pipeline.scala:23:27] wire _io_busy_T = valids_0 | valids_1; // @[Pipeline.scala:22:25, :24:46] assign _io_busy_T_1 = io_in_valid_0 | _io_busy_T; // @[Pipeline.scala:6:7, :24:{28,46}] assign io_busy_0 = _io_busy_T_1; // @[Pipeline.scala:6:7, :24:28] assign _io_in_ready_T = ~stalling_0; // @[Pipeline.scala:23:27, :27:20] assign io_in_ready_0 = _io_in_ready_T; // @[Pipeline.scala:6:7, :27:20] wire _stalling_1_T = ~io_out_ready_0; // @[Pipeline.scala:6:7, :28:37] assign _stalling_1_T_1 = valids_1 & _stalling_1_T; // @[Pipeline.scala:22:25, :28:{34,37}] assign stalling_1 = _stalling_1_T_1; // @[Pipeline.scala:23:27, :28:34] assign _stalling_0_T = valids_0 & stalling_1; // @[Pipeline.scala:22:25, :23:27, :30:16] assign stalling_0 = _stalling_0_T; // @[Pipeline.scala:23:27, :30:16] wire _T_2 = io_in_ready_0 & io_in_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Pipeline.scala:6:7] if (_T_2) begin // @[Decoupled.scala:51:35] stages_0_cmd_inst_funct <= io_in_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7, :21:21] stages_0_cmd_rs1 <= io_in_bits_cmd_rs1_0; // @[Pipeline.scala:6:7, :21:21] stages_0_dram_addr <= io_in_bits_dram_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_spad_addr <= io_in_bits_spad_addr_0; // @[Pipeline.scala:6:7, :21:21] stages_0_I <= io_in_bits_I_0; // @[Pipeline.scala:6:7, :21:21] stages_0_J <= io_in_bits_J_0; // @[Pipeline.scala:6:7, :21:21] end if (stalling_1) begin // @[Pipeline.scala:23:27] end else begin // @[Pipeline.scala:23:27] stages_1_cmd_inst_funct <= stages_0_cmd_inst_funct; // @[Pipeline.scala:21:21] stages_1_cmd_inst_rs2 <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_rs1 <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_rd <= 5'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_inst_opcode <= 7'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_rs1 <= stages_0_cmd_rs1; // @[Pipeline.scala:21:21] stages_1_cmd_rs2 <= 64'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_isa <= 32'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_dprv <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_prv <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_zero2 <= 23'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_sxl <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_uxl <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_zero1 <= 8'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_xs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_fs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_mpp <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_cmd_status_vs <= 2'h0; // @[Pipeline.scala:6:7, :7:14, :21:21] stages_1_dram_addr <= stages_0_dram_addr; // @[Pipeline.scala:21:21] stages_1_spad_addr <= stages_0_spad_addr; // @[Pipeline.scala:21:21] stages_1_I <= stages_0_I; // @[Pipeline.scala:21:21] stages_1_J <= stages_0_J; // @[Pipeline.scala:21:21] end stages_1_cmd_inst_xd <= stalling_1 & stages_1_cmd_inst_xd; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_inst_xs1 <= stalling_1 & stages_1_cmd_inst_xs1; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_inst_xs2 <= stalling_1 & stages_1_cmd_inst_xs2; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_debug <= stalling_1 & stages_1_cmd_status_debug; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_cease <= stalling_1 & stages_1_cmd_status_cease; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_wfi <= stalling_1 & stages_1_cmd_status_wfi; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_dv <= stalling_1 & stages_1_cmd_status_dv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_v <= stalling_1 & stages_1_cmd_status_v; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sd <= stalling_1 & stages_1_cmd_status_sd; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mpv <= stalling_1 & stages_1_cmd_status_mpv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_gva <= stalling_1 & stages_1_cmd_status_gva; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mbe <= stalling_1 & stages_1_cmd_status_mbe; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sbe <= stalling_1 & stages_1_cmd_status_sbe; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sd_rv32 <= stalling_1 & stages_1_cmd_status_sd_rv32; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tsr <= stalling_1 & stages_1_cmd_status_tsr; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tw <= stalling_1 & stages_1_cmd_status_tw; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_tvm <= stalling_1 & stages_1_cmd_status_tvm; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mxr <= stalling_1 & stages_1_cmd_status_mxr; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sum <= stalling_1 & stages_1_cmd_status_sum; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mprv <= stalling_1 & stages_1_cmd_status_mprv; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_spp <= stalling_1 & stages_1_cmd_status_spp; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mpie <= stalling_1 & stages_1_cmd_status_mpie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_ube <= stalling_1 & stages_1_cmd_status_ube; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_spie <= stalling_1 & stages_1_cmd_status_spie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_upie <= stalling_1 & stages_1_cmd_status_upie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_mie <= stalling_1 & stages_1_cmd_status_mie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_hie <= stalling_1 & stages_1_cmd_status_hie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_sie <= stalling_1 & stages_1_cmd_status_sie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] stages_1_cmd_status_uie <= stalling_1 & stages_1_cmd_status_uie; // @[Pipeline.scala:21:21, :23:27, :60:17, :61:13] if (reset) begin // @[Pipeline.scala:6:7] valids_0 <= 1'h0; // @[Pipeline.scala:22:25] valids_1 <= 1'h0; // @[Pipeline.scala:22:25] end else begin // @[Pipeline.scala:6:7] valids_0 <= _T_2 | stalling_1 & valids_0; // @[Decoupled.scala:51:35] valids_1 <= valids_0 | ~io_out_ready_0 & valids_1; // @[Pipeline.scala:6:7, :22:25, :36:24, :37:19, :49:16, :50:12] end always @(posedge) assign io_in_ready = io_in_ready_0; // @[Pipeline.scala:6:7] assign io_out_valid = io_out_valid_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_funct = io_out_bits_cmd_inst_funct_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rs2 = io_out_bits_cmd_inst_rs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rs1 = io_out_bits_cmd_inst_rs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xd = io_out_bits_cmd_inst_xd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xs1 = io_out_bits_cmd_inst_xs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_xs2 = io_out_bits_cmd_inst_xs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_rd = io_out_bits_cmd_inst_rd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_inst_opcode = io_out_bits_cmd_inst_opcode_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_rs1 = io_out_bits_cmd_rs1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_rs2 = io_out_bits_cmd_rs2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_debug = io_out_bits_cmd_status_debug_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_cease = io_out_bits_cmd_status_cease_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_wfi = io_out_bits_cmd_status_wfi_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_isa = io_out_bits_cmd_status_isa_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_dprv = io_out_bits_cmd_status_dprv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_dv = io_out_bits_cmd_status_dv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_prv = io_out_bits_cmd_status_prv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_v = io_out_bits_cmd_status_v_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sd = io_out_bits_cmd_status_sd_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_zero2 = io_out_bits_cmd_status_zero2_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpv = io_out_bits_cmd_status_mpv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_gva = io_out_bits_cmd_status_gva_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mbe = io_out_bits_cmd_status_mbe_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sbe = io_out_bits_cmd_status_sbe_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sxl = io_out_bits_cmd_status_sxl_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_uxl = io_out_bits_cmd_status_uxl_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sd_rv32 = io_out_bits_cmd_status_sd_rv32_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_zero1 = io_out_bits_cmd_status_zero1_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tsr = io_out_bits_cmd_status_tsr_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tw = io_out_bits_cmd_status_tw_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_tvm = io_out_bits_cmd_status_tvm_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mxr = io_out_bits_cmd_status_mxr_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sum = io_out_bits_cmd_status_sum_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mprv = io_out_bits_cmd_status_mprv_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_xs = io_out_bits_cmd_status_xs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_fs = io_out_bits_cmd_status_fs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpp = io_out_bits_cmd_status_mpp_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_vs = io_out_bits_cmd_status_vs_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_spp = io_out_bits_cmd_status_spp_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mpie = io_out_bits_cmd_status_mpie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_ube = io_out_bits_cmd_status_ube_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_spie = io_out_bits_cmd_status_spie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_upie = io_out_bits_cmd_status_upie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_mie = io_out_bits_cmd_status_mie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_hie = io_out_bits_cmd_status_hie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_sie = io_out_bits_cmd_status_sie_0; // @[Pipeline.scala:6:7] assign io_out_bits_cmd_status_uie = io_out_bits_cmd_status_uie_0; // @[Pipeline.scala:6:7] assign io_out_bits_dram_addr = io_out_bits_dram_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_spad_addr = io_out_bits_spad_addr_0; // @[Pipeline.scala:6:7] assign io_out_bits_I = io_out_bits_I_0; // @[Pipeline.scala:6:7] assign io_out_bits_J = io_out_bits_J_0; // @[Pipeline.scala:6:7] assign io_busy = io_busy_0; // @[Pipeline.scala:6:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_101 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_sink_valid_1 of AsyncResetSynchronizerShiftReg_w1_d3_i0_114 connect io_out_sink_valid_1.clock, clock connect io_out_sink_valid_1.reset, reset connect io_out_sink_valid_1.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_sink_valid_1.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_101( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_114 io_out_sink_valid_1 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_48 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<3>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}}, flip vcalloc_resp : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}, flip out_credit_available : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}, out_virt_channel : UInt<3>}}[1], debug : { va_stall : UInt<3>, sa_stall : UInt<3>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], flip credit_return : UInt<8>, flip vc_free : UInt<8>}} inst input_buffer of InputBuffer_48 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) connect input_buffer.io.deq[3].ready, UInt<1>(0h0) connect input_buffer.io.deq[4].ready, UInt<1>(0h0) connect input_buffer.io.deq[5].ready, UInt<1>(0h0) connect input_buffer.io.deq[6].ready, UInt<1>(0h0) connect input_buffer.io.deq[7].ready, UInt<1>(0h0) inst route_arbiter of Arbiter8_RouteComputerReq_48 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, fifo_deps : UInt<8>}[8], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<4>(0h8)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<5>(0h18)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[3], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[4], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[5], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[6], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[7], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow connect route_arbiter.io.in[0].valid, UInt<1>(0h0) invalidate route_arbiter.io.in[0].bits.flow.egress_node_id invalidate route_arbiter.io.in[0].bits.flow.egress_node invalidate route_arbiter.io.in[0].bits.flow.ingress_node_id invalidate route_arbiter.io.in[0].bits.flow.ingress_node invalidate route_arbiter.io.in[0].bits.flow.vnet_id invalidate route_arbiter.io.in[0].bits.src_virt_id node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_9 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_9 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_10 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_10 : connect states[2].g, UInt<3>(0h2) node _route_arbiter_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h1)) connect route_arbiter.io.in[3].valid, _route_arbiter_io_in_3_valid_T connect route_arbiter.io.in[3].bits.flow.egress_node_id, states[3].flow.egress_node_id connect route_arbiter.io.in[3].bits.flow.egress_node, states[3].flow.egress_node connect route_arbiter.io.in[3].bits.flow.ingress_node_id, states[3].flow.ingress_node_id connect route_arbiter.io.in[3].bits.flow.ingress_node, states[3].flow.ingress_node connect route_arbiter.io.in[3].bits.flow.vnet_id, states[3].flow.vnet_id connect route_arbiter.io.in[3].bits.src_virt_id, UInt<2>(0h3) node _T_11 = and(route_arbiter.io.in[3].ready, route_arbiter.io.in[3].valid) when _T_11 : connect states[3].g, UInt<3>(0h2) node _route_arbiter_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h1)) connect route_arbiter.io.in[4].valid, _route_arbiter_io_in_4_valid_T connect route_arbiter.io.in[4].bits.flow.egress_node_id, states[4].flow.egress_node_id connect route_arbiter.io.in[4].bits.flow.egress_node, states[4].flow.egress_node connect route_arbiter.io.in[4].bits.flow.ingress_node_id, states[4].flow.ingress_node_id connect route_arbiter.io.in[4].bits.flow.ingress_node, states[4].flow.ingress_node connect route_arbiter.io.in[4].bits.flow.vnet_id, states[4].flow.vnet_id connect route_arbiter.io.in[4].bits.src_virt_id, UInt<3>(0h4) node _T_12 = and(route_arbiter.io.in[4].ready, route_arbiter.io.in[4].valid) when _T_12 : connect states[4].g, UInt<3>(0h2) node _route_arbiter_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h1)) connect route_arbiter.io.in[5].valid, _route_arbiter_io_in_5_valid_T connect route_arbiter.io.in[5].bits.flow.egress_node_id, states[5].flow.egress_node_id connect route_arbiter.io.in[5].bits.flow.egress_node, states[5].flow.egress_node connect route_arbiter.io.in[5].bits.flow.ingress_node_id, states[5].flow.ingress_node_id connect route_arbiter.io.in[5].bits.flow.ingress_node, states[5].flow.ingress_node connect route_arbiter.io.in[5].bits.flow.vnet_id, states[5].flow.vnet_id connect route_arbiter.io.in[5].bits.src_virt_id, UInt<3>(0h5) node _T_13 = and(route_arbiter.io.in[5].ready, route_arbiter.io.in[5].valid) when _T_13 : connect states[5].g, UInt<3>(0h2) node _route_arbiter_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h1)) connect route_arbiter.io.in[6].valid, _route_arbiter_io_in_6_valid_T connect route_arbiter.io.in[6].bits.flow.egress_node_id, states[6].flow.egress_node_id connect route_arbiter.io.in[6].bits.flow.egress_node, states[6].flow.egress_node connect route_arbiter.io.in[6].bits.flow.ingress_node_id, states[6].flow.ingress_node_id connect route_arbiter.io.in[6].bits.flow.ingress_node, states[6].flow.ingress_node connect route_arbiter.io.in[6].bits.flow.vnet_id, states[6].flow.vnet_id connect route_arbiter.io.in[6].bits.src_virt_id, UInt<3>(0h6) node _T_14 = and(route_arbiter.io.in[6].ready, route_arbiter.io.in[6].valid) when _T_14 : connect states[6].g, UInt<3>(0h2) node _route_arbiter_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h1)) connect route_arbiter.io.in[7].valid, _route_arbiter_io_in_7_valid_T connect route_arbiter.io.in[7].bits.flow.egress_node_id, states[7].flow.egress_node_id connect route_arbiter.io.in[7].bits.flow.egress_node, states[7].flow.egress_node connect route_arbiter.io.in[7].bits.flow.ingress_node_id, states[7].flow.ingress_node_id connect route_arbiter.io.in[7].bits.flow.ingress_node, states[7].flow.ingress_node connect route_arbiter.io.in[7].bits.flow.vnet_id, states[7].flow.vnet_id connect route_arbiter.io.in[7].bits.src_virt_id, UInt<3>(0h7) node _T_15 = and(route_arbiter.io.in[7].ready, route_arbiter.io.in[7].valid) when _T_15 : connect states[7].g, UInt<3>(0h2) node _T_16 = and(io.router_req.ready, io.router_req.valid) when _T_16 : node _T_17 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_18 = asUInt(reset) node _T_19 = eq(_T_18, UInt<1>(0h0)) when _T_19 : node _T_20 = eq(_T_17, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_17, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_21 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_21 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_22 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_22 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_23 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_23 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_24 = eq(UInt<2>(0h3), io.router_req.bits.src_virt_id) when _T_24 : connect states[3].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_25 = eq(UInt<3>(0h4), io.router_req.bits.src_virt_id) when _T_25 : connect states[4].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_26 = eq(UInt<3>(0h5), io.router_req.bits.src_virt_id) when _T_26 : connect states[5].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_27 = eq(UInt<3>(0h6), io.router_req.bits.src_virt_id) when _T_27 : connect states[6].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.router_resp.vc_sel.`2` node _T_28 = eq(UInt<3>(0h7), io.router_req.bits.src_virt_id) when _T_28 : connect states[7].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.router_resp.vc_sel.`2` regreset mask : UInt<8>, clock, reset, UInt<8>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}}[8] wire vcalloc_vals : UInt<1>[8] node vcalloc_filter_lo_lo = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo = cat(vcalloc_filter_lo_hi, vcalloc_filter_lo_lo) node vcalloc_filter_hi_lo = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi = cat(vcalloc_filter_hi_hi, vcalloc_filter_hi_lo) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_filter_lo) node vcalloc_filter_lo_lo_1 = cat(vcalloc_vals[1], vcalloc_vals[0]) node vcalloc_filter_lo_hi_1 = cat(vcalloc_vals[3], vcalloc_vals[2]) node vcalloc_filter_lo_1 = cat(vcalloc_filter_lo_hi_1, vcalloc_filter_lo_lo_1) node vcalloc_filter_hi_lo_1 = cat(vcalloc_vals[5], vcalloc_vals[4]) node vcalloc_filter_hi_hi_1 = cat(vcalloc_vals[7], vcalloc_vals[6]) node vcalloc_filter_hi_1 = cat(vcalloc_filter_hi_hi_1, vcalloc_filter_hi_lo_1) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_filter_lo_1) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = bits(_vcalloc_filter_T_4, 6, 6) node _vcalloc_filter_T_12 = bits(_vcalloc_filter_T_4, 7, 7) node _vcalloc_filter_T_13 = bits(_vcalloc_filter_T_4, 8, 8) node _vcalloc_filter_T_14 = bits(_vcalloc_filter_T_4, 9, 9) node _vcalloc_filter_T_15 = bits(_vcalloc_filter_T_4, 10, 10) node _vcalloc_filter_T_16 = bits(_vcalloc_filter_T_4, 11, 11) node _vcalloc_filter_T_17 = bits(_vcalloc_filter_T_4, 12, 12) node _vcalloc_filter_T_18 = bits(_vcalloc_filter_T_4, 13, 13) node _vcalloc_filter_T_19 = bits(_vcalloc_filter_T_4, 14, 14) node _vcalloc_filter_T_20 = bits(_vcalloc_filter_T_4, 15, 15) node _vcalloc_filter_T_21 = mux(_vcalloc_filter_T_20, UInt<16>(0h8000), UInt<16>(0h0)) node _vcalloc_filter_T_22 = mux(_vcalloc_filter_T_19, UInt<16>(0h4000), _vcalloc_filter_T_21) node _vcalloc_filter_T_23 = mux(_vcalloc_filter_T_18, UInt<16>(0h2000), _vcalloc_filter_T_22) node _vcalloc_filter_T_24 = mux(_vcalloc_filter_T_17, UInt<16>(0h1000), _vcalloc_filter_T_23) node _vcalloc_filter_T_25 = mux(_vcalloc_filter_T_16, UInt<16>(0h800), _vcalloc_filter_T_24) node _vcalloc_filter_T_26 = mux(_vcalloc_filter_T_15, UInt<16>(0h400), _vcalloc_filter_T_25) node _vcalloc_filter_T_27 = mux(_vcalloc_filter_T_14, UInt<16>(0h200), _vcalloc_filter_T_26) node _vcalloc_filter_T_28 = mux(_vcalloc_filter_T_13, UInt<16>(0h100), _vcalloc_filter_T_27) node _vcalloc_filter_T_29 = mux(_vcalloc_filter_T_12, UInt<16>(0h80), _vcalloc_filter_T_28) node _vcalloc_filter_T_30 = mux(_vcalloc_filter_T_11, UInt<16>(0h40), _vcalloc_filter_T_29) node _vcalloc_filter_T_31 = mux(_vcalloc_filter_T_10, UInt<16>(0h20), _vcalloc_filter_T_30) node _vcalloc_filter_T_32 = mux(_vcalloc_filter_T_9, UInt<16>(0h10), _vcalloc_filter_T_31) node _vcalloc_filter_T_33 = mux(_vcalloc_filter_T_8, UInt<16>(0h8), _vcalloc_filter_T_32) node _vcalloc_filter_T_34 = mux(_vcalloc_filter_T_7, UInt<16>(0h4), _vcalloc_filter_T_33) node _vcalloc_filter_T_35 = mux(_vcalloc_filter_T_6, UInt<16>(0h2), _vcalloc_filter_T_34) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<16>(0h1), _vcalloc_filter_T_35) node _vcalloc_sel_T = bits(vcalloc_filter, 7, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 8) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_29 = and(io.router_req.ready, io.router_req.valid) when _T_29 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_30 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_31 = or(_T_30, vcalloc_vals[2]) node _T_32 = or(_T_31, vcalloc_vals[3]) node _T_33 = or(_T_32, vcalloc_vals[4]) node _T_34 = or(_T_33, vcalloc_vals[5]) node _T_35 = or(_T_34, vcalloc_vals[6]) node _T_36 = or(_T_35, vcalloc_vals[7]) when _T_36 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = not(UInt<4>(0h0)) node _mask_T_7 = not(UInt<5>(0h0)) node _mask_T_8 = not(UInt<6>(0h0)) node _mask_T_9 = not(UInt<7>(0h0)) node _mask_T_10 = not(UInt<8>(0h0)) node _mask_T_11 = bits(vcalloc_sel, 0, 0) node _mask_T_12 = bits(vcalloc_sel, 1, 1) node _mask_T_13 = bits(vcalloc_sel, 2, 2) node _mask_T_14 = bits(vcalloc_sel, 3, 3) node _mask_T_15 = bits(vcalloc_sel, 4, 4) node _mask_T_16 = bits(vcalloc_sel, 5, 5) node _mask_T_17 = bits(vcalloc_sel, 6, 6) node _mask_T_18 = bits(vcalloc_sel, 7, 7) node _mask_T_19 = mux(_mask_T_11, _mask_T_3, UInt<1>(0h0)) node _mask_T_20 = mux(_mask_T_12, _mask_T_4, UInt<1>(0h0)) node _mask_T_21 = mux(_mask_T_13, _mask_T_5, UInt<1>(0h0)) node _mask_T_22 = mux(_mask_T_14, _mask_T_6, UInt<1>(0h0)) node _mask_T_23 = mux(_mask_T_15, _mask_T_7, UInt<1>(0h0)) node _mask_T_24 = mux(_mask_T_16, _mask_T_8, UInt<1>(0h0)) node _mask_T_25 = mux(_mask_T_17, _mask_T_9, UInt<1>(0h0)) node _mask_T_26 = mux(_mask_T_18, _mask_T_10, UInt<1>(0h0)) node _mask_T_27 = or(_mask_T_19, _mask_T_20) node _mask_T_28 = or(_mask_T_27, _mask_T_21) node _mask_T_29 = or(_mask_T_28, _mask_T_22) node _mask_T_30 = or(_mask_T_29, _mask_T_23) node _mask_T_31 = or(_mask_T_30, _mask_T_24) node _mask_T_32 = or(_mask_T_31, _mask_T_25) node _mask_T_33 = or(_mask_T_32, _mask_T_26) wire _mask_WIRE : UInt<8> connect _mask_WIRE, _mask_T_33 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) node _io_vcalloc_req_valid_T_2 = or(_io_vcalloc_req_valid_T_1, vcalloc_vals[3]) node _io_vcalloc_req_valid_T_3 = or(_io_vcalloc_req_valid_T_2, vcalloc_vals[4]) node _io_vcalloc_req_valid_T_4 = or(_io_vcalloc_req_valid_T_3, vcalloc_vals[5]) node _io_vcalloc_req_valid_T_5 = or(_io_vcalloc_req_valid_T_4, vcalloc_vals[6]) node _io_vcalloc_req_valid_T_6 = or(_io_vcalloc_req_valid_T_5, vcalloc_vals[7]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_6 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) node _io_vcalloc_req_bits_T_3 = bits(vcalloc_sel, 3, 3) node _io_vcalloc_req_bits_T_4 = bits(vcalloc_sel, 4, 4) node _io_vcalloc_req_bits_T_5 = bits(vcalloc_sel, 5, 5) node _io_vcalloc_req_bits_T_6 = bits(vcalloc_sel, 6, 6) node _io_vcalloc_req_bits_T_7 = bits(vcalloc_sel, 7, 7) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, in_vc : UInt<3>, vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]}} wire _io_vcalloc_req_bits_WIRE_1 : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[8] node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_12 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_10) node _io_vcalloc_req_bits_T_18 = or(_io_vcalloc_req_bits_T_17, _io_vcalloc_req_bits_T_11) node _io_vcalloc_req_bits_T_19 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_12) node _io_vcalloc_req_bits_T_20 = or(_io_vcalloc_req_bits_T_19, _io_vcalloc_req_bits_T_13) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_20, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_27 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_25) node _io_vcalloc_req_bits_T_33 = or(_io_vcalloc_req_bits_T_32, _io_vcalloc_req_bits_T_26) node _io_vcalloc_req_bits_T_34 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_27) node _io_vcalloc_req_bits_T_35 = or(_io_vcalloc_req_bits_T_34, _io_vcalloc_req_bits_T_28) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_35, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_42 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_40) node _io_vcalloc_req_bits_T_48 = or(_io_vcalloc_req_bits_T_47, _io_vcalloc_req_bits_T_41) node _io_vcalloc_req_bits_T_49 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_42) node _io_vcalloc_req_bits_T_50 = or(_io_vcalloc_req_bits_T_49, _io_vcalloc_req_bits_T_43) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_50, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_57 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_55) node _io_vcalloc_req_bits_T_63 = or(_io_vcalloc_req_bits_T_62, _io_vcalloc_req_bits_T_56) node _io_vcalloc_req_bits_T_64 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_57) node _io_vcalloc_req_bits_T_65 = or(_io_vcalloc_req_bits_T_64, _io_vcalloc_req_bits_T_58) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_65, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_6 : UInt<1> connect _io_vcalloc_req_bits_WIRE_6, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_2[3], _io_vcalloc_req_bits_WIRE_6 node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_72 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_70) node _io_vcalloc_req_bits_T_78 = or(_io_vcalloc_req_bits_T_77, _io_vcalloc_req_bits_T_71) node _io_vcalloc_req_bits_T_79 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_72) node _io_vcalloc_req_bits_T_80 = or(_io_vcalloc_req_bits_T_79, _io_vcalloc_req_bits_T_73) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_80, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_2[4], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_87 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_85) node _io_vcalloc_req_bits_T_93 = or(_io_vcalloc_req_bits_T_92, _io_vcalloc_req_bits_T_86) node _io_vcalloc_req_bits_T_94 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_87) node _io_vcalloc_req_bits_T_95 = or(_io_vcalloc_req_bits_T_94, _io_vcalloc_req_bits_T_88) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_95, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_2[5], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_102 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_103 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_104 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_105 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_106 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_107 = or(_io_vcalloc_req_bits_T_106, _io_vcalloc_req_bits_T_100) node _io_vcalloc_req_bits_T_108 = or(_io_vcalloc_req_bits_T_107, _io_vcalloc_req_bits_T_101) node _io_vcalloc_req_bits_T_109 = or(_io_vcalloc_req_bits_T_108, _io_vcalloc_req_bits_T_102) node _io_vcalloc_req_bits_T_110 = or(_io_vcalloc_req_bits_T_109, _io_vcalloc_req_bits_T_103) node _io_vcalloc_req_bits_T_111 = or(_io_vcalloc_req_bits_T_110, _io_vcalloc_req_bits_T_104) node _io_vcalloc_req_bits_T_112 = or(_io_vcalloc_req_bits_T_111, _io_vcalloc_req_bits_T_105) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_112 connect _io_vcalloc_req_bits_WIRE_2[6], _io_vcalloc_req_bits_WIRE_9 node _io_vcalloc_req_bits_T_113 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_114 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_115 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_116 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_117 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_118 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_119 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_120 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`0`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_121 = or(_io_vcalloc_req_bits_T_113, _io_vcalloc_req_bits_T_114) node _io_vcalloc_req_bits_T_122 = or(_io_vcalloc_req_bits_T_121, _io_vcalloc_req_bits_T_115) node _io_vcalloc_req_bits_T_123 = or(_io_vcalloc_req_bits_T_122, _io_vcalloc_req_bits_T_116) node _io_vcalloc_req_bits_T_124 = or(_io_vcalloc_req_bits_T_123, _io_vcalloc_req_bits_T_117) node _io_vcalloc_req_bits_T_125 = or(_io_vcalloc_req_bits_T_124, _io_vcalloc_req_bits_T_118) node _io_vcalloc_req_bits_T_126 = or(_io_vcalloc_req_bits_T_125, _io_vcalloc_req_bits_T_119) node _io_vcalloc_req_bits_T_127 = or(_io_vcalloc_req_bits_T_126, _io_vcalloc_req_bits_T_120) wire _io_vcalloc_req_bits_WIRE_10 : UInt<1> connect _io_vcalloc_req_bits_WIRE_10, _io_vcalloc_req_bits_T_127 connect _io_vcalloc_req_bits_WIRE_2[7], _io_vcalloc_req_bits_WIRE_10 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_11 : UInt<1>[8] node _io_vcalloc_req_bits_T_128 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_129 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_130 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_131 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_132 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_133 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_134 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_135 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_136 = or(_io_vcalloc_req_bits_T_128, _io_vcalloc_req_bits_T_129) node _io_vcalloc_req_bits_T_137 = or(_io_vcalloc_req_bits_T_136, _io_vcalloc_req_bits_T_130) node _io_vcalloc_req_bits_T_138 = or(_io_vcalloc_req_bits_T_137, _io_vcalloc_req_bits_T_131) node _io_vcalloc_req_bits_T_139 = or(_io_vcalloc_req_bits_T_138, _io_vcalloc_req_bits_T_132) node _io_vcalloc_req_bits_T_140 = or(_io_vcalloc_req_bits_T_139, _io_vcalloc_req_bits_T_133) node _io_vcalloc_req_bits_T_141 = or(_io_vcalloc_req_bits_T_140, _io_vcalloc_req_bits_T_134) node _io_vcalloc_req_bits_T_142 = or(_io_vcalloc_req_bits_T_141, _io_vcalloc_req_bits_T_135) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_142 connect _io_vcalloc_req_bits_WIRE_11[0], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_143 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_144 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_145 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_146 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_147 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_148 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_149 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_150 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_151 = or(_io_vcalloc_req_bits_T_143, _io_vcalloc_req_bits_T_144) node _io_vcalloc_req_bits_T_152 = or(_io_vcalloc_req_bits_T_151, _io_vcalloc_req_bits_T_145) node _io_vcalloc_req_bits_T_153 = or(_io_vcalloc_req_bits_T_152, _io_vcalloc_req_bits_T_146) node _io_vcalloc_req_bits_T_154 = or(_io_vcalloc_req_bits_T_153, _io_vcalloc_req_bits_T_147) node _io_vcalloc_req_bits_T_155 = or(_io_vcalloc_req_bits_T_154, _io_vcalloc_req_bits_T_148) node _io_vcalloc_req_bits_T_156 = or(_io_vcalloc_req_bits_T_155, _io_vcalloc_req_bits_T_149) node _io_vcalloc_req_bits_T_157 = or(_io_vcalloc_req_bits_T_156, _io_vcalloc_req_bits_T_150) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_157 connect _io_vcalloc_req_bits_WIRE_11[1], _io_vcalloc_req_bits_WIRE_13 node _io_vcalloc_req_bits_T_158 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_159 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_160 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_161 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_162 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_163 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_164 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_165 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_166 = or(_io_vcalloc_req_bits_T_158, _io_vcalloc_req_bits_T_159) node _io_vcalloc_req_bits_T_167 = or(_io_vcalloc_req_bits_T_166, _io_vcalloc_req_bits_T_160) node _io_vcalloc_req_bits_T_168 = or(_io_vcalloc_req_bits_T_167, _io_vcalloc_req_bits_T_161) node _io_vcalloc_req_bits_T_169 = or(_io_vcalloc_req_bits_T_168, _io_vcalloc_req_bits_T_162) node _io_vcalloc_req_bits_T_170 = or(_io_vcalloc_req_bits_T_169, _io_vcalloc_req_bits_T_163) node _io_vcalloc_req_bits_T_171 = or(_io_vcalloc_req_bits_T_170, _io_vcalloc_req_bits_T_164) node _io_vcalloc_req_bits_T_172 = or(_io_vcalloc_req_bits_T_171, _io_vcalloc_req_bits_T_165) wire _io_vcalloc_req_bits_WIRE_14 : UInt<1> connect _io_vcalloc_req_bits_WIRE_14, _io_vcalloc_req_bits_T_172 connect _io_vcalloc_req_bits_WIRE_11[2], _io_vcalloc_req_bits_WIRE_14 node _io_vcalloc_req_bits_T_173 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_174 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_175 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_176 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_177 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_178 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_179 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_180 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_181 = or(_io_vcalloc_req_bits_T_173, _io_vcalloc_req_bits_T_174) node _io_vcalloc_req_bits_T_182 = or(_io_vcalloc_req_bits_T_181, _io_vcalloc_req_bits_T_175) node _io_vcalloc_req_bits_T_183 = or(_io_vcalloc_req_bits_T_182, _io_vcalloc_req_bits_T_176) node _io_vcalloc_req_bits_T_184 = or(_io_vcalloc_req_bits_T_183, _io_vcalloc_req_bits_T_177) node _io_vcalloc_req_bits_T_185 = or(_io_vcalloc_req_bits_T_184, _io_vcalloc_req_bits_T_178) node _io_vcalloc_req_bits_T_186 = or(_io_vcalloc_req_bits_T_185, _io_vcalloc_req_bits_T_179) node _io_vcalloc_req_bits_T_187 = or(_io_vcalloc_req_bits_T_186, _io_vcalloc_req_bits_T_180) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_187 connect _io_vcalloc_req_bits_WIRE_11[3], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_188 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_189 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_190 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_191 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_192 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_193 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_194 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_195 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_196 = or(_io_vcalloc_req_bits_T_188, _io_vcalloc_req_bits_T_189) node _io_vcalloc_req_bits_T_197 = or(_io_vcalloc_req_bits_T_196, _io_vcalloc_req_bits_T_190) node _io_vcalloc_req_bits_T_198 = or(_io_vcalloc_req_bits_T_197, _io_vcalloc_req_bits_T_191) node _io_vcalloc_req_bits_T_199 = or(_io_vcalloc_req_bits_T_198, _io_vcalloc_req_bits_T_192) node _io_vcalloc_req_bits_T_200 = or(_io_vcalloc_req_bits_T_199, _io_vcalloc_req_bits_T_193) node _io_vcalloc_req_bits_T_201 = or(_io_vcalloc_req_bits_T_200, _io_vcalloc_req_bits_T_194) node _io_vcalloc_req_bits_T_202 = or(_io_vcalloc_req_bits_T_201, _io_vcalloc_req_bits_T_195) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_202 connect _io_vcalloc_req_bits_WIRE_11[4], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_203 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_204 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_205 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_206 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_207 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_208 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_209 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_210 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_211 = or(_io_vcalloc_req_bits_T_203, _io_vcalloc_req_bits_T_204) node _io_vcalloc_req_bits_T_212 = or(_io_vcalloc_req_bits_T_211, _io_vcalloc_req_bits_T_205) node _io_vcalloc_req_bits_T_213 = or(_io_vcalloc_req_bits_T_212, _io_vcalloc_req_bits_T_206) node _io_vcalloc_req_bits_T_214 = or(_io_vcalloc_req_bits_T_213, _io_vcalloc_req_bits_T_207) node _io_vcalloc_req_bits_T_215 = or(_io_vcalloc_req_bits_T_214, _io_vcalloc_req_bits_T_208) node _io_vcalloc_req_bits_T_216 = or(_io_vcalloc_req_bits_T_215, _io_vcalloc_req_bits_T_209) node _io_vcalloc_req_bits_T_217 = or(_io_vcalloc_req_bits_T_216, _io_vcalloc_req_bits_T_210) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_217 connect _io_vcalloc_req_bits_WIRE_11[5], _io_vcalloc_req_bits_WIRE_17 node _io_vcalloc_req_bits_T_218 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_219 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_220 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_221 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_222 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_223 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_224 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_225 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_226 = or(_io_vcalloc_req_bits_T_218, _io_vcalloc_req_bits_T_219) node _io_vcalloc_req_bits_T_227 = or(_io_vcalloc_req_bits_T_226, _io_vcalloc_req_bits_T_220) node _io_vcalloc_req_bits_T_228 = or(_io_vcalloc_req_bits_T_227, _io_vcalloc_req_bits_T_221) node _io_vcalloc_req_bits_T_229 = or(_io_vcalloc_req_bits_T_228, _io_vcalloc_req_bits_T_222) node _io_vcalloc_req_bits_T_230 = or(_io_vcalloc_req_bits_T_229, _io_vcalloc_req_bits_T_223) node _io_vcalloc_req_bits_T_231 = or(_io_vcalloc_req_bits_T_230, _io_vcalloc_req_bits_T_224) node _io_vcalloc_req_bits_T_232 = or(_io_vcalloc_req_bits_T_231, _io_vcalloc_req_bits_T_225) wire _io_vcalloc_req_bits_WIRE_18 : UInt<1> connect _io_vcalloc_req_bits_WIRE_18, _io_vcalloc_req_bits_T_232 connect _io_vcalloc_req_bits_WIRE_11[6], _io_vcalloc_req_bits_WIRE_18 node _io_vcalloc_req_bits_T_233 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_234 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_235 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_236 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_237 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_238 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_239 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_240 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`1`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_241 = or(_io_vcalloc_req_bits_T_233, _io_vcalloc_req_bits_T_234) node _io_vcalloc_req_bits_T_242 = or(_io_vcalloc_req_bits_T_241, _io_vcalloc_req_bits_T_235) node _io_vcalloc_req_bits_T_243 = or(_io_vcalloc_req_bits_T_242, _io_vcalloc_req_bits_T_236) node _io_vcalloc_req_bits_T_244 = or(_io_vcalloc_req_bits_T_243, _io_vcalloc_req_bits_T_237) node _io_vcalloc_req_bits_T_245 = or(_io_vcalloc_req_bits_T_244, _io_vcalloc_req_bits_T_238) node _io_vcalloc_req_bits_T_246 = or(_io_vcalloc_req_bits_T_245, _io_vcalloc_req_bits_T_239) node _io_vcalloc_req_bits_T_247 = or(_io_vcalloc_req_bits_T_246, _io_vcalloc_req_bits_T_240) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_247 connect _io_vcalloc_req_bits_WIRE_11[7], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_11 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[8] node _io_vcalloc_req_bits_T_248 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_249 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_250 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_251 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_252 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_253 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_254 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_255 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_256 = or(_io_vcalloc_req_bits_T_248, _io_vcalloc_req_bits_T_249) node _io_vcalloc_req_bits_T_257 = or(_io_vcalloc_req_bits_T_256, _io_vcalloc_req_bits_T_250) node _io_vcalloc_req_bits_T_258 = or(_io_vcalloc_req_bits_T_257, _io_vcalloc_req_bits_T_251) node _io_vcalloc_req_bits_T_259 = or(_io_vcalloc_req_bits_T_258, _io_vcalloc_req_bits_T_252) node _io_vcalloc_req_bits_T_260 = or(_io_vcalloc_req_bits_T_259, _io_vcalloc_req_bits_T_253) node _io_vcalloc_req_bits_T_261 = or(_io_vcalloc_req_bits_T_260, _io_vcalloc_req_bits_T_254) node _io_vcalloc_req_bits_T_262 = or(_io_vcalloc_req_bits_T_261, _io_vcalloc_req_bits_T_255) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_262 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 node _io_vcalloc_req_bits_T_263 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_264 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_265 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_266 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_267 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_268 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_269 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_270 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_271 = or(_io_vcalloc_req_bits_T_263, _io_vcalloc_req_bits_T_264) node _io_vcalloc_req_bits_T_272 = or(_io_vcalloc_req_bits_T_271, _io_vcalloc_req_bits_T_265) node _io_vcalloc_req_bits_T_273 = or(_io_vcalloc_req_bits_T_272, _io_vcalloc_req_bits_T_266) node _io_vcalloc_req_bits_T_274 = or(_io_vcalloc_req_bits_T_273, _io_vcalloc_req_bits_T_267) node _io_vcalloc_req_bits_T_275 = or(_io_vcalloc_req_bits_T_274, _io_vcalloc_req_bits_T_268) node _io_vcalloc_req_bits_T_276 = or(_io_vcalloc_req_bits_T_275, _io_vcalloc_req_bits_T_269) node _io_vcalloc_req_bits_T_277 = or(_io_vcalloc_req_bits_T_276, _io_vcalloc_req_bits_T_270) wire _io_vcalloc_req_bits_WIRE_22 : UInt<1> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_277 connect _io_vcalloc_req_bits_WIRE_20[1], _io_vcalloc_req_bits_WIRE_22 node _io_vcalloc_req_bits_T_278 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_279 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_280 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_281 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_282 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_283 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_284 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_285 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_286 = or(_io_vcalloc_req_bits_T_278, _io_vcalloc_req_bits_T_279) node _io_vcalloc_req_bits_T_287 = or(_io_vcalloc_req_bits_T_286, _io_vcalloc_req_bits_T_280) node _io_vcalloc_req_bits_T_288 = or(_io_vcalloc_req_bits_T_287, _io_vcalloc_req_bits_T_281) node _io_vcalloc_req_bits_T_289 = or(_io_vcalloc_req_bits_T_288, _io_vcalloc_req_bits_T_282) node _io_vcalloc_req_bits_T_290 = or(_io_vcalloc_req_bits_T_289, _io_vcalloc_req_bits_T_283) node _io_vcalloc_req_bits_T_291 = or(_io_vcalloc_req_bits_T_290, _io_vcalloc_req_bits_T_284) node _io_vcalloc_req_bits_T_292 = or(_io_vcalloc_req_bits_T_291, _io_vcalloc_req_bits_T_285) wire _io_vcalloc_req_bits_WIRE_23 : UInt<1> connect _io_vcalloc_req_bits_WIRE_23, _io_vcalloc_req_bits_T_292 connect _io_vcalloc_req_bits_WIRE_20[2], _io_vcalloc_req_bits_WIRE_23 node _io_vcalloc_req_bits_T_293 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_294 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_295 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_296 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_297 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_298 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_299 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_300 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[3], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_301 = or(_io_vcalloc_req_bits_T_293, _io_vcalloc_req_bits_T_294) node _io_vcalloc_req_bits_T_302 = or(_io_vcalloc_req_bits_T_301, _io_vcalloc_req_bits_T_295) node _io_vcalloc_req_bits_T_303 = or(_io_vcalloc_req_bits_T_302, _io_vcalloc_req_bits_T_296) node _io_vcalloc_req_bits_T_304 = or(_io_vcalloc_req_bits_T_303, _io_vcalloc_req_bits_T_297) node _io_vcalloc_req_bits_T_305 = or(_io_vcalloc_req_bits_T_304, _io_vcalloc_req_bits_T_298) node _io_vcalloc_req_bits_T_306 = or(_io_vcalloc_req_bits_T_305, _io_vcalloc_req_bits_T_299) node _io_vcalloc_req_bits_T_307 = or(_io_vcalloc_req_bits_T_306, _io_vcalloc_req_bits_T_300) wire _io_vcalloc_req_bits_WIRE_24 : UInt<1> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_307 connect _io_vcalloc_req_bits_WIRE_20[3], _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_308 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_309 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_310 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_311 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_312 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_313 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_314 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_315 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[4], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_316 = or(_io_vcalloc_req_bits_T_308, _io_vcalloc_req_bits_T_309) node _io_vcalloc_req_bits_T_317 = or(_io_vcalloc_req_bits_T_316, _io_vcalloc_req_bits_T_310) node _io_vcalloc_req_bits_T_318 = or(_io_vcalloc_req_bits_T_317, _io_vcalloc_req_bits_T_311) node _io_vcalloc_req_bits_T_319 = or(_io_vcalloc_req_bits_T_318, _io_vcalloc_req_bits_T_312) node _io_vcalloc_req_bits_T_320 = or(_io_vcalloc_req_bits_T_319, _io_vcalloc_req_bits_T_313) node _io_vcalloc_req_bits_T_321 = or(_io_vcalloc_req_bits_T_320, _io_vcalloc_req_bits_T_314) node _io_vcalloc_req_bits_T_322 = or(_io_vcalloc_req_bits_T_321, _io_vcalloc_req_bits_T_315) wire _io_vcalloc_req_bits_WIRE_25 : UInt<1> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_322 connect _io_vcalloc_req_bits_WIRE_20[4], _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_323 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_324 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_325 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_326 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_327 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_328 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_329 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_330 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[5], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_331 = or(_io_vcalloc_req_bits_T_323, _io_vcalloc_req_bits_T_324) node _io_vcalloc_req_bits_T_332 = or(_io_vcalloc_req_bits_T_331, _io_vcalloc_req_bits_T_325) node _io_vcalloc_req_bits_T_333 = or(_io_vcalloc_req_bits_T_332, _io_vcalloc_req_bits_T_326) node _io_vcalloc_req_bits_T_334 = or(_io_vcalloc_req_bits_T_333, _io_vcalloc_req_bits_T_327) node _io_vcalloc_req_bits_T_335 = or(_io_vcalloc_req_bits_T_334, _io_vcalloc_req_bits_T_328) node _io_vcalloc_req_bits_T_336 = or(_io_vcalloc_req_bits_T_335, _io_vcalloc_req_bits_T_329) node _io_vcalloc_req_bits_T_337 = or(_io_vcalloc_req_bits_T_336, _io_vcalloc_req_bits_T_330) wire _io_vcalloc_req_bits_WIRE_26 : UInt<1> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_337 connect _io_vcalloc_req_bits_WIRE_20[5], _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_338 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_339 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_340 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_341 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_342 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_343 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_344 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_345 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[6], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_346 = or(_io_vcalloc_req_bits_T_338, _io_vcalloc_req_bits_T_339) node _io_vcalloc_req_bits_T_347 = or(_io_vcalloc_req_bits_T_346, _io_vcalloc_req_bits_T_340) node _io_vcalloc_req_bits_T_348 = or(_io_vcalloc_req_bits_T_347, _io_vcalloc_req_bits_T_341) node _io_vcalloc_req_bits_T_349 = or(_io_vcalloc_req_bits_T_348, _io_vcalloc_req_bits_T_342) node _io_vcalloc_req_bits_T_350 = or(_io_vcalloc_req_bits_T_349, _io_vcalloc_req_bits_T_343) node _io_vcalloc_req_bits_T_351 = or(_io_vcalloc_req_bits_T_350, _io_vcalloc_req_bits_T_344) node _io_vcalloc_req_bits_T_352 = or(_io_vcalloc_req_bits_T_351, _io_vcalloc_req_bits_T_345) wire _io_vcalloc_req_bits_WIRE_27 : UInt<1> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_352 connect _io_vcalloc_req_bits_WIRE_20[6], _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_353 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_354 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_355 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_356 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_357 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_358 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_359 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_360 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].vc_sel.`2`[7], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_361 = or(_io_vcalloc_req_bits_T_353, _io_vcalloc_req_bits_T_354) node _io_vcalloc_req_bits_T_362 = or(_io_vcalloc_req_bits_T_361, _io_vcalloc_req_bits_T_355) node _io_vcalloc_req_bits_T_363 = or(_io_vcalloc_req_bits_T_362, _io_vcalloc_req_bits_T_356) node _io_vcalloc_req_bits_T_364 = or(_io_vcalloc_req_bits_T_363, _io_vcalloc_req_bits_T_357) node _io_vcalloc_req_bits_T_365 = or(_io_vcalloc_req_bits_T_364, _io_vcalloc_req_bits_T_358) node _io_vcalloc_req_bits_T_366 = or(_io_vcalloc_req_bits_T_365, _io_vcalloc_req_bits_T_359) node _io_vcalloc_req_bits_T_367 = or(_io_vcalloc_req_bits_T_366, _io_vcalloc_req_bits_T_360) wire _io_vcalloc_req_bits_WIRE_28 : UInt<1> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_367 connect _io_vcalloc_req_bits_WIRE_20[7], _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_20 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_368 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_369 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_370 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_371 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_372 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_373 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_374 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_375 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_376 = or(_io_vcalloc_req_bits_T_368, _io_vcalloc_req_bits_T_369) node _io_vcalloc_req_bits_T_377 = or(_io_vcalloc_req_bits_T_376, _io_vcalloc_req_bits_T_370) node _io_vcalloc_req_bits_T_378 = or(_io_vcalloc_req_bits_T_377, _io_vcalloc_req_bits_T_371) node _io_vcalloc_req_bits_T_379 = or(_io_vcalloc_req_bits_T_378, _io_vcalloc_req_bits_T_372) node _io_vcalloc_req_bits_T_380 = or(_io_vcalloc_req_bits_T_379, _io_vcalloc_req_bits_T_373) node _io_vcalloc_req_bits_T_381 = or(_io_vcalloc_req_bits_T_380, _io_vcalloc_req_bits_T_374) node _io_vcalloc_req_bits_T_382 = or(_io_vcalloc_req_bits_T_381, _io_vcalloc_req_bits_T_375) wire _io_vcalloc_req_bits_WIRE_29 : UInt<3> connect _io_vcalloc_req_bits_WIRE_29, _io_vcalloc_req_bits_T_382 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_29 wire _io_vcalloc_req_bits_WIRE_30 : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_383 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_384 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_385 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_386 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_387 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_388 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_389 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_390 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_391 = or(_io_vcalloc_req_bits_T_383, _io_vcalloc_req_bits_T_384) node _io_vcalloc_req_bits_T_392 = or(_io_vcalloc_req_bits_T_391, _io_vcalloc_req_bits_T_385) node _io_vcalloc_req_bits_T_393 = or(_io_vcalloc_req_bits_T_392, _io_vcalloc_req_bits_T_386) node _io_vcalloc_req_bits_T_394 = or(_io_vcalloc_req_bits_T_393, _io_vcalloc_req_bits_T_387) node _io_vcalloc_req_bits_T_395 = or(_io_vcalloc_req_bits_T_394, _io_vcalloc_req_bits_T_388) node _io_vcalloc_req_bits_T_396 = or(_io_vcalloc_req_bits_T_395, _io_vcalloc_req_bits_T_389) node _io_vcalloc_req_bits_T_397 = or(_io_vcalloc_req_bits_T_396, _io_vcalloc_req_bits_T_390) wire _io_vcalloc_req_bits_WIRE_31 : UInt<2> connect _io_vcalloc_req_bits_WIRE_31, _io_vcalloc_req_bits_T_397 connect _io_vcalloc_req_bits_WIRE_30.egress_node_id, _io_vcalloc_req_bits_WIRE_31 node _io_vcalloc_req_bits_T_398 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_399 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_400 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_401 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_402 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_403 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_404 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_405 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_406 = or(_io_vcalloc_req_bits_T_398, _io_vcalloc_req_bits_T_399) node _io_vcalloc_req_bits_T_407 = or(_io_vcalloc_req_bits_T_406, _io_vcalloc_req_bits_T_400) node _io_vcalloc_req_bits_T_408 = or(_io_vcalloc_req_bits_T_407, _io_vcalloc_req_bits_T_401) node _io_vcalloc_req_bits_T_409 = or(_io_vcalloc_req_bits_T_408, _io_vcalloc_req_bits_T_402) node _io_vcalloc_req_bits_T_410 = or(_io_vcalloc_req_bits_T_409, _io_vcalloc_req_bits_T_403) node _io_vcalloc_req_bits_T_411 = or(_io_vcalloc_req_bits_T_410, _io_vcalloc_req_bits_T_404) node _io_vcalloc_req_bits_T_412 = or(_io_vcalloc_req_bits_T_411, _io_vcalloc_req_bits_T_405) wire _io_vcalloc_req_bits_WIRE_32 : UInt<5> connect _io_vcalloc_req_bits_WIRE_32, _io_vcalloc_req_bits_T_412 connect _io_vcalloc_req_bits_WIRE_30.egress_node, _io_vcalloc_req_bits_WIRE_32 node _io_vcalloc_req_bits_T_413 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_414 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_415 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_416 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_417 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_418 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_419 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_420 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_421 = or(_io_vcalloc_req_bits_T_413, _io_vcalloc_req_bits_T_414) node _io_vcalloc_req_bits_T_422 = or(_io_vcalloc_req_bits_T_421, _io_vcalloc_req_bits_T_415) node _io_vcalloc_req_bits_T_423 = or(_io_vcalloc_req_bits_T_422, _io_vcalloc_req_bits_T_416) node _io_vcalloc_req_bits_T_424 = or(_io_vcalloc_req_bits_T_423, _io_vcalloc_req_bits_T_417) node _io_vcalloc_req_bits_T_425 = or(_io_vcalloc_req_bits_T_424, _io_vcalloc_req_bits_T_418) node _io_vcalloc_req_bits_T_426 = or(_io_vcalloc_req_bits_T_425, _io_vcalloc_req_bits_T_419) node _io_vcalloc_req_bits_T_427 = or(_io_vcalloc_req_bits_T_426, _io_vcalloc_req_bits_T_420) wire _io_vcalloc_req_bits_WIRE_33 : UInt<2> connect _io_vcalloc_req_bits_WIRE_33, _io_vcalloc_req_bits_T_427 connect _io_vcalloc_req_bits_WIRE_30.ingress_node_id, _io_vcalloc_req_bits_WIRE_33 node _io_vcalloc_req_bits_T_428 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_429 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_430 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_431 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_432 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_433 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_434 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_435 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_436 = or(_io_vcalloc_req_bits_T_428, _io_vcalloc_req_bits_T_429) node _io_vcalloc_req_bits_T_437 = or(_io_vcalloc_req_bits_T_436, _io_vcalloc_req_bits_T_430) node _io_vcalloc_req_bits_T_438 = or(_io_vcalloc_req_bits_T_437, _io_vcalloc_req_bits_T_431) node _io_vcalloc_req_bits_T_439 = or(_io_vcalloc_req_bits_T_438, _io_vcalloc_req_bits_T_432) node _io_vcalloc_req_bits_T_440 = or(_io_vcalloc_req_bits_T_439, _io_vcalloc_req_bits_T_433) node _io_vcalloc_req_bits_T_441 = or(_io_vcalloc_req_bits_T_440, _io_vcalloc_req_bits_T_434) node _io_vcalloc_req_bits_T_442 = or(_io_vcalloc_req_bits_T_441, _io_vcalloc_req_bits_T_435) wire _io_vcalloc_req_bits_WIRE_34 : UInt<5> connect _io_vcalloc_req_bits_WIRE_34, _io_vcalloc_req_bits_T_442 connect _io_vcalloc_req_bits_WIRE_30.ingress_node, _io_vcalloc_req_bits_WIRE_34 node _io_vcalloc_req_bits_T_443 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_444 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_445 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_446 = mux(_io_vcalloc_req_bits_T_3, vcalloc_reqs[3].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_447 = mux(_io_vcalloc_req_bits_T_4, vcalloc_reqs[4].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_448 = mux(_io_vcalloc_req_bits_T_5, vcalloc_reqs[5].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_449 = mux(_io_vcalloc_req_bits_T_6, vcalloc_reqs[6].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_450 = mux(_io_vcalloc_req_bits_T_7, vcalloc_reqs[7].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_451 = or(_io_vcalloc_req_bits_T_443, _io_vcalloc_req_bits_T_444) node _io_vcalloc_req_bits_T_452 = or(_io_vcalloc_req_bits_T_451, _io_vcalloc_req_bits_T_445) node _io_vcalloc_req_bits_T_453 = or(_io_vcalloc_req_bits_T_452, _io_vcalloc_req_bits_T_446) node _io_vcalloc_req_bits_T_454 = or(_io_vcalloc_req_bits_T_453, _io_vcalloc_req_bits_T_447) node _io_vcalloc_req_bits_T_455 = or(_io_vcalloc_req_bits_T_454, _io_vcalloc_req_bits_T_448) node _io_vcalloc_req_bits_T_456 = or(_io_vcalloc_req_bits_T_455, _io_vcalloc_req_bits_T_449) node _io_vcalloc_req_bits_T_457 = or(_io_vcalloc_req_bits_T_456, _io_vcalloc_req_bits_T_450) wire _io_vcalloc_req_bits_WIRE_35 : UInt<3> connect _io_vcalloc_req_bits_WIRE_35, _io_vcalloc_req_bits_T_457 connect _io_vcalloc_req_bits_WIRE_30.vnet_id, _io_vcalloc_req_bits_WIRE_35 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_30 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE connect vcalloc_vals[0], UInt<1>(0h0) invalidate vcalloc_reqs[0].vc_sel.`0`[0] invalidate vcalloc_reqs[0].vc_sel.`0`[1] invalidate vcalloc_reqs[0].vc_sel.`0`[2] invalidate vcalloc_reqs[0].vc_sel.`0`[3] invalidate vcalloc_reqs[0].vc_sel.`0`[4] invalidate vcalloc_reqs[0].vc_sel.`0`[5] invalidate vcalloc_reqs[0].vc_sel.`0`[6] invalidate vcalloc_reqs[0].vc_sel.`0`[7] invalidate vcalloc_reqs[0].vc_sel.`1`[0] invalidate vcalloc_reqs[0].vc_sel.`1`[1] invalidate vcalloc_reqs[0].vc_sel.`1`[2] invalidate vcalloc_reqs[0].vc_sel.`1`[3] invalidate vcalloc_reqs[0].vc_sel.`1`[4] invalidate vcalloc_reqs[0].vc_sel.`1`[5] invalidate vcalloc_reqs[0].vc_sel.`1`[6] invalidate vcalloc_reqs[0].vc_sel.`1`[7] invalidate vcalloc_reqs[0].vc_sel.`2`[0] invalidate vcalloc_reqs[0].vc_sel.`2`[1] invalidate vcalloc_reqs[0].vc_sel.`2`[2] invalidate vcalloc_reqs[0].vc_sel.`2`[3] invalidate vcalloc_reqs[0].vc_sel.`2`[4] invalidate vcalloc_reqs[0].vc_sel.`2`[5] invalidate vcalloc_reqs[0].vc_sel.`2`[6] invalidate vcalloc_reqs[0].vc_sel.`2`[7] invalidate vcalloc_reqs[0].in_vc invalidate vcalloc_reqs[0].flow.egress_node_id invalidate vcalloc_reqs[0].flow.egress_node invalidate vcalloc_reqs[0].flow.ingress_node_id invalidate vcalloc_reqs[0].flow.ingress_node invalidate vcalloc_reqs[0].flow.vnet_id node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].flow, states[1].flow node _T_37 = bits(vcalloc_sel, 1, 1) node _T_38 = and(vcalloc_vals[1], _T_37) node _T_39 = and(_T_38, io.vcalloc_req.ready) when _T_39 : connect states[1].g, UInt<3>(0h3) node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].flow, states[2].flow node _T_40 = bits(vcalloc_sel, 2, 2) node _T_41 = and(vcalloc_vals[2], _T_40) node _T_42 = and(_T_41, io.vcalloc_req.ready) when _T_42 : connect states[2].g, UInt<3>(0h3) node _vcalloc_vals_3_T = eq(states[3].g, UInt<3>(0h2)) node _vcalloc_vals_3_T_1 = eq(states[3].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_3_T_2 = and(_vcalloc_vals_3_T, _vcalloc_vals_3_T_1) connect vcalloc_vals[3], _vcalloc_vals_3_T_2 connect vcalloc_reqs[3].in_vc, UInt<2>(0h3) connect vcalloc_reqs[3].vc_sel.`0`, states[3].vc_sel.`0` connect vcalloc_reqs[3].vc_sel.`1`, states[3].vc_sel.`1` connect vcalloc_reqs[3].vc_sel.`2`, states[3].vc_sel.`2` connect vcalloc_reqs[3].flow, states[3].flow node _T_43 = bits(vcalloc_sel, 3, 3) node _T_44 = and(vcalloc_vals[3], _T_43) node _T_45 = and(_T_44, io.vcalloc_req.ready) when _T_45 : connect states[3].g, UInt<3>(0h3) node _vcalloc_vals_4_T = eq(states[4].g, UInt<3>(0h2)) node _vcalloc_vals_4_T_1 = eq(states[4].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_4_T_2 = and(_vcalloc_vals_4_T, _vcalloc_vals_4_T_1) connect vcalloc_vals[4], _vcalloc_vals_4_T_2 connect vcalloc_reqs[4].in_vc, UInt<3>(0h4) connect vcalloc_reqs[4].vc_sel.`0`, states[4].vc_sel.`0` connect vcalloc_reqs[4].vc_sel.`1`, states[4].vc_sel.`1` connect vcalloc_reqs[4].vc_sel.`2`, states[4].vc_sel.`2` connect vcalloc_reqs[4].flow, states[4].flow node _T_46 = bits(vcalloc_sel, 4, 4) node _T_47 = and(vcalloc_vals[4], _T_46) node _T_48 = and(_T_47, io.vcalloc_req.ready) when _T_48 : connect states[4].g, UInt<3>(0h3) node _vcalloc_vals_5_T = eq(states[5].g, UInt<3>(0h2)) node _vcalloc_vals_5_T_1 = eq(states[5].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_5_T_2 = and(_vcalloc_vals_5_T, _vcalloc_vals_5_T_1) connect vcalloc_vals[5], _vcalloc_vals_5_T_2 connect vcalloc_reqs[5].in_vc, UInt<3>(0h5) connect vcalloc_reqs[5].vc_sel.`0`, states[5].vc_sel.`0` connect vcalloc_reqs[5].vc_sel.`1`, states[5].vc_sel.`1` connect vcalloc_reqs[5].vc_sel.`2`, states[5].vc_sel.`2` connect vcalloc_reqs[5].flow, states[5].flow node _T_49 = bits(vcalloc_sel, 5, 5) node _T_50 = and(vcalloc_vals[5], _T_49) node _T_51 = and(_T_50, io.vcalloc_req.ready) when _T_51 : connect states[5].g, UInt<3>(0h3) node _vcalloc_vals_6_T = eq(states[6].g, UInt<3>(0h2)) node _vcalloc_vals_6_T_1 = eq(states[6].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_6_T_2 = and(_vcalloc_vals_6_T, _vcalloc_vals_6_T_1) connect vcalloc_vals[6], _vcalloc_vals_6_T_2 connect vcalloc_reqs[6].in_vc, UInt<3>(0h6) connect vcalloc_reqs[6].vc_sel.`0`, states[6].vc_sel.`0` connect vcalloc_reqs[6].vc_sel.`1`, states[6].vc_sel.`1` connect vcalloc_reqs[6].vc_sel.`2`, states[6].vc_sel.`2` connect vcalloc_reqs[6].flow, states[6].flow node _T_52 = bits(vcalloc_sel, 6, 6) node _T_53 = and(vcalloc_vals[6], _T_52) node _T_54 = and(_T_53, io.vcalloc_req.ready) when _T_54 : connect states[6].g, UInt<3>(0h3) node _vcalloc_vals_7_T = eq(states[7].g, UInt<3>(0h2)) node _vcalloc_vals_7_T_1 = eq(states[7].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_7_T_2 = and(_vcalloc_vals_7_T, _vcalloc_vals_7_T_1) connect vcalloc_vals[7], _vcalloc_vals_7_T_2 connect vcalloc_reqs[7].in_vc, UInt<3>(0h7) connect vcalloc_reqs[7].vc_sel.`0`, states[7].vc_sel.`0` connect vcalloc_reqs[7].vc_sel.`1`, states[7].vc_sel.`1` connect vcalloc_reqs[7].vc_sel.`2`, states[7].vc_sel.`2` connect vcalloc_reqs[7].flow, states[7].flow node _T_55 = bits(vcalloc_sel, 7, 7) node _T_56 = and(vcalloc_vals[7], _T_55) node _T_57 = and(_T_56, io.vcalloc_req.ready) when _T_57 : connect states[7].g, UInt<3>(0h3) node _io_debug_va_stall_T = add(vcalloc_vals[0], vcalloc_vals[1]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[2], vcalloc_vals[3]) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = add(_io_debug_va_stall_T_1, _io_debug_va_stall_T_3) node _io_debug_va_stall_T_5 = bits(_io_debug_va_stall_T_4, 2, 0) node _io_debug_va_stall_T_6 = add(vcalloc_vals[4], vcalloc_vals[5]) node _io_debug_va_stall_T_7 = bits(_io_debug_va_stall_T_6, 1, 0) node _io_debug_va_stall_T_8 = add(vcalloc_vals[6], vcalloc_vals[7]) node _io_debug_va_stall_T_9 = bits(_io_debug_va_stall_T_8, 1, 0) node _io_debug_va_stall_T_10 = add(_io_debug_va_stall_T_7, _io_debug_va_stall_T_9) node _io_debug_va_stall_T_11 = bits(_io_debug_va_stall_T_10, 2, 0) node _io_debug_va_stall_T_12 = add(_io_debug_va_stall_T_5, _io_debug_va_stall_T_11) node _io_debug_va_stall_T_13 = bits(_io_debug_va_stall_T_12, 3, 0) node _io_debug_va_stall_T_14 = sub(_io_debug_va_stall_T_13, io.vcalloc_req.ready) node _io_debug_va_stall_T_15 = tail(_io_debug_va_stall_T_14, 1) connect io.debug.va_stall, _io_debug_va_stall_T_15 node _T_58 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_58 : node _T_59 = bits(vcalloc_sel, 0, 0) when _T_59 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].g, UInt<3>(0h3) node _T_60 = eq(states[0].g, UInt<3>(0h2)) node _T_61 = asUInt(reset) node _T_62 = eq(_T_61, UInt<1>(0h0)) when _T_62 : node _T_63 = eq(_T_60, UInt<1>(0h0)) when _T_63 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_3 assert(clock, _T_60, UInt<1>(0h1), "") : assert_3 node _T_64 = bits(vcalloc_sel, 1, 1) when _T_64 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].g, UInt<3>(0h3) node _T_65 = eq(states[1].g, UInt<3>(0h2)) node _T_66 = asUInt(reset) node _T_67 = eq(_T_66, UInt<1>(0h0)) when _T_67 : node _T_68 = eq(_T_65, UInt<1>(0h0)) when _T_68 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_4 assert(clock, _T_65, UInt<1>(0h1), "") : assert_4 node _T_69 = bits(vcalloc_sel, 2, 2) when _T_69 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].g, UInt<3>(0h3) node _T_70 = eq(states[2].g, UInt<3>(0h2)) node _T_71 = asUInt(reset) node _T_72 = eq(_T_71, UInt<1>(0h0)) when _T_72 : node _T_73 = eq(_T_70, UInt<1>(0h0)) when _T_73 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_5 assert(clock, _T_70, UInt<1>(0h1), "") : assert_5 node _T_74 = bits(vcalloc_sel, 3, 3) when _T_74 : connect states[3].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[3].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[3].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[3].g, UInt<3>(0h3) node _T_75 = eq(states[3].g, UInt<3>(0h2)) node _T_76 = asUInt(reset) node _T_77 = eq(_T_76, UInt<1>(0h0)) when _T_77 : node _T_78 = eq(_T_75, UInt<1>(0h0)) when _T_78 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_6 assert(clock, _T_75, UInt<1>(0h1), "") : assert_6 node _T_79 = bits(vcalloc_sel, 4, 4) when _T_79 : connect states[4].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[4].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[4].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[4].g, UInt<3>(0h3) node _T_80 = eq(states[4].g, UInt<3>(0h2)) node _T_81 = asUInt(reset) node _T_82 = eq(_T_81, UInt<1>(0h0)) when _T_82 : node _T_83 = eq(_T_80, UInt<1>(0h0)) when _T_83 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_7 assert(clock, _T_80, UInt<1>(0h1), "") : assert_7 node _T_84 = bits(vcalloc_sel, 5, 5) when _T_84 : connect states[5].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[5].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[5].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[5].g, UInt<3>(0h3) node _T_85 = eq(states[5].g, UInt<3>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_8 assert(clock, _T_85, UInt<1>(0h1), "") : assert_8 node _T_89 = bits(vcalloc_sel, 6, 6) when _T_89 : connect states[6].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[6].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[6].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[6].g, UInt<3>(0h3) node _T_90 = eq(states[6].g, UInt<3>(0h2)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_9 assert(clock, _T_90, UInt<1>(0h1), "") : assert_9 node _T_94 = bits(vcalloc_sel, 7, 7) when _T_94 : connect states[7].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[7].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[7].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[7].g, UInt<3>(0h3) node _T_95 = eq(states[7].g, UInt<3>(0h2)) node _T_96 = asUInt(reset) node _T_97 = eq(_T_96, UInt<1>(0h0)) when _T_97 : node _T_98 = eq(_T_95, UInt<1>(0h0)) when _T_98 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:291 assert(states(i).g === g_v)\n") : printf_10 assert(clock, _T_95, UInt<1>(0h1), "") : assert_10 inst salloc_arb of SwitchArbiter_127 connect salloc_arb.clock, clock connect salloc_arb.reset, reset connect salloc_arb.io.in[0].valid, UInt<1>(0h0) invalidate salloc_arb.io.in[0].bits.tail invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`0`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`1`[7] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[0] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[1] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[2] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[3] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[4] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[5] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[6] invalidate salloc_arb.io.in[0].bits.vc_sel.`2`[7] node credit_available_lo_lo = cat(states[1].vc_sel.`0`[1], states[1].vc_sel.`0`[0]) node credit_available_lo_hi = cat(states[1].vc_sel.`0`[3], states[1].vc_sel.`0`[2]) node credit_available_lo = cat(credit_available_lo_hi, credit_available_lo_lo) node credit_available_hi_lo = cat(states[1].vc_sel.`0`[5], states[1].vc_sel.`0`[4]) node credit_available_hi_hi = cat(states[1].vc_sel.`0`[7], states[1].vc_sel.`0`[6]) node credit_available_hi = cat(credit_available_hi_hi, credit_available_hi_lo) node _credit_available_T = cat(credit_available_hi, credit_available_lo) node credit_available_lo_lo_1 = cat(states[1].vc_sel.`1`[1], states[1].vc_sel.`1`[0]) node credit_available_lo_hi_1 = cat(states[1].vc_sel.`1`[3], states[1].vc_sel.`1`[2]) node credit_available_lo_1 = cat(credit_available_lo_hi_1, credit_available_lo_lo_1) node credit_available_hi_lo_1 = cat(states[1].vc_sel.`1`[5], states[1].vc_sel.`1`[4]) node credit_available_hi_hi_1 = cat(states[1].vc_sel.`1`[7], states[1].vc_sel.`1`[6]) node credit_available_hi_1 = cat(credit_available_hi_hi_1, credit_available_hi_lo_1) node _credit_available_T_1 = cat(credit_available_hi_1, credit_available_lo_1) node credit_available_lo_lo_2 = cat(states[1].vc_sel.`2`[1], states[1].vc_sel.`2`[0]) node credit_available_lo_hi_2 = cat(states[1].vc_sel.`2`[3], states[1].vc_sel.`2`[2]) node credit_available_lo_2 = cat(credit_available_lo_hi_2, credit_available_lo_lo_2) node credit_available_hi_lo_2 = cat(states[1].vc_sel.`2`[5], states[1].vc_sel.`2`[4]) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`2`[7], states[1].vc_sel.`2`[6]) node credit_available_hi_2 = cat(credit_available_hi_hi_2, credit_available_hi_lo_2) node _credit_available_T_2 = cat(credit_available_hi_2, credit_available_lo_2) node credit_available_hi_3 = cat(_credit_available_T_2, _credit_available_T_1) node _credit_available_T_3 = cat(credit_available_hi_3, _credit_available_T) node credit_available_lo_lo_3 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_3 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_3 = cat(credit_available_lo_hi_3, credit_available_lo_lo_3) node credit_available_hi_lo_3 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_3 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_4 = cat(credit_available_hi_hi_3, credit_available_hi_lo_3) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo_3) node credit_available_lo_lo_4 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_4 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_4 = cat(credit_available_lo_hi_4, credit_available_lo_lo_4) node credit_available_hi_lo_4 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_4 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_5 = cat(credit_available_hi_hi_4, credit_available_hi_lo_4) node _credit_available_T_5 = cat(credit_available_hi_5, credit_available_lo_4) node credit_available_lo_lo_5 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_5 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_5 = cat(credit_available_lo_hi_5, credit_available_lo_lo_5) node credit_available_hi_lo_5 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_5 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_6 = cat(credit_available_hi_hi_5, credit_available_hi_lo_5) node _credit_available_T_6 = cat(credit_available_hi_6, credit_available_lo_5) node credit_available_hi_7 = cat(_credit_available_T_6, _credit_available_T_5) node _credit_available_T_7 = cat(credit_available_hi_7, _credit_available_T_4) node _credit_available_T_8 = and(_credit_available_T_3, _credit_available_T_7) node credit_available = neq(_credit_available_T_8, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`0`[3], states[1].vc_sel.`0`[3] connect salloc_arb.io.in[1].bits.vc_sel.`0`[4], states[1].vc_sel.`0`[4] connect salloc_arb.io.in[1].bits.vc_sel.`0`[5], states[1].vc_sel.`0`[5] connect salloc_arb.io.in[1].bits.vc_sel.`0`[6], states[1].vc_sel.`0`[6] connect salloc_arb.io.in[1].bits.vc_sel.`0`[7], states[1].vc_sel.`0`[7] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[3], states[1].vc_sel.`1`[3] connect salloc_arb.io.in[1].bits.vc_sel.`1`[4], states[1].vc_sel.`1`[4] connect salloc_arb.io.in[1].bits.vc_sel.`1`[5], states[1].vc_sel.`1`[5] connect salloc_arb.io.in[1].bits.vc_sel.`1`[6], states[1].vc_sel.`1`[6] connect salloc_arb.io.in[1].bits.vc_sel.`1`[7], states[1].vc_sel.`1`[7] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[3], states[1].vc_sel.`2`[3] connect salloc_arb.io.in[1].bits.vc_sel.`2`[4], states[1].vc_sel.`2`[4] connect salloc_arb.io.in[1].bits.vc_sel.`2`[5], states[1].vc_sel.`2`[5] connect salloc_arb.io.in[1].bits.vc_sel.`2`[6], states[1].vc_sel.`2`[6] connect salloc_arb.io.in[1].bits.vc_sel.`2`[7], states[1].vc_sel.`2`[7] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_99 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_100 = and(_T_99, input_buffer.io.deq[1].bits.tail) when _T_100 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_lo_lo_6 = cat(states[2].vc_sel.`0`[1], states[2].vc_sel.`0`[0]) node credit_available_lo_hi_6 = cat(states[2].vc_sel.`0`[3], states[2].vc_sel.`0`[2]) node credit_available_lo_6 = cat(credit_available_lo_hi_6, credit_available_lo_lo_6) node credit_available_hi_lo_6 = cat(states[2].vc_sel.`0`[5], states[2].vc_sel.`0`[4]) node credit_available_hi_hi_6 = cat(states[2].vc_sel.`0`[7], states[2].vc_sel.`0`[6]) node credit_available_hi_8 = cat(credit_available_hi_hi_6, credit_available_hi_lo_6) node _credit_available_T_9 = cat(credit_available_hi_8, credit_available_lo_6) node credit_available_lo_lo_7 = cat(states[2].vc_sel.`1`[1], states[2].vc_sel.`1`[0]) node credit_available_lo_hi_7 = cat(states[2].vc_sel.`1`[3], states[2].vc_sel.`1`[2]) node credit_available_lo_7 = cat(credit_available_lo_hi_7, credit_available_lo_lo_7) node credit_available_hi_lo_7 = cat(states[2].vc_sel.`1`[5], states[2].vc_sel.`1`[4]) node credit_available_hi_hi_7 = cat(states[2].vc_sel.`1`[7], states[2].vc_sel.`1`[6]) node credit_available_hi_9 = cat(credit_available_hi_hi_7, credit_available_hi_lo_7) node _credit_available_T_10 = cat(credit_available_hi_9, credit_available_lo_7) node credit_available_lo_lo_8 = cat(states[2].vc_sel.`2`[1], states[2].vc_sel.`2`[0]) node credit_available_lo_hi_8 = cat(states[2].vc_sel.`2`[3], states[2].vc_sel.`2`[2]) node credit_available_lo_8 = cat(credit_available_lo_hi_8, credit_available_lo_lo_8) node credit_available_hi_lo_8 = cat(states[2].vc_sel.`2`[5], states[2].vc_sel.`2`[4]) node credit_available_hi_hi_8 = cat(states[2].vc_sel.`2`[7], states[2].vc_sel.`2`[6]) node credit_available_hi_10 = cat(credit_available_hi_hi_8, credit_available_hi_lo_8) node _credit_available_T_11 = cat(credit_available_hi_10, credit_available_lo_8) node credit_available_hi_11 = cat(_credit_available_T_11, _credit_available_T_10) node _credit_available_T_12 = cat(credit_available_hi_11, _credit_available_T_9) node credit_available_lo_lo_9 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_9 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_9 = cat(credit_available_lo_hi_9, credit_available_lo_lo_9) node credit_available_hi_lo_9 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_9 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_12 = cat(credit_available_hi_hi_9, credit_available_hi_lo_9) node _credit_available_T_13 = cat(credit_available_hi_12, credit_available_lo_9) node credit_available_lo_lo_10 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_10 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_10 = cat(credit_available_lo_hi_10, credit_available_lo_lo_10) node credit_available_hi_lo_10 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_10 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_13 = cat(credit_available_hi_hi_10, credit_available_hi_lo_10) node _credit_available_T_14 = cat(credit_available_hi_13, credit_available_lo_10) node credit_available_lo_lo_11 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_11 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_11 = cat(credit_available_lo_hi_11, credit_available_lo_lo_11) node credit_available_hi_lo_11 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_11 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_14 = cat(credit_available_hi_hi_11, credit_available_hi_lo_11) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_11) node credit_available_hi_15 = cat(_credit_available_T_15, _credit_available_T_14) node _credit_available_T_16 = cat(credit_available_hi_15, _credit_available_T_13) node _credit_available_T_17 = and(_credit_available_T_12, _credit_available_T_16) node credit_available_1 = neq(_credit_available_T_17, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_1) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`0`[3], states[2].vc_sel.`0`[3] connect salloc_arb.io.in[2].bits.vc_sel.`0`[4], states[2].vc_sel.`0`[4] connect salloc_arb.io.in[2].bits.vc_sel.`0`[5], states[2].vc_sel.`0`[5] connect salloc_arb.io.in[2].bits.vc_sel.`0`[6], states[2].vc_sel.`0`[6] connect salloc_arb.io.in[2].bits.vc_sel.`0`[7], states[2].vc_sel.`0`[7] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[3], states[2].vc_sel.`1`[3] connect salloc_arb.io.in[2].bits.vc_sel.`1`[4], states[2].vc_sel.`1`[4] connect salloc_arb.io.in[2].bits.vc_sel.`1`[5], states[2].vc_sel.`1`[5] connect salloc_arb.io.in[2].bits.vc_sel.`1`[6], states[2].vc_sel.`1`[6] connect salloc_arb.io.in[2].bits.vc_sel.`1`[7], states[2].vc_sel.`1`[7] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[3], states[2].vc_sel.`2`[3] connect salloc_arb.io.in[2].bits.vc_sel.`2`[4], states[2].vc_sel.`2`[4] connect salloc_arb.io.in[2].bits.vc_sel.`2`[5], states[2].vc_sel.`2`[5] connect salloc_arb.io.in[2].bits.vc_sel.`2`[6], states[2].vc_sel.`2`[6] connect salloc_arb.io.in[2].bits.vc_sel.`2`[7], states[2].vc_sel.`2`[7] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_101 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_102 = and(_T_101, input_buffer.io.deq[2].bits.tail) when _T_102 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node credit_available_lo_lo_12 = cat(states[3].vc_sel.`0`[1], states[3].vc_sel.`0`[0]) node credit_available_lo_hi_12 = cat(states[3].vc_sel.`0`[3], states[3].vc_sel.`0`[2]) node credit_available_lo_12 = cat(credit_available_lo_hi_12, credit_available_lo_lo_12) node credit_available_hi_lo_12 = cat(states[3].vc_sel.`0`[5], states[3].vc_sel.`0`[4]) node credit_available_hi_hi_12 = cat(states[3].vc_sel.`0`[7], states[3].vc_sel.`0`[6]) node credit_available_hi_16 = cat(credit_available_hi_hi_12, credit_available_hi_lo_12) node _credit_available_T_18 = cat(credit_available_hi_16, credit_available_lo_12) node credit_available_lo_lo_13 = cat(states[3].vc_sel.`1`[1], states[3].vc_sel.`1`[0]) node credit_available_lo_hi_13 = cat(states[3].vc_sel.`1`[3], states[3].vc_sel.`1`[2]) node credit_available_lo_13 = cat(credit_available_lo_hi_13, credit_available_lo_lo_13) node credit_available_hi_lo_13 = cat(states[3].vc_sel.`1`[5], states[3].vc_sel.`1`[4]) node credit_available_hi_hi_13 = cat(states[3].vc_sel.`1`[7], states[3].vc_sel.`1`[6]) node credit_available_hi_17 = cat(credit_available_hi_hi_13, credit_available_hi_lo_13) node _credit_available_T_19 = cat(credit_available_hi_17, credit_available_lo_13) node credit_available_lo_lo_14 = cat(states[3].vc_sel.`2`[1], states[3].vc_sel.`2`[0]) node credit_available_lo_hi_14 = cat(states[3].vc_sel.`2`[3], states[3].vc_sel.`2`[2]) node credit_available_lo_14 = cat(credit_available_lo_hi_14, credit_available_lo_lo_14) node credit_available_hi_lo_14 = cat(states[3].vc_sel.`2`[5], states[3].vc_sel.`2`[4]) node credit_available_hi_hi_14 = cat(states[3].vc_sel.`2`[7], states[3].vc_sel.`2`[6]) node credit_available_hi_18 = cat(credit_available_hi_hi_14, credit_available_hi_lo_14) node _credit_available_T_20 = cat(credit_available_hi_18, credit_available_lo_14) node credit_available_hi_19 = cat(_credit_available_T_20, _credit_available_T_19) node _credit_available_T_21 = cat(credit_available_hi_19, _credit_available_T_18) node credit_available_lo_lo_15 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_15 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_15 = cat(credit_available_lo_hi_15, credit_available_lo_lo_15) node credit_available_hi_lo_15 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_15 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_20 = cat(credit_available_hi_hi_15, credit_available_hi_lo_15) node _credit_available_T_22 = cat(credit_available_hi_20, credit_available_lo_15) node credit_available_lo_lo_16 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_16 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_16 = cat(credit_available_lo_hi_16, credit_available_lo_lo_16) node credit_available_hi_lo_16 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_16 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_21 = cat(credit_available_hi_hi_16, credit_available_hi_lo_16) node _credit_available_T_23 = cat(credit_available_hi_21, credit_available_lo_16) node credit_available_lo_lo_17 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_17 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_17 = cat(credit_available_lo_hi_17, credit_available_lo_lo_17) node credit_available_hi_lo_17 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_17 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_22 = cat(credit_available_hi_hi_17, credit_available_hi_lo_17) node _credit_available_T_24 = cat(credit_available_hi_22, credit_available_lo_17) node credit_available_hi_23 = cat(_credit_available_T_24, _credit_available_T_23) node _credit_available_T_25 = cat(credit_available_hi_23, _credit_available_T_22) node _credit_available_T_26 = and(_credit_available_T_21, _credit_available_T_25) node credit_available_2 = neq(_credit_available_T_26, UInt<1>(0h0)) node _salloc_arb_io_in_3_valid_T = eq(states[3].g, UInt<3>(0h3)) node _salloc_arb_io_in_3_valid_T_1 = and(_salloc_arb_io_in_3_valid_T, credit_available_2) node _salloc_arb_io_in_3_valid_T_2 = and(_salloc_arb_io_in_3_valid_T_1, input_buffer.io.deq[3].valid) connect salloc_arb.io.in[3].valid, _salloc_arb_io_in_3_valid_T_2 connect salloc_arb.io.in[3].bits.vc_sel.`0`[0], states[3].vc_sel.`0`[0] connect salloc_arb.io.in[3].bits.vc_sel.`0`[1], states[3].vc_sel.`0`[1] connect salloc_arb.io.in[3].bits.vc_sel.`0`[2], states[3].vc_sel.`0`[2] connect salloc_arb.io.in[3].bits.vc_sel.`0`[3], states[3].vc_sel.`0`[3] connect salloc_arb.io.in[3].bits.vc_sel.`0`[4], states[3].vc_sel.`0`[4] connect salloc_arb.io.in[3].bits.vc_sel.`0`[5], states[3].vc_sel.`0`[5] connect salloc_arb.io.in[3].bits.vc_sel.`0`[6], states[3].vc_sel.`0`[6] connect salloc_arb.io.in[3].bits.vc_sel.`0`[7], states[3].vc_sel.`0`[7] connect salloc_arb.io.in[3].bits.vc_sel.`1`[0], states[3].vc_sel.`1`[0] connect salloc_arb.io.in[3].bits.vc_sel.`1`[1], states[3].vc_sel.`1`[1] connect salloc_arb.io.in[3].bits.vc_sel.`1`[2], states[3].vc_sel.`1`[2] connect salloc_arb.io.in[3].bits.vc_sel.`1`[3], states[3].vc_sel.`1`[3] connect salloc_arb.io.in[3].bits.vc_sel.`1`[4], states[3].vc_sel.`1`[4] connect salloc_arb.io.in[3].bits.vc_sel.`1`[5], states[3].vc_sel.`1`[5] connect salloc_arb.io.in[3].bits.vc_sel.`1`[6], states[3].vc_sel.`1`[6] connect salloc_arb.io.in[3].bits.vc_sel.`1`[7], states[3].vc_sel.`1`[7] connect salloc_arb.io.in[3].bits.vc_sel.`2`[0], states[3].vc_sel.`2`[0] connect salloc_arb.io.in[3].bits.vc_sel.`2`[1], states[3].vc_sel.`2`[1] connect salloc_arb.io.in[3].bits.vc_sel.`2`[2], states[3].vc_sel.`2`[2] connect salloc_arb.io.in[3].bits.vc_sel.`2`[3], states[3].vc_sel.`2`[3] connect salloc_arb.io.in[3].bits.vc_sel.`2`[4], states[3].vc_sel.`2`[4] connect salloc_arb.io.in[3].bits.vc_sel.`2`[5], states[3].vc_sel.`2`[5] connect salloc_arb.io.in[3].bits.vc_sel.`2`[6], states[3].vc_sel.`2`[6] connect salloc_arb.io.in[3].bits.vc_sel.`2`[7], states[3].vc_sel.`2`[7] connect salloc_arb.io.in[3].bits.tail, input_buffer.io.deq[3].bits.tail node _T_103 = and(salloc_arb.io.in[3].ready, salloc_arb.io.in[3].valid) node _T_104 = and(_T_103, input_buffer.io.deq[3].bits.tail) when _T_104 : connect states[3].g, UInt<3>(0h0) connect input_buffer.io.deq[3].ready, salloc_arb.io.in[3].ready node credit_available_lo_lo_18 = cat(states[4].vc_sel.`0`[1], states[4].vc_sel.`0`[0]) node credit_available_lo_hi_18 = cat(states[4].vc_sel.`0`[3], states[4].vc_sel.`0`[2]) node credit_available_lo_18 = cat(credit_available_lo_hi_18, credit_available_lo_lo_18) node credit_available_hi_lo_18 = cat(states[4].vc_sel.`0`[5], states[4].vc_sel.`0`[4]) node credit_available_hi_hi_18 = cat(states[4].vc_sel.`0`[7], states[4].vc_sel.`0`[6]) node credit_available_hi_24 = cat(credit_available_hi_hi_18, credit_available_hi_lo_18) node _credit_available_T_27 = cat(credit_available_hi_24, credit_available_lo_18) node credit_available_lo_lo_19 = cat(states[4].vc_sel.`1`[1], states[4].vc_sel.`1`[0]) node credit_available_lo_hi_19 = cat(states[4].vc_sel.`1`[3], states[4].vc_sel.`1`[2]) node credit_available_lo_19 = cat(credit_available_lo_hi_19, credit_available_lo_lo_19) node credit_available_hi_lo_19 = cat(states[4].vc_sel.`1`[5], states[4].vc_sel.`1`[4]) node credit_available_hi_hi_19 = cat(states[4].vc_sel.`1`[7], states[4].vc_sel.`1`[6]) node credit_available_hi_25 = cat(credit_available_hi_hi_19, credit_available_hi_lo_19) node _credit_available_T_28 = cat(credit_available_hi_25, credit_available_lo_19) node credit_available_lo_lo_20 = cat(states[4].vc_sel.`2`[1], states[4].vc_sel.`2`[0]) node credit_available_lo_hi_20 = cat(states[4].vc_sel.`2`[3], states[4].vc_sel.`2`[2]) node credit_available_lo_20 = cat(credit_available_lo_hi_20, credit_available_lo_lo_20) node credit_available_hi_lo_20 = cat(states[4].vc_sel.`2`[5], states[4].vc_sel.`2`[4]) node credit_available_hi_hi_20 = cat(states[4].vc_sel.`2`[7], states[4].vc_sel.`2`[6]) node credit_available_hi_26 = cat(credit_available_hi_hi_20, credit_available_hi_lo_20) node _credit_available_T_29 = cat(credit_available_hi_26, credit_available_lo_20) node credit_available_hi_27 = cat(_credit_available_T_29, _credit_available_T_28) node _credit_available_T_30 = cat(credit_available_hi_27, _credit_available_T_27) node credit_available_lo_lo_21 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_21 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_21 = cat(credit_available_lo_hi_21, credit_available_lo_lo_21) node credit_available_hi_lo_21 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_21 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_28 = cat(credit_available_hi_hi_21, credit_available_hi_lo_21) node _credit_available_T_31 = cat(credit_available_hi_28, credit_available_lo_21) node credit_available_lo_lo_22 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_22 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_22 = cat(credit_available_lo_hi_22, credit_available_lo_lo_22) node credit_available_hi_lo_22 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_22 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_29 = cat(credit_available_hi_hi_22, credit_available_hi_lo_22) node _credit_available_T_32 = cat(credit_available_hi_29, credit_available_lo_22) node credit_available_lo_lo_23 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_23 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_23 = cat(credit_available_lo_hi_23, credit_available_lo_lo_23) node credit_available_hi_lo_23 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_23 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_30 = cat(credit_available_hi_hi_23, credit_available_hi_lo_23) node _credit_available_T_33 = cat(credit_available_hi_30, credit_available_lo_23) node credit_available_hi_31 = cat(_credit_available_T_33, _credit_available_T_32) node _credit_available_T_34 = cat(credit_available_hi_31, _credit_available_T_31) node _credit_available_T_35 = and(_credit_available_T_30, _credit_available_T_34) node credit_available_3 = neq(_credit_available_T_35, UInt<1>(0h0)) node _salloc_arb_io_in_4_valid_T = eq(states[4].g, UInt<3>(0h3)) node _salloc_arb_io_in_4_valid_T_1 = and(_salloc_arb_io_in_4_valid_T, credit_available_3) node _salloc_arb_io_in_4_valid_T_2 = and(_salloc_arb_io_in_4_valid_T_1, input_buffer.io.deq[4].valid) connect salloc_arb.io.in[4].valid, _salloc_arb_io_in_4_valid_T_2 connect salloc_arb.io.in[4].bits.vc_sel.`0`[0], states[4].vc_sel.`0`[0] connect salloc_arb.io.in[4].bits.vc_sel.`0`[1], states[4].vc_sel.`0`[1] connect salloc_arb.io.in[4].bits.vc_sel.`0`[2], states[4].vc_sel.`0`[2] connect salloc_arb.io.in[4].bits.vc_sel.`0`[3], states[4].vc_sel.`0`[3] connect salloc_arb.io.in[4].bits.vc_sel.`0`[4], states[4].vc_sel.`0`[4] connect salloc_arb.io.in[4].bits.vc_sel.`0`[5], states[4].vc_sel.`0`[5] connect salloc_arb.io.in[4].bits.vc_sel.`0`[6], states[4].vc_sel.`0`[6] connect salloc_arb.io.in[4].bits.vc_sel.`0`[7], states[4].vc_sel.`0`[7] connect salloc_arb.io.in[4].bits.vc_sel.`1`[0], states[4].vc_sel.`1`[0] connect salloc_arb.io.in[4].bits.vc_sel.`1`[1], states[4].vc_sel.`1`[1] connect salloc_arb.io.in[4].bits.vc_sel.`1`[2], states[4].vc_sel.`1`[2] connect salloc_arb.io.in[4].bits.vc_sel.`1`[3], states[4].vc_sel.`1`[3] connect salloc_arb.io.in[4].bits.vc_sel.`1`[4], states[4].vc_sel.`1`[4] connect salloc_arb.io.in[4].bits.vc_sel.`1`[5], states[4].vc_sel.`1`[5] connect salloc_arb.io.in[4].bits.vc_sel.`1`[6], states[4].vc_sel.`1`[6] connect salloc_arb.io.in[4].bits.vc_sel.`1`[7], states[4].vc_sel.`1`[7] connect salloc_arb.io.in[4].bits.vc_sel.`2`[0], states[4].vc_sel.`2`[0] connect salloc_arb.io.in[4].bits.vc_sel.`2`[1], states[4].vc_sel.`2`[1] connect salloc_arb.io.in[4].bits.vc_sel.`2`[2], states[4].vc_sel.`2`[2] connect salloc_arb.io.in[4].bits.vc_sel.`2`[3], states[4].vc_sel.`2`[3] connect salloc_arb.io.in[4].bits.vc_sel.`2`[4], states[4].vc_sel.`2`[4] connect salloc_arb.io.in[4].bits.vc_sel.`2`[5], states[4].vc_sel.`2`[5] connect salloc_arb.io.in[4].bits.vc_sel.`2`[6], states[4].vc_sel.`2`[6] connect salloc_arb.io.in[4].bits.vc_sel.`2`[7], states[4].vc_sel.`2`[7] connect salloc_arb.io.in[4].bits.tail, input_buffer.io.deq[4].bits.tail node _T_105 = and(salloc_arb.io.in[4].ready, salloc_arb.io.in[4].valid) node _T_106 = and(_T_105, input_buffer.io.deq[4].bits.tail) when _T_106 : connect states[4].g, UInt<3>(0h0) connect input_buffer.io.deq[4].ready, salloc_arb.io.in[4].ready node credit_available_lo_lo_24 = cat(states[5].vc_sel.`0`[1], states[5].vc_sel.`0`[0]) node credit_available_lo_hi_24 = cat(states[5].vc_sel.`0`[3], states[5].vc_sel.`0`[2]) node credit_available_lo_24 = cat(credit_available_lo_hi_24, credit_available_lo_lo_24) node credit_available_hi_lo_24 = cat(states[5].vc_sel.`0`[5], states[5].vc_sel.`0`[4]) node credit_available_hi_hi_24 = cat(states[5].vc_sel.`0`[7], states[5].vc_sel.`0`[6]) node credit_available_hi_32 = cat(credit_available_hi_hi_24, credit_available_hi_lo_24) node _credit_available_T_36 = cat(credit_available_hi_32, credit_available_lo_24) node credit_available_lo_lo_25 = cat(states[5].vc_sel.`1`[1], states[5].vc_sel.`1`[0]) node credit_available_lo_hi_25 = cat(states[5].vc_sel.`1`[3], states[5].vc_sel.`1`[2]) node credit_available_lo_25 = cat(credit_available_lo_hi_25, credit_available_lo_lo_25) node credit_available_hi_lo_25 = cat(states[5].vc_sel.`1`[5], states[5].vc_sel.`1`[4]) node credit_available_hi_hi_25 = cat(states[5].vc_sel.`1`[7], states[5].vc_sel.`1`[6]) node credit_available_hi_33 = cat(credit_available_hi_hi_25, credit_available_hi_lo_25) node _credit_available_T_37 = cat(credit_available_hi_33, credit_available_lo_25) node credit_available_lo_lo_26 = cat(states[5].vc_sel.`2`[1], states[5].vc_sel.`2`[0]) node credit_available_lo_hi_26 = cat(states[5].vc_sel.`2`[3], states[5].vc_sel.`2`[2]) node credit_available_lo_26 = cat(credit_available_lo_hi_26, credit_available_lo_lo_26) node credit_available_hi_lo_26 = cat(states[5].vc_sel.`2`[5], states[5].vc_sel.`2`[4]) node credit_available_hi_hi_26 = cat(states[5].vc_sel.`2`[7], states[5].vc_sel.`2`[6]) node credit_available_hi_34 = cat(credit_available_hi_hi_26, credit_available_hi_lo_26) node _credit_available_T_38 = cat(credit_available_hi_34, credit_available_lo_26) node credit_available_hi_35 = cat(_credit_available_T_38, _credit_available_T_37) node _credit_available_T_39 = cat(credit_available_hi_35, _credit_available_T_36) node credit_available_lo_lo_27 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_27 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_27 = cat(credit_available_lo_hi_27, credit_available_lo_lo_27) node credit_available_hi_lo_27 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_27 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_36 = cat(credit_available_hi_hi_27, credit_available_hi_lo_27) node _credit_available_T_40 = cat(credit_available_hi_36, credit_available_lo_27) node credit_available_lo_lo_28 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_28 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_28 = cat(credit_available_lo_hi_28, credit_available_lo_lo_28) node credit_available_hi_lo_28 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_28 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_37 = cat(credit_available_hi_hi_28, credit_available_hi_lo_28) node _credit_available_T_41 = cat(credit_available_hi_37, credit_available_lo_28) node credit_available_lo_lo_29 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_29 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_29 = cat(credit_available_lo_hi_29, credit_available_lo_lo_29) node credit_available_hi_lo_29 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_29 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_38 = cat(credit_available_hi_hi_29, credit_available_hi_lo_29) node _credit_available_T_42 = cat(credit_available_hi_38, credit_available_lo_29) node credit_available_hi_39 = cat(_credit_available_T_42, _credit_available_T_41) node _credit_available_T_43 = cat(credit_available_hi_39, _credit_available_T_40) node _credit_available_T_44 = and(_credit_available_T_39, _credit_available_T_43) node credit_available_4 = neq(_credit_available_T_44, UInt<1>(0h0)) node _salloc_arb_io_in_5_valid_T = eq(states[5].g, UInt<3>(0h3)) node _salloc_arb_io_in_5_valid_T_1 = and(_salloc_arb_io_in_5_valid_T, credit_available_4) node _salloc_arb_io_in_5_valid_T_2 = and(_salloc_arb_io_in_5_valid_T_1, input_buffer.io.deq[5].valid) connect salloc_arb.io.in[5].valid, _salloc_arb_io_in_5_valid_T_2 connect salloc_arb.io.in[5].bits.vc_sel.`0`[0], states[5].vc_sel.`0`[0] connect salloc_arb.io.in[5].bits.vc_sel.`0`[1], states[5].vc_sel.`0`[1] connect salloc_arb.io.in[5].bits.vc_sel.`0`[2], states[5].vc_sel.`0`[2] connect salloc_arb.io.in[5].bits.vc_sel.`0`[3], states[5].vc_sel.`0`[3] connect salloc_arb.io.in[5].bits.vc_sel.`0`[4], states[5].vc_sel.`0`[4] connect salloc_arb.io.in[5].bits.vc_sel.`0`[5], states[5].vc_sel.`0`[5] connect salloc_arb.io.in[5].bits.vc_sel.`0`[6], states[5].vc_sel.`0`[6] connect salloc_arb.io.in[5].bits.vc_sel.`0`[7], states[5].vc_sel.`0`[7] connect salloc_arb.io.in[5].bits.vc_sel.`1`[0], states[5].vc_sel.`1`[0] connect salloc_arb.io.in[5].bits.vc_sel.`1`[1], states[5].vc_sel.`1`[1] connect salloc_arb.io.in[5].bits.vc_sel.`1`[2], states[5].vc_sel.`1`[2] connect salloc_arb.io.in[5].bits.vc_sel.`1`[3], states[5].vc_sel.`1`[3] connect salloc_arb.io.in[5].bits.vc_sel.`1`[4], states[5].vc_sel.`1`[4] connect salloc_arb.io.in[5].bits.vc_sel.`1`[5], states[5].vc_sel.`1`[5] connect salloc_arb.io.in[5].bits.vc_sel.`1`[6], states[5].vc_sel.`1`[6] connect salloc_arb.io.in[5].bits.vc_sel.`1`[7], states[5].vc_sel.`1`[7] connect salloc_arb.io.in[5].bits.vc_sel.`2`[0], states[5].vc_sel.`2`[0] connect salloc_arb.io.in[5].bits.vc_sel.`2`[1], states[5].vc_sel.`2`[1] connect salloc_arb.io.in[5].bits.vc_sel.`2`[2], states[5].vc_sel.`2`[2] connect salloc_arb.io.in[5].bits.vc_sel.`2`[3], states[5].vc_sel.`2`[3] connect salloc_arb.io.in[5].bits.vc_sel.`2`[4], states[5].vc_sel.`2`[4] connect salloc_arb.io.in[5].bits.vc_sel.`2`[5], states[5].vc_sel.`2`[5] connect salloc_arb.io.in[5].bits.vc_sel.`2`[6], states[5].vc_sel.`2`[6] connect salloc_arb.io.in[5].bits.vc_sel.`2`[7], states[5].vc_sel.`2`[7] connect salloc_arb.io.in[5].bits.tail, input_buffer.io.deq[5].bits.tail node _T_107 = and(salloc_arb.io.in[5].ready, salloc_arb.io.in[5].valid) node _T_108 = and(_T_107, input_buffer.io.deq[5].bits.tail) when _T_108 : connect states[5].g, UInt<3>(0h0) connect input_buffer.io.deq[5].ready, salloc_arb.io.in[5].ready node credit_available_lo_lo_30 = cat(states[6].vc_sel.`0`[1], states[6].vc_sel.`0`[0]) node credit_available_lo_hi_30 = cat(states[6].vc_sel.`0`[3], states[6].vc_sel.`0`[2]) node credit_available_lo_30 = cat(credit_available_lo_hi_30, credit_available_lo_lo_30) node credit_available_hi_lo_30 = cat(states[6].vc_sel.`0`[5], states[6].vc_sel.`0`[4]) node credit_available_hi_hi_30 = cat(states[6].vc_sel.`0`[7], states[6].vc_sel.`0`[6]) node credit_available_hi_40 = cat(credit_available_hi_hi_30, credit_available_hi_lo_30) node _credit_available_T_45 = cat(credit_available_hi_40, credit_available_lo_30) node credit_available_lo_lo_31 = cat(states[6].vc_sel.`1`[1], states[6].vc_sel.`1`[0]) node credit_available_lo_hi_31 = cat(states[6].vc_sel.`1`[3], states[6].vc_sel.`1`[2]) node credit_available_lo_31 = cat(credit_available_lo_hi_31, credit_available_lo_lo_31) node credit_available_hi_lo_31 = cat(states[6].vc_sel.`1`[5], states[6].vc_sel.`1`[4]) node credit_available_hi_hi_31 = cat(states[6].vc_sel.`1`[7], states[6].vc_sel.`1`[6]) node credit_available_hi_41 = cat(credit_available_hi_hi_31, credit_available_hi_lo_31) node _credit_available_T_46 = cat(credit_available_hi_41, credit_available_lo_31) node credit_available_lo_lo_32 = cat(states[6].vc_sel.`2`[1], states[6].vc_sel.`2`[0]) node credit_available_lo_hi_32 = cat(states[6].vc_sel.`2`[3], states[6].vc_sel.`2`[2]) node credit_available_lo_32 = cat(credit_available_lo_hi_32, credit_available_lo_lo_32) node credit_available_hi_lo_32 = cat(states[6].vc_sel.`2`[5], states[6].vc_sel.`2`[4]) node credit_available_hi_hi_32 = cat(states[6].vc_sel.`2`[7], states[6].vc_sel.`2`[6]) node credit_available_hi_42 = cat(credit_available_hi_hi_32, credit_available_hi_lo_32) node _credit_available_T_47 = cat(credit_available_hi_42, credit_available_lo_32) node credit_available_hi_43 = cat(_credit_available_T_47, _credit_available_T_46) node _credit_available_T_48 = cat(credit_available_hi_43, _credit_available_T_45) node credit_available_lo_lo_33 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_33 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_33 = cat(credit_available_lo_hi_33, credit_available_lo_lo_33) node credit_available_hi_lo_33 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_33 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_44 = cat(credit_available_hi_hi_33, credit_available_hi_lo_33) node _credit_available_T_49 = cat(credit_available_hi_44, credit_available_lo_33) node credit_available_lo_lo_34 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_34 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_34 = cat(credit_available_lo_hi_34, credit_available_lo_lo_34) node credit_available_hi_lo_34 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_34 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_45 = cat(credit_available_hi_hi_34, credit_available_hi_lo_34) node _credit_available_T_50 = cat(credit_available_hi_45, credit_available_lo_34) node credit_available_lo_lo_35 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_35 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_35 = cat(credit_available_lo_hi_35, credit_available_lo_lo_35) node credit_available_hi_lo_35 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_35 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_46 = cat(credit_available_hi_hi_35, credit_available_hi_lo_35) node _credit_available_T_51 = cat(credit_available_hi_46, credit_available_lo_35) node credit_available_hi_47 = cat(_credit_available_T_51, _credit_available_T_50) node _credit_available_T_52 = cat(credit_available_hi_47, _credit_available_T_49) node _credit_available_T_53 = and(_credit_available_T_48, _credit_available_T_52) node credit_available_5 = neq(_credit_available_T_53, UInt<1>(0h0)) node _salloc_arb_io_in_6_valid_T = eq(states[6].g, UInt<3>(0h3)) node _salloc_arb_io_in_6_valid_T_1 = and(_salloc_arb_io_in_6_valid_T, credit_available_5) node _salloc_arb_io_in_6_valid_T_2 = and(_salloc_arb_io_in_6_valid_T_1, input_buffer.io.deq[6].valid) connect salloc_arb.io.in[6].valid, _salloc_arb_io_in_6_valid_T_2 connect salloc_arb.io.in[6].bits.vc_sel.`0`[0], states[6].vc_sel.`0`[0] connect salloc_arb.io.in[6].bits.vc_sel.`0`[1], states[6].vc_sel.`0`[1] connect salloc_arb.io.in[6].bits.vc_sel.`0`[2], states[6].vc_sel.`0`[2] connect salloc_arb.io.in[6].bits.vc_sel.`0`[3], states[6].vc_sel.`0`[3] connect salloc_arb.io.in[6].bits.vc_sel.`0`[4], states[6].vc_sel.`0`[4] connect salloc_arb.io.in[6].bits.vc_sel.`0`[5], states[6].vc_sel.`0`[5] connect salloc_arb.io.in[6].bits.vc_sel.`0`[6], states[6].vc_sel.`0`[6] connect salloc_arb.io.in[6].bits.vc_sel.`0`[7], states[6].vc_sel.`0`[7] connect salloc_arb.io.in[6].bits.vc_sel.`1`[0], states[6].vc_sel.`1`[0] connect salloc_arb.io.in[6].bits.vc_sel.`1`[1], states[6].vc_sel.`1`[1] connect salloc_arb.io.in[6].bits.vc_sel.`1`[2], states[6].vc_sel.`1`[2] connect salloc_arb.io.in[6].bits.vc_sel.`1`[3], states[6].vc_sel.`1`[3] connect salloc_arb.io.in[6].bits.vc_sel.`1`[4], states[6].vc_sel.`1`[4] connect salloc_arb.io.in[6].bits.vc_sel.`1`[5], states[6].vc_sel.`1`[5] connect salloc_arb.io.in[6].bits.vc_sel.`1`[6], states[6].vc_sel.`1`[6] connect salloc_arb.io.in[6].bits.vc_sel.`1`[7], states[6].vc_sel.`1`[7] connect salloc_arb.io.in[6].bits.vc_sel.`2`[0], states[6].vc_sel.`2`[0] connect salloc_arb.io.in[6].bits.vc_sel.`2`[1], states[6].vc_sel.`2`[1] connect salloc_arb.io.in[6].bits.vc_sel.`2`[2], states[6].vc_sel.`2`[2] connect salloc_arb.io.in[6].bits.vc_sel.`2`[3], states[6].vc_sel.`2`[3] connect salloc_arb.io.in[6].bits.vc_sel.`2`[4], states[6].vc_sel.`2`[4] connect salloc_arb.io.in[6].bits.vc_sel.`2`[5], states[6].vc_sel.`2`[5] connect salloc_arb.io.in[6].bits.vc_sel.`2`[6], states[6].vc_sel.`2`[6] connect salloc_arb.io.in[6].bits.vc_sel.`2`[7], states[6].vc_sel.`2`[7] connect salloc_arb.io.in[6].bits.tail, input_buffer.io.deq[6].bits.tail node _T_109 = and(salloc_arb.io.in[6].ready, salloc_arb.io.in[6].valid) node _T_110 = and(_T_109, input_buffer.io.deq[6].bits.tail) when _T_110 : connect states[6].g, UInt<3>(0h0) connect input_buffer.io.deq[6].ready, salloc_arb.io.in[6].ready node credit_available_lo_lo_36 = cat(states[7].vc_sel.`0`[1], states[7].vc_sel.`0`[0]) node credit_available_lo_hi_36 = cat(states[7].vc_sel.`0`[3], states[7].vc_sel.`0`[2]) node credit_available_lo_36 = cat(credit_available_lo_hi_36, credit_available_lo_lo_36) node credit_available_hi_lo_36 = cat(states[7].vc_sel.`0`[5], states[7].vc_sel.`0`[4]) node credit_available_hi_hi_36 = cat(states[7].vc_sel.`0`[7], states[7].vc_sel.`0`[6]) node credit_available_hi_48 = cat(credit_available_hi_hi_36, credit_available_hi_lo_36) node _credit_available_T_54 = cat(credit_available_hi_48, credit_available_lo_36) node credit_available_lo_lo_37 = cat(states[7].vc_sel.`1`[1], states[7].vc_sel.`1`[0]) node credit_available_lo_hi_37 = cat(states[7].vc_sel.`1`[3], states[7].vc_sel.`1`[2]) node credit_available_lo_37 = cat(credit_available_lo_hi_37, credit_available_lo_lo_37) node credit_available_hi_lo_37 = cat(states[7].vc_sel.`1`[5], states[7].vc_sel.`1`[4]) node credit_available_hi_hi_37 = cat(states[7].vc_sel.`1`[7], states[7].vc_sel.`1`[6]) node credit_available_hi_49 = cat(credit_available_hi_hi_37, credit_available_hi_lo_37) node _credit_available_T_55 = cat(credit_available_hi_49, credit_available_lo_37) node credit_available_lo_lo_38 = cat(states[7].vc_sel.`2`[1], states[7].vc_sel.`2`[0]) node credit_available_lo_hi_38 = cat(states[7].vc_sel.`2`[3], states[7].vc_sel.`2`[2]) node credit_available_lo_38 = cat(credit_available_lo_hi_38, credit_available_lo_lo_38) node credit_available_hi_lo_38 = cat(states[7].vc_sel.`2`[5], states[7].vc_sel.`2`[4]) node credit_available_hi_hi_38 = cat(states[7].vc_sel.`2`[7], states[7].vc_sel.`2`[6]) node credit_available_hi_50 = cat(credit_available_hi_hi_38, credit_available_hi_lo_38) node _credit_available_T_56 = cat(credit_available_hi_50, credit_available_lo_38) node credit_available_hi_51 = cat(_credit_available_T_56, _credit_available_T_55) node _credit_available_T_57 = cat(credit_available_hi_51, _credit_available_T_54) node credit_available_lo_lo_39 = cat(io.out_credit_available.`0`[1], io.out_credit_available.`0`[0]) node credit_available_lo_hi_39 = cat(io.out_credit_available.`0`[3], io.out_credit_available.`0`[2]) node credit_available_lo_39 = cat(credit_available_lo_hi_39, credit_available_lo_lo_39) node credit_available_hi_lo_39 = cat(io.out_credit_available.`0`[5], io.out_credit_available.`0`[4]) node credit_available_hi_hi_39 = cat(io.out_credit_available.`0`[7], io.out_credit_available.`0`[6]) node credit_available_hi_52 = cat(credit_available_hi_hi_39, credit_available_hi_lo_39) node _credit_available_T_58 = cat(credit_available_hi_52, credit_available_lo_39) node credit_available_lo_lo_40 = cat(io.out_credit_available.`1`[1], io.out_credit_available.`1`[0]) node credit_available_lo_hi_40 = cat(io.out_credit_available.`1`[3], io.out_credit_available.`1`[2]) node credit_available_lo_40 = cat(credit_available_lo_hi_40, credit_available_lo_lo_40) node credit_available_hi_lo_40 = cat(io.out_credit_available.`1`[5], io.out_credit_available.`1`[4]) node credit_available_hi_hi_40 = cat(io.out_credit_available.`1`[7], io.out_credit_available.`1`[6]) node credit_available_hi_53 = cat(credit_available_hi_hi_40, credit_available_hi_lo_40) node _credit_available_T_59 = cat(credit_available_hi_53, credit_available_lo_40) node credit_available_lo_lo_41 = cat(io.out_credit_available.`2`[1], io.out_credit_available.`2`[0]) node credit_available_lo_hi_41 = cat(io.out_credit_available.`2`[3], io.out_credit_available.`2`[2]) node credit_available_lo_41 = cat(credit_available_lo_hi_41, credit_available_lo_lo_41) node credit_available_hi_lo_41 = cat(io.out_credit_available.`2`[5], io.out_credit_available.`2`[4]) node credit_available_hi_hi_41 = cat(io.out_credit_available.`2`[7], io.out_credit_available.`2`[6]) node credit_available_hi_54 = cat(credit_available_hi_hi_41, credit_available_hi_lo_41) node _credit_available_T_60 = cat(credit_available_hi_54, credit_available_lo_41) node credit_available_hi_55 = cat(_credit_available_T_60, _credit_available_T_59) node _credit_available_T_61 = cat(credit_available_hi_55, _credit_available_T_58) node _credit_available_T_62 = and(_credit_available_T_57, _credit_available_T_61) node credit_available_6 = neq(_credit_available_T_62, UInt<1>(0h0)) node _salloc_arb_io_in_7_valid_T = eq(states[7].g, UInt<3>(0h3)) node _salloc_arb_io_in_7_valid_T_1 = and(_salloc_arb_io_in_7_valid_T, credit_available_6) node _salloc_arb_io_in_7_valid_T_2 = and(_salloc_arb_io_in_7_valid_T_1, input_buffer.io.deq[7].valid) connect salloc_arb.io.in[7].valid, _salloc_arb_io_in_7_valid_T_2 connect salloc_arb.io.in[7].bits.vc_sel.`0`[0], states[7].vc_sel.`0`[0] connect salloc_arb.io.in[7].bits.vc_sel.`0`[1], states[7].vc_sel.`0`[1] connect salloc_arb.io.in[7].bits.vc_sel.`0`[2], states[7].vc_sel.`0`[2] connect salloc_arb.io.in[7].bits.vc_sel.`0`[3], states[7].vc_sel.`0`[3] connect salloc_arb.io.in[7].bits.vc_sel.`0`[4], states[7].vc_sel.`0`[4] connect salloc_arb.io.in[7].bits.vc_sel.`0`[5], states[7].vc_sel.`0`[5] connect salloc_arb.io.in[7].bits.vc_sel.`0`[6], states[7].vc_sel.`0`[6] connect salloc_arb.io.in[7].bits.vc_sel.`0`[7], states[7].vc_sel.`0`[7] connect salloc_arb.io.in[7].bits.vc_sel.`1`[0], states[7].vc_sel.`1`[0] connect salloc_arb.io.in[7].bits.vc_sel.`1`[1], states[7].vc_sel.`1`[1] connect salloc_arb.io.in[7].bits.vc_sel.`1`[2], states[7].vc_sel.`1`[2] connect salloc_arb.io.in[7].bits.vc_sel.`1`[3], states[7].vc_sel.`1`[3] connect salloc_arb.io.in[7].bits.vc_sel.`1`[4], states[7].vc_sel.`1`[4] connect salloc_arb.io.in[7].bits.vc_sel.`1`[5], states[7].vc_sel.`1`[5] connect salloc_arb.io.in[7].bits.vc_sel.`1`[6], states[7].vc_sel.`1`[6] connect salloc_arb.io.in[7].bits.vc_sel.`1`[7], states[7].vc_sel.`1`[7] connect salloc_arb.io.in[7].bits.vc_sel.`2`[0], states[7].vc_sel.`2`[0] connect salloc_arb.io.in[7].bits.vc_sel.`2`[1], states[7].vc_sel.`2`[1] connect salloc_arb.io.in[7].bits.vc_sel.`2`[2], states[7].vc_sel.`2`[2] connect salloc_arb.io.in[7].bits.vc_sel.`2`[3], states[7].vc_sel.`2`[3] connect salloc_arb.io.in[7].bits.vc_sel.`2`[4], states[7].vc_sel.`2`[4] connect salloc_arb.io.in[7].bits.vc_sel.`2`[5], states[7].vc_sel.`2`[5] connect salloc_arb.io.in[7].bits.vc_sel.`2`[6], states[7].vc_sel.`2`[6] connect salloc_arb.io.in[7].bits.vc_sel.`2`[7], states[7].vc_sel.`2`[7] connect salloc_arb.io.in[7].bits.tail, input_buffer.io.deq[7].bits.tail node _T_111 = and(salloc_arb.io.in[7].ready, salloc_arb.io.in[7].valid) node _T_112 = and(_T_111, input_buffer.io.deq[7].bits.tail) when _T_112 : connect states[7].g, UInt<3>(0h0) connect input_buffer.io.deq[7].ready, salloc_arb.io.in[7].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = eq(salloc_arb.io.in[3].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_7 = and(salloc_arb.io.in[3].valid, _io_debug_sa_stall_T_6) node _io_debug_sa_stall_T_8 = eq(salloc_arb.io.in[4].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_9 = and(salloc_arb.io.in[4].valid, _io_debug_sa_stall_T_8) node _io_debug_sa_stall_T_10 = eq(salloc_arb.io.in[5].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_11 = and(salloc_arb.io.in[5].valid, _io_debug_sa_stall_T_10) node _io_debug_sa_stall_T_12 = eq(salloc_arb.io.in[6].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_13 = and(salloc_arb.io.in[6].valid, _io_debug_sa_stall_T_12) node _io_debug_sa_stall_T_14 = eq(salloc_arb.io.in[7].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_15 = and(salloc_arb.io.in[7].valid, _io_debug_sa_stall_T_14) node _io_debug_sa_stall_T_16 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_3) node _io_debug_sa_stall_T_17 = bits(_io_debug_sa_stall_T_16, 1, 0) node _io_debug_sa_stall_T_18 = add(_io_debug_sa_stall_T_5, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_19 = bits(_io_debug_sa_stall_T_18, 1, 0) node _io_debug_sa_stall_T_20 = add(_io_debug_sa_stall_T_17, _io_debug_sa_stall_T_19) node _io_debug_sa_stall_T_21 = bits(_io_debug_sa_stall_T_20, 2, 0) node _io_debug_sa_stall_T_22 = add(_io_debug_sa_stall_T_9, _io_debug_sa_stall_T_11) node _io_debug_sa_stall_T_23 = bits(_io_debug_sa_stall_T_22, 1, 0) node _io_debug_sa_stall_T_24 = add(_io_debug_sa_stall_T_13, _io_debug_sa_stall_T_15) node _io_debug_sa_stall_T_25 = bits(_io_debug_sa_stall_T_24, 1, 0) node _io_debug_sa_stall_T_26 = add(_io_debug_sa_stall_T_23, _io_debug_sa_stall_T_25) node _io_debug_sa_stall_T_27 = bits(_io_debug_sa_stall_T_26, 2, 0) node _io_debug_sa_stall_T_28 = add(_io_debug_sa_stall_T_21, _io_debug_sa_stall_T_27) node _io_debug_sa_stall_T_29 = bits(_io_debug_sa_stall_T_28, 3, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_29 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) reg salloc_outs : { valid : UInt<1>, vid : UInt<3>, out_vid : UInt<3>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<73>, flow : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>}, virt_channel_id : UInt<3>}}[1], clock node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _io_in_vc_free_T_5 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _io_in_vc_free_T_6 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _io_in_vc_free_T_7 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _io_in_vc_free_T_8 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _io_in_vc_free_T_9 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_11 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_12 = mux(_io_in_vc_free_T_4, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_13 = mux(_io_in_vc_free_T_5, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_14 = mux(_io_in_vc_free_T_6, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_15 = mux(_io_in_vc_free_T_7, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_16 = mux(_io_in_vc_free_T_8, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_17 = or(_io_in_vc_free_T_9, _io_in_vc_free_T_10) node _io_in_vc_free_T_18 = or(_io_in_vc_free_T_17, _io_in_vc_free_T_11) node _io_in_vc_free_T_19 = or(_io_in_vc_free_T_18, _io_in_vc_free_T_12) node _io_in_vc_free_T_20 = or(_io_in_vc_free_T_19, _io_in_vc_free_T_13) node _io_in_vc_free_T_21 = or(_io_in_vc_free_T_20, _io_in_vc_free_T_14) node _io_in_vc_free_T_22 = or(_io_in_vc_free_T_21, _io_in_vc_free_T_15) node _io_in_vc_free_T_23 = or(_io_in_vc_free_T_22, _io_in_vc_free_T_16) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_23 node _io_in_vc_free_T_24 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_25 = mux(_io_in_vc_free_T_24, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_25 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 7, 4) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 3, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node salloc_outs_0_vid_hi_1 = bits(_salloc_outs_0_vid_T_1, 3, 2) node salloc_outs_0_vid_lo_1 = bits(_salloc_outs_0_vid_T_1, 1, 0) node _salloc_outs_0_vid_T_2 = orr(salloc_outs_0_vid_hi_1) node _salloc_outs_0_vid_T_3 = or(salloc_outs_0_vid_hi_1, salloc_outs_0_vid_lo_1) node _salloc_outs_0_vid_T_4 = bits(_salloc_outs_0_vid_T_3, 1, 1) node _salloc_outs_0_vid_T_5 = cat(_salloc_outs_0_vid_T_2, _salloc_outs_0_vid_T_4) node _salloc_outs_0_vid_T_6 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_5) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_6 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _vc_sel_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _vc_sel_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _vc_sel_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _vc_sel_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _vc_sel_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire vc_sel : { `2` : UInt<1>[8], `1` : UInt<1>[8], `0` : UInt<1>[8]} wire _vc_sel_WIRE : UInt<1>[8] node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_11 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_12 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_13 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_10) node _vc_sel_T_18 = or(_vc_sel_T_17, _vc_sel_T_11) node _vc_sel_T_19 = or(_vc_sel_T_18, _vc_sel_T_12) node _vc_sel_T_20 = or(_vc_sel_T_19, _vc_sel_T_13) node _vc_sel_T_21 = or(_vc_sel_T_20, _vc_sel_T_14) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_15) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_22 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_26 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_27 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_28 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_25) node _vc_sel_T_33 = or(_vc_sel_T_32, _vc_sel_T_26) node _vc_sel_T_34 = or(_vc_sel_T_33, _vc_sel_T_27) node _vc_sel_T_35 = or(_vc_sel_T_34, _vc_sel_T_28) node _vc_sel_T_36 = or(_vc_sel_T_35, _vc_sel_T_29) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_30) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_37 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_41 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_42 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_43 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_40) node _vc_sel_T_48 = or(_vc_sel_T_47, _vc_sel_T_41) node _vc_sel_T_49 = or(_vc_sel_T_48, _vc_sel_T_42) node _vc_sel_T_50 = or(_vc_sel_T_49, _vc_sel_T_43) node _vc_sel_T_51 = or(_vc_sel_T_50, _vc_sel_T_44) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_45) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_52 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_56 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_57 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_58 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[3], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_55) node _vc_sel_T_63 = or(_vc_sel_T_62, _vc_sel_T_56) node _vc_sel_T_64 = or(_vc_sel_T_63, _vc_sel_T_57) node _vc_sel_T_65 = or(_vc_sel_T_64, _vc_sel_T_58) node _vc_sel_T_66 = or(_vc_sel_T_65, _vc_sel_T_59) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_60) wire _vc_sel_WIRE_4 : UInt<1> connect _vc_sel_WIRE_4, _vc_sel_T_67 connect _vc_sel_WIRE[3], _vc_sel_WIRE_4 node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_71 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_72 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_73 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_74 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_75 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[4], UInt<1>(0h0)) node _vc_sel_T_76 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_77 = or(_vc_sel_T_76, _vc_sel_T_70) node _vc_sel_T_78 = or(_vc_sel_T_77, _vc_sel_T_71) node _vc_sel_T_79 = or(_vc_sel_T_78, _vc_sel_T_72) node _vc_sel_T_80 = or(_vc_sel_T_79, _vc_sel_T_73) node _vc_sel_T_81 = or(_vc_sel_T_80, _vc_sel_T_74) node _vc_sel_T_82 = or(_vc_sel_T_81, _vc_sel_T_75) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_82 connect _vc_sel_WIRE[4], _vc_sel_WIRE_5 node _vc_sel_T_83 = mux(_vc_sel_T, states[0].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_84 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_85 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_86 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_87 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_88 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_89 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_90 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[5], UInt<1>(0h0)) node _vc_sel_T_91 = or(_vc_sel_T_83, _vc_sel_T_84) node _vc_sel_T_92 = or(_vc_sel_T_91, _vc_sel_T_85) node _vc_sel_T_93 = or(_vc_sel_T_92, _vc_sel_T_86) node _vc_sel_T_94 = or(_vc_sel_T_93, _vc_sel_T_87) node _vc_sel_T_95 = or(_vc_sel_T_94, _vc_sel_T_88) node _vc_sel_T_96 = or(_vc_sel_T_95, _vc_sel_T_89) node _vc_sel_T_97 = or(_vc_sel_T_96, _vc_sel_T_90) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_97 connect _vc_sel_WIRE[5], _vc_sel_WIRE_6 node _vc_sel_T_98 = mux(_vc_sel_T, states[0].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_99 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_100 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_101 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_102 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_103 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_104 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_105 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[6], UInt<1>(0h0)) node _vc_sel_T_106 = or(_vc_sel_T_98, _vc_sel_T_99) node _vc_sel_T_107 = or(_vc_sel_T_106, _vc_sel_T_100) node _vc_sel_T_108 = or(_vc_sel_T_107, _vc_sel_T_101) node _vc_sel_T_109 = or(_vc_sel_T_108, _vc_sel_T_102) node _vc_sel_T_110 = or(_vc_sel_T_109, _vc_sel_T_103) node _vc_sel_T_111 = or(_vc_sel_T_110, _vc_sel_T_104) node _vc_sel_T_112 = or(_vc_sel_T_111, _vc_sel_T_105) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_112 connect _vc_sel_WIRE[6], _vc_sel_WIRE_7 node _vc_sel_T_113 = mux(_vc_sel_T, states[0].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_114 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_115 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_116 = mux(_vc_sel_T_3, states[3].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_117 = mux(_vc_sel_T_4, states[4].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_118 = mux(_vc_sel_T_5, states[5].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_119 = mux(_vc_sel_T_6, states[6].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_120 = mux(_vc_sel_T_7, states[7].vc_sel.`0`[7], UInt<1>(0h0)) node _vc_sel_T_121 = or(_vc_sel_T_113, _vc_sel_T_114) node _vc_sel_T_122 = or(_vc_sel_T_121, _vc_sel_T_115) node _vc_sel_T_123 = or(_vc_sel_T_122, _vc_sel_T_116) node _vc_sel_T_124 = or(_vc_sel_T_123, _vc_sel_T_117) node _vc_sel_T_125 = or(_vc_sel_T_124, _vc_sel_T_118) node _vc_sel_T_126 = or(_vc_sel_T_125, _vc_sel_T_119) node _vc_sel_T_127 = or(_vc_sel_T_126, _vc_sel_T_120) wire _vc_sel_WIRE_8 : UInt<1> connect _vc_sel_WIRE_8, _vc_sel_T_127 connect _vc_sel_WIRE[7], _vc_sel_WIRE_8 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_9 : UInt<1>[8] node _vc_sel_T_128 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_129 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_130 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_131 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_132 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_133 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_134 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_135 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_136 = or(_vc_sel_T_128, _vc_sel_T_129) node _vc_sel_T_137 = or(_vc_sel_T_136, _vc_sel_T_130) node _vc_sel_T_138 = or(_vc_sel_T_137, _vc_sel_T_131) node _vc_sel_T_139 = or(_vc_sel_T_138, _vc_sel_T_132) node _vc_sel_T_140 = or(_vc_sel_T_139, _vc_sel_T_133) node _vc_sel_T_141 = or(_vc_sel_T_140, _vc_sel_T_134) node _vc_sel_T_142 = or(_vc_sel_T_141, _vc_sel_T_135) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_142 connect _vc_sel_WIRE_9[0], _vc_sel_WIRE_10 node _vc_sel_T_143 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_144 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_145 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_146 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_147 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_148 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_149 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_150 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_151 = or(_vc_sel_T_143, _vc_sel_T_144) node _vc_sel_T_152 = or(_vc_sel_T_151, _vc_sel_T_145) node _vc_sel_T_153 = or(_vc_sel_T_152, _vc_sel_T_146) node _vc_sel_T_154 = or(_vc_sel_T_153, _vc_sel_T_147) node _vc_sel_T_155 = or(_vc_sel_T_154, _vc_sel_T_148) node _vc_sel_T_156 = or(_vc_sel_T_155, _vc_sel_T_149) node _vc_sel_T_157 = or(_vc_sel_T_156, _vc_sel_T_150) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_157 connect _vc_sel_WIRE_9[1], _vc_sel_WIRE_11 node _vc_sel_T_158 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_159 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_160 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_161 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_162 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_163 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_164 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_165 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_166 = or(_vc_sel_T_158, _vc_sel_T_159) node _vc_sel_T_167 = or(_vc_sel_T_166, _vc_sel_T_160) node _vc_sel_T_168 = or(_vc_sel_T_167, _vc_sel_T_161) node _vc_sel_T_169 = or(_vc_sel_T_168, _vc_sel_T_162) node _vc_sel_T_170 = or(_vc_sel_T_169, _vc_sel_T_163) node _vc_sel_T_171 = or(_vc_sel_T_170, _vc_sel_T_164) node _vc_sel_T_172 = or(_vc_sel_T_171, _vc_sel_T_165) wire _vc_sel_WIRE_12 : UInt<1> connect _vc_sel_WIRE_12, _vc_sel_T_172 connect _vc_sel_WIRE_9[2], _vc_sel_WIRE_12 node _vc_sel_T_173 = mux(_vc_sel_T, states[0].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_174 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_175 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_176 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_177 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_178 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_179 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_180 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[3], UInt<1>(0h0)) node _vc_sel_T_181 = or(_vc_sel_T_173, _vc_sel_T_174) node _vc_sel_T_182 = or(_vc_sel_T_181, _vc_sel_T_175) node _vc_sel_T_183 = or(_vc_sel_T_182, _vc_sel_T_176) node _vc_sel_T_184 = or(_vc_sel_T_183, _vc_sel_T_177) node _vc_sel_T_185 = or(_vc_sel_T_184, _vc_sel_T_178) node _vc_sel_T_186 = or(_vc_sel_T_185, _vc_sel_T_179) node _vc_sel_T_187 = or(_vc_sel_T_186, _vc_sel_T_180) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_187 connect _vc_sel_WIRE_9[3], _vc_sel_WIRE_13 node _vc_sel_T_188 = mux(_vc_sel_T, states[0].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_189 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_190 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_191 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_192 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_193 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_194 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_195 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[4], UInt<1>(0h0)) node _vc_sel_T_196 = or(_vc_sel_T_188, _vc_sel_T_189) node _vc_sel_T_197 = or(_vc_sel_T_196, _vc_sel_T_190) node _vc_sel_T_198 = or(_vc_sel_T_197, _vc_sel_T_191) node _vc_sel_T_199 = or(_vc_sel_T_198, _vc_sel_T_192) node _vc_sel_T_200 = or(_vc_sel_T_199, _vc_sel_T_193) node _vc_sel_T_201 = or(_vc_sel_T_200, _vc_sel_T_194) node _vc_sel_T_202 = or(_vc_sel_T_201, _vc_sel_T_195) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_202 connect _vc_sel_WIRE_9[4], _vc_sel_WIRE_14 node _vc_sel_T_203 = mux(_vc_sel_T, states[0].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_204 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_205 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_206 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_207 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_208 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_209 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_210 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[5], UInt<1>(0h0)) node _vc_sel_T_211 = or(_vc_sel_T_203, _vc_sel_T_204) node _vc_sel_T_212 = or(_vc_sel_T_211, _vc_sel_T_205) node _vc_sel_T_213 = or(_vc_sel_T_212, _vc_sel_T_206) node _vc_sel_T_214 = or(_vc_sel_T_213, _vc_sel_T_207) node _vc_sel_T_215 = or(_vc_sel_T_214, _vc_sel_T_208) node _vc_sel_T_216 = or(_vc_sel_T_215, _vc_sel_T_209) node _vc_sel_T_217 = or(_vc_sel_T_216, _vc_sel_T_210) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_217 connect _vc_sel_WIRE_9[5], _vc_sel_WIRE_15 node _vc_sel_T_218 = mux(_vc_sel_T, states[0].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_219 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_220 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_221 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_222 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_223 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_224 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_225 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[6], UInt<1>(0h0)) node _vc_sel_T_226 = or(_vc_sel_T_218, _vc_sel_T_219) node _vc_sel_T_227 = or(_vc_sel_T_226, _vc_sel_T_220) node _vc_sel_T_228 = or(_vc_sel_T_227, _vc_sel_T_221) node _vc_sel_T_229 = or(_vc_sel_T_228, _vc_sel_T_222) node _vc_sel_T_230 = or(_vc_sel_T_229, _vc_sel_T_223) node _vc_sel_T_231 = or(_vc_sel_T_230, _vc_sel_T_224) node _vc_sel_T_232 = or(_vc_sel_T_231, _vc_sel_T_225) wire _vc_sel_WIRE_16 : UInt<1> connect _vc_sel_WIRE_16, _vc_sel_T_232 connect _vc_sel_WIRE_9[6], _vc_sel_WIRE_16 node _vc_sel_T_233 = mux(_vc_sel_T, states[0].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_234 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_235 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_236 = mux(_vc_sel_T_3, states[3].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_237 = mux(_vc_sel_T_4, states[4].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_238 = mux(_vc_sel_T_5, states[5].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_239 = mux(_vc_sel_T_6, states[6].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_240 = mux(_vc_sel_T_7, states[7].vc_sel.`1`[7], UInt<1>(0h0)) node _vc_sel_T_241 = or(_vc_sel_T_233, _vc_sel_T_234) node _vc_sel_T_242 = or(_vc_sel_T_241, _vc_sel_T_235) node _vc_sel_T_243 = or(_vc_sel_T_242, _vc_sel_T_236) node _vc_sel_T_244 = or(_vc_sel_T_243, _vc_sel_T_237) node _vc_sel_T_245 = or(_vc_sel_T_244, _vc_sel_T_238) node _vc_sel_T_246 = or(_vc_sel_T_245, _vc_sel_T_239) node _vc_sel_T_247 = or(_vc_sel_T_246, _vc_sel_T_240) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_247 connect _vc_sel_WIRE_9[7], _vc_sel_WIRE_17 connect vc_sel.`1`, _vc_sel_WIRE_9 wire _vc_sel_WIRE_18 : UInt<1>[8] node _vc_sel_T_248 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_249 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_250 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_251 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_252 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_253 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_254 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_255 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_256 = or(_vc_sel_T_248, _vc_sel_T_249) node _vc_sel_T_257 = or(_vc_sel_T_256, _vc_sel_T_250) node _vc_sel_T_258 = or(_vc_sel_T_257, _vc_sel_T_251) node _vc_sel_T_259 = or(_vc_sel_T_258, _vc_sel_T_252) node _vc_sel_T_260 = or(_vc_sel_T_259, _vc_sel_T_253) node _vc_sel_T_261 = or(_vc_sel_T_260, _vc_sel_T_254) node _vc_sel_T_262 = or(_vc_sel_T_261, _vc_sel_T_255) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_262 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 node _vc_sel_T_263 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_264 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_265 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_266 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_267 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_268 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_269 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_270 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_271 = or(_vc_sel_T_263, _vc_sel_T_264) node _vc_sel_T_272 = or(_vc_sel_T_271, _vc_sel_T_265) node _vc_sel_T_273 = or(_vc_sel_T_272, _vc_sel_T_266) node _vc_sel_T_274 = or(_vc_sel_T_273, _vc_sel_T_267) node _vc_sel_T_275 = or(_vc_sel_T_274, _vc_sel_T_268) node _vc_sel_T_276 = or(_vc_sel_T_275, _vc_sel_T_269) node _vc_sel_T_277 = or(_vc_sel_T_276, _vc_sel_T_270) wire _vc_sel_WIRE_20 : UInt<1> connect _vc_sel_WIRE_20, _vc_sel_T_277 connect _vc_sel_WIRE_18[1], _vc_sel_WIRE_20 node _vc_sel_T_278 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_279 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_280 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_281 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_282 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_283 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_284 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_285 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_286 = or(_vc_sel_T_278, _vc_sel_T_279) node _vc_sel_T_287 = or(_vc_sel_T_286, _vc_sel_T_280) node _vc_sel_T_288 = or(_vc_sel_T_287, _vc_sel_T_281) node _vc_sel_T_289 = or(_vc_sel_T_288, _vc_sel_T_282) node _vc_sel_T_290 = or(_vc_sel_T_289, _vc_sel_T_283) node _vc_sel_T_291 = or(_vc_sel_T_290, _vc_sel_T_284) node _vc_sel_T_292 = or(_vc_sel_T_291, _vc_sel_T_285) wire _vc_sel_WIRE_21 : UInt<1> connect _vc_sel_WIRE_21, _vc_sel_T_292 connect _vc_sel_WIRE_18[2], _vc_sel_WIRE_21 node _vc_sel_T_293 = mux(_vc_sel_T, states[0].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_294 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_295 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_296 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_297 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_298 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_299 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_300 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[3], UInt<1>(0h0)) node _vc_sel_T_301 = or(_vc_sel_T_293, _vc_sel_T_294) node _vc_sel_T_302 = or(_vc_sel_T_301, _vc_sel_T_295) node _vc_sel_T_303 = or(_vc_sel_T_302, _vc_sel_T_296) node _vc_sel_T_304 = or(_vc_sel_T_303, _vc_sel_T_297) node _vc_sel_T_305 = or(_vc_sel_T_304, _vc_sel_T_298) node _vc_sel_T_306 = or(_vc_sel_T_305, _vc_sel_T_299) node _vc_sel_T_307 = or(_vc_sel_T_306, _vc_sel_T_300) wire _vc_sel_WIRE_22 : UInt<1> connect _vc_sel_WIRE_22, _vc_sel_T_307 connect _vc_sel_WIRE_18[3], _vc_sel_WIRE_22 node _vc_sel_T_308 = mux(_vc_sel_T, states[0].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_309 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_310 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_311 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_312 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_313 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_314 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_315 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[4], UInt<1>(0h0)) node _vc_sel_T_316 = or(_vc_sel_T_308, _vc_sel_T_309) node _vc_sel_T_317 = or(_vc_sel_T_316, _vc_sel_T_310) node _vc_sel_T_318 = or(_vc_sel_T_317, _vc_sel_T_311) node _vc_sel_T_319 = or(_vc_sel_T_318, _vc_sel_T_312) node _vc_sel_T_320 = or(_vc_sel_T_319, _vc_sel_T_313) node _vc_sel_T_321 = or(_vc_sel_T_320, _vc_sel_T_314) node _vc_sel_T_322 = or(_vc_sel_T_321, _vc_sel_T_315) wire _vc_sel_WIRE_23 : UInt<1> connect _vc_sel_WIRE_23, _vc_sel_T_322 connect _vc_sel_WIRE_18[4], _vc_sel_WIRE_23 node _vc_sel_T_323 = mux(_vc_sel_T, states[0].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_324 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_325 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_326 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_327 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_328 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_329 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_330 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[5], UInt<1>(0h0)) node _vc_sel_T_331 = or(_vc_sel_T_323, _vc_sel_T_324) node _vc_sel_T_332 = or(_vc_sel_T_331, _vc_sel_T_325) node _vc_sel_T_333 = or(_vc_sel_T_332, _vc_sel_T_326) node _vc_sel_T_334 = or(_vc_sel_T_333, _vc_sel_T_327) node _vc_sel_T_335 = or(_vc_sel_T_334, _vc_sel_T_328) node _vc_sel_T_336 = or(_vc_sel_T_335, _vc_sel_T_329) node _vc_sel_T_337 = or(_vc_sel_T_336, _vc_sel_T_330) wire _vc_sel_WIRE_24 : UInt<1> connect _vc_sel_WIRE_24, _vc_sel_T_337 connect _vc_sel_WIRE_18[5], _vc_sel_WIRE_24 node _vc_sel_T_338 = mux(_vc_sel_T, states[0].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_339 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_340 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_341 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_342 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_343 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_344 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_345 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[6], UInt<1>(0h0)) node _vc_sel_T_346 = or(_vc_sel_T_338, _vc_sel_T_339) node _vc_sel_T_347 = or(_vc_sel_T_346, _vc_sel_T_340) node _vc_sel_T_348 = or(_vc_sel_T_347, _vc_sel_T_341) node _vc_sel_T_349 = or(_vc_sel_T_348, _vc_sel_T_342) node _vc_sel_T_350 = or(_vc_sel_T_349, _vc_sel_T_343) node _vc_sel_T_351 = or(_vc_sel_T_350, _vc_sel_T_344) node _vc_sel_T_352 = or(_vc_sel_T_351, _vc_sel_T_345) wire _vc_sel_WIRE_25 : UInt<1> connect _vc_sel_WIRE_25, _vc_sel_T_352 connect _vc_sel_WIRE_18[6], _vc_sel_WIRE_25 node _vc_sel_T_353 = mux(_vc_sel_T, states[0].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_354 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_355 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_356 = mux(_vc_sel_T_3, states[3].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_357 = mux(_vc_sel_T_4, states[4].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_358 = mux(_vc_sel_T_5, states[5].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_359 = mux(_vc_sel_T_6, states[6].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_360 = mux(_vc_sel_T_7, states[7].vc_sel.`2`[7], UInt<1>(0h0)) node _vc_sel_T_361 = or(_vc_sel_T_353, _vc_sel_T_354) node _vc_sel_T_362 = or(_vc_sel_T_361, _vc_sel_T_355) node _vc_sel_T_363 = or(_vc_sel_T_362, _vc_sel_T_356) node _vc_sel_T_364 = or(_vc_sel_T_363, _vc_sel_T_357) node _vc_sel_T_365 = or(_vc_sel_T_364, _vc_sel_T_358) node _vc_sel_T_366 = or(_vc_sel_T_365, _vc_sel_T_359) node _vc_sel_T_367 = or(_vc_sel_T_366, _vc_sel_T_360) wire _vc_sel_WIRE_26 : UInt<1> connect _vc_sel_WIRE_26, _vc_sel_T_367 connect _vc_sel_WIRE_18[7], _vc_sel_WIRE_26 connect vc_sel.`2`, _vc_sel_WIRE_18 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node _channel_oh_T_1 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_2 = or(_channel_oh_T_1, vc_sel.`0`[3]) node _channel_oh_T_3 = or(_channel_oh_T_2, vc_sel.`0`[4]) node _channel_oh_T_4 = or(_channel_oh_T_3, vc_sel.`0`[5]) node _channel_oh_T_5 = or(_channel_oh_T_4, vc_sel.`0`[6]) node channel_oh_0 = or(_channel_oh_T_5, vc_sel.`0`[7]) node _channel_oh_T_6 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node _channel_oh_T_7 = or(_channel_oh_T_6, vc_sel.`1`[2]) node _channel_oh_T_8 = or(_channel_oh_T_7, vc_sel.`1`[3]) node _channel_oh_T_9 = or(_channel_oh_T_8, vc_sel.`1`[4]) node _channel_oh_T_10 = or(_channel_oh_T_9, vc_sel.`1`[5]) node _channel_oh_T_11 = or(_channel_oh_T_10, vc_sel.`1`[6]) node channel_oh_1 = or(_channel_oh_T_11, vc_sel.`1`[7]) node _channel_oh_T_12 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node _channel_oh_T_13 = or(_channel_oh_T_12, vc_sel.`2`[2]) node _channel_oh_T_14 = or(_channel_oh_T_13, vc_sel.`2`[3]) node _channel_oh_T_15 = or(_channel_oh_T_14, vc_sel.`2`[4]) node _channel_oh_T_16 = or(_channel_oh_T_15, vc_sel.`2`[5]) node _channel_oh_T_17 = or(_channel_oh_T_16, vc_sel.`2`[6]) node channel_oh_2 = or(_channel_oh_T_17, vc_sel.`2`[7]) node virt_channel_lo_lo = cat(vc_sel.`0`[1], vc_sel.`0`[0]) node virt_channel_lo_hi = cat(vc_sel.`0`[3], vc_sel.`0`[2]) node virt_channel_lo = cat(virt_channel_lo_hi, virt_channel_lo_lo) node virt_channel_hi_lo = cat(vc_sel.`0`[5], vc_sel.`0`[4]) node virt_channel_hi_hi = cat(vc_sel.`0`[7], vc_sel.`0`[6]) node virt_channel_hi = cat(virt_channel_hi_hi, virt_channel_hi_lo) node _virt_channel_T = cat(virt_channel_hi, virt_channel_lo) node virt_channel_hi_1 = bits(_virt_channel_T, 7, 4) node virt_channel_lo_1 = bits(_virt_channel_T, 3, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo_1) node virt_channel_hi_2 = bits(_virt_channel_T_2, 3, 2) node virt_channel_lo_2 = bits(_virt_channel_T_2, 1, 0) node _virt_channel_T_3 = orr(virt_channel_hi_2) node _virt_channel_T_4 = or(virt_channel_hi_2, virt_channel_lo_2) node _virt_channel_T_5 = bits(_virt_channel_T_4, 1, 1) node _virt_channel_T_6 = cat(_virt_channel_T_3, _virt_channel_T_5) node _virt_channel_T_7 = cat(_virt_channel_T_1, _virt_channel_T_6) node virt_channel_lo_lo_1 = cat(vc_sel.`1`[1], vc_sel.`1`[0]) node virt_channel_lo_hi_1 = cat(vc_sel.`1`[3], vc_sel.`1`[2]) node virt_channel_lo_3 = cat(virt_channel_lo_hi_1, virt_channel_lo_lo_1) node virt_channel_hi_lo_1 = cat(vc_sel.`1`[5], vc_sel.`1`[4]) node virt_channel_hi_hi_1 = cat(vc_sel.`1`[7], vc_sel.`1`[6]) node virt_channel_hi_3 = cat(virt_channel_hi_hi_1, virt_channel_hi_lo_1) node _virt_channel_T_8 = cat(virt_channel_hi_3, virt_channel_lo_3) node virt_channel_hi_4 = bits(_virt_channel_T_8, 7, 4) node virt_channel_lo_4 = bits(_virt_channel_T_8, 3, 0) node _virt_channel_T_9 = orr(virt_channel_hi_4) node _virt_channel_T_10 = or(virt_channel_hi_4, virt_channel_lo_4) node virt_channel_hi_5 = bits(_virt_channel_T_10, 3, 2) node virt_channel_lo_5 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_5) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node _virt_channel_T_15 = cat(_virt_channel_T_9, _virt_channel_T_14) node virt_channel_lo_lo_2 = cat(vc_sel.`2`[1], vc_sel.`2`[0]) node virt_channel_lo_hi_2 = cat(vc_sel.`2`[3], vc_sel.`2`[2]) node virt_channel_lo_6 = cat(virt_channel_lo_hi_2, virt_channel_lo_lo_2) node virt_channel_hi_lo_2 = cat(vc_sel.`2`[5], vc_sel.`2`[4]) node virt_channel_hi_hi_2 = cat(vc_sel.`2`[7], vc_sel.`2`[6]) node virt_channel_hi_6 = cat(virt_channel_hi_hi_2, virt_channel_hi_lo_2) node _virt_channel_T_16 = cat(virt_channel_hi_6, virt_channel_lo_6) node virt_channel_hi_7 = bits(_virt_channel_T_16, 7, 4) node virt_channel_lo_7 = bits(_virt_channel_T_16, 3, 0) node _virt_channel_T_17 = orr(virt_channel_hi_7) node _virt_channel_T_18 = or(virt_channel_hi_7, virt_channel_lo_7) node virt_channel_hi_8 = bits(_virt_channel_T_18, 3, 2) node virt_channel_lo_8 = bits(_virt_channel_T_18, 1, 0) node _virt_channel_T_19 = orr(virt_channel_hi_8) node _virt_channel_T_20 = or(virt_channel_hi_8, virt_channel_lo_8) node _virt_channel_T_21 = bits(_virt_channel_T_20, 1, 1) node _virt_channel_T_22 = cat(_virt_channel_T_19, _virt_channel_T_21) node _virt_channel_T_23 = cat(_virt_channel_T_17, _virt_channel_T_22) node _virt_channel_T_24 = mux(channel_oh_0, _virt_channel_T_7, UInt<1>(0h0)) node _virt_channel_T_25 = mux(channel_oh_1, _virt_channel_T_15, UInt<1>(0h0)) node _virt_channel_T_26 = mux(channel_oh_2, _virt_channel_T_23, UInt<1>(0h0)) node _virt_channel_T_27 = or(_virt_channel_T_24, _virt_channel_T_25) node _virt_channel_T_28 = or(_virt_channel_T_27, _virt_channel_T_26) wire virt_channel : UInt<3> connect virt_channel, _virt_channel_T_28 node _T_113 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_113 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_payload_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_payload_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_payload_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_payload_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_payload_T_8 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_9 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_10 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_11 = mux(_salloc_outs_0_flit_payload_T_3, input_buffer.io.deq[3].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_12 = mux(_salloc_outs_0_flit_payload_T_4, input_buffer.io.deq[4].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_13 = mux(_salloc_outs_0_flit_payload_T_5, input_buffer.io.deq[5].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_14 = mux(_salloc_outs_0_flit_payload_T_6, input_buffer.io.deq[6].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_15 = mux(_salloc_outs_0_flit_payload_T_7, input_buffer.io.deq[7].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_16 = or(_salloc_outs_0_flit_payload_T_8, _salloc_outs_0_flit_payload_T_9) node _salloc_outs_0_flit_payload_T_17 = or(_salloc_outs_0_flit_payload_T_16, _salloc_outs_0_flit_payload_T_10) node _salloc_outs_0_flit_payload_T_18 = or(_salloc_outs_0_flit_payload_T_17, _salloc_outs_0_flit_payload_T_11) node _salloc_outs_0_flit_payload_T_19 = or(_salloc_outs_0_flit_payload_T_18, _salloc_outs_0_flit_payload_T_12) node _salloc_outs_0_flit_payload_T_20 = or(_salloc_outs_0_flit_payload_T_19, _salloc_outs_0_flit_payload_T_13) node _salloc_outs_0_flit_payload_T_21 = or(_salloc_outs_0_flit_payload_T_20, _salloc_outs_0_flit_payload_T_14) node _salloc_outs_0_flit_payload_T_22 = or(_salloc_outs_0_flit_payload_T_21, _salloc_outs_0_flit_payload_T_15) wire _salloc_outs_0_flit_payload_WIRE : UInt<73> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_22 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_head_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_head_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_head_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_head_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_head_T_8 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_9 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_10 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_11 = mux(_salloc_outs_0_flit_head_T_3, input_buffer.io.deq[3].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_12 = mux(_salloc_outs_0_flit_head_T_4, input_buffer.io.deq[4].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_13 = mux(_salloc_outs_0_flit_head_T_5, input_buffer.io.deq[5].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_14 = mux(_salloc_outs_0_flit_head_T_6, input_buffer.io.deq[6].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_15 = mux(_salloc_outs_0_flit_head_T_7, input_buffer.io.deq[7].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_16 = or(_salloc_outs_0_flit_head_T_8, _salloc_outs_0_flit_head_T_9) node _salloc_outs_0_flit_head_T_17 = or(_salloc_outs_0_flit_head_T_16, _salloc_outs_0_flit_head_T_10) node _salloc_outs_0_flit_head_T_18 = or(_salloc_outs_0_flit_head_T_17, _salloc_outs_0_flit_head_T_11) node _salloc_outs_0_flit_head_T_19 = or(_salloc_outs_0_flit_head_T_18, _salloc_outs_0_flit_head_T_12) node _salloc_outs_0_flit_head_T_20 = or(_salloc_outs_0_flit_head_T_19, _salloc_outs_0_flit_head_T_13) node _salloc_outs_0_flit_head_T_21 = or(_salloc_outs_0_flit_head_T_20, _salloc_outs_0_flit_head_T_14) node _salloc_outs_0_flit_head_T_22 = or(_salloc_outs_0_flit_head_T_21, _salloc_outs_0_flit_head_T_15) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_22 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_tail_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_tail_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_tail_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_tail_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) node _salloc_outs_0_flit_tail_T_8 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_9 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_10 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_11 = mux(_salloc_outs_0_flit_tail_T_3, input_buffer.io.deq[3].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_12 = mux(_salloc_outs_0_flit_tail_T_4, input_buffer.io.deq[4].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_13 = mux(_salloc_outs_0_flit_tail_T_5, input_buffer.io.deq[5].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_14 = mux(_salloc_outs_0_flit_tail_T_6, input_buffer.io.deq[6].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_15 = mux(_salloc_outs_0_flit_tail_T_7, input_buffer.io.deq[7].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_16 = or(_salloc_outs_0_flit_tail_T_8, _salloc_outs_0_flit_tail_T_9) node _salloc_outs_0_flit_tail_T_17 = or(_salloc_outs_0_flit_tail_T_16, _salloc_outs_0_flit_tail_T_10) node _salloc_outs_0_flit_tail_T_18 = or(_salloc_outs_0_flit_tail_T_17, _salloc_outs_0_flit_tail_T_11) node _salloc_outs_0_flit_tail_T_19 = or(_salloc_outs_0_flit_tail_T_18, _salloc_outs_0_flit_tail_T_12) node _salloc_outs_0_flit_tail_T_20 = or(_salloc_outs_0_flit_tail_T_19, _salloc_outs_0_flit_tail_T_13) node _salloc_outs_0_flit_tail_T_21 = or(_salloc_outs_0_flit_tail_T_20, _salloc_outs_0_flit_tail_T_14) node _salloc_outs_0_flit_tail_T_22 = or(_salloc_outs_0_flit_tail_T_21, _salloc_outs_0_flit_tail_T_15) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_22 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_flow_T_3 = bits(salloc_arb.io.chosen_oh[0], 3, 3) node _salloc_outs_0_flit_flow_T_4 = bits(salloc_arb.io.chosen_oh[0], 4, 4) node _salloc_outs_0_flit_flow_T_5 = bits(salloc_arb.io.chosen_oh[0], 5, 5) node _salloc_outs_0_flit_flow_T_6 = bits(salloc_arb.io.chosen_oh[0], 6, 6) node _salloc_outs_0_flit_flow_T_7 = bits(salloc_arb.io.chosen_oh[0], 7, 7) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<3>, ingress_node : UInt<5>, ingress_node_id : UInt<2>, egress_node : UInt<5>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_12 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_10) node _salloc_outs_0_flit_flow_T_18 = or(_salloc_outs_0_flit_flow_T_17, _salloc_outs_0_flit_flow_T_11) node _salloc_outs_0_flit_flow_T_19 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_12) node _salloc_outs_0_flit_flow_T_20 = or(_salloc_outs_0_flit_flow_T_19, _salloc_outs_0_flit_flow_T_13) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_20, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_27 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_28 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_29 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_30 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_31 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_32 = or(_salloc_outs_0_flit_flow_T_31, _salloc_outs_0_flit_flow_T_25) node _salloc_outs_0_flit_flow_T_33 = or(_salloc_outs_0_flit_flow_T_32, _salloc_outs_0_flit_flow_T_26) node _salloc_outs_0_flit_flow_T_34 = or(_salloc_outs_0_flit_flow_T_33, _salloc_outs_0_flit_flow_T_27) node _salloc_outs_0_flit_flow_T_35 = or(_salloc_outs_0_flit_flow_T_34, _salloc_outs_0_flit_flow_T_28) node _salloc_outs_0_flit_flow_T_36 = or(_salloc_outs_0_flit_flow_T_35, _salloc_outs_0_flit_flow_T_29) node _salloc_outs_0_flit_flow_T_37 = or(_salloc_outs_0_flit_flow_T_36, _salloc_outs_0_flit_flow_T_30) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_37 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_38 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_39 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_40 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_41 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_42 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_43 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_44 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_45 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_46 = or(_salloc_outs_0_flit_flow_T_38, _salloc_outs_0_flit_flow_T_39) node _salloc_outs_0_flit_flow_T_47 = or(_salloc_outs_0_flit_flow_T_46, _salloc_outs_0_flit_flow_T_40) node _salloc_outs_0_flit_flow_T_48 = or(_salloc_outs_0_flit_flow_T_47, _salloc_outs_0_flit_flow_T_41) node _salloc_outs_0_flit_flow_T_49 = or(_salloc_outs_0_flit_flow_T_48, _salloc_outs_0_flit_flow_T_42) node _salloc_outs_0_flit_flow_T_50 = or(_salloc_outs_0_flit_flow_T_49, _salloc_outs_0_flit_flow_T_43) node _salloc_outs_0_flit_flow_T_51 = or(_salloc_outs_0_flit_flow_T_50, _salloc_outs_0_flit_flow_T_44) node _salloc_outs_0_flit_flow_T_52 = or(_salloc_outs_0_flit_flow_T_51, _salloc_outs_0_flit_flow_T_45) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_52 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_53 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_54 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_55 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_56 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_57 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_58 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_59 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_60 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_61 = or(_salloc_outs_0_flit_flow_T_53, _salloc_outs_0_flit_flow_T_54) node _salloc_outs_0_flit_flow_T_62 = or(_salloc_outs_0_flit_flow_T_61, _salloc_outs_0_flit_flow_T_55) node _salloc_outs_0_flit_flow_T_63 = or(_salloc_outs_0_flit_flow_T_62, _salloc_outs_0_flit_flow_T_56) node _salloc_outs_0_flit_flow_T_64 = or(_salloc_outs_0_flit_flow_T_63, _salloc_outs_0_flit_flow_T_57) node _salloc_outs_0_flit_flow_T_65 = or(_salloc_outs_0_flit_flow_T_64, _salloc_outs_0_flit_flow_T_58) node _salloc_outs_0_flit_flow_T_66 = or(_salloc_outs_0_flit_flow_T_65, _salloc_outs_0_flit_flow_T_59) node _salloc_outs_0_flit_flow_T_67 = or(_salloc_outs_0_flit_flow_T_66, _salloc_outs_0_flit_flow_T_60) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<5> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_67 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_68 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_69 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_70 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_71 = mux(_salloc_outs_0_flit_flow_T_3, states[3].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_72 = mux(_salloc_outs_0_flit_flow_T_4, states[4].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_73 = mux(_salloc_outs_0_flit_flow_T_5, states[5].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_74 = mux(_salloc_outs_0_flit_flow_T_6, states[6].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_75 = mux(_salloc_outs_0_flit_flow_T_7, states[7].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_76 = or(_salloc_outs_0_flit_flow_T_68, _salloc_outs_0_flit_flow_T_69) node _salloc_outs_0_flit_flow_T_77 = or(_salloc_outs_0_flit_flow_T_76, _salloc_outs_0_flit_flow_T_70) node _salloc_outs_0_flit_flow_T_78 = or(_salloc_outs_0_flit_flow_T_77, _salloc_outs_0_flit_flow_T_71) node _salloc_outs_0_flit_flow_T_79 = or(_salloc_outs_0_flit_flow_T_78, _salloc_outs_0_flit_flow_T_72) node _salloc_outs_0_flit_flow_T_80 = or(_salloc_outs_0_flit_flow_T_79, _salloc_outs_0_flit_flow_T_73) node _salloc_outs_0_flit_flow_T_81 = or(_salloc_outs_0_flit_flow_T_80, _salloc_outs_0_flit_flow_T_74) node _salloc_outs_0_flit_flow_T_82 = or(_salloc_outs_0_flit_flow_T_81, _salloc_outs_0_flit_flow_T_75) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_82 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid invalidate states[0].fifo_deps invalidate states[0].flow.egress_node_id invalidate states[0].flow.egress_node invalidate states[0].flow.ingress_node_id invalidate states[0].flow.ingress_node invalidate states[0].flow.vnet_id invalidate states[0].vc_sel.`0`[0] invalidate states[0].vc_sel.`0`[1] invalidate states[0].vc_sel.`0`[2] invalidate states[0].vc_sel.`0`[3] invalidate states[0].vc_sel.`0`[4] invalidate states[0].vc_sel.`0`[5] invalidate states[0].vc_sel.`0`[6] invalidate states[0].vc_sel.`0`[7] invalidate states[0].vc_sel.`1`[0] invalidate states[0].vc_sel.`1`[1] invalidate states[0].vc_sel.`1`[2] invalidate states[0].vc_sel.`1`[3] invalidate states[0].vc_sel.`1`[4] invalidate states[0].vc_sel.`1`[5] invalidate states[0].vc_sel.`1`[6] invalidate states[0].vc_sel.`1`[7] invalidate states[0].vc_sel.`2`[0] invalidate states[0].vc_sel.`2`[1] invalidate states[0].vc_sel.`2`[2] invalidate states[0].vc_sel.`2`[3] invalidate states[0].vc_sel.`2`[4] invalidate states[0].vc_sel.`2`[5] invalidate states[0].vc_sel.`2`[6] invalidate states[0].vc_sel.`2`[7] invalidate states[0].g connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[3], UInt<1>(0h0) connect states[1].vc_sel.`1`[4], UInt<1>(0h0) connect states[1].vc_sel.`1`[5], UInt<1>(0h0) connect states[1].vc_sel.`1`[6], UInt<1>(0h0) connect states[1].vc_sel.`1`[7], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[3], UInt<1>(0h0) connect states[1].vc_sel.`2`[4], UInt<1>(0h0) connect states[1].vc_sel.`2`[5], UInt<1>(0h0) connect states[1].vc_sel.`2`[6], UInt<1>(0h0) connect states[1].vc_sel.`2`[7], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[1], UInt<1>(0h0) connect states[2].vc_sel.`2`[2], UInt<1>(0h0) connect states[2].vc_sel.`2`[3], UInt<1>(0h0) connect states[2].vc_sel.`2`[4], UInt<1>(0h0) connect states[2].vc_sel.`2`[5], UInt<1>(0h0) connect states[2].vc_sel.`2`[6], UInt<1>(0h0) connect states[2].vc_sel.`2`[7], UInt<1>(0h0) connect states[3].vc_sel.`0`[0], UInt<1>(0h0) connect states[3].vc_sel.`1`[0], UInt<1>(0h0) connect states[3].vc_sel.`2`[0], UInt<1>(0h0) connect states[3].vc_sel.`2`[1], UInt<1>(0h0) connect states[3].vc_sel.`2`[2], UInt<1>(0h0) connect states[3].vc_sel.`2`[3], UInt<1>(0h0) connect states[3].vc_sel.`2`[4], UInt<1>(0h0) connect states[3].vc_sel.`2`[5], UInt<1>(0h0) connect states[3].vc_sel.`2`[6], UInt<1>(0h0) connect states[3].vc_sel.`2`[7], UInt<1>(0h0) connect states[4].vc_sel.`0`[0], UInt<1>(0h0) connect states[4].vc_sel.`1`[0], UInt<1>(0h0) connect states[4].vc_sel.`2`[0], UInt<1>(0h0) connect states[4].vc_sel.`2`[1], UInt<1>(0h0) connect states[4].vc_sel.`2`[2], UInt<1>(0h0) connect states[4].vc_sel.`2`[3], UInt<1>(0h0) connect states[4].vc_sel.`2`[4], UInt<1>(0h0) connect states[4].vc_sel.`2`[5], UInt<1>(0h0) connect states[4].vc_sel.`2`[6], UInt<1>(0h0) connect states[4].vc_sel.`2`[7], UInt<1>(0h0) connect states[5].vc_sel.`0`[0], UInt<1>(0h0) connect states[5].vc_sel.`1`[0], UInt<1>(0h0) connect states[5].vc_sel.`2`[0], UInt<1>(0h0) connect states[5].vc_sel.`2`[1], UInt<1>(0h0) connect states[5].vc_sel.`2`[2], UInt<1>(0h0) connect states[5].vc_sel.`2`[3], UInt<1>(0h0) connect states[5].vc_sel.`2`[4], UInt<1>(0h0) connect states[5].vc_sel.`2`[5], UInt<1>(0h0) connect states[5].vc_sel.`2`[6], UInt<1>(0h0) connect states[5].vc_sel.`2`[7], UInt<1>(0h0) connect states[6].vc_sel.`0`[0], UInt<1>(0h0) connect states[6].vc_sel.`1`[0], UInt<1>(0h0) connect states[6].vc_sel.`2`[0], UInt<1>(0h0) connect states[6].vc_sel.`2`[1], UInt<1>(0h0) connect states[6].vc_sel.`2`[2], UInt<1>(0h0) connect states[6].vc_sel.`2`[3], UInt<1>(0h0) connect states[6].vc_sel.`2`[4], UInt<1>(0h0) connect states[6].vc_sel.`2`[5], UInt<1>(0h0) connect states[6].vc_sel.`2`[6], UInt<1>(0h0) connect states[6].vc_sel.`2`[7], UInt<1>(0h0) connect states[7].vc_sel.`0`[0], UInt<1>(0h0) connect states[7].vc_sel.`1`[0], UInt<1>(0h0) connect states[7].vc_sel.`2`[0], UInt<1>(0h0) connect states[7].vc_sel.`2`[1], UInt<1>(0h0) connect states[7].vc_sel.`2`[2], UInt<1>(0h0) connect states[7].vc_sel.`2`[3], UInt<1>(0h0) connect states[7].vc_sel.`2`[4], UInt<1>(0h0) connect states[7].vc_sel.`2`[5], UInt<1>(0h0) connect states[7].vc_sel.`2`[6], UInt<1>(0h0) connect states[7].vc_sel.`2`[7], UInt<1>(0h0) node _T_114 = asUInt(reset) when _T_114 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0) connect states[3].g, UInt<3>(0h0) connect states[4].g, UInt<3>(0h0) connect states[5].g, UInt<3>(0h0) connect states[6].g, UInt<3>(0h0) connect states[7].g, UInt<3>(0h0)
module InputUnit_48( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [2:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_7, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_3, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_4, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_5, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_6, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_7, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_2_3, // @[InputUnit.scala:170:14] input io_out_credit_available_2_4, // @[InputUnit.scala:170:14] input io_out_credit_available_2_5, // @[InputUnit.scala:170:14] input io_out_credit_available_2_6, // @[InputUnit.scala:170:14] input io_out_credit_available_2_7, // @[InputUnit.scala:170:14] input io_out_credit_available_1_1, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_3, // @[InputUnit.scala:170:14] input io_out_credit_available_1_4, // @[InputUnit.scala:170:14] input io_out_credit_available_1_5, // @[InputUnit.scala:170:14] input io_out_credit_available_1_6, // @[InputUnit.scala:170:14] input io_out_credit_available_1_7, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_3, // @[InputUnit.scala:170:14] input io_out_credit_available_0_4, // @[InputUnit.scala:170:14] input io_out_credit_available_0_5, // @[InputUnit.scala:170:14] input io_out_credit_available_0_6, // @[InputUnit.scala:170:14] input io_out_credit_available_0_7, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_3, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_4, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_5, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_6, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_7, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [72:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [4:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [2:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [2:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [72:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [4:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [7:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [7:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire vcalloc_vals_7; // @[InputUnit.scala:266:32] wire vcalloc_vals_6; // @[InputUnit.scala:266:32] wire vcalloc_vals_5; // @[InputUnit.scala:266:32] wire vcalloc_vals_4; // @[InputUnit.scala:266:32] wire vcalloc_vals_3; // @[InputUnit.scala:266:32] wire vcalloc_vals_2; // @[InputUnit.scala:266:32] wire vcalloc_vals_1; // @[InputUnit.scala:266:32] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_3_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_4_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_5_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_6_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_7_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [7:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_3_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_4_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_5_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_6_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_7_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [2:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_3_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_3_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_4_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_4_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_5_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_5_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_6_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_6_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_7_bits_tail; // @[InputUnit.scala:181:28] wire [72:0] _input_buffer_io_deq_7_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_3_g; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_3_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_3_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_3_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_3_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_4_g; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_4_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_4_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_4_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_4_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_5_g; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_5_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_5_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_5_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_5_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_6_g; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_6_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_6_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_6_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_6_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_7_g; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_1_7; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_1; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_2; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_3; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_4; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_5; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_6; // @[InputUnit.scala:192:19] reg states_7_vc_sel_0_7; // @[InputUnit.scala:192:19] reg [2:0] states_7_flow_vnet_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_ingress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [4:0] states_7_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_7_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_3_valid = states_3_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_4_valid = states_4_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_5_valid = states_5_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_6_valid = states_6_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] wire route_arbiter_io_in_7_valid = states_7_g == 3'h1; // @[InputUnit.scala:192:19, :229:22] reg [7:0] mask; // @[InputUnit.scala:250:21] wire [7:0] _vcalloc_filter_T_3 = {vcalloc_vals_7, vcalloc_vals_6, vcalloc_vals_5, vcalloc_vals_4, vcalloc_vals_3, vcalloc_vals_2, vcalloc_vals_1, 1'h0} & ~mask; // @[InputUnit.scala:250:21, :253:{80,87,89}, :266:32] wire [15:0] vcalloc_filter = _vcalloc_filter_T_3[0] ? 16'h1 : _vcalloc_filter_T_3[1] ? 16'h2 : _vcalloc_filter_T_3[2] ? 16'h4 : _vcalloc_filter_T_3[3] ? 16'h8 : _vcalloc_filter_T_3[4] ? 16'h10 : _vcalloc_filter_T_3[5] ? 16'h20 : _vcalloc_filter_T_3[6] ? 16'h40 : _vcalloc_filter_T_3[7] ? 16'h80 : vcalloc_vals_1 ? 16'h200 : vcalloc_vals_2 ? 16'h400 : vcalloc_vals_3 ? 16'h800 : vcalloc_vals_4 ? 16'h1000 : vcalloc_vals_5 ? 16'h2000 : vcalloc_vals_6 ? 16'h4000 : {vcalloc_vals_7, 15'h0}; // @[OneHot.scala:85:71] wire [7:0] vcalloc_sel = vcalloc_filter[7:0] | vcalloc_filter[15:8]; // @[Mux.scala:50:70] wire io_vcalloc_req_valid_0 = vcalloc_vals_1 | vcalloc_vals_2 | vcalloc_vals_3 | vcalloc_vals_4 | vcalloc_vals_5 | vcalloc_vals_6 | vcalloc_vals_7; // @[package.scala:81:59] assign vcalloc_vals_1 = states_1_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_2 = states_2_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_3 = states_3_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_4 = states_4_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_5 = states_5_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_6 = states_6_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] assign vcalloc_vals_7 = states_7_g == 3'h2; // @[InputUnit.scala:192:19, :266:32] wire _GEN_0 = io_vcalloc_req_ready & io_vcalloc_req_valid_0; // @[Decoupled.scala:51:35] wire _GEN_1 = _GEN_0 & vcalloc_sel[1]; // @[Mux.scala:32:36] wire _GEN_2 = _GEN_0 & vcalloc_sel[2]; // @[Mux.scala:32:36] wire _GEN_3 = _GEN_0 & vcalloc_sel[3]; // @[Mux.scala:32:36] wire _GEN_4 = _GEN_0 & vcalloc_sel[4]; // @[Mux.scala:32:36] wire _GEN_5 = _GEN_0 & vcalloc_sel[5]; // @[Mux.scala:32:36] wire _GEN_6 = _GEN_0 & vcalloc_sel[6]; // @[Mux.scala:32:36] wire _GEN_7 = _GEN_0 & vcalloc_sel[7]; // @[Mux.scala:32:36]
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_41 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h1)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0hf)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.a.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0hf)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE : UInt<1>[2] connect _source_ok_WIRE[0], _source_ok_T_5 connect _source_ok_WIRE[1], _source_ok_T_11 node source_ok = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<4>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 3, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<3>(0h4)) node mask_sub_sub_sub_size = bits(mask_sizeOH, 3, 3) node mask_sub_sub_sub_bit = bits(io.in.a.bits.address, 3, 3) node mask_sub_sub_sub_nbit = eq(mask_sub_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_sub_nbit) node _mask_sub_sub_sub_acc_T = and(mask_sub_sub_sub_size, mask_sub_sub_sub_0_2) node mask_sub_sub_sub_0_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T) node mask_sub_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_sub_bit) node _mask_sub_sub_sub_acc_T_1 = and(mask_sub_sub_sub_size, mask_sub_sub_sub_1_2) node mask_sub_sub_sub_1_1 = or(mask_sub_sub_sub_sub_0_1, _mask_sub_sub_sub_acc_T_1) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(mask_sub_sub_sub_0_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_sub_2_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_nbit) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size, mask_sub_sub_2_2) node mask_sub_sub_2_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_3_2 = and(mask_sub_sub_sub_1_2, mask_sub_sub_bit) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size, mask_sub_sub_3_2) node mask_sub_sub_3_1 = or(mask_sub_sub_sub_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_sub_4_2 = and(mask_sub_sub_2_2, mask_sub_nbit) node _mask_sub_acc_T_4 = and(mask_sub_size, mask_sub_4_2) node mask_sub_4_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_4) node mask_sub_5_2 = and(mask_sub_sub_2_2, mask_sub_bit) node _mask_sub_acc_T_5 = and(mask_sub_size, mask_sub_5_2) node mask_sub_5_1 = or(mask_sub_sub_2_1, _mask_sub_acc_T_5) node mask_sub_6_2 = and(mask_sub_sub_3_2, mask_sub_nbit) node _mask_sub_acc_T_6 = and(mask_sub_size, mask_sub_6_2) node mask_sub_6_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_6) node mask_sub_7_2 = and(mask_sub_sub_3_2, mask_sub_bit) node _mask_sub_acc_T_7 = and(mask_sub_size, mask_sub_7_2) node mask_sub_7_1 = or(mask_sub_sub_3_1, _mask_sub_acc_T_7) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_eq_8 = and(mask_sub_4_2, mask_nbit) node _mask_acc_T_8 = and(mask_size, mask_eq_8) node mask_acc_8 = or(mask_sub_4_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_4_2, mask_bit) node _mask_acc_T_9 = and(mask_size, mask_eq_9) node mask_acc_9 = or(mask_sub_4_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_5_2, mask_nbit) node _mask_acc_T_10 = and(mask_size, mask_eq_10) node mask_acc_10 = or(mask_sub_5_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_5_2, mask_bit) node _mask_acc_T_11 = and(mask_size, mask_eq_11) node mask_acc_11 = or(mask_sub_5_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_6_2, mask_nbit) node _mask_acc_T_12 = and(mask_size, mask_eq_12) node mask_acc_12 = or(mask_sub_6_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_6_2, mask_bit) node _mask_acc_T_13 = and(mask_size, mask_eq_13) node mask_acc_13 = or(mask_sub_6_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_7_2, mask_nbit) node _mask_acc_T_14 = and(mask_size, mask_eq_14) node mask_acc_14 = or(mask_sub_7_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_7_2, mask_bit) node _mask_acc_T_15 = and(mask_size, mask_eq_15) node mask_acc_15 = or(mask_sub_7_1, _mask_acc_T_15) node mask_lo_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo_lo = cat(mask_lo_lo_hi, mask_lo_lo_lo) node mask_lo_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_lo_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_lo_hi = cat(mask_lo_hi_hi, mask_lo_hi_lo) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo_lo = cat(mask_acc_9, mask_acc_8) node mask_hi_lo_hi = cat(mask_acc_11, mask_acc_10) node mask_hi_lo = cat(mask_hi_lo_hi, mask_hi_lo_lo) node mask_hi_hi_lo = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_hi = cat(mask_acc_15, mask_acc_14) node mask_hi_hi = cat(mask_hi_hi_hi, mask_hi_hi_lo) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h1)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0hf)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_17 = shr(io.in.a.bits.source, 4) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = leq(UInt<1>(0h0), uncommonBits_1) node _T_20 = and(_T_18, _T_19) node _T_21 = leq(uncommonBits_1, UInt<4>(0hf)) node _T_22 = and(_T_20, _T_21) node _T_23 = eq(_T_22, UInt<1>(0h0)) node _T_24 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_25 = cvt(_T_24) node _T_26 = and(_T_25, asSInt(UInt<1>(0h0))) node _T_27 = asSInt(_T_26) node _T_28 = eq(_T_27, asSInt(UInt<1>(0h0))) node _T_29 = or(_T_23, _T_28) node _T_30 = and(_T_16, _T_29) node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : node _T_33 = eq(_T_30, UInt<1>(0h0)) when _T_33 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_30, UInt<1>(0h1), "") : assert_1 node _T_34 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_34 : node _T_35 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_36 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_37 = and(_T_35, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_38 = shr(io.in.a.bits.source, 4) node _T_39 = eq(_T_38, UInt<1>(0h1)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<4>(0hf)) node _T_43 = and(_T_41, _T_42) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_44 = shr(io.in.a.bits.source, 4) node _T_45 = eq(_T_44, UInt<1>(0h0)) node _T_46 = leq(UInt<1>(0h0), uncommonBits_3) node _T_47 = and(_T_45, _T_46) node _T_48 = leq(uncommonBits_3, UInt<4>(0hf)) node _T_49 = and(_T_47, _T_48) node _T_50 = or(_T_43, _T_49) node _T_51 = and(_T_37, _T_50) node _T_52 = or(UInt<1>(0h0), _T_51) node _T_53 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_54 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_55 = cvt(_T_54) node _T_56 = and(_T_55, asSInt(UInt<14>(0h2000))) node _T_57 = asSInt(_T_56) node _T_58 = eq(_T_57, asSInt(UInt<1>(0h0))) node _T_59 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_60 = cvt(_T_59) node _T_61 = and(_T_60, asSInt(UInt<13>(0h1000))) node _T_62 = asSInt(_T_61) node _T_63 = eq(_T_62, asSInt(UInt<1>(0h0))) node _T_64 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_65 = cvt(_T_64) node _T_66 = and(_T_65, asSInt(UInt<17>(0h10000))) node _T_67 = asSInt(_T_66) node _T_68 = eq(_T_67, asSInt(UInt<1>(0h0))) node _T_69 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_70 = cvt(_T_69) node _T_71 = and(_T_70, asSInt(UInt<18>(0h2f000))) node _T_72 = asSInt(_T_71) node _T_73 = eq(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_75 = cvt(_T_74) node _T_76 = and(_T_75, asSInt(UInt<17>(0h10000))) node _T_77 = asSInt(_T_76) node _T_78 = eq(_T_77, asSInt(UInt<1>(0h0))) node _T_79 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<13>(0h1000))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_85 = cvt(_T_84) node _T_86 = and(_T_85, asSInt(UInt<27>(0h4000000))) node _T_87 = asSInt(_T_86) node _T_88 = eq(_T_87, asSInt(UInt<1>(0h0))) node _T_89 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_90 = cvt(_T_89) node _T_91 = and(_T_90, asSInt(UInt<13>(0h1000))) node _T_92 = asSInt(_T_91) node _T_93 = eq(_T_92, asSInt(UInt<1>(0h0))) node _T_94 = or(_T_58, _T_63) node _T_95 = or(_T_94, _T_68) node _T_96 = or(_T_95, _T_73) node _T_97 = or(_T_96, _T_78) node _T_98 = or(_T_97, _T_83) node _T_99 = or(_T_98, _T_88) node _T_100 = or(_T_99, _T_93) node _T_101 = and(_T_53, _T_100) node _T_102 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_103 = or(UInt<1>(0h0), _T_102) node _T_104 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_105 = cvt(_T_104) node _T_106 = and(_T_105, asSInt(UInt<17>(0h10000))) node _T_107 = asSInt(_T_106) node _T_108 = eq(_T_107, asSInt(UInt<1>(0h0))) node _T_109 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_110 = cvt(_T_109) node _T_111 = and(_T_110, asSInt(UInt<29>(0h10000000))) node _T_112 = asSInt(_T_111) node _T_113 = eq(_T_112, asSInt(UInt<1>(0h0))) node _T_114 = or(_T_108, _T_113) node _T_115 = and(_T_103, _T_114) node _T_116 = or(UInt<1>(0h0), _T_101) node _T_117 = or(_T_116, _T_115) node _T_118 = and(_T_52, _T_117) node _T_119 = asUInt(reset) node _T_120 = eq(_T_119, UInt<1>(0h0)) when _T_120 : node _T_121 = eq(_T_118, UInt<1>(0h0)) when _T_121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_118, UInt<1>(0h1), "") : assert_2 node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = or(UInt<1>(0h0), _T_124) node _T_126 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_127 = cvt(_T_126) node _T_128 = and(_T_127, asSInt(UInt<14>(0h2000))) node _T_129 = asSInt(_T_128) node _T_130 = eq(_T_129, asSInt(UInt<1>(0h0))) node _T_131 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_132 = cvt(_T_131) node _T_133 = and(_T_132, asSInt(UInt<13>(0h1000))) node _T_134 = asSInt(_T_133) node _T_135 = eq(_T_134, asSInt(UInt<1>(0h0))) node _T_136 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<18>(0h2f000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_147 = cvt(_T_146) node _T_148 = and(_T_147, asSInt(UInt<17>(0h10000))) node _T_149 = asSInt(_T_148) node _T_150 = eq(_T_149, asSInt(UInt<1>(0h0))) node _T_151 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_152 = cvt(_T_151) node _T_153 = and(_T_152, asSInt(UInt<13>(0h1000))) node _T_154 = asSInt(_T_153) node _T_155 = eq(_T_154, asSInt(UInt<1>(0h0))) node _T_156 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_157 = cvt(_T_156) node _T_158 = and(_T_157, asSInt(UInt<17>(0h10000))) node _T_159 = asSInt(_T_158) node _T_160 = eq(_T_159, asSInt(UInt<1>(0h0))) node _T_161 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_162 = cvt(_T_161) node _T_163 = and(_T_162, asSInt(UInt<27>(0h4000000))) node _T_164 = asSInt(_T_163) node _T_165 = eq(_T_164, asSInt(UInt<1>(0h0))) node _T_166 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_167 = cvt(_T_166) node _T_168 = and(_T_167, asSInt(UInt<13>(0h1000))) node _T_169 = asSInt(_T_168) node _T_170 = eq(_T_169, asSInt(UInt<1>(0h0))) node _T_171 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_172 = cvt(_T_171) node _T_173 = and(_T_172, asSInt(UInt<29>(0h10000000))) node _T_174 = asSInt(_T_173) node _T_175 = eq(_T_174, asSInt(UInt<1>(0h0))) node _T_176 = or(_T_130, _T_135) node _T_177 = or(_T_176, _T_140) node _T_178 = or(_T_177, _T_145) node _T_179 = or(_T_178, _T_150) node _T_180 = or(_T_179, _T_155) node _T_181 = or(_T_180, _T_160) node _T_182 = or(_T_181, _T_165) node _T_183 = or(_T_182, _T_170) node _T_184 = or(_T_183, _T_175) node _T_185 = and(_T_125, _T_184) node _T_186 = or(UInt<1>(0h0), _T_185) node _T_187 = and(UInt<1>(0h0), _T_186) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_187, UInt<1>(0h1), "") : assert_3 node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(source_ok, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_194 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_194, UInt<1>(0h1), "") : assert_5 node _T_198 = asUInt(reset) node _T_199 = eq(_T_198, UInt<1>(0h0)) when _T_199 : node _T_200 = eq(is_aligned, UInt<1>(0h0)) when _T_200 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_201 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_202 = asUInt(reset) node _T_203 = eq(_T_202, UInt<1>(0h0)) when _T_203 : node _T_204 = eq(_T_201, UInt<1>(0h0)) when _T_204 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_201, UInt<1>(0h1), "") : assert_7 node _T_205 = not(io.in.a.bits.mask) node _T_206 = eq(_T_205, UInt<1>(0h0)) node _T_207 = asUInt(reset) node _T_208 = eq(_T_207, UInt<1>(0h0)) when _T_208 : node _T_209 = eq(_T_206, UInt<1>(0h0)) when _T_209 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_206, UInt<1>(0h1), "") : assert_8 node _T_210 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_211 = asUInt(reset) node _T_212 = eq(_T_211, UInt<1>(0h0)) when _T_212 : node _T_213 = eq(_T_210, UInt<1>(0h0)) when _T_213 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_210, UInt<1>(0h1), "") : assert_9 node _T_214 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_214 : node _T_215 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_216 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_217 = and(_T_215, _T_216) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_218 = shr(io.in.a.bits.source, 4) node _T_219 = eq(_T_218, UInt<1>(0h1)) node _T_220 = leq(UInt<1>(0h0), uncommonBits_4) node _T_221 = and(_T_219, _T_220) node _T_222 = leq(uncommonBits_4, UInt<4>(0hf)) node _T_223 = and(_T_221, _T_222) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_224 = shr(io.in.a.bits.source, 4) node _T_225 = eq(_T_224, UInt<1>(0h0)) node _T_226 = leq(UInt<1>(0h0), uncommonBits_5) node _T_227 = and(_T_225, _T_226) node _T_228 = leq(uncommonBits_5, UInt<4>(0hf)) node _T_229 = and(_T_227, _T_228) node _T_230 = or(_T_223, _T_229) node _T_231 = and(_T_217, _T_230) node _T_232 = or(UInt<1>(0h0), _T_231) node _T_233 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_234 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_235 = cvt(_T_234) node _T_236 = and(_T_235, asSInt(UInt<14>(0h2000))) node _T_237 = asSInt(_T_236) node _T_238 = eq(_T_237, asSInt(UInt<1>(0h0))) node _T_239 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_240 = cvt(_T_239) node _T_241 = and(_T_240, asSInt(UInt<13>(0h1000))) node _T_242 = asSInt(_T_241) node _T_243 = eq(_T_242, asSInt(UInt<1>(0h0))) node _T_244 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_245 = cvt(_T_244) node _T_246 = and(_T_245, asSInt(UInt<17>(0h10000))) node _T_247 = asSInt(_T_246) node _T_248 = eq(_T_247, asSInt(UInt<1>(0h0))) node _T_249 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<18>(0h2f000))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<17>(0h10000))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_260 = cvt(_T_259) node _T_261 = and(_T_260, asSInt(UInt<13>(0h1000))) node _T_262 = asSInt(_T_261) node _T_263 = eq(_T_262, asSInt(UInt<1>(0h0))) node _T_264 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_265 = cvt(_T_264) node _T_266 = and(_T_265, asSInt(UInt<27>(0h4000000))) node _T_267 = asSInt(_T_266) node _T_268 = eq(_T_267, asSInt(UInt<1>(0h0))) node _T_269 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_270 = cvt(_T_269) node _T_271 = and(_T_270, asSInt(UInt<13>(0h1000))) node _T_272 = asSInt(_T_271) node _T_273 = eq(_T_272, asSInt(UInt<1>(0h0))) node _T_274 = or(_T_238, _T_243) node _T_275 = or(_T_274, _T_248) node _T_276 = or(_T_275, _T_253) node _T_277 = or(_T_276, _T_258) node _T_278 = or(_T_277, _T_263) node _T_279 = or(_T_278, _T_268) node _T_280 = or(_T_279, _T_273) node _T_281 = and(_T_233, _T_280) node _T_282 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_283 = or(UInt<1>(0h0), _T_282) node _T_284 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_285 = cvt(_T_284) node _T_286 = and(_T_285, asSInt(UInt<17>(0h10000))) node _T_287 = asSInt(_T_286) node _T_288 = eq(_T_287, asSInt(UInt<1>(0h0))) node _T_289 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_290 = cvt(_T_289) node _T_291 = and(_T_290, asSInt(UInt<29>(0h10000000))) node _T_292 = asSInt(_T_291) node _T_293 = eq(_T_292, asSInt(UInt<1>(0h0))) node _T_294 = or(_T_288, _T_293) node _T_295 = and(_T_283, _T_294) node _T_296 = or(UInt<1>(0h0), _T_281) node _T_297 = or(_T_296, _T_295) node _T_298 = and(_T_232, _T_297) node _T_299 = asUInt(reset) node _T_300 = eq(_T_299, UInt<1>(0h0)) when _T_300 : node _T_301 = eq(_T_298, UInt<1>(0h0)) when _T_301 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_298, UInt<1>(0h1), "") : assert_10 node _T_302 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_303 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_304 = and(_T_302, _T_303) node _T_305 = or(UInt<1>(0h0), _T_304) node _T_306 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_307 = cvt(_T_306) node _T_308 = and(_T_307, asSInt(UInt<14>(0h2000))) node _T_309 = asSInt(_T_308) node _T_310 = eq(_T_309, asSInt(UInt<1>(0h0))) node _T_311 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_312 = cvt(_T_311) node _T_313 = and(_T_312, asSInt(UInt<13>(0h1000))) node _T_314 = asSInt(_T_313) node _T_315 = eq(_T_314, asSInt(UInt<1>(0h0))) node _T_316 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_317 = cvt(_T_316) node _T_318 = and(_T_317, asSInt(UInt<17>(0h10000))) node _T_319 = asSInt(_T_318) node _T_320 = eq(_T_319, asSInt(UInt<1>(0h0))) node _T_321 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_322 = cvt(_T_321) node _T_323 = and(_T_322, asSInt(UInt<18>(0h2f000))) node _T_324 = asSInt(_T_323) node _T_325 = eq(_T_324, asSInt(UInt<1>(0h0))) node _T_326 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_327 = cvt(_T_326) node _T_328 = and(_T_327, asSInt(UInt<17>(0h10000))) node _T_329 = asSInt(_T_328) node _T_330 = eq(_T_329, asSInt(UInt<1>(0h0))) node _T_331 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_332 = cvt(_T_331) node _T_333 = and(_T_332, asSInt(UInt<13>(0h1000))) node _T_334 = asSInt(_T_333) node _T_335 = eq(_T_334, asSInt(UInt<1>(0h0))) node _T_336 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_337 = cvt(_T_336) node _T_338 = and(_T_337, asSInt(UInt<17>(0h10000))) node _T_339 = asSInt(_T_338) node _T_340 = eq(_T_339, asSInt(UInt<1>(0h0))) node _T_341 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_342 = cvt(_T_341) node _T_343 = and(_T_342, asSInt(UInt<27>(0h4000000))) node _T_344 = asSInt(_T_343) node _T_345 = eq(_T_344, asSInt(UInt<1>(0h0))) node _T_346 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_347 = cvt(_T_346) node _T_348 = and(_T_347, asSInt(UInt<13>(0h1000))) node _T_349 = asSInt(_T_348) node _T_350 = eq(_T_349, asSInt(UInt<1>(0h0))) node _T_351 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_352 = cvt(_T_351) node _T_353 = and(_T_352, asSInt(UInt<29>(0h10000000))) node _T_354 = asSInt(_T_353) node _T_355 = eq(_T_354, asSInt(UInt<1>(0h0))) node _T_356 = or(_T_310, _T_315) node _T_357 = or(_T_356, _T_320) node _T_358 = or(_T_357, _T_325) node _T_359 = or(_T_358, _T_330) node _T_360 = or(_T_359, _T_335) node _T_361 = or(_T_360, _T_340) node _T_362 = or(_T_361, _T_345) node _T_363 = or(_T_362, _T_350) node _T_364 = or(_T_363, _T_355) node _T_365 = and(_T_305, _T_364) node _T_366 = or(UInt<1>(0h0), _T_365) node _T_367 = and(UInt<1>(0h0), _T_366) node _T_368 = asUInt(reset) node _T_369 = eq(_T_368, UInt<1>(0h0)) when _T_369 : node _T_370 = eq(_T_367, UInt<1>(0h0)) when _T_370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_367, UInt<1>(0h1), "") : assert_11 node _T_371 = asUInt(reset) node _T_372 = eq(_T_371, UInt<1>(0h0)) when _T_372 : node _T_373 = eq(source_ok, UInt<1>(0h0)) when _T_373 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_374 = geq(io.in.a.bits.size, UInt<3>(0h4)) node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(_T_374, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_374, UInt<1>(0h1), "") : assert_13 node _T_378 = asUInt(reset) node _T_379 = eq(_T_378, UInt<1>(0h0)) when _T_379 : node _T_380 = eq(is_aligned, UInt<1>(0h0)) when _T_380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_381 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_382 = asUInt(reset) node _T_383 = eq(_T_382, UInt<1>(0h0)) when _T_383 : node _T_384 = eq(_T_381, UInt<1>(0h0)) when _T_384 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_381, UInt<1>(0h1), "") : assert_15 node _T_385 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_386 = asUInt(reset) node _T_387 = eq(_T_386, UInt<1>(0h0)) when _T_387 : node _T_388 = eq(_T_385, UInt<1>(0h0)) when _T_388 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_385, UInt<1>(0h1), "") : assert_16 node _T_389 = not(io.in.a.bits.mask) node _T_390 = eq(_T_389, UInt<1>(0h0)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_390, UInt<1>(0h1), "") : assert_17 node _T_394 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_T_394, UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_394, UInt<1>(0h1), "") : assert_18 node _T_398 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_398 : node _T_399 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_400 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_401 = and(_T_399, _T_400) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_402 = shr(io.in.a.bits.source, 4) node _T_403 = eq(_T_402, UInt<1>(0h1)) node _T_404 = leq(UInt<1>(0h0), uncommonBits_6) node _T_405 = and(_T_403, _T_404) node _T_406 = leq(uncommonBits_6, UInt<4>(0hf)) node _T_407 = and(_T_405, _T_406) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_408 = shr(io.in.a.bits.source, 4) node _T_409 = eq(_T_408, UInt<1>(0h0)) node _T_410 = leq(UInt<1>(0h0), uncommonBits_7) node _T_411 = and(_T_409, _T_410) node _T_412 = leq(uncommonBits_7, UInt<4>(0hf)) node _T_413 = and(_T_411, _T_412) node _T_414 = or(_T_407, _T_413) node _T_415 = and(_T_401, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = asUInt(reset) node _T_418 = eq(_T_417, UInt<1>(0h0)) when _T_418 : node _T_419 = eq(_T_416, UInt<1>(0h0)) when _T_419 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_416, UInt<1>(0h1), "") : assert_19 node _T_420 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_421 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_422 = and(_T_420, _T_421) node _T_423 = or(UInt<1>(0h0), _T_422) node _T_424 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_425 = cvt(_T_424) node _T_426 = and(_T_425, asSInt(UInt<13>(0h1000))) node _T_427 = asSInt(_T_426) node _T_428 = eq(_T_427, asSInt(UInt<1>(0h0))) node _T_429 = and(_T_423, _T_428) node _T_430 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_431 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_432 = and(_T_430, _T_431) node _T_433 = or(UInt<1>(0h0), _T_432) node _T_434 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_435 = cvt(_T_434) node _T_436 = and(_T_435, asSInt(UInt<14>(0h2000))) node _T_437 = asSInt(_T_436) node _T_438 = eq(_T_437, asSInt(UInt<1>(0h0))) node _T_439 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_440 = cvt(_T_439) node _T_441 = and(_T_440, asSInt(UInt<17>(0h10000))) node _T_442 = asSInt(_T_441) node _T_443 = eq(_T_442, asSInt(UInt<1>(0h0))) node _T_444 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_445 = cvt(_T_444) node _T_446 = and(_T_445, asSInt(UInt<18>(0h2f000))) node _T_447 = asSInt(_T_446) node _T_448 = eq(_T_447, asSInt(UInt<1>(0h0))) node _T_449 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_450 = cvt(_T_449) node _T_451 = and(_T_450, asSInt(UInt<17>(0h10000))) node _T_452 = asSInt(_T_451) node _T_453 = eq(_T_452, asSInt(UInt<1>(0h0))) node _T_454 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_455 = cvt(_T_454) node _T_456 = and(_T_455, asSInt(UInt<13>(0h1000))) node _T_457 = asSInt(_T_456) node _T_458 = eq(_T_457, asSInt(UInt<1>(0h0))) node _T_459 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_460 = cvt(_T_459) node _T_461 = and(_T_460, asSInt(UInt<17>(0h10000))) node _T_462 = asSInt(_T_461) node _T_463 = eq(_T_462, asSInt(UInt<1>(0h0))) node _T_464 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_465 = cvt(_T_464) node _T_466 = and(_T_465, asSInt(UInt<27>(0h4000000))) node _T_467 = asSInt(_T_466) node _T_468 = eq(_T_467, asSInt(UInt<1>(0h0))) node _T_469 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_470 = cvt(_T_469) node _T_471 = and(_T_470, asSInt(UInt<13>(0h1000))) node _T_472 = asSInt(_T_471) node _T_473 = eq(_T_472, asSInt(UInt<1>(0h0))) node _T_474 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_475 = cvt(_T_474) node _T_476 = and(_T_475, asSInt(UInt<29>(0h10000000))) node _T_477 = asSInt(_T_476) node _T_478 = eq(_T_477, asSInt(UInt<1>(0h0))) node _T_479 = or(_T_438, _T_443) node _T_480 = or(_T_479, _T_448) node _T_481 = or(_T_480, _T_453) node _T_482 = or(_T_481, _T_458) node _T_483 = or(_T_482, _T_463) node _T_484 = or(_T_483, _T_468) node _T_485 = or(_T_484, _T_473) node _T_486 = or(_T_485, _T_478) node _T_487 = and(_T_433, _T_486) node _T_488 = or(UInt<1>(0h0), _T_429) node _T_489 = or(_T_488, _T_487) node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_T_489, UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_489, UInt<1>(0h1), "") : assert_20 node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(source_ok, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_496 = asUInt(reset) node _T_497 = eq(_T_496, UInt<1>(0h0)) when _T_497 : node _T_498 = eq(is_aligned, UInt<1>(0h0)) when _T_498 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_499 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_500 = asUInt(reset) node _T_501 = eq(_T_500, UInt<1>(0h0)) when _T_501 : node _T_502 = eq(_T_499, UInt<1>(0h0)) when _T_502 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_499, UInt<1>(0h1), "") : assert_23 node _T_503 = eq(io.in.a.bits.mask, mask) node _T_504 = asUInt(reset) node _T_505 = eq(_T_504, UInt<1>(0h0)) when _T_505 : node _T_506 = eq(_T_503, UInt<1>(0h0)) when _T_506 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_503, UInt<1>(0h1), "") : assert_24 node _T_507 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_508 = asUInt(reset) node _T_509 = eq(_T_508, UInt<1>(0h0)) when _T_509 : node _T_510 = eq(_T_507, UInt<1>(0h0)) when _T_510 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_507, UInt<1>(0h1), "") : assert_25 node _T_511 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_511 : node _T_512 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_513 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_514 = and(_T_512, _T_513) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_515 = shr(io.in.a.bits.source, 4) node _T_516 = eq(_T_515, UInt<1>(0h1)) node _T_517 = leq(UInt<1>(0h0), uncommonBits_8) node _T_518 = and(_T_516, _T_517) node _T_519 = leq(uncommonBits_8, UInt<4>(0hf)) node _T_520 = and(_T_518, _T_519) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_521 = shr(io.in.a.bits.source, 4) node _T_522 = eq(_T_521, UInt<1>(0h0)) node _T_523 = leq(UInt<1>(0h0), uncommonBits_9) node _T_524 = and(_T_522, _T_523) node _T_525 = leq(uncommonBits_9, UInt<4>(0hf)) node _T_526 = and(_T_524, _T_525) node _T_527 = or(_T_520, _T_526) node _T_528 = and(_T_514, _T_527) node _T_529 = or(UInt<1>(0h0), _T_528) node _T_530 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_531 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_532 = and(_T_530, _T_531) node _T_533 = or(UInt<1>(0h0), _T_532) node _T_534 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_535 = cvt(_T_534) node _T_536 = and(_T_535, asSInt(UInt<13>(0h1000))) node _T_537 = asSInt(_T_536) node _T_538 = eq(_T_537, asSInt(UInt<1>(0h0))) node _T_539 = and(_T_533, _T_538) node _T_540 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_541 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_542 = and(_T_540, _T_541) node _T_543 = or(UInt<1>(0h0), _T_542) node _T_544 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_545 = cvt(_T_544) node _T_546 = and(_T_545, asSInt(UInt<14>(0h2000))) node _T_547 = asSInt(_T_546) node _T_548 = eq(_T_547, asSInt(UInt<1>(0h0))) node _T_549 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_550 = cvt(_T_549) node _T_551 = and(_T_550, asSInt(UInt<18>(0h2f000))) node _T_552 = asSInt(_T_551) node _T_553 = eq(_T_552, asSInt(UInt<1>(0h0))) node _T_554 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_555 = cvt(_T_554) node _T_556 = and(_T_555, asSInt(UInt<17>(0h10000))) node _T_557 = asSInt(_T_556) node _T_558 = eq(_T_557, asSInt(UInt<1>(0h0))) node _T_559 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_560 = cvt(_T_559) node _T_561 = and(_T_560, asSInt(UInt<13>(0h1000))) node _T_562 = asSInt(_T_561) node _T_563 = eq(_T_562, asSInt(UInt<1>(0h0))) node _T_564 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_565 = cvt(_T_564) node _T_566 = and(_T_565, asSInt(UInt<17>(0h10000))) node _T_567 = asSInt(_T_566) node _T_568 = eq(_T_567, asSInt(UInt<1>(0h0))) node _T_569 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_570 = cvt(_T_569) node _T_571 = and(_T_570, asSInt(UInt<27>(0h4000000))) node _T_572 = asSInt(_T_571) node _T_573 = eq(_T_572, asSInt(UInt<1>(0h0))) node _T_574 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<13>(0h1000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_580 = cvt(_T_579) node _T_581 = and(_T_580, asSInt(UInt<29>(0h10000000))) node _T_582 = asSInt(_T_581) node _T_583 = eq(_T_582, asSInt(UInt<1>(0h0))) node _T_584 = or(_T_548, _T_553) node _T_585 = or(_T_584, _T_558) node _T_586 = or(_T_585, _T_563) node _T_587 = or(_T_586, _T_568) node _T_588 = or(_T_587, _T_573) node _T_589 = or(_T_588, _T_578) node _T_590 = or(_T_589, _T_583) node _T_591 = and(_T_543, _T_590) node _T_592 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_593 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_594 = cvt(_T_593) node _T_595 = and(_T_594, asSInt(UInt<17>(0h10000))) node _T_596 = asSInt(_T_595) node _T_597 = eq(_T_596, asSInt(UInt<1>(0h0))) node _T_598 = and(_T_592, _T_597) node _T_599 = or(UInt<1>(0h0), _T_539) node _T_600 = or(_T_599, _T_591) node _T_601 = or(_T_600, _T_598) node _T_602 = and(_T_529, _T_601) node _T_603 = asUInt(reset) node _T_604 = eq(_T_603, UInt<1>(0h0)) when _T_604 : node _T_605 = eq(_T_602, UInt<1>(0h0)) when _T_605 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_602, UInt<1>(0h1), "") : assert_26 node _T_606 = asUInt(reset) node _T_607 = eq(_T_606, UInt<1>(0h0)) when _T_607 : node _T_608 = eq(source_ok, UInt<1>(0h0)) when _T_608 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_609 = asUInt(reset) node _T_610 = eq(_T_609, UInt<1>(0h0)) when _T_610 : node _T_611 = eq(is_aligned, UInt<1>(0h0)) when _T_611 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_612 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_613 = asUInt(reset) node _T_614 = eq(_T_613, UInt<1>(0h0)) when _T_614 : node _T_615 = eq(_T_612, UInt<1>(0h0)) when _T_615 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_612, UInt<1>(0h1), "") : assert_29 node _T_616 = eq(io.in.a.bits.mask, mask) node _T_617 = asUInt(reset) node _T_618 = eq(_T_617, UInt<1>(0h0)) when _T_618 : node _T_619 = eq(_T_616, UInt<1>(0h0)) when _T_619 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_616, UInt<1>(0h1), "") : assert_30 node _T_620 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_620 : node _T_621 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_622 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_623 = and(_T_621, _T_622) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_624 = shr(io.in.a.bits.source, 4) node _T_625 = eq(_T_624, UInt<1>(0h1)) node _T_626 = leq(UInt<1>(0h0), uncommonBits_10) node _T_627 = and(_T_625, _T_626) node _T_628 = leq(uncommonBits_10, UInt<4>(0hf)) node _T_629 = and(_T_627, _T_628) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_630 = shr(io.in.a.bits.source, 4) node _T_631 = eq(_T_630, UInt<1>(0h0)) node _T_632 = leq(UInt<1>(0h0), uncommonBits_11) node _T_633 = and(_T_631, _T_632) node _T_634 = leq(uncommonBits_11, UInt<4>(0hf)) node _T_635 = and(_T_633, _T_634) node _T_636 = or(_T_629, _T_635) node _T_637 = and(_T_623, _T_636) node _T_638 = or(UInt<1>(0h0), _T_637) node _T_639 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_640 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_641 = and(_T_639, _T_640) node _T_642 = or(UInt<1>(0h0), _T_641) node _T_643 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_644 = cvt(_T_643) node _T_645 = and(_T_644, asSInt(UInt<13>(0h1000))) node _T_646 = asSInt(_T_645) node _T_647 = eq(_T_646, asSInt(UInt<1>(0h0))) node _T_648 = and(_T_642, _T_647) node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_650 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_651 = and(_T_649, _T_650) node _T_652 = or(UInt<1>(0h0), _T_651) node _T_653 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<14>(0h2000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_659 = cvt(_T_658) node _T_660 = and(_T_659, asSInt(UInt<18>(0h2f000))) node _T_661 = asSInt(_T_660) node _T_662 = eq(_T_661, asSInt(UInt<1>(0h0))) node _T_663 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_664 = cvt(_T_663) node _T_665 = and(_T_664, asSInt(UInt<17>(0h10000))) node _T_666 = asSInt(_T_665) node _T_667 = eq(_T_666, asSInt(UInt<1>(0h0))) node _T_668 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_669 = cvt(_T_668) node _T_670 = and(_T_669, asSInt(UInt<13>(0h1000))) node _T_671 = asSInt(_T_670) node _T_672 = eq(_T_671, asSInt(UInt<1>(0h0))) node _T_673 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_674 = cvt(_T_673) node _T_675 = and(_T_674, asSInt(UInt<17>(0h10000))) node _T_676 = asSInt(_T_675) node _T_677 = eq(_T_676, asSInt(UInt<1>(0h0))) node _T_678 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_679 = cvt(_T_678) node _T_680 = and(_T_679, asSInt(UInt<27>(0h4000000))) node _T_681 = asSInt(_T_680) node _T_682 = eq(_T_681, asSInt(UInt<1>(0h0))) node _T_683 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_684 = cvt(_T_683) node _T_685 = and(_T_684, asSInt(UInt<13>(0h1000))) node _T_686 = asSInt(_T_685) node _T_687 = eq(_T_686, asSInt(UInt<1>(0h0))) node _T_688 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_689 = cvt(_T_688) node _T_690 = and(_T_689, asSInt(UInt<29>(0h10000000))) node _T_691 = asSInt(_T_690) node _T_692 = eq(_T_691, asSInt(UInt<1>(0h0))) node _T_693 = or(_T_657, _T_662) node _T_694 = or(_T_693, _T_667) node _T_695 = or(_T_694, _T_672) node _T_696 = or(_T_695, _T_677) node _T_697 = or(_T_696, _T_682) node _T_698 = or(_T_697, _T_687) node _T_699 = or(_T_698, _T_692) node _T_700 = and(_T_652, _T_699) node _T_701 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_702 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_703 = cvt(_T_702) node _T_704 = and(_T_703, asSInt(UInt<17>(0h10000))) node _T_705 = asSInt(_T_704) node _T_706 = eq(_T_705, asSInt(UInt<1>(0h0))) node _T_707 = and(_T_701, _T_706) node _T_708 = or(UInt<1>(0h0), _T_648) node _T_709 = or(_T_708, _T_700) node _T_710 = or(_T_709, _T_707) node _T_711 = and(_T_638, _T_710) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_711, UInt<1>(0h1), "") : assert_31 node _T_715 = asUInt(reset) node _T_716 = eq(_T_715, UInt<1>(0h0)) when _T_716 : node _T_717 = eq(source_ok, UInt<1>(0h0)) when _T_717 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_718 = asUInt(reset) node _T_719 = eq(_T_718, UInt<1>(0h0)) when _T_719 : node _T_720 = eq(is_aligned, UInt<1>(0h0)) when _T_720 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_721 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_722 = asUInt(reset) node _T_723 = eq(_T_722, UInt<1>(0h0)) when _T_723 : node _T_724 = eq(_T_721, UInt<1>(0h0)) when _T_724 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_721, UInt<1>(0h1), "") : assert_34 node _T_725 = not(mask) node _T_726 = and(io.in.a.bits.mask, _T_725) node _T_727 = eq(_T_726, UInt<1>(0h0)) node _T_728 = asUInt(reset) node _T_729 = eq(_T_728, UInt<1>(0h0)) when _T_729 : node _T_730 = eq(_T_727, UInt<1>(0h0)) when _T_730 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_727, UInt<1>(0h1), "") : assert_35 node _T_731 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_731 : node _T_732 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_733 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_734 = and(_T_732, _T_733) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_735 = shr(io.in.a.bits.source, 4) node _T_736 = eq(_T_735, UInt<1>(0h1)) node _T_737 = leq(UInt<1>(0h0), uncommonBits_12) node _T_738 = and(_T_736, _T_737) node _T_739 = leq(uncommonBits_12, UInt<4>(0hf)) node _T_740 = and(_T_738, _T_739) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 3, 0) node _T_741 = shr(io.in.a.bits.source, 4) node _T_742 = eq(_T_741, UInt<1>(0h0)) node _T_743 = leq(UInt<1>(0h0), uncommonBits_13) node _T_744 = and(_T_742, _T_743) node _T_745 = leq(uncommonBits_13, UInt<4>(0hf)) node _T_746 = and(_T_744, _T_745) node _T_747 = or(_T_740, _T_746) node _T_748 = and(_T_734, _T_747) node _T_749 = or(UInt<1>(0h0), _T_748) node _T_750 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_751 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_752 = and(_T_750, _T_751) node _T_753 = or(UInt<1>(0h0), _T_752) node _T_754 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<14>(0h2000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_760 = cvt(_T_759) node _T_761 = and(_T_760, asSInt(UInt<13>(0h1000))) node _T_762 = asSInt(_T_761) node _T_763 = eq(_T_762, asSInt(UInt<1>(0h0))) node _T_764 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_765 = cvt(_T_764) node _T_766 = and(_T_765, asSInt(UInt<18>(0h2f000))) node _T_767 = asSInt(_T_766) node _T_768 = eq(_T_767, asSInt(UInt<1>(0h0))) node _T_769 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_770 = cvt(_T_769) node _T_771 = and(_T_770, asSInt(UInt<17>(0h10000))) node _T_772 = asSInt(_T_771) node _T_773 = eq(_T_772, asSInt(UInt<1>(0h0))) node _T_774 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_775 = cvt(_T_774) node _T_776 = and(_T_775, asSInt(UInt<13>(0h1000))) node _T_777 = asSInt(_T_776) node _T_778 = eq(_T_777, asSInt(UInt<1>(0h0))) node _T_779 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_780 = cvt(_T_779) node _T_781 = and(_T_780, asSInt(UInt<27>(0h4000000))) node _T_782 = asSInt(_T_781) node _T_783 = eq(_T_782, asSInt(UInt<1>(0h0))) node _T_784 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_785 = cvt(_T_784) node _T_786 = and(_T_785, asSInt(UInt<13>(0h1000))) node _T_787 = asSInt(_T_786) node _T_788 = eq(_T_787, asSInt(UInt<1>(0h0))) node _T_789 = or(_T_758, _T_763) node _T_790 = or(_T_789, _T_768) node _T_791 = or(_T_790, _T_773) node _T_792 = or(_T_791, _T_778) node _T_793 = or(_T_792, _T_783) node _T_794 = or(_T_793, _T_788) node _T_795 = and(_T_753, _T_794) node _T_796 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_797 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<17>(0h10000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = and(_T_796, _T_801) node _T_803 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_804 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_805 = and(_T_803, _T_804) node _T_806 = or(UInt<1>(0h0), _T_805) node _T_807 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_808 = cvt(_T_807) node _T_809 = and(_T_808, asSInt(UInt<17>(0h10000))) node _T_810 = asSInt(_T_809) node _T_811 = eq(_T_810, asSInt(UInt<1>(0h0))) node _T_812 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_813 = cvt(_T_812) node _T_814 = and(_T_813, asSInt(UInt<29>(0h10000000))) node _T_815 = asSInt(_T_814) node _T_816 = eq(_T_815, asSInt(UInt<1>(0h0))) node _T_817 = or(_T_811, _T_816) node _T_818 = and(_T_806, _T_817) node _T_819 = or(UInt<1>(0h0), _T_795) node _T_820 = or(_T_819, _T_802) node _T_821 = or(_T_820, _T_818) node _T_822 = and(_T_749, _T_821) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_822, UInt<1>(0h1), "") : assert_36 node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(source_ok, UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(is_aligned, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_832 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_832, UInt<1>(0h1), "") : assert_39 node _T_836 = eq(io.in.a.bits.mask, mask) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_836, UInt<1>(0h1), "") : assert_40 node _T_840 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_840 : node _T_841 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_842 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_843 = and(_T_841, _T_842) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 3, 0) node _T_844 = shr(io.in.a.bits.source, 4) node _T_845 = eq(_T_844, UInt<1>(0h1)) node _T_846 = leq(UInt<1>(0h0), uncommonBits_14) node _T_847 = and(_T_845, _T_846) node _T_848 = leq(uncommonBits_14, UInt<4>(0hf)) node _T_849 = and(_T_847, _T_848) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 3, 0) node _T_850 = shr(io.in.a.bits.source, 4) node _T_851 = eq(_T_850, UInt<1>(0h0)) node _T_852 = leq(UInt<1>(0h0), uncommonBits_15) node _T_853 = and(_T_851, _T_852) node _T_854 = leq(uncommonBits_15, UInt<4>(0hf)) node _T_855 = and(_T_853, _T_854) node _T_856 = or(_T_849, _T_855) node _T_857 = and(_T_843, _T_856) node _T_858 = or(UInt<1>(0h0), _T_857) node _T_859 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_860 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_861 = and(_T_859, _T_860) node _T_862 = or(UInt<1>(0h0), _T_861) node _T_863 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_864 = cvt(_T_863) node _T_865 = and(_T_864, asSInt(UInt<14>(0h2000))) node _T_866 = asSInt(_T_865) node _T_867 = eq(_T_866, asSInt(UInt<1>(0h0))) node _T_868 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_869 = cvt(_T_868) node _T_870 = and(_T_869, asSInt(UInt<13>(0h1000))) node _T_871 = asSInt(_T_870) node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0))) node _T_873 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<18>(0h2f000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_879 = cvt(_T_878) node _T_880 = and(_T_879, asSInt(UInt<17>(0h10000))) node _T_881 = asSInt(_T_880) node _T_882 = eq(_T_881, asSInt(UInt<1>(0h0))) node _T_883 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_884 = cvt(_T_883) node _T_885 = and(_T_884, asSInt(UInt<13>(0h1000))) node _T_886 = asSInt(_T_885) node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0))) node _T_888 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_889 = cvt(_T_888) node _T_890 = and(_T_889, asSInt(UInt<27>(0h4000000))) node _T_891 = asSInt(_T_890) node _T_892 = eq(_T_891, asSInt(UInt<1>(0h0))) node _T_893 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_894 = cvt(_T_893) node _T_895 = and(_T_894, asSInt(UInt<13>(0h1000))) node _T_896 = asSInt(_T_895) node _T_897 = eq(_T_896, asSInt(UInt<1>(0h0))) node _T_898 = or(_T_867, _T_872) node _T_899 = or(_T_898, _T_877) node _T_900 = or(_T_899, _T_882) node _T_901 = or(_T_900, _T_887) node _T_902 = or(_T_901, _T_892) node _T_903 = or(_T_902, _T_897) node _T_904 = and(_T_862, _T_903) node _T_905 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_906 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_907 = cvt(_T_906) node _T_908 = and(_T_907, asSInt(UInt<17>(0h10000))) node _T_909 = asSInt(_T_908) node _T_910 = eq(_T_909, asSInt(UInt<1>(0h0))) node _T_911 = and(_T_905, _T_910) node _T_912 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_913 = leq(io.in.a.bits.size, UInt<3>(0h4)) node _T_914 = and(_T_912, _T_913) node _T_915 = or(UInt<1>(0h0), _T_914) node _T_916 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_917 = cvt(_T_916) node _T_918 = and(_T_917, asSInt(UInt<17>(0h10000))) node _T_919 = asSInt(_T_918) node _T_920 = eq(_T_919, asSInt(UInt<1>(0h0))) node _T_921 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_922 = cvt(_T_921) node _T_923 = and(_T_922, asSInt(UInt<29>(0h10000000))) node _T_924 = asSInt(_T_923) node _T_925 = eq(_T_924, asSInt(UInt<1>(0h0))) node _T_926 = or(_T_920, _T_925) node _T_927 = and(_T_915, _T_926) node _T_928 = or(UInt<1>(0h0), _T_904) node _T_929 = or(_T_928, _T_911) node _T_930 = or(_T_929, _T_927) node _T_931 = and(_T_858, _T_930) node _T_932 = asUInt(reset) node _T_933 = eq(_T_932, UInt<1>(0h0)) when _T_933 : node _T_934 = eq(_T_931, UInt<1>(0h0)) when _T_934 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_931, UInt<1>(0h1), "") : assert_41 node _T_935 = asUInt(reset) node _T_936 = eq(_T_935, UInt<1>(0h0)) when _T_936 : node _T_937 = eq(source_ok, UInt<1>(0h0)) when _T_937 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_938 = asUInt(reset) node _T_939 = eq(_T_938, UInt<1>(0h0)) when _T_939 : node _T_940 = eq(is_aligned, UInt<1>(0h0)) when _T_940 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_941 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_942 = asUInt(reset) node _T_943 = eq(_T_942, UInt<1>(0h0)) when _T_943 : node _T_944 = eq(_T_941, UInt<1>(0h0)) when _T_944 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_941, UInt<1>(0h1), "") : assert_44 node _T_945 = eq(io.in.a.bits.mask, mask) node _T_946 = asUInt(reset) node _T_947 = eq(_T_946, UInt<1>(0h0)) when _T_947 : node _T_948 = eq(_T_945, UInt<1>(0h0)) when _T_948 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_945, UInt<1>(0h1), "") : assert_45 node _T_949 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_949 : node _T_950 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_951 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_952 = and(_T_950, _T_951) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 3, 0) node _T_953 = shr(io.in.a.bits.source, 4) node _T_954 = eq(_T_953, UInt<1>(0h1)) node _T_955 = leq(UInt<1>(0h0), uncommonBits_16) node _T_956 = and(_T_954, _T_955) node _T_957 = leq(uncommonBits_16, UInt<4>(0hf)) node _T_958 = and(_T_956, _T_957) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 3, 0) node _T_959 = shr(io.in.a.bits.source, 4) node _T_960 = eq(_T_959, UInt<1>(0h0)) node _T_961 = leq(UInt<1>(0h0), uncommonBits_17) node _T_962 = and(_T_960, _T_961) node _T_963 = leq(uncommonBits_17, UInt<4>(0hf)) node _T_964 = and(_T_962, _T_963) node _T_965 = or(_T_958, _T_964) node _T_966 = and(_T_952, _T_965) node _T_967 = or(UInt<1>(0h0), _T_966) node _T_968 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_969 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_970 = and(_T_968, _T_969) node _T_971 = or(UInt<1>(0h0), _T_970) node _T_972 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_973 = cvt(_T_972) node _T_974 = and(_T_973, asSInt(UInt<13>(0h1000))) node _T_975 = asSInt(_T_974) node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0))) node _T_977 = and(_T_971, _T_976) node _T_978 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_979 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_980 = cvt(_T_979) node _T_981 = and(_T_980, asSInt(UInt<14>(0h2000))) node _T_982 = asSInt(_T_981) node _T_983 = eq(_T_982, asSInt(UInt<1>(0h0))) node _T_984 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_985 = cvt(_T_984) node _T_986 = and(_T_985, asSInt(UInt<17>(0h10000))) node _T_987 = asSInt(_T_986) node _T_988 = eq(_T_987, asSInt(UInt<1>(0h0))) node _T_989 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_990 = cvt(_T_989) node _T_991 = and(_T_990, asSInt(UInt<18>(0h2f000))) node _T_992 = asSInt(_T_991) node _T_993 = eq(_T_992, asSInt(UInt<1>(0h0))) node _T_994 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_995 = cvt(_T_994) node _T_996 = and(_T_995, asSInt(UInt<17>(0h10000))) node _T_997 = asSInt(_T_996) node _T_998 = eq(_T_997, asSInt(UInt<1>(0h0))) node _T_999 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_1000 = cvt(_T_999) node _T_1001 = and(_T_1000, asSInt(UInt<13>(0h1000))) node _T_1002 = asSInt(_T_1001) node _T_1003 = eq(_T_1002, asSInt(UInt<1>(0h0))) node _T_1004 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_1005 = cvt(_T_1004) node _T_1006 = and(_T_1005, asSInt(UInt<27>(0h4000000))) node _T_1007 = asSInt(_T_1006) node _T_1008 = eq(_T_1007, asSInt(UInt<1>(0h0))) node _T_1009 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1010 = cvt(_T_1009) node _T_1011 = and(_T_1010, asSInt(UInt<13>(0h1000))) node _T_1012 = asSInt(_T_1011) node _T_1013 = eq(_T_1012, asSInt(UInt<1>(0h0))) node _T_1014 = or(_T_983, _T_988) node _T_1015 = or(_T_1014, _T_993) node _T_1016 = or(_T_1015, _T_998) node _T_1017 = or(_T_1016, _T_1003) node _T_1018 = or(_T_1017, _T_1008) node _T_1019 = or(_T_1018, _T_1013) node _T_1020 = and(_T_978, _T_1019) node _T_1021 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1022 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1023 = and(_T_1021, _T_1022) node _T_1024 = or(UInt<1>(0h0), _T_1023) node _T_1025 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1026 = cvt(_T_1025) node _T_1027 = and(_T_1026, asSInt(UInt<17>(0h10000))) node _T_1028 = asSInt(_T_1027) node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0))) node _T_1030 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1031 = cvt(_T_1030) node _T_1032 = and(_T_1031, asSInt(UInt<29>(0h10000000))) node _T_1033 = asSInt(_T_1032) node _T_1034 = eq(_T_1033, asSInt(UInt<1>(0h0))) node _T_1035 = or(_T_1029, _T_1034) node _T_1036 = and(_T_1024, _T_1035) node _T_1037 = or(UInt<1>(0h0), _T_977) node _T_1038 = or(_T_1037, _T_1020) node _T_1039 = or(_T_1038, _T_1036) node _T_1040 = and(_T_967, _T_1039) node _T_1041 = asUInt(reset) node _T_1042 = eq(_T_1041, UInt<1>(0h0)) when _T_1042 : node _T_1043 = eq(_T_1040, UInt<1>(0h0)) when _T_1043 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1040, UInt<1>(0h1), "") : assert_46 node _T_1044 = asUInt(reset) node _T_1045 = eq(_T_1044, UInt<1>(0h0)) when _T_1045 : node _T_1046 = eq(source_ok, UInt<1>(0h0)) when _T_1046 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_1047 = asUInt(reset) node _T_1048 = eq(_T_1047, UInt<1>(0h0)) when _T_1048 : node _T_1049 = eq(is_aligned, UInt<1>(0h0)) when _T_1049 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1050 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1051 = asUInt(reset) node _T_1052 = eq(_T_1051, UInt<1>(0h0)) when _T_1052 : node _T_1053 = eq(_T_1050, UInt<1>(0h0)) when _T_1053 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1050, UInt<1>(0h1), "") : assert_49 node _T_1054 = eq(io.in.a.bits.mask, mask) node _T_1055 = asUInt(reset) node _T_1056 = eq(_T_1055, UInt<1>(0h0)) when _T_1056 : node _T_1057 = eq(_T_1054, UInt<1>(0h0)) when _T_1057 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1054, UInt<1>(0h1), "") : assert_50 node _T_1058 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1059 = asUInt(reset) node _T_1060 = eq(_T_1059, UInt<1>(0h0)) when _T_1060 : node _T_1061 = eq(_T_1058, UInt<1>(0h0)) when _T_1061 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1058, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1062 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1063 = asUInt(reset) node _T_1064 = eq(_T_1063, UInt<1>(0h0)) when _T_1064 : node _T_1065 = eq(_T_1062, UInt<1>(0h0)) when _T_1065 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1062, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_2 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_12 = shr(io.in.d.bits.source, 4) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h1)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<4>(0hf)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) node _source_ok_uncommonBits_T_3 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 3, 0) node _source_ok_T_18 = shr(io.in.d.bits.source, 4) node _source_ok_T_19 = eq(_source_ok_T_18, UInt<1>(0h0)) node _source_ok_T_20 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_21 = and(_source_ok_T_19, _source_ok_T_20) node _source_ok_T_22 = leq(source_ok_uncommonBits_3, UInt<4>(0hf)) node _source_ok_T_23 = and(_source_ok_T_21, _source_ok_T_22) wire _source_ok_WIRE_1 : UInt<1>[2] connect _source_ok_WIRE_1[0], _source_ok_T_17 connect _source_ok_WIRE_1[1], _source_ok_T_23 node source_ok_1 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node sink_ok = lt(io.in.d.bits.sink, UInt<5>(0h10)) node _T_1066 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1066 : node _T_1067 = asUInt(reset) node _T_1068 = eq(_T_1067, UInt<1>(0h0)) when _T_1068 : node _T_1069 = eq(source_ok_1, UInt<1>(0h0)) when _T_1069 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_1070 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1071 = asUInt(reset) node _T_1072 = eq(_T_1071, UInt<1>(0h0)) when _T_1072 : node _T_1073 = eq(_T_1070, UInt<1>(0h0)) when _T_1073 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1070, UInt<1>(0h1), "") : assert_54 node _T_1074 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1075 = asUInt(reset) node _T_1076 = eq(_T_1075, UInt<1>(0h0)) when _T_1076 : node _T_1077 = eq(_T_1074, UInt<1>(0h0)) when _T_1077 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1074, UInt<1>(0h1), "") : assert_55 node _T_1078 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1079 = asUInt(reset) node _T_1080 = eq(_T_1079, UInt<1>(0h0)) when _T_1080 : node _T_1081 = eq(_T_1078, UInt<1>(0h0)) when _T_1081 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1078, UInt<1>(0h1), "") : assert_56 node _T_1082 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1083 = asUInt(reset) node _T_1084 = eq(_T_1083, UInt<1>(0h0)) when _T_1084 : node _T_1085 = eq(_T_1082, UInt<1>(0h0)) when _T_1085 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1082, UInt<1>(0h1), "") : assert_57 node _T_1086 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1086 : node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(source_ok_1, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(sink_ok, UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1093 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(_T_1093, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1093, UInt<1>(0h1), "") : assert_60 node _T_1097 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1098 = asUInt(reset) node _T_1099 = eq(_T_1098, UInt<1>(0h0)) when _T_1099 : node _T_1100 = eq(_T_1097, UInt<1>(0h0)) when _T_1100 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1097, UInt<1>(0h1), "") : assert_61 node _T_1101 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1102 = asUInt(reset) node _T_1103 = eq(_T_1102, UInt<1>(0h0)) when _T_1103 : node _T_1104 = eq(_T_1101, UInt<1>(0h0)) when _T_1104 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1101, UInt<1>(0h1), "") : assert_62 node _T_1105 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_63 node _T_1109 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1110 = or(UInt<1>(0h1), _T_1109) node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(_T_1110, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1110, UInt<1>(0h1), "") : assert_64 node _T_1114 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1114 : node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(source_ok_1, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_1118 = asUInt(reset) node _T_1119 = eq(_T_1118, UInt<1>(0h0)) when _T_1119 : node _T_1120 = eq(sink_ok, UInt<1>(0h0)) when _T_1120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1121 = geq(io.in.d.bits.size, UInt<3>(0h4)) node _T_1122 = asUInt(reset) node _T_1123 = eq(_T_1122, UInt<1>(0h0)) when _T_1123 : node _T_1124 = eq(_T_1121, UInt<1>(0h0)) when _T_1124 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1121, UInt<1>(0h1), "") : assert_67 node _T_1125 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_T_1125, UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1125, UInt<1>(0h1), "") : assert_68 node _T_1129 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_69 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(_T_1133, io.in.d.bits.corrupt) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_70 node _T_1138 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1139 = or(UInt<1>(0h1), _T_1138) node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_T_1139, UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1139, UInt<1>(0h1), "") : assert_71 node _T_1143 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1143 : node _T_1144 = asUInt(reset) node _T_1145 = eq(_T_1144, UInt<1>(0h0)) when _T_1145 : node _T_1146 = eq(source_ok_1, UInt<1>(0h0)) when _T_1146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_1147 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1148 = asUInt(reset) node _T_1149 = eq(_T_1148, UInt<1>(0h0)) when _T_1149 : node _T_1150 = eq(_T_1147, UInt<1>(0h0)) when _T_1150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1147, UInt<1>(0h1), "") : assert_73 node _T_1151 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_74 node _T_1155 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1156 = or(UInt<1>(0h1), _T_1155) node _T_1157 = asUInt(reset) node _T_1158 = eq(_T_1157, UInt<1>(0h0)) when _T_1158 : node _T_1159 = eq(_T_1156, UInt<1>(0h0)) when _T_1159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1156, UInt<1>(0h1), "") : assert_75 node _T_1160 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1160 : node _T_1161 = asUInt(reset) node _T_1162 = eq(_T_1161, UInt<1>(0h0)) when _T_1162 : node _T_1163 = eq(source_ok_1, UInt<1>(0h0)) when _T_1163 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1164 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_77 node _T_1168 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1169 = or(_T_1168, io.in.d.bits.corrupt) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_78 node _T_1173 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1174 = or(UInt<1>(0h1), _T_1173) node _T_1175 = asUInt(reset) node _T_1176 = eq(_T_1175, UInt<1>(0h0)) when _T_1176 : node _T_1177 = eq(_T_1174, UInt<1>(0h0)) when _T_1177 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1174, UInt<1>(0h1), "") : assert_79 node _T_1178 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1178 : node _T_1179 = asUInt(reset) node _T_1180 = eq(_T_1179, UInt<1>(0h0)) when _T_1180 : node _T_1181 = eq(source_ok_1, UInt<1>(0h0)) when _T_1181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1182 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1183 = asUInt(reset) node _T_1184 = eq(_T_1183, UInt<1>(0h0)) when _T_1184 : node _T_1185 = eq(_T_1182, UInt<1>(0h0)) when _T_1185 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1182, UInt<1>(0h1), "") : assert_81 node _T_1186 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_82 node _T_1190 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1191 = or(UInt<1>(0h1), _T_1190) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<128>(0h0) connect _WIRE.bits.mask, UInt<16>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<5>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<5>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1195 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<128>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<5>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1199 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_4.bits.sink, UInt<4>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1203 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 4) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1207 = eq(a_first, UInt<1>(0h0)) node _T_1208 = and(io.in.a.valid, _T_1207) when _T_1208 : node _T_1209 = eq(io.in.a.bits.opcode, opcode) node _T_1210 = asUInt(reset) node _T_1211 = eq(_T_1210, UInt<1>(0h0)) when _T_1211 : node _T_1212 = eq(_T_1209, UInt<1>(0h0)) when _T_1212 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1209, UInt<1>(0h1), "") : assert_87 node _T_1213 = eq(io.in.a.bits.param, param) node _T_1214 = asUInt(reset) node _T_1215 = eq(_T_1214, UInt<1>(0h0)) when _T_1215 : node _T_1216 = eq(_T_1213, UInt<1>(0h0)) when _T_1216 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1213, UInt<1>(0h1), "") : assert_88 node _T_1217 = eq(io.in.a.bits.size, size) node _T_1218 = asUInt(reset) node _T_1219 = eq(_T_1218, UInt<1>(0h0)) when _T_1219 : node _T_1220 = eq(_T_1217, UInt<1>(0h0)) when _T_1220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1217, UInt<1>(0h1), "") : assert_89 node _T_1221 = eq(io.in.a.bits.source, source) node _T_1222 = asUInt(reset) node _T_1223 = eq(_T_1222, UInt<1>(0h0)) when _T_1223 : node _T_1224 = eq(_T_1221, UInt<1>(0h0)) when _T_1224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1221, UInt<1>(0h1), "") : assert_90 node _T_1225 = eq(io.in.a.bits.address, address) node _T_1226 = asUInt(reset) node _T_1227 = eq(_T_1226, UInt<1>(0h0)) when _T_1227 : node _T_1228 = eq(_T_1225, UInt<1>(0h0)) when _T_1228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1225, UInt<1>(0h1), "") : assert_91 node _T_1229 = and(io.in.a.ready, io.in.a.valid) node _T_1230 = and(_T_1229, a_first) when _T_1230 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 4) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1231 = eq(d_first, UInt<1>(0h0)) node _T_1232 = and(io.in.d.valid, _T_1231) when _T_1232 : node _T_1233 = eq(io.in.d.bits.opcode, opcode_1) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_92 node _T_1237 = eq(io.in.d.bits.param, param_1) node _T_1238 = asUInt(reset) node _T_1239 = eq(_T_1238, UInt<1>(0h0)) when _T_1239 : node _T_1240 = eq(_T_1237, UInt<1>(0h0)) when _T_1240 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1237, UInt<1>(0h1), "") : assert_93 node _T_1241 = eq(io.in.d.bits.size, size_1) node _T_1242 = asUInt(reset) node _T_1243 = eq(_T_1242, UInt<1>(0h0)) when _T_1243 : node _T_1244 = eq(_T_1241, UInt<1>(0h0)) when _T_1244 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1241, UInt<1>(0h1), "") : assert_94 node _T_1245 = eq(io.in.d.bits.source, source_1) node _T_1246 = asUInt(reset) node _T_1247 = eq(_T_1246, UInt<1>(0h0)) when _T_1247 : node _T_1248 = eq(_T_1245, UInt<1>(0h0)) when _T_1248 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1245, UInt<1>(0h1), "") : assert_95 node _T_1249 = eq(io.in.d.bits.sink, sink) node _T_1250 = asUInt(reset) node _T_1251 = eq(_T_1250, UInt<1>(0h0)) when _T_1251 : node _T_1252 = eq(_T_1249, UInt<1>(0h0)) when _T_1252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1249, UInt<1>(0h1), "") : assert_96 node _T_1253 = eq(io.in.d.bits.denied, denied) node _T_1254 = asUInt(reset) node _T_1255 = eq(_T_1254, UInt<1>(0h0)) when _T_1255 : node _T_1256 = eq(_T_1253, UInt<1>(0h0)) when _T_1256 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1253, UInt<1>(0h1), "") : assert_97 node _T_1257 = and(io.in.d.ready, io.in.d.valid) node _T_1258 = and(_T_1257, d_first) when _T_1258 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes : UInt<256>, clock, reset, UInt<256>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 4) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 4) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<32> connect a_set, UInt<32>(0h0) wire a_set_wo_ready : UInt<32> connect a_set_wo_ready, UInt<32>(0h0) wire a_opcodes_set : UInt<128> connect a_opcodes_set, UInt<128>(0h0) wire a_sizes_set : UInt<256> connect a_sizes_set, UInt<256>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1259 = and(io.in.a.valid, a_first_1) node _T_1260 = and(_T_1259, UInt<1>(0h1)) when _T_1260 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1261 = and(io.in.a.ready, io.in.a.valid) node _T_1262 = and(_T_1261, a_first_1) node _T_1263 = and(_T_1262, UInt<1>(0h1)) when _T_1263 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1264 = dshr(inflight, io.in.a.bits.source) node _T_1265 = bits(_T_1264, 0, 0) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) node _T_1267 = asUInt(reset) node _T_1268 = eq(_T_1267, UInt<1>(0h0)) when _T_1268 : node _T_1269 = eq(_T_1266, UInt<1>(0h0)) when _T_1269 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1266, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<32> connect d_clr, UInt<32>(0h0) wire d_clr_wo_ready : UInt<32> connect d_clr_wo_ready, UInt<32>(0h0) wire d_opcodes_clr : UInt<128> connect d_opcodes_clr, UInt<128>(0h0) wire d_sizes_clr : UInt<256> connect d_sizes_clr, UInt<256>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1270 = and(io.in.d.valid, d_first_1) node _T_1271 = and(_T_1270, UInt<1>(0h1)) node _T_1272 = eq(d_release_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1274 = and(io.in.d.ready, io.in.d.valid) node _T_1275 = and(_T_1274, d_first_1) node _T_1276 = and(_T_1275, UInt<1>(0h1)) node _T_1277 = eq(d_release_ack, UInt<1>(0h0)) node _T_1278 = and(_T_1276, _T_1277) when _T_1278 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1279 = and(io.in.d.valid, d_first_1) node _T_1280 = and(_T_1279, UInt<1>(0h1)) node _T_1281 = eq(d_release_ack, UInt<1>(0h0)) node _T_1282 = and(_T_1280, _T_1281) when _T_1282 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1283 = dshr(inflight, io.in.d.bits.source) node _T_1284 = bits(_T_1283, 0, 0) node _T_1285 = or(_T_1284, same_cycle_resp) node _T_1286 = asUInt(reset) node _T_1287 = eq(_T_1286, UInt<1>(0h0)) when _T_1287 : node _T_1288 = eq(_T_1285, UInt<1>(0h0)) when _T_1288 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1285, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1289 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1290 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1291 = or(_T_1289, _T_1290) node _T_1292 = asUInt(reset) node _T_1293 = eq(_T_1292, UInt<1>(0h0)) when _T_1293 : node _T_1294 = eq(_T_1291, UInt<1>(0h0)) when _T_1294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1291, UInt<1>(0h1), "") : assert_100 node _T_1295 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1296 = asUInt(reset) node _T_1297 = eq(_T_1296, UInt<1>(0h0)) when _T_1297 : node _T_1298 = eq(_T_1295, UInt<1>(0h0)) when _T_1298 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1295, UInt<1>(0h1), "") : assert_101 else : node _T_1299 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1300 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1301 = or(_T_1299, _T_1300) node _T_1302 = asUInt(reset) node _T_1303 = eq(_T_1302, UInt<1>(0h0)) when _T_1303 : node _T_1304 = eq(_T_1301, UInt<1>(0h0)) when _T_1304 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1301, UInt<1>(0h1), "") : assert_102 node _T_1305 = eq(io.in.d.bits.size, a_size_lookup) node _T_1306 = asUInt(reset) node _T_1307 = eq(_T_1306, UInt<1>(0h0)) when _T_1307 : node _T_1308 = eq(_T_1305, UInt<1>(0h0)) when _T_1308 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1305, UInt<1>(0h1), "") : assert_103 node _T_1309 = and(io.in.d.valid, d_first_1) node _T_1310 = and(_T_1309, a_first_1) node _T_1311 = and(_T_1310, io.in.a.valid) node _T_1312 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1313 = and(_T_1311, _T_1312) node _T_1314 = eq(d_release_ack, UInt<1>(0h0)) node _T_1315 = and(_T_1313, _T_1314) when _T_1315 : node _T_1316 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1317 = or(_T_1316, io.in.a.ready) node _T_1318 = asUInt(reset) node _T_1319 = eq(_T_1318, UInt<1>(0h0)) when _T_1319 : node _T_1320 = eq(_T_1317, UInt<1>(0h0)) when _T_1320 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1317, UInt<1>(0h1), "") : assert_104 node _T_1321 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1322 = orr(a_set_wo_ready) node _T_1323 = eq(_T_1322, UInt<1>(0h0)) node _T_1324 = or(_T_1321, _T_1323) node _T_1325 = asUInt(reset) node _T_1326 = eq(_T_1325, UInt<1>(0h0)) when _T_1326 : node _T_1327 = eq(_T_1324, UInt<1>(0h0)) when _T_1327 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1324, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_82 node _T_1328 = orr(inflight) node _T_1329 = eq(_T_1328, UInt<1>(0h0)) node _T_1330 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1331 = or(_T_1329, _T_1330) node _T_1332 = lt(watchdog, plusarg_reader.out) node _T_1333 = or(_T_1331, _T_1332) node _T_1334 = asUInt(reset) node _T_1335 = eq(_T_1334, UInt<1>(0h0)) when _T_1335 : node _T_1336 = eq(_T_1333, UInt<1>(0h0)) when _T_1336 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1333, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1337 = and(io.in.a.ready, io.in.a.valid) node _T_1338 = and(io.in.d.ready, io.in.d.valid) node _T_1339 = or(_T_1337, _T_1338) when _T_1339 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<32>, clock, reset, UInt<32>(0h0) regreset inflight_opcodes_1 : UInt<128>, clock, reset, UInt<128>(0h0) regreset inflight_sizes_1 : UInt<256>, clock, reset, UInt<256>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<128>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<5>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<128>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<5>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 4) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<8>, clock, reset, UInt<8>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 4) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<32> connect c_set, UInt<32>(0h0) wire c_set_wo_ready : UInt<32> connect c_set_wo_ready, UInt<32>(0h0) wire c_opcodes_set : UInt<128> connect c_opcodes_set, UInt<128>(0h0) wire c_sizes_set : UInt<256> connect c_sizes_set, UInt<256>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<128>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<5>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1340 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<128>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<5>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1341 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1342 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1343 = and(_T_1341, _T_1342) node _T_1344 = and(_T_1340, _T_1343) when _T_1344 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<128>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<5>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<128>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<5>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1345 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1346 = and(_T_1345, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<128>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<5>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1347 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1348 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1349 = and(_T_1347, _T_1348) node _T_1350 = and(_T_1346, _T_1349) when _T_1350 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<128>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<5>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<128>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<5>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<128>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<5>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1351 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1352 = bits(_T_1351, 0, 0) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) node _T_1354 = asUInt(reset) node _T_1355 = eq(_T_1354, UInt<1>(0h0)) when _T_1355 : node _T_1356 = eq(_T_1353, UInt<1>(0h0)) when _T_1356 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1353, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<128>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<5>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<32> connect d_clr_1, UInt<32>(0h0) wire d_clr_wo_ready_1 : UInt<32> connect d_clr_wo_ready_1, UInt<32>(0h0) wire d_opcodes_clr_1 : UInt<128> connect d_opcodes_clr_1, UInt<128>(0h0) wire d_sizes_clr_1 : UInt<256> connect d_sizes_clr_1, UInt<256>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1357 = and(io.in.d.valid, d_first_2) node _T_1358 = and(_T_1357, UInt<1>(0h1)) node _T_1359 = and(_T_1358, d_release_ack_1) when _T_1359 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1360 = and(io.in.d.ready, io.in.d.valid) node _T_1361 = and(_T_1360, d_first_2) node _T_1362 = and(_T_1361, UInt<1>(0h1)) node _T_1363 = and(_T_1362, d_release_ack_1) when _T_1363 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1364 = and(io.in.d.valid, d_first_2) node _T_1365 = and(_T_1364, UInt<1>(0h1)) node _T_1366 = and(_T_1365, d_release_ack_1) when _T_1366 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<128>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<5>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1367 = dshr(inflight_1, io.in.d.bits.source) node _T_1368 = bits(_T_1367, 0, 0) node _T_1369 = or(_T_1368, same_cycle_resp_1) node _T_1370 = asUInt(reset) node _T_1371 = eq(_T_1370, UInt<1>(0h0)) when _T_1371 : node _T_1372 = eq(_T_1369, UInt<1>(0h0)) when _T_1372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1369, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<128>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<5>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1373 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1374 = asUInt(reset) node _T_1375 = eq(_T_1374, UInt<1>(0h0)) when _T_1375 : node _T_1376 = eq(_T_1373, UInt<1>(0h0)) when _T_1376 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1373, UInt<1>(0h1), "") : assert_109 else : node _T_1377 = eq(io.in.d.bits.size, c_size_lookup) node _T_1378 = asUInt(reset) node _T_1379 = eq(_T_1378, UInt<1>(0h0)) when _T_1379 : node _T_1380 = eq(_T_1377, UInt<1>(0h0)) when _T_1380 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1377, UInt<1>(0h1), "") : assert_110 node _T_1381 = and(io.in.d.valid, d_first_2) node _T_1382 = and(_T_1381, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<128>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<5>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1383 = and(_T_1382, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<128>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<5>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1384 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1385 = and(_T_1383, _T_1384) node _T_1386 = and(_T_1385, d_release_ack_1) node _T_1387 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1388 = and(_T_1386, _T_1387) when _T_1388 : node _T_1389 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<128>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<5>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1390 = or(_T_1389, _WIRE_23.ready) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_111 node _T_1394 = orr(c_set_wo_ready) when _T_1394 : node _T_1395 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1396 = asUInt(reset) node _T_1397 = eq(_T_1396, UInt<1>(0h0)) when _T_1397 : node _T_1398 = eq(_T_1395, UInt<1>(0h0)) when _T_1398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1395, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_83 node _T_1399 = orr(inflight_1) node _T_1400 = eq(_T_1399, UInt<1>(0h0)) node _T_1401 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1402 = or(_T_1400, _T_1401) node _T_1403 = lt(watchdog_1, plusarg_reader_1.out) node _T_1404 = or(_T_1402, _T_1403) node _T_1405 = asUInt(reset) node _T_1406 = eq(_T_1405, UInt<1>(0h0)) when _T_1406 : node _T_1407 = eq(_T_1404, UInt<1>(0h0)) when _T_1407 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/tile/LazyRoCC.scala:89:59)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1404, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<128>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<5>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<5>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1408 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1409 = and(io.in.d.ready, io.in.d.valid) node _T_1410 = or(_T_1408, _T_1409) when _T_1410 : connect watchdog_1, UInt<1>(0h0) extmodule plusarg_reader_84 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_85 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TLMonitor_41( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [15:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [127:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [4:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [127:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [4:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [127:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [7:0] c_first_beats1_decode = 8'h0; // @[Edges.scala:220:59] wire [7:0] c_first_beats1 = 8'h0; // @[Edges.scala:221:14] wire [7:0] _c_first_count_T = 8'h0; // @[Edges.scala:234:27] wire [7:0] c_first_count = 8'h0; // @[Edges.scala:234:25] wire [7:0] _c_first_counter_T = 8'h0; // @[Edges.scala:236:21] wire [7:0] _c_opcodes_set_T = 8'h0; // @[Monitor.scala:767:79] wire [7:0] _c_sizes_set_T = 8'h0; // @[Monitor.scala:768:77] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_10 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_16 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_20 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_22 = 1'h1; // @[Parameters.scala:57:20] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [7:0] c_first_counter1 = 8'hFF; // @[Edges.scala:230:28] wire [8:0] _c_first_counter1_T = 9'h1FF; // @[Edges.scala:230:28] wire [127:0] _c_first_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_first_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_first_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] c_opcodes_set = 128'h0; // @[Monitor.scala:740:34] wire [127:0] _c_set_wo_ready_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_wo_ready_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_interm_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_interm_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_opcodes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_opcodes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_sizes_set_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_sizes_set_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _c_probe_ack_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _c_probe_ack_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_1_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_2_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_3_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [127:0] _same_cycle_resp_WIRE_4_bits_data = 128'h0; // @[Bundles.scala:265:74] wire [127:0] _same_cycle_resp_WIRE_5_bits_data = 128'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] c_set = 32'h0; // @[Monitor.scala:738:34] wire [31:0] c_set_wo_ready = 32'h0; // @[Monitor.scala:739:34] wire [31:0] _c_set_wo_ready_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_address = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_address = 32'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_first_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_first_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] c_sizes_set_interm = 5'h0; // @[Monitor.scala:755:40] wire [4:0] _c_set_wo_ready_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_wo_ready_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_opcodes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_interm_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_interm_T = 5'h0; // @[Monitor.scala:766:51] wire [4:0] _c_opcodes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_opcodes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_sizes_set_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_sizes_set_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _c_probe_ack_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _c_probe_ack_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_1_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_2_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_3_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [4:0] _same_cycle_resp_WIRE_4_bits_source = 5'h0; // @[Bundles.scala:265:74] wire [4:0] _same_cycle_resp_WIRE_5_bits_source = 5'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_first_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_first_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_set_wo_ready_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_wo_ready_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_interm_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_opcodes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_opcodes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_sizes_set_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_sizes_set_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _c_probe_ack_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _c_probe_ack_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_1_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_2_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_3_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [3:0] _same_cycle_resp_WIRE_4_bits_size = 4'h0; // @[Bundles.scala:265:74] wire [3:0] _same_cycle_resp_WIRE_5_bits_size = 4'h0; // @[Bundles.scala:265:61] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [15:0] _a_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hFF; // @[Monitor.scala:612:57] wire [15:0] _c_size_lookup_T_5 = 16'hFF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hFF; // @[Monitor.scala:724:57] wire [16:0] _a_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hFF; // @[Monitor.scala:612:57] wire [16:0] _c_size_lookup_T_4 = 17'hFF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hFF; // @[Monitor.scala:724:57] wire [15:0] _a_size_lookup_T_3 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h100; // @[Monitor.scala:612:51] wire [15:0] _c_size_lookup_T_3 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h100; // @[Monitor.scala:724:51] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [259:0] _c_sizes_set_T_1 = 260'h0; // @[Monitor.scala:768:52] wire [258:0] _c_opcodes_set_T_1 = 259'h0; // @[Monitor.scala:767:54] wire [4:0] _c_sizes_set_interm_T_1 = 5'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [31:0] _c_set_wo_ready_T = 32'h1; // @[OneHot.scala:58:35] wire [31:0] _c_set_T = 32'h1; // @[OneHot.scala:58:35] wire [255:0] c_sizes_set = 256'h0; // @[Monitor.scala:741:34] wire [11:0] _c_first_beats1_decode_T_2 = 12'h0; // @[package.scala:243:46] wire [11:0] _c_first_beats1_decode_T_1 = 12'hFFF; // @[package.scala:243:76] wire [26:0] _c_first_beats1_decode_T = 27'hFFF; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_size_lookup_T_2 = 4'h8; // @[Monitor.scala:641:117] wire [3:0] _d_sizes_clr_T = 4'h8; // @[Monitor.scala:681:48] wire [3:0] _c_size_lookup_T_2 = 4'h8; // @[Monitor.scala:750:119] wire [3:0] _d_sizes_clr_T_6 = 4'h8; // @[Monitor.scala:791:48] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [4:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_2 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [4:0] _source_ok_uncommonBits_T_3 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_6 = io_in_a_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_1 = _source_ok_T; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_3 = _source_ok_T_1; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_5 = _source_ok_T_3; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_7 = ~_source_ok_T_6; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_9 = _source_ok_T_7; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_11 = _source_ok_T_9; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire source_ok = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire [26:0] _GEN = 27'hFFF << io_in_a_bits_size_0; // @[package.scala:243:71] wire [26:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [26:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [11:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {20'h0, io_in_a_bits_address_0[11:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [3:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1; // @[OneHot.scala:65:{12,27}] wire [3:0] mask_sizeOH = {_mask_sizeOH_T_2[3:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_sub_0_1 = |(io_in_a_bits_size_0[3:2]); // @[Misc.scala:206:21] wire mask_sub_sub_sub_size = mask_sizeOH[3]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_sub_bit = io_in_a_bits_address_0[3]; // @[Misc.scala:210:26] wire mask_sub_sub_sub_1_2 = mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_sub_nbit = ~mask_sub_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_sub_0_2 = mask_sub_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_sub_acc_T = mask_sub_sub_sub_size & mask_sub_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_0_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_sub_acc_T_1 = mask_sub_sub_sub_size & mask_sub_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_sub_1_1 = mask_sub_sub_sub_sub_0_1 | _mask_sub_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_1_2 = mask_sub_sub_sub_0_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_2_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T_2 = mask_sub_sub_size & mask_sub_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_2_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_sub_3_2 = mask_sub_sub_sub_1_2 & mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_sub_acc_T_3 = mask_sub_sub_size & mask_sub_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_3_1 = mask_sub_sub_sub_1_1 | _mask_sub_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_sub_4_2 = mask_sub_sub_2_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_4 = mask_sub_size & mask_sub_4_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_4_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_sub_5_2 = mask_sub_sub_2_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_5 = mask_sub_size & mask_sub_5_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_5_1 = mask_sub_sub_2_1 | _mask_sub_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_sub_6_2 = mask_sub_sub_3_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_6 = mask_sub_size & mask_sub_6_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_6_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_sub_7_2 = mask_sub_sub_3_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_7 = mask_sub_size & mask_sub_7_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_7_1 = mask_sub_sub_3_1 | _mask_sub_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire mask_eq_8 = mask_sub_4_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_8 = mask_size & mask_eq_8; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_8 = mask_sub_4_1 | _mask_acc_T_8; // @[Misc.scala:215:{29,38}] wire mask_eq_9 = mask_sub_4_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_9 = mask_size & mask_eq_9; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_9 = mask_sub_4_1 | _mask_acc_T_9; // @[Misc.scala:215:{29,38}] wire mask_eq_10 = mask_sub_5_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_10 = mask_size & mask_eq_10; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_10 = mask_sub_5_1 | _mask_acc_T_10; // @[Misc.scala:215:{29,38}] wire mask_eq_11 = mask_sub_5_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_11 = mask_size & mask_eq_11; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_11 = mask_sub_5_1 | _mask_acc_T_11; // @[Misc.scala:215:{29,38}] wire mask_eq_12 = mask_sub_6_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_12 = mask_size & mask_eq_12; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_12 = mask_sub_6_1 | _mask_acc_T_12; // @[Misc.scala:215:{29,38}] wire mask_eq_13 = mask_sub_6_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_13 = mask_size & mask_eq_13; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_13 = mask_sub_6_1 | _mask_acc_T_13; // @[Misc.scala:215:{29,38}] wire mask_eq_14 = mask_sub_7_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_14 = mask_size & mask_eq_14; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_14 = mask_sub_7_1 | _mask_acc_T_14; // @[Misc.scala:215:{29,38}] wire mask_eq_15 = mask_sub_7_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_15 = mask_size & mask_eq_15; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_15 = mask_sub_7_1 | _mask_acc_T_15; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_lo = {mask_lo_lo_hi, mask_lo_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_lo_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo_hi = {mask_lo_hi_hi, mask_lo_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_lo = {mask_acc_9, mask_acc_8}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_lo_hi = {mask_acc_11, mask_acc_10}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_lo = {mask_hi_lo_hi, mask_hi_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_lo = {mask_acc_13, mask_acc_12}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi_hi = {mask_acc_15, mask_acc_14}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi_hi = {mask_hi_hi_hi, mask_hi_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [15:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_9 = _uncommonBits_T_9[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_10 = _uncommonBits_T_10[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_12 = _uncommonBits_T_12[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_13 = _uncommonBits_T_13[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_14 = _uncommonBits_T_14[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_15 = _uncommonBits_T_15[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_16 = _uncommonBits_T_16[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_17 = _uncommonBits_T_17[3:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_12 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_18 = io_in_d_bits_source_0[4]; // @[Monitor.scala:36:7] wire _source_ok_T_13 = _source_ok_T_12; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_15 = _source_ok_T_13; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_17 = _source_ok_T_15; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_0 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[3:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_19 = ~_source_ok_T_18; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_21 = _source_ok_T_19; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_23 = _source_ok_T_21; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_23; // @[Parameters.scala:1138:31] wire source_ok_1 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _T_1337 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1337; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1337; // @[Decoupled.scala:51:35] wire [11:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T = {1'h0, a_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1 = _a_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [4:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1410 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1410; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1410; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1410; // @[Decoupled.scala:51:35] wire [26:0] _GEN_0 = 27'hFFF << io_in_d_bits_size_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [26:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [11:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[11:4]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [7:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T = {1'h0, d_first_counter} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1 = _d_first_counter1_T[7:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg [4:0] source_1; // @[Monitor.scala:541:22] reg [3:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [31:0] inflight; // @[Monitor.scala:614:27] reg [127:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [255:0] inflight_sizes; // @[Monitor.scala:618:33] wire [11:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [7:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 8'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [7:0] a_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] a_first_counter1_1 = _a_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [11:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_1; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_1 = _d_first_counter1_T_1[7:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [31:0] a_set; // @[Monitor.scala:626:34] wire [31:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [127:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [255:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [7:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [7:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [7:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [7:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [7:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [127:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [127:0] _a_opcode_lookup_T_6 = {124'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [127:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [7:0] a_size_lookup; // @[Monitor.scala:639:33] wire [7:0] _GEN_2 = {io_in_d_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :641:65] wire [7:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65] wire [7:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_2; // @[Monitor.scala:641:65, :681:99] wire [7:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_2; // @[Monitor.scala:641:65, :750:67] wire [7:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_2; // @[Monitor.scala:641:65, :791:99] wire [255:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [255:0] _a_size_lookup_T_6 = {248'h0, _a_size_lookup_T_1[7:0]}; // @[Monitor.scala:641:{40,91}] wire [255:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[255:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[7:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [4:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [31:0] _GEN_3 = {27'h0, io_in_a_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_4 = 32'h1 << _GEN_3; // @[OneHot.scala:58:35] wire [31:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [31:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1263 = _T_1337 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1263 ? _a_set_T : 32'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1263 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [4:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [4:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[4:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1263 ? _a_sizes_set_interm_T_1 : 5'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [7:0] _a_opcodes_set_T = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [258:0] _a_opcodes_set_T_1 = {255'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1263 ? _a_opcodes_set_T_1[127:0] : 128'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [7:0] _a_sizes_set_T = {io_in_a_bits_source_0, 3'h0}; // @[Monitor.scala:36:7, :660:77] wire [259:0] _a_sizes_set_T_1 = {255'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1263 ? _a_sizes_set_T_1[255:0] : 256'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [31:0] d_clr; // @[Monitor.scala:664:34] wire [31:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [127:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [255:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_5 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_5; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_5; // @[Monitor.scala:673:46, :783:46] wire _T_1309 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [31:0] _GEN_6 = {27'h0, io_in_d_bits_source_0}; // @[OneHot.scala:58:35] wire [31:0] _GEN_7 = 32'h1 << _GEN_6; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [31:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1309 & ~d_release_ack ? _d_clr_wo_ready_T : 32'h0; // @[OneHot.scala:58:35] wire _T_1278 = _T_1410 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1278 ? _d_clr_T : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_5 = 271'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1278 ? _d_opcodes_clr_T_5[127:0] : 128'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [270:0] _d_sizes_clr_T_5 = 271'hFF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1278 ? _d_sizes_clr_T_5[255:0] : 256'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [31:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [31:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [31:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [127:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [127:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [127:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [255:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [255:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [255:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [31:0] inflight_1; // @[Monitor.scala:726:35] wire [31:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [127:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [127:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [255:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [255:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [11:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[11:0]; // @[package.scala:243:{71,76}] wire [11:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [7:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[11:4]; // @[package.scala:243:46] wire [7:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 8'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [7:0] d_first_counter_2; // @[Edges.scala:229:27] wire [8:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 9'h1; // @[Edges.scala:229:27, :230:28] wire [7:0] d_first_counter1_2 = _d_first_counter1_T_2[7:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 8'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 8'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 8'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [7:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [7:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [7:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [7:0] c_size_lookup; // @[Monitor.scala:748:35] wire [127:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [127:0] _c_opcode_lookup_T_6 = {124'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [127:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[127:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [255:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [255:0] _c_size_lookup_T_6 = {248'h0, _c_size_lookup_T_1[7:0]}; // @[Monitor.scala:750:{42,93}] wire [255:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[255:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[7:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [31:0] d_clr_1; // @[Monitor.scala:774:34] wire [31:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [127:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [255:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1381 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1381 & d_release_ack_1 ? _d_clr_wo_ready_T_1 : 32'h0; // @[OneHot.scala:58:35] wire _T_1363 = _T_1410 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1363 ? _d_clr_T_1 : 32'h0; // @[OneHot.scala:58:35] wire [270:0] _d_opcodes_clr_T_11 = 271'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1363 ? _d_opcodes_clr_T_11[127:0] : 128'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [270:0] _d_sizes_clr_T_11 = 271'hFF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1363 ? _d_sizes_clr_T_11[255:0] : 256'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 5'h0; // @[Monitor.scala:36:7, :795:113] wire [31:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [31:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [127:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [127:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [255:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [255:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module Tile_116 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_372 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_116( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [7:0] io_out_a_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0 // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire io_bad_dataflow = 1'h0; // @[Tile.scala:16:7, :17:14, :42:44] wire [7:0] io_out_a_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] PE_372 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0) ); // @[Tile.scala:42:44] assign io_out_a_0 = io_out_a_0_0; // @[Tile.scala:16:7] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_61 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_125 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_61( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_125 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCMsgArbiter_2 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}[5], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} regreset lockIdx : UInt<3>, clock, reset, UInt<3>(0h0) regreset locked : UInt<1>, clock, reset, UInt<1>(0h0) node _choice_T = mux(io.in[3].valid, UInt<2>(0h3), UInt<3>(0h4)) node _choice_T_1 = mux(io.in[2].valid, UInt<2>(0h2), _choice_T) node _choice_T_2 = mux(io.in[1].valid, UInt<1>(0h1), _choice_T_1) node choice = mux(io.in[0].valid, UInt<1>(0h0), _choice_T_2) node chosen = mux(locked, lockIdx, choice) node _io_in_0_ready_T = eq(chosen, UInt<1>(0h0)) node _io_in_0_ready_T_1 = and(io.out.ready, _io_in_0_ready_T) connect io.in[0].ready, _io_in_0_ready_T_1 node _io_in_1_ready_T = eq(chosen, UInt<1>(0h1)) node _io_in_1_ready_T_1 = and(io.out.ready, _io_in_1_ready_T) connect io.in[1].ready, _io_in_1_ready_T_1 node _io_in_2_ready_T = eq(chosen, UInt<2>(0h2)) node _io_in_2_ready_T_1 = and(io.out.ready, _io_in_2_ready_T) connect io.in[2].ready, _io_in_2_ready_T_1 node _io_in_3_ready_T = eq(chosen, UInt<2>(0h3)) node _io_in_3_ready_T_1 = and(io.out.ready, _io_in_3_ready_T) connect io.in[3].ready, _io_in_3_ready_T_1 node _io_in_4_ready_T = eq(chosen, UInt<3>(0h4)) node _io_in_4_ready_T_1 = and(io.out.ready, _io_in_4_ready_T) connect io.in[4].ready, _io_in_4_ready_T_1 connect io.out.valid, io.in[chosen].valid connect io.out.bits, io.in[chosen].bits node _T = and(io.out.ready, io.out.valid) when _T : node _T_1 = eq(locked, UInt<1>(0h0)) when _T_1 : connect lockIdx, choice connect locked, UInt<1>(0h1) regreset beat : UInt<2>, clock, reset, UInt<2>(0h0) regreset max_beat : UInt<2>, clock, reset, UInt<2>(0h0) node first = eq(beat, UInt<1>(0h0)) wire last : UInt<1> wire inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} wire _inst_WIRE : UInt<32> connect _inst_WIRE, io.out.bits.data node _inst_T = bits(_inst_WIRE, 6, 0) connect inst.opcode, _inst_T node _inst_T_1 = bits(_inst_WIRE, 11, 7) connect inst.rd, _inst_T_1 node _inst_T_2 = bits(_inst_WIRE, 12, 12) connect inst.xs2, _inst_T_2 node _inst_T_3 = bits(_inst_WIRE, 13, 13) connect inst.xs1, _inst_T_3 node _inst_T_4 = bits(_inst_WIRE, 14, 14) connect inst.xd, _inst_T_4 node _inst_T_5 = bits(_inst_WIRE, 19, 15) connect inst.rs1, _inst_T_5 node _inst_T_6 = bits(_inst_WIRE, 24, 20) connect inst.rs2, _inst_T_6 node _inst_T_7 = bits(_inst_WIRE, 31, 25) connect inst.funct, _inst_T_7 node _T_2 = and(io.out.ready, io.out.valid) node _T_3 = and(_T_2, first) when _T_3 : connect max_beat, UInt<1>(0h0) node _T_4 = eq(io.out.bits.opcode, UInt<3>(0h2)) when _T_4 : connect max_beat, UInt<1>(0h1) connect last, UInt<1>(0h1) node _T_5 = eq(io.out.bits.opcode, UInt<3>(0h2)) when _T_5 : node _last_T = eq(beat, max_beat) node _last_T_1 = eq(first, UInt<1>(0h0)) node _last_T_2 = and(_last_T, _last_T_1) connect last, _last_T_2 node _T_6 = and(io.out.ready, io.out.valid) when _T_6 : node _beat_T = add(beat, UInt<1>(0h1)) node _beat_T_1 = tail(_beat_T, 1) connect beat, _beat_T_1 node _T_7 = and(io.out.ready, io.out.valid) node _T_8 = and(_T_7, last) when _T_8 : connect max_beat, UInt<1>(0h0) connect beat, UInt<1>(0h0) when last : connect locked, UInt<1>(0h0)
module ReRoCCMsgArbiter_2( // @[Arbiter.scala:7:7] input clock, // @[Arbiter.scala:7:7] input reset, // @[Arbiter.scala:7:7] output io_in_0_ready, // @[Arbiters.scala:14:14] input io_in_0_valid, // @[Arbiters.scala:14:14] input [3:0] io_in_0_bits_client_id, // @[Arbiters.scala:14:14] input io_in_0_bits_manager_id, // @[Arbiters.scala:14:14] input [63:0] io_in_0_bits_data, // @[Arbiters.scala:14:14] output io_in_1_ready, // @[Arbiters.scala:14:14] input io_in_1_valid, // @[Arbiters.scala:14:14] input [3:0] io_in_1_bits_client_id, // @[Arbiters.scala:14:14] input io_in_1_bits_manager_id, // @[Arbiters.scala:14:14] output io_in_2_ready, // @[Arbiters.scala:14:14] input io_in_2_valid, // @[Arbiters.scala:14:14] input [3:0] io_in_2_bits_client_id, // @[Arbiters.scala:14:14] input io_in_2_bits_manager_id, // @[Arbiters.scala:14:14] input [63:0] io_in_2_bits_data, // @[Arbiters.scala:14:14] output io_in_3_ready, // @[Arbiters.scala:14:14] input io_in_3_valid, // @[Arbiters.scala:14:14] input [3:0] io_in_3_bits_client_id, // @[Arbiters.scala:14:14] input io_in_3_bits_manager_id, // @[Arbiters.scala:14:14] output io_in_4_ready, // @[Arbiters.scala:14:14] input io_in_4_valid, // @[Arbiters.scala:14:14] input [3:0] io_in_4_bits_client_id, // @[Arbiters.scala:14:14] input io_in_4_bits_manager_id, // @[Arbiters.scala:14:14] input io_out_ready, // @[Arbiters.scala:14:14] output io_out_valid, // @[Arbiters.scala:14:14] output [2:0] io_out_bits_opcode, // @[Arbiters.scala:14:14] output [3:0] io_out_bits_client_id, // @[Arbiters.scala:14:14] output io_out_bits_manager_id, // @[Arbiters.scala:14:14] output [63:0] io_out_bits_data // @[Arbiters.scala:14:14] ); wire io_in_0_valid_0 = io_in_0_valid; // @[Arbiter.scala:7:7] wire [3:0] io_in_0_bits_client_id_0 = io_in_0_bits_client_id; // @[Arbiter.scala:7:7] wire io_in_0_bits_manager_id_0 = io_in_0_bits_manager_id; // @[Arbiter.scala:7:7] wire [63:0] io_in_0_bits_data_0 = io_in_0_bits_data; // @[Arbiter.scala:7:7] wire io_in_1_valid_0 = io_in_1_valid; // @[Arbiter.scala:7:7] wire [3:0] io_in_1_bits_client_id_0 = io_in_1_bits_client_id; // @[Arbiter.scala:7:7] wire io_in_1_bits_manager_id_0 = io_in_1_bits_manager_id; // @[Arbiter.scala:7:7] wire io_in_2_valid_0 = io_in_2_valid; // @[Arbiter.scala:7:7] wire [3:0] io_in_2_bits_client_id_0 = io_in_2_bits_client_id; // @[Arbiter.scala:7:7] wire io_in_2_bits_manager_id_0 = io_in_2_bits_manager_id; // @[Arbiter.scala:7:7] wire [63:0] io_in_2_bits_data_0 = io_in_2_bits_data; // @[Arbiter.scala:7:7] wire io_in_3_valid_0 = io_in_3_valid; // @[Arbiter.scala:7:7] wire [3:0] io_in_3_bits_client_id_0 = io_in_3_bits_client_id; // @[Arbiter.scala:7:7] wire io_in_3_bits_manager_id_0 = io_in_3_bits_manager_id; // @[Arbiter.scala:7:7] wire io_in_4_valid_0 = io_in_4_valid; // @[Arbiter.scala:7:7] wire [3:0] io_in_4_bits_client_id_0 = io_in_4_bits_client_id; // @[Arbiter.scala:7:7] wire io_in_4_bits_manager_id_0 = io_in_4_bits_manager_id; // @[Arbiter.scala:7:7] wire io_out_ready_0 = io_out_ready; // @[Arbiter.scala:7:7] wire [7:0][2:0] _GEN = '{3'h0, 3'h0, 3'h0, 3'h4, 3'h3, 3'h2, 3'h1, 3'h0}; wire [2:0] io_in_4_bits_opcode = 3'h4; // @[Arbiter.scala:7:7] wire [2:0] io_in_3_bits_opcode = 3'h3; // @[Arbiters.scala:40:46] wire [2:0] io_in_2_bits_opcode = 3'h2; // @[Arbiters.scala:40:46] wire [63:0] io_in_1_bits_data = 64'h0; // @[Arbiters.scala:14:14] wire [63:0] io_in_3_bits_data = 64'h0; // @[Arbiters.scala:14:14] wire [63:0] io_in_4_bits_data = 64'h0; // @[Arbiters.scala:14:14] wire [2:0] io_in_1_bits_opcode = 3'h1; // @[Arbiters.scala:40:46] wire [2:0] io_in_0_bits_opcode = 3'h0; // @[Arbiter.scala:7:7] wire _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_1_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_2_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_3_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_4_ready_T_1; // @[Arbiters.scala:40:36] wire io_in_0_ready_0; // @[Arbiter.scala:7:7] wire io_in_1_ready_0; // @[Arbiter.scala:7:7] wire io_in_2_ready_0; // @[Arbiter.scala:7:7] wire io_in_3_ready_0; // @[Arbiter.scala:7:7] wire io_in_4_ready_0; // @[Arbiter.scala:7:7] wire [2:0] io_out_bits_opcode_0; // @[Arbiter.scala:7:7] wire [3:0] io_out_bits_client_id_0; // @[Arbiter.scala:7:7] wire io_out_bits_manager_id_0; // @[Arbiter.scala:7:7] wire [63:0] io_out_bits_data_0; // @[Arbiter.scala:7:7] wire io_out_valid_0; // @[Arbiter.scala:7:7] reg [2:0] lockIdx; // @[Arbiters.scala:26:24] reg locked; // @[Arbiters.scala:27:23] wire [2:0] _choice_T = io_in_3_valid_0 ? 3'h3 : 3'h4; // @[Mux.scala:50:70] wire [2:0] _choice_T_1 = io_in_2_valid_0 ? 3'h2 : _choice_T; // @[Mux.scala:50:70] wire [2:0] _choice_T_2 = io_in_1_valid_0 ? 3'h1 : _choice_T_1; // @[Mux.scala:50:70] wire [2:0] choice = io_in_0_valid_0 ? 3'h0 : _choice_T_2; // @[Mux.scala:50:70] wire [2:0] chosen = locked ? lockIdx : choice; // @[Mux.scala:50:70] wire _io_in_0_ready_T = chosen == 3'h0; // @[Arbiters.scala:37:19, :40:46] assign _io_in_0_ready_T_1 = io_out_ready_0 & _io_in_0_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_0_ready_0 = _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_1_ready_T = chosen == 3'h1; // @[Arbiters.scala:37:19, :40:46] assign _io_in_1_ready_T_1 = io_out_ready_0 & _io_in_1_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_1_ready_0 = _io_in_1_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_2_ready_T = chosen == 3'h2; // @[Arbiters.scala:37:19, :40:46] assign _io_in_2_ready_T_1 = io_out_ready_0 & _io_in_2_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_2_ready_0 = _io_in_2_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_3_ready_T = chosen == 3'h3; // @[Arbiters.scala:37:19, :40:46] assign _io_in_3_ready_T_1 = io_out_ready_0 & _io_in_3_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_3_ready_0 = _io_in_3_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_4_ready_T = chosen == 3'h4; // @[Arbiters.scala:37:19, :40:46] assign _io_in_4_ready_T_1 = io_out_ready_0 & _io_in_4_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_4_ready_0 = _io_in_4_ready_T_1; // @[Arbiters.scala:40:36] wire [7:0] _GEN_0 = {{io_in_0_valid_0}, {io_in_0_valid_0}, {io_in_0_valid_0}, {io_in_4_valid_0}, {io_in_3_valid_0}, {io_in_2_valid_0}, {io_in_1_valid_0}, {io_in_0_valid_0}}; // @[Arbiters.scala:43:16] assign io_out_valid_0 = _GEN_0[chosen]; // @[Arbiters.scala:37:19, :43:16] assign io_out_bits_opcode_0 = _GEN[chosen]; // @[Arbiters.scala:37:19, :43:16] wire [7:0][3:0] _GEN_1 = {{io_in_0_bits_client_id_0}, {io_in_0_bits_client_id_0}, {io_in_0_bits_client_id_0}, {io_in_4_bits_client_id_0}, {io_in_3_bits_client_id_0}, {io_in_2_bits_client_id_0}, {io_in_1_bits_client_id_0}, {io_in_0_bits_client_id_0}}; // @[Arbiters.scala:43:16] assign io_out_bits_client_id_0 = _GEN_1[chosen]; // @[Arbiters.scala:37:19, :43:16] wire [7:0] _GEN_2 = {{io_in_0_bits_manager_id_0}, {io_in_0_bits_manager_id_0}, {io_in_0_bits_manager_id_0}, {io_in_4_bits_manager_id_0}, {io_in_3_bits_manager_id_0}, {io_in_2_bits_manager_id_0}, {io_in_1_bits_manager_id_0}, {io_in_0_bits_manager_id_0}}; // @[Arbiters.scala:43:16] assign io_out_bits_manager_id_0 = _GEN_2[chosen]; // @[Arbiters.scala:37:19, :43:16] wire [7:0][63:0] _GEN_3 = {{io_in_0_bits_data_0}, {io_in_0_bits_data_0}, {io_in_0_bits_data_0}, {64'h0}, {64'h0}, {io_in_2_bits_data_0}, {64'h0}, {io_in_0_bits_data_0}}; // @[Arbiters.scala:14:14, :43:16] assign io_out_bits_data_0 = _GEN_3[chosen]; // @[Arbiters.scala:37:19, :43:16] reg [1:0] beat; // @[Protocol.scala:54:23] reg [1:0] max_beat; // @[Protocol.scala:55:27] wire first = beat == 2'h0; // @[Protocol.scala:54:23, :56:22] wire last; // @[Protocol.scala:57:20] wire [6:0] _inst_T_7; // @[Protocol.scala:58:36] wire [4:0] _inst_T_6; // @[Protocol.scala:58:36] wire [4:0] _inst_T_5; // @[Protocol.scala:58:36] wire _inst_T_4; // @[Protocol.scala:58:36] wire _inst_T_3; // @[Protocol.scala:58:36] wire _inst_T_2; // @[Protocol.scala:58:36] wire [4:0] _inst_T_1; // @[Protocol.scala:58:36] wire [6:0] _inst_T; // @[Protocol.scala:58:36] wire [6:0] inst_funct; // @[Protocol.scala:58:36] wire [4:0] inst_rs2; // @[Protocol.scala:58:36] wire [4:0] inst_rs1; // @[Protocol.scala:58:36] wire inst_xd; // @[Protocol.scala:58:36] wire inst_xs1; // @[Protocol.scala:58:36] wire inst_xs2; // @[Protocol.scala:58:36] wire [4:0] inst_rd; // @[Protocol.scala:58:36] wire [6:0] inst_opcode; // @[Protocol.scala:58:36] wire [31:0] _inst_WIRE = io_out_bits_data_0[31:0]; // @[Protocol.scala:58:36] assign _inst_T = _inst_WIRE[6:0]; // @[Protocol.scala:58:36] assign inst_opcode = _inst_T; // @[Protocol.scala:58:36] assign _inst_T_1 = _inst_WIRE[11:7]; // @[Protocol.scala:58:36] assign inst_rd = _inst_T_1; // @[Protocol.scala:58:36] assign _inst_T_2 = _inst_WIRE[12]; // @[Protocol.scala:58:36] assign inst_xs2 = _inst_T_2; // @[Protocol.scala:58:36] assign _inst_T_3 = _inst_WIRE[13]; // @[Protocol.scala:58:36] assign inst_xs1 = _inst_T_3; // @[Protocol.scala:58:36] assign _inst_T_4 = _inst_WIRE[14]; // @[Protocol.scala:58:36] assign inst_xd = _inst_T_4; // @[Protocol.scala:58:36] assign _inst_T_5 = _inst_WIRE[19:15]; // @[Protocol.scala:58:36] assign inst_rs1 = _inst_T_5; // @[Protocol.scala:58:36] assign _inst_T_6 = _inst_WIRE[24:20]; // @[Protocol.scala:58:36] assign inst_rs2 = _inst_T_6; // @[Protocol.scala:58:36] assign _inst_T_7 = _inst_WIRE[31:25]; // @[Protocol.scala:58:36] assign inst_funct = _inst_T_7; // @[Protocol.scala:58:36] wire _last_T = beat == max_beat; // @[Protocol.scala:54:23, :55:27, :83:22] wire _last_T_1 = ~first; // @[Protocol.scala:56:22, :83:38] wire _last_T_2 = _last_T & _last_T_1; // @[Protocol.scala:83:{22,35,38}] assign last = io_out_bits_opcode_0 != 3'h2 | _last_T_2; // @[Arbiters.scala:40:46] wire [2:0] _beat_T = {1'h0, beat} + 3'h1; // @[Arbiters.scala:40:46] wire [1:0] _beat_T_1 = _beat_T[1:0]; // @[Protocol.scala:87:34] wire _T_7 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Arbiter.scala:7:7] if (reset) begin // @[Arbiter.scala:7:7] lockIdx <= 3'h0; // @[Arbiters.scala:26:24] locked <= 1'h0; // @[Arbiters.scala:27:23] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Arbiter.scala:7:7] if (_T_7 & ~locked) // @[Decoupled.scala:51:35] lockIdx <= choice; // @[Mux.scala:50:70] if (_T_7) // @[Decoupled.scala:51:35] locked <= ~last; // @[Arbiters.scala:27:23] if (_T_7 & last) begin // @[Decoupled.scala:51:35] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Protocol.scala:88:18] if (_T_7) // @[Decoupled.scala:51:35] beat <= _beat_T_1; // @[Protocol.scala:54:23, :87:34] if (_T_7 & first) // @[Decoupled.scala:51:35] max_beat <= {1'h0, io_out_bits_opcode_0 == 3'h2}; // @[Arbiters.scala:40:46] end end always @(posedge) assign io_in_0_ready = io_in_0_ready_0; // @[Arbiter.scala:7:7] assign io_in_1_ready = io_in_1_ready_0; // @[Arbiter.scala:7:7] assign io_in_2_ready = io_in_2_ready_0; // @[Arbiter.scala:7:7] assign io_in_3_ready = io_in_3_ready_0; // @[Arbiter.scala:7:7] assign io_in_4_ready = io_in_4_ready_0; // @[Arbiter.scala:7:7] assign io_out_valid = io_out_valid_0; // @[Arbiter.scala:7:7] assign io_out_bits_opcode = io_out_bits_opcode_0; // @[Arbiter.scala:7:7] assign io_out_bits_client_id = io_out_bits_client_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_manager_id = io_out_bits_manager_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_data = io_out_bits_data_0; // @[Arbiter.scala:7:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_57 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}}, resp : { `2` : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, `1` : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, `0` : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<20> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<30> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_1, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_0_2) node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_1_2) node decoded_orMatrixOutputs_lo_lo_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_lo_hi, _decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_lo_lo_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_orMatrixOutputs_lo_lo_hi_lo) node decoded_orMatrixOutputs_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_hi, decoded_orMatrixOutputs_lo_lo_lo) node decoded_orMatrixOutputs_lo_hi_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_hi = cat(_decoded_orMatrixOutputs_T_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_orMatrixOutputs_lo_hi_lo_lo) node decoded_orMatrixOutputs_lo_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_orMatrixOutputs_lo_hi_hi_lo) node decoded_orMatrixOutputs_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_hi, decoded_orMatrixOutputs_lo_hi_lo) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_orMatrixOutputs_hi_lo_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_orMatrixOutputs_hi_lo_hi_lo) node decoded_orMatrixOutputs_hi_lo = cat(decoded_orMatrixOutputs_hi_lo_hi, decoded_orMatrixOutputs_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_orMatrixOutputs_hi_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_hi_lo) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_lo) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs, 9, 9) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs, 10, 10) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs, 11, 11) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs, 12, 12) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs, 13, 13) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs, 14, 14) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs, 15, 15) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs, 16, 16) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs, 17, 17) node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs, 18, 18) node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs, 19, 19) node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs, 20, 20) node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs, 21, 21) node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs, 22, 22) node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs, 23, 23) node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs, 24, 24) node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs, 25, 25) node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs, 26, 26) node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs, 27, 27) node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs, 28, 28) node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs, 29, 29) node decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1) node decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_lo_hi, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_lo_hi_lo = cat(_decoded_invMatrixOutputs_T_4, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_6, _decoded_invMatrixOutputs_T_5) node decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_invMatrixOutputs_lo_lo_hi_lo) node decoded_invMatrixOutputs_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_hi, decoded_invMatrixOutputs_lo_lo_lo) node decoded_invMatrixOutputs_lo_hi_lo_lo = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_invMatrixOutputs_lo_hi_lo_lo) node decoded_invMatrixOutputs_lo_hi_hi_lo = cat(_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11) node decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_invMatrixOutputs_lo_hi_hi_lo) node decoded_invMatrixOutputs_lo_hi = cat(decoded_invMatrixOutputs_lo_hi_hi, decoded_invMatrixOutputs_lo_hi_lo) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_invMatrixOutputs_hi_lo_lo_hi, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_lo_hi_lo = cat(_decoded_invMatrixOutputs_T_19, _decoded_invMatrixOutputs_T_18) node decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_21, _decoded_invMatrixOutputs_T_20) node decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_invMatrixOutputs_hi_lo_hi_lo) node decoded_invMatrixOutputs_hi_lo = cat(decoded_invMatrixOutputs_hi_lo_hi, decoded_invMatrixOutputs_hi_lo_lo) node decoded_invMatrixOutputs_hi_hi_lo_lo = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22) node decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_25, _decoded_invMatrixOutputs_T_24) node decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_invMatrixOutputs_hi_hi_lo_lo) node decoded_invMatrixOutputs_hi_hi_hi_lo = cat(_decoded_invMatrixOutputs_T_27, _decoded_invMatrixOutputs_T_26) node decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28) node decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_invMatrixOutputs_hi_hi_hi_lo) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, decoded_invMatrixOutputs_hi_hi_lo) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 15, 0) node _decoded_T_1 = shl(UInt<8>(0hff), 8) node _decoded_T_2 = xor(UInt<16>(0hffff), _decoded_T_1) node _decoded_T_3 = shr(_decoded_T, 8) node _decoded_T_4 = and(_decoded_T_3, _decoded_T_2) node _decoded_T_5 = bits(_decoded_T, 7, 0) node _decoded_T_6 = shl(_decoded_T_5, 8) node _decoded_T_7 = not(_decoded_T_2) node _decoded_T_8 = and(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = or(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(_decoded_T_2, 11, 0) node _decoded_T_11 = shl(_decoded_T_10, 4) node _decoded_T_12 = xor(_decoded_T_2, _decoded_T_11) node _decoded_T_13 = shr(_decoded_T_9, 4) node _decoded_T_14 = and(_decoded_T_13, _decoded_T_12) node _decoded_T_15 = bits(_decoded_T_9, 11, 0) node _decoded_T_16 = shl(_decoded_T_15, 4) node _decoded_T_17 = not(_decoded_T_12) node _decoded_T_18 = and(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = or(_decoded_T_14, _decoded_T_18) node _decoded_T_20 = bits(_decoded_T_12, 13, 0) node _decoded_T_21 = shl(_decoded_T_20, 2) node _decoded_T_22 = xor(_decoded_T_12, _decoded_T_21) node _decoded_T_23 = shr(_decoded_T_19, 2) node _decoded_T_24 = and(_decoded_T_23, _decoded_T_22) node _decoded_T_25 = bits(_decoded_T_19, 13, 0) node _decoded_T_26 = shl(_decoded_T_25, 2) node _decoded_T_27 = not(_decoded_T_22) node _decoded_T_28 = and(_decoded_T_26, _decoded_T_27) node _decoded_T_29 = or(_decoded_T_24, _decoded_T_28) node _decoded_T_30 = bits(_decoded_T_22, 14, 0) node _decoded_T_31 = shl(_decoded_T_30, 1) node _decoded_T_32 = xor(_decoded_T_22, _decoded_T_31) node _decoded_T_33 = shr(_decoded_T_29, 1) node _decoded_T_34 = and(_decoded_T_33, _decoded_T_32) node _decoded_T_35 = bits(_decoded_T_29, 14, 0) node _decoded_T_36 = shl(_decoded_T_35, 1) node _decoded_T_37 = not(_decoded_T_32) node _decoded_T_38 = and(_decoded_T_36, _decoded_T_37) node _decoded_T_39 = or(_decoded_T_34, _decoded_T_38) node _decoded_T_40 = bits(decoded_plaOutput, 29, 16) node _decoded_T_41 = bits(_decoded_T_40, 7, 0) node _decoded_T_42 = shl(UInt<4>(0hf), 4) node _decoded_T_43 = xor(UInt<8>(0hff), _decoded_T_42) node _decoded_T_44 = shr(_decoded_T_41, 4) node _decoded_T_45 = and(_decoded_T_44, _decoded_T_43) node _decoded_T_46 = bits(_decoded_T_41, 3, 0) node _decoded_T_47 = shl(_decoded_T_46, 4) node _decoded_T_48 = not(_decoded_T_43) node _decoded_T_49 = and(_decoded_T_47, _decoded_T_48) node _decoded_T_50 = or(_decoded_T_45, _decoded_T_49) node _decoded_T_51 = bits(_decoded_T_43, 5, 0) node _decoded_T_52 = shl(_decoded_T_51, 2) node _decoded_T_53 = xor(_decoded_T_43, _decoded_T_52) node _decoded_T_54 = shr(_decoded_T_50, 2) node _decoded_T_55 = and(_decoded_T_54, _decoded_T_53) node _decoded_T_56 = bits(_decoded_T_50, 5, 0) node _decoded_T_57 = shl(_decoded_T_56, 2) node _decoded_T_58 = not(_decoded_T_53) node _decoded_T_59 = and(_decoded_T_57, _decoded_T_58) node _decoded_T_60 = or(_decoded_T_55, _decoded_T_59) node _decoded_T_61 = bits(_decoded_T_53, 6, 0) node _decoded_T_62 = shl(_decoded_T_61, 1) node _decoded_T_63 = xor(_decoded_T_53, _decoded_T_62) node _decoded_T_64 = shr(_decoded_T_60, 1) node _decoded_T_65 = and(_decoded_T_64, _decoded_T_63) node _decoded_T_66 = bits(_decoded_T_60, 6, 0) node _decoded_T_67 = shl(_decoded_T_66, 1) node _decoded_T_68 = not(_decoded_T_63) node _decoded_T_69 = and(_decoded_T_67, _decoded_T_68) node _decoded_T_70 = or(_decoded_T_65, _decoded_T_69) node _decoded_T_71 = bits(_decoded_T_40, 13, 8) node _decoded_T_72 = bits(_decoded_T_71, 3, 0) node _decoded_T_73 = bits(_decoded_T_72, 1, 0) node _decoded_T_74 = bits(_decoded_T_73, 0, 0) node _decoded_T_75 = bits(_decoded_T_73, 1, 1) node _decoded_T_76 = cat(_decoded_T_74, _decoded_T_75) node _decoded_T_77 = bits(_decoded_T_72, 3, 2) node _decoded_T_78 = bits(_decoded_T_77, 0, 0) node _decoded_T_79 = bits(_decoded_T_77, 1, 1) node _decoded_T_80 = cat(_decoded_T_78, _decoded_T_79) node _decoded_T_81 = cat(_decoded_T_76, _decoded_T_80) node _decoded_T_82 = bits(_decoded_T_71, 5, 4) node _decoded_T_83 = bits(_decoded_T_82, 0, 0) node _decoded_T_84 = bits(_decoded_T_82, 1, 1) node _decoded_T_85 = cat(_decoded_T_83, _decoded_T_84) node _decoded_T_86 = cat(_decoded_T_81, _decoded_T_85) node _decoded_T_87 = cat(_decoded_T_70, _decoded_T_86) node decoded = cat(_decoded_T_39, _decoded_T_87) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T node _io_resp_0_vc_sel_0_4_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`0`[4], _io_resp_0_vc_sel_0_4_T node _io_resp_0_vc_sel_0_5_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`0`[5], _io_resp_0_vc_sel_0_5_T node _io_resp_0_vc_sel_0_6_T = bits(decoded, 6, 6) connect io.resp.`0`.vc_sel.`0`[6], _io_resp_0_vc_sel_0_6_T node _io_resp_0_vc_sel_0_7_T = bits(decoded, 7, 7) connect io.resp.`0`.vc_sel.`0`[7], _io_resp_0_vc_sel_0_7_T node _io_resp_0_vc_sel_0_8_T = bits(decoded, 8, 8) connect io.resp.`0`.vc_sel.`0`[8], _io_resp_0_vc_sel_0_8_T node _io_resp_0_vc_sel_0_9_T = bits(decoded, 9, 9) connect io.resp.`0`.vc_sel.`0`[9], _io_resp_0_vc_sel_0_9_T node _io_resp_0_vc_sel_1_0_T = bits(decoded, 10, 10) connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T node _io_resp_0_vc_sel_1_1_T = bits(decoded, 11, 11) connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T node _io_resp_0_vc_sel_1_2_T = bits(decoded, 12, 12) connect io.resp.`0`.vc_sel.`1`[2], _io_resp_0_vc_sel_1_2_T node _io_resp_0_vc_sel_1_3_T = bits(decoded, 13, 13) connect io.resp.`0`.vc_sel.`1`[3], _io_resp_0_vc_sel_1_3_T node _io_resp_0_vc_sel_1_4_T = bits(decoded, 14, 14) connect io.resp.`0`.vc_sel.`1`[4], _io_resp_0_vc_sel_1_4_T node _io_resp_0_vc_sel_1_5_T = bits(decoded, 15, 15) connect io.resp.`0`.vc_sel.`1`[5], _io_resp_0_vc_sel_1_5_T node _io_resp_0_vc_sel_1_6_T = bits(decoded, 16, 16) connect io.resp.`0`.vc_sel.`1`[6], _io_resp_0_vc_sel_1_6_T node _io_resp_0_vc_sel_1_7_T = bits(decoded, 17, 17) connect io.resp.`0`.vc_sel.`1`[7], _io_resp_0_vc_sel_1_7_T node _io_resp_0_vc_sel_1_8_T = bits(decoded, 18, 18) connect io.resp.`0`.vc_sel.`1`[8], _io_resp_0_vc_sel_1_8_T node _io_resp_0_vc_sel_1_9_T = bits(decoded, 19, 19) connect io.resp.`0`.vc_sel.`1`[9], _io_resp_0_vc_sel_1_9_T node _io_resp_0_vc_sel_2_0_T = bits(decoded, 20, 20) connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T node _io_resp_0_vc_sel_2_1_T = bits(decoded, 21, 21) connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T node _io_resp_0_vc_sel_2_2_T = bits(decoded, 22, 22) connect io.resp.`0`.vc_sel.`2`[2], _io_resp_0_vc_sel_2_2_T node _io_resp_0_vc_sel_2_3_T = bits(decoded, 23, 23) connect io.resp.`0`.vc_sel.`2`[3], _io_resp_0_vc_sel_2_3_T node _io_resp_0_vc_sel_2_4_T = bits(decoded, 24, 24) connect io.resp.`0`.vc_sel.`2`[4], _io_resp_0_vc_sel_2_4_T node _io_resp_0_vc_sel_2_5_T = bits(decoded, 25, 25) connect io.resp.`0`.vc_sel.`2`[5], _io_resp_0_vc_sel_2_5_T node _io_resp_0_vc_sel_2_6_T = bits(decoded, 26, 26) connect io.resp.`0`.vc_sel.`2`[6], _io_resp_0_vc_sel_2_6_T node _io_resp_0_vc_sel_2_7_T = bits(decoded, 27, 27) connect io.resp.`0`.vc_sel.`2`[7], _io_resp_0_vc_sel_2_7_T node _io_resp_0_vc_sel_2_8_T = bits(decoded, 28, 28) connect io.resp.`0`.vc_sel.`2`[8], _io_resp_0_vc_sel_2_8_T node _io_resp_0_vc_sel_2_9_T = bits(decoded, 29, 29) connect io.resp.`0`.vc_sel.`2`[9], _io_resp_0_vc_sel_2_9_T connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<20> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<30> node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs_1, 19, 19) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs_1, 19, 19) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_3, decoded_andMatrixOutputs_andMatrixInput_3_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs_1, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs_1, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_orMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_2 = cat(decoded_orMatrixOutputs_hi_1, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node decoded_orMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_4 = cat(decoded_orMatrixOutputs_hi_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_6 = cat(decoded_orMatrixOutputs_hi_3, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_7 = orr(_decoded_orMatrixOutputs_T_6) node decoded_orMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_8 = cat(decoded_orMatrixOutputs_hi_4, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8) node decoded_orMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_10 = cat(decoded_orMatrixOutputs_hi_5, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_12 = cat(decoded_orMatrixOutputs_hi_6, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_14 = cat(decoded_orMatrixOutputs_hi_7, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_15 = orr(_decoded_orMatrixOutputs_T_14) node decoded_orMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_0_2_1, decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_16 = cat(decoded_orMatrixOutputs_hi_8, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_17 = orr(_decoded_orMatrixOutputs_T_16) node decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_lo_1 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_1, decoded_orMatrixOutputs_lo_lo_hi_lo_1) node decoded_orMatrixOutputs_lo_lo_1 = cat(decoded_orMatrixOutputs_lo_lo_hi_1, decoded_orMatrixOutputs_lo_lo_lo_1) node decoded_orMatrixOutputs_lo_hi_lo_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_1, decoded_orMatrixOutputs_lo_hi_lo_lo_1) node decoded_orMatrixOutputs_lo_hi_hi_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_1, decoded_orMatrixOutputs_lo_hi_hi_lo_1) node decoded_orMatrixOutputs_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_1, decoded_orMatrixOutputs_lo_hi_lo_1) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_1 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_5, _decoded_orMatrixOutputs_T_3) node decoded_orMatrixOutputs_hi_lo_hi_1 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_1, decoded_orMatrixOutputs_hi_lo_hi_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(decoded_orMatrixOutputs_hi_lo_hi_1, decoded_orMatrixOutputs_hi_lo_lo_1) node decoded_orMatrixOutputs_hi_hi_lo_lo_1 = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_hi_hi_lo_1 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_1, decoded_orMatrixOutputs_hi_hi_lo_lo_1) node decoded_orMatrixOutputs_hi_hi_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_17, _decoded_orMatrixOutputs_T_15) node decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_1, decoded_orMatrixOutputs_hi_hi_hi_lo_1) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, decoded_orMatrixOutputs_hi_hi_lo_1) node decoded_orMatrixOutputs_hi_9 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_9, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_1, 8, 8) node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_1, 9, 9) node _decoded_invMatrixOutputs_T_40 = bits(decoded_orMatrixOutputs_1, 10, 10) node _decoded_invMatrixOutputs_T_41 = bits(decoded_orMatrixOutputs_1, 11, 11) node _decoded_invMatrixOutputs_T_42 = bits(decoded_orMatrixOutputs_1, 12, 12) node _decoded_invMatrixOutputs_T_43 = bits(decoded_orMatrixOutputs_1, 13, 13) node _decoded_invMatrixOutputs_T_44 = bits(decoded_orMatrixOutputs_1, 14, 14) node _decoded_invMatrixOutputs_T_45 = bits(decoded_orMatrixOutputs_1, 15, 15) node _decoded_invMatrixOutputs_T_46 = bits(decoded_orMatrixOutputs_1, 16, 16) node _decoded_invMatrixOutputs_T_47 = bits(decoded_orMatrixOutputs_1, 17, 17) node _decoded_invMatrixOutputs_T_48 = bits(decoded_orMatrixOutputs_1, 18, 18) node _decoded_invMatrixOutputs_T_49 = bits(decoded_orMatrixOutputs_1, 19, 19) node _decoded_invMatrixOutputs_T_50 = bits(decoded_orMatrixOutputs_1, 20, 20) node _decoded_invMatrixOutputs_T_51 = bits(decoded_orMatrixOutputs_1, 21, 21) node _decoded_invMatrixOutputs_T_52 = bits(decoded_orMatrixOutputs_1, 22, 22) node _decoded_invMatrixOutputs_T_53 = bits(decoded_orMatrixOutputs_1, 23, 23) node _decoded_invMatrixOutputs_T_54 = bits(decoded_orMatrixOutputs_1, 24, 24) node _decoded_invMatrixOutputs_T_55 = bits(decoded_orMatrixOutputs_1, 25, 25) node _decoded_invMatrixOutputs_T_56 = bits(decoded_orMatrixOutputs_1, 26, 26) node _decoded_invMatrixOutputs_T_57 = bits(decoded_orMatrixOutputs_1, 27, 27) node _decoded_invMatrixOutputs_T_58 = bits(decoded_orMatrixOutputs_1, 28, 28) node _decoded_invMatrixOutputs_T_59 = bits(decoded_orMatrixOutputs_1, 29, 29) node decoded_invMatrixOutputs_lo_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_32, _decoded_invMatrixOutputs_T_31) node decoded_invMatrixOutputs_lo_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_1, _decoded_invMatrixOutputs_T_30) node decoded_invMatrixOutputs_lo_lo_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_34, _decoded_invMatrixOutputs_T_33) node decoded_invMatrixOutputs_lo_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_36, _decoded_invMatrixOutputs_T_35) node decoded_invMatrixOutputs_lo_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_1, decoded_invMatrixOutputs_lo_lo_hi_lo_1) node decoded_invMatrixOutputs_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_1, decoded_invMatrixOutputs_lo_lo_lo_1) node decoded_invMatrixOutputs_lo_hi_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_38, _decoded_invMatrixOutputs_T_37) node decoded_invMatrixOutputs_lo_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_40, _decoded_invMatrixOutputs_T_39) node decoded_invMatrixOutputs_lo_hi_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_1, decoded_invMatrixOutputs_lo_hi_lo_lo_1) node decoded_invMatrixOutputs_lo_hi_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_42, _decoded_invMatrixOutputs_T_41) node decoded_invMatrixOutputs_lo_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_44, _decoded_invMatrixOutputs_T_43) node decoded_invMatrixOutputs_lo_hi_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_1, decoded_invMatrixOutputs_lo_hi_hi_lo_1) node decoded_invMatrixOutputs_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_1, decoded_invMatrixOutputs_lo_hi_lo_1) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_47, _decoded_invMatrixOutputs_T_46) node decoded_invMatrixOutputs_hi_lo_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_1, _decoded_invMatrixOutputs_T_45) node decoded_invMatrixOutputs_hi_lo_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_49, _decoded_invMatrixOutputs_T_48) node decoded_invMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_51, _decoded_invMatrixOutputs_T_50) node decoded_invMatrixOutputs_hi_lo_hi_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_1, decoded_invMatrixOutputs_hi_lo_hi_lo_1) node decoded_invMatrixOutputs_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_1, decoded_invMatrixOutputs_hi_lo_lo_1) node decoded_invMatrixOutputs_hi_hi_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_53, _decoded_invMatrixOutputs_T_52) node decoded_invMatrixOutputs_hi_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_55, _decoded_invMatrixOutputs_T_54) node decoded_invMatrixOutputs_hi_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_1, decoded_invMatrixOutputs_hi_hi_lo_lo_1) node decoded_invMatrixOutputs_hi_hi_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_57, _decoded_invMatrixOutputs_T_56) node decoded_invMatrixOutputs_hi_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_59, _decoded_invMatrixOutputs_T_58) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_1, decoded_invMatrixOutputs_hi_hi_hi_lo_1) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, decoded_invMatrixOutputs_hi_hi_lo_1) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_88 = bits(decoded_plaOutput_1, 15, 0) node _decoded_T_89 = shl(UInt<8>(0hff), 8) node _decoded_T_90 = xor(UInt<16>(0hffff), _decoded_T_89) node _decoded_T_91 = shr(_decoded_T_88, 8) node _decoded_T_92 = and(_decoded_T_91, _decoded_T_90) node _decoded_T_93 = bits(_decoded_T_88, 7, 0) node _decoded_T_94 = shl(_decoded_T_93, 8) node _decoded_T_95 = not(_decoded_T_90) node _decoded_T_96 = and(_decoded_T_94, _decoded_T_95) node _decoded_T_97 = or(_decoded_T_92, _decoded_T_96) node _decoded_T_98 = bits(_decoded_T_90, 11, 0) node _decoded_T_99 = shl(_decoded_T_98, 4) node _decoded_T_100 = xor(_decoded_T_90, _decoded_T_99) node _decoded_T_101 = shr(_decoded_T_97, 4) node _decoded_T_102 = and(_decoded_T_101, _decoded_T_100) node _decoded_T_103 = bits(_decoded_T_97, 11, 0) node _decoded_T_104 = shl(_decoded_T_103, 4) node _decoded_T_105 = not(_decoded_T_100) node _decoded_T_106 = and(_decoded_T_104, _decoded_T_105) node _decoded_T_107 = or(_decoded_T_102, _decoded_T_106) node _decoded_T_108 = bits(_decoded_T_100, 13, 0) node _decoded_T_109 = shl(_decoded_T_108, 2) node _decoded_T_110 = xor(_decoded_T_100, _decoded_T_109) node _decoded_T_111 = shr(_decoded_T_107, 2) node _decoded_T_112 = and(_decoded_T_111, _decoded_T_110) node _decoded_T_113 = bits(_decoded_T_107, 13, 0) node _decoded_T_114 = shl(_decoded_T_113, 2) node _decoded_T_115 = not(_decoded_T_110) node _decoded_T_116 = and(_decoded_T_114, _decoded_T_115) node _decoded_T_117 = or(_decoded_T_112, _decoded_T_116) node _decoded_T_118 = bits(_decoded_T_110, 14, 0) node _decoded_T_119 = shl(_decoded_T_118, 1) node _decoded_T_120 = xor(_decoded_T_110, _decoded_T_119) node _decoded_T_121 = shr(_decoded_T_117, 1) node _decoded_T_122 = and(_decoded_T_121, _decoded_T_120) node _decoded_T_123 = bits(_decoded_T_117, 14, 0) node _decoded_T_124 = shl(_decoded_T_123, 1) node _decoded_T_125 = not(_decoded_T_120) node _decoded_T_126 = and(_decoded_T_124, _decoded_T_125) node _decoded_T_127 = or(_decoded_T_122, _decoded_T_126) node _decoded_T_128 = bits(decoded_plaOutput_1, 29, 16) node _decoded_T_129 = bits(_decoded_T_128, 7, 0) node _decoded_T_130 = shl(UInt<4>(0hf), 4) node _decoded_T_131 = xor(UInt<8>(0hff), _decoded_T_130) node _decoded_T_132 = shr(_decoded_T_129, 4) node _decoded_T_133 = and(_decoded_T_132, _decoded_T_131) node _decoded_T_134 = bits(_decoded_T_129, 3, 0) node _decoded_T_135 = shl(_decoded_T_134, 4) node _decoded_T_136 = not(_decoded_T_131) node _decoded_T_137 = and(_decoded_T_135, _decoded_T_136) node _decoded_T_138 = or(_decoded_T_133, _decoded_T_137) node _decoded_T_139 = bits(_decoded_T_131, 5, 0) node _decoded_T_140 = shl(_decoded_T_139, 2) node _decoded_T_141 = xor(_decoded_T_131, _decoded_T_140) node _decoded_T_142 = shr(_decoded_T_138, 2) node _decoded_T_143 = and(_decoded_T_142, _decoded_T_141) node _decoded_T_144 = bits(_decoded_T_138, 5, 0) node _decoded_T_145 = shl(_decoded_T_144, 2) node _decoded_T_146 = not(_decoded_T_141) node _decoded_T_147 = and(_decoded_T_145, _decoded_T_146) node _decoded_T_148 = or(_decoded_T_143, _decoded_T_147) node _decoded_T_149 = bits(_decoded_T_141, 6, 0) node _decoded_T_150 = shl(_decoded_T_149, 1) node _decoded_T_151 = xor(_decoded_T_141, _decoded_T_150) node _decoded_T_152 = shr(_decoded_T_148, 1) node _decoded_T_153 = and(_decoded_T_152, _decoded_T_151) node _decoded_T_154 = bits(_decoded_T_148, 6, 0) node _decoded_T_155 = shl(_decoded_T_154, 1) node _decoded_T_156 = not(_decoded_T_151) node _decoded_T_157 = and(_decoded_T_155, _decoded_T_156) node _decoded_T_158 = or(_decoded_T_153, _decoded_T_157) node _decoded_T_159 = bits(_decoded_T_128, 13, 8) node _decoded_T_160 = bits(_decoded_T_159, 3, 0) node _decoded_T_161 = bits(_decoded_T_160, 1, 0) node _decoded_T_162 = bits(_decoded_T_161, 0, 0) node _decoded_T_163 = bits(_decoded_T_161, 1, 1) node _decoded_T_164 = cat(_decoded_T_162, _decoded_T_163) node _decoded_T_165 = bits(_decoded_T_160, 3, 2) node _decoded_T_166 = bits(_decoded_T_165, 0, 0) node _decoded_T_167 = bits(_decoded_T_165, 1, 1) node _decoded_T_168 = cat(_decoded_T_166, _decoded_T_167) node _decoded_T_169 = cat(_decoded_T_164, _decoded_T_168) node _decoded_T_170 = bits(_decoded_T_159, 5, 4) node _decoded_T_171 = bits(_decoded_T_170, 0, 0) node _decoded_T_172 = bits(_decoded_T_170, 1, 1) node _decoded_T_173 = cat(_decoded_T_171, _decoded_T_172) node _decoded_T_174 = cat(_decoded_T_169, _decoded_T_173) node _decoded_T_175 = cat(_decoded_T_158, _decoded_T_174) node decoded_1 = cat(_decoded_T_127, _decoded_T_175) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T node _io_resp_1_vc_sel_0_4_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`0`[4], _io_resp_1_vc_sel_0_4_T node _io_resp_1_vc_sel_0_5_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`0`[5], _io_resp_1_vc_sel_0_5_T node _io_resp_1_vc_sel_0_6_T = bits(decoded_1, 6, 6) connect io.resp.`1`.vc_sel.`0`[6], _io_resp_1_vc_sel_0_6_T node _io_resp_1_vc_sel_0_7_T = bits(decoded_1, 7, 7) connect io.resp.`1`.vc_sel.`0`[7], _io_resp_1_vc_sel_0_7_T node _io_resp_1_vc_sel_0_8_T = bits(decoded_1, 8, 8) connect io.resp.`1`.vc_sel.`0`[8], _io_resp_1_vc_sel_0_8_T node _io_resp_1_vc_sel_0_9_T = bits(decoded_1, 9, 9) connect io.resp.`1`.vc_sel.`0`[9], _io_resp_1_vc_sel_0_9_T node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 10, 10) connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 11, 11) connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T node _io_resp_1_vc_sel_1_2_T = bits(decoded_1, 12, 12) connect io.resp.`1`.vc_sel.`1`[2], _io_resp_1_vc_sel_1_2_T node _io_resp_1_vc_sel_1_3_T = bits(decoded_1, 13, 13) connect io.resp.`1`.vc_sel.`1`[3], _io_resp_1_vc_sel_1_3_T node _io_resp_1_vc_sel_1_4_T = bits(decoded_1, 14, 14) connect io.resp.`1`.vc_sel.`1`[4], _io_resp_1_vc_sel_1_4_T node _io_resp_1_vc_sel_1_5_T = bits(decoded_1, 15, 15) connect io.resp.`1`.vc_sel.`1`[5], _io_resp_1_vc_sel_1_5_T node _io_resp_1_vc_sel_1_6_T = bits(decoded_1, 16, 16) connect io.resp.`1`.vc_sel.`1`[6], _io_resp_1_vc_sel_1_6_T node _io_resp_1_vc_sel_1_7_T = bits(decoded_1, 17, 17) connect io.resp.`1`.vc_sel.`1`[7], _io_resp_1_vc_sel_1_7_T node _io_resp_1_vc_sel_1_8_T = bits(decoded_1, 18, 18) connect io.resp.`1`.vc_sel.`1`[8], _io_resp_1_vc_sel_1_8_T node _io_resp_1_vc_sel_1_9_T = bits(decoded_1, 19, 19) connect io.resp.`1`.vc_sel.`1`[9], _io_resp_1_vc_sel_1_9_T node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 20, 20) connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 21, 21) connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T node _io_resp_1_vc_sel_2_2_T = bits(decoded_1, 22, 22) connect io.resp.`1`.vc_sel.`2`[2], _io_resp_1_vc_sel_2_2_T node _io_resp_1_vc_sel_2_3_T = bits(decoded_1, 23, 23) connect io.resp.`1`.vc_sel.`2`[3], _io_resp_1_vc_sel_2_3_T node _io_resp_1_vc_sel_2_4_T = bits(decoded_1, 24, 24) connect io.resp.`1`.vc_sel.`2`[4], _io_resp_1_vc_sel_2_4_T node _io_resp_1_vc_sel_2_5_T = bits(decoded_1, 25, 25) connect io.resp.`1`.vc_sel.`2`[5], _io_resp_1_vc_sel_2_5_T node _io_resp_1_vc_sel_2_6_T = bits(decoded_1, 26, 26) connect io.resp.`1`.vc_sel.`2`[6], _io_resp_1_vc_sel_2_6_T node _io_resp_1_vc_sel_2_7_T = bits(decoded_1, 27, 27) connect io.resp.`1`.vc_sel.`2`[7], _io_resp_1_vc_sel_2_7_T node _io_resp_1_vc_sel_2_8_T = bits(decoded_1, 28, 28) connect io.resp.`1`.vc_sel.`2`[8], _io_resp_1_vc_sel_2_8_T node _io_resp_1_vc_sel_2_9_T = bits(decoded_1, 29, 29) connect io.resp.`1`.vc_sel.`2`[9], _io_resp_1_vc_sel_2_9_T connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<20> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<30> node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput_2, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs_2, 19, 19) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_5, decoded_andMatrixOutputs_andMatrixInput_3_5) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs_2, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_plaInput_2, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_2, 19, 19) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_6, decoded_andMatrixOutputs_andMatrixInput_3_6) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_1_2_2 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs_2, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_2, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_7) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_2_2_1 = andr(_decoded_andMatrixOutputs_T_7) node decoded_orMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_18 = cat(decoded_orMatrixOutputs_hi_10, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_19 = orr(_decoded_orMatrixOutputs_T_18) node decoded_orMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_20 = cat(decoded_orMatrixOutputs_hi_11, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_21 = orr(_decoded_orMatrixOutputs_T_20) node decoded_orMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_22 = cat(decoded_orMatrixOutputs_hi_12, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_23 = orr(_decoded_orMatrixOutputs_T_22) node decoded_orMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_24 = cat(decoded_orMatrixOutputs_hi_13, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_25 = orr(_decoded_orMatrixOutputs_T_24) node decoded_orMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_26 = cat(decoded_orMatrixOutputs_hi_14, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_27 = orr(_decoded_orMatrixOutputs_T_26) node decoded_orMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_28 = cat(decoded_orMatrixOutputs_hi_15, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_29 = orr(_decoded_orMatrixOutputs_T_28) node decoded_orMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_30 = cat(decoded_orMatrixOutputs_hi_16, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_31 = orr(_decoded_orMatrixOutputs_T_30) node decoded_orMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_0_2_2, decoded_andMatrixOutputs_1_2_2) node _decoded_orMatrixOutputs_T_32 = cat(decoded_orMatrixOutputs_hi_17, decoded_andMatrixOutputs_2_2_1) node _decoded_orMatrixOutputs_T_33 = orr(_decoded_orMatrixOutputs_T_32) node decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_lo_2 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_2, decoded_orMatrixOutputs_lo_lo_hi_lo_2) node decoded_orMatrixOutputs_lo_lo_2 = cat(decoded_orMatrixOutputs_lo_lo_hi_2, decoded_orMatrixOutputs_lo_lo_lo_2) node decoded_orMatrixOutputs_lo_hi_lo_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_2, decoded_orMatrixOutputs_lo_hi_lo_lo_2) node decoded_orMatrixOutputs_lo_hi_hi_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_2, decoded_orMatrixOutputs_lo_hi_hi_lo_2) node decoded_orMatrixOutputs_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_2, decoded_orMatrixOutputs_lo_hi_lo_2) node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_2) node decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_2 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_21, _decoded_orMatrixOutputs_T_19) node decoded_orMatrixOutputs_hi_lo_hi_2 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_2, decoded_orMatrixOutputs_hi_lo_hi_lo_2) node decoded_orMatrixOutputs_hi_lo_2 = cat(decoded_orMatrixOutputs_hi_lo_hi_2, decoded_orMatrixOutputs_hi_lo_lo_2) node decoded_orMatrixOutputs_hi_hi_lo_lo_2 = cat(_decoded_orMatrixOutputs_T_25, _decoded_orMatrixOutputs_T_23) node decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(_decoded_orMatrixOutputs_T_29, _decoded_orMatrixOutputs_T_27) node decoded_orMatrixOutputs_hi_hi_lo_2 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_2, decoded_orMatrixOutputs_hi_hi_lo_lo_2) node decoded_orMatrixOutputs_hi_hi_hi_lo_2 = cat(_decoded_orMatrixOutputs_T_33, _decoded_orMatrixOutputs_T_31) node decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_2, decoded_orMatrixOutputs_hi_hi_hi_lo_2) node decoded_orMatrixOutputs_hi_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_hi_2, decoded_orMatrixOutputs_hi_hi_lo_2) node decoded_orMatrixOutputs_hi_18 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_2) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_18, decoded_orMatrixOutputs_lo_2) node _decoded_invMatrixOutputs_T_60 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_61 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_62 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_63 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_64 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_65 = bits(decoded_orMatrixOutputs_2, 5, 5) node _decoded_invMatrixOutputs_T_66 = bits(decoded_orMatrixOutputs_2, 6, 6) node _decoded_invMatrixOutputs_T_67 = bits(decoded_orMatrixOutputs_2, 7, 7) node _decoded_invMatrixOutputs_T_68 = bits(decoded_orMatrixOutputs_2, 8, 8) node _decoded_invMatrixOutputs_T_69 = bits(decoded_orMatrixOutputs_2, 9, 9) node _decoded_invMatrixOutputs_T_70 = bits(decoded_orMatrixOutputs_2, 10, 10) node _decoded_invMatrixOutputs_T_71 = bits(decoded_orMatrixOutputs_2, 11, 11) node _decoded_invMatrixOutputs_T_72 = bits(decoded_orMatrixOutputs_2, 12, 12) node _decoded_invMatrixOutputs_T_73 = bits(decoded_orMatrixOutputs_2, 13, 13) node _decoded_invMatrixOutputs_T_74 = bits(decoded_orMatrixOutputs_2, 14, 14) node _decoded_invMatrixOutputs_T_75 = bits(decoded_orMatrixOutputs_2, 15, 15) node _decoded_invMatrixOutputs_T_76 = bits(decoded_orMatrixOutputs_2, 16, 16) node _decoded_invMatrixOutputs_T_77 = bits(decoded_orMatrixOutputs_2, 17, 17) node _decoded_invMatrixOutputs_T_78 = bits(decoded_orMatrixOutputs_2, 18, 18) node _decoded_invMatrixOutputs_T_79 = bits(decoded_orMatrixOutputs_2, 19, 19) node _decoded_invMatrixOutputs_T_80 = bits(decoded_orMatrixOutputs_2, 20, 20) node _decoded_invMatrixOutputs_T_81 = bits(decoded_orMatrixOutputs_2, 21, 21) node _decoded_invMatrixOutputs_T_82 = bits(decoded_orMatrixOutputs_2, 22, 22) node _decoded_invMatrixOutputs_T_83 = bits(decoded_orMatrixOutputs_2, 23, 23) node _decoded_invMatrixOutputs_T_84 = bits(decoded_orMatrixOutputs_2, 24, 24) node _decoded_invMatrixOutputs_T_85 = bits(decoded_orMatrixOutputs_2, 25, 25) node _decoded_invMatrixOutputs_T_86 = bits(decoded_orMatrixOutputs_2, 26, 26) node _decoded_invMatrixOutputs_T_87 = bits(decoded_orMatrixOutputs_2, 27, 27) node _decoded_invMatrixOutputs_T_88 = bits(decoded_orMatrixOutputs_2, 28, 28) node _decoded_invMatrixOutputs_T_89 = bits(decoded_orMatrixOutputs_2, 29, 29) node decoded_invMatrixOutputs_lo_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_62, _decoded_invMatrixOutputs_T_61) node decoded_invMatrixOutputs_lo_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_2, _decoded_invMatrixOutputs_T_60) node decoded_invMatrixOutputs_lo_lo_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_64, _decoded_invMatrixOutputs_T_63) node decoded_invMatrixOutputs_lo_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_66, _decoded_invMatrixOutputs_T_65) node decoded_invMatrixOutputs_lo_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_2, decoded_invMatrixOutputs_lo_lo_hi_lo_2) node decoded_invMatrixOutputs_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_2, decoded_invMatrixOutputs_lo_lo_lo_2) node decoded_invMatrixOutputs_lo_hi_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_68, _decoded_invMatrixOutputs_T_67) node decoded_invMatrixOutputs_lo_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_70, _decoded_invMatrixOutputs_T_69) node decoded_invMatrixOutputs_lo_hi_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_2, decoded_invMatrixOutputs_lo_hi_lo_lo_2) node decoded_invMatrixOutputs_lo_hi_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_72, _decoded_invMatrixOutputs_T_71) node decoded_invMatrixOutputs_lo_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_74, _decoded_invMatrixOutputs_T_73) node decoded_invMatrixOutputs_lo_hi_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_2, decoded_invMatrixOutputs_lo_hi_hi_lo_2) node decoded_invMatrixOutputs_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_2, decoded_invMatrixOutputs_lo_hi_lo_2) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2) node decoded_invMatrixOutputs_hi_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_77, _decoded_invMatrixOutputs_T_76) node decoded_invMatrixOutputs_hi_lo_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_2, _decoded_invMatrixOutputs_T_75) node decoded_invMatrixOutputs_hi_lo_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_79, _decoded_invMatrixOutputs_T_78) node decoded_invMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_81, _decoded_invMatrixOutputs_T_80) node decoded_invMatrixOutputs_hi_lo_hi_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_2, decoded_invMatrixOutputs_hi_lo_hi_lo_2) node decoded_invMatrixOutputs_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_2, decoded_invMatrixOutputs_hi_lo_lo_2) node decoded_invMatrixOutputs_hi_hi_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_83, _decoded_invMatrixOutputs_T_82) node decoded_invMatrixOutputs_hi_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_85, _decoded_invMatrixOutputs_T_84) node decoded_invMatrixOutputs_hi_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_2, decoded_invMatrixOutputs_hi_hi_lo_lo_2) node decoded_invMatrixOutputs_hi_hi_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_87, _decoded_invMatrixOutputs_T_86) node decoded_invMatrixOutputs_hi_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_89, _decoded_invMatrixOutputs_T_88) node decoded_invMatrixOutputs_hi_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_2, decoded_invMatrixOutputs_hi_hi_hi_lo_2) node decoded_invMatrixOutputs_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_2, decoded_invMatrixOutputs_hi_hi_lo_2) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_176 = bits(decoded_plaOutput_2, 15, 0) node _decoded_T_177 = shl(UInt<8>(0hff), 8) node _decoded_T_178 = xor(UInt<16>(0hffff), _decoded_T_177) node _decoded_T_179 = shr(_decoded_T_176, 8) node _decoded_T_180 = and(_decoded_T_179, _decoded_T_178) node _decoded_T_181 = bits(_decoded_T_176, 7, 0) node _decoded_T_182 = shl(_decoded_T_181, 8) node _decoded_T_183 = not(_decoded_T_178) node _decoded_T_184 = and(_decoded_T_182, _decoded_T_183) node _decoded_T_185 = or(_decoded_T_180, _decoded_T_184) node _decoded_T_186 = bits(_decoded_T_178, 11, 0) node _decoded_T_187 = shl(_decoded_T_186, 4) node _decoded_T_188 = xor(_decoded_T_178, _decoded_T_187) node _decoded_T_189 = shr(_decoded_T_185, 4) node _decoded_T_190 = and(_decoded_T_189, _decoded_T_188) node _decoded_T_191 = bits(_decoded_T_185, 11, 0) node _decoded_T_192 = shl(_decoded_T_191, 4) node _decoded_T_193 = not(_decoded_T_188) node _decoded_T_194 = and(_decoded_T_192, _decoded_T_193) node _decoded_T_195 = or(_decoded_T_190, _decoded_T_194) node _decoded_T_196 = bits(_decoded_T_188, 13, 0) node _decoded_T_197 = shl(_decoded_T_196, 2) node _decoded_T_198 = xor(_decoded_T_188, _decoded_T_197) node _decoded_T_199 = shr(_decoded_T_195, 2) node _decoded_T_200 = and(_decoded_T_199, _decoded_T_198) node _decoded_T_201 = bits(_decoded_T_195, 13, 0) node _decoded_T_202 = shl(_decoded_T_201, 2) node _decoded_T_203 = not(_decoded_T_198) node _decoded_T_204 = and(_decoded_T_202, _decoded_T_203) node _decoded_T_205 = or(_decoded_T_200, _decoded_T_204) node _decoded_T_206 = bits(_decoded_T_198, 14, 0) node _decoded_T_207 = shl(_decoded_T_206, 1) node _decoded_T_208 = xor(_decoded_T_198, _decoded_T_207) node _decoded_T_209 = shr(_decoded_T_205, 1) node _decoded_T_210 = and(_decoded_T_209, _decoded_T_208) node _decoded_T_211 = bits(_decoded_T_205, 14, 0) node _decoded_T_212 = shl(_decoded_T_211, 1) node _decoded_T_213 = not(_decoded_T_208) node _decoded_T_214 = and(_decoded_T_212, _decoded_T_213) node _decoded_T_215 = or(_decoded_T_210, _decoded_T_214) node _decoded_T_216 = bits(decoded_plaOutput_2, 29, 16) node _decoded_T_217 = bits(_decoded_T_216, 7, 0) node _decoded_T_218 = shl(UInt<4>(0hf), 4) node _decoded_T_219 = xor(UInt<8>(0hff), _decoded_T_218) node _decoded_T_220 = shr(_decoded_T_217, 4) node _decoded_T_221 = and(_decoded_T_220, _decoded_T_219) node _decoded_T_222 = bits(_decoded_T_217, 3, 0) node _decoded_T_223 = shl(_decoded_T_222, 4) node _decoded_T_224 = not(_decoded_T_219) node _decoded_T_225 = and(_decoded_T_223, _decoded_T_224) node _decoded_T_226 = or(_decoded_T_221, _decoded_T_225) node _decoded_T_227 = bits(_decoded_T_219, 5, 0) node _decoded_T_228 = shl(_decoded_T_227, 2) node _decoded_T_229 = xor(_decoded_T_219, _decoded_T_228) node _decoded_T_230 = shr(_decoded_T_226, 2) node _decoded_T_231 = and(_decoded_T_230, _decoded_T_229) node _decoded_T_232 = bits(_decoded_T_226, 5, 0) node _decoded_T_233 = shl(_decoded_T_232, 2) node _decoded_T_234 = not(_decoded_T_229) node _decoded_T_235 = and(_decoded_T_233, _decoded_T_234) node _decoded_T_236 = or(_decoded_T_231, _decoded_T_235) node _decoded_T_237 = bits(_decoded_T_229, 6, 0) node _decoded_T_238 = shl(_decoded_T_237, 1) node _decoded_T_239 = xor(_decoded_T_229, _decoded_T_238) node _decoded_T_240 = shr(_decoded_T_236, 1) node _decoded_T_241 = and(_decoded_T_240, _decoded_T_239) node _decoded_T_242 = bits(_decoded_T_236, 6, 0) node _decoded_T_243 = shl(_decoded_T_242, 1) node _decoded_T_244 = not(_decoded_T_239) node _decoded_T_245 = and(_decoded_T_243, _decoded_T_244) node _decoded_T_246 = or(_decoded_T_241, _decoded_T_245) node _decoded_T_247 = bits(_decoded_T_216, 13, 8) node _decoded_T_248 = bits(_decoded_T_247, 3, 0) node _decoded_T_249 = bits(_decoded_T_248, 1, 0) node _decoded_T_250 = bits(_decoded_T_249, 0, 0) node _decoded_T_251 = bits(_decoded_T_249, 1, 1) node _decoded_T_252 = cat(_decoded_T_250, _decoded_T_251) node _decoded_T_253 = bits(_decoded_T_248, 3, 2) node _decoded_T_254 = bits(_decoded_T_253, 0, 0) node _decoded_T_255 = bits(_decoded_T_253, 1, 1) node _decoded_T_256 = cat(_decoded_T_254, _decoded_T_255) node _decoded_T_257 = cat(_decoded_T_252, _decoded_T_256) node _decoded_T_258 = bits(_decoded_T_247, 5, 4) node _decoded_T_259 = bits(_decoded_T_258, 0, 0) node _decoded_T_260 = bits(_decoded_T_258, 1, 1) node _decoded_T_261 = cat(_decoded_T_259, _decoded_T_260) node _decoded_T_262 = cat(_decoded_T_257, _decoded_T_261) node _decoded_T_263 = cat(_decoded_T_246, _decoded_T_262) node decoded_2 = cat(_decoded_T_215, _decoded_T_263) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_0_3_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`0`[3], _io_resp_2_vc_sel_0_3_T node _io_resp_2_vc_sel_0_4_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`0`[4], _io_resp_2_vc_sel_0_4_T node _io_resp_2_vc_sel_0_5_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`0`[5], _io_resp_2_vc_sel_0_5_T node _io_resp_2_vc_sel_0_6_T = bits(decoded_2, 6, 6) connect io.resp.`2`.vc_sel.`0`[6], _io_resp_2_vc_sel_0_6_T node _io_resp_2_vc_sel_0_7_T = bits(decoded_2, 7, 7) connect io.resp.`2`.vc_sel.`0`[7], _io_resp_2_vc_sel_0_7_T node _io_resp_2_vc_sel_0_8_T = bits(decoded_2, 8, 8) connect io.resp.`2`.vc_sel.`0`[8], _io_resp_2_vc_sel_0_8_T node _io_resp_2_vc_sel_0_9_T = bits(decoded_2, 9, 9) connect io.resp.`2`.vc_sel.`0`[9], _io_resp_2_vc_sel_0_9_T node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 10, 10) connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 11, 11) connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T node _io_resp_2_vc_sel_1_2_T = bits(decoded_2, 12, 12) connect io.resp.`2`.vc_sel.`1`[2], _io_resp_2_vc_sel_1_2_T node _io_resp_2_vc_sel_1_3_T = bits(decoded_2, 13, 13) connect io.resp.`2`.vc_sel.`1`[3], _io_resp_2_vc_sel_1_3_T node _io_resp_2_vc_sel_1_4_T = bits(decoded_2, 14, 14) connect io.resp.`2`.vc_sel.`1`[4], _io_resp_2_vc_sel_1_4_T node _io_resp_2_vc_sel_1_5_T = bits(decoded_2, 15, 15) connect io.resp.`2`.vc_sel.`1`[5], _io_resp_2_vc_sel_1_5_T node _io_resp_2_vc_sel_1_6_T = bits(decoded_2, 16, 16) connect io.resp.`2`.vc_sel.`1`[6], _io_resp_2_vc_sel_1_6_T node _io_resp_2_vc_sel_1_7_T = bits(decoded_2, 17, 17) connect io.resp.`2`.vc_sel.`1`[7], _io_resp_2_vc_sel_1_7_T node _io_resp_2_vc_sel_1_8_T = bits(decoded_2, 18, 18) connect io.resp.`2`.vc_sel.`1`[8], _io_resp_2_vc_sel_1_8_T node _io_resp_2_vc_sel_1_9_T = bits(decoded_2, 19, 19) connect io.resp.`2`.vc_sel.`1`[9], _io_resp_2_vc_sel_1_9_T node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 20, 20) connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 21, 21) connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T node _io_resp_2_vc_sel_2_2_T = bits(decoded_2, 22, 22) connect io.resp.`2`.vc_sel.`2`[2], _io_resp_2_vc_sel_2_2_T node _io_resp_2_vc_sel_2_3_T = bits(decoded_2, 23, 23) connect io.resp.`2`.vc_sel.`2`[3], _io_resp_2_vc_sel_2_3_T node _io_resp_2_vc_sel_2_4_T = bits(decoded_2, 24, 24) connect io.resp.`2`.vc_sel.`2`[4], _io_resp_2_vc_sel_2_4_T node _io_resp_2_vc_sel_2_5_T = bits(decoded_2, 25, 25) connect io.resp.`2`.vc_sel.`2`[5], _io_resp_2_vc_sel_2_5_T node _io_resp_2_vc_sel_2_6_T = bits(decoded_2, 26, 26) connect io.resp.`2`.vc_sel.`2`[6], _io_resp_2_vc_sel_2_6_T node _io_resp_2_vc_sel_2_7_T = bits(decoded_2, 27, 27) connect io.resp.`2`.vc_sel.`2`[7], _io_resp_2_vc_sel_2_7_T node _io_resp_2_vc_sel_2_8_T = bits(decoded_2, 28, 28) connect io.resp.`2`.vc_sel.`2`[8], _io_resp_2_vc_sel_2_8_T node _io_resp_2_vc_sel_2_9_T = bits(decoded_2, 29, 29) connect io.resp.`2`.vc_sel.`2`[9], _io_resp_2_vc_sel_2_9_T extmodule plusarg_reader_135 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20
module RouteComputer_57( // @[RouteComputer.scala:29:7] input [3:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_8, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_0_9, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_8, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_9, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_2_9, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_9 // @[RouteComputer.scala:40:14] ); wire [18:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id[2:0], io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [18:0] decoded_invInputs_1 = ~{io_req_1_bits_src_virt_id, io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id[2:1]}; // @[pla.scala:78:21] wire [3:0] _decoded_andMatrixOutputs_T_2 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_src_virt_id[1], decoded_invInputs_1[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [3:0] _decoded_andMatrixOutputs_T_3 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_src_virt_id[2], decoded_invInputs_1[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [3:0] _decoded_andMatrixOutputs_T_4 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[16], decoded_invInputs_1[17], io_req_1_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [18:0] decoded_invInputs_2 = ~{io_req_2_bits_src_virt_id, io_req_2_bits_flow_vnet_id, io_req_2_bits_flow_ingress_node, io_req_2_bits_flow_ingress_node_id, io_req_2_bits_flow_egress_node, io_req_2_bits_flow_egress_node_id[2:1]}; // @[pla.scala:78:21] wire [3:0] _decoded_andMatrixOutputs_T_5 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_src_virt_id[1], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [3:0] _decoded_andMatrixOutputs_T_6 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], io_req_2_bits_src_virt_id[2], decoded_invInputs_2[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [3:0] _decoded_andMatrixOutputs_T_7 = {io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[16], decoded_invInputs_2[17], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] assign io_resp_2_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_8 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_2_vc_sel_0_9 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_6, &_decoded_andMatrixOutputs_T_7}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_8 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_9 = |{&_decoded_andMatrixOutputs_T_2, &_decoded_andMatrixOutputs_T_3, &_decoded_andMatrixOutputs_T_4}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_2_9 = &{decoded_invInputs[0], decoded_invInputs[17], decoded_invInputs[18], io_req_0_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_0_vc_sel_1_9 = &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[17], decoded_invInputs[18], io_req_0_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module OptimizationBarrier_TLBEntryData_59 : input clock : Clock input reset : Reset output io : { flip x : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}, y : { ppn : UInt<20>, u : UInt<1>, g : UInt<1>, ae_ptw : UInt<1>, ae_final : UInt<1>, ae_stage2 : UInt<1>, pf : UInt<1>, gf : UInt<1>, sw : UInt<1>, sx : UInt<1>, sr : UInt<1>, hw : UInt<1>, hx : UInt<1>, hr : UInt<1>, pw : UInt<1>, px : UInt<1>, pr : UInt<1>, ppp : UInt<1>, pal : UInt<1>, paa : UInt<1>, eff : UInt<1>, c : UInt<1>, fragmented_superpage : UInt<1>}} connect io.y, io.x
module OptimizationBarrier_TLBEntryData_59( // @[package.scala:267:30] input clock, // @[package.scala:267:30] input reset, // @[package.scala:267:30] input [19:0] io_x_ppn, // @[package.scala:268:18] input io_x_u, // @[package.scala:268:18] input io_x_g, // @[package.scala:268:18] input io_x_ae_ptw, // @[package.scala:268:18] input io_x_ae_final, // @[package.scala:268:18] input io_x_ae_stage2, // @[package.scala:268:18] input io_x_pf, // @[package.scala:268:18] input io_x_gf, // @[package.scala:268:18] input io_x_sw, // @[package.scala:268:18] input io_x_sx, // @[package.scala:268:18] input io_x_sr, // @[package.scala:268:18] input io_x_hw, // @[package.scala:268:18] input io_x_hx, // @[package.scala:268:18] input io_x_hr, // @[package.scala:268:18] input io_x_pw, // @[package.scala:268:18] input io_x_px, // @[package.scala:268:18] input io_x_pr, // @[package.scala:268:18] input io_x_ppp, // @[package.scala:268:18] input io_x_pal, // @[package.scala:268:18] input io_x_paa, // @[package.scala:268:18] input io_x_eff, // @[package.scala:268:18] input io_x_c, // @[package.scala:268:18] input io_x_fragmented_superpage, // @[package.scala:268:18] output [19:0] io_y_ppn, // @[package.scala:268:18] output io_y_u, // @[package.scala:268:18] output io_y_ae_ptw, // @[package.scala:268:18] output io_y_ae_final, // @[package.scala:268:18] output io_y_ae_stage2, // @[package.scala:268:18] output io_y_pf, // @[package.scala:268:18] output io_y_gf, // @[package.scala:268:18] output io_y_sw, // @[package.scala:268:18] output io_y_sx, // @[package.scala:268:18] output io_y_sr, // @[package.scala:268:18] output io_y_hw, // @[package.scala:268:18] output io_y_hx, // @[package.scala:268:18] output io_y_hr, // @[package.scala:268:18] output io_y_pw, // @[package.scala:268:18] output io_y_px, // @[package.scala:268:18] output io_y_pr, // @[package.scala:268:18] output io_y_ppp, // @[package.scala:268:18] output io_y_pal, // @[package.scala:268:18] output io_y_paa, // @[package.scala:268:18] output io_y_eff, // @[package.scala:268:18] output io_y_c // @[package.scala:268:18] ); wire [19:0] io_x_ppn_0 = io_x_ppn; // @[package.scala:267:30] wire io_x_u_0 = io_x_u; // @[package.scala:267:30] wire io_x_g_0 = io_x_g; // @[package.scala:267:30] wire io_x_ae_ptw_0 = io_x_ae_ptw; // @[package.scala:267:30] wire io_x_ae_final_0 = io_x_ae_final; // @[package.scala:267:30] wire io_x_ae_stage2_0 = io_x_ae_stage2; // @[package.scala:267:30] wire io_x_pf_0 = io_x_pf; // @[package.scala:267:30] wire io_x_gf_0 = io_x_gf; // @[package.scala:267:30] wire io_x_sw_0 = io_x_sw; // @[package.scala:267:30] wire io_x_sx_0 = io_x_sx; // @[package.scala:267:30] wire io_x_sr_0 = io_x_sr; // @[package.scala:267:30] wire io_x_hw_0 = io_x_hw; // @[package.scala:267:30] wire io_x_hx_0 = io_x_hx; // @[package.scala:267:30] wire io_x_hr_0 = io_x_hr; // @[package.scala:267:30] wire io_x_pw_0 = io_x_pw; // @[package.scala:267:30] wire io_x_px_0 = io_x_px; // @[package.scala:267:30] wire io_x_pr_0 = io_x_pr; // @[package.scala:267:30] wire io_x_ppp_0 = io_x_ppp; // @[package.scala:267:30] wire io_x_pal_0 = io_x_pal; // @[package.scala:267:30] wire io_x_paa_0 = io_x_paa; // @[package.scala:267:30] wire io_x_eff_0 = io_x_eff; // @[package.scala:267:30] wire io_x_c_0 = io_x_c; // @[package.scala:267:30] wire io_x_fragmented_superpage_0 = io_x_fragmented_superpage; // @[package.scala:267:30] wire [19:0] io_y_ppn_0 = io_x_ppn_0; // @[package.scala:267:30] wire io_y_u_0 = io_x_u_0; // @[package.scala:267:30] wire io_y_g = io_x_g_0; // @[package.scala:267:30] wire io_y_ae_ptw_0 = io_x_ae_ptw_0; // @[package.scala:267:30] wire io_y_ae_final_0 = io_x_ae_final_0; // @[package.scala:267:30] wire io_y_ae_stage2_0 = io_x_ae_stage2_0; // @[package.scala:267:30] wire io_y_pf_0 = io_x_pf_0; // @[package.scala:267:30] wire io_y_gf_0 = io_x_gf_0; // @[package.scala:267:30] wire io_y_sw_0 = io_x_sw_0; // @[package.scala:267:30] wire io_y_sx_0 = io_x_sx_0; // @[package.scala:267:30] wire io_y_sr_0 = io_x_sr_0; // @[package.scala:267:30] wire io_y_hw_0 = io_x_hw_0; // @[package.scala:267:30] wire io_y_hx_0 = io_x_hx_0; // @[package.scala:267:30] wire io_y_hr_0 = io_x_hr_0; // @[package.scala:267:30] wire io_y_pw_0 = io_x_pw_0; // @[package.scala:267:30] wire io_y_px_0 = io_x_px_0; // @[package.scala:267:30] wire io_y_pr_0 = io_x_pr_0; // @[package.scala:267:30] wire io_y_ppp_0 = io_x_ppp_0; // @[package.scala:267:30] wire io_y_pal_0 = io_x_pal_0; // @[package.scala:267:30] wire io_y_paa_0 = io_x_paa_0; // @[package.scala:267:30] wire io_y_eff_0 = io_x_eff_0; // @[package.scala:267:30] wire io_y_c_0 = io_x_c_0; // @[package.scala:267:30] wire io_y_fragmented_superpage = io_x_fragmented_superpage_0; // @[package.scala:267:30] assign io_y_ppn = io_y_ppn_0; // @[package.scala:267:30] assign io_y_u = io_y_u_0; // @[package.scala:267:30] assign io_y_ae_ptw = io_y_ae_ptw_0; // @[package.scala:267:30] assign io_y_ae_final = io_y_ae_final_0; // @[package.scala:267:30] assign io_y_ae_stage2 = io_y_ae_stage2_0; // @[package.scala:267:30] assign io_y_pf = io_y_pf_0; // @[package.scala:267:30] assign io_y_gf = io_y_gf_0; // @[package.scala:267:30] assign io_y_sw = io_y_sw_0; // @[package.scala:267:30] assign io_y_sx = io_y_sx_0; // @[package.scala:267:30] assign io_y_sr = io_y_sr_0; // @[package.scala:267:30] assign io_y_hw = io_y_hw_0; // @[package.scala:267:30] assign io_y_hx = io_y_hx_0; // @[package.scala:267:30] assign io_y_hr = io_y_hr_0; // @[package.scala:267:30] assign io_y_pw = io_y_pw_0; // @[package.scala:267:30] assign io_y_px = io_y_px_0; // @[package.scala:267:30] assign io_y_pr = io_y_pr_0; // @[package.scala:267:30] assign io_y_ppp = io_y_ppp_0; // @[package.scala:267:30] assign io_y_pal = io_y_pal_0; // @[package.scala:267:30] assign io_y_paa = io_y_paa_0; // @[package.scala:267:30] assign io_y_eff = io_y_eff_0; // @[package.scala:267:30] assign io_y_c = io_y_c_0; // @[package.scala:267:30] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_74 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 11, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_17 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_18 = and(_T_16, _T_17) node _T_19 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_20 = and(_T_18, _T_19) node _T_21 = or(UInt<1>(0h0), _T_20) node _T_22 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_23 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_24 = cvt(_T_23) node _T_25 = and(_T_24, asSInt(UInt<14>(0h2000))) node _T_26 = asSInt(_T_25) node _T_27 = eq(_T_26, asSInt(UInt<1>(0h0))) node _T_28 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_29 = cvt(_T_28) node _T_30 = and(_T_29, asSInt(UInt<11>(0h400))) node _T_31 = asSInt(_T_30) node _T_32 = eq(_T_31, asSInt(UInt<1>(0h0))) node _T_33 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_34 = cvt(_T_33) node _T_35 = and(_T_34, asSInt(UInt<9>(0h100))) node _T_36 = asSInt(_T_35) node _T_37 = eq(_T_36, asSInt(UInt<1>(0h0))) node _T_38 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_39 = cvt(_T_38) node _T_40 = and(_T_39, asSInt(UInt<13>(0h1000))) node _T_41 = asSInt(_T_40) node _T_42 = eq(_T_41, asSInt(UInt<1>(0h0))) node _T_43 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_44 = cvt(_T_43) node _T_45 = and(_T_44, asSInt(UInt<17>(0h10000))) node _T_46 = asSInt(_T_45) node _T_47 = eq(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_49 = cvt(_T_48) node _T_50 = and(_T_49, asSInt(UInt<18>(0h2f000))) node _T_51 = asSInt(_T_50) node _T_52 = eq(_T_51, asSInt(UInt<1>(0h0))) node _T_53 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_54 = cvt(_T_53) node _T_55 = and(_T_54, asSInt(UInt<17>(0h10000))) node _T_56 = asSInt(_T_55) node _T_57 = eq(_T_56, asSInt(UInt<1>(0h0))) node _T_58 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<13>(0h1000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<27>(0h4000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_69 = cvt(_T_68) node _T_70 = and(_T_69, asSInt(UInt<13>(0h1000))) node _T_71 = asSInt(_T_70) node _T_72 = eq(_T_71, asSInt(UInt<1>(0h0))) node _T_73 = or(_T_27, _T_32) node _T_74 = or(_T_73, _T_37) node _T_75 = or(_T_74, _T_42) node _T_76 = or(_T_75, _T_47) node _T_77 = or(_T_76, _T_52) node _T_78 = or(_T_77, _T_57) node _T_79 = or(_T_78, _T_62) node _T_80 = or(_T_79, _T_67) node _T_81 = or(_T_80, _T_72) node _T_82 = and(_T_22, _T_81) node _T_83 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_84 = or(UInt<1>(0h0), _T_83) node _T_85 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_86 = cvt(_T_85) node _T_87 = and(_T_86, asSInt(UInt<17>(0h10000))) node _T_88 = asSInt(_T_87) node _T_89 = eq(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_91 = cvt(_T_90) node _T_92 = and(_T_91, asSInt(UInt<29>(0h10000000))) node _T_93 = asSInt(_T_92) node _T_94 = eq(_T_93, asSInt(UInt<1>(0h0))) node _T_95 = or(_T_89, _T_94) node _T_96 = and(_T_84, _T_95) node _T_97 = or(UInt<1>(0h0), _T_82) node _T_98 = or(_T_97, _T_96) node _T_99 = and(_T_21, _T_98) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_99, UInt<1>(0h1), "") : assert_2 node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_105 = and(_T_103, _T_104) node _T_106 = or(UInt<1>(0h0), _T_105) node _T_107 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<14>(0h2000))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<11>(0h400))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_118 = cvt(_T_117) node _T_119 = and(_T_118, asSInt(UInt<9>(0h100))) node _T_120 = asSInt(_T_119) node _T_121 = eq(_T_120, asSInt(UInt<1>(0h0))) node _T_122 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_123 = cvt(_T_122) node _T_124 = and(_T_123, asSInt(UInt<13>(0h1000))) node _T_125 = asSInt(_T_124) node _T_126 = eq(_T_125, asSInt(UInt<1>(0h0))) node _T_127 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_128 = cvt(_T_127) node _T_129 = and(_T_128, asSInt(UInt<17>(0h10000))) node _T_130 = asSInt(_T_129) node _T_131 = eq(_T_130, asSInt(UInt<1>(0h0))) node _T_132 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_133 = cvt(_T_132) node _T_134 = and(_T_133, asSInt(UInt<18>(0h2f000))) node _T_135 = asSInt(_T_134) node _T_136 = eq(_T_135, asSInt(UInt<1>(0h0))) node _T_137 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_138 = cvt(_T_137) node _T_139 = and(_T_138, asSInt(UInt<17>(0h10000))) node _T_140 = asSInt(_T_139) node _T_141 = eq(_T_140, asSInt(UInt<1>(0h0))) node _T_142 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_143 = cvt(_T_142) node _T_144 = and(_T_143, asSInt(UInt<13>(0h1000))) node _T_145 = asSInt(_T_144) node _T_146 = eq(_T_145, asSInt(UInt<1>(0h0))) node _T_147 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_148 = cvt(_T_147) node _T_149 = and(_T_148, asSInt(UInt<17>(0h10000))) node _T_150 = asSInt(_T_149) node _T_151 = eq(_T_150, asSInt(UInt<1>(0h0))) node _T_152 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_153 = cvt(_T_152) node _T_154 = and(_T_153, asSInt(UInt<27>(0h4000000))) node _T_155 = asSInt(_T_154) node _T_156 = eq(_T_155, asSInt(UInt<1>(0h0))) node _T_157 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_158 = cvt(_T_157) node _T_159 = and(_T_158, asSInt(UInt<13>(0h1000))) node _T_160 = asSInt(_T_159) node _T_161 = eq(_T_160, asSInt(UInt<1>(0h0))) node _T_162 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_163 = cvt(_T_162) node _T_164 = and(_T_163, asSInt(UInt<29>(0h10000000))) node _T_165 = asSInt(_T_164) node _T_166 = eq(_T_165, asSInt(UInt<1>(0h0))) node _T_167 = or(_T_111, _T_116) node _T_168 = or(_T_167, _T_121) node _T_169 = or(_T_168, _T_126) node _T_170 = or(_T_169, _T_131) node _T_171 = or(_T_170, _T_136) node _T_172 = or(_T_171, _T_141) node _T_173 = or(_T_172, _T_146) node _T_174 = or(_T_173, _T_151) node _T_175 = or(_T_174, _T_156) node _T_176 = or(_T_175, _T_161) node _T_177 = or(_T_176, _T_166) node _T_178 = and(_T_106, _T_177) node _T_179 = or(UInt<1>(0h0), _T_178) node _T_180 = and(UInt<1>(0h0), _T_179) node _T_181 = asUInt(reset) node _T_182 = eq(_T_181, UInt<1>(0h0)) when _T_182 : node _T_183 = eq(_T_180, UInt<1>(0h0)) when _T_183 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_180, UInt<1>(0h1), "") : assert_3 node _T_184 = asUInt(reset) node _T_185 = eq(_T_184, UInt<1>(0h0)) when _T_185 : node _T_186 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_187 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_188 = asUInt(reset) node _T_189 = eq(_T_188, UInt<1>(0h0)) when _T_189 : node _T_190 = eq(_T_187, UInt<1>(0h0)) when _T_190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_187, UInt<1>(0h1), "") : assert_5 node _T_191 = asUInt(reset) node _T_192 = eq(_T_191, UInt<1>(0h0)) when _T_192 : node _T_193 = eq(is_aligned, UInt<1>(0h0)) when _T_193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_194 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_195 = asUInt(reset) node _T_196 = eq(_T_195, UInt<1>(0h0)) when _T_196 : node _T_197 = eq(_T_194, UInt<1>(0h0)) when _T_197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_194, UInt<1>(0h1), "") : assert_7 node _T_198 = not(io.in.a.bits.mask) node _T_199 = eq(_T_198, UInt<1>(0h0)) node _T_200 = asUInt(reset) node _T_201 = eq(_T_200, UInt<1>(0h0)) when _T_201 : node _T_202 = eq(_T_199, UInt<1>(0h0)) when _T_202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_199, UInt<1>(0h1), "") : assert_8 node _T_203 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_204 = asUInt(reset) node _T_205 = eq(_T_204, UInt<1>(0h0)) when _T_205 : node _T_206 = eq(_T_203, UInt<1>(0h0)) when _T_206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_203, UInt<1>(0h1), "") : assert_9 node _T_207 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_207 : node _T_208 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_209 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_210 = and(_T_208, _T_209) node _T_211 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_212 = and(_T_210, _T_211) node _T_213 = or(UInt<1>(0h0), _T_212) node _T_214 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_215 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_216 = cvt(_T_215) node _T_217 = and(_T_216, asSInt(UInt<14>(0h2000))) node _T_218 = asSInt(_T_217) node _T_219 = eq(_T_218, asSInt(UInt<1>(0h0))) node _T_220 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_221 = cvt(_T_220) node _T_222 = and(_T_221, asSInt(UInt<11>(0h400))) node _T_223 = asSInt(_T_222) node _T_224 = eq(_T_223, asSInt(UInt<1>(0h0))) node _T_225 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_226 = cvt(_T_225) node _T_227 = and(_T_226, asSInt(UInt<9>(0h100))) node _T_228 = asSInt(_T_227) node _T_229 = eq(_T_228, asSInt(UInt<1>(0h0))) node _T_230 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_231 = cvt(_T_230) node _T_232 = and(_T_231, asSInt(UInt<13>(0h1000))) node _T_233 = asSInt(_T_232) node _T_234 = eq(_T_233, asSInt(UInt<1>(0h0))) node _T_235 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_236 = cvt(_T_235) node _T_237 = and(_T_236, asSInt(UInt<17>(0h10000))) node _T_238 = asSInt(_T_237) node _T_239 = eq(_T_238, asSInt(UInt<1>(0h0))) node _T_240 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_241 = cvt(_T_240) node _T_242 = and(_T_241, asSInt(UInt<18>(0h2f000))) node _T_243 = asSInt(_T_242) node _T_244 = eq(_T_243, asSInt(UInt<1>(0h0))) node _T_245 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<17>(0h10000))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<13>(0h1000))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_256 = cvt(_T_255) node _T_257 = and(_T_256, asSInt(UInt<27>(0h4000000))) node _T_258 = asSInt(_T_257) node _T_259 = eq(_T_258, asSInt(UInt<1>(0h0))) node _T_260 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_261 = cvt(_T_260) node _T_262 = and(_T_261, asSInt(UInt<13>(0h1000))) node _T_263 = asSInt(_T_262) node _T_264 = eq(_T_263, asSInt(UInt<1>(0h0))) node _T_265 = or(_T_219, _T_224) node _T_266 = or(_T_265, _T_229) node _T_267 = or(_T_266, _T_234) node _T_268 = or(_T_267, _T_239) node _T_269 = or(_T_268, _T_244) node _T_270 = or(_T_269, _T_249) node _T_271 = or(_T_270, _T_254) node _T_272 = or(_T_271, _T_259) node _T_273 = or(_T_272, _T_264) node _T_274 = and(_T_214, _T_273) node _T_275 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_276 = or(UInt<1>(0h0), _T_275) node _T_277 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_278 = cvt(_T_277) node _T_279 = and(_T_278, asSInt(UInt<17>(0h10000))) node _T_280 = asSInt(_T_279) node _T_281 = eq(_T_280, asSInt(UInt<1>(0h0))) node _T_282 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_283 = cvt(_T_282) node _T_284 = and(_T_283, asSInt(UInt<29>(0h10000000))) node _T_285 = asSInt(_T_284) node _T_286 = eq(_T_285, asSInt(UInt<1>(0h0))) node _T_287 = or(_T_281, _T_286) node _T_288 = and(_T_276, _T_287) node _T_289 = or(UInt<1>(0h0), _T_274) node _T_290 = or(_T_289, _T_288) node _T_291 = and(_T_213, _T_290) node _T_292 = asUInt(reset) node _T_293 = eq(_T_292, UInt<1>(0h0)) when _T_293 : node _T_294 = eq(_T_291, UInt<1>(0h0)) when _T_294 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_291, UInt<1>(0h1), "") : assert_10 node _T_295 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_296 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_297 = and(_T_295, _T_296) node _T_298 = or(UInt<1>(0h0), _T_297) node _T_299 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_300 = cvt(_T_299) node _T_301 = and(_T_300, asSInt(UInt<14>(0h2000))) node _T_302 = asSInt(_T_301) node _T_303 = eq(_T_302, asSInt(UInt<1>(0h0))) node _T_304 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_305 = cvt(_T_304) node _T_306 = and(_T_305, asSInt(UInt<11>(0h400))) node _T_307 = asSInt(_T_306) node _T_308 = eq(_T_307, asSInt(UInt<1>(0h0))) node _T_309 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_310 = cvt(_T_309) node _T_311 = and(_T_310, asSInt(UInt<9>(0h100))) node _T_312 = asSInt(_T_311) node _T_313 = eq(_T_312, asSInt(UInt<1>(0h0))) node _T_314 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_315 = cvt(_T_314) node _T_316 = and(_T_315, asSInt(UInt<13>(0h1000))) node _T_317 = asSInt(_T_316) node _T_318 = eq(_T_317, asSInt(UInt<1>(0h0))) node _T_319 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<17>(0h10000))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<18>(0h2f000))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_330 = cvt(_T_329) node _T_331 = and(_T_330, asSInt(UInt<17>(0h10000))) node _T_332 = asSInt(_T_331) node _T_333 = eq(_T_332, asSInt(UInt<1>(0h0))) node _T_334 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_335 = cvt(_T_334) node _T_336 = and(_T_335, asSInt(UInt<13>(0h1000))) node _T_337 = asSInt(_T_336) node _T_338 = eq(_T_337, asSInt(UInt<1>(0h0))) node _T_339 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_340 = cvt(_T_339) node _T_341 = and(_T_340, asSInt(UInt<17>(0h10000))) node _T_342 = asSInt(_T_341) node _T_343 = eq(_T_342, asSInt(UInt<1>(0h0))) node _T_344 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_345 = cvt(_T_344) node _T_346 = and(_T_345, asSInt(UInt<27>(0h4000000))) node _T_347 = asSInt(_T_346) node _T_348 = eq(_T_347, asSInt(UInt<1>(0h0))) node _T_349 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_350 = cvt(_T_349) node _T_351 = and(_T_350, asSInt(UInt<13>(0h1000))) node _T_352 = asSInt(_T_351) node _T_353 = eq(_T_352, asSInt(UInt<1>(0h0))) node _T_354 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_355 = cvt(_T_354) node _T_356 = and(_T_355, asSInt(UInt<29>(0h10000000))) node _T_357 = asSInt(_T_356) node _T_358 = eq(_T_357, asSInt(UInt<1>(0h0))) node _T_359 = or(_T_303, _T_308) node _T_360 = or(_T_359, _T_313) node _T_361 = or(_T_360, _T_318) node _T_362 = or(_T_361, _T_323) node _T_363 = or(_T_362, _T_328) node _T_364 = or(_T_363, _T_333) node _T_365 = or(_T_364, _T_338) node _T_366 = or(_T_365, _T_343) node _T_367 = or(_T_366, _T_348) node _T_368 = or(_T_367, _T_353) node _T_369 = or(_T_368, _T_358) node _T_370 = and(_T_298, _T_369) node _T_371 = or(UInt<1>(0h0), _T_370) node _T_372 = and(UInt<1>(0h0), _T_371) node _T_373 = asUInt(reset) node _T_374 = eq(_T_373, UInt<1>(0h0)) when _T_374 : node _T_375 = eq(_T_372, UInt<1>(0h0)) when _T_375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_372, UInt<1>(0h1), "") : assert_11 node _T_376 = asUInt(reset) node _T_377 = eq(_T_376, UInt<1>(0h0)) when _T_377 : node _T_378 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_379 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_380 = asUInt(reset) node _T_381 = eq(_T_380, UInt<1>(0h0)) when _T_381 : node _T_382 = eq(_T_379, UInt<1>(0h0)) when _T_382 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_379, UInt<1>(0h1), "") : assert_13 node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(is_aligned, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_386 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_386, UInt<1>(0h1), "") : assert_15 node _T_390 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_390, UInt<1>(0h1), "") : assert_16 node _T_394 = not(io.in.a.bits.mask) node _T_395 = eq(_T_394, UInt<1>(0h0)) node _T_396 = asUInt(reset) node _T_397 = eq(_T_396, UInt<1>(0h0)) when _T_397 : node _T_398 = eq(_T_395, UInt<1>(0h0)) when _T_398 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_395, UInt<1>(0h1), "") : assert_17 node _T_399 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_399, UInt<1>(0h1), "") : assert_18 node _T_403 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_403 : node _T_404 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_405 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_406 = and(_T_404, _T_405) node _T_407 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_408 = and(_T_406, _T_407) node _T_409 = or(UInt<1>(0h0), _T_408) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_409, UInt<1>(0h1), "") : assert_19 node _T_413 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_414 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_415 = and(_T_413, _T_414) node _T_416 = or(UInt<1>(0h0), _T_415) node _T_417 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_418 = cvt(_T_417) node _T_419 = and(_T_418, asSInt(UInt<13>(0h1000))) node _T_420 = asSInt(_T_419) node _T_421 = eq(_T_420, asSInt(UInt<1>(0h0))) node _T_422 = and(_T_416, _T_421) node _T_423 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_424 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_425 = and(_T_423, _T_424) node _T_426 = or(UInt<1>(0h0), _T_425) node _T_427 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_428 = cvt(_T_427) node _T_429 = and(_T_428, asSInt(UInt<14>(0h2000))) node _T_430 = asSInt(_T_429) node _T_431 = eq(_T_430, asSInt(UInt<1>(0h0))) node _T_432 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_433 = cvt(_T_432) node _T_434 = and(_T_433, asSInt(UInt<11>(0h400))) node _T_435 = asSInt(_T_434) node _T_436 = eq(_T_435, asSInt(UInt<1>(0h0))) node _T_437 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_438 = cvt(_T_437) node _T_439 = and(_T_438, asSInt(UInt<9>(0h100))) node _T_440 = asSInt(_T_439) node _T_441 = eq(_T_440, asSInt(UInt<1>(0h0))) node _T_442 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_443 = cvt(_T_442) node _T_444 = and(_T_443, asSInt(UInt<17>(0h10000))) node _T_445 = asSInt(_T_444) node _T_446 = eq(_T_445, asSInt(UInt<1>(0h0))) node _T_447 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_448 = cvt(_T_447) node _T_449 = and(_T_448, asSInt(UInt<18>(0h2f000))) node _T_450 = asSInt(_T_449) node _T_451 = eq(_T_450, asSInt(UInt<1>(0h0))) node _T_452 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_453 = cvt(_T_452) node _T_454 = and(_T_453, asSInt(UInt<17>(0h10000))) node _T_455 = asSInt(_T_454) node _T_456 = eq(_T_455, asSInt(UInt<1>(0h0))) node _T_457 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_458 = cvt(_T_457) node _T_459 = and(_T_458, asSInt(UInt<13>(0h1000))) node _T_460 = asSInt(_T_459) node _T_461 = eq(_T_460, asSInt(UInt<1>(0h0))) node _T_462 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_463 = cvt(_T_462) node _T_464 = and(_T_463, asSInt(UInt<17>(0h10000))) node _T_465 = asSInt(_T_464) node _T_466 = eq(_T_465, asSInt(UInt<1>(0h0))) node _T_467 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_468 = cvt(_T_467) node _T_469 = and(_T_468, asSInt(UInt<27>(0h4000000))) node _T_470 = asSInt(_T_469) node _T_471 = eq(_T_470, asSInt(UInt<1>(0h0))) node _T_472 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_473 = cvt(_T_472) node _T_474 = and(_T_473, asSInt(UInt<13>(0h1000))) node _T_475 = asSInt(_T_474) node _T_476 = eq(_T_475, asSInt(UInt<1>(0h0))) node _T_477 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_478 = cvt(_T_477) node _T_479 = and(_T_478, asSInt(UInt<29>(0h10000000))) node _T_480 = asSInt(_T_479) node _T_481 = eq(_T_480, asSInt(UInt<1>(0h0))) node _T_482 = or(_T_431, _T_436) node _T_483 = or(_T_482, _T_441) node _T_484 = or(_T_483, _T_446) node _T_485 = or(_T_484, _T_451) node _T_486 = or(_T_485, _T_456) node _T_487 = or(_T_486, _T_461) node _T_488 = or(_T_487, _T_466) node _T_489 = or(_T_488, _T_471) node _T_490 = or(_T_489, _T_476) node _T_491 = or(_T_490, _T_481) node _T_492 = and(_T_426, _T_491) node _T_493 = or(UInt<1>(0h0), _T_422) node _T_494 = or(_T_493, _T_492) node _T_495 = asUInt(reset) node _T_496 = eq(_T_495, UInt<1>(0h0)) when _T_496 : node _T_497 = eq(_T_494, UInt<1>(0h0)) when _T_497 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_494, UInt<1>(0h1), "") : assert_20 node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(is_aligned, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_504 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_504, UInt<1>(0h1), "") : assert_23 node _T_508 = eq(io.in.a.bits.mask, mask) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_508, UInt<1>(0h1), "") : assert_24 node _T_512 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_512, UInt<1>(0h1), "") : assert_25 node _T_516 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_516 : node _T_517 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_518 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_519 = and(_T_517, _T_518) node _T_520 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_521 = and(_T_519, _T_520) node _T_522 = or(UInt<1>(0h0), _T_521) node _T_523 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_524 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_525 = and(_T_523, _T_524) node _T_526 = or(UInt<1>(0h0), _T_525) node _T_527 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_528 = cvt(_T_527) node _T_529 = and(_T_528, asSInt(UInt<13>(0h1000))) node _T_530 = asSInt(_T_529) node _T_531 = eq(_T_530, asSInt(UInt<1>(0h0))) node _T_532 = and(_T_526, _T_531) node _T_533 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_534 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_535 = and(_T_533, _T_534) node _T_536 = or(UInt<1>(0h0), _T_535) node _T_537 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_538 = cvt(_T_537) node _T_539 = and(_T_538, asSInt(UInt<14>(0h2000))) node _T_540 = asSInt(_T_539) node _T_541 = eq(_T_540, asSInt(UInt<1>(0h0))) node _T_542 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_543 = cvt(_T_542) node _T_544 = and(_T_543, asSInt(UInt<11>(0h400))) node _T_545 = asSInt(_T_544) node _T_546 = eq(_T_545, asSInt(UInt<1>(0h0))) node _T_547 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_548 = cvt(_T_547) node _T_549 = and(_T_548, asSInt(UInt<9>(0h100))) node _T_550 = asSInt(_T_549) node _T_551 = eq(_T_550, asSInt(UInt<1>(0h0))) node _T_552 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_553 = cvt(_T_552) node _T_554 = and(_T_553, asSInt(UInt<18>(0h2f000))) node _T_555 = asSInt(_T_554) node _T_556 = eq(_T_555, asSInt(UInt<1>(0h0))) node _T_557 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_558 = cvt(_T_557) node _T_559 = and(_T_558, asSInt(UInt<17>(0h10000))) node _T_560 = asSInt(_T_559) node _T_561 = eq(_T_560, asSInt(UInt<1>(0h0))) node _T_562 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_563 = cvt(_T_562) node _T_564 = and(_T_563, asSInt(UInt<13>(0h1000))) node _T_565 = asSInt(_T_564) node _T_566 = eq(_T_565, asSInt(UInt<1>(0h0))) node _T_567 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_568 = cvt(_T_567) node _T_569 = and(_T_568, asSInt(UInt<17>(0h10000))) node _T_570 = asSInt(_T_569) node _T_571 = eq(_T_570, asSInt(UInt<1>(0h0))) node _T_572 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_573 = cvt(_T_572) node _T_574 = and(_T_573, asSInt(UInt<27>(0h4000000))) node _T_575 = asSInt(_T_574) node _T_576 = eq(_T_575, asSInt(UInt<1>(0h0))) node _T_577 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_578 = cvt(_T_577) node _T_579 = and(_T_578, asSInt(UInt<13>(0h1000))) node _T_580 = asSInt(_T_579) node _T_581 = eq(_T_580, asSInt(UInt<1>(0h0))) node _T_582 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_583 = cvt(_T_582) node _T_584 = and(_T_583, asSInt(UInt<29>(0h10000000))) node _T_585 = asSInt(_T_584) node _T_586 = eq(_T_585, asSInt(UInt<1>(0h0))) node _T_587 = or(_T_541, _T_546) node _T_588 = or(_T_587, _T_551) node _T_589 = or(_T_588, _T_556) node _T_590 = or(_T_589, _T_561) node _T_591 = or(_T_590, _T_566) node _T_592 = or(_T_591, _T_571) node _T_593 = or(_T_592, _T_576) node _T_594 = or(_T_593, _T_581) node _T_595 = or(_T_594, _T_586) node _T_596 = and(_T_536, _T_595) node _T_597 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_598 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_599 = cvt(_T_598) node _T_600 = and(_T_599, asSInt(UInt<17>(0h10000))) node _T_601 = asSInt(_T_600) node _T_602 = eq(_T_601, asSInt(UInt<1>(0h0))) node _T_603 = and(_T_597, _T_602) node _T_604 = or(UInt<1>(0h0), _T_532) node _T_605 = or(_T_604, _T_596) node _T_606 = or(_T_605, _T_603) node _T_607 = and(_T_522, _T_606) node _T_608 = asUInt(reset) node _T_609 = eq(_T_608, UInt<1>(0h0)) when _T_609 : node _T_610 = eq(_T_607, UInt<1>(0h0)) when _T_610 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_607, UInt<1>(0h1), "") : assert_26 node _T_611 = asUInt(reset) node _T_612 = eq(_T_611, UInt<1>(0h0)) when _T_612 : node _T_613 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_613 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(is_aligned, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_617 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_618 = asUInt(reset) node _T_619 = eq(_T_618, UInt<1>(0h0)) when _T_619 : node _T_620 = eq(_T_617, UInt<1>(0h0)) when _T_620 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_617, UInt<1>(0h1), "") : assert_29 node _T_621 = eq(io.in.a.bits.mask, mask) node _T_622 = asUInt(reset) node _T_623 = eq(_T_622, UInt<1>(0h0)) when _T_623 : node _T_624 = eq(_T_621, UInt<1>(0h0)) when _T_624 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_621, UInt<1>(0h1), "") : assert_30 node _T_625 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_625 : node _T_626 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_627 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_628 = and(_T_626, _T_627) node _T_629 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_630 = and(_T_628, _T_629) node _T_631 = or(UInt<1>(0h0), _T_630) node _T_632 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_633 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_634 = and(_T_632, _T_633) node _T_635 = or(UInt<1>(0h0), _T_634) node _T_636 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_637 = cvt(_T_636) node _T_638 = and(_T_637, asSInt(UInt<13>(0h1000))) node _T_639 = asSInt(_T_638) node _T_640 = eq(_T_639, asSInt(UInt<1>(0h0))) node _T_641 = and(_T_635, _T_640) node _T_642 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_643 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_644 = and(_T_642, _T_643) node _T_645 = or(UInt<1>(0h0), _T_644) node _T_646 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_647 = cvt(_T_646) node _T_648 = and(_T_647, asSInt(UInt<14>(0h2000))) node _T_649 = asSInt(_T_648) node _T_650 = eq(_T_649, asSInt(UInt<1>(0h0))) node _T_651 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_652 = cvt(_T_651) node _T_653 = and(_T_652, asSInt(UInt<11>(0h400))) node _T_654 = asSInt(_T_653) node _T_655 = eq(_T_654, asSInt(UInt<1>(0h0))) node _T_656 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_657 = cvt(_T_656) node _T_658 = and(_T_657, asSInt(UInt<9>(0h100))) node _T_659 = asSInt(_T_658) node _T_660 = eq(_T_659, asSInt(UInt<1>(0h0))) node _T_661 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_662 = cvt(_T_661) node _T_663 = and(_T_662, asSInt(UInt<18>(0h2f000))) node _T_664 = asSInt(_T_663) node _T_665 = eq(_T_664, asSInt(UInt<1>(0h0))) node _T_666 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_667 = cvt(_T_666) node _T_668 = and(_T_667, asSInt(UInt<17>(0h10000))) node _T_669 = asSInt(_T_668) node _T_670 = eq(_T_669, asSInt(UInt<1>(0h0))) node _T_671 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_672 = cvt(_T_671) node _T_673 = and(_T_672, asSInt(UInt<13>(0h1000))) node _T_674 = asSInt(_T_673) node _T_675 = eq(_T_674, asSInt(UInt<1>(0h0))) node _T_676 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_677 = cvt(_T_676) node _T_678 = and(_T_677, asSInt(UInt<17>(0h10000))) node _T_679 = asSInt(_T_678) node _T_680 = eq(_T_679, asSInt(UInt<1>(0h0))) node _T_681 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_682 = cvt(_T_681) node _T_683 = and(_T_682, asSInt(UInt<27>(0h4000000))) node _T_684 = asSInt(_T_683) node _T_685 = eq(_T_684, asSInt(UInt<1>(0h0))) node _T_686 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_687 = cvt(_T_686) node _T_688 = and(_T_687, asSInt(UInt<13>(0h1000))) node _T_689 = asSInt(_T_688) node _T_690 = eq(_T_689, asSInt(UInt<1>(0h0))) node _T_691 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_692 = cvt(_T_691) node _T_693 = and(_T_692, asSInt(UInt<29>(0h10000000))) node _T_694 = asSInt(_T_693) node _T_695 = eq(_T_694, asSInt(UInt<1>(0h0))) node _T_696 = or(_T_650, _T_655) node _T_697 = or(_T_696, _T_660) node _T_698 = or(_T_697, _T_665) node _T_699 = or(_T_698, _T_670) node _T_700 = or(_T_699, _T_675) node _T_701 = or(_T_700, _T_680) node _T_702 = or(_T_701, _T_685) node _T_703 = or(_T_702, _T_690) node _T_704 = or(_T_703, _T_695) node _T_705 = and(_T_645, _T_704) node _T_706 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_707 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_708 = cvt(_T_707) node _T_709 = and(_T_708, asSInt(UInt<17>(0h10000))) node _T_710 = asSInt(_T_709) node _T_711 = eq(_T_710, asSInt(UInt<1>(0h0))) node _T_712 = and(_T_706, _T_711) node _T_713 = or(UInt<1>(0h0), _T_641) node _T_714 = or(_T_713, _T_705) node _T_715 = or(_T_714, _T_712) node _T_716 = and(_T_631, _T_715) node _T_717 = asUInt(reset) node _T_718 = eq(_T_717, UInt<1>(0h0)) when _T_718 : node _T_719 = eq(_T_716, UInt<1>(0h0)) when _T_719 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_716, UInt<1>(0h1), "") : assert_31 node _T_720 = asUInt(reset) node _T_721 = eq(_T_720, UInt<1>(0h0)) when _T_721 : node _T_722 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_722 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_723 = asUInt(reset) node _T_724 = eq(_T_723, UInt<1>(0h0)) when _T_724 : node _T_725 = eq(is_aligned, UInt<1>(0h0)) when _T_725 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_726 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(_T_726, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_726, UInt<1>(0h1), "") : assert_34 node _T_730 = not(mask) node _T_731 = and(io.in.a.bits.mask, _T_730) node _T_732 = eq(_T_731, UInt<1>(0h0)) node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(_T_732, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_732, UInt<1>(0h1), "") : assert_35 node _T_736 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_736 : node _T_737 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_738 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_739 = and(_T_737, _T_738) node _T_740 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_741 = and(_T_739, _T_740) node _T_742 = or(UInt<1>(0h0), _T_741) node _T_743 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_744 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_745 = and(_T_743, _T_744) node _T_746 = or(UInt<1>(0h0), _T_745) node _T_747 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_748 = cvt(_T_747) node _T_749 = and(_T_748, asSInt(UInt<14>(0h2000))) node _T_750 = asSInt(_T_749) node _T_751 = eq(_T_750, asSInt(UInt<1>(0h0))) node _T_752 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_753 = cvt(_T_752) node _T_754 = and(_T_753, asSInt(UInt<11>(0h400))) node _T_755 = asSInt(_T_754) node _T_756 = eq(_T_755, asSInt(UInt<1>(0h0))) node _T_757 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_758 = cvt(_T_757) node _T_759 = and(_T_758, asSInt(UInt<9>(0h100))) node _T_760 = asSInt(_T_759) node _T_761 = eq(_T_760, asSInt(UInt<1>(0h0))) node _T_762 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_763 = cvt(_T_762) node _T_764 = and(_T_763, asSInt(UInt<13>(0h1000))) node _T_765 = asSInt(_T_764) node _T_766 = eq(_T_765, asSInt(UInt<1>(0h0))) node _T_767 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_768 = cvt(_T_767) node _T_769 = and(_T_768, asSInt(UInt<18>(0h2f000))) node _T_770 = asSInt(_T_769) node _T_771 = eq(_T_770, asSInt(UInt<1>(0h0))) node _T_772 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_773 = cvt(_T_772) node _T_774 = and(_T_773, asSInt(UInt<17>(0h10000))) node _T_775 = asSInt(_T_774) node _T_776 = eq(_T_775, asSInt(UInt<1>(0h0))) node _T_777 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_778 = cvt(_T_777) node _T_779 = and(_T_778, asSInt(UInt<13>(0h1000))) node _T_780 = asSInt(_T_779) node _T_781 = eq(_T_780, asSInt(UInt<1>(0h0))) node _T_782 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_783 = cvt(_T_782) node _T_784 = and(_T_783, asSInt(UInt<17>(0h10000))) node _T_785 = asSInt(_T_784) node _T_786 = eq(_T_785, asSInt(UInt<1>(0h0))) node _T_787 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_788 = cvt(_T_787) node _T_789 = and(_T_788, asSInt(UInt<27>(0h4000000))) node _T_790 = asSInt(_T_789) node _T_791 = eq(_T_790, asSInt(UInt<1>(0h0))) node _T_792 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_793 = cvt(_T_792) node _T_794 = and(_T_793, asSInt(UInt<13>(0h1000))) node _T_795 = asSInt(_T_794) node _T_796 = eq(_T_795, asSInt(UInt<1>(0h0))) node _T_797 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_798 = cvt(_T_797) node _T_799 = and(_T_798, asSInt(UInt<29>(0h10000000))) node _T_800 = asSInt(_T_799) node _T_801 = eq(_T_800, asSInt(UInt<1>(0h0))) node _T_802 = or(_T_751, _T_756) node _T_803 = or(_T_802, _T_761) node _T_804 = or(_T_803, _T_766) node _T_805 = or(_T_804, _T_771) node _T_806 = or(_T_805, _T_776) node _T_807 = or(_T_806, _T_781) node _T_808 = or(_T_807, _T_786) node _T_809 = or(_T_808, _T_791) node _T_810 = or(_T_809, _T_796) node _T_811 = or(_T_810, _T_801) node _T_812 = and(_T_746, _T_811) node _T_813 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_814 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_815 = cvt(_T_814) node _T_816 = and(_T_815, asSInt(UInt<17>(0h10000))) node _T_817 = asSInt(_T_816) node _T_818 = eq(_T_817, asSInt(UInt<1>(0h0))) node _T_819 = and(_T_813, _T_818) node _T_820 = or(UInt<1>(0h0), _T_812) node _T_821 = or(_T_820, _T_819) node _T_822 = and(_T_742, _T_821) node _T_823 = asUInt(reset) node _T_824 = eq(_T_823, UInt<1>(0h0)) when _T_824 : node _T_825 = eq(_T_822, UInt<1>(0h0)) when _T_825 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_822, UInt<1>(0h1), "") : assert_36 node _T_826 = asUInt(reset) node _T_827 = eq(_T_826, UInt<1>(0h0)) when _T_827 : node _T_828 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_828 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(is_aligned, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_832 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_833 = asUInt(reset) node _T_834 = eq(_T_833, UInt<1>(0h0)) when _T_834 : node _T_835 = eq(_T_832, UInt<1>(0h0)) when _T_835 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_832, UInt<1>(0h1), "") : assert_39 node _T_836 = eq(io.in.a.bits.mask, mask) node _T_837 = asUInt(reset) node _T_838 = eq(_T_837, UInt<1>(0h0)) when _T_838 : node _T_839 = eq(_T_836, UInt<1>(0h0)) when _T_839 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_836, UInt<1>(0h1), "") : assert_40 node _T_840 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_840 : node _T_841 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_842 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_843 = and(_T_841, _T_842) node _T_844 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_845 = and(_T_843, _T_844) node _T_846 = or(UInt<1>(0h0), _T_845) node _T_847 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_848 = leq(io.in.a.bits.size, UInt<2>(0h3)) node _T_849 = and(_T_847, _T_848) node _T_850 = or(UInt<1>(0h0), _T_849) node _T_851 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_852 = cvt(_T_851) node _T_853 = and(_T_852, asSInt(UInt<14>(0h2000))) node _T_854 = asSInt(_T_853) node _T_855 = eq(_T_854, asSInt(UInt<1>(0h0))) node _T_856 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_857 = cvt(_T_856) node _T_858 = and(_T_857, asSInt(UInt<11>(0h400))) node _T_859 = asSInt(_T_858) node _T_860 = eq(_T_859, asSInt(UInt<1>(0h0))) node _T_861 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_862 = cvt(_T_861) node _T_863 = and(_T_862, asSInt(UInt<9>(0h100))) node _T_864 = asSInt(_T_863) node _T_865 = eq(_T_864, asSInt(UInt<1>(0h0))) node _T_866 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_867 = cvt(_T_866) node _T_868 = and(_T_867, asSInt(UInt<13>(0h1000))) node _T_869 = asSInt(_T_868) node _T_870 = eq(_T_869, asSInt(UInt<1>(0h0))) node _T_871 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_872 = cvt(_T_871) node _T_873 = and(_T_872, asSInt(UInt<18>(0h2f000))) node _T_874 = asSInt(_T_873) node _T_875 = eq(_T_874, asSInt(UInt<1>(0h0))) node _T_876 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_877 = cvt(_T_876) node _T_878 = and(_T_877, asSInt(UInt<17>(0h10000))) node _T_879 = asSInt(_T_878) node _T_880 = eq(_T_879, asSInt(UInt<1>(0h0))) node _T_881 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_882 = cvt(_T_881) node _T_883 = and(_T_882, asSInt(UInt<13>(0h1000))) node _T_884 = asSInt(_T_883) node _T_885 = eq(_T_884, asSInt(UInt<1>(0h0))) node _T_886 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_887 = cvt(_T_886) node _T_888 = and(_T_887, asSInt(UInt<17>(0h10000))) node _T_889 = asSInt(_T_888) node _T_890 = eq(_T_889, asSInt(UInt<1>(0h0))) node _T_891 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_892 = cvt(_T_891) node _T_893 = and(_T_892, asSInt(UInt<27>(0h4000000))) node _T_894 = asSInt(_T_893) node _T_895 = eq(_T_894, asSInt(UInt<1>(0h0))) node _T_896 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_897 = cvt(_T_896) node _T_898 = and(_T_897, asSInt(UInt<13>(0h1000))) node _T_899 = asSInt(_T_898) node _T_900 = eq(_T_899, asSInt(UInt<1>(0h0))) node _T_901 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_902 = cvt(_T_901) node _T_903 = and(_T_902, asSInt(UInt<29>(0h10000000))) node _T_904 = asSInt(_T_903) node _T_905 = eq(_T_904, asSInt(UInt<1>(0h0))) node _T_906 = or(_T_855, _T_860) node _T_907 = or(_T_906, _T_865) node _T_908 = or(_T_907, _T_870) node _T_909 = or(_T_908, _T_875) node _T_910 = or(_T_909, _T_880) node _T_911 = or(_T_910, _T_885) node _T_912 = or(_T_911, _T_890) node _T_913 = or(_T_912, _T_895) node _T_914 = or(_T_913, _T_900) node _T_915 = or(_T_914, _T_905) node _T_916 = and(_T_850, _T_915) node _T_917 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_918 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_919 = cvt(_T_918) node _T_920 = and(_T_919, asSInt(UInt<17>(0h10000))) node _T_921 = asSInt(_T_920) node _T_922 = eq(_T_921, asSInt(UInt<1>(0h0))) node _T_923 = and(_T_917, _T_922) node _T_924 = or(UInt<1>(0h0), _T_916) node _T_925 = or(_T_924, _T_923) node _T_926 = and(_T_846, _T_925) node _T_927 = asUInt(reset) node _T_928 = eq(_T_927, UInt<1>(0h0)) when _T_928 : node _T_929 = eq(_T_926, UInt<1>(0h0)) when _T_929 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_926, UInt<1>(0h1), "") : assert_41 node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(is_aligned, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_936 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_936, UInt<1>(0h1), "") : assert_44 node _T_940 = eq(io.in.a.bits.mask, mask) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_940, UInt<1>(0h1), "") : assert_45 node _T_944 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_944 : node _T_945 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_946 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_947 = and(_T_945, _T_946) node _T_948 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_949 = and(_T_947, _T_948) node _T_950 = or(UInt<1>(0h0), _T_949) node _T_951 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_952 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_953 = and(_T_951, _T_952) node _T_954 = or(UInt<1>(0h0), _T_953) node _T_955 = xor(io.in.a.bits.address, UInt<14>(0h3000)) node _T_956 = cvt(_T_955) node _T_957 = and(_T_956, asSInt(UInt<13>(0h1000))) node _T_958 = asSInt(_T_957) node _T_959 = eq(_T_958, asSInt(UInt<1>(0h0))) node _T_960 = and(_T_954, _T_959) node _T_961 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_962 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_963 = cvt(_T_962) node _T_964 = and(_T_963, asSInt(UInt<14>(0h2000))) node _T_965 = asSInt(_T_964) node _T_966 = eq(_T_965, asSInt(UInt<1>(0h0))) node _T_967 = xor(io.in.a.bits.address, UInt<14>(0h2000)) node _T_968 = cvt(_T_967) node _T_969 = and(_T_968, asSInt(UInt<11>(0h400))) node _T_970 = asSInt(_T_969) node _T_971 = eq(_T_970, asSInt(UInt<1>(0h0))) node _T_972 = xor(io.in.a.bits.address, UInt<14>(0h2400)) node _T_973 = cvt(_T_972) node _T_974 = and(_T_973, asSInt(UInt<9>(0h100))) node _T_975 = asSInt(_T_974) node _T_976 = eq(_T_975, asSInt(UInt<1>(0h0))) node _T_977 = xor(io.in.a.bits.address, UInt<17>(0h10000)) node _T_978 = cvt(_T_977) node _T_979 = and(_T_978, asSInt(UInt<17>(0h10000))) node _T_980 = asSInt(_T_979) node _T_981 = eq(_T_980, asSInt(UInt<1>(0h0))) node _T_982 = xor(io.in.a.bits.address, UInt<21>(0h100000)) node _T_983 = cvt(_T_982) node _T_984 = and(_T_983, asSInt(UInt<18>(0h2f000))) node _T_985 = asSInt(_T_984) node _T_986 = eq(_T_985, asSInt(UInt<1>(0h0))) node _T_987 = xor(io.in.a.bits.address, UInt<26>(0h2000000)) node _T_988 = cvt(_T_987) node _T_989 = and(_T_988, asSInt(UInt<17>(0h10000))) node _T_990 = asSInt(_T_989) node _T_991 = eq(_T_990, asSInt(UInt<1>(0h0))) node _T_992 = xor(io.in.a.bits.address, UInt<26>(0h2010000)) node _T_993 = cvt(_T_992) node _T_994 = and(_T_993, asSInt(UInt<13>(0h1000))) node _T_995 = asSInt(_T_994) node _T_996 = eq(_T_995, asSInt(UInt<1>(0h0))) node _T_997 = xor(io.in.a.bits.address, UInt<28>(0hc000000)) node _T_998 = cvt(_T_997) node _T_999 = and(_T_998, asSInt(UInt<27>(0h4000000))) node _T_1000 = asSInt(_T_999) node _T_1001 = eq(_T_1000, asSInt(UInt<1>(0h0))) node _T_1002 = xor(io.in.a.bits.address, UInt<29>(0h10020000)) node _T_1003 = cvt(_T_1002) node _T_1004 = and(_T_1003, asSInt(UInt<13>(0h1000))) node _T_1005 = asSInt(_T_1004) node _T_1006 = eq(_T_1005, asSInt(UInt<1>(0h0))) node _T_1007 = or(_T_966, _T_971) node _T_1008 = or(_T_1007, _T_976) node _T_1009 = or(_T_1008, _T_981) node _T_1010 = or(_T_1009, _T_986) node _T_1011 = or(_T_1010, _T_991) node _T_1012 = or(_T_1011, _T_996) node _T_1013 = or(_T_1012, _T_1001) node _T_1014 = or(_T_1013, _T_1006) node _T_1015 = and(_T_961, _T_1014) node _T_1016 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_1017 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_1018 = and(_T_1016, _T_1017) node _T_1019 = or(UInt<1>(0h0), _T_1018) node _T_1020 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_1021 = cvt(_T_1020) node _T_1022 = and(_T_1021, asSInt(UInt<17>(0h10000))) node _T_1023 = asSInt(_T_1022) node _T_1024 = eq(_T_1023, asSInt(UInt<1>(0h0))) node _T_1025 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_1026 = cvt(_T_1025) node _T_1027 = and(_T_1026, asSInt(UInt<29>(0h10000000))) node _T_1028 = asSInt(_T_1027) node _T_1029 = eq(_T_1028, asSInt(UInt<1>(0h0))) node _T_1030 = or(_T_1024, _T_1029) node _T_1031 = and(_T_1019, _T_1030) node _T_1032 = or(UInt<1>(0h0), _T_960) node _T_1033 = or(_T_1032, _T_1015) node _T_1034 = or(_T_1033, _T_1031) node _T_1035 = and(_T_950, _T_1034) node _T_1036 = asUInt(reset) node _T_1037 = eq(_T_1036, UInt<1>(0h0)) when _T_1037 : node _T_1038 = eq(_T_1035, UInt<1>(0h0)) when _T_1038 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_1035, UInt<1>(0h1), "") : assert_46 node _T_1039 = asUInt(reset) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) when _T_1040 : node _T_1041 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_1041 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(is_aligned, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_1045 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_49 node _T_1049 = eq(io.in.a.bits.mask, mask) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_50 node _T_1053 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_1057 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1058 = asUInt(reset) node _T_1059 = eq(_T_1058, UInt<1>(0h0)) when _T_1059 : node _T_1060 = eq(_T_1057, UInt<1>(0h0)) when _T_1060 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_1057, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_1061 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_1061 : node _T_1062 = asUInt(reset) node _T_1063 = eq(_T_1062, UInt<1>(0h0)) when _T_1063 : node _T_1064 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1064 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_1065 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1066 = asUInt(reset) node _T_1067 = eq(_T_1066, UInt<1>(0h0)) when _T_1067 : node _T_1068 = eq(_T_1065, UInt<1>(0h0)) when _T_1068 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_1065, UInt<1>(0h1), "") : assert_54 node _T_1069 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1070 = asUInt(reset) node _T_1071 = eq(_T_1070, UInt<1>(0h0)) when _T_1071 : node _T_1072 = eq(_T_1069, UInt<1>(0h0)) when _T_1072 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_1069, UInt<1>(0h1), "") : assert_55 node _T_1073 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1074 = asUInt(reset) node _T_1075 = eq(_T_1074, UInt<1>(0h0)) when _T_1075 : node _T_1076 = eq(_T_1073, UInt<1>(0h0)) when _T_1076 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_1073, UInt<1>(0h1), "") : assert_56 node _T_1077 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1078 = asUInt(reset) node _T_1079 = eq(_T_1078, UInt<1>(0h0)) when _T_1079 : node _T_1080 = eq(_T_1077, UInt<1>(0h0)) when _T_1080 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_1077, UInt<1>(0h1), "") : assert_57 node _T_1081 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_1081 : node _T_1082 = asUInt(reset) node _T_1083 = eq(_T_1082, UInt<1>(0h0)) when _T_1083 : node _T_1084 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1084 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_1085 = asUInt(reset) node _T_1086 = eq(_T_1085, UInt<1>(0h0)) when _T_1086 : node _T_1087 = eq(sink_ok, UInt<1>(0h0)) when _T_1087 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_1088 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1089 = asUInt(reset) node _T_1090 = eq(_T_1089, UInt<1>(0h0)) when _T_1090 : node _T_1091 = eq(_T_1088, UInt<1>(0h0)) when _T_1091 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_1088, UInt<1>(0h1), "") : assert_60 node _T_1092 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1093 = asUInt(reset) node _T_1094 = eq(_T_1093, UInt<1>(0h0)) when _T_1094 : node _T_1095 = eq(_T_1092, UInt<1>(0h0)) when _T_1095 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_1092, UInt<1>(0h1), "") : assert_61 node _T_1096 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(_T_1096, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_1096, UInt<1>(0h1), "") : assert_62 node _T_1100 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_63 node _T_1104 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1105 = or(UInt<1>(0h1), _T_1104) node _T_1106 = asUInt(reset) node _T_1107 = eq(_T_1106, UInt<1>(0h0)) when _T_1107 : node _T_1108 = eq(_T_1105, UInt<1>(0h0)) when _T_1108 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_1105, UInt<1>(0h1), "") : assert_64 node _T_1109 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_1109 : node _T_1110 = asUInt(reset) node _T_1111 = eq(_T_1110, UInt<1>(0h0)) when _T_1111 : node _T_1112 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1112 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_1113 = asUInt(reset) node _T_1114 = eq(_T_1113, UInt<1>(0h0)) when _T_1114 : node _T_1115 = eq(sink_ok, UInt<1>(0h0)) when _T_1115 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_1116 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_67 node _T_1120 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1121 = asUInt(reset) node _T_1122 = eq(_T_1121, UInt<1>(0h0)) when _T_1122 : node _T_1123 = eq(_T_1120, UInt<1>(0h0)) when _T_1123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_1120, UInt<1>(0h1), "") : assert_68 node _T_1124 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_1125 = asUInt(reset) node _T_1126 = eq(_T_1125, UInt<1>(0h0)) when _T_1126 : node _T_1127 = eq(_T_1124, UInt<1>(0h0)) when _T_1127 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_1124, UInt<1>(0h1), "") : assert_69 node _T_1128 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1129 = or(_T_1128, io.in.d.bits.corrupt) node _T_1130 = asUInt(reset) node _T_1131 = eq(_T_1130, UInt<1>(0h0)) when _T_1131 : node _T_1132 = eq(_T_1129, UInt<1>(0h0)) when _T_1132 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_1129, UInt<1>(0h1), "") : assert_70 node _T_1133 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1134 = or(UInt<1>(0h1), _T_1133) node _T_1135 = asUInt(reset) node _T_1136 = eq(_T_1135, UInt<1>(0h0)) when _T_1136 : node _T_1137 = eq(_T_1134, UInt<1>(0h0)) when _T_1137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_1134, UInt<1>(0h1), "") : assert_71 node _T_1138 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_1138 : node _T_1139 = asUInt(reset) node _T_1140 = eq(_T_1139, UInt<1>(0h0)) when _T_1140 : node _T_1141 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_1142 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(_T_1142, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_1142, UInt<1>(0h1), "") : assert_73 node _T_1146 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_74 node _T_1150 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1151 = or(UInt<1>(0h1), _T_1150) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_75 node _T_1155 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1155 : node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_1159 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_77 node _T_1163 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1164 = or(_T_1163, io.in.d.bits.corrupt) node _T_1165 = asUInt(reset) node _T_1166 = eq(_T_1165, UInt<1>(0h0)) when _T_1166 : node _T_1167 = eq(_T_1164, UInt<1>(0h0)) when _T_1167 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1164, UInt<1>(0h1), "") : assert_78 node _T_1168 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1169 = or(UInt<1>(0h1), _T_1168) node _T_1170 = asUInt(reset) node _T_1171 = eq(_T_1170, UInt<1>(0h0)) when _T_1171 : node _T_1172 = eq(_T_1169, UInt<1>(0h0)) when _T_1172 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1169, UInt<1>(0h1), "") : assert_79 node _T_1173 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1173 : node _T_1174 = asUInt(reset) node _T_1175 = eq(_T_1174, UInt<1>(0h0)) when _T_1175 : node _T_1176 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_1176 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_1177 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1178 = asUInt(reset) node _T_1179 = eq(_T_1178, UInt<1>(0h0)) when _T_1179 : node _T_1180 = eq(_T_1177, UInt<1>(0h0)) when _T_1180 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1177, UInt<1>(0h1), "") : assert_81 node _T_1181 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1182 = asUInt(reset) node _T_1183 = eq(_T_1182, UInt<1>(0h0)) when _T_1183 : node _T_1184 = eq(_T_1181, UInt<1>(0h0)) when _T_1184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1181, UInt<1>(0h1), "") : assert_82 node _T_1185 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1186 = or(UInt<1>(0h1), _T_1185) node _T_1187 = asUInt(reset) node _T_1188 = eq(_T_1187, UInt<1>(0h0)) when _T_1188 : node _T_1189 = eq(_T_1186, UInt<1>(0h0)) when _T_1189 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1186, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_1190 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_1191 = asUInt(reset) node _T_1192 = eq(_T_1191, UInt<1>(0h0)) when _T_1192 : node _T_1193 = eq(_T_1190, UInt<1>(0h0)) when _T_1193 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1190, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_1194 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_1195 = asUInt(reset) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) when _T_1196 : node _T_1197 = eq(_T_1194, UInt<1>(0h0)) when _T_1197 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1194, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1198 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1199 = asUInt(reset) node _T_1200 = eq(_T_1199, UInt<1>(0h0)) when _T_1200 : node _T_1201 = eq(_T_1198, UInt<1>(0h0)) when _T_1201 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1198, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 11, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1202 = eq(a_first, UInt<1>(0h0)) node _T_1203 = and(io.in.a.valid, _T_1202) when _T_1203 : node _T_1204 = eq(io.in.a.bits.opcode, opcode) node _T_1205 = asUInt(reset) node _T_1206 = eq(_T_1205, UInt<1>(0h0)) when _T_1206 : node _T_1207 = eq(_T_1204, UInt<1>(0h0)) when _T_1207 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1204, UInt<1>(0h1), "") : assert_87 node _T_1208 = eq(io.in.a.bits.param, param) node _T_1209 = asUInt(reset) node _T_1210 = eq(_T_1209, UInt<1>(0h0)) when _T_1210 : node _T_1211 = eq(_T_1208, UInt<1>(0h0)) when _T_1211 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1208, UInt<1>(0h1), "") : assert_88 node _T_1212 = eq(io.in.a.bits.size, size) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_89 node _T_1216 = eq(io.in.a.bits.source, source) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_90 node _T_1220 = eq(io.in.a.bits.address, address) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_91 node _T_1224 = and(io.in.a.ready, io.in.a.valid) node _T_1225 = and(_T_1224, a_first) when _T_1225 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 11, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1226 = eq(d_first, UInt<1>(0h0)) node _T_1227 = and(io.in.d.valid, _T_1226) when _T_1227 : node _T_1228 = eq(io.in.d.bits.opcode, opcode_1) node _T_1229 = asUInt(reset) node _T_1230 = eq(_T_1229, UInt<1>(0h0)) when _T_1230 : node _T_1231 = eq(_T_1228, UInt<1>(0h0)) when _T_1231 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1228, UInt<1>(0h1), "") : assert_92 node _T_1232 = eq(io.in.d.bits.param, param_1) node _T_1233 = asUInt(reset) node _T_1234 = eq(_T_1233, UInt<1>(0h0)) when _T_1234 : node _T_1235 = eq(_T_1232, UInt<1>(0h0)) when _T_1235 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1232, UInt<1>(0h1), "") : assert_93 node _T_1236 = eq(io.in.d.bits.size, size_1) node _T_1237 = asUInt(reset) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) when _T_1238 : node _T_1239 = eq(_T_1236, UInt<1>(0h0)) when _T_1239 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1236, UInt<1>(0h1), "") : assert_94 node _T_1240 = eq(io.in.d.bits.source, source_1) node _T_1241 = asUInt(reset) node _T_1242 = eq(_T_1241, UInt<1>(0h0)) when _T_1242 : node _T_1243 = eq(_T_1240, UInt<1>(0h0)) when _T_1243 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1240, UInt<1>(0h1), "") : assert_95 node _T_1244 = eq(io.in.d.bits.sink, sink) node _T_1245 = asUInt(reset) node _T_1246 = eq(_T_1245, UInt<1>(0h0)) when _T_1246 : node _T_1247 = eq(_T_1244, UInt<1>(0h0)) when _T_1247 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1244, UInt<1>(0h1), "") : assert_96 node _T_1248 = eq(io.in.d.bits.denied, denied) node _T_1249 = asUInt(reset) node _T_1250 = eq(_T_1249, UInt<1>(0h0)) when _T_1250 : node _T_1251 = eq(_T_1248, UInt<1>(0h0)) when _T_1251 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1248, UInt<1>(0h1), "") : assert_97 node _T_1252 = and(io.in.d.ready, io.in.d.valid) node _T_1253 = and(_T_1252, d_first) when _T_1253 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<8>, clock, reset, UInt<8>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 11, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 11, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<8> connect a_sizes_set, UInt<8>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<8> connect a_size_lookup, UInt<8>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<5> connect a_sizes_set_interm, UInt<5>(0h0) node _T_1254 = and(io.in.a.valid, a_first_1) node _T_1255 = and(_T_1254, UInt<1>(0h1)) when _T_1255 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1256 = and(io.in.a.ready, io.in.a.valid) node _T_1257 = and(_T_1256, a_first_1) node _T_1258 = and(_T_1257, UInt<1>(0h1)) when _T_1258 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h3)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1259 = dshr(inflight, io.in.a.bits.source) node _T_1260 = bits(_T_1259, 0, 0) node _T_1261 = eq(_T_1260, UInt<1>(0h0)) node _T_1262 = asUInt(reset) node _T_1263 = eq(_T_1262, UInt<1>(0h0)) when _T_1263 : node _T_1264 = eq(_T_1261, UInt<1>(0h0)) when _T_1264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1261, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<8> connect d_sizes_clr, UInt<8>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1265 = and(io.in.d.valid, d_first_1) node _T_1266 = and(_T_1265, UInt<1>(0h1)) node _T_1267 = eq(d_release_ack, UInt<1>(0h0)) node _T_1268 = and(_T_1266, _T_1267) when _T_1268 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1269 = and(io.in.d.ready, io.in.d.valid) node _T_1270 = and(_T_1269, d_first_1) node _T_1271 = and(_T_1270, UInt<1>(0h1)) node _T_1272 = eq(d_release_ack, UInt<1>(0h0)) node _T_1273 = and(_T_1271, _T_1272) when _T_1273 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1274 = and(io.in.d.valid, d_first_1) node _T_1275 = and(_T_1274, UInt<1>(0h1)) node _T_1276 = eq(d_release_ack, UInt<1>(0h0)) node _T_1277 = and(_T_1275, _T_1276) when _T_1277 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1278 = dshr(inflight, io.in.d.bits.source) node _T_1279 = bits(_T_1278, 0, 0) node _T_1280 = or(_T_1279, same_cycle_resp) node _T_1281 = asUInt(reset) node _T_1282 = eq(_T_1281, UInt<1>(0h0)) when _T_1282 : node _T_1283 = eq(_T_1280, UInt<1>(0h0)) when _T_1283 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1280, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1284 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1285 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1286 = or(_T_1284, _T_1285) node _T_1287 = asUInt(reset) node _T_1288 = eq(_T_1287, UInt<1>(0h0)) when _T_1288 : node _T_1289 = eq(_T_1286, UInt<1>(0h0)) when _T_1289 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1286, UInt<1>(0h1), "") : assert_100 node _T_1290 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1291 = asUInt(reset) node _T_1292 = eq(_T_1291, UInt<1>(0h0)) when _T_1292 : node _T_1293 = eq(_T_1290, UInt<1>(0h0)) when _T_1293 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1290, UInt<1>(0h1), "") : assert_101 else : node _T_1294 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1295 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1296 = or(_T_1294, _T_1295) node _T_1297 = asUInt(reset) node _T_1298 = eq(_T_1297, UInt<1>(0h0)) when _T_1298 : node _T_1299 = eq(_T_1296, UInt<1>(0h0)) when _T_1299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1296, UInt<1>(0h1), "") : assert_102 node _T_1300 = eq(io.in.d.bits.size, a_size_lookup) node _T_1301 = asUInt(reset) node _T_1302 = eq(_T_1301, UInt<1>(0h0)) when _T_1302 : node _T_1303 = eq(_T_1300, UInt<1>(0h0)) when _T_1303 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1300, UInt<1>(0h1), "") : assert_103 node _T_1304 = and(io.in.d.valid, d_first_1) node _T_1305 = and(_T_1304, a_first_1) node _T_1306 = and(_T_1305, io.in.a.valid) node _T_1307 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1308 = and(_T_1306, _T_1307) node _T_1309 = eq(d_release_ack, UInt<1>(0h0)) node _T_1310 = and(_T_1308, _T_1309) when _T_1310 : node _T_1311 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1312 = or(_T_1311, io.in.a.ready) node _T_1313 = asUInt(reset) node _T_1314 = eq(_T_1313, UInt<1>(0h0)) when _T_1314 : node _T_1315 = eq(_T_1312, UInt<1>(0h0)) when _T_1315 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1312, UInt<1>(0h1), "") : assert_104 node _T_1316 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1317 = orr(a_set_wo_ready) node _T_1318 = eq(_T_1317, UInt<1>(0h0)) node _T_1319 = or(_T_1316, _T_1318) node _T_1320 = asUInt(reset) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) when _T_1321 : node _T_1322 = eq(_T_1319, UInt<1>(0h0)) when _T_1322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_105 assert(clock, _T_1319, UInt<1>(0h1), "") : assert_105 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_155 node _T_1323 = orr(inflight) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) node _T_1325 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1326 = or(_T_1324, _T_1325) node _T_1327 = lt(watchdog, plusarg_reader.out) node _T_1328 = or(_T_1326, _T_1327) node _T_1329 = asUInt(reset) node _T_1330 = eq(_T_1329, UInt<1>(0h0)) when _T_1330 : node _T_1331 = eq(_T_1328, UInt<1>(0h0)) when _T_1331 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1328, UInt<1>(0h1), "") : assert_106 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1332 = and(io.in.a.ready, io.in.a.valid) node _T_1333 = and(io.in.d.ready, io.in.d.valid) node _T_1334 = or(_T_1332, _T_1333) when _T_1334 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<8>, clock, reset, UInt<8>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<32>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<4>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<32>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<4>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<12>(0hfff), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 11, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<9>, clock, reset, UInt<9>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<12>(0hfff), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 11, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<9>, clock, reset, UInt<9>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<8> connect c_sizes_set, UInt<8>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<8> connect c_size_lookup, UInt<8>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<5> connect c_sizes_set_interm, UInt<5>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1335 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1336 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_1337 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_1338 = and(_T_1336, _T_1337) node _T_1339 = and(_T_1335, _T_1338) when _T_1339 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<4>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<32>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<4>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1340 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_1341 = and(_T_1340, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<32>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<4>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1342 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1343 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1344 = and(_T_1342, _T_1343) node _T_1345 = and(_T_1341, _T_1344) when _T_1345 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<32>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<4>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<4>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h3)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<32>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<4>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1346 = dshr(inflight_1, _WIRE_15.bits.source) node _T_1347 = bits(_T_1346, 0, 0) node _T_1348 = eq(_T_1347, UInt<1>(0h0)) node _T_1349 = asUInt(reset) node _T_1350 = eq(_T_1349, UInt<1>(0h0)) when _T_1350 : node _T_1351 = eq(_T_1348, UInt<1>(0h0)) when _T_1351 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, _T_1348, UInt<1>(0h1), "") : assert_107 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<4>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<8> connect d_sizes_clr_1, UInt<8>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1352 = and(io.in.d.valid, d_first_2) node _T_1353 = and(_T_1352, UInt<1>(0h1)) node _T_1354 = and(_T_1353, d_release_ack_1) when _T_1354 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1355 = and(io.in.d.ready, io.in.d.valid) node _T_1356 = and(_T_1355, d_first_2) node _T_1357 = and(_T_1356, UInt<1>(0h1)) node _T_1358 = and(_T_1357, d_release_ack_1) when _T_1358 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h3)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h3)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1359 = and(io.in.d.valid, d_first_2) node _T_1360 = and(_T_1359, UInt<1>(0h1)) node _T_1361 = and(_T_1360, d_release_ack_1) when _T_1361 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<4>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1362 = dshr(inflight_1, io.in.d.bits.source) node _T_1363 = bits(_T_1362, 0, 0) node _T_1364 = or(_T_1363, same_cycle_resp_1) node _T_1365 = asUInt(reset) node _T_1366 = eq(_T_1365, UInt<1>(0h0)) when _T_1366 : node _T_1367 = eq(_T_1364, UInt<1>(0h0)) when _T_1367 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1364, UInt<1>(0h1), "") : assert_108 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<32>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<4>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1368 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_1369 = asUInt(reset) node _T_1370 = eq(_T_1369, UInt<1>(0h0)) when _T_1370 : node _T_1371 = eq(_T_1368, UInt<1>(0h0)) when _T_1371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1368, UInt<1>(0h1), "") : assert_109 else : node _T_1372 = eq(io.in.d.bits.size, c_size_lookup) node _T_1373 = asUInt(reset) node _T_1374 = eq(_T_1373, UInt<1>(0h0)) when _T_1374 : node _T_1375 = eq(_T_1372, UInt<1>(0h0)) when _T_1375 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1372, UInt<1>(0h1), "") : assert_110 node _T_1376 = and(io.in.d.valid, d_first_2) node _T_1377 = and(_T_1376, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<32>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<4>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1378 = and(_T_1377, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<32>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<4>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1379 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_1380 = and(_T_1378, _T_1379) node _T_1381 = and(_T_1380, d_release_ack_1) node _T_1382 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1383 = and(_T_1381, _T_1382) when _T_1383 : node _T_1384 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<32>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<4>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1385 = or(_T_1384, _WIRE_23.ready) node _T_1386 = asUInt(reset) node _T_1387 = eq(_T_1386, UInt<1>(0h0)) when _T_1387 : node _T_1388 = eq(_T_1385, UInt<1>(0h0)) when _T_1388 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_111 assert(clock, _T_1385, UInt<1>(0h1), "") : assert_111 node _T_1389 = orr(c_set_wo_ready) when _T_1389 : node _T_1390 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1391 = asUInt(reset) node _T_1392 = eq(_T_1391, UInt<1>(0h0)) when _T_1392 : node _T_1393 = eq(_T_1390, UInt<1>(0h0)) when _T_1393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:52 assert(cond, message)\n") : printf_112 assert(clock, _T_1390, UInt<1>(0h1), "") : assert_112 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_156 node _T_1394 = orr(inflight_1) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) node _T_1396 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1397 = or(_T_1395, _T_1396) node _T_1398 = lt(watchdog_1, plusarg_reader_1.out) node _T_1399 = or(_T_1397, _T_1398) node _T_1400 = asUInt(reset) node _T_1401 = eq(_T_1400, UInt<1>(0h0)) when _T_1401 : node _T_1402 = eq(_T_1399, UInt<1>(0h0)) when _T_1402 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/testchipip/src/main/scala/tsi/TSIHarness.scala:77:45)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, _T_1399, UInt<1>(0h1), "") : assert_113 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<32>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<4>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1403 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_1404 = and(io.in.d.ready, io.in.d.valid) node _T_1405 = or(_T_1403, _T_1404) when _T_1405 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_74( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire [26:0] _GEN = {23'h0, io_in_a_bits_size}; // @[package.scala:243:71] wire _a_first_T_1 = io_in_a_ready & io_in_a_valid; // @[Decoupled.scala:51:35] reg [8:0] a_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [3:0] size; // @[Monitor.scala:389:22] reg [31:0] address; // @[Monitor.scala:391:22] reg [8:0] d_first_counter; // @[Edges.scala:229:27] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [3:0] size_1; // @[Monitor.scala:540:22] reg source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [7:0] inflight_sizes; // @[Monitor.scala:618:33] reg [8:0] a_first_counter_1; // @[Edges.scala:229:27] wire a_first_1 = a_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [8:0] d_first_counter_1; // @[Edges.scala:229:27] wire d_first_1 = d_first_counter_1 == 9'h0; // @[Edges.scala:229:27, :231:25] wire a_set = _a_first_T_1 & a_first_1; // @[Decoupled.scala:51:35] wire d_release_ack = io_in_d_bits_opcode == 3'h6; // @[Monitor.scala:36:7, :673:46] wire _GEN_0 = io_in_d_bits_opcode != 3'h6; // @[Monitor.scala:36:7, :673:46, :674:74] reg [31:0] watchdog; // @[Monitor.scala:709:27] reg [1:0] inflight_1; // @[Monitor.scala:726:35] reg [7:0] inflight_sizes_1; // @[Monitor.scala:728:35] reg [8:0] d_first_counter_2; // @[Edges.scala:229:27] wire d_first_2 = d_first_counter_2 == 9'h0; // @[Edges.scala:229:27, :231:25] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module TLBuffer_a32d64s4k5z4u : input clock : Clock input reset : Reset output auto : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} wire nodeIn : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeIn.d.bits.corrupt invalidate nodeIn.d.bits.data invalidate nodeIn.d.bits.denied invalidate nodeIn.d.bits.sink invalidate nodeIn.d.bits.source invalidate nodeIn.d.bits.size invalidate nodeIn.d.bits.param invalidate nodeIn.d.bits.opcode invalidate nodeIn.d.valid invalidate nodeIn.d.ready invalidate nodeIn.a.bits.corrupt invalidate nodeIn.a.bits.data invalidate nodeIn.a.bits.mask invalidate nodeIn.a.bits.address invalidate nodeIn.a.bits.source invalidate nodeIn.a.bits.size invalidate nodeIn.a.bits.param invalidate nodeIn.a.bits.opcode invalidate nodeIn.a.valid invalidate nodeIn.a.ready inst monitor of TLMonitor_16 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, nodeIn.d.bits.corrupt connect monitor.io.in.d.bits.data, nodeIn.d.bits.data connect monitor.io.in.d.bits.denied, nodeIn.d.bits.denied connect monitor.io.in.d.bits.sink, nodeIn.d.bits.sink connect monitor.io.in.d.bits.source, nodeIn.d.bits.source connect monitor.io.in.d.bits.size, nodeIn.d.bits.size connect monitor.io.in.d.bits.param, nodeIn.d.bits.param connect monitor.io.in.d.bits.opcode, nodeIn.d.bits.opcode connect monitor.io.in.d.valid, nodeIn.d.valid connect monitor.io.in.d.ready, nodeIn.d.ready connect monitor.io.in.a.bits.corrupt, nodeIn.a.bits.corrupt connect monitor.io.in.a.bits.data, nodeIn.a.bits.data connect monitor.io.in.a.bits.mask, nodeIn.a.bits.mask connect monitor.io.in.a.bits.address, nodeIn.a.bits.address connect monitor.io.in.a.bits.source, nodeIn.a.bits.source connect monitor.io.in.a.bits.size, nodeIn.a.bits.size connect monitor.io.in.a.bits.param, nodeIn.a.bits.param connect monitor.io.in.a.bits.opcode, nodeIn.a.bits.opcode connect monitor.io.in.a.valid, nodeIn.a.valid connect monitor.io.in.a.ready, nodeIn.a.ready wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, sink : UInt<5>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut connect nodeIn, auto.in inst nodeOut_a_q of Queue2_TLBundleA_a32d64s4k5z4u connect nodeOut_a_q.clock, clock connect nodeOut_a_q.reset, reset connect nodeOut_a_q.io.enq.valid, nodeIn.a.valid connect nodeOut_a_q.io.enq.bits.corrupt, nodeIn.a.bits.corrupt connect nodeOut_a_q.io.enq.bits.data, nodeIn.a.bits.data connect nodeOut_a_q.io.enq.bits.mask, nodeIn.a.bits.mask connect nodeOut_a_q.io.enq.bits.address, nodeIn.a.bits.address connect nodeOut_a_q.io.enq.bits.source, nodeIn.a.bits.source connect nodeOut_a_q.io.enq.bits.size, nodeIn.a.bits.size connect nodeOut_a_q.io.enq.bits.param, nodeIn.a.bits.param connect nodeOut_a_q.io.enq.bits.opcode, nodeIn.a.bits.opcode connect nodeIn.a.ready, nodeOut_a_q.io.enq.ready connect nodeOut.a.bits, nodeOut_a_q.io.deq.bits connect nodeOut.a.valid, nodeOut_a_q.io.deq.valid connect nodeOut_a_q.io.deq.ready, nodeOut.a.ready inst nodeIn_d_q of Queue2_TLBundleD_a32d64s4k5z4u connect nodeIn_d_q.clock, clock connect nodeIn_d_q.reset, reset connect nodeIn_d_q.io.enq.valid, nodeOut.d.valid connect nodeIn_d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect nodeIn_d_q.io.enq.bits.data, nodeOut.d.bits.data connect nodeIn_d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect nodeIn_d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect nodeIn_d_q.io.enq.bits.source, nodeOut.d.bits.source connect nodeIn_d_q.io.enq.bits.size, nodeOut.d.bits.size connect nodeIn_d_q.io.enq.bits.param, nodeOut.d.bits.param connect nodeIn_d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, nodeIn_d_q.io.enq.ready connect nodeIn.d.bits, nodeIn_d_q.io.deq.bits connect nodeIn.d.valid, nodeIn_d_q.io.deq.valid connect nodeIn_d_q.io.deq.ready, nodeIn.d.ready wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<4>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<4>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_4.bits.sink, UInt<5>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.mask, UInt<8>(0h0) connect _WIRE_6.bits.address, UInt<32>(0h0) connect _WIRE_6.bits.source, UInt<4>(0h0) connect _WIRE_6.bits.size, UInt<4>(0h0) connect _WIRE_6.bits.param, UInt<2>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready connect _WIRE_7.ready, UInt<1>(0h1) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<64>(0h0) connect _WIRE_8.bits.address, UInt<32>(0h0) connect _WIRE_8.bits.source, UInt<4>(0h0) connect _WIRE_8.bits.size, UInt<4>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready connect _WIRE_9.valid, UInt<1>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_10.bits.sink, UInt<5>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<5>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready connect _WIRE_11.valid, UInt<1>(0h0)
module TLBuffer_a32d64s4k5z4u( // @[Buffer.scala:40:9] input clock, // @[Buffer.scala:40:9] input reset, // @[Buffer.scala:40:9] output auto_in_a_ready, // @[LazyModuleImp.scala:107:25] input auto_in_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_in_a_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_in_a_bits_source, // @[LazyModuleImp.scala:107:25] input [31:0] auto_in_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_in_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_in_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_in_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_in_d_ready, // @[LazyModuleImp.scala:107:25] output auto_in_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_in_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_in_d_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_in_d_bits_source, // @[LazyModuleImp.scala:107:25] output [4:0] auto_in_d_bits_sink, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_denied, // @[LazyModuleImp.scala:107:25] output [63:0] auto_in_d_bits_data, // @[LazyModuleImp.scala:107:25] output auto_in_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_param, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_source, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_mask, // @[LazyModuleImp.scala:107:25] output [63:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_source, // @[LazyModuleImp.scala:107:25] input [4:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [63:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt // @[LazyModuleImp.scala:107:25] ); wire _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire [2:0] _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] wire [1:0] _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] wire [3:0] _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] wire [4:0] _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] wire _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] TLMonitor_16 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (_nodeOut_a_q_io_enq_ready), // @[Decoupled.scala:362:21] .io_in_a_valid (auto_in_a_valid), .io_in_a_bits_opcode (auto_in_a_bits_opcode), .io_in_a_bits_param (auto_in_a_bits_param), .io_in_a_bits_size (auto_in_a_bits_size), .io_in_a_bits_source (auto_in_a_bits_source), .io_in_a_bits_address (auto_in_a_bits_address), .io_in_a_bits_mask (auto_in_a_bits_mask), .io_in_a_bits_corrupt (auto_in_a_bits_corrupt), .io_in_d_ready (auto_in_d_ready), .io_in_d_valid (_nodeIn_d_q_io_deq_valid), // @[Decoupled.scala:362:21] .io_in_d_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), // @[Decoupled.scala:362:21] .io_in_d_bits_param (_nodeIn_d_q_io_deq_bits_param), // @[Decoupled.scala:362:21] .io_in_d_bits_size (_nodeIn_d_q_io_deq_bits_size), // @[Decoupled.scala:362:21] .io_in_d_bits_source (_nodeIn_d_q_io_deq_bits_source), // @[Decoupled.scala:362:21] .io_in_d_bits_sink (_nodeIn_d_q_io_deq_bits_sink), // @[Decoupled.scala:362:21] .io_in_d_bits_denied (_nodeIn_d_q_io_deq_bits_denied), // @[Decoupled.scala:362:21] .io_in_d_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) // @[Decoupled.scala:362:21] ); // @[Nodes.scala:27:25] Queue2_TLBundleA_a32d64s4k5z4u nodeOut_a_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (_nodeOut_a_q_io_enq_ready), .io_enq_valid (auto_in_a_valid), .io_enq_bits_opcode (auto_in_a_bits_opcode), .io_enq_bits_param (auto_in_a_bits_param), .io_enq_bits_size (auto_in_a_bits_size), .io_enq_bits_source (auto_in_a_bits_source), .io_enq_bits_address (auto_in_a_bits_address), .io_enq_bits_mask (auto_in_a_bits_mask), .io_enq_bits_data (auto_in_a_bits_data), .io_enq_bits_corrupt (auto_in_a_bits_corrupt), .io_deq_ready (auto_out_a_ready), .io_deq_valid (auto_out_a_valid), .io_deq_bits_opcode (auto_out_a_bits_opcode), .io_deq_bits_param (auto_out_a_bits_param), .io_deq_bits_size (auto_out_a_bits_size), .io_deq_bits_source (auto_out_a_bits_source), .io_deq_bits_address (auto_out_a_bits_address), .io_deq_bits_mask (auto_out_a_bits_mask), .io_deq_bits_data (auto_out_a_bits_data), .io_deq_bits_corrupt (auto_out_a_bits_corrupt) ); // @[Decoupled.scala:362:21] Queue2_TLBundleD_a32d64s4k5z4u nodeIn_d_q ( // @[Decoupled.scala:362:21] .clock (clock), .reset (reset), .io_enq_ready (auto_out_d_ready), .io_enq_valid (auto_out_d_valid), .io_enq_bits_opcode (auto_out_d_bits_opcode), .io_enq_bits_param (auto_out_d_bits_param), .io_enq_bits_size (auto_out_d_bits_size), .io_enq_bits_source (auto_out_d_bits_source), .io_enq_bits_sink (auto_out_d_bits_sink), .io_enq_bits_denied (auto_out_d_bits_denied), .io_enq_bits_data (auto_out_d_bits_data), .io_enq_bits_corrupt (auto_out_d_bits_corrupt), .io_deq_ready (auto_in_d_ready), .io_deq_valid (_nodeIn_d_q_io_deq_valid), .io_deq_bits_opcode (_nodeIn_d_q_io_deq_bits_opcode), .io_deq_bits_param (_nodeIn_d_q_io_deq_bits_param), .io_deq_bits_size (_nodeIn_d_q_io_deq_bits_size), .io_deq_bits_source (_nodeIn_d_q_io_deq_bits_source), .io_deq_bits_sink (_nodeIn_d_q_io_deq_bits_sink), .io_deq_bits_denied (_nodeIn_d_q_io_deq_bits_denied), .io_deq_bits_data (auto_in_d_bits_data), .io_deq_bits_corrupt (_nodeIn_d_q_io_deq_bits_corrupt) ); // @[Decoupled.scala:362:21] assign auto_in_a_ready = _nodeOut_a_q_io_enq_ready; // @[Decoupled.scala:362:21] assign auto_in_d_valid = _nodeIn_d_q_io_deq_valid; // @[Decoupled.scala:362:21] assign auto_in_d_bits_opcode = _nodeIn_d_q_io_deq_bits_opcode; // @[Decoupled.scala:362:21] assign auto_in_d_bits_param = _nodeIn_d_q_io_deq_bits_param; // @[Decoupled.scala:362:21] assign auto_in_d_bits_size = _nodeIn_d_q_io_deq_bits_size; // @[Decoupled.scala:362:21] assign auto_in_d_bits_source = _nodeIn_d_q_io_deq_bits_source; // @[Decoupled.scala:362:21] assign auto_in_d_bits_sink = _nodeIn_d_q_io_deq_bits_sink; // @[Decoupled.scala:362:21] assign auto_in_d_bits_denied = _nodeIn_d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] assign auto_in_d_bits_corrupt = _nodeIn_d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] endmodule
Generate the Verilog code corresponding to this FIRRTL code module GenericDeserializer_TLBeatw87_f32 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { flit : UInt<32>}}, out : { flip ready : UInt<1>, valid : UInt<1>, bits : { payload : UInt<85>, head : UInt<1>, tail : UInt<1>}}, busy : UInt<1>} reg data : UInt<32>[2], clock regreset beat : UInt<2>, clock, reset, UInt<2>(0h0) node _io_in_ready_T = neq(beat, UInt<2>(0h2)) node _io_in_ready_T_1 = or(io.out.ready, _io_in_ready_T) connect io.in.ready, _io_in_ready_T_1 node _io_out_valid_T = eq(beat, UInt<2>(0h2)) node _io_out_valid_T_1 = and(io.in.valid, _io_out_valid_T) connect io.out.valid, _io_out_valid_T_1 node _io_out_bits_T = cat(data[1], data[0]) node _io_out_bits_T_1 = cat(io.in.bits.flit, _io_out_bits_T) wire _io_out_bits_WIRE : { payload : UInt<85>, head : UInt<1>, tail : UInt<1>} wire _io_out_bits_WIRE_1 : UInt<87> connect _io_out_bits_WIRE_1, _io_out_bits_T_1 node _io_out_bits_T_2 = bits(_io_out_bits_WIRE_1, 0, 0) connect _io_out_bits_WIRE.tail, _io_out_bits_T_2 node _io_out_bits_T_3 = bits(_io_out_bits_WIRE_1, 1, 1) connect _io_out_bits_WIRE.head, _io_out_bits_T_3 node _io_out_bits_T_4 = bits(_io_out_bits_WIRE_1, 86, 2) connect _io_out_bits_WIRE.payload, _io_out_bits_T_4 connect io.out.bits, _io_out_bits_WIRE node _T = and(io.in.ready, io.in.valid) when _T : node _beat_T = eq(beat, UInt<2>(0h2)) node _beat_T_1 = add(beat, UInt<1>(0h1)) node _beat_T_2 = tail(_beat_T_1, 1) node _beat_T_3 = mux(_beat_T, UInt<1>(0h0), _beat_T_2) connect beat, _beat_T_3 node _T_1 = neq(beat, UInt<2>(0h2)) when _T_1 : node _T_2 = bits(beat, 0, 0) connect data[_T_2], io.in.bits.flit node _io_busy_T = neq(beat, UInt<1>(0h0)) connect io.busy, _io_busy_T
module GenericDeserializer_TLBeatw87_f32( // @[Serdes.scala:37:7] input clock, // @[Serdes.scala:37:7] input reset, // @[Serdes.scala:37:7] output io_in_ready, // @[Serdes.scala:39:14] input io_in_valid, // @[Serdes.scala:39:14] input [31:0] io_in_bits_flit, // @[Serdes.scala:39:14] input io_out_ready, // @[Serdes.scala:39:14] output io_out_valid, // @[Serdes.scala:39:14] output io_out_bits_head, // @[Serdes.scala:39:14] output io_out_bits_tail // @[Serdes.scala:39:14] ); reg [31:0] data_0; // @[Serdes.scala:48:17] reg [31:0] data_1; // @[Serdes.scala:48:17] reg [1:0] beat; // @[Serdes.scala:49:21] wire io_in_ready_0 = io_out_ready | beat != 2'h2; // @[Serdes.scala:37:7, :49:21, :51:{31,39}] wire _beat_T = beat == 2'h2; // @[Serdes.scala:37:7, :49:21, :52:39] wire _GEN = io_in_ready_0 & io_in_valid; // @[Decoupled.scala:51:35] wire _GEN_0 = beat == 2'h2; // @[Serdes.scala:37:7, :48:17, :49:21, :51:39, :62:39, :63:47] always @(posedge clock) begin // @[Serdes.scala:37:7] if (~_GEN | _GEN_0 | beat[0]) begin // @[Decoupled.scala:51:35] end else // @[Serdes.scala:48:17, :51:39, :59:21, :62:39, :63:47] data_0 <= io_in_bits_flit; // @[Serdes.scala:48:17] if (~_GEN | _GEN_0 | ~(beat[0])) begin // @[Decoupled.scala:51:35] end else // @[Serdes.scala:48:17, :51:39, :59:21, :62:39, :63:47] data_1 <= io_in_bits_flit; // @[Serdes.scala:48:17] if (reset) // @[Serdes.scala:37:7] beat <= 2'h0; // @[Serdes.scala:37:7, :49:21] else if (_GEN) // @[Decoupled.scala:51:35] beat <= _beat_T ? 2'h0 : beat + 2'h1; // @[Serdes.scala:37:7, :49:21, :52:39, :60:{16,53}] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_56 : input clock : Clock input reset : Reset output io : { req : { flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<2>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}}, resp : { `2` : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, `1` : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}, `0` : { vc_sel : { `2` : UInt<1>[10], `1` : UInt<1>[10], `0` : UInt<1>[10]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<20> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<30> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_plaInput, 19, 19) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2, decoded_andMatrixOutputs_andMatrixInput_3) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T) node _decoded_orMatrixOutputs_T = orr(decoded_andMatrixOutputs_0_2) node decoded_orMatrixOutputs_lo_lo_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_orMatrixOutputs_lo_lo_hi_hi, decoded_orMatrixOutputs_lo_lo_hi_lo) node decoded_orMatrixOutputs_lo_lo = cat(decoded_orMatrixOutputs_lo_lo_hi, decoded_orMatrixOutputs_lo_lo_lo) node decoded_orMatrixOutputs_lo_hi_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_hi = cat(_decoded_orMatrixOutputs_T, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_orMatrixOutputs_lo_hi_lo_hi, decoded_orMatrixOutputs_lo_hi_lo_lo) node decoded_orMatrixOutputs_lo_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_orMatrixOutputs_lo_hi_hi_lo) node decoded_orMatrixOutputs_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_hi, decoded_orMatrixOutputs_lo_hi_lo) node decoded_orMatrixOutputs_lo = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_orMatrixOutputs_hi_lo_lo_hi, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_orMatrixOutputs_hi_lo_hi_hi, decoded_orMatrixOutputs_hi_lo_hi_lo) node decoded_orMatrixOutputs_hi_lo = cat(decoded_orMatrixOutputs_hi_lo_hi, decoded_orMatrixOutputs_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_lo_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_lo_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_orMatrixOutputs_hi_hi_lo_hi, decoded_orMatrixOutputs_hi_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_hi_lo = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_hi = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_hi_lo) node decoded_orMatrixOutputs_hi_hi = cat(decoded_orMatrixOutputs_hi_hi_hi, decoded_orMatrixOutputs_hi_hi_lo) node decoded_orMatrixOutputs_hi = cat(decoded_orMatrixOutputs_hi_hi, decoded_orMatrixOutputs_hi_lo) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi, decoded_orMatrixOutputs_lo) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs, 9, 9) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs, 10, 10) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs, 11, 11) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs, 12, 12) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs, 13, 13) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs, 14, 14) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs, 15, 15) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs, 16, 16) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs, 17, 17) node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs, 18, 18) node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs, 19, 19) node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs, 20, 20) node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs, 21, 21) node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs, 22, 22) node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs, 23, 23) node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs, 24, 24) node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs, 25, 25) node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs, 26, 26) node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs, 27, 27) node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs, 28, 28) node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs, 29, 29) node decoded_invMatrixOutputs_lo_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_2, _decoded_invMatrixOutputs_T_1) node decoded_invMatrixOutputs_lo_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_lo_hi, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_lo_hi_lo = cat(_decoded_invMatrixOutputs_T_4, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs_lo_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_6, _decoded_invMatrixOutputs_T_5) node decoded_invMatrixOutputs_lo_lo_hi = cat(decoded_invMatrixOutputs_lo_lo_hi_hi, decoded_invMatrixOutputs_lo_lo_hi_lo) node decoded_invMatrixOutputs_lo_lo = cat(decoded_invMatrixOutputs_lo_lo_hi, decoded_invMatrixOutputs_lo_lo_lo) node decoded_invMatrixOutputs_lo_hi_lo_lo = cat(_decoded_invMatrixOutputs_T_8, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_lo_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_10, _decoded_invMatrixOutputs_T_9) node decoded_invMatrixOutputs_lo_hi_lo = cat(decoded_invMatrixOutputs_lo_hi_lo_hi, decoded_invMatrixOutputs_lo_hi_lo_lo) node decoded_invMatrixOutputs_lo_hi_hi_lo = cat(_decoded_invMatrixOutputs_T_12, _decoded_invMatrixOutputs_T_11) node decoded_invMatrixOutputs_lo_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_lo_hi_hi = cat(decoded_invMatrixOutputs_lo_hi_hi_hi, decoded_invMatrixOutputs_lo_hi_hi_lo) node decoded_invMatrixOutputs_lo_hi = cat(decoded_invMatrixOutputs_lo_hi_hi, decoded_invMatrixOutputs_lo_hi_lo) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo_lo_hi = cat(_decoded_invMatrixOutputs_T_17, _decoded_invMatrixOutputs_T_16) node decoded_invMatrixOutputs_hi_lo_lo = cat(decoded_invMatrixOutputs_hi_lo_lo_hi, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_lo_hi_lo = cat(_decoded_invMatrixOutputs_T_19, _decoded_invMatrixOutputs_T_18) node decoded_invMatrixOutputs_hi_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_21, _decoded_invMatrixOutputs_T_20) node decoded_invMatrixOutputs_hi_lo_hi = cat(decoded_invMatrixOutputs_hi_lo_hi_hi, decoded_invMatrixOutputs_hi_lo_hi_lo) node decoded_invMatrixOutputs_hi_lo = cat(decoded_invMatrixOutputs_hi_lo_hi, decoded_invMatrixOutputs_hi_lo_lo) node decoded_invMatrixOutputs_hi_hi_lo_lo = cat(_decoded_invMatrixOutputs_T_23, _decoded_invMatrixOutputs_T_22) node decoded_invMatrixOutputs_hi_hi_lo_hi = cat(_decoded_invMatrixOutputs_T_25, _decoded_invMatrixOutputs_T_24) node decoded_invMatrixOutputs_hi_hi_lo = cat(decoded_invMatrixOutputs_hi_hi_lo_hi, decoded_invMatrixOutputs_hi_hi_lo_lo) node decoded_invMatrixOutputs_hi_hi_hi_lo = cat(_decoded_invMatrixOutputs_T_27, _decoded_invMatrixOutputs_T_26) node decoded_invMatrixOutputs_hi_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28) node decoded_invMatrixOutputs_hi_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi_hi, decoded_invMatrixOutputs_hi_hi_hi_lo) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, decoded_invMatrixOutputs_hi_hi_lo) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 15, 0) node _decoded_T_1 = shl(UInt<8>(0hff), 8) node _decoded_T_2 = xor(UInt<16>(0hffff), _decoded_T_1) node _decoded_T_3 = shr(_decoded_T, 8) node _decoded_T_4 = and(_decoded_T_3, _decoded_T_2) node _decoded_T_5 = bits(_decoded_T, 7, 0) node _decoded_T_6 = shl(_decoded_T_5, 8) node _decoded_T_7 = not(_decoded_T_2) node _decoded_T_8 = and(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = or(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(_decoded_T_2, 11, 0) node _decoded_T_11 = shl(_decoded_T_10, 4) node _decoded_T_12 = xor(_decoded_T_2, _decoded_T_11) node _decoded_T_13 = shr(_decoded_T_9, 4) node _decoded_T_14 = and(_decoded_T_13, _decoded_T_12) node _decoded_T_15 = bits(_decoded_T_9, 11, 0) node _decoded_T_16 = shl(_decoded_T_15, 4) node _decoded_T_17 = not(_decoded_T_12) node _decoded_T_18 = and(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = or(_decoded_T_14, _decoded_T_18) node _decoded_T_20 = bits(_decoded_T_12, 13, 0) node _decoded_T_21 = shl(_decoded_T_20, 2) node _decoded_T_22 = xor(_decoded_T_12, _decoded_T_21) node _decoded_T_23 = shr(_decoded_T_19, 2) node _decoded_T_24 = and(_decoded_T_23, _decoded_T_22) node _decoded_T_25 = bits(_decoded_T_19, 13, 0) node _decoded_T_26 = shl(_decoded_T_25, 2) node _decoded_T_27 = not(_decoded_T_22) node _decoded_T_28 = and(_decoded_T_26, _decoded_T_27) node _decoded_T_29 = or(_decoded_T_24, _decoded_T_28) node _decoded_T_30 = bits(_decoded_T_22, 14, 0) node _decoded_T_31 = shl(_decoded_T_30, 1) node _decoded_T_32 = xor(_decoded_T_22, _decoded_T_31) node _decoded_T_33 = shr(_decoded_T_29, 1) node _decoded_T_34 = and(_decoded_T_33, _decoded_T_32) node _decoded_T_35 = bits(_decoded_T_29, 14, 0) node _decoded_T_36 = shl(_decoded_T_35, 1) node _decoded_T_37 = not(_decoded_T_32) node _decoded_T_38 = and(_decoded_T_36, _decoded_T_37) node _decoded_T_39 = or(_decoded_T_34, _decoded_T_38) node _decoded_T_40 = bits(decoded_plaOutput, 29, 16) node _decoded_T_41 = bits(_decoded_T_40, 7, 0) node _decoded_T_42 = shl(UInt<4>(0hf), 4) node _decoded_T_43 = xor(UInt<8>(0hff), _decoded_T_42) node _decoded_T_44 = shr(_decoded_T_41, 4) node _decoded_T_45 = and(_decoded_T_44, _decoded_T_43) node _decoded_T_46 = bits(_decoded_T_41, 3, 0) node _decoded_T_47 = shl(_decoded_T_46, 4) node _decoded_T_48 = not(_decoded_T_43) node _decoded_T_49 = and(_decoded_T_47, _decoded_T_48) node _decoded_T_50 = or(_decoded_T_45, _decoded_T_49) node _decoded_T_51 = bits(_decoded_T_43, 5, 0) node _decoded_T_52 = shl(_decoded_T_51, 2) node _decoded_T_53 = xor(_decoded_T_43, _decoded_T_52) node _decoded_T_54 = shr(_decoded_T_50, 2) node _decoded_T_55 = and(_decoded_T_54, _decoded_T_53) node _decoded_T_56 = bits(_decoded_T_50, 5, 0) node _decoded_T_57 = shl(_decoded_T_56, 2) node _decoded_T_58 = not(_decoded_T_53) node _decoded_T_59 = and(_decoded_T_57, _decoded_T_58) node _decoded_T_60 = or(_decoded_T_55, _decoded_T_59) node _decoded_T_61 = bits(_decoded_T_53, 6, 0) node _decoded_T_62 = shl(_decoded_T_61, 1) node _decoded_T_63 = xor(_decoded_T_53, _decoded_T_62) node _decoded_T_64 = shr(_decoded_T_60, 1) node _decoded_T_65 = and(_decoded_T_64, _decoded_T_63) node _decoded_T_66 = bits(_decoded_T_60, 6, 0) node _decoded_T_67 = shl(_decoded_T_66, 1) node _decoded_T_68 = not(_decoded_T_63) node _decoded_T_69 = and(_decoded_T_67, _decoded_T_68) node _decoded_T_70 = or(_decoded_T_65, _decoded_T_69) node _decoded_T_71 = bits(_decoded_T_40, 13, 8) node _decoded_T_72 = bits(_decoded_T_71, 3, 0) node _decoded_T_73 = bits(_decoded_T_72, 1, 0) node _decoded_T_74 = bits(_decoded_T_73, 0, 0) node _decoded_T_75 = bits(_decoded_T_73, 1, 1) node _decoded_T_76 = cat(_decoded_T_74, _decoded_T_75) node _decoded_T_77 = bits(_decoded_T_72, 3, 2) node _decoded_T_78 = bits(_decoded_T_77, 0, 0) node _decoded_T_79 = bits(_decoded_T_77, 1, 1) node _decoded_T_80 = cat(_decoded_T_78, _decoded_T_79) node _decoded_T_81 = cat(_decoded_T_76, _decoded_T_80) node _decoded_T_82 = bits(_decoded_T_71, 5, 4) node _decoded_T_83 = bits(_decoded_T_82, 0, 0) node _decoded_T_84 = bits(_decoded_T_82, 1, 1) node _decoded_T_85 = cat(_decoded_T_83, _decoded_T_84) node _decoded_T_86 = cat(_decoded_T_81, _decoded_T_85) node _decoded_T_87 = cat(_decoded_T_70, _decoded_T_86) node decoded = cat(_decoded_T_39, _decoded_T_87) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T node _io_resp_0_vc_sel_0_4_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`0`[4], _io_resp_0_vc_sel_0_4_T node _io_resp_0_vc_sel_0_5_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`0`[5], _io_resp_0_vc_sel_0_5_T node _io_resp_0_vc_sel_0_6_T = bits(decoded, 6, 6) connect io.resp.`0`.vc_sel.`0`[6], _io_resp_0_vc_sel_0_6_T node _io_resp_0_vc_sel_0_7_T = bits(decoded, 7, 7) connect io.resp.`0`.vc_sel.`0`[7], _io_resp_0_vc_sel_0_7_T node _io_resp_0_vc_sel_0_8_T = bits(decoded, 8, 8) connect io.resp.`0`.vc_sel.`0`[8], _io_resp_0_vc_sel_0_8_T node _io_resp_0_vc_sel_0_9_T = bits(decoded, 9, 9) connect io.resp.`0`.vc_sel.`0`[9], _io_resp_0_vc_sel_0_9_T node _io_resp_0_vc_sel_1_0_T = bits(decoded, 10, 10) connect io.resp.`0`.vc_sel.`1`[0], _io_resp_0_vc_sel_1_0_T node _io_resp_0_vc_sel_1_1_T = bits(decoded, 11, 11) connect io.resp.`0`.vc_sel.`1`[1], _io_resp_0_vc_sel_1_1_T node _io_resp_0_vc_sel_1_2_T = bits(decoded, 12, 12) connect io.resp.`0`.vc_sel.`1`[2], _io_resp_0_vc_sel_1_2_T node _io_resp_0_vc_sel_1_3_T = bits(decoded, 13, 13) connect io.resp.`0`.vc_sel.`1`[3], _io_resp_0_vc_sel_1_3_T node _io_resp_0_vc_sel_1_4_T = bits(decoded, 14, 14) connect io.resp.`0`.vc_sel.`1`[4], _io_resp_0_vc_sel_1_4_T node _io_resp_0_vc_sel_1_5_T = bits(decoded, 15, 15) connect io.resp.`0`.vc_sel.`1`[5], _io_resp_0_vc_sel_1_5_T node _io_resp_0_vc_sel_1_6_T = bits(decoded, 16, 16) connect io.resp.`0`.vc_sel.`1`[6], _io_resp_0_vc_sel_1_6_T node _io_resp_0_vc_sel_1_7_T = bits(decoded, 17, 17) connect io.resp.`0`.vc_sel.`1`[7], _io_resp_0_vc_sel_1_7_T node _io_resp_0_vc_sel_1_8_T = bits(decoded, 18, 18) connect io.resp.`0`.vc_sel.`1`[8], _io_resp_0_vc_sel_1_8_T node _io_resp_0_vc_sel_1_9_T = bits(decoded, 19, 19) connect io.resp.`0`.vc_sel.`1`[9], _io_resp_0_vc_sel_1_9_T node _io_resp_0_vc_sel_2_0_T = bits(decoded, 20, 20) connect io.resp.`0`.vc_sel.`2`[0], _io_resp_0_vc_sel_2_0_T node _io_resp_0_vc_sel_2_1_T = bits(decoded, 21, 21) connect io.resp.`0`.vc_sel.`2`[1], _io_resp_0_vc_sel_2_1_T node _io_resp_0_vc_sel_2_2_T = bits(decoded, 22, 22) connect io.resp.`0`.vc_sel.`2`[2], _io_resp_0_vc_sel_2_2_T node _io_resp_0_vc_sel_2_3_T = bits(decoded, 23, 23) connect io.resp.`0`.vc_sel.`2`[3], _io_resp_0_vc_sel_2_3_T node _io_resp_0_vc_sel_2_4_T = bits(decoded, 24, 24) connect io.resp.`0`.vc_sel.`2`[4], _io_resp_0_vc_sel_2_4_T node _io_resp_0_vc_sel_2_5_T = bits(decoded, 25, 25) connect io.resp.`0`.vc_sel.`2`[5], _io_resp_0_vc_sel_2_5_T node _io_resp_0_vc_sel_2_6_T = bits(decoded, 26, 26) connect io.resp.`0`.vc_sel.`2`[6], _io_resp_0_vc_sel_2_6_T node _io_resp_0_vc_sel_2_7_T = bits(decoded, 27, 27) connect io.resp.`0`.vc_sel.`2`[7], _io_resp_0_vc_sel_2_7_T node _io_resp_0_vc_sel_2_8_T = bits(decoded, 28, 28) connect io.resp.`0`.vc_sel.`2`[8], _io_resp_0_vc_sel_2_8_T node _io_resp_0_vc_sel_2_9_T = bits(decoded, 29, 29) connect io.resp.`0`.vc_sel.`2`[9], _io_resp_0_vc_sel_2_9_T connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<20> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<30> node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_invInputs_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_14, decoded_andMatrixOutputs_andMatrixInput_15) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_12, decoded_andMatrixOutputs_andMatrixInput_13) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_lo_lo_lo) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_10, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_8, decoded_andMatrixOutputs_andMatrixInput_9) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_4, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_2_1, decoded_andMatrixOutputs_andMatrixInput_3_1) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_14_1, decoded_andMatrixOutputs_andMatrixInput_15_1) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_12_1, decoded_andMatrixOutputs_andMatrixInput_13_1) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_lo_lo_lo_1) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_10_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_8_1, decoded_andMatrixOutputs_andMatrixInput_9_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_4_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_2_2, decoded_andMatrixOutputs_andMatrixInput_3_2) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoded_plaInput_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(decoded_invInputs_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_14_2, decoded_andMatrixOutputs_andMatrixInput_15_2) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_12_2, decoded_andMatrixOutputs_andMatrixInput_13_2) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo_2) node decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_10_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_lo_hi_lo_2) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_6_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_4_2, decoded_andMatrixOutputs_andMatrixInput_5_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo_2) node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_2_3, decoded_andMatrixOutputs_andMatrixInput_3_3) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_hi_hi_lo_2) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_invInputs_1, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(decoded_invInputs_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_14_3, decoded_andMatrixOutputs_andMatrixInput_15_3) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_12_3, decoded_andMatrixOutputs_andMatrixInput_13_3) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_lo_lo_lo_3) node decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_10_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_lo_hi_lo_3) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_6_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_4_3, decoded_andMatrixOutputs_andMatrixInput_5_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_hi_lo_lo_3) node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_2_4, decoded_andMatrixOutputs_andMatrixInput_3_4) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_hi_hi_lo_3) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(decoded_invInputs_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_14_4, decoded_andMatrixOutputs_andMatrixInput_15_4) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_12_4, decoded_andMatrixOutputs_andMatrixInput_13_4) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_lo_lo_lo_4) node decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_10_4, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_8_4, decoded_andMatrixOutputs_andMatrixInput_9_4) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo_4) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_4, decoded_andMatrixOutputs_andMatrixInput_7_4) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_4_4, decoded_andMatrixOutputs_andMatrixInput_5_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_hi_lo_lo_4) node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_5, decoded_andMatrixOutputs_andMatrixInput_3_5) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo_4) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoded_plaInput_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(decoded_invInputs_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_14_5, decoded_andMatrixOutputs_andMatrixInput_15_5) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_12_5, decoded_andMatrixOutputs_andMatrixInput_13_5) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_5) node decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_10_5, decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_8_5, decoded_andMatrixOutputs_andMatrixInput_9_5) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_lo_hi_lo_5) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_5, decoded_andMatrixOutputs_andMatrixInput_7_5) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_4_5, decoded_andMatrixOutputs_andMatrixInput_5_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_5) node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_6, decoded_andMatrixOutputs_andMatrixInput_3_6) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_hi_hi_lo_5) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_10_2 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(decoded_invInputs_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_14_6, decoded_andMatrixOutputs_andMatrixInput_15_6) node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_12_6, decoded_andMatrixOutputs_andMatrixInput_13_6) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_lo_lo_lo_6) node decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_10_6, decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_8_6, decoded_andMatrixOutputs_andMatrixInput_9_6) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_lo_hi_lo_6) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_6_6, decoded_andMatrixOutputs_andMatrixInput_7_6) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_6, decoded_andMatrixOutputs_andMatrixInput_5_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_hi_lo_lo_6) node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_2_7, decoded_andMatrixOutputs_andMatrixInput_3_7) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_hi_hi_lo_6) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_plaInput_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoded_plaInput_1, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(decoded_plaInput_1, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(decoded_invInputs_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_14_7, decoded_andMatrixOutputs_andMatrixInput_15_7) node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_12_7, decoded_andMatrixOutputs_andMatrixInput_13_7) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_lo_lo_lo_7) node decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_10_7, decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_8_7, decoded_andMatrixOutputs_andMatrixInput_9_7) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_lo_hi_lo_7) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_6_7, decoded_andMatrixOutputs_andMatrixInput_7_7) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_4_7, decoded_andMatrixOutputs_andMatrixInput_5_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_hi_lo_lo_7) node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_2_8, decoded_andMatrixOutputs_andMatrixInput_3_8) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_hi_hi_lo_7) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs_1, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoded_invInputs_1, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(decoded_invInputs_1, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_14_8, decoded_andMatrixOutputs_andMatrixInput_15_8) node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_12_8, decoded_andMatrixOutputs_andMatrixInput_13_8) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_lo_lo_lo_8) node decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_10_8, decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_lo_hi_lo_8) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_4_8, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_hi_lo_lo_8) node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_2_9, decoded_andMatrixOutputs_andMatrixInput_3_9) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_hi_hi_lo_8) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput_1, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoded_invInputs_1, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(decoded_invInputs_1, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_14_9, decoded_andMatrixOutputs_andMatrixInput_15_9) node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_12_9, decoded_andMatrixOutputs_andMatrixInput_13_9) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_lo_lo_lo_9) node decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_10_9, decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_lo_hi_lo_9) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_4_9, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_hi_lo_lo_9) node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_2_10, decoded_andMatrixOutputs_andMatrixInput_3_10) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_hi_hi_lo_9) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_0_2_1 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput_1, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs_1, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs_1, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_plaInput_1, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_plaInput_1, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs_1, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_invInputs_1, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs_1, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs_1, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_plaInput_1, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_invInputs_1, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_invInputs_1, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_plaInput_1, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoded_invInputs_1, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(decoded_invInputs_1, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(decoded_plaInput_1, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_14_10, decoded_andMatrixOutputs_andMatrixInput_15_10) node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_12_10, decoded_andMatrixOutputs_andMatrixInput_13_10) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_lo_lo_lo_10) node decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_10_10, decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_8_10, decoded_andMatrixOutputs_andMatrixInput_9_10) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_10) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_6_10, decoded_andMatrixOutputs_andMatrixInput_7_10) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_4_10, decoded_andMatrixOutputs_andMatrixInput_5_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_hi_lo_lo_10) node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_2_11, decoded_andMatrixOutputs_andMatrixInput_3_11) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_10) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T_11) node _decoded_orMatrixOutputs_T_1 = orr(decoded_andMatrixOutputs_8_2) node _decoded_orMatrixOutputs_T_2 = orr(decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_4_2, decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_4 = orr(_decoded_orMatrixOutputs_T_3) node _decoded_orMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_3_2, decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_6 = orr(_decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_3_2) node _decoded_orMatrixOutputs_T_7 = cat(decoded_orMatrixOutputs_hi_1, decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_8 = orr(_decoded_orMatrixOutputs_T_7) node _decoded_orMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_10 = orr(_decoded_orMatrixOutputs_T_9) node decoded_orMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_5_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_11 = cat(decoded_orMatrixOutputs_hi_2, decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_12 = orr(_decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_7_2, decoded_andMatrixOutputs_2_2) node _decoded_orMatrixOutputs_T_13 = cat(decoded_orMatrixOutputs_hi_3, decoded_andMatrixOutputs_0_2_1) node _decoded_orMatrixOutputs_T_14 = orr(_decoded_orMatrixOutputs_T_13) node decoded_orMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_6_2) node _decoded_orMatrixOutputs_T_15 = cat(decoded_orMatrixOutputs_hi_4, decoded_andMatrixOutputs_9_2) node _decoded_orMatrixOutputs_T_16 = orr(_decoded_orMatrixOutputs_T_15) node decoded_orMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_6_2) node _decoded_orMatrixOutputs_T_17 = cat(decoded_orMatrixOutputs_hi_5, decoded_andMatrixOutputs_9_2) node _decoded_orMatrixOutputs_T_18 = orr(_decoded_orMatrixOutputs_T_17) node decoded_orMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_6_2) node _decoded_orMatrixOutputs_T_19 = cat(decoded_orMatrixOutputs_hi_6, decoded_andMatrixOutputs_9_2) node _decoded_orMatrixOutputs_T_20 = orr(_decoded_orMatrixOutputs_T_19) node decoded_orMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_6_2) node _decoded_orMatrixOutputs_T_21 = cat(decoded_orMatrixOutputs_hi_7, decoded_andMatrixOutputs_9_2) node _decoded_orMatrixOutputs_T_22 = orr(_decoded_orMatrixOutputs_T_21) node decoded_orMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_6_2) node _decoded_orMatrixOutputs_T_23 = cat(decoded_orMatrixOutputs_hi_8, decoded_andMatrixOutputs_9_2) node _decoded_orMatrixOutputs_T_24 = orr(_decoded_orMatrixOutputs_T_23) node decoded_orMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_6_2) node _decoded_orMatrixOutputs_T_25 = cat(decoded_orMatrixOutputs_hi_9, decoded_andMatrixOutputs_9_2) node _decoded_orMatrixOutputs_T_26 = orr(_decoded_orMatrixOutputs_T_25) node decoded_orMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_6_2) node _decoded_orMatrixOutputs_T_27 = cat(decoded_orMatrixOutputs_hi_10, decoded_andMatrixOutputs_9_2) node _decoded_orMatrixOutputs_T_28 = orr(_decoded_orMatrixOutputs_T_27) node decoded_orMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_6_2) node _decoded_orMatrixOutputs_T_29 = cat(decoded_orMatrixOutputs_hi_11, decoded_andMatrixOutputs_9_2) node _decoded_orMatrixOutputs_T_30 = orr(_decoded_orMatrixOutputs_T_29) node decoded_orMatrixOutputs_lo_lo_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_4, _decoded_orMatrixOutputs_T_2) node decoded_orMatrixOutputs_lo_lo_lo_1 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_1, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_lo_lo_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_8, _decoded_orMatrixOutputs_T_6) node decoded_orMatrixOutputs_lo_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_12, _decoded_orMatrixOutputs_T_10) node decoded_orMatrixOutputs_lo_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_1, decoded_orMatrixOutputs_lo_lo_hi_lo_1) node decoded_orMatrixOutputs_lo_lo_1 = cat(decoded_orMatrixOutputs_lo_lo_hi_1, decoded_orMatrixOutputs_lo_lo_lo_1) node decoded_orMatrixOutputs_lo_hi_lo_lo_1 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_14) node decoded_orMatrixOutputs_lo_hi_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_1, decoded_orMatrixOutputs_lo_hi_lo_lo_1) node decoded_orMatrixOutputs_lo_hi_hi_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_1, decoded_orMatrixOutputs_lo_hi_hi_lo_1) node decoded_orMatrixOutputs_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_1, decoded_orMatrixOutputs_lo_hi_lo_1) node decoded_orMatrixOutputs_lo_1 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_lo_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_1 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_1, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_lo_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_orMatrixOutputs_T_18, _decoded_orMatrixOutputs_T_16) node decoded_orMatrixOutputs_hi_lo_hi_1 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_1, decoded_orMatrixOutputs_hi_lo_hi_lo_1) node decoded_orMatrixOutputs_hi_lo_1 = cat(decoded_orMatrixOutputs_hi_lo_hi_1, decoded_orMatrixOutputs_hi_lo_lo_1) node decoded_orMatrixOutputs_hi_hi_lo_lo_1 = cat(_decoded_orMatrixOutputs_T_22, _decoded_orMatrixOutputs_T_20) node decoded_orMatrixOutputs_hi_hi_lo_hi_1 = cat(_decoded_orMatrixOutputs_T_26, _decoded_orMatrixOutputs_T_24) node decoded_orMatrixOutputs_hi_hi_lo_1 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_1, decoded_orMatrixOutputs_hi_hi_lo_lo_1) node decoded_orMatrixOutputs_hi_hi_hi_lo_1 = cat(_decoded_orMatrixOutputs_T_30, _decoded_orMatrixOutputs_T_28) node decoded_orMatrixOutputs_hi_hi_hi_hi_1 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_1, decoded_orMatrixOutputs_hi_hi_hi_lo_1) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, decoded_orMatrixOutputs_hi_hi_lo_1) node decoded_orMatrixOutputs_hi_12 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo_1) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_12, decoded_orMatrixOutputs_lo_1) node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_1, 8, 8) node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_1, 9, 9) node _decoded_invMatrixOutputs_T_40 = bits(decoded_orMatrixOutputs_1, 10, 10) node _decoded_invMatrixOutputs_T_41 = bits(decoded_orMatrixOutputs_1, 11, 11) node _decoded_invMatrixOutputs_T_42 = bits(decoded_orMatrixOutputs_1, 12, 12) node _decoded_invMatrixOutputs_T_43 = bits(decoded_orMatrixOutputs_1, 13, 13) node _decoded_invMatrixOutputs_T_44 = bits(decoded_orMatrixOutputs_1, 14, 14) node _decoded_invMatrixOutputs_T_45 = bits(decoded_orMatrixOutputs_1, 15, 15) node _decoded_invMatrixOutputs_T_46 = bits(decoded_orMatrixOutputs_1, 16, 16) node _decoded_invMatrixOutputs_T_47 = bits(decoded_orMatrixOutputs_1, 17, 17) node _decoded_invMatrixOutputs_T_48 = bits(decoded_orMatrixOutputs_1, 18, 18) node _decoded_invMatrixOutputs_T_49 = bits(decoded_orMatrixOutputs_1, 19, 19) node _decoded_invMatrixOutputs_T_50 = bits(decoded_orMatrixOutputs_1, 20, 20) node _decoded_invMatrixOutputs_T_51 = bits(decoded_orMatrixOutputs_1, 21, 21) node _decoded_invMatrixOutputs_T_52 = bits(decoded_orMatrixOutputs_1, 22, 22) node _decoded_invMatrixOutputs_T_53 = bits(decoded_orMatrixOutputs_1, 23, 23) node _decoded_invMatrixOutputs_T_54 = bits(decoded_orMatrixOutputs_1, 24, 24) node _decoded_invMatrixOutputs_T_55 = bits(decoded_orMatrixOutputs_1, 25, 25) node _decoded_invMatrixOutputs_T_56 = bits(decoded_orMatrixOutputs_1, 26, 26) node _decoded_invMatrixOutputs_T_57 = bits(decoded_orMatrixOutputs_1, 27, 27) node _decoded_invMatrixOutputs_T_58 = bits(decoded_orMatrixOutputs_1, 28, 28) node _decoded_invMatrixOutputs_T_59 = bits(decoded_orMatrixOutputs_1, 29, 29) node decoded_invMatrixOutputs_lo_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_32, _decoded_invMatrixOutputs_T_31) node decoded_invMatrixOutputs_lo_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_1, _decoded_invMatrixOutputs_T_30) node decoded_invMatrixOutputs_lo_lo_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_34, _decoded_invMatrixOutputs_T_33) node decoded_invMatrixOutputs_lo_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_36, _decoded_invMatrixOutputs_T_35) node decoded_invMatrixOutputs_lo_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_1, decoded_invMatrixOutputs_lo_lo_hi_lo_1) node decoded_invMatrixOutputs_lo_lo_1 = cat(decoded_invMatrixOutputs_lo_lo_hi_1, decoded_invMatrixOutputs_lo_lo_lo_1) node decoded_invMatrixOutputs_lo_hi_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_38, _decoded_invMatrixOutputs_T_37) node decoded_invMatrixOutputs_lo_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_40, _decoded_invMatrixOutputs_T_39) node decoded_invMatrixOutputs_lo_hi_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_1, decoded_invMatrixOutputs_lo_hi_lo_lo_1) node decoded_invMatrixOutputs_lo_hi_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_42, _decoded_invMatrixOutputs_T_41) node decoded_invMatrixOutputs_lo_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_44, _decoded_invMatrixOutputs_T_43) node decoded_invMatrixOutputs_lo_hi_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_1, decoded_invMatrixOutputs_lo_hi_hi_lo_1) node decoded_invMatrixOutputs_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_1, decoded_invMatrixOutputs_lo_hi_lo_1) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_47, _decoded_invMatrixOutputs_T_46) node decoded_invMatrixOutputs_hi_lo_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_1, _decoded_invMatrixOutputs_T_45) node decoded_invMatrixOutputs_hi_lo_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_49, _decoded_invMatrixOutputs_T_48) node decoded_invMatrixOutputs_hi_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_51, _decoded_invMatrixOutputs_T_50) node decoded_invMatrixOutputs_hi_lo_hi_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_1, decoded_invMatrixOutputs_hi_lo_hi_lo_1) node decoded_invMatrixOutputs_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_lo_hi_1, decoded_invMatrixOutputs_hi_lo_lo_1) node decoded_invMatrixOutputs_hi_hi_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_53, _decoded_invMatrixOutputs_T_52) node decoded_invMatrixOutputs_hi_hi_lo_hi_1 = cat(_decoded_invMatrixOutputs_T_55, _decoded_invMatrixOutputs_T_54) node decoded_invMatrixOutputs_hi_hi_lo_1 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_1, decoded_invMatrixOutputs_hi_hi_lo_lo_1) node decoded_invMatrixOutputs_hi_hi_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_57, _decoded_invMatrixOutputs_T_56) node decoded_invMatrixOutputs_hi_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_59, _decoded_invMatrixOutputs_T_58) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_1, decoded_invMatrixOutputs_hi_hi_hi_lo_1) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, decoded_invMatrixOutputs_hi_hi_lo_1) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_88 = bits(decoded_plaOutput_1, 15, 0) node _decoded_T_89 = shl(UInt<8>(0hff), 8) node _decoded_T_90 = xor(UInt<16>(0hffff), _decoded_T_89) node _decoded_T_91 = shr(_decoded_T_88, 8) node _decoded_T_92 = and(_decoded_T_91, _decoded_T_90) node _decoded_T_93 = bits(_decoded_T_88, 7, 0) node _decoded_T_94 = shl(_decoded_T_93, 8) node _decoded_T_95 = not(_decoded_T_90) node _decoded_T_96 = and(_decoded_T_94, _decoded_T_95) node _decoded_T_97 = or(_decoded_T_92, _decoded_T_96) node _decoded_T_98 = bits(_decoded_T_90, 11, 0) node _decoded_T_99 = shl(_decoded_T_98, 4) node _decoded_T_100 = xor(_decoded_T_90, _decoded_T_99) node _decoded_T_101 = shr(_decoded_T_97, 4) node _decoded_T_102 = and(_decoded_T_101, _decoded_T_100) node _decoded_T_103 = bits(_decoded_T_97, 11, 0) node _decoded_T_104 = shl(_decoded_T_103, 4) node _decoded_T_105 = not(_decoded_T_100) node _decoded_T_106 = and(_decoded_T_104, _decoded_T_105) node _decoded_T_107 = or(_decoded_T_102, _decoded_T_106) node _decoded_T_108 = bits(_decoded_T_100, 13, 0) node _decoded_T_109 = shl(_decoded_T_108, 2) node _decoded_T_110 = xor(_decoded_T_100, _decoded_T_109) node _decoded_T_111 = shr(_decoded_T_107, 2) node _decoded_T_112 = and(_decoded_T_111, _decoded_T_110) node _decoded_T_113 = bits(_decoded_T_107, 13, 0) node _decoded_T_114 = shl(_decoded_T_113, 2) node _decoded_T_115 = not(_decoded_T_110) node _decoded_T_116 = and(_decoded_T_114, _decoded_T_115) node _decoded_T_117 = or(_decoded_T_112, _decoded_T_116) node _decoded_T_118 = bits(_decoded_T_110, 14, 0) node _decoded_T_119 = shl(_decoded_T_118, 1) node _decoded_T_120 = xor(_decoded_T_110, _decoded_T_119) node _decoded_T_121 = shr(_decoded_T_117, 1) node _decoded_T_122 = and(_decoded_T_121, _decoded_T_120) node _decoded_T_123 = bits(_decoded_T_117, 14, 0) node _decoded_T_124 = shl(_decoded_T_123, 1) node _decoded_T_125 = not(_decoded_T_120) node _decoded_T_126 = and(_decoded_T_124, _decoded_T_125) node _decoded_T_127 = or(_decoded_T_122, _decoded_T_126) node _decoded_T_128 = bits(decoded_plaOutput_1, 29, 16) node _decoded_T_129 = bits(_decoded_T_128, 7, 0) node _decoded_T_130 = shl(UInt<4>(0hf), 4) node _decoded_T_131 = xor(UInt<8>(0hff), _decoded_T_130) node _decoded_T_132 = shr(_decoded_T_129, 4) node _decoded_T_133 = and(_decoded_T_132, _decoded_T_131) node _decoded_T_134 = bits(_decoded_T_129, 3, 0) node _decoded_T_135 = shl(_decoded_T_134, 4) node _decoded_T_136 = not(_decoded_T_131) node _decoded_T_137 = and(_decoded_T_135, _decoded_T_136) node _decoded_T_138 = or(_decoded_T_133, _decoded_T_137) node _decoded_T_139 = bits(_decoded_T_131, 5, 0) node _decoded_T_140 = shl(_decoded_T_139, 2) node _decoded_T_141 = xor(_decoded_T_131, _decoded_T_140) node _decoded_T_142 = shr(_decoded_T_138, 2) node _decoded_T_143 = and(_decoded_T_142, _decoded_T_141) node _decoded_T_144 = bits(_decoded_T_138, 5, 0) node _decoded_T_145 = shl(_decoded_T_144, 2) node _decoded_T_146 = not(_decoded_T_141) node _decoded_T_147 = and(_decoded_T_145, _decoded_T_146) node _decoded_T_148 = or(_decoded_T_143, _decoded_T_147) node _decoded_T_149 = bits(_decoded_T_141, 6, 0) node _decoded_T_150 = shl(_decoded_T_149, 1) node _decoded_T_151 = xor(_decoded_T_141, _decoded_T_150) node _decoded_T_152 = shr(_decoded_T_148, 1) node _decoded_T_153 = and(_decoded_T_152, _decoded_T_151) node _decoded_T_154 = bits(_decoded_T_148, 6, 0) node _decoded_T_155 = shl(_decoded_T_154, 1) node _decoded_T_156 = not(_decoded_T_151) node _decoded_T_157 = and(_decoded_T_155, _decoded_T_156) node _decoded_T_158 = or(_decoded_T_153, _decoded_T_157) node _decoded_T_159 = bits(_decoded_T_128, 13, 8) node _decoded_T_160 = bits(_decoded_T_159, 3, 0) node _decoded_T_161 = bits(_decoded_T_160, 1, 0) node _decoded_T_162 = bits(_decoded_T_161, 0, 0) node _decoded_T_163 = bits(_decoded_T_161, 1, 1) node _decoded_T_164 = cat(_decoded_T_162, _decoded_T_163) node _decoded_T_165 = bits(_decoded_T_160, 3, 2) node _decoded_T_166 = bits(_decoded_T_165, 0, 0) node _decoded_T_167 = bits(_decoded_T_165, 1, 1) node _decoded_T_168 = cat(_decoded_T_166, _decoded_T_167) node _decoded_T_169 = cat(_decoded_T_164, _decoded_T_168) node _decoded_T_170 = bits(_decoded_T_159, 5, 4) node _decoded_T_171 = bits(_decoded_T_170, 0, 0) node _decoded_T_172 = bits(_decoded_T_170, 1, 1) node _decoded_T_173 = cat(_decoded_T_171, _decoded_T_172) node _decoded_T_174 = cat(_decoded_T_169, _decoded_T_173) node _decoded_T_175 = cat(_decoded_T_158, _decoded_T_174) node decoded_1 = cat(_decoded_T_127, _decoded_T_175) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T node _io_resp_1_vc_sel_0_4_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`0`[4], _io_resp_1_vc_sel_0_4_T node _io_resp_1_vc_sel_0_5_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`0`[5], _io_resp_1_vc_sel_0_5_T node _io_resp_1_vc_sel_0_6_T = bits(decoded_1, 6, 6) connect io.resp.`1`.vc_sel.`0`[6], _io_resp_1_vc_sel_0_6_T node _io_resp_1_vc_sel_0_7_T = bits(decoded_1, 7, 7) connect io.resp.`1`.vc_sel.`0`[7], _io_resp_1_vc_sel_0_7_T node _io_resp_1_vc_sel_0_8_T = bits(decoded_1, 8, 8) connect io.resp.`1`.vc_sel.`0`[8], _io_resp_1_vc_sel_0_8_T node _io_resp_1_vc_sel_0_9_T = bits(decoded_1, 9, 9) connect io.resp.`1`.vc_sel.`0`[9], _io_resp_1_vc_sel_0_9_T node _io_resp_1_vc_sel_1_0_T = bits(decoded_1, 10, 10) connect io.resp.`1`.vc_sel.`1`[0], _io_resp_1_vc_sel_1_0_T node _io_resp_1_vc_sel_1_1_T = bits(decoded_1, 11, 11) connect io.resp.`1`.vc_sel.`1`[1], _io_resp_1_vc_sel_1_1_T node _io_resp_1_vc_sel_1_2_T = bits(decoded_1, 12, 12) connect io.resp.`1`.vc_sel.`1`[2], _io_resp_1_vc_sel_1_2_T node _io_resp_1_vc_sel_1_3_T = bits(decoded_1, 13, 13) connect io.resp.`1`.vc_sel.`1`[3], _io_resp_1_vc_sel_1_3_T node _io_resp_1_vc_sel_1_4_T = bits(decoded_1, 14, 14) connect io.resp.`1`.vc_sel.`1`[4], _io_resp_1_vc_sel_1_4_T node _io_resp_1_vc_sel_1_5_T = bits(decoded_1, 15, 15) connect io.resp.`1`.vc_sel.`1`[5], _io_resp_1_vc_sel_1_5_T node _io_resp_1_vc_sel_1_6_T = bits(decoded_1, 16, 16) connect io.resp.`1`.vc_sel.`1`[6], _io_resp_1_vc_sel_1_6_T node _io_resp_1_vc_sel_1_7_T = bits(decoded_1, 17, 17) connect io.resp.`1`.vc_sel.`1`[7], _io_resp_1_vc_sel_1_7_T node _io_resp_1_vc_sel_1_8_T = bits(decoded_1, 18, 18) connect io.resp.`1`.vc_sel.`1`[8], _io_resp_1_vc_sel_1_8_T node _io_resp_1_vc_sel_1_9_T = bits(decoded_1, 19, 19) connect io.resp.`1`.vc_sel.`1`[9], _io_resp_1_vc_sel_1_9_T node _io_resp_1_vc_sel_2_0_T = bits(decoded_1, 20, 20) connect io.resp.`1`.vc_sel.`2`[0], _io_resp_1_vc_sel_2_0_T node _io_resp_1_vc_sel_2_1_T = bits(decoded_1, 21, 21) connect io.resp.`1`.vc_sel.`2`[1], _io_resp_1_vc_sel_2_1_T node _io_resp_1_vc_sel_2_2_T = bits(decoded_1, 22, 22) connect io.resp.`1`.vc_sel.`2`[2], _io_resp_1_vc_sel_2_2_T node _io_resp_1_vc_sel_2_3_T = bits(decoded_1, 23, 23) connect io.resp.`1`.vc_sel.`2`[3], _io_resp_1_vc_sel_2_3_T node _io_resp_1_vc_sel_2_4_T = bits(decoded_1, 24, 24) connect io.resp.`1`.vc_sel.`2`[4], _io_resp_1_vc_sel_2_4_T node _io_resp_1_vc_sel_2_5_T = bits(decoded_1, 25, 25) connect io.resp.`1`.vc_sel.`2`[5], _io_resp_1_vc_sel_2_5_T node _io_resp_1_vc_sel_2_6_T = bits(decoded_1, 26, 26) connect io.resp.`1`.vc_sel.`2`[6], _io_resp_1_vc_sel_2_6_T node _io_resp_1_vc_sel_2_7_T = bits(decoded_1, 27, 27) connect io.resp.`1`.vc_sel.`2`[7], _io_resp_1_vc_sel_2_7_T node _io_resp_1_vc_sel_2_8_T = bits(decoded_1, 28, 28) connect io.resp.`1`.vc_sel.`2`[8], _io_resp_1_vc_sel_2_8_T node _io_resp_1_vc_sel_2_9_T = bits(decoded_1, 29, 29) connect io.resp.`1`.vc_sel.`2`[9], _io_resp_1_vc_sel_2_9_T connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<20> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<30> node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput_2, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs_2, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_invInputs_2, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_2_12, decoded_andMatrixOutputs_andMatrixInput_3_12) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_0_2_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput_2, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs_2, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_invInputs_2, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_plaInput_2, 19, 19) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_2_13, decoded_andMatrixOutputs_andMatrixInput_3_13) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_1_2_1 = andr(_decoded_andMatrixOutputs_T_13) node _decoded_orMatrixOutputs_T_31 = orr(decoded_andMatrixOutputs_1_2_1) node _decoded_orMatrixOutputs_T_32 = orr(decoded_andMatrixOutputs_0_2_2) node decoded_orMatrixOutputs_lo_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_lo_2 = cat(decoded_orMatrixOutputs_lo_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_lo_hi_hi_2, decoded_orMatrixOutputs_lo_lo_hi_lo_2) node decoded_orMatrixOutputs_lo_lo_2 = cat(decoded_orMatrixOutputs_lo_lo_hi_2, decoded_orMatrixOutputs_lo_lo_lo_2) node decoded_orMatrixOutputs_lo_hi_lo_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_hi_2 = cat(_decoded_orMatrixOutputs_T_31, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_lo_hi_2, decoded_orMatrixOutputs_lo_hi_lo_lo_2) node decoded_orMatrixOutputs_lo_hi_hi_lo_2 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_32) node decoded_orMatrixOutputs_lo_hi_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi_2, decoded_orMatrixOutputs_lo_hi_hi_lo_2) node decoded_orMatrixOutputs_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_2, decoded_orMatrixOutputs_lo_hi_lo_2) node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_2) node decoded_orMatrixOutputs_hi_lo_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_lo_2 = cat(decoded_orMatrixOutputs_hi_lo_lo_hi_2, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_lo_hi_2 = cat(decoded_orMatrixOutputs_hi_lo_hi_hi_2, decoded_orMatrixOutputs_hi_lo_hi_lo_2) node decoded_orMatrixOutputs_hi_lo_2 = cat(decoded_orMatrixOutputs_hi_lo_hi_2, decoded_orMatrixOutputs_hi_lo_lo_2) node decoded_orMatrixOutputs_hi_hi_lo_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_lo_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_lo_2 = cat(decoded_orMatrixOutputs_hi_hi_lo_hi_2, decoded_orMatrixOutputs_hi_hi_lo_lo_2) node decoded_orMatrixOutputs_hi_hi_hi_lo_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_hi_2 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi_2, decoded_orMatrixOutputs_hi_hi_hi_lo_2) node decoded_orMatrixOutputs_hi_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_hi_2, decoded_orMatrixOutputs_hi_hi_lo_2) node decoded_orMatrixOutputs_hi_13 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_2) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_13, decoded_orMatrixOutputs_lo_2) node _decoded_invMatrixOutputs_T_60 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_61 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_62 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_63 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_64 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_65 = bits(decoded_orMatrixOutputs_2, 5, 5) node _decoded_invMatrixOutputs_T_66 = bits(decoded_orMatrixOutputs_2, 6, 6) node _decoded_invMatrixOutputs_T_67 = bits(decoded_orMatrixOutputs_2, 7, 7) node _decoded_invMatrixOutputs_T_68 = bits(decoded_orMatrixOutputs_2, 8, 8) node _decoded_invMatrixOutputs_T_69 = bits(decoded_orMatrixOutputs_2, 9, 9) node _decoded_invMatrixOutputs_T_70 = bits(decoded_orMatrixOutputs_2, 10, 10) node _decoded_invMatrixOutputs_T_71 = bits(decoded_orMatrixOutputs_2, 11, 11) node _decoded_invMatrixOutputs_T_72 = bits(decoded_orMatrixOutputs_2, 12, 12) node _decoded_invMatrixOutputs_T_73 = bits(decoded_orMatrixOutputs_2, 13, 13) node _decoded_invMatrixOutputs_T_74 = bits(decoded_orMatrixOutputs_2, 14, 14) node _decoded_invMatrixOutputs_T_75 = bits(decoded_orMatrixOutputs_2, 15, 15) node _decoded_invMatrixOutputs_T_76 = bits(decoded_orMatrixOutputs_2, 16, 16) node _decoded_invMatrixOutputs_T_77 = bits(decoded_orMatrixOutputs_2, 17, 17) node _decoded_invMatrixOutputs_T_78 = bits(decoded_orMatrixOutputs_2, 18, 18) node _decoded_invMatrixOutputs_T_79 = bits(decoded_orMatrixOutputs_2, 19, 19) node _decoded_invMatrixOutputs_T_80 = bits(decoded_orMatrixOutputs_2, 20, 20) node _decoded_invMatrixOutputs_T_81 = bits(decoded_orMatrixOutputs_2, 21, 21) node _decoded_invMatrixOutputs_T_82 = bits(decoded_orMatrixOutputs_2, 22, 22) node _decoded_invMatrixOutputs_T_83 = bits(decoded_orMatrixOutputs_2, 23, 23) node _decoded_invMatrixOutputs_T_84 = bits(decoded_orMatrixOutputs_2, 24, 24) node _decoded_invMatrixOutputs_T_85 = bits(decoded_orMatrixOutputs_2, 25, 25) node _decoded_invMatrixOutputs_T_86 = bits(decoded_orMatrixOutputs_2, 26, 26) node _decoded_invMatrixOutputs_T_87 = bits(decoded_orMatrixOutputs_2, 27, 27) node _decoded_invMatrixOutputs_T_88 = bits(decoded_orMatrixOutputs_2, 28, 28) node _decoded_invMatrixOutputs_T_89 = bits(decoded_orMatrixOutputs_2, 29, 29) node decoded_invMatrixOutputs_lo_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_62, _decoded_invMatrixOutputs_T_61) node decoded_invMatrixOutputs_lo_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_lo_hi_2, _decoded_invMatrixOutputs_T_60) node decoded_invMatrixOutputs_lo_lo_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_64, _decoded_invMatrixOutputs_T_63) node decoded_invMatrixOutputs_lo_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_66, _decoded_invMatrixOutputs_T_65) node decoded_invMatrixOutputs_lo_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_hi_2, decoded_invMatrixOutputs_lo_lo_hi_lo_2) node decoded_invMatrixOutputs_lo_lo_2 = cat(decoded_invMatrixOutputs_lo_lo_hi_2, decoded_invMatrixOutputs_lo_lo_lo_2) node decoded_invMatrixOutputs_lo_hi_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_68, _decoded_invMatrixOutputs_T_67) node decoded_invMatrixOutputs_lo_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_70, _decoded_invMatrixOutputs_T_69) node decoded_invMatrixOutputs_lo_hi_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_lo_hi_2, decoded_invMatrixOutputs_lo_hi_lo_lo_2) node decoded_invMatrixOutputs_lo_hi_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_72, _decoded_invMatrixOutputs_T_71) node decoded_invMatrixOutputs_lo_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_74, _decoded_invMatrixOutputs_T_73) node decoded_invMatrixOutputs_lo_hi_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_hi_2, decoded_invMatrixOutputs_lo_hi_hi_lo_2) node decoded_invMatrixOutputs_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_2, decoded_invMatrixOutputs_lo_hi_lo_2) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2) node decoded_invMatrixOutputs_hi_lo_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_77, _decoded_invMatrixOutputs_T_76) node decoded_invMatrixOutputs_hi_lo_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_lo_hi_2, _decoded_invMatrixOutputs_T_75) node decoded_invMatrixOutputs_hi_lo_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_79, _decoded_invMatrixOutputs_T_78) node decoded_invMatrixOutputs_hi_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_81, _decoded_invMatrixOutputs_T_80) node decoded_invMatrixOutputs_hi_lo_hi_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_hi_2, decoded_invMatrixOutputs_hi_lo_hi_lo_2) node decoded_invMatrixOutputs_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_lo_hi_2, decoded_invMatrixOutputs_hi_lo_lo_2) node decoded_invMatrixOutputs_hi_hi_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_83, _decoded_invMatrixOutputs_T_82) node decoded_invMatrixOutputs_hi_hi_lo_hi_2 = cat(_decoded_invMatrixOutputs_T_85, _decoded_invMatrixOutputs_T_84) node decoded_invMatrixOutputs_hi_hi_lo_2 = cat(decoded_invMatrixOutputs_hi_hi_lo_hi_2, decoded_invMatrixOutputs_hi_hi_lo_lo_2) node decoded_invMatrixOutputs_hi_hi_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_87, _decoded_invMatrixOutputs_T_86) node decoded_invMatrixOutputs_hi_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_89, _decoded_invMatrixOutputs_T_88) node decoded_invMatrixOutputs_hi_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_hi_2, decoded_invMatrixOutputs_hi_hi_hi_lo_2) node decoded_invMatrixOutputs_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_2, decoded_invMatrixOutputs_hi_hi_lo_2) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_176 = bits(decoded_plaOutput_2, 15, 0) node _decoded_T_177 = shl(UInt<8>(0hff), 8) node _decoded_T_178 = xor(UInt<16>(0hffff), _decoded_T_177) node _decoded_T_179 = shr(_decoded_T_176, 8) node _decoded_T_180 = and(_decoded_T_179, _decoded_T_178) node _decoded_T_181 = bits(_decoded_T_176, 7, 0) node _decoded_T_182 = shl(_decoded_T_181, 8) node _decoded_T_183 = not(_decoded_T_178) node _decoded_T_184 = and(_decoded_T_182, _decoded_T_183) node _decoded_T_185 = or(_decoded_T_180, _decoded_T_184) node _decoded_T_186 = bits(_decoded_T_178, 11, 0) node _decoded_T_187 = shl(_decoded_T_186, 4) node _decoded_T_188 = xor(_decoded_T_178, _decoded_T_187) node _decoded_T_189 = shr(_decoded_T_185, 4) node _decoded_T_190 = and(_decoded_T_189, _decoded_T_188) node _decoded_T_191 = bits(_decoded_T_185, 11, 0) node _decoded_T_192 = shl(_decoded_T_191, 4) node _decoded_T_193 = not(_decoded_T_188) node _decoded_T_194 = and(_decoded_T_192, _decoded_T_193) node _decoded_T_195 = or(_decoded_T_190, _decoded_T_194) node _decoded_T_196 = bits(_decoded_T_188, 13, 0) node _decoded_T_197 = shl(_decoded_T_196, 2) node _decoded_T_198 = xor(_decoded_T_188, _decoded_T_197) node _decoded_T_199 = shr(_decoded_T_195, 2) node _decoded_T_200 = and(_decoded_T_199, _decoded_T_198) node _decoded_T_201 = bits(_decoded_T_195, 13, 0) node _decoded_T_202 = shl(_decoded_T_201, 2) node _decoded_T_203 = not(_decoded_T_198) node _decoded_T_204 = and(_decoded_T_202, _decoded_T_203) node _decoded_T_205 = or(_decoded_T_200, _decoded_T_204) node _decoded_T_206 = bits(_decoded_T_198, 14, 0) node _decoded_T_207 = shl(_decoded_T_206, 1) node _decoded_T_208 = xor(_decoded_T_198, _decoded_T_207) node _decoded_T_209 = shr(_decoded_T_205, 1) node _decoded_T_210 = and(_decoded_T_209, _decoded_T_208) node _decoded_T_211 = bits(_decoded_T_205, 14, 0) node _decoded_T_212 = shl(_decoded_T_211, 1) node _decoded_T_213 = not(_decoded_T_208) node _decoded_T_214 = and(_decoded_T_212, _decoded_T_213) node _decoded_T_215 = or(_decoded_T_210, _decoded_T_214) node _decoded_T_216 = bits(decoded_plaOutput_2, 29, 16) node _decoded_T_217 = bits(_decoded_T_216, 7, 0) node _decoded_T_218 = shl(UInt<4>(0hf), 4) node _decoded_T_219 = xor(UInt<8>(0hff), _decoded_T_218) node _decoded_T_220 = shr(_decoded_T_217, 4) node _decoded_T_221 = and(_decoded_T_220, _decoded_T_219) node _decoded_T_222 = bits(_decoded_T_217, 3, 0) node _decoded_T_223 = shl(_decoded_T_222, 4) node _decoded_T_224 = not(_decoded_T_219) node _decoded_T_225 = and(_decoded_T_223, _decoded_T_224) node _decoded_T_226 = or(_decoded_T_221, _decoded_T_225) node _decoded_T_227 = bits(_decoded_T_219, 5, 0) node _decoded_T_228 = shl(_decoded_T_227, 2) node _decoded_T_229 = xor(_decoded_T_219, _decoded_T_228) node _decoded_T_230 = shr(_decoded_T_226, 2) node _decoded_T_231 = and(_decoded_T_230, _decoded_T_229) node _decoded_T_232 = bits(_decoded_T_226, 5, 0) node _decoded_T_233 = shl(_decoded_T_232, 2) node _decoded_T_234 = not(_decoded_T_229) node _decoded_T_235 = and(_decoded_T_233, _decoded_T_234) node _decoded_T_236 = or(_decoded_T_231, _decoded_T_235) node _decoded_T_237 = bits(_decoded_T_229, 6, 0) node _decoded_T_238 = shl(_decoded_T_237, 1) node _decoded_T_239 = xor(_decoded_T_229, _decoded_T_238) node _decoded_T_240 = shr(_decoded_T_236, 1) node _decoded_T_241 = and(_decoded_T_240, _decoded_T_239) node _decoded_T_242 = bits(_decoded_T_236, 6, 0) node _decoded_T_243 = shl(_decoded_T_242, 1) node _decoded_T_244 = not(_decoded_T_239) node _decoded_T_245 = and(_decoded_T_243, _decoded_T_244) node _decoded_T_246 = or(_decoded_T_241, _decoded_T_245) node _decoded_T_247 = bits(_decoded_T_216, 13, 8) node _decoded_T_248 = bits(_decoded_T_247, 3, 0) node _decoded_T_249 = bits(_decoded_T_248, 1, 0) node _decoded_T_250 = bits(_decoded_T_249, 0, 0) node _decoded_T_251 = bits(_decoded_T_249, 1, 1) node _decoded_T_252 = cat(_decoded_T_250, _decoded_T_251) node _decoded_T_253 = bits(_decoded_T_248, 3, 2) node _decoded_T_254 = bits(_decoded_T_253, 0, 0) node _decoded_T_255 = bits(_decoded_T_253, 1, 1) node _decoded_T_256 = cat(_decoded_T_254, _decoded_T_255) node _decoded_T_257 = cat(_decoded_T_252, _decoded_T_256) node _decoded_T_258 = bits(_decoded_T_247, 5, 4) node _decoded_T_259 = bits(_decoded_T_258, 0, 0) node _decoded_T_260 = bits(_decoded_T_258, 1, 1) node _decoded_T_261 = cat(_decoded_T_259, _decoded_T_260) node _decoded_T_262 = cat(_decoded_T_257, _decoded_T_261) node _decoded_T_263 = cat(_decoded_T_246, _decoded_T_262) node decoded_2 = cat(_decoded_T_215, _decoded_T_263) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_0_3_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`0`[3], _io_resp_2_vc_sel_0_3_T node _io_resp_2_vc_sel_0_4_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`0`[4], _io_resp_2_vc_sel_0_4_T node _io_resp_2_vc_sel_0_5_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`0`[5], _io_resp_2_vc_sel_0_5_T node _io_resp_2_vc_sel_0_6_T = bits(decoded_2, 6, 6) connect io.resp.`2`.vc_sel.`0`[6], _io_resp_2_vc_sel_0_6_T node _io_resp_2_vc_sel_0_7_T = bits(decoded_2, 7, 7) connect io.resp.`2`.vc_sel.`0`[7], _io_resp_2_vc_sel_0_7_T node _io_resp_2_vc_sel_0_8_T = bits(decoded_2, 8, 8) connect io.resp.`2`.vc_sel.`0`[8], _io_resp_2_vc_sel_0_8_T node _io_resp_2_vc_sel_0_9_T = bits(decoded_2, 9, 9) connect io.resp.`2`.vc_sel.`0`[9], _io_resp_2_vc_sel_0_9_T node _io_resp_2_vc_sel_1_0_T = bits(decoded_2, 10, 10) connect io.resp.`2`.vc_sel.`1`[0], _io_resp_2_vc_sel_1_0_T node _io_resp_2_vc_sel_1_1_T = bits(decoded_2, 11, 11) connect io.resp.`2`.vc_sel.`1`[1], _io_resp_2_vc_sel_1_1_T node _io_resp_2_vc_sel_1_2_T = bits(decoded_2, 12, 12) connect io.resp.`2`.vc_sel.`1`[2], _io_resp_2_vc_sel_1_2_T node _io_resp_2_vc_sel_1_3_T = bits(decoded_2, 13, 13) connect io.resp.`2`.vc_sel.`1`[3], _io_resp_2_vc_sel_1_3_T node _io_resp_2_vc_sel_1_4_T = bits(decoded_2, 14, 14) connect io.resp.`2`.vc_sel.`1`[4], _io_resp_2_vc_sel_1_4_T node _io_resp_2_vc_sel_1_5_T = bits(decoded_2, 15, 15) connect io.resp.`2`.vc_sel.`1`[5], _io_resp_2_vc_sel_1_5_T node _io_resp_2_vc_sel_1_6_T = bits(decoded_2, 16, 16) connect io.resp.`2`.vc_sel.`1`[6], _io_resp_2_vc_sel_1_6_T node _io_resp_2_vc_sel_1_7_T = bits(decoded_2, 17, 17) connect io.resp.`2`.vc_sel.`1`[7], _io_resp_2_vc_sel_1_7_T node _io_resp_2_vc_sel_1_8_T = bits(decoded_2, 18, 18) connect io.resp.`2`.vc_sel.`1`[8], _io_resp_2_vc_sel_1_8_T node _io_resp_2_vc_sel_1_9_T = bits(decoded_2, 19, 19) connect io.resp.`2`.vc_sel.`1`[9], _io_resp_2_vc_sel_1_9_T node _io_resp_2_vc_sel_2_0_T = bits(decoded_2, 20, 20) connect io.resp.`2`.vc_sel.`2`[0], _io_resp_2_vc_sel_2_0_T node _io_resp_2_vc_sel_2_1_T = bits(decoded_2, 21, 21) connect io.resp.`2`.vc_sel.`2`[1], _io_resp_2_vc_sel_2_1_T node _io_resp_2_vc_sel_2_2_T = bits(decoded_2, 22, 22) connect io.resp.`2`.vc_sel.`2`[2], _io_resp_2_vc_sel_2_2_T node _io_resp_2_vc_sel_2_3_T = bits(decoded_2, 23, 23) connect io.resp.`2`.vc_sel.`2`[3], _io_resp_2_vc_sel_2_3_T node _io_resp_2_vc_sel_2_4_T = bits(decoded_2, 24, 24) connect io.resp.`2`.vc_sel.`2`[4], _io_resp_2_vc_sel_2_4_T node _io_resp_2_vc_sel_2_5_T = bits(decoded_2, 25, 25) connect io.resp.`2`.vc_sel.`2`[5], _io_resp_2_vc_sel_2_5_T node _io_resp_2_vc_sel_2_6_T = bits(decoded_2, 26, 26) connect io.resp.`2`.vc_sel.`2`[6], _io_resp_2_vc_sel_2_6_T node _io_resp_2_vc_sel_2_7_T = bits(decoded_2, 27, 27) connect io.resp.`2`.vc_sel.`2`[7], _io_resp_2_vc_sel_2_7_T node _io_resp_2_vc_sel_2_8_T = bits(decoded_2, 28, 28) connect io.resp.`2`.vc_sel.`2`[8], _io_resp_2_vc_sel_2_8_T node _io_resp_2_vc_sel_2_9_T = bits(decoded_2, 29, 29) connect io.resp.`2`.vc_sel.`2`[9], _io_resp_2_vc_sel_2_9_T extmodule plusarg_reader_134 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20
module RouteComputer_56( // @[RouteComputer.scala:29:7] input [3:0] io_req_2_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_2_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_2_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_2_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_1_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_1_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_1_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [1:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_8, // @[RouteComputer.scala:40:14] output io_resp_2_vc_sel_1_9, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_8, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_2_9, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_8, // @[RouteComputer.scala:40:14] output io_resp_1_vc_sel_0_9, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_1_9 // @[RouteComputer.scala:40:14] ); wire [16:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id[2:0], io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id[2]}; // @[pla.scala:78:21] wire [18:0] decoded_invInputs_1 = ~{io_req_1_bits_src_virt_id, io_req_1_bits_flow_vnet_id, io_req_1_bits_flow_ingress_node, io_req_1_bits_flow_ingress_node_id, io_req_1_bits_flow_egress_node, io_req_1_bits_flow_egress_node_id[2:1]}; // @[pla.scala:78:21] wire [15:0] _decoded_andMatrixOutputs_T_1 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_src_virt_id[1], decoded_invInputs_1[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_4 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], decoded_invInputs_1[1], decoded_invInputs_1[3], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_src_virt_id[2], decoded_invInputs_1[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_5 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_src_virt_id[2], decoded_invInputs_1[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_7 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2], decoded_invInputs_1[18]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_9 = {io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], decoded_invInputs_1[3], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[16], decoded_invInputs_1[17], io_req_1_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [15:0] _decoded_andMatrixOutputs_T_10 = {io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[13], decoded_invInputs_1[14], decoded_invInputs_1[16], decoded_invInputs_1[17], io_req_1_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:53] wire [1:0] decoded_invInputs_2 = ~(io_req_2_bits_src_virt_id[2:1]); // @[pla.scala:78:21] assign io_resp_2_vc_sel_1_8 = &{io_req_2_bits_flow_egress_node_id[0], decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_2_vc_sel_1_9 = &{io_req_2_bits_src_virt_id[0], decoded_invInputs_2[0], decoded_invInputs_2[1], io_req_2_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_1_vc_sel_2_2 = |{&{io_req_1_bits_flow_egress_node_id[0], decoded_invInputs_1[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_src_virt_id[1], decoded_invInputs_1[18]}, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_10}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_3 = |{&{io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1], decoded_invInputs_1[18]}, &_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_10}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_4 = |{&_decoded_andMatrixOutputs_T_5, &_decoded_andMatrixOutputs_T_10}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_5 = |{&{io_req_1_bits_flow_egress_node_id[0], io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[2], decoded_invInputs_1[18]}, &_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_10}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_6 = |{&_decoded_andMatrixOutputs_T_7, &_decoded_andMatrixOutputs_T_10}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_7 = |{&{io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_src_virt_id[0], io_req_1_bits_src_virt_id[1], io_req_1_bits_src_virt_id[2], decoded_invInputs_1[18]}, &_decoded_andMatrixOutputs_T_10}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_2_8 = &_decoded_andMatrixOutputs_T_10; // @[pla.scala:98:{53,70}] assign io_resp_1_vc_sel_2_9 = &{io_req_1_bits_flow_egress_node[1], decoded_invInputs_1[4], decoded_invInputs_1[5], io_req_1_bits_flow_ingress_node_id[0], io_req_1_bits_flow_ingress_node_id[1], decoded_invInputs_1[8], decoded_invInputs_1[9], decoded_invInputs_1[10], decoded_invInputs_1[11], io_req_1_bits_flow_vnet_id[0], decoded_invInputs_1[13], decoded_invInputs_1[14], io_req_1_bits_src_virt_id[0], decoded_invInputs_1[16], decoded_invInputs_1[17], io_req_1_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] assign io_resp_1_vc_sel_0_2 = |{&_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_3 = |{&_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_4 = |{&_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_5 = |{&_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_6 = |{&_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_7 = |{&_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_8 = |{&_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_1_vc_sel_0_9 = |{&_decoded_andMatrixOutputs_T_1, &_decoded_andMatrixOutputs_T_4, &_decoded_andMatrixOutputs_T_9}; // @[pla.scala:98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_1_9 = &{decoded_invInputs[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[3]}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_225 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_225( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MulFullRawFN_29 : output io : { flip a : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, flip b : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>}, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<48>}} node _notSigNaN_invalidExc_T = and(io.a.isInf, io.b.isZero) node _notSigNaN_invalidExc_T_1 = and(io.a.isZero, io.b.isInf) node notSigNaN_invalidExc = or(_notSigNaN_invalidExc_T, _notSigNaN_invalidExc_T_1) node notNaN_isInfOut = or(io.a.isInf, io.b.isInf) node notNaN_isZeroOut = or(io.a.isZero, io.b.isZero) node notNaN_signOut = xor(io.a.sign, io.b.sign) node _common_sExpOut_T = add(io.a.sExp, io.b.sExp) node _common_sExpOut_T_1 = tail(_common_sExpOut_T, 1) node _common_sExpOut_T_2 = asSInt(_common_sExpOut_T_1) node _common_sExpOut_T_3 = sub(_common_sExpOut_T_2, asSInt(UInt<10>(0h100))) node _common_sExpOut_T_4 = tail(_common_sExpOut_T_3, 1) node common_sExpOut = asSInt(_common_sExpOut_T_4) node _common_sigOut_T = mul(io.a.sig, io.b.sig) node common_sigOut = bits(_common_sigOut_T, 47, 0) node _io_invalidExc_T = bits(io.a.sig, 22, 22) node _io_invalidExc_T_1 = eq(_io_invalidExc_T, UInt<1>(0h0)) node _io_invalidExc_T_2 = and(io.a.isNaN, _io_invalidExc_T_1) node _io_invalidExc_T_3 = bits(io.b.sig, 22, 22) node _io_invalidExc_T_4 = eq(_io_invalidExc_T_3, UInt<1>(0h0)) node _io_invalidExc_T_5 = and(io.b.isNaN, _io_invalidExc_T_4) node _io_invalidExc_T_6 = or(_io_invalidExc_T_2, _io_invalidExc_T_5) node _io_invalidExc_T_7 = or(_io_invalidExc_T_6, notSigNaN_invalidExc) connect io.invalidExc, _io_invalidExc_T_7 connect io.rawOut.isInf, notNaN_isInfOut connect io.rawOut.isZero, notNaN_isZeroOut connect io.rawOut.sExp, common_sExpOut node _io_rawOut_isNaN_T = or(io.a.isNaN, io.b.isNaN) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.sign, notNaN_signOut connect io.rawOut.sig, common_sigOut
module MulFullRawFN_29( // @[MulRecFN.scala:47:7] input io_a_isNaN, // @[MulRecFN.scala:49:16] input io_a_isInf, // @[MulRecFN.scala:49:16] input io_a_isZero, // @[MulRecFN.scala:49:16] input io_a_sign, // @[MulRecFN.scala:49:16] input [9:0] io_a_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_a_sig, // @[MulRecFN.scala:49:16] input io_b_isNaN, // @[MulRecFN.scala:49:16] input io_b_isInf, // @[MulRecFN.scala:49:16] input io_b_isZero, // @[MulRecFN.scala:49:16] input io_b_sign, // @[MulRecFN.scala:49:16] input [9:0] io_b_sExp, // @[MulRecFN.scala:49:16] input [24:0] io_b_sig, // @[MulRecFN.scala:49:16] output io_invalidExc, // @[MulRecFN.scala:49:16] output io_rawOut_isNaN, // @[MulRecFN.scala:49:16] output io_rawOut_isInf, // @[MulRecFN.scala:49:16] output io_rawOut_isZero, // @[MulRecFN.scala:49:16] output io_rawOut_sign, // @[MulRecFN.scala:49:16] output [9:0] io_rawOut_sExp, // @[MulRecFN.scala:49:16] output [47:0] io_rawOut_sig // @[MulRecFN.scala:49:16] ); wire io_a_isNaN_0 = io_a_isNaN; // @[MulRecFN.scala:47:7] wire io_a_isInf_0 = io_a_isInf; // @[MulRecFN.scala:47:7] wire io_a_isZero_0 = io_a_isZero; // @[MulRecFN.scala:47:7] wire io_a_sign_0 = io_a_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_a_sExp_0 = io_a_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_a_sig_0 = io_a_sig; // @[MulRecFN.scala:47:7] wire io_b_isNaN_0 = io_b_isNaN; // @[MulRecFN.scala:47:7] wire io_b_isInf_0 = io_b_isInf; // @[MulRecFN.scala:47:7] wire io_b_isZero_0 = io_b_isZero; // @[MulRecFN.scala:47:7] wire io_b_sign_0 = io_b_sign; // @[MulRecFN.scala:47:7] wire [9:0] io_b_sExp_0 = io_b_sExp; // @[MulRecFN.scala:47:7] wire [24:0] io_b_sig_0 = io_b_sig; // @[MulRecFN.scala:47:7] wire _io_invalidExc_T_7; // @[MulRecFN.scala:66:71] wire _io_rawOut_isNaN_T; // @[MulRecFN.scala:70:35] wire notNaN_isInfOut; // @[MulRecFN.scala:59:38] wire notNaN_isZeroOut; // @[MulRecFN.scala:60:40] wire notNaN_signOut; // @[MulRecFN.scala:61:36] wire [9:0] common_sExpOut; // @[MulRecFN.scala:62:48] wire [47:0] common_sigOut; // @[MulRecFN.scala:63:46] wire io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] wire io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] wire io_rawOut_sign_0; // @[MulRecFN.scala:47:7] wire [9:0] io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] wire [47:0] io_rawOut_sig_0; // @[MulRecFN.scala:47:7] wire io_invalidExc_0; // @[MulRecFN.scala:47:7] wire _notSigNaN_invalidExc_T = io_a_isInf_0 & io_b_isZero_0; // @[MulRecFN.scala:47:7, :58:44] wire _notSigNaN_invalidExc_T_1 = io_a_isZero_0 & io_b_isInf_0; // @[MulRecFN.scala:47:7, :58:76] wire notSigNaN_invalidExc = _notSigNaN_invalidExc_T | _notSigNaN_invalidExc_T_1; // @[MulRecFN.scala:58:{44,60,76}] assign notNaN_isInfOut = io_a_isInf_0 | io_b_isInf_0; // @[MulRecFN.scala:47:7, :59:38] assign io_rawOut_isInf_0 = notNaN_isInfOut; // @[MulRecFN.scala:47:7, :59:38] assign notNaN_isZeroOut = io_a_isZero_0 | io_b_isZero_0; // @[MulRecFN.scala:47:7, :60:40] assign io_rawOut_isZero_0 = notNaN_isZeroOut; // @[MulRecFN.scala:47:7, :60:40] assign notNaN_signOut = io_a_sign_0 ^ io_b_sign_0; // @[MulRecFN.scala:47:7, :61:36] assign io_rawOut_sign_0 = notNaN_signOut; // @[MulRecFN.scala:47:7, :61:36] wire [10:0] _common_sExpOut_T = {io_a_sExp_0[9], io_a_sExp_0} + {io_b_sExp_0[9], io_b_sExp_0}; // @[MulRecFN.scala:47:7, :62:36] wire [9:0] _common_sExpOut_T_1 = _common_sExpOut_T[9:0]; // @[MulRecFN.scala:62:36] wire [9:0] _common_sExpOut_T_2 = _common_sExpOut_T_1; // @[MulRecFN.scala:62:36] wire [10:0] _common_sExpOut_T_3 = {_common_sExpOut_T_2[9], _common_sExpOut_T_2} - 11'h100; // @[MulRecFN.scala:62:{36,48}] wire [9:0] _common_sExpOut_T_4 = _common_sExpOut_T_3[9:0]; // @[MulRecFN.scala:62:48] assign common_sExpOut = _common_sExpOut_T_4; // @[MulRecFN.scala:62:48] assign io_rawOut_sExp_0 = common_sExpOut; // @[MulRecFN.scala:47:7, :62:48] wire [49:0] _common_sigOut_T = {25'h0, io_a_sig_0} * {25'h0, io_b_sig_0}; // @[MulRecFN.scala:47:7, :63:35] assign common_sigOut = _common_sigOut_T[47:0]; // @[MulRecFN.scala:63:{35,46}] assign io_rawOut_sig_0 = common_sigOut; // @[MulRecFN.scala:47:7, :63:46] wire _io_invalidExc_T = io_a_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_1 = ~_io_invalidExc_T; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_2 = io_a_isNaN_0 & _io_invalidExc_T_1; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_3 = io_b_sig_0[22]; // @[common.scala:82:56] wire _io_invalidExc_T_4 = ~_io_invalidExc_T_3; // @[common.scala:82:{49,56}] wire _io_invalidExc_T_5 = io_b_isNaN_0 & _io_invalidExc_T_4; // @[common.scala:82:{46,49}] wire _io_invalidExc_T_6 = _io_invalidExc_T_2 | _io_invalidExc_T_5; // @[common.scala:82:46] assign _io_invalidExc_T_7 = _io_invalidExc_T_6 | notSigNaN_invalidExc; // @[MulRecFN.scala:58:60, :66:{45,71}] assign io_invalidExc_0 = _io_invalidExc_T_7; // @[MulRecFN.scala:47:7, :66:71] assign _io_rawOut_isNaN_T = io_a_isNaN_0 | io_b_isNaN_0; // @[MulRecFN.scala:47:7, :70:35] assign io_rawOut_isNaN_0 = _io_rawOut_isNaN_T; // @[MulRecFN.scala:47:7, :70:35] assign io_invalidExc = io_invalidExc_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isNaN = io_rawOut_isNaN_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isInf = io_rawOut_isInf_0; // @[MulRecFN.scala:47:7] assign io_rawOut_isZero = io_rawOut_isZero_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sign = io_rawOut_sign_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sExp = io_rawOut_sExp_0; // @[MulRecFN.scala:47:7] assign io_rawOut_sig = io_rawOut_sig_0; // @[MulRecFN.scala:47:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_47 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_47( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] output io_q // @[ShiftReg.scala:36:14] ); wire io_d = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire _sync_2_T = 1'h1; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h1; // @[SynchronizerReg.scala:51:87, :54:22, :68:19] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module RouteComputer_2 : input clock : Clock input reset : Reset output io : { req : { flip `3` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip `2` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip `1` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}, flip `0` : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<4>, flow : { vnet_id : UInt<3>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<3>}}}}, resp : { `3` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `2` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `1` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}, `0` : { vc_sel : { `2` : UInt<1>[1], `1` : UInt<1>[1], `0` : UInt<1>[10]}}}} connect io.req.`0`.ready, UInt<1>(0h1) node addr_lo = cat(io.req.`0`.bits.flow.egress_node, io.req.`0`.bits.flow.egress_node_id) node addr_hi_hi = cat(io.req.`0`.bits.flow.vnet_id, io.req.`0`.bits.flow.ingress_node) node addr_hi = cat(addr_hi_hi, io.req.`0`.bits.flow.ingress_node_id) node _addr_T = cat(addr_hi, addr_lo) node addr = cat(io.req.`0`.bits.src_virt_id, _addr_T) wire decoded_plaInput : UInt<21> node decoded_invInputs = not(decoded_plaInput) wire decoded_plaOutput : UInt<10> node decoded_andMatrixOutputs_andMatrixInput_0 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_8 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_9 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_10 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_9, decoded_andMatrixOutputs_andMatrixInput_10) node decoded_andMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_6, decoded_andMatrixOutputs_andMatrixInput_7) node decoded_andMatrixOutputs_lo_hi = cat(decoded_andMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_andMatrixInput_8) node decoded_andMatrixOutputs_lo = cat(decoded_andMatrixOutputs_lo_hi, decoded_andMatrixOutputs_lo_lo) node decoded_andMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_3, decoded_andMatrixOutputs_andMatrixInput_4) node decoded_andMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_hi_lo_hi, decoded_andMatrixOutputs_andMatrixInput_5) node decoded_andMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0, decoded_andMatrixOutputs_andMatrixInput_1) node decoded_andMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2) node decoded_andMatrixOutputs_hi = cat(decoded_andMatrixOutputs_hi_hi, decoded_andMatrixOutputs_hi_lo) node _decoded_andMatrixOutputs_T = cat(decoded_andMatrixOutputs_hi, decoded_andMatrixOutputs_lo) node decoded_andMatrixOutputs_27_2 = andr(_decoded_andMatrixOutputs_T) node decoded_andMatrixOutputs_andMatrixInput_0_1 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_1 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_1 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_1 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_1 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_1 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_1 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_1 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_9_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_10_1 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_1, decoded_andMatrixOutputs_andMatrixInput_10_1) node decoded_andMatrixOutputs_lo_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_6_1, decoded_andMatrixOutputs_andMatrixInput_7_1) node decoded_andMatrixOutputs_lo_hi_1 = cat(decoded_andMatrixOutputs_lo_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_8_1) node decoded_andMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_lo_hi_1, decoded_andMatrixOutputs_lo_lo_1) node decoded_andMatrixOutputs_hi_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_1, decoded_andMatrixOutputs_andMatrixInput_4_1) node decoded_andMatrixOutputs_hi_lo_1 = cat(decoded_andMatrixOutputs_hi_lo_hi_1, decoded_andMatrixOutputs_andMatrixInput_5_1) node decoded_andMatrixOutputs_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_1, decoded_andMatrixOutputs_andMatrixInput_1_1) node decoded_andMatrixOutputs_hi_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_1) node decoded_andMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_hi_hi_1, decoded_andMatrixOutputs_hi_lo_1) node _decoded_andMatrixOutputs_T_1 = cat(decoded_andMatrixOutputs_hi_1, decoded_andMatrixOutputs_lo_1) node decoded_andMatrixOutputs_7_2 = andr(_decoded_andMatrixOutputs_T_1) node decoded_andMatrixOutputs_andMatrixInput_0_2 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_2 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_2 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_2 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_2 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_2 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_2 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_2 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_2 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_9_2 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_8_2, decoded_andMatrixOutputs_andMatrixInput_9_2) node decoded_andMatrixOutputs_lo_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_2, decoded_andMatrixOutputs_andMatrixInput_6_2) node decoded_andMatrixOutputs_lo_hi_2 = cat(decoded_andMatrixOutputs_lo_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_7_2) node decoded_andMatrixOutputs_lo_2 = cat(decoded_andMatrixOutputs_lo_hi_2, decoded_andMatrixOutputs_lo_lo_2) node decoded_andMatrixOutputs_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_2, decoded_andMatrixOutputs_andMatrixInput_4_2) node decoded_andMatrixOutputs_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_2, decoded_andMatrixOutputs_andMatrixInput_1_2) node decoded_andMatrixOutputs_hi_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_2) node decoded_andMatrixOutputs_hi_2 = cat(decoded_andMatrixOutputs_hi_hi_2, decoded_andMatrixOutputs_hi_lo_2) node _decoded_andMatrixOutputs_T_2 = cat(decoded_andMatrixOutputs_hi_2, decoded_andMatrixOutputs_lo_2) node decoded_andMatrixOutputs_14_2 = andr(_decoded_andMatrixOutputs_T_2) node decoded_andMatrixOutputs_andMatrixInput_0_3 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_3 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_3 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_3 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_3 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_3 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_3 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_3 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_8_3 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_9_3 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_8_3, decoded_andMatrixOutputs_andMatrixInput_9_3) node decoded_andMatrixOutputs_lo_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_3, decoded_andMatrixOutputs_andMatrixInput_6_3) node decoded_andMatrixOutputs_lo_hi_3 = cat(decoded_andMatrixOutputs_lo_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_7_3) node decoded_andMatrixOutputs_lo_3 = cat(decoded_andMatrixOutputs_lo_hi_3, decoded_andMatrixOutputs_lo_lo_3) node decoded_andMatrixOutputs_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_3, decoded_andMatrixOutputs_andMatrixInput_4_3) node decoded_andMatrixOutputs_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_3, decoded_andMatrixOutputs_andMatrixInput_1_3) node decoded_andMatrixOutputs_hi_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_3) node decoded_andMatrixOutputs_hi_3 = cat(decoded_andMatrixOutputs_hi_hi_3, decoded_andMatrixOutputs_hi_lo_3) node _decoded_andMatrixOutputs_T_3 = cat(decoded_andMatrixOutputs_hi_3, decoded_andMatrixOutputs_lo_3) node decoded_andMatrixOutputs_3_2 = andr(_decoded_andMatrixOutputs_T_3) node decoded_andMatrixOutputs_andMatrixInput_0_4 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_4 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_4 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_4 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_4 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_4 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_4 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_4 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_4 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_4 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_2 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_16 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_16, decoded_andMatrixOutputs_andMatrixInput_17) node decoded_andMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_andMatrixInput_14, decoded_andMatrixOutputs_andMatrixInput_15) node decoded_andMatrixOutputs_lo_lo_4 = cat(decoded_andMatrixOutputs_lo_lo_hi, decoded_andMatrixOutputs_lo_lo_lo) node decoded_andMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_12, decoded_andMatrixOutputs_andMatrixInput_13) node decoded_andMatrixOutputs_lo_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_9_4, decoded_andMatrixOutputs_andMatrixInput_10_2) node decoded_andMatrixOutputs_lo_hi_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_11) node decoded_andMatrixOutputs_lo_hi_4 = cat(decoded_andMatrixOutputs_lo_hi_hi_4, decoded_andMatrixOutputs_lo_hi_lo) node decoded_andMatrixOutputs_lo_4 = cat(decoded_andMatrixOutputs_lo_hi_4, decoded_andMatrixOutputs_lo_lo_4) node decoded_andMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_andMatrixInput_7_4, decoded_andMatrixOutputs_andMatrixInput_8_4) node decoded_andMatrixOutputs_hi_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_5_4, decoded_andMatrixOutputs_andMatrixInput_6_4) node decoded_andMatrixOutputs_hi_lo_4 = cat(decoded_andMatrixOutputs_hi_lo_hi_2, decoded_andMatrixOutputs_hi_lo_lo) node decoded_andMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_andMatrixInput_3_4, decoded_andMatrixOutputs_andMatrixInput_4_4) node decoded_andMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_andMatrixInput_0_4, decoded_andMatrixOutputs_andMatrixInput_1_4) node decoded_andMatrixOutputs_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_andMatrixInput_2_4) node decoded_andMatrixOutputs_hi_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_hi_4, decoded_andMatrixOutputs_hi_hi_lo) node decoded_andMatrixOutputs_hi_4 = cat(decoded_andMatrixOutputs_hi_hi_4, decoded_andMatrixOutputs_hi_lo_4) node _decoded_andMatrixOutputs_T_4 = cat(decoded_andMatrixOutputs_hi_4, decoded_andMatrixOutputs_lo_4) node decoded_andMatrixOutputs_4_2 = andr(_decoded_andMatrixOutputs_T_4) node decoded_andMatrixOutputs_andMatrixInput_0_5 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_5 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_5 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_5 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_5 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_5 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_5 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_5 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_5 = bits(decoded_plaInput, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_5 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_3 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_1 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_1 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_1 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_1 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_1 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_1 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_1 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_16_1, decoded_andMatrixOutputs_andMatrixInput_17_1) node decoded_andMatrixOutputs_lo_lo_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_14_1, decoded_andMatrixOutputs_andMatrixInput_15_1) node decoded_andMatrixOutputs_lo_lo_5 = cat(decoded_andMatrixOutputs_lo_lo_hi_1, decoded_andMatrixOutputs_lo_lo_lo_1) node decoded_andMatrixOutputs_lo_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_12_1, decoded_andMatrixOutputs_andMatrixInput_13_1) node decoded_andMatrixOutputs_lo_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_9_5, decoded_andMatrixOutputs_andMatrixInput_10_3) node decoded_andMatrixOutputs_lo_hi_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_11_1) node decoded_andMatrixOutputs_lo_hi_5 = cat(decoded_andMatrixOutputs_lo_hi_hi_5, decoded_andMatrixOutputs_lo_hi_lo_1) node decoded_andMatrixOutputs_lo_5 = cat(decoded_andMatrixOutputs_lo_hi_5, decoded_andMatrixOutputs_lo_lo_5) node decoded_andMatrixOutputs_hi_lo_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_7_5, decoded_andMatrixOutputs_andMatrixInput_8_5) node decoded_andMatrixOutputs_hi_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_5_5, decoded_andMatrixOutputs_andMatrixInput_6_5) node decoded_andMatrixOutputs_hi_lo_5 = cat(decoded_andMatrixOutputs_hi_lo_hi_3, decoded_andMatrixOutputs_hi_lo_lo_1) node decoded_andMatrixOutputs_hi_hi_lo_1 = cat(decoded_andMatrixOutputs_andMatrixInput_3_5, decoded_andMatrixOutputs_andMatrixInput_4_5) node decoded_andMatrixOutputs_hi_hi_hi_hi_1 = cat(decoded_andMatrixOutputs_andMatrixInput_0_5, decoded_andMatrixOutputs_andMatrixInput_1_5) node decoded_andMatrixOutputs_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_1, decoded_andMatrixOutputs_andMatrixInput_2_5) node decoded_andMatrixOutputs_hi_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_hi_5, decoded_andMatrixOutputs_hi_hi_lo_1) node decoded_andMatrixOutputs_hi_5 = cat(decoded_andMatrixOutputs_hi_hi_5, decoded_andMatrixOutputs_hi_lo_5) node _decoded_andMatrixOutputs_T_5 = cat(decoded_andMatrixOutputs_hi_5, decoded_andMatrixOutputs_lo_5) node decoded_andMatrixOutputs_0_2 = andr(_decoded_andMatrixOutputs_T_5) node decoded_andMatrixOutputs_andMatrixInput_0_6 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_6 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_6 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_6 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_6 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_6 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_6 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_6 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_6 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_6 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_4 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_2 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_2 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_2 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_2 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_2 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_16_2 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_2 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_16_2, decoded_andMatrixOutputs_andMatrixInput_17_2) node decoded_andMatrixOutputs_lo_lo_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_14_2, decoded_andMatrixOutputs_andMatrixInput_15_2) node decoded_andMatrixOutputs_lo_lo_6 = cat(decoded_andMatrixOutputs_lo_lo_hi_2, decoded_andMatrixOutputs_lo_lo_lo_2) node decoded_andMatrixOutputs_lo_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_12_2, decoded_andMatrixOutputs_andMatrixInput_13_2) node decoded_andMatrixOutputs_lo_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_9_6, decoded_andMatrixOutputs_andMatrixInput_10_4) node decoded_andMatrixOutputs_lo_hi_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_11_2) node decoded_andMatrixOutputs_lo_hi_6 = cat(decoded_andMatrixOutputs_lo_hi_hi_6, decoded_andMatrixOutputs_lo_hi_lo_2) node decoded_andMatrixOutputs_lo_6 = cat(decoded_andMatrixOutputs_lo_hi_6, decoded_andMatrixOutputs_lo_lo_6) node decoded_andMatrixOutputs_hi_lo_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_7_6, decoded_andMatrixOutputs_andMatrixInput_8_6) node decoded_andMatrixOutputs_hi_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_5_6, decoded_andMatrixOutputs_andMatrixInput_6_6) node decoded_andMatrixOutputs_hi_lo_6 = cat(decoded_andMatrixOutputs_hi_lo_hi_4, decoded_andMatrixOutputs_hi_lo_lo_2) node decoded_andMatrixOutputs_hi_hi_lo_2 = cat(decoded_andMatrixOutputs_andMatrixInput_3_6, decoded_andMatrixOutputs_andMatrixInput_4_6) node decoded_andMatrixOutputs_hi_hi_hi_hi_2 = cat(decoded_andMatrixOutputs_andMatrixInput_0_6, decoded_andMatrixOutputs_andMatrixInput_1_6) node decoded_andMatrixOutputs_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_2, decoded_andMatrixOutputs_andMatrixInput_2_6) node decoded_andMatrixOutputs_hi_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_hi_6, decoded_andMatrixOutputs_hi_hi_lo_2) node decoded_andMatrixOutputs_hi_6 = cat(decoded_andMatrixOutputs_hi_hi_6, decoded_andMatrixOutputs_hi_lo_6) node _decoded_andMatrixOutputs_T_6 = cat(decoded_andMatrixOutputs_hi_6, decoded_andMatrixOutputs_lo_6) node decoded_andMatrixOutputs_47_2 = andr(_decoded_andMatrixOutputs_T_6) node decoded_andMatrixOutputs_andMatrixInput_0_7 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_7 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_7 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_7 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_7 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_7 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_7 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_7 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_7 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_7 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_5 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_11_3 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_3 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_3 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_3 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_3 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_3 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_3 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_16_3, decoded_andMatrixOutputs_andMatrixInput_17_3) node decoded_andMatrixOutputs_lo_lo_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_14_3, decoded_andMatrixOutputs_andMatrixInput_15_3) node decoded_andMatrixOutputs_lo_lo_7 = cat(decoded_andMatrixOutputs_lo_lo_hi_3, decoded_andMatrixOutputs_lo_lo_lo_3) node decoded_andMatrixOutputs_lo_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_12_3, decoded_andMatrixOutputs_andMatrixInput_13_3) node decoded_andMatrixOutputs_lo_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_9_7, decoded_andMatrixOutputs_andMatrixInput_10_5) node decoded_andMatrixOutputs_lo_hi_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_11_3) node decoded_andMatrixOutputs_lo_hi_7 = cat(decoded_andMatrixOutputs_lo_hi_hi_7, decoded_andMatrixOutputs_lo_hi_lo_3) node decoded_andMatrixOutputs_lo_7 = cat(decoded_andMatrixOutputs_lo_hi_7, decoded_andMatrixOutputs_lo_lo_7) node decoded_andMatrixOutputs_hi_lo_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_7_7, decoded_andMatrixOutputs_andMatrixInput_8_7) node decoded_andMatrixOutputs_hi_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_5_7, decoded_andMatrixOutputs_andMatrixInput_6_7) node decoded_andMatrixOutputs_hi_lo_7 = cat(decoded_andMatrixOutputs_hi_lo_hi_5, decoded_andMatrixOutputs_hi_lo_lo_3) node decoded_andMatrixOutputs_hi_hi_lo_3 = cat(decoded_andMatrixOutputs_andMatrixInput_3_7, decoded_andMatrixOutputs_andMatrixInput_4_7) node decoded_andMatrixOutputs_hi_hi_hi_hi_3 = cat(decoded_andMatrixOutputs_andMatrixInput_0_7, decoded_andMatrixOutputs_andMatrixInput_1_7) node decoded_andMatrixOutputs_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_3, decoded_andMatrixOutputs_andMatrixInput_2_7) node decoded_andMatrixOutputs_hi_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_hi_7, decoded_andMatrixOutputs_hi_hi_lo_3) node decoded_andMatrixOutputs_hi_7 = cat(decoded_andMatrixOutputs_hi_hi_7, decoded_andMatrixOutputs_hi_lo_7) node _decoded_andMatrixOutputs_T_7 = cat(decoded_andMatrixOutputs_hi_7, decoded_andMatrixOutputs_lo_7) node decoded_andMatrixOutputs_41_2 = andr(_decoded_andMatrixOutputs_T_7) node decoded_andMatrixOutputs_andMatrixInput_0_8 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_8 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_8 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_8 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_8 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_8 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_8 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_8 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_8 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_8 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_6 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_4 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_4 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_4 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_4 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_15_4 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_14_4, decoded_andMatrixOutputs_andMatrixInput_15_4) node decoded_andMatrixOutputs_lo_lo_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_12_4, decoded_andMatrixOutputs_andMatrixInput_13_4) node decoded_andMatrixOutputs_lo_lo_8 = cat(decoded_andMatrixOutputs_lo_lo_hi_4, decoded_andMatrixOutputs_lo_lo_lo_4) node decoded_andMatrixOutputs_lo_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_10_6, decoded_andMatrixOutputs_andMatrixInput_11_4) node decoded_andMatrixOutputs_lo_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_8_8, decoded_andMatrixOutputs_andMatrixInput_9_8) node decoded_andMatrixOutputs_lo_hi_8 = cat(decoded_andMatrixOutputs_lo_hi_hi_8, decoded_andMatrixOutputs_lo_hi_lo_4) node decoded_andMatrixOutputs_lo_8 = cat(decoded_andMatrixOutputs_lo_hi_8, decoded_andMatrixOutputs_lo_lo_8) node decoded_andMatrixOutputs_hi_lo_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_6_8, decoded_andMatrixOutputs_andMatrixInput_7_8) node decoded_andMatrixOutputs_hi_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_4_8, decoded_andMatrixOutputs_andMatrixInput_5_8) node decoded_andMatrixOutputs_hi_lo_8 = cat(decoded_andMatrixOutputs_hi_lo_hi_6, decoded_andMatrixOutputs_hi_lo_lo_4) node decoded_andMatrixOutputs_hi_hi_lo_4 = cat(decoded_andMatrixOutputs_andMatrixInput_2_8, decoded_andMatrixOutputs_andMatrixInput_3_8) node decoded_andMatrixOutputs_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_8, decoded_andMatrixOutputs_andMatrixInput_1_8) node decoded_andMatrixOutputs_hi_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_hi_8, decoded_andMatrixOutputs_hi_hi_lo_4) node decoded_andMatrixOutputs_hi_8 = cat(decoded_andMatrixOutputs_hi_hi_8, decoded_andMatrixOutputs_hi_lo_8) node _decoded_andMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_hi_8, decoded_andMatrixOutputs_lo_8) node decoded_andMatrixOutputs_6_2 = andr(_decoded_andMatrixOutputs_T_8) node decoded_andMatrixOutputs_andMatrixInput_0_9 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_9 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_9 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_9 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_9 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_9 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_9 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_9 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_9 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_9 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_7 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_5 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_5 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_5 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_5 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_5 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_14_5, decoded_andMatrixOutputs_andMatrixInput_15_5) node decoded_andMatrixOutputs_lo_lo_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_12_5, decoded_andMatrixOutputs_andMatrixInput_13_5) node decoded_andMatrixOutputs_lo_lo_9 = cat(decoded_andMatrixOutputs_lo_lo_hi_5, decoded_andMatrixOutputs_lo_lo_lo_5) node decoded_andMatrixOutputs_lo_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_10_7, decoded_andMatrixOutputs_andMatrixInput_11_5) node decoded_andMatrixOutputs_lo_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_8_9, decoded_andMatrixOutputs_andMatrixInput_9_9) node decoded_andMatrixOutputs_lo_hi_9 = cat(decoded_andMatrixOutputs_lo_hi_hi_9, decoded_andMatrixOutputs_lo_hi_lo_5) node decoded_andMatrixOutputs_lo_9 = cat(decoded_andMatrixOutputs_lo_hi_9, decoded_andMatrixOutputs_lo_lo_9) node decoded_andMatrixOutputs_hi_lo_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_6_9, decoded_andMatrixOutputs_andMatrixInput_7_9) node decoded_andMatrixOutputs_hi_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_4_9, decoded_andMatrixOutputs_andMatrixInput_5_9) node decoded_andMatrixOutputs_hi_lo_9 = cat(decoded_andMatrixOutputs_hi_lo_hi_7, decoded_andMatrixOutputs_hi_lo_lo_5) node decoded_andMatrixOutputs_hi_hi_lo_5 = cat(decoded_andMatrixOutputs_andMatrixInput_2_9, decoded_andMatrixOutputs_andMatrixInput_3_9) node decoded_andMatrixOutputs_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_9, decoded_andMatrixOutputs_andMatrixInput_1_9) node decoded_andMatrixOutputs_hi_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_hi_9, decoded_andMatrixOutputs_hi_hi_lo_5) node decoded_andMatrixOutputs_hi_9 = cat(decoded_andMatrixOutputs_hi_hi_9, decoded_andMatrixOutputs_hi_lo_9) node _decoded_andMatrixOutputs_T_9 = cat(decoded_andMatrixOutputs_hi_9, decoded_andMatrixOutputs_lo_9) node decoded_andMatrixOutputs_49_2 = andr(_decoded_andMatrixOutputs_T_9) node decoded_andMatrixOutputs_andMatrixInput_0_10 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_10 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_10 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_10 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_10 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_10 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_10 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_10 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_10 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_10 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_8 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_6 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_6 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_6 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_6 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_6 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_16_4 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_4 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_16_4, decoded_andMatrixOutputs_andMatrixInput_17_4) node decoded_andMatrixOutputs_lo_lo_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_14_6, decoded_andMatrixOutputs_andMatrixInput_15_6) node decoded_andMatrixOutputs_lo_lo_10 = cat(decoded_andMatrixOutputs_lo_lo_hi_6, decoded_andMatrixOutputs_lo_lo_lo_6) node decoded_andMatrixOutputs_lo_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_12_6, decoded_andMatrixOutputs_andMatrixInput_13_6) node decoded_andMatrixOutputs_lo_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_9_10, decoded_andMatrixOutputs_andMatrixInput_10_8) node decoded_andMatrixOutputs_lo_hi_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_11_6) node decoded_andMatrixOutputs_lo_hi_10 = cat(decoded_andMatrixOutputs_lo_hi_hi_10, decoded_andMatrixOutputs_lo_hi_lo_6) node decoded_andMatrixOutputs_lo_10 = cat(decoded_andMatrixOutputs_lo_hi_10, decoded_andMatrixOutputs_lo_lo_10) node decoded_andMatrixOutputs_hi_lo_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_7_10, decoded_andMatrixOutputs_andMatrixInput_8_10) node decoded_andMatrixOutputs_hi_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_5_10, decoded_andMatrixOutputs_andMatrixInput_6_10) node decoded_andMatrixOutputs_hi_lo_10 = cat(decoded_andMatrixOutputs_hi_lo_hi_8, decoded_andMatrixOutputs_hi_lo_lo_6) node decoded_andMatrixOutputs_hi_hi_lo_6 = cat(decoded_andMatrixOutputs_andMatrixInput_3_10, decoded_andMatrixOutputs_andMatrixInput_4_10) node decoded_andMatrixOutputs_hi_hi_hi_hi_4 = cat(decoded_andMatrixOutputs_andMatrixInput_0_10, decoded_andMatrixOutputs_andMatrixInput_1_10) node decoded_andMatrixOutputs_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_4, decoded_andMatrixOutputs_andMatrixInput_2_10) node decoded_andMatrixOutputs_hi_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_hi_10, decoded_andMatrixOutputs_hi_hi_lo_6) node decoded_andMatrixOutputs_hi_10 = cat(decoded_andMatrixOutputs_hi_hi_10, decoded_andMatrixOutputs_hi_lo_10) node _decoded_andMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_hi_10, decoded_andMatrixOutputs_lo_10) node decoded_andMatrixOutputs_44_2 = andr(_decoded_andMatrixOutputs_T_10) node decoded_andMatrixOutputs_andMatrixInput_0_11 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_11 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_11 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_11 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_11 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_11 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_11 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_11 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_11 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_11 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_9 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_7 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_7 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_7 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_7 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_7 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_5 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_5 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_16_5, decoded_andMatrixOutputs_andMatrixInput_17_5) node decoded_andMatrixOutputs_lo_lo_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_14_7, decoded_andMatrixOutputs_andMatrixInput_15_7) node decoded_andMatrixOutputs_lo_lo_11 = cat(decoded_andMatrixOutputs_lo_lo_hi_7, decoded_andMatrixOutputs_lo_lo_lo_7) node decoded_andMatrixOutputs_lo_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_12_7, decoded_andMatrixOutputs_andMatrixInput_13_7) node decoded_andMatrixOutputs_lo_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_9_11, decoded_andMatrixOutputs_andMatrixInput_10_9) node decoded_andMatrixOutputs_lo_hi_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_11_7) node decoded_andMatrixOutputs_lo_hi_11 = cat(decoded_andMatrixOutputs_lo_hi_hi_11, decoded_andMatrixOutputs_lo_hi_lo_7) node decoded_andMatrixOutputs_lo_11 = cat(decoded_andMatrixOutputs_lo_hi_11, decoded_andMatrixOutputs_lo_lo_11) node decoded_andMatrixOutputs_hi_lo_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_7_11, decoded_andMatrixOutputs_andMatrixInput_8_11) node decoded_andMatrixOutputs_hi_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_5_11, decoded_andMatrixOutputs_andMatrixInput_6_11) node decoded_andMatrixOutputs_hi_lo_11 = cat(decoded_andMatrixOutputs_hi_lo_hi_9, decoded_andMatrixOutputs_hi_lo_lo_7) node decoded_andMatrixOutputs_hi_hi_lo_7 = cat(decoded_andMatrixOutputs_andMatrixInput_3_11, decoded_andMatrixOutputs_andMatrixInput_4_11) node decoded_andMatrixOutputs_hi_hi_hi_hi_5 = cat(decoded_andMatrixOutputs_andMatrixInput_0_11, decoded_andMatrixOutputs_andMatrixInput_1_11) node decoded_andMatrixOutputs_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_5, decoded_andMatrixOutputs_andMatrixInput_2_11) node decoded_andMatrixOutputs_hi_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_hi_11, decoded_andMatrixOutputs_hi_hi_lo_7) node decoded_andMatrixOutputs_hi_11 = cat(decoded_andMatrixOutputs_hi_hi_11, decoded_andMatrixOutputs_hi_lo_11) node _decoded_andMatrixOutputs_T_11 = cat(decoded_andMatrixOutputs_hi_11, decoded_andMatrixOutputs_lo_11) node decoded_andMatrixOutputs_39_2 = andr(_decoded_andMatrixOutputs_T_11) node decoded_andMatrixOutputs_andMatrixInput_0_12 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_12 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_12 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_12 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_12 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_12 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_12 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_12 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_12 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_12 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_10 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_8 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_8 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_8 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_8 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_15_8 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_14_8, decoded_andMatrixOutputs_andMatrixInput_15_8) node decoded_andMatrixOutputs_lo_lo_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_12_8, decoded_andMatrixOutputs_andMatrixInput_13_8) node decoded_andMatrixOutputs_lo_lo_12 = cat(decoded_andMatrixOutputs_lo_lo_hi_8, decoded_andMatrixOutputs_lo_lo_lo_8) node decoded_andMatrixOutputs_lo_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_10_10, decoded_andMatrixOutputs_andMatrixInput_11_8) node decoded_andMatrixOutputs_lo_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_8_12, decoded_andMatrixOutputs_andMatrixInput_9_12) node decoded_andMatrixOutputs_lo_hi_12 = cat(decoded_andMatrixOutputs_lo_hi_hi_12, decoded_andMatrixOutputs_lo_hi_lo_8) node decoded_andMatrixOutputs_lo_12 = cat(decoded_andMatrixOutputs_lo_hi_12, decoded_andMatrixOutputs_lo_lo_12) node decoded_andMatrixOutputs_hi_lo_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_6_12, decoded_andMatrixOutputs_andMatrixInput_7_12) node decoded_andMatrixOutputs_hi_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_4_12, decoded_andMatrixOutputs_andMatrixInput_5_12) node decoded_andMatrixOutputs_hi_lo_12 = cat(decoded_andMatrixOutputs_hi_lo_hi_10, decoded_andMatrixOutputs_hi_lo_lo_8) node decoded_andMatrixOutputs_hi_hi_lo_8 = cat(decoded_andMatrixOutputs_andMatrixInput_2_12, decoded_andMatrixOutputs_andMatrixInput_3_12) node decoded_andMatrixOutputs_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_12, decoded_andMatrixOutputs_andMatrixInput_1_12) node decoded_andMatrixOutputs_hi_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_hi_12, decoded_andMatrixOutputs_hi_hi_lo_8) node decoded_andMatrixOutputs_hi_12 = cat(decoded_andMatrixOutputs_hi_hi_12, decoded_andMatrixOutputs_hi_lo_12) node _decoded_andMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_hi_12, decoded_andMatrixOutputs_lo_12) node decoded_andMatrixOutputs_20_2 = andr(_decoded_andMatrixOutputs_T_12) node decoded_andMatrixOutputs_andMatrixInput_0_13 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_13 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_13 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_13 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_13 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_13 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_13 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_13 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_13 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_13 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_11 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_9 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_9 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_9 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_9 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_9 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_14_9, decoded_andMatrixOutputs_andMatrixInput_15_9) node decoded_andMatrixOutputs_lo_lo_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_12_9, decoded_andMatrixOutputs_andMatrixInput_13_9) node decoded_andMatrixOutputs_lo_lo_13 = cat(decoded_andMatrixOutputs_lo_lo_hi_9, decoded_andMatrixOutputs_lo_lo_lo_9) node decoded_andMatrixOutputs_lo_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_10_11, decoded_andMatrixOutputs_andMatrixInput_11_9) node decoded_andMatrixOutputs_lo_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_8_13, decoded_andMatrixOutputs_andMatrixInput_9_13) node decoded_andMatrixOutputs_lo_hi_13 = cat(decoded_andMatrixOutputs_lo_hi_hi_13, decoded_andMatrixOutputs_lo_hi_lo_9) node decoded_andMatrixOutputs_lo_13 = cat(decoded_andMatrixOutputs_lo_hi_13, decoded_andMatrixOutputs_lo_lo_13) node decoded_andMatrixOutputs_hi_lo_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_6_13, decoded_andMatrixOutputs_andMatrixInput_7_13) node decoded_andMatrixOutputs_hi_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_4_13, decoded_andMatrixOutputs_andMatrixInput_5_13) node decoded_andMatrixOutputs_hi_lo_13 = cat(decoded_andMatrixOutputs_hi_lo_hi_11, decoded_andMatrixOutputs_hi_lo_lo_9) node decoded_andMatrixOutputs_hi_hi_lo_9 = cat(decoded_andMatrixOutputs_andMatrixInput_2_13, decoded_andMatrixOutputs_andMatrixInput_3_13) node decoded_andMatrixOutputs_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_13, decoded_andMatrixOutputs_andMatrixInput_1_13) node decoded_andMatrixOutputs_hi_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_hi_13, decoded_andMatrixOutputs_hi_hi_lo_9) node decoded_andMatrixOutputs_hi_13 = cat(decoded_andMatrixOutputs_hi_hi_13, decoded_andMatrixOutputs_hi_lo_13) node _decoded_andMatrixOutputs_T_13 = cat(decoded_andMatrixOutputs_hi_13, decoded_andMatrixOutputs_lo_13) node decoded_andMatrixOutputs_43_2 = andr(_decoded_andMatrixOutputs_T_13) node decoded_andMatrixOutputs_andMatrixInput_0_14 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_14 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_14 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_14 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_14 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_14 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_14 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_14 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_14 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_14 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_12 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_10 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_10 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_10 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_10 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_10 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_16_6 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_6 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_16_6, decoded_andMatrixOutputs_andMatrixInput_17_6) node decoded_andMatrixOutputs_lo_lo_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_14_10, decoded_andMatrixOutputs_andMatrixInput_15_10) node decoded_andMatrixOutputs_lo_lo_14 = cat(decoded_andMatrixOutputs_lo_lo_hi_10, decoded_andMatrixOutputs_lo_lo_lo_10) node decoded_andMatrixOutputs_lo_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_12_10, decoded_andMatrixOutputs_andMatrixInput_13_10) node decoded_andMatrixOutputs_lo_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_9_14, decoded_andMatrixOutputs_andMatrixInput_10_12) node decoded_andMatrixOutputs_lo_hi_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_11_10) node decoded_andMatrixOutputs_lo_hi_14 = cat(decoded_andMatrixOutputs_lo_hi_hi_14, decoded_andMatrixOutputs_lo_hi_lo_10) node decoded_andMatrixOutputs_lo_14 = cat(decoded_andMatrixOutputs_lo_hi_14, decoded_andMatrixOutputs_lo_lo_14) node decoded_andMatrixOutputs_hi_lo_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_7_14, decoded_andMatrixOutputs_andMatrixInput_8_14) node decoded_andMatrixOutputs_hi_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_5_14, decoded_andMatrixOutputs_andMatrixInput_6_14) node decoded_andMatrixOutputs_hi_lo_14 = cat(decoded_andMatrixOutputs_hi_lo_hi_12, decoded_andMatrixOutputs_hi_lo_lo_10) node decoded_andMatrixOutputs_hi_hi_lo_10 = cat(decoded_andMatrixOutputs_andMatrixInput_3_14, decoded_andMatrixOutputs_andMatrixInput_4_14) node decoded_andMatrixOutputs_hi_hi_hi_hi_6 = cat(decoded_andMatrixOutputs_andMatrixInput_0_14, decoded_andMatrixOutputs_andMatrixInput_1_14) node decoded_andMatrixOutputs_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_6, decoded_andMatrixOutputs_andMatrixInput_2_14) node decoded_andMatrixOutputs_hi_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_hi_14, decoded_andMatrixOutputs_hi_hi_lo_10) node decoded_andMatrixOutputs_hi_14 = cat(decoded_andMatrixOutputs_hi_hi_14, decoded_andMatrixOutputs_hi_lo_14) node _decoded_andMatrixOutputs_T_14 = cat(decoded_andMatrixOutputs_hi_14, decoded_andMatrixOutputs_lo_14) node decoded_andMatrixOutputs_15_2 = andr(_decoded_andMatrixOutputs_T_14) node decoded_andMatrixOutputs_andMatrixInput_0_15 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_15 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_15 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_15 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_15 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_15 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_15 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_15 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_15 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_15 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_13 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_11 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_11 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_11 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_11 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_11 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_7 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_17_7 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_16_7, decoded_andMatrixOutputs_andMatrixInput_17_7) node decoded_andMatrixOutputs_lo_lo_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_14_11, decoded_andMatrixOutputs_andMatrixInput_15_11) node decoded_andMatrixOutputs_lo_lo_15 = cat(decoded_andMatrixOutputs_lo_lo_hi_11, decoded_andMatrixOutputs_lo_lo_lo_11) node decoded_andMatrixOutputs_lo_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_12_11, decoded_andMatrixOutputs_andMatrixInput_13_11) node decoded_andMatrixOutputs_lo_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_9_15, decoded_andMatrixOutputs_andMatrixInput_10_13) node decoded_andMatrixOutputs_lo_hi_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_11_11) node decoded_andMatrixOutputs_lo_hi_15 = cat(decoded_andMatrixOutputs_lo_hi_hi_15, decoded_andMatrixOutputs_lo_hi_lo_11) node decoded_andMatrixOutputs_lo_15 = cat(decoded_andMatrixOutputs_lo_hi_15, decoded_andMatrixOutputs_lo_lo_15) node decoded_andMatrixOutputs_hi_lo_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_7_15, decoded_andMatrixOutputs_andMatrixInput_8_15) node decoded_andMatrixOutputs_hi_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_5_15, decoded_andMatrixOutputs_andMatrixInput_6_15) node decoded_andMatrixOutputs_hi_lo_15 = cat(decoded_andMatrixOutputs_hi_lo_hi_13, decoded_andMatrixOutputs_hi_lo_lo_11) node decoded_andMatrixOutputs_hi_hi_lo_11 = cat(decoded_andMatrixOutputs_andMatrixInput_3_15, decoded_andMatrixOutputs_andMatrixInput_4_15) node decoded_andMatrixOutputs_hi_hi_hi_hi_7 = cat(decoded_andMatrixOutputs_andMatrixInput_0_15, decoded_andMatrixOutputs_andMatrixInput_1_15) node decoded_andMatrixOutputs_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_7, decoded_andMatrixOutputs_andMatrixInput_2_15) node decoded_andMatrixOutputs_hi_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_hi_15, decoded_andMatrixOutputs_hi_hi_lo_11) node decoded_andMatrixOutputs_hi_15 = cat(decoded_andMatrixOutputs_hi_hi_15, decoded_andMatrixOutputs_hi_lo_15) node _decoded_andMatrixOutputs_T_15 = cat(decoded_andMatrixOutputs_hi_15, decoded_andMatrixOutputs_lo_15) node decoded_andMatrixOutputs_5_2 = andr(_decoded_andMatrixOutputs_T_15) node decoded_andMatrixOutputs_andMatrixInput_0_16 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_16 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_16 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_16 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_16 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_16 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_16 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_16 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_16 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_16 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_14 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_12 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_12 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_12 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_12 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_12 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_8 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_8 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_16_8, decoded_andMatrixOutputs_andMatrixInput_17_8) node decoded_andMatrixOutputs_lo_lo_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_14_12, decoded_andMatrixOutputs_andMatrixInput_15_12) node decoded_andMatrixOutputs_lo_lo_16 = cat(decoded_andMatrixOutputs_lo_lo_hi_12, decoded_andMatrixOutputs_lo_lo_lo_12) node decoded_andMatrixOutputs_lo_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_12_12, decoded_andMatrixOutputs_andMatrixInput_13_12) node decoded_andMatrixOutputs_lo_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_9_16, decoded_andMatrixOutputs_andMatrixInput_10_14) node decoded_andMatrixOutputs_lo_hi_hi_16 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_11_12) node decoded_andMatrixOutputs_lo_hi_16 = cat(decoded_andMatrixOutputs_lo_hi_hi_16, decoded_andMatrixOutputs_lo_hi_lo_12) node decoded_andMatrixOutputs_lo_16 = cat(decoded_andMatrixOutputs_lo_hi_16, decoded_andMatrixOutputs_lo_lo_16) node decoded_andMatrixOutputs_hi_lo_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_7_16, decoded_andMatrixOutputs_andMatrixInput_8_16) node decoded_andMatrixOutputs_hi_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_5_16, decoded_andMatrixOutputs_andMatrixInput_6_16) node decoded_andMatrixOutputs_hi_lo_16 = cat(decoded_andMatrixOutputs_hi_lo_hi_14, decoded_andMatrixOutputs_hi_lo_lo_12) node decoded_andMatrixOutputs_hi_hi_lo_12 = cat(decoded_andMatrixOutputs_andMatrixInput_3_16, decoded_andMatrixOutputs_andMatrixInput_4_16) node decoded_andMatrixOutputs_hi_hi_hi_hi_8 = cat(decoded_andMatrixOutputs_andMatrixInput_0_16, decoded_andMatrixOutputs_andMatrixInput_1_16) node decoded_andMatrixOutputs_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_8, decoded_andMatrixOutputs_andMatrixInput_2_16) node decoded_andMatrixOutputs_hi_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_hi_16, decoded_andMatrixOutputs_hi_hi_lo_12) node decoded_andMatrixOutputs_hi_16 = cat(decoded_andMatrixOutputs_hi_hi_16, decoded_andMatrixOutputs_hi_lo_16) node _decoded_andMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_hi_16, decoded_andMatrixOutputs_lo_16) node decoded_andMatrixOutputs_10_2 = andr(_decoded_andMatrixOutputs_T_16) node decoded_andMatrixOutputs_andMatrixInput_0_17 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_17 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_17 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_17 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_17 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_17 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_17 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_17 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_17 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_17 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_15 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_11_13 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_12_13 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_13_13 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_14_13 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_15_13 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_16_9 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_17_9 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_16_9, decoded_andMatrixOutputs_andMatrixInput_17_9) node decoded_andMatrixOutputs_lo_lo_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_14_13, decoded_andMatrixOutputs_andMatrixInput_15_13) node decoded_andMatrixOutputs_lo_lo_17 = cat(decoded_andMatrixOutputs_lo_lo_hi_13, decoded_andMatrixOutputs_lo_lo_lo_13) node decoded_andMatrixOutputs_lo_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_12_13, decoded_andMatrixOutputs_andMatrixInput_13_13) node decoded_andMatrixOutputs_lo_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_9_17, decoded_andMatrixOutputs_andMatrixInput_10_15) node decoded_andMatrixOutputs_lo_hi_hi_17 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_11_13) node decoded_andMatrixOutputs_lo_hi_17 = cat(decoded_andMatrixOutputs_lo_hi_hi_17, decoded_andMatrixOutputs_lo_hi_lo_13) node decoded_andMatrixOutputs_lo_17 = cat(decoded_andMatrixOutputs_lo_hi_17, decoded_andMatrixOutputs_lo_lo_17) node decoded_andMatrixOutputs_hi_lo_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_7_17, decoded_andMatrixOutputs_andMatrixInput_8_17) node decoded_andMatrixOutputs_hi_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_5_17, decoded_andMatrixOutputs_andMatrixInput_6_17) node decoded_andMatrixOutputs_hi_lo_17 = cat(decoded_andMatrixOutputs_hi_lo_hi_15, decoded_andMatrixOutputs_hi_lo_lo_13) node decoded_andMatrixOutputs_hi_hi_lo_13 = cat(decoded_andMatrixOutputs_andMatrixInput_3_17, decoded_andMatrixOutputs_andMatrixInput_4_17) node decoded_andMatrixOutputs_hi_hi_hi_hi_9 = cat(decoded_andMatrixOutputs_andMatrixInput_0_17, decoded_andMatrixOutputs_andMatrixInput_1_17) node decoded_andMatrixOutputs_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_9, decoded_andMatrixOutputs_andMatrixInput_2_17) node decoded_andMatrixOutputs_hi_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_hi_17, decoded_andMatrixOutputs_hi_hi_lo_13) node decoded_andMatrixOutputs_hi_17 = cat(decoded_andMatrixOutputs_hi_hi_17, decoded_andMatrixOutputs_hi_lo_17) node _decoded_andMatrixOutputs_T_17 = cat(decoded_andMatrixOutputs_hi_17, decoded_andMatrixOutputs_lo_17) node decoded_andMatrixOutputs_45_2 = andr(_decoded_andMatrixOutputs_T_17) node decoded_andMatrixOutputs_andMatrixInput_0_18 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_18 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_18 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_18 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_4_18 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_5_18 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_6_18 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_7_18 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_8_18 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_9_18 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_10_16 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_11_14 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_12_14 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_13_14 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_14_14 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_15_14 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_14_14, decoded_andMatrixOutputs_andMatrixInput_15_14) node decoded_andMatrixOutputs_lo_lo_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_12_14, decoded_andMatrixOutputs_andMatrixInput_13_14) node decoded_andMatrixOutputs_lo_lo_18 = cat(decoded_andMatrixOutputs_lo_lo_hi_14, decoded_andMatrixOutputs_lo_lo_lo_14) node decoded_andMatrixOutputs_lo_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_10_16, decoded_andMatrixOutputs_andMatrixInput_11_14) node decoded_andMatrixOutputs_lo_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_8_18, decoded_andMatrixOutputs_andMatrixInput_9_18) node decoded_andMatrixOutputs_lo_hi_18 = cat(decoded_andMatrixOutputs_lo_hi_hi_18, decoded_andMatrixOutputs_lo_hi_lo_14) node decoded_andMatrixOutputs_lo_18 = cat(decoded_andMatrixOutputs_lo_hi_18, decoded_andMatrixOutputs_lo_lo_18) node decoded_andMatrixOutputs_hi_lo_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_6_18, decoded_andMatrixOutputs_andMatrixInput_7_18) node decoded_andMatrixOutputs_hi_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_4_18, decoded_andMatrixOutputs_andMatrixInput_5_18) node decoded_andMatrixOutputs_hi_lo_18 = cat(decoded_andMatrixOutputs_hi_lo_hi_16, decoded_andMatrixOutputs_hi_lo_lo_14) node decoded_andMatrixOutputs_hi_hi_lo_14 = cat(decoded_andMatrixOutputs_andMatrixInput_2_18, decoded_andMatrixOutputs_andMatrixInput_3_18) node decoded_andMatrixOutputs_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_18, decoded_andMatrixOutputs_andMatrixInput_1_18) node decoded_andMatrixOutputs_hi_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_hi_18, decoded_andMatrixOutputs_hi_hi_lo_14) node decoded_andMatrixOutputs_hi_18 = cat(decoded_andMatrixOutputs_hi_hi_18, decoded_andMatrixOutputs_hi_lo_18) node _decoded_andMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_hi_18, decoded_andMatrixOutputs_lo_18) node decoded_andMatrixOutputs_26_2 = andr(_decoded_andMatrixOutputs_T_18) node decoded_andMatrixOutputs_andMatrixInput_0_19 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_19 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_19 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_19 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_19 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_19 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_19 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_19 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_19 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_19 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_17 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_15 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_15 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_15 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_15 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_15 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_14_15, decoded_andMatrixOutputs_andMatrixInput_15_15) node decoded_andMatrixOutputs_lo_lo_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_12_15, decoded_andMatrixOutputs_andMatrixInput_13_15) node decoded_andMatrixOutputs_lo_lo_19 = cat(decoded_andMatrixOutputs_lo_lo_hi_15, decoded_andMatrixOutputs_lo_lo_lo_15) node decoded_andMatrixOutputs_lo_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_10_17, decoded_andMatrixOutputs_andMatrixInput_11_15) node decoded_andMatrixOutputs_lo_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_8_19, decoded_andMatrixOutputs_andMatrixInput_9_19) node decoded_andMatrixOutputs_lo_hi_19 = cat(decoded_andMatrixOutputs_lo_hi_hi_19, decoded_andMatrixOutputs_lo_hi_lo_15) node decoded_andMatrixOutputs_lo_19 = cat(decoded_andMatrixOutputs_lo_hi_19, decoded_andMatrixOutputs_lo_lo_19) node decoded_andMatrixOutputs_hi_lo_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_6_19, decoded_andMatrixOutputs_andMatrixInput_7_19) node decoded_andMatrixOutputs_hi_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_4_19, decoded_andMatrixOutputs_andMatrixInput_5_19) node decoded_andMatrixOutputs_hi_lo_19 = cat(decoded_andMatrixOutputs_hi_lo_hi_17, decoded_andMatrixOutputs_hi_lo_lo_15) node decoded_andMatrixOutputs_hi_hi_lo_15 = cat(decoded_andMatrixOutputs_andMatrixInput_2_19, decoded_andMatrixOutputs_andMatrixInput_3_19) node decoded_andMatrixOutputs_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_0_19, decoded_andMatrixOutputs_andMatrixInput_1_19) node decoded_andMatrixOutputs_hi_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_hi_19, decoded_andMatrixOutputs_hi_hi_lo_15) node decoded_andMatrixOutputs_hi_19 = cat(decoded_andMatrixOutputs_hi_hi_19, decoded_andMatrixOutputs_hi_lo_19) node _decoded_andMatrixOutputs_T_19 = cat(decoded_andMatrixOutputs_hi_19, decoded_andMatrixOutputs_lo_19) node decoded_andMatrixOutputs_28_2 = andr(_decoded_andMatrixOutputs_T_19) node decoded_andMatrixOutputs_andMatrixInput_0_20 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_20 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_20 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_20 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_20 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_20 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_20 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_20 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_8_20 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_9_20 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_10_18 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_9_20, decoded_andMatrixOutputs_andMatrixInput_10_18) node decoded_andMatrixOutputs_lo_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_6_20, decoded_andMatrixOutputs_andMatrixInput_7_20) node decoded_andMatrixOutputs_lo_hi_20 = cat(decoded_andMatrixOutputs_lo_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_8_20) node decoded_andMatrixOutputs_lo_20 = cat(decoded_andMatrixOutputs_lo_hi_20, decoded_andMatrixOutputs_lo_lo_20) node decoded_andMatrixOutputs_hi_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_3_20, decoded_andMatrixOutputs_andMatrixInput_4_20) node decoded_andMatrixOutputs_hi_lo_20 = cat(decoded_andMatrixOutputs_hi_lo_hi_18, decoded_andMatrixOutputs_andMatrixInput_5_20) node decoded_andMatrixOutputs_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_20, decoded_andMatrixOutputs_andMatrixInput_1_20) node decoded_andMatrixOutputs_hi_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_2_20) node decoded_andMatrixOutputs_hi_20 = cat(decoded_andMatrixOutputs_hi_hi_20, decoded_andMatrixOutputs_hi_lo_20) node _decoded_andMatrixOutputs_T_20 = cat(decoded_andMatrixOutputs_hi_20, decoded_andMatrixOutputs_lo_20) node decoded_andMatrixOutputs_8_2 = andr(_decoded_andMatrixOutputs_T_20) node decoded_andMatrixOutputs_andMatrixInput_0_21 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_21 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_21 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_21 = bits(decoded_plaInput, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_21 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_21 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_21 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_21 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_21 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_9_21 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_10_19 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_9_21, decoded_andMatrixOutputs_andMatrixInput_10_19) node decoded_andMatrixOutputs_lo_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_6_21, decoded_andMatrixOutputs_andMatrixInput_7_21) node decoded_andMatrixOutputs_lo_hi_21 = cat(decoded_andMatrixOutputs_lo_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_8_21) node decoded_andMatrixOutputs_lo_21 = cat(decoded_andMatrixOutputs_lo_hi_21, decoded_andMatrixOutputs_lo_lo_21) node decoded_andMatrixOutputs_hi_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_3_21, decoded_andMatrixOutputs_andMatrixInput_4_21) node decoded_andMatrixOutputs_hi_lo_21 = cat(decoded_andMatrixOutputs_hi_lo_hi_19, decoded_andMatrixOutputs_andMatrixInput_5_21) node decoded_andMatrixOutputs_hi_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_21, decoded_andMatrixOutputs_andMatrixInput_1_21) node decoded_andMatrixOutputs_hi_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_21) node decoded_andMatrixOutputs_hi_21 = cat(decoded_andMatrixOutputs_hi_hi_21, decoded_andMatrixOutputs_hi_lo_21) node _decoded_andMatrixOutputs_T_21 = cat(decoded_andMatrixOutputs_hi_21, decoded_andMatrixOutputs_lo_21) node decoded_andMatrixOutputs_16_2 = andr(_decoded_andMatrixOutputs_T_21) node decoded_andMatrixOutputs_andMatrixInput_0_22 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_22 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_22 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_22 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_22 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_22 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_22 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_22 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_22 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_9_22 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_8_22, decoded_andMatrixOutputs_andMatrixInput_9_22) node decoded_andMatrixOutputs_lo_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_5_22, decoded_andMatrixOutputs_andMatrixInput_6_22) node decoded_andMatrixOutputs_lo_hi_22 = cat(decoded_andMatrixOutputs_lo_hi_hi_22, decoded_andMatrixOutputs_andMatrixInput_7_22) node decoded_andMatrixOutputs_lo_22 = cat(decoded_andMatrixOutputs_lo_hi_22, decoded_andMatrixOutputs_lo_lo_22) node decoded_andMatrixOutputs_hi_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_3_22, decoded_andMatrixOutputs_andMatrixInput_4_22) node decoded_andMatrixOutputs_hi_hi_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_0_22, decoded_andMatrixOutputs_andMatrixInput_1_22) node decoded_andMatrixOutputs_hi_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_hi_22, decoded_andMatrixOutputs_andMatrixInput_2_22) node decoded_andMatrixOutputs_hi_22 = cat(decoded_andMatrixOutputs_hi_hi_22, decoded_andMatrixOutputs_hi_lo_22) node _decoded_andMatrixOutputs_T_22 = cat(decoded_andMatrixOutputs_hi_22, decoded_andMatrixOutputs_lo_22) node decoded_andMatrixOutputs_29_2 = andr(_decoded_andMatrixOutputs_T_22) node decoded_andMatrixOutputs_andMatrixInput_0_23 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_23 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_23 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_23 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_23 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_23 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_23 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_23 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_8_23 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_9_23 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_8_23, decoded_andMatrixOutputs_andMatrixInput_9_23) node decoded_andMatrixOutputs_lo_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_5_23, decoded_andMatrixOutputs_andMatrixInput_6_23) node decoded_andMatrixOutputs_lo_hi_23 = cat(decoded_andMatrixOutputs_lo_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_7_23) node decoded_andMatrixOutputs_lo_23 = cat(decoded_andMatrixOutputs_lo_hi_23, decoded_andMatrixOutputs_lo_lo_23) node decoded_andMatrixOutputs_hi_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_3_23, decoded_andMatrixOutputs_andMatrixInput_4_23) node decoded_andMatrixOutputs_hi_hi_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_0_23, decoded_andMatrixOutputs_andMatrixInput_1_23) node decoded_andMatrixOutputs_hi_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_hi_23, decoded_andMatrixOutputs_andMatrixInput_2_23) node decoded_andMatrixOutputs_hi_23 = cat(decoded_andMatrixOutputs_hi_hi_23, decoded_andMatrixOutputs_hi_lo_23) node _decoded_andMatrixOutputs_T_23 = cat(decoded_andMatrixOutputs_hi_23, decoded_andMatrixOutputs_lo_23) node decoded_andMatrixOutputs_11_2 = andr(_decoded_andMatrixOutputs_T_23) node decoded_andMatrixOutputs_andMatrixInput_0_24 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_24 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_24 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_24 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_24 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_24 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_24 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_24 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_24 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_24 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_20 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_16 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_16 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_16 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_16 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_16 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_16_10 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_10 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_16_10, decoded_andMatrixOutputs_andMatrixInput_17_10) node decoded_andMatrixOutputs_lo_lo_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_14_16, decoded_andMatrixOutputs_andMatrixInput_15_16) node decoded_andMatrixOutputs_lo_lo_24 = cat(decoded_andMatrixOutputs_lo_lo_hi_16, decoded_andMatrixOutputs_lo_lo_lo_16) node decoded_andMatrixOutputs_lo_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_12_16, decoded_andMatrixOutputs_andMatrixInput_13_16) node decoded_andMatrixOutputs_lo_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_9_24, decoded_andMatrixOutputs_andMatrixInput_10_20) node decoded_andMatrixOutputs_lo_hi_hi_24 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_11_16) node decoded_andMatrixOutputs_lo_hi_24 = cat(decoded_andMatrixOutputs_lo_hi_hi_24, decoded_andMatrixOutputs_lo_hi_lo_16) node decoded_andMatrixOutputs_lo_24 = cat(decoded_andMatrixOutputs_lo_hi_24, decoded_andMatrixOutputs_lo_lo_24) node decoded_andMatrixOutputs_hi_lo_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_7_24, decoded_andMatrixOutputs_andMatrixInput_8_24) node decoded_andMatrixOutputs_hi_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_5_24, decoded_andMatrixOutputs_andMatrixInput_6_24) node decoded_andMatrixOutputs_hi_lo_24 = cat(decoded_andMatrixOutputs_hi_lo_hi_20, decoded_andMatrixOutputs_hi_lo_lo_16) node decoded_andMatrixOutputs_hi_hi_lo_16 = cat(decoded_andMatrixOutputs_andMatrixInput_3_24, decoded_andMatrixOutputs_andMatrixInput_4_24) node decoded_andMatrixOutputs_hi_hi_hi_hi_10 = cat(decoded_andMatrixOutputs_andMatrixInput_0_24, decoded_andMatrixOutputs_andMatrixInput_1_24) node decoded_andMatrixOutputs_hi_hi_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_10, decoded_andMatrixOutputs_andMatrixInput_2_24) node decoded_andMatrixOutputs_hi_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_hi_24, decoded_andMatrixOutputs_hi_hi_lo_16) node decoded_andMatrixOutputs_hi_24 = cat(decoded_andMatrixOutputs_hi_hi_24, decoded_andMatrixOutputs_hi_lo_24) node _decoded_andMatrixOutputs_T_24 = cat(decoded_andMatrixOutputs_hi_24, decoded_andMatrixOutputs_lo_24) node decoded_andMatrixOutputs_34_2 = andr(_decoded_andMatrixOutputs_T_24) node decoded_andMatrixOutputs_andMatrixInput_0_25 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_25 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_25 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_25 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_25 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_25 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_25 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_25 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_25 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_25 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_21 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_11_17 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_17 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_17 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_17 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_17 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_11 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_11 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_16_11, decoded_andMatrixOutputs_andMatrixInput_17_11) node decoded_andMatrixOutputs_lo_lo_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_14_17, decoded_andMatrixOutputs_andMatrixInput_15_17) node decoded_andMatrixOutputs_lo_lo_25 = cat(decoded_andMatrixOutputs_lo_lo_hi_17, decoded_andMatrixOutputs_lo_lo_lo_17) node decoded_andMatrixOutputs_lo_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_12_17, decoded_andMatrixOutputs_andMatrixInput_13_17) node decoded_andMatrixOutputs_lo_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_9_25, decoded_andMatrixOutputs_andMatrixInput_10_21) node decoded_andMatrixOutputs_lo_hi_hi_25 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_11_17) node decoded_andMatrixOutputs_lo_hi_25 = cat(decoded_andMatrixOutputs_lo_hi_hi_25, decoded_andMatrixOutputs_lo_hi_lo_17) node decoded_andMatrixOutputs_lo_25 = cat(decoded_andMatrixOutputs_lo_hi_25, decoded_andMatrixOutputs_lo_lo_25) node decoded_andMatrixOutputs_hi_lo_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_7_25, decoded_andMatrixOutputs_andMatrixInput_8_25) node decoded_andMatrixOutputs_hi_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_5_25, decoded_andMatrixOutputs_andMatrixInput_6_25) node decoded_andMatrixOutputs_hi_lo_25 = cat(decoded_andMatrixOutputs_hi_lo_hi_21, decoded_andMatrixOutputs_hi_lo_lo_17) node decoded_andMatrixOutputs_hi_hi_lo_17 = cat(decoded_andMatrixOutputs_andMatrixInput_3_25, decoded_andMatrixOutputs_andMatrixInput_4_25) node decoded_andMatrixOutputs_hi_hi_hi_hi_11 = cat(decoded_andMatrixOutputs_andMatrixInput_0_25, decoded_andMatrixOutputs_andMatrixInput_1_25) node decoded_andMatrixOutputs_hi_hi_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_11, decoded_andMatrixOutputs_andMatrixInput_2_25) node decoded_andMatrixOutputs_hi_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_hi_25, decoded_andMatrixOutputs_hi_hi_lo_17) node decoded_andMatrixOutputs_hi_25 = cat(decoded_andMatrixOutputs_hi_hi_25, decoded_andMatrixOutputs_hi_lo_25) node _decoded_andMatrixOutputs_T_25 = cat(decoded_andMatrixOutputs_hi_25, decoded_andMatrixOutputs_lo_25) node decoded_andMatrixOutputs_19_2 = andr(_decoded_andMatrixOutputs_T_25) node decoded_andMatrixOutputs_andMatrixInput_0_26 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_26 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_26 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_26 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_26 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_26 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_26 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_26 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_26 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_26 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_22 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_18 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_18 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_18 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_18 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_18 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_16_12 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_12 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_16_12, decoded_andMatrixOutputs_andMatrixInput_17_12) node decoded_andMatrixOutputs_lo_lo_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_14_18, decoded_andMatrixOutputs_andMatrixInput_15_18) node decoded_andMatrixOutputs_lo_lo_26 = cat(decoded_andMatrixOutputs_lo_lo_hi_18, decoded_andMatrixOutputs_lo_lo_lo_18) node decoded_andMatrixOutputs_lo_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_12_18, decoded_andMatrixOutputs_andMatrixInput_13_18) node decoded_andMatrixOutputs_lo_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_9_26, decoded_andMatrixOutputs_andMatrixInput_10_22) node decoded_andMatrixOutputs_lo_hi_hi_26 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_11_18) node decoded_andMatrixOutputs_lo_hi_26 = cat(decoded_andMatrixOutputs_lo_hi_hi_26, decoded_andMatrixOutputs_lo_hi_lo_18) node decoded_andMatrixOutputs_lo_26 = cat(decoded_andMatrixOutputs_lo_hi_26, decoded_andMatrixOutputs_lo_lo_26) node decoded_andMatrixOutputs_hi_lo_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_7_26, decoded_andMatrixOutputs_andMatrixInput_8_26) node decoded_andMatrixOutputs_hi_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_5_26, decoded_andMatrixOutputs_andMatrixInput_6_26) node decoded_andMatrixOutputs_hi_lo_26 = cat(decoded_andMatrixOutputs_hi_lo_hi_22, decoded_andMatrixOutputs_hi_lo_lo_18) node decoded_andMatrixOutputs_hi_hi_lo_18 = cat(decoded_andMatrixOutputs_andMatrixInput_3_26, decoded_andMatrixOutputs_andMatrixInput_4_26) node decoded_andMatrixOutputs_hi_hi_hi_hi_12 = cat(decoded_andMatrixOutputs_andMatrixInput_0_26, decoded_andMatrixOutputs_andMatrixInput_1_26) node decoded_andMatrixOutputs_hi_hi_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_12, decoded_andMatrixOutputs_andMatrixInput_2_26) node decoded_andMatrixOutputs_hi_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_hi_26, decoded_andMatrixOutputs_hi_hi_lo_18) node decoded_andMatrixOutputs_hi_26 = cat(decoded_andMatrixOutputs_hi_hi_26, decoded_andMatrixOutputs_hi_lo_26) node _decoded_andMatrixOutputs_T_26 = cat(decoded_andMatrixOutputs_hi_26, decoded_andMatrixOutputs_lo_26) node decoded_andMatrixOutputs_13_2 = andr(_decoded_andMatrixOutputs_T_26) node decoded_andMatrixOutputs_andMatrixInput_0_27 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_27 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_27 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_27 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_27 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_27 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_27 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_27 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_27 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_27 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_23 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_19 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_19 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_19 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_19 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_19 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_13 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_13 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_16_13, decoded_andMatrixOutputs_andMatrixInput_17_13) node decoded_andMatrixOutputs_lo_lo_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_14_19, decoded_andMatrixOutputs_andMatrixInput_15_19) node decoded_andMatrixOutputs_lo_lo_27 = cat(decoded_andMatrixOutputs_lo_lo_hi_19, decoded_andMatrixOutputs_lo_lo_lo_19) node decoded_andMatrixOutputs_lo_hi_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_12_19, decoded_andMatrixOutputs_andMatrixInput_13_19) node decoded_andMatrixOutputs_lo_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_9_27, decoded_andMatrixOutputs_andMatrixInput_10_23) node decoded_andMatrixOutputs_lo_hi_hi_27 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_11_19) node decoded_andMatrixOutputs_lo_hi_27 = cat(decoded_andMatrixOutputs_lo_hi_hi_27, decoded_andMatrixOutputs_lo_hi_lo_19) node decoded_andMatrixOutputs_lo_27 = cat(decoded_andMatrixOutputs_lo_hi_27, decoded_andMatrixOutputs_lo_lo_27) node decoded_andMatrixOutputs_hi_lo_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_7_27, decoded_andMatrixOutputs_andMatrixInput_8_27) node decoded_andMatrixOutputs_hi_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_5_27, decoded_andMatrixOutputs_andMatrixInput_6_27) node decoded_andMatrixOutputs_hi_lo_27 = cat(decoded_andMatrixOutputs_hi_lo_hi_23, decoded_andMatrixOutputs_hi_lo_lo_19) node decoded_andMatrixOutputs_hi_hi_lo_19 = cat(decoded_andMatrixOutputs_andMatrixInput_3_27, decoded_andMatrixOutputs_andMatrixInput_4_27) node decoded_andMatrixOutputs_hi_hi_hi_hi_13 = cat(decoded_andMatrixOutputs_andMatrixInput_0_27, decoded_andMatrixOutputs_andMatrixInput_1_27) node decoded_andMatrixOutputs_hi_hi_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_13, decoded_andMatrixOutputs_andMatrixInput_2_27) node decoded_andMatrixOutputs_hi_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_hi_27, decoded_andMatrixOutputs_hi_hi_lo_19) node decoded_andMatrixOutputs_hi_27 = cat(decoded_andMatrixOutputs_hi_hi_27, decoded_andMatrixOutputs_hi_lo_27) node _decoded_andMatrixOutputs_T_27 = cat(decoded_andMatrixOutputs_hi_27, decoded_andMatrixOutputs_lo_27) node decoded_andMatrixOutputs_40_2 = andr(_decoded_andMatrixOutputs_T_27) node decoded_andMatrixOutputs_andMatrixInput_0_28 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_28 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_28 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_28 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_28 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_28 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_28 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_28 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_28 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_28 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_24 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_20 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_20 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_20 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_20 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_20 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_16_14 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_14 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_16_14, decoded_andMatrixOutputs_andMatrixInput_17_14) node decoded_andMatrixOutputs_lo_lo_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_14_20, decoded_andMatrixOutputs_andMatrixInput_15_20) node decoded_andMatrixOutputs_lo_lo_28 = cat(decoded_andMatrixOutputs_lo_lo_hi_20, decoded_andMatrixOutputs_lo_lo_lo_20) node decoded_andMatrixOutputs_lo_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_12_20, decoded_andMatrixOutputs_andMatrixInput_13_20) node decoded_andMatrixOutputs_lo_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_9_28, decoded_andMatrixOutputs_andMatrixInput_10_24) node decoded_andMatrixOutputs_lo_hi_hi_28 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_11_20) node decoded_andMatrixOutputs_lo_hi_28 = cat(decoded_andMatrixOutputs_lo_hi_hi_28, decoded_andMatrixOutputs_lo_hi_lo_20) node decoded_andMatrixOutputs_lo_28 = cat(decoded_andMatrixOutputs_lo_hi_28, decoded_andMatrixOutputs_lo_lo_28) node decoded_andMatrixOutputs_hi_lo_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_7_28, decoded_andMatrixOutputs_andMatrixInput_8_28) node decoded_andMatrixOutputs_hi_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_5_28, decoded_andMatrixOutputs_andMatrixInput_6_28) node decoded_andMatrixOutputs_hi_lo_28 = cat(decoded_andMatrixOutputs_hi_lo_hi_24, decoded_andMatrixOutputs_hi_lo_lo_20) node decoded_andMatrixOutputs_hi_hi_lo_20 = cat(decoded_andMatrixOutputs_andMatrixInput_3_28, decoded_andMatrixOutputs_andMatrixInput_4_28) node decoded_andMatrixOutputs_hi_hi_hi_hi_14 = cat(decoded_andMatrixOutputs_andMatrixInput_0_28, decoded_andMatrixOutputs_andMatrixInput_1_28) node decoded_andMatrixOutputs_hi_hi_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_14, decoded_andMatrixOutputs_andMatrixInput_2_28) node decoded_andMatrixOutputs_hi_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_hi_28, decoded_andMatrixOutputs_hi_hi_lo_20) node decoded_andMatrixOutputs_hi_28 = cat(decoded_andMatrixOutputs_hi_hi_28, decoded_andMatrixOutputs_hi_lo_28) node _decoded_andMatrixOutputs_T_28 = cat(decoded_andMatrixOutputs_hi_28, decoded_andMatrixOutputs_lo_28) node decoded_andMatrixOutputs_37_2 = andr(_decoded_andMatrixOutputs_T_28) node decoded_andMatrixOutputs_andMatrixInput_0_29 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_29 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_29 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_29 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_29 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_29 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_29 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_29 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_29 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_29 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_25 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_21 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_21 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_21 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_21 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_21 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_15 = bits(decoded_invInputs, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_17_15 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_16_15, decoded_andMatrixOutputs_andMatrixInput_17_15) node decoded_andMatrixOutputs_lo_lo_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_14_21, decoded_andMatrixOutputs_andMatrixInput_15_21) node decoded_andMatrixOutputs_lo_lo_29 = cat(decoded_andMatrixOutputs_lo_lo_hi_21, decoded_andMatrixOutputs_lo_lo_lo_21) node decoded_andMatrixOutputs_lo_hi_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_12_21, decoded_andMatrixOutputs_andMatrixInput_13_21) node decoded_andMatrixOutputs_lo_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_9_29, decoded_andMatrixOutputs_andMatrixInput_10_25) node decoded_andMatrixOutputs_lo_hi_hi_29 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_11_21) node decoded_andMatrixOutputs_lo_hi_29 = cat(decoded_andMatrixOutputs_lo_hi_hi_29, decoded_andMatrixOutputs_lo_hi_lo_21) node decoded_andMatrixOutputs_lo_29 = cat(decoded_andMatrixOutputs_lo_hi_29, decoded_andMatrixOutputs_lo_lo_29) node decoded_andMatrixOutputs_hi_lo_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_7_29, decoded_andMatrixOutputs_andMatrixInput_8_29) node decoded_andMatrixOutputs_hi_lo_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_5_29, decoded_andMatrixOutputs_andMatrixInput_6_29) node decoded_andMatrixOutputs_hi_lo_29 = cat(decoded_andMatrixOutputs_hi_lo_hi_25, decoded_andMatrixOutputs_hi_lo_lo_21) node decoded_andMatrixOutputs_hi_hi_lo_21 = cat(decoded_andMatrixOutputs_andMatrixInput_3_29, decoded_andMatrixOutputs_andMatrixInput_4_29) node decoded_andMatrixOutputs_hi_hi_hi_hi_15 = cat(decoded_andMatrixOutputs_andMatrixInput_0_29, decoded_andMatrixOutputs_andMatrixInput_1_29) node decoded_andMatrixOutputs_hi_hi_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_15, decoded_andMatrixOutputs_andMatrixInput_2_29) node decoded_andMatrixOutputs_hi_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_hi_29, decoded_andMatrixOutputs_hi_hi_lo_21) node decoded_andMatrixOutputs_hi_29 = cat(decoded_andMatrixOutputs_hi_hi_29, decoded_andMatrixOutputs_hi_lo_29) node _decoded_andMatrixOutputs_T_29 = cat(decoded_andMatrixOutputs_hi_29, decoded_andMatrixOutputs_lo_29) node decoded_andMatrixOutputs_38_2 = andr(_decoded_andMatrixOutputs_T_29) node decoded_andMatrixOutputs_andMatrixInput_0_30 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_30 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_30 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_30 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_30 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_30 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_30 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_30 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_30 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_30 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_26 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_22 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_22 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_22 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_22 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_22 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_16 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_16 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_16_16, decoded_andMatrixOutputs_andMatrixInput_17_16) node decoded_andMatrixOutputs_lo_lo_hi_22 = cat(decoded_andMatrixOutputs_andMatrixInput_14_22, decoded_andMatrixOutputs_andMatrixInput_15_22) node decoded_andMatrixOutputs_lo_lo_30 = cat(decoded_andMatrixOutputs_lo_lo_hi_22, decoded_andMatrixOutputs_lo_lo_lo_22) node decoded_andMatrixOutputs_lo_hi_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_12_22, decoded_andMatrixOutputs_andMatrixInput_13_22) node decoded_andMatrixOutputs_lo_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_9_30, decoded_andMatrixOutputs_andMatrixInput_10_26) node decoded_andMatrixOutputs_lo_hi_hi_30 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_16, decoded_andMatrixOutputs_andMatrixInput_11_22) node decoded_andMatrixOutputs_lo_hi_30 = cat(decoded_andMatrixOutputs_lo_hi_hi_30, decoded_andMatrixOutputs_lo_hi_lo_22) node decoded_andMatrixOutputs_lo_30 = cat(decoded_andMatrixOutputs_lo_hi_30, decoded_andMatrixOutputs_lo_lo_30) node decoded_andMatrixOutputs_hi_lo_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_7_30, decoded_andMatrixOutputs_andMatrixInput_8_30) node decoded_andMatrixOutputs_hi_lo_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_5_30, decoded_andMatrixOutputs_andMatrixInput_6_30) node decoded_andMatrixOutputs_hi_lo_30 = cat(decoded_andMatrixOutputs_hi_lo_hi_26, decoded_andMatrixOutputs_hi_lo_lo_22) node decoded_andMatrixOutputs_hi_hi_lo_22 = cat(decoded_andMatrixOutputs_andMatrixInput_3_30, decoded_andMatrixOutputs_andMatrixInput_4_30) node decoded_andMatrixOutputs_hi_hi_hi_hi_16 = cat(decoded_andMatrixOutputs_andMatrixInput_0_30, decoded_andMatrixOutputs_andMatrixInput_1_30) node decoded_andMatrixOutputs_hi_hi_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_16, decoded_andMatrixOutputs_andMatrixInput_2_30) node decoded_andMatrixOutputs_hi_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_hi_30, decoded_andMatrixOutputs_hi_hi_lo_22) node decoded_andMatrixOutputs_hi_30 = cat(decoded_andMatrixOutputs_hi_hi_30, decoded_andMatrixOutputs_hi_lo_30) node _decoded_andMatrixOutputs_T_30 = cat(decoded_andMatrixOutputs_hi_30, decoded_andMatrixOutputs_lo_30) node decoded_andMatrixOutputs_12_2 = andr(_decoded_andMatrixOutputs_T_30) node decoded_andMatrixOutputs_andMatrixInput_0_31 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_31 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_31 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_31 = bits(decoded_plaInput, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_4_31 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_5_31 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_6_31 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_7_31 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_8_31 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_9_31 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_10_27 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_11_23 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_12_23 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_13_23 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_14_23 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_15_23 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_16_17 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_17_17 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_16_17, decoded_andMatrixOutputs_andMatrixInput_17_17) node decoded_andMatrixOutputs_lo_lo_hi_23 = cat(decoded_andMatrixOutputs_andMatrixInput_14_23, decoded_andMatrixOutputs_andMatrixInput_15_23) node decoded_andMatrixOutputs_lo_lo_31 = cat(decoded_andMatrixOutputs_lo_lo_hi_23, decoded_andMatrixOutputs_lo_lo_lo_23) node decoded_andMatrixOutputs_lo_hi_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_12_23, decoded_andMatrixOutputs_andMatrixInput_13_23) node decoded_andMatrixOutputs_lo_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_9_31, decoded_andMatrixOutputs_andMatrixInput_10_27) node decoded_andMatrixOutputs_lo_hi_hi_31 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_11_23) node decoded_andMatrixOutputs_lo_hi_31 = cat(decoded_andMatrixOutputs_lo_hi_hi_31, decoded_andMatrixOutputs_lo_hi_lo_23) node decoded_andMatrixOutputs_lo_31 = cat(decoded_andMatrixOutputs_lo_hi_31, decoded_andMatrixOutputs_lo_lo_31) node decoded_andMatrixOutputs_hi_lo_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_7_31, decoded_andMatrixOutputs_andMatrixInput_8_31) node decoded_andMatrixOutputs_hi_lo_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_5_31, decoded_andMatrixOutputs_andMatrixInput_6_31) node decoded_andMatrixOutputs_hi_lo_31 = cat(decoded_andMatrixOutputs_hi_lo_hi_27, decoded_andMatrixOutputs_hi_lo_lo_23) node decoded_andMatrixOutputs_hi_hi_lo_23 = cat(decoded_andMatrixOutputs_andMatrixInput_3_31, decoded_andMatrixOutputs_andMatrixInput_4_31) node decoded_andMatrixOutputs_hi_hi_hi_hi_17 = cat(decoded_andMatrixOutputs_andMatrixInput_0_31, decoded_andMatrixOutputs_andMatrixInput_1_31) node decoded_andMatrixOutputs_hi_hi_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_17, decoded_andMatrixOutputs_andMatrixInput_2_31) node decoded_andMatrixOutputs_hi_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_hi_31, decoded_andMatrixOutputs_hi_hi_lo_23) node decoded_andMatrixOutputs_hi_31 = cat(decoded_andMatrixOutputs_hi_hi_31, decoded_andMatrixOutputs_hi_lo_31) node _decoded_andMatrixOutputs_T_31 = cat(decoded_andMatrixOutputs_hi_31, decoded_andMatrixOutputs_lo_31) node decoded_andMatrixOutputs_33_2 = andr(_decoded_andMatrixOutputs_T_31) node decoded_andMatrixOutputs_andMatrixInput_0_32 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_32 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_32 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_32 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_32 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_32 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_32 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_32 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_8_32 = bits(decoded_plaInput, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_9_32 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_10_28 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_32 = cat(decoded_andMatrixOutputs_andMatrixInput_9_32, decoded_andMatrixOutputs_andMatrixInput_10_28) node decoded_andMatrixOutputs_lo_hi_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_6_32, decoded_andMatrixOutputs_andMatrixInput_7_32) node decoded_andMatrixOutputs_lo_hi_32 = cat(decoded_andMatrixOutputs_lo_hi_hi_32, decoded_andMatrixOutputs_andMatrixInput_8_32) node decoded_andMatrixOutputs_lo_32 = cat(decoded_andMatrixOutputs_lo_hi_32, decoded_andMatrixOutputs_lo_lo_32) node decoded_andMatrixOutputs_hi_lo_hi_28 = cat(decoded_andMatrixOutputs_andMatrixInput_3_32, decoded_andMatrixOutputs_andMatrixInput_4_32) node decoded_andMatrixOutputs_hi_lo_32 = cat(decoded_andMatrixOutputs_hi_lo_hi_28, decoded_andMatrixOutputs_andMatrixInput_5_32) node decoded_andMatrixOutputs_hi_hi_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_0_32, decoded_andMatrixOutputs_andMatrixInput_1_32) node decoded_andMatrixOutputs_hi_hi_32 = cat(decoded_andMatrixOutputs_hi_hi_hi_32, decoded_andMatrixOutputs_andMatrixInput_2_32) node decoded_andMatrixOutputs_hi_32 = cat(decoded_andMatrixOutputs_hi_hi_32, decoded_andMatrixOutputs_hi_lo_32) node _decoded_andMatrixOutputs_T_32 = cat(decoded_andMatrixOutputs_hi_32, decoded_andMatrixOutputs_lo_32) node decoded_andMatrixOutputs_42_2 = andr(_decoded_andMatrixOutputs_T_32) node decoded_andMatrixOutputs_andMatrixInput_0_33 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_33 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_33 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_33 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_33 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_33 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_33 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_33 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_33 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_9_33 = bits(decoded_plaInput, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_10_29 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_33 = cat(decoded_andMatrixOutputs_andMatrixInput_9_33, decoded_andMatrixOutputs_andMatrixInput_10_29) node decoded_andMatrixOutputs_lo_hi_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_6_33, decoded_andMatrixOutputs_andMatrixInput_7_33) node decoded_andMatrixOutputs_lo_hi_33 = cat(decoded_andMatrixOutputs_lo_hi_hi_33, decoded_andMatrixOutputs_andMatrixInput_8_33) node decoded_andMatrixOutputs_lo_33 = cat(decoded_andMatrixOutputs_lo_hi_33, decoded_andMatrixOutputs_lo_lo_33) node decoded_andMatrixOutputs_hi_lo_hi_29 = cat(decoded_andMatrixOutputs_andMatrixInput_3_33, decoded_andMatrixOutputs_andMatrixInput_4_33) node decoded_andMatrixOutputs_hi_lo_33 = cat(decoded_andMatrixOutputs_hi_lo_hi_29, decoded_andMatrixOutputs_andMatrixInput_5_33) node decoded_andMatrixOutputs_hi_hi_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_0_33, decoded_andMatrixOutputs_andMatrixInput_1_33) node decoded_andMatrixOutputs_hi_hi_33 = cat(decoded_andMatrixOutputs_hi_hi_hi_33, decoded_andMatrixOutputs_andMatrixInput_2_33) node decoded_andMatrixOutputs_hi_33 = cat(decoded_andMatrixOutputs_hi_hi_33, decoded_andMatrixOutputs_hi_lo_33) node _decoded_andMatrixOutputs_T_33 = cat(decoded_andMatrixOutputs_hi_33, decoded_andMatrixOutputs_lo_33) node decoded_andMatrixOutputs_36_2 = andr(_decoded_andMatrixOutputs_T_33) node decoded_andMatrixOutputs_andMatrixInput_0_34 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_34 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_34 = bits(decoded_invInputs, 3, 3) node decoded_andMatrixOutputs_andMatrixInput_3_34 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_4_34 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_5_34 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_6_34 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_7_34 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_8_34 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_9_34 = bits(decoded_plaInput, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_10_30 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_34 = cat(decoded_andMatrixOutputs_andMatrixInput_9_34, decoded_andMatrixOutputs_andMatrixInput_10_30) node decoded_andMatrixOutputs_lo_hi_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_6_34, decoded_andMatrixOutputs_andMatrixInput_7_34) node decoded_andMatrixOutputs_lo_hi_34 = cat(decoded_andMatrixOutputs_lo_hi_hi_34, decoded_andMatrixOutputs_andMatrixInput_8_34) node decoded_andMatrixOutputs_lo_34 = cat(decoded_andMatrixOutputs_lo_hi_34, decoded_andMatrixOutputs_lo_lo_34) node decoded_andMatrixOutputs_hi_lo_hi_30 = cat(decoded_andMatrixOutputs_andMatrixInput_3_34, decoded_andMatrixOutputs_andMatrixInput_4_34) node decoded_andMatrixOutputs_hi_lo_34 = cat(decoded_andMatrixOutputs_hi_lo_hi_30, decoded_andMatrixOutputs_andMatrixInput_5_34) node decoded_andMatrixOutputs_hi_hi_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_0_34, decoded_andMatrixOutputs_andMatrixInput_1_34) node decoded_andMatrixOutputs_hi_hi_34 = cat(decoded_andMatrixOutputs_hi_hi_hi_34, decoded_andMatrixOutputs_andMatrixInput_2_34) node decoded_andMatrixOutputs_hi_34 = cat(decoded_andMatrixOutputs_hi_hi_34, decoded_andMatrixOutputs_hi_lo_34) node _decoded_andMatrixOutputs_T_34 = cat(decoded_andMatrixOutputs_hi_34, decoded_andMatrixOutputs_lo_34) node decoded_andMatrixOutputs_1_2 = andr(_decoded_andMatrixOutputs_T_34) node decoded_andMatrixOutputs_andMatrixInput_0_35 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_35 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_35 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_35 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_35 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_35 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_35 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_35 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_8_35 = bits(decoded_plaInput, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_9_35 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_10_31 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_35 = cat(decoded_andMatrixOutputs_andMatrixInput_9_35, decoded_andMatrixOutputs_andMatrixInput_10_31) node decoded_andMatrixOutputs_lo_hi_hi_35 = cat(decoded_andMatrixOutputs_andMatrixInput_6_35, decoded_andMatrixOutputs_andMatrixInput_7_35) node decoded_andMatrixOutputs_lo_hi_35 = cat(decoded_andMatrixOutputs_lo_hi_hi_35, decoded_andMatrixOutputs_andMatrixInput_8_35) node decoded_andMatrixOutputs_lo_35 = cat(decoded_andMatrixOutputs_lo_hi_35, decoded_andMatrixOutputs_lo_lo_35) node decoded_andMatrixOutputs_hi_lo_hi_31 = cat(decoded_andMatrixOutputs_andMatrixInput_3_35, decoded_andMatrixOutputs_andMatrixInput_4_35) node decoded_andMatrixOutputs_hi_lo_35 = cat(decoded_andMatrixOutputs_hi_lo_hi_31, decoded_andMatrixOutputs_andMatrixInput_5_35) node decoded_andMatrixOutputs_hi_hi_hi_35 = cat(decoded_andMatrixOutputs_andMatrixInput_0_35, decoded_andMatrixOutputs_andMatrixInput_1_35) node decoded_andMatrixOutputs_hi_hi_35 = cat(decoded_andMatrixOutputs_hi_hi_hi_35, decoded_andMatrixOutputs_andMatrixInput_2_35) node decoded_andMatrixOutputs_hi_35 = cat(decoded_andMatrixOutputs_hi_hi_35, decoded_andMatrixOutputs_hi_lo_35) node _decoded_andMatrixOutputs_T_35 = cat(decoded_andMatrixOutputs_hi_35, decoded_andMatrixOutputs_lo_35) node decoded_andMatrixOutputs_24_2 = andr(_decoded_andMatrixOutputs_T_35) node decoded_andMatrixOutputs_andMatrixInput_0_36 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_36 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_2_36 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_3_36 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_4_36 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_5_36 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_3_36, decoded_andMatrixOutputs_andMatrixInput_4_36) node decoded_andMatrixOutputs_lo_36 = cat(decoded_andMatrixOutputs_lo_hi_36, decoded_andMatrixOutputs_andMatrixInput_5_36) node decoded_andMatrixOutputs_hi_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_0_36, decoded_andMatrixOutputs_andMatrixInput_1_36) node decoded_andMatrixOutputs_hi_36 = cat(decoded_andMatrixOutputs_hi_hi_36, decoded_andMatrixOutputs_andMatrixInput_2_36) node _decoded_andMatrixOutputs_T_36 = cat(decoded_andMatrixOutputs_hi_36, decoded_andMatrixOutputs_lo_36) node decoded_andMatrixOutputs_2_2 = andr(_decoded_andMatrixOutputs_T_36) node decoded_andMatrixOutputs_andMatrixInput_0_37 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_37 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_37 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_3_37 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_4_37 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_5_37 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_3_37, decoded_andMatrixOutputs_andMatrixInput_4_37) node decoded_andMatrixOutputs_lo_37 = cat(decoded_andMatrixOutputs_lo_hi_37, decoded_andMatrixOutputs_andMatrixInput_5_37) node decoded_andMatrixOutputs_hi_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_0_37, decoded_andMatrixOutputs_andMatrixInput_1_37) node decoded_andMatrixOutputs_hi_37 = cat(decoded_andMatrixOutputs_hi_hi_37, decoded_andMatrixOutputs_andMatrixInput_2_37) node _decoded_andMatrixOutputs_T_37 = cat(decoded_andMatrixOutputs_hi_37, decoded_andMatrixOutputs_lo_37) node decoded_andMatrixOutputs_23_2 = andr(_decoded_andMatrixOutputs_T_37) node decoded_andMatrixOutputs_andMatrixInput_0_38 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_38 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_38 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_3_38 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_38 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_38 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_36 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_36 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_36 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_9_36 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_10_32 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_36 = cat(decoded_andMatrixOutputs_andMatrixInput_9_36, decoded_andMatrixOutputs_andMatrixInput_10_32) node decoded_andMatrixOutputs_lo_hi_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_6_36, decoded_andMatrixOutputs_andMatrixInput_7_36) node decoded_andMatrixOutputs_lo_hi_38 = cat(decoded_andMatrixOutputs_lo_hi_hi_36, decoded_andMatrixOutputs_andMatrixInput_8_36) node decoded_andMatrixOutputs_lo_38 = cat(decoded_andMatrixOutputs_lo_hi_38, decoded_andMatrixOutputs_lo_lo_36) node decoded_andMatrixOutputs_hi_lo_hi_32 = cat(decoded_andMatrixOutputs_andMatrixInput_3_38, decoded_andMatrixOutputs_andMatrixInput_4_38) node decoded_andMatrixOutputs_hi_lo_36 = cat(decoded_andMatrixOutputs_hi_lo_hi_32, decoded_andMatrixOutputs_andMatrixInput_5_38) node decoded_andMatrixOutputs_hi_hi_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_0_38, decoded_andMatrixOutputs_andMatrixInput_1_38) node decoded_andMatrixOutputs_hi_hi_38 = cat(decoded_andMatrixOutputs_hi_hi_hi_36, decoded_andMatrixOutputs_andMatrixInput_2_38) node decoded_andMatrixOutputs_hi_38 = cat(decoded_andMatrixOutputs_hi_hi_38, decoded_andMatrixOutputs_hi_lo_36) node _decoded_andMatrixOutputs_T_38 = cat(decoded_andMatrixOutputs_hi_38, decoded_andMatrixOutputs_lo_38) node decoded_andMatrixOutputs_25_2 = andr(_decoded_andMatrixOutputs_T_38) node decoded_andMatrixOutputs_andMatrixInput_0_39 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_39 = bits(decoded_plaInput, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_39 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_39 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_39 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_39 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_37 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_37 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_8_37 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_9_37 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_10_33 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_37 = cat(decoded_andMatrixOutputs_andMatrixInput_9_37, decoded_andMatrixOutputs_andMatrixInput_10_33) node decoded_andMatrixOutputs_lo_hi_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_6_37, decoded_andMatrixOutputs_andMatrixInput_7_37) node decoded_andMatrixOutputs_lo_hi_39 = cat(decoded_andMatrixOutputs_lo_hi_hi_37, decoded_andMatrixOutputs_andMatrixInput_8_37) node decoded_andMatrixOutputs_lo_39 = cat(decoded_andMatrixOutputs_lo_hi_39, decoded_andMatrixOutputs_lo_lo_37) node decoded_andMatrixOutputs_hi_lo_hi_33 = cat(decoded_andMatrixOutputs_andMatrixInput_3_39, decoded_andMatrixOutputs_andMatrixInput_4_39) node decoded_andMatrixOutputs_hi_lo_37 = cat(decoded_andMatrixOutputs_hi_lo_hi_33, decoded_andMatrixOutputs_andMatrixInput_5_39) node decoded_andMatrixOutputs_hi_hi_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_0_39, decoded_andMatrixOutputs_andMatrixInput_1_39) node decoded_andMatrixOutputs_hi_hi_39 = cat(decoded_andMatrixOutputs_hi_hi_hi_37, decoded_andMatrixOutputs_andMatrixInput_2_39) node decoded_andMatrixOutputs_hi_39 = cat(decoded_andMatrixOutputs_hi_hi_39, decoded_andMatrixOutputs_hi_lo_37) node _decoded_andMatrixOutputs_T_39 = cat(decoded_andMatrixOutputs_hi_39, decoded_andMatrixOutputs_lo_39) node decoded_andMatrixOutputs_21_2 = andr(_decoded_andMatrixOutputs_T_39) node decoded_andMatrixOutputs_andMatrixInput_0_40 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_40 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_40 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_3_40 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_40 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_40 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_38 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_38 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_38 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_9_38 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_10_34 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_38 = cat(decoded_andMatrixOutputs_andMatrixInput_9_38, decoded_andMatrixOutputs_andMatrixInput_10_34) node decoded_andMatrixOutputs_lo_hi_hi_38 = cat(decoded_andMatrixOutputs_andMatrixInput_6_38, decoded_andMatrixOutputs_andMatrixInput_7_38) node decoded_andMatrixOutputs_lo_hi_40 = cat(decoded_andMatrixOutputs_lo_hi_hi_38, decoded_andMatrixOutputs_andMatrixInput_8_38) node decoded_andMatrixOutputs_lo_40 = cat(decoded_andMatrixOutputs_lo_hi_40, decoded_andMatrixOutputs_lo_lo_38) node decoded_andMatrixOutputs_hi_lo_hi_34 = cat(decoded_andMatrixOutputs_andMatrixInput_3_40, decoded_andMatrixOutputs_andMatrixInput_4_40) node decoded_andMatrixOutputs_hi_lo_38 = cat(decoded_andMatrixOutputs_hi_lo_hi_34, decoded_andMatrixOutputs_andMatrixInput_5_40) node decoded_andMatrixOutputs_hi_hi_hi_38 = cat(decoded_andMatrixOutputs_andMatrixInput_0_40, decoded_andMatrixOutputs_andMatrixInput_1_40) node decoded_andMatrixOutputs_hi_hi_40 = cat(decoded_andMatrixOutputs_hi_hi_hi_38, decoded_andMatrixOutputs_andMatrixInput_2_40) node decoded_andMatrixOutputs_hi_40 = cat(decoded_andMatrixOutputs_hi_hi_40, decoded_andMatrixOutputs_hi_lo_38) node _decoded_andMatrixOutputs_T_40 = cat(decoded_andMatrixOutputs_hi_40, decoded_andMatrixOutputs_lo_40) node decoded_andMatrixOutputs_22_2 = andr(_decoded_andMatrixOutputs_T_40) node decoded_andMatrixOutputs_andMatrixInput_0_41 = bits(decoded_plaInput, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_41 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_41 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_41 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_41 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_41 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_39 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_39 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_8_39 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_9_39 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_10_35 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_39 = cat(decoded_andMatrixOutputs_andMatrixInput_9_39, decoded_andMatrixOutputs_andMatrixInput_10_35) node decoded_andMatrixOutputs_lo_hi_hi_39 = cat(decoded_andMatrixOutputs_andMatrixInput_6_39, decoded_andMatrixOutputs_andMatrixInput_7_39) node decoded_andMatrixOutputs_lo_hi_41 = cat(decoded_andMatrixOutputs_lo_hi_hi_39, decoded_andMatrixOutputs_andMatrixInput_8_39) node decoded_andMatrixOutputs_lo_41 = cat(decoded_andMatrixOutputs_lo_hi_41, decoded_andMatrixOutputs_lo_lo_39) node decoded_andMatrixOutputs_hi_lo_hi_35 = cat(decoded_andMatrixOutputs_andMatrixInput_3_41, decoded_andMatrixOutputs_andMatrixInput_4_41) node decoded_andMatrixOutputs_hi_lo_39 = cat(decoded_andMatrixOutputs_hi_lo_hi_35, decoded_andMatrixOutputs_andMatrixInput_5_41) node decoded_andMatrixOutputs_hi_hi_hi_39 = cat(decoded_andMatrixOutputs_andMatrixInput_0_41, decoded_andMatrixOutputs_andMatrixInput_1_41) node decoded_andMatrixOutputs_hi_hi_41 = cat(decoded_andMatrixOutputs_hi_hi_hi_39, decoded_andMatrixOutputs_andMatrixInput_2_41) node decoded_andMatrixOutputs_hi_41 = cat(decoded_andMatrixOutputs_hi_hi_41, decoded_andMatrixOutputs_hi_lo_39) node _decoded_andMatrixOutputs_T_41 = cat(decoded_andMatrixOutputs_hi_41, decoded_andMatrixOutputs_lo_41) node decoded_andMatrixOutputs_48_2 = andr(_decoded_andMatrixOutputs_T_41) node decoded_andMatrixOutputs_andMatrixInput_0_42 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_42 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_42 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_42 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_42 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_42 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_40 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_40 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_40 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_9_40 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_40 = cat(decoded_andMatrixOutputs_andMatrixInput_8_40, decoded_andMatrixOutputs_andMatrixInput_9_40) node decoded_andMatrixOutputs_lo_hi_hi_40 = cat(decoded_andMatrixOutputs_andMatrixInput_5_42, decoded_andMatrixOutputs_andMatrixInput_6_40) node decoded_andMatrixOutputs_lo_hi_42 = cat(decoded_andMatrixOutputs_lo_hi_hi_40, decoded_andMatrixOutputs_andMatrixInput_7_40) node decoded_andMatrixOutputs_lo_42 = cat(decoded_andMatrixOutputs_lo_hi_42, decoded_andMatrixOutputs_lo_lo_40) node decoded_andMatrixOutputs_hi_lo_40 = cat(decoded_andMatrixOutputs_andMatrixInput_3_42, decoded_andMatrixOutputs_andMatrixInput_4_42) node decoded_andMatrixOutputs_hi_hi_hi_40 = cat(decoded_andMatrixOutputs_andMatrixInput_0_42, decoded_andMatrixOutputs_andMatrixInput_1_42) node decoded_andMatrixOutputs_hi_hi_42 = cat(decoded_andMatrixOutputs_hi_hi_hi_40, decoded_andMatrixOutputs_andMatrixInput_2_42) node decoded_andMatrixOutputs_hi_42 = cat(decoded_andMatrixOutputs_hi_hi_42, decoded_andMatrixOutputs_hi_lo_40) node _decoded_andMatrixOutputs_T_42 = cat(decoded_andMatrixOutputs_hi_42, decoded_andMatrixOutputs_lo_42) node decoded_andMatrixOutputs_31_2 = andr(_decoded_andMatrixOutputs_T_42) node decoded_andMatrixOutputs_andMatrixInput_0_43 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_43 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_43 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_43 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_43 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_43 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_41 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_41 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_41 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_41 = bits(decoded_plaInput, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_36 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_24 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_24 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_24 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_24 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_24 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_16_18 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_18 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_24 = cat(decoded_andMatrixOutputs_andMatrixInput_16_18, decoded_andMatrixOutputs_andMatrixInput_17_18) node decoded_andMatrixOutputs_lo_lo_hi_24 = cat(decoded_andMatrixOutputs_andMatrixInput_14_24, decoded_andMatrixOutputs_andMatrixInput_15_24) node decoded_andMatrixOutputs_lo_lo_41 = cat(decoded_andMatrixOutputs_lo_lo_hi_24, decoded_andMatrixOutputs_lo_lo_lo_24) node decoded_andMatrixOutputs_lo_hi_lo_24 = cat(decoded_andMatrixOutputs_andMatrixInput_12_24, decoded_andMatrixOutputs_andMatrixInput_13_24) node decoded_andMatrixOutputs_lo_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_9_41, decoded_andMatrixOutputs_andMatrixInput_10_36) node decoded_andMatrixOutputs_lo_hi_hi_41 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_18, decoded_andMatrixOutputs_andMatrixInput_11_24) node decoded_andMatrixOutputs_lo_hi_43 = cat(decoded_andMatrixOutputs_lo_hi_hi_41, decoded_andMatrixOutputs_lo_hi_lo_24) node decoded_andMatrixOutputs_lo_43 = cat(decoded_andMatrixOutputs_lo_hi_43, decoded_andMatrixOutputs_lo_lo_41) node decoded_andMatrixOutputs_hi_lo_lo_24 = cat(decoded_andMatrixOutputs_andMatrixInput_7_41, decoded_andMatrixOutputs_andMatrixInput_8_41) node decoded_andMatrixOutputs_hi_lo_hi_36 = cat(decoded_andMatrixOutputs_andMatrixInput_5_43, decoded_andMatrixOutputs_andMatrixInput_6_41) node decoded_andMatrixOutputs_hi_lo_41 = cat(decoded_andMatrixOutputs_hi_lo_hi_36, decoded_andMatrixOutputs_hi_lo_lo_24) node decoded_andMatrixOutputs_hi_hi_lo_24 = cat(decoded_andMatrixOutputs_andMatrixInput_3_43, decoded_andMatrixOutputs_andMatrixInput_4_43) node decoded_andMatrixOutputs_hi_hi_hi_hi_18 = cat(decoded_andMatrixOutputs_andMatrixInput_0_43, decoded_andMatrixOutputs_andMatrixInput_1_43) node decoded_andMatrixOutputs_hi_hi_hi_41 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_18, decoded_andMatrixOutputs_andMatrixInput_2_43) node decoded_andMatrixOutputs_hi_hi_43 = cat(decoded_andMatrixOutputs_hi_hi_hi_41, decoded_andMatrixOutputs_hi_hi_lo_24) node decoded_andMatrixOutputs_hi_43 = cat(decoded_andMatrixOutputs_hi_hi_43, decoded_andMatrixOutputs_hi_lo_41) node _decoded_andMatrixOutputs_T_43 = cat(decoded_andMatrixOutputs_hi_43, decoded_andMatrixOutputs_lo_43) node decoded_andMatrixOutputs_46_2 = andr(_decoded_andMatrixOutputs_T_43) node decoded_andMatrixOutputs_andMatrixInput_0_44 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_44 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_44 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_44 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_44 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_44 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_42 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_42 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_42 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_42 = bits(decoded_plaInput, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_37 = bits(decoded_plaInput, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_25 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_25 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_25 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_25 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_25 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_16_19 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_19 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_25 = cat(decoded_andMatrixOutputs_andMatrixInput_16_19, decoded_andMatrixOutputs_andMatrixInput_17_19) node decoded_andMatrixOutputs_lo_lo_hi_25 = cat(decoded_andMatrixOutputs_andMatrixInput_14_25, decoded_andMatrixOutputs_andMatrixInput_15_25) node decoded_andMatrixOutputs_lo_lo_42 = cat(decoded_andMatrixOutputs_lo_lo_hi_25, decoded_andMatrixOutputs_lo_lo_lo_25) node decoded_andMatrixOutputs_lo_hi_lo_25 = cat(decoded_andMatrixOutputs_andMatrixInput_12_25, decoded_andMatrixOutputs_andMatrixInput_13_25) node decoded_andMatrixOutputs_lo_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_9_42, decoded_andMatrixOutputs_andMatrixInput_10_37) node decoded_andMatrixOutputs_lo_hi_hi_42 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_19, decoded_andMatrixOutputs_andMatrixInput_11_25) node decoded_andMatrixOutputs_lo_hi_44 = cat(decoded_andMatrixOutputs_lo_hi_hi_42, decoded_andMatrixOutputs_lo_hi_lo_25) node decoded_andMatrixOutputs_lo_44 = cat(decoded_andMatrixOutputs_lo_hi_44, decoded_andMatrixOutputs_lo_lo_42) node decoded_andMatrixOutputs_hi_lo_lo_25 = cat(decoded_andMatrixOutputs_andMatrixInput_7_42, decoded_andMatrixOutputs_andMatrixInput_8_42) node decoded_andMatrixOutputs_hi_lo_hi_37 = cat(decoded_andMatrixOutputs_andMatrixInput_5_44, decoded_andMatrixOutputs_andMatrixInput_6_42) node decoded_andMatrixOutputs_hi_lo_42 = cat(decoded_andMatrixOutputs_hi_lo_hi_37, decoded_andMatrixOutputs_hi_lo_lo_25) node decoded_andMatrixOutputs_hi_hi_lo_25 = cat(decoded_andMatrixOutputs_andMatrixInput_3_44, decoded_andMatrixOutputs_andMatrixInput_4_44) node decoded_andMatrixOutputs_hi_hi_hi_hi_19 = cat(decoded_andMatrixOutputs_andMatrixInput_0_44, decoded_andMatrixOutputs_andMatrixInput_1_44) node decoded_andMatrixOutputs_hi_hi_hi_42 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_19, decoded_andMatrixOutputs_andMatrixInput_2_44) node decoded_andMatrixOutputs_hi_hi_44 = cat(decoded_andMatrixOutputs_hi_hi_hi_42, decoded_andMatrixOutputs_hi_hi_lo_25) node decoded_andMatrixOutputs_hi_44 = cat(decoded_andMatrixOutputs_hi_hi_44, decoded_andMatrixOutputs_hi_lo_42) node _decoded_andMatrixOutputs_T_44 = cat(decoded_andMatrixOutputs_hi_44, decoded_andMatrixOutputs_lo_44) node decoded_andMatrixOutputs_9_2 = andr(_decoded_andMatrixOutputs_T_44) node decoded_andMatrixOutputs_andMatrixInput_0_45 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_45 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_45 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_3_45 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_4_45 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_5_45 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_6_43 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_7_43 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_8_43 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_9_43 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_10_38 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_11_26 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_12_26 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_13_26 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_14_26 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_15_26 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_16_20 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_17_20 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_16_20, decoded_andMatrixOutputs_andMatrixInput_17_20) node decoded_andMatrixOutputs_lo_lo_hi_26 = cat(decoded_andMatrixOutputs_andMatrixInput_14_26, decoded_andMatrixOutputs_andMatrixInput_15_26) node decoded_andMatrixOutputs_lo_lo_43 = cat(decoded_andMatrixOutputs_lo_lo_hi_26, decoded_andMatrixOutputs_lo_lo_lo_26) node decoded_andMatrixOutputs_lo_hi_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_12_26, decoded_andMatrixOutputs_andMatrixInput_13_26) node decoded_andMatrixOutputs_lo_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_9_43, decoded_andMatrixOutputs_andMatrixInput_10_38) node decoded_andMatrixOutputs_lo_hi_hi_43 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_11_26) node decoded_andMatrixOutputs_lo_hi_45 = cat(decoded_andMatrixOutputs_lo_hi_hi_43, decoded_andMatrixOutputs_lo_hi_lo_26) node decoded_andMatrixOutputs_lo_45 = cat(decoded_andMatrixOutputs_lo_hi_45, decoded_andMatrixOutputs_lo_lo_43) node decoded_andMatrixOutputs_hi_lo_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_7_43, decoded_andMatrixOutputs_andMatrixInput_8_43) node decoded_andMatrixOutputs_hi_lo_hi_38 = cat(decoded_andMatrixOutputs_andMatrixInput_5_45, decoded_andMatrixOutputs_andMatrixInput_6_43) node decoded_andMatrixOutputs_hi_lo_43 = cat(decoded_andMatrixOutputs_hi_lo_hi_38, decoded_andMatrixOutputs_hi_lo_lo_26) node decoded_andMatrixOutputs_hi_hi_lo_26 = cat(decoded_andMatrixOutputs_andMatrixInput_3_45, decoded_andMatrixOutputs_andMatrixInput_4_45) node decoded_andMatrixOutputs_hi_hi_hi_hi_20 = cat(decoded_andMatrixOutputs_andMatrixInput_0_45, decoded_andMatrixOutputs_andMatrixInput_1_45) node decoded_andMatrixOutputs_hi_hi_hi_43 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_20, decoded_andMatrixOutputs_andMatrixInput_2_45) node decoded_andMatrixOutputs_hi_hi_45 = cat(decoded_andMatrixOutputs_hi_hi_hi_43, decoded_andMatrixOutputs_hi_hi_lo_26) node decoded_andMatrixOutputs_hi_45 = cat(decoded_andMatrixOutputs_hi_hi_45, decoded_andMatrixOutputs_hi_lo_43) node _decoded_andMatrixOutputs_T_45 = cat(decoded_andMatrixOutputs_hi_45, decoded_andMatrixOutputs_lo_45) node decoded_andMatrixOutputs_17_2 = andr(_decoded_andMatrixOutputs_T_45) node decoded_andMatrixOutputs_andMatrixInput_0_46 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_46 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_46 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_46 = bits(decoded_plaInput, 4, 4) node decoded_andMatrixOutputs_andMatrixInput_4_46 = bits(decoded_invInputs, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_5_46 = bits(decoded_invInputs, 6, 6) node decoded_andMatrixOutputs_andMatrixInput_6_44 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_7_44 = bits(decoded_invInputs, 8, 8) node decoded_andMatrixOutputs_andMatrixInput_8_44 = bits(decoded_invInputs, 9, 9) node decoded_andMatrixOutputs_andMatrixInput_9_44 = bits(decoded_invInputs, 10, 10) node decoded_andMatrixOutputs_andMatrixInput_10_39 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_11_27 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_12_27 = bits(decoded_plaInput, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_13_27 = bits(decoded_plaInput, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_14_27 = bits(decoded_plaInput, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_15_27 = bits(decoded_invInputs, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_16_21 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_17_21 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_16_21, decoded_andMatrixOutputs_andMatrixInput_17_21) node decoded_andMatrixOutputs_lo_lo_hi_27 = cat(decoded_andMatrixOutputs_andMatrixInput_14_27, decoded_andMatrixOutputs_andMatrixInput_15_27) node decoded_andMatrixOutputs_lo_lo_44 = cat(decoded_andMatrixOutputs_lo_lo_hi_27, decoded_andMatrixOutputs_lo_lo_lo_27) node decoded_andMatrixOutputs_lo_hi_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_12_27, decoded_andMatrixOutputs_andMatrixInput_13_27) node decoded_andMatrixOutputs_lo_hi_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_9_44, decoded_andMatrixOutputs_andMatrixInput_10_39) node decoded_andMatrixOutputs_lo_hi_hi_44 = cat(decoded_andMatrixOutputs_lo_hi_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_11_27) node decoded_andMatrixOutputs_lo_hi_46 = cat(decoded_andMatrixOutputs_lo_hi_hi_44, decoded_andMatrixOutputs_lo_hi_lo_27) node decoded_andMatrixOutputs_lo_46 = cat(decoded_andMatrixOutputs_lo_hi_46, decoded_andMatrixOutputs_lo_lo_44) node decoded_andMatrixOutputs_hi_lo_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_7_44, decoded_andMatrixOutputs_andMatrixInput_8_44) node decoded_andMatrixOutputs_hi_lo_hi_39 = cat(decoded_andMatrixOutputs_andMatrixInput_5_46, decoded_andMatrixOutputs_andMatrixInput_6_44) node decoded_andMatrixOutputs_hi_lo_44 = cat(decoded_andMatrixOutputs_hi_lo_hi_39, decoded_andMatrixOutputs_hi_lo_lo_27) node decoded_andMatrixOutputs_hi_hi_lo_27 = cat(decoded_andMatrixOutputs_andMatrixInput_3_46, decoded_andMatrixOutputs_andMatrixInput_4_46) node decoded_andMatrixOutputs_hi_hi_hi_hi_21 = cat(decoded_andMatrixOutputs_andMatrixInput_0_46, decoded_andMatrixOutputs_andMatrixInput_1_46) node decoded_andMatrixOutputs_hi_hi_hi_44 = cat(decoded_andMatrixOutputs_hi_hi_hi_hi_21, decoded_andMatrixOutputs_andMatrixInput_2_46) node decoded_andMatrixOutputs_hi_hi_46 = cat(decoded_andMatrixOutputs_hi_hi_hi_44, decoded_andMatrixOutputs_hi_hi_lo_27) node decoded_andMatrixOutputs_hi_46 = cat(decoded_andMatrixOutputs_hi_hi_46, decoded_andMatrixOutputs_hi_lo_44) node _decoded_andMatrixOutputs_T_46 = cat(decoded_andMatrixOutputs_hi_46, decoded_andMatrixOutputs_lo_46) node decoded_andMatrixOutputs_30_2 = andr(_decoded_andMatrixOutputs_T_46) node decoded_andMatrixOutputs_andMatrixInput_0_47 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_47 = bits(decoded_invInputs, 7, 7) node decoded_andMatrixOutputs_andMatrixInput_2_47 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_3_47 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_4_47 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_5_47 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_6_45 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_7_45 = bits(decoded_plaInput, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_8_45 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_9_45 = bits(decoded_invInputs, 18, 18) node decoded_andMatrixOutputs_andMatrixInput_10_40 = bits(decoded_invInputs, 19, 19) node decoded_andMatrixOutputs_lo_lo_45 = cat(decoded_andMatrixOutputs_andMatrixInput_9_45, decoded_andMatrixOutputs_andMatrixInput_10_40) node decoded_andMatrixOutputs_lo_hi_hi_45 = cat(decoded_andMatrixOutputs_andMatrixInput_6_45, decoded_andMatrixOutputs_andMatrixInput_7_45) node decoded_andMatrixOutputs_lo_hi_47 = cat(decoded_andMatrixOutputs_lo_hi_hi_45, decoded_andMatrixOutputs_andMatrixInput_8_45) node decoded_andMatrixOutputs_lo_47 = cat(decoded_andMatrixOutputs_lo_hi_47, decoded_andMatrixOutputs_lo_lo_45) node decoded_andMatrixOutputs_hi_lo_hi_40 = cat(decoded_andMatrixOutputs_andMatrixInput_3_47, decoded_andMatrixOutputs_andMatrixInput_4_47) node decoded_andMatrixOutputs_hi_lo_45 = cat(decoded_andMatrixOutputs_hi_lo_hi_40, decoded_andMatrixOutputs_andMatrixInput_5_47) node decoded_andMatrixOutputs_hi_hi_hi_45 = cat(decoded_andMatrixOutputs_andMatrixInput_0_47, decoded_andMatrixOutputs_andMatrixInput_1_47) node decoded_andMatrixOutputs_hi_hi_47 = cat(decoded_andMatrixOutputs_hi_hi_hi_45, decoded_andMatrixOutputs_andMatrixInput_2_47) node decoded_andMatrixOutputs_hi_47 = cat(decoded_andMatrixOutputs_hi_hi_47, decoded_andMatrixOutputs_hi_lo_45) node _decoded_andMatrixOutputs_T_47 = cat(decoded_andMatrixOutputs_hi_47, decoded_andMatrixOutputs_lo_47) node decoded_andMatrixOutputs_18_2 = andr(_decoded_andMatrixOutputs_T_47) node decoded_andMatrixOutputs_andMatrixInput_0_48 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_48 = bits(decoded_invInputs, 1, 1) node decoded_andMatrixOutputs_andMatrixInput_2_48 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_3_48 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_48 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_48 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_46 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_46 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_8_46 = bits(decoded_plaInput, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_9_46 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_10_41 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_46 = cat(decoded_andMatrixOutputs_andMatrixInput_9_46, decoded_andMatrixOutputs_andMatrixInput_10_41) node decoded_andMatrixOutputs_lo_hi_hi_46 = cat(decoded_andMatrixOutputs_andMatrixInput_6_46, decoded_andMatrixOutputs_andMatrixInput_7_46) node decoded_andMatrixOutputs_lo_hi_48 = cat(decoded_andMatrixOutputs_lo_hi_hi_46, decoded_andMatrixOutputs_andMatrixInput_8_46) node decoded_andMatrixOutputs_lo_48 = cat(decoded_andMatrixOutputs_lo_hi_48, decoded_andMatrixOutputs_lo_lo_46) node decoded_andMatrixOutputs_hi_lo_hi_41 = cat(decoded_andMatrixOutputs_andMatrixInput_3_48, decoded_andMatrixOutputs_andMatrixInput_4_48) node decoded_andMatrixOutputs_hi_lo_46 = cat(decoded_andMatrixOutputs_hi_lo_hi_41, decoded_andMatrixOutputs_andMatrixInput_5_48) node decoded_andMatrixOutputs_hi_hi_hi_46 = cat(decoded_andMatrixOutputs_andMatrixInput_0_48, decoded_andMatrixOutputs_andMatrixInput_1_48) node decoded_andMatrixOutputs_hi_hi_48 = cat(decoded_andMatrixOutputs_hi_hi_hi_46, decoded_andMatrixOutputs_andMatrixInput_2_48) node decoded_andMatrixOutputs_hi_48 = cat(decoded_andMatrixOutputs_hi_hi_48, decoded_andMatrixOutputs_hi_lo_46) node _decoded_andMatrixOutputs_T_48 = cat(decoded_andMatrixOutputs_hi_48, decoded_andMatrixOutputs_lo_48) node decoded_andMatrixOutputs_35_2 = andr(_decoded_andMatrixOutputs_T_48) node decoded_andMatrixOutputs_andMatrixInput_0_49 = bits(decoded_invInputs, 0, 0) node decoded_andMatrixOutputs_andMatrixInput_1_49 = bits(decoded_invInputs, 2, 2) node decoded_andMatrixOutputs_andMatrixInput_2_49 = bits(decoded_plaInput, 5, 5) node decoded_andMatrixOutputs_andMatrixInput_3_49 = bits(decoded_invInputs, 11, 11) node decoded_andMatrixOutputs_andMatrixInput_4_49 = bits(decoded_invInputs, 12, 12) node decoded_andMatrixOutputs_andMatrixInput_5_49 = bits(decoded_invInputs, 13, 13) node decoded_andMatrixOutputs_andMatrixInput_6_47 = bits(decoded_invInputs, 14, 14) node decoded_andMatrixOutputs_andMatrixInput_7_47 = bits(decoded_invInputs, 15, 15) node decoded_andMatrixOutputs_andMatrixInput_8_47 = bits(decoded_plaInput, 16, 16) node decoded_andMatrixOutputs_andMatrixInput_9_47 = bits(decoded_plaInput, 17, 17) node decoded_andMatrixOutputs_andMatrixInput_10_42 = bits(decoded_invInputs, 20, 20) node decoded_andMatrixOutputs_lo_lo_47 = cat(decoded_andMatrixOutputs_andMatrixInput_9_47, decoded_andMatrixOutputs_andMatrixInput_10_42) node decoded_andMatrixOutputs_lo_hi_hi_47 = cat(decoded_andMatrixOutputs_andMatrixInput_6_47, decoded_andMatrixOutputs_andMatrixInput_7_47) node decoded_andMatrixOutputs_lo_hi_49 = cat(decoded_andMatrixOutputs_lo_hi_hi_47, decoded_andMatrixOutputs_andMatrixInput_8_47) node decoded_andMatrixOutputs_lo_49 = cat(decoded_andMatrixOutputs_lo_hi_49, decoded_andMatrixOutputs_lo_lo_47) node decoded_andMatrixOutputs_hi_lo_hi_42 = cat(decoded_andMatrixOutputs_andMatrixInput_3_49, decoded_andMatrixOutputs_andMatrixInput_4_49) node decoded_andMatrixOutputs_hi_lo_47 = cat(decoded_andMatrixOutputs_hi_lo_hi_42, decoded_andMatrixOutputs_andMatrixInput_5_49) node decoded_andMatrixOutputs_hi_hi_hi_47 = cat(decoded_andMatrixOutputs_andMatrixInput_0_49, decoded_andMatrixOutputs_andMatrixInput_1_49) node decoded_andMatrixOutputs_hi_hi_49 = cat(decoded_andMatrixOutputs_hi_hi_hi_47, decoded_andMatrixOutputs_andMatrixInput_2_49) node decoded_andMatrixOutputs_hi_49 = cat(decoded_andMatrixOutputs_hi_hi_49, decoded_andMatrixOutputs_hi_lo_47) node _decoded_andMatrixOutputs_T_49 = cat(decoded_andMatrixOutputs_hi_49, decoded_andMatrixOutputs_lo_49) node decoded_andMatrixOutputs_32_2 = andr(_decoded_andMatrixOutputs_T_49) node decoded_orMatrixOutputs_hi = cat(decoded_andMatrixOutputs_18_2, decoded_andMatrixOutputs_35_2) node _decoded_orMatrixOutputs_T = cat(decoded_orMatrixOutputs_hi, decoded_andMatrixOutputs_32_2) node _decoded_orMatrixOutputs_T_1 = orr(_decoded_orMatrixOutputs_T) node decoded_orMatrixOutputs_lo = cat(decoded_andMatrixOutputs_1_2, decoded_andMatrixOutputs_24_2) node decoded_orMatrixOutputs_hi_1 = cat(decoded_andMatrixOutputs_42_2, decoded_andMatrixOutputs_36_2) node _decoded_orMatrixOutputs_T_2 = cat(decoded_orMatrixOutputs_hi_1, decoded_orMatrixOutputs_lo) node _decoded_orMatrixOutputs_T_3 = orr(_decoded_orMatrixOutputs_T_2) node decoded_orMatrixOutputs_lo_1 = cat(decoded_andMatrixOutputs_17_2, decoded_andMatrixOutputs_30_2) node decoded_orMatrixOutputs_hi_hi = cat(decoded_andMatrixOutputs_31_2, decoded_andMatrixOutputs_46_2) node decoded_orMatrixOutputs_hi_2 = cat(decoded_orMatrixOutputs_hi_hi, decoded_andMatrixOutputs_9_2) node _decoded_orMatrixOutputs_T_4 = cat(decoded_orMatrixOutputs_hi_2, decoded_orMatrixOutputs_lo_1) node _decoded_orMatrixOutputs_T_5 = orr(_decoded_orMatrixOutputs_T_4) node decoded_orMatrixOutputs_lo_lo = cat(decoded_andMatrixOutputs_12_2, decoded_andMatrixOutputs_33_2) node decoded_orMatrixOutputs_lo_hi_hi = cat(decoded_andMatrixOutputs_40_2, decoded_andMatrixOutputs_37_2) node decoded_orMatrixOutputs_lo_hi = cat(decoded_orMatrixOutputs_lo_hi_hi, decoded_andMatrixOutputs_38_2) node decoded_orMatrixOutputs_lo_2 = cat(decoded_orMatrixOutputs_lo_hi, decoded_orMatrixOutputs_lo_lo) node decoded_orMatrixOutputs_hi_lo = cat(decoded_andMatrixOutputs_19_2, decoded_andMatrixOutputs_13_2) node decoded_orMatrixOutputs_hi_hi_hi = cat(decoded_andMatrixOutputs_29_2, decoded_andMatrixOutputs_11_2) node decoded_orMatrixOutputs_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi, decoded_andMatrixOutputs_34_2) node decoded_orMatrixOutputs_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_1, decoded_orMatrixOutputs_hi_lo) node _decoded_orMatrixOutputs_T_6 = cat(decoded_orMatrixOutputs_hi_3, decoded_orMatrixOutputs_lo_2) node _decoded_orMatrixOutputs_T_7 = orr(_decoded_orMatrixOutputs_T_6) node _decoded_orMatrixOutputs_T_8 = cat(decoded_andMatrixOutputs_22_2, decoded_andMatrixOutputs_48_2) node _decoded_orMatrixOutputs_T_9 = orr(_decoded_orMatrixOutputs_T_8) node _decoded_orMatrixOutputs_T_10 = cat(decoded_andMatrixOutputs_8_2, decoded_andMatrixOutputs_16_2) node _decoded_orMatrixOutputs_T_11 = orr(_decoded_orMatrixOutputs_T_10) node _decoded_orMatrixOutputs_T_12 = cat(decoded_andMatrixOutputs_2_2, decoded_andMatrixOutputs_23_2) node _decoded_orMatrixOutputs_T_13 = orr(_decoded_orMatrixOutputs_T_12) node decoded_orMatrixOutputs_lo_lo_lo = cat(decoded_andMatrixOutputs_26_2, decoded_andMatrixOutputs_28_2) node decoded_orMatrixOutputs_lo_lo_hi = cat(decoded_andMatrixOutputs_10_2, decoded_andMatrixOutputs_45_2) node decoded_orMatrixOutputs_lo_lo_1 = cat(decoded_orMatrixOutputs_lo_lo_hi, decoded_orMatrixOutputs_lo_lo_lo) node decoded_orMatrixOutputs_lo_hi_lo = cat(decoded_andMatrixOutputs_15_2, decoded_andMatrixOutputs_5_2) node decoded_orMatrixOutputs_lo_hi_hi_hi = cat(decoded_andMatrixOutputs_39_2, decoded_andMatrixOutputs_20_2) node decoded_orMatrixOutputs_lo_hi_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_hi, decoded_andMatrixOutputs_43_2) node decoded_orMatrixOutputs_lo_hi_1 = cat(decoded_orMatrixOutputs_lo_hi_hi_1, decoded_orMatrixOutputs_lo_hi_lo) node decoded_orMatrixOutputs_lo_3 = cat(decoded_orMatrixOutputs_lo_hi_1, decoded_orMatrixOutputs_lo_lo_1) node decoded_orMatrixOutputs_hi_lo_lo = cat(decoded_andMatrixOutputs_49_2, decoded_andMatrixOutputs_44_2) node decoded_orMatrixOutputs_hi_lo_hi = cat(decoded_andMatrixOutputs_41_2, decoded_andMatrixOutputs_6_2) node decoded_orMatrixOutputs_hi_lo_1 = cat(decoded_orMatrixOutputs_hi_lo_hi, decoded_orMatrixOutputs_hi_lo_lo) node decoded_orMatrixOutputs_hi_hi_lo = cat(decoded_andMatrixOutputs_0_2, decoded_andMatrixOutputs_47_2) node decoded_orMatrixOutputs_hi_hi_hi_hi = cat(decoded_andMatrixOutputs_14_2, decoded_andMatrixOutputs_3_2) node decoded_orMatrixOutputs_hi_hi_hi_1 = cat(decoded_orMatrixOutputs_hi_hi_hi_hi, decoded_andMatrixOutputs_4_2) node decoded_orMatrixOutputs_hi_hi_2 = cat(decoded_orMatrixOutputs_hi_hi_hi_1, decoded_orMatrixOutputs_hi_hi_lo) node decoded_orMatrixOutputs_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_2, decoded_orMatrixOutputs_hi_lo_1) node _decoded_orMatrixOutputs_T_14 = cat(decoded_orMatrixOutputs_hi_4, decoded_orMatrixOutputs_lo_3) node _decoded_orMatrixOutputs_T_15 = orr(_decoded_orMatrixOutputs_T_14) node _decoded_orMatrixOutputs_T_16 = cat(decoded_andMatrixOutputs_25_2, decoded_andMatrixOutputs_21_2) node _decoded_orMatrixOutputs_T_17 = orr(_decoded_orMatrixOutputs_T_16) node _decoded_orMatrixOutputs_T_18 = cat(decoded_andMatrixOutputs_27_2, decoded_andMatrixOutputs_7_2) node _decoded_orMatrixOutputs_T_19 = orr(_decoded_orMatrixOutputs_T_18) node decoded_orMatrixOutputs_lo_lo_2 = cat(_decoded_orMatrixOutputs_T_3, _decoded_orMatrixOutputs_T_1) node decoded_orMatrixOutputs_lo_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_9, _decoded_orMatrixOutputs_T_7) node decoded_orMatrixOutputs_lo_hi_2 = cat(decoded_orMatrixOutputs_lo_hi_hi_2, _decoded_orMatrixOutputs_T_5) node decoded_orMatrixOutputs_lo_4 = cat(decoded_orMatrixOutputs_lo_hi_2, decoded_orMatrixOutputs_lo_lo_2) node decoded_orMatrixOutputs_hi_lo_2 = cat(_decoded_orMatrixOutputs_T_13, _decoded_orMatrixOutputs_T_11) node decoded_orMatrixOutputs_hi_hi_hi_2 = cat(_decoded_orMatrixOutputs_T_19, _decoded_orMatrixOutputs_T_17) node decoded_orMatrixOutputs_hi_hi_3 = cat(decoded_orMatrixOutputs_hi_hi_hi_2, _decoded_orMatrixOutputs_T_15) node decoded_orMatrixOutputs_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_3, decoded_orMatrixOutputs_hi_lo_2) node decoded_orMatrixOutputs = cat(decoded_orMatrixOutputs_hi_5, decoded_orMatrixOutputs_lo_4) node _decoded_invMatrixOutputs_T = bits(decoded_orMatrixOutputs, 0, 0) node _decoded_invMatrixOutputs_T_1 = bits(decoded_orMatrixOutputs, 1, 1) node _decoded_invMatrixOutputs_T_2 = bits(decoded_orMatrixOutputs, 2, 2) node _decoded_invMatrixOutputs_T_3 = bits(decoded_orMatrixOutputs, 3, 3) node _decoded_invMatrixOutputs_T_4 = bits(decoded_orMatrixOutputs, 4, 4) node _decoded_invMatrixOutputs_T_5 = bits(decoded_orMatrixOutputs, 5, 5) node _decoded_invMatrixOutputs_T_6 = bits(decoded_orMatrixOutputs, 6, 6) node _decoded_invMatrixOutputs_T_7 = bits(decoded_orMatrixOutputs, 7, 7) node _decoded_invMatrixOutputs_T_8 = bits(decoded_orMatrixOutputs, 8, 8) node _decoded_invMatrixOutputs_T_9 = bits(decoded_orMatrixOutputs, 9, 9) node decoded_invMatrixOutputs_lo_lo = cat(_decoded_invMatrixOutputs_T_1, _decoded_invMatrixOutputs_T) node decoded_invMatrixOutputs_lo_hi_hi = cat(_decoded_invMatrixOutputs_T_4, _decoded_invMatrixOutputs_T_3) node decoded_invMatrixOutputs_lo_hi = cat(decoded_invMatrixOutputs_lo_hi_hi, _decoded_invMatrixOutputs_T_2) node decoded_invMatrixOutputs_lo = cat(decoded_invMatrixOutputs_lo_hi, decoded_invMatrixOutputs_lo_lo) node decoded_invMatrixOutputs_hi_lo = cat(_decoded_invMatrixOutputs_T_6, _decoded_invMatrixOutputs_T_5) node decoded_invMatrixOutputs_hi_hi_hi = cat(_decoded_invMatrixOutputs_T_9, _decoded_invMatrixOutputs_T_8) node decoded_invMatrixOutputs_hi_hi = cat(decoded_invMatrixOutputs_hi_hi_hi, _decoded_invMatrixOutputs_T_7) node decoded_invMatrixOutputs_hi = cat(decoded_invMatrixOutputs_hi_hi, decoded_invMatrixOutputs_hi_lo) node decoded_invMatrixOutputs = cat(decoded_invMatrixOutputs_hi, decoded_invMatrixOutputs_lo) connect decoded_plaOutput, decoded_invMatrixOutputs connect decoded_plaInput, addr node _decoded_T = bits(decoded_plaOutput, 7, 0) node _decoded_T_1 = shl(UInt<4>(0hf), 4) node _decoded_T_2 = xor(UInt<8>(0hff), _decoded_T_1) node _decoded_T_3 = shr(_decoded_T, 4) node _decoded_T_4 = and(_decoded_T_3, _decoded_T_2) node _decoded_T_5 = bits(_decoded_T, 3, 0) node _decoded_T_6 = shl(_decoded_T_5, 4) node _decoded_T_7 = not(_decoded_T_2) node _decoded_T_8 = and(_decoded_T_6, _decoded_T_7) node _decoded_T_9 = or(_decoded_T_4, _decoded_T_8) node _decoded_T_10 = bits(_decoded_T_2, 5, 0) node _decoded_T_11 = shl(_decoded_T_10, 2) node _decoded_T_12 = xor(_decoded_T_2, _decoded_T_11) node _decoded_T_13 = shr(_decoded_T_9, 2) node _decoded_T_14 = and(_decoded_T_13, _decoded_T_12) node _decoded_T_15 = bits(_decoded_T_9, 5, 0) node _decoded_T_16 = shl(_decoded_T_15, 2) node _decoded_T_17 = not(_decoded_T_12) node _decoded_T_18 = and(_decoded_T_16, _decoded_T_17) node _decoded_T_19 = or(_decoded_T_14, _decoded_T_18) node _decoded_T_20 = bits(_decoded_T_12, 6, 0) node _decoded_T_21 = shl(_decoded_T_20, 1) node _decoded_T_22 = xor(_decoded_T_12, _decoded_T_21) node _decoded_T_23 = shr(_decoded_T_19, 1) node _decoded_T_24 = and(_decoded_T_23, _decoded_T_22) node _decoded_T_25 = bits(_decoded_T_19, 6, 0) node _decoded_T_26 = shl(_decoded_T_25, 1) node _decoded_T_27 = not(_decoded_T_22) node _decoded_T_28 = and(_decoded_T_26, _decoded_T_27) node _decoded_T_29 = or(_decoded_T_24, _decoded_T_28) node _decoded_T_30 = bits(decoded_plaOutput, 9, 8) node _decoded_T_31 = bits(_decoded_T_30, 0, 0) node _decoded_T_32 = bits(_decoded_T_30, 1, 1) node _decoded_T_33 = cat(_decoded_T_31, _decoded_T_32) node decoded = cat(_decoded_T_29, _decoded_T_33) node _io_resp_0_vc_sel_0_0_T = bits(decoded, 0, 0) connect io.resp.`0`.vc_sel.`0`[0], _io_resp_0_vc_sel_0_0_T node _io_resp_0_vc_sel_0_1_T = bits(decoded, 1, 1) connect io.resp.`0`.vc_sel.`0`[1], _io_resp_0_vc_sel_0_1_T node _io_resp_0_vc_sel_0_2_T = bits(decoded, 2, 2) connect io.resp.`0`.vc_sel.`0`[2], _io_resp_0_vc_sel_0_2_T node _io_resp_0_vc_sel_0_3_T = bits(decoded, 3, 3) connect io.resp.`0`.vc_sel.`0`[3], _io_resp_0_vc_sel_0_3_T node _io_resp_0_vc_sel_0_4_T = bits(decoded, 4, 4) connect io.resp.`0`.vc_sel.`0`[4], _io_resp_0_vc_sel_0_4_T node _io_resp_0_vc_sel_0_5_T = bits(decoded, 5, 5) connect io.resp.`0`.vc_sel.`0`[5], _io_resp_0_vc_sel_0_5_T node _io_resp_0_vc_sel_0_6_T = bits(decoded, 6, 6) connect io.resp.`0`.vc_sel.`0`[6], _io_resp_0_vc_sel_0_6_T node _io_resp_0_vc_sel_0_7_T = bits(decoded, 7, 7) connect io.resp.`0`.vc_sel.`0`[7], _io_resp_0_vc_sel_0_7_T node _io_resp_0_vc_sel_0_8_T = bits(decoded, 8, 8) connect io.resp.`0`.vc_sel.`0`[8], _io_resp_0_vc_sel_0_8_T node _io_resp_0_vc_sel_0_9_T = bits(decoded, 9, 9) connect io.resp.`0`.vc_sel.`0`[9], _io_resp_0_vc_sel_0_9_T connect io.resp.`0`.vc_sel.`1`[0], UInt<1>(0h0) connect io.resp.`0`.vc_sel.`2`[0], UInt<1>(0h0) connect io.req.`1`.ready, UInt<1>(0h1) node addr_lo_1 = cat(io.req.`1`.bits.flow.egress_node, io.req.`1`.bits.flow.egress_node_id) node addr_hi_hi_1 = cat(io.req.`1`.bits.flow.vnet_id, io.req.`1`.bits.flow.ingress_node) node addr_hi_1 = cat(addr_hi_hi_1, io.req.`1`.bits.flow.ingress_node_id) node _addr_T_1 = cat(addr_hi_1, addr_lo_1) node addr_1 = cat(io.req.`1`.bits.src_virt_id, _addr_T_1) wire decoded_plaInput_1 : UInt<21> node decoded_invInputs_1 = not(decoded_plaInput_1) wire decoded_plaOutput_1 : UInt<10> node _decoded_orMatrixOutputs_T_20 = orr(UInt<1>(0h1)) node decoded_orMatrixOutputs_lo_lo_3 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_20) node decoded_orMatrixOutputs_lo_hi_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_3 = cat(decoded_orMatrixOutputs_lo_hi_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_5 = cat(decoded_orMatrixOutputs_lo_hi_3, decoded_orMatrixOutputs_lo_lo_3) node decoded_orMatrixOutputs_hi_lo_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_3 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_4 = cat(decoded_orMatrixOutputs_hi_hi_hi_3, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_4, decoded_orMatrixOutputs_hi_lo_3) node decoded_orMatrixOutputs_1 = cat(decoded_orMatrixOutputs_hi_6, decoded_orMatrixOutputs_lo_5) node _decoded_invMatrixOutputs_T_10 = bits(decoded_orMatrixOutputs_1, 0, 0) node _decoded_invMatrixOutputs_T_11 = bits(decoded_orMatrixOutputs_1, 1, 1) node _decoded_invMatrixOutputs_T_12 = bits(decoded_orMatrixOutputs_1, 2, 2) node _decoded_invMatrixOutputs_T_13 = bits(decoded_orMatrixOutputs_1, 3, 3) node _decoded_invMatrixOutputs_T_14 = bits(decoded_orMatrixOutputs_1, 4, 4) node _decoded_invMatrixOutputs_T_15 = bits(decoded_orMatrixOutputs_1, 5, 5) node _decoded_invMatrixOutputs_T_16 = bits(decoded_orMatrixOutputs_1, 6, 6) node _decoded_invMatrixOutputs_T_17 = bits(decoded_orMatrixOutputs_1, 7, 7) node _decoded_invMatrixOutputs_T_18 = bits(decoded_orMatrixOutputs_1, 8, 8) node _decoded_invMatrixOutputs_T_19 = bits(decoded_orMatrixOutputs_1, 9, 9) node decoded_invMatrixOutputs_lo_lo_1 = cat(_decoded_invMatrixOutputs_T_11, _decoded_invMatrixOutputs_T_10) node decoded_invMatrixOutputs_lo_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_14, _decoded_invMatrixOutputs_T_13) node decoded_invMatrixOutputs_lo_hi_1 = cat(decoded_invMatrixOutputs_lo_hi_hi_1, _decoded_invMatrixOutputs_T_12) node decoded_invMatrixOutputs_lo_1 = cat(decoded_invMatrixOutputs_lo_hi_1, decoded_invMatrixOutputs_lo_lo_1) node decoded_invMatrixOutputs_hi_lo_1 = cat(_decoded_invMatrixOutputs_T_16, _decoded_invMatrixOutputs_T_15) node decoded_invMatrixOutputs_hi_hi_hi_1 = cat(_decoded_invMatrixOutputs_T_19, _decoded_invMatrixOutputs_T_18) node decoded_invMatrixOutputs_hi_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_hi_1, _decoded_invMatrixOutputs_T_17) node decoded_invMatrixOutputs_hi_1 = cat(decoded_invMatrixOutputs_hi_hi_1, decoded_invMatrixOutputs_hi_lo_1) node decoded_invMatrixOutputs_1 = cat(decoded_invMatrixOutputs_hi_1, decoded_invMatrixOutputs_lo_1) connect decoded_plaOutput_1, decoded_invMatrixOutputs_1 connect decoded_plaInput_1, addr_1 node _decoded_T_34 = bits(decoded_plaOutput_1, 7, 0) node _decoded_T_35 = shl(UInt<4>(0hf), 4) node _decoded_T_36 = xor(UInt<8>(0hff), _decoded_T_35) node _decoded_T_37 = shr(_decoded_T_34, 4) node _decoded_T_38 = and(_decoded_T_37, _decoded_T_36) node _decoded_T_39 = bits(_decoded_T_34, 3, 0) node _decoded_T_40 = shl(_decoded_T_39, 4) node _decoded_T_41 = not(_decoded_T_36) node _decoded_T_42 = and(_decoded_T_40, _decoded_T_41) node _decoded_T_43 = or(_decoded_T_38, _decoded_T_42) node _decoded_T_44 = bits(_decoded_T_36, 5, 0) node _decoded_T_45 = shl(_decoded_T_44, 2) node _decoded_T_46 = xor(_decoded_T_36, _decoded_T_45) node _decoded_T_47 = shr(_decoded_T_43, 2) node _decoded_T_48 = and(_decoded_T_47, _decoded_T_46) node _decoded_T_49 = bits(_decoded_T_43, 5, 0) node _decoded_T_50 = shl(_decoded_T_49, 2) node _decoded_T_51 = not(_decoded_T_46) node _decoded_T_52 = and(_decoded_T_50, _decoded_T_51) node _decoded_T_53 = or(_decoded_T_48, _decoded_T_52) node _decoded_T_54 = bits(_decoded_T_46, 6, 0) node _decoded_T_55 = shl(_decoded_T_54, 1) node _decoded_T_56 = xor(_decoded_T_46, _decoded_T_55) node _decoded_T_57 = shr(_decoded_T_53, 1) node _decoded_T_58 = and(_decoded_T_57, _decoded_T_56) node _decoded_T_59 = bits(_decoded_T_53, 6, 0) node _decoded_T_60 = shl(_decoded_T_59, 1) node _decoded_T_61 = not(_decoded_T_56) node _decoded_T_62 = and(_decoded_T_60, _decoded_T_61) node _decoded_T_63 = or(_decoded_T_58, _decoded_T_62) node _decoded_T_64 = bits(decoded_plaOutput_1, 9, 8) node _decoded_T_65 = bits(_decoded_T_64, 0, 0) node _decoded_T_66 = bits(_decoded_T_64, 1, 1) node _decoded_T_67 = cat(_decoded_T_65, _decoded_T_66) node decoded_1 = cat(_decoded_T_63, _decoded_T_67) node _io_resp_1_vc_sel_0_0_T = bits(decoded_1, 0, 0) connect io.resp.`1`.vc_sel.`0`[0], _io_resp_1_vc_sel_0_0_T node _io_resp_1_vc_sel_0_1_T = bits(decoded_1, 1, 1) connect io.resp.`1`.vc_sel.`0`[1], _io_resp_1_vc_sel_0_1_T node _io_resp_1_vc_sel_0_2_T = bits(decoded_1, 2, 2) connect io.resp.`1`.vc_sel.`0`[2], _io_resp_1_vc_sel_0_2_T node _io_resp_1_vc_sel_0_3_T = bits(decoded_1, 3, 3) connect io.resp.`1`.vc_sel.`0`[3], _io_resp_1_vc_sel_0_3_T node _io_resp_1_vc_sel_0_4_T = bits(decoded_1, 4, 4) connect io.resp.`1`.vc_sel.`0`[4], _io_resp_1_vc_sel_0_4_T node _io_resp_1_vc_sel_0_5_T = bits(decoded_1, 5, 5) connect io.resp.`1`.vc_sel.`0`[5], _io_resp_1_vc_sel_0_5_T node _io_resp_1_vc_sel_0_6_T = bits(decoded_1, 6, 6) connect io.resp.`1`.vc_sel.`0`[6], _io_resp_1_vc_sel_0_6_T node _io_resp_1_vc_sel_0_7_T = bits(decoded_1, 7, 7) connect io.resp.`1`.vc_sel.`0`[7], _io_resp_1_vc_sel_0_7_T node _io_resp_1_vc_sel_0_8_T = bits(decoded_1, 8, 8) connect io.resp.`1`.vc_sel.`0`[8], _io_resp_1_vc_sel_0_8_T node _io_resp_1_vc_sel_0_9_T = bits(decoded_1, 9, 9) connect io.resp.`1`.vc_sel.`0`[9], _io_resp_1_vc_sel_0_9_T connect io.resp.`1`.vc_sel.`1`[0], UInt<1>(0h0) connect io.resp.`1`.vc_sel.`2`[0], UInt<1>(0h0) connect io.req.`2`.ready, UInt<1>(0h1) node addr_lo_2 = cat(io.req.`2`.bits.flow.egress_node, io.req.`2`.bits.flow.egress_node_id) node addr_hi_hi_2 = cat(io.req.`2`.bits.flow.vnet_id, io.req.`2`.bits.flow.ingress_node) node addr_hi_2 = cat(addr_hi_hi_2, io.req.`2`.bits.flow.ingress_node_id) node _addr_T_2 = cat(addr_hi_2, addr_lo_2) node addr_2 = cat(io.req.`2`.bits.src_virt_id, _addr_T_2) wire decoded_plaInput_2 : UInt<21> node decoded_invInputs_2 = not(decoded_plaInput_2) wire decoded_plaOutput_2 : UInt<10> node _decoded_orMatrixOutputs_T_21 = orr(UInt<1>(0h1)) node decoded_orMatrixOutputs_lo_lo_4 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_4 = cat(_decoded_orMatrixOutputs_T_21, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_4 = cat(decoded_orMatrixOutputs_lo_hi_hi_4, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_6 = cat(decoded_orMatrixOutputs_lo_hi_4, decoded_orMatrixOutputs_lo_lo_4) node decoded_orMatrixOutputs_hi_lo_4 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_4 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_5 = cat(decoded_orMatrixOutputs_hi_hi_hi_4, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_7 = cat(decoded_orMatrixOutputs_hi_hi_5, decoded_orMatrixOutputs_hi_lo_4) node decoded_orMatrixOutputs_2 = cat(decoded_orMatrixOutputs_hi_7, decoded_orMatrixOutputs_lo_6) node _decoded_invMatrixOutputs_T_20 = bits(decoded_orMatrixOutputs_2, 0, 0) node _decoded_invMatrixOutputs_T_21 = bits(decoded_orMatrixOutputs_2, 1, 1) node _decoded_invMatrixOutputs_T_22 = bits(decoded_orMatrixOutputs_2, 2, 2) node _decoded_invMatrixOutputs_T_23 = bits(decoded_orMatrixOutputs_2, 3, 3) node _decoded_invMatrixOutputs_T_24 = bits(decoded_orMatrixOutputs_2, 4, 4) node _decoded_invMatrixOutputs_T_25 = bits(decoded_orMatrixOutputs_2, 5, 5) node _decoded_invMatrixOutputs_T_26 = bits(decoded_orMatrixOutputs_2, 6, 6) node _decoded_invMatrixOutputs_T_27 = bits(decoded_orMatrixOutputs_2, 7, 7) node _decoded_invMatrixOutputs_T_28 = bits(decoded_orMatrixOutputs_2, 8, 8) node _decoded_invMatrixOutputs_T_29 = bits(decoded_orMatrixOutputs_2, 9, 9) node decoded_invMatrixOutputs_lo_lo_2 = cat(_decoded_invMatrixOutputs_T_21, _decoded_invMatrixOutputs_T_20) node decoded_invMatrixOutputs_lo_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_24, _decoded_invMatrixOutputs_T_23) node decoded_invMatrixOutputs_lo_hi_2 = cat(decoded_invMatrixOutputs_lo_hi_hi_2, _decoded_invMatrixOutputs_T_22) node decoded_invMatrixOutputs_lo_2 = cat(decoded_invMatrixOutputs_lo_hi_2, decoded_invMatrixOutputs_lo_lo_2) node decoded_invMatrixOutputs_hi_lo_2 = cat(_decoded_invMatrixOutputs_T_26, _decoded_invMatrixOutputs_T_25) node decoded_invMatrixOutputs_hi_hi_hi_2 = cat(_decoded_invMatrixOutputs_T_29, _decoded_invMatrixOutputs_T_28) node decoded_invMatrixOutputs_hi_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_hi_2, _decoded_invMatrixOutputs_T_27) node decoded_invMatrixOutputs_hi_2 = cat(decoded_invMatrixOutputs_hi_hi_2, decoded_invMatrixOutputs_hi_lo_2) node decoded_invMatrixOutputs_2 = cat(decoded_invMatrixOutputs_hi_2, decoded_invMatrixOutputs_lo_2) connect decoded_plaOutput_2, decoded_invMatrixOutputs_2 connect decoded_plaInput_2, addr_2 node _decoded_T_68 = bits(decoded_plaOutput_2, 7, 0) node _decoded_T_69 = shl(UInt<4>(0hf), 4) node _decoded_T_70 = xor(UInt<8>(0hff), _decoded_T_69) node _decoded_T_71 = shr(_decoded_T_68, 4) node _decoded_T_72 = and(_decoded_T_71, _decoded_T_70) node _decoded_T_73 = bits(_decoded_T_68, 3, 0) node _decoded_T_74 = shl(_decoded_T_73, 4) node _decoded_T_75 = not(_decoded_T_70) node _decoded_T_76 = and(_decoded_T_74, _decoded_T_75) node _decoded_T_77 = or(_decoded_T_72, _decoded_T_76) node _decoded_T_78 = bits(_decoded_T_70, 5, 0) node _decoded_T_79 = shl(_decoded_T_78, 2) node _decoded_T_80 = xor(_decoded_T_70, _decoded_T_79) node _decoded_T_81 = shr(_decoded_T_77, 2) node _decoded_T_82 = and(_decoded_T_81, _decoded_T_80) node _decoded_T_83 = bits(_decoded_T_77, 5, 0) node _decoded_T_84 = shl(_decoded_T_83, 2) node _decoded_T_85 = not(_decoded_T_80) node _decoded_T_86 = and(_decoded_T_84, _decoded_T_85) node _decoded_T_87 = or(_decoded_T_82, _decoded_T_86) node _decoded_T_88 = bits(_decoded_T_80, 6, 0) node _decoded_T_89 = shl(_decoded_T_88, 1) node _decoded_T_90 = xor(_decoded_T_80, _decoded_T_89) node _decoded_T_91 = shr(_decoded_T_87, 1) node _decoded_T_92 = and(_decoded_T_91, _decoded_T_90) node _decoded_T_93 = bits(_decoded_T_87, 6, 0) node _decoded_T_94 = shl(_decoded_T_93, 1) node _decoded_T_95 = not(_decoded_T_90) node _decoded_T_96 = and(_decoded_T_94, _decoded_T_95) node _decoded_T_97 = or(_decoded_T_92, _decoded_T_96) node _decoded_T_98 = bits(decoded_plaOutput_2, 9, 8) node _decoded_T_99 = bits(_decoded_T_98, 0, 0) node _decoded_T_100 = bits(_decoded_T_98, 1, 1) node _decoded_T_101 = cat(_decoded_T_99, _decoded_T_100) node decoded_2 = cat(_decoded_T_97, _decoded_T_101) node _io_resp_2_vc_sel_0_0_T = bits(decoded_2, 0, 0) connect io.resp.`2`.vc_sel.`0`[0], _io_resp_2_vc_sel_0_0_T node _io_resp_2_vc_sel_0_1_T = bits(decoded_2, 1, 1) connect io.resp.`2`.vc_sel.`0`[1], _io_resp_2_vc_sel_0_1_T node _io_resp_2_vc_sel_0_2_T = bits(decoded_2, 2, 2) connect io.resp.`2`.vc_sel.`0`[2], _io_resp_2_vc_sel_0_2_T node _io_resp_2_vc_sel_0_3_T = bits(decoded_2, 3, 3) connect io.resp.`2`.vc_sel.`0`[3], _io_resp_2_vc_sel_0_3_T node _io_resp_2_vc_sel_0_4_T = bits(decoded_2, 4, 4) connect io.resp.`2`.vc_sel.`0`[4], _io_resp_2_vc_sel_0_4_T node _io_resp_2_vc_sel_0_5_T = bits(decoded_2, 5, 5) connect io.resp.`2`.vc_sel.`0`[5], _io_resp_2_vc_sel_0_5_T node _io_resp_2_vc_sel_0_6_T = bits(decoded_2, 6, 6) connect io.resp.`2`.vc_sel.`0`[6], _io_resp_2_vc_sel_0_6_T node _io_resp_2_vc_sel_0_7_T = bits(decoded_2, 7, 7) connect io.resp.`2`.vc_sel.`0`[7], _io_resp_2_vc_sel_0_7_T node _io_resp_2_vc_sel_0_8_T = bits(decoded_2, 8, 8) connect io.resp.`2`.vc_sel.`0`[8], _io_resp_2_vc_sel_0_8_T node _io_resp_2_vc_sel_0_9_T = bits(decoded_2, 9, 9) connect io.resp.`2`.vc_sel.`0`[9], _io_resp_2_vc_sel_0_9_T connect io.resp.`2`.vc_sel.`1`[0], UInt<1>(0h0) connect io.resp.`2`.vc_sel.`2`[0], UInt<1>(0h0) connect io.req.`3`.ready, UInt<1>(0h1) node addr_lo_3 = cat(io.req.`3`.bits.flow.egress_node, io.req.`3`.bits.flow.egress_node_id) node addr_hi_hi_3 = cat(io.req.`3`.bits.flow.vnet_id, io.req.`3`.bits.flow.ingress_node) node addr_hi_3 = cat(addr_hi_hi_3, io.req.`3`.bits.flow.ingress_node_id) node _addr_T_3 = cat(addr_hi_3, addr_lo_3) node addr_3 = cat(io.req.`3`.bits.src_virt_id, _addr_T_3) wire decoded_plaInput_3 : UInt<21> node decoded_invInputs_3 = not(decoded_plaInput_3) wire decoded_plaOutput_3 : UInt<10> node _decoded_orMatrixOutputs_T_22 = orr(UInt<1>(0h1)) node decoded_orMatrixOutputs_lo_lo_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_hi_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_hi_5 = cat(decoded_orMatrixOutputs_lo_hi_hi_5, UInt<1>(0h0)) node decoded_orMatrixOutputs_lo_7 = cat(decoded_orMatrixOutputs_lo_hi_5, decoded_orMatrixOutputs_lo_lo_5) node decoded_orMatrixOutputs_hi_lo_5 = cat(UInt<1>(0h0), UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_hi_hi_5 = cat(UInt<1>(0h0), _decoded_orMatrixOutputs_T_22) node decoded_orMatrixOutputs_hi_hi_6 = cat(decoded_orMatrixOutputs_hi_hi_hi_5, UInt<1>(0h0)) node decoded_orMatrixOutputs_hi_8 = cat(decoded_orMatrixOutputs_hi_hi_6, decoded_orMatrixOutputs_hi_lo_5) node decoded_orMatrixOutputs_3 = cat(decoded_orMatrixOutputs_hi_8, decoded_orMatrixOutputs_lo_7) node _decoded_invMatrixOutputs_T_30 = bits(decoded_orMatrixOutputs_3, 0, 0) node _decoded_invMatrixOutputs_T_31 = bits(decoded_orMatrixOutputs_3, 1, 1) node _decoded_invMatrixOutputs_T_32 = bits(decoded_orMatrixOutputs_3, 2, 2) node _decoded_invMatrixOutputs_T_33 = bits(decoded_orMatrixOutputs_3, 3, 3) node _decoded_invMatrixOutputs_T_34 = bits(decoded_orMatrixOutputs_3, 4, 4) node _decoded_invMatrixOutputs_T_35 = bits(decoded_orMatrixOutputs_3, 5, 5) node _decoded_invMatrixOutputs_T_36 = bits(decoded_orMatrixOutputs_3, 6, 6) node _decoded_invMatrixOutputs_T_37 = bits(decoded_orMatrixOutputs_3, 7, 7) node _decoded_invMatrixOutputs_T_38 = bits(decoded_orMatrixOutputs_3, 8, 8) node _decoded_invMatrixOutputs_T_39 = bits(decoded_orMatrixOutputs_3, 9, 9) node decoded_invMatrixOutputs_lo_lo_3 = cat(_decoded_invMatrixOutputs_T_31, _decoded_invMatrixOutputs_T_30) node decoded_invMatrixOutputs_lo_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_34, _decoded_invMatrixOutputs_T_33) node decoded_invMatrixOutputs_lo_hi_3 = cat(decoded_invMatrixOutputs_lo_hi_hi_3, _decoded_invMatrixOutputs_T_32) node decoded_invMatrixOutputs_lo_3 = cat(decoded_invMatrixOutputs_lo_hi_3, decoded_invMatrixOutputs_lo_lo_3) node decoded_invMatrixOutputs_hi_lo_3 = cat(_decoded_invMatrixOutputs_T_36, _decoded_invMatrixOutputs_T_35) node decoded_invMatrixOutputs_hi_hi_hi_3 = cat(_decoded_invMatrixOutputs_T_39, _decoded_invMatrixOutputs_T_38) node decoded_invMatrixOutputs_hi_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_hi_3, _decoded_invMatrixOutputs_T_37) node decoded_invMatrixOutputs_hi_3 = cat(decoded_invMatrixOutputs_hi_hi_3, decoded_invMatrixOutputs_hi_lo_3) node decoded_invMatrixOutputs_3 = cat(decoded_invMatrixOutputs_hi_3, decoded_invMatrixOutputs_lo_3) connect decoded_plaOutput_3, decoded_invMatrixOutputs_3 connect decoded_plaInput_3, addr_3 node _decoded_T_102 = bits(decoded_plaOutput_3, 7, 0) node _decoded_T_103 = shl(UInt<4>(0hf), 4) node _decoded_T_104 = xor(UInt<8>(0hff), _decoded_T_103) node _decoded_T_105 = shr(_decoded_T_102, 4) node _decoded_T_106 = and(_decoded_T_105, _decoded_T_104) node _decoded_T_107 = bits(_decoded_T_102, 3, 0) node _decoded_T_108 = shl(_decoded_T_107, 4) node _decoded_T_109 = not(_decoded_T_104) node _decoded_T_110 = and(_decoded_T_108, _decoded_T_109) node _decoded_T_111 = or(_decoded_T_106, _decoded_T_110) node _decoded_T_112 = bits(_decoded_T_104, 5, 0) node _decoded_T_113 = shl(_decoded_T_112, 2) node _decoded_T_114 = xor(_decoded_T_104, _decoded_T_113) node _decoded_T_115 = shr(_decoded_T_111, 2) node _decoded_T_116 = and(_decoded_T_115, _decoded_T_114) node _decoded_T_117 = bits(_decoded_T_111, 5, 0) node _decoded_T_118 = shl(_decoded_T_117, 2) node _decoded_T_119 = not(_decoded_T_114) node _decoded_T_120 = and(_decoded_T_118, _decoded_T_119) node _decoded_T_121 = or(_decoded_T_116, _decoded_T_120) node _decoded_T_122 = bits(_decoded_T_114, 6, 0) node _decoded_T_123 = shl(_decoded_T_122, 1) node _decoded_T_124 = xor(_decoded_T_114, _decoded_T_123) node _decoded_T_125 = shr(_decoded_T_121, 1) node _decoded_T_126 = and(_decoded_T_125, _decoded_T_124) node _decoded_T_127 = bits(_decoded_T_121, 6, 0) node _decoded_T_128 = shl(_decoded_T_127, 1) node _decoded_T_129 = not(_decoded_T_124) node _decoded_T_130 = and(_decoded_T_128, _decoded_T_129) node _decoded_T_131 = or(_decoded_T_126, _decoded_T_130) node _decoded_T_132 = bits(decoded_plaOutput_3, 9, 8) node _decoded_T_133 = bits(_decoded_T_132, 0, 0) node _decoded_T_134 = bits(_decoded_T_132, 1, 1) node _decoded_T_135 = cat(_decoded_T_133, _decoded_T_134) node decoded_3 = cat(_decoded_T_131, _decoded_T_135) node _io_resp_3_vc_sel_0_0_T = bits(decoded_3, 0, 0) connect io.resp.`3`.vc_sel.`0`[0], _io_resp_3_vc_sel_0_0_T node _io_resp_3_vc_sel_0_1_T = bits(decoded_3, 1, 1) connect io.resp.`3`.vc_sel.`0`[1], _io_resp_3_vc_sel_0_1_T node _io_resp_3_vc_sel_0_2_T = bits(decoded_3, 2, 2) connect io.resp.`3`.vc_sel.`0`[2], _io_resp_3_vc_sel_0_2_T node _io_resp_3_vc_sel_0_3_T = bits(decoded_3, 3, 3) connect io.resp.`3`.vc_sel.`0`[3], _io_resp_3_vc_sel_0_3_T node _io_resp_3_vc_sel_0_4_T = bits(decoded_3, 4, 4) connect io.resp.`3`.vc_sel.`0`[4], _io_resp_3_vc_sel_0_4_T node _io_resp_3_vc_sel_0_5_T = bits(decoded_3, 5, 5) connect io.resp.`3`.vc_sel.`0`[5], _io_resp_3_vc_sel_0_5_T node _io_resp_3_vc_sel_0_6_T = bits(decoded_3, 6, 6) connect io.resp.`3`.vc_sel.`0`[6], _io_resp_3_vc_sel_0_6_T node _io_resp_3_vc_sel_0_7_T = bits(decoded_3, 7, 7) connect io.resp.`3`.vc_sel.`0`[7], _io_resp_3_vc_sel_0_7_T node _io_resp_3_vc_sel_0_8_T = bits(decoded_3, 8, 8) connect io.resp.`3`.vc_sel.`0`[8], _io_resp_3_vc_sel_0_8_T node _io_resp_3_vc_sel_0_9_T = bits(decoded_3, 9, 9) connect io.resp.`3`.vc_sel.`0`[9], _io_resp_3_vc_sel_0_9_T connect io.resp.`3`.vc_sel.`1`[0], UInt<1>(0h0) connect io.resp.`3`.vc_sel.`2`[0], UInt<1>(0h0) extmodule plusarg_reader_12 : output out : UInt<20> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "noc_util_sample_rate=%d" parameter WIDTH = 20
module RouteComputer_2( // @[RouteComputer.scala:29:7] input [3:0] io_req_0_bits_src_virt_id, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_vnet_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_ingress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_ingress_node_id, // @[RouteComputer.scala:40:14] input [3:0] io_req_0_bits_flow_egress_node, // @[RouteComputer.scala:40:14] input [2:0] io_req_0_bits_flow_egress_node_id, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_0, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_1, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_2, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_3, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_4, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_5, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_6, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_7, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_8, // @[RouteComputer.scala:40:14] output io_resp_0_vc_sel_0_9 // @[RouteComputer.scala:40:14] ); wire [20:0] decoded_invInputs = ~{io_req_0_bits_src_virt_id, io_req_0_bits_flow_vnet_id, io_req_0_bits_flow_ingress_node, io_req_0_bits_flow_ingress_node_id, io_req_0_bits_flow_egress_node, io_req_0_bits_flow_egress_node_id}; // @[pla.scala:78:21] wire [17:0] _decoded_orMatrixOutputs_T_14 = {&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node_id[2], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], io_req_0_bits_flow_ingress_node_id[2], decoded_invInputs[10], decoded_invInputs[11], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[3], io_req_0_bits_flow_egress_node[2], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[2], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], decoded_invInputs[6], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:19] assign io_resp_0_vc_sel_0_0 = |{&{decoded_invInputs[0], io_req_0_bits_flow_egress_node_id[1], decoded_invInputs[2], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node_id[1], decoded_invInputs[2], decoded_invInputs[7], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], decoded_invInputs[16], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_1 = |{&{decoded_invInputs[0], io_req_0_bits_flow_egress_node_id[1], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], io_req_0_bits_flow_egress_node_id[1], decoded_invInputs[2], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_2 = |_decoded_orMatrixOutputs_T_14; // @[pla.scala:114:{19,36}] assign io_resp_0_vc_sel_0_3 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[15], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_4 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_ingress_node_id[0], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_5 = |{&{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{io_req_0_bits_flow_egress_node_id[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_6 = |{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[17], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[0], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_7 = |{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[0], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], io_req_0_bits_flow_ingress_node[1], io_req_0_bits_flow_ingress_node[2], decoded_invInputs[13], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], io_req_0_bits_flow_egress_node[1], decoded_invInputs[5], decoded_invInputs[6], decoded_invInputs[7], decoded_invInputs[8], decoded_invInputs[9], decoded_invInputs[10], decoded_invInputs[11], decoded_invInputs[12], io_req_0_bits_flow_ingress_node[3], io_req_0_bits_flow_vnet_id[0], io_req_0_bits_flow_vnet_id[1], decoded_invInputs[16], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_8 = |{&{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[7], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[2], decoded_invInputs[3], decoded_invInputs[7], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], decoded_invInputs[18], decoded_invInputs[19]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] assign io_resp_0_vc_sel_0_9 = |{&{decoded_invInputs[0], decoded_invInputs[7], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], io_req_0_bits_src_virt_id[0], decoded_invInputs[18], decoded_invInputs[19]}, &{decoded_invInputs[0], decoded_invInputs[1], decoded_invInputs[2], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}, &{decoded_invInputs[0], decoded_invInputs[2], io_req_0_bits_flow_egress_node[2], decoded_invInputs[11], decoded_invInputs[12], decoded_invInputs[13], decoded_invInputs[14], decoded_invInputs[15], io_req_0_bits_flow_vnet_id[2], io_req_0_bits_src_virt_id[0], decoded_invInputs[20]}}; // @[pla.scala:78:21, :90:45, :91:29, :98:{53,70}, :114:{19,36}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Tile_159 : input clock : Clock input reset : Reset output io : { flip in_a : SInt<8>[1], flip in_b : SInt<20>[1], flip in_d : SInt<20>[1], flip in_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], flip in_id : UInt<3>[1], flip in_last : UInt<1>[1], out_a : SInt<8>[1], out_c : SInt<20>[1], out_b : SInt<20>[1], out_control : { dataflow : UInt<1>, propagate : UInt<1>, shift : UInt<5>}[1], out_id : UInt<3>[1], out_last : UInt<1>[1], flip in_valid : UInt<1>[1], out_valid : UInt<1>[1], bad_dataflow : UInt<1>} inst tile_0_0 of PE_415 connect tile_0_0.clock, clock connect tile_0_0.reset, reset connect tile_0_0.io.in_a, io.in_a[0] connect tile_0_0.io.in_b, io.in_b[0] connect tile_0_0.io.in_d, io.in_d[0] connect tile_0_0.io.in_control.shift, io.in_control[0].shift connect tile_0_0.io.in_control.propagate, io.in_control[0].propagate connect tile_0_0.io.in_control.dataflow, io.in_control[0].dataflow connect tile_0_0.io.in_valid, io.in_valid[0] connect tile_0_0.io.in_id, io.in_id[0] connect tile_0_0.io.in_last, io.in_last[0] connect io.out_c[0], tile_0_0.io.out_c connect io.out_control[0], tile_0_0.io.out_control connect io.out_id[0], tile_0_0.io.out_id connect io.out_last[0], tile_0_0.io.out_last connect io.out_valid[0], tile_0_0.io.out_valid connect io.out_b[0], tile_0_0.io.out_b connect io.bad_dataflow, tile_0_0.io.bad_dataflow connect io.out_a[0], tile_0_0.io.out_a
module Tile_159( // @[Tile.scala:16:7] input clock, // @[Tile.scala:16:7] input reset, // @[Tile.scala:16:7] input [7:0] io_in_a_0, // @[Tile.scala:17:14] input [19:0] io_in_b_0, // @[Tile.scala:17:14] input [19:0] io_in_d_0, // @[Tile.scala:17:14] input io_in_control_0_dataflow, // @[Tile.scala:17:14] input io_in_control_0_propagate, // @[Tile.scala:17:14] input [4:0] io_in_control_0_shift, // @[Tile.scala:17:14] input [2:0] io_in_id_0, // @[Tile.scala:17:14] input io_in_last_0, // @[Tile.scala:17:14] output [19:0] io_out_c_0, // @[Tile.scala:17:14] output [19:0] io_out_b_0, // @[Tile.scala:17:14] output io_out_control_0_dataflow, // @[Tile.scala:17:14] output io_out_control_0_propagate, // @[Tile.scala:17:14] output [4:0] io_out_control_0_shift, // @[Tile.scala:17:14] output [2:0] io_out_id_0, // @[Tile.scala:17:14] output io_out_last_0, // @[Tile.scala:17:14] input io_in_valid_0, // @[Tile.scala:17:14] output io_out_valid_0, // @[Tile.scala:17:14] output io_bad_dataflow // @[Tile.scala:17:14] ); wire [7:0] io_in_a_0_0 = io_in_a_0; // @[Tile.scala:16:7] wire [19:0] io_in_b_0_0 = io_in_b_0; // @[Tile.scala:16:7] wire [19:0] io_in_d_0_0 = io_in_d_0; // @[Tile.scala:16:7] wire io_in_control_0_dataflow_0 = io_in_control_0_dataflow; // @[Tile.scala:16:7] wire io_in_control_0_propagate_0 = io_in_control_0_propagate; // @[Tile.scala:16:7] wire [4:0] io_in_control_0_shift_0 = io_in_control_0_shift; // @[Tile.scala:16:7] wire [2:0] io_in_id_0_0 = io_in_id_0; // @[Tile.scala:16:7] wire io_in_last_0_0 = io_in_last_0; // @[Tile.scala:16:7] wire io_in_valid_0_0 = io_in_valid_0; // @[Tile.scala:16:7] wire [7:0] io_out_a_0; // @[Tile.scala:16:7] wire [19:0] io_out_c_0_0; // @[Tile.scala:16:7] wire [19:0] io_out_b_0_0; // @[Tile.scala:16:7] wire io_out_control_0_dataflow_0; // @[Tile.scala:16:7] wire io_out_control_0_propagate_0; // @[Tile.scala:16:7] wire [4:0] io_out_control_0_shift_0; // @[Tile.scala:16:7] wire [2:0] io_out_id_0_0; // @[Tile.scala:16:7] wire io_out_last_0_0; // @[Tile.scala:16:7] wire io_out_valid_0_0; // @[Tile.scala:16:7] wire io_bad_dataflow_0; // @[Tile.scala:16:7] PE_415 tile_0_0 ( // @[Tile.scala:42:44] .clock (clock), .reset (reset), .io_in_a (io_in_a_0_0), // @[Tile.scala:16:7] .io_in_b (io_in_b_0_0), // @[Tile.scala:16:7] .io_in_d (io_in_d_0_0), // @[Tile.scala:16:7] .io_out_a (io_out_a_0), .io_out_b (io_out_b_0_0), .io_out_c (io_out_c_0_0), .io_in_control_dataflow (io_in_control_0_dataflow_0), // @[Tile.scala:16:7] .io_in_control_propagate (io_in_control_0_propagate_0), // @[Tile.scala:16:7] .io_in_control_shift (io_in_control_0_shift_0), // @[Tile.scala:16:7] .io_out_control_dataflow (io_out_control_0_dataflow_0), .io_out_control_propagate (io_out_control_0_propagate_0), .io_out_control_shift (io_out_control_0_shift_0), .io_in_id (io_in_id_0_0), // @[Tile.scala:16:7] .io_out_id (io_out_id_0_0), .io_in_last (io_in_last_0_0), // @[Tile.scala:16:7] .io_out_last (io_out_last_0_0), .io_in_valid (io_in_valid_0_0), // @[Tile.scala:16:7] .io_out_valid (io_out_valid_0_0), .io_bad_dataflow (io_bad_dataflow_0) ); // @[Tile.scala:42:44] assign io_out_c_0 = io_out_c_0_0; // @[Tile.scala:16:7] assign io_out_b_0 = io_out_b_0_0; // @[Tile.scala:16:7] assign io_out_control_0_dataflow = io_out_control_0_dataflow_0; // @[Tile.scala:16:7] assign io_out_control_0_propagate = io_out_control_0_propagate_0; // @[Tile.scala:16:7] assign io_out_control_0_shift = io_out_control_0_shift_0; // @[Tile.scala:16:7] assign io_out_id_0 = io_out_id_0_0; // @[Tile.scala:16:7] assign io_out_last_0 = io_out_last_0_0; // @[Tile.scala:16:7] assign io_out_valid_0 = io_out_valid_0_0; // @[Tile.scala:16:7] assign io_bad_dataflow = io_bad_dataflow_0; // @[Tile.scala:16:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PriorityQueueStage_53 : input clock : Clock input reset : Reset output io : { output_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, output_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_prev : { key : UInt<31>, value : { symbol : UInt<10>}}, flip input_nxt : { key : UInt<31>, value : { symbol : UInt<10>}}, flip cmd : { valid : UInt<1>, bits : UInt<1>}, flip insert_here : UInt<1>, flip cur_input_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}, cur_output_keyval : { key : UInt<31>, value : { symbol : UInt<10>}}} regreset key_reg : UInt<31>, clock, reset, UInt<31>(0h7fffffff) reg value_reg : { symbol : UInt<10>}, clock connect io.output_prev.key, key_reg connect io.output_prev.value, value_reg connect io.output_nxt.key, key_reg connect io.output_nxt.value, value_reg connect io.cur_output_keyval.key, key_reg connect io.cur_output_keyval.value, value_reg when io.cmd.valid : node _T = eq(UInt<1>(0h0), io.cmd.bits) when _T : connect key_reg, io.input_nxt.key connect value_reg, io.input_nxt.value else : node _T_1 = eq(UInt<1>(0h1), io.cmd.bits) when _T_1 : when io.insert_here : connect key_reg, io.cur_input_keyval.key connect value_reg, io.cur_input_keyval.value else : node _T_2 = geq(key_reg, io.cur_input_keyval.key) when _T_2 : connect key_reg, io.input_prev.key connect value_reg, io.input_prev.value else : skip
module PriorityQueueStage_53( // @[ShiftRegisterPriorityQueue.scala:21:7] input clock, // @[ShiftRegisterPriorityQueue.scala:21:7] input reset, // @[ShiftRegisterPriorityQueue.scala:21:7] output [30:0] io_output_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_output_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_output_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_prev_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_prev_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_input_nxt_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_input_nxt_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_valid, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_cmd_bits, // @[ShiftRegisterPriorityQueue.scala:22:14] input io_insert_here, // @[ShiftRegisterPriorityQueue.scala:22:14] input [30:0] io_cur_input_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] input [9:0] io_cur_input_keyval_value_symbol, // @[ShiftRegisterPriorityQueue.scala:22:14] output [30:0] io_cur_output_keyval_key, // @[ShiftRegisterPriorityQueue.scala:22:14] output [9:0] io_cur_output_keyval_value_symbol // @[ShiftRegisterPriorityQueue.scala:22:14] ); wire [30:0] io_input_prev_key_0 = io_input_prev_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_prev_value_symbol_0 = io_input_prev_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_input_nxt_key_0 = io_input_nxt_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_input_nxt_value_symbol_0 = io_input_nxt_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_valid_0 = io_cmd_valid; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_cmd_bits_0 = io_cmd_bits; // @[ShiftRegisterPriorityQueue.scala:21:7] wire io_insert_here_0 = io_insert_here; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_input_keyval_key_0 = io_cur_input_keyval_key; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_input_keyval_value_symbol_0 = io_cur_input_keyval_value_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [9:0] io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] wire [30:0] io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] reg [30:0] key_reg; // @[ShiftRegisterPriorityQueue.scala:30:24] assign io_output_prev_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_output_nxt_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] assign io_cur_output_keyval_key_0 = key_reg; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] reg [9:0] value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:31:22] assign io_output_prev_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_output_nxt_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] assign io_cur_output_keyval_value_symbol_0 = value_reg_symbol; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] wire _T_2 = key_reg >= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24, :52:30] always @(posedge clock) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (reset) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= 31'h7FFFFFFF; // @[ShiftRegisterPriorityQueue.scala:30:24] else if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_cur_input_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] key_reg <= io_input_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end else // @[ShiftRegisterPriorityQueue.scala:21:7] key_reg <= io_input_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :30:24] end if (io_cmd_valid_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_cmd_bits_0) begin // @[ShiftRegisterPriorityQueue.scala:21:7] if (io_insert_here_0) // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_cur_input_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] else if (_T_2) // @[ShiftRegisterPriorityQueue.scala:52:30] value_reg_symbol <= io_input_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end else // @[ShiftRegisterPriorityQueue.scala:21:7] value_reg_symbol <= io_input_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7, :31:22] end always @(posedge) assign io_output_prev_key = io_output_prev_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_prev_value_symbol = io_output_prev_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_key = io_output_nxt_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_output_nxt_value_symbol = io_output_nxt_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_key = io_cur_output_keyval_key_0; // @[ShiftRegisterPriorityQueue.scala:21:7] assign io_cur_output_keyval_value_symbol = io_cur_output_keyval_value_symbol_0; // @[ShiftRegisterPriorityQueue.scala:21:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_postMul_e11_s53 : output io : { flip fromPreMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}, flip mulAddResult : UInt<107>, flip roundingMode : UInt<3>, invalidExc : UInt<1>, rawOut : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<56>}} node roundingMode_min = eq(io.roundingMode, UInt<3>(0h2)) node opSignC = xor(io.fromPreMul.signProd, io.fromPreMul.doSubMags) node _sigSum_T = bits(io.mulAddResult, 106, 106) node _sigSum_T_1 = add(io.fromPreMul.highAlignedSigC, UInt<1>(0h1)) node _sigSum_T_2 = tail(_sigSum_T_1, 1) node _sigSum_T_3 = mux(_sigSum_T, _sigSum_T_2, io.fromPreMul.highAlignedSigC) node _sigSum_T_4 = bits(io.mulAddResult, 105, 0) node sigSum_hi = cat(_sigSum_T_3, _sigSum_T_4) node sigSum = cat(sigSum_hi, io.fromPreMul.bit0AlignedSigC) node _CDom_sExp_T = cvt(io.fromPreMul.doSubMags) node _CDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _CDom_sExp_T) node _CDom_sExp_T_2 = tail(_CDom_sExp_T_1, 1) node CDom_sExp = asSInt(_CDom_sExp_T_2) node _CDom_absSigSum_T = bits(sigSum, 161, 54) node _CDom_absSigSum_T_1 = not(_CDom_absSigSum_T) node _CDom_absSigSum_T_2 = bits(io.fromPreMul.highAlignedSigC, 54, 53) node _CDom_absSigSum_T_3 = cat(UInt<1>(0h0), _CDom_absSigSum_T_2) node _CDom_absSigSum_T_4 = bits(sigSum, 159, 55) node _CDom_absSigSum_T_5 = cat(_CDom_absSigSum_T_3, _CDom_absSigSum_T_4) node CDom_absSigSum = mux(io.fromPreMul.doSubMags, _CDom_absSigSum_T_1, _CDom_absSigSum_T_5) node _CDom_absSigSumExtra_T = bits(sigSum, 53, 1) node _CDom_absSigSumExtra_T_1 = not(_CDom_absSigSumExtra_T) node _CDom_absSigSumExtra_T_2 = orr(_CDom_absSigSumExtra_T_1) node _CDom_absSigSumExtra_T_3 = bits(sigSum, 54, 1) node _CDom_absSigSumExtra_T_4 = orr(_CDom_absSigSumExtra_T_3) node CDom_absSigSumExtra = mux(io.fromPreMul.doSubMags, _CDom_absSigSumExtra_T_2, _CDom_absSigSumExtra_T_4) node _CDom_mainSig_T = dshl(CDom_absSigSum, io.fromPreMul.CDom_CAlignDist) node CDom_mainSig = bits(_CDom_mainSig_T, 107, 50) node _CDom_reduced4SigExtra_T = bits(CDom_absSigSum, 52, 0) node _CDom_reduced4SigExtra_T_1 = shl(_CDom_reduced4SigExtra_T, 2) wire CDom_reduced4SigExtra_reducedVec : UInt<1>[14] node _CDom_reduced4SigExtra_reducedVec_0_T = bits(_CDom_reduced4SigExtra_T_1, 3, 0) node _CDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_0_T) connect CDom_reduced4SigExtra_reducedVec[0], _CDom_reduced4SigExtra_reducedVec_0_T_1 node _CDom_reduced4SigExtra_reducedVec_1_T = bits(_CDom_reduced4SigExtra_T_1, 7, 4) node _CDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_1_T) connect CDom_reduced4SigExtra_reducedVec[1], _CDom_reduced4SigExtra_reducedVec_1_T_1 node _CDom_reduced4SigExtra_reducedVec_2_T = bits(_CDom_reduced4SigExtra_T_1, 11, 8) node _CDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_2_T) connect CDom_reduced4SigExtra_reducedVec[2], _CDom_reduced4SigExtra_reducedVec_2_T_1 node _CDom_reduced4SigExtra_reducedVec_3_T = bits(_CDom_reduced4SigExtra_T_1, 15, 12) node _CDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_3_T) connect CDom_reduced4SigExtra_reducedVec[3], _CDom_reduced4SigExtra_reducedVec_3_T_1 node _CDom_reduced4SigExtra_reducedVec_4_T = bits(_CDom_reduced4SigExtra_T_1, 19, 16) node _CDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_4_T) connect CDom_reduced4SigExtra_reducedVec[4], _CDom_reduced4SigExtra_reducedVec_4_T_1 node _CDom_reduced4SigExtra_reducedVec_5_T = bits(_CDom_reduced4SigExtra_T_1, 23, 20) node _CDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_5_T) connect CDom_reduced4SigExtra_reducedVec[5], _CDom_reduced4SigExtra_reducedVec_5_T_1 node _CDom_reduced4SigExtra_reducedVec_6_T = bits(_CDom_reduced4SigExtra_T_1, 27, 24) node _CDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_6_T) connect CDom_reduced4SigExtra_reducedVec[6], _CDom_reduced4SigExtra_reducedVec_6_T_1 node _CDom_reduced4SigExtra_reducedVec_7_T = bits(_CDom_reduced4SigExtra_T_1, 31, 28) node _CDom_reduced4SigExtra_reducedVec_7_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_7_T) connect CDom_reduced4SigExtra_reducedVec[7], _CDom_reduced4SigExtra_reducedVec_7_T_1 node _CDom_reduced4SigExtra_reducedVec_8_T = bits(_CDom_reduced4SigExtra_T_1, 35, 32) node _CDom_reduced4SigExtra_reducedVec_8_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_8_T) connect CDom_reduced4SigExtra_reducedVec[8], _CDom_reduced4SigExtra_reducedVec_8_T_1 node _CDom_reduced4SigExtra_reducedVec_9_T = bits(_CDom_reduced4SigExtra_T_1, 39, 36) node _CDom_reduced4SigExtra_reducedVec_9_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_9_T) connect CDom_reduced4SigExtra_reducedVec[9], _CDom_reduced4SigExtra_reducedVec_9_T_1 node _CDom_reduced4SigExtra_reducedVec_10_T = bits(_CDom_reduced4SigExtra_T_1, 43, 40) node _CDom_reduced4SigExtra_reducedVec_10_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_10_T) connect CDom_reduced4SigExtra_reducedVec[10], _CDom_reduced4SigExtra_reducedVec_10_T_1 node _CDom_reduced4SigExtra_reducedVec_11_T = bits(_CDom_reduced4SigExtra_T_1, 47, 44) node _CDom_reduced4SigExtra_reducedVec_11_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_11_T) connect CDom_reduced4SigExtra_reducedVec[11], _CDom_reduced4SigExtra_reducedVec_11_T_1 node _CDom_reduced4SigExtra_reducedVec_12_T = bits(_CDom_reduced4SigExtra_T_1, 51, 48) node _CDom_reduced4SigExtra_reducedVec_12_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_12_T) connect CDom_reduced4SigExtra_reducedVec[12], _CDom_reduced4SigExtra_reducedVec_12_T_1 node _CDom_reduced4SigExtra_reducedVec_13_T = bits(_CDom_reduced4SigExtra_T_1, 54, 52) node _CDom_reduced4SigExtra_reducedVec_13_T_1 = orr(_CDom_reduced4SigExtra_reducedVec_13_T) connect CDom_reduced4SigExtra_reducedVec[13], _CDom_reduced4SigExtra_reducedVec_13_T_1 node CDom_reduced4SigExtra_lo_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[2], CDom_reduced4SigExtra_reducedVec[1]) node CDom_reduced4SigExtra_lo_lo = cat(CDom_reduced4SigExtra_lo_lo_hi, CDom_reduced4SigExtra_reducedVec[0]) node CDom_reduced4SigExtra_lo_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[4], CDom_reduced4SigExtra_reducedVec[3]) node CDom_reduced4SigExtra_lo_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[6], CDom_reduced4SigExtra_reducedVec[5]) node CDom_reduced4SigExtra_lo_hi = cat(CDom_reduced4SigExtra_lo_hi_hi, CDom_reduced4SigExtra_lo_hi_lo) node CDom_reduced4SigExtra_lo = cat(CDom_reduced4SigExtra_lo_hi, CDom_reduced4SigExtra_lo_lo) node CDom_reduced4SigExtra_hi_lo_hi = cat(CDom_reduced4SigExtra_reducedVec[9], CDom_reduced4SigExtra_reducedVec[8]) node CDom_reduced4SigExtra_hi_lo = cat(CDom_reduced4SigExtra_hi_lo_hi, CDom_reduced4SigExtra_reducedVec[7]) node CDom_reduced4SigExtra_hi_hi_lo = cat(CDom_reduced4SigExtra_reducedVec[11], CDom_reduced4SigExtra_reducedVec[10]) node CDom_reduced4SigExtra_hi_hi_hi = cat(CDom_reduced4SigExtra_reducedVec[13], CDom_reduced4SigExtra_reducedVec[12]) node CDom_reduced4SigExtra_hi_hi = cat(CDom_reduced4SigExtra_hi_hi_hi, CDom_reduced4SigExtra_hi_hi_lo) node CDom_reduced4SigExtra_hi = cat(CDom_reduced4SigExtra_hi_hi, CDom_reduced4SigExtra_hi_lo) node _CDom_reduced4SigExtra_T_2 = cat(CDom_reduced4SigExtra_hi, CDom_reduced4SigExtra_lo) node _CDom_reduced4SigExtra_T_3 = shr(io.fromPreMul.CDom_CAlignDist, 2) node _CDom_reduced4SigExtra_T_4 = not(_CDom_reduced4SigExtra_T_3) node CDom_reduced4SigExtra_shift = dshr(asSInt(UInt<17>(0h10000)), _CDom_reduced4SigExtra_T_4) node _CDom_reduced4SigExtra_T_5 = bits(CDom_reduced4SigExtra_shift, 13, 1) node _CDom_reduced4SigExtra_T_6 = bits(_CDom_reduced4SigExtra_T_5, 7, 0) node _CDom_reduced4SigExtra_T_7 = shl(UInt<4>(0hf), 4) node _CDom_reduced4SigExtra_T_8 = xor(UInt<8>(0hff), _CDom_reduced4SigExtra_T_7) node _CDom_reduced4SigExtra_T_9 = shr(_CDom_reduced4SigExtra_T_6, 4) node _CDom_reduced4SigExtra_T_10 = and(_CDom_reduced4SigExtra_T_9, _CDom_reduced4SigExtra_T_8) node _CDom_reduced4SigExtra_T_11 = bits(_CDom_reduced4SigExtra_T_6, 3, 0) node _CDom_reduced4SigExtra_T_12 = shl(_CDom_reduced4SigExtra_T_11, 4) node _CDom_reduced4SigExtra_T_13 = not(_CDom_reduced4SigExtra_T_8) node _CDom_reduced4SigExtra_T_14 = and(_CDom_reduced4SigExtra_T_12, _CDom_reduced4SigExtra_T_13) node _CDom_reduced4SigExtra_T_15 = or(_CDom_reduced4SigExtra_T_10, _CDom_reduced4SigExtra_T_14) node _CDom_reduced4SigExtra_T_16 = bits(_CDom_reduced4SigExtra_T_8, 5, 0) node _CDom_reduced4SigExtra_T_17 = shl(_CDom_reduced4SigExtra_T_16, 2) node _CDom_reduced4SigExtra_T_18 = xor(_CDom_reduced4SigExtra_T_8, _CDom_reduced4SigExtra_T_17) node _CDom_reduced4SigExtra_T_19 = shr(_CDom_reduced4SigExtra_T_15, 2) node _CDom_reduced4SigExtra_T_20 = and(_CDom_reduced4SigExtra_T_19, _CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_21 = bits(_CDom_reduced4SigExtra_T_15, 5, 0) node _CDom_reduced4SigExtra_T_22 = shl(_CDom_reduced4SigExtra_T_21, 2) node _CDom_reduced4SigExtra_T_23 = not(_CDom_reduced4SigExtra_T_18) node _CDom_reduced4SigExtra_T_24 = and(_CDom_reduced4SigExtra_T_22, _CDom_reduced4SigExtra_T_23) node _CDom_reduced4SigExtra_T_25 = or(_CDom_reduced4SigExtra_T_20, _CDom_reduced4SigExtra_T_24) node _CDom_reduced4SigExtra_T_26 = bits(_CDom_reduced4SigExtra_T_18, 6, 0) node _CDom_reduced4SigExtra_T_27 = shl(_CDom_reduced4SigExtra_T_26, 1) node _CDom_reduced4SigExtra_T_28 = xor(_CDom_reduced4SigExtra_T_18, _CDom_reduced4SigExtra_T_27) node _CDom_reduced4SigExtra_T_29 = shr(_CDom_reduced4SigExtra_T_25, 1) node _CDom_reduced4SigExtra_T_30 = and(_CDom_reduced4SigExtra_T_29, _CDom_reduced4SigExtra_T_28) node _CDom_reduced4SigExtra_T_31 = bits(_CDom_reduced4SigExtra_T_25, 6, 0) node _CDom_reduced4SigExtra_T_32 = shl(_CDom_reduced4SigExtra_T_31, 1) node _CDom_reduced4SigExtra_T_33 = not(_CDom_reduced4SigExtra_T_28) node _CDom_reduced4SigExtra_T_34 = and(_CDom_reduced4SigExtra_T_32, _CDom_reduced4SigExtra_T_33) node _CDom_reduced4SigExtra_T_35 = or(_CDom_reduced4SigExtra_T_30, _CDom_reduced4SigExtra_T_34) node _CDom_reduced4SigExtra_T_36 = bits(_CDom_reduced4SigExtra_T_5, 12, 8) node _CDom_reduced4SigExtra_T_37 = bits(_CDom_reduced4SigExtra_T_36, 3, 0) node _CDom_reduced4SigExtra_T_38 = bits(_CDom_reduced4SigExtra_T_37, 1, 0) node _CDom_reduced4SigExtra_T_39 = bits(_CDom_reduced4SigExtra_T_38, 0, 0) node _CDom_reduced4SigExtra_T_40 = bits(_CDom_reduced4SigExtra_T_38, 1, 1) node _CDom_reduced4SigExtra_T_41 = cat(_CDom_reduced4SigExtra_T_39, _CDom_reduced4SigExtra_T_40) node _CDom_reduced4SigExtra_T_42 = bits(_CDom_reduced4SigExtra_T_37, 3, 2) node _CDom_reduced4SigExtra_T_43 = bits(_CDom_reduced4SigExtra_T_42, 0, 0) node _CDom_reduced4SigExtra_T_44 = bits(_CDom_reduced4SigExtra_T_42, 1, 1) node _CDom_reduced4SigExtra_T_45 = cat(_CDom_reduced4SigExtra_T_43, _CDom_reduced4SigExtra_T_44) node _CDom_reduced4SigExtra_T_46 = cat(_CDom_reduced4SigExtra_T_41, _CDom_reduced4SigExtra_T_45) node _CDom_reduced4SigExtra_T_47 = bits(_CDom_reduced4SigExtra_T_36, 4, 4) node _CDom_reduced4SigExtra_T_48 = cat(_CDom_reduced4SigExtra_T_46, _CDom_reduced4SigExtra_T_47) node _CDom_reduced4SigExtra_T_49 = cat(_CDom_reduced4SigExtra_T_35, _CDom_reduced4SigExtra_T_48) node _CDom_reduced4SigExtra_T_50 = and(_CDom_reduced4SigExtra_T_2, _CDom_reduced4SigExtra_T_49) node CDom_reduced4SigExtra = orr(_CDom_reduced4SigExtra_T_50) node _CDom_sig_T = shr(CDom_mainSig, 3) node _CDom_sig_T_1 = bits(CDom_mainSig, 2, 0) node _CDom_sig_T_2 = orr(_CDom_sig_T_1) node _CDom_sig_T_3 = or(_CDom_sig_T_2, CDom_reduced4SigExtra) node _CDom_sig_T_4 = or(_CDom_sig_T_3, CDom_absSigSumExtra) node CDom_sig = cat(_CDom_sig_T, _CDom_sig_T_4) node notCDom_signSigSum = bits(sigSum, 109, 109) node _notCDom_absSigSum_T = bits(sigSum, 108, 0) node _notCDom_absSigSum_T_1 = not(_notCDom_absSigSum_T) node _notCDom_absSigSum_T_2 = bits(sigSum, 108, 0) node _notCDom_absSigSum_T_3 = add(_notCDom_absSigSum_T_2, io.fromPreMul.doSubMags) node _notCDom_absSigSum_T_4 = tail(_notCDom_absSigSum_T_3, 1) node notCDom_absSigSum = mux(notCDom_signSigSum, _notCDom_absSigSum_T_1, _notCDom_absSigSum_T_4) wire notCDom_reduced2AbsSigSum_reducedVec : UInt<1>[55] node _notCDom_reduced2AbsSigSum_reducedVec_0_T = bits(notCDom_absSigSum, 1, 0) node _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_0_T) connect notCDom_reduced2AbsSigSum_reducedVec[0], _notCDom_reduced2AbsSigSum_reducedVec_0_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_1_T = bits(notCDom_absSigSum, 3, 2) node _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_1_T) connect notCDom_reduced2AbsSigSum_reducedVec[1], _notCDom_reduced2AbsSigSum_reducedVec_1_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_2_T = bits(notCDom_absSigSum, 5, 4) node _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_2_T) connect notCDom_reduced2AbsSigSum_reducedVec[2], _notCDom_reduced2AbsSigSum_reducedVec_2_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_3_T = bits(notCDom_absSigSum, 7, 6) node _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_3_T) connect notCDom_reduced2AbsSigSum_reducedVec[3], _notCDom_reduced2AbsSigSum_reducedVec_3_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_4_T = bits(notCDom_absSigSum, 9, 8) node _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_4_T) connect notCDom_reduced2AbsSigSum_reducedVec[4], _notCDom_reduced2AbsSigSum_reducedVec_4_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_5_T = bits(notCDom_absSigSum, 11, 10) node _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_5_T) connect notCDom_reduced2AbsSigSum_reducedVec[5], _notCDom_reduced2AbsSigSum_reducedVec_5_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_6_T = bits(notCDom_absSigSum, 13, 12) node _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_6_T) connect notCDom_reduced2AbsSigSum_reducedVec[6], _notCDom_reduced2AbsSigSum_reducedVec_6_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_7_T = bits(notCDom_absSigSum, 15, 14) node _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_7_T) connect notCDom_reduced2AbsSigSum_reducedVec[7], _notCDom_reduced2AbsSigSum_reducedVec_7_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_8_T = bits(notCDom_absSigSum, 17, 16) node _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_8_T) connect notCDom_reduced2AbsSigSum_reducedVec[8], _notCDom_reduced2AbsSigSum_reducedVec_8_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_9_T = bits(notCDom_absSigSum, 19, 18) node _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_9_T) connect notCDom_reduced2AbsSigSum_reducedVec[9], _notCDom_reduced2AbsSigSum_reducedVec_9_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_10_T = bits(notCDom_absSigSum, 21, 20) node _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_10_T) connect notCDom_reduced2AbsSigSum_reducedVec[10], _notCDom_reduced2AbsSigSum_reducedVec_10_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_11_T = bits(notCDom_absSigSum, 23, 22) node _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_11_T) connect notCDom_reduced2AbsSigSum_reducedVec[11], _notCDom_reduced2AbsSigSum_reducedVec_11_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_12_T = bits(notCDom_absSigSum, 25, 24) node _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_12_T) connect notCDom_reduced2AbsSigSum_reducedVec[12], _notCDom_reduced2AbsSigSum_reducedVec_12_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_13_T = bits(notCDom_absSigSum, 27, 26) node _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_13_T) connect notCDom_reduced2AbsSigSum_reducedVec[13], _notCDom_reduced2AbsSigSum_reducedVec_13_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_14_T = bits(notCDom_absSigSum, 29, 28) node _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_14_T) connect notCDom_reduced2AbsSigSum_reducedVec[14], _notCDom_reduced2AbsSigSum_reducedVec_14_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_15_T = bits(notCDom_absSigSum, 31, 30) node _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_15_T) connect notCDom_reduced2AbsSigSum_reducedVec[15], _notCDom_reduced2AbsSigSum_reducedVec_15_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_16_T = bits(notCDom_absSigSum, 33, 32) node _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_16_T) connect notCDom_reduced2AbsSigSum_reducedVec[16], _notCDom_reduced2AbsSigSum_reducedVec_16_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_17_T = bits(notCDom_absSigSum, 35, 34) node _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_17_T) connect notCDom_reduced2AbsSigSum_reducedVec[17], _notCDom_reduced2AbsSigSum_reducedVec_17_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_18_T = bits(notCDom_absSigSum, 37, 36) node _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_18_T) connect notCDom_reduced2AbsSigSum_reducedVec[18], _notCDom_reduced2AbsSigSum_reducedVec_18_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_19_T = bits(notCDom_absSigSum, 39, 38) node _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_19_T) connect notCDom_reduced2AbsSigSum_reducedVec[19], _notCDom_reduced2AbsSigSum_reducedVec_19_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_20_T = bits(notCDom_absSigSum, 41, 40) node _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_20_T) connect notCDom_reduced2AbsSigSum_reducedVec[20], _notCDom_reduced2AbsSigSum_reducedVec_20_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_21_T = bits(notCDom_absSigSum, 43, 42) node _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_21_T) connect notCDom_reduced2AbsSigSum_reducedVec[21], _notCDom_reduced2AbsSigSum_reducedVec_21_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_22_T = bits(notCDom_absSigSum, 45, 44) node _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_22_T) connect notCDom_reduced2AbsSigSum_reducedVec[22], _notCDom_reduced2AbsSigSum_reducedVec_22_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_23_T = bits(notCDom_absSigSum, 47, 46) node _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_23_T) connect notCDom_reduced2AbsSigSum_reducedVec[23], _notCDom_reduced2AbsSigSum_reducedVec_23_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_24_T = bits(notCDom_absSigSum, 49, 48) node _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_24_T) connect notCDom_reduced2AbsSigSum_reducedVec[24], _notCDom_reduced2AbsSigSum_reducedVec_24_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_25_T = bits(notCDom_absSigSum, 51, 50) node _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_25_T) connect notCDom_reduced2AbsSigSum_reducedVec[25], _notCDom_reduced2AbsSigSum_reducedVec_25_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_26_T = bits(notCDom_absSigSum, 53, 52) node _notCDom_reduced2AbsSigSum_reducedVec_26_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_26_T) connect notCDom_reduced2AbsSigSum_reducedVec[26], _notCDom_reduced2AbsSigSum_reducedVec_26_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_27_T = bits(notCDom_absSigSum, 55, 54) node _notCDom_reduced2AbsSigSum_reducedVec_27_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_27_T) connect notCDom_reduced2AbsSigSum_reducedVec[27], _notCDom_reduced2AbsSigSum_reducedVec_27_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_28_T = bits(notCDom_absSigSum, 57, 56) node _notCDom_reduced2AbsSigSum_reducedVec_28_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_28_T) connect notCDom_reduced2AbsSigSum_reducedVec[28], _notCDom_reduced2AbsSigSum_reducedVec_28_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_29_T = bits(notCDom_absSigSum, 59, 58) node _notCDom_reduced2AbsSigSum_reducedVec_29_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_29_T) connect notCDom_reduced2AbsSigSum_reducedVec[29], _notCDom_reduced2AbsSigSum_reducedVec_29_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_30_T = bits(notCDom_absSigSum, 61, 60) node _notCDom_reduced2AbsSigSum_reducedVec_30_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_30_T) connect notCDom_reduced2AbsSigSum_reducedVec[30], _notCDom_reduced2AbsSigSum_reducedVec_30_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_31_T = bits(notCDom_absSigSum, 63, 62) node _notCDom_reduced2AbsSigSum_reducedVec_31_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_31_T) connect notCDom_reduced2AbsSigSum_reducedVec[31], _notCDom_reduced2AbsSigSum_reducedVec_31_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_32_T = bits(notCDom_absSigSum, 65, 64) node _notCDom_reduced2AbsSigSum_reducedVec_32_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_32_T) connect notCDom_reduced2AbsSigSum_reducedVec[32], _notCDom_reduced2AbsSigSum_reducedVec_32_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_33_T = bits(notCDom_absSigSum, 67, 66) node _notCDom_reduced2AbsSigSum_reducedVec_33_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_33_T) connect notCDom_reduced2AbsSigSum_reducedVec[33], _notCDom_reduced2AbsSigSum_reducedVec_33_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_34_T = bits(notCDom_absSigSum, 69, 68) node _notCDom_reduced2AbsSigSum_reducedVec_34_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_34_T) connect notCDom_reduced2AbsSigSum_reducedVec[34], _notCDom_reduced2AbsSigSum_reducedVec_34_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_35_T = bits(notCDom_absSigSum, 71, 70) node _notCDom_reduced2AbsSigSum_reducedVec_35_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_35_T) connect notCDom_reduced2AbsSigSum_reducedVec[35], _notCDom_reduced2AbsSigSum_reducedVec_35_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_36_T = bits(notCDom_absSigSum, 73, 72) node _notCDom_reduced2AbsSigSum_reducedVec_36_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_36_T) connect notCDom_reduced2AbsSigSum_reducedVec[36], _notCDom_reduced2AbsSigSum_reducedVec_36_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_37_T = bits(notCDom_absSigSum, 75, 74) node _notCDom_reduced2AbsSigSum_reducedVec_37_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_37_T) connect notCDom_reduced2AbsSigSum_reducedVec[37], _notCDom_reduced2AbsSigSum_reducedVec_37_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_38_T = bits(notCDom_absSigSum, 77, 76) node _notCDom_reduced2AbsSigSum_reducedVec_38_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_38_T) connect notCDom_reduced2AbsSigSum_reducedVec[38], _notCDom_reduced2AbsSigSum_reducedVec_38_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_39_T = bits(notCDom_absSigSum, 79, 78) node _notCDom_reduced2AbsSigSum_reducedVec_39_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_39_T) connect notCDom_reduced2AbsSigSum_reducedVec[39], _notCDom_reduced2AbsSigSum_reducedVec_39_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_40_T = bits(notCDom_absSigSum, 81, 80) node _notCDom_reduced2AbsSigSum_reducedVec_40_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_40_T) connect notCDom_reduced2AbsSigSum_reducedVec[40], _notCDom_reduced2AbsSigSum_reducedVec_40_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_41_T = bits(notCDom_absSigSum, 83, 82) node _notCDom_reduced2AbsSigSum_reducedVec_41_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_41_T) connect notCDom_reduced2AbsSigSum_reducedVec[41], _notCDom_reduced2AbsSigSum_reducedVec_41_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_42_T = bits(notCDom_absSigSum, 85, 84) node _notCDom_reduced2AbsSigSum_reducedVec_42_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_42_T) connect notCDom_reduced2AbsSigSum_reducedVec[42], _notCDom_reduced2AbsSigSum_reducedVec_42_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_43_T = bits(notCDom_absSigSum, 87, 86) node _notCDom_reduced2AbsSigSum_reducedVec_43_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_43_T) connect notCDom_reduced2AbsSigSum_reducedVec[43], _notCDom_reduced2AbsSigSum_reducedVec_43_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_44_T = bits(notCDom_absSigSum, 89, 88) node _notCDom_reduced2AbsSigSum_reducedVec_44_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_44_T) connect notCDom_reduced2AbsSigSum_reducedVec[44], _notCDom_reduced2AbsSigSum_reducedVec_44_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_45_T = bits(notCDom_absSigSum, 91, 90) node _notCDom_reduced2AbsSigSum_reducedVec_45_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_45_T) connect notCDom_reduced2AbsSigSum_reducedVec[45], _notCDom_reduced2AbsSigSum_reducedVec_45_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_46_T = bits(notCDom_absSigSum, 93, 92) node _notCDom_reduced2AbsSigSum_reducedVec_46_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_46_T) connect notCDom_reduced2AbsSigSum_reducedVec[46], _notCDom_reduced2AbsSigSum_reducedVec_46_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_47_T = bits(notCDom_absSigSum, 95, 94) node _notCDom_reduced2AbsSigSum_reducedVec_47_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_47_T) connect notCDom_reduced2AbsSigSum_reducedVec[47], _notCDom_reduced2AbsSigSum_reducedVec_47_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_48_T = bits(notCDom_absSigSum, 97, 96) node _notCDom_reduced2AbsSigSum_reducedVec_48_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_48_T) connect notCDom_reduced2AbsSigSum_reducedVec[48], _notCDom_reduced2AbsSigSum_reducedVec_48_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_49_T = bits(notCDom_absSigSum, 99, 98) node _notCDom_reduced2AbsSigSum_reducedVec_49_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_49_T) connect notCDom_reduced2AbsSigSum_reducedVec[49], _notCDom_reduced2AbsSigSum_reducedVec_49_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_50_T = bits(notCDom_absSigSum, 101, 100) node _notCDom_reduced2AbsSigSum_reducedVec_50_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_50_T) connect notCDom_reduced2AbsSigSum_reducedVec[50], _notCDom_reduced2AbsSigSum_reducedVec_50_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_51_T = bits(notCDom_absSigSum, 103, 102) node _notCDom_reduced2AbsSigSum_reducedVec_51_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_51_T) connect notCDom_reduced2AbsSigSum_reducedVec[51], _notCDom_reduced2AbsSigSum_reducedVec_51_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_52_T = bits(notCDom_absSigSum, 105, 104) node _notCDom_reduced2AbsSigSum_reducedVec_52_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_52_T) connect notCDom_reduced2AbsSigSum_reducedVec[52], _notCDom_reduced2AbsSigSum_reducedVec_52_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_53_T = bits(notCDom_absSigSum, 107, 106) node _notCDom_reduced2AbsSigSum_reducedVec_53_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_53_T) connect notCDom_reduced2AbsSigSum_reducedVec[53], _notCDom_reduced2AbsSigSum_reducedVec_53_T_1 node _notCDom_reduced2AbsSigSum_reducedVec_54_T = bits(notCDom_absSigSum, 108, 108) node _notCDom_reduced2AbsSigSum_reducedVec_54_T_1 = orr(_notCDom_reduced2AbsSigSum_reducedVec_54_T) connect notCDom_reduced2AbsSigSum_reducedVec[54], _notCDom_reduced2AbsSigSum_reducedVec_54_T_1 node notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[2], notCDom_reduced2AbsSigSum_reducedVec[1]) node notCDom_reduced2AbsSigSum_lo_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[0]) node notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[5], notCDom_reduced2AbsSigSum_reducedVec[4]) node notCDom_reduced2AbsSigSum_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_reducedVec[3]) node notCDom_reduced2AbsSigSum_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[8], notCDom_reduced2AbsSigSum_reducedVec[7]) node notCDom_reduced2AbsSigSum_lo_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[6]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[10], notCDom_reduced2AbsSigSum_reducedVec[9]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[12], notCDom_reduced2AbsSigSum_reducedVec[11]) node notCDom_reduced2AbsSigSum_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_lo_hi, notCDom_reduced2AbsSigSum_lo_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[15], notCDom_reduced2AbsSigSum_reducedVec[14]) node notCDom_reduced2AbsSigSum_lo_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[13]) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[17], notCDom_reduced2AbsSigSum_reducedVec[16]) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[19], notCDom_reduced2AbsSigSum_reducedVec[18]) node notCDom_reduced2AbsSigSum_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_lo_hi_lo_lo) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[22], notCDom_reduced2AbsSigSum_reducedVec[21]) node notCDom_reduced2AbsSigSum_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[20]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[24], notCDom_reduced2AbsSigSum_reducedVec[23]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[26], notCDom_reduced2AbsSigSum_reducedVec[25]) node notCDom_reduced2AbsSigSum_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_lo_hi = cat(notCDom_reduced2AbsSigSum_lo_hi_hi, notCDom_reduced2AbsSigSum_lo_hi_lo) node notCDom_reduced2AbsSigSum_lo = cat(notCDom_reduced2AbsSigSum_lo_hi, notCDom_reduced2AbsSigSum_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[29], notCDom_reduced2AbsSigSum_reducedVec[28]) node notCDom_reduced2AbsSigSum_hi_lo_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[27]) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[31], notCDom_reduced2AbsSigSum_reducedVec[30]) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[33], notCDom_reduced2AbsSigSum_reducedVec[32]) node notCDom_reduced2AbsSigSum_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_hi_lo) node notCDom_reduced2AbsSigSum_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo_lo) node notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[36], notCDom_reduced2AbsSigSum_reducedVec[35]) node notCDom_reduced2AbsSigSum_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[34]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[38], notCDom_reduced2AbsSigSum_reducedVec[37]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[40], notCDom_reduced2AbsSigSum_reducedVec[39]) node notCDom_reduced2AbsSigSum_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_lo_hi_lo) node notCDom_reduced2AbsSigSum_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[43], notCDom_reduced2AbsSigSum_reducedVec[42]) node notCDom_reduced2AbsSigSum_hi_hi_lo_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[41]) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[45], notCDom_reduced2AbsSigSum_reducedVec[44]) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[47], notCDom_reduced2AbsSigSum_reducedVec[46]) node notCDom_reduced2AbsSigSum_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_hi_hi_lo_lo) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[50], notCDom_reduced2AbsSigSum_reducedVec[49]) node notCDom_reduced2AbsSigSum_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_lo_hi, notCDom_reduced2AbsSigSum_reducedVec[48]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo = cat(notCDom_reduced2AbsSigSum_reducedVec[52], notCDom_reduced2AbsSigSum_reducedVec[51]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_reducedVec[54], notCDom_reduced2AbsSigSum_reducedVec[53]) node notCDom_reduced2AbsSigSum_hi_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi_hi = cat(notCDom_reduced2AbsSigSum_hi_hi_hi, notCDom_reduced2AbsSigSum_hi_hi_lo) node notCDom_reduced2AbsSigSum_hi = cat(notCDom_reduced2AbsSigSum_hi_hi, notCDom_reduced2AbsSigSum_hi_lo) node notCDom_reduced2AbsSigSum = cat(notCDom_reduced2AbsSigSum_hi, notCDom_reduced2AbsSigSum_lo) node _notCDom_normDistReduced2_T = bits(notCDom_reduced2AbsSigSum, 0, 0) node _notCDom_normDistReduced2_T_1 = bits(notCDom_reduced2AbsSigSum, 1, 1) node _notCDom_normDistReduced2_T_2 = bits(notCDom_reduced2AbsSigSum, 2, 2) node _notCDom_normDistReduced2_T_3 = bits(notCDom_reduced2AbsSigSum, 3, 3) node _notCDom_normDistReduced2_T_4 = bits(notCDom_reduced2AbsSigSum, 4, 4) node _notCDom_normDistReduced2_T_5 = bits(notCDom_reduced2AbsSigSum, 5, 5) node _notCDom_normDistReduced2_T_6 = bits(notCDom_reduced2AbsSigSum, 6, 6) node _notCDom_normDistReduced2_T_7 = bits(notCDom_reduced2AbsSigSum, 7, 7) node _notCDom_normDistReduced2_T_8 = bits(notCDom_reduced2AbsSigSum, 8, 8) node _notCDom_normDistReduced2_T_9 = bits(notCDom_reduced2AbsSigSum, 9, 9) node _notCDom_normDistReduced2_T_10 = bits(notCDom_reduced2AbsSigSum, 10, 10) node _notCDom_normDistReduced2_T_11 = bits(notCDom_reduced2AbsSigSum, 11, 11) node _notCDom_normDistReduced2_T_12 = bits(notCDom_reduced2AbsSigSum, 12, 12) node _notCDom_normDistReduced2_T_13 = bits(notCDom_reduced2AbsSigSum, 13, 13) node _notCDom_normDistReduced2_T_14 = bits(notCDom_reduced2AbsSigSum, 14, 14) node _notCDom_normDistReduced2_T_15 = bits(notCDom_reduced2AbsSigSum, 15, 15) node _notCDom_normDistReduced2_T_16 = bits(notCDom_reduced2AbsSigSum, 16, 16) node _notCDom_normDistReduced2_T_17 = bits(notCDom_reduced2AbsSigSum, 17, 17) node _notCDom_normDistReduced2_T_18 = bits(notCDom_reduced2AbsSigSum, 18, 18) node _notCDom_normDistReduced2_T_19 = bits(notCDom_reduced2AbsSigSum, 19, 19) node _notCDom_normDistReduced2_T_20 = bits(notCDom_reduced2AbsSigSum, 20, 20) node _notCDom_normDistReduced2_T_21 = bits(notCDom_reduced2AbsSigSum, 21, 21) node _notCDom_normDistReduced2_T_22 = bits(notCDom_reduced2AbsSigSum, 22, 22) node _notCDom_normDistReduced2_T_23 = bits(notCDom_reduced2AbsSigSum, 23, 23) node _notCDom_normDistReduced2_T_24 = bits(notCDom_reduced2AbsSigSum, 24, 24) node _notCDom_normDistReduced2_T_25 = bits(notCDom_reduced2AbsSigSum, 25, 25) node _notCDom_normDistReduced2_T_26 = bits(notCDom_reduced2AbsSigSum, 26, 26) node _notCDom_normDistReduced2_T_27 = bits(notCDom_reduced2AbsSigSum, 27, 27) node _notCDom_normDistReduced2_T_28 = bits(notCDom_reduced2AbsSigSum, 28, 28) node _notCDom_normDistReduced2_T_29 = bits(notCDom_reduced2AbsSigSum, 29, 29) node _notCDom_normDistReduced2_T_30 = bits(notCDom_reduced2AbsSigSum, 30, 30) node _notCDom_normDistReduced2_T_31 = bits(notCDom_reduced2AbsSigSum, 31, 31) node _notCDom_normDistReduced2_T_32 = bits(notCDom_reduced2AbsSigSum, 32, 32) node _notCDom_normDistReduced2_T_33 = bits(notCDom_reduced2AbsSigSum, 33, 33) node _notCDom_normDistReduced2_T_34 = bits(notCDom_reduced2AbsSigSum, 34, 34) node _notCDom_normDistReduced2_T_35 = bits(notCDom_reduced2AbsSigSum, 35, 35) node _notCDom_normDistReduced2_T_36 = bits(notCDom_reduced2AbsSigSum, 36, 36) node _notCDom_normDistReduced2_T_37 = bits(notCDom_reduced2AbsSigSum, 37, 37) node _notCDom_normDistReduced2_T_38 = bits(notCDom_reduced2AbsSigSum, 38, 38) node _notCDom_normDistReduced2_T_39 = bits(notCDom_reduced2AbsSigSum, 39, 39) node _notCDom_normDistReduced2_T_40 = bits(notCDom_reduced2AbsSigSum, 40, 40) node _notCDom_normDistReduced2_T_41 = bits(notCDom_reduced2AbsSigSum, 41, 41) node _notCDom_normDistReduced2_T_42 = bits(notCDom_reduced2AbsSigSum, 42, 42) node _notCDom_normDistReduced2_T_43 = bits(notCDom_reduced2AbsSigSum, 43, 43) node _notCDom_normDistReduced2_T_44 = bits(notCDom_reduced2AbsSigSum, 44, 44) node _notCDom_normDistReduced2_T_45 = bits(notCDom_reduced2AbsSigSum, 45, 45) node _notCDom_normDistReduced2_T_46 = bits(notCDom_reduced2AbsSigSum, 46, 46) node _notCDom_normDistReduced2_T_47 = bits(notCDom_reduced2AbsSigSum, 47, 47) node _notCDom_normDistReduced2_T_48 = bits(notCDom_reduced2AbsSigSum, 48, 48) node _notCDom_normDistReduced2_T_49 = bits(notCDom_reduced2AbsSigSum, 49, 49) node _notCDom_normDistReduced2_T_50 = bits(notCDom_reduced2AbsSigSum, 50, 50) node _notCDom_normDistReduced2_T_51 = bits(notCDom_reduced2AbsSigSum, 51, 51) node _notCDom_normDistReduced2_T_52 = bits(notCDom_reduced2AbsSigSum, 52, 52) node _notCDom_normDistReduced2_T_53 = bits(notCDom_reduced2AbsSigSum, 53, 53) node _notCDom_normDistReduced2_T_54 = bits(notCDom_reduced2AbsSigSum, 54, 54) node _notCDom_normDistReduced2_T_55 = mux(_notCDom_normDistReduced2_T_1, UInt<6>(0h35), UInt<6>(0h36)) node _notCDom_normDistReduced2_T_56 = mux(_notCDom_normDistReduced2_T_2, UInt<6>(0h34), _notCDom_normDistReduced2_T_55) node _notCDom_normDistReduced2_T_57 = mux(_notCDom_normDistReduced2_T_3, UInt<6>(0h33), _notCDom_normDistReduced2_T_56) node _notCDom_normDistReduced2_T_58 = mux(_notCDom_normDistReduced2_T_4, UInt<6>(0h32), _notCDom_normDistReduced2_T_57) node _notCDom_normDistReduced2_T_59 = mux(_notCDom_normDistReduced2_T_5, UInt<6>(0h31), _notCDom_normDistReduced2_T_58) node _notCDom_normDistReduced2_T_60 = mux(_notCDom_normDistReduced2_T_6, UInt<6>(0h30), _notCDom_normDistReduced2_T_59) node _notCDom_normDistReduced2_T_61 = mux(_notCDom_normDistReduced2_T_7, UInt<6>(0h2f), _notCDom_normDistReduced2_T_60) node _notCDom_normDistReduced2_T_62 = mux(_notCDom_normDistReduced2_T_8, UInt<6>(0h2e), _notCDom_normDistReduced2_T_61) node _notCDom_normDistReduced2_T_63 = mux(_notCDom_normDistReduced2_T_9, UInt<6>(0h2d), _notCDom_normDistReduced2_T_62) node _notCDom_normDistReduced2_T_64 = mux(_notCDom_normDistReduced2_T_10, UInt<6>(0h2c), _notCDom_normDistReduced2_T_63) node _notCDom_normDistReduced2_T_65 = mux(_notCDom_normDistReduced2_T_11, UInt<6>(0h2b), _notCDom_normDistReduced2_T_64) node _notCDom_normDistReduced2_T_66 = mux(_notCDom_normDistReduced2_T_12, UInt<6>(0h2a), _notCDom_normDistReduced2_T_65) node _notCDom_normDistReduced2_T_67 = mux(_notCDom_normDistReduced2_T_13, UInt<6>(0h29), _notCDom_normDistReduced2_T_66) node _notCDom_normDistReduced2_T_68 = mux(_notCDom_normDistReduced2_T_14, UInt<6>(0h28), _notCDom_normDistReduced2_T_67) node _notCDom_normDistReduced2_T_69 = mux(_notCDom_normDistReduced2_T_15, UInt<6>(0h27), _notCDom_normDistReduced2_T_68) node _notCDom_normDistReduced2_T_70 = mux(_notCDom_normDistReduced2_T_16, UInt<6>(0h26), _notCDom_normDistReduced2_T_69) node _notCDom_normDistReduced2_T_71 = mux(_notCDom_normDistReduced2_T_17, UInt<6>(0h25), _notCDom_normDistReduced2_T_70) node _notCDom_normDistReduced2_T_72 = mux(_notCDom_normDistReduced2_T_18, UInt<6>(0h24), _notCDom_normDistReduced2_T_71) node _notCDom_normDistReduced2_T_73 = mux(_notCDom_normDistReduced2_T_19, UInt<6>(0h23), _notCDom_normDistReduced2_T_72) node _notCDom_normDistReduced2_T_74 = mux(_notCDom_normDistReduced2_T_20, UInt<6>(0h22), _notCDom_normDistReduced2_T_73) node _notCDom_normDistReduced2_T_75 = mux(_notCDom_normDistReduced2_T_21, UInt<6>(0h21), _notCDom_normDistReduced2_T_74) node _notCDom_normDistReduced2_T_76 = mux(_notCDom_normDistReduced2_T_22, UInt<6>(0h20), _notCDom_normDistReduced2_T_75) node _notCDom_normDistReduced2_T_77 = mux(_notCDom_normDistReduced2_T_23, UInt<5>(0h1f), _notCDom_normDistReduced2_T_76) node _notCDom_normDistReduced2_T_78 = mux(_notCDom_normDistReduced2_T_24, UInt<5>(0h1e), _notCDom_normDistReduced2_T_77) node _notCDom_normDistReduced2_T_79 = mux(_notCDom_normDistReduced2_T_25, UInt<5>(0h1d), _notCDom_normDistReduced2_T_78) node _notCDom_normDistReduced2_T_80 = mux(_notCDom_normDistReduced2_T_26, UInt<5>(0h1c), _notCDom_normDistReduced2_T_79) node _notCDom_normDistReduced2_T_81 = mux(_notCDom_normDistReduced2_T_27, UInt<5>(0h1b), _notCDom_normDistReduced2_T_80) node _notCDom_normDistReduced2_T_82 = mux(_notCDom_normDistReduced2_T_28, UInt<5>(0h1a), _notCDom_normDistReduced2_T_81) node _notCDom_normDistReduced2_T_83 = mux(_notCDom_normDistReduced2_T_29, UInt<5>(0h19), _notCDom_normDistReduced2_T_82) node _notCDom_normDistReduced2_T_84 = mux(_notCDom_normDistReduced2_T_30, UInt<5>(0h18), _notCDom_normDistReduced2_T_83) node _notCDom_normDistReduced2_T_85 = mux(_notCDom_normDistReduced2_T_31, UInt<5>(0h17), _notCDom_normDistReduced2_T_84) node _notCDom_normDistReduced2_T_86 = mux(_notCDom_normDistReduced2_T_32, UInt<5>(0h16), _notCDom_normDistReduced2_T_85) node _notCDom_normDistReduced2_T_87 = mux(_notCDom_normDistReduced2_T_33, UInt<5>(0h15), _notCDom_normDistReduced2_T_86) node _notCDom_normDistReduced2_T_88 = mux(_notCDom_normDistReduced2_T_34, UInt<5>(0h14), _notCDom_normDistReduced2_T_87) node _notCDom_normDistReduced2_T_89 = mux(_notCDom_normDistReduced2_T_35, UInt<5>(0h13), _notCDom_normDistReduced2_T_88) node _notCDom_normDistReduced2_T_90 = mux(_notCDom_normDistReduced2_T_36, UInt<5>(0h12), _notCDom_normDistReduced2_T_89) node _notCDom_normDistReduced2_T_91 = mux(_notCDom_normDistReduced2_T_37, UInt<5>(0h11), _notCDom_normDistReduced2_T_90) node _notCDom_normDistReduced2_T_92 = mux(_notCDom_normDistReduced2_T_38, UInt<5>(0h10), _notCDom_normDistReduced2_T_91) node _notCDom_normDistReduced2_T_93 = mux(_notCDom_normDistReduced2_T_39, UInt<4>(0hf), _notCDom_normDistReduced2_T_92) node _notCDom_normDistReduced2_T_94 = mux(_notCDom_normDistReduced2_T_40, UInt<4>(0he), _notCDom_normDistReduced2_T_93) node _notCDom_normDistReduced2_T_95 = mux(_notCDom_normDistReduced2_T_41, UInt<4>(0hd), _notCDom_normDistReduced2_T_94) node _notCDom_normDistReduced2_T_96 = mux(_notCDom_normDistReduced2_T_42, UInt<4>(0hc), _notCDom_normDistReduced2_T_95) node _notCDom_normDistReduced2_T_97 = mux(_notCDom_normDistReduced2_T_43, UInt<4>(0hb), _notCDom_normDistReduced2_T_96) node _notCDom_normDistReduced2_T_98 = mux(_notCDom_normDistReduced2_T_44, UInt<4>(0ha), _notCDom_normDistReduced2_T_97) node _notCDom_normDistReduced2_T_99 = mux(_notCDom_normDistReduced2_T_45, UInt<4>(0h9), _notCDom_normDistReduced2_T_98) node _notCDom_normDistReduced2_T_100 = mux(_notCDom_normDistReduced2_T_46, UInt<4>(0h8), _notCDom_normDistReduced2_T_99) node _notCDom_normDistReduced2_T_101 = mux(_notCDom_normDistReduced2_T_47, UInt<3>(0h7), _notCDom_normDistReduced2_T_100) node _notCDom_normDistReduced2_T_102 = mux(_notCDom_normDistReduced2_T_48, UInt<3>(0h6), _notCDom_normDistReduced2_T_101) node _notCDom_normDistReduced2_T_103 = mux(_notCDom_normDistReduced2_T_49, UInt<3>(0h5), _notCDom_normDistReduced2_T_102) node _notCDom_normDistReduced2_T_104 = mux(_notCDom_normDistReduced2_T_50, UInt<3>(0h4), _notCDom_normDistReduced2_T_103) node _notCDom_normDistReduced2_T_105 = mux(_notCDom_normDistReduced2_T_51, UInt<2>(0h3), _notCDom_normDistReduced2_T_104) node _notCDom_normDistReduced2_T_106 = mux(_notCDom_normDistReduced2_T_52, UInt<2>(0h2), _notCDom_normDistReduced2_T_105) node _notCDom_normDistReduced2_T_107 = mux(_notCDom_normDistReduced2_T_53, UInt<1>(0h1), _notCDom_normDistReduced2_T_106) node notCDom_normDistReduced2 = mux(_notCDom_normDistReduced2_T_54, UInt<1>(0h0), _notCDom_normDistReduced2_T_107) node notCDom_nearNormDist = shl(notCDom_normDistReduced2, 1) node _notCDom_sExp_T = cvt(notCDom_nearNormDist) node _notCDom_sExp_T_1 = sub(io.fromPreMul.sExpSum, _notCDom_sExp_T) node _notCDom_sExp_T_2 = tail(_notCDom_sExp_T_1, 1) node notCDom_sExp = asSInt(_notCDom_sExp_T_2) node _notCDom_mainSig_T = dshl(notCDom_absSigSum, notCDom_nearNormDist) node notCDom_mainSig = bits(_notCDom_mainSig_T, 109, 52) node _notCDom_reduced4SigExtra_T = bits(notCDom_reduced2AbsSigSum, 26, 0) node _notCDom_reduced4SigExtra_T_1 = shl(_notCDom_reduced4SigExtra_T, 0) wire notCDom_reduced4SigExtra_reducedVec : UInt<1>[14] node _notCDom_reduced4SigExtra_reducedVec_0_T = bits(_notCDom_reduced4SigExtra_T_1, 1, 0) node _notCDom_reduced4SigExtra_reducedVec_0_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_0_T) connect notCDom_reduced4SigExtra_reducedVec[0], _notCDom_reduced4SigExtra_reducedVec_0_T_1 node _notCDom_reduced4SigExtra_reducedVec_1_T = bits(_notCDom_reduced4SigExtra_T_1, 3, 2) node _notCDom_reduced4SigExtra_reducedVec_1_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_1_T) connect notCDom_reduced4SigExtra_reducedVec[1], _notCDom_reduced4SigExtra_reducedVec_1_T_1 node _notCDom_reduced4SigExtra_reducedVec_2_T = bits(_notCDom_reduced4SigExtra_T_1, 5, 4) node _notCDom_reduced4SigExtra_reducedVec_2_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_2_T) connect notCDom_reduced4SigExtra_reducedVec[2], _notCDom_reduced4SigExtra_reducedVec_2_T_1 node _notCDom_reduced4SigExtra_reducedVec_3_T = bits(_notCDom_reduced4SigExtra_T_1, 7, 6) node _notCDom_reduced4SigExtra_reducedVec_3_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_3_T) connect notCDom_reduced4SigExtra_reducedVec[3], _notCDom_reduced4SigExtra_reducedVec_3_T_1 node _notCDom_reduced4SigExtra_reducedVec_4_T = bits(_notCDom_reduced4SigExtra_T_1, 9, 8) node _notCDom_reduced4SigExtra_reducedVec_4_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_4_T) connect notCDom_reduced4SigExtra_reducedVec[4], _notCDom_reduced4SigExtra_reducedVec_4_T_1 node _notCDom_reduced4SigExtra_reducedVec_5_T = bits(_notCDom_reduced4SigExtra_T_1, 11, 10) node _notCDom_reduced4SigExtra_reducedVec_5_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_5_T) connect notCDom_reduced4SigExtra_reducedVec[5], _notCDom_reduced4SigExtra_reducedVec_5_T_1 node _notCDom_reduced4SigExtra_reducedVec_6_T = bits(_notCDom_reduced4SigExtra_T_1, 13, 12) node _notCDom_reduced4SigExtra_reducedVec_6_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_6_T) connect notCDom_reduced4SigExtra_reducedVec[6], _notCDom_reduced4SigExtra_reducedVec_6_T_1 node _notCDom_reduced4SigExtra_reducedVec_7_T = bits(_notCDom_reduced4SigExtra_T_1, 15, 14) node _notCDom_reduced4SigExtra_reducedVec_7_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_7_T) connect notCDom_reduced4SigExtra_reducedVec[7], _notCDom_reduced4SigExtra_reducedVec_7_T_1 node _notCDom_reduced4SigExtra_reducedVec_8_T = bits(_notCDom_reduced4SigExtra_T_1, 17, 16) node _notCDom_reduced4SigExtra_reducedVec_8_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_8_T) connect notCDom_reduced4SigExtra_reducedVec[8], _notCDom_reduced4SigExtra_reducedVec_8_T_1 node _notCDom_reduced4SigExtra_reducedVec_9_T = bits(_notCDom_reduced4SigExtra_T_1, 19, 18) node _notCDom_reduced4SigExtra_reducedVec_9_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_9_T) connect notCDom_reduced4SigExtra_reducedVec[9], _notCDom_reduced4SigExtra_reducedVec_9_T_1 node _notCDom_reduced4SigExtra_reducedVec_10_T = bits(_notCDom_reduced4SigExtra_T_1, 21, 20) node _notCDom_reduced4SigExtra_reducedVec_10_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_10_T) connect notCDom_reduced4SigExtra_reducedVec[10], _notCDom_reduced4SigExtra_reducedVec_10_T_1 node _notCDom_reduced4SigExtra_reducedVec_11_T = bits(_notCDom_reduced4SigExtra_T_1, 23, 22) node _notCDom_reduced4SigExtra_reducedVec_11_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_11_T) connect notCDom_reduced4SigExtra_reducedVec[11], _notCDom_reduced4SigExtra_reducedVec_11_T_1 node _notCDom_reduced4SigExtra_reducedVec_12_T = bits(_notCDom_reduced4SigExtra_T_1, 25, 24) node _notCDom_reduced4SigExtra_reducedVec_12_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_12_T) connect notCDom_reduced4SigExtra_reducedVec[12], _notCDom_reduced4SigExtra_reducedVec_12_T_1 node _notCDom_reduced4SigExtra_reducedVec_13_T = bits(_notCDom_reduced4SigExtra_T_1, 26, 26) node _notCDom_reduced4SigExtra_reducedVec_13_T_1 = orr(_notCDom_reduced4SigExtra_reducedVec_13_T) connect notCDom_reduced4SigExtra_reducedVec[13], _notCDom_reduced4SigExtra_reducedVec_13_T_1 node notCDom_reduced4SigExtra_lo_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[2], notCDom_reduced4SigExtra_reducedVec[1]) node notCDom_reduced4SigExtra_lo_lo = cat(notCDom_reduced4SigExtra_lo_lo_hi, notCDom_reduced4SigExtra_reducedVec[0]) node notCDom_reduced4SigExtra_lo_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[4], notCDom_reduced4SigExtra_reducedVec[3]) node notCDom_reduced4SigExtra_lo_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[6], notCDom_reduced4SigExtra_reducedVec[5]) node notCDom_reduced4SigExtra_lo_hi = cat(notCDom_reduced4SigExtra_lo_hi_hi, notCDom_reduced4SigExtra_lo_hi_lo) node notCDom_reduced4SigExtra_lo = cat(notCDom_reduced4SigExtra_lo_hi, notCDom_reduced4SigExtra_lo_lo) node notCDom_reduced4SigExtra_hi_lo_hi = cat(notCDom_reduced4SigExtra_reducedVec[9], notCDom_reduced4SigExtra_reducedVec[8]) node notCDom_reduced4SigExtra_hi_lo = cat(notCDom_reduced4SigExtra_hi_lo_hi, notCDom_reduced4SigExtra_reducedVec[7]) node notCDom_reduced4SigExtra_hi_hi_lo = cat(notCDom_reduced4SigExtra_reducedVec[11], notCDom_reduced4SigExtra_reducedVec[10]) node notCDom_reduced4SigExtra_hi_hi_hi = cat(notCDom_reduced4SigExtra_reducedVec[13], notCDom_reduced4SigExtra_reducedVec[12]) node notCDom_reduced4SigExtra_hi_hi = cat(notCDom_reduced4SigExtra_hi_hi_hi, notCDom_reduced4SigExtra_hi_hi_lo) node notCDom_reduced4SigExtra_hi = cat(notCDom_reduced4SigExtra_hi_hi, notCDom_reduced4SigExtra_hi_lo) node _notCDom_reduced4SigExtra_T_2 = cat(notCDom_reduced4SigExtra_hi, notCDom_reduced4SigExtra_lo) node _notCDom_reduced4SigExtra_T_3 = shr(notCDom_normDistReduced2, 1) node _notCDom_reduced4SigExtra_T_4 = not(_notCDom_reduced4SigExtra_T_3) node notCDom_reduced4SigExtra_shift = dshr(asSInt(UInt<33>(0h100000000)), _notCDom_reduced4SigExtra_T_4) node _notCDom_reduced4SigExtra_T_5 = bits(notCDom_reduced4SigExtra_shift, 13, 1) node _notCDom_reduced4SigExtra_T_6 = bits(_notCDom_reduced4SigExtra_T_5, 7, 0) node _notCDom_reduced4SigExtra_T_7 = shl(UInt<4>(0hf), 4) node _notCDom_reduced4SigExtra_T_8 = xor(UInt<8>(0hff), _notCDom_reduced4SigExtra_T_7) node _notCDom_reduced4SigExtra_T_9 = shr(_notCDom_reduced4SigExtra_T_6, 4) node _notCDom_reduced4SigExtra_T_10 = and(_notCDom_reduced4SigExtra_T_9, _notCDom_reduced4SigExtra_T_8) node _notCDom_reduced4SigExtra_T_11 = bits(_notCDom_reduced4SigExtra_T_6, 3, 0) node _notCDom_reduced4SigExtra_T_12 = shl(_notCDom_reduced4SigExtra_T_11, 4) node _notCDom_reduced4SigExtra_T_13 = not(_notCDom_reduced4SigExtra_T_8) node _notCDom_reduced4SigExtra_T_14 = and(_notCDom_reduced4SigExtra_T_12, _notCDom_reduced4SigExtra_T_13) node _notCDom_reduced4SigExtra_T_15 = or(_notCDom_reduced4SigExtra_T_10, _notCDom_reduced4SigExtra_T_14) node _notCDom_reduced4SigExtra_T_16 = bits(_notCDom_reduced4SigExtra_T_8, 5, 0) node _notCDom_reduced4SigExtra_T_17 = shl(_notCDom_reduced4SigExtra_T_16, 2) node _notCDom_reduced4SigExtra_T_18 = xor(_notCDom_reduced4SigExtra_T_8, _notCDom_reduced4SigExtra_T_17) node _notCDom_reduced4SigExtra_T_19 = shr(_notCDom_reduced4SigExtra_T_15, 2) node _notCDom_reduced4SigExtra_T_20 = and(_notCDom_reduced4SigExtra_T_19, _notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_21 = bits(_notCDom_reduced4SigExtra_T_15, 5, 0) node _notCDom_reduced4SigExtra_T_22 = shl(_notCDom_reduced4SigExtra_T_21, 2) node _notCDom_reduced4SigExtra_T_23 = not(_notCDom_reduced4SigExtra_T_18) node _notCDom_reduced4SigExtra_T_24 = and(_notCDom_reduced4SigExtra_T_22, _notCDom_reduced4SigExtra_T_23) node _notCDom_reduced4SigExtra_T_25 = or(_notCDom_reduced4SigExtra_T_20, _notCDom_reduced4SigExtra_T_24) node _notCDom_reduced4SigExtra_T_26 = bits(_notCDom_reduced4SigExtra_T_18, 6, 0) node _notCDom_reduced4SigExtra_T_27 = shl(_notCDom_reduced4SigExtra_T_26, 1) node _notCDom_reduced4SigExtra_T_28 = xor(_notCDom_reduced4SigExtra_T_18, _notCDom_reduced4SigExtra_T_27) node _notCDom_reduced4SigExtra_T_29 = shr(_notCDom_reduced4SigExtra_T_25, 1) node _notCDom_reduced4SigExtra_T_30 = and(_notCDom_reduced4SigExtra_T_29, _notCDom_reduced4SigExtra_T_28) node _notCDom_reduced4SigExtra_T_31 = bits(_notCDom_reduced4SigExtra_T_25, 6, 0) node _notCDom_reduced4SigExtra_T_32 = shl(_notCDom_reduced4SigExtra_T_31, 1) node _notCDom_reduced4SigExtra_T_33 = not(_notCDom_reduced4SigExtra_T_28) node _notCDom_reduced4SigExtra_T_34 = and(_notCDom_reduced4SigExtra_T_32, _notCDom_reduced4SigExtra_T_33) node _notCDom_reduced4SigExtra_T_35 = or(_notCDom_reduced4SigExtra_T_30, _notCDom_reduced4SigExtra_T_34) node _notCDom_reduced4SigExtra_T_36 = bits(_notCDom_reduced4SigExtra_T_5, 12, 8) node _notCDom_reduced4SigExtra_T_37 = bits(_notCDom_reduced4SigExtra_T_36, 3, 0) node _notCDom_reduced4SigExtra_T_38 = bits(_notCDom_reduced4SigExtra_T_37, 1, 0) node _notCDom_reduced4SigExtra_T_39 = bits(_notCDom_reduced4SigExtra_T_38, 0, 0) node _notCDom_reduced4SigExtra_T_40 = bits(_notCDom_reduced4SigExtra_T_38, 1, 1) node _notCDom_reduced4SigExtra_T_41 = cat(_notCDom_reduced4SigExtra_T_39, _notCDom_reduced4SigExtra_T_40) node _notCDom_reduced4SigExtra_T_42 = bits(_notCDom_reduced4SigExtra_T_37, 3, 2) node _notCDom_reduced4SigExtra_T_43 = bits(_notCDom_reduced4SigExtra_T_42, 0, 0) node _notCDom_reduced4SigExtra_T_44 = bits(_notCDom_reduced4SigExtra_T_42, 1, 1) node _notCDom_reduced4SigExtra_T_45 = cat(_notCDom_reduced4SigExtra_T_43, _notCDom_reduced4SigExtra_T_44) node _notCDom_reduced4SigExtra_T_46 = cat(_notCDom_reduced4SigExtra_T_41, _notCDom_reduced4SigExtra_T_45) node _notCDom_reduced4SigExtra_T_47 = bits(_notCDom_reduced4SigExtra_T_36, 4, 4) node _notCDom_reduced4SigExtra_T_48 = cat(_notCDom_reduced4SigExtra_T_46, _notCDom_reduced4SigExtra_T_47) node _notCDom_reduced4SigExtra_T_49 = cat(_notCDom_reduced4SigExtra_T_35, _notCDom_reduced4SigExtra_T_48) node _notCDom_reduced4SigExtra_T_50 = and(_notCDom_reduced4SigExtra_T_2, _notCDom_reduced4SigExtra_T_49) node notCDom_reduced4SigExtra = orr(_notCDom_reduced4SigExtra_T_50) node _notCDom_sig_T = shr(notCDom_mainSig, 3) node _notCDom_sig_T_1 = bits(notCDom_mainSig, 2, 0) node _notCDom_sig_T_2 = orr(_notCDom_sig_T_1) node _notCDom_sig_T_3 = or(_notCDom_sig_T_2, notCDom_reduced4SigExtra) node notCDom_sig = cat(_notCDom_sig_T, _notCDom_sig_T_3) node _notCDom_completeCancellation_T = bits(notCDom_sig, 55, 54) node notCDom_completeCancellation = eq(_notCDom_completeCancellation_T, UInt<1>(0h0)) node _notCDom_sign_T = xor(io.fromPreMul.signProd, notCDom_signSigSum) node notCDom_sign = mux(notCDom_completeCancellation, roundingMode_min, _notCDom_sign_T) node notNaN_isInfProd = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node notNaN_isInfOut = or(notNaN_isInfProd, io.fromPreMul.isInfC) node _notNaN_addZeros_T = or(io.fromPreMul.isZeroA, io.fromPreMul.isZeroB) node notNaN_addZeros = and(_notNaN_addZeros_T, io.fromPreMul.isZeroC) node _io_invalidExc_T = and(io.fromPreMul.isInfA, io.fromPreMul.isZeroB) node _io_invalidExc_T_1 = or(io.fromPreMul.isSigNaNAny, _io_invalidExc_T) node _io_invalidExc_T_2 = and(io.fromPreMul.isZeroA, io.fromPreMul.isInfB) node _io_invalidExc_T_3 = or(_io_invalidExc_T_1, _io_invalidExc_T_2) node _io_invalidExc_T_4 = eq(io.fromPreMul.isNaNAOrB, UInt<1>(0h0)) node _io_invalidExc_T_5 = or(io.fromPreMul.isInfA, io.fromPreMul.isInfB) node _io_invalidExc_T_6 = and(_io_invalidExc_T_4, _io_invalidExc_T_5) node _io_invalidExc_T_7 = and(_io_invalidExc_T_6, io.fromPreMul.isInfC) node _io_invalidExc_T_8 = and(_io_invalidExc_T_7, io.fromPreMul.doSubMags) node _io_invalidExc_T_9 = or(_io_invalidExc_T_3, _io_invalidExc_T_8) connect io.invalidExc, _io_invalidExc_T_9 node _io_rawOut_isNaN_T = or(io.fromPreMul.isNaNAOrB, io.fromPreMul.isNaNC) connect io.rawOut.isNaN, _io_rawOut_isNaN_T connect io.rawOut.isInf, notNaN_isInfOut node _io_rawOut_isZero_T = eq(io.fromPreMul.CIsDominant, UInt<1>(0h0)) node _io_rawOut_isZero_T_1 = and(_io_rawOut_isZero_T, notCDom_completeCancellation) node _io_rawOut_isZero_T_2 = or(notNaN_addZeros, _io_rawOut_isZero_T_1) connect io.rawOut.isZero, _io_rawOut_isZero_T_2 node _io_rawOut_sign_T = and(notNaN_isInfProd, io.fromPreMul.signProd) node _io_rawOut_sign_T_1 = and(io.fromPreMul.isInfC, opSignC) node _io_rawOut_sign_T_2 = or(_io_rawOut_sign_T, _io_rawOut_sign_T_1) node _io_rawOut_sign_T_3 = eq(roundingMode_min, UInt<1>(0h0)) node _io_rawOut_sign_T_4 = and(notNaN_addZeros, _io_rawOut_sign_T_3) node _io_rawOut_sign_T_5 = and(_io_rawOut_sign_T_4, io.fromPreMul.signProd) node _io_rawOut_sign_T_6 = and(_io_rawOut_sign_T_5, opSignC) node _io_rawOut_sign_T_7 = or(_io_rawOut_sign_T_2, _io_rawOut_sign_T_6) node _io_rawOut_sign_T_8 = and(notNaN_addZeros, roundingMode_min) node _io_rawOut_sign_T_9 = or(io.fromPreMul.signProd, opSignC) node _io_rawOut_sign_T_10 = and(_io_rawOut_sign_T_8, _io_rawOut_sign_T_9) node _io_rawOut_sign_T_11 = or(_io_rawOut_sign_T_7, _io_rawOut_sign_T_10) node _io_rawOut_sign_T_12 = eq(notNaN_isInfOut, UInt<1>(0h0)) node _io_rawOut_sign_T_13 = eq(notNaN_addZeros, UInt<1>(0h0)) node _io_rawOut_sign_T_14 = and(_io_rawOut_sign_T_12, _io_rawOut_sign_T_13) node _io_rawOut_sign_T_15 = mux(io.fromPreMul.CIsDominant, opSignC, notCDom_sign) node _io_rawOut_sign_T_16 = and(_io_rawOut_sign_T_14, _io_rawOut_sign_T_15) node _io_rawOut_sign_T_17 = or(_io_rawOut_sign_T_11, _io_rawOut_sign_T_16) connect io.rawOut.sign, _io_rawOut_sign_T_17 node _io_rawOut_sExp_T = mux(io.fromPreMul.CIsDominant, CDom_sExp, notCDom_sExp) connect io.rawOut.sExp, _io_rawOut_sExp_T node _io_rawOut_sig_T = mux(io.fromPreMul.CIsDominant, CDom_sig, notCDom_sig) connect io.rawOut.sig, _io_rawOut_sig_T
module MulAddRecFNToRaw_postMul_e11_s53( // @[MulAddRecFN.scala:169:7] input io_fromPreMul_isSigNaNAny, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNAOrB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroA, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroB, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_signProd, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isNaNC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isInfC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_isZeroC, // @[MulAddRecFN.scala:172:16] input [12:0] io_fromPreMul_sExpSum, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_doSubMags, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_CIsDominant, // @[MulAddRecFN.scala:172:16] input [5:0] io_fromPreMul_CDom_CAlignDist, // @[MulAddRecFN.scala:172:16] input [54:0] io_fromPreMul_highAlignedSigC, // @[MulAddRecFN.scala:172:16] input io_fromPreMul_bit0AlignedSigC, // @[MulAddRecFN.scala:172:16] input [106:0] io_mulAddResult, // @[MulAddRecFN.scala:172:16] input [2:0] io_roundingMode, // @[MulAddRecFN.scala:172:16] output io_invalidExc, // @[MulAddRecFN.scala:172:16] output io_rawOut_isNaN, // @[MulAddRecFN.scala:172:16] output io_rawOut_isInf, // @[MulAddRecFN.scala:172:16] output io_rawOut_isZero, // @[MulAddRecFN.scala:172:16] output io_rawOut_sign, // @[MulAddRecFN.scala:172:16] output [12:0] io_rawOut_sExp, // @[MulAddRecFN.scala:172:16] output [55:0] io_rawOut_sig // @[MulAddRecFN.scala:172:16] ); wire roundingMode_min = io_roundingMode == 3'h2; // @[MulAddRecFN.scala:186:45] wire opSignC = io_fromPreMul_signProd ^ io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:190:42] wire [54:0] _sigSum_T_3 = io_mulAddResult[106] ? io_fromPreMul_highAlignedSigC + 55'h1 : io_fromPreMul_highAlignedSigC; // @[MulAddRecFN.scala:192:{16,32}, :193:47] wire [107:0] CDom_absSigSum = io_fromPreMul_doSubMags ? ~{_sigSum_T_3, io_mulAddResult[105:53]} : {1'h0, io_fromPreMul_highAlignedSigC[54:53], _sigSum_T_3[52:0], io_mulAddResult[105:54]}; // @[MulAddRecFN.scala:192:16, :205:12, :206:{13,20}, :209:{46,71}, :210:23] wire [170:0] _CDom_mainSig_T = {63'h0, CDom_absSigSum} << io_fromPreMul_CDom_CAlignDist; // @[MulAddRecFN.scala:205:12, :219:24] wire [16:0] CDom_reduced4SigExtra_shift = $signed(17'sh10000 >>> ~(io_fromPreMul_CDom_CAlignDist[5:2])); // @[primitives.scala:52:21, :76:56] wire [108:0] notCDom_absSigSum = _sigSum_T_3[2] ? ~{_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC} : {_sigSum_T_3[1:0], io_mulAddResult[105:0], io_fromPreMul_bit0AlignedSigC} + {108'h0, io_fromPreMul_doSubMags}; // @[MulAddRecFN.scala:192:16, :196:28, :232:36, :234:12, :235:{13,20}, :236:41] wire [5:0] notCDom_normDistReduced2 = notCDom_absSigSum[108] ? 6'h0 : (|(notCDom_absSigSum[107:106])) ? 6'h1 : (|(notCDom_absSigSum[105:104])) ? 6'h2 : (|(notCDom_absSigSum[103:102])) ? 6'h3 : (|(notCDom_absSigSum[101:100])) ? 6'h4 : (|(notCDom_absSigSum[99:98])) ? 6'h5 : (|(notCDom_absSigSum[97:96])) ? 6'h6 : (|(notCDom_absSigSum[95:94])) ? 6'h7 : (|(notCDom_absSigSum[93:92])) ? 6'h8 : (|(notCDom_absSigSum[91:90])) ? 6'h9 : (|(notCDom_absSigSum[89:88])) ? 6'hA : (|(notCDom_absSigSum[87:86])) ? 6'hB : (|(notCDom_absSigSum[85:84])) ? 6'hC : (|(notCDom_absSigSum[83:82])) ? 6'hD : (|(notCDom_absSigSum[81:80])) ? 6'hE : (|(notCDom_absSigSum[79:78])) ? 6'hF : (|(notCDom_absSigSum[77:76])) ? 6'h10 : (|(notCDom_absSigSum[75:74])) ? 6'h11 : (|(notCDom_absSigSum[73:72])) ? 6'h12 : (|(notCDom_absSigSum[71:70])) ? 6'h13 : (|(notCDom_absSigSum[69:68])) ? 6'h14 : (|(notCDom_absSigSum[67:66])) ? 6'h15 : (|(notCDom_absSigSum[65:64])) ? 6'h16 : (|(notCDom_absSigSum[63:62])) ? 6'h17 : (|(notCDom_absSigSum[61:60])) ? 6'h18 : (|(notCDom_absSigSum[59:58])) ? 6'h19 : (|(notCDom_absSigSum[57:56])) ? 6'h1A : (|(notCDom_absSigSum[55:54])) ? 6'h1B : (|(notCDom_absSigSum[53:52])) ? 6'h1C : (|(notCDom_absSigSum[51:50])) ? 6'h1D : (|(notCDom_absSigSum[49:48])) ? 6'h1E : (|(notCDom_absSigSum[47:46])) ? 6'h1F : (|(notCDom_absSigSum[45:44])) ? 6'h20 : (|(notCDom_absSigSum[43:42])) ? 6'h21 : (|(notCDom_absSigSum[41:40])) ? 6'h22 : (|(notCDom_absSigSum[39:38])) ? 6'h23 : (|(notCDom_absSigSum[37:36])) ? 6'h24 : (|(notCDom_absSigSum[35:34])) ? 6'h25 : (|(notCDom_absSigSum[33:32])) ? 6'h26 : (|(notCDom_absSigSum[31:30])) ? 6'h27 : (|(notCDom_absSigSum[29:28])) ? 6'h28 : (|(notCDom_absSigSum[27:26])) ? 6'h29 : (|(notCDom_absSigSum[25:24])) ? 6'h2A : (|(notCDom_absSigSum[23:22])) ? 6'h2B : (|(notCDom_absSigSum[21:20])) ? 6'h2C : (|(notCDom_absSigSum[19:18])) ? 6'h2D : (|(notCDom_absSigSum[17:16])) ? 6'h2E : (|(notCDom_absSigSum[15:14])) ? 6'h2F : (|(notCDom_absSigSum[13:12])) ? 6'h30 : (|(notCDom_absSigSum[11:10])) ? 6'h31 : (|(notCDom_absSigSum[9:8])) ? 6'h32 : (|(notCDom_absSigSum[7:6])) ? 6'h33 : (|(notCDom_absSigSum[5:4])) ? 6'h34 : (|(notCDom_absSigSum[3:2])) ? 6'h35 : 6'h36; // @[Mux.scala:50:70] wire [235:0] _notCDom_mainSig_T = {127'h0, notCDom_absSigSum} << {229'h0, notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] wire [32:0] notCDom_reduced4SigExtra_shift = $signed(33'sh100000000 >>> ~(notCDom_normDistReduced2[5:1])); // @[Mux.scala:50:70] wire notCDom_completeCancellation = _notCDom_mainSig_T[109:108] == 2'h0; // @[MulAddRecFN.scala:243:27, :255:{21,50}] wire notNaN_isInfProd = io_fromPreMul_isInfA | io_fromPreMul_isInfB; // @[MulAddRecFN.scala:264:49] wire notNaN_isInfOut = notNaN_isInfProd | io_fromPreMul_isInfC; // @[MulAddRecFN.scala:264:49, :265:44] wire notNaN_addZeros = (io_fromPreMul_isZeroA | io_fromPreMul_isZeroB) & io_fromPreMul_isZeroC; // @[MulAddRecFN.scala:267:{32,58}] assign io_invalidExc = io_fromPreMul_isSigNaNAny | io_fromPreMul_isInfA & io_fromPreMul_isZeroB | io_fromPreMul_isZeroA & io_fromPreMul_isInfB | ~io_fromPreMul_isNaNAOrB & notNaN_isInfProd & io_fromPreMul_isInfC & io_fromPreMul_doSubMags; // @[MulAddRecFN.scala:169:7, :264:49, :271:35, :272:{31,57}, :273:{32,57}, :274:{10,36}, :275:61, :276:35] assign io_rawOut_isNaN = io_fromPreMul_isNaNAOrB | io_fromPreMul_isNaNC; // @[MulAddRecFN.scala:169:7, :278:48] assign io_rawOut_isInf = notNaN_isInfOut; // @[MulAddRecFN.scala:169:7, :265:44] assign io_rawOut_isZero = notNaN_addZeros | ~io_fromPreMul_CIsDominant & notCDom_completeCancellation; // @[MulAddRecFN.scala:169:7, :255:50, :267:58, :282:25, :283:{14,42}] assign io_rawOut_sign = notNaN_isInfProd & io_fromPreMul_signProd | io_fromPreMul_isInfC & opSignC | notNaN_addZeros & io_roundingMode != 3'h2 & io_fromPreMul_signProd & opSignC | notNaN_addZeros & roundingMode_min & (io_fromPreMul_signProd | opSignC) | ~notNaN_isInfOut & ~notNaN_addZeros & (io_fromPreMul_CIsDominant ? opSignC : notCDom_completeCancellation ? roundingMode_min : io_fromPreMul_signProd ^ _sigSum_T_3[2]); // @[MulAddRecFN.scala:169:7, :186:45, :190:42, :192:16, :232:36, :255:50, :257:12, :259:36, :264:49, :265:44, :267:58, :285:{27,54}, :286:{31,43}, :287:{26,29,48}, :288:{36,48}, :289:{26,46}, :290:{37,50}, :291:{10,28,31,49}, :292:17] assign io_rawOut_sExp = io_fromPreMul_CIsDominant ? io_fromPreMul_sExpSum - {12'h0, io_fromPreMul_doSubMags} : io_fromPreMul_sExpSum - {6'h0, notCDom_normDistReduced2, 1'h0}; // @[Mux.scala:50:70] assign io_rawOut_sig = io_fromPreMul_CIsDominant ? {_CDom_mainSig_T[107:53], (|{_CDom_mainSig_T[52:50], {|(CDom_absSigSum[49:46]), |(CDom_absSigSum[45:42]), |(CDom_absSigSum[41:38]), |(CDom_absSigSum[37:34]), |(CDom_absSigSum[33:30]), |(CDom_absSigSum[29:26]), |(CDom_absSigSum[25:22]), |(CDom_absSigSum[21:18]), |(CDom_absSigSum[17:14]), |(CDom_absSigSum[13:10]), |(CDom_absSigSum[9:6]), |(CDom_absSigSum[5:2]), |(CDom_absSigSum[1:0])} & {CDom_reduced4SigExtra_shift[1], CDom_reduced4SigExtra_shift[2], CDom_reduced4SigExtra_shift[3], CDom_reduced4SigExtra_shift[4], CDom_reduced4SigExtra_shift[5], CDom_reduced4SigExtra_shift[6], CDom_reduced4SigExtra_shift[7], CDom_reduced4SigExtra_shift[8], CDom_reduced4SigExtra_shift[9], CDom_reduced4SigExtra_shift[10], CDom_reduced4SigExtra_shift[11], CDom_reduced4SigExtra_shift[12], CDom_reduced4SigExtra_shift[13]}}) | (io_fromPreMul_doSubMags ? io_mulAddResult[52:0] != 53'h1FFFFFFFFFFFFF : (|(io_mulAddResult[53:0])))} : {_notCDom_mainSig_T[109:55], |{_notCDom_mainSig_T[54:52], {|{|(notCDom_absSigSum[51:50]), |(notCDom_absSigSum[49:48])}, |{|(notCDom_absSigSum[47:46]), |(notCDom_absSigSum[45:44])}, |{|(notCDom_absSigSum[43:42]), |(notCDom_absSigSum[41:40])}, |{|(notCDom_absSigSum[39:38]), |(notCDom_absSigSum[37:36])}, |{|(notCDom_absSigSum[35:34]), |(notCDom_absSigSum[33:32])}, |{|(notCDom_absSigSum[31:30]), |(notCDom_absSigSum[29:28])}, |{|(notCDom_absSigSum[27:26]), |(notCDom_absSigSum[25:24])}, |{|(notCDom_absSigSum[23:22]), |(notCDom_absSigSum[21:20])}, |{|(notCDom_absSigSum[19:18]), |(notCDom_absSigSum[17:16])}, |{|(notCDom_absSigSum[15:14]), |(notCDom_absSigSum[13:12])}, |{|(notCDom_absSigSum[11:10]), |(notCDom_absSigSum[9:8])}, |{|(notCDom_absSigSum[7:6]), |(notCDom_absSigSum[5:4])}, |{|(notCDom_absSigSum[3:2]), |(notCDom_absSigSum[1:0])}} & {notCDom_reduced4SigExtra_shift[1], notCDom_reduced4SigExtra_shift[2], notCDom_reduced4SigExtra_shift[3], notCDom_reduced4SigExtra_shift[4], notCDom_reduced4SigExtra_shift[5], notCDom_reduced4SigExtra_shift[6], notCDom_reduced4SigExtra_shift[7], notCDom_reduced4SigExtra_shift[8], notCDom_reduced4SigExtra_shift[9], notCDom_reduced4SigExtra_shift[10], notCDom_reduced4SigExtra_shift[11], notCDom_reduced4SigExtra_shift[12], notCDom_reduced4SigExtra_shift[13]}}}; // @[primitives.scala:76:56, :77:20, :78:22, :103:{33,54}, :120:{33,54}] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_58 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T node _is_aligned_mask_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 1, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<2>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 0, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 1, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h2)) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(UInt<1>(0h1), mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(UInt<1>(0h1), mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_lo = cat(mask_acc_1, mask_acc) node mask_hi = cat(mask_acc_3, mask_acc_2) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _T_12 = asUInt(reset) node _T_13 = eq(_T_12, UInt<1>(0h0)) when _T_13 : node _T_14 = eq(_T_11, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_11, UInt<1>(0h1), "") : assert_1 node _T_15 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_15 : node _T_16 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_17 = and(UInt<1>(0h0), _T_16) node _T_18 = or(UInt<1>(0h0), _T_17) node _T_19 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_20 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_21 = cvt(_T_20) node _T_22 = and(_T_21, asSInt(UInt<5>(0h14))) node _T_23 = asSInt(_T_22) node _T_24 = eq(_T_23, asSInt(UInt<1>(0h0))) node _T_25 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_26 = cvt(_T_25) node _T_27 = and(_T_26, asSInt(UInt<4>(0h8))) node _T_28 = asSInt(_T_27) node _T_29 = eq(_T_28, asSInt(UInt<1>(0h0))) node _T_30 = or(_T_24, _T_29) node _T_31 = and(_T_19, _T_30) node _T_32 = or(UInt<1>(0h0), _T_31) node _T_33 = and(_T_18, _T_32) node _T_34 = asUInt(reset) node _T_35 = eq(_T_34, UInt<1>(0h0)) when _T_35 : node _T_36 = eq(_T_33, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_33, UInt<1>(0h1), "") : assert_2 node _T_37 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_38 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_39 = and(_T_37, _T_38) node _T_40 = or(UInt<1>(0h0), _T_39) node _T_41 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<5>(0h14))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_47 = cvt(_T_46) node _T_48 = and(_T_47, asSInt(UInt<4>(0h8))) node _T_49 = asSInt(_T_48) node _T_50 = eq(_T_49, asSInt(UInt<1>(0h0))) node _T_51 = or(_T_45, _T_50) node _T_52 = and(_T_40, _T_51) node _T_53 = or(UInt<1>(0h0), _T_52) node _T_54 = and(UInt<1>(0h0), _T_53) node _T_55 = asUInt(reset) node _T_56 = eq(_T_55, UInt<1>(0h0)) when _T_56 : node _T_57 = eq(_T_54, UInt<1>(0h0)) when _T_57 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_54, UInt<1>(0h1), "") : assert_3 node _T_58 = asUInt(reset) node _T_59 = eq(_T_58, UInt<1>(0h0)) when _T_59 : node _T_60 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_60 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_61 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_62 = asUInt(reset) node _T_63 = eq(_T_62, UInt<1>(0h0)) when _T_63 : node _T_64 = eq(_T_61, UInt<1>(0h0)) when _T_64 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_61, UInt<1>(0h1), "") : assert_5 node _T_65 = asUInt(reset) node _T_66 = eq(_T_65, UInt<1>(0h0)) when _T_66 : node _T_67 = eq(is_aligned, UInt<1>(0h0)) when _T_67 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_68 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_69 = asUInt(reset) node _T_70 = eq(_T_69, UInt<1>(0h0)) when _T_70 : node _T_71 = eq(_T_68, UInt<1>(0h0)) when _T_71 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_68, UInt<1>(0h1), "") : assert_7 node _T_72 = not(io.in.a.bits.mask) node _T_73 = eq(_T_72, UInt<1>(0h0)) node _T_74 = asUInt(reset) node _T_75 = eq(_T_74, UInt<1>(0h0)) when _T_75 : node _T_76 = eq(_T_73, UInt<1>(0h0)) when _T_76 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_73, UInt<1>(0h1), "") : assert_8 node _T_77 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_78 = asUInt(reset) node _T_79 = eq(_T_78, UInt<1>(0h0)) when _T_79 : node _T_80 = eq(_T_77, UInt<1>(0h0)) when _T_80 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_77, UInt<1>(0h1), "") : assert_9 node _T_81 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_81 : node _T_82 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_83 = and(UInt<1>(0h0), _T_82) node _T_84 = or(UInt<1>(0h0), _T_83) node _T_85 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_86 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_87 = cvt(_T_86) node _T_88 = and(_T_87, asSInt(UInt<5>(0h14))) node _T_89 = asSInt(_T_88) node _T_90 = eq(_T_89, asSInt(UInt<1>(0h0))) node _T_91 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_92 = cvt(_T_91) node _T_93 = and(_T_92, asSInt(UInt<4>(0h8))) node _T_94 = asSInt(_T_93) node _T_95 = eq(_T_94, asSInt(UInt<1>(0h0))) node _T_96 = or(_T_90, _T_95) node _T_97 = and(_T_85, _T_96) node _T_98 = or(UInt<1>(0h0), _T_97) node _T_99 = and(_T_84, _T_98) node _T_100 = asUInt(reset) node _T_101 = eq(_T_100, UInt<1>(0h0)) when _T_101 : node _T_102 = eq(_T_99, UInt<1>(0h0)) when _T_102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_99, UInt<1>(0h1), "") : assert_10 node _T_103 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_104 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_105 = and(_T_103, _T_104) node _T_106 = or(UInt<1>(0h0), _T_105) node _T_107 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_108 = cvt(_T_107) node _T_109 = and(_T_108, asSInt(UInt<5>(0h14))) node _T_110 = asSInt(_T_109) node _T_111 = eq(_T_110, asSInt(UInt<1>(0h0))) node _T_112 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_113 = cvt(_T_112) node _T_114 = and(_T_113, asSInt(UInt<4>(0h8))) node _T_115 = asSInt(_T_114) node _T_116 = eq(_T_115, asSInt(UInt<1>(0h0))) node _T_117 = or(_T_111, _T_116) node _T_118 = and(_T_106, _T_117) node _T_119 = or(UInt<1>(0h0), _T_118) node _T_120 = and(UInt<1>(0h0), _T_119) node _T_121 = asUInt(reset) node _T_122 = eq(_T_121, UInt<1>(0h0)) when _T_122 : node _T_123 = eq(_T_120, UInt<1>(0h0)) when _T_123 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_120, UInt<1>(0h1), "") : assert_11 node _T_124 = asUInt(reset) node _T_125 = eq(_T_124, UInt<1>(0h0)) when _T_125 : node _T_126 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_126 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_127 = geq(io.in.a.bits.size, UInt<2>(0h2)) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_127, UInt<1>(0h1), "") : assert_13 node _T_131 = asUInt(reset) node _T_132 = eq(_T_131, UInt<1>(0h0)) when _T_132 : node _T_133 = eq(is_aligned, UInt<1>(0h0)) when _T_133 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_134 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_135 = asUInt(reset) node _T_136 = eq(_T_135, UInt<1>(0h0)) when _T_136 : node _T_137 = eq(_T_134, UInt<1>(0h0)) when _T_137 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_134, UInt<1>(0h1), "") : assert_15 node _T_138 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_139 = asUInt(reset) node _T_140 = eq(_T_139, UInt<1>(0h0)) when _T_140 : node _T_141 = eq(_T_138, UInt<1>(0h0)) when _T_141 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_138, UInt<1>(0h1), "") : assert_16 node _T_142 = not(io.in.a.bits.mask) node _T_143 = eq(_T_142, UInt<1>(0h0)) node _T_144 = asUInt(reset) node _T_145 = eq(_T_144, UInt<1>(0h0)) when _T_145 : node _T_146 = eq(_T_143, UInt<1>(0h0)) when _T_146 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_143, UInt<1>(0h1), "") : assert_17 node _T_147 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_148 = asUInt(reset) node _T_149 = eq(_T_148, UInt<1>(0h0)) when _T_149 : node _T_150 = eq(_T_147, UInt<1>(0h0)) when _T_150 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_147, UInt<1>(0h1), "") : assert_18 node _T_151 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_151 : node _T_152 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_153 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_154 = and(_T_152, _T_153) node _T_155 = or(UInt<1>(0h0), _T_154) node _T_156 = asUInt(reset) node _T_157 = eq(_T_156, UInt<1>(0h0)) when _T_157 : node _T_158 = eq(_T_155, UInt<1>(0h0)) when _T_158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_155, UInt<1>(0h1), "") : assert_19 node _T_159 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_160 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_161 = and(_T_159, _T_160) node _T_162 = or(UInt<1>(0h0), _T_161) node _T_163 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_164 = cvt(_T_163) node _T_165 = and(_T_164, asSInt(UInt<5>(0h14))) node _T_166 = asSInt(_T_165) node _T_167 = eq(_T_166, asSInt(UInt<1>(0h0))) node _T_168 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_169 = cvt(_T_168) node _T_170 = and(_T_169, asSInt(UInt<4>(0h8))) node _T_171 = asSInt(_T_170) node _T_172 = eq(_T_171, asSInt(UInt<1>(0h0))) node _T_173 = or(_T_167, _T_172) node _T_174 = and(_T_162, _T_173) node _T_175 = or(UInt<1>(0h0), _T_174) node _T_176 = asUInt(reset) node _T_177 = eq(_T_176, UInt<1>(0h0)) when _T_177 : node _T_178 = eq(_T_175, UInt<1>(0h0)) when _T_178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_175, UInt<1>(0h1), "") : assert_20 node _T_179 = asUInt(reset) node _T_180 = eq(_T_179, UInt<1>(0h0)) when _T_180 : node _T_181 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_181 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_182 = asUInt(reset) node _T_183 = eq(_T_182, UInt<1>(0h0)) when _T_183 : node _T_184 = eq(is_aligned, UInt<1>(0h0)) when _T_184 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_185 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_186 = asUInt(reset) node _T_187 = eq(_T_186, UInt<1>(0h0)) when _T_187 : node _T_188 = eq(_T_185, UInt<1>(0h0)) when _T_188 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_185, UInt<1>(0h1), "") : assert_23 node _T_189 = eq(io.in.a.bits.mask, mask) node _T_190 = asUInt(reset) node _T_191 = eq(_T_190, UInt<1>(0h0)) when _T_191 : node _T_192 = eq(_T_189, UInt<1>(0h0)) when _T_192 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_189, UInt<1>(0h1), "") : assert_24 node _T_193 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_194 = asUInt(reset) node _T_195 = eq(_T_194, UInt<1>(0h0)) when _T_195 : node _T_196 = eq(_T_193, UInt<1>(0h0)) when _T_196 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_193, UInt<1>(0h1), "") : assert_25 node _T_197 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_197 : node _T_198 = eq(UInt<2>(0h2), io.in.a.bits.size) node _T_199 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_200 = and(_T_198, _T_199) node _T_201 = or(UInt<1>(0h0), _T_200) node _T_202 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_203 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_204 = and(_T_202, _T_203) node _T_205 = or(UInt<1>(0h0), _T_204) node _T_206 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_207 = cvt(_T_206) node _T_208 = and(_T_207, asSInt(UInt<5>(0h14))) node _T_209 = asSInt(_T_208) node _T_210 = eq(_T_209, asSInt(UInt<1>(0h0))) node _T_211 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_212 = cvt(_T_211) node _T_213 = and(_T_212, asSInt(UInt<4>(0h8))) node _T_214 = asSInt(_T_213) node _T_215 = eq(_T_214, asSInt(UInt<1>(0h0))) node _T_216 = or(_T_210, _T_215) node _T_217 = and(_T_205, _T_216) node _T_218 = or(UInt<1>(0h0), _T_217) node _T_219 = and(_T_201, _T_218) node _T_220 = asUInt(reset) node _T_221 = eq(_T_220, UInt<1>(0h0)) when _T_221 : node _T_222 = eq(_T_219, UInt<1>(0h0)) when _T_222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_219, UInt<1>(0h1), "") : assert_26 node _T_223 = asUInt(reset) node _T_224 = eq(_T_223, UInt<1>(0h0)) when _T_224 : node _T_225 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_225 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(is_aligned, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_229 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_229, UInt<1>(0h1), "") : assert_29 node _T_233 = eq(io.in.a.bits.mask, mask) node _T_234 = asUInt(reset) node _T_235 = eq(_T_234, UInt<1>(0h0)) when _T_235 : node _T_236 = eq(_T_233, UInt<1>(0h0)) when _T_236 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_233, UInt<1>(0h1), "") : assert_30 node _T_237 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_237 : node _T_238 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_239 = and(UInt<1>(0h0), _T_238) node _T_240 = or(UInt<1>(0h0), _T_239) node _T_241 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_242 = leq(io.in.a.bits.size, UInt<2>(0h2)) node _T_243 = and(_T_241, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_246 = cvt(_T_245) node _T_247 = and(_T_246, asSInt(UInt<5>(0h14))) node _T_248 = asSInt(_T_247) node _T_249 = eq(_T_248, asSInt(UInt<1>(0h0))) node _T_250 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_251 = cvt(_T_250) node _T_252 = and(_T_251, asSInt(UInt<4>(0h8))) node _T_253 = asSInt(_T_252) node _T_254 = eq(_T_253, asSInt(UInt<1>(0h0))) node _T_255 = or(_T_249, _T_254) node _T_256 = and(_T_244, _T_255) node _T_257 = or(UInt<1>(0h0), _T_256) node _T_258 = and(_T_240, _T_257) node _T_259 = asUInt(reset) node _T_260 = eq(_T_259, UInt<1>(0h0)) when _T_260 : node _T_261 = eq(_T_258, UInt<1>(0h0)) when _T_261 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_258, UInt<1>(0h1), "") : assert_31 node _T_262 = asUInt(reset) node _T_263 = eq(_T_262, UInt<1>(0h0)) when _T_263 : node _T_264 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_264 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_265 = asUInt(reset) node _T_266 = eq(_T_265, UInt<1>(0h0)) when _T_266 : node _T_267 = eq(is_aligned, UInt<1>(0h0)) when _T_267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_268 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_268, UInt<1>(0h1), "") : assert_34 node _T_272 = not(mask) node _T_273 = and(io.in.a.bits.mask, _T_272) node _T_274 = eq(_T_273, UInt<1>(0h0)) node _T_275 = asUInt(reset) node _T_276 = eq(_T_275, UInt<1>(0h0)) when _T_276 : node _T_277 = eq(_T_274, UInt<1>(0h0)) when _T_277 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_274, UInt<1>(0h1), "") : assert_35 node _T_278 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_278 : node _T_279 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_280 = and(UInt<1>(0h0), _T_279) node _T_281 = or(UInt<1>(0h0), _T_280) node _T_282 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_283 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_284 = cvt(_T_283) node _T_285 = and(_T_284, asSInt(UInt<5>(0h14))) node _T_286 = asSInt(_T_285) node _T_287 = eq(_T_286, asSInt(UInt<1>(0h0))) node _T_288 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_289 = cvt(_T_288) node _T_290 = and(_T_289, asSInt(UInt<4>(0h8))) node _T_291 = asSInt(_T_290) node _T_292 = eq(_T_291, asSInt(UInt<1>(0h0))) node _T_293 = or(_T_287, _T_292) node _T_294 = and(_T_282, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = and(_T_281, _T_295) node _T_297 = asUInt(reset) node _T_298 = eq(_T_297, UInt<1>(0h0)) when _T_298 : node _T_299 = eq(_T_296, UInt<1>(0h0)) when _T_299 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_296, UInt<1>(0h1), "") : assert_36 node _T_300 = asUInt(reset) node _T_301 = eq(_T_300, UInt<1>(0h0)) when _T_301 : node _T_302 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_303 = asUInt(reset) node _T_304 = eq(_T_303, UInt<1>(0h0)) when _T_304 : node _T_305 = eq(is_aligned, UInt<1>(0h0)) when _T_305 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_306 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_307 = asUInt(reset) node _T_308 = eq(_T_307, UInt<1>(0h0)) when _T_308 : node _T_309 = eq(_T_306, UInt<1>(0h0)) when _T_309 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_306, UInt<1>(0h1), "") : assert_39 node _T_310 = eq(io.in.a.bits.mask, mask) node _T_311 = asUInt(reset) node _T_312 = eq(_T_311, UInt<1>(0h0)) when _T_312 : node _T_313 = eq(_T_310, UInt<1>(0h0)) when _T_313 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_310, UInt<1>(0h1), "") : assert_40 node _T_314 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_314 : node _T_315 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_316 = and(UInt<1>(0h0), _T_315) node _T_317 = or(UInt<1>(0h0), _T_316) node _T_318 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_319 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_320 = cvt(_T_319) node _T_321 = and(_T_320, asSInt(UInt<5>(0h14))) node _T_322 = asSInt(_T_321) node _T_323 = eq(_T_322, asSInt(UInt<1>(0h0))) node _T_324 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_325 = cvt(_T_324) node _T_326 = and(_T_325, asSInt(UInt<4>(0h8))) node _T_327 = asSInt(_T_326) node _T_328 = eq(_T_327, asSInt(UInt<1>(0h0))) node _T_329 = or(_T_323, _T_328) node _T_330 = and(_T_318, _T_329) node _T_331 = or(UInt<1>(0h0), _T_330) node _T_332 = and(_T_317, _T_331) node _T_333 = asUInt(reset) node _T_334 = eq(_T_333, UInt<1>(0h0)) when _T_334 : node _T_335 = eq(_T_332, UInt<1>(0h0)) when _T_335 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_332, UInt<1>(0h1), "") : assert_41 node _T_336 = asUInt(reset) node _T_337 = eq(_T_336, UInt<1>(0h0)) when _T_337 : node _T_338 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_338 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_339 = asUInt(reset) node _T_340 = eq(_T_339, UInt<1>(0h0)) when _T_340 : node _T_341 = eq(is_aligned, UInt<1>(0h0)) when _T_341 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_342 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_343 = asUInt(reset) node _T_344 = eq(_T_343, UInt<1>(0h0)) when _T_344 : node _T_345 = eq(_T_342, UInt<1>(0h0)) when _T_345 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_342, UInt<1>(0h1), "") : assert_44 node _T_346 = eq(io.in.a.bits.mask, mask) node _T_347 = asUInt(reset) node _T_348 = eq(_T_347, UInt<1>(0h0)) when _T_348 : node _T_349 = eq(_T_346, UInt<1>(0h0)) when _T_349 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_346, UInt<1>(0h1), "") : assert_45 node _T_350 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_350 : node _T_351 = eq(io.in.a.bits.source, UInt<1>(0h0)) node _T_352 = and(UInt<1>(0h0), _T_351) node _T_353 = or(UInt<1>(0h0), _T_352) node _T_354 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_355 = xor(io.in.a.bits.address, UInt<7>(0h40)) node _T_356 = cvt(_T_355) node _T_357 = and(_T_356, asSInt(UInt<5>(0h14))) node _T_358 = asSInt(_T_357) node _T_359 = eq(_T_358, asSInt(UInt<1>(0h0))) node _T_360 = xor(io.in.a.bits.address, UInt<7>(0h50)) node _T_361 = cvt(_T_360) node _T_362 = and(_T_361, asSInt(UInt<4>(0h8))) node _T_363 = asSInt(_T_362) node _T_364 = eq(_T_363, asSInt(UInt<1>(0h0))) node _T_365 = or(_T_359, _T_364) node _T_366 = and(_T_354, _T_365) node _T_367 = or(UInt<1>(0h0), _T_366) node _T_368 = and(_T_353, _T_367) node _T_369 = asUInt(reset) node _T_370 = eq(_T_369, UInt<1>(0h0)) when _T_370 : node _T_371 = eq(_T_368, UInt<1>(0h0)) when _T_371 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_368, UInt<1>(0h1), "") : assert_46 node _T_372 = asUInt(reset) node _T_373 = eq(_T_372, UInt<1>(0h0)) when _T_373 : node _T_374 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_375 = asUInt(reset) node _T_376 = eq(_T_375, UInt<1>(0h0)) when _T_376 : node _T_377 = eq(is_aligned, UInt<1>(0h0)) when _T_377 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_378 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_379 = asUInt(reset) node _T_380 = eq(_T_379, UInt<1>(0h0)) when _T_380 : node _T_381 = eq(_T_378, UInt<1>(0h0)) when _T_381 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_378, UInt<1>(0h1), "") : assert_49 node _T_382 = eq(io.in.a.bits.mask, mask) node _T_383 = asUInt(reset) node _T_384 = eq(_T_383, UInt<1>(0h0)) when _T_384 : node _T_385 = eq(_T_382, UInt<1>(0h0)) when _T_385 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_382, UInt<1>(0h1), "") : assert_50 node _T_386 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_387 = asUInt(reset) node _T_388 = eq(_T_387, UInt<1>(0h0)) when _T_388 : node _T_389 = eq(_T_386, UInt<1>(0h0)) when _T_389 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_386, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_390 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_391 = asUInt(reset) node _T_392 = eq(_T_391, UInt<1>(0h0)) when _T_392 : node _T_393 = eq(_T_390, UInt<1>(0h0)) when _T_393 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_390, UInt<1>(0h1), "") : assert_52 node _source_ok_T_1 = eq(io.in.d.bits.source, UInt<1>(0h0)) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_1 node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_394 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_394 : node _T_395 = asUInt(reset) node _T_396 = eq(_T_395, UInt<1>(0h0)) when _T_396 : node _T_397 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_397 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_398 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_399 = asUInt(reset) node _T_400 = eq(_T_399, UInt<1>(0h0)) when _T_400 : node _T_401 = eq(_T_398, UInt<1>(0h0)) when _T_401 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_398, UInt<1>(0h1), "") : assert_54 node _T_402 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_T_402, UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_402, UInt<1>(0h1), "") : assert_55 node _T_406 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_407 = asUInt(reset) node _T_408 = eq(_T_407, UInt<1>(0h0)) when _T_408 : node _T_409 = eq(_T_406, UInt<1>(0h0)) when _T_409 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_406, UInt<1>(0h1), "") : assert_56 node _T_410 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_411 = asUInt(reset) node _T_412 = eq(_T_411, UInt<1>(0h0)) when _T_412 : node _T_413 = eq(_T_410, UInt<1>(0h0)) when _T_413 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_410, UInt<1>(0h1), "") : assert_57 node _T_414 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_414 : node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_418 = asUInt(reset) node _T_419 = eq(_T_418, UInt<1>(0h0)) when _T_419 : node _T_420 = eq(sink_ok, UInt<1>(0h0)) when _T_420 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_421 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_422 = asUInt(reset) node _T_423 = eq(_T_422, UInt<1>(0h0)) when _T_423 : node _T_424 = eq(_T_421, UInt<1>(0h0)) when _T_424 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_421, UInt<1>(0h1), "") : assert_60 node _T_425 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_426 = asUInt(reset) node _T_427 = eq(_T_426, UInt<1>(0h0)) when _T_427 : node _T_428 = eq(_T_425, UInt<1>(0h0)) when _T_428 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_425, UInt<1>(0h1), "") : assert_61 node _T_429 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_430 = asUInt(reset) node _T_431 = eq(_T_430, UInt<1>(0h0)) when _T_431 : node _T_432 = eq(_T_429, UInt<1>(0h0)) when _T_432 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_429, UInt<1>(0h1), "") : assert_62 node _T_433 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_434 = asUInt(reset) node _T_435 = eq(_T_434, UInt<1>(0h0)) when _T_435 : node _T_436 = eq(_T_433, UInt<1>(0h0)) when _T_436 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_433, UInt<1>(0h1), "") : assert_63 node _T_437 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_438 = or(UInt<1>(0h0), _T_437) node _T_439 = asUInt(reset) node _T_440 = eq(_T_439, UInt<1>(0h0)) when _T_440 : node _T_441 = eq(_T_438, UInt<1>(0h0)) when _T_441 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_438, UInt<1>(0h1), "") : assert_64 node _T_442 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_442 : node _T_443 = asUInt(reset) node _T_444 = eq(_T_443, UInt<1>(0h0)) when _T_444 : node _T_445 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_445 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_446 = asUInt(reset) node _T_447 = eq(_T_446, UInt<1>(0h0)) when _T_447 : node _T_448 = eq(sink_ok, UInt<1>(0h0)) when _T_448 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_449 = geq(io.in.d.bits.size, UInt<2>(0h2)) node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(_T_449, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_449, UInt<1>(0h1), "") : assert_67 node _T_453 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_453, UInt<1>(0h1), "") : assert_68 node _T_457 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_457, UInt<1>(0h1), "") : assert_69 node _T_461 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_462 = or(_T_461, io.in.d.bits.corrupt) node _T_463 = asUInt(reset) node _T_464 = eq(_T_463, UInt<1>(0h0)) when _T_464 : node _T_465 = eq(_T_462, UInt<1>(0h0)) when _T_465 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_462, UInt<1>(0h1), "") : assert_70 node _T_466 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_467 = or(UInt<1>(0h0), _T_466) node _T_468 = asUInt(reset) node _T_469 = eq(_T_468, UInt<1>(0h0)) when _T_469 : node _T_470 = eq(_T_467, UInt<1>(0h0)) when _T_470 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_467, UInt<1>(0h1), "") : assert_71 node _T_471 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_471 : node _T_472 = asUInt(reset) node _T_473 = eq(_T_472, UInt<1>(0h0)) when _T_473 : node _T_474 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_474 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_475 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_476 = asUInt(reset) node _T_477 = eq(_T_476, UInt<1>(0h0)) when _T_477 : node _T_478 = eq(_T_475, UInt<1>(0h0)) when _T_478 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_475, UInt<1>(0h1), "") : assert_73 node _T_479 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_480 = asUInt(reset) node _T_481 = eq(_T_480, UInt<1>(0h0)) when _T_481 : node _T_482 = eq(_T_479, UInt<1>(0h0)) when _T_482 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_479, UInt<1>(0h1), "") : assert_74 node _T_483 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_484, UInt<1>(0h1), "") : assert_75 node _T_488 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_488 : node _T_489 = asUInt(reset) node _T_490 = eq(_T_489, UInt<1>(0h0)) when _T_490 : node _T_491 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_491 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_492 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(_T_492, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_492, UInt<1>(0h1), "") : assert_77 node _T_496 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_497 = or(_T_496, io.in.d.bits.corrupt) node _T_498 = asUInt(reset) node _T_499 = eq(_T_498, UInt<1>(0h0)) when _T_499 : node _T_500 = eq(_T_497, UInt<1>(0h0)) when _T_500 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_497, UInt<1>(0h1), "") : assert_78 node _T_501 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_502 = or(UInt<1>(0h0), _T_501) node _T_503 = asUInt(reset) node _T_504 = eq(_T_503, UInt<1>(0h0)) when _T_504 : node _T_505 = eq(_T_502, UInt<1>(0h0)) when _T_505 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_502, UInt<1>(0h1), "") : assert_79 node _T_506 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_506 : node _T_507 = asUInt(reset) node _T_508 = eq(_T_507, UInt<1>(0h0)) when _T_508 : node _T_509 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_509 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_510 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_511 = asUInt(reset) node _T_512 = eq(_T_511, UInt<1>(0h0)) when _T_512 : node _T_513 = eq(_T_510, UInt<1>(0h0)) when _T_513 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_510, UInt<1>(0h1), "") : assert_81 node _T_514 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_515 = asUInt(reset) node _T_516 = eq(_T_515, UInt<1>(0h0)) when _T_516 : node _T_517 = eq(_T_514, UInt<1>(0h0)) when _T_517 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_514, UInt<1>(0h1), "") : assert_82 node _T_518 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_519 = or(UInt<1>(0h0), _T_518) node _T_520 = asUInt(reset) node _T_521 = eq(_T_520, UInt<1>(0h0)) when _T_521 : node _T_522 = eq(_T_519, UInt<1>(0h0)) when _T_522 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_519, UInt<1>(0h1), "") : assert_83 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<32>(0h0) connect _WIRE.bits.mask, UInt<4>(0h0) connect _WIRE.bits.address, UInt<7>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<1>, address : UInt<7>, mask : UInt<4>, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready node _T_523 = eq(_WIRE_1.valid, UInt<1>(0h0)) node _T_524 = asUInt(reset) node _T_525 = eq(_T_524, UInt<1>(0h0)) when _T_525 : node _T_526 = eq(_T_523, UInt<1>(0h0)) when _T_526 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_523, UInt<1>(0h1), "") : assert_84 wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<32>(0h0) connect _WIRE_2.bits.address, UInt<7>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready node _T_527 = eq(_WIRE_3.valid, UInt<1>(0h0)) node _T_528 = asUInt(reset) node _T_529 = eq(_T_528, UInt<1>(0h0)) when _T_529 : node _T_530 = eq(_T_527, UInt<1>(0h0)) when _T_530 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_527, UInt<1>(0h1), "") : assert_85 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_531 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_532 = asUInt(reset) node _T_533 = eq(_T_532, UInt<1>(0h0)) when _T_533 : node _T_534 = eq(_T_531, UInt<1>(0h0)) when _T_534 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_531, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 1, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 2) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_535 = eq(a_first, UInt<1>(0h0)) node _T_536 = and(io.in.a.valid, _T_535) when _T_536 : node _T_537 = eq(io.in.a.bits.opcode, opcode) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_537, UInt<1>(0h1), "") : assert_87 node _T_541 = eq(io.in.a.bits.param, param) node _T_542 = asUInt(reset) node _T_543 = eq(_T_542, UInt<1>(0h0)) when _T_543 : node _T_544 = eq(_T_541, UInt<1>(0h0)) when _T_544 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_541, UInt<1>(0h1), "") : assert_88 node _T_545 = eq(io.in.a.bits.size, size) node _T_546 = asUInt(reset) node _T_547 = eq(_T_546, UInt<1>(0h0)) when _T_547 : node _T_548 = eq(_T_545, UInt<1>(0h0)) when _T_548 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_545, UInt<1>(0h1), "") : assert_89 node _T_549 = eq(io.in.a.bits.source, source) node _T_550 = asUInt(reset) node _T_551 = eq(_T_550, UInt<1>(0h0)) when _T_551 : node _T_552 = eq(_T_549, UInt<1>(0h0)) when _T_552 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_549, UInt<1>(0h1), "") : assert_90 node _T_553 = eq(io.in.a.bits.address, address) node _T_554 = asUInt(reset) node _T_555 = eq(_T_554, UInt<1>(0h0)) when _T_555 : node _T_556 = eq(_T_553, UInt<1>(0h0)) when _T_556 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_553, UInt<1>(0h1), "") : assert_91 node _T_557 = and(io.in.a.ready, io.in.a.valid) node _T_558 = and(_T_557, a_first) when _T_558 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 1, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 2) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_559 = eq(d_first, UInt<1>(0h0)) node _T_560 = and(io.in.d.valid, _T_559) when _T_560 : node _T_561 = eq(io.in.d.bits.opcode, opcode_1) node _T_562 = asUInt(reset) node _T_563 = eq(_T_562, UInt<1>(0h0)) when _T_563 : node _T_564 = eq(_T_561, UInt<1>(0h0)) when _T_564 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_561, UInt<1>(0h1), "") : assert_92 node _T_565 = eq(io.in.d.bits.param, param_1) node _T_566 = asUInt(reset) node _T_567 = eq(_T_566, UInt<1>(0h0)) when _T_567 : node _T_568 = eq(_T_565, UInt<1>(0h0)) when _T_568 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_565, UInt<1>(0h1), "") : assert_93 node _T_569 = eq(io.in.d.bits.size, size_1) node _T_570 = asUInt(reset) node _T_571 = eq(_T_570, UInt<1>(0h0)) when _T_571 : node _T_572 = eq(_T_569, UInt<1>(0h0)) when _T_572 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_569, UInt<1>(0h1), "") : assert_94 node _T_573 = eq(io.in.d.bits.source, source_1) node _T_574 = asUInt(reset) node _T_575 = eq(_T_574, UInt<1>(0h0)) when _T_575 : node _T_576 = eq(_T_573, UInt<1>(0h0)) when _T_576 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_573, UInt<1>(0h1), "") : assert_95 node _T_577 = eq(io.in.d.bits.sink, sink) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_577, UInt<1>(0h1), "") : assert_96 node _T_581 = eq(io.in.d.bits.denied, denied) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_581, UInt<1>(0h1), "") : assert_97 node _T_585 = and(io.in.d.ready, io.in.d.valid) node _T_586 = and(_T_585, d_first) when _T_586 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes : UInt<4>, clock, reset, UInt<4>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 1, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 2) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 1, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 2) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<1> connect a_set, UInt<1>(0h0) wire a_set_wo_ready : UInt<1> connect a_set_wo_ready, UInt<1>(0h0) wire a_opcodes_set : UInt<4> connect a_opcodes_set, UInt<4>(0h0) wire a_sizes_set : UInt<4> connect a_sizes_set, UInt<4>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<3> connect a_sizes_set_interm, UInt<3>(0h0) node _T_587 = and(io.in.a.valid, a_first_1) node _T_588 = and(_T_587, UInt<1>(0h1)) when _T_588 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_589 = and(io.in.a.ready, io.in.a.valid) node _T_590 = and(_T_589, a_first_1) node _T_591 = and(_T_590, UInt<1>(0h1)) when _T_591 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_592 = dshr(inflight, io.in.a.bits.source) node _T_593 = bits(_T_592, 0, 0) node _T_594 = eq(_T_593, UInt<1>(0h0)) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_594, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<1> connect d_clr, UInt<1>(0h0) wire d_clr_wo_ready : UInt<1> connect d_clr_wo_ready, UInt<1>(0h0) wire d_opcodes_clr : UInt<4> connect d_opcodes_clr, UInt<4>(0h0) wire d_sizes_clr : UInt<4> connect d_sizes_clr, UInt<4>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_598 = and(io.in.d.valid, d_first_1) node _T_599 = and(_T_598, UInt<1>(0h1)) node _T_600 = eq(d_release_ack, UInt<1>(0h0)) node _T_601 = and(_T_599, _T_600) when _T_601 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_602 = and(io.in.d.ready, io.in.d.valid) node _T_603 = and(_T_602, d_first_1) node _T_604 = and(_T_603, UInt<1>(0h1)) node _T_605 = eq(d_release_ack, UInt<1>(0h0)) node _T_606 = and(_T_604, _T_605) when _T_606 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_607 = and(io.in.d.valid, d_first_1) node _T_608 = and(_T_607, UInt<1>(0h1)) node _T_609 = eq(d_release_ack, UInt<1>(0h0)) node _T_610 = and(_T_608, _T_609) when _T_610 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_611 = dshr(inflight, io.in.d.bits.source) node _T_612 = bits(_T_611, 0, 0) node _T_613 = or(_T_612, same_cycle_resp) node _T_614 = asUInt(reset) node _T_615 = eq(_T_614, UInt<1>(0h0)) when _T_615 : node _T_616 = eq(_T_613, UInt<1>(0h0)) when _T_616 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_613, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_617 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_618 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_619 = or(_T_617, _T_618) node _T_620 = asUInt(reset) node _T_621 = eq(_T_620, UInt<1>(0h0)) when _T_621 : node _T_622 = eq(_T_619, UInt<1>(0h0)) when _T_622 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_619, UInt<1>(0h1), "") : assert_100 node _T_623 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_624 = asUInt(reset) node _T_625 = eq(_T_624, UInt<1>(0h0)) when _T_625 : node _T_626 = eq(_T_623, UInt<1>(0h0)) when _T_626 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_623, UInt<1>(0h1), "") : assert_101 else : node _T_627 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_628 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_629 = or(_T_627, _T_628) node _T_630 = asUInt(reset) node _T_631 = eq(_T_630, UInt<1>(0h0)) when _T_631 : node _T_632 = eq(_T_629, UInt<1>(0h0)) when _T_632 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_629, UInt<1>(0h1), "") : assert_102 node _T_633 = eq(io.in.d.bits.size, a_size_lookup) node _T_634 = asUInt(reset) node _T_635 = eq(_T_634, UInt<1>(0h0)) when _T_635 : node _T_636 = eq(_T_633, UInt<1>(0h0)) when _T_636 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_633, UInt<1>(0h1), "") : assert_103 node _T_637 = and(io.in.d.valid, d_first_1) node _T_638 = and(_T_637, a_first_1) node _T_639 = and(_T_638, io.in.a.valid) node _T_640 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_641 = and(_T_639, _T_640) node _T_642 = eq(d_release_ack, UInt<1>(0h0)) node _T_643 = and(_T_641, _T_642) when _T_643 : node _T_644 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_645 = or(_T_644, io.in.a.ready) node _T_646 = asUInt(reset) node _T_647 = eq(_T_646, UInt<1>(0h0)) when _T_647 : node _T_648 = eq(_T_645, UInt<1>(0h0)) when _T_648 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_645, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_118 node _T_649 = orr(inflight) node _T_650 = eq(_T_649, UInt<1>(0h0)) node _T_651 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_652 = or(_T_650, _T_651) node _T_653 = lt(watchdog, plusarg_reader.out) node _T_654 = or(_T_652, _T_653) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_654, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_658 = and(io.in.a.ready, io.in.a.valid) node _T_659 = and(io.in.d.ready, io.in.d.valid) node _T_660 = or(_T_658, _T_659) when _T_660 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<2>, clock, reset, UInt<2>(0h0) regreset inflight_opcodes_1 : UInt<4>, clock, reset, UInt<4>(0h0) regreset inflight_sizes_1 : UInt<4>, clock, reset, UInt<4>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<32>(0h0) connect _c_first_WIRE.bits.address, UInt<7>(0h0) connect _c_first_WIRE.bits.source, UInt<1>(0h0) connect _c_first_WIRE.bits.size, UInt<2>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<32>(0h0) connect _c_first_WIRE_2.bits.address, UInt<7>(0h0) connect _c_first_WIRE_2.bits.source, UInt<1>(0h0) connect _c_first_WIRE_2.bits.size, UInt<2>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<2>(0h3), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 1, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 2) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(UInt<1>(0h0), c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<1>, clock, reset, UInt<1>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<2>(0h3), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 1, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 2) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<1> connect c_set, UInt<1>(0h0) wire c_set_wo_ready : UInt<1> connect c_set_wo_ready, UInt<1>(0h0) wire c_opcodes_set : UInt<4> connect c_opcodes_set, UInt<4>(0h0) wire c_sizes_set : UInt<4> connect c_sizes_set, UInt<4>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<3> connect c_sizes_set_interm, UInt<3>(0h0) wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<32>(0h0) connect _WIRE_6.bits.address, UInt<7>(0h0) connect _WIRE_6.bits.source, UInt<1>(0h0) connect _WIRE_6.bits.size, UInt<2>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_661 = and(_WIRE_7.valid, c_first) wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_8.bits.corrupt, UInt<1>(0h0) connect _WIRE_8.bits.data, UInt<32>(0h0) connect _WIRE_8.bits.address, UInt<7>(0h0) connect _WIRE_8.bits.source, UInt<1>(0h0) connect _WIRE_8.bits.size, UInt<2>(0h0) connect _WIRE_8.bits.param, UInt<3>(0h0) connect _WIRE_8.bits.opcode, UInt<3>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_662 = bits(_WIRE_9.bits.opcode, 2, 2) node _T_663 = bits(_WIRE_9.bits.opcode, 1, 1) node _T_664 = and(_T_662, _T_663) node _T_665 = and(_T_661, _T_664) when _T_665 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<32>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<2>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<32>(0h0) connect _WIRE_10.bits.address, UInt<7>(0h0) connect _WIRE_10.bits.source, UInt<1>(0h0) connect _WIRE_10.bits.size, UInt<2>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_666 = and(_WIRE_11.ready, _WIRE_11.valid) node _T_667 = and(_T_666, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<32>(0h0) connect _WIRE_12.bits.address, UInt<7>(0h0) connect _WIRE_12.bits.source, UInt<1>(0h0) connect _WIRE_12.bits.size, UInt<2>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_668 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_669 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_670 = and(_T_668, _T_669) node _T_671 = and(_T_667, _T_670) when _T_671 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<32>(0h0) connect _c_set_WIRE.bits.address, UInt<7>(0h0) connect _c_set_WIRE.bits.source, UInt<1>(0h0) connect _c_set_WIRE.bits.size, UInt<2>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<32>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<2>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<32>(0h0) connect _WIRE_14.bits.address, UInt<7>(0h0) connect _WIRE_14.bits.source, UInt<1>(0h0) connect _WIRE_14.bits.size, UInt<2>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_672 = dshr(inflight_1, _WIRE_15.bits.source) node _T_673 = bits(_T_672, 0, 0) node _T_674 = eq(_T_673, UInt<1>(0h0)) node _T_675 = asUInt(reset) node _T_676 = eq(_T_675, UInt<1>(0h0)) when _T_676 : node _T_677 = eq(_T_674, UInt<1>(0h0)) when _T_677 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_674, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<32>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<2>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<1> connect d_clr_1, UInt<1>(0h0) wire d_clr_wo_ready_1 : UInt<1> connect d_clr_wo_ready_1, UInt<1>(0h0) wire d_opcodes_clr_1 : UInt<4> connect d_opcodes_clr_1, UInt<4>(0h0) wire d_sizes_clr_1 : UInt<4> connect d_sizes_clr_1, UInt<4>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_678 = and(io.in.d.valid, d_first_2) node _T_679 = and(_T_678, UInt<1>(0h1)) node _T_680 = and(_T_679, d_release_ack_1) when _T_680 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_681 = and(io.in.d.ready, io.in.d.valid) node _T_682 = and(_T_681, d_first_2) node _T_683 = and(_T_682, UInt<1>(0h1)) node _T_684 = and(_T_683, d_release_ack_1) when _T_684 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_685 = and(io.in.d.valid, d_first_2) node _T_686 = and(_T_685, UInt<1>(0h1)) node _T_687 = and(_T_686, d_release_ack_1) when _T_687 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<32>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<2>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_688 = dshr(inflight_1, io.in.d.bits.source) node _T_689 = bits(_T_688, 0, 0) node _T_690 = or(_T_689, same_cycle_resp_1) node _T_691 = asUInt(reset) node _T_692 = eq(_T_691, UInt<1>(0h0)) when _T_692 : node _T_693 = eq(_T_690, UInt<1>(0h0)) when _T_693 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_690, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<32>(0h0) connect _WIRE_16.bits.address, UInt<7>(0h0) connect _WIRE_16.bits.source, UInt<1>(0h0) connect _WIRE_16.bits.size, UInt<2>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_694 = eq(io.in.d.bits.size, _WIRE_17.bits.size) node _T_695 = asUInt(reset) node _T_696 = eq(_T_695, UInt<1>(0h0)) when _T_696 : node _T_697 = eq(_T_694, UInt<1>(0h0)) when _T_697 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_694, UInt<1>(0h1), "") : assert_108 else : node _T_698 = eq(io.in.d.bits.size, c_size_lookup) node _T_699 = asUInt(reset) node _T_700 = eq(_T_699, UInt<1>(0h0)) when _T_700 : node _T_701 = eq(_T_698, UInt<1>(0h0)) when _T_701 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_698, UInt<1>(0h1), "") : assert_109 node _T_702 = and(io.in.d.valid, d_first_2) node _T_703 = and(_T_702, c_first) wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<32>(0h0) connect _WIRE_18.bits.address, UInt<7>(0h0) connect _WIRE_18.bits.source, UInt<1>(0h0) connect _WIRE_18.bits.size, UInt<2>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_704 = and(_T_703, _WIRE_19.valid) wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<32>(0h0) connect _WIRE_20.bits.address, UInt<7>(0h0) connect _WIRE_20.bits.source, UInt<1>(0h0) connect _WIRE_20.bits.size, UInt<2>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_705 = eq(_WIRE_21.bits.source, io.in.d.bits.source) node _T_706 = and(_T_704, _T_705) node _T_707 = and(_T_706, d_release_ack_1) node _T_708 = eq(c_probe_ack, UInt<1>(0h0)) node _T_709 = and(_T_707, _T_708) when _T_709 : node _T_710 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<32>(0h0) connect _WIRE_22.bits.address, UInt<7>(0h0) connect _WIRE_22.bits.source, UInt<1>(0h0) connect _WIRE_22.bits.size, UInt<2>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_711 = or(_T_710, _WIRE_23.ready) node _T_712 = asUInt(reset) node _T_713 = eq(_T_712, UInt<1>(0h0)) when _T_713 : node _T_714 = eq(_T_711, UInt<1>(0h0)) when _T_714 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_711, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_119 node _T_715 = orr(inflight_1) node _T_716 = eq(_T_715, UInt<1>(0h0)) node _T_717 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_718 = or(_T_716, _T_717) node _T_719 = lt(watchdog_1, plusarg_reader_1.out) node _T_720 = or(_T_718, _T_719) node _T_721 = asUInt(reset) node _T_722 = eq(_T_721, UInt<1>(0h0)) when _T_722 : node _T_723 = eq(_T_720, UInt<1>(0h0)) when _T_723 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip/src/main/scala/devices/debug/Debug.scala:706:19)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_720, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<32>(0h0) connect _WIRE_24.bits.address, UInt<7>(0h0) connect _WIRE_24.bits.source, UInt<1>(0h0) connect _WIRE_24.bits.size, UInt<2>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<1>, address : UInt<7>, user : { }, echo : { }, data : UInt<32>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_724 = and(_WIRE_25.ready, _WIRE_25.valid) node _T_725 = and(io.in.d.ready, io.in.d.valid) node _T_726 = or(_T_724, _T_725) when _T_726 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_58( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [31:0] io_in_d_bits_data // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [31:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_source = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire mask_sizeOH_shiftAmount = 1'h0; // @[OneHot.scala:64:49] wire mask_sub_size = 1'h0; // @[Misc.scala:209:26] wire _mask_sub_acc_T = 1'h0; // @[Misc.scala:215:38] wire _mask_sub_acc_T_1 = 1'h0; // @[Misc.scala:215:38] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire a_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count = 1'h0; // @[Edges.scala:234:25] wire a_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire a_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire a_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire d_first_beats1_decode_1 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_1 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_1 = 1'h0; // @[Edges.scala:234:25] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_decode = 1'h0; // @[Edges.scala:220:59] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire c_first_beats1 = 1'h0; // @[Edges.scala:221:14] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_first_count_T = 1'h0; // @[Edges.scala:234:27] wire c_first_count = 1'h0; // @[Edges.scala:234:25] wire _c_first_counter_T = 1'h0; // @[Edges.scala:236:21] wire d_first_beats1_decode_2 = 1'h0; // @[Edges.scala:220:59] wire d_first_beats1_2 = 1'h0; // @[Edges.scala:221:14] wire d_first_count_2 = 1'h0; // @[Edges.scala:234:25] wire c_set = 1'h0; // @[Monitor.scala:738:34] wire c_set_wo_ready = 1'h0; // @[Monitor.scala:739:34] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_source = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_source = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire _source_ok_T = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire mask_sub_sub_0_1 = 1'h1; // @[Misc.scala:206:21] wire mask_sub_0_1 = 1'h1; // @[Misc.scala:215:29] wire mask_sub_1_1 = 1'h1; // @[Misc.scala:215:29] wire mask_size = 1'h1; // @[Misc.scala:209:26] wire mask_acc = 1'h1; // @[Misc.scala:215:29] wire mask_acc_1 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_2 = 1'h1; // @[Misc.scala:215:29] wire mask_acc_3 = 1'h1; // @[Misc.scala:215:29] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:46:9] wire _source_ok_WIRE_1_0 = 1'h1; // @[Parameters.scala:1138:31] wire _a_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire a_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire d_first_last = 1'h1; // @[Edges.scala:232:33] wire _a_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire a_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_3 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_1 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_2 = 1'h1; // @[Monitor.scala:684:113] wire c_first_counter1 = 1'h1; // @[Edges.scala:230:28] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire _d_first_last_T_5 = 1'h1; // @[Edges.scala:232:43] wire d_first_last_2 = 1'h1; // @[Edges.scala:232:33] wire _same_cycle_resp_T_8 = 1'h1; // @[Monitor.scala:795:113] wire [1:0] is_aligned_mask = 2'h3; // @[package.scala:243:46] wire [1:0] mask_lo = 2'h3; // @[Misc.scala:222:10] wire [1:0] mask_hi = 2'h3; // @[Misc.scala:222:10] wire [1:0] _a_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_2 = 2'h3; // @[package.scala:243:46] wire [1:0] _a_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_5 = 2'h3; // @[package.scala:243:46] wire [1:0] _c_first_beats1_decode_T_1 = 2'h3; // @[package.scala:243:76] wire [1:0] _c_first_counter1_T = 2'h3; // @[Edges.scala:230:28] wire [1:0] _d_first_beats1_decode_T_8 = 2'h3; // @[package.scala:243:46] wire [1:0] io_in_a_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_size = 2'h2; // @[Monitor.scala:36:7] wire [1:0] _mask_sizeOH_T = 2'h2; // @[Misc.scala:202:34] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] _is_aligned_mask_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_1 = 2'h0; // @[package.scala:243:76] wire [1:0] _a_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _d_first_beats1_decode_T_4 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_first_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_first_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_first_beats1_decode_T_2 = 2'h0; // @[package.scala:243:46] wire [1:0] _d_first_beats1_decode_T_7 = 2'h0; // @[package.scala:243:76] wire [1:0] _c_set_wo_ready_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_wo_ready_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_interm_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_interm_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_opcodes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_opcodes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_sizes_set_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_sizes_set_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _c_probe_ack_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _c_probe_ack_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_1_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_2_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_3_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [1:0] _same_cycle_resp_WIRE_4_bits_size = 2'h0; // @[Bundles.scala:265:74] wire [1:0] _same_cycle_resp_WIRE_5_bits_size = 2'h0; // @[Bundles.scala:265:61] wire [2:0] io_in_a_bits_param = 3'h0; // @[Monitor.scala:36:7] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_sizes_set_interm = 3'h0; // @[Monitor.scala:755:40] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_T = 3'h0; // @[Monitor.scala:766:51] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [3:0] io_in_a_bits_mask = 4'hF; // @[Monitor.scala:36:7] wire [3:0] mask = 4'hF; // @[Misc.scala:222:10] wire [31:0] _c_first_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_first_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_first_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_wo_ready_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_wo_ready_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_interm_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_interm_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_opcodes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_opcodes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_sizes_set_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_sizes_set_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _c_probe_ack_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _c_probe_ack_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_1_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_2_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_3_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [31:0] _same_cycle_resp_WIRE_4_bits_data = 32'h0; // @[Bundles.scala:265:74] wire [31:0] _same_cycle_resp_WIRE_5_bits_data = 32'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_address = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_address = 7'h0; // @[Bundles.scala:265:61] wire [30:0] _d_opcodes_clr_T_5 = 31'hF; // @[Monitor.scala:680:76] wire [30:0] _d_sizes_clr_T_5 = 31'hF; // @[Monitor.scala:681:74] wire [30:0] _d_opcodes_clr_T_11 = 31'hF; // @[Monitor.scala:790:76] wire [30:0] _d_sizes_clr_T_11 = 31'hF; // @[Monitor.scala:791:74] wire [3:0] _a_opcode_lookup_T = 4'h0; // @[Monitor.scala:637:69] wire [3:0] _a_size_lookup_T = 4'h0; // @[Monitor.scala:641:65] wire [3:0] _a_opcodes_set_T = 4'h0; // @[Monitor.scala:659:79] wire [3:0] _a_sizes_set_T = 4'h0; // @[Monitor.scala:660:77] wire [3:0] _d_opcodes_clr_T_4 = 4'h0; // @[Monitor.scala:680:101] wire [3:0] _d_sizes_clr_T_4 = 4'h0; // @[Monitor.scala:681:99] wire [3:0] c_opcodes_set = 4'h0; // @[Monitor.scala:740:34] wire [3:0] c_sizes_set = 4'h0; // @[Monitor.scala:741:34] wire [3:0] _c_opcode_lookup_T = 4'h0; // @[Monitor.scala:749:69] wire [3:0] _c_size_lookup_T = 4'h0; // @[Monitor.scala:750:67] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_opcodes_set_T = 4'h0; // @[Monitor.scala:767:79] wire [3:0] _c_sizes_set_T = 4'h0; // @[Monitor.scala:768:77] wire [3:0] _d_opcodes_clr_T_10 = 4'h0; // @[Monitor.scala:790:101] wire [3:0] _d_sizes_clr_T_10 = 4'h0; // @[Monitor.scala:791:99] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1:0] _mask_sizeOH_T_1 = 2'h1; // @[OneHot.scala:65:12] wire [1:0] _mask_sizeOH_T_2 = 2'h1; // @[OneHot.scala:65:27] wire [1:0] mask_sizeOH = 2'h1; // @[Misc.scala:202:81] wire [1:0] _a_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _a_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_wo_ready_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _c_set_T = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_wo_ready_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [1:0] _d_clr_T_1 = 2'h1; // @[OneHot.scala:58:35] wire [17:0] _c_sizes_set_T_1 = 18'h0; // @[Monitor.scala:768:52] wire [18:0] _c_opcodes_set_T_1 = 19'h0; // @[Monitor.scala:767:54] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] _c_sizes_set_interm_T_1 = 3'h1; // @[Monitor.scala:766:59] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [4:0] _is_aligned_mask_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T = 5'hC; // @[package.scala:243:71] wire [4:0] _a_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_3 = 5'hC; // @[package.scala:243:71] wire [4:0] _d_first_beats1_decode_T_6 = 5'hC; // @[package.scala:243:71] wire [4:0] _c_first_beats1_decode_T = 5'h3; // @[package.scala:243:71] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T_1 = 3'h5; // @[Monitor.scala:658:59] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] _a_sizes_set_interm_T = 3'h4; // @[Monitor.scala:658:51] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [6:0] _is_aligned_T = {5'h0, io_in_a_bits_address_0[1:0]}; // @[Monitor.scala:36:7] wire is_aligned = _is_aligned_T == 7'h0; // @[Edges.scala:21:{16,24}] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_1_2 = mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_eq; // @[Misc.scala:214:27, :215:38] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_eq_1; // @[Misc.scala:214:27, :215:38] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_eq_2; // @[Misc.scala:214:27, :215:38] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_eq_3; // @[Misc.scala:214:27, :215:38] wire _T_658 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_658; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_658; // @[Decoupled.scala:51:35] wire a_first_done = _a_first_T; // @[Decoupled.scala:51:35] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] reg a_first_counter; // @[Edges.scala:229:27] wire _a_first_last_T = a_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T = {1'h0, a_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1 = _a_first_counter1_T[0]; // @[Edges.scala:230:28] wire a_first = ~a_first_counter; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T = ~a_first & a_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [6:0] address; // @[Monitor.scala:391:22] wire _T_726 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_726; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_726; // @[Decoupled.scala:51:35] wire d_first_done = _d_first_T; // @[Decoupled.scala:51:35] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] reg d_first_counter; // @[Edges.scala:229:27] wire _d_first_last_T = d_first_counter; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T = {1'h0, d_first_counter} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1 = _d_first_counter1_T[0]; // @[Edges.scala:230:28] wire d_first = ~d_first_counter; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T = ~d_first & d_first_counter1; // @[Edges.scala:230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] inflight; // @[Monitor.scala:614:27] reg [3:0] inflight_opcodes; // @[Monitor.scala:616:35] wire [3:0] _a_opcode_lookup_T_1 = inflight_opcodes; // @[Monitor.scala:616:35, :637:44] reg [3:0] inflight_sizes; // @[Monitor.scala:618:33] wire [3:0] _a_size_lookup_T_1 = inflight_sizes; // @[Monitor.scala:618:33, :641:40] wire a_first_done_1 = _a_first_T_1; // @[Decoupled.scala:51:35] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] reg a_first_counter_1; // @[Edges.scala:229:27] wire _a_first_last_T_2 = a_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire a_first_counter1_1 = _a_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire a_first_1 = ~a_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _a_first_counter_T_1 = ~a_first_1 & a_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire d_first_done_1 = _d_first_T_1; // @[Decoupled.scala:51:35] reg d_first_counter_1; // @[Edges.scala:229:27] wire _d_first_last_T_2 = d_first_counter_1; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_1 = _d_first_counter1_T_1[0]; // @[Edges.scala:230:28] wire d_first_1 = ~d_first_counter_1; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_1 = ~d_first_1 & d_first_counter1_1; // @[Edges.scala:230:28, :231:25, :236:21] wire a_set; // @[Monitor.scala:626:34] wire a_set_wo_ready; // @[Monitor.scala:627:34] wire [3:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [3:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [15:0] _a_opcode_lookup_T_6 = {12'h0, _a_opcode_lookup_T_1}; // @[Monitor.scala:637:{44,97}] wire [15:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [15:0] _a_size_lookup_T_6 = {12'h0, _a_size_lookup_T_1}; // @[Monitor.scala:637:97, :641:{40,91}] wire [15:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[15:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [2:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _T_588 = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26] assign a_set_wo_ready = _T_588; // @[Monitor.scala:627:34, :651:26] wire _same_cycle_resp_T; // @[Monitor.scala:684:44] assign _same_cycle_resp_T = _T_588; // @[Monitor.scala:651:26, :684:44] assign a_set = _T_658 & a_first_1; // @[Decoupled.scala:51:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = a_set ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:626:34, :646:40, :655:70, :657:{28,61}] assign a_sizes_set_interm = a_set ? 3'h5 : 3'h0; // @[Monitor.scala:626:34, :648:38, :655:70, :658:28] wire [18:0] _a_opcodes_set_T_1 = {15'h0, a_opcodes_set_interm}; // @[Monitor.scala:646:40, :659:54] assign a_opcodes_set = a_set ? _a_opcodes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :630:33, :655:70, :659:{28,54}] wire [17:0] _a_sizes_set_T_1 = {15'h0, a_sizes_set_interm}; // @[Monitor.scala:648:38, :659:54, :660:52] assign a_sizes_set = a_set ? _a_sizes_set_T_1[3:0] : 4'h0; // @[Monitor.scala:626:34, :632:31, :655:70, :660:{28,52}] wire d_clr; // @[Monitor.scala:664:34] wire d_clr_wo_ready; // @[Monitor.scala:665:34] wire [3:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [3:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN; // @[Monitor.scala:673:46, :783:46] wire _T_637 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] assign d_clr_wo_ready = _T_637 & ~d_release_ack; // @[Monitor.scala:665:34, :673:46, :674:{26,71,74}] assign d_clr = _T_726 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] wire [3:0] _GEN_0 = {4{d_clr}}; // @[Monitor.scala:664:34, :668:33, :678:89, :680:21] assign d_opcodes_clr = _GEN_0; // @[Monitor.scala:668:33, :678:89, :680:21] assign d_sizes_clr = _GEN_0; // @[Monitor.scala:668:33, :670:31, :678:89, :680:21] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire same_cycle_resp = _same_cycle_resp_T_1; // @[Monitor.scala:684:{55,88}] wire [1:0] _inflight_T = {inflight[1], inflight[0] | a_set}; // @[Monitor.scala:614:27, :626:34, :705:27] wire _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [1:0] _inflight_T_2 = {1'h0, _inflight_T[0] & _inflight_T_1}; // @[Monitor.scala:705:{27,36,38}] wire [3:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [3:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [3:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [3:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [3:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [3:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [1:0] inflight_1; // @[Monitor.scala:726:35] wire [1:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [3:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [3:0] _c_opcode_lookup_T_1 = inflight_opcodes_1; // @[Monitor.scala:727:35, :749:44] wire [3:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [3:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [3:0] _c_size_lookup_T_1 = inflight_sizes_1; // @[Monitor.scala:728:35, :750:42] wire [3:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire d_first_done_2 = _d_first_T_2; // @[Decoupled.scala:51:35] reg d_first_counter_2; // @[Edges.scala:229:27] wire _d_first_last_T_4 = d_first_counter_2; // @[Edges.scala:229:27, :232:25] wire [1:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 2'h1; // @[Edges.scala:229:27, :230:28] wire d_first_counter1_2 = _d_first_counter1_T_2[0]; // @[Edges.scala:230:28] wire d_first_2 = ~d_first_counter_2; // @[Edges.scala:229:27, :231:25] wire _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire _d_first_counter_T_2 = ~d_first_2 & d_first_counter1_2; // @[Edges.scala:230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [15:0] _c_opcode_lookup_T_6 = {12'h0, _c_opcode_lookup_T_1}; // @[Monitor.scala:637:97, :749:{44,97}] wire [15:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[15:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [15:0] _c_size_lookup_T_6 = {12'h0, _c_size_lookup_T_1}; // @[Monitor.scala:637:97, :750:{42,93}] wire [15:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[15:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire d_clr_1; // @[Monitor.scala:774:34] wire d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [3:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [3:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_702 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_702 & d_release_ack_1; // @[Monitor.scala:775:34, :783:46, :784:{26,71}] assign d_clr_1 = _T_726 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] wire [3:0] _GEN_1 = {4{d_clr_1}}; // @[Monitor.scala:774:34, :776:34, :788:88, :790:21] assign d_opcodes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :788:88, :790:21] assign d_sizes_clr_1 = _GEN_1; // @[Monitor.scala:776:34, :777:34, :788:88, :790:21] wire _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [1:0] _inflight_T_5 = {1'h0, _inflight_T_3[0] & _inflight_T_4}; // @[Monitor.scala:814:{35,44,46}] wire [3:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [3:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [3:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [3:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_16 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid_0 of AsyncResetSynchronizerShiftReg_w1_d3_i0_26 connect io_out_source_valid_0.clock, clock connect io_out_source_valid_0.reset, reset connect io_out_source_valid_0.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid_0.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_16( // @[AsyncQueue.scala:58:7] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in = 1'h1; // @[ShiftReg.scala:45:23] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_26 io_out_source_valid_0 ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module BranchKillableQueue_9 : input clock : Clock input reset : Reset output io : { flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>}}, flip brupdate : { b1 : { resolve_mask : UInt<16>, mispredict_mask : UInt<16>}, b2 : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, valid : UInt<1>, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt}}, flip flush : UInt<1>, empty : UInt<1>, count : UInt<4>} cmem ram : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} [16] wire _valids_WIRE : UInt<1>[16] connect _valids_WIRE[0], UInt<1>(0h0) connect _valids_WIRE[1], UInt<1>(0h0) connect _valids_WIRE[2], UInt<1>(0h0) connect _valids_WIRE[3], UInt<1>(0h0) connect _valids_WIRE[4], UInt<1>(0h0) connect _valids_WIRE[5], UInt<1>(0h0) connect _valids_WIRE[6], UInt<1>(0h0) connect _valids_WIRE[7], UInt<1>(0h0) connect _valids_WIRE[8], UInt<1>(0h0) connect _valids_WIRE[9], UInt<1>(0h0) connect _valids_WIRE[10], UInt<1>(0h0) connect _valids_WIRE[11], UInt<1>(0h0) connect _valids_WIRE[12], UInt<1>(0h0) connect _valids_WIRE[13], UInt<1>(0h0) connect _valids_WIRE[14], UInt<1>(0h0) connect _valids_WIRE[15], UInt<1>(0h0) regreset valids : UInt<1>[16], clock, reset, _valids_WIRE reg uops : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}[16], clock regreset enq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset deq_ptr_value : UInt<4>, clock, reset, UInt<4>(0h0) regreset maybe_full : UInt<1>, clock, reset, UInt<1>(0h0) node ptr_match = eq(enq_ptr_value, deq_ptr_value) node _io_empty_T = eq(maybe_full, UInt<1>(0h0)) node _io_empty_T_1 = and(ptr_match, _io_empty_T) connect io.empty, _io_empty_T_1 node full = and(ptr_match, maybe_full) node _do_enq_T = and(io.enq.ready, io.enq.valid) wire do_enq : UInt<1> connect do_enq, _do_enq_T node _do_deq_T = eq(valids[deq_ptr_value], UInt<1>(0h0)) node _do_deq_T_1 = or(io.deq.ready, _do_deq_T) node _do_deq_T_2 = eq(io.empty, UInt<1>(0h0)) node _do_deq_T_3 = and(_do_deq_T_1, _do_deq_T_2) wire do_deq : UInt<1> connect do_deq, _do_deq_T_3 node _valids_0_T = and(io.brupdate.b1.mispredict_mask, uops[0].br_mask) node _valids_0_T_1 = neq(_valids_0_T, UInt<1>(0h0)) node _valids_0_T_2 = eq(_valids_0_T_1, UInt<1>(0h0)) node _valids_0_T_3 = and(valids[0], _valids_0_T_2) node _valids_0_T_4 = and(io.flush, uops[0].uses_ldq) node _valids_0_T_5 = eq(_valids_0_T_4, UInt<1>(0h0)) node _valids_0_T_6 = and(_valids_0_T_3, _valids_0_T_5) connect valids[0], _valids_0_T_6 when valids[0] : node _uops_0_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_0_br_mask_T_1 = and(uops[0].br_mask, _uops_0_br_mask_T) connect uops[0].br_mask, _uops_0_br_mask_T_1 node _valids_1_T = and(io.brupdate.b1.mispredict_mask, uops[1].br_mask) node _valids_1_T_1 = neq(_valids_1_T, UInt<1>(0h0)) node _valids_1_T_2 = eq(_valids_1_T_1, UInt<1>(0h0)) node _valids_1_T_3 = and(valids[1], _valids_1_T_2) node _valids_1_T_4 = and(io.flush, uops[1].uses_ldq) node _valids_1_T_5 = eq(_valids_1_T_4, UInt<1>(0h0)) node _valids_1_T_6 = and(_valids_1_T_3, _valids_1_T_5) connect valids[1], _valids_1_T_6 when valids[1] : node _uops_1_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_1_br_mask_T_1 = and(uops[1].br_mask, _uops_1_br_mask_T) connect uops[1].br_mask, _uops_1_br_mask_T_1 node _valids_2_T = and(io.brupdate.b1.mispredict_mask, uops[2].br_mask) node _valids_2_T_1 = neq(_valids_2_T, UInt<1>(0h0)) node _valids_2_T_2 = eq(_valids_2_T_1, UInt<1>(0h0)) node _valids_2_T_3 = and(valids[2], _valids_2_T_2) node _valids_2_T_4 = and(io.flush, uops[2].uses_ldq) node _valids_2_T_5 = eq(_valids_2_T_4, UInt<1>(0h0)) node _valids_2_T_6 = and(_valids_2_T_3, _valids_2_T_5) connect valids[2], _valids_2_T_6 when valids[2] : node _uops_2_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_2_br_mask_T_1 = and(uops[2].br_mask, _uops_2_br_mask_T) connect uops[2].br_mask, _uops_2_br_mask_T_1 node _valids_3_T = and(io.brupdate.b1.mispredict_mask, uops[3].br_mask) node _valids_3_T_1 = neq(_valids_3_T, UInt<1>(0h0)) node _valids_3_T_2 = eq(_valids_3_T_1, UInt<1>(0h0)) node _valids_3_T_3 = and(valids[3], _valids_3_T_2) node _valids_3_T_4 = and(io.flush, uops[3].uses_ldq) node _valids_3_T_5 = eq(_valids_3_T_4, UInt<1>(0h0)) node _valids_3_T_6 = and(_valids_3_T_3, _valids_3_T_5) connect valids[3], _valids_3_T_6 when valids[3] : node _uops_3_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_3_br_mask_T_1 = and(uops[3].br_mask, _uops_3_br_mask_T) connect uops[3].br_mask, _uops_3_br_mask_T_1 node _valids_4_T = and(io.brupdate.b1.mispredict_mask, uops[4].br_mask) node _valids_4_T_1 = neq(_valids_4_T, UInt<1>(0h0)) node _valids_4_T_2 = eq(_valids_4_T_1, UInt<1>(0h0)) node _valids_4_T_3 = and(valids[4], _valids_4_T_2) node _valids_4_T_4 = and(io.flush, uops[4].uses_ldq) node _valids_4_T_5 = eq(_valids_4_T_4, UInt<1>(0h0)) node _valids_4_T_6 = and(_valids_4_T_3, _valids_4_T_5) connect valids[4], _valids_4_T_6 when valids[4] : node _uops_4_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_4_br_mask_T_1 = and(uops[4].br_mask, _uops_4_br_mask_T) connect uops[4].br_mask, _uops_4_br_mask_T_1 node _valids_5_T = and(io.brupdate.b1.mispredict_mask, uops[5].br_mask) node _valids_5_T_1 = neq(_valids_5_T, UInt<1>(0h0)) node _valids_5_T_2 = eq(_valids_5_T_1, UInt<1>(0h0)) node _valids_5_T_3 = and(valids[5], _valids_5_T_2) node _valids_5_T_4 = and(io.flush, uops[5].uses_ldq) node _valids_5_T_5 = eq(_valids_5_T_4, UInt<1>(0h0)) node _valids_5_T_6 = and(_valids_5_T_3, _valids_5_T_5) connect valids[5], _valids_5_T_6 when valids[5] : node _uops_5_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_5_br_mask_T_1 = and(uops[5].br_mask, _uops_5_br_mask_T) connect uops[5].br_mask, _uops_5_br_mask_T_1 node _valids_6_T = and(io.brupdate.b1.mispredict_mask, uops[6].br_mask) node _valids_6_T_1 = neq(_valids_6_T, UInt<1>(0h0)) node _valids_6_T_2 = eq(_valids_6_T_1, UInt<1>(0h0)) node _valids_6_T_3 = and(valids[6], _valids_6_T_2) node _valids_6_T_4 = and(io.flush, uops[6].uses_ldq) node _valids_6_T_5 = eq(_valids_6_T_4, UInt<1>(0h0)) node _valids_6_T_6 = and(_valids_6_T_3, _valids_6_T_5) connect valids[6], _valids_6_T_6 when valids[6] : node _uops_6_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_6_br_mask_T_1 = and(uops[6].br_mask, _uops_6_br_mask_T) connect uops[6].br_mask, _uops_6_br_mask_T_1 node _valids_7_T = and(io.brupdate.b1.mispredict_mask, uops[7].br_mask) node _valids_7_T_1 = neq(_valids_7_T, UInt<1>(0h0)) node _valids_7_T_2 = eq(_valids_7_T_1, UInt<1>(0h0)) node _valids_7_T_3 = and(valids[7], _valids_7_T_2) node _valids_7_T_4 = and(io.flush, uops[7].uses_ldq) node _valids_7_T_5 = eq(_valids_7_T_4, UInt<1>(0h0)) node _valids_7_T_6 = and(_valids_7_T_3, _valids_7_T_5) connect valids[7], _valids_7_T_6 when valids[7] : node _uops_7_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_7_br_mask_T_1 = and(uops[7].br_mask, _uops_7_br_mask_T) connect uops[7].br_mask, _uops_7_br_mask_T_1 node _valids_8_T = and(io.brupdate.b1.mispredict_mask, uops[8].br_mask) node _valids_8_T_1 = neq(_valids_8_T, UInt<1>(0h0)) node _valids_8_T_2 = eq(_valids_8_T_1, UInt<1>(0h0)) node _valids_8_T_3 = and(valids[8], _valids_8_T_2) node _valids_8_T_4 = and(io.flush, uops[8].uses_ldq) node _valids_8_T_5 = eq(_valids_8_T_4, UInt<1>(0h0)) node _valids_8_T_6 = and(_valids_8_T_3, _valids_8_T_5) connect valids[8], _valids_8_T_6 when valids[8] : node _uops_8_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_8_br_mask_T_1 = and(uops[8].br_mask, _uops_8_br_mask_T) connect uops[8].br_mask, _uops_8_br_mask_T_1 node _valids_9_T = and(io.brupdate.b1.mispredict_mask, uops[9].br_mask) node _valids_9_T_1 = neq(_valids_9_T, UInt<1>(0h0)) node _valids_9_T_2 = eq(_valids_9_T_1, UInt<1>(0h0)) node _valids_9_T_3 = and(valids[9], _valids_9_T_2) node _valids_9_T_4 = and(io.flush, uops[9].uses_ldq) node _valids_9_T_5 = eq(_valids_9_T_4, UInt<1>(0h0)) node _valids_9_T_6 = and(_valids_9_T_3, _valids_9_T_5) connect valids[9], _valids_9_T_6 when valids[9] : node _uops_9_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_9_br_mask_T_1 = and(uops[9].br_mask, _uops_9_br_mask_T) connect uops[9].br_mask, _uops_9_br_mask_T_1 node _valids_10_T = and(io.brupdate.b1.mispredict_mask, uops[10].br_mask) node _valids_10_T_1 = neq(_valids_10_T, UInt<1>(0h0)) node _valids_10_T_2 = eq(_valids_10_T_1, UInt<1>(0h0)) node _valids_10_T_3 = and(valids[10], _valids_10_T_2) node _valids_10_T_4 = and(io.flush, uops[10].uses_ldq) node _valids_10_T_5 = eq(_valids_10_T_4, UInt<1>(0h0)) node _valids_10_T_6 = and(_valids_10_T_3, _valids_10_T_5) connect valids[10], _valids_10_T_6 when valids[10] : node _uops_10_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_10_br_mask_T_1 = and(uops[10].br_mask, _uops_10_br_mask_T) connect uops[10].br_mask, _uops_10_br_mask_T_1 node _valids_11_T = and(io.brupdate.b1.mispredict_mask, uops[11].br_mask) node _valids_11_T_1 = neq(_valids_11_T, UInt<1>(0h0)) node _valids_11_T_2 = eq(_valids_11_T_1, UInt<1>(0h0)) node _valids_11_T_3 = and(valids[11], _valids_11_T_2) node _valids_11_T_4 = and(io.flush, uops[11].uses_ldq) node _valids_11_T_5 = eq(_valids_11_T_4, UInt<1>(0h0)) node _valids_11_T_6 = and(_valids_11_T_3, _valids_11_T_5) connect valids[11], _valids_11_T_6 when valids[11] : node _uops_11_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_11_br_mask_T_1 = and(uops[11].br_mask, _uops_11_br_mask_T) connect uops[11].br_mask, _uops_11_br_mask_T_1 node _valids_12_T = and(io.brupdate.b1.mispredict_mask, uops[12].br_mask) node _valids_12_T_1 = neq(_valids_12_T, UInt<1>(0h0)) node _valids_12_T_2 = eq(_valids_12_T_1, UInt<1>(0h0)) node _valids_12_T_3 = and(valids[12], _valids_12_T_2) node _valids_12_T_4 = and(io.flush, uops[12].uses_ldq) node _valids_12_T_5 = eq(_valids_12_T_4, UInt<1>(0h0)) node _valids_12_T_6 = and(_valids_12_T_3, _valids_12_T_5) connect valids[12], _valids_12_T_6 when valids[12] : node _uops_12_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_12_br_mask_T_1 = and(uops[12].br_mask, _uops_12_br_mask_T) connect uops[12].br_mask, _uops_12_br_mask_T_1 node _valids_13_T = and(io.brupdate.b1.mispredict_mask, uops[13].br_mask) node _valids_13_T_1 = neq(_valids_13_T, UInt<1>(0h0)) node _valids_13_T_2 = eq(_valids_13_T_1, UInt<1>(0h0)) node _valids_13_T_3 = and(valids[13], _valids_13_T_2) node _valids_13_T_4 = and(io.flush, uops[13].uses_ldq) node _valids_13_T_5 = eq(_valids_13_T_4, UInt<1>(0h0)) node _valids_13_T_6 = and(_valids_13_T_3, _valids_13_T_5) connect valids[13], _valids_13_T_6 when valids[13] : node _uops_13_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_13_br_mask_T_1 = and(uops[13].br_mask, _uops_13_br_mask_T) connect uops[13].br_mask, _uops_13_br_mask_T_1 node _valids_14_T = and(io.brupdate.b1.mispredict_mask, uops[14].br_mask) node _valids_14_T_1 = neq(_valids_14_T, UInt<1>(0h0)) node _valids_14_T_2 = eq(_valids_14_T_1, UInt<1>(0h0)) node _valids_14_T_3 = and(valids[14], _valids_14_T_2) node _valids_14_T_4 = and(io.flush, uops[14].uses_ldq) node _valids_14_T_5 = eq(_valids_14_T_4, UInt<1>(0h0)) node _valids_14_T_6 = and(_valids_14_T_3, _valids_14_T_5) connect valids[14], _valids_14_T_6 when valids[14] : node _uops_14_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_14_br_mask_T_1 = and(uops[14].br_mask, _uops_14_br_mask_T) connect uops[14].br_mask, _uops_14_br_mask_T_1 node _valids_15_T = and(io.brupdate.b1.mispredict_mask, uops[15].br_mask) node _valids_15_T_1 = neq(_valids_15_T, UInt<1>(0h0)) node _valids_15_T_2 = eq(_valids_15_T_1, UInt<1>(0h0)) node _valids_15_T_3 = and(valids[15], _valids_15_T_2) node _valids_15_T_4 = and(io.flush, uops[15].uses_ldq) node _valids_15_T_5 = eq(_valids_15_T_4, UInt<1>(0h0)) node _valids_15_T_6 = and(_valids_15_T_3, _valids_15_T_5) connect valids[15], _valids_15_T_6 when valids[15] : node _uops_15_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_15_br_mask_T_1 = and(uops[15].br_mask, _uops_15_br_mask_T) connect uops[15].br_mask, _uops_15_br_mask_T_1 when do_enq : infer mport MPORT = ram[enq_ptr_value], clock connect MPORT, io.enq.bits connect valids[enq_ptr_value], UInt<1>(0h1) connect uops[enq_ptr_value], io.enq.bits.uop node _uops_br_mask_T = not(io.brupdate.b1.resolve_mask) node _uops_br_mask_T_1 = and(io.enq.bits.uop.br_mask, _uops_br_mask_T) connect uops[enq_ptr_value].br_mask, _uops_br_mask_T_1 node wrap = eq(enq_ptr_value, UInt<4>(0hf)) node _value_T = add(enq_ptr_value, UInt<1>(0h1)) node _value_T_1 = tail(_value_T, 1) connect enq_ptr_value, _value_T_1 when do_deq : connect valids[deq_ptr_value], UInt<1>(0h0) node wrap_1 = eq(deq_ptr_value, UInt<4>(0hf)) node _value_T_2 = add(deq_ptr_value, UInt<1>(0h1)) node _value_T_3 = tail(_value_T_2, 1) connect deq_ptr_value, _value_T_3 node _T = neq(do_enq, do_deq) when _T : connect maybe_full, do_enq node _io_enq_ready_T = eq(full, UInt<1>(0h0)) connect io.enq.ready, _io_enq_ready_T wire out : { uop : { uopc : UInt<7>, inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<3>, fu_code : UInt<10>, ctrl : { br_type : UInt<4>, op1_sel : UInt<2>, op2_sel : UInt<3>, imm_sel : UInt<3>, op_fcn : UInt<5>, fcn_dw : UInt<1>, csr_cmd : UInt<3>, is_load : UInt<1>, is_sta : UInt<1>, is_std : UInt<1>}, iw_state : UInt<2>, iw_p1_poisoned : UInt<1>, iw_p2_poisoned : UInt<1>, is_br : UInt<1>, is_jalr : UInt<1>, is_jal : UInt<1>, is_sfb : UInt<1>, br_mask : UInt<16>, br_tag : UInt<4>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_packed : UInt<20>, csr_addr : UInt<12>, rob_idx : UInt<7>, ldq_idx : UInt<5>, stq_idx : UInt<5>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, bypassable : UInt<1>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_amo : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_sys_pc2epc : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, ldst_val : UInt<1>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fp_val : UInt<1>, fp_single : UInt<1>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<2>, debug_tsrc : UInt<2>}, addr : UInt<40>, data : UInt<64>, is_hella : UInt<1>, tag_match : UInt<1>, old_meta : { coh : { state : UInt<2>}, tag : UInt<20>}, way_en : UInt<8>, sdq_id : UInt<5>} infer mport out_MPORT = ram[deq_ptr_value], clock connect out, out_MPORT connect out.uop, uops[deq_ptr_value] node _io_deq_valid_T = eq(io.empty, UInt<1>(0h0)) node _io_deq_valid_T_1 = and(_io_deq_valid_T, valids[deq_ptr_value]) node _io_deq_valid_T_2 = and(io.brupdate.b1.mispredict_mask, out.uop.br_mask) node _io_deq_valid_T_3 = neq(_io_deq_valid_T_2, UInt<1>(0h0)) node _io_deq_valid_T_4 = eq(_io_deq_valid_T_3, UInt<1>(0h0)) node _io_deq_valid_T_5 = and(_io_deq_valid_T_1, _io_deq_valid_T_4) node _io_deq_valid_T_6 = and(io.flush, out.uop.uses_ldq) node _io_deq_valid_T_7 = eq(_io_deq_valid_T_6, UInt<1>(0h0)) node _io_deq_valid_T_8 = and(_io_deq_valid_T_5, _io_deq_valid_T_7) connect io.deq.valid, _io_deq_valid_T_8 connect io.deq.bits, out node _io_deq_bits_uop_br_mask_T = not(io.brupdate.b1.resolve_mask) node _io_deq_bits_uop_br_mask_T_1 = and(out.uop.br_mask, _io_deq_bits_uop_br_mask_T) connect io.deq.bits.uop.br_mask, _io_deq_bits_uop_br_mask_T_1 node _ptr_diff_T = sub(enq_ptr_value, deq_ptr_value) node ptr_diff = tail(_ptr_diff_T, 1) node _io_count_T = and(maybe_full, ptr_match) node _io_count_T_1 = cat(_io_count_T, ptr_diff) connect io.count, _io_count_T_1
module BranchKillableQueue_9( // @[util.scala:448:7] input clock, // @[util.scala:448:7] input reset, // @[util.scala:448:7] output io_enq_ready, // @[util.scala:453:14] input io_enq_valid, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_uopc, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_inst, // @[util.scala:453:14] input [31:0] io_enq_bits_uop_debug_inst, // @[util.scala:453:14] input io_enq_bits_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_enq_bits_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_iq_type, // @[util.scala:453:14] input [9:0] io_enq_bits_uop_fu_code, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_enq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_load, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] input io_enq_bits_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_iw_state, // @[util.scala:453:14] input io_enq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_enq_bits_uop_is_br, // @[util.scala:453:14] input io_enq_bits_uop_is_jalr, // @[util.scala:453:14] input io_enq_bits_uop_is_jal, // @[util.scala:453:14] input io_enq_bits_uop_is_sfb, // @[util.scala:453:14] input [15:0] io_enq_bits_uop_br_mask, // @[util.scala:453:14] input [3:0] io_enq_bits_uop_br_tag, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ftq_idx, // @[util.scala:453:14] input io_enq_bits_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_pc_lob, // @[util.scala:453:14] input io_enq_bits_uop_taken, // @[util.scala:453:14] input [19:0] io_enq_bits_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_enq_bits_uop_csr_addr, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_rob_idx, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ldq_idx, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_pdst, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs1, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs2, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_prs3, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_ppred, // @[util.scala:453:14] input io_enq_bits_uop_prs1_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs2_busy, // @[util.scala:453:14] input io_enq_bits_uop_prs3_busy, // @[util.scala:453:14] input io_enq_bits_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_enq_bits_uop_stale_pdst, // @[util.scala:453:14] input io_enq_bits_uop_exception, // @[util.scala:453:14] input [63:0] io_enq_bits_uop_exc_cause, // @[util.scala:453:14] input io_enq_bits_uop_bypassable, // @[util.scala:453:14] input [4:0] io_enq_bits_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_mem_size, // @[util.scala:453:14] input io_enq_bits_uop_mem_signed, // @[util.scala:453:14] input io_enq_bits_uop_is_fence, // @[util.scala:453:14] input io_enq_bits_uop_is_fencei, // @[util.scala:453:14] input io_enq_bits_uop_is_amo, // @[util.scala:453:14] input io_enq_bits_uop_uses_ldq, // @[util.scala:453:14] input io_enq_bits_uop_uses_stq, // @[util.scala:453:14] input io_enq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_enq_bits_uop_is_unique, // @[util.scala:453:14] input io_enq_bits_uop_flush_on_commit, // @[util.scala:453:14] input io_enq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_ldst, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs1, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs2, // @[util.scala:453:14] input [5:0] io_enq_bits_uop_lrs3, // @[util.scala:453:14] input io_enq_bits_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_lrs2_rtype, // @[util.scala:453:14] input io_enq_bits_uop_frs3_en, // @[util.scala:453:14] input io_enq_bits_uop_fp_val, // @[util.scala:453:14] input io_enq_bits_uop_fp_single, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] input io_enq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_debug_if, // @[util.scala:453:14] input io_enq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_enq_bits_uop_debug_tsrc, // @[util.scala:453:14] input [39:0] io_enq_bits_addr, // @[util.scala:453:14] input [63:0] io_enq_bits_data, // @[util.scala:453:14] input io_enq_bits_is_hella, // @[util.scala:453:14] input io_enq_bits_tag_match, // @[util.scala:453:14] input [1:0] io_enq_bits_old_meta_coh_state, // @[util.scala:453:14] input [19:0] io_enq_bits_old_meta_tag, // @[util.scala:453:14] input [7:0] io_enq_bits_way_en, // @[util.scala:453:14] input [4:0] io_enq_bits_sdq_id, // @[util.scala:453:14] input io_deq_ready, // @[util.scala:453:14] output io_deq_valid, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_uopc, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_inst, // @[util.scala:453:14] output [31:0] io_deq_bits_uop_debug_inst, // @[util.scala:453:14] output io_deq_bits_uop_is_rvc, // @[util.scala:453:14] output [39:0] io_deq_bits_uop_debug_pc, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_iq_type, // @[util.scala:453:14] output [9:0] io_deq_bits_uop_fu_code, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_ctrl_br_type, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_ctrl_op1_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_op2_sel, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_imm_sel, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ctrl_op_fcn, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_fcn_dw, // @[util.scala:453:14] output [2:0] io_deq_bits_uop_ctrl_csr_cmd, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_load, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_sta, // @[util.scala:453:14] output io_deq_bits_uop_ctrl_is_std, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_iw_state, // @[util.scala:453:14] output io_deq_bits_uop_iw_p1_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_iw_p2_poisoned, // @[util.scala:453:14] output io_deq_bits_uop_is_br, // @[util.scala:453:14] output io_deq_bits_uop_is_jalr, // @[util.scala:453:14] output io_deq_bits_uop_is_jal, // @[util.scala:453:14] output io_deq_bits_uop_is_sfb, // @[util.scala:453:14] output [15:0] io_deq_bits_uop_br_mask, // @[util.scala:453:14] output [3:0] io_deq_bits_uop_br_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ftq_idx, // @[util.scala:453:14] output io_deq_bits_uop_edge_inst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_pc_lob, // @[util.scala:453:14] output io_deq_bits_uop_taken, // @[util.scala:453:14] output [19:0] io_deq_bits_uop_imm_packed, // @[util.scala:453:14] output [11:0] io_deq_bits_uop_csr_addr, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_rob_idx, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ldq_idx, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_stq_idx, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_rxq_idx, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_pdst, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs1, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs2, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_prs3, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_ppred, // @[util.scala:453:14] output io_deq_bits_uop_prs1_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs2_busy, // @[util.scala:453:14] output io_deq_bits_uop_prs3_busy, // @[util.scala:453:14] output io_deq_bits_uop_ppred_busy, // @[util.scala:453:14] output [6:0] io_deq_bits_uop_stale_pdst, // @[util.scala:453:14] output io_deq_bits_uop_exception, // @[util.scala:453:14] output [63:0] io_deq_bits_uop_exc_cause, // @[util.scala:453:14] output io_deq_bits_uop_bypassable, // @[util.scala:453:14] output [4:0] io_deq_bits_uop_mem_cmd, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_mem_size, // @[util.scala:453:14] output io_deq_bits_uop_mem_signed, // @[util.scala:453:14] output io_deq_bits_uop_is_fence, // @[util.scala:453:14] output io_deq_bits_uop_is_fencei, // @[util.scala:453:14] output io_deq_bits_uop_is_amo, // @[util.scala:453:14] output io_deq_bits_uop_uses_ldq, // @[util.scala:453:14] output io_deq_bits_uop_uses_stq, // @[util.scala:453:14] output io_deq_bits_uop_is_sys_pc2epc, // @[util.scala:453:14] output io_deq_bits_uop_is_unique, // @[util.scala:453:14] output io_deq_bits_uop_flush_on_commit, // @[util.scala:453:14] output io_deq_bits_uop_ldst_is_rs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_ldst, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs1, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs2, // @[util.scala:453:14] output [5:0] io_deq_bits_uop_lrs3, // @[util.scala:453:14] output io_deq_bits_uop_ldst_val, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_dst_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs1_rtype, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_lrs2_rtype, // @[util.scala:453:14] output io_deq_bits_uop_frs3_en, // @[util.scala:453:14] output io_deq_bits_uop_fp_val, // @[util.scala:453:14] output io_deq_bits_uop_fp_single, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_pf_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ae_if, // @[util.scala:453:14] output io_deq_bits_uop_xcpt_ma_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_debug_if, // @[util.scala:453:14] output io_deq_bits_uop_bp_xcpt_if, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_fsrc, // @[util.scala:453:14] output [1:0] io_deq_bits_uop_debug_tsrc, // @[util.scala:453:14] output [39:0] io_deq_bits_addr, // @[util.scala:453:14] output [63:0] io_deq_bits_data, // @[util.scala:453:14] output io_deq_bits_is_hella, // @[util.scala:453:14] output io_deq_bits_tag_match, // @[util.scala:453:14] output [1:0] io_deq_bits_old_meta_coh_state, // @[util.scala:453:14] output [19:0] io_deq_bits_old_meta_tag, // @[util.scala:453:14] output [4:0] io_deq_bits_sdq_id, // @[util.scala:453:14] input [15:0] io_brupdate_b1_resolve_mask, // @[util.scala:453:14] input [15:0] io_brupdate_b1_mispredict_mask, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_uopc, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_inst, // @[util.scala:453:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[util.scala:453:14] input io_brupdate_b2_uop_is_rvc, // @[util.scala:453:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_iq_type, // @[util.scala:453:14] input [9:0] io_brupdate_b2_uop_fu_code, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_ctrl_br_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_ctrl_op1_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_op2_sel, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_imm_sel, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ctrl_op_fcn, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_fcn_dw, // @[util.scala:453:14] input [2:0] io_brupdate_b2_uop_ctrl_csr_cmd, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_load, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_sta, // @[util.scala:453:14] input io_brupdate_b2_uop_ctrl_is_std, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_iw_state, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p1_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_iw_p2_poisoned, // @[util.scala:453:14] input io_brupdate_b2_uop_is_br, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jalr, // @[util.scala:453:14] input io_brupdate_b2_uop_is_jal, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sfb, // @[util.scala:453:14] input [15:0] io_brupdate_b2_uop_br_mask, // @[util.scala:453:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[util.scala:453:14] input io_brupdate_b2_uop_edge_inst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[util.scala:453:14] input io_brupdate_b2_uop_taken, // @[util.scala:453:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[util.scala:453:14] input [11:0] io_brupdate_b2_uop_csr_addr, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_rob_idx, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ldq_idx, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_stq_idx, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_pdst, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs1, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs2, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_prs3, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_ppred, // @[util.scala:453:14] input io_brupdate_b2_uop_prs1_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs2_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_prs3_busy, // @[util.scala:453:14] input io_brupdate_b2_uop_ppred_busy, // @[util.scala:453:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[util.scala:453:14] input io_brupdate_b2_uop_exception, // @[util.scala:453:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[util.scala:453:14] input io_brupdate_b2_uop_bypassable, // @[util.scala:453:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[util.scala:453:14] input io_brupdate_b2_uop_mem_signed, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fence, // @[util.scala:453:14] input io_brupdate_b2_uop_is_fencei, // @[util.scala:453:14] input io_brupdate_b2_uop_is_amo, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_ldq, // @[util.scala:453:14] input io_brupdate_b2_uop_uses_stq, // @[util.scala:453:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[util.scala:453:14] input io_brupdate_b2_uop_is_unique, // @[util.scala:453:14] input io_brupdate_b2_uop_flush_on_commit, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_ldst, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[util.scala:453:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[util.scala:453:14] input io_brupdate_b2_uop_ldst_val, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[util.scala:453:14] input io_brupdate_b2_uop_frs3_en, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_val, // @[util.scala:453:14] input io_brupdate_b2_uop_fp_single, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[util.scala:453:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_debug_if, // @[util.scala:453:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_fsrc, // @[util.scala:453:14] input [1:0] io_brupdate_b2_uop_debug_tsrc, // @[util.scala:453:14] input io_brupdate_b2_valid, // @[util.scala:453:14] input io_brupdate_b2_mispredict, // @[util.scala:453:14] input io_brupdate_b2_taken, // @[util.scala:453:14] input [2:0] io_brupdate_b2_cfi_type, // @[util.scala:453:14] input [1:0] io_brupdate_b2_pc_sel, // @[util.scala:453:14] input [39:0] io_brupdate_b2_jalr_target, // @[util.scala:453:14] input [20:0] io_brupdate_b2_target_offset, // @[util.scala:453:14] input io_flush, // @[util.scala:453:14] output io_empty // @[util.scala:453:14] ); wire [140:0] _ram_ext_R0_data; // @[util.scala:464:20] wire io_enq_valid_0 = io_enq_valid; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_uopc_0 = io_enq_bits_uop_uopc; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_inst_0 = io_enq_bits_uop_inst; // @[util.scala:448:7] wire [31:0] io_enq_bits_uop_debug_inst_0 = io_enq_bits_uop_debug_inst; // @[util.scala:448:7] wire io_enq_bits_uop_is_rvc_0 = io_enq_bits_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_enq_bits_uop_debug_pc_0 = io_enq_bits_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_iq_type_0 = io_enq_bits_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_enq_bits_uop_fu_code_0 = io_enq_bits_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_ctrl_br_type_0 = io_enq_bits_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_ctrl_op1_sel_0 = io_enq_bits_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_op2_sel_0 = io_enq_bits_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_imm_sel_0 = io_enq_bits_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ctrl_op_fcn_0 = io_enq_bits_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_fcn_dw_0 = io_enq_bits_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_enq_bits_uop_ctrl_csr_cmd_0 = io_enq_bits_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_load_0 = io_enq_bits_uop_ctrl_is_load; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_sta_0 = io_enq_bits_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_enq_bits_uop_ctrl_is_std_0 = io_enq_bits_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_iw_state_0 = io_enq_bits_uop_iw_state; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p1_poisoned_0 = io_enq_bits_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_iw_p2_poisoned_0 = io_enq_bits_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_enq_bits_uop_is_br_0 = io_enq_bits_uop_is_br; // @[util.scala:448:7] wire io_enq_bits_uop_is_jalr_0 = io_enq_bits_uop_is_jalr; // @[util.scala:448:7] wire io_enq_bits_uop_is_jal_0 = io_enq_bits_uop_is_jal; // @[util.scala:448:7] wire io_enq_bits_uop_is_sfb_0 = io_enq_bits_uop_is_sfb; // @[util.scala:448:7] wire [15:0] io_enq_bits_uop_br_mask_0 = io_enq_bits_uop_br_mask; // @[util.scala:448:7] wire [3:0] io_enq_bits_uop_br_tag_0 = io_enq_bits_uop_br_tag; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ftq_idx_0 = io_enq_bits_uop_ftq_idx; // @[util.scala:448:7] wire io_enq_bits_uop_edge_inst_0 = io_enq_bits_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_pc_lob_0 = io_enq_bits_uop_pc_lob; // @[util.scala:448:7] wire io_enq_bits_uop_taken_0 = io_enq_bits_uop_taken; // @[util.scala:448:7] wire [19:0] io_enq_bits_uop_imm_packed_0 = io_enq_bits_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_enq_bits_uop_csr_addr_0 = io_enq_bits_uop_csr_addr; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_rob_idx_0 = io_enq_bits_uop_rob_idx; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ldq_idx_0 = io_enq_bits_uop_ldq_idx; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_stq_idx_0 = io_enq_bits_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_rxq_idx_0 = io_enq_bits_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_pdst_0 = io_enq_bits_uop_pdst; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs1_0 = io_enq_bits_uop_prs1; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs2_0 = io_enq_bits_uop_prs2; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_prs3_0 = io_enq_bits_uop_prs3; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_ppred_0 = io_enq_bits_uop_ppred; // @[util.scala:448:7] wire io_enq_bits_uop_prs1_busy_0 = io_enq_bits_uop_prs1_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs2_busy_0 = io_enq_bits_uop_prs2_busy; // @[util.scala:448:7] wire io_enq_bits_uop_prs3_busy_0 = io_enq_bits_uop_prs3_busy; // @[util.scala:448:7] wire io_enq_bits_uop_ppred_busy_0 = io_enq_bits_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_enq_bits_uop_stale_pdst_0 = io_enq_bits_uop_stale_pdst; // @[util.scala:448:7] wire io_enq_bits_uop_exception_0 = io_enq_bits_uop_exception; // @[util.scala:448:7] wire [63:0] io_enq_bits_uop_exc_cause_0 = io_enq_bits_uop_exc_cause; // @[util.scala:448:7] wire io_enq_bits_uop_bypassable_0 = io_enq_bits_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_enq_bits_uop_mem_cmd_0 = io_enq_bits_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_mem_size_0 = io_enq_bits_uop_mem_size; // @[util.scala:448:7] wire io_enq_bits_uop_mem_signed_0 = io_enq_bits_uop_mem_signed; // @[util.scala:448:7] wire io_enq_bits_uop_is_fence_0 = io_enq_bits_uop_is_fence; // @[util.scala:448:7] wire io_enq_bits_uop_is_fencei_0 = io_enq_bits_uop_is_fencei; // @[util.scala:448:7] wire io_enq_bits_uop_is_amo_0 = io_enq_bits_uop_is_amo; // @[util.scala:448:7] wire io_enq_bits_uop_uses_ldq_0 = io_enq_bits_uop_uses_ldq; // @[util.scala:448:7] wire io_enq_bits_uop_uses_stq_0 = io_enq_bits_uop_uses_stq; // @[util.scala:448:7] wire io_enq_bits_uop_is_sys_pc2epc_0 = io_enq_bits_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_enq_bits_uop_is_unique_0 = io_enq_bits_uop_is_unique; // @[util.scala:448:7] wire io_enq_bits_uop_flush_on_commit_0 = io_enq_bits_uop_flush_on_commit; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_is_rs1_0 = io_enq_bits_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_ldst_0 = io_enq_bits_uop_ldst; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs1_0 = io_enq_bits_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs2_0 = io_enq_bits_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_enq_bits_uop_lrs3_0 = io_enq_bits_uop_lrs3; // @[util.scala:448:7] wire io_enq_bits_uop_ldst_val_0 = io_enq_bits_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_dst_rtype_0 = io_enq_bits_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs1_rtype_0 = io_enq_bits_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_lrs2_rtype_0 = io_enq_bits_uop_lrs2_rtype; // @[util.scala:448:7] wire io_enq_bits_uop_frs3_en_0 = io_enq_bits_uop_frs3_en; // @[util.scala:448:7] wire io_enq_bits_uop_fp_val_0 = io_enq_bits_uop_fp_val; // @[util.scala:448:7] wire io_enq_bits_uop_fp_single_0 = io_enq_bits_uop_fp_single; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_pf_if_0 = io_enq_bits_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ae_if_0 = io_enq_bits_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_enq_bits_uop_xcpt_ma_if_0 = io_enq_bits_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_debug_if_0 = io_enq_bits_uop_bp_debug_if; // @[util.scala:448:7] wire io_enq_bits_uop_bp_xcpt_if_0 = io_enq_bits_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_fsrc_0 = io_enq_bits_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_enq_bits_uop_debug_tsrc_0 = io_enq_bits_uop_debug_tsrc; // @[util.scala:448:7] wire [39:0] io_enq_bits_addr_0 = io_enq_bits_addr; // @[util.scala:448:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[util.scala:448:7] wire io_enq_bits_is_hella_0 = io_enq_bits_is_hella; // @[util.scala:448:7] wire io_enq_bits_tag_match_0 = io_enq_bits_tag_match; // @[util.scala:448:7] wire [1:0] io_enq_bits_old_meta_coh_state_0 = io_enq_bits_old_meta_coh_state; // @[util.scala:448:7] wire [19:0] io_enq_bits_old_meta_tag_0 = io_enq_bits_old_meta_tag; // @[util.scala:448:7] wire [7:0] io_enq_bits_way_en_0 = io_enq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_enq_bits_sdq_id_0 = io_enq_bits_sdq_id; // @[util.scala:448:7] wire io_deq_ready_0 = io_deq_ready; // @[util.scala:448:7] wire [15:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[util.scala:448:7] wire [15:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_uopc_0 = io_brupdate_b2_uop_uopc; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[util.scala:448:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_iq_type_0 = io_brupdate_b2_uop_iq_type; // @[util.scala:448:7] wire [9:0] io_brupdate_b2_uop_fu_code_0 = io_brupdate_b2_uop_fu_code; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_ctrl_br_type_0 = io_brupdate_b2_uop_ctrl_br_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_ctrl_op1_sel_0 = io_brupdate_b2_uop_ctrl_op1_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_op2_sel_0 = io_brupdate_b2_uop_ctrl_op2_sel; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_imm_sel_0 = io_brupdate_b2_uop_ctrl_imm_sel; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ctrl_op_fcn_0 = io_brupdate_b2_uop_ctrl_op_fcn; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_fcn_dw_0 = io_brupdate_b2_uop_ctrl_fcn_dw; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_uop_ctrl_csr_cmd_0 = io_brupdate_b2_uop_ctrl_csr_cmd; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_load_0 = io_brupdate_b2_uop_ctrl_is_load; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_sta_0 = io_brupdate_b2_uop_ctrl_is_sta; // @[util.scala:448:7] wire io_brupdate_b2_uop_ctrl_is_std_0 = io_brupdate_b2_uop_ctrl_is_std; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_iw_state_0 = io_brupdate_b2_uop_iw_state; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p1_poisoned_0 = io_brupdate_b2_uop_iw_p1_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_iw_p2_poisoned_0 = io_brupdate_b2_uop_iw_p2_poisoned; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_br_0 = io_brupdate_b2_uop_is_br; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jalr_0 = io_brupdate_b2_uop_is_jalr; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_jal_0 = io_brupdate_b2_uop_is_jal; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[util.scala:448:7] wire [15:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[util.scala:448:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[util.scala:448:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[util.scala:448:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[util.scala:448:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[util.scala:448:7] wire [11:0] io_brupdate_b2_uop_csr_addr_0 = io_brupdate_b2_uop_csr_addr; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[util.scala:448:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[util.scala:448:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[util.scala:448:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[util.scala:448:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[util.scala:448:7] wire io_brupdate_b2_uop_bypassable_0 = io_brupdate_b2_uop_bypassable; // @[util.scala:448:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[util.scala:448:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[util.scala:448:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[util.scala:448:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[util.scala:448:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[util.scala:448:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[util.scala:448:7] wire io_brupdate_b2_uop_ldst_val_0 = io_brupdate_b2_uop_ldst_val; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[util.scala:448:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[util.scala:448:7] wire io_brupdate_b2_uop_fp_single_0 = io_brupdate_b2_uop_fp_single; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[util.scala:448:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[util.scala:448:7] wire io_brupdate_b2_valid_0 = io_brupdate_b2_valid; // @[util.scala:448:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[util.scala:448:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[util.scala:448:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[util.scala:448:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[util.scala:448:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[util.scala:448:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[util.scala:448:7] wire io_flush_0 = io_flush; // @[util.scala:448:7] wire _valids_WIRE_0 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_1 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_2 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_3 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_4 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_5 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_6 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_7 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_8 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_9 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_10 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_11 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_12 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_13 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_14 = 1'h0; // @[util.scala:465:32] wire _valids_WIRE_15 = 1'h0; // @[util.scala:465:32] wire _io_enq_ready_T; // @[util.scala:504:19] wire _io_deq_valid_T_8; // @[util.scala:509:108] wire [6:0] out_uop_uopc; // @[util.scala:506:17] wire [31:0] out_uop_inst; // @[util.scala:506:17] wire [31:0] out_uop_debug_inst; // @[util.scala:506:17] wire out_uop_is_rvc; // @[util.scala:506:17] wire [39:0] out_uop_debug_pc; // @[util.scala:506:17] wire [2:0] out_uop_iq_type; // @[util.scala:506:17] wire [9:0] out_uop_fu_code; // @[util.scala:506:17] wire [3:0] out_uop_ctrl_br_type; // @[util.scala:506:17] wire [1:0] out_uop_ctrl_op1_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_op2_sel; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_imm_sel; // @[util.scala:506:17] wire [4:0] out_uop_ctrl_op_fcn; // @[util.scala:506:17] wire out_uop_ctrl_fcn_dw; // @[util.scala:506:17] wire [2:0] out_uop_ctrl_csr_cmd; // @[util.scala:506:17] wire out_uop_ctrl_is_load; // @[util.scala:506:17] wire out_uop_ctrl_is_sta; // @[util.scala:506:17] wire out_uop_ctrl_is_std; // @[util.scala:506:17] wire [1:0] out_uop_iw_state; // @[util.scala:506:17] wire out_uop_iw_p1_poisoned; // @[util.scala:506:17] wire out_uop_iw_p2_poisoned; // @[util.scala:506:17] wire out_uop_is_br; // @[util.scala:506:17] wire out_uop_is_jalr; // @[util.scala:506:17] wire out_uop_is_jal; // @[util.scala:506:17] wire out_uop_is_sfb; // @[util.scala:506:17] wire [15:0] _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25] wire [3:0] out_uop_br_tag; // @[util.scala:506:17] wire [4:0] out_uop_ftq_idx; // @[util.scala:506:17] wire out_uop_edge_inst; // @[util.scala:506:17] wire [5:0] out_uop_pc_lob; // @[util.scala:506:17] wire out_uop_taken; // @[util.scala:506:17] wire [19:0] out_uop_imm_packed; // @[util.scala:506:17] wire [11:0] out_uop_csr_addr; // @[util.scala:506:17] wire [6:0] out_uop_rob_idx; // @[util.scala:506:17] wire [4:0] out_uop_ldq_idx; // @[util.scala:506:17] wire [4:0] out_uop_stq_idx; // @[util.scala:506:17] wire [1:0] out_uop_rxq_idx; // @[util.scala:506:17] wire [6:0] out_uop_pdst; // @[util.scala:506:17] wire [6:0] out_uop_prs1; // @[util.scala:506:17] wire [6:0] out_uop_prs2; // @[util.scala:506:17] wire [6:0] out_uop_prs3; // @[util.scala:506:17] wire [4:0] out_uop_ppred; // @[util.scala:506:17] wire out_uop_prs1_busy; // @[util.scala:506:17] wire out_uop_prs2_busy; // @[util.scala:506:17] wire out_uop_prs3_busy; // @[util.scala:506:17] wire out_uop_ppred_busy; // @[util.scala:506:17] wire [6:0] out_uop_stale_pdst; // @[util.scala:506:17] wire out_uop_exception; // @[util.scala:506:17] wire [63:0] out_uop_exc_cause; // @[util.scala:506:17] wire out_uop_bypassable; // @[util.scala:506:17] wire [4:0] out_uop_mem_cmd; // @[util.scala:506:17] wire [1:0] out_uop_mem_size; // @[util.scala:506:17] wire out_uop_mem_signed; // @[util.scala:506:17] wire out_uop_is_fence; // @[util.scala:506:17] wire out_uop_is_fencei; // @[util.scala:506:17] wire out_uop_is_amo; // @[util.scala:506:17] wire out_uop_uses_ldq; // @[util.scala:506:17] wire out_uop_uses_stq; // @[util.scala:506:17] wire out_uop_is_sys_pc2epc; // @[util.scala:506:17] wire out_uop_is_unique; // @[util.scala:506:17] wire out_uop_flush_on_commit; // @[util.scala:506:17] wire out_uop_ldst_is_rs1; // @[util.scala:506:17] wire [5:0] out_uop_ldst; // @[util.scala:506:17] wire [5:0] out_uop_lrs1; // @[util.scala:506:17] wire [5:0] out_uop_lrs2; // @[util.scala:506:17] wire [5:0] out_uop_lrs3; // @[util.scala:506:17] wire out_uop_ldst_val; // @[util.scala:506:17] wire [1:0] out_uop_dst_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs1_rtype; // @[util.scala:506:17] wire [1:0] out_uop_lrs2_rtype; // @[util.scala:506:17] wire out_uop_frs3_en; // @[util.scala:506:17] wire out_uop_fp_val; // @[util.scala:506:17] wire out_uop_fp_single; // @[util.scala:506:17] wire out_uop_xcpt_pf_if; // @[util.scala:506:17] wire out_uop_xcpt_ae_if; // @[util.scala:506:17] wire out_uop_xcpt_ma_if; // @[util.scala:506:17] wire out_uop_bp_debug_if; // @[util.scala:506:17] wire out_uop_bp_xcpt_if; // @[util.scala:506:17] wire [1:0] out_uop_debug_fsrc; // @[util.scala:506:17] wire [1:0] out_uop_debug_tsrc; // @[util.scala:506:17] wire [39:0] out_addr; // @[util.scala:506:17] wire [63:0] out_data; // @[util.scala:506:17] wire out_is_hella; // @[util.scala:506:17] wire out_tag_match; // @[util.scala:506:17] wire [1:0] out_old_meta_coh_state; // @[util.scala:506:17] wire [19:0] out_old_meta_tag; // @[util.scala:506:17] wire [7:0] out_way_en; // @[util.scala:506:17] wire [4:0] out_sdq_id; // @[util.scala:506:17] wire _io_empty_T_1; // @[util.scala:473:25] wire io_enq_ready_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] wire io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_uopc_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_inst_0; // @[util.scala:448:7] wire [31:0] io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] wire [2:0] io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] wire [9:0] io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_br_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] wire [15:0] io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] wire [3:0] io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] wire io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] wire io_deq_bits_uop_taken_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] wire [11:0] io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_pdst_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs1_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs2_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_prs3_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_ppred_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] wire io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] wire [6:0] io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] wire io_deq_bits_uop_exception_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] wire io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] wire [4:0] io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] wire io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] wire io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] wire io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] wire io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_ldst_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] wire [5:0] io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] wire io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] wire io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] wire io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] wire io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] wire [1:0] io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] wire [19:0] io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] wire [39:0] io_deq_bits_addr_0; // @[util.scala:448:7] wire [63:0] io_deq_bits_data_0; // @[util.scala:448:7] wire io_deq_bits_is_hella_0; // @[util.scala:448:7] wire io_deq_bits_tag_match_0; // @[util.scala:448:7] wire [7:0] io_deq_bits_way_en; // @[util.scala:448:7] wire [4:0] io_deq_bits_sdq_id_0; // @[util.scala:448:7] wire io_deq_valid_0; // @[util.scala:448:7] wire io_empty_0; // @[util.scala:448:7] wire [3:0] io_count; // @[util.scala:448:7] assign out_addr = _ram_ext_R0_data[39:0]; // @[util.scala:464:20, :506:17] assign out_data = _ram_ext_R0_data[103:40]; // @[util.scala:464:20, :506:17] assign out_is_hella = _ram_ext_R0_data[104]; // @[util.scala:464:20, :506:17] assign out_tag_match = _ram_ext_R0_data[105]; // @[util.scala:464:20, :506:17] assign out_old_meta_coh_state = _ram_ext_R0_data[107:106]; // @[util.scala:464:20, :506:17] assign out_old_meta_tag = _ram_ext_R0_data[127:108]; // @[util.scala:464:20, :506:17] assign out_way_en = _ram_ext_R0_data[135:128]; // @[util.scala:464:20, :506:17] assign out_sdq_id = _ram_ext_R0_data[140:136]; // @[util.scala:464:20, :506:17] reg valids_0; // @[util.scala:465:24] reg valids_1; // @[util.scala:465:24] reg valids_2; // @[util.scala:465:24] reg valids_3; // @[util.scala:465:24] reg valids_4; // @[util.scala:465:24] reg valids_5; // @[util.scala:465:24] reg valids_6; // @[util.scala:465:24] reg valids_7; // @[util.scala:465:24] reg valids_8; // @[util.scala:465:24] reg valids_9; // @[util.scala:465:24] reg valids_10; // @[util.scala:465:24] reg valids_11; // @[util.scala:465:24] reg valids_12; // @[util.scala:465:24] reg valids_13; // @[util.scala:465:24] reg valids_14; // @[util.scala:465:24] reg valids_15; // @[util.scala:465:24] reg [6:0] uops_0_uopc; // @[util.scala:466:20] reg [31:0] uops_0_inst; // @[util.scala:466:20] reg [31:0] uops_0_debug_inst; // @[util.scala:466:20] reg uops_0_is_rvc; // @[util.scala:466:20] reg [39:0] uops_0_debug_pc; // @[util.scala:466:20] reg [2:0] uops_0_iq_type; // @[util.scala:466:20] reg [9:0] uops_0_fu_code; // @[util.scala:466:20] reg [3:0] uops_0_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_0_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_0_ctrl_op_fcn; // @[util.scala:466:20] reg uops_0_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_0_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_0_ctrl_is_load; // @[util.scala:466:20] reg uops_0_ctrl_is_sta; // @[util.scala:466:20] reg uops_0_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_0_iw_state; // @[util.scala:466:20] reg uops_0_iw_p1_poisoned; // @[util.scala:466:20] reg uops_0_iw_p2_poisoned; // @[util.scala:466:20] reg uops_0_is_br; // @[util.scala:466:20] reg uops_0_is_jalr; // @[util.scala:466:20] reg uops_0_is_jal; // @[util.scala:466:20] reg uops_0_is_sfb; // @[util.scala:466:20] reg [15:0] uops_0_br_mask; // @[util.scala:466:20] reg [3:0] uops_0_br_tag; // @[util.scala:466:20] reg [4:0] uops_0_ftq_idx; // @[util.scala:466:20] reg uops_0_edge_inst; // @[util.scala:466:20] reg [5:0] uops_0_pc_lob; // @[util.scala:466:20] reg uops_0_taken; // @[util.scala:466:20] reg [19:0] uops_0_imm_packed; // @[util.scala:466:20] reg [11:0] uops_0_csr_addr; // @[util.scala:466:20] reg [6:0] uops_0_rob_idx; // @[util.scala:466:20] reg [4:0] uops_0_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_0_stq_idx; // @[util.scala:466:20] reg [1:0] uops_0_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_0_pdst; // @[util.scala:466:20] reg [6:0] uops_0_prs1; // @[util.scala:466:20] reg [6:0] uops_0_prs2; // @[util.scala:466:20] reg [6:0] uops_0_prs3; // @[util.scala:466:20] reg [4:0] uops_0_ppred; // @[util.scala:466:20] reg uops_0_prs1_busy; // @[util.scala:466:20] reg uops_0_prs2_busy; // @[util.scala:466:20] reg uops_0_prs3_busy; // @[util.scala:466:20] reg uops_0_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_0_stale_pdst; // @[util.scala:466:20] reg uops_0_exception; // @[util.scala:466:20] reg [63:0] uops_0_exc_cause; // @[util.scala:466:20] reg uops_0_bypassable; // @[util.scala:466:20] reg [4:0] uops_0_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_0_mem_size; // @[util.scala:466:20] reg uops_0_mem_signed; // @[util.scala:466:20] reg uops_0_is_fence; // @[util.scala:466:20] reg uops_0_is_fencei; // @[util.scala:466:20] reg uops_0_is_amo; // @[util.scala:466:20] reg uops_0_uses_ldq; // @[util.scala:466:20] reg uops_0_uses_stq; // @[util.scala:466:20] reg uops_0_is_sys_pc2epc; // @[util.scala:466:20] reg uops_0_is_unique; // @[util.scala:466:20] reg uops_0_flush_on_commit; // @[util.scala:466:20] reg uops_0_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_0_ldst; // @[util.scala:466:20] reg [5:0] uops_0_lrs1; // @[util.scala:466:20] reg [5:0] uops_0_lrs2; // @[util.scala:466:20] reg [5:0] uops_0_lrs3; // @[util.scala:466:20] reg uops_0_ldst_val; // @[util.scala:466:20] reg [1:0] uops_0_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_0_lrs2_rtype; // @[util.scala:466:20] reg uops_0_frs3_en; // @[util.scala:466:20] reg uops_0_fp_val; // @[util.scala:466:20] reg uops_0_fp_single; // @[util.scala:466:20] reg uops_0_xcpt_pf_if; // @[util.scala:466:20] reg uops_0_xcpt_ae_if; // @[util.scala:466:20] reg uops_0_xcpt_ma_if; // @[util.scala:466:20] reg uops_0_bp_debug_if; // @[util.scala:466:20] reg uops_0_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_0_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_0_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_1_uopc; // @[util.scala:466:20] reg [31:0] uops_1_inst; // @[util.scala:466:20] reg [31:0] uops_1_debug_inst; // @[util.scala:466:20] reg uops_1_is_rvc; // @[util.scala:466:20] reg [39:0] uops_1_debug_pc; // @[util.scala:466:20] reg [2:0] uops_1_iq_type; // @[util.scala:466:20] reg [9:0] uops_1_fu_code; // @[util.scala:466:20] reg [3:0] uops_1_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_1_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_1_ctrl_op_fcn; // @[util.scala:466:20] reg uops_1_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_1_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_1_ctrl_is_load; // @[util.scala:466:20] reg uops_1_ctrl_is_sta; // @[util.scala:466:20] reg uops_1_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_1_iw_state; // @[util.scala:466:20] reg uops_1_iw_p1_poisoned; // @[util.scala:466:20] reg uops_1_iw_p2_poisoned; // @[util.scala:466:20] reg uops_1_is_br; // @[util.scala:466:20] reg uops_1_is_jalr; // @[util.scala:466:20] reg uops_1_is_jal; // @[util.scala:466:20] reg uops_1_is_sfb; // @[util.scala:466:20] reg [15:0] uops_1_br_mask; // @[util.scala:466:20] reg [3:0] uops_1_br_tag; // @[util.scala:466:20] reg [4:0] uops_1_ftq_idx; // @[util.scala:466:20] reg uops_1_edge_inst; // @[util.scala:466:20] reg [5:0] uops_1_pc_lob; // @[util.scala:466:20] reg uops_1_taken; // @[util.scala:466:20] reg [19:0] uops_1_imm_packed; // @[util.scala:466:20] reg [11:0] uops_1_csr_addr; // @[util.scala:466:20] reg [6:0] uops_1_rob_idx; // @[util.scala:466:20] reg [4:0] uops_1_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_1_stq_idx; // @[util.scala:466:20] reg [1:0] uops_1_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_1_pdst; // @[util.scala:466:20] reg [6:0] uops_1_prs1; // @[util.scala:466:20] reg [6:0] uops_1_prs2; // @[util.scala:466:20] reg [6:0] uops_1_prs3; // @[util.scala:466:20] reg [4:0] uops_1_ppred; // @[util.scala:466:20] reg uops_1_prs1_busy; // @[util.scala:466:20] reg uops_1_prs2_busy; // @[util.scala:466:20] reg uops_1_prs3_busy; // @[util.scala:466:20] reg uops_1_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_1_stale_pdst; // @[util.scala:466:20] reg uops_1_exception; // @[util.scala:466:20] reg [63:0] uops_1_exc_cause; // @[util.scala:466:20] reg uops_1_bypassable; // @[util.scala:466:20] reg [4:0] uops_1_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_1_mem_size; // @[util.scala:466:20] reg uops_1_mem_signed; // @[util.scala:466:20] reg uops_1_is_fence; // @[util.scala:466:20] reg uops_1_is_fencei; // @[util.scala:466:20] reg uops_1_is_amo; // @[util.scala:466:20] reg uops_1_uses_ldq; // @[util.scala:466:20] reg uops_1_uses_stq; // @[util.scala:466:20] reg uops_1_is_sys_pc2epc; // @[util.scala:466:20] reg uops_1_is_unique; // @[util.scala:466:20] reg uops_1_flush_on_commit; // @[util.scala:466:20] reg uops_1_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_1_ldst; // @[util.scala:466:20] reg [5:0] uops_1_lrs1; // @[util.scala:466:20] reg [5:0] uops_1_lrs2; // @[util.scala:466:20] reg [5:0] uops_1_lrs3; // @[util.scala:466:20] reg uops_1_ldst_val; // @[util.scala:466:20] reg [1:0] uops_1_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_1_lrs2_rtype; // @[util.scala:466:20] reg uops_1_frs3_en; // @[util.scala:466:20] reg uops_1_fp_val; // @[util.scala:466:20] reg uops_1_fp_single; // @[util.scala:466:20] reg uops_1_xcpt_pf_if; // @[util.scala:466:20] reg uops_1_xcpt_ae_if; // @[util.scala:466:20] reg uops_1_xcpt_ma_if; // @[util.scala:466:20] reg uops_1_bp_debug_if; // @[util.scala:466:20] reg uops_1_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_1_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_1_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_2_uopc; // @[util.scala:466:20] reg [31:0] uops_2_inst; // @[util.scala:466:20] reg [31:0] uops_2_debug_inst; // @[util.scala:466:20] reg uops_2_is_rvc; // @[util.scala:466:20] reg [39:0] uops_2_debug_pc; // @[util.scala:466:20] reg [2:0] uops_2_iq_type; // @[util.scala:466:20] reg [9:0] uops_2_fu_code; // @[util.scala:466:20] reg [3:0] uops_2_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_2_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_2_ctrl_op_fcn; // @[util.scala:466:20] reg uops_2_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_2_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_2_ctrl_is_load; // @[util.scala:466:20] reg uops_2_ctrl_is_sta; // @[util.scala:466:20] reg uops_2_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_2_iw_state; // @[util.scala:466:20] reg uops_2_iw_p1_poisoned; // @[util.scala:466:20] reg uops_2_iw_p2_poisoned; // @[util.scala:466:20] reg uops_2_is_br; // @[util.scala:466:20] reg uops_2_is_jalr; // @[util.scala:466:20] reg uops_2_is_jal; // @[util.scala:466:20] reg uops_2_is_sfb; // @[util.scala:466:20] reg [15:0] uops_2_br_mask; // @[util.scala:466:20] reg [3:0] uops_2_br_tag; // @[util.scala:466:20] reg [4:0] uops_2_ftq_idx; // @[util.scala:466:20] reg uops_2_edge_inst; // @[util.scala:466:20] reg [5:0] uops_2_pc_lob; // @[util.scala:466:20] reg uops_2_taken; // @[util.scala:466:20] reg [19:0] uops_2_imm_packed; // @[util.scala:466:20] reg [11:0] uops_2_csr_addr; // @[util.scala:466:20] reg [6:0] uops_2_rob_idx; // @[util.scala:466:20] reg [4:0] uops_2_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_2_stq_idx; // @[util.scala:466:20] reg [1:0] uops_2_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_2_pdst; // @[util.scala:466:20] reg [6:0] uops_2_prs1; // @[util.scala:466:20] reg [6:0] uops_2_prs2; // @[util.scala:466:20] reg [6:0] uops_2_prs3; // @[util.scala:466:20] reg [4:0] uops_2_ppred; // @[util.scala:466:20] reg uops_2_prs1_busy; // @[util.scala:466:20] reg uops_2_prs2_busy; // @[util.scala:466:20] reg uops_2_prs3_busy; // @[util.scala:466:20] reg uops_2_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_2_stale_pdst; // @[util.scala:466:20] reg uops_2_exception; // @[util.scala:466:20] reg [63:0] uops_2_exc_cause; // @[util.scala:466:20] reg uops_2_bypassable; // @[util.scala:466:20] reg [4:0] uops_2_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_2_mem_size; // @[util.scala:466:20] reg uops_2_mem_signed; // @[util.scala:466:20] reg uops_2_is_fence; // @[util.scala:466:20] reg uops_2_is_fencei; // @[util.scala:466:20] reg uops_2_is_amo; // @[util.scala:466:20] reg uops_2_uses_ldq; // @[util.scala:466:20] reg uops_2_uses_stq; // @[util.scala:466:20] reg uops_2_is_sys_pc2epc; // @[util.scala:466:20] reg uops_2_is_unique; // @[util.scala:466:20] reg uops_2_flush_on_commit; // @[util.scala:466:20] reg uops_2_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_2_ldst; // @[util.scala:466:20] reg [5:0] uops_2_lrs1; // @[util.scala:466:20] reg [5:0] uops_2_lrs2; // @[util.scala:466:20] reg [5:0] uops_2_lrs3; // @[util.scala:466:20] reg uops_2_ldst_val; // @[util.scala:466:20] reg [1:0] uops_2_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_2_lrs2_rtype; // @[util.scala:466:20] reg uops_2_frs3_en; // @[util.scala:466:20] reg uops_2_fp_val; // @[util.scala:466:20] reg uops_2_fp_single; // @[util.scala:466:20] reg uops_2_xcpt_pf_if; // @[util.scala:466:20] reg uops_2_xcpt_ae_if; // @[util.scala:466:20] reg uops_2_xcpt_ma_if; // @[util.scala:466:20] reg uops_2_bp_debug_if; // @[util.scala:466:20] reg uops_2_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_2_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_2_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_3_uopc; // @[util.scala:466:20] reg [31:0] uops_3_inst; // @[util.scala:466:20] reg [31:0] uops_3_debug_inst; // @[util.scala:466:20] reg uops_3_is_rvc; // @[util.scala:466:20] reg [39:0] uops_3_debug_pc; // @[util.scala:466:20] reg [2:0] uops_3_iq_type; // @[util.scala:466:20] reg [9:0] uops_3_fu_code; // @[util.scala:466:20] reg [3:0] uops_3_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_3_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_3_ctrl_op_fcn; // @[util.scala:466:20] reg uops_3_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_3_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_3_ctrl_is_load; // @[util.scala:466:20] reg uops_3_ctrl_is_sta; // @[util.scala:466:20] reg uops_3_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_3_iw_state; // @[util.scala:466:20] reg uops_3_iw_p1_poisoned; // @[util.scala:466:20] reg uops_3_iw_p2_poisoned; // @[util.scala:466:20] reg uops_3_is_br; // @[util.scala:466:20] reg uops_3_is_jalr; // @[util.scala:466:20] reg uops_3_is_jal; // @[util.scala:466:20] reg uops_3_is_sfb; // @[util.scala:466:20] reg [15:0] uops_3_br_mask; // @[util.scala:466:20] reg [3:0] uops_3_br_tag; // @[util.scala:466:20] reg [4:0] uops_3_ftq_idx; // @[util.scala:466:20] reg uops_3_edge_inst; // @[util.scala:466:20] reg [5:0] uops_3_pc_lob; // @[util.scala:466:20] reg uops_3_taken; // @[util.scala:466:20] reg [19:0] uops_3_imm_packed; // @[util.scala:466:20] reg [11:0] uops_3_csr_addr; // @[util.scala:466:20] reg [6:0] uops_3_rob_idx; // @[util.scala:466:20] reg [4:0] uops_3_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_3_stq_idx; // @[util.scala:466:20] reg [1:0] uops_3_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_3_pdst; // @[util.scala:466:20] reg [6:0] uops_3_prs1; // @[util.scala:466:20] reg [6:0] uops_3_prs2; // @[util.scala:466:20] reg [6:0] uops_3_prs3; // @[util.scala:466:20] reg [4:0] uops_3_ppred; // @[util.scala:466:20] reg uops_3_prs1_busy; // @[util.scala:466:20] reg uops_3_prs2_busy; // @[util.scala:466:20] reg uops_3_prs3_busy; // @[util.scala:466:20] reg uops_3_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_3_stale_pdst; // @[util.scala:466:20] reg uops_3_exception; // @[util.scala:466:20] reg [63:0] uops_3_exc_cause; // @[util.scala:466:20] reg uops_3_bypassable; // @[util.scala:466:20] reg [4:0] uops_3_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_3_mem_size; // @[util.scala:466:20] reg uops_3_mem_signed; // @[util.scala:466:20] reg uops_3_is_fence; // @[util.scala:466:20] reg uops_3_is_fencei; // @[util.scala:466:20] reg uops_3_is_amo; // @[util.scala:466:20] reg uops_3_uses_ldq; // @[util.scala:466:20] reg uops_3_uses_stq; // @[util.scala:466:20] reg uops_3_is_sys_pc2epc; // @[util.scala:466:20] reg uops_3_is_unique; // @[util.scala:466:20] reg uops_3_flush_on_commit; // @[util.scala:466:20] reg uops_3_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_3_ldst; // @[util.scala:466:20] reg [5:0] uops_3_lrs1; // @[util.scala:466:20] reg [5:0] uops_3_lrs2; // @[util.scala:466:20] reg [5:0] uops_3_lrs3; // @[util.scala:466:20] reg uops_3_ldst_val; // @[util.scala:466:20] reg [1:0] uops_3_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_3_lrs2_rtype; // @[util.scala:466:20] reg uops_3_frs3_en; // @[util.scala:466:20] reg uops_3_fp_val; // @[util.scala:466:20] reg uops_3_fp_single; // @[util.scala:466:20] reg uops_3_xcpt_pf_if; // @[util.scala:466:20] reg uops_3_xcpt_ae_if; // @[util.scala:466:20] reg uops_3_xcpt_ma_if; // @[util.scala:466:20] reg uops_3_bp_debug_if; // @[util.scala:466:20] reg uops_3_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_3_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_3_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_4_uopc; // @[util.scala:466:20] reg [31:0] uops_4_inst; // @[util.scala:466:20] reg [31:0] uops_4_debug_inst; // @[util.scala:466:20] reg uops_4_is_rvc; // @[util.scala:466:20] reg [39:0] uops_4_debug_pc; // @[util.scala:466:20] reg [2:0] uops_4_iq_type; // @[util.scala:466:20] reg [9:0] uops_4_fu_code; // @[util.scala:466:20] reg [3:0] uops_4_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_4_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_4_ctrl_op_fcn; // @[util.scala:466:20] reg uops_4_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_4_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_4_ctrl_is_load; // @[util.scala:466:20] reg uops_4_ctrl_is_sta; // @[util.scala:466:20] reg uops_4_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_4_iw_state; // @[util.scala:466:20] reg uops_4_iw_p1_poisoned; // @[util.scala:466:20] reg uops_4_iw_p2_poisoned; // @[util.scala:466:20] reg uops_4_is_br; // @[util.scala:466:20] reg uops_4_is_jalr; // @[util.scala:466:20] reg uops_4_is_jal; // @[util.scala:466:20] reg uops_4_is_sfb; // @[util.scala:466:20] reg [15:0] uops_4_br_mask; // @[util.scala:466:20] reg [3:0] uops_4_br_tag; // @[util.scala:466:20] reg [4:0] uops_4_ftq_idx; // @[util.scala:466:20] reg uops_4_edge_inst; // @[util.scala:466:20] reg [5:0] uops_4_pc_lob; // @[util.scala:466:20] reg uops_4_taken; // @[util.scala:466:20] reg [19:0] uops_4_imm_packed; // @[util.scala:466:20] reg [11:0] uops_4_csr_addr; // @[util.scala:466:20] reg [6:0] uops_4_rob_idx; // @[util.scala:466:20] reg [4:0] uops_4_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_4_stq_idx; // @[util.scala:466:20] reg [1:0] uops_4_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_4_pdst; // @[util.scala:466:20] reg [6:0] uops_4_prs1; // @[util.scala:466:20] reg [6:0] uops_4_prs2; // @[util.scala:466:20] reg [6:0] uops_4_prs3; // @[util.scala:466:20] reg [4:0] uops_4_ppred; // @[util.scala:466:20] reg uops_4_prs1_busy; // @[util.scala:466:20] reg uops_4_prs2_busy; // @[util.scala:466:20] reg uops_4_prs3_busy; // @[util.scala:466:20] reg uops_4_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_4_stale_pdst; // @[util.scala:466:20] reg uops_4_exception; // @[util.scala:466:20] reg [63:0] uops_4_exc_cause; // @[util.scala:466:20] reg uops_4_bypassable; // @[util.scala:466:20] reg [4:0] uops_4_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_4_mem_size; // @[util.scala:466:20] reg uops_4_mem_signed; // @[util.scala:466:20] reg uops_4_is_fence; // @[util.scala:466:20] reg uops_4_is_fencei; // @[util.scala:466:20] reg uops_4_is_amo; // @[util.scala:466:20] reg uops_4_uses_ldq; // @[util.scala:466:20] reg uops_4_uses_stq; // @[util.scala:466:20] reg uops_4_is_sys_pc2epc; // @[util.scala:466:20] reg uops_4_is_unique; // @[util.scala:466:20] reg uops_4_flush_on_commit; // @[util.scala:466:20] reg uops_4_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_4_ldst; // @[util.scala:466:20] reg [5:0] uops_4_lrs1; // @[util.scala:466:20] reg [5:0] uops_4_lrs2; // @[util.scala:466:20] reg [5:0] uops_4_lrs3; // @[util.scala:466:20] reg uops_4_ldst_val; // @[util.scala:466:20] reg [1:0] uops_4_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_4_lrs2_rtype; // @[util.scala:466:20] reg uops_4_frs3_en; // @[util.scala:466:20] reg uops_4_fp_val; // @[util.scala:466:20] reg uops_4_fp_single; // @[util.scala:466:20] reg uops_4_xcpt_pf_if; // @[util.scala:466:20] reg uops_4_xcpt_ae_if; // @[util.scala:466:20] reg uops_4_xcpt_ma_if; // @[util.scala:466:20] reg uops_4_bp_debug_if; // @[util.scala:466:20] reg uops_4_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_4_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_4_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_5_uopc; // @[util.scala:466:20] reg [31:0] uops_5_inst; // @[util.scala:466:20] reg [31:0] uops_5_debug_inst; // @[util.scala:466:20] reg uops_5_is_rvc; // @[util.scala:466:20] reg [39:0] uops_5_debug_pc; // @[util.scala:466:20] reg [2:0] uops_5_iq_type; // @[util.scala:466:20] reg [9:0] uops_5_fu_code; // @[util.scala:466:20] reg [3:0] uops_5_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_5_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_5_ctrl_op_fcn; // @[util.scala:466:20] reg uops_5_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_5_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_5_ctrl_is_load; // @[util.scala:466:20] reg uops_5_ctrl_is_sta; // @[util.scala:466:20] reg uops_5_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_5_iw_state; // @[util.scala:466:20] reg uops_5_iw_p1_poisoned; // @[util.scala:466:20] reg uops_5_iw_p2_poisoned; // @[util.scala:466:20] reg uops_5_is_br; // @[util.scala:466:20] reg uops_5_is_jalr; // @[util.scala:466:20] reg uops_5_is_jal; // @[util.scala:466:20] reg uops_5_is_sfb; // @[util.scala:466:20] reg [15:0] uops_5_br_mask; // @[util.scala:466:20] reg [3:0] uops_5_br_tag; // @[util.scala:466:20] reg [4:0] uops_5_ftq_idx; // @[util.scala:466:20] reg uops_5_edge_inst; // @[util.scala:466:20] reg [5:0] uops_5_pc_lob; // @[util.scala:466:20] reg uops_5_taken; // @[util.scala:466:20] reg [19:0] uops_5_imm_packed; // @[util.scala:466:20] reg [11:0] uops_5_csr_addr; // @[util.scala:466:20] reg [6:0] uops_5_rob_idx; // @[util.scala:466:20] reg [4:0] uops_5_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_5_stq_idx; // @[util.scala:466:20] reg [1:0] uops_5_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_5_pdst; // @[util.scala:466:20] reg [6:0] uops_5_prs1; // @[util.scala:466:20] reg [6:0] uops_5_prs2; // @[util.scala:466:20] reg [6:0] uops_5_prs3; // @[util.scala:466:20] reg [4:0] uops_5_ppred; // @[util.scala:466:20] reg uops_5_prs1_busy; // @[util.scala:466:20] reg uops_5_prs2_busy; // @[util.scala:466:20] reg uops_5_prs3_busy; // @[util.scala:466:20] reg uops_5_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_5_stale_pdst; // @[util.scala:466:20] reg uops_5_exception; // @[util.scala:466:20] reg [63:0] uops_5_exc_cause; // @[util.scala:466:20] reg uops_5_bypassable; // @[util.scala:466:20] reg [4:0] uops_5_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_5_mem_size; // @[util.scala:466:20] reg uops_5_mem_signed; // @[util.scala:466:20] reg uops_5_is_fence; // @[util.scala:466:20] reg uops_5_is_fencei; // @[util.scala:466:20] reg uops_5_is_amo; // @[util.scala:466:20] reg uops_5_uses_ldq; // @[util.scala:466:20] reg uops_5_uses_stq; // @[util.scala:466:20] reg uops_5_is_sys_pc2epc; // @[util.scala:466:20] reg uops_5_is_unique; // @[util.scala:466:20] reg uops_5_flush_on_commit; // @[util.scala:466:20] reg uops_5_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_5_ldst; // @[util.scala:466:20] reg [5:0] uops_5_lrs1; // @[util.scala:466:20] reg [5:0] uops_5_lrs2; // @[util.scala:466:20] reg [5:0] uops_5_lrs3; // @[util.scala:466:20] reg uops_5_ldst_val; // @[util.scala:466:20] reg [1:0] uops_5_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_5_lrs2_rtype; // @[util.scala:466:20] reg uops_5_frs3_en; // @[util.scala:466:20] reg uops_5_fp_val; // @[util.scala:466:20] reg uops_5_fp_single; // @[util.scala:466:20] reg uops_5_xcpt_pf_if; // @[util.scala:466:20] reg uops_5_xcpt_ae_if; // @[util.scala:466:20] reg uops_5_xcpt_ma_if; // @[util.scala:466:20] reg uops_5_bp_debug_if; // @[util.scala:466:20] reg uops_5_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_5_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_5_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_6_uopc; // @[util.scala:466:20] reg [31:0] uops_6_inst; // @[util.scala:466:20] reg [31:0] uops_6_debug_inst; // @[util.scala:466:20] reg uops_6_is_rvc; // @[util.scala:466:20] reg [39:0] uops_6_debug_pc; // @[util.scala:466:20] reg [2:0] uops_6_iq_type; // @[util.scala:466:20] reg [9:0] uops_6_fu_code; // @[util.scala:466:20] reg [3:0] uops_6_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_6_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_6_ctrl_op_fcn; // @[util.scala:466:20] reg uops_6_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_6_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_6_ctrl_is_load; // @[util.scala:466:20] reg uops_6_ctrl_is_sta; // @[util.scala:466:20] reg uops_6_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_6_iw_state; // @[util.scala:466:20] reg uops_6_iw_p1_poisoned; // @[util.scala:466:20] reg uops_6_iw_p2_poisoned; // @[util.scala:466:20] reg uops_6_is_br; // @[util.scala:466:20] reg uops_6_is_jalr; // @[util.scala:466:20] reg uops_6_is_jal; // @[util.scala:466:20] reg uops_6_is_sfb; // @[util.scala:466:20] reg [15:0] uops_6_br_mask; // @[util.scala:466:20] reg [3:0] uops_6_br_tag; // @[util.scala:466:20] reg [4:0] uops_6_ftq_idx; // @[util.scala:466:20] reg uops_6_edge_inst; // @[util.scala:466:20] reg [5:0] uops_6_pc_lob; // @[util.scala:466:20] reg uops_6_taken; // @[util.scala:466:20] reg [19:0] uops_6_imm_packed; // @[util.scala:466:20] reg [11:0] uops_6_csr_addr; // @[util.scala:466:20] reg [6:0] uops_6_rob_idx; // @[util.scala:466:20] reg [4:0] uops_6_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_6_stq_idx; // @[util.scala:466:20] reg [1:0] uops_6_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_6_pdst; // @[util.scala:466:20] reg [6:0] uops_6_prs1; // @[util.scala:466:20] reg [6:0] uops_6_prs2; // @[util.scala:466:20] reg [6:0] uops_6_prs3; // @[util.scala:466:20] reg [4:0] uops_6_ppred; // @[util.scala:466:20] reg uops_6_prs1_busy; // @[util.scala:466:20] reg uops_6_prs2_busy; // @[util.scala:466:20] reg uops_6_prs3_busy; // @[util.scala:466:20] reg uops_6_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_6_stale_pdst; // @[util.scala:466:20] reg uops_6_exception; // @[util.scala:466:20] reg [63:0] uops_6_exc_cause; // @[util.scala:466:20] reg uops_6_bypassable; // @[util.scala:466:20] reg [4:0] uops_6_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_6_mem_size; // @[util.scala:466:20] reg uops_6_mem_signed; // @[util.scala:466:20] reg uops_6_is_fence; // @[util.scala:466:20] reg uops_6_is_fencei; // @[util.scala:466:20] reg uops_6_is_amo; // @[util.scala:466:20] reg uops_6_uses_ldq; // @[util.scala:466:20] reg uops_6_uses_stq; // @[util.scala:466:20] reg uops_6_is_sys_pc2epc; // @[util.scala:466:20] reg uops_6_is_unique; // @[util.scala:466:20] reg uops_6_flush_on_commit; // @[util.scala:466:20] reg uops_6_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_6_ldst; // @[util.scala:466:20] reg [5:0] uops_6_lrs1; // @[util.scala:466:20] reg [5:0] uops_6_lrs2; // @[util.scala:466:20] reg [5:0] uops_6_lrs3; // @[util.scala:466:20] reg uops_6_ldst_val; // @[util.scala:466:20] reg [1:0] uops_6_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_6_lrs2_rtype; // @[util.scala:466:20] reg uops_6_frs3_en; // @[util.scala:466:20] reg uops_6_fp_val; // @[util.scala:466:20] reg uops_6_fp_single; // @[util.scala:466:20] reg uops_6_xcpt_pf_if; // @[util.scala:466:20] reg uops_6_xcpt_ae_if; // @[util.scala:466:20] reg uops_6_xcpt_ma_if; // @[util.scala:466:20] reg uops_6_bp_debug_if; // @[util.scala:466:20] reg uops_6_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_6_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_6_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_7_uopc; // @[util.scala:466:20] reg [31:0] uops_7_inst; // @[util.scala:466:20] reg [31:0] uops_7_debug_inst; // @[util.scala:466:20] reg uops_7_is_rvc; // @[util.scala:466:20] reg [39:0] uops_7_debug_pc; // @[util.scala:466:20] reg [2:0] uops_7_iq_type; // @[util.scala:466:20] reg [9:0] uops_7_fu_code; // @[util.scala:466:20] reg [3:0] uops_7_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_7_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_7_ctrl_op_fcn; // @[util.scala:466:20] reg uops_7_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_7_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_7_ctrl_is_load; // @[util.scala:466:20] reg uops_7_ctrl_is_sta; // @[util.scala:466:20] reg uops_7_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_7_iw_state; // @[util.scala:466:20] reg uops_7_iw_p1_poisoned; // @[util.scala:466:20] reg uops_7_iw_p2_poisoned; // @[util.scala:466:20] reg uops_7_is_br; // @[util.scala:466:20] reg uops_7_is_jalr; // @[util.scala:466:20] reg uops_7_is_jal; // @[util.scala:466:20] reg uops_7_is_sfb; // @[util.scala:466:20] reg [15:0] uops_7_br_mask; // @[util.scala:466:20] reg [3:0] uops_7_br_tag; // @[util.scala:466:20] reg [4:0] uops_7_ftq_idx; // @[util.scala:466:20] reg uops_7_edge_inst; // @[util.scala:466:20] reg [5:0] uops_7_pc_lob; // @[util.scala:466:20] reg uops_7_taken; // @[util.scala:466:20] reg [19:0] uops_7_imm_packed; // @[util.scala:466:20] reg [11:0] uops_7_csr_addr; // @[util.scala:466:20] reg [6:0] uops_7_rob_idx; // @[util.scala:466:20] reg [4:0] uops_7_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_7_stq_idx; // @[util.scala:466:20] reg [1:0] uops_7_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_7_pdst; // @[util.scala:466:20] reg [6:0] uops_7_prs1; // @[util.scala:466:20] reg [6:0] uops_7_prs2; // @[util.scala:466:20] reg [6:0] uops_7_prs3; // @[util.scala:466:20] reg [4:0] uops_7_ppred; // @[util.scala:466:20] reg uops_7_prs1_busy; // @[util.scala:466:20] reg uops_7_prs2_busy; // @[util.scala:466:20] reg uops_7_prs3_busy; // @[util.scala:466:20] reg uops_7_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_7_stale_pdst; // @[util.scala:466:20] reg uops_7_exception; // @[util.scala:466:20] reg [63:0] uops_7_exc_cause; // @[util.scala:466:20] reg uops_7_bypassable; // @[util.scala:466:20] reg [4:0] uops_7_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_7_mem_size; // @[util.scala:466:20] reg uops_7_mem_signed; // @[util.scala:466:20] reg uops_7_is_fence; // @[util.scala:466:20] reg uops_7_is_fencei; // @[util.scala:466:20] reg uops_7_is_amo; // @[util.scala:466:20] reg uops_7_uses_ldq; // @[util.scala:466:20] reg uops_7_uses_stq; // @[util.scala:466:20] reg uops_7_is_sys_pc2epc; // @[util.scala:466:20] reg uops_7_is_unique; // @[util.scala:466:20] reg uops_7_flush_on_commit; // @[util.scala:466:20] reg uops_7_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_7_ldst; // @[util.scala:466:20] reg [5:0] uops_7_lrs1; // @[util.scala:466:20] reg [5:0] uops_7_lrs2; // @[util.scala:466:20] reg [5:0] uops_7_lrs3; // @[util.scala:466:20] reg uops_7_ldst_val; // @[util.scala:466:20] reg [1:0] uops_7_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_7_lrs2_rtype; // @[util.scala:466:20] reg uops_7_frs3_en; // @[util.scala:466:20] reg uops_7_fp_val; // @[util.scala:466:20] reg uops_7_fp_single; // @[util.scala:466:20] reg uops_7_xcpt_pf_if; // @[util.scala:466:20] reg uops_7_xcpt_ae_if; // @[util.scala:466:20] reg uops_7_xcpt_ma_if; // @[util.scala:466:20] reg uops_7_bp_debug_if; // @[util.scala:466:20] reg uops_7_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_7_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_7_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_8_uopc; // @[util.scala:466:20] reg [31:0] uops_8_inst; // @[util.scala:466:20] reg [31:0] uops_8_debug_inst; // @[util.scala:466:20] reg uops_8_is_rvc; // @[util.scala:466:20] reg [39:0] uops_8_debug_pc; // @[util.scala:466:20] reg [2:0] uops_8_iq_type; // @[util.scala:466:20] reg [9:0] uops_8_fu_code; // @[util.scala:466:20] reg [3:0] uops_8_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_8_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_8_ctrl_op_fcn; // @[util.scala:466:20] reg uops_8_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_8_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_8_ctrl_is_load; // @[util.scala:466:20] reg uops_8_ctrl_is_sta; // @[util.scala:466:20] reg uops_8_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_8_iw_state; // @[util.scala:466:20] reg uops_8_iw_p1_poisoned; // @[util.scala:466:20] reg uops_8_iw_p2_poisoned; // @[util.scala:466:20] reg uops_8_is_br; // @[util.scala:466:20] reg uops_8_is_jalr; // @[util.scala:466:20] reg uops_8_is_jal; // @[util.scala:466:20] reg uops_8_is_sfb; // @[util.scala:466:20] reg [15:0] uops_8_br_mask; // @[util.scala:466:20] reg [3:0] uops_8_br_tag; // @[util.scala:466:20] reg [4:0] uops_8_ftq_idx; // @[util.scala:466:20] reg uops_8_edge_inst; // @[util.scala:466:20] reg [5:0] uops_8_pc_lob; // @[util.scala:466:20] reg uops_8_taken; // @[util.scala:466:20] reg [19:0] uops_8_imm_packed; // @[util.scala:466:20] reg [11:0] uops_8_csr_addr; // @[util.scala:466:20] reg [6:0] uops_8_rob_idx; // @[util.scala:466:20] reg [4:0] uops_8_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_8_stq_idx; // @[util.scala:466:20] reg [1:0] uops_8_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_8_pdst; // @[util.scala:466:20] reg [6:0] uops_8_prs1; // @[util.scala:466:20] reg [6:0] uops_8_prs2; // @[util.scala:466:20] reg [6:0] uops_8_prs3; // @[util.scala:466:20] reg [4:0] uops_8_ppred; // @[util.scala:466:20] reg uops_8_prs1_busy; // @[util.scala:466:20] reg uops_8_prs2_busy; // @[util.scala:466:20] reg uops_8_prs3_busy; // @[util.scala:466:20] reg uops_8_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_8_stale_pdst; // @[util.scala:466:20] reg uops_8_exception; // @[util.scala:466:20] reg [63:0] uops_8_exc_cause; // @[util.scala:466:20] reg uops_8_bypassable; // @[util.scala:466:20] reg [4:0] uops_8_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_8_mem_size; // @[util.scala:466:20] reg uops_8_mem_signed; // @[util.scala:466:20] reg uops_8_is_fence; // @[util.scala:466:20] reg uops_8_is_fencei; // @[util.scala:466:20] reg uops_8_is_amo; // @[util.scala:466:20] reg uops_8_uses_ldq; // @[util.scala:466:20] reg uops_8_uses_stq; // @[util.scala:466:20] reg uops_8_is_sys_pc2epc; // @[util.scala:466:20] reg uops_8_is_unique; // @[util.scala:466:20] reg uops_8_flush_on_commit; // @[util.scala:466:20] reg uops_8_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_8_ldst; // @[util.scala:466:20] reg [5:0] uops_8_lrs1; // @[util.scala:466:20] reg [5:0] uops_8_lrs2; // @[util.scala:466:20] reg [5:0] uops_8_lrs3; // @[util.scala:466:20] reg uops_8_ldst_val; // @[util.scala:466:20] reg [1:0] uops_8_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_8_lrs2_rtype; // @[util.scala:466:20] reg uops_8_frs3_en; // @[util.scala:466:20] reg uops_8_fp_val; // @[util.scala:466:20] reg uops_8_fp_single; // @[util.scala:466:20] reg uops_8_xcpt_pf_if; // @[util.scala:466:20] reg uops_8_xcpt_ae_if; // @[util.scala:466:20] reg uops_8_xcpt_ma_if; // @[util.scala:466:20] reg uops_8_bp_debug_if; // @[util.scala:466:20] reg uops_8_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_8_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_8_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_9_uopc; // @[util.scala:466:20] reg [31:0] uops_9_inst; // @[util.scala:466:20] reg [31:0] uops_9_debug_inst; // @[util.scala:466:20] reg uops_9_is_rvc; // @[util.scala:466:20] reg [39:0] uops_9_debug_pc; // @[util.scala:466:20] reg [2:0] uops_9_iq_type; // @[util.scala:466:20] reg [9:0] uops_9_fu_code; // @[util.scala:466:20] reg [3:0] uops_9_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_9_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_9_ctrl_op_fcn; // @[util.scala:466:20] reg uops_9_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_9_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_9_ctrl_is_load; // @[util.scala:466:20] reg uops_9_ctrl_is_sta; // @[util.scala:466:20] reg uops_9_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_9_iw_state; // @[util.scala:466:20] reg uops_9_iw_p1_poisoned; // @[util.scala:466:20] reg uops_9_iw_p2_poisoned; // @[util.scala:466:20] reg uops_9_is_br; // @[util.scala:466:20] reg uops_9_is_jalr; // @[util.scala:466:20] reg uops_9_is_jal; // @[util.scala:466:20] reg uops_9_is_sfb; // @[util.scala:466:20] reg [15:0] uops_9_br_mask; // @[util.scala:466:20] reg [3:0] uops_9_br_tag; // @[util.scala:466:20] reg [4:0] uops_9_ftq_idx; // @[util.scala:466:20] reg uops_9_edge_inst; // @[util.scala:466:20] reg [5:0] uops_9_pc_lob; // @[util.scala:466:20] reg uops_9_taken; // @[util.scala:466:20] reg [19:0] uops_9_imm_packed; // @[util.scala:466:20] reg [11:0] uops_9_csr_addr; // @[util.scala:466:20] reg [6:0] uops_9_rob_idx; // @[util.scala:466:20] reg [4:0] uops_9_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_9_stq_idx; // @[util.scala:466:20] reg [1:0] uops_9_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_9_pdst; // @[util.scala:466:20] reg [6:0] uops_9_prs1; // @[util.scala:466:20] reg [6:0] uops_9_prs2; // @[util.scala:466:20] reg [6:0] uops_9_prs3; // @[util.scala:466:20] reg [4:0] uops_9_ppred; // @[util.scala:466:20] reg uops_9_prs1_busy; // @[util.scala:466:20] reg uops_9_prs2_busy; // @[util.scala:466:20] reg uops_9_prs3_busy; // @[util.scala:466:20] reg uops_9_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_9_stale_pdst; // @[util.scala:466:20] reg uops_9_exception; // @[util.scala:466:20] reg [63:0] uops_9_exc_cause; // @[util.scala:466:20] reg uops_9_bypassable; // @[util.scala:466:20] reg [4:0] uops_9_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_9_mem_size; // @[util.scala:466:20] reg uops_9_mem_signed; // @[util.scala:466:20] reg uops_9_is_fence; // @[util.scala:466:20] reg uops_9_is_fencei; // @[util.scala:466:20] reg uops_9_is_amo; // @[util.scala:466:20] reg uops_9_uses_ldq; // @[util.scala:466:20] reg uops_9_uses_stq; // @[util.scala:466:20] reg uops_9_is_sys_pc2epc; // @[util.scala:466:20] reg uops_9_is_unique; // @[util.scala:466:20] reg uops_9_flush_on_commit; // @[util.scala:466:20] reg uops_9_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_9_ldst; // @[util.scala:466:20] reg [5:0] uops_9_lrs1; // @[util.scala:466:20] reg [5:0] uops_9_lrs2; // @[util.scala:466:20] reg [5:0] uops_9_lrs3; // @[util.scala:466:20] reg uops_9_ldst_val; // @[util.scala:466:20] reg [1:0] uops_9_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_9_lrs2_rtype; // @[util.scala:466:20] reg uops_9_frs3_en; // @[util.scala:466:20] reg uops_9_fp_val; // @[util.scala:466:20] reg uops_9_fp_single; // @[util.scala:466:20] reg uops_9_xcpt_pf_if; // @[util.scala:466:20] reg uops_9_xcpt_ae_if; // @[util.scala:466:20] reg uops_9_xcpt_ma_if; // @[util.scala:466:20] reg uops_9_bp_debug_if; // @[util.scala:466:20] reg uops_9_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_9_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_9_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_10_uopc; // @[util.scala:466:20] reg [31:0] uops_10_inst; // @[util.scala:466:20] reg [31:0] uops_10_debug_inst; // @[util.scala:466:20] reg uops_10_is_rvc; // @[util.scala:466:20] reg [39:0] uops_10_debug_pc; // @[util.scala:466:20] reg [2:0] uops_10_iq_type; // @[util.scala:466:20] reg [9:0] uops_10_fu_code; // @[util.scala:466:20] reg [3:0] uops_10_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_10_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_10_ctrl_op_fcn; // @[util.scala:466:20] reg uops_10_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_10_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_10_ctrl_is_load; // @[util.scala:466:20] reg uops_10_ctrl_is_sta; // @[util.scala:466:20] reg uops_10_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_10_iw_state; // @[util.scala:466:20] reg uops_10_iw_p1_poisoned; // @[util.scala:466:20] reg uops_10_iw_p2_poisoned; // @[util.scala:466:20] reg uops_10_is_br; // @[util.scala:466:20] reg uops_10_is_jalr; // @[util.scala:466:20] reg uops_10_is_jal; // @[util.scala:466:20] reg uops_10_is_sfb; // @[util.scala:466:20] reg [15:0] uops_10_br_mask; // @[util.scala:466:20] reg [3:0] uops_10_br_tag; // @[util.scala:466:20] reg [4:0] uops_10_ftq_idx; // @[util.scala:466:20] reg uops_10_edge_inst; // @[util.scala:466:20] reg [5:0] uops_10_pc_lob; // @[util.scala:466:20] reg uops_10_taken; // @[util.scala:466:20] reg [19:0] uops_10_imm_packed; // @[util.scala:466:20] reg [11:0] uops_10_csr_addr; // @[util.scala:466:20] reg [6:0] uops_10_rob_idx; // @[util.scala:466:20] reg [4:0] uops_10_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_10_stq_idx; // @[util.scala:466:20] reg [1:0] uops_10_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_10_pdst; // @[util.scala:466:20] reg [6:0] uops_10_prs1; // @[util.scala:466:20] reg [6:0] uops_10_prs2; // @[util.scala:466:20] reg [6:0] uops_10_prs3; // @[util.scala:466:20] reg [4:0] uops_10_ppred; // @[util.scala:466:20] reg uops_10_prs1_busy; // @[util.scala:466:20] reg uops_10_prs2_busy; // @[util.scala:466:20] reg uops_10_prs3_busy; // @[util.scala:466:20] reg uops_10_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_10_stale_pdst; // @[util.scala:466:20] reg uops_10_exception; // @[util.scala:466:20] reg [63:0] uops_10_exc_cause; // @[util.scala:466:20] reg uops_10_bypassable; // @[util.scala:466:20] reg [4:0] uops_10_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_10_mem_size; // @[util.scala:466:20] reg uops_10_mem_signed; // @[util.scala:466:20] reg uops_10_is_fence; // @[util.scala:466:20] reg uops_10_is_fencei; // @[util.scala:466:20] reg uops_10_is_amo; // @[util.scala:466:20] reg uops_10_uses_ldq; // @[util.scala:466:20] reg uops_10_uses_stq; // @[util.scala:466:20] reg uops_10_is_sys_pc2epc; // @[util.scala:466:20] reg uops_10_is_unique; // @[util.scala:466:20] reg uops_10_flush_on_commit; // @[util.scala:466:20] reg uops_10_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_10_ldst; // @[util.scala:466:20] reg [5:0] uops_10_lrs1; // @[util.scala:466:20] reg [5:0] uops_10_lrs2; // @[util.scala:466:20] reg [5:0] uops_10_lrs3; // @[util.scala:466:20] reg uops_10_ldst_val; // @[util.scala:466:20] reg [1:0] uops_10_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_10_lrs2_rtype; // @[util.scala:466:20] reg uops_10_frs3_en; // @[util.scala:466:20] reg uops_10_fp_val; // @[util.scala:466:20] reg uops_10_fp_single; // @[util.scala:466:20] reg uops_10_xcpt_pf_if; // @[util.scala:466:20] reg uops_10_xcpt_ae_if; // @[util.scala:466:20] reg uops_10_xcpt_ma_if; // @[util.scala:466:20] reg uops_10_bp_debug_if; // @[util.scala:466:20] reg uops_10_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_10_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_10_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_11_uopc; // @[util.scala:466:20] reg [31:0] uops_11_inst; // @[util.scala:466:20] reg [31:0] uops_11_debug_inst; // @[util.scala:466:20] reg uops_11_is_rvc; // @[util.scala:466:20] reg [39:0] uops_11_debug_pc; // @[util.scala:466:20] reg [2:0] uops_11_iq_type; // @[util.scala:466:20] reg [9:0] uops_11_fu_code; // @[util.scala:466:20] reg [3:0] uops_11_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_11_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_11_ctrl_op_fcn; // @[util.scala:466:20] reg uops_11_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_11_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_11_ctrl_is_load; // @[util.scala:466:20] reg uops_11_ctrl_is_sta; // @[util.scala:466:20] reg uops_11_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_11_iw_state; // @[util.scala:466:20] reg uops_11_iw_p1_poisoned; // @[util.scala:466:20] reg uops_11_iw_p2_poisoned; // @[util.scala:466:20] reg uops_11_is_br; // @[util.scala:466:20] reg uops_11_is_jalr; // @[util.scala:466:20] reg uops_11_is_jal; // @[util.scala:466:20] reg uops_11_is_sfb; // @[util.scala:466:20] reg [15:0] uops_11_br_mask; // @[util.scala:466:20] reg [3:0] uops_11_br_tag; // @[util.scala:466:20] reg [4:0] uops_11_ftq_idx; // @[util.scala:466:20] reg uops_11_edge_inst; // @[util.scala:466:20] reg [5:0] uops_11_pc_lob; // @[util.scala:466:20] reg uops_11_taken; // @[util.scala:466:20] reg [19:0] uops_11_imm_packed; // @[util.scala:466:20] reg [11:0] uops_11_csr_addr; // @[util.scala:466:20] reg [6:0] uops_11_rob_idx; // @[util.scala:466:20] reg [4:0] uops_11_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_11_stq_idx; // @[util.scala:466:20] reg [1:0] uops_11_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_11_pdst; // @[util.scala:466:20] reg [6:0] uops_11_prs1; // @[util.scala:466:20] reg [6:0] uops_11_prs2; // @[util.scala:466:20] reg [6:0] uops_11_prs3; // @[util.scala:466:20] reg [4:0] uops_11_ppred; // @[util.scala:466:20] reg uops_11_prs1_busy; // @[util.scala:466:20] reg uops_11_prs2_busy; // @[util.scala:466:20] reg uops_11_prs3_busy; // @[util.scala:466:20] reg uops_11_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_11_stale_pdst; // @[util.scala:466:20] reg uops_11_exception; // @[util.scala:466:20] reg [63:0] uops_11_exc_cause; // @[util.scala:466:20] reg uops_11_bypassable; // @[util.scala:466:20] reg [4:0] uops_11_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_11_mem_size; // @[util.scala:466:20] reg uops_11_mem_signed; // @[util.scala:466:20] reg uops_11_is_fence; // @[util.scala:466:20] reg uops_11_is_fencei; // @[util.scala:466:20] reg uops_11_is_amo; // @[util.scala:466:20] reg uops_11_uses_ldq; // @[util.scala:466:20] reg uops_11_uses_stq; // @[util.scala:466:20] reg uops_11_is_sys_pc2epc; // @[util.scala:466:20] reg uops_11_is_unique; // @[util.scala:466:20] reg uops_11_flush_on_commit; // @[util.scala:466:20] reg uops_11_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_11_ldst; // @[util.scala:466:20] reg [5:0] uops_11_lrs1; // @[util.scala:466:20] reg [5:0] uops_11_lrs2; // @[util.scala:466:20] reg [5:0] uops_11_lrs3; // @[util.scala:466:20] reg uops_11_ldst_val; // @[util.scala:466:20] reg [1:0] uops_11_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_11_lrs2_rtype; // @[util.scala:466:20] reg uops_11_frs3_en; // @[util.scala:466:20] reg uops_11_fp_val; // @[util.scala:466:20] reg uops_11_fp_single; // @[util.scala:466:20] reg uops_11_xcpt_pf_if; // @[util.scala:466:20] reg uops_11_xcpt_ae_if; // @[util.scala:466:20] reg uops_11_xcpt_ma_if; // @[util.scala:466:20] reg uops_11_bp_debug_if; // @[util.scala:466:20] reg uops_11_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_11_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_11_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_12_uopc; // @[util.scala:466:20] reg [31:0] uops_12_inst; // @[util.scala:466:20] reg [31:0] uops_12_debug_inst; // @[util.scala:466:20] reg uops_12_is_rvc; // @[util.scala:466:20] reg [39:0] uops_12_debug_pc; // @[util.scala:466:20] reg [2:0] uops_12_iq_type; // @[util.scala:466:20] reg [9:0] uops_12_fu_code; // @[util.scala:466:20] reg [3:0] uops_12_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_12_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_12_ctrl_op_fcn; // @[util.scala:466:20] reg uops_12_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_12_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_12_ctrl_is_load; // @[util.scala:466:20] reg uops_12_ctrl_is_sta; // @[util.scala:466:20] reg uops_12_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_12_iw_state; // @[util.scala:466:20] reg uops_12_iw_p1_poisoned; // @[util.scala:466:20] reg uops_12_iw_p2_poisoned; // @[util.scala:466:20] reg uops_12_is_br; // @[util.scala:466:20] reg uops_12_is_jalr; // @[util.scala:466:20] reg uops_12_is_jal; // @[util.scala:466:20] reg uops_12_is_sfb; // @[util.scala:466:20] reg [15:0] uops_12_br_mask; // @[util.scala:466:20] reg [3:0] uops_12_br_tag; // @[util.scala:466:20] reg [4:0] uops_12_ftq_idx; // @[util.scala:466:20] reg uops_12_edge_inst; // @[util.scala:466:20] reg [5:0] uops_12_pc_lob; // @[util.scala:466:20] reg uops_12_taken; // @[util.scala:466:20] reg [19:0] uops_12_imm_packed; // @[util.scala:466:20] reg [11:0] uops_12_csr_addr; // @[util.scala:466:20] reg [6:0] uops_12_rob_idx; // @[util.scala:466:20] reg [4:0] uops_12_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_12_stq_idx; // @[util.scala:466:20] reg [1:0] uops_12_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_12_pdst; // @[util.scala:466:20] reg [6:0] uops_12_prs1; // @[util.scala:466:20] reg [6:0] uops_12_prs2; // @[util.scala:466:20] reg [6:0] uops_12_prs3; // @[util.scala:466:20] reg [4:0] uops_12_ppred; // @[util.scala:466:20] reg uops_12_prs1_busy; // @[util.scala:466:20] reg uops_12_prs2_busy; // @[util.scala:466:20] reg uops_12_prs3_busy; // @[util.scala:466:20] reg uops_12_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_12_stale_pdst; // @[util.scala:466:20] reg uops_12_exception; // @[util.scala:466:20] reg [63:0] uops_12_exc_cause; // @[util.scala:466:20] reg uops_12_bypassable; // @[util.scala:466:20] reg [4:0] uops_12_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_12_mem_size; // @[util.scala:466:20] reg uops_12_mem_signed; // @[util.scala:466:20] reg uops_12_is_fence; // @[util.scala:466:20] reg uops_12_is_fencei; // @[util.scala:466:20] reg uops_12_is_amo; // @[util.scala:466:20] reg uops_12_uses_ldq; // @[util.scala:466:20] reg uops_12_uses_stq; // @[util.scala:466:20] reg uops_12_is_sys_pc2epc; // @[util.scala:466:20] reg uops_12_is_unique; // @[util.scala:466:20] reg uops_12_flush_on_commit; // @[util.scala:466:20] reg uops_12_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_12_ldst; // @[util.scala:466:20] reg [5:0] uops_12_lrs1; // @[util.scala:466:20] reg [5:0] uops_12_lrs2; // @[util.scala:466:20] reg [5:0] uops_12_lrs3; // @[util.scala:466:20] reg uops_12_ldst_val; // @[util.scala:466:20] reg [1:0] uops_12_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_12_lrs2_rtype; // @[util.scala:466:20] reg uops_12_frs3_en; // @[util.scala:466:20] reg uops_12_fp_val; // @[util.scala:466:20] reg uops_12_fp_single; // @[util.scala:466:20] reg uops_12_xcpt_pf_if; // @[util.scala:466:20] reg uops_12_xcpt_ae_if; // @[util.scala:466:20] reg uops_12_xcpt_ma_if; // @[util.scala:466:20] reg uops_12_bp_debug_if; // @[util.scala:466:20] reg uops_12_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_12_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_12_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_13_uopc; // @[util.scala:466:20] reg [31:0] uops_13_inst; // @[util.scala:466:20] reg [31:0] uops_13_debug_inst; // @[util.scala:466:20] reg uops_13_is_rvc; // @[util.scala:466:20] reg [39:0] uops_13_debug_pc; // @[util.scala:466:20] reg [2:0] uops_13_iq_type; // @[util.scala:466:20] reg [9:0] uops_13_fu_code; // @[util.scala:466:20] reg [3:0] uops_13_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_13_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_13_ctrl_op_fcn; // @[util.scala:466:20] reg uops_13_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_13_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_13_ctrl_is_load; // @[util.scala:466:20] reg uops_13_ctrl_is_sta; // @[util.scala:466:20] reg uops_13_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_13_iw_state; // @[util.scala:466:20] reg uops_13_iw_p1_poisoned; // @[util.scala:466:20] reg uops_13_iw_p2_poisoned; // @[util.scala:466:20] reg uops_13_is_br; // @[util.scala:466:20] reg uops_13_is_jalr; // @[util.scala:466:20] reg uops_13_is_jal; // @[util.scala:466:20] reg uops_13_is_sfb; // @[util.scala:466:20] reg [15:0] uops_13_br_mask; // @[util.scala:466:20] reg [3:0] uops_13_br_tag; // @[util.scala:466:20] reg [4:0] uops_13_ftq_idx; // @[util.scala:466:20] reg uops_13_edge_inst; // @[util.scala:466:20] reg [5:0] uops_13_pc_lob; // @[util.scala:466:20] reg uops_13_taken; // @[util.scala:466:20] reg [19:0] uops_13_imm_packed; // @[util.scala:466:20] reg [11:0] uops_13_csr_addr; // @[util.scala:466:20] reg [6:0] uops_13_rob_idx; // @[util.scala:466:20] reg [4:0] uops_13_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_13_stq_idx; // @[util.scala:466:20] reg [1:0] uops_13_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_13_pdst; // @[util.scala:466:20] reg [6:0] uops_13_prs1; // @[util.scala:466:20] reg [6:0] uops_13_prs2; // @[util.scala:466:20] reg [6:0] uops_13_prs3; // @[util.scala:466:20] reg [4:0] uops_13_ppred; // @[util.scala:466:20] reg uops_13_prs1_busy; // @[util.scala:466:20] reg uops_13_prs2_busy; // @[util.scala:466:20] reg uops_13_prs3_busy; // @[util.scala:466:20] reg uops_13_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_13_stale_pdst; // @[util.scala:466:20] reg uops_13_exception; // @[util.scala:466:20] reg [63:0] uops_13_exc_cause; // @[util.scala:466:20] reg uops_13_bypassable; // @[util.scala:466:20] reg [4:0] uops_13_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_13_mem_size; // @[util.scala:466:20] reg uops_13_mem_signed; // @[util.scala:466:20] reg uops_13_is_fence; // @[util.scala:466:20] reg uops_13_is_fencei; // @[util.scala:466:20] reg uops_13_is_amo; // @[util.scala:466:20] reg uops_13_uses_ldq; // @[util.scala:466:20] reg uops_13_uses_stq; // @[util.scala:466:20] reg uops_13_is_sys_pc2epc; // @[util.scala:466:20] reg uops_13_is_unique; // @[util.scala:466:20] reg uops_13_flush_on_commit; // @[util.scala:466:20] reg uops_13_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_13_ldst; // @[util.scala:466:20] reg [5:0] uops_13_lrs1; // @[util.scala:466:20] reg [5:0] uops_13_lrs2; // @[util.scala:466:20] reg [5:0] uops_13_lrs3; // @[util.scala:466:20] reg uops_13_ldst_val; // @[util.scala:466:20] reg [1:0] uops_13_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_13_lrs2_rtype; // @[util.scala:466:20] reg uops_13_frs3_en; // @[util.scala:466:20] reg uops_13_fp_val; // @[util.scala:466:20] reg uops_13_fp_single; // @[util.scala:466:20] reg uops_13_xcpt_pf_if; // @[util.scala:466:20] reg uops_13_xcpt_ae_if; // @[util.scala:466:20] reg uops_13_xcpt_ma_if; // @[util.scala:466:20] reg uops_13_bp_debug_if; // @[util.scala:466:20] reg uops_13_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_13_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_13_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_14_uopc; // @[util.scala:466:20] reg [31:0] uops_14_inst; // @[util.scala:466:20] reg [31:0] uops_14_debug_inst; // @[util.scala:466:20] reg uops_14_is_rvc; // @[util.scala:466:20] reg [39:0] uops_14_debug_pc; // @[util.scala:466:20] reg [2:0] uops_14_iq_type; // @[util.scala:466:20] reg [9:0] uops_14_fu_code; // @[util.scala:466:20] reg [3:0] uops_14_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_14_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_14_ctrl_op_fcn; // @[util.scala:466:20] reg uops_14_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_14_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_14_ctrl_is_load; // @[util.scala:466:20] reg uops_14_ctrl_is_sta; // @[util.scala:466:20] reg uops_14_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_14_iw_state; // @[util.scala:466:20] reg uops_14_iw_p1_poisoned; // @[util.scala:466:20] reg uops_14_iw_p2_poisoned; // @[util.scala:466:20] reg uops_14_is_br; // @[util.scala:466:20] reg uops_14_is_jalr; // @[util.scala:466:20] reg uops_14_is_jal; // @[util.scala:466:20] reg uops_14_is_sfb; // @[util.scala:466:20] reg [15:0] uops_14_br_mask; // @[util.scala:466:20] reg [3:0] uops_14_br_tag; // @[util.scala:466:20] reg [4:0] uops_14_ftq_idx; // @[util.scala:466:20] reg uops_14_edge_inst; // @[util.scala:466:20] reg [5:0] uops_14_pc_lob; // @[util.scala:466:20] reg uops_14_taken; // @[util.scala:466:20] reg [19:0] uops_14_imm_packed; // @[util.scala:466:20] reg [11:0] uops_14_csr_addr; // @[util.scala:466:20] reg [6:0] uops_14_rob_idx; // @[util.scala:466:20] reg [4:0] uops_14_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_14_stq_idx; // @[util.scala:466:20] reg [1:0] uops_14_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_14_pdst; // @[util.scala:466:20] reg [6:0] uops_14_prs1; // @[util.scala:466:20] reg [6:0] uops_14_prs2; // @[util.scala:466:20] reg [6:0] uops_14_prs3; // @[util.scala:466:20] reg [4:0] uops_14_ppred; // @[util.scala:466:20] reg uops_14_prs1_busy; // @[util.scala:466:20] reg uops_14_prs2_busy; // @[util.scala:466:20] reg uops_14_prs3_busy; // @[util.scala:466:20] reg uops_14_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_14_stale_pdst; // @[util.scala:466:20] reg uops_14_exception; // @[util.scala:466:20] reg [63:0] uops_14_exc_cause; // @[util.scala:466:20] reg uops_14_bypassable; // @[util.scala:466:20] reg [4:0] uops_14_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_14_mem_size; // @[util.scala:466:20] reg uops_14_mem_signed; // @[util.scala:466:20] reg uops_14_is_fence; // @[util.scala:466:20] reg uops_14_is_fencei; // @[util.scala:466:20] reg uops_14_is_amo; // @[util.scala:466:20] reg uops_14_uses_ldq; // @[util.scala:466:20] reg uops_14_uses_stq; // @[util.scala:466:20] reg uops_14_is_sys_pc2epc; // @[util.scala:466:20] reg uops_14_is_unique; // @[util.scala:466:20] reg uops_14_flush_on_commit; // @[util.scala:466:20] reg uops_14_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_14_ldst; // @[util.scala:466:20] reg [5:0] uops_14_lrs1; // @[util.scala:466:20] reg [5:0] uops_14_lrs2; // @[util.scala:466:20] reg [5:0] uops_14_lrs3; // @[util.scala:466:20] reg uops_14_ldst_val; // @[util.scala:466:20] reg [1:0] uops_14_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_14_lrs2_rtype; // @[util.scala:466:20] reg uops_14_frs3_en; // @[util.scala:466:20] reg uops_14_fp_val; // @[util.scala:466:20] reg uops_14_fp_single; // @[util.scala:466:20] reg uops_14_xcpt_pf_if; // @[util.scala:466:20] reg uops_14_xcpt_ae_if; // @[util.scala:466:20] reg uops_14_xcpt_ma_if; // @[util.scala:466:20] reg uops_14_bp_debug_if; // @[util.scala:466:20] reg uops_14_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_14_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_14_debug_tsrc; // @[util.scala:466:20] reg [6:0] uops_15_uopc; // @[util.scala:466:20] reg [31:0] uops_15_inst; // @[util.scala:466:20] reg [31:0] uops_15_debug_inst; // @[util.scala:466:20] reg uops_15_is_rvc; // @[util.scala:466:20] reg [39:0] uops_15_debug_pc; // @[util.scala:466:20] reg [2:0] uops_15_iq_type; // @[util.scala:466:20] reg [9:0] uops_15_fu_code; // @[util.scala:466:20] reg [3:0] uops_15_ctrl_br_type; // @[util.scala:466:20] reg [1:0] uops_15_ctrl_op1_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_op2_sel; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_imm_sel; // @[util.scala:466:20] reg [4:0] uops_15_ctrl_op_fcn; // @[util.scala:466:20] reg uops_15_ctrl_fcn_dw; // @[util.scala:466:20] reg [2:0] uops_15_ctrl_csr_cmd; // @[util.scala:466:20] reg uops_15_ctrl_is_load; // @[util.scala:466:20] reg uops_15_ctrl_is_sta; // @[util.scala:466:20] reg uops_15_ctrl_is_std; // @[util.scala:466:20] reg [1:0] uops_15_iw_state; // @[util.scala:466:20] reg uops_15_iw_p1_poisoned; // @[util.scala:466:20] reg uops_15_iw_p2_poisoned; // @[util.scala:466:20] reg uops_15_is_br; // @[util.scala:466:20] reg uops_15_is_jalr; // @[util.scala:466:20] reg uops_15_is_jal; // @[util.scala:466:20] reg uops_15_is_sfb; // @[util.scala:466:20] reg [15:0] uops_15_br_mask; // @[util.scala:466:20] reg [3:0] uops_15_br_tag; // @[util.scala:466:20] reg [4:0] uops_15_ftq_idx; // @[util.scala:466:20] reg uops_15_edge_inst; // @[util.scala:466:20] reg [5:0] uops_15_pc_lob; // @[util.scala:466:20] reg uops_15_taken; // @[util.scala:466:20] reg [19:0] uops_15_imm_packed; // @[util.scala:466:20] reg [11:0] uops_15_csr_addr; // @[util.scala:466:20] reg [6:0] uops_15_rob_idx; // @[util.scala:466:20] reg [4:0] uops_15_ldq_idx; // @[util.scala:466:20] reg [4:0] uops_15_stq_idx; // @[util.scala:466:20] reg [1:0] uops_15_rxq_idx; // @[util.scala:466:20] reg [6:0] uops_15_pdst; // @[util.scala:466:20] reg [6:0] uops_15_prs1; // @[util.scala:466:20] reg [6:0] uops_15_prs2; // @[util.scala:466:20] reg [6:0] uops_15_prs3; // @[util.scala:466:20] reg [4:0] uops_15_ppred; // @[util.scala:466:20] reg uops_15_prs1_busy; // @[util.scala:466:20] reg uops_15_prs2_busy; // @[util.scala:466:20] reg uops_15_prs3_busy; // @[util.scala:466:20] reg uops_15_ppred_busy; // @[util.scala:466:20] reg [6:0] uops_15_stale_pdst; // @[util.scala:466:20] reg uops_15_exception; // @[util.scala:466:20] reg [63:0] uops_15_exc_cause; // @[util.scala:466:20] reg uops_15_bypassable; // @[util.scala:466:20] reg [4:0] uops_15_mem_cmd; // @[util.scala:466:20] reg [1:0] uops_15_mem_size; // @[util.scala:466:20] reg uops_15_mem_signed; // @[util.scala:466:20] reg uops_15_is_fence; // @[util.scala:466:20] reg uops_15_is_fencei; // @[util.scala:466:20] reg uops_15_is_amo; // @[util.scala:466:20] reg uops_15_uses_ldq; // @[util.scala:466:20] reg uops_15_uses_stq; // @[util.scala:466:20] reg uops_15_is_sys_pc2epc; // @[util.scala:466:20] reg uops_15_is_unique; // @[util.scala:466:20] reg uops_15_flush_on_commit; // @[util.scala:466:20] reg uops_15_ldst_is_rs1; // @[util.scala:466:20] reg [5:0] uops_15_ldst; // @[util.scala:466:20] reg [5:0] uops_15_lrs1; // @[util.scala:466:20] reg [5:0] uops_15_lrs2; // @[util.scala:466:20] reg [5:0] uops_15_lrs3; // @[util.scala:466:20] reg uops_15_ldst_val; // @[util.scala:466:20] reg [1:0] uops_15_dst_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs1_rtype; // @[util.scala:466:20] reg [1:0] uops_15_lrs2_rtype; // @[util.scala:466:20] reg uops_15_frs3_en; // @[util.scala:466:20] reg uops_15_fp_val; // @[util.scala:466:20] reg uops_15_fp_single; // @[util.scala:466:20] reg uops_15_xcpt_pf_if; // @[util.scala:466:20] reg uops_15_xcpt_ae_if; // @[util.scala:466:20] reg uops_15_xcpt_ma_if; // @[util.scala:466:20] reg uops_15_bp_debug_if; // @[util.scala:466:20] reg uops_15_bp_xcpt_if; // @[util.scala:466:20] reg [1:0] uops_15_debug_fsrc; // @[util.scala:466:20] reg [1:0] uops_15_debug_tsrc; // @[util.scala:466:20] reg [3:0] enq_ptr_value; // @[Counter.scala:61:40] reg [3:0] deq_ptr_value; // @[Counter.scala:61:40] reg maybe_full; // @[util.scala:470:27] wire ptr_match = enq_ptr_value == deq_ptr_value; // @[Counter.scala:61:40] wire _io_empty_T = ~maybe_full; // @[util.scala:470:27, :473:28] assign _io_empty_T_1 = ptr_match & _io_empty_T; // @[util.scala:472:33, :473:{25,28}] assign io_empty_0 = _io_empty_T_1; // @[util.scala:448:7, :473:25] wire _GEN = ptr_match & maybe_full; // @[util.scala:470:27, :472:33, :474:24] wire full; // @[util.scala:474:24] assign full = _GEN; // @[util.scala:474:24] wire _io_count_T; // @[util.scala:526:32] assign _io_count_T = _GEN; // @[util.scala:474:24, :526:32] wire _do_enq_T = io_enq_ready_0 & io_enq_valid_0; // @[Decoupled.scala:51:35] wire do_enq = _do_enq_T; // @[Decoupled.scala:51:35] wire [15:0] _GEN_0 = {{valids_15}, {valids_14}, {valids_13}, {valids_12}, {valids_11}, {valids_10}, {valids_9}, {valids_8}, {valids_7}, {valids_6}, {valids_5}, {valids_4}, {valids_3}, {valids_2}, {valids_1}, {valids_0}}; // @[util.scala:465:24, :476:42] wire _GEN_1 = _GEN_0[deq_ptr_value]; // @[Counter.scala:61:40] wire _do_deq_T = ~_GEN_1; // @[util.scala:476:42] wire _do_deq_T_1 = io_deq_ready_0 | _do_deq_T; // @[util.scala:448:7, :476:{39,42}] wire _do_deq_T_2 = ~io_empty_0; // @[util.scala:448:7, :476:69] wire _do_deq_T_3 = _do_deq_T_1 & _do_deq_T_2; // @[util.scala:476:{39,66,69}] wire do_deq = _do_deq_T_3; // @[util.scala:476:{24,66}] wire [15:0] _valids_0_T = io_brupdate_b1_mispredict_mask_0 & uops_0_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_0_T_1 = |_valids_0_T; // @[util.scala:118:{51,59}] wire _valids_0_T_2 = ~_valids_0_T_1; // @[util.scala:118:59, :481:32] wire _valids_0_T_3 = valids_0 & _valids_0_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_0_T_4 = io_flush_0 & uops_0_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_0_T_5 = ~_valids_0_T_4; // @[util.scala:481:{72,83}] wire _valids_0_T_6 = _valids_0_T_3 & _valids_0_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_0_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_0_br_mask_T_1 = uops_0_br_mask & _uops_0_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_1_T = io_brupdate_b1_mispredict_mask_0 & uops_1_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_1_T_1 = |_valids_1_T; // @[util.scala:118:{51,59}] wire _valids_1_T_2 = ~_valids_1_T_1; // @[util.scala:118:59, :481:32] wire _valids_1_T_3 = valids_1 & _valids_1_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_1_T_4 = io_flush_0 & uops_1_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_1_T_5 = ~_valids_1_T_4; // @[util.scala:481:{72,83}] wire _valids_1_T_6 = _valids_1_T_3 & _valids_1_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_1_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_1_br_mask_T_1 = uops_1_br_mask & _uops_1_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_2_T = io_brupdate_b1_mispredict_mask_0 & uops_2_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_2_T_1 = |_valids_2_T; // @[util.scala:118:{51,59}] wire _valids_2_T_2 = ~_valids_2_T_1; // @[util.scala:118:59, :481:32] wire _valids_2_T_3 = valids_2 & _valids_2_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_2_T_4 = io_flush_0 & uops_2_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_2_T_5 = ~_valids_2_T_4; // @[util.scala:481:{72,83}] wire _valids_2_T_6 = _valids_2_T_3 & _valids_2_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_2_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_2_br_mask_T_1 = uops_2_br_mask & _uops_2_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_3_T = io_brupdate_b1_mispredict_mask_0 & uops_3_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_3_T_1 = |_valids_3_T; // @[util.scala:118:{51,59}] wire _valids_3_T_2 = ~_valids_3_T_1; // @[util.scala:118:59, :481:32] wire _valids_3_T_3 = valids_3 & _valids_3_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_3_T_4 = io_flush_0 & uops_3_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_3_T_5 = ~_valids_3_T_4; // @[util.scala:481:{72,83}] wire _valids_3_T_6 = _valids_3_T_3 & _valids_3_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_3_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_3_br_mask_T_1 = uops_3_br_mask & _uops_3_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_4_T = io_brupdate_b1_mispredict_mask_0 & uops_4_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_4_T_1 = |_valids_4_T; // @[util.scala:118:{51,59}] wire _valids_4_T_2 = ~_valids_4_T_1; // @[util.scala:118:59, :481:32] wire _valids_4_T_3 = valids_4 & _valids_4_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_4_T_4 = io_flush_0 & uops_4_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_4_T_5 = ~_valids_4_T_4; // @[util.scala:481:{72,83}] wire _valids_4_T_6 = _valids_4_T_3 & _valids_4_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_4_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_4_br_mask_T_1 = uops_4_br_mask & _uops_4_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_5_T = io_brupdate_b1_mispredict_mask_0 & uops_5_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_5_T_1 = |_valids_5_T; // @[util.scala:118:{51,59}] wire _valids_5_T_2 = ~_valids_5_T_1; // @[util.scala:118:59, :481:32] wire _valids_5_T_3 = valids_5 & _valids_5_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_5_T_4 = io_flush_0 & uops_5_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_5_T_5 = ~_valids_5_T_4; // @[util.scala:481:{72,83}] wire _valids_5_T_6 = _valids_5_T_3 & _valids_5_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_5_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_5_br_mask_T_1 = uops_5_br_mask & _uops_5_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_6_T = io_brupdate_b1_mispredict_mask_0 & uops_6_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_6_T_1 = |_valids_6_T; // @[util.scala:118:{51,59}] wire _valids_6_T_2 = ~_valids_6_T_1; // @[util.scala:118:59, :481:32] wire _valids_6_T_3 = valids_6 & _valids_6_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_6_T_4 = io_flush_0 & uops_6_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_6_T_5 = ~_valids_6_T_4; // @[util.scala:481:{72,83}] wire _valids_6_T_6 = _valids_6_T_3 & _valids_6_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_6_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_6_br_mask_T_1 = uops_6_br_mask & _uops_6_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_7_T = io_brupdate_b1_mispredict_mask_0 & uops_7_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_7_T_1 = |_valids_7_T; // @[util.scala:118:{51,59}] wire _valids_7_T_2 = ~_valids_7_T_1; // @[util.scala:118:59, :481:32] wire _valids_7_T_3 = valids_7 & _valids_7_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_7_T_4 = io_flush_0 & uops_7_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_7_T_5 = ~_valids_7_T_4; // @[util.scala:481:{72,83}] wire _valids_7_T_6 = _valids_7_T_3 & _valids_7_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_7_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_7_br_mask_T_1 = uops_7_br_mask & _uops_7_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_8_T = io_brupdate_b1_mispredict_mask_0 & uops_8_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_8_T_1 = |_valids_8_T; // @[util.scala:118:{51,59}] wire _valids_8_T_2 = ~_valids_8_T_1; // @[util.scala:118:59, :481:32] wire _valids_8_T_3 = valids_8 & _valids_8_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_8_T_4 = io_flush_0 & uops_8_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_8_T_5 = ~_valids_8_T_4; // @[util.scala:481:{72,83}] wire _valids_8_T_6 = _valids_8_T_3 & _valids_8_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_8_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_8_br_mask_T_1 = uops_8_br_mask & _uops_8_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_9_T = io_brupdate_b1_mispredict_mask_0 & uops_9_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_9_T_1 = |_valids_9_T; // @[util.scala:118:{51,59}] wire _valids_9_T_2 = ~_valids_9_T_1; // @[util.scala:118:59, :481:32] wire _valids_9_T_3 = valids_9 & _valids_9_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_9_T_4 = io_flush_0 & uops_9_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_9_T_5 = ~_valids_9_T_4; // @[util.scala:481:{72,83}] wire _valids_9_T_6 = _valids_9_T_3 & _valids_9_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_9_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_9_br_mask_T_1 = uops_9_br_mask & _uops_9_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_10_T = io_brupdate_b1_mispredict_mask_0 & uops_10_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_10_T_1 = |_valids_10_T; // @[util.scala:118:{51,59}] wire _valids_10_T_2 = ~_valids_10_T_1; // @[util.scala:118:59, :481:32] wire _valids_10_T_3 = valids_10 & _valids_10_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_10_T_4 = io_flush_0 & uops_10_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_10_T_5 = ~_valids_10_T_4; // @[util.scala:481:{72,83}] wire _valids_10_T_6 = _valids_10_T_3 & _valids_10_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_10_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_10_br_mask_T_1 = uops_10_br_mask & _uops_10_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_11_T = io_brupdate_b1_mispredict_mask_0 & uops_11_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_11_T_1 = |_valids_11_T; // @[util.scala:118:{51,59}] wire _valids_11_T_2 = ~_valids_11_T_1; // @[util.scala:118:59, :481:32] wire _valids_11_T_3 = valids_11 & _valids_11_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_11_T_4 = io_flush_0 & uops_11_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_11_T_5 = ~_valids_11_T_4; // @[util.scala:481:{72,83}] wire _valids_11_T_6 = _valids_11_T_3 & _valids_11_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_11_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_11_br_mask_T_1 = uops_11_br_mask & _uops_11_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_12_T = io_brupdate_b1_mispredict_mask_0 & uops_12_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_12_T_1 = |_valids_12_T; // @[util.scala:118:{51,59}] wire _valids_12_T_2 = ~_valids_12_T_1; // @[util.scala:118:59, :481:32] wire _valids_12_T_3 = valids_12 & _valids_12_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_12_T_4 = io_flush_0 & uops_12_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_12_T_5 = ~_valids_12_T_4; // @[util.scala:481:{72,83}] wire _valids_12_T_6 = _valids_12_T_3 & _valids_12_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_12_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_12_br_mask_T_1 = uops_12_br_mask & _uops_12_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_13_T = io_brupdate_b1_mispredict_mask_0 & uops_13_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_13_T_1 = |_valids_13_T; // @[util.scala:118:{51,59}] wire _valids_13_T_2 = ~_valids_13_T_1; // @[util.scala:118:59, :481:32] wire _valids_13_T_3 = valids_13 & _valids_13_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_13_T_4 = io_flush_0 & uops_13_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_13_T_5 = ~_valids_13_T_4; // @[util.scala:481:{72,83}] wire _valids_13_T_6 = _valids_13_T_3 & _valids_13_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_13_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_13_br_mask_T_1 = uops_13_br_mask & _uops_13_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_14_T = io_brupdate_b1_mispredict_mask_0 & uops_14_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_14_T_1 = |_valids_14_T; // @[util.scala:118:{51,59}] wire _valids_14_T_2 = ~_valids_14_T_1; // @[util.scala:118:59, :481:32] wire _valids_14_T_3 = valids_14 & _valids_14_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_14_T_4 = io_flush_0 & uops_14_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_14_T_5 = ~_valids_14_T_4; // @[util.scala:481:{72,83}] wire _valids_14_T_6 = _valids_14_T_3 & _valids_14_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_14_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_14_br_mask_T_1 = uops_14_br_mask & _uops_14_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _valids_15_T = io_brupdate_b1_mispredict_mask_0 & uops_15_br_mask; // @[util.scala:118:51, :448:7, :466:20] wire _valids_15_T_1 = |_valids_15_T; // @[util.scala:118:{51,59}] wire _valids_15_T_2 = ~_valids_15_T_1; // @[util.scala:118:59, :481:32] wire _valids_15_T_3 = valids_15 & _valids_15_T_2; // @[util.scala:465:24, :481:{29,32}] wire _valids_15_T_4 = io_flush_0 & uops_15_uses_ldq; // @[util.scala:448:7, :466:20, :481:83] wire _valids_15_T_5 = ~_valids_15_T_4; // @[util.scala:481:{72,83}] wire _valids_15_T_6 = _valids_15_T_3 & _valids_15_T_5; // @[util.scala:481:{29,69,72}] wire [15:0] _uops_15_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:89:23, :448:7] wire [15:0] _uops_15_br_mask_T_1 = uops_15_br_mask & _uops_15_br_mask_T; // @[util.scala:89:{21,23}, :466:20] wire [15:0] _uops_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] wire [15:0] _uops_br_mask_T_1 = io_enq_bits_uop_br_mask_0 & _uops_br_mask_T; // @[util.scala:85:{25,27}, :448:7] wire wrap = &enq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_2 = {1'h0, enq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T = _GEN_2 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_1 = _value_T[3:0]; // @[Counter.scala:77:24] wire wrap_1 = &deq_ptr_value; // @[Counter.scala:61:40, :73:24] wire [4:0] _GEN_3 = {1'h0, deq_ptr_value}; // @[Counter.scala:61:40, :77:24] wire [4:0] _value_T_2 = _GEN_3 + 5'h1; // @[Counter.scala:77:24] wire [3:0] _value_T_3 = _value_T_2[3:0]; // @[Counter.scala:77:24] assign _io_enq_ready_T = ~full; // @[util.scala:474:24, :504:19] assign io_enq_ready_0 = _io_enq_ready_T; // @[util.scala:448:7, :504:19] assign io_deq_bits_uop_uopc_0 = out_uop_uopc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_inst_0 = out_uop_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_inst_0 = out_uop_debug_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_rvc_0 = out_uop_is_rvc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_pc_0 = out_uop_debug_pc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iq_type_0 = out_uop_iq_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fu_code_0 = out_uop_fu_code; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_br_type_0 = out_uop_ctrl_br_type; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op1_sel_0 = out_uop_ctrl_op1_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op2_sel_0 = out_uop_ctrl_op2_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_imm_sel_0 = out_uop_ctrl_imm_sel; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_op_fcn_0 = out_uop_ctrl_op_fcn; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_fcn_dw_0 = out_uop_ctrl_fcn_dw; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_csr_cmd_0 = out_uop_ctrl_csr_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_load_0 = out_uop_ctrl_is_load; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_sta_0 = out_uop_ctrl_is_sta; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ctrl_is_std_0 = out_uop_ctrl_is_std; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_state_0 = out_uop_iw_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p1_poisoned_0 = out_uop_iw_p1_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_iw_p2_poisoned_0 = out_uop_iw_p2_poisoned; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_br_0 = out_uop_is_br; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jalr_0 = out_uop_is_jalr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_jal_0 = out_uop_is_jal; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sfb_0 = out_uop_is_sfb; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_br_tag_0 = out_uop_br_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ftq_idx_0 = out_uop_ftq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_edge_inst_0 = out_uop_edge_inst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pc_lob_0 = out_uop_pc_lob; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_taken_0 = out_uop_taken; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_imm_packed_0 = out_uop_imm_packed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_csr_addr_0 = out_uop_csr_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rob_idx_0 = out_uop_rob_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldq_idx_0 = out_uop_ldq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stq_idx_0 = out_uop_stq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_rxq_idx_0 = out_uop_rxq_idx; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_pdst_0 = out_uop_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_0 = out_uop_prs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_0 = out_uop_prs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_0 = out_uop_prs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_0 = out_uop_ppred; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs1_busy_0 = out_uop_prs1_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs2_busy_0 = out_uop_prs2_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_prs3_busy_0 = out_uop_prs3_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ppred_busy_0 = out_uop_ppred_busy; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_stale_pdst_0 = out_uop_stale_pdst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exception_0 = out_uop_exception; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_exc_cause_0 = out_uop_exc_cause; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bypassable_0 = out_uop_bypassable; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_cmd_0 = out_uop_mem_cmd; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_size_0 = out_uop_mem_size; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_mem_signed_0 = out_uop_mem_signed; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fence_0 = out_uop_is_fence; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_fencei_0 = out_uop_is_fencei; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_amo_0 = out_uop_is_amo; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_ldq_0 = out_uop_uses_ldq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_uses_stq_0 = out_uop_uses_stq; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_sys_pc2epc_0 = out_uop_is_sys_pc2epc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_is_unique_0 = out_uop_is_unique; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_flush_on_commit_0 = out_uop_flush_on_commit; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_is_rs1_0 = out_uop_ldst_is_rs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_0 = out_uop_ldst; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_0 = out_uop_lrs1; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_0 = out_uop_lrs2; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs3_0 = out_uop_lrs3; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_ldst_val_0 = out_uop_ldst_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_dst_rtype_0 = out_uop_dst_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs1_rtype_0 = out_uop_lrs1_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_lrs2_rtype_0 = out_uop_lrs2_rtype; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_frs3_en_0 = out_uop_frs3_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_val_0 = out_uop_fp_val; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_fp_single_0 = out_uop_fp_single; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_pf_if_0 = out_uop_xcpt_pf_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ae_if_0 = out_uop_xcpt_ae_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_xcpt_ma_if_0 = out_uop_xcpt_ma_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_debug_if_0 = out_uop_bp_debug_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_bp_xcpt_if_0 = out_uop_bp_xcpt_if; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_fsrc_0 = out_uop_debug_fsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_uop_debug_tsrc_0 = out_uop_debug_tsrc; // @[util.scala:448:7, :506:17] assign io_deq_bits_addr_0 = out_addr; // @[util.scala:448:7, :506:17] assign io_deq_bits_data_0 = out_data; // @[util.scala:448:7, :506:17] assign io_deq_bits_is_hella_0 = out_is_hella; // @[util.scala:448:7, :506:17] assign io_deq_bits_tag_match_0 = out_tag_match; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_coh_state_0 = out_old_meta_coh_state; // @[util.scala:448:7, :506:17] assign io_deq_bits_old_meta_tag_0 = out_old_meta_tag; // @[util.scala:448:7, :506:17] assign io_deq_bits_way_en = out_way_en; // @[util.scala:448:7, :506:17] assign io_deq_bits_sdq_id_0 = out_sdq_id; // @[util.scala:448:7, :506:17] wire [15:0] out_uop_br_mask; // @[util.scala:506:17] wire [15:0][6:0] _GEN_4 = {{uops_15_uopc}, {uops_14_uopc}, {uops_13_uopc}, {uops_12_uopc}, {uops_11_uopc}, {uops_10_uopc}, {uops_9_uopc}, {uops_8_uopc}, {uops_7_uopc}, {uops_6_uopc}, {uops_5_uopc}, {uops_4_uopc}, {uops_3_uopc}, {uops_2_uopc}, {uops_1_uopc}, {uops_0_uopc}}; // @[util.scala:466:20, :508:19] assign out_uop_uopc = _GEN_4[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_5 = {{uops_15_inst}, {uops_14_inst}, {uops_13_inst}, {uops_12_inst}, {uops_11_inst}, {uops_10_inst}, {uops_9_inst}, {uops_8_inst}, {uops_7_inst}, {uops_6_inst}, {uops_5_inst}, {uops_4_inst}, {uops_3_inst}, {uops_2_inst}, {uops_1_inst}, {uops_0_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_inst = _GEN_5[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][31:0] _GEN_6 = {{uops_15_debug_inst}, {uops_14_debug_inst}, {uops_13_debug_inst}, {uops_12_debug_inst}, {uops_11_debug_inst}, {uops_10_debug_inst}, {uops_9_debug_inst}, {uops_8_debug_inst}, {uops_7_debug_inst}, {uops_6_debug_inst}, {uops_5_debug_inst}, {uops_4_debug_inst}, {uops_3_debug_inst}, {uops_2_debug_inst}, {uops_1_debug_inst}, {uops_0_debug_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_inst = _GEN_6[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_7 = {{uops_15_is_rvc}, {uops_14_is_rvc}, {uops_13_is_rvc}, {uops_12_is_rvc}, {uops_11_is_rvc}, {uops_10_is_rvc}, {uops_9_is_rvc}, {uops_8_is_rvc}, {uops_7_is_rvc}, {uops_6_is_rvc}, {uops_5_is_rvc}, {uops_4_is_rvc}, {uops_3_is_rvc}, {uops_2_is_rvc}, {uops_1_is_rvc}, {uops_0_is_rvc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_rvc = _GEN_7[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][39:0] _GEN_8 = {{uops_15_debug_pc}, {uops_14_debug_pc}, {uops_13_debug_pc}, {uops_12_debug_pc}, {uops_11_debug_pc}, {uops_10_debug_pc}, {uops_9_debug_pc}, {uops_8_debug_pc}, {uops_7_debug_pc}, {uops_6_debug_pc}, {uops_5_debug_pc}, {uops_4_debug_pc}, {uops_3_debug_pc}, {uops_2_debug_pc}, {uops_1_debug_pc}, {uops_0_debug_pc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_pc = _GEN_8[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_9 = {{uops_15_iq_type}, {uops_14_iq_type}, {uops_13_iq_type}, {uops_12_iq_type}, {uops_11_iq_type}, {uops_10_iq_type}, {uops_9_iq_type}, {uops_8_iq_type}, {uops_7_iq_type}, {uops_6_iq_type}, {uops_5_iq_type}, {uops_4_iq_type}, {uops_3_iq_type}, {uops_2_iq_type}, {uops_1_iq_type}, {uops_0_iq_type}}; // @[util.scala:466:20, :508:19] assign out_uop_iq_type = _GEN_9[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][9:0] _GEN_10 = {{uops_15_fu_code}, {uops_14_fu_code}, {uops_13_fu_code}, {uops_12_fu_code}, {uops_11_fu_code}, {uops_10_fu_code}, {uops_9_fu_code}, {uops_8_fu_code}, {uops_7_fu_code}, {uops_6_fu_code}, {uops_5_fu_code}, {uops_4_fu_code}, {uops_3_fu_code}, {uops_2_fu_code}, {uops_1_fu_code}, {uops_0_fu_code}}; // @[util.scala:466:20, :508:19] assign out_uop_fu_code = _GEN_10[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_11 = {{uops_15_ctrl_br_type}, {uops_14_ctrl_br_type}, {uops_13_ctrl_br_type}, {uops_12_ctrl_br_type}, {uops_11_ctrl_br_type}, {uops_10_ctrl_br_type}, {uops_9_ctrl_br_type}, {uops_8_ctrl_br_type}, {uops_7_ctrl_br_type}, {uops_6_ctrl_br_type}, {uops_5_ctrl_br_type}, {uops_4_ctrl_br_type}, {uops_3_ctrl_br_type}, {uops_2_ctrl_br_type}, {uops_1_ctrl_br_type}, {uops_0_ctrl_br_type}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_br_type = _GEN_11[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_12 = {{uops_15_ctrl_op1_sel}, {uops_14_ctrl_op1_sel}, {uops_13_ctrl_op1_sel}, {uops_12_ctrl_op1_sel}, {uops_11_ctrl_op1_sel}, {uops_10_ctrl_op1_sel}, {uops_9_ctrl_op1_sel}, {uops_8_ctrl_op1_sel}, {uops_7_ctrl_op1_sel}, {uops_6_ctrl_op1_sel}, {uops_5_ctrl_op1_sel}, {uops_4_ctrl_op1_sel}, {uops_3_ctrl_op1_sel}, {uops_2_ctrl_op1_sel}, {uops_1_ctrl_op1_sel}, {uops_0_ctrl_op1_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op1_sel = _GEN_12[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_13 = {{uops_15_ctrl_op2_sel}, {uops_14_ctrl_op2_sel}, {uops_13_ctrl_op2_sel}, {uops_12_ctrl_op2_sel}, {uops_11_ctrl_op2_sel}, {uops_10_ctrl_op2_sel}, {uops_9_ctrl_op2_sel}, {uops_8_ctrl_op2_sel}, {uops_7_ctrl_op2_sel}, {uops_6_ctrl_op2_sel}, {uops_5_ctrl_op2_sel}, {uops_4_ctrl_op2_sel}, {uops_3_ctrl_op2_sel}, {uops_2_ctrl_op2_sel}, {uops_1_ctrl_op2_sel}, {uops_0_ctrl_op2_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op2_sel = _GEN_13[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_14 = {{uops_15_ctrl_imm_sel}, {uops_14_ctrl_imm_sel}, {uops_13_ctrl_imm_sel}, {uops_12_ctrl_imm_sel}, {uops_11_ctrl_imm_sel}, {uops_10_ctrl_imm_sel}, {uops_9_ctrl_imm_sel}, {uops_8_ctrl_imm_sel}, {uops_7_ctrl_imm_sel}, {uops_6_ctrl_imm_sel}, {uops_5_ctrl_imm_sel}, {uops_4_ctrl_imm_sel}, {uops_3_ctrl_imm_sel}, {uops_2_ctrl_imm_sel}, {uops_1_ctrl_imm_sel}, {uops_0_ctrl_imm_sel}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_imm_sel = _GEN_14[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_15 = {{uops_15_ctrl_op_fcn}, {uops_14_ctrl_op_fcn}, {uops_13_ctrl_op_fcn}, {uops_12_ctrl_op_fcn}, {uops_11_ctrl_op_fcn}, {uops_10_ctrl_op_fcn}, {uops_9_ctrl_op_fcn}, {uops_8_ctrl_op_fcn}, {uops_7_ctrl_op_fcn}, {uops_6_ctrl_op_fcn}, {uops_5_ctrl_op_fcn}, {uops_4_ctrl_op_fcn}, {uops_3_ctrl_op_fcn}, {uops_2_ctrl_op_fcn}, {uops_1_ctrl_op_fcn}, {uops_0_ctrl_op_fcn}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_op_fcn = _GEN_15[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_16 = {{uops_15_ctrl_fcn_dw}, {uops_14_ctrl_fcn_dw}, {uops_13_ctrl_fcn_dw}, {uops_12_ctrl_fcn_dw}, {uops_11_ctrl_fcn_dw}, {uops_10_ctrl_fcn_dw}, {uops_9_ctrl_fcn_dw}, {uops_8_ctrl_fcn_dw}, {uops_7_ctrl_fcn_dw}, {uops_6_ctrl_fcn_dw}, {uops_5_ctrl_fcn_dw}, {uops_4_ctrl_fcn_dw}, {uops_3_ctrl_fcn_dw}, {uops_2_ctrl_fcn_dw}, {uops_1_ctrl_fcn_dw}, {uops_0_ctrl_fcn_dw}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_fcn_dw = _GEN_16[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][2:0] _GEN_17 = {{uops_15_ctrl_csr_cmd}, {uops_14_ctrl_csr_cmd}, {uops_13_ctrl_csr_cmd}, {uops_12_ctrl_csr_cmd}, {uops_11_ctrl_csr_cmd}, {uops_10_ctrl_csr_cmd}, {uops_9_ctrl_csr_cmd}, {uops_8_ctrl_csr_cmd}, {uops_7_ctrl_csr_cmd}, {uops_6_ctrl_csr_cmd}, {uops_5_ctrl_csr_cmd}, {uops_4_ctrl_csr_cmd}, {uops_3_ctrl_csr_cmd}, {uops_2_ctrl_csr_cmd}, {uops_1_ctrl_csr_cmd}, {uops_0_ctrl_csr_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_csr_cmd = _GEN_17[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_18 = {{uops_15_ctrl_is_load}, {uops_14_ctrl_is_load}, {uops_13_ctrl_is_load}, {uops_12_ctrl_is_load}, {uops_11_ctrl_is_load}, {uops_10_ctrl_is_load}, {uops_9_ctrl_is_load}, {uops_8_ctrl_is_load}, {uops_7_ctrl_is_load}, {uops_6_ctrl_is_load}, {uops_5_ctrl_is_load}, {uops_4_ctrl_is_load}, {uops_3_ctrl_is_load}, {uops_2_ctrl_is_load}, {uops_1_ctrl_is_load}, {uops_0_ctrl_is_load}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_load = _GEN_18[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_19 = {{uops_15_ctrl_is_sta}, {uops_14_ctrl_is_sta}, {uops_13_ctrl_is_sta}, {uops_12_ctrl_is_sta}, {uops_11_ctrl_is_sta}, {uops_10_ctrl_is_sta}, {uops_9_ctrl_is_sta}, {uops_8_ctrl_is_sta}, {uops_7_ctrl_is_sta}, {uops_6_ctrl_is_sta}, {uops_5_ctrl_is_sta}, {uops_4_ctrl_is_sta}, {uops_3_ctrl_is_sta}, {uops_2_ctrl_is_sta}, {uops_1_ctrl_is_sta}, {uops_0_ctrl_is_sta}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_sta = _GEN_19[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_20 = {{uops_15_ctrl_is_std}, {uops_14_ctrl_is_std}, {uops_13_ctrl_is_std}, {uops_12_ctrl_is_std}, {uops_11_ctrl_is_std}, {uops_10_ctrl_is_std}, {uops_9_ctrl_is_std}, {uops_8_ctrl_is_std}, {uops_7_ctrl_is_std}, {uops_6_ctrl_is_std}, {uops_5_ctrl_is_std}, {uops_4_ctrl_is_std}, {uops_3_ctrl_is_std}, {uops_2_ctrl_is_std}, {uops_1_ctrl_is_std}, {uops_0_ctrl_is_std}}; // @[util.scala:466:20, :508:19] assign out_uop_ctrl_is_std = _GEN_20[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_21 = {{uops_15_iw_state}, {uops_14_iw_state}, {uops_13_iw_state}, {uops_12_iw_state}, {uops_11_iw_state}, {uops_10_iw_state}, {uops_9_iw_state}, {uops_8_iw_state}, {uops_7_iw_state}, {uops_6_iw_state}, {uops_5_iw_state}, {uops_4_iw_state}, {uops_3_iw_state}, {uops_2_iw_state}, {uops_1_iw_state}, {uops_0_iw_state}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_state = _GEN_21[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_22 = {{uops_15_iw_p1_poisoned}, {uops_14_iw_p1_poisoned}, {uops_13_iw_p1_poisoned}, {uops_12_iw_p1_poisoned}, {uops_11_iw_p1_poisoned}, {uops_10_iw_p1_poisoned}, {uops_9_iw_p1_poisoned}, {uops_8_iw_p1_poisoned}, {uops_7_iw_p1_poisoned}, {uops_6_iw_p1_poisoned}, {uops_5_iw_p1_poisoned}, {uops_4_iw_p1_poisoned}, {uops_3_iw_p1_poisoned}, {uops_2_iw_p1_poisoned}, {uops_1_iw_p1_poisoned}, {uops_0_iw_p1_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p1_poisoned = _GEN_22[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_23 = {{uops_15_iw_p2_poisoned}, {uops_14_iw_p2_poisoned}, {uops_13_iw_p2_poisoned}, {uops_12_iw_p2_poisoned}, {uops_11_iw_p2_poisoned}, {uops_10_iw_p2_poisoned}, {uops_9_iw_p2_poisoned}, {uops_8_iw_p2_poisoned}, {uops_7_iw_p2_poisoned}, {uops_6_iw_p2_poisoned}, {uops_5_iw_p2_poisoned}, {uops_4_iw_p2_poisoned}, {uops_3_iw_p2_poisoned}, {uops_2_iw_p2_poisoned}, {uops_1_iw_p2_poisoned}, {uops_0_iw_p2_poisoned}}; // @[util.scala:466:20, :508:19] assign out_uop_iw_p2_poisoned = _GEN_23[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_24 = {{uops_15_is_br}, {uops_14_is_br}, {uops_13_is_br}, {uops_12_is_br}, {uops_11_is_br}, {uops_10_is_br}, {uops_9_is_br}, {uops_8_is_br}, {uops_7_is_br}, {uops_6_is_br}, {uops_5_is_br}, {uops_4_is_br}, {uops_3_is_br}, {uops_2_is_br}, {uops_1_is_br}, {uops_0_is_br}}; // @[util.scala:466:20, :508:19] assign out_uop_is_br = _GEN_24[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_25 = {{uops_15_is_jalr}, {uops_14_is_jalr}, {uops_13_is_jalr}, {uops_12_is_jalr}, {uops_11_is_jalr}, {uops_10_is_jalr}, {uops_9_is_jalr}, {uops_8_is_jalr}, {uops_7_is_jalr}, {uops_6_is_jalr}, {uops_5_is_jalr}, {uops_4_is_jalr}, {uops_3_is_jalr}, {uops_2_is_jalr}, {uops_1_is_jalr}, {uops_0_is_jalr}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jalr = _GEN_25[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_26 = {{uops_15_is_jal}, {uops_14_is_jal}, {uops_13_is_jal}, {uops_12_is_jal}, {uops_11_is_jal}, {uops_10_is_jal}, {uops_9_is_jal}, {uops_8_is_jal}, {uops_7_is_jal}, {uops_6_is_jal}, {uops_5_is_jal}, {uops_4_is_jal}, {uops_3_is_jal}, {uops_2_is_jal}, {uops_1_is_jal}, {uops_0_is_jal}}; // @[util.scala:466:20, :508:19] assign out_uop_is_jal = _GEN_26[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_27 = {{uops_15_is_sfb}, {uops_14_is_sfb}, {uops_13_is_sfb}, {uops_12_is_sfb}, {uops_11_is_sfb}, {uops_10_is_sfb}, {uops_9_is_sfb}, {uops_8_is_sfb}, {uops_7_is_sfb}, {uops_6_is_sfb}, {uops_5_is_sfb}, {uops_4_is_sfb}, {uops_3_is_sfb}, {uops_2_is_sfb}, {uops_1_is_sfb}, {uops_0_is_sfb}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sfb = _GEN_27[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][15:0] _GEN_28 = {{uops_15_br_mask}, {uops_14_br_mask}, {uops_13_br_mask}, {uops_12_br_mask}, {uops_11_br_mask}, {uops_10_br_mask}, {uops_9_br_mask}, {uops_8_br_mask}, {uops_7_br_mask}, {uops_6_br_mask}, {uops_5_br_mask}, {uops_4_br_mask}, {uops_3_br_mask}, {uops_2_br_mask}, {uops_1_br_mask}, {uops_0_br_mask}}; // @[util.scala:466:20, :508:19] assign out_uop_br_mask = _GEN_28[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][3:0] _GEN_29 = {{uops_15_br_tag}, {uops_14_br_tag}, {uops_13_br_tag}, {uops_12_br_tag}, {uops_11_br_tag}, {uops_10_br_tag}, {uops_9_br_tag}, {uops_8_br_tag}, {uops_7_br_tag}, {uops_6_br_tag}, {uops_5_br_tag}, {uops_4_br_tag}, {uops_3_br_tag}, {uops_2_br_tag}, {uops_1_br_tag}, {uops_0_br_tag}}; // @[util.scala:466:20, :508:19] assign out_uop_br_tag = _GEN_29[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_30 = {{uops_15_ftq_idx}, {uops_14_ftq_idx}, {uops_13_ftq_idx}, {uops_12_ftq_idx}, {uops_11_ftq_idx}, {uops_10_ftq_idx}, {uops_9_ftq_idx}, {uops_8_ftq_idx}, {uops_7_ftq_idx}, {uops_6_ftq_idx}, {uops_5_ftq_idx}, {uops_4_ftq_idx}, {uops_3_ftq_idx}, {uops_2_ftq_idx}, {uops_1_ftq_idx}, {uops_0_ftq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ftq_idx = _GEN_30[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_31 = {{uops_15_edge_inst}, {uops_14_edge_inst}, {uops_13_edge_inst}, {uops_12_edge_inst}, {uops_11_edge_inst}, {uops_10_edge_inst}, {uops_9_edge_inst}, {uops_8_edge_inst}, {uops_7_edge_inst}, {uops_6_edge_inst}, {uops_5_edge_inst}, {uops_4_edge_inst}, {uops_3_edge_inst}, {uops_2_edge_inst}, {uops_1_edge_inst}, {uops_0_edge_inst}}; // @[util.scala:466:20, :508:19] assign out_uop_edge_inst = _GEN_31[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_32 = {{uops_15_pc_lob}, {uops_14_pc_lob}, {uops_13_pc_lob}, {uops_12_pc_lob}, {uops_11_pc_lob}, {uops_10_pc_lob}, {uops_9_pc_lob}, {uops_8_pc_lob}, {uops_7_pc_lob}, {uops_6_pc_lob}, {uops_5_pc_lob}, {uops_4_pc_lob}, {uops_3_pc_lob}, {uops_2_pc_lob}, {uops_1_pc_lob}, {uops_0_pc_lob}}; // @[util.scala:466:20, :508:19] assign out_uop_pc_lob = _GEN_32[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_33 = {{uops_15_taken}, {uops_14_taken}, {uops_13_taken}, {uops_12_taken}, {uops_11_taken}, {uops_10_taken}, {uops_9_taken}, {uops_8_taken}, {uops_7_taken}, {uops_6_taken}, {uops_5_taken}, {uops_4_taken}, {uops_3_taken}, {uops_2_taken}, {uops_1_taken}, {uops_0_taken}}; // @[util.scala:466:20, :508:19] assign out_uop_taken = _GEN_33[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][19:0] _GEN_34 = {{uops_15_imm_packed}, {uops_14_imm_packed}, {uops_13_imm_packed}, {uops_12_imm_packed}, {uops_11_imm_packed}, {uops_10_imm_packed}, {uops_9_imm_packed}, {uops_8_imm_packed}, {uops_7_imm_packed}, {uops_6_imm_packed}, {uops_5_imm_packed}, {uops_4_imm_packed}, {uops_3_imm_packed}, {uops_2_imm_packed}, {uops_1_imm_packed}, {uops_0_imm_packed}}; // @[util.scala:466:20, :508:19] assign out_uop_imm_packed = _GEN_34[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][11:0] _GEN_35 = {{uops_15_csr_addr}, {uops_14_csr_addr}, {uops_13_csr_addr}, {uops_12_csr_addr}, {uops_11_csr_addr}, {uops_10_csr_addr}, {uops_9_csr_addr}, {uops_8_csr_addr}, {uops_7_csr_addr}, {uops_6_csr_addr}, {uops_5_csr_addr}, {uops_4_csr_addr}, {uops_3_csr_addr}, {uops_2_csr_addr}, {uops_1_csr_addr}, {uops_0_csr_addr}}; // @[util.scala:466:20, :508:19] assign out_uop_csr_addr = _GEN_35[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_36 = {{uops_15_rob_idx}, {uops_14_rob_idx}, {uops_13_rob_idx}, {uops_12_rob_idx}, {uops_11_rob_idx}, {uops_10_rob_idx}, {uops_9_rob_idx}, {uops_8_rob_idx}, {uops_7_rob_idx}, {uops_6_rob_idx}, {uops_5_rob_idx}, {uops_4_rob_idx}, {uops_3_rob_idx}, {uops_2_rob_idx}, {uops_1_rob_idx}, {uops_0_rob_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rob_idx = _GEN_36[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_37 = {{uops_15_ldq_idx}, {uops_14_ldq_idx}, {uops_13_ldq_idx}, {uops_12_ldq_idx}, {uops_11_ldq_idx}, {uops_10_ldq_idx}, {uops_9_ldq_idx}, {uops_8_ldq_idx}, {uops_7_ldq_idx}, {uops_6_ldq_idx}, {uops_5_ldq_idx}, {uops_4_ldq_idx}, {uops_3_ldq_idx}, {uops_2_ldq_idx}, {uops_1_ldq_idx}, {uops_0_ldq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_ldq_idx = _GEN_37[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_38 = {{uops_15_stq_idx}, {uops_14_stq_idx}, {uops_13_stq_idx}, {uops_12_stq_idx}, {uops_11_stq_idx}, {uops_10_stq_idx}, {uops_9_stq_idx}, {uops_8_stq_idx}, {uops_7_stq_idx}, {uops_6_stq_idx}, {uops_5_stq_idx}, {uops_4_stq_idx}, {uops_3_stq_idx}, {uops_2_stq_idx}, {uops_1_stq_idx}, {uops_0_stq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_stq_idx = _GEN_38[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_39 = {{uops_15_rxq_idx}, {uops_14_rxq_idx}, {uops_13_rxq_idx}, {uops_12_rxq_idx}, {uops_11_rxq_idx}, {uops_10_rxq_idx}, {uops_9_rxq_idx}, {uops_8_rxq_idx}, {uops_7_rxq_idx}, {uops_6_rxq_idx}, {uops_5_rxq_idx}, {uops_4_rxq_idx}, {uops_3_rxq_idx}, {uops_2_rxq_idx}, {uops_1_rxq_idx}, {uops_0_rxq_idx}}; // @[util.scala:466:20, :508:19] assign out_uop_rxq_idx = _GEN_39[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_40 = {{uops_15_pdst}, {uops_14_pdst}, {uops_13_pdst}, {uops_12_pdst}, {uops_11_pdst}, {uops_10_pdst}, {uops_9_pdst}, {uops_8_pdst}, {uops_7_pdst}, {uops_6_pdst}, {uops_5_pdst}, {uops_4_pdst}, {uops_3_pdst}, {uops_2_pdst}, {uops_1_pdst}, {uops_0_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_pdst = _GEN_40[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_41 = {{uops_15_prs1}, {uops_14_prs1}, {uops_13_prs1}, {uops_12_prs1}, {uops_11_prs1}, {uops_10_prs1}, {uops_9_prs1}, {uops_8_prs1}, {uops_7_prs1}, {uops_6_prs1}, {uops_5_prs1}, {uops_4_prs1}, {uops_3_prs1}, {uops_2_prs1}, {uops_1_prs1}, {uops_0_prs1}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1 = _GEN_41[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_42 = {{uops_15_prs2}, {uops_14_prs2}, {uops_13_prs2}, {uops_12_prs2}, {uops_11_prs2}, {uops_10_prs2}, {uops_9_prs2}, {uops_8_prs2}, {uops_7_prs2}, {uops_6_prs2}, {uops_5_prs2}, {uops_4_prs2}, {uops_3_prs2}, {uops_2_prs2}, {uops_1_prs2}, {uops_0_prs2}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2 = _GEN_42[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_43 = {{uops_15_prs3}, {uops_14_prs3}, {uops_13_prs3}, {uops_12_prs3}, {uops_11_prs3}, {uops_10_prs3}, {uops_9_prs3}, {uops_8_prs3}, {uops_7_prs3}, {uops_6_prs3}, {uops_5_prs3}, {uops_4_prs3}, {uops_3_prs3}, {uops_2_prs3}, {uops_1_prs3}, {uops_0_prs3}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3 = _GEN_43[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_44 = {{uops_15_ppred}, {uops_14_ppred}, {uops_13_ppred}, {uops_12_ppred}, {uops_11_ppred}, {uops_10_ppred}, {uops_9_ppred}, {uops_8_ppred}, {uops_7_ppred}, {uops_6_ppred}, {uops_5_ppred}, {uops_4_ppred}, {uops_3_ppred}, {uops_2_ppred}, {uops_1_ppred}, {uops_0_ppred}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred = _GEN_44[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_45 = {{uops_15_prs1_busy}, {uops_14_prs1_busy}, {uops_13_prs1_busy}, {uops_12_prs1_busy}, {uops_11_prs1_busy}, {uops_10_prs1_busy}, {uops_9_prs1_busy}, {uops_8_prs1_busy}, {uops_7_prs1_busy}, {uops_6_prs1_busy}, {uops_5_prs1_busy}, {uops_4_prs1_busy}, {uops_3_prs1_busy}, {uops_2_prs1_busy}, {uops_1_prs1_busy}, {uops_0_prs1_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs1_busy = _GEN_45[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_46 = {{uops_15_prs2_busy}, {uops_14_prs2_busy}, {uops_13_prs2_busy}, {uops_12_prs2_busy}, {uops_11_prs2_busy}, {uops_10_prs2_busy}, {uops_9_prs2_busy}, {uops_8_prs2_busy}, {uops_7_prs2_busy}, {uops_6_prs2_busy}, {uops_5_prs2_busy}, {uops_4_prs2_busy}, {uops_3_prs2_busy}, {uops_2_prs2_busy}, {uops_1_prs2_busy}, {uops_0_prs2_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs2_busy = _GEN_46[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_47 = {{uops_15_prs3_busy}, {uops_14_prs3_busy}, {uops_13_prs3_busy}, {uops_12_prs3_busy}, {uops_11_prs3_busy}, {uops_10_prs3_busy}, {uops_9_prs3_busy}, {uops_8_prs3_busy}, {uops_7_prs3_busy}, {uops_6_prs3_busy}, {uops_5_prs3_busy}, {uops_4_prs3_busy}, {uops_3_prs3_busy}, {uops_2_prs3_busy}, {uops_1_prs3_busy}, {uops_0_prs3_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_prs3_busy = _GEN_47[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_48 = {{uops_15_ppred_busy}, {uops_14_ppred_busy}, {uops_13_ppred_busy}, {uops_12_ppred_busy}, {uops_11_ppred_busy}, {uops_10_ppred_busy}, {uops_9_ppred_busy}, {uops_8_ppred_busy}, {uops_7_ppred_busy}, {uops_6_ppred_busy}, {uops_5_ppred_busy}, {uops_4_ppred_busy}, {uops_3_ppred_busy}, {uops_2_ppred_busy}, {uops_1_ppred_busy}, {uops_0_ppred_busy}}; // @[util.scala:466:20, :508:19] assign out_uop_ppred_busy = _GEN_48[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][6:0] _GEN_49 = {{uops_15_stale_pdst}, {uops_14_stale_pdst}, {uops_13_stale_pdst}, {uops_12_stale_pdst}, {uops_11_stale_pdst}, {uops_10_stale_pdst}, {uops_9_stale_pdst}, {uops_8_stale_pdst}, {uops_7_stale_pdst}, {uops_6_stale_pdst}, {uops_5_stale_pdst}, {uops_4_stale_pdst}, {uops_3_stale_pdst}, {uops_2_stale_pdst}, {uops_1_stale_pdst}, {uops_0_stale_pdst}}; // @[util.scala:466:20, :508:19] assign out_uop_stale_pdst = _GEN_49[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_50 = {{uops_15_exception}, {uops_14_exception}, {uops_13_exception}, {uops_12_exception}, {uops_11_exception}, {uops_10_exception}, {uops_9_exception}, {uops_8_exception}, {uops_7_exception}, {uops_6_exception}, {uops_5_exception}, {uops_4_exception}, {uops_3_exception}, {uops_2_exception}, {uops_1_exception}, {uops_0_exception}}; // @[util.scala:466:20, :508:19] assign out_uop_exception = _GEN_50[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][63:0] _GEN_51 = {{uops_15_exc_cause}, {uops_14_exc_cause}, {uops_13_exc_cause}, {uops_12_exc_cause}, {uops_11_exc_cause}, {uops_10_exc_cause}, {uops_9_exc_cause}, {uops_8_exc_cause}, {uops_7_exc_cause}, {uops_6_exc_cause}, {uops_5_exc_cause}, {uops_4_exc_cause}, {uops_3_exc_cause}, {uops_2_exc_cause}, {uops_1_exc_cause}, {uops_0_exc_cause}}; // @[util.scala:466:20, :508:19] assign out_uop_exc_cause = _GEN_51[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_52 = {{uops_15_bypassable}, {uops_14_bypassable}, {uops_13_bypassable}, {uops_12_bypassable}, {uops_11_bypassable}, {uops_10_bypassable}, {uops_9_bypassable}, {uops_8_bypassable}, {uops_7_bypassable}, {uops_6_bypassable}, {uops_5_bypassable}, {uops_4_bypassable}, {uops_3_bypassable}, {uops_2_bypassable}, {uops_1_bypassable}, {uops_0_bypassable}}; // @[util.scala:466:20, :508:19] assign out_uop_bypassable = _GEN_52[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][4:0] _GEN_53 = {{uops_15_mem_cmd}, {uops_14_mem_cmd}, {uops_13_mem_cmd}, {uops_12_mem_cmd}, {uops_11_mem_cmd}, {uops_10_mem_cmd}, {uops_9_mem_cmd}, {uops_8_mem_cmd}, {uops_7_mem_cmd}, {uops_6_mem_cmd}, {uops_5_mem_cmd}, {uops_4_mem_cmd}, {uops_3_mem_cmd}, {uops_2_mem_cmd}, {uops_1_mem_cmd}, {uops_0_mem_cmd}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_cmd = _GEN_53[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_54 = {{uops_15_mem_size}, {uops_14_mem_size}, {uops_13_mem_size}, {uops_12_mem_size}, {uops_11_mem_size}, {uops_10_mem_size}, {uops_9_mem_size}, {uops_8_mem_size}, {uops_7_mem_size}, {uops_6_mem_size}, {uops_5_mem_size}, {uops_4_mem_size}, {uops_3_mem_size}, {uops_2_mem_size}, {uops_1_mem_size}, {uops_0_mem_size}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_size = _GEN_54[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_55 = {{uops_15_mem_signed}, {uops_14_mem_signed}, {uops_13_mem_signed}, {uops_12_mem_signed}, {uops_11_mem_signed}, {uops_10_mem_signed}, {uops_9_mem_signed}, {uops_8_mem_signed}, {uops_7_mem_signed}, {uops_6_mem_signed}, {uops_5_mem_signed}, {uops_4_mem_signed}, {uops_3_mem_signed}, {uops_2_mem_signed}, {uops_1_mem_signed}, {uops_0_mem_signed}}; // @[util.scala:466:20, :508:19] assign out_uop_mem_signed = _GEN_55[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_56 = {{uops_15_is_fence}, {uops_14_is_fence}, {uops_13_is_fence}, {uops_12_is_fence}, {uops_11_is_fence}, {uops_10_is_fence}, {uops_9_is_fence}, {uops_8_is_fence}, {uops_7_is_fence}, {uops_6_is_fence}, {uops_5_is_fence}, {uops_4_is_fence}, {uops_3_is_fence}, {uops_2_is_fence}, {uops_1_is_fence}, {uops_0_is_fence}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fence = _GEN_56[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_57 = {{uops_15_is_fencei}, {uops_14_is_fencei}, {uops_13_is_fencei}, {uops_12_is_fencei}, {uops_11_is_fencei}, {uops_10_is_fencei}, {uops_9_is_fencei}, {uops_8_is_fencei}, {uops_7_is_fencei}, {uops_6_is_fencei}, {uops_5_is_fencei}, {uops_4_is_fencei}, {uops_3_is_fencei}, {uops_2_is_fencei}, {uops_1_is_fencei}, {uops_0_is_fencei}}; // @[util.scala:466:20, :508:19] assign out_uop_is_fencei = _GEN_57[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_58 = {{uops_15_is_amo}, {uops_14_is_amo}, {uops_13_is_amo}, {uops_12_is_amo}, {uops_11_is_amo}, {uops_10_is_amo}, {uops_9_is_amo}, {uops_8_is_amo}, {uops_7_is_amo}, {uops_6_is_amo}, {uops_5_is_amo}, {uops_4_is_amo}, {uops_3_is_amo}, {uops_2_is_amo}, {uops_1_is_amo}, {uops_0_is_amo}}; // @[util.scala:466:20, :508:19] assign out_uop_is_amo = _GEN_58[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_59 = {{uops_15_uses_ldq}, {uops_14_uses_ldq}, {uops_13_uses_ldq}, {uops_12_uses_ldq}, {uops_11_uses_ldq}, {uops_10_uses_ldq}, {uops_9_uses_ldq}, {uops_8_uses_ldq}, {uops_7_uses_ldq}, {uops_6_uses_ldq}, {uops_5_uses_ldq}, {uops_4_uses_ldq}, {uops_3_uses_ldq}, {uops_2_uses_ldq}, {uops_1_uses_ldq}, {uops_0_uses_ldq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_ldq = _GEN_59[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_60 = {{uops_15_uses_stq}, {uops_14_uses_stq}, {uops_13_uses_stq}, {uops_12_uses_stq}, {uops_11_uses_stq}, {uops_10_uses_stq}, {uops_9_uses_stq}, {uops_8_uses_stq}, {uops_7_uses_stq}, {uops_6_uses_stq}, {uops_5_uses_stq}, {uops_4_uses_stq}, {uops_3_uses_stq}, {uops_2_uses_stq}, {uops_1_uses_stq}, {uops_0_uses_stq}}; // @[util.scala:466:20, :508:19] assign out_uop_uses_stq = _GEN_60[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_61 = {{uops_15_is_sys_pc2epc}, {uops_14_is_sys_pc2epc}, {uops_13_is_sys_pc2epc}, {uops_12_is_sys_pc2epc}, {uops_11_is_sys_pc2epc}, {uops_10_is_sys_pc2epc}, {uops_9_is_sys_pc2epc}, {uops_8_is_sys_pc2epc}, {uops_7_is_sys_pc2epc}, {uops_6_is_sys_pc2epc}, {uops_5_is_sys_pc2epc}, {uops_4_is_sys_pc2epc}, {uops_3_is_sys_pc2epc}, {uops_2_is_sys_pc2epc}, {uops_1_is_sys_pc2epc}, {uops_0_is_sys_pc2epc}}; // @[util.scala:466:20, :508:19] assign out_uop_is_sys_pc2epc = _GEN_61[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_62 = {{uops_15_is_unique}, {uops_14_is_unique}, {uops_13_is_unique}, {uops_12_is_unique}, {uops_11_is_unique}, {uops_10_is_unique}, {uops_9_is_unique}, {uops_8_is_unique}, {uops_7_is_unique}, {uops_6_is_unique}, {uops_5_is_unique}, {uops_4_is_unique}, {uops_3_is_unique}, {uops_2_is_unique}, {uops_1_is_unique}, {uops_0_is_unique}}; // @[util.scala:466:20, :508:19] assign out_uop_is_unique = _GEN_62[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_63 = {{uops_15_flush_on_commit}, {uops_14_flush_on_commit}, {uops_13_flush_on_commit}, {uops_12_flush_on_commit}, {uops_11_flush_on_commit}, {uops_10_flush_on_commit}, {uops_9_flush_on_commit}, {uops_8_flush_on_commit}, {uops_7_flush_on_commit}, {uops_6_flush_on_commit}, {uops_5_flush_on_commit}, {uops_4_flush_on_commit}, {uops_3_flush_on_commit}, {uops_2_flush_on_commit}, {uops_1_flush_on_commit}, {uops_0_flush_on_commit}}; // @[util.scala:466:20, :508:19] assign out_uop_flush_on_commit = _GEN_63[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_64 = {{uops_15_ldst_is_rs1}, {uops_14_ldst_is_rs1}, {uops_13_ldst_is_rs1}, {uops_12_ldst_is_rs1}, {uops_11_ldst_is_rs1}, {uops_10_ldst_is_rs1}, {uops_9_ldst_is_rs1}, {uops_8_ldst_is_rs1}, {uops_7_ldst_is_rs1}, {uops_6_ldst_is_rs1}, {uops_5_ldst_is_rs1}, {uops_4_ldst_is_rs1}, {uops_3_ldst_is_rs1}, {uops_2_ldst_is_rs1}, {uops_1_ldst_is_rs1}, {uops_0_ldst_is_rs1}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_is_rs1 = _GEN_64[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_65 = {{uops_15_ldst}, {uops_14_ldst}, {uops_13_ldst}, {uops_12_ldst}, {uops_11_ldst}, {uops_10_ldst}, {uops_9_ldst}, {uops_8_ldst}, {uops_7_ldst}, {uops_6_ldst}, {uops_5_ldst}, {uops_4_ldst}, {uops_3_ldst}, {uops_2_ldst}, {uops_1_ldst}, {uops_0_ldst}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst = _GEN_65[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_66 = {{uops_15_lrs1}, {uops_14_lrs1}, {uops_13_lrs1}, {uops_12_lrs1}, {uops_11_lrs1}, {uops_10_lrs1}, {uops_9_lrs1}, {uops_8_lrs1}, {uops_7_lrs1}, {uops_6_lrs1}, {uops_5_lrs1}, {uops_4_lrs1}, {uops_3_lrs1}, {uops_2_lrs1}, {uops_1_lrs1}, {uops_0_lrs1}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1 = _GEN_66[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_67 = {{uops_15_lrs2}, {uops_14_lrs2}, {uops_13_lrs2}, {uops_12_lrs2}, {uops_11_lrs2}, {uops_10_lrs2}, {uops_9_lrs2}, {uops_8_lrs2}, {uops_7_lrs2}, {uops_6_lrs2}, {uops_5_lrs2}, {uops_4_lrs2}, {uops_3_lrs2}, {uops_2_lrs2}, {uops_1_lrs2}, {uops_0_lrs2}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2 = _GEN_67[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][5:0] _GEN_68 = {{uops_15_lrs3}, {uops_14_lrs3}, {uops_13_lrs3}, {uops_12_lrs3}, {uops_11_lrs3}, {uops_10_lrs3}, {uops_9_lrs3}, {uops_8_lrs3}, {uops_7_lrs3}, {uops_6_lrs3}, {uops_5_lrs3}, {uops_4_lrs3}, {uops_3_lrs3}, {uops_2_lrs3}, {uops_1_lrs3}, {uops_0_lrs3}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs3 = _GEN_68[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_69 = {{uops_15_ldst_val}, {uops_14_ldst_val}, {uops_13_ldst_val}, {uops_12_ldst_val}, {uops_11_ldst_val}, {uops_10_ldst_val}, {uops_9_ldst_val}, {uops_8_ldst_val}, {uops_7_ldst_val}, {uops_6_ldst_val}, {uops_5_ldst_val}, {uops_4_ldst_val}, {uops_3_ldst_val}, {uops_2_ldst_val}, {uops_1_ldst_val}, {uops_0_ldst_val}}; // @[util.scala:466:20, :508:19] assign out_uop_ldst_val = _GEN_69[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_70 = {{uops_15_dst_rtype}, {uops_14_dst_rtype}, {uops_13_dst_rtype}, {uops_12_dst_rtype}, {uops_11_dst_rtype}, {uops_10_dst_rtype}, {uops_9_dst_rtype}, {uops_8_dst_rtype}, {uops_7_dst_rtype}, {uops_6_dst_rtype}, {uops_5_dst_rtype}, {uops_4_dst_rtype}, {uops_3_dst_rtype}, {uops_2_dst_rtype}, {uops_1_dst_rtype}, {uops_0_dst_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_dst_rtype = _GEN_70[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_71 = {{uops_15_lrs1_rtype}, {uops_14_lrs1_rtype}, {uops_13_lrs1_rtype}, {uops_12_lrs1_rtype}, {uops_11_lrs1_rtype}, {uops_10_lrs1_rtype}, {uops_9_lrs1_rtype}, {uops_8_lrs1_rtype}, {uops_7_lrs1_rtype}, {uops_6_lrs1_rtype}, {uops_5_lrs1_rtype}, {uops_4_lrs1_rtype}, {uops_3_lrs1_rtype}, {uops_2_lrs1_rtype}, {uops_1_lrs1_rtype}, {uops_0_lrs1_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs1_rtype = _GEN_71[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_72 = {{uops_15_lrs2_rtype}, {uops_14_lrs2_rtype}, {uops_13_lrs2_rtype}, {uops_12_lrs2_rtype}, {uops_11_lrs2_rtype}, {uops_10_lrs2_rtype}, {uops_9_lrs2_rtype}, {uops_8_lrs2_rtype}, {uops_7_lrs2_rtype}, {uops_6_lrs2_rtype}, {uops_5_lrs2_rtype}, {uops_4_lrs2_rtype}, {uops_3_lrs2_rtype}, {uops_2_lrs2_rtype}, {uops_1_lrs2_rtype}, {uops_0_lrs2_rtype}}; // @[util.scala:466:20, :508:19] assign out_uop_lrs2_rtype = _GEN_72[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_73 = {{uops_15_frs3_en}, {uops_14_frs3_en}, {uops_13_frs3_en}, {uops_12_frs3_en}, {uops_11_frs3_en}, {uops_10_frs3_en}, {uops_9_frs3_en}, {uops_8_frs3_en}, {uops_7_frs3_en}, {uops_6_frs3_en}, {uops_5_frs3_en}, {uops_4_frs3_en}, {uops_3_frs3_en}, {uops_2_frs3_en}, {uops_1_frs3_en}, {uops_0_frs3_en}}; // @[util.scala:466:20, :508:19] assign out_uop_frs3_en = _GEN_73[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_74 = {{uops_15_fp_val}, {uops_14_fp_val}, {uops_13_fp_val}, {uops_12_fp_val}, {uops_11_fp_val}, {uops_10_fp_val}, {uops_9_fp_val}, {uops_8_fp_val}, {uops_7_fp_val}, {uops_6_fp_val}, {uops_5_fp_val}, {uops_4_fp_val}, {uops_3_fp_val}, {uops_2_fp_val}, {uops_1_fp_val}, {uops_0_fp_val}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_val = _GEN_74[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_75 = {{uops_15_fp_single}, {uops_14_fp_single}, {uops_13_fp_single}, {uops_12_fp_single}, {uops_11_fp_single}, {uops_10_fp_single}, {uops_9_fp_single}, {uops_8_fp_single}, {uops_7_fp_single}, {uops_6_fp_single}, {uops_5_fp_single}, {uops_4_fp_single}, {uops_3_fp_single}, {uops_2_fp_single}, {uops_1_fp_single}, {uops_0_fp_single}}; // @[util.scala:466:20, :508:19] assign out_uop_fp_single = _GEN_75[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_76 = {{uops_15_xcpt_pf_if}, {uops_14_xcpt_pf_if}, {uops_13_xcpt_pf_if}, {uops_12_xcpt_pf_if}, {uops_11_xcpt_pf_if}, {uops_10_xcpt_pf_if}, {uops_9_xcpt_pf_if}, {uops_8_xcpt_pf_if}, {uops_7_xcpt_pf_if}, {uops_6_xcpt_pf_if}, {uops_5_xcpt_pf_if}, {uops_4_xcpt_pf_if}, {uops_3_xcpt_pf_if}, {uops_2_xcpt_pf_if}, {uops_1_xcpt_pf_if}, {uops_0_xcpt_pf_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_pf_if = _GEN_76[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_77 = {{uops_15_xcpt_ae_if}, {uops_14_xcpt_ae_if}, {uops_13_xcpt_ae_if}, {uops_12_xcpt_ae_if}, {uops_11_xcpt_ae_if}, {uops_10_xcpt_ae_if}, {uops_9_xcpt_ae_if}, {uops_8_xcpt_ae_if}, {uops_7_xcpt_ae_if}, {uops_6_xcpt_ae_if}, {uops_5_xcpt_ae_if}, {uops_4_xcpt_ae_if}, {uops_3_xcpt_ae_if}, {uops_2_xcpt_ae_if}, {uops_1_xcpt_ae_if}, {uops_0_xcpt_ae_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ae_if = _GEN_77[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_78 = {{uops_15_xcpt_ma_if}, {uops_14_xcpt_ma_if}, {uops_13_xcpt_ma_if}, {uops_12_xcpt_ma_if}, {uops_11_xcpt_ma_if}, {uops_10_xcpt_ma_if}, {uops_9_xcpt_ma_if}, {uops_8_xcpt_ma_if}, {uops_7_xcpt_ma_if}, {uops_6_xcpt_ma_if}, {uops_5_xcpt_ma_if}, {uops_4_xcpt_ma_if}, {uops_3_xcpt_ma_if}, {uops_2_xcpt_ma_if}, {uops_1_xcpt_ma_if}, {uops_0_xcpt_ma_if}}; // @[util.scala:466:20, :508:19] assign out_uop_xcpt_ma_if = _GEN_78[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_79 = {{uops_15_bp_debug_if}, {uops_14_bp_debug_if}, {uops_13_bp_debug_if}, {uops_12_bp_debug_if}, {uops_11_bp_debug_if}, {uops_10_bp_debug_if}, {uops_9_bp_debug_if}, {uops_8_bp_debug_if}, {uops_7_bp_debug_if}, {uops_6_bp_debug_if}, {uops_5_bp_debug_if}, {uops_4_bp_debug_if}, {uops_3_bp_debug_if}, {uops_2_bp_debug_if}, {uops_1_bp_debug_if}, {uops_0_bp_debug_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_debug_if = _GEN_79[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0] _GEN_80 = {{uops_15_bp_xcpt_if}, {uops_14_bp_xcpt_if}, {uops_13_bp_xcpt_if}, {uops_12_bp_xcpt_if}, {uops_11_bp_xcpt_if}, {uops_10_bp_xcpt_if}, {uops_9_bp_xcpt_if}, {uops_8_bp_xcpt_if}, {uops_7_bp_xcpt_if}, {uops_6_bp_xcpt_if}, {uops_5_bp_xcpt_if}, {uops_4_bp_xcpt_if}, {uops_3_bp_xcpt_if}, {uops_2_bp_xcpt_if}, {uops_1_bp_xcpt_if}, {uops_0_bp_xcpt_if}}; // @[util.scala:466:20, :508:19] assign out_uop_bp_xcpt_if = _GEN_80[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_81 = {{uops_15_debug_fsrc}, {uops_14_debug_fsrc}, {uops_13_debug_fsrc}, {uops_12_debug_fsrc}, {uops_11_debug_fsrc}, {uops_10_debug_fsrc}, {uops_9_debug_fsrc}, {uops_8_debug_fsrc}, {uops_7_debug_fsrc}, {uops_6_debug_fsrc}, {uops_5_debug_fsrc}, {uops_4_debug_fsrc}, {uops_3_debug_fsrc}, {uops_2_debug_fsrc}, {uops_1_debug_fsrc}, {uops_0_debug_fsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_fsrc = _GEN_81[deq_ptr_value]; // @[Counter.scala:61:40] wire [15:0][1:0] _GEN_82 = {{uops_15_debug_tsrc}, {uops_14_debug_tsrc}, {uops_13_debug_tsrc}, {uops_12_debug_tsrc}, {uops_11_debug_tsrc}, {uops_10_debug_tsrc}, {uops_9_debug_tsrc}, {uops_8_debug_tsrc}, {uops_7_debug_tsrc}, {uops_6_debug_tsrc}, {uops_5_debug_tsrc}, {uops_4_debug_tsrc}, {uops_3_debug_tsrc}, {uops_2_debug_tsrc}, {uops_1_debug_tsrc}, {uops_0_debug_tsrc}}; // @[util.scala:466:20, :508:19] assign out_uop_debug_tsrc = _GEN_82[deq_ptr_value]; // @[Counter.scala:61:40] wire _io_deq_valid_T = ~io_empty_0; // @[util.scala:448:7, :476:69, :509:30] wire _io_deq_valid_T_1 = _io_deq_valid_T & _GEN_1; // @[util.scala:476:42, :509:{30,40}] wire [15:0] _io_deq_valid_T_2 = io_brupdate_b1_mispredict_mask_0 & out_uop_br_mask; // @[util.scala:118:51, :448:7, :506:17] wire _io_deq_valid_T_3 = |_io_deq_valid_T_2; // @[util.scala:118:{51,59}] wire _io_deq_valid_T_4 = ~_io_deq_valid_T_3; // @[util.scala:118:59, :509:68] wire _io_deq_valid_T_5 = _io_deq_valid_T_1 & _io_deq_valid_T_4; // @[util.scala:509:{40,65,68}] wire _io_deq_valid_T_6 = io_flush_0 & out_uop_uses_ldq; // @[util.scala:448:7, :506:17, :509:122] wire _io_deq_valid_T_7 = ~_io_deq_valid_T_6; // @[util.scala:509:{111,122}] assign _io_deq_valid_T_8 = _io_deq_valid_T_5 & _io_deq_valid_T_7; // @[util.scala:509:{65,108,111}] assign io_deq_valid_0 = _io_deq_valid_T_8; // @[util.scala:448:7, :509:108] wire [15:0] _io_deq_bits_uop_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:85:27, :89:23, :448:7] assign _io_deq_bits_uop_br_mask_T_1 = out_uop_br_mask & _io_deq_bits_uop_br_mask_T; // @[util.scala:85:{25,27}, :506:17] assign io_deq_bits_uop_br_mask_0 = _io_deq_bits_uop_br_mask_T_1; // @[util.scala:85:25, :448:7] wire [4:0] _ptr_diff_T = _GEN_2 - _GEN_3; // @[Counter.scala:77:24] wire [3:0] ptr_diff = _ptr_diff_T[3:0]; // @[util.scala:524:40] wire [4:0] _io_count_T_1 = {_io_count_T, ptr_diff}; // @[util.scala:524:40, :526:{20,32}] assign io_count = _io_count_T_1[3:0]; // @[util.scala:448:7, :526:{14,20}] wire _GEN_83 = enq_ptr_value == 4'h0; // @[Counter.scala:61:40] wire _GEN_84 = do_enq & _GEN_83; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_85 = enq_ptr_value == 4'h1; // @[Counter.scala:61:40] wire _GEN_86 = do_enq & _GEN_85; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_87 = enq_ptr_value == 4'h2; // @[Counter.scala:61:40] wire _GEN_88 = do_enq & _GEN_87; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_89 = enq_ptr_value == 4'h3; // @[Counter.scala:61:40] wire _GEN_90 = do_enq & _GEN_89; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_91 = enq_ptr_value == 4'h4; // @[Counter.scala:61:40] wire _GEN_92 = do_enq & _GEN_91; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_93 = enq_ptr_value == 4'h5; // @[Counter.scala:61:40] wire _GEN_94 = do_enq & _GEN_93; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_95 = enq_ptr_value == 4'h6; // @[Counter.scala:61:40] wire _GEN_96 = do_enq & _GEN_95; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_97 = enq_ptr_value == 4'h7; // @[Counter.scala:61:40] wire _GEN_98 = do_enq & _GEN_97; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_99 = enq_ptr_value == 4'h8; // @[Counter.scala:61:40] wire _GEN_100 = do_enq & _GEN_99; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_101 = enq_ptr_value == 4'h9; // @[Counter.scala:61:40] wire _GEN_102 = do_enq & _GEN_101; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_103 = enq_ptr_value == 4'hA; // @[Counter.scala:61:40] wire _GEN_104 = do_enq & _GEN_103; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_105 = enq_ptr_value == 4'hB; // @[Counter.scala:61:40] wire _GEN_106 = do_enq & _GEN_105; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_107 = enq_ptr_value == 4'hC; // @[Counter.scala:61:40] wire _GEN_108 = do_enq & _GEN_107; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_109 = enq_ptr_value == 4'hD; // @[Counter.scala:61:40] wire _GEN_110 = do_enq & _GEN_109; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_111 = enq_ptr_value == 4'hE; // @[Counter.scala:61:40] wire _GEN_112 = do_enq & _GEN_111; // @[util.scala:475:24, :481:16, :487:17, :489:33] wire _GEN_113 = do_enq & (&enq_ptr_value); // @[Counter.scala:61:40] always @(posedge clock) begin // @[util.scala:448:7] if (reset) begin // @[util.scala:448:7] valids_0 <= 1'h0; // @[util.scala:465:24] valids_1 <= 1'h0; // @[util.scala:465:24] valids_2 <= 1'h0; // @[util.scala:465:24] valids_3 <= 1'h0; // @[util.scala:465:24] valids_4 <= 1'h0; // @[util.scala:465:24] valids_5 <= 1'h0; // @[util.scala:465:24] valids_6 <= 1'h0; // @[util.scala:465:24] valids_7 <= 1'h0; // @[util.scala:465:24] valids_8 <= 1'h0; // @[util.scala:465:24] valids_9 <= 1'h0; // @[util.scala:465:24] valids_10 <= 1'h0; // @[util.scala:465:24] valids_11 <= 1'h0; // @[util.scala:465:24] valids_12 <= 1'h0; // @[util.scala:465:24] valids_13 <= 1'h0; // @[util.scala:465:24] valids_14 <= 1'h0; // @[util.scala:465:24] valids_15 <= 1'h0; // @[util.scala:465:24] enq_ptr_value <= 4'h0; // @[Counter.scala:61:40] deq_ptr_value <= 4'h0; // @[Counter.scala:61:40] maybe_full <= 1'h0; // @[util.scala:470:27] end else begin // @[util.scala:448:7] valids_0 <= ~(do_deq & deq_ptr_value == 4'h0) & (_GEN_84 | _valids_0_T_6); // @[Counter.scala:61:40] valids_1 <= ~(do_deq & deq_ptr_value == 4'h1) & (_GEN_86 | _valids_1_T_6); // @[Counter.scala:61:40] valids_2 <= ~(do_deq & deq_ptr_value == 4'h2) & (_GEN_88 | _valids_2_T_6); // @[Counter.scala:61:40] valids_3 <= ~(do_deq & deq_ptr_value == 4'h3) & (_GEN_90 | _valids_3_T_6); // @[Counter.scala:61:40] valids_4 <= ~(do_deq & deq_ptr_value == 4'h4) & (_GEN_92 | _valids_4_T_6); // @[Counter.scala:61:40] valids_5 <= ~(do_deq & deq_ptr_value == 4'h5) & (_GEN_94 | _valids_5_T_6); // @[Counter.scala:61:40] valids_6 <= ~(do_deq & deq_ptr_value == 4'h6) & (_GEN_96 | _valids_6_T_6); // @[Counter.scala:61:40] valids_7 <= ~(do_deq & deq_ptr_value == 4'h7) & (_GEN_98 | _valids_7_T_6); // @[Counter.scala:61:40] valids_8 <= ~(do_deq & deq_ptr_value == 4'h8) & (_GEN_100 | _valids_8_T_6); // @[Counter.scala:61:40] valids_9 <= ~(do_deq & deq_ptr_value == 4'h9) & (_GEN_102 | _valids_9_T_6); // @[Counter.scala:61:40] valids_10 <= ~(do_deq & deq_ptr_value == 4'hA) & (_GEN_104 | _valids_10_T_6); // @[Counter.scala:61:40] valids_11 <= ~(do_deq & deq_ptr_value == 4'hB) & (_GEN_106 | _valids_11_T_6); // @[Counter.scala:61:40] valids_12 <= ~(do_deq & deq_ptr_value == 4'hC) & (_GEN_108 | _valids_12_T_6); // @[Counter.scala:61:40] valids_13 <= ~(do_deq & deq_ptr_value == 4'hD) & (_GEN_110 | _valids_13_T_6); // @[Counter.scala:61:40] valids_14 <= ~(do_deq & deq_ptr_value == 4'hE) & (_GEN_112 | _valids_14_T_6); // @[Counter.scala:61:40] valids_15 <= ~(do_deq & (&deq_ptr_value)) & (_GEN_113 | _valids_15_T_6); // @[Counter.scala:61:40] if (do_enq) // @[util.scala:475:24] enq_ptr_value <= _value_T_1; // @[Counter.scala:61:40, :77:24] if (do_deq) // @[util.scala:476:24] deq_ptr_value <= _value_T_3; // @[Counter.scala:61:40, :77:24] if (~(do_enq == do_deq)) // @[util.scala:470:27, :475:24, :476:24, :500:{16,28}, :501:16] maybe_full <= do_enq; // @[util.scala:470:27, :475:24] end if (_GEN_84) begin // @[util.scala:481:16, :487:17, :489:33] uops_0_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_0_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_0_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_0_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_0_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_0_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_0_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_0_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_0_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_0_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_0_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_0_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_0_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_0_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_0_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_0_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_0_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_0_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_0_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_0_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_0_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_0_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_0_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_0_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_0_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_0_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_0_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_0_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_0_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_0_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_0_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_0_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_0_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_0_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_0_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_0_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_0_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_0_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_0_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_0_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_0_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_0_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_0_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_0_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_0_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_0_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_0_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_0_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_0_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_0_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_0_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_0_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_0_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_0_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_0_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_0_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_0_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_0_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_0_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_0_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_0_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_0_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_0_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_83) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_0_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_0) // @[util.scala:465:24] uops_0_br_mask <= _uops_0_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_86) begin // @[util.scala:481:16, :487:17, :489:33] uops_1_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_1_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_1_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_1_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_1_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_1_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_1_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_1_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_1_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_1_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_1_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_1_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_1_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_1_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_1_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_1_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_1_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_1_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_1_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_1_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_1_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_1_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_1_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_1_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_1_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_1_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_1_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_1_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_1_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_1_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_1_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_1_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_1_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_1_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_1_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_1_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_1_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_1_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_1_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_1_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_1_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_1_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_1_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_1_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_1_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_1_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_1_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_1_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_1_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_1_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_1_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_1_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_1_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_1_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_1_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_1_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_1_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_1_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_1_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_1_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_1_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_1_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_1_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_85) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_1_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_1) // @[util.scala:465:24] uops_1_br_mask <= _uops_1_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_88) begin // @[util.scala:481:16, :487:17, :489:33] uops_2_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_2_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_2_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_2_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_2_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_2_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_2_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_2_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_2_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_2_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_2_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_2_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_2_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_2_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_2_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_2_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_2_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_2_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_2_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_2_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_2_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_2_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_2_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_2_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_2_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_2_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_2_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_2_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_2_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_2_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_2_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_2_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_2_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_2_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_2_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_2_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_2_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_2_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_2_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_2_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_2_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_2_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_2_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_2_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_2_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_2_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_2_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_2_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_2_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_2_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_2_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_2_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_2_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_2_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_2_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_2_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_2_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_2_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_2_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_2_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_2_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_2_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_2_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_87) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_2_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_2) // @[util.scala:465:24] uops_2_br_mask <= _uops_2_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_90) begin // @[util.scala:481:16, :487:17, :489:33] uops_3_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_3_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_3_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_3_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_3_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_3_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_3_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_3_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_3_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_3_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_3_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_3_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_3_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_3_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_3_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_3_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_3_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_3_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_3_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_3_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_3_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_3_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_3_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_3_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_3_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_3_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_3_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_3_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_3_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_3_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_3_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_3_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_3_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_3_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_3_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_3_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_3_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_3_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_3_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_3_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_3_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_3_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_3_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_3_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_3_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_3_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_3_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_3_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_3_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_3_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_3_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_3_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_3_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_3_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_3_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_3_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_3_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_3_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_3_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_3_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_3_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_3_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_3_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_89) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_3_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_3) // @[util.scala:465:24] uops_3_br_mask <= _uops_3_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_92) begin // @[util.scala:481:16, :487:17, :489:33] uops_4_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_4_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_4_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_4_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_4_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_4_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_4_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_4_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_4_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_4_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_4_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_4_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_4_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_4_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_4_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_4_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_4_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_4_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_4_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_4_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_4_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_4_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_4_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_4_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_4_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_4_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_4_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_4_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_4_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_4_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_4_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_4_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_4_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_4_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_4_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_4_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_4_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_4_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_4_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_4_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_4_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_4_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_4_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_4_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_4_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_4_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_4_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_4_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_4_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_4_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_4_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_4_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_4_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_4_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_4_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_4_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_4_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_4_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_4_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_4_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_4_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_4_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_4_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_91) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_4_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_4) // @[util.scala:465:24] uops_4_br_mask <= _uops_4_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_94) begin // @[util.scala:481:16, :487:17, :489:33] uops_5_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_5_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_5_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_5_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_5_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_5_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_5_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_5_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_5_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_5_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_5_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_5_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_5_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_5_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_5_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_5_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_5_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_5_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_5_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_5_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_5_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_5_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_5_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_5_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_5_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_5_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_5_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_5_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_5_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_5_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_5_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_5_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_5_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_5_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_5_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_5_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_5_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_5_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_5_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_5_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_5_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_5_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_5_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_5_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_5_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_5_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_5_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_5_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_5_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_5_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_5_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_5_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_5_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_5_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_5_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_5_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_5_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_5_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_5_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_5_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_5_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_5_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_5_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_93) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_5_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_5) // @[util.scala:465:24] uops_5_br_mask <= _uops_5_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_96) begin // @[util.scala:481:16, :487:17, :489:33] uops_6_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_6_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_6_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_6_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_6_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_6_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_6_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_6_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_6_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_6_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_6_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_6_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_6_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_6_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_6_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_6_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_6_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_6_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_6_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_6_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_6_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_6_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_6_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_6_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_6_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_6_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_6_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_6_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_6_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_6_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_6_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_6_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_6_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_6_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_6_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_6_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_6_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_6_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_6_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_6_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_6_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_6_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_6_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_6_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_6_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_6_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_6_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_6_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_6_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_6_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_6_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_6_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_6_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_6_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_6_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_6_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_6_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_6_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_6_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_6_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_6_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_6_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_6_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_95) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_6_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_6) // @[util.scala:465:24] uops_6_br_mask <= _uops_6_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_98) begin // @[util.scala:481:16, :487:17, :489:33] uops_7_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_7_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_7_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_7_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_7_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_7_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_7_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_7_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_7_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_7_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_7_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_7_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_7_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_7_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_7_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_7_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_7_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_7_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_7_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_7_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_7_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_7_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_7_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_7_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_7_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_7_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_7_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_7_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_7_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_7_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_7_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_7_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_7_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_7_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_7_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_7_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_7_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_7_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_7_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_7_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_7_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_7_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_7_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_7_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_7_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_7_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_7_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_7_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_7_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_7_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_7_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_7_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_7_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_7_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_7_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_7_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_7_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_7_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_7_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_7_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_7_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_7_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_7_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_97) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_7_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_7) // @[util.scala:465:24] uops_7_br_mask <= _uops_7_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_100) begin // @[util.scala:481:16, :487:17, :489:33] uops_8_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_8_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_8_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_8_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_8_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_8_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_8_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_8_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_8_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_8_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_8_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_8_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_8_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_8_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_8_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_8_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_8_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_8_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_8_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_8_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_8_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_8_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_8_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_8_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_8_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_8_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_8_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_8_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_8_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_8_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_8_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_8_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_8_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_8_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_8_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_8_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_8_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_8_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_8_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_8_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_8_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_8_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_8_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_8_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_8_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_8_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_8_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_8_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_8_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_8_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_8_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_8_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_8_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_8_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_8_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_8_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_8_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_8_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_8_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_8_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_8_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_8_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_8_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_99) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_8_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_8) // @[util.scala:465:24] uops_8_br_mask <= _uops_8_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_102) begin // @[util.scala:481:16, :487:17, :489:33] uops_9_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_9_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_9_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_9_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_9_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_9_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_9_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_9_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_9_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_9_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_9_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_9_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_9_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_9_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_9_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_9_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_9_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_9_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_9_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_9_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_9_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_9_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_9_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_9_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_9_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_9_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_9_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_9_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_9_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_9_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_9_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_9_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_9_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_9_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_9_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_9_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_9_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_9_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_9_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_9_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_9_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_9_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_9_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_9_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_9_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_9_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_9_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_9_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_9_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_9_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_9_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_9_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_9_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_9_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_9_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_9_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_9_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_9_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_9_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_9_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_9_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_9_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_9_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_101) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_9_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_9) // @[util.scala:465:24] uops_9_br_mask <= _uops_9_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_104) begin // @[util.scala:481:16, :487:17, :489:33] uops_10_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_10_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_10_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_10_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_10_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_10_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_10_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_10_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_10_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_10_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_10_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_10_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_10_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_10_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_10_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_10_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_10_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_10_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_10_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_10_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_10_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_10_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_10_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_10_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_10_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_10_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_10_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_10_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_10_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_10_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_10_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_10_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_10_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_10_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_10_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_10_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_10_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_10_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_10_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_10_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_10_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_10_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_10_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_10_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_10_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_10_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_10_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_10_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_10_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_10_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_10_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_10_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_10_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_10_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_10_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_10_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_10_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_10_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_10_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_10_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_10_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_10_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_10_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_103) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_10_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_10) // @[util.scala:465:24] uops_10_br_mask <= _uops_10_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_106) begin // @[util.scala:481:16, :487:17, :489:33] uops_11_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_11_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_11_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_11_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_11_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_11_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_11_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_11_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_11_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_11_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_11_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_11_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_11_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_11_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_11_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_11_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_11_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_11_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_11_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_11_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_11_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_11_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_11_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_11_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_11_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_11_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_11_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_11_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_11_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_11_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_11_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_11_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_11_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_11_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_11_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_11_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_11_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_11_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_11_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_11_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_11_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_11_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_11_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_11_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_11_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_11_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_11_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_11_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_11_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_11_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_11_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_11_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_11_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_11_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_11_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_11_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_11_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_11_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_11_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_11_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_11_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_11_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_11_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_105) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_11_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_11) // @[util.scala:465:24] uops_11_br_mask <= _uops_11_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_108) begin // @[util.scala:481:16, :487:17, :489:33] uops_12_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_12_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_12_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_12_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_12_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_12_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_12_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_12_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_12_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_12_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_12_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_12_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_12_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_12_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_12_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_12_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_12_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_12_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_12_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_12_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_12_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_12_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_12_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_12_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_12_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_12_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_12_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_12_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_12_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_12_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_12_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_12_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_12_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_12_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_12_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_12_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_12_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_12_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_12_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_12_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_12_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_12_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_12_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_12_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_12_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_12_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_12_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_12_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_12_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_12_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_12_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_12_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_12_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_12_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_12_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_12_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_12_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_12_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_12_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_12_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_12_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_12_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_12_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_107) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_12_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_12) // @[util.scala:465:24] uops_12_br_mask <= _uops_12_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_110) begin // @[util.scala:481:16, :487:17, :489:33] uops_13_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_13_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_13_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_13_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_13_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_13_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_13_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_13_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_13_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_13_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_13_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_13_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_13_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_13_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_13_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_13_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_13_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_13_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_13_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_13_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_13_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_13_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_13_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_13_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_13_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_13_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_13_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_13_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_13_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_13_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_13_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_13_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_13_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_13_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_13_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_13_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_13_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_13_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_13_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_13_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_13_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_13_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_13_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_13_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_13_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_13_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_13_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_13_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_13_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_13_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_13_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_13_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_13_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_13_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_13_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_13_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_13_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_13_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_13_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_13_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_13_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_13_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_13_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_109) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_13_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_13) // @[util.scala:465:24] uops_13_br_mask <= _uops_13_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_112) begin // @[util.scala:481:16, :487:17, :489:33] uops_14_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_14_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_14_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_14_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_14_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_14_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_14_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_14_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_14_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_14_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_14_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_14_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_14_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_14_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_14_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_14_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_14_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_14_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_14_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_14_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_14_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_14_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_14_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_14_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_14_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_14_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_14_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_14_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_14_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_14_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_14_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_14_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_14_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_14_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_14_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_14_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_14_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_14_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_14_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_14_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_14_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_14_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_14_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_14_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_14_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_14_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_14_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_14_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_14_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_14_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_14_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_14_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_14_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_14_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_14_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_14_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_14_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_14_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_14_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_14_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_14_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_14_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_14_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & _GEN_111) // @[util.scala:475:24, :482:22, :487:17, :489:33, :491:33] uops_14_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_14) // @[util.scala:465:24] uops_14_br_mask <= _uops_14_br_mask_T_1; // @[util.scala:89:21, :466:20] if (_GEN_113) begin // @[util.scala:481:16, :487:17, :489:33] uops_15_uopc <= io_enq_bits_uop_uopc_0; // @[util.scala:448:7, :466:20] uops_15_inst <= io_enq_bits_uop_inst_0; // @[util.scala:448:7, :466:20] uops_15_debug_inst <= io_enq_bits_uop_debug_inst_0; // @[util.scala:448:7, :466:20] uops_15_is_rvc <= io_enq_bits_uop_is_rvc_0; // @[util.scala:448:7, :466:20] uops_15_debug_pc <= io_enq_bits_uop_debug_pc_0; // @[util.scala:448:7, :466:20] uops_15_iq_type <= io_enq_bits_uop_iq_type_0; // @[util.scala:448:7, :466:20] uops_15_fu_code <= io_enq_bits_uop_fu_code_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_br_type <= io_enq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op1_sel <= io_enq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op2_sel <= io_enq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_imm_sel <= io_enq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_op_fcn <= io_enq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_fcn_dw <= io_enq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_csr_cmd <= io_enq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_load <= io_enq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_sta <= io_enq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7, :466:20] uops_15_ctrl_is_std <= io_enq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7, :466:20] uops_15_iw_state <= io_enq_bits_uop_iw_state_0; // @[util.scala:448:7, :466:20] uops_15_iw_p1_poisoned <= io_enq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_iw_p2_poisoned <= io_enq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7, :466:20] uops_15_is_br <= io_enq_bits_uop_is_br_0; // @[util.scala:448:7, :466:20] uops_15_is_jalr <= io_enq_bits_uop_is_jalr_0; // @[util.scala:448:7, :466:20] uops_15_is_jal <= io_enq_bits_uop_is_jal_0; // @[util.scala:448:7, :466:20] uops_15_is_sfb <= io_enq_bits_uop_is_sfb_0; // @[util.scala:448:7, :466:20] uops_15_br_tag <= io_enq_bits_uop_br_tag_0; // @[util.scala:448:7, :466:20] uops_15_ftq_idx <= io_enq_bits_uop_ftq_idx_0; // @[util.scala:448:7, :466:20] uops_15_edge_inst <= io_enq_bits_uop_edge_inst_0; // @[util.scala:448:7, :466:20] uops_15_pc_lob <= io_enq_bits_uop_pc_lob_0; // @[util.scala:448:7, :466:20] uops_15_taken <= io_enq_bits_uop_taken_0; // @[util.scala:448:7, :466:20] uops_15_imm_packed <= io_enq_bits_uop_imm_packed_0; // @[util.scala:448:7, :466:20] uops_15_csr_addr <= io_enq_bits_uop_csr_addr_0; // @[util.scala:448:7, :466:20] uops_15_rob_idx <= io_enq_bits_uop_rob_idx_0; // @[util.scala:448:7, :466:20] uops_15_ldq_idx <= io_enq_bits_uop_ldq_idx_0; // @[util.scala:448:7, :466:20] uops_15_stq_idx <= io_enq_bits_uop_stq_idx_0; // @[util.scala:448:7, :466:20] uops_15_rxq_idx <= io_enq_bits_uop_rxq_idx_0; // @[util.scala:448:7, :466:20] uops_15_pdst <= io_enq_bits_uop_pdst_0; // @[util.scala:448:7, :466:20] uops_15_prs1 <= io_enq_bits_uop_prs1_0; // @[util.scala:448:7, :466:20] uops_15_prs2 <= io_enq_bits_uop_prs2_0; // @[util.scala:448:7, :466:20] uops_15_prs3 <= io_enq_bits_uop_prs3_0; // @[util.scala:448:7, :466:20] uops_15_ppred <= io_enq_bits_uop_ppred_0; // @[util.scala:448:7, :466:20] uops_15_prs1_busy <= io_enq_bits_uop_prs1_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs2_busy <= io_enq_bits_uop_prs2_busy_0; // @[util.scala:448:7, :466:20] uops_15_prs3_busy <= io_enq_bits_uop_prs3_busy_0; // @[util.scala:448:7, :466:20] uops_15_ppred_busy <= io_enq_bits_uop_ppred_busy_0; // @[util.scala:448:7, :466:20] uops_15_stale_pdst <= io_enq_bits_uop_stale_pdst_0; // @[util.scala:448:7, :466:20] uops_15_exception <= io_enq_bits_uop_exception_0; // @[util.scala:448:7, :466:20] uops_15_exc_cause <= io_enq_bits_uop_exc_cause_0; // @[util.scala:448:7, :466:20] uops_15_bypassable <= io_enq_bits_uop_bypassable_0; // @[util.scala:448:7, :466:20] uops_15_mem_cmd <= io_enq_bits_uop_mem_cmd_0; // @[util.scala:448:7, :466:20] uops_15_mem_size <= io_enq_bits_uop_mem_size_0; // @[util.scala:448:7, :466:20] uops_15_mem_signed <= io_enq_bits_uop_mem_signed_0; // @[util.scala:448:7, :466:20] uops_15_is_fence <= io_enq_bits_uop_is_fence_0; // @[util.scala:448:7, :466:20] uops_15_is_fencei <= io_enq_bits_uop_is_fencei_0; // @[util.scala:448:7, :466:20] uops_15_is_amo <= io_enq_bits_uop_is_amo_0; // @[util.scala:448:7, :466:20] uops_15_uses_ldq <= io_enq_bits_uop_uses_ldq_0; // @[util.scala:448:7, :466:20] uops_15_uses_stq <= io_enq_bits_uop_uses_stq_0; // @[util.scala:448:7, :466:20] uops_15_is_sys_pc2epc <= io_enq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7, :466:20] uops_15_is_unique <= io_enq_bits_uop_is_unique_0; // @[util.scala:448:7, :466:20] uops_15_flush_on_commit <= io_enq_bits_uop_flush_on_commit_0; // @[util.scala:448:7, :466:20] uops_15_ldst_is_rs1 <= io_enq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7, :466:20] uops_15_ldst <= io_enq_bits_uop_ldst_0; // @[util.scala:448:7, :466:20] uops_15_lrs1 <= io_enq_bits_uop_lrs1_0; // @[util.scala:448:7, :466:20] uops_15_lrs2 <= io_enq_bits_uop_lrs2_0; // @[util.scala:448:7, :466:20] uops_15_lrs3 <= io_enq_bits_uop_lrs3_0; // @[util.scala:448:7, :466:20] uops_15_ldst_val <= io_enq_bits_uop_ldst_val_0; // @[util.scala:448:7, :466:20] uops_15_dst_rtype <= io_enq_bits_uop_dst_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs1_rtype <= io_enq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7, :466:20] uops_15_lrs2_rtype <= io_enq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7, :466:20] uops_15_frs3_en <= io_enq_bits_uop_frs3_en_0; // @[util.scala:448:7, :466:20] uops_15_fp_val <= io_enq_bits_uop_fp_val_0; // @[util.scala:448:7, :466:20] uops_15_fp_single <= io_enq_bits_uop_fp_single_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_pf_if <= io_enq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ae_if <= io_enq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7, :466:20] uops_15_xcpt_ma_if <= io_enq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_debug_if <= io_enq_bits_uop_bp_debug_if_0; // @[util.scala:448:7, :466:20] uops_15_bp_xcpt_if <= io_enq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7, :466:20] uops_15_debug_fsrc <= io_enq_bits_uop_debug_fsrc_0; // @[util.scala:448:7, :466:20] uops_15_debug_tsrc <= io_enq_bits_uop_debug_tsrc_0; // @[util.scala:448:7, :466:20] end if (do_enq & (&enq_ptr_value)) // @[Counter.scala:61:40] uops_15_br_mask <= _uops_br_mask_T_1; // @[util.scala:85:25, :466:20] else if (valids_15) // @[util.scala:465:24] uops_15_br_mask <= _uops_15_br_mask_T_1; // @[util.scala:89:21, :466:20] always @(posedge) ram_16x141 ram_ext ( // @[util.scala:464:20] .R0_addr (deq_ptr_value), // @[Counter.scala:61:40] .R0_en (1'h1), .R0_clk (clock), .R0_data (_ram_ext_R0_data), .W0_addr (enq_ptr_value), // @[Counter.scala:61:40] .W0_en (do_enq), // @[util.scala:475:24] .W0_clk (clock), .W0_data ({io_enq_bits_sdq_id_0, io_enq_bits_way_en_0, io_enq_bits_old_meta_tag_0, io_enq_bits_old_meta_coh_state_0, io_enq_bits_tag_match_0, io_enq_bits_is_hella_0, io_enq_bits_data_0, io_enq_bits_addr_0}) // @[util.scala:448:7, :464:20] ); // @[util.scala:464:20] assign io_enq_ready = io_enq_ready_0; // @[util.scala:448:7] assign io_deq_valid = io_deq_valid_0; // @[util.scala:448:7] assign io_deq_bits_uop_uopc = io_deq_bits_uop_uopc_0; // @[util.scala:448:7] assign io_deq_bits_uop_inst = io_deq_bits_uop_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_inst = io_deq_bits_uop_debug_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_rvc = io_deq_bits_uop_is_rvc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_pc = io_deq_bits_uop_debug_pc_0; // @[util.scala:448:7] assign io_deq_bits_uop_iq_type = io_deq_bits_uop_iq_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_fu_code = io_deq_bits_uop_fu_code_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_br_type = io_deq_bits_uop_ctrl_br_type_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op1_sel = io_deq_bits_uop_ctrl_op1_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op2_sel = io_deq_bits_uop_ctrl_op2_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_imm_sel = io_deq_bits_uop_ctrl_imm_sel_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_op_fcn = io_deq_bits_uop_ctrl_op_fcn_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_fcn_dw = io_deq_bits_uop_ctrl_fcn_dw_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_csr_cmd = io_deq_bits_uop_ctrl_csr_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_load = io_deq_bits_uop_ctrl_is_load_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_sta = io_deq_bits_uop_ctrl_is_sta_0; // @[util.scala:448:7] assign io_deq_bits_uop_ctrl_is_std = io_deq_bits_uop_ctrl_is_std_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_state = io_deq_bits_uop_iw_state_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p1_poisoned = io_deq_bits_uop_iw_p1_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_iw_p2_poisoned = io_deq_bits_uop_iw_p2_poisoned_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_br = io_deq_bits_uop_is_br_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jalr = io_deq_bits_uop_is_jalr_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_jal = io_deq_bits_uop_is_jal_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sfb = io_deq_bits_uop_is_sfb_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_mask = io_deq_bits_uop_br_mask_0; // @[util.scala:448:7] assign io_deq_bits_uop_br_tag = io_deq_bits_uop_br_tag_0; // @[util.scala:448:7] assign io_deq_bits_uop_ftq_idx = io_deq_bits_uop_ftq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_edge_inst = io_deq_bits_uop_edge_inst_0; // @[util.scala:448:7] assign io_deq_bits_uop_pc_lob = io_deq_bits_uop_pc_lob_0; // @[util.scala:448:7] assign io_deq_bits_uop_taken = io_deq_bits_uop_taken_0; // @[util.scala:448:7] assign io_deq_bits_uop_imm_packed = io_deq_bits_uop_imm_packed_0; // @[util.scala:448:7] assign io_deq_bits_uop_csr_addr = io_deq_bits_uop_csr_addr_0; // @[util.scala:448:7] assign io_deq_bits_uop_rob_idx = io_deq_bits_uop_rob_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldq_idx = io_deq_bits_uop_ldq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_stq_idx = io_deq_bits_uop_stq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_rxq_idx = io_deq_bits_uop_rxq_idx_0; // @[util.scala:448:7] assign io_deq_bits_uop_pdst = io_deq_bits_uop_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1 = io_deq_bits_uop_prs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2 = io_deq_bits_uop_prs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3 = io_deq_bits_uop_prs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred = io_deq_bits_uop_ppred_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs1_busy = io_deq_bits_uop_prs1_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs2_busy = io_deq_bits_uop_prs2_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_prs3_busy = io_deq_bits_uop_prs3_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_ppred_busy = io_deq_bits_uop_ppred_busy_0; // @[util.scala:448:7] assign io_deq_bits_uop_stale_pdst = io_deq_bits_uop_stale_pdst_0; // @[util.scala:448:7] assign io_deq_bits_uop_exception = io_deq_bits_uop_exception_0; // @[util.scala:448:7] assign io_deq_bits_uop_exc_cause = io_deq_bits_uop_exc_cause_0; // @[util.scala:448:7] assign io_deq_bits_uop_bypassable = io_deq_bits_uop_bypassable_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_cmd = io_deq_bits_uop_mem_cmd_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_size = io_deq_bits_uop_mem_size_0; // @[util.scala:448:7] assign io_deq_bits_uop_mem_signed = io_deq_bits_uop_mem_signed_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fence = io_deq_bits_uop_is_fence_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_fencei = io_deq_bits_uop_is_fencei_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_amo = io_deq_bits_uop_is_amo_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_ldq = io_deq_bits_uop_uses_ldq_0; // @[util.scala:448:7] assign io_deq_bits_uop_uses_stq = io_deq_bits_uop_uses_stq_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_sys_pc2epc = io_deq_bits_uop_is_sys_pc2epc_0; // @[util.scala:448:7] assign io_deq_bits_uop_is_unique = io_deq_bits_uop_is_unique_0; // @[util.scala:448:7] assign io_deq_bits_uop_flush_on_commit = io_deq_bits_uop_flush_on_commit_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_is_rs1 = io_deq_bits_uop_ldst_is_rs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst = io_deq_bits_uop_ldst_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1 = io_deq_bits_uop_lrs1_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2 = io_deq_bits_uop_lrs2_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs3 = io_deq_bits_uop_lrs3_0; // @[util.scala:448:7] assign io_deq_bits_uop_ldst_val = io_deq_bits_uop_ldst_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_dst_rtype = io_deq_bits_uop_dst_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs1_rtype = io_deq_bits_uop_lrs1_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_lrs2_rtype = io_deq_bits_uop_lrs2_rtype_0; // @[util.scala:448:7] assign io_deq_bits_uop_frs3_en = io_deq_bits_uop_frs3_en_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_val = io_deq_bits_uop_fp_val_0; // @[util.scala:448:7] assign io_deq_bits_uop_fp_single = io_deq_bits_uop_fp_single_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_pf_if = io_deq_bits_uop_xcpt_pf_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ae_if = io_deq_bits_uop_xcpt_ae_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_xcpt_ma_if = io_deq_bits_uop_xcpt_ma_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_debug_if = io_deq_bits_uop_bp_debug_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_bp_xcpt_if = io_deq_bits_uop_bp_xcpt_if_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_fsrc = io_deq_bits_uop_debug_fsrc_0; // @[util.scala:448:7] assign io_deq_bits_uop_debug_tsrc = io_deq_bits_uop_debug_tsrc_0; // @[util.scala:448:7] assign io_deq_bits_addr = io_deq_bits_addr_0; // @[util.scala:448:7] assign io_deq_bits_data = io_deq_bits_data_0; // @[util.scala:448:7] assign io_deq_bits_is_hella = io_deq_bits_is_hella_0; // @[util.scala:448:7] assign io_deq_bits_tag_match = io_deq_bits_tag_match_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_coh_state = io_deq_bits_old_meta_coh_state_0; // @[util.scala:448:7] assign io_deq_bits_old_meta_tag = io_deq_bits_old_meta_tag_0; // @[util.scala:448:7] assign io_deq_bits_sdq_id = io_deq_bits_sdq_id_0; // @[util.scala:448:7] assign io_empty = io_empty_0; // @[util.scala:448:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Repeater_TLBundleA_a26d64s10k1z3u : input clock : Clock input reset : Reset output io : { flip repeat : UInt<1>, full : UInt<1>, flip enq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, deq : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}} regreset full : UInt<1>, clock, reset, UInt<1>(0h0) reg saved : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<10>, address : UInt<26>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}, clock node _io_deq_valid_T = or(io.enq.valid, full) connect io.deq.valid, _io_deq_valid_T node _io_enq_ready_T = eq(full, UInt<1>(0h0)) node _io_enq_ready_T_1 = and(io.deq.ready, _io_enq_ready_T) connect io.enq.ready, _io_enq_ready_T_1 node _io_deq_bits_T = mux(full, saved, io.enq.bits) connect io.deq.bits, _io_deq_bits_T connect io.full, full node _T = and(io.enq.ready, io.enq.valid) node _T_1 = and(_T, io.repeat) when _T_1 : connect full, UInt<1>(0h1) connect saved, io.enq.bits node _T_2 = and(io.deq.ready, io.deq.valid) node _T_3 = eq(io.repeat, UInt<1>(0h0)) node _T_4 = and(_T_2, _T_3) when _T_4 : connect full, UInt<1>(0h0)
module Repeater_TLBundleA_a26d64s10k1z3u( // @[Repeater.scala:10:7] input clock, // @[Repeater.scala:10:7] input reset, // @[Repeater.scala:10:7] input io_repeat, // @[Repeater.scala:13:14] output io_full, // @[Repeater.scala:13:14] output io_enq_ready, // @[Repeater.scala:13:14] input io_enq_valid, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_opcode, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_param, // @[Repeater.scala:13:14] input [2:0] io_enq_bits_size, // @[Repeater.scala:13:14] input [9:0] io_enq_bits_source, // @[Repeater.scala:13:14] input [25:0] io_enq_bits_address, // @[Repeater.scala:13:14] input [7:0] io_enq_bits_mask, // @[Repeater.scala:13:14] input [63:0] io_enq_bits_data, // @[Repeater.scala:13:14] input io_enq_bits_corrupt, // @[Repeater.scala:13:14] input io_deq_ready, // @[Repeater.scala:13:14] output io_deq_valid, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_opcode, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_param, // @[Repeater.scala:13:14] output [2:0] io_deq_bits_size, // @[Repeater.scala:13:14] output [9:0] io_deq_bits_source, // @[Repeater.scala:13:14] output [25:0] io_deq_bits_address, // @[Repeater.scala:13:14] output [7:0] io_deq_bits_mask, // @[Repeater.scala:13:14] output io_deq_bits_corrupt // @[Repeater.scala:13:14] ); wire io_repeat_0 = io_repeat; // @[Repeater.scala:10:7] wire io_enq_valid_0 = io_enq_valid; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_opcode_0 = io_enq_bits_opcode; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_param_0 = io_enq_bits_param; // @[Repeater.scala:10:7] wire [2:0] io_enq_bits_size_0 = io_enq_bits_size; // @[Repeater.scala:10:7] wire [9:0] io_enq_bits_source_0 = io_enq_bits_source; // @[Repeater.scala:10:7] wire [25:0] io_enq_bits_address_0 = io_enq_bits_address; // @[Repeater.scala:10:7] wire [7:0] io_enq_bits_mask_0 = io_enq_bits_mask; // @[Repeater.scala:10:7] wire [63:0] io_enq_bits_data_0 = io_enq_bits_data; // @[Repeater.scala:10:7] wire io_enq_bits_corrupt_0 = io_enq_bits_corrupt; // @[Repeater.scala:10:7] wire io_deq_ready_0 = io_deq_ready; // @[Repeater.scala:10:7] wire _io_enq_ready_T_1; // @[Repeater.scala:25:32] wire _io_deq_valid_T; // @[Repeater.scala:24:32] wire [2:0] _io_deq_bits_T_opcode; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_param; // @[Repeater.scala:26:21] wire [2:0] _io_deq_bits_T_size; // @[Repeater.scala:26:21] wire [9:0] _io_deq_bits_T_source; // @[Repeater.scala:26:21] wire [25:0] _io_deq_bits_T_address; // @[Repeater.scala:26:21] wire [7:0] _io_deq_bits_T_mask; // @[Repeater.scala:26:21] wire [63:0] _io_deq_bits_T_data; // @[Repeater.scala:26:21] wire _io_deq_bits_T_corrupt; // @[Repeater.scala:26:21] wire io_enq_ready_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_opcode_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_param_0; // @[Repeater.scala:10:7] wire [2:0] io_deq_bits_size_0; // @[Repeater.scala:10:7] wire [9:0] io_deq_bits_source_0; // @[Repeater.scala:10:7] wire [25:0] io_deq_bits_address_0; // @[Repeater.scala:10:7] wire [7:0] io_deq_bits_mask_0; // @[Repeater.scala:10:7] wire [63:0] io_deq_bits_data; // @[Repeater.scala:10:7] wire io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] wire io_deq_valid_0; // @[Repeater.scala:10:7] wire io_full_0; // @[Repeater.scala:10:7] reg full; // @[Repeater.scala:20:21] assign io_full_0 = full; // @[Repeater.scala:10:7, :20:21] reg [2:0] saved_opcode; // @[Repeater.scala:21:18] reg [2:0] saved_param; // @[Repeater.scala:21:18] reg [2:0] saved_size; // @[Repeater.scala:21:18] reg [9:0] saved_source; // @[Repeater.scala:21:18] reg [25:0] saved_address; // @[Repeater.scala:21:18] reg [7:0] saved_mask; // @[Repeater.scala:21:18] reg [63:0] saved_data; // @[Repeater.scala:21:18] reg saved_corrupt; // @[Repeater.scala:21:18] assign _io_deq_valid_T = io_enq_valid_0 | full; // @[Repeater.scala:10:7, :20:21, :24:32] assign io_deq_valid_0 = _io_deq_valid_T; // @[Repeater.scala:10:7, :24:32] wire _io_enq_ready_T = ~full; // @[Repeater.scala:20:21, :25:35] assign _io_enq_ready_T_1 = io_deq_ready_0 & _io_enq_ready_T; // @[Repeater.scala:10:7, :25:{32,35}] assign io_enq_ready_0 = _io_enq_ready_T_1; // @[Repeater.scala:10:7, :25:32] assign _io_deq_bits_T_opcode = full ? saved_opcode : io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_param = full ? saved_param : io_enq_bits_param_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_size = full ? saved_size : io_enq_bits_size_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_source = full ? saved_source : io_enq_bits_source_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_address = full ? saved_address : io_enq_bits_address_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_mask = full ? saved_mask : io_enq_bits_mask_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_data = full ? saved_data : io_enq_bits_data_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign _io_deq_bits_T_corrupt = full ? saved_corrupt : io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :20:21, :21:18, :26:21] assign io_deq_bits_opcode_0 = _io_deq_bits_T_opcode; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_param_0 = _io_deq_bits_T_param; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_size_0 = _io_deq_bits_T_size; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_source_0 = _io_deq_bits_T_source; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_address_0 = _io_deq_bits_T_address; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_mask_0 = _io_deq_bits_T_mask; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_data = _io_deq_bits_T_data; // @[Repeater.scala:10:7, :26:21] assign io_deq_bits_corrupt_0 = _io_deq_bits_T_corrupt; // @[Repeater.scala:10:7, :26:21] wire _T_1 = io_enq_ready_0 & io_enq_valid_0 & io_repeat_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Repeater.scala:10:7] if (reset) // @[Repeater.scala:10:7] full <= 1'h0; // @[Repeater.scala:20:21] else // @[Repeater.scala:10:7] full <= ~(io_deq_ready_0 & io_deq_valid_0 & ~io_repeat_0) & (_T_1 | full); // @[Decoupled.scala:51:35] if (_T_1) begin // @[Decoupled.scala:51:35] saved_opcode <= io_enq_bits_opcode_0; // @[Repeater.scala:10:7, :21:18] saved_param <= io_enq_bits_param_0; // @[Repeater.scala:10:7, :21:18] saved_size <= io_enq_bits_size_0; // @[Repeater.scala:10:7, :21:18] saved_source <= io_enq_bits_source_0; // @[Repeater.scala:10:7, :21:18] saved_address <= io_enq_bits_address_0; // @[Repeater.scala:10:7, :21:18] saved_mask <= io_enq_bits_mask_0; // @[Repeater.scala:10:7, :21:18] saved_data <= io_enq_bits_data_0; // @[Repeater.scala:10:7, :21:18] saved_corrupt <= io_enq_bits_corrupt_0; // @[Repeater.scala:10:7, :21:18] end always @(posedge) assign io_full = io_full_0; // @[Repeater.scala:10:7] assign io_enq_ready = io_enq_ready_0; // @[Repeater.scala:10:7] assign io_deq_valid = io_deq_valid_0; // @[Repeater.scala:10:7] assign io_deq_bits_opcode = io_deq_bits_opcode_0; // @[Repeater.scala:10:7] assign io_deq_bits_param = io_deq_bits_param_0; // @[Repeater.scala:10:7] assign io_deq_bits_size = io_deq_bits_size_0; // @[Repeater.scala:10:7] assign io_deq_bits_source = io_deq_bits_source_0; // @[Repeater.scala:10:7] assign io_deq_bits_address = io_deq_bits_address_0; // @[Repeater.scala:10:7] assign io_deq_bits_mask = io_deq_bits_mask_0; // @[Repeater.scala:10:7] assign io_deq_bits_corrupt = io_deq_bits_corrupt_0; // @[Repeater.scala:10:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module FPUFMAPipe_l3_f32_3 : input clock : Clock input reset : Reset output io : { flip in : { valid : UInt<1>, bits : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}}} reg valid : UInt<1>, clock connect valid, io.in.valid reg in : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>, rm : UInt<3>, fmaCmd : UInt<2>, typ : UInt<2>, fmt : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clock when io.in.valid : node one = shl(UInt<1>(0h1), 31) node _zero_T = xor(io.in.bits.in1, io.in.bits.in2) node _zero_T_1 = shl(UInt<1>(0h1), 32) node zero = and(_zero_T, _zero_T_1) connect in, io.in.bits when io.in.bits.swap23 : connect in.in2, one node _T = or(io.in.bits.ren3, io.in.bits.swap23) node _T_1 = eq(_T, UInt<1>(0h0)) when _T_1 : connect in.in3, zero inst fma of MulAddRecFNPipe_l2_e8_s24_3 connect fma.clock, clock connect fma.reset, reset connect fma.io.validin, valid connect fma.io.op, in.fmaCmd connect fma.io.roundingMode, in.rm connect fma.io.detectTininess, UInt<1>(0h1) connect fma.io.a, in.in1 connect fma.io.b, in.in2 connect fma.io.c, in.in3 wire res : { data : UInt<65>, exc : UInt<5>} node _res_data_maskedNaN_T = not(UInt<33>(0h10800000)) node res_data_maskedNaN = and(fma.io.out, _res_data_maskedNaN_T) node _res_data_T = bits(fma.io.out, 31, 29) node _res_data_T_1 = andr(_res_data_T) node _res_data_T_2 = mux(_res_data_T_1, res_data_maskedNaN, fma.io.out) connect res.data, _res_data_T_2 connect res.exc, fma.io.exceptionFlags wire io_out_out : { valid : UInt<1>, bits : { data : UInt<65>, exc : UInt<5>}} connect io_out_out.valid, fma.io.validout connect io_out_out.bits, res connect io.out, io_out_out
module FPUFMAPipe_l3_f32_3( // @[FPU.scala:697:7] input clock, // @[FPU.scala:697:7] input reset, // @[FPU.scala:697:7] input io_in_valid, // @[FPU.scala:702:14] input io_in_bits_ldst, // @[FPU.scala:702:14] input io_in_bits_wen, // @[FPU.scala:702:14] input io_in_bits_ren1, // @[FPU.scala:702:14] input io_in_bits_ren2, // @[FPU.scala:702:14] input io_in_bits_ren3, // @[FPU.scala:702:14] input io_in_bits_swap12, // @[FPU.scala:702:14] input io_in_bits_swap23, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagIn, // @[FPU.scala:702:14] input [1:0] io_in_bits_typeTagOut, // @[FPU.scala:702:14] input io_in_bits_fromint, // @[FPU.scala:702:14] input io_in_bits_toint, // @[FPU.scala:702:14] input io_in_bits_fastpipe, // @[FPU.scala:702:14] input io_in_bits_fma, // @[FPU.scala:702:14] input io_in_bits_div, // @[FPU.scala:702:14] input io_in_bits_sqrt, // @[FPU.scala:702:14] input io_in_bits_wflags, // @[FPU.scala:702:14] input io_in_bits_vec, // @[FPU.scala:702:14] input [2:0] io_in_bits_rm, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmaCmd, // @[FPU.scala:702:14] input [1:0] io_in_bits_typ, // @[FPU.scala:702:14] input [1:0] io_in_bits_fmt, // @[FPU.scala:702:14] input [64:0] io_in_bits_in1, // @[FPU.scala:702:14] input [64:0] io_in_bits_in2, // @[FPU.scala:702:14] input [64:0] io_in_bits_in3, // @[FPU.scala:702:14] output [64:0] io_out_bits_data, // @[FPU.scala:702:14] output [4:0] io_out_bits_exc // @[FPU.scala:702:14] ); wire [64:0] res_data; // @[FPU.scala:728:17] wire [32:0] _fma_io_out; // @[FPU.scala:719:19] wire io_in_valid_0 = io_in_valid; // @[FPU.scala:697:7] wire io_in_bits_ldst_0 = io_in_bits_ldst; // @[FPU.scala:697:7] wire io_in_bits_wen_0 = io_in_bits_wen; // @[FPU.scala:697:7] wire io_in_bits_ren1_0 = io_in_bits_ren1; // @[FPU.scala:697:7] wire io_in_bits_ren2_0 = io_in_bits_ren2; // @[FPU.scala:697:7] wire io_in_bits_ren3_0 = io_in_bits_ren3; // @[FPU.scala:697:7] wire io_in_bits_swap12_0 = io_in_bits_swap12; // @[FPU.scala:697:7] wire io_in_bits_swap23_0 = io_in_bits_swap23; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagIn_0 = io_in_bits_typeTagIn; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typeTagOut_0 = io_in_bits_typeTagOut; // @[FPU.scala:697:7] wire io_in_bits_fromint_0 = io_in_bits_fromint; // @[FPU.scala:697:7] wire io_in_bits_toint_0 = io_in_bits_toint; // @[FPU.scala:697:7] wire io_in_bits_fastpipe_0 = io_in_bits_fastpipe; // @[FPU.scala:697:7] wire io_in_bits_fma_0 = io_in_bits_fma; // @[FPU.scala:697:7] wire io_in_bits_div_0 = io_in_bits_div; // @[FPU.scala:697:7] wire io_in_bits_sqrt_0 = io_in_bits_sqrt; // @[FPU.scala:697:7] wire io_in_bits_wflags_0 = io_in_bits_wflags; // @[FPU.scala:697:7] wire io_in_bits_vec_0 = io_in_bits_vec; // @[FPU.scala:697:7] wire [2:0] io_in_bits_rm_0 = io_in_bits_rm; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmaCmd_0 = io_in_bits_fmaCmd; // @[FPU.scala:697:7] wire [1:0] io_in_bits_typ_0 = io_in_bits_typ; // @[FPU.scala:697:7] wire [1:0] io_in_bits_fmt_0 = io_in_bits_fmt; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in1_0 = io_in_bits_in1; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in2_0 = io_in_bits_in2; // @[FPU.scala:697:7] wire [64:0] io_in_bits_in3_0 = io_in_bits_in3; // @[FPU.scala:697:7] wire [31:0] one = 32'h80000000; // @[FPU.scala:710:19] wire [32:0] _zero_T_1 = 33'h100000000; // @[FPU.scala:711:57] wire [32:0] _res_data_maskedNaN_T = 33'h1EF7FFFFF; // @[FPU.scala:413:27] wire io_out_out_valid; // @[Valid.scala:135:21] wire [64:0] io_out_out_bits_data; // @[Valid.scala:135:21] wire [4:0] io_out_out_bits_exc; // @[Valid.scala:135:21] wire [64:0] io_out_bits_data_0; // @[FPU.scala:697:7] wire [4:0] io_out_bits_exc_0; // @[FPU.scala:697:7] wire io_out_valid; // @[FPU.scala:697:7] reg valid; // @[FPU.scala:707:22] reg in_ldst; // @[FPU.scala:708:15] reg in_wen; // @[FPU.scala:708:15] reg in_ren1; // @[FPU.scala:708:15] reg in_ren2; // @[FPU.scala:708:15] reg in_ren3; // @[FPU.scala:708:15] reg in_swap12; // @[FPU.scala:708:15] reg in_swap23; // @[FPU.scala:708:15] reg [1:0] in_typeTagIn; // @[FPU.scala:708:15] reg [1:0] in_typeTagOut; // @[FPU.scala:708:15] reg in_fromint; // @[FPU.scala:708:15] reg in_toint; // @[FPU.scala:708:15] reg in_fastpipe; // @[FPU.scala:708:15] reg in_fma; // @[FPU.scala:708:15] reg in_div; // @[FPU.scala:708:15] reg in_sqrt; // @[FPU.scala:708:15] reg in_wflags; // @[FPU.scala:708:15] reg in_vec; // @[FPU.scala:708:15] reg [2:0] in_rm; // @[FPU.scala:708:15] reg [1:0] in_fmaCmd; // @[FPU.scala:708:15] reg [1:0] in_typ; // @[FPU.scala:708:15] reg [1:0] in_fmt; // @[FPU.scala:708:15] reg [64:0] in_in1; // @[FPU.scala:708:15] reg [64:0] in_in2; // @[FPU.scala:708:15] reg [64:0] in_in3; // @[FPU.scala:708:15] wire [64:0] _zero_T = io_in_bits_in1_0 ^ io_in_bits_in2_0; // @[FPU.scala:697:7, :711:32] wire [64:0] zero = {32'h0, _zero_T[32], 32'h0}; // @[FPU.scala:711:{32,50}] assign io_out_out_bits_data = res_data; // @[Valid.scala:135:21] wire [4:0] res_exc; // @[FPU.scala:728:17] assign io_out_out_bits_exc = res_exc; // @[Valid.scala:135:21] wire [32:0] res_data_maskedNaN = _fma_io_out & 33'h1EF7FFFFF; // @[FPU.scala:413:25, :719:19] wire [2:0] _res_data_T = _fma_io_out[31:29]; // @[FPU.scala:249:25, :719:19] wire _res_data_T_1 = &_res_data_T; // @[FPU.scala:249:{25,56}] wire [32:0] _res_data_T_2 = _res_data_T_1 ? res_data_maskedNaN : _fma_io_out; // @[FPU.scala:249:56, :413:25, :414:10, :719:19] assign res_data = {32'h0, _res_data_T_2}; // @[FPU.scala:414:10, :728:17, :729:12] assign io_out_valid = io_out_out_valid; // @[Valid.scala:135:21] assign io_out_bits_data_0 = io_out_out_bits_data; // @[Valid.scala:135:21] assign io_out_bits_exc_0 = io_out_out_bits_exc; // @[Valid.scala:135:21] always @(posedge clock) begin // @[FPU.scala:697:7] valid <= io_in_valid_0; // @[FPU.scala:697:7, :707:22] if (io_in_valid_0) begin // @[FPU.scala:697:7] in_ldst <= io_in_bits_ldst_0; // @[FPU.scala:697:7, :708:15] in_wen <= io_in_bits_wen_0; // @[FPU.scala:697:7, :708:15] in_ren1 <= io_in_bits_ren1_0; // @[FPU.scala:697:7, :708:15] in_ren2 <= io_in_bits_ren2_0; // @[FPU.scala:697:7, :708:15] in_ren3 <= io_in_bits_ren3_0; // @[FPU.scala:697:7, :708:15] in_swap12 <= io_in_bits_swap12_0; // @[FPU.scala:697:7, :708:15] in_swap23 <= io_in_bits_swap23_0; // @[FPU.scala:697:7, :708:15] in_typeTagIn <= io_in_bits_typeTagIn_0; // @[FPU.scala:697:7, :708:15] in_typeTagOut <= io_in_bits_typeTagOut_0; // @[FPU.scala:697:7, :708:15] in_fromint <= io_in_bits_fromint_0; // @[FPU.scala:697:7, :708:15] in_toint <= io_in_bits_toint_0; // @[FPU.scala:697:7, :708:15] in_fastpipe <= io_in_bits_fastpipe_0; // @[FPU.scala:697:7, :708:15] in_fma <= io_in_bits_fma_0; // @[FPU.scala:697:7, :708:15] in_div <= io_in_bits_div_0; // @[FPU.scala:697:7, :708:15] in_sqrt <= io_in_bits_sqrt_0; // @[FPU.scala:697:7, :708:15] in_wflags <= io_in_bits_wflags_0; // @[FPU.scala:697:7, :708:15] in_vec <= io_in_bits_vec_0; // @[FPU.scala:697:7, :708:15] in_rm <= io_in_bits_rm_0; // @[FPU.scala:697:7, :708:15] in_fmaCmd <= io_in_bits_fmaCmd_0; // @[FPU.scala:697:7, :708:15] in_typ <= io_in_bits_typ_0; // @[FPU.scala:697:7, :708:15] in_fmt <= io_in_bits_fmt_0; // @[FPU.scala:697:7, :708:15] in_in1 <= io_in_bits_in1_0; // @[FPU.scala:697:7, :708:15] in_in2 <= io_in_bits_swap23_0 ? 65'h80000000 : io_in_bits_in2_0; // @[FPU.scala:697:7, :708:15, :714:8, :715:{23,32}] in_in3 <= io_in_bits_ren3_0 | io_in_bits_swap23_0 ? io_in_bits_in3_0 : zero; // @[FPU.scala:697:7, :708:15, :711:50, :714:8, :716:{21,37,46}] end always @(posedge) MulAddRecFNPipe_l2_e8_s24_3 fma ( // @[FPU.scala:719:19] .clock (clock), .reset (reset), .io_validin (valid), // @[FPU.scala:707:22] .io_op (in_fmaCmd), // @[FPU.scala:708:15] .io_a (in_in1[32:0]), // @[FPU.scala:708:15, :724:12] .io_b (in_in2[32:0]), // @[FPU.scala:708:15, :725:12] .io_c (in_in3[32:0]), // @[FPU.scala:708:15, :726:12] .io_roundingMode (in_rm), // @[FPU.scala:708:15] .io_out (_fma_io_out), .io_exceptionFlags (res_exc), .io_validout (io_out_out_valid) ); // @[FPU.scala:719:19] assign io_out_bits_data = io_out_bits_data_0; // @[FPU.scala:697:7] assign io_out_bits_exc = io_out_bits_exc_0; // @[FPU.scala:697:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module RVCExpander_5 : input clock : Clock input reset : Reset output io : { flip in : UInt<32>, out : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>}, rvc : UInt<1>, ill : UInt<1>} node _io_rvc_T = bits(io.in, 1, 0) node _io_rvc_T_1 = neq(_io_rvc_T, UInt<2>(0h3)) connect io.rvc, _io_rvc_T_1 node _io_out_s_opc_T = bits(io.in, 12, 5) node _io_out_s_opc_T_1 = orr(_io_out_s_opc_T) node io_out_s_opc = mux(_io_out_s_opc_T_1, UInt<7>(0h13), UInt<7>(0h1f)) node _io_out_s_T = bits(io.in, 10, 7) node _io_out_s_T_1 = bits(io.in, 12, 11) node _io_out_s_T_2 = bits(io.in, 5, 5) node _io_out_s_T_3 = bits(io.in, 6, 6) node io_out_s_lo = cat(_io_out_s_T_3, UInt<2>(0h0)) node io_out_s_hi_hi = cat(_io_out_s_T, _io_out_s_T_1) node io_out_s_hi = cat(io_out_s_hi_hi, _io_out_s_T_2) node _io_out_s_T_4 = cat(io_out_s_hi, io_out_s_lo) node _io_out_s_T_5 = bits(io.in, 4, 2) node _io_out_s_T_6 = cat(UInt<2>(0h1), _io_out_s_T_5) node io_out_s_lo_1 = cat(_io_out_s_T_6, io_out_s_opc) node io_out_s_hi_hi_1 = cat(_io_out_s_T_4, UInt<5>(0h2)) node io_out_s_hi_1 = cat(io_out_s_hi_hi_1, UInt<3>(0h0)) node _io_out_s_T_7 = cat(io_out_s_hi_1, io_out_s_lo_1) node _io_out_s_T_8 = bits(io.in, 4, 2) node _io_out_s_T_9 = cat(UInt<2>(0h1), _io_out_s_T_8) node _io_out_s_T_10 = bits(io.in, 4, 2) node _io_out_s_T_11 = cat(UInt<2>(0h1), _io_out_s_T_10) node _io_out_s_T_12 = bits(io.in, 31, 27) wire io_out_s_0 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_0.bits, _io_out_s_T_7 connect io_out_s_0.rd, _io_out_s_T_9 connect io_out_s_0.rs1, UInt<5>(0h2) connect io_out_s_0.rs2, _io_out_s_T_11 connect io_out_s_0.rs3, _io_out_s_T_12 node _io_out_s_T_13 = bits(io.in, 6, 5) node _io_out_s_T_14 = bits(io.in, 12, 10) node io_out_s_hi_2 = cat(_io_out_s_T_13, _io_out_s_T_14) node _io_out_s_T_15 = cat(io_out_s_hi_2, UInt<3>(0h0)) node _io_out_s_T_16 = bits(io.in, 9, 7) node _io_out_s_T_17 = cat(UInt<2>(0h1), _io_out_s_T_16) node _io_out_s_T_18 = bits(io.in, 4, 2) node _io_out_s_T_19 = cat(UInt<2>(0h1), _io_out_s_T_18) node io_out_s_lo_2 = cat(_io_out_s_T_19, UInt<7>(0h7)) node io_out_s_hi_hi_2 = cat(_io_out_s_T_15, _io_out_s_T_17) node io_out_s_hi_3 = cat(io_out_s_hi_hi_2, UInt<3>(0h3)) node _io_out_s_T_20 = cat(io_out_s_hi_3, io_out_s_lo_2) node _io_out_s_T_21 = bits(io.in, 4, 2) node _io_out_s_T_22 = cat(UInt<2>(0h1), _io_out_s_T_21) node _io_out_s_T_23 = bits(io.in, 9, 7) node _io_out_s_T_24 = cat(UInt<2>(0h1), _io_out_s_T_23) node _io_out_s_T_25 = bits(io.in, 4, 2) node _io_out_s_T_26 = cat(UInt<2>(0h1), _io_out_s_T_25) node _io_out_s_T_27 = bits(io.in, 31, 27) wire io_out_s_1 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_1.bits, _io_out_s_T_20 connect io_out_s_1.rd, _io_out_s_T_22 connect io_out_s_1.rs1, _io_out_s_T_24 connect io_out_s_1.rs2, _io_out_s_T_26 connect io_out_s_1.rs3, _io_out_s_T_27 node _io_out_s_T_28 = bits(io.in, 5, 5) node _io_out_s_T_29 = bits(io.in, 12, 10) node _io_out_s_T_30 = bits(io.in, 6, 6) node io_out_s_lo_3 = cat(_io_out_s_T_30, UInt<2>(0h0)) node io_out_s_hi_4 = cat(_io_out_s_T_28, _io_out_s_T_29) node _io_out_s_T_31 = cat(io_out_s_hi_4, io_out_s_lo_3) node _io_out_s_T_32 = bits(io.in, 9, 7) node _io_out_s_T_33 = cat(UInt<2>(0h1), _io_out_s_T_32) node _io_out_s_T_34 = bits(io.in, 4, 2) node _io_out_s_T_35 = cat(UInt<2>(0h1), _io_out_s_T_34) node io_out_s_lo_4 = cat(_io_out_s_T_35, UInt<7>(0h3)) node io_out_s_hi_hi_3 = cat(_io_out_s_T_31, _io_out_s_T_33) node io_out_s_hi_5 = cat(io_out_s_hi_hi_3, UInt<3>(0h2)) node _io_out_s_T_36 = cat(io_out_s_hi_5, io_out_s_lo_4) node _io_out_s_T_37 = bits(io.in, 4, 2) node _io_out_s_T_38 = cat(UInt<2>(0h1), _io_out_s_T_37) node _io_out_s_T_39 = bits(io.in, 9, 7) node _io_out_s_T_40 = cat(UInt<2>(0h1), _io_out_s_T_39) node _io_out_s_T_41 = bits(io.in, 4, 2) node _io_out_s_T_42 = cat(UInt<2>(0h1), _io_out_s_T_41) node _io_out_s_T_43 = bits(io.in, 31, 27) wire io_out_s_2 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_2.bits, _io_out_s_T_36 connect io_out_s_2.rd, _io_out_s_T_38 connect io_out_s_2.rs1, _io_out_s_T_40 connect io_out_s_2.rs2, _io_out_s_T_42 connect io_out_s_2.rs3, _io_out_s_T_43 node _io_out_s_T_44 = bits(io.in, 6, 5) node _io_out_s_T_45 = bits(io.in, 12, 10) node io_out_s_hi_6 = cat(_io_out_s_T_44, _io_out_s_T_45) node _io_out_s_T_46 = cat(io_out_s_hi_6, UInt<3>(0h0)) node _io_out_s_T_47 = bits(io.in, 9, 7) node _io_out_s_T_48 = cat(UInt<2>(0h1), _io_out_s_T_47) node _io_out_s_T_49 = bits(io.in, 4, 2) node _io_out_s_T_50 = cat(UInt<2>(0h1), _io_out_s_T_49) node io_out_s_lo_5 = cat(_io_out_s_T_50, UInt<7>(0h3)) node io_out_s_hi_hi_4 = cat(_io_out_s_T_46, _io_out_s_T_48) node io_out_s_hi_7 = cat(io_out_s_hi_hi_4, UInt<3>(0h3)) node _io_out_s_T_51 = cat(io_out_s_hi_7, io_out_s_lo_5) node _io_out_s_T_52 = bits(io.in, 4, 2) node _io_out_s_T_53 = cat(UInt<2>(0h1), _io_out_s_T_52) node _io_out_s_T_54 = bits(io.in, 9, 7) node _io_out_s_T_55 = cat(UInt<2>(0h1), _io_out_s_T_54) node _io_out_s_T_56 = bits(io.in, 4, 2) node _io_out_s_T_57 = cat(UInt<2>(0h1), _io_out_s_T_56) node _io_out_s_T_58 = bits(io.in, 31, 27) wire io_out_s_3 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_3.bits, _io_out_s_T_51 connect io_out_s_3.rd, _io_out_s_T_53 connect io_out_s_3.rs1, _io_out_s_T_55 connect io_out_s_3.rs2, _io_out_s_T_57 connect io_out_s_3.rs3, _io_out_s_T_58 node _io_out_s_T_59 = bits(io.in, 5, 5) node _io_out_s_T_60 = bits(io.in, 12, 10) node _io_out_s_T_61 = bits(io.in, 6, 6) node io_out_s_lo_6 = cat(_io_out_s_T_61, UInt<2>(0h0)) node io_out_s_hi_8 = cat(_io_out_s_T_59, _io_out_s_T_60) node _io_out_s_T_62 = cat(io_out_s_hi_8, io_out_s_lo_6) node _io_out_s_T_63 = shr(_io_out_s_T_62, 5) node _io_out_s_T_64 = bits(io.in, 4, 2) node _io_out_s_T_65 = cat(UInt<2>(0h1), _io_out_s_T_64) node _io_out_s_T_66 = bits(io.in, 9, 7) node _io_out_s_T_67 = cat(UInt<2>(0h1), _io_out_s_T_66) node _io_out_s_T_68 = bits(io.in, 5, 5) node _io_out_s_T_69 = bits(io.in, 12, 10) node _io_out_s_T_70 = bits(io.in, 6, 6) node io_out_s_lo_7 = cat(_io_out_s_T_70, UInt<2>(0h0)) node io_out_s_hi_9 = cat(_io_out_s_T_68, _io_out_s_T_69) node _io_out_s_T_71 = cat(io_out_s_hi_9, io_out_s_lo_7) node _io_out_s_T_72 = bits(_io_out_s_T_71, 4, 0) node io_out_s_lo_hi = cat(UInt<3>(0h2), _io_out_s_T_72) node io_out_s_lo_8 = cat(io_out_s_lo_hi, UInt<7>(0h3f)) node io_out_s_hi_hi_5 = cat(_io_out_s_T_63, _io_out_s_T_65) node io_out_s_hi_10 = cat(io_out_s_hi_hi_5, _io_out_s_T_67) node _io_out_s_T_73 = cat(io_out_s_hi_10, io_out_s_lo_8) node _io_out_s_T_74 = bits(io.in, 4, 2) node _io_out_s_T_75 = cat(UInt<2>(0h1), _io_out_s_T_74) node _io_out_s_T_76 = bits(io.in, 9, 7) node _io_out_s_T_77 = cat(UInt<2>(0h1), _io_out_s_T_76) node _io_out_s_T_78 = bits(io.in, 4, 2) node _io_out_s_T_79 = cat(UInt<2>(0h1), _io_out_s_T_78) node _io_out_s_T_80 = bits(io.in, 31, 27) wire io_out_s_4 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_4.bits, _io_out_s_T_73 connect io_out_s_4.rd, _io_out_s_T_75 connect io_out_s_4.rs1, _io_out_s_T_77 connect io_out_s_4.rs2, _io_out_s_T_79 connect io_out_s_4.rs3, _io_out_s_T_80 node _io_out_s_T_81 = bits(io.in, 6, 5) node _io_out_s_T_82 = bits(io.in, 12, 10) node io_out_s_hi_11 = cat(_io_out_s_T_81, _io_out_s_T_82) node _io_out_s_T_83 = cat(io_out_s_hi_11, UInt<3>(0h0)) node _io_out_s_T_84 = shr(_io_out_s_T_83, 5) node _io_out_s_T_85 = bits(io.in, 4, 2) node _io_out_s_T_86 = cat(UInt<2>(0h1), _io_out_s_T_85) node _io_out_s_T_87 = bits(io.in, 9, 7) node _io_out_s_T_88 = cat(UInt<2>(0h1), _io_out_s_T_87) node _io_out_s_T_89 = bits(io.in, 6, 5) node _io_out_s_T_90 = bits(io.in, 12, 10) node io_out_s_hi_12 = cat(_io_out_s_T_89, _io_out_s_T_90) node _io_out_s_T_91 = cat(io_out_s_hi_12, UInt<3>(0h0)) node _io_out_s_T_92 = bits(_io_out_s_T_91, 4, 0) node io_out_s_lo_hi_1 = cat(UInt<3>(0h3), _io_out_s_T_92) node io_out_s_lo_9 = cat(io_out_s_lo_hi_1, UInt<7>(0h27)) node io_out_s_hi_hi_6 = cat(_io_out_s_T_84, _io_out_s_T_86) node io_out_s_hi_13 = cat(io_out_s_hi_hi_6, _io_out_s_T_88) node _io_out_s_T_93 = cat(io_out_s_hi_13, io_out_s_lo_9) node _io_out_s_T_94 = bits(io.in, 4, 2) node _io_out_s_T_95 = cat(UInt<2>(0h1), _io_out_s_T_94) node _io_out_s_T_96 = bits(io.in, 9, 7) node _io_out_s_T_97 = cat(UInt<2>(0h1), _io_out_s_T_96) node _io_out_s_T_98 = bits(io.in, 4, 2) node _io_out_s_T_99 = cat(UInt<2>(0h1), _io_out_s_T_98) node _io_out_s_T_100 = bits(io.in, 31, 27) wire io_out_s_5 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_5.bits, _io_out_s_T_93 connect io_out_s_5.rd, _io_out_s_T_95 connect io_out_s_5.rs1, _io_out_s_T_97 connect io_out_s_5.rs2, _io_out_s_T_99 connect io_out_s_5.rs3, _io_out_s_T_100 node _io_out_s_T_101 = bits(io.in, 5, 5) node _io_out_s_T_102 = bits(io.in, 12, 10) node _io_out_s_T_103 = bits(io.in, 6, 6) node io_out_s_lo_10 = cat(_io_out_s_T_103, UInt<2>(0h0)) node io_out_s_hi_14 = cat(_io_out_s_T_101, _io_out_s_T_102) node _io_out_s_T_104 = cat(io_out_s_hi_14, io_out_s_lo_10) node _io_out_s_T_105 = shr(_io_out_s_T_104, 5) node _io_out_s_T_106 = bits(io.in, 4, 2) node _io_out_s_T_107 = cat(UInt<2>(0h1), _io_out_s_T_106) node _io_out_s_T_108 = bits(io.in, 9, 7) node _io_out_s_T_109 = cat(UInt<2>(0h1), _io_out_s_T_108) node _io_out_s_T_110 = bits(io.in, 5, 5) node _io_out_s_T_111 = bits(io.in, 12, 10) node _io_out_s_T_112 = bits(io.in, 6, 6) node io_out_s_lo_11 = cat(_io_out_s_T_112, UInt<2>(0h0)) node io_out_s_hi_15 = cat(_io_out_s_T_110, _io_out_s_T_111) node _io_out_s_T_113 = cat(io_out_s_hi_15, io_out_s_lo_11) node _io_out_s_T_114 = bits(_io_out_s_T_113, 4, 0) node io_out_s_lo_hi_2 = cat(UInt<3>(0h2), _io_out_s_T_114) node io_out_s_lo_12 = cat(io_out_s_lo_hi_2, UInt<7>(0h23)) node io_out_s_hi_hi_7 = cat(_io_out_s_T_105, _io_out_s_T_107) node io_out_s_hi_16 = cat(io_out_s_hi_hi_7, _io_out_s_T_109) node _io_out_s_T_115 = cat(io_out_s_hi_16, io_out_s_lo_12) node _io_out_s_T_116 = bits(io.in, 4, 2) node _io_out_s_T_117 = cat(UInt<2>(0h1), _io_out_s_T_116) node _io_out_s_T_118 = bits(io.in, 9, 7) node _io_out_s_T_119 = cat(UInt<2>(0h1), _io_out_s_T_118) node _io_out_s_T_120 = bits(io.in, 4, 2) node _io_out_s_T_121 = cat(UInt<2>(0h1), _io_out_s_T_120) node _io_out_s_T_122 = bits(io.in, 31, 27) wire io_out_s_6 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_6.bits, _io_out_s_T_115 connect io_out_s_6.rd, _io_out_s_T_117 connect io_out_s_6.rs1, _io_out_s_T_119 connect io_out_s_6.rs2, _io_out_s_T_121 connect io_out_s_6.rs3, _io_out_s_T_122 node _io_out_s_T_123 = bits(io.in, 6, 5) node _io_out_s_T_124 = bits(io.in, 12, 10) node io_out_s_hi_17 = cat(_io_out_s_T_123, _io_out_s_T_124) node _io_out_s_T_125 = cat(io_out_s_hi_17, UInt<3>(0h0)) node _io_out_s_T_126 = shr(_io_out_s_T_125, 5) node _io_out_s_T_127 = bits(io.in, 4, 2) node _io_out_s_T_128 = cat(UInt<2>(0h1), _io_out_s_T_127) node _io_out_s_T_129 = bits(io.in, 9, 7) node _io_out_s_T_130 = cat(UInt<2>(0h1), _io_out_s_T_129) node _io_out_s_T_131 = bits(io.in, 6, 5) node _io_out_s_T_132 = bits(io.in, 12, 10) node io_out_s_hi_18 = cat(_io_out_s_T_131, _io_out_s_T_132) node _io_out_s_T_133 = cat(io_out_s_hi_18, UInt<3>(0h0)) node _io_out_s_T_134 = bits(_io_out_s_T_133, 4, 0) node io_out_s_lo_hi_3 = cat(UInt<3>(0h3), _io_out_s_T_134) node io_out_s_lo_13 = cat(io_out_s_lo_hi_3, UInt<7>(0h23)) node io_out_s_hi_hi_8 = cat(_io_out_s_T_126, _io_out_s_T_128) node io_out_s_hi_19 = cat(io_out_s_hi_hi_8, _io_out_s_T_130) node _io_out_s_T_135 = cat(io_out_s_hi_19, io_out_s_lo_13) node _io_out_s_T_136 = bits(io.in, 4, 2) node _io_out_s_T_137 = cat(UInt<2>(0h1), _io_out_s_T_136) node _io_out_s_T_138 = bits(io.in, 9, 7) node _io_out_s_T_139 = cat(UInt<2>(0h1), _io_out_s_T_138) node _io_out_s_T_140 = bits(io.in, 4, 2) node _io_out_s_T_141 = cat(UInt<2>(0h1), _io_out_s_T_140) node _io_out_s_T_142 = bits(io.in, 31, 27) wire io_out_s_7 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_7.bits, _io_out_s_T_135 connect io_out_s_7.rd, _io_out_s_T_137 connect io_out_s_7.rs1, _io_out_s_T_139 connect io_out_s_7.rs2, _io_out_s_T_141 connect io_out_s_7.rs3, _io_out_s_T_142 node _io_out_s_T_143 = bits(io.in, 12, 12) node _io_out_s_T_144 = mux(_io_out_s_T_143, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_145 = bits(io.in, 6, 2) node _io_out_s_T_146 = cat(_io_out_s_T_144, _io_out_s_T_145) node _io_out_s_T_147 = bits(io.in, 11, 7) node _io_out_s_T_148 = bits(io.in, 11, 7) node io_out_s_lo_14 = cat(_io_out_s_T_148, UInt<7>(0h13)) node io_out_s_hi_hi_9 = cat(_io_out_s_T_146, _io_out_s_T_147) node io_out_s_hi_20 = cat(io_out_s_hi_hi_9, UInt<3>(0h0)) node _io_out_s_T_149 = cat(io_out_s_hi_20, io_out_s_lo_14) node _io_out_s_T_150 = bits(io.in, 11, 7) node _io_out_s_T_151 = bits(io.in, 11, 7) node _io_out_s_T_152 = bits(io.in, 4, 2) node _io_out_s_T_153 = cat(UInt<2>(0h1), _io_out_s_T_152) node _io_out_s_T_154 = bits(io.in, 31, 27) wire io_out_s_8 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_8.bits, _io_out_s_T_149 connect io_out_s_8.rd, _io_out_s_T_150 connect io_out_s_8.rs1, _io_out_s_T_151 connect io_out_s_8.rs2, _io_out_s_T_153 connect io_out_s_8.rs3, _io_out_s_T_154 node _io_out_s_opc_T_2 = bits(io.in, 11, 7) node _io_out_s_opc_T_3 = orr(_io_out_s_opc_T_2) node io_out_s_opc_1 = mux(_io_out_s_opc_T_3, UInt<7>(0h1b), UInt<7>(0h1f)) node _io_out_s_T_155 = bits(io.in, 12, 12) node _io_out_s_T_156 = mux(_io_out_s_T_155, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_157 = bits(io.in, 6, 2) node _io_out_s_T_158 = cat(_io_out_s_T_156, _io_out_s_T_157) node _io_out_s_T_159 = bits(io.in, 11, 7) node _io_out_s_T_160 = bits(io.in, 11, 7) node io_out_s_lo_15 = cat(_io_out_s_T_160, io_out_s_opc_1) node io_out_s_hi_hi_10 = cat(_io_out_s_T_158, _io_out_s_T_159) node io_out_s_hi_21 = cat(io_out_s_hi_hi_10, UInt<3>(0h0)) node _io_out_s_T_161 = cat(io_out_s_hi_21, io_out_s_lo_15) node _io_out_s_T_162 = bits(io.in, 11, 7) node _io_out_s_T_163 = bits(io.in, 11, 7) node _io_out_s_T_164 = bits(io.in, 4, 2) node _io_out_s_T_165 = cat(UInt<2>(0h1), _io_out_s_T_164) node _io_out_s_T_166 = bits(io.in, 31, 27) wire io_out_s_9 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_9.bits, _io_out_s_T_161 connect io_out_s_9.rd, _io_out_s_T_162 connect io_out_s_9.rs1, _io_out_s_T_163 connect io_out_s_9.rs2, _io_out_s_T_165 connect io_out_s_9.rs3, _io_out_s_T_166 node _io_out_s_T_167 = bits(io.in, 12, 12) node _io_out_s_T_168 = mux(_io_out_s_T_167, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_169 = bits(io.in, 6, 2) node _io_out_s_T_170 = cat(_io_out_s_T_168, _io_out_s_T_169) node _io_out_s_T_171 = bits(io.in, 11, 7) node io_out_s_lo_16 = cat(_io_out_s_T_171, UInt<7>(0h13)) node io_out_s_hi_hi_11 = cat(_io_out_s_T_170, UInt<5>(0h0)) node io_out_s_hi_22 = cat(io_out_s_hi_hi_11, UInt<3>(0h0)) node _io_out_s_T_172 = cat(io_out_s_hi_22, io_out_s_lo_16) node _io_out_s_T_173 = bits(io.in, 11, 7) node _io_out_s_T_174 = bits(io.in, 4, 2) node _io_out_s_T_175 = cat(UInt<2>(0h1), _io_out_s_T_174) node _io_out_s_T_176 = bits(io.in, 31, 27) wire io_out_s_10 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_10.bits, _io_out_s_T_172 connect io_out_s_10.rd, _io_out_s_T_173 connect io_out_s_10.rs1, UInt<5>(0h0) connect io_out_s_10.rs2, _io_out_s_T_175 connect io_out_s_10.rs3, _io_out_s_T_176 node _io_out_s_opc_T_4 = bits(io.in, 12, 12) node _io_out_s_opc_T_5 = mux(_io_out_s_opc_T_4, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_opc_T_6 = bits(io.in, 6, 2) node _io_out_s_opc_T_7 = cat(_io_out_s_opc_T_5, _io_out_s_opc_T_6) node _io_out_s_opc_T_8 = orr(_io_out_s_opc_T_7) node io_out_s_opc_2 = mux(_io_out_s_opc_T_8, UInt<7>(0h37), UInt<7>(0h3f)) node _io_out_s_me_T = bits(io.in, 12, 12) node _io_out_s_me_T_1 = mux(_io_out_s_me_T, UInt<15>(0h7fff), UInt<15>(0h0)) node _io_out_s_me_T_2 = bits(io.in, 6, 2) node io_out_s_me_hi = cat(_io_out_s_me_T_1, _io_out_s_me_T_2) node _io_out_s_me_T_3 = cat(io_out_s_me_hi, UInt<12>(0h0)) node _io_out_s_me_T_4 = bits(_io_out_s_me_T_3, 31, 12) node _io_out_s_me_T_5 = bits(io.in, 11, 7) node io_out_s_me_hi_1 = cat(_io_out_s_me_T_4, _io_out_s_me_T_5) node _io_out_s_me_T_6 = cat(io_out_s_me_hi_1, io_out_s_opc_2) node _io_out_s_me_T_7 = bits(io.in, 11, 7) node _io_out_s_me_T_8 = bits(io.in, 11, 7) node _io_out_s_me_T_9 = bits(io.in, 4, 2) node _io_out_s_me_T_10 = cat(UInt<2>(0h1), _io_out_s_me_T_9) node _io_out_s_me_T_11 = bits(io.in, 31, 27) wire io_out_s_me : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_me.bits, _io_out_s_me_T_6 connect io_out_s_me.rd, _io_out_s_me_T_7 connect io_out_s_me.rs1, _io_out_s_me_T_8 connect io_out_s_me.rs2, _io_out_s_me_T_10 connect io_out_s_me.rs3, _io_out_s_me_T_11 node _io_out_s_T_177 = bits(io.in, 11, 7) node _io_out_s_T_178 = eq(_io_out_s_T_177, UInt<5>(0h0)) node _io_out_s_T_179 = bits(io.in, 11, 7) node _io_out_s_T_180 = eq(_io_out_s_T_179, UInt<5>(0h2)) node _io_out_s_T_181 = or(_io_out_s_T_178, _io_out_s_T_180) node _io_out_s_opc_T_9 = bits(io.in, 12, 12) node _io_out_s_opc_T_10 = mux(_io_out_s_opc_T_9, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_opc_T_11 = bits(io.in, 6, 2) node _io_out_s_opc_T_12 = cat(_io_out_s_opc_T_10, _io_out_s_opc_T_11) node _io_out_s_opc_T_13 = orr(_io_out_s_opc_T_12) node io_out_s_opc_3 = mux(_io_out_s_opc_T_13, UInt<7>(0h13), UInt<7>(0h1f)) node _io_out_s_T_182 = bits(io.in, 12, 12) node _io_out_s_T_183 = mux(_io_out_s_T_182, UInt<3>(0h7), UInt<3>(0h0)) node _io_out_s_T_184 = bits(io.in, 4, 3) node _io_out_s_T_185 = bits(io.in, 5, 5) node _io_out_s_T_186 = bits(io.in, 2, 2) node _io_out_s_T_187 = bits(io.in, 6, 6) node io_out_s_lo_hi_4 = cat(_io_out_s_T_186, _io_out_s_T_187) node io_out_s_lo_17 = cat(io_out_s_lo_hi_4, UInt<4>(0h0)) node io_out_s_hi_hi_12 = cat(_io_out_s_T_183, _io_out_s_T_184) node io_out_s_hi_23 = cat(io_out_s_hi_hi_12, _io_out_s_T_185) node _io_out_s_T_188 = cat(io_out_s_hi_23, io_out_s_lo_17) node _io_out_s_T_189 = bits(io.in, 11, 7) node _io_out_s_T_190 = bits(io.in, 11, 7) node io_out_s_lo_18 = cat(_io_out_s_T_190, io_out_s_opc_3) node io_out_s_hi_hi_13 = cat(_io_out_s_T_188, _io_out_s_T_189) node io_out_s_hi_24 = cat(io_out_s_hi_hi_13, UInt<3>(0h0)) node _io_out_s_T_191 = cat(io_out_s_hi_24, io_out_s_lo_18) node _io_out_s_T_192 = bits(io.in, 11, 7) node _io_out_s_T_193 = bits(io.in, 11, 7) node _io_out_s_T_194 = bits(io.in, 4, 2) node _io_out_s_T_195 = cat(UInt<2>(0h1), _io_out_s_T_194) node _io_out_s_T_196 = bits(io.in, 31, 27) wire io_out_s_res : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_res.bits, _io_out_s_T_191 connect io_out_s_res.rd, _io_out_s_T_192 connect io_out_s_res.rs1, _io_out_s_T_193 connect io_out_s_res.rs2, _io_out_s_T_195 connect io_out_s_res.rs3, _io_out_s_T_196 node io_out_s_11 = mux(_io_out_s_T_181, io_out_s_res, io_out_s_me) node _io_out_s_T_197 = bits(io.in, 12, 12) node _io_out_s_T_198 = bits(io.in, 6, 2) node _io_out_s_T_199 = cat(_io_out_s_T_197, _io_out_s_T_198) node _io_out_s_T_200 = bits(io.in, 9, 7) node _io_out_s_T_201 = cat(UInt<2>(0h1), _io_out_s_T_200) node _io_out_s_T_202 = bits(io.in, 9, 7) node _io_out_s_T_203 = cat(UInt<2>(0h1), _io_out_s_T_202) node io_out_s_lo_19 = cat(_io_out_s_T_203, UInt<7>(0h13)) node io_out_s_hi_hi_14 = cat(_io_out_s_T_199, _io_out_s_T_201) node io_out_s_hi_25 = cat(io_out_s_hi_hi_14, UInt<3>(0h5)) node _io_out_s_T_204 = cat(io_out_s_hi_25, io_out_s_lo_19) node _io_out_s_T_205 = bits(io.in, 12, 12) node _io_out_s_T_206 = bits(io.in, 6, 2) node _io_out_s_T_207 = cat(_io_out_s_T_205, _io_out_s_T_206) node _io_out_s_T_208 = bits(io.in, 9, 7) node _io_out_s_T_209 = cat(UInt<2>(0h1), _io_out_s_T_208) node _io_out_s_T_210 = bits(io.in, 9, 7) node _io_out_s_T_211 = cat(UInt<2>(0h1), _io_out_s_T_210) node io_out_s_lo_20 = cat(_io_out_s_T_211, UInt<7>(0h13)) node io_out_s_hi_hi_15 = cat(_io_out_s_T_207, _io_out_s_T_209) node io_out_s_hi_26 = cat(io_out_s_hi_hi_15, UInt<3>(0h5)) node _io_out_s_T_212 = cat(io_out_s_hi_26, io_out_s_lo_20) node _io_out_s_T_213 = or(_io_out_s_T_212, UInt<31>(0h40000000)) node _io_out_s_T_214 = bits(io.in, 12, 12) node _io_out_s_T_215 = mux(_io_out_s_T_214, UInt<7>(0h7f), UInt<7>(0h0)) node _io_out_s_T_216 = bits(io.in, 6, 2) node _io_out_s_T_217 = cat(_io_out_s_T_215, _io_out_s_T_216) node _io_out_s_T_218 = bits(io.in, 9, 7) node _io_out_s_T_219 = cat(UInt<2>(0h1), _io_out_s_T_218) node _io_out_s_T_220 = bits(io.in, 9, 7) node _io_out_s_T_221 = cat(UInt<2>(0h1), _io_out_s_T_220) node io_out_s_lo_21 = cat(_io_out_s_T_221, UInt<7>(0h13)) node io_out_s_hi_hi_16 = cat(_io_out_s_T_217, _io_out_s_T_219) node io_out_s_hi_27 = cat(io_out_s_hi_hi_16, UInt<3>(0h7)) node _io_out_s_T_222 = cat(io_out_s_hi_27, io_out_s_lo_21) node _io_out_s_funct_T = bits(io.in, 12, 12) node _io_out_s_funct_T_1 = bits(io.in, 6, 5) node _io_out_s_funct_T_2 = cat(_io_out_s_funct_T, _io_out_s_funct_T_1) node _io_out_s_funct_T_3 = eq(_io_out_s_funct_T_2, UInt<1>(0h1)) node _io_out_s_funct_T_4 = mux(_io_out_s_funct_T_3, UInt<3>(0h4), UInt<1>(0h0)) node _io_out_s_funct_T_5 = eq(_io_out_s_funct_T_2, UInt<2>(0h2)) node _io_out_s_funct_T_6 = mux(_io_out_s_funct_T_5, UInt<3>(0h6), _io_out_s_funct_T_4) node _io_out_s_funct_T_7 = eq(_io_out_s_funct_T_2, UInt<2>(0h3)) node _io_out_s_funct_T_8 = mux(_io_out_s_funct_T_7, UInt<3>(0h7), _io_out_s_funct_T_6) node _io_out_s_funct_T_9 = eq(_io_out_s_funct_T_2, UInt<3>(0h4)) node _io_out_s_funct_T_10 = mux(_io_out_s_funct_T_9, UInt<1>(0h0), _io_out_s_funct_T_8) node _io_out_s_funct_T_11 = eq(_io_out_s_funct_T_2, UInt<3>(0h5)) node _io_out_s_funct_T_12 = mux(_io_out_s_funct_T_11, UInt<1>(0h0), _io_out_s_funct_T_10) node _io_out_s_funct_T_13 = eq(_io_out_s_funct_T_2, UInt<3>(0h6)) node _io_out_s_funct_T_14 = mux(_io_out_s_funct_T_13, UInt<2>(0h2), _io_out_s_funct_T_12) node _io_out_s_funct_T_15 = eq(_io_out_s_funct_T_2, UInt<3>(0h7)) node io_out_s_funct = mux(_io_out_s_funct_T_15, UInt<2>(0h3), _io_out_s_funct_T_14) node _io_out_s_sub_T = bits(io.in, 6, 5) node _io_out_s_sub_T_1 = eq(_io_out_s_sub_T, UInt<1>(0h0)) node io_out_s_sub = mux(_io_out_s_sub_T_1, UInt<31>(0h40000000), UInt<1>(0h0)) node _io_out_s_opc_T_14 = bits(io.in, 12, 12) node io_out_s_opc_4 = mux(_io_out_s_opc_T_14, UInt<7>(0h3b), UInt<7>(0h33)) node _io_out_s_T_223 = bits(io.in, 4, 2) node _io_out_s_T_224 = cat(UInt<2>(0h1), _io_out_s_T_223) node _io_out_s_T_225 = bits(io.in, 9, 7) node _io_out_s_T_226 = cat(UInt<2>(0h1), _io_out_s_T_225) node _io_out_s_T_227 = bits(io.in, 9, 7) node _io_out_s_T_228 = cat(UInt<2>(0h1), _io_out_s_T_227) node io_out_s_lo_22 = cat(_io_out_s_T_228, io_out_s_opc_4) node io_out_s_hi_hi_17 = cat(_io_out_s_T_224, _io_out_s_T_226) node io_out_s_hi_28 = cat(io_out_s_hi_hi_17, io_out_s_funct) node _io_out_s_T_229 = cat(io_out_s_hi_28, io_out_s_lo_22) node _io_out_s_T_230 = or(_io_out_s_T_229, io_out_s_sub) node _io_out_s_T_231 = bits(io.in, 11, 10) node _io_out_s_T_232 = eq(_io_out_s_T_231, UInt<1>(0h1)) node _io_out_s_T_233 = mux(_io_out_s_T_232, _io_out_s_T_213, _io_out_s_T_204) node _io_out_s_T_234 = eq(_io_out_s_T_231, UInt<2>(0h2)) node _io_out_s_T_235 = mux(_io_out_s_T_234, _io_out_s_T_222, _io_out_s_T_233) node _io_out_s_T_236 = eq(_io_out_s_T_231, UInt<2>(0h3)) node _io_out_s_T_237 = mux(_io_out_s_T_236, _io_out_s_T_230, _io_out_s_T_235) node _io_out_s_T_238 = bits(io.in, 9, 7) node _io_out_s_T_239 = cat(UInt<2>(0h1), _io_out_s_T_238) node _io_out_s_T_240 = bits(io.in, 9, 7) node _io_out_s_T_241 = cat(UInt<2>(0h1), _io_out_s_T_240) node _io_out_s_T_242 = bits(io.in, 4, 2) node _io_out_s_T_243 = cat(UInt<2>(0h1), _io_out_s_T_242) node _io_out_s_T_244 = bits(io.in, 31, 27) wire io_out_s_12 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_12.bits, _io_out_s_T_237 connect io_out_s_12.rd, _io_out_s_T_239 connect io_out_s_12.rs1, _io_out_s_T_241 connect io_out_s_12.rs2, _io_out_s_T_243 connect io_out_s_12.rs3, _io_out_s_T_244 node _io_out_s_T_245 = bits(io.in, 12, 12) node _io_out_s_T_246 = mux(_io_out_s_T_245, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_247 = bits(io.in, 8, 8) node _io_out_s_T_248 = bits(io.in, 10, 9) node _io_out_s_T_249 = bits(io.in, 6, 6) node _io_out_s_T_250 = bits(io.in, 7, 7) node _io_out_s_T_251 = bits(io.in, 2, 2) node _io_out_s_T_252 = bits(io.in, 11, 11) node _io_out_s_T_253 = bits(io.in, 5, 3) node io_out_s_lo_lo = cat(_io_out_s_T_253, UInt<1>(0h0)) node io_out_s_lo_hi_5 = cat(_io_out_s_T_251, _io_out_s_T_252) node io_out_s_lo_23 = cat(io_out_s_lo_hi_5, io_out_s_lo_lo) node io_out_s_hi_lo = cat(_io_out_s_T_249, _io_out_s_T_250) node io_out_s_hi_hi_hi = cat(_io_out_s_T_246, _io_out_s_T_247) node io_out_s_hi_hi_18 = cat(io_out_s_hi_hi_hi, _io_out_s_T_248) node io_out_s_hi_29 = cat(io_out_s_hi_hi_18, io_out_s_hi_lo) node _io_out_s_T_254 = cat(io_out_s_hi_29, io_out_s_lo_23) node _io_out_s_T_255 = bits(_io_out_s_T_254, 20, 20) node _io_out_s_T_256 = bits(io.in, 12, 12) node _io_out_s_T_257 = mux(_io_out_s_T_256, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_258 = bits(io.in, 8, 8) node _io_out_s_T_259 = bits(io.in, 10, 9) node _io_out_s_T_260 = bits(io.in, 6, 6) node _io_out_s_T_261 = bits(io.in, 7, 7) node _io_out_s_T_262 = bits(io.in, 2, 2) node _io_out_s_T_263 = bits(io.in, 11, 11) node _io_out_s_T_264 = bits(io.in, 5, 3) node io_out_s_lo_lo_1 = cat(_io_out_s_T_264, UInt<1>(0h0)) node io_out_s_lo_hi_6 = cat(_io_out_s_T_262, _io_out_s_T_263) node io_out_s_lo_24 = cat(io_out_s_lo_hi_6, io_out_s_lo_lo_1) node io_out_s_hi_lo_1 = cat(_io_out_s_T_260, _io_out_s_T_261) node io_out_s_hi_hi_hi_1 = cat(_io_out_s_T_257, _io_out_s_T_258) node io_out_s_hi_hi_19 = cat(io_out_s_hi_hi_hi_1, _io_out_s_T_259) node io_out_s_hi_30 = cat(io_out_s_hi_hi_19, io_out_s_hi_lo_1) node _io_out_s_T_265 = cat(io_out_s_hi_30, io_out_s_lo_24) node _io_out_s_T_266 = bits(_io_out_s_T_265, 10, 1) node _io_out_s_T_267 = bits(io.in, 12, 12) node _io_out_s_T_268 = mux(_io_out_s_T_267, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_269 = bits(io.in, 8, 8) node _io_out_s_T_270 = bits(io.in, 10, 9) node _io_out_s_T_271 = bits(io.in, 6, 6) node _io_out_s_T_272 = bits(io.in, 7, 7) node _io_out_s_T_273 = bits(io.in, 2, 2) node _io_out_s_T_274 = bits(io.in, 11, 11) node _io_out_s_T_275 = bits(io.in, 5, 3) node io_out_s_lo_lo_2 = cat(_io_out_s_T_275, UInt<1>(0h0)) node io_out_s_lo_hi_7 = cat(_io_out_s_T_273, _io_out_s_T_274) node io_out_s_lo_25 = cat(io_out_s_lo_hi_7, io_out_s_lo_lo_2) node io_out_s_hi_lo_2 = cat(_io_out_s_T_271, _io_out_s_T_272) node io_out_s_hi_hi_hi_2 = cat(_io_out_s_T_268, _io_out_s_T_269) node io_out_s_hi_hi_20 = cat(io_out_s_hi_hi_hi_2, _io_out_s_T_270) node io_out_s_hi_31 = cat(io_out_s_hi_hi_20, io_out_s_hi_lo_2) node _io_out_s_T_276 = cat(io_out_s_hi_31, io_out_s_lo_25) node _io_out_s_T_277 = bits(_io_out_s_T_276, 11, 11) node _io_out_s_T_278 = bits(io.in, 12, 12) node _io_out_s_T_279 = mux(_io_out_s_T_278, UInt<10>(0h3ff), UInt<10>(0h0)) node _io_out_s_T_280 = bits(io.in, 8, 8) node _io_out_s_T_281 = bits(io.in, 10, 9) node _io_out_s_T_282 = bits(io.in, 6, 6) node _io_out_s_T_283 = bits(io.in, 7, 7) node _io_out_s_T_284 = bits(io.in, 2, 2) node _io_out_s_T_285 = bits(io.in, 11, 11) node _io_out_s_T_286 = bits(io.in, 5, 3) node io_out_s_lo_lo_3 = cat(_io_out_s_T_286, UInt<1>(0h0)) node io_out_s_lo_hi_8 = cat(_io_out_s_T_284, _io_out_s_T_285) node io_out_s_lo_26 = cat(io_out_s_lo_hi_8, io_out_s_lo_lo_3) node io_out_s_hi_lo_3 = cat(_io_out_s_T_282, _io_out_s_T_283) node io_out_s_hi_hi_hi_3 = cat(_io_out_s_T_279, _io_out_s_T_280) node io_out_s_hi_hi_21 = cat(io_out_s_hi_hi_hi_3, _io_out_s_T_281) node io_out_s_hi_32 = cat(io_out_s_hi_hi_21, io_out_s_hi_lo_3) node _io_out_s_T_287 = cat(io_out_s_hi_32, io_out_s_lo_26) node _io_out_s_T_288 = bits(_io_out_s_T_287, 19, 12) node io_out_s_lo_hi_9 = cat(_io_out_s_T_288, UInt<5>(0h0)) node io_out_s_lo_27 = cat(io_out_s_lo_hi_9, UInt<7>(0h6f)) node io_out_s_hi_hi_22 = cat(_io_out_s_T_255, _io_out_s_T_266) node io_out_s_hi_33 = cat(io_out_s_hi_hi_22, _io_out_s_T_277) node _io_out_s_T_289 = cat(io_out_s_hi_33, io_out_s_lo_27) node _io_out_s_T_290 = bits(io.in, 9, 7) node _io_out_s_T_291 = cat(UInt<2>(0h1), _io_out_s_T_290) node _io_out_s_T_292 = bits(io.in, 4, 2) node _io_out_s_T_293 = cat(UInt<2>(0h1), _io_out_s_T_292) node _io_out_s_T_294 = bits(io.in, 31, 27) wire io_out_s_13 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_13.bits, _io_out_s_T_289 connect io_out_s_13.rd, UInt<5>(0h0) connect io_out_s_13.rs1, _io_out_s_T_291 connect io_out_s_13.rs2, _io_out_s_T_293 connect io_out_s_13.rs3, _io_out_s_T_294 node _io_out_s_T_295 = bits(io.in, 12, 12) node _io_out_s_T_296 = mux(_io_out_s_T_295, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_297 = bits(io.in, 6, 5) node _io_out_s_T_298 = bits(io.in, 2, 2) node _io_out_s_T_299 = bits(io.in, 11, 10) node _io_out_s_T_300 = bits(io.in, 4, 3) node io_out_s_lo_hi_10 = cat(_io_out_s_T_299, _io_out_s_T_300) node io_out_s_lo_28 = cat(io_out_s_lo_hi_10, UInt<1>(0h0)) node io_out_s_hi_hi_23 = cat(_io_out_s_T_296, _io_out_s_T_297) node io_out_s_hi_34 = cat(io_out_s_hi_hi_23, _io_out_s_T_298) node _io_out_s_T_301 = cat(io_out_s_hi_34, io_out_s_lo_28) node _io_out_s_T_302 = bits(_io_out_s_T_301, 12, 12) node _io_out_s_T_303 = bits(io.in, 12, 12) node _io_out_s_T_304 = mux(_io_out_s_T_303, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_305 = bits(io.in, 6, 5) node _io_out_s_T_306 = bits(io.in, 2, 2) node _io_out_s_T_307 = bits(io.in, 11, 10) node _io_out_s_T_308 = bits(io.in, 4, 3) node io_out_s_lo_hi_11 = cat(_io_out_s_T_307, _io_out_s_T_308) node io_out_s_lo_29 = cat(io_out_s_lo_hi_11, UInt<1>(0h0)) node io_out_s_hi_hi_24 = cat(_io_out_s_T_304, _io_out_s_T_305) node io_out_s_hi_35 = cat(io_out_s_hi_hi_24, _io_out_s_T_306) node _io_out_s_T_309 = cat(io_out_s_hi_35, io_out_s_lo_29) node _io_out_s_T_310 = bits(_io_out_s_T_309, 10, 5) node _io_out_s_T_311 = bits(io.in, 9, 7) node _io_out_s_T_312 = cat(UInt<2>(0h1), _io_out_s_T_311) node _io_out_s_T_313 = bits(io.in, 12, 12) node _io_out_s_T_314 = mux(_io_out_s_T_313, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_315 = bits(io.in, 6, 5) node _io_out_s_T_316 = bits(io.in, 2, 2) node _io_out_s_T_317 = bits(io.in, 11, 10) node _io_out_s_T_318 = bits(io.in, 4, 3) node io_out_s_lo_hi_12 = cat(_io_out_s_T_317, _io_out_s_T_318) node io_out_s_lo_30 = cat(io_out_s_lo_hi_12, UInt<1>(0h0)) node io_out_s_hi_hi_25 = cat(_io_out_s_T_314, _io_out_s_T_315) node io_out_s_hi_36 = cat(io_out_s_hi_hi_25, _io_out_s_T_316) node _io_out_s_T_319 = cat(io_out_s_hi_36, io_out_s_lo_30) node _io_out_s_T_320 = bits(_io_out_s_T_319, 4, 1) node _io_out_s_T_321 = bits(io.in, 12, 12) node _io_out_s_T_322 = mux(_io_out_s_T_321, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_323 = bits(io.in, 6, 5) node _io_out_s_T_324 = bits(io.in, 2, 2) node _io_out_s_T_325 = bits(io.in, 11, 10) node _io_out_s_T_326 = bits(io.in, 4, 3) node io_out_s_lo_hi_13 = cat(_io_out_s_T_325, _io_out_s_T_326) node io_out_s_lo_31 = cat(io_out_s_lo_hi_13, UInt<1>(0h0)) node io_out_s_hi_hi_26 = cat(_io_out_s_T_322, _io_out_s_T_323) node io_out_s_hi_37 = cat(io_out_s_hi_hi_26, _io_out_s_T_324) node _io_out_s_T_327 = cat(io_out_s_hi_37, io_out_s_lo_31) node _io_out_s_T_328 = bits(_io_out_s_T_327, 11, 11) node io_out_s_lo_lo_4 = cat(_io_out_s_T_328, UInt<7>(0h63)) node io_out_s_lo_hi_14 = cat(UInt<3>(0h0), _io_out_s_T_320) node io_out_s_lo_32 = cat(io_out_s_lo_hi_14, io_out_s_lo_lo_4) node io_out_s_hi_lo_4 = cat(UInt<5>(0h0), _io_out_s_T_312) node io_out_s_hi_hi_27 = cat(_io_out_s_T_302, _io_out_s_T_310) node io_out_s_hi_38 = cat(io_out_s_hi_hi_27, io_out_s_hi_lo_4) node _io_out_s_T_329 = cat(io_out_s_hi_38, io_out_s_lo_32) node _io_out_s_T_330 = bits(io.in, 9, 7) node _io_out_s_T_331 = cat(UInt<2>(0h1), _io_out_s_T_330) node _io_out_s_T_332 = bits(io.in, 9, 7) node _io_out_s_T_333 = cat(UInt<2>(0h1), _io_out_s_T_332) node _io_out_s_T_334 = bits(io.in, 31, 27) wire io_out_s_14 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_14.bits, _io_out_s_T_329 connect io_out_s_14.rd, _io_out_s_T_331 connect io_out_s_14.rs1, _io_out_s_T_333 connect io_out_s_14.rs2, UInt<5>(0h0) connect io_out_s_14.rs3, _io_out_s_T_334 node _io_out_s_T_335 = bits(io.in, 12, 12) node _io_out_s_T_336 = mux(_io_out_s_T_335, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_337 = bits(io.in, 6, 5) node _io_out_s_T_338 = bits(io.in, 2, 2) node _io_out_s_T_339 = bits(io.in, 11, 10) node _io_out_s_T_340 = bits(io.in, 4, 3) node io_out_s_lo_hi_15 = cat(_io_out_s_T_339, _io_out_s_T_340) node io_out_s_lo_33 = cat(io_out_s_lo_hi_15, UInt<1>(0h0)) node io_out_s_hi_hi_28 = cat(_io_out_s_T_336, _io_out_s_T_337) node io_out_s_hi_39 = cat(io_out_s_hi_hi_28, _io_out_s_T_338) node _io_out_s_T_341 = cat(io_out_s_hi_39, io_out_s_lo_33) node _io_out_s_T_342 = bits(_io_out_s_T_341, 12, 12) node _io_out_s_T_343 = bits(io.in, 12, 12) node _io_out_s_T_344 = mux(_io_out_s_T_343, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_345 = bits(io.in, 6, 5) node _io_out_s_T_346 = bits(io.in, 2, 2) node _io_out_s_T_347 = bits(io.in, 11, 10) node _io_out_s_T_348 = bits(io.in, 4, 3) node io_out_s_lo_hi_16 = cat(_io_out_s_T_347, _io_out_s_T_348) node io_out_s_lo_34 = cat(io_out_s_lo_hi_16, UInt<1>(0h0)) node io_out_s_hi_hi_29 = cat(_io_out_s_T_344, _io_out_s_T_345) node io_out_s_hi_40 = cat(io_out_s_hi_hi_29, _io_out_s_T_346) node _io_out_s_T_349 = cat(io_out_s_hi_40, io_out_s_lo_34) node _io_out_s_T_350 = bits(_io_out_s_T_349, 10, 5) node _io_out_s_T_351 = bits(io.in, 9, 7) node _io_out_s_T_352 = cat(UInt<2>(0h1), _io_out_s_T_351) node _io_out_s_T_353 = bits(io.in, 12, 12) node _io_out_s_T_354 = mux(_io_out_s_T_353, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_355 = bits(io.in, 6, 5) node _io_out_s_T_356 = bits(io.in, 2, 2) node _io_out_s_T_357 = bits(io.in, 11, 10) node _io_out_s_T_358 = bits(io.in, 4, 3) node io_out_s_lo_hi_17 = cat(_io_out_s_T_357, _io_out_s_T_358) node io_out_s_lo_35 = cat(io_out_s_lo_hi_17, UInt<1>(0h0)) node io_out_s_hi_hi_30 = cat(_io_out_s_T_354, _io_out_s_T_355) node io_out_s_hi_41 = cat(io_out_s_hi_hi_30, _io_out_s_T_356) node _io_out_s_T_359 = cat(io_out_s_hi_41, io_out_s_lo_35) node _io_out_s_T_360 = bits(_io_out_s_T_359, 4, 1) node _io_out_s_T_361 = bits(io.in, 12, 12) node _io_out_s_T_362 = mux(_io_out_s_T_361, UInt<5>(0h1f), UInt<5>(0h0)) node _io_out_s_T_363 = bits(io.in, 6, 5) node _io_out_s_T_364 = bits(io.in, 2, 2) node _io_out_s_T_365 = bits(io.in, 11, 10) node _io_out_s_T_366 = bits(io.in, 4, 3) node io_out_s_lo_hi_18 = cat(_io_out_s_T_365, _io_out_s_T_366) node io_out_s_lo_36 = cat(io_out_s_lo_hi_18, UInt<1>(0h0)) node io_out_s_hi_hi_31 = cat(_io_out_s_T_362, _io_out_s_T_363) node io_out_s_hi_42 = cat(io_out_s_hi_hi_31, _io_out_s_T_364) node _io_out_s_T_367 = cat(io_out_s_hi_42, io_out_s_lo_36) node _io_out_s_T_368 = bits(_io_out_s_T_367, 11, 11) node io_out_s_lo_lo_5 = cat(_io_out_s_T_368, UInt<7>(0h63)) node io_out_s_lo_hi_19 = cat(UInt<3>(0h1), _io_out_s_T_360) node io_out_s_lo_37 = cat(io_out_s_lo_hi_19, io_out_s_lo_lo_5) node io_out_s_hi_lo_5 = cat(UInt<5>(0h0), _io_out_s_T_352) node io_out_s_hi_hi_32 = cat(_io_out_s_T_342, _io_out_s_T_350) node io_out_s_hi_43 = cat(io_out_s_hi_hi_32, io_out_s_hi_lo_5) node _io_out_s_T_369 = cat(io_out_s_hi_43, io_out_s_lo_37) node _io_out_s_T_370 = bits(io.in, 9, 7) node _io_out_s_T_371 = cat(UInt<2>(0h1), _io_out_s_T_370) node _io_out_s_T_372 = bits(io.in, 31, 27) wire io_out_s_15 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_15.bits, _io_out_s_T_369 connect io_out_s_15.rd, UInt<5>(0h0) connect io_out_s_15.rs1, _io_out_s_T_371 connect io_out_s_15.rs2, UInt<5>(0h0) connect io_out_s_15.rs3, _io_out_s_T_372 node _io_out_s_load_opc_T = bits(io.in, 11, 7) node _io_out_s_load_opc_T_1 = orr(_io_out_s_load_opc_T) node io_out_s_load_opc = mux(_io_out_s_load_opc_T_1, UInt<7>(0h3), UInt<7>(0h1f)) node _io_out_s_T_373 = bits(io.in, 12, 12) node _io_out_s_T_374 = bits(io.in, 6, 2) node _io_out_s_T_375 = cat(_io_out_s_T_373, _io_out_s_T_374) node _io_out_s_T_376 = bits(io.in, 11, 7) node _io_out_s_T_377 = bits(io.in, 11, 7) node io_out_s_lo_38 = cat(_io_out_s_T_377, UInt<7>(0h13)) node io_out_s_hi_hi_33 = cat(_io_out_s_T_375, _io_out_s_T_376) node io_out_s_hi_44 = cat(io_out_s_hi_hi_33, UInt<3>(0h1)) node _io_out_s_T_378 = cat(io_out_s_hi_44, io_out_s_lo_38) node _io_out_s_T_379 = bits(io.in, 11, 7) node _io_out_s_T_380 = bits(io.in, 11, 7) node _io_out_s_T_381 = bits(io.in, 6, 2) node _io_out_s_T_382 = bits(io.in, 31, 27) wire io_out_s_16 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_16.bits, _io_out_s_T_378 connect io_out_s_16.rd, _io_out_s_T_379 connect io_out_s_16.rs1, _io_out_s_T_380 connect io_out_s_16.rs2, _io_out_s_T_381 connect io_out_s_16.rs3, _io_out_s_T_382 node _io_out_s_T_383 = bits(io.in, 4, 2) node _io_out_s_T_384 = bits(io.in, 12, 12) node _io_out_s_T_385 = bits(io.in, 6, 5) node io_out_s_lo_39 = cat(_io_out_s_T_385, UInt<3>(0h0)) node io_out_s_hi_45 = cat(_io_out_s_T_383, _io_out_s_T_384) node _io_out_s_T_386 = cat(io_out_s_hi_45, io_out_s_lo_39) node _io_out_s_T_387 = bits(io.in, 11, 7) node io_out_s_lo_40 = cat(_io_out_s_T_387, UInt<7>(0h7)) node io_out_s_hi_hi_34 = cat(_io_out_s_T_386, UInt<5>(0h2)) node io_out_s_hi_46 = cat(io_out_s_hi_hi_34, UInt<3>(0h3)) node _io_out_s_T_388 = cat(io_out_s_hi_46, io_out_s_lo_40) node _io_out_s_T_389 = bits(io.in, 11, 7) node _io_out_s_T_390 = bits(io.in, 6, 2) node _io_out_s_T_391 = bits(io.in, 31, 27) wire io_out_s_17 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_17.bits, _io_out_s_T_388 connect io_out_s_17.rd, _io_out_s_T_389 connect io_out_s_17.rs1, UInt<5>(0h2) connect io_out_s_17.rs2, _io_out_s_T_390 connect io_out_s_17.rs3, _io_out_s_T_391 node _io_out_s_T_392 = bits(io.in, 3, 2) node _io_out_s_T_393 = bits(io.in, 12, 12) node _io_out_s_T_394 = bits(io.in, 6, 4) node io_out_s_lo_41 = cat(_io_out_s_T_394, UInt<2>(0h0)) node io_out_s_hi_47 = cat(_io_out_s_T_392, _io_out_s_T_393) node _io_out_s_T_395 = cat(io_out_s_hi_47, io_out_s_lo_41) node _io_out_s_T_396 = bits(io.in, 11, 7) node io_out_s_lo_42 = cat(_io_out_s_T_396, io_out_s_load_opc) node io_out_s_hi_hi_35 = cat(_io_out_s_T_395, UInt<5>(0h2)) node io_out_s_hi_48 = cat(io_out_s_hi_hi_35, UInt<3>(0h2)) node _io_out_s_T_397 = cat(io_out_s_hi_48, io_out_s_lo_42) node _io_out_s_T_398 = bits(io.in, 11, 7) node _io_out_s_T_399 = bits(io.in, 6, 2) node _io_out_s_T_400 = bits(io.in, 31, 27) wire io_out_s_18 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_18.bits, _io_out_s_T_397 connect io_out_s_18.rd, _io_out_s_T_398 connect io_out_s_18.rs1, UInt<5>(0h2) connect io_out_s_18.rs2, _io_out_s_T_399 connect io_out_s_18.rs3, _io_out_s_T_400 node _io_out_s_T_401 = bits(io.in, 4, 2) node _io_out_s_T_402 = bits(io.in, 12, 12) node _io_out_s_T_403 = bits(io.in, 6, 5) node io_out_s_lo_43 = cat(_io_out_s_T_403, UInt<3>(0h0)) node io_out_s_hi_49 = cat(_io_out_s_T_401, _io_out_s_T_402) node _io_out_s_T_404 = cat(io_out_s_hi_49, io_out_s_lo_43) node _io_out_s_T_405 = bits(io.in, 11, 7) node io_out_s_lo_44 = cat(_io_out_s_T_405, io_out_s_load_opc) node io_out_s_hi_hi_36 = cat(_io_out_s_T_404, UInt<5>(0h2)) node io_out_s_hi_50 = cat(io_out_s_hi_hi_36, UInt<3>(0h3)) node _io_out_s_T_406 = cat(io_out_s_hi_50, io_out_s_lo_44) node _io_out_s_T_407 = bits(io.in, 11, 7) node _io_out_s_T_408 = bits(io.in, 6, 2) node _io_out_s_T_409 = bits(io.in, 31, 27) wire io_out_s_19 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_19.bits, _io_out_s_T_406 connect io_out_s_19.rd, _io_out_s_T_407 connect io_out_s_19.rs1, UInt<5>(0h2) connect io_out_s_19.rs2, _io_out_s_T_408 connect io_out_s_19.rs3, _io_out_s_T_409 node _io_out_s_mv_T = bits(io.in, 6, 2) node _io_out_s_mv_T_1 = bits(io.in, 11, 7) node io_out_s_mv_lo = cat(_io_out_s_mv_T_1, UInt<7>(0h33)) node io_out_s_mv_hi_hi = cat(_io_out_s_mv_T, UInt<5>(0h0)) node io_out_s_mv_hi = cat(io_out_s_mv_hi_hi, UInt<3>(0h0)) node _io_out_s_mv_T_2 = cat(io_out_s_mv_hi, io_out_s_mv_lo) node _io_out_s_mv_T_3 = bits(io.in, 11, 7) node _io_out_s_mv_T_4 = bits(io.in, 6, 2) node _io_out_s_mv_T_5 = bits(io.in, 31, 27) wire io_out_s_mv : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_mv.bits, _io_out_s_mv_T_2 connect io_out_s_mv.rd, _io_out_s_mv_T_3 connect io_out_s_mv.rs1, UInt<5>(0h0) connect io_out_s_mv.rs2, _io_out_s_mv_T_4 connect io_out_s_mv.rs3, _io_out_s_mv_T_5 node _io_out_s_add_T = bits(io.in, 6, 2) node _io_out_s_add_T_1 = bits(io.in, 11, 7) node _io_out_s_add_T_2 = bits(io.in, 11, 7) node io_out_s_add_lo = cat(_io_out_s_add_T_2, UInt<7>(0h33)) node io_out_s_add_hi_hi = cat(_io_out_s_add_T, _io_out_s_add_T_1) node io_out_s_add_hi = cat(io_out_s_add_hi_hi, UInt<3>(0h0)) node _io_out_s_add_T_3 = cat(io_out_s_add_hi, io_out_s_add_lo) node _io_out_s_add_T_4 = bits(io.in, 11, 7) node _io_out_s_add_T_5 = bits(io.in, 11, 7) node _io_out_s_add_T_6 = bits(io.in, 6, 2) node _io_out_s_add_T_7 = bits(io.in, 31, 27) wire io_out_s_add : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_add.bits, _io_out_s_add_T_3 connect io_out_s_add.rd, _io_out_s_add_T_4 connect io_out_s_add.rs1, _io_out_s_add_T_5 connect io_out_s_add.rs2, _io_out_s_add_T_6 connect io_out_s_add.rs3, _io_out_s_add_T_7 node _io_out_s_jr_T = bits(io.in, 6, 2) node _io_out_s_jr_T_1 = bits(io.in, 11, 7) node io_out_s_jr_lo = cat(UInt<5>(0h0), UInt<7>(0h67)) node io_out_s_jr_hi_hi = cat(_io_out_s_jr_T, _io_out_s_jr_T_1) node io_out_s_jr_hi = cat(io_out_s_jr_hi_hi, UInt<3>(0h0)) node io_out_s_jr = cat(io_out_s_jr_hi, io_out_s_jr_lo) node _io_out_s_reserved_T = shr(io_out_s_jr, 7) node io_out_s_reserved = cat(_io_out_s_reserved_T, UInt<7>(0h1f)) node _io_out_s_jr_reserved_T = bits(io.in, 11, 7) node _io_out_s_jr_reserved_T_1 = orr(_io_out_s_jr_reserved_T) node _io_out_s_jr_reserved_T_2 = mux(_io_out_s_jr_reserved_T_1, io_out_s_jr, io_out_s_reserved) node _io_out_s_jr_reserved_T_3 = bits(io.in, 11, 7) node _io_out_s_jr_reserved_T_4 = bits(io.in, 6, 2) node _io_out_s_jr_reserved_T_5 = bits(io.in, 31, 27) wire io_out_s_jr_reserved : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_jr_reserved.bits, _io_out_s_jr_reserved_T_2 connect io_out_s_jr_reserved.rd, UInt<5>(0h0) connect io_out_s_jr_reserved.rs1, _io_out_s_jr_reserved_T_3 connect io_out_s_jr_reserved.rs2, _io_out_s_jr_reserved_T_4 connect io_out_s_jr_reserved.rs3, _io_out_s_jr_reserved_T_5 node _io_out_s_jr_mv_T = bits(io.in, 6, 2) node _io_out_s_jr_mv_T_1 = orr(_io_out_s_jr_mv_T) node io_out_s_jr_mv = mux(_io_out_s_jr_mv_T_1, io_out_s_mv, io_out_s_jr_reserved) node _io_out_s_jalr_T = bits(io.in, 6, 2) node _io_out_s_jalr_T_1 = bits(io.in, 11, 7) node io_out_s_jalr_lo = cat(UInt<5>(0h1), UInt<7>(0h67)) node io_out_s_jalr_hi_hi = cat(_io_out_s_jalr_T, _io_out_s_jalr_T_1) node io_out_s_jalr_hi = cat(io_out_s_jalr_hi_hi, UInt<3>(0h0)) node io_out_s_jalr = cat(io_out_s_jalr_hi, io_out_s_jalr_lo) node _io_out_s_ebreak_T = shr(io_out_s_jr, 7) node _io_out_s_ebreak_T_1 = cat(_io_out_s_ebreak_T, UInt<7>(0h73)) node io_out_s_ebreak = or(_io_out_s_ebreak_T_1, UInt<21>(0h100000)) node _io_out_s_jalr_ebreak_T = bits(io.in, 11, 7) node _io_out_s_jalr_ebreak_T_1 = orr(_io_out_s_jalr_ebreak_T) node _io_out_s_jalr_ebreak_T_2 = mux(_io_out_s_jalr_ebreak_T_1, io_out_s_jalr, io_out_s_ebreak) node _io_out_s_jalr_ebreak_T_3 = bits(io.in, 11, 7) node _io_out_s_jalr_ebreak_T_4 = bits(io.in, 6, 2) node _io_out_s_jalr_ebreak_T_5 = bits(io.in, 31, 27) wire io_out_s_jalr_ebreak : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_jalr_ebreak.bits, _io_out_s_jalr_ebreak_T_2 connect io_out_s_jalr_ebreak.rd, UInt<5>(0h1) connect io_out_s_jalr_ebreak.rs1, _io_out_s_jalr_ebreak_T_3 connect io_out_s_jalr_ebreak.rs2, _io_out_s_jalr_ebreak_T_4 connect io_out_s_jalr_ebreak.rs3, _io_out_s_jalr_ebreak_T_5 node _io_out_s_jalr_add_T = bits(io.in, 6, 2) node _io_out_s_jalr_add_T_1 = orr(_io_out_s_jalr_add_T) node io_out_s_jalr_add = mux(_io_out_s_jalr_add_T_1, io_out_s_add, io_out_s_jalr_ebreak) node _io_out_s_T_410 = bits(io.in, 12, 12) node io_out_s_20 = mux(_io_out_s_T_410, io_out_s_jalr_add, io_out_s_jr_mv) node _io_out_s_T_411 = bits(io.in, 9, 7) node _io_out_s_T_412 = bits(io.in, 12, 10) node io_out_s_hi_51 = cat(_io_out_s_T_411, _io_out_s_T_412) node _io_out_s_T_413 = cat(io_out_s_hi_51, UInt<3>(0h0)) node _io_out_s_T_414 = shr(_io_out_s_T_413, 5) node _io_out_s_T_415 = bits(io.in, 6, 2) node _io_out_s_T_416 = bits(io.in, 9, 7) node _io_out_s_T_417 = bits(io.in, 12, 10) node io_out_s_hi_52 = cat(_io_out_s_T_416, _io_out_s_T_417) node _io_out_s_T_418 = cat(io_out_s_hi_52, UInt<3>(0h0)) node _io_out_s_T_419 = bits(_io_out_s_T_418, 4, 0) node io_out_s_lo_hi_20 = cat(UInt<3>(0h3), _io_out_s_T_419) node io_out_s_lo_45 = cat(io_out_s_lo_hi_20, UInt<7>(0h27)) node io_out_s_hi_hi_37 = cat(_io_out_s_T_414, _io_out_s_T_415) node io_out_s_hi_53 = cat(io_out_s_hi_hi_37, UInt<5>(0h2)) node _io_out_s_T_420 = cat(io_out_s_hi_53, io_out_s_lo_45) node _io_out_s_T_421 = bits(io.in, 11, 7) node _io_out_s_T_422 = bits(io.in, 6, 2) node _io_out_s_T_423 = bits(io.in, 31, 27) wire io_out_s_21 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_21.bits, _io_out_s_T_420 connect io_out_s_21.rd, _io_out_s_T_421 connect io_out_s_21.rs1, UInt<5>(0h2) connect io_out_s_21.rs2, _io_out_s_T_422 connect io_out_s_21.rs3, _io_out_s_T_423 node _io_out_s_T_424 = bits(io.in, 8, 7) node _io_out_s_T_425 = bits(io.in, 12, 9) node io_out_s_hi_54 = cat(_io_out_s_T_424, _io_out_s_T_425) node _io_out_s_T_426 = cat(io_out_s_hi_54, UInt<2>(0h0)) node _io_out_s_T_427 = shr(_io_out_s_T_426, 5) node _io_out_s_T_428 = bits(io.in, 6, 2) node _io_out_s_T_429 = bits(io.in, 8, 7) node _io_out_s_T_430 = bits(io.in, 12, 9) node io_out_s_hi_55 = cat(_io_out_s_T_429, _io_out_s_T_430) node _io_out_s_T_431 = cat(io_out_s_hi_55, UInt<2>(0h0)) node _io_out_s_T_432 = bits(_io_out_s_T_431, 4, 0) node io_out_s_lo_hi_21 = cat(UInt<3>(0h2), _io_out_s_T_432) node io_out_s_lo_46 = cat(io_out_s_lo_hi_21, UInt<7>(0h23)) node io_out_s_hi_hi_38 = cat(_io_out_s_T_427, _io_out_s_T_428) node io_out_s_hi_56 = cat(io_out_s_hi_hi_38, UInt<5>(0h2)) node _io_out_s_T_433 = cat(io_out_s_hi_56, io_out_s_lo_46) node _io_out_s_T_434 = bits(io.in, 11, 7) node _io_out_s_T_435 = bits(io.in, 6, 2) node _io_out_s_T_436 = bits(io.in, 31, 27) wire io_out_s_22 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_22.bits, _io_out_s_T_433 connect io_out_s_22.rd, _io_out_s_T_434 connect io_out_s_22.rs1, UInt<5>(0h2) connect io_out_s_22.rs2, _io_out_s_T_435 connect io_out_s_22.rs3, _io_out_s_T_436 node _io_out_s_T_437 = bits(io.in, 9, 7) node _io_out_s_T_438 = bits(io.in, 12, 10) node io_out_s_hi_57 = cat(_io_out_s_T_437, _io_out_s_T_438) node _io_out_s_T_439 = cat(io_out_s_hi_57, UInt<3>(0h0)) node _io_out_s_T_440 = shr(_io_out_s_T_439, 5) node _io_out_s_T_441 = bits(io.in, 6, 2) node _io_out_s_T_442 = bits(io.in, 9, 7) node _io_out_s_T_443 = bits(io.in, 12, 10) node io_out_s_hi_58 = cat(_io_out_s_T_442, _io_out_s_T_443) node _io_out_s_T_444 = cat(io_out_s_hi_58, UInt<3>(0h0)) node _io_out_s_T_445 = bits(_io_out_s_T_444, 4, 0) node io_out_s_lo_hi_22 = cat(UInt<3>(0h3), _io_out_s_T_445) node io_out_s_lo_47 = cat(io_out_s_lo_hi_22, UInt<7>(0h23)) node io_out_s_hi_hi_39 = cat(_io_out_s_T_440, _io_out_s_T_441) node io_out_s_hi_59 = cat(io_out_s_hi_hi_39, UInt<5>(0h2)) node _io_out_s_T_446 = cat(io_out_s_hi_59, io_out_s_lo_47) node _io_out_s_T_447 = bits(io.in, 11, 7) node _io_out_s_T_448 = bits(io.in, 6, 2) node _io_out_s_T_449 = bits(io.in, 31, 27) wire io_out_s_23 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_23.bits, _io_out_s_T_446 connect io_out_s_23.rd, _io_out_s_T_447 connect io_out_s_23.rs1, UInt<5>(0h2) connect io_out_s_23.rs2, _io_out_s_T_448 connect io_out_s_23.rs3, _io_out_s_T_449 node _io_out_s_T_450 = bits(io.in, 11, 7) node _io_out_s_T_451 = bits(io.in, 19, 15) node _io_out_s_T_452 = bits(io.in, 24, 20) node _io_out_s_T_453 = bits(io.in, 31, 27) wire io_out_s_24 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_24.bits, io.in connect io_out_s_24.rd, _io_out_s_T_450 connect io_out_s_24.rs1, _io_out_s_T_451 connect io_out_s_24.rs2, _io_out_s_T_452 connect io_out_s_24.rs3, _io_out_s_T_453 node _io_out_s_T_454 = bits(io.in, 11, 7) node _io_out_s_T_455 = bits(io.in, 19, 15) node _io_out_s_T_456 = bits(io.in, 24, 20) node _io_out_s_T_457 = bits(io.in, 31, 27) wire io_out_s_25 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_25.bits, io.in connect io_out_s_25.rd, _io_out_s_T_454 connect io_out_s_25.rs1, _io_out_s_T_455 connect io_out_s_25.rs2, _io_out_s_T_456 connect io_out_s_25.rs3, _io_out_s_T_457 node _io_out_s_T_458 = bits(io.in, 11, 7) node _io_out_s_T_459 = bits(io.in, 19, 15) node _io_out_s_T_460 = bits(io.in, 24, 20) node _io_out_s_T_461 = bits(io.in, 31, 27) wire io_out_s_26 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_26.bits, io.in connect io_out_s_26.rd, _io_out_s_T_458 connect io_out_s_26.rs1, _io_out_s_T_459 connect io_out_s_26.rs2, _io_out_s_T_460 connect io_out_s_26.rs3, _io_out_s_T_461 node _io_out_s_T_462 = bits(io.in, 11, 7) node _io_out_s_T_463 = bits(io.in, 19, 15) node _io_out_s_T_464 = bits(io.in, 24, 20) node _io_out_s_T_465 = bits(io.in, 31, 27) wire io_out_s_27 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_27.bits, io.in connect io_out_s_27.rd, _io_out_s_T_462 connect io_out_s_27.rs1, _io_out_s_T_463 connect io_out_s_27.rs2, _io_out_s_T_464 connect io_out_s_27.rs3, _io_out_s_T_465 node _io_out_s_T_466 = bits(io.in, 11, 7) node _io_out_s_T_467 = bits(io.in, 19, 15) node _io_out_s_T_468 = bits(io.in, 24, 20) node _io_out_s_T_469 = bits(io.in, 31, 27) wire io_out_s_28 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_28.bits, io.in connect io_out_s_28.rd, _io_out_s_T_466 connect io_out_s_28.rs1, _io_out_s_T_467 connect io_out_s_28.rs2, _io_out_s_T_468 connect io_out_s_28.rs3, _io_out_s_T_469 node _io_out_s_T_470 = bits(io.in, 11, 7) node _io_out_s_T_471 = bits(io.in, 19, 15) node _io_out_s_T_472 = bits(io.in, 24, 20) node _io_out_s_T_473 = bits(io.in, 31, 27) wire io_out_s_29 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_29.bits, io.in connect io_out_s_29.rd, _io_out_s_T_470 connect io_out_s_29.rs1, _io_out_s_T_471 connect io_out_s_29.rs2, _io_out_s_T_472 connect io_out_s_29.rs3, _io_out_s_T_473 node _io_out_s_T_474 = bits(io.in, 11, 7) node _io_out_s_T_475 = bits(io.in, 19, 15) node _io_out_s_T_476 = bits(io.in, 24, 20) node _io_out_s_T_477 = bits(io.in, 31, 27) wire io_out_s_30 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_30.bits, io.in connect io_out_s_30.rd, _io_out_s_T_474 connect io_out_s_30.rs1, _io_out_s_T_475 connect io_out_s_30.rs2, _io_out_s_T_476 connect io_out_s_30.rs3, _io_out_s_T_477 node _io_out_s_T_478 = bits(io.in, 11, 7) node _io_out_s_T_479 = bits(io.in, 19, 15) node _io_out_s_T_480 = bits(io.in, 24, 20) node _io_out_s_T_481 = bits(io.in, 31, 27) wire io_out_s_31 : { bits : UInt<32>, rd : UInt<5>, rs1 : UInt<5>, rs2 : UInt<5>, rs3 : UInt<5>} connect io_out_s_31.bits, io.in connect io_out_s_31.rd, _io_out_s_T_478 connect io_out_s_31.rs1, _io_out_s_T_479 connect io_out_s_31.rs2, _io_out_s_T_480 connect io_out_s_31.rs3, _io_out_s_T_481 node _io_out_T = bits(io.in, 1, 0) node _io_out_T_1 = bits(io.in, 15, 13) node _io_out_T_2 = cat(_io_out_T, _io_out_T_1) node _io_out_T_3 = eq(_io_out_T_2, UInt<1>(0h1)) node _io_out_T_4 = mux(_io_out_T_3, io_out_s_1, io_out_s_0) node _io_out_T_5 = eq(_io_out_T_2, UInt<2>(0h2)) node _io_out_T_6 = mux(_io_out_T_5, io_out_s_2, _io_out_T_4) node _io_out_T_7 = eq(_io_out_T_2, UInt<2>(0h3)) node _io_out_T_8 = mux(_io_out_T_7, io_out_s_3, _io_out_T_6) node _io_out_T_9 = eq(_io_out_T_2, UInt<3>(0h4)) node _io_out_T_10 = mux(_io_out_T_9, io_out_s_4, _io_out_T_8) node _io_out_T_11 = eq(_io_out_T_2, UInt<3>(0h5)) node _io_out_T_12 = mux(_io_out_T_11, io_out_s_5, _io_out_T_10) node _io_out_T_13 = eq(_io_out_T_2, UInt<3>(0h6)) node _io_out_T_14 = mux(_io_out_T_13, io_out_s_6, _io_out_T_12) node _io_out_T_15 = eq(_io_out_T_2, UInt<3>(0h7)) node _io_out_T_16 = mux(_io_out_T_15, io_out_s_7, _io_out_T_14) node _io_out_T_17 = eq(_io_out_T_2, UInt<4>(0h8)) node _io_out_T_18 = mux(_io_out_T_17, io_out_s_8, _io_out_T_16) node _io_out_T_19 = eq(_io_out_T_2, UInt<4>(0h9)) node _io_out_T_20 = mux(_io_out_T_19, io_out_s_9, _io_out_T_18) node _io_out_T_21 = eq(_io_out_T_2, UInt<4>(0ha)) node _io_out_T_22 = mux(_io_out_T_21, io_out_s_10, _io_out_T_20) node _io_out_T_23 = eq(_io_out_T_2, UInt<4>(0hb)) node _io_out_T_24 = mux(_io_out_T_23, io_out_s_11, _io_out_T_22) node _io_out_T_25 = eq(_io_out_T_2, UInt<4>(0hc)) node _io_out_T_26 = mux(_io_out_T_25, io_out_s_12, _io_out_T_24) node _io_out_T_27 = eq(_io_out_T_2, UInt<4>(0hd)) node _io_out_T_28 = mux(_io_out_T_27, io_out_s_13, _io_out_T_26) node _io_out_T_29 = eq(_io_out_T_2, UInt<4>(0he)) node _io_out_T_30 = mux(_io_out_T_29, io_out_s_14, _io_out_T_28) node _io_out_T_31 = eq(_io_out_T_2, UInt<4>(0hf)) node _io_out_T_32 = mux(_io_out_T_31, io_out_s_15, _io_out_T_30) node _io_out_T_33 = eq(_io_out_T_2, UInt<5>(0h10)) node _io_out_T_34 = mux(_io_out_T_33, io_out_s_16, _io_out_T_32) node _io_out_T_35 = eq(_io_out_T_2, UInt<5>(0h11)) node _io_out_T_36 = mux(_io_out_T_35, io_out_s_17, _io_out_T_34) node _io_out_T_37 = eq(_io_out_T_2, UInt<5>(0h12)) node _io_out_T_38 = mux(_io_out_T_37, io_out_s_18, _io_out_T_36) node _io_out_T_39 = eq(_io_out_T_2, UInt<5>(0h13)) node _io_out_T_40 = mux(_io_out_T_39, io_out_s_19, _io_out_T_38) node _io_out_T_41 = eq(_io_out_T_2, UInt<5>(0h14)) node _io_out_T_42 = mux(_io_out_T_41, io_out_s_20, _io_out_T_40) node _io_out_T_43 = eq(_io_out_T_2, UInt<5>(0h15)) node _io_out_T_44 = mux(_io_out_T_43, io_out_s_21, _io_out_T_42) node _io_out_T_45 = eq(_io_out_T_2, UInt<5>(0h16)) node _io_out_T_46 = mux(_io_out_T_45, io_out_s_22, _io_out_T_44) node _io_out_T_47 = eq(_io_out_T_2, UInt<5>(0h17)) node _io_out_T_48 = mux(_io_out_T_47, io_out_s_23, _io_out_T_46) node _io_out_T_49 = eq(_io_out_T_2, UInt<5>(0h18)) node _io_out_T_50 = mux(_io_out_T_49, io_out_s_24, _io_out_T_48) node _io_out_T_51 = eq(_io_out_T_2, UInt<5>(0h19)) node _io_out_T_52 = mux(_io_out_T_51, io_out_s_25, _io_out_T_50) node _io_out_T_53 = eq(_io_out_T_2, UInt<5>(0h1a)) node _io_out_T_54 = mux(_io_out_T_53, io_out_s_26, _io_out_T_52) node _io_out_T_55 = eq(_io_out_T_2, UInt<5>(0h1b)) node _io_out_T_56 = mux(_io_out_T_55, io_out_s_27, _io_out_T_54) node _io_out_T_57 = eq(_io_out_T_2, UInt<5>(0h1c)) node _io_out_T_58 = mux(_io_out_T_57, io_out_s_28, _io_out_T_56) node _io_out_T_59 = eq(_io_out_T_2, UInt<5>(0h1d)) node _io_out_T_60 = mux(_io_out_T_59, io_out_s_29, _io_out_T_58) node _io_out_T_61 = eq(_io_out_T_2, UInt<5>(0h1e)) node _io_out_T_62 = mux(_io_out_T_61, io_out_s_30, _io_out_T_60) node _io_out_T_63 = eq(_io_out_T_2, UInt<5>(0h1f)) node _io_out_T_64 = mux(_io_out_T_63, io_out_s_31, _io_out_T_62) connect io.out, _io_out_T_64 node _io_ill_s_T = bits(io.in, 12, 2) node _io_ill_s_T_1 = orr(_io_ill_s_T) node io_ill_s_0 = eq(_io_ill_s_T_1, UInt<1>(0h0)) node _io_ill_s_T_2 = bits(io.in, 11, 7) node io_ill_s_9 = eq(_io_ill_s_T_2, UInt<1>(0h0)) node _io_ill_s_T_3 = bits(io.in, 12, 12) node _io_ill_s_T_4 = bits(io.in, 6, 2) node _io_ill_s_T_5 = orr(_io_ill_s_T_4) node _io_ill_s_T_6 = or(_io_ill_s_T_3, _io_ill_s_T_5) node io_ill_s_11 = eq(_io_ill_s_T_6, UInt<1>(0h0)) node _io_ill_s_T_7 = bits(io.in, 12, 10) node _io_ill_s_T_8 = andr(_io_ill_s_T_7) node _io_ill_s_T_9 = bits(io.in, 6, 6) node _io_ill_s_T_10 = eq(_io_ill_s_T_9, UInt<1>(0h1)) node io_ill_s_12 = and(_io_ill_s_T_8, _io_ill_s_T_10) node _io_ill_s_T_11 = bits(io.in, 11, 7) node io_ill_s_18 = eq(_io_ill_s_T_11, UInt<1>(0h0)) node _io_ill_s_T_12 = bits(io.in, 11, 7) node io_ill_s_19 = eq(_io_ill_s_T_12, UInt<1>(0h0)) node _io_ill_s_T_13 = bits(io.in, 12, 2) node _io_ill_s_T_14 = orr(_io_ill_s_T_13) node io_ill_s_20 = eq(_io_ill_s_T_14, UInt<1>(0h0)) node _io_ill_T = bits(io.in, 1, 0) node _io_ill_T_1 = bits(io.in, 15, 13) node _io_ill_T_2 = cat(_io_ill_T, _io_ill_T_1) node _io_ill_T_3 = eq(_io_ill_T_2, UInt<1>(0h1)) node _io_ill_T_4 = mux(_io_ill_T_3, UInt<1>(0h0), io_ill_s_0) node _io_ill_T_5 = eq(_io_ill_T_2, UInt<2>(0h2)) node _io_ill_T_6 = mux(_io_ill_T_5, UInt<1>(0h0), _io_ill_T_4) node _io_ill_T_7 = eq(_io_ill_T_2, UInt<2>(0h3)) node _io_ill_T_8 = mux(_io_ill_T_7, UInt<1>(0h0), _io_ill_T_6) node _io_ill_T_9 = eq(_io_ill_T_2, UInt<3>(0h4)) node _io_ill_T_10 = mux(_io_ill_T_9, UInt<1>(0h1), _io_ill_T_8) node _io_ill_T_11 = eq(_io_ill_T_2, UInt<3>(0h5)) node _io_ill_T_12 = mux(_io_ill_T_11, UInt<1>(0h0), _io_ill_T_10) node _io_ill_T_13 = eq(_io_ill_T_2, UInt<3>(0h6)) node _io_ill_T_14 = mux(_io_ill_T_13, UInt<1>(0h0), _io_ill_T_12) node _io_ill_T_15 = eq(_io_ill_T_2, UInt<3>(0h7)) node _io_ill_T_16 = mux(_io_ill_T_15, UInt<1>(0h0), _io_ill_T_14) node _io_ill_T_17 = eq(_io_ill_T_2, UInt<4>(0h8)) node _io_ill_T_18 = mux(_io_ill_T_17, UInt<1>(0h0), _io_ill_T_16) node _io_ill_T_19 = eq(_io_ill_T_2, UInt<4>(0h9)) node _io_ill_T_20 = mux(_io_ill_T_19, io_ill_s_9, _io_ill_T_18) node _io_ill_T_21 = eq(_io_ill_T_2, UInt<4>(0ha)) node _io_ill_T_22 = mux(_io_ill_T_21, UInt<1>(0h0), _io_ill_T_20) node _io_ill_T_23 = eq(_io_ill_T_2, UInt<4>(0hb)) node _io_ill_T_24 = mux(_io_ill_T_23, io_ill_s_11, _io_ill_T_22) node _io_ill_T_25 = eq(_io_ill_T_2, UInt<4>(0hc)) node _io_ill_T_26 = mux(_io_ill_T_25, io_ill_s_12, _io_ill_T_24) node _io_ill_T_27 = eq(_io_ill_T_2, UInt<4>(0hd)) node _io_ill_T_28 = mux(_io_ill_T_27, UInt<1>(0h0), _io_ill_T_26) node _io_ill_T_29 = eq(_io_ill_T_2, UInt<4>(0he)) node _io_ill_T_30 = mux(_io_ill_T_29, UInt<1>(0h0), _io_ill_T_28) node _io_ill_T_31 = eq(_io_ill_T_2, UInt<4>(0hf)) node _io_ill_T_32 = mux(_io_ill_T_31, UInt<1>(0h0), _io_ill_T_30) node _io_ill_T_33 = eq(_io_ill_T_2, UInt<5>(0h10)) node _io_ill_T_34 = mux(_io_ill_T_33, UInt<1>(0h0), _io_ill_T_32) node _io_ill_T_35 = eq(_io_ill_T_2, UInt<5>(0h11)) node _io_ill_T_36 = mux(_io_ill_T_35, UInt<1>(0h0), _io_ill_T_34) node _io_ill_T_37 = eq(_io_ill_T_2, UInt<5>(0h12)) node _io_ill_T_38 = mux(_io_ill_T_37, io_ill_s_18, _io_ill_T_36) node _io_ill_T_39 = eq(_io_ill_T_2, UInt<5>(0h13)) node _io_ill_T_40 = mux(_io_ill_T_39, io_ill_s_19, _io_ill_T_38) node _io_ill_T_41 = eq(_io_ill_T_2, UInt<5>(0h14)) node _io_ill_T_42 = mux(_io_ill_T_41, io_ill_s_20, _io_ill_T_40) node _io_ill_T_43 = eq(_io_ill_T_2, UInt<5>(0h15)) node _io_ill_T_44 = mux(_io_ill_T_43, UInt<1>(0h0), _io_ill_T_42) node _io_ill_T_45 = eq(_io_ill_T_2, UInt<5>(0h16)) node _io_ill_T_46 = mux(_io_ill_T_45, UInt<1>(0h0), _io_ill_T_44) node _io_ill_T_47 = eq(_io_ill_T_2, UInt<5>(0h17)) node _io_ill_T_48 = mux(_io_ill_T_47, UInt<1>(0h0), _io_ill_T_46) node _io_ill_T_49 = eq(_io_ill_T_2, UInt<5>(0h18)) node _io_ill_T_50 = mux(_io_ill_T_49, UInt<1>(0h0), _io_ill_T_48) node _io_ill_T_51 = eq(_io_ill_T_2, UInt<5>(0h19)) node _io_ill_T_52 = mux(_io_ill_T_51, UInt<1>(0h0), _io_ill_T_50) node _io_ill_T_53 = eq(_io_ill_T_2, UInt<5>(0h1a)) node _io_ill_T_54 = mux(_io_ill_T_53, UInt<1>(0h0), _io_ill_T_52) node _io_ill_T_55 = eq(_io_ill_T_2, UInt<5>(0h1b)) node _io_ill_T_56 = mux(_io_ill_T_55, UInt<1>(0h0), _io_ill_T_54) node _io_ill_T_57 = eq(_io_ill_T_2, UInt<5>(0h1c)) node _io_ill_T_58 = mux(_io_ill_T_57, UInt<1>(0h0), _io_ill_T_56) node _io_ill_T_59 = eq(_io_ill_T_2, UInt<5>(0h1d)) node _io_ill_T_60 = mux(_io_ill_T_59, UInt<1>(0h0), _io_ill_T_58) node _io_ill_T_61 = eq(_io_ill_T_2, UInt<5>(0h1e)) node _io_ill_T_62 = mux(_io_ill_T_61, UInt<1>(0h0), _io_ill_T_60) node _io_ill_T_63 = eq(_io_ill_T_2, UInt<5>(0h1f)) node _io_ill_T_64 = mux(_io_ill_T_63, UInt<1>(0h0), _io_ill_T_62) connect io.ill, _io_ill_T_64
module RVCExpander_5( // @[RVC.scala:190:7] input clock, // @[RVC.scala:190:7] input reset, // @[RVC.scala:190:7] input [31:0] io_in, // @[RVC.scala:191:14] output [31:0] io_out_bits, // @[RVC.scala:191:14] output io_rvc // @[RVC.scala:191:14] ); wire [31:0] io_in_0 = io_in; // @[RVC.scala:190:7] wire [11:0] io_out_s_jr_lo = 12'h67; // @[RVC.scala:135:19] wire [4:0] io_out_s_10_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_13_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_14_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rd = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_15_rs2 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_mv_rs1 = 5'h0; // @[RVC.scala:21:19] wire [4:0] io_out_s_jr_reserved_rd = 5'h0; // @[RVC.scala:21:19] wire [11:0] io_out_s_jalr_lo = 12'hE7; // @[RVC.scala:139:21] wire [4:0] io_out_s_jalr_ebreak_rd = 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_17_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_18_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_19_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_21_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_22_rs1 = 5'h2; // @[package.scala:39:86] wire [4:0] io_out_s_23_rs1 = 5'h2; // @[package.scala:39:86] wire [31:0] io_out_s_24_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_25_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_26_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_27_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_28_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_29_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_30_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] io_out_s_31_bits = io_in_0; // @[RVC.scala:21:19, :190:7] wire [31:0] _io_out_T_64_bits; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rd; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs1; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs2; // @[package.scala:39:76] wire [4:0] _io_out_T_64_rs3; // @[package.scala:39:76] wire _io_rvc_T_1; // @[RVC.scala:199:26] wire _io_ill_T_64; // @[package.scala:39:76] wire [31:0] io_out_bits_0; // @[RVC.scala:190:7] wire [4:0] io_out_rd; // @[RVC.scala:190:7] wire [4:0] io_out_rs1; // @[RVC.scala:190:7] wire [4:0] io_out_rs2; // @[RVC.scala:190:7] wire [4:0] io_out_rs3; // @[RVC.scala:190:7] wire io_rvc_0; // @[RVC.scala:190:7] wire io_ill; // @[RVC.scala:190:7] wire [1:0] _io_rvc_T = io_in_0[1:0]; // @[RVC.scala:190:7, :199:20] wire [1:0] _io_out_T = io_in_0[1:0]; // @[RVC.scala:154:12, :190:7, :199:20] wire [1:0] _io_ill_T = io_in_0[1:0]; // @[RVC.scala:186:12, :190:7, :199:20] assign _io_rvc_T_1 = _io_rvc_T != 2'h3; // @[RVC.scala:199:{20,26}] assign io_rvc_0 = _io_rvc_T_1; // @[RVC.scala:190:7, :199:26] wire [7:0] _io_out_s_opc_T = io_in_0[12:5]; // @[RVC.scala:53:22, :190:7] wire _io_out_s_opc_T_1 = |_io_out_s_opc_T; // @[RVC.scala:53:{22,29}] wire [6:0] io_out_s_opc = _io_out_s_opc_T_1 ? 7'h13 : 7'h1F; // @[RVC.scala:53:{20,29}] wire [3:0] _io_out_s_T = io_in_0[10:7]; // @[RVC.scala:34:26, :190:7] wire [1:0] _io_out_s_T_1 = io_in_0[12:11]; // @[RVC.scala:34:35, :190:7] wire _io_out_s_T_2 = io_in_0[5]; // @[RVC.scala:34:45, :190:7] wire _io_out_s_T_28 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_59 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_68 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_101 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_110 = io_in_0[5]; // @[RVC.scala:34:45, :35:20, :190:7] wire _io_out_s_T_185 = io_in_0[5]; // @[RVC.scala:34:45, :42:50, :190:7] wire _io_out_s_T_3 = io_in_0[6]; // @[RVC.scala:34:51, :190:7] wire _io_out_s_T_30 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_61 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_70 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_103 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_112 = io_in_0[6]; // @[RVC.scala:34:51, :35:36, :190:7] wire _io_out_s_T_187 = io_in_0[6]; // @[RVC.scala:34:51, :42:62, :190:7] wire _io_out_s_T_249 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_260 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_271 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_out_s_T_282 = io_in_0[6]; // @[RVC.scala:34:51, :44:51, :190:7] wire _io_ill_s_T_9 = io_in_0[6]; // @[RVC.scala:34:51, :169:69, :190:7] wire [2:0] io_out_s_lo = {_io_out_s_T_3, 2'h0}; // @[RVC.scala:34:{24,51}] wire [5:0] io_out_s_hi_hi = {_io_out_s_T, _io_out_s_T_1}; // @[RVC.scala:34:{24,26,35}] wire [6:0] io_out_s_hi = {io_out_s_hi_hi, _io_out_s_T_2}; // @[RVC.scala:34:{24,45}] wire [9:0] _io_out_s_T_4 = {io_out_s_hi, io_out_s_lo}; // @[RVC.scala:34:24] wire [2:0] _io_out_s_T_5 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_8 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_10 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_18 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_21 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_25 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_34 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_37 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_41 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_49 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_52 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_56 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_64 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_74 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_78 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_85 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_94 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_98 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_106 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_116 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_120 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_127 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_136 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_140 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_152 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_164 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_174 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_me_T_9 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_194 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_223 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_242 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_292 = io_in_0[4:2]; // @[RVC.scala:31:29, :190:7] wire [2:0] _io_out_s_T_383 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [2:0] _io_out_s_T_401 = io_in_0[4:2]; // @[RVC.scala:31:29, :38:22, :190:7] wire [4:0] _io_out_s_T_6 = {2'h1, _io_out_s_T_5}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_1 = {_io_out_s_T_6, io_out_s_opc}; // @[RVC.scala:31:17, :53:20, :54:15] wire [14:0] io_out_s_hi_hi_1 = {_io_out_s_T_4, 5'h2}; // @[package.scala:39:86] wire [17:0] io_out_s_hi_1 = {io_out_s_hi_hi_1, 3'h0}; // @[RVC.scala:54:15] wire [29:0] _io_out_s_T_7 = {io_out_s_hi_1, io_out_s_lo_1}; // @[RVC.scala:54:15] wire [4:0] _io_out_s_T_9 = {2'h1, _io_out_s_T_8}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rd = _io_out_s_T_9; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_11 = {2'h1, _io_out_s_T_10}; // @[package.scala:39:86] wire [4:0] io_out_s_0_rs2 = _io_out_s_T_11; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_12 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_27 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_43 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_58 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_80 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_100 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_122 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_142 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_154 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_166 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_176 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_me_T_11 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_196 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_244 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_294 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_334 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_372 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_382 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_391 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_400 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_409 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_mv_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_add_T_7 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jr_reserved_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_5 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_423 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_436 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_449 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_453 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_457 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_461 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_465 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_469 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_473 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_477 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] _io_out_s_T_481 = io_in_0[31:27]; // @[RVC.scala:20:101, :190:7] wire [4:0] io_out_s_0_rs3 = _io_out_s_T_12; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_0_bits; // @[RVC.scala:21:19] assign io_out_s_0_bits = {2'h0, _io_out_s_T_7}; // @[RVC.scala:21:19, :22:14, :54:15] wire [1:0] _io_out_s_T_13 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_44 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_81 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_89 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_123 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_T_131 = io_in_0[6:5]; // @[RVC.scala:36:20, :190:7] wire [1:0] _io_out_s_funct_T_1 = io_in_0[6:5]; // @[RVC.scala:36:20, :102:77, :190:7] wire [1:0] _io_out_s_sub_T = io_in_0[6:5]; // @[RVC.scala:36:20, :103:24, :190:7] wire [1:0] _io_out_s_T_297 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_305 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_315 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_323 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_337 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_345 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_355 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_363 = io_in_0[6:5]; // @[RVC.scala:36:20, :45:35, :190:7] wire [1:0] _io_out_s_T_385 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [1:0] _io_out_s_T_403 = io_in_0[6:5]; // @[RVC.scala:36:20, :38:37, :190:7] wire [2:0] _io_out_s_T_14 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_29 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_45 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_60 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_69 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_82 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_90 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_102 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_111 = io_in_0[12:10]; // @[RVC.scala:35:26, :36:28, :190:7] wire [2:0] _io_out_s_T_124 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_132 = io_in_0[12:10]; // @[RVC.scala:36:28, :190:7] wire [2:0] _io_out_s_T_412 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_417 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_438 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_out_s_T_443 = io_in_0[12:10]; // @[RVC.scala:36:28, :40:30, :190:7] wire [2:0] _io_ill_s_T_7 = io_in_0[12:10]; // @[RVC.scala:36:28, :169:22, :190:7] wire [4:0] io_out_s_hi_2 = {_io_out_s_T_13, _io_out_s_T_14}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_15 = {io_out_s_hi_2, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_16 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_23 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_32 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_39 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_47 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_54 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_66 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_76 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_87 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_96 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_108 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_118 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_129 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_138 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_200 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_202 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_208 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_210 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_218 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_220 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_225 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_227 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_238 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_240 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_290 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_311 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_330 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_332 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_351 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_370 = io_in_0[9:7]; // @[RVC.scala:30:29, :190:7] wire [2:0] _io_out_s_T_411 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_416 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_437 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [2:0] _io_out_s_T_442 = io_in_0[9:7]; // @[RVC.scala:30:29, :40:22, :190:7] wire [4:0] _io_out_s_T_17 = {2'h1, _io_out_s_T_16}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_19 = {2'h1, _io_out_s_T_18}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_2 = {_io_out_s_T_19, 7'h7}; // @[RVC.scala:31:17, :58:23] wire [12:0] io_out_s_hi_hi_2 = {_io_out_s_T_15, _io_out_s_T_17}; // @[RVC.scala:30:17, :36:18, :58:23] wire [15:0] io_out_s_hi_3 = {io_out_s_hi_hi_2, 3'h3}; // @[RVC.scala:58:23] wire [27:0] _io_out_s_T_20 = {io_out_s_hi_3, io_out_s_lo_2}; // @[RVC.scala:58:23] wire [4:0] _io_out_s_T_22 = {2'h1, _io_out_s_T_21}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rd = _io_out_s_T_22; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_24 = {2'h1, _io_out_s_T_23}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs1 = _io_out_s_T_24; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_26 = {2'h1, _io_out_s_T_25}; // @[package.scala:39:86] wire [4:0] io_out_s_1_rs2 = _io_out_s_T_26; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_1_rs3 = _io_out_s_T_27; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_1_bits; // @[RVC.scala:21:19] assign io_out_s_1_bits = {4'h0, _io_out_s_T_20}; // @[RVC.scala:21:19, :22:14, :58:23] wire [2:0] io_out_s_lo_3 = {_io_out_s_T_30, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_4 = {_io_out_s_T_28, _io_out_s_T_29}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_31 = {io_out_s_hi_4, io_out_s_lo_3}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_33 = {2'h1, _io_out_s_T_32}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_35 = {2'h1, _io_out_s_T_34}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_4 = {_io_out_s_T_35, 7'h3}; // @[RVC.scala:31:17, :57:22] wire [11:0] io_out_s_hi_hi_3 = {_io_out_s_T_31, _io_out_s_T_33}; // @[RVC.scala:30:17, :35:18, :57:22] wire [14:0] io_out_s_hi_5 = {io_out_s_hi_hi_3, 3'h2}; // @[package.scala:39:86] wire [26:0] _io_out_s_T_36 = {io_out_s_hi_5, io_out_s_lo_4}; // @[RVC.scala:57:22] wire [4:0] _io_out_s_T_38 = {2'h1, _io_out_s_T_37}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rd = _io_out_s_T_38; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_40 = {2'h1, _io_out_s_T_39}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs1 = _io_out_s_T_40; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_42 = {2'h1, _io_out_s_T_41}; // @[package.scala:39:86] wire [4:0] io_out_s_2_rs2 = _io_out_s_T_42; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_2_rs3 = _io_out_s_T_43; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_2_bits; // @[RVC.scala:21:19] assign io_out_s_2_bits = {5'h0, _io_out_s_T_36}; // @[RVC.scala:21:19, :22:14, :57:22] wire [4:0] io_out_s_hi_6 = {_io_out_s_T_44, _io_out_s_T_45}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_46 = {io_out_s_hi_6, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_48 = {2'h1, _io_out_s_T_47}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_50 = {2'h1, _io_out_s_T_49}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_5 = {_io_out_s_T_50, 7'h3}; // @[RVC.scala:31:17, :56:22] wire [12:0] io_out_s_hi_hi_4 = {_io_out_s_T_46, _io_out_s_T_48}; // @[RVC.scala:30:17, :36:18, :56:22] wire [15:0] io_out_s_hi_7 = {io_out_s_hi_hi_4, 3'h3}; // @[RVC.scala:56:22] wire [27:0] _io_out_s_T_51 = {io_out_s_hi_7, io_out_s_lo_5}; // @[RVC.scala:56:22] wire [4:0] _io_out_s_T_53 = {2'h1, _io_out_s_T_52}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rd = _io_out_s_T_53; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_55 = {2'h1, _io_out_s_T_54}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs1 = _io_out_s_T_55; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_57 = {2'h1, _io_out_s_T_56}; // @[package.scala:39:86] wire [4:0] io_out_s_3_rs2 = _io_out_s_T_57; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_3_rs3 = _io_out_s_T_58; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_3_bits; // @[RVC.scala:21:19] assign io_out_s_3_bits = {4'h0, _io_out_s_T_51}; // @[RVC.scala:21:19, :22:14, :56:22] wire [2:0] io_out_s_lo_6 = {_io_out_s_T_61, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_8 = {_io_out_s_T_59, _io_out_s_T_60}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_62 = {io_out_s_hi_8, io_out_s_lo_6}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_63 = _io_out_s_T_62[6:5]; // @[RVC.scala:35:18, :63:32] wire [4:0] _io_out_s_T_65 = {2'h1, _io_out_s_T_64}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_67 = {2'h1, _io_out_s_T_66}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_7 = {_io_out_s_T_70, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_9 = {_io_out_s_T_68, _io_out_s_T_69}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_71 = {io_out_s_hi_9, io_out_s_lo_7}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_72 = _io_out_s_T_71[4:0]; // @[RVC.scala:35:18, :63:65] wire [7:0] io_out_s_lo_hi = {3'h2, _io_out_s_T_72}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_8 = {io_out_s_lo_hi, 7'h3F}; // @[RVC.scala:63:25] wire [6:0] io_out_s_hi_hi_5 = {_io_out_s_T_63, _io_out_s_T_65}; // @[RVC.scala:31:17, :63:{25,32}] wire [11:0] io_out_s_hi_10 = {io_out_s_hi_hi_5, _io_out_s_T_67}; // @[RVC.scala:30:17, :63:25] wire [26:0] _io_out_s_T_73 = {io_out_s_hi_10, io_out_s_lo_8}; // @[RVC.scala:63:25] wire [4:0] _io_out_s_T_75 = {2'h1, _io_out_s_T_74}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rd = _io_out_s_T_75; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_77 = {2'h1, _io_out_s_T_76}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs1 = _io_out_s_T_77; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_79 = {2'h1, _io_out_s_T_78}; // @[package.scala:39:86] wire [4:0] io_out_s_4_rs2 = _io_out_s_T_79; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_4_rs3 = _io_out_s_T_80; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_4_bits; // @[RVC.scala:21:19] assign io_out_s_4_bits = {5'h0, _io_out_s_T_73}; // @[RVC.scala:21:19, :22:14, :63:25] wire [4:0] io_out_s_hi_11 = {_io_out_s_T_81, _io_out_s_T_82}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_83 = {io_out_s_hi_11, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_84 = _io_out_s_T_83[7:5]; // @[RVC.scala:36:18, :66:30] wire [4:0] _io_out_s_T_86 = {2'h1, _io_out_s_T_85}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_88 = {2'h1, _io_out_s_T_87}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_12 = {_io_out_s_T_89, _io_out_s_T_90}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_91 = {io_out_s_hi_12, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_92 = _io_out_s_T_91[4:0]; // @[RVC.scala:36:18, :66:63] wire [7:0] io_out_s_lo_hi_1 = {3'h3, _io_out_s_T_92}; // @[RVC.scala:66:{23,63}] wire [14:0] io_out_s_lo_9 = {io_out_s_lo_hi_1, 7'h27}; // @[RVC.scala:66:23] wire [7:0] io_out_s_hi_hi_6 = {_io_out_s_T_84, _io_out_s_T_86}; // @[RVC.scala:31:17, :66:{23,30}] wire [12:0] io_out_s_hi_13 = {io_out_s_hi_hi_6, _io_out_s_T_88}; // @[RVC.scala:30:17, :66:23] wire [27:0] _io_out_s_T_93 = {io_out_s_hi_13, io_out_s_lo_9}; // @[RVC.scala:66:23] wire [4:0] _io_out_s_T_95 = {2'h1, _io_out_s_T_94}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rd = _io_out_s_T_95; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_97 = {2'h1, _io_out_s_T_96}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs1 = _io_out_s_T_97; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_99 = {2'h1, _io_out_s_T_98}; // @[package.scala:39:86] wire [4:0] io_out_s_5_rs2 = _io_out_s_T_99; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_5_rs3 = _io_out_s_T_100; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_5_bits; // @[RVC.scala:21:19] assign io_out_s_5_bits = {4'h0, _io_out_s_T_93}; // @[RVC.scala:21:19, :22:14, :66:23] wire [2:0] io_out_s_lo_10 = {_io_out_s_T_103, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_14 = {_io_out_s_T_101, _io_out_s_T_102}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_104 = {io_out_s_hi_14, io_out_s_lo_10}; // @[RVC.scala:35:18] wire [1:0] _io_out_s_T_105 = _io_out_s_T_104[6:5]; // @[RVC.scala:35:18, :65:29] wire [4:0] _io_out_s_T_107 = {2'h1, _io_out_s_T_106}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_109 = {2'h1, _io_out_s_T_108}; // @[package.scala:39:86] wire [2:0] io_out_s_lo_11 = {_io_out_s_T_112, 2'h0}; // @[RVC.scala:35:{18,36}] wire [3:0] io_out_s_hi_15 = {_io_out_s_T_110, _io_out_s_T_111}; // @[RVC.scala:35:{18,20,26}] wire [6:0] _io_out_s_T_113 = {io_out_s_hi_15, io_out_s_lo_11}; // @[RVC.scala:35:18] wire [4:0] _io_out_s_T_114 = _io_out_s_T_113[4:0]; // @[RVC.scala:35:18, :65:62] wire [7:0] io_out_s_lo_hi_2 = {3'h2, _io_out_s_T_114}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_12 = {io_out_s_lo_hi_2, 7'h23}; // @[RVC.scala:65:22] wire [6:0] io_out_s_hi_hi_7 = {_io_out_s_T_105, _io_out_s_T_107}; // @[RVC.scala:31:17, :65:{22,29}] wire [11:0] io_out_s_hi_16 = {io_out_s_hi_hi_7, _io_out_s_T_109}; // @[RVC.scala:30:17, :65:22] wire [26:0] _io_out_s_T_115 = {io_out_s_hi_16, io_out_s_lo_12}; // @[RVC.scala:65:22] wire [4:0] _io_out_s_T_117 = {2'h1, _io_out_s_T_116}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rd = _io_out_s_T_117; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_119 = {2'h1, _io_out_s_T_118}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs1 = _io_out_s_T_119; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_121 = {2'h1, _io_out_s_T_120}; // @[package.scala:39:86] wire [4:0] io_out_s_6_rs2 = _io_out_s_T_121; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_6_rs3 = _io_out_s_T_122; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_6_bits; // @[RVC.scala:21:19] assign io_out_s_6_bits = {5'h0, _io_out_s_T_115}; // @[RVC.scala:21:19, :22:14, :65:22] wire [4:0] io_out_s_hi_17 = {_io_out_s_T_123, _io_out_s_T_124}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_125 = {io_out_s_hi_17, 3'h0}; // @[RVC.scala:36:18] wire [2:0] _io_out_s_T_126 = _io_out_s_T_125[7:5]; // @[RVC.scala:36:18, :64:29] wire [4:0] _io_out_s_T_128 = {2'h1, _io_out_s_T_127}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_130 = {2'h1, _io_out_s_T_129}; // @[package.scala:39:86] wire [4:0] io_out_s_hi_18 = {_io_out_s_T_131, _io_out_s_T_132}; // @[RVC.scala:36:{18,20,28}] wire [7:0] _io_out_s_T_133 = {io_out_s_hi_18, 3'h0}; // @[RVC.scala:36:18] wire [4:0] _io_out_s_T_134 = _io_out_s_T_133[4:0]; // @[RVC.scala:36:18, :64:62] wire [7:0] io_out_s_lo_hi_3 = {3'h3, _io_out_s_T_134}; // @[RVC.scala:64:{22,62}] wire [14:0] io_out_s_lo_13 = {io_out_s_lo_hi_3, 7'h23}; // @[RVC.scala:64:22] wire [7:0] io_out_s_hi_hi_8 = {_io_out_s_T_126, _io_out_s_T_128}; // @[RVC.scala:31:17, :64:{22,29}] wire [12:0] io_out_s_hi_19 = {io_out_s_hi_hi_8, _io_out_s_T_130}; // @[RVC.scala:30:17, :64:22] wire [27:0] _io_out_s_T_135 = {io_out_s_hi_19, io_out_s_lo_13}; // @[RVC.scala:64:22] wire [4:0] _io_out_s_T_137 = {2'h1, _io_out_s_T_136}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rd = _io_out_s_T_137; // @[RVC.scala:21:19, :31:17] wire [4:0] _io_out_s_T_139 = {2'h1, _io_out_s_T_138}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs1 = _io_out_s_T_139; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_141 = {2'h1, _io_out_s_T_140}; // @[package.scala:39:86] wire [4:0] io_out_s_7_rs2 = _io_out_s_T_141; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_7_rs3 = _io_out_s_T_142; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_7_bits; // @[RVC.scala:21:19] assign io_out_s_7_bits = {4'h0, _io_out_s_T_135}; // @[RVC.scala:21:19, :22:14, :64:22] wire _io_out_s_T_143 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_155 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_167 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_opc_T_4 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_me_T = io_in_0[12]; // @[RVC.scala:41:30, :43:30, :190:7] wire _io_out_s_opc_T_9 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_T_182 = io_in_0[12]; // @[RVC.scala:42:34, :43:30, :190:7] wire _io_out_s_T_197 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_205 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_214 = io_in_0[12]; // @[RVC.scala:43:30, :190:7] wire _io_out_s_funct_T = io_in_0[12]; // @[RVC.scala:43:30, :102:70, :190:7] wire _io_out_s_opc_T_14 = io_in_0[12]; // @[RVC.scala:43:30, :104:24, :190:7] wire _io_out_s_T_245 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_256 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_267 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_278 = io_in_0[12]; // @[RVC.scala:43:30, :44:28, :190:7] wire _io_out_s_T_295 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_303 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_313 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_321 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_335 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_343 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_353 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_361 = io_in_0[12]; // @[RVC.scala:43:30, :45:27, :190:7] wire _io_out_s_T_373 = io_in_0[12]; // @[RVC.scala:43:30, :46:20, :190:7] wire _io_out_s_T_384 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_393 = io_in_0[12]; // @[RVC.scala:37:30, :43:30, :190:7] wire _io_out_s_T_402 = io_in_0[12]; // @[RVC.scala:38:30, :43:30, :190:7] wire _io_out_s_T_410 = io_in_0[12]; // @[RVC.scala:43:30, :143:12, :190:7] wire _io_ill_s_T_3 = io_in_0[12]; // @[RVC.scala:43:30, :168:19, :190:7] wire [6:0] _io_out_s_T_144 = {7{_io_out_s_T_143}}; // @[RVC.scala:43:{25,30}] wire [4:0] _io_out_s_T_145 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_157 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_169 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_opc_T_6 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_me_T_2 = io_in_0[6:2]; // @[RVC.scala:41:38, :43:38, :190:7] wire [4:0] _io_out_s_opc_T_11 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_198 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_206 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_216 = io_in_0[6:2]; // @[RVC.scala:43:38, :190:7] wire [4:0] _io_out_s_T_374 = io_in_0[6:2]; // @[RVC.scala:43:38, :46:27, :190:7] wire [4:0] _io_out_s_T_381 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_390 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_399 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_408 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_mv_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_add_T_6 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_reserved_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jr_mv_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_4 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_jalr_add_T = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_415 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_422 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_428 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_435 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_441 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_out_s_T_448 = io_in_0[6:2]; // @[RVC.scala:32:14, :43:38, :190:7] wire [4:0] _io_ill_s_T_4 = io_in_0[6:2]; // @[RVC.scala:43:38, :168:27, :190:7] wire [11:0] _io_out_s_T_146 = {_io_out_s_T_144, _io_out_s_T_145}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_147 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_148 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_150 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_151 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_opc_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_159 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_160 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_162 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_163 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_171 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_173 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_7 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_me_T_8 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_177 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_179 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_189 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_190 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_192 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_193 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_load_opc_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_376 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_377 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_379 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_380 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_387 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_389 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_396 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_398 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_405 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_407 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_mv_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_4 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_add_T_5 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jr_reserved_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_T_1 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_jalr_ebreak_T_3 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_421 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_434 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_447 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_out_s_T_450 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_454 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_458 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_462 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_466 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_470 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_474 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_out_s_T_478 = io_in_0[11:7]; // @[RVC.scala:20:36, :33:13, :190:7] wire [4:0] _io_ill_s_T_2 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_11 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [4:0] _io_ill_s_T_12 = io_in_0[11:7]; // @[RVC.scala:33:13, :190:7] wire [11:0] io_out_s_lo_14 = {_io_out_s_T_148, 7'h13}; // @[RVC.scala:33:13, :75:24] wire [16:0] io_out_s_hi_hi_9 = {_io_out_s_T_146, _io_out_s_T_147}; // @[RVC.scala:33:13, :43:20, :75:24] wire [19:0] io_out_s_hi_20 = {io_out_s_hi_hi_9, 3'h0}; // @[RVC.scala:75:24] wire [31:0] _io_out_s_T_149 = {io_out_s_hi_20, io_out_s_lo_14}; // @[RVC.scala:75:24] wire [31:0] io_out_s_8_bits = _io_out_s_T_149; // @[RVC.scala:21:19, :75:24] wire [4:0] io_out_s_8_rd = _io_out_s_T_150; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_8_rs1 = _io_out_s_T_151; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_153 = {2'h1, _io_out_s_T_152}; // @[package.scala:39:86] wire [4:0] io_out_s_8_rs2 = _io_out_s_T_153; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_8_rs3 = _io_out_s_T_154; // @[RVC.scala:20:101, :21:19] wire _io_out_s_opc_T_3 = |_io_out_s_opc_T_2; // @[RVC.scala:33:13, :77:24] wire [6:0] io_out_s_opc_1 = {4'h3, ~_io_out_s_opc_T_3, 2'h3}; // @[RVC.scala:77:{20,24}] wire [6:0] _io_out_s_T_156 = {7{_io_out_s_T_155}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_158 = {_io_out_s_T_156, _io_out_s_T_157}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_15 = {_io_out_s_T_160, io_out_s_opc_1}; // @[RVC.scala:33:13, :77:20, :78:15] wire [16:0] io_out_s_hi_hi_10 = {_io_out_s_T_158, _io_out_s_T_159}; // @[RVC.scala:33:13, :43:20, :78:15] wire [19:0] io_out_s_hi_21 = {io_out_s_hi_hi_10, 3'h0}; // @[RVC.scala:78:15] wire [31:0] _io_out_s_T_161 = {io_out_s_hi_21, io_out_s_lo_15}; // @[RVC.scala:78:15] wire [31:0] io_out_s_9_bits = _io_out_s_T_161; // @[RVC.scala:21:19, :78:15] wire [4:0] io_out_s_9_rd = _io_out_s_T_162; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_9_rs1 = _io_out_s_T_163; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_165 = {2'h1, _io_out_s_T_164}; // @[package.scala:39:86] wire [4:0] io_out_s_9_rs2 = _io_out_s_T_165; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_9_rs3 = _io_out_s_T_166; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_T_168 = {7{_io_out_s_T_167}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_170 = {_io_out_s_T_168, _io_out_s_T_169}; // @[RVC.scala:43:{20,25,38}] wire [11:0] io_out_s_lo_16 = {_io_out_s_T_171, 7'h13}; // @[RVC.scala:33:13, :84:22] wire [16:0] io_out_s_hi_hi_11 = {_io_out_s_T_170, 5'h0}; // @[RVC.scala:43:20, :84:22] wire [19:0] io_out_s_hi_22 = {io_out_s_hi_hi_11, 3'h0}; // @[RVC.scala:84:22] wire [31:0] _io_out_s_T_172 = {io_out_s_hi_22, io_out_s_lo_16}; // @[RVC.scala:84:22] wire [31:0] io_out_s_10_bits = _io_out_s_T_172; // @[RVC.scala:21:19, :84:22] wire [4:0] io_out_s_10_rd = _io_out_s_T_173; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_175 = {2'h1, _io_out_s_T_174}; // @[package.scala:39:86] wire [4:0] io_out_s_10_rs2 = _io_out_s_T_175; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_10_rs3 = _io_out_s_T_176; // @[RVC.scala:20:101, :21:19] wire [6:0] _io_out_s_opc_T_5 = {7{_io_out_s_opc_T_4}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_7 = {_io_out_s_opc_T_5, _io_out_s_opc_T_6}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_8 = |_io_out_s_opc_T_7; // @[RVC.scala:43:20, :90:29] wire [6:0] io_out_s_opc_2 = {3'h3, ~_io_out_s_opc_T_8, 3'h7}; // @[RVC.scala:90:{20,29}] wire [14:0] _io_out_s_me_T_1 = {15{_io_out_s_me_T}}; // @[RVC.scala:41:{24,30}] wire [19:0] io_out_s_me_hi = {_io_out_s_me_T_1, _io_out_s_me_T_2}; // @[RVC.scala:41:{19,24,38}] wire [31:0] _io_out_s_me_T_3 = {io_out_s_me_hi, 12'h0}; // @[RVC.scala:41:19] wire [19:0] _io_out_s_me_T_4 = _io_out_s_me_T_3[31:12]; // @[RVC.scala:41:19, :91:31] wire [24:0] io_out_s_me_hi_1 = {_io_out_s_me_T_4, _io_out_s_me_T_5}; // @[RVC.scala:33:13, :91:{24,31}] wire [31:0] _io_out_s_me_T_6 = {io_out_s_me_hi_1, io_out_s_opc_2}; // @[RVC.scala:90:20, :91:24] wire [31:0] io_out_s_me_bits = _io_out_s_me_T_6; // @[RVC.scala:21:19, :91:24] wire [4:0] io_out_s_me_rd = _io_out_s_me_T_7; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_me_rs1 = _io_out_s_me_T_8; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_me_T_10 = {2'h1, _io_out_s_me_T_9}; // @[package.scala:39:86] wire [4:0] io_out_s_me_rs2 = _io_out_s_me_T_10; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_me_rs3 = _io_out_s_me_T_11; // @[RVC.scala:20:101, :21:19] wire _io_out_s_T_178 = _io_out_s_T_177 == 5'h0; // @[RVC.scala:33:13, :92:14] wire _io_out_s_T_180 = _io_out_s_T_179 == 5'h2; // @[package.scala:39:86] wire _io_out_s_T_181 = _io_out_s_T_178 | _io_out_s_T_180; // @[RVC.scala:92:{14,21,27}] wire [6:0] _io_out_s_opc_T_10 = {7{_io_out_s_opc_T_9}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_opc_T_12 = {_io_out_s_opc_T_10, _io_out_s_opc_T_11}; // @[RVC.scala:43:{20,25,38}] wire _io_out_s_opc_T_13 = |_io_out_s_opc_T_12; // @[RVC.scala:43:20, :86:29] wire [6:0] io_out_s_opc_3 = _io_out_s_opc_T_13 ? 7'h13 : 7'h1F; // @[RVC.scala:86:{20,29}] wire [2:0] _io_out_s_T_183 = {3{_io_out_s_T_182}}; // @[RVC.scala:42:{29,34}] wire [1:0] _io_out_s_T_184 = io_in_0[4:3]; // @[RVC.scala:42:42, :190:7] wire [1:0] _io_out_s_T_300 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_308 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_318 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_326 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_340 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_348 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_358 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire [1:0] _io_out_s_T_366 = io_in_0[4:3]; // @[RVC.scala:42:42, :45:59, :190:7] wire _io_out_s_T_186 = io_in_0[2]; // @[RVC.scala:42:56, :190:7] wire _io_out_s_T_251 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_262 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_273 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_284 = io_in_0[2]; // @[RVC.scala:42:56, :44:63, :190:7] wire _io_out_s_T_298 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_306 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_316 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_324 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_338 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_346 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_356 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire _io_out_s_T_364 = io_in_0[2]; // @[RVC.scala:42:56, :45:43, :190:7] wire [1:0] io_out_s_lo_hi_4 = {_io_out_s_T_186, _io_out_s_T_187}; // @[RVC.scala:42:{24,56,62}] wire [5:0] io_out_s_lo_17 = {io_out_s_lo_hi_4, 4'h0}; // @[RVC.scala:42:24] wire [4:0] io_out_s_hi_hi_12 = {_io_out_s_T_183, _io_out_s_T_184}; // @[RVC.scala:42:{24,29,42}] wire [5:0] io_out_s_hi_23 = {io_out_s_hi_hi_12, _io_out_s_T_185}; // @[RVC.scala:42:{24,50}] wire [11:0] _io_out_s_T_188 = {io_out_s_hi_23, io_out_s_lo_17}; // @[RVC.scala:42:24] wire [11:0] io_out_s_lo_18 = {_io_out_s_T_190, io_out_s_opc_3}; // @[RVC.scala:33:13, :86:20, :87:15] wire [16:0] io_out_s_hi_hi_13 = {_io_out_s_T_188, _io_out_s_T_189}; // @[RVC.scala:33:13, :42:24, :87:15] wire [19:0] io_out_s_hi_24 = {io_out_s_hi_hi_13, 3'h0}; // @[RVC.scala:87:15] wire [31:0] _io_out_s_T_191 = {io_out_s_hi_24, io_out_s_lo_18}; // @[RVC.scala:87:15] wire [31:0] io_out_s_res_bits = _io_out_s_T_191; // @[RVC.scala:21:19, :87:15] wire [4:0] io_out_s_res_rd = _io_out_s_T_192; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_res_rs1 = _io_out_s_T_193; // @[RVC.scala:21:19, :33:13] wire [4:0] _io_out_s_T_195 = {2'h1, _io_out_s_T_194}; // @[package.scala:39:86] wire [4:0] io_out_s_res_rs2 = _io_out_s_T_195; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_res_rs3 = _io_out_s_T_196; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_11_bits = _io_out_s_T_181 ? io_out_s_res_bits : io_out_s_me_bits; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rd = _io_out_s_T_181 ? io_out_s_res_rd : io_out_s_me_rd; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs1 = _io_out_s_T_181 ? io_out_s_res_rs1 : io_out_s_me_rs1; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs2 = _io_out_s_T_181 ? io_out_s_res_rs2 : io_out_s_me_rs2; // @[RVC.scala:21:19, :92:{10,21}] wire [4:0] io_out_s_11_rs3 = _io_out_s_T_181 ? io_out_s_res_rs3 : io_out_s_me_rs3; // @[RVC.scala:21:19, :92:{10,21}] wire [5:0] _io_out_s_T_199 = {_io_out_s_T_197, _io_out_s_T_198}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_201 = {2'h1, _io_out_s_T_200}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_203 = {2'h1, _io_out_s_T_202}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_19 = {_io_out_s_T_203, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_14 = {_io_out_s_T_199, _io_out_s_T_201}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_25 = {io_out_s_hi_hi_14, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_204 = {io_out_s_hi_25, io_out_s_lo_19}; // @[RVC.scala:98:21] wire [5:0] _io_out_s_T_207 = {_io_out_s_T_205, _io_out_s_T_206}; // @[RVC.scala:46:{18,20,27}] wire [4:0] _io_out_s_T_209 = {2'h1, _io_out_s_T_208}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_211 = {2'h1, _io_out_s_T_210}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_20 = {_io_out_s_T_211, 7'h13}; // @[RVC.scala:30:17, :98:21] wire [10:0] io_out_s_hi_hi_15 = {_io_out_s_T_207, _io_out_s_T_209}; // @[RVC.scala:30:17, :46:18, :98:21] wire [13:0] io_out_s_hi_26 = {io_out_s_hi_hi_15, 3'h5}; // @[RVC.scala:98:21] wire [25:0] _io_out_s_T_212 = {io_out_s_hi_26, io_out_s_lo_20}; // @[RVC.scala:98:21] wire [30:0] _io_out_s_T_213 = {5'h10, _io_out_s_T_212}; // @[RVC.scala:98:21, :99:23] wire [6:0] _io_out_s_T_215 = {7{_io_out_s_T_214}}; // @[RVC.scala:43:{25,30}] wire [11:0] _io_out_s_T_217 = {_io_out_s_T_215, _io_out_s_T_216}; // @[RVC.scala:43:{20,25,38}] wire [4:0] _io_out_s_T_219 = {2'h1, _io_out_s_T_218}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_221 = {2'h1, _io_out_s_T_220}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_21 = {_io_out_s_T_221, 7'h13}; // @[RVC.scala:30:17, :100:21] wire [16:0] io_out_s_hi_hi_16 = {_io_out_s_T_217, _io_out_s_T_219}; // @[RVC.scala:30:17, :43:20, :100:21] wire [19:0] io_out_s_hi_27 = {io_out_s_hi_hi_16, 3'h7}; // @[RVC.scala:100:21] wire [31:0] _io_out_s_T_222 = {io_out_s_hi_27, io_out_s_lo_21}; // @[RVC.scala:100:21] wire [2:0] _io_out_s_funct_T_2 = {_io_out_s_funct_T, _io_out_s_funct_T_1}; // @[RVC.scala:102:{68,70,77}] wire _io_out_s_funct_T_3 = _io_out_s_funct_T_2 == 3'h1; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_4 = {_io_out_s_funct_T_3, 2'h0}; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_5 = _io_out_s_funct_T_2 == 3'h2; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_6 = _io_out_s_funct_T_5 ? 3'h6 : _io_out_s_funct_T_4; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_7 = _io_out_s_funct_T_2 == 3'h3; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_8 = _io_out_s_funct_T_7 ? 3'h7 : _io_out_s_funct_T_6; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_9 = _io_out_s_funct_T_2 == 3'h4; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_10 = _io_out_s_funct_T_9 ? 3'h0 : _io_out_s_funct_T_8; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_11 = _io_out_s_funct_T_2 == 3'h5; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_12 = _io_out_s_funct_T_11 ? 3'h0 : _io_out_s_funct_T_10; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_13 = _io_out_s_funct_T_2 == 3'h6; // @[package.scala:39:86] wire [2:0] _io_out_s_funct_T_14 = _io_out_s_funct_T_13 ? 3'h2 : _io_out_s_funct_T_12; // @[package.scala:39:{76,86}] wire _io_out_s_funct_T_15 = &_io_out_s_funct_T_2; // @[package.scala:39:86] wire [2:0] io_out_s_funct = _io_out_s_funct_T_15 ? 3'h3 : _io_out_s_funct_T_14; // @[package.scala:39:{76,86}] wire _io_out_s_sub_T_1 = _io_out_s_sub_T == 2'h0; // @[RVC.scala:103:{24,30}] wire [30:0] io_out_s_sub = {_io_out_s_sub_T_1, 30'h0}; // @[RVC.scala:103:{22,30}] wire [6:0] io_out_s_opc_4 = {3'h3, _io_out_s_opc_T_14, 3'h3}; // @[RVC.scala:104:{22,24}] wire [4:0] _io_out_s_T_224 = {2'h1, _io_out_s_T_223}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_226 = {2'h1, _io_out_s_T_225}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_228 = {2'h1, _io_out_s_T_227}; // @[package.scala:39:86] wire [11:0] io_out_s_lo_22 = {_io_out_s_T_228, io_out_s_opc_4}; // @[RVC.scala:30:17, :104:22, :105:12] wire [9:0] io_out_s_hi_hi_17 = {_io_out_s_T_224, _io_out_s_T_226}; // @[RVC.scala:30:17, :31:17, :105:12] wire [12:0] io_out_s_hi_28 = {io_out_s_hi_hi_17, io_out_s_funct}; // @[package.scala:39:76] wire [24:0] _io_out_s_T_229 = {io_out_s_hi_28, io_out_s_lo_22}; // @[RVC.scala:105:12] wire [30:0] _io_out_s_T_230 = {6'h0, _io_out_s_T_229} | io_out_s_sub; // @[RVC.scala:103:22, :105:{12,43}] wire [1:0] _io_out_s_T_231 = io_in_0[11:10]; // @[RVC.scala:107:42, :190:7] wire [1:0] _io_out_s_T_299 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_307 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_317 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_325 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_339 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_347 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_357 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire [1:0] _io_out_s_T_365 = io_in_0[11:10]; // @[RVC.scala:45:49, :107:42, :190:7] wire _io_out_s_T_232 = _io_out_s_T_231 == 2'h1; // @[package.scala:39:86] wire [30:0] _io_out_s_T_233 = _io_out_s_T_232 ? _io_out_s_T_213 : {5'h0, _io_out_s_T_204}; // @[package.scala:39:{76,86}] wire _io_out_s_T_234 = _io_out_s_T_231 == 2'h2; // @[package.scala:39:86] wire [31:0] _io_out_s_T_235 = _io_out_s_T_234 ? _io_out_s_T_222 : {1'h0, _io_out_s_T_233}; // @[package.scala:39:{76,86}] wire _io_out_s_T_236 = &_io_out_s_T_231; // @[package.scala:39:86] wire [31:0] _io_out_s_T_237 = _io_out_s_T_236 ? {1'h0, _io_out_s_T_230} : _io_out_s_T_235; // @[package.scala:39:{76,86}] wire [31:0] io_out_s_12_bits = _io_out_s_T_237; // @[package.scala:39:76] wire [4:0] _io_out_s_T_239 = {2'h1, _io_out_s_T_238}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rd = _io_out_s_T_239; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_241 = {2'h1, _io_out_s_T_240}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs1 = _io_out_s_T_241; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_243 = {2'h1, _io_out_s_T_242}; // @[package.scala:39:86] wire [4:0] io_out_s_12_rs2 = _io_out_s_T_243; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_12_rs3 = _io_out_s_T_244; // @[RVC.scala:20:101, :21:19] wire [9:0] _io_out_s_T_246 = {10{_io_out_s_T_245}}; // @[RVC.scala:44:{22,28}] wire _io_out_s_T_247 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_258 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_269 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire _io_out_s_T_280 = io_in_0[8]; // @[RVC.scala:44:36, :190:7] wire [1:0] _io_out_s_T_248 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_259 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_270 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire [1:0] _io_out_s_T_281 = io_in_0[10:9]; // @[RVC.scala:44:42, :190:7] wire _io_out_s_T_250 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_261 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_272 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_283 = io_in_0[7]; // @[RVC.scala:44:57, :190:7] wire _io_out_s_T_252 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_263 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_274 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire _io_out_s_T_285 = io_in_0[11]; // @[RVC.scala:44:69, :190:7] wire [2:0] _io_out_s_T_253 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_264 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_275 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [2:0] _io_out_s_T_286 = io_in_0[5:3]; // @[RVC.scala:44:76, :190:7] wire [3:0] io_out_s_lo_lo = {_io_out_s_T_253, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_5 = {_io_out_s_T_251, _io_out_s_T_252}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_23 = {io_out_s_lo_hi_5, io_out_s_lo_lo}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo = {_io_out_s_T_249, _io_out_s_T_250}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi = {_io_out_s_T_246, _io_out_s_T_247}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_18 = {io_out_s_hi_hi_hi, _io_out_s_T_248}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_29 = {io_out_s_hi_hi_18, io_out_s_hi_lo}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_254 = {io_out_s_hi_29, io_out_s_lo_23}; // @[RVC.scala:44:17] wire _io_out_s_T_255 = _io_out_s_T_254[20]; // @[RVC.scala:44:17, :94:26] wire [9:0] _io_out_s_T_257 = {10{_io_out_s_T_256}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_1 = {_io_out_s_T_264, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_6 = {_io_out_s_T_262, _io_out_s_T_263}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_24 = {io_out_s_lo_hi_6, io_out_s_lo_lo_1}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_1 = {_io_out_s_T_260, _io_out_s_T_261}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_1 = {_io_out_s_T_257, _io_out_s_T_258}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_19 = {io_out_s_hi_hi_hi_1, _io_out_s_T_259}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_30 = {io_out_s_hi_hi_19, io_out_s_hi_lo_1}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_265 = {io_out_s_hi_30, io_out_s_lo_24}; // @[RVC.scala:44:17] wire [9:0] _io_out_s_T_266 = _io_out_s_T_265[10:1]; // @[RVC.scala:44:17, :94:36] wire [9:0] _io_out_s_T_268 = {10{_io_out_s_T_267}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_2 = {_io_out_s_T_275, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_7 = {_io_out_s_T_273, _io_out_s_T_274}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_25 = {io_out_s_lo_hi_7, io_out_s_lo_lo_2}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_2 = {_io_out_s_T_271, _io_out_s_T_272}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_2 = {_io_out_s_T_268, _io_out_s_T_269}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_20 = {io_out_s_hi_hi_hi_2, _io_out_s_T_270}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_31 = {io_out_s_hi_hi_20, io_out_s_hi_lo_2}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_276 = {io_out_s_hi_31, io_out_s_lo_25}; // @[RVC.scala:44:17] wire _io_out_s_T_277 = _io_out_s_T_276[11]; // @[RVC.scala:44:17, :94:48] wire [9:0] _io_out_s_T_279 = {10{_io_out_s_T_278}}; // @[RVC.scala:44:{22,28}] wire [3:0] io_out_s_lo_lo_3 = {_io_out_s_T_286, 1'h0}; // @[RVC.scala:44:{17,76}] wire [1:0] io_out_s_lo_hi_8 = {_io_out_s_T_284, _io_out_s_T_285}; // @[RVC.scala:44:{17,63,69}] wire [5:0] io_out_s_lo_26 = {io_out_s_lo_hi_8, io_out_s_lo_lo_3}; // @[RVC.scala:44:17] wire [1:0] io_out_s_hi_lo_3 = {_io_out_s_T_282, _io_out_s_T_283}; // @[RVC.scala:44:{17,51,57}] wire [10:0] io_out_s_hi_hi_hi_3 = {_io_out_s_T_279, _io_out_s_T_280}; // @[RVC.scala:44:{17,22,36}] wire [12:0] io_out_s_hi_hi_21 = {io_out_s_hi_hi_hi_3, _io_out_s_T_281}; // @[RVC.scala:44:{17,42}] wire [14:0] io_out_s_hi_32 = {io_out_s_hi_hi_21, io_out_s_hi_lo_3}; // @[RVC.scala:44:17] wire [20:0] _io_out_s_T_287 = {io_out_s_hi_32, io_out_s_lo_26}; // @[RVC.scala:44:17] wire [7:0] _io_out_s_T_288 = _io_out_s_T_287[19:12]; // @[RVC.scala:44:17, :94:58] wire [12:0] io_out_s_lo_hi_9 = {_io_out_s_T_288, 5'h0}; // @[RVC.scala:94:{21,58}] wire [19:0] io_out_s_lo_27 = {io_out_s_lo_hi_9, 7'h6F}; // @[RVC.scala:94:21] wire [10:0] io_out_s_hi_hi_22 = {_io_out_s_T_255, _io_out_s_T_266}; // @[RVC.scala:94:{21,26,36}] wire [11:0] io_out_s_hi_33 = {io_out_s_hi_hi_22, _io_out_s_T_277}; // @[RVC.scala:94:{21,48}] wire [31:0] _io_out_s_T_289 = {io_out_s_hi_33, io_out_s_lo_27}; // @[RVC.scala:94:21] wire [31:0] io_out_s_13_bits = _io_out_s_T_289; // @[RVC.scala:21:19, :94:21] wire [4:0] _io_out_s_T_291 = {2'h1, _io_out_s_T_290}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs1 = _io_out_s_T_291; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_293 = {2'h1, _io_out_s_T_292}; // @[package.scala:39:86] wire [4:0] io_out_s_13_rs2 = _io_out_s_T_293; // @[RVC.scala:21:19, :31:17] wire [4:0] io_out_s_13_rs3 = _io_out_s_T_294; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_296 = {5{_io_out_s_T_295}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_10 = {_io_out_s_T_299, _io_out_s_T_300}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_28 = {io_out_s_lo_hi_10, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_23 = {_io_out_s_T_296, _io_out_s_T_297}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_34 = {io_out_s_hi_hi_23, _io_out_s_T_298}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_301 = {io_out_s_hi_34, io_out_s_lo_28}; // @[RVC.scala:45:17] wire _io_out_s_T_302 = _io_out_s_T_301[12]; // @[RVC.scala:45:17, :95:29] wire [4:0] _io_out_s_T_304 = {5{_io_out_s_T_303}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_11 = {_io_out_s_T_307, _io_out_s_T_308}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_29 = {io_out_s_lo_hi_11, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_24 = {_io_out_s_T_304, _io_out_s_T_305}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_35 = {io_out_s_hi_hi_24, _io_out_s_T_306}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_309 = {io_out_s_hi_35, io_out_s_lo_29}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_310 = _io_out_s_T_309[10:5]; // @[RVC.scala:45:17, :95:39] wire [4:0] _io_out_s_T_312 = {2'h1, _io_out_s_T_311}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_314 = {5{_io_out_s_T_313}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_12 = {_io_out_s_T_317, _io_out_s_T_318}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_30 = {io_out_s_lo_hi_12, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_25 = {_io_out_s_T_314, _io_out_s_T_315}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_36 = {io_out_s_hi_hi_25, _io_out_s_T_316}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_319 = {io_out_s_hi_36, io_out_s_lo_30}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_320 = _io_out_s_T_319[4:1]; // @[RVC.scala:45:17, :95:71] wire [4:0] _io_out_s_T_322 = {5{_io_out_s_T_321}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_13 = {_io_out_s_T_325, _io_out_s_T_326}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_31 = {io_out_s_lo_hi_13, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_26 = {_io_out_s_T_322, _io_out_s_T_323}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_37 = {io_out_s_hi_hi_26, _io_out_s_T_324}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_327 = {io_out_s_hi_37, io_out_s_lo_31}; // @[RVC.scala:45:17] wire _io_out_s_T_328 = _io_out_s_T_327[11]; // @[RVC.scala:45:17, :95:82] wire [7:0] io_out_s_lo_lo_4 = {_io_out_s_T_328, 7'h63}; // @[RVC.scala:95:{24,82}] wire [6:0] io_out_s_lo_hi_14 = {3'h0, _io_out_s_T_320}; // @[RVC.scala:95:{24,71}] wire [14:0] io_out_s_lo_32 = {io_out_s_lo_hi_14, io_out_s_lo_lo_4}; // @[RVC.scala:95:24] wire [9:0] io_out_s_hi_lo_4 = {5'h0, _io_out_s_T_312}; // @[RVC.scala:30:17, :95:24] wire [6:0] io_out_s_hi_hi_27 = {_io_out_s_T_302, _io_out_s_T_310}; // @[RVC.scala:95:{24,29,39}] wire [16:0] io_out_s_hi_38 = {io_out_s_hi_hi_27, io_out_s_hi_lo_4}; // @[RVC.scala:95:24] wire [31:0] _io_out_s_T_329 = {io_out_s_hi_38, io_out_s_lo_32}; // @[RVC.scala:95:24] wire [31:0] io_out_s_14_bits = _io_out_s_T_329; // @[RVC.scala:21:19, :95:24] wire [4:0] _io_out_s_T_331 = {2'h1, _io_out_s_T_330}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rd = _io_out_s_T_331; // @[RVC.scala:21:19, :30:17] wire [4:0] _io_out_s_T_333 = {2'h1, _io_out_s_T_332}; // @[package.scala:39:86] wire [4:0] io_out_s_14_rs1 = _io_out_s_T_333; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_14_rs3 = _io_out_s_T_334; // @[RVC.scala:20:101, :21:19] wire [4:0] _io_out_s_T_336 = {5{_io_out_s_T_335}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_15 = {_io_out_s_T_339, _io_out_s_T_340}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_33 = {io_out_s_lo_hi_15, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_28 = {_io_out_s_T_336, _io_out_s_T_337}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_39 = {io_out_s_hi_hi_28, _io_out_s_T_338}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_341 = {io_out_s_hi_39, io_out_s_lo_33}; // @[RVC.scala:45:17] wire _io_out_s_T_342 = _io_out_s_T_341[12]; // @[RVC.scala:45:17, :96:29] wire [4:0] _io_out_s_T_344 = {5{_io_out_s_T_343}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_16 = {_io_out_s_T_347, _io_out_s_T_348}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_34 = {io_out_s_lo_hi_16, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_29 = {_io_out_s_T_344, _io_out_s_T_345}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_40 = {io_out_s_hi_hi_29, _io_out_s_T_346}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_349 = {io_out_s_hi_40, io_out_s_lo_34}; // @[RVC.scala:45:17] wire [5:0] _io_out_s_T_350 = _io_out_s_T_349[10:5]; // @[RVC.scala:45:17, :96:39] wire [4:0] _io_out_s_T_352 = {2'h1, _io_out_s_T_351}; // @[package.scala:39:86] wire [4:0] _io_out_s_T_354 = {5{_io_out_s_T_353}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_17 = {_io_out_s_T_357, _io_out_s_T_358}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_35 = {io_out_s_lo_hi_17, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_30 = {_io_out_s_T_354, _io_out_s_T_355}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_41 = {io_out_s_hi_hi_30, _io_out_s_T_356}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_359 = {io_out_s_hi_41, io_out_s_lo_35}; // @[RVC.scala:45:17] wire [3:0] _io_out_s_T_360 = _io_out_s_T_359[4:1]; // @[RVC.scala:45:17, :96:71] wire [4:0] _io_out_s_T_362 = {5{_io_out_s_T_361}}; // @[RVC.scala:45:{22,27}] wire [3:0] io_out_s_lo_hi_18 = {_io_out_s_T_365, _io_out_s_T_366}; // @[RVC.scala:45:{17,49,59}] wire [4:0] io_out_s_lo_36 = {io_out_s_lo_hi_18, 1'h0}; // @[RVC.scala:45:17] wire [6:0] io_out_s_hi_hi_31 = {_io_out_s_T_362, _io_out_s_T_363}; // @[RVC.scala:45:{17,22,35}] wire [7:0] io_out_s_hi_42 = {io_out_s_hi_hi_31, _io_out_s_T_364}; // @[RVC.scala:45:{17,43}] wire [12:0] _io_out_s_T_367 = {io_out_s_hi_42, io_out_s_lo_36}; // @[RVC.scala:45:17] wire _io_out_s_T_368 = _io_out_s_T_367[11]; // @[RVC.scala:45:17, :96:82] wire [7:0] io_out_s_lo_lo_5 = {_io_out_s_T_368, 7'h63}; // @[RVC.scala:96:{24,82}] wire [6:0] io_out_s_lo_hi_19 = {3'h1, _io_out_s_T_360}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_37 = {io_out_s_lo_hi_19, io_out_s_lo_lo_5}; // @[RVC.scala:96:24] wire [9:0] io_out_s_hi_lo_5 = {5'h0, _io_out_s_T_352}; // @[RVC.scala:30:17, :96:24] wire [6:0] io_out_s_hi_hi_32 = {_io_out_s_T_342, _io_out_s_T_350}; // @[RVC.scala:96:{24,29,39}] wire [16:0] io_out_s_hi_43 = {io_out_s_hi_hi_32, io_out_s_hi_lo_5}; // @[RVC.scala:96:24] wire [31:0] _io_out_s_T_369 = {io_out_s_hi_43, io_out_s_lo_37}; // @[RVC.scala:96:24] wire [31:0] io_out_s_15_bits = _io_out_s_T_369; // @[RVC.scala:21:19, :96:24] wire [4:0] _io_out_s_T_371 = {2'h1, _io_out_s_T_370}; // @[package.scala:39:86] wire [4:0] io_out_s_15_rs1 = _io_out_s_T_371; // @[RVC.scala:21:19, :30:17] wire [4:0] io_out_s_15_rs3 = _io_out_s_T_372; // @[RVC.scala:20:101, :21:19] wire _io_out_s_load_opc_T_1 = |_io_out_s_load_opc_T; // @[RVC.scala:33:13, :113:27] wire [6:0] io_out_s_load_opc = _io_out_s_load_opc_T_1 ? 7'h3 : 7'h1F; // @[RVC.scala:113:{23,27}] wire [5:0] _io_out_s_T_375 = {_io_out_s_T_373, _io_out_s_T_374}; // @[RVC.scala:46:{18,20,27}] wire [11:0] io_out_s_lo_38 = {_io_out_s_T_377, 7'h13}; // @[RVC.scala:33:13, :114:24] wire [10:0] io_out_s_hi_hi_33 = {_io_out_s_T_375, _io_out_s_T_376}; // @[RVC.scala:33:13, :46:18, :114:24] wire [13:0] io_out_s_hi_44 = {io_out_s_hi_hi_33, 3'h1}; // @[package.scala:39:86] wire [25:0] _io_out_s_T_378 = {io_out_s_hi_44, io_out_s_lo_38}; // @[RVC.scala:114:24] wire [4:0] io_out_s_16_rd = _io_out_s_T_379; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs1 = _io_out_s_T_380; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_16_rs2 = _io_out_s_T_381; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_16_rs3 = _io_out_s_T_382; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_16_bits; // @[RVC.scala:21:19] assign io_out_s_16_bits = {6'h0, _io_out_s_T_378}; // @[RVC.scala:21:19, :22:14, :105:43, :114:24] wire [4:0] io_out_s_lo_39 = {_io_out_s_T_385, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_45 = {_io_out_s_T_383, _io_out_s_T_384}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_386 = {io_out_s_hi_45, io_out_s_lo_39}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_40 = {_io_out_s_T_387, 7'h7}; // @[RVC.scala:33:13, :117:25] wire [13:0] io_out_s_hi_hi_34 = {_io_out_s_T_386, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_46 = {io_out_s_hi_hi_34, 3'h3}; // @[RVC.scala:117:25] wire [28:0] _io_out_s_T_388 = {io_out_s_hi_46, io_out_s_lo_40}; // @[RVC.scala:117:25] wire [4:0] io_out_s_17_rd = _io_out_s_T_389; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_17_rs2 = _io_out_s_T_390; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_17_rs3 = _io_out_s_T_391; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_17_bits; // @[RVC.scala:21:19] assign io_out_s_17_bits = {3'h0, _io_out_s_T_388}; // @[RVC.scala:21:19, :22:14, :117:25] wire [1:0] _io_out_s_T_392 = io_in_0[3:2]; // @[RVC.scala:37:22, :190:7] wire [2:0] _io_out_s_T_394 = io_in_0[6:4]; // @[RVC.scala:37:37, :190:7] wire [4:0] io_out_s_lo_41 = {_io_out_s_T_394, 2'h0}; // @[RVC.scala:37:{20,37}] wire [2:0] io_out_s_hi_47 = {_io_out_s_T_392, _io_out_s_T_393}; // @[RVC.scala:37:{20,22,30}] wire [7:0] _io_out_s_T_395 = {io_out_s_hi_47, io_out_s_lo_41}; // @[RVC.scala:37:20] wire [11:0] io_out_s_lo_42 = {_io_out_s_T_396, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :116:24] wire [12:0] io_out_s_hi_hi_35 = {_io_out_s_T_395, 5'h2}; // @[package.scala:39:86] wire [15:0] io_out_s_hi_48 = {io_out_s_hi_hi_35, 3'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_397 = {io_out_s_hi_48, io_out_s_lo_42}; // @[RVC.scala:116:24] wire [4:0] io_out_s_18_rd = _io_out_s_T_398; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_18_rs2 = _io_out_s_T_399; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_18_rs3 = _io_out_s_T_400; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_18_bits; // @[RVC.scala:21:19] assign io_out_s_18_bits = {4'h0, _io_out_s_T_397}; // @[RVC.scala:21:19, :22:14, :116:24] wire [4:0] io_out_s_lo_43 = {_io_out_s_T_403, 3'h0}; // @[RVC.scala:38:{20,37}] wire [3:0] io_out_s_hi_49 = {_io_out_s_T_401, _io_out_s_T_402}; // @[RVC.scala:38:{20,22,30}] wire [8:0] _io_out_s_T_404 = {io_out_s_hi_49, io_out_s_lo_43}; // @[RVC.scala:38:20] wire [11:0] io_out_s_lo_44 = {_io_out_s_T_405, io_out_s_load_opc}; // @[RVC.scala:33:13, :113:23, :115:24] wire [13:0] io_out_s_hi_hi_36 = {_io_out_s_T_404, 5'h2}; // @[package.scala:39:86] wire [16:0] io_out_s_hi_50 = {io_out_s_hi_hi_36, 3'h3}; // @[RVC.scala:115:24] wire [28:0] _io_out_s_T_406 = {io_out_s_hi_50, io_out_s_lo_44}; // @[RVC.scala:115:24] wire [4:0] io_out_s_19_rd = _io_out_s_T_407; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_19_rs2 = _io_out_s_T_408; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_19_rs3 = _io_out_s_T_409; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_19_bits; // @[RVC.scala:21:19] assign io_out_s_19_bits = {3'h0, _io_out_s_T_406}; // @[RVC.scala:21:19, :22:14, :115:24] wire [11:0] io_out_s_mv_lo = {_io_out_s_mv_T_1, 7'h33}; // @[RVC.scala:33:13, :132:22] wire [9:0] io_out_s_mv_hi_hi = {_io_out_s_mv_T, 5'h0}; // @[RVC.scala:32:14, :132:22] wire [12:0] io_out_s_mv_hi = {io_out_s_mv_hi_hi, 3'h0}; // @[RVC.scala:132:22] wire [24:0] _io_out_s_mv_T_2 = {io_out_s_mv_hi, io_out_s_mv_lo}; // @[RVC.scala:132:22] wire [4:0] io_out_s_mv_rd = _io_out_s_mv_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_mv_rs2 = _io_out_s_mv_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_mv_rs3 = _io_out_s_mv_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_mv_bits; // @[RVC.scala:21:19] assign io_out_s_mv_bits = {7'h0, _io_out_s_mv_T_2}; // @[RVC.scala:21:19, :22:14, :132:22] wire [11:0] io_out_s_add_lo = {_io_out_s_add_T_2, 7'h33}; // @[RVC.scala:33:13, :134:25] wire [9:0] io_out_s_add_hi_hi = {_io_out_s_add_T, _io_out_s_add_T_1}; // @[RVC.scala:32:14, :33:13, :134:25] wire [12:0] io_out_s_add_hi = {io_out_s_add_hi_hi, 3'h0}; // @[RVC.scala:134:25] wire [24:0] _io_out_s_add_T_3 = {io_out_s_add_hi, io_out_s_add_lo}; // @[RVC.scala:134:25] wire [4:0] io_out_s_add_rd = _io_out_s_add_T_4; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs1 = _io_out_s_add_T_5; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_add_rs2 = _io_out_s_add_T_6; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_add_rs3 = _io_out_s_add_T_7; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_add_bits; // @[RVC.scala:21:19] assign io_out_s_add_bits = {7'h0, _io_out_s_add_T_3}; // @[RVC.scala:21:19, :22:14, :134:25] wire [9:0] io_out_s_jr_hi_hi = {_io_out_s_jr_T, _io_out_s_jr_T_1}; // @[RVC.scala:32:14, :33:13, :135:19] wire [12:0] io_out_s_jr_hi = {io_out_s_jr_hi_hi, 3'h0}; // @[RVC.scala:135:19] wire [24:0] io_out_s_jr = {io_out_s_jr_hi, 12'h67}; // @[RVC.scala:135:19] wire [17:0] _io_out_s_reserved_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29] wire [17:0] _io_out_s_ebreak_T = io_out_s_jr[24:7]; // @[RVC.scala:135:19, :136:29, :140:27] wire [24:0] io_out_s_reserved = {_io_out_s_reserved_T, 7'h1F}; // @[RVC.scala:136:{25,29}] wire _io_out_s_jr_reserved_T_1 = |_io_out_s_jr_reserved_T; // @[RVC.scala:33:13, :137:37] wire [24:0] _io_out_s_jr_reserved_T_2 = _io_out_s_jr_reserved_T_1 ? io_out_s_jr : io_out_s_reserved; // @[RVC.scala:135:19, :136:25, :137:{33,37}] wire [4:0] io_out_s_jr_reserved_rs1 = _io_out_s_jr_reserved_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jr_reserved_rs2 = _io_out_s_jr_reserved_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jr_reserved_rs3 = _io_out_s_jr_reserved_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jr_reserved_bits; // @[RVC.scala:21:19] assign io_out_s_jr_reserved_bits = {7'h0, _io_out_s_jr_reserved_T_2}; // @[RVC.scala:21:19, :22:14, :137:33] wire _io_out_s_jr_mv_T_1 = |_io_out_s_jr_mv_T; // @[RVC.scala:32:14, :138:27] wire [31:0] io_out_s_jr_mv_bits = _io_out_s_jr_mv_T_1 ? io_out_s_mv_bits : io_out_s_jr_reserved_bits; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rd = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rd : 5'h0; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs1 = _io_out_s_jr_mv_T_1 ? 5'h0 : io_out_s_jr_reserved_rs1; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs2 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs2 : io_out_s_jr_reserved_rs2; // @[RVC.scala:21:19, :138:{22,27}] wire [4:0] io_out_s_jr_mv_rs3 = _io_out_s_jr_mv_T_1 ? io_out_s_mv_rs3 : io_out_s_jr_reserved_rs3; // @[RVC.scala:21:19, :138:{22,27}] wire [9:0] io_out_s_jalr_hi_hi = {_io_out_s_jalr_T, _io_out_s_jalr_T_1}; // @[RVC.scala:32:14, :33:13, :139:21] wire [12:0] io_out_s_jalr_hi = {io_out_s_jalr_hi_hi, 3'h0}; // @[RVC.scala:139:21] wire [24:0] io_out_s_jalr = {io_out_s_jalr_hi, 12'hE7}; // @[RVC.scala:139:21] wire [24:0] _io_out_s_ebreak_T_1 = {_io_out_s_ebreak_T, 7'h73}; // @[RVC.scala:140:{23,27}] wire [24:0] io_out_s_ebreak = {_io_out_s_ebreak_T_1[24:21], _io_out_s_ebreak_T_1[20:0] | 21'h100000}; // @[RVC.scala:140:{23,46}] wire _io_out_s_jalr_ebreak_T_1 = |_io_out_s_jalr_ebreak_T; // @[RVC.scala:33:13, :141:37] wire [24:0] _io_out_s_jalr_ebreak_T_2 = _io_out_s_jalr_ebreak_T_1 ? io_out_s_jalr : io_out_s_ebreak; // @[RVC.scala:139:21, :140:46, :141:{33,37}] wire [4:0] io_out_s_jalr_ebreak_rs1 = _io_out_s_jalr_ebreak_T_3; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_jalr_ebreak_rs2 = _io_out_s_jalr_ebreak_T_4; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_jalr_ebreak_rs3 = _io_out_s_jalr_ebreak_T_5; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19] assign io_out_s_jalr_ebreak_bits = {7'h0, _io_out_s_jalr_ebreak_T_2}; // @[RVC.scala:21:19, :22:14, :141:33] wire _io_out_s_jalr_add_T_1 = |_io_out_s_jalr_add_T; // @[RVC.scala:32:14, :142:30] wire [31:0] io_out_s_jalr_add_bits = _io_out_s_jalr_add_T_1 ? io_out_s_add_bits : io_out_s_jalr_ebreak_bits; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rd = _io_out_s_jalr_add_T_1 ? io_out_s_add_rd : 5'h1; // @[package.scala:39:86] wire [4:0] io_out_s_jalr_add_rs1 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs1 : io_out_s_jalr_ebreak_rs1; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs2 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs2 : io_out_s_jalr_ebreak_rs2; // @[RVC.scala:21:19, :142:{25,30}] wire [4:0] io_out_s_jalr_add_rs3 = _io_out_s_jalr_add_T_1 ? io_out_s_add_rs3 : io_out_s_jalr_ebreak_rs3; // @[RVC.scala:21:19, :142:{25,30}] wire [31:0] io_out_s_20_bits = _io_out_s_T_410 ? io_out_s_jalr_add_bits : io_out_s_jr_mv_bits; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rd = _io_out_s_T_410 ? io_out_s_jalr_add_rd : io_out_s_jr_mv_rd; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs1 = _io_out_s_T_410 ? io_out_s_jalr_add_rs1 : io_out_s_jr_mv_rs1; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs2 = _io_out_s_T_410 ? io_out_s_jalr_add_rs2 : io_out_s_jr_mv_rs2; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [4:0] io_out_s_20_rs3 = _io_out_s_T_410 ? io_out_s_jalr_add_rs3 : io_out_s_jr_mv_rs3; // @[RVC.scala:138:22, :142:25, :143:{10,12}] wire [5:0] io_out_s_hi_51 = {_io_out_s_T_411, _io_out_s_T_412}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_413 = {io_out_s_hi_51, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_414 = _io_out_s_T_413[8:5]; // @[RVC.scala:40:20, :124:34] wire [5:0] io_out_s_hi_52 = {_io_out_s_T_416, _io_out_s_T_417}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_418 = {io_out_s_hi_52, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_419 = _io_out_s_T_418[4:0]; // @[RVC.scala:40:20, :124:66] wire [7:0] io_out_s_lo_hi_20 = {3'h3, _io_out_s_T_419}; // @[RVC.scala:124:{25,66}] wire [14:0] io_out_s_lo_45 = {io_out_s_lo_hi_20, 7'h27}; // @[RVC.scala:124:25] wire [8:0] io_out_s_hi_hi_37 = {_io_out_s_T_414, _io_out_s_T_415}; // @[RVC.scala:32:14, :124:{25,34}] wire [13:0] io_out_s_hi_53 = {io_out_s_hi_hi_37, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_420 = {io_out_s_hi_53, io_out_s_lo_45}; // @[RVC.scala:124:25] wire [4:0] io_out_s_21_rd = _io_out_s_T_421; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_21_rs2 = _io_out_s_T_422; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_21_rs3 = _io_out_s_T_423; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_21_bits; // @[RVC.scala:21:19] assign io_out_s_21_bits = {3'h0, _io_out_s_T_420}; // @[RVC.scala:21:19, :22:14, :124:25] wire [1:0] _io_out_s_T_424 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [1:0] _io_out_s_T_429 = io_in_0[8:7]; // @[RVC.scala:39:22, :190:7] wire [3:0] _io_out_s_T_425 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [3:0] _io_out_s_T_430 = io_in_0[12:9]; // @[RVC.scala:39:30, :190:7] wire [5:0] io_out_s_hi_54 = {_io_out_s_T_424, _io_out_s_T_425}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_426 = {io_out_s_hi_54, 2'h0}; // @[RVC.scala:39:20] wire [2:0] _io_out_s_T_427 = _io_out_s_T_426[7:5]; // @[RVC.scala:39:20, :123:33] wire [5:0] io_out_s_hi_55 = {_io_out_s_T_429, _io_out_s_T_430}; // @[RVC.scala:39:{20,22,30}] wire [7:0] _io_out_s_T_431 = {io_out_s_hi_55, 2'h0}; // @[RVC.scala:39:20] wire [4:0] _io_out_s_T_432 = _io_out_s_T_431[4:0]; // @[RVC.scala:39:20, :123:65] wire [7:0] io_out_s_lo_hi_21 = {3'h2, _io_out_s_T_432}; // @[package.scala:39:86] wire [14:0] io_out_s_lo_46 = {io_out_s_lo_hi_21, 7'h23}; // @[RVC.scala:123:24] wire [7:0] io_out_s_hi_hi_38 = {_io_out_s_T_427, _io_out_s_T_428}; // @[RVC.scala:32:14, :123:{24,33}] wire [12:0] io_out_s_hi_56 = {io_out_s_hi_hi_38, 5'h2}; // @[package.scala:39:86] wire [27:0] _io_out_s_T_433 = {io_out_s_hi_56, io_out_s_lo_46}; // @[RVC.scala:123:24] wire [4:0] io_out_s_22_rd = _io_out_s_T_434; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_22_rs2 = _io_out_s_T_435; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_22_rs3 = _io_out_s_T_436; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_22_bits; // @[RVC.scala:21:19] assign io_out_s_22_bits = {4'h0, _io_out_s_T_433}; // @[RVC.scala:21:19, :22:14, :123:24] wire [5:0] io_out_s_hi_57 = {_io_out_s_T_437, _io_out_s_T_438}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_439 = {io_out_s_hi_57, 3'h0}; // @[RVC.scala:40:20] wire [3:0] _io_out_s_T_440 = _io_out_s_T_439[8:5]; // @[RVC.scala:40:20, :122:33] wire [5:0] io_out_s_hi_58 = {_io_out_s_T_442, _io_out_s_T_443}; // @[RVC.scala:40:{20,22,30}] wire [8:0] _io_out_s_T_444 = {io_out_s_hi_58, 3'h0}; // @[RVC.scala:40:20] wire [4:0] _io_out_s_T_445 = _io_out_s_T_444[4:0]; // @[RVC.scala:40:20, :122:65] wire [7:0] io_out_s_lo_hi_22 = {3'h3, _io_out_s_T_445}; // @[RVC.scala:122:{24,65}] wire [14:0] io_out_s_lo_47 = {io_out_s_lo_hi_22, 7'h23}; // @[RVC.scala:122:24] wire [8:0] io_out_s_hi_hi_39 = {_io_out_s_T_440, _io_out_s_T_441}; // @[RVC.scala:32:14, :122:{24,33}] wire [13:0] io_out_s_hi_59 = {io_out_s_hi_hi_39, 5'h2}; // @[package.scala:39:86] wire [28:0] _io_out_s_T_446 = {io_out_s_hi_59, io_out_s_lo_47}; // @[RVC.scala:122:24] wire [4:0] io_out_s_23_rd = _io_out_s_T_447; // @[RVC.scala:21:19, :33:13] wire [4:0] io_out_s_23_rs2 = _io_out_s_T_448; // @[RVC.scala:21:19, :32:14] wire [4:0] io_out_s_23_rs3 = _io_out_s_T_449; // @[RVC.scala:20:101, :21:19] wire [31:0] io_out_s_23_bits; // @[RVC.scala:21:19] assign io_out_s_23_bits = {3'h0, _io_out_s_T_446}; // @[RVC.scala:21:19, :22:14, :122:24] wire [4:0] io_out_s_24_rd = _io_out_s_T_450; // @[RVC.scala:20:36, :21:19] wire [4:0] _io_out_s_T_451 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_455 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_459 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_463 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_467 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_471 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_475 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] _io_out_s_T_479 = io_in_0[19:15]; // @[RVC.scala:20:57, :190:7] wire [4:0] io_out_s_24_rs1 = _io_out_s_T_451; // @[RVC.scala:20:57, :21:19] wire [4:0] _io_out_s_T_452 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_456 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_460 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_464 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_468 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_472 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_476 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] _io_out_s_T_480 = io_in_0[24:20]; // @[RVC.scala:20:79, :190:7] wire [4:0] io_out_s_24_rs2 = _io_out_s_T_452; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_24_rs3 = _io_out_s_T_453; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_25_rd = _io_out_s_T_454; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_25_rs1 = _io_out_s_T_455; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_25_rs2 = _io_out_s_T_456; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_25_rs3 = _io_out_s_T_457; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_26_rd = _io_out_s_T_458; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_26_rs1 = _io_out_s_T_459; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_26_rs2 = _io_out_s_T_460; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_26_rs3 = _io_out_s_T_461; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_27_rd = _io_out_s_T_462; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_27_rs1 = _io_out_s_T_463; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_27_rs2 = _io_out_s_T_464; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_27_rs3 = _io_out_s_T_465; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_28_rd = _io_out_s_T_466; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_28_rs1 = _io_out_s_T_467; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_28_rs2 = _io_out_s_T_468; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_28_rs3 = _io_out_s_T_469; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_29_rd = _io_out_s_T_470; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_29_rs1 = _io_out_s_T_471; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_29_rs2 = _io_out_s_T_472; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_29_rs3 = _io_out_s_T_473; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_30_rd = _io_out_s_T_474; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_30_rs1 = _io_out_s_T_475; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_30_rs2 = _io_out_s_T_476; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_30_rs3 = _io_out_s_T_477; // @[RVC.scala:20:101, :21:19] wire [4:0] io_out_s_31_rd = _io_out_s_T_478; // @[RVC.scala:20:36, :21:19] wire [4:0] io_out_s_31_rs1 = _io_out_s_T_479; // @[RVC.scala:20:57, :21:19] wire [4:0] io_out_s_31_rs2 = _io_out_s_T_480; // @[RVC.scala:20:79, :21:19] wire [4:0] io_out_s_31_rs3 = _io_out_s_T_481; // @[RVC.scala:20:101, :21:19] wire [2:0] _io_out_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :190:7] wire [2:0] _io_ill_T_1 = io_in_0[15:13]; // @[RVC.scala:154:20, :186:20, :190:7] wire [4:0] _io_out_T_2 = {_io_out_T, _io_out_T_1}; // @[RVC.scala:154:{10,12,20}] wire _io_out_T_3 = _io_out_T_2 == 5'h1; // @[package.scala:39:86] wire [31:0] _io_out_T_4_bits = _io_out_T_3 ? io_out_s_1_bits : io_out_s_0_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rd = _io_out_T_3 ? io_out_s_1_rd : io_out_s_0_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs1 = _io_out_T_3 ? io_out_s_1_rs1 : 5'h2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs2 = _io_out_T_3 ? io_out_s_1_rs2 : io_out_s_0_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_4_rs3 = _io_out_T_3 ? io_out_s_1_rs3 : io_out_s_0_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_5 = _io_out_T_2 == 5'h2; // @[package.scala:39:86] wire [31:0] _io_out_T_6_bits = _io_out_T_5 ? io_out_s_2_bits : _io_out_T_4_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rd = _io_out_T_5 ? io_out_s_2_rd : _io_out_T_4_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs1 = _io_out_T_5 ? io_out_s_2_rs1 : _io_out_T_4_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs2 = _io_out_T_5 ? io_out_s_2_rs2 : _io_out_T_4_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_6_rs3 = _io_out_T_5 ? io_out_s_2_rs3 : _io_out_T_4_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_7 = _io_out_T_2 == 5'h3; // @[package.scala:39:86] wire [31:0] _io_out_T_8_bits = _io_out_T_7 ? io_out_s_3_bits : _io_out_T_6_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rd = _io_out_T_7 ? io_out_s_3_rd : _io_out_T_6_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs1 = _io_out_T_7 ? io_out_s_3_rs1 : _io_out_T_6_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs2 = _io_out_T_7 ? io_out_s_3_rs2 : _io_out_T_6_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_8_rs3 = _io_out_T_7 ? io_out_s_3_rs3 : _io_out_T_6_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_9 = _io_out_T_2 == 5'h4; // @[package.scala:39:86] wire [31:0] _io_out_T_10_bits = _io_out_T_9 ? io_out_s_4_bits : _io_out_T_8_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rd = _io_out_T_9 ? io_out_s_4_rd : _io_out_T_8_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs1 = _io_out_T_9 ? io_out_s_4_rs1 : _io_out_T_8_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs2 = _io_out_T_9 ? io_out_s_4_rs2 : _io_out_T_8_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_10_rs3 = _io_out_T_9 ? io_out_s_4_rs3 : _io_out_T_8_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_11 = _io_out_T_2 == 5'h5; // @[package.scala:39:86] wire [31:0] _io_out_T_12_bits = _io_out_T_11 ? io_out_s_5_bits : _io_out_T_10_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rd = _io_out_T_11 ? io_out_s_5_rd : _io_out_T_10_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs1 = _io_out_T_11 ? io_out_s_5_rs1 : _io_out_T_10_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs2 = _io_out_T_11 ? io_out_s_5_rs2 : _io_out_T_10_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_12_rs3 = _io_out_T_11 ? io_out_s_5_rs3 : _io_out_T_10_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_13 = _io_out_T_2 == 5'h6; // @[package.scala:39:86] wire [31:0] _io_out_T_14_bits = _io_out_T_13 ? io_out_s_6_bits : _io_out_T_12_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rd = _io_out_T_13 ? io_out_s_6_rd : _io_out_T_12_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs1 = _io_out_T_13 ? io_out_s_6_rs1 : _io_out_T_12_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs2 = _io_out_T_13 ? io_out_s_6_rs2 : _io_out_T_12_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_14_rs3 = _io_out_T_13 ? io_out_s_6_rs3 : _io_out_T_12_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_15 = _io_out_T_2 == 5'h7; // @[package.scala:39:86] wire [31:0] _io_out_T_16_bits = _io_out_T_15 ? io_out_s_7_bits : _io_out_T_14_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rd = _io_out_T_15 ? io_out_s_7_rd : _io_out_T_14_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs1 = _io_out_T_15 ? io_out_s_7_rs1 : _io_out_T_14_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs2 = _io_out_T_15 ? io_out_s_7_rs2 : _io_out_T_14_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_16_rs3 = _io_out_T_15 ? io_out_s_7_rs3 : _io_out_T_14_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_17 = _io_out_T_2 == 5'h8; // @[package.scala:39:86] wire [31:0] _io_out_T_18_bits = _io_out_T_17 ? io_out_s_8_bits : _io_out_T_16_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rd = _io_out_T_17 ? io_out_s_8_rd : _io_out_T_16_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs1 = _io_out_T_17 ? io_out_s_8_rs1 : _io_out_T_16_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs2 = _io_out_T_17 ? io_out_s_8_rs2 : _io_out_T_16_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_18_rs3 = _io_out_T_17 ? io_out_s_8_rs3 : _io_out_T_16_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_19 = _io_out_T_2 == 5'h9; // @[package.scala:39:86] wire [31:0] _io_out_T_20_bits = _io_out_T_19 ? io_out_s_9_bits : _io_out_T_18_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rd = _io_out_T_19 ? io_out_s_9_rd : _io_out_T_18_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs1 = _io_out_T_19 ? io_out_s_9_rs1 : _io_out_T_18_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs2 = _io_out_T_19 ? io_out_s_9_rs2 : _io_out_T_18_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_20_rs3 = _io_out_T_19 ? io_out_s_9_rs3 : _io_out_T_18_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_21 = _io_out_T_2 == 5'hA; // @[package.scala:39:86] wire [31:0] _io_out_T_22_bits = _io_out_T_21 ? io_out_s_10_bits : _io_out_T_20_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rd = _io_out_T_21 ? io_out_s_10_rd : _io_out_T_20_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs1 = _io_out_T_21 ? 5'h0 : _io_out_T_20_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs2 = _io_out_T_21 ? io_out_s_10_rs2 : _io_out_T_20_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_22_rs3 = _io_out_T_21 ? io_out_s_10_rs3 : _io_out_T_20_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_23 = _io_out_T_2 == 5'hB; // @[package.scala:39:86] wire [31:0] _io_out_T_24_bits = _io_out_T_23 ? io_out_s_11_bits : _io_out_T_22_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rd = _io_out_T_23 ? io_out_s_11_rd : _io_out_T_22_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs1 = _io_out_T_23 ? io_out_s_11_rs1 : _io_out_T_22_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs2 = _io_out_T_23 ? io_out_s_11_rs2 : _io_out_T_22_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_24_rs3 = _io_out_T_23 ? io_out_s_11_rs3 : _io_out_T_22_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_25 = _io_out_T_2 == 5'hC; // @[package.scala:39:86] wire [31:0] _io_out_T_26_bits = _io_out_T_25 ? io_out_s_12_bits : _io_out_T_24_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rd = _io_out_T_25 ? io_out_s_12_rd : _io_out_T_24_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs1 = _io_out_T_25 ? io_out_s_12_rs1 : _io_out_T_24_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs2 = _io_out_T_25 ? io_out_s_12_rs2 : _io_out_T_24_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_26_rs3 = _io_out_T_25 ? io_out_s_12_rs3 : _io_out_T_24_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_27 = _io_out_T_2 == 5'hD; // @[package.scala:39:86] wire [31:0] _io_out_T_28_bits = _io_out_T_27 ? io_out_s_13_bits : _io_out_T_26_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rd = _io_out_T_27 ? 5'h0 : _io_out_T_26_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs1 = _io_out_T_27 ? io_out_s_13_rs1 : _io_out_T_26_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs2 = _io_out_T_27 ? io_out_s_13_rs2 : _io_out_T_26_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_28_rs3 = _io_out_T_27 ? io_out_s_13_rs3 : _io_out_T_26_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_29 = _io_out_T_2 == 5'hE; // @[package.scala:39:86] wire [31:0] _io_out_T_30_bits = _io_out_T_29 ? io_out_s_14_bits : _io_out_T_28_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rd = _io_out_T_29 ? io_out_s_14_rd : _io_out_T_28_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs1 = _io_out_T_29 ? io_out_s_14_rs1 : _io_out_T_28_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs2 = _io_out_T_29 ? 5'h0 : _io_out_T_28_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_30_rs3 = _io_out_T_29 ? io_out_s_14_rs3 : _io_out_T_28_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_31 = _io_out_T_2 == 5'hF; // @[package.scala:39:86] wire [31:0] _io_out_T_32_bits = _io_out_T_31 ? io_out_s_15_bits : _io_out_T_30_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rd = _io_out_T_31 ? 5'h0 : _io_out_T_30_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs1 = _io_out_T_31 ? io_out_s_15_rs1 : _io_out_T_30_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs2 = _io_out_T_31 ? 5'h0 : _io_out_T_30_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_32_rs3 = _io_out_T_31 ? io_out_s_15_rs3 : _io_out_T_30_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_33 = _io_out_T_2 == 5'h10; // @[package.scala:39:86] wire [31:0] _io_out_T_34_bits = _io_out_T_33 ? io_out_s_16_bits : _io_out_T_32_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rd = _io_out_T_33 ? io_out_s_16_rd : _io_out_T_32_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs1 = _io_out_T_33 ? io_out_s_16_rs1 : _io_out_T_32_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs2 = _io_out_T_33 ? io_out_s_16_rs2 : _io_out_T_32_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_34_rs3 = _io_out_T_33 ? io_out_s_16_rs3 : _io_out_T_32_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_35 = _io_out_T_2 == 5'h11; // @[package.scala:39:86] wire [31:0] _io_out_T_36_bits = _io_out_T_35 ? io_out_s_17_bits : _io_out_T_34_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rd = _io_out_T_35 ? io_out_s_17_rd : _io_out_T_34_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs1 = _io_out_T_35 ? 5'h2 : _io_out_T_34_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs2 = _io_out_T_35 ? io_out_s_17_rs2 : _io_out_T_34_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_36_rs3 = _io_out_T_35 ? io_out_s_17_rs3 : _io_out_T_34_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_37 = _io_out_T_2 == 5'h12; // @[package.scala:39:86] wire [31:0] _io_out_T_38_bits = _io_out_T_37 ? io_out_s_18_bits : _io_out_T_36_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rd = _io_out_T_37 ? io_out_s_18_rd : _io_out_T_36_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs1 = _io_out_T_37 ? 5'h2 : _io_out_T_36_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs2 = _io_out_T_37 ? io_out_s_18_rs2 : _io_out_T_36_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_38_rs3 = _io_out_T_37 ? io_out_s_18_rs3 : _io_out_T_36_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_39 = _io_out_T_2 == 5'h13; // @[package.scala:39:86] wire [31:0] _io_out_T_40_bits = _io_out_T_39 ? io_out_s_19_bits : _io_out_T_38_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rd = _io_out_T_39 ? io_out_s_19_rd : _io_out_T_38_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs1 = _io_out_T_39 ? 5'h2 : _io_out_T_38_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs2 = _io_out_T_39 ? io_out_s_19_rs2 : _io_out_T_38_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_40_rs3 = _io_out_T_39 ? io_out_s_19_rs3 : _io_out_T_38_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_41 = _io_out_T_2 == 5'h14; // @[package.scala:39:86] wire [31:0] _io_out_T_42_bits = _io_out_T_41 ? io_out_s_20_bits : _io_out_T_40_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rd = _io_out_T_41 ? io_out_s_20_rd : _io_out_T_40_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs1 = _io_out_T_41 ? io_out_s_20_rs1 : _io_out_T_40_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs2 = _io_out_T_41 ? io_out_s_20_rs2 : _io_out_T_40_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_42_rs3 = _io_out_T_41 ? io_out_s_20_rs3 : _io_out_T_40_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_43 = _io_out_T_2 == 5'h15; // @[package.scala:39:86] wire [31:0] _io_out_T_44_bits = _io_out_T_43 ? io_out_s_21_bits : _io_out_T_42_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rd = _io_out_T_43 ? io_out_s_21_rd : _io_out_T_42_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs1 = _io_out_T_43 ? 5'h2 : _io_out_T_42_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs2 = _io_out_T_43 ? io_out_s_21_rs2 : _io_out_T_42_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_44_rs3 = _io_out_T_43 ? io_out_s_21_rs3 : _io_out_T_42_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_45 = _io_out_T_2 == 5'h16; // @[package.scala:39:86] wire [31:0] _io_out_T_46_bits = _io_out_T_45 ? io_out_s_22_bits : _io_out_T_44_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rd = _io_out_T_45 ? io_out_s_22_rd : _io_out_T_44_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs1 = _io_out_T_45 ? 5'h2 : _io_out_T_44_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs2 = _io_out_T_45 ? io_out_s_22_rs2 : _io_out_T_44_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_46_rs3 = _io_out_T_45 ? io_out_s_22_rs3 : _io_out_T_44_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_47 = _io_out_T_2 == 5'h17; // @[package.scala:39:86] wire [31:0] _io_out_T_48_bits = _io_out_T_47 ? io_out_s_23_bits : _io_out_T_46_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rd = _io_out_T_47 ? io_out_s_23_rd : _io_out_T_46_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs1 = _io_out_T_47 ? 5'h2 : _io_out_T_46_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs2 = _io_out_T_47 ? io_out_s_23_rs2 : _io_out_T_46_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_48_rs3 = _io_out_T_47 ? io_out_s_23_rs3 : _io_out_T_46_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_49 = _io_out_T_2 == 5'h18; // @[package.scala:39:86] wire [31:0] _io_out_T_50_bits = _io_out_T_49 ? io_out_s_24_bits : _io_out_T_48_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rd = _io_out_T_49 ? io_out_s_24_rd : _io_out_T_48_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs1 = _io_out_T_49 ? io_out_s_24_rs1 : _io_out_T_48_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs2 = _io_out_T_49 ? io_out_s_24_rs2 : _io_out_T_48_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_50_rs3 = _io_out_T_49 ? io_out_s_24_rs3 : _io_out_T_48_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_51 = _io_out_T_2 == 5'h19; // @[package.scala:39:86] wire [31:0] _io_out_T_52_bits = _io_out_T_51 ? io_out_s_25_bits : _io_out_T_50_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rd = _io_out_T_51 ? io_out_s_25_rd : _io_out_T_50_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs1 = _io_out_T_51 ? io_out_s_25_rs1 : _io_out_T_50_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs2 = _io_out_T_51 ? io_out_s_25_rs2 : _io_out_T_50_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_52_rs3 = _io_out_T_51 ? io_out_s_25_rs3 : _io_out_T_50_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_53 = _io_out_T_2 == 5'h1A; // @[package.scala:39:86] wire [31:0] _io_out_T_54_bits = _io_out_T_53 ? io_out_s_26_bits : _io_out_T_52_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rd = _io_out_T_53 ? io_out_s_26_rd : _io_out_T_52_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs1 = _io_out_T_53 ? io_out_s_26_rs1 : _io_out_T_52_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs2 = _io_out_T_53 ? io_out_s_26_rs2 : _io_out_T_52_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_54_rs3 = _io_out_T_53 ? io_out_s_26_rs3 : _io_out_T_52_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_55 = _io_out_T_2 == 5'h1B; // @[package.scala:39:86] wire [31:0] _io_out_T_56_bits = _io_out_T_55 ? io_out_s_27_bits : _io_out_T_54_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rd = _io_out_T_55 ? io_out_s_27_rd : _io_out_T_54_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs1 = _io_out_T_55 ? io_out_s_27_rs1 : _io_out_T_54_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs2 = _io_out_T_55 ? io_out_s_27_rs2 : _io_out_T_54_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_56_rs3 = _io_out_T_55 ? io_out_s_27_rs3 : _io_out_T_54_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_57 = _io_out_T_2 == 5'h1C; // @[package.scala:39:86] wire [31:0] _io_out_T_58_bits = _io_out_T_57 ? io_out_s_28_bits : _io_out_T_56_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rd = _io_out_T_57 ? io_out_s_28_rd : _io_out_T_56_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs1 = _io_out_T_57 ? io_out_s_28_rs1 : _io_out_T_56_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs2 = _io_out_T_57 ? io_out_s_28_rs2 : _io_out_T_56_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_58_rs3 = _io_out_T_57 ? io_out_s_28_rs3 : _io_out_T_56_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_59 = _io_out_T_2 == 5'h1D; // @[package.scala:39:86] wire [31:0] _io_out_T_60_bits = _io_out_T_59 ? io_out_s_29_bits : _io_out_T_58_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rd = _io_out_T_59 ? io_out_s_29_rd : _io_out_T_58_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs1 = _io_out_T_59 ? io_out_s_29_rs1 : _io_out_T_58_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs2 = _io_out_T_59 ? io_out_s_29_rs2 : _io_out_T_58_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_60_rs3 = _io_out_T_59 ? io_out_s_29_rs3 : _io_out_T_58_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_61 = _io_out_T_2 == 5'h1E; // @[package.scala:39:86] wire [31:0] _io_out_T_62_bits = _io_out_T_61 ? io_out_s_30_bits : _io_out_T_60_bits; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rd = _io_out_T_61 ? io_out_s_30_rd : _io_out_T_60_rd; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs1 = _io_out_T_61 ? io_out_s_30_rs1 : _io_out_T_60_rs1; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs2 = _io_out_T_61 ? io_out_s_30_rs2 : _io_out_T_60_rs2; // @[package.scala:39:{76,86}] wire [4:0] _io_out_T_62_rs3 = _io_out_T_61 ? io_out_s_30_rs3 : _io_out_T_60_rs3; // @[package.scala:39:{76,86}] wire _io_out_T_63 = &_io_out_T_2; // @[package.scala:39:86] assign _io_out_T_64_bits = _io_out_T_63 ? io_out_s_31_bits : _io_out_T_62_bits; // @[package.scala:39:{76,86}] assign _io_out_T_64_rd = _io_out_T_63 ? io_out_s_31_rd : _io_out_T_62_rd; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs1 = _io_out_T_63 ? io_out_s_31_rs1 : _io_out_T_62_rs1; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs2 = _io_out_T_63 ? io_out_s_31_rs2 : _io_out_T_62_rs2; // @[package.scala:39:{76,86}] assign _io_out_T_64_rs3 = _io_out_T_63 ? io_out_s_31_rs3 : _io_out_T_62_rs3; // @[package.scala:39:{76,86}] assign io_out_bits_0 = _io_out_T_64_bits; // @[package.scala:39:76] assign io_out_rd = _io_out_T_64_rd; // @[package.scala:39:76] assign io_out_rs1 = _io_out_T_64_rs1; // @[package.scala:39:76] assign io_out_rs2 = _io_out_T_64_rs2; // @[package.scala:39:76] assign io_out_rs3 = _io_out_T_64_rs3; // @[package.scala:39:76] wire [10:0] _io_ill_s_T = io_in_0[12:2]; // @[RVC.scala:158:19, :190:7] wire [10:0] _io_ill_s_T_13 = io_in_0[12:2]; // @[RVC.scala:158:19, :177:21, :190:7] wire _io_ill_s_T_1 = |_io_ill_s_T; // @[RVC.scala:158:{19,27}] wire io_ill_s_0 = ~_io_ill_s_T_1; // @[RVC.scala:158:{16,27}] wire io_ill_s_9 = _io_ill_s_T_2 == 5'h0; // @[RVC.scala:33:13, :167:47] wire _io_ill_s_T_5 = |_io_ill_s_T_4; // @[RVC.scala:168:{27,34}] wire _io_ill_s_T_6 = _io_ill_s_T_3 | _io_ill_s_T_5; // @[RVC.scala:168:{19,24,34}] wire io_ill_s_11 = ~_io_ill_s_T_6; // @[RVC.scala:168:{16,24}] wire _io_ill_s_T_8 = &_io_ill_s_T_7; // @[RVC.scala:169:{22,31}] wire _io_ill_s_T_10 = _io_ill_s_T_9; // @[RVC.scala:169:{69,73}] wire io_ill_s_12 = _io_ill_s_T_8 & _io_ill_s_T_10; // @[RVC.scala:169:{31,36,73}] wire io_ill_s_18 = _io_ill_s_T_11 == 5'h0; // @[RVC.scala:33:13, :175:18] wire io_ill_s_19 = _io_ill_s_T_12 == 5'h0; // @[RVC.scala:33:13, :175:18] wire _io_ill_s_T_14 = |_io_ill_s_T_13; // @[RVC.scala:177:{21,29}] wire io_ill_s_20 = ~_io_ill_s_T_14; // @[RVC.scala:177:{18,29}] wire [4:0] _io_ill_T_2 = {_io_ill_T, _io_ill_T_1}; // @[RVC.scala:186:{10,12,20}] wire _io_ill_T_3 = _io_ill_T_2 == 5'h1; // @[package.scala:39:86] wire _io_ill_T_4 = ~_io_ill_T_3 & io_ill_s_0; // @[package.scala:39:{76,86}] wire _io_ill_T_5 = _io_ill_T_2 == 5'h2; // @[package.scala:39:86] wire _io_ill_T_6 = ~_io_ill_T_5 & _io_ill_T_4; // @[package.scala:39:{76,86}] wire _io_ill_T_7 = _io_ill_T_2 == 5'h3; // @[package.scala:39:86] wire _io_ill_T_8 = ~_io_ill_T_7 & _io_ill_T_6; // @[package.scala:39:{76,86}] wire _io_ill_T_9 = _io_ill_T_2 == 5'h4; // @[package.scala:39:86] wire _io_ill_T_10 = _io_ill_T_9 | _io_ill_T_8; // @[package.scala:39:{76,86}] wire _io_ill_T_11 = _io_ill_T_2 == 5'h5; // @[package.scala:39:86] wire _io_ill_T_12 = ~_io_ill_T_11 & _io_ill_T_10; // @[package.scala:39:{76,86}] wire _io_ill_T_13 = _io_ill_T_2 == 5'h6; // @[package.scala:39:86] wire _io_ill_T_14 = ~_io_ill_T_13 & _io_ill_T_12; // @[package.scala:39:{76,86}] wire _io_ill_T_15 = _io_ill_T_2 == 5'h7; // @[package.scala:39:86] wire _io_ill_T_16 = ~_io_ill_T_15 & _io_ill_T_14; // @[package.scala:39:{76,86}] wire _io_ill_T_17 = _io_ill_T_2 == 5'h8; // @[package.scala:39:86] wire _io_ill_T_18 = ~_io_ill_T_17 & _io_ill_T_16; // @[package.scala:39:{76,86}] wire _io_ill_T_19 = _io_ill_T_2 == 5'h9; // @[package.scala:39:86] wire _io_ill_T_20 = _io_ill_T_19 ? io_ill_s_9 : _io_ill_T_18; // @[package.scala:39:{76,86}] wire _io_ill_T_21 = _io_ill_T_2 == 5'hA; // @[package.scala:39:86] wire _io_ill_T_22 = ~_io_ill_T_21 & _io_ill_T_20; // @[package.scala:39:{76,86}] wire _io_ill_T_23 = _io_ill_T_2 == 5'hB; // @[package.scala:39:86] wire _io_ill_T_24 = _io_ill_T_23 ? io_ill_s_11 : _io_ill_T_22; // @[package.scala:39:{76,86}] wire _io_ill_T_25 = _io_ill_T_2 == 5'hC; // @[package.scala:39:86] wire _io_ill_T_26 = _io_ill_T_25 ? io_ill_s_12 : _io_ill_T_24; // @[package.scala:39:{76,86}] wire _io_ill_T_27 = _io_ill_T_2 == 5'hD; // @[package.scala:39:86] wire _io_ill_T_28 = ~_io_ill_T_27 & _io_ill_T_26; // @[package.scala:39:{76,86}] wire _io_ill_T_29 = _io_ill_T_2 == 5'hE; // @[package.scala:39:86] wire _io_ill_T_30 = ~_io_ill_T_29 & _io_ill_T_28; // @[package.scala:39:{76,86}] wire _io_ill_T_31 = _io_ill_T_2 == 5'hF; // @[package.scala:39:86] wire _io_ill_T_32 = ~_io_ill_T_31 & _io_ill_T_30; // @[package.scala:39:{76,86}] wire _io_ill_T_33 = _io_ill_T_2 == 5'h10; // @[package.scala:39:86] wire _io_ill_T_34 = ~_io_ill_T_33 & _io_ill_T_32; // @[package.scala:39:{76,86}] wire _io_ill_T_35 = _io_ill_T_2 == 5'h11; // @[package.scala:39:86] wire _io_ill_T_36 = ~_io_ill_T_35 & _io_ill_T_34; // @[package.scala:39:{76,86}] wire _io_ill_T_37 = _io_ill_T_2 == 5'h12; // @[package.scala:39:86] wire _io_ill_T_38 = _io_ill_T_37 ? io_ill_s_18 : _io_ill_T_36; // @[package.scala:39:{76,86}] wire _io_ill_T_39 = _io_ill_T_2 == 5'h13; // @[package.scala:39:86] wire _io_ill_T_40 = _io_ill_T_39 ? io_ill_s_19 : _io_ill_T_38; // @[package.scala:39:{76,86}] wire _io_ill_T_41 = _io_ill_T_2 == 5'h14; // @[package.scala:39:86] wire _io_ill_T_42 = _io_ill_T_41 ? io_ill_s_20 : _io_ill_T_40; // @[package.scala:39:{76,86}] wire _io_ill_T_43 = _io_ill_T_2 == 5'h15; // @[package.scala:39:86] wire _io_ill_T_44 = ~_io_ill_T_43 & _io_ill_T_42; // @[package.scala:39:{76,86}] wire _io_ill_T_45 = _io_ill_T_2 == 5'h16; // @[package.scala:39:86] wire _io_ill_T_46 = ~_io_ill_T_45 & _io_ill_T_44; // @[package.scala:39:{76,86}] wire _io_ill_T_47 = _io_ill_T_2 == 5'h17; // @[package.scala:39:86] wire _io_ill_T_48 = ~_io_ill_T_47 & _io_ill_T_46; // @[package.scala:39:{76,86}] wire _io_ill_T_49 = _io_ill_T_2 == 5'h18; // @[package.scala:39:86] wire _io_ill_T_50 = ~_io_ill_T_49 & _io_ill_T_48; // @[package.scala:39:{76,86}] wire _io_ill_T_51 = _io_ill_T_2 == 5'h19; // @[package.scala:39:86] wire _io_ill_T_52 = ~_io_ill_T_51 & _io_ill_T_50; // @[package.scala:39:{76,86}] wire _io_ill_T_53 = _io_ill_T_2 == 5'h1A; // @[package.scala:39:86] wire _io_ill_T_54 = ~_io_ill_T_53 & _io_ill_T_52; // @[package.scala:39:{76,86}] wire _io_ill_T_55 = _io_ill_T_2 == 5'h1B; // @[package.scala:39:86] wire _io_ill_T_56 = ~_io_ill_T_55 & _io_ill_T_54; // @[package.scala:39:{76,86}] wire _io_ill_T_57 = _io_ill_T_2 == 5'h1C; // @[package.scala:39:86] wire _io_ill_T_58 = ~_io_ill_T_57 & _io_ill_T_56; // @[package.scala:39:{76,86}] wire _io_ill_T_59 = _io_ill_T_2 == 5'h1D; // @[package.scala:39:86] wire _io_ill_T_60 = ~_io_ill_T_59 & _io_ill_T_58; // @[package.scala:39:{76,86}] wire _io_ill_T_61 = _io_ill_T_2 == 5'h1E; // @[package.scala:39:86] wire _io_ill_T_62 = ~_io_ill_T_61 & _io_ill_T_60; // @[package.scala:39:{76,86}] wire _io_ill_T_63 = &_io_ill_T_2; // @[package.scala:39:86] assign _io_ill_T_64 = ~_io_ill_T_63 & _io_ill_T_62; // @[package.scala:39:{76,86}] assign io_ill = _io_ill_T_64; // @[package.scala:39:76] assign io_out_bits = io_out_bits_0; // @[RVC.scala:190:7] assign io_rvc = io_rvc_0; // @[RVC.scala:190:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_41 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, b : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 3, 0) node _source_ok_T = shr(io.in.a.bits.source, 4) node _source_ok_T_1 = eq(_source_ok_T, UInt<1>(0h0)) node _source_ok_T_2 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_3 = and(_source_ok_T_1, _source_ok_T_2) node _source_ok_T_4 = leq(source_ok_uncommonBits, UInt<4>(0h9)) node _source_ok_T_5 = and(_source_ok_T_3, _source_ok_T_4) wire _source_ok_WIRE : UInt<1>[1] connect _source_ok_WIRE[0], _source_ok_T_5 node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _uncommonBits_T = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits = bits(_uncommonBits_T, 3, 0) node _T_4 = shr(io.in.a.bits.source, 4) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = leq(UInt<1>(0h0), uncommonBits) node _T_7 = and(_T_5, _T_6) node _T_8 = leq(uncommonBits, UInt<4>(0h9)) node _T_9 = and(_T_7, _T_8) node _T_10 = eq(_T_9, UInt<1>(0h0)) node _T_11 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_12 = cvt(_T_11) node _T_13 = and(_T_12, asSInt(UInt<1>(0h0))) node _T_14 = asSInt(_T_13) node _T_15 = eq(_T_14, asSInt(UInt<1>(0h0))) node _T_16 = or(_T_10, _T_15) node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : node _T_19 = eq(_T_16, UInt<1>(0h0)) when _T_19 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_16, UInt<1>(0h1), "") : assert_1 node _T_20 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_20 : node _T_21 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_22 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_23 = and(_T_21, _T_22) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 3, 0) node _T_24 = shr(io.in.a.bits.source, 4) node _T_25 = eq(_T_24, UInt<1>(0h0)) node _T_26 = leq(UInt<1>(0h0), uncommonBits_1) node _T_27 = and(_T_25, _T_26) node _T_28 = leq(uncommonBits_1, UInt<4>(0h9)) node _T_29 = and(_T_27, _T_28) node _T_30 = and(_T_23, _T_29) node _T_31 = or(UInt<1>(0h0), _T_30) node _T_32 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_33 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_34 = and(_T_32, _T_33) node _T_35 = or(UInt<1>(0h0), _T_34) node _T_36 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_37 = cvt(_T_36) node _T_38 = and(_T_37, asSInt(UInt<17>(0h10000))) node _T_39 = asSInt(_T_38) node _T_40 = eq(_T_39, asSInt(UInt<1>(0h0))) node _T_41 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_42 = cvt(_T_41) node _T_43 = and(_T_42, asSInt(UInt<29>(0h10000000))) node _T_44 = asSInt(_T_43) node _T_45 = eq(_T_44, asSInt(UInt<1>(0h0))) node _T_46 = or(_T_40, _T_45) node _T_47 = and(_T_35, _T_46) node _T_48 = or(UInt<1>(0h0), _T_47) node _T_49 = and(_T_31, _T_48) node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : node _T_52 = eq(_T_49, UInt<1>(0h0)) when _T_52 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_49, UInt<1>(0h1), "") : assert_2 node _T_53 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_54 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_55 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_56 = and(_T_54, _T_55) node _T_57 = or(UInt<1>(0h0), _T_56) node _T_58 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<17>(0h10000))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_64 = cvt(_T_63) node _T_65 = and(_T_64, asSInt(UInt<29>(0h10000000))) node _T_66 = asSInt(_T_65) node _T_67 = eq(_T_66, asSInt(UInt<1>(0h0))) node _T_68 = or(_T_62, _T_67) node _T_69 = and(_T_57, _T_68) node _T_70 = or(UInt<1>(0h0), _T_69) node _T_71 = and(_T_53, _T_70) node _T_72 = asUInt(reset) node _T_73 = eq(_T_72, UInt<1>(0h0)) when _T_73 : node _T_74 = eq(_T_71, UInt<1>(0h0)) when _T_74 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_71, UInt<1>(0h1), "") : assert_3 node _T_75 = asUInt(reset) node _T_76 = eq(_T_75, UInt<1>(0h0)) when _T_76 : node _T_77 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_77 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_4 node _T_78 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_79 = asUInt(reset) node _T_80 = eq(_T_79, UInt<1>(0h0)) when _T_80 : node _T_81 = eq(_T_78, UInt<1>(0h0)) when _T_81 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_78, UInt<1>(0h1), "") : assert_5 node _T_82 = asUInt(reset) node _T_83 = eq(_T_82, UInt<1>(0h0)) when _T_83 : node _T_84 = eq(is_aligned, UInt<1>(0h0)) when _T_84 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_85 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_86 = asUInt(reset) node _T_87 = eq(_T_86, UInt<1>(0h0)) when _T_87 : node _T_88 = eq(_T_85, UInt<1>(0h0)) when _T_88 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_85, UInt<1>(0h1), "") : assert_7 node _T_89 = not(io.in.a.bits.mask) node _T_90 = eq(_T_89, UInt<1>(0h0)) node _T_91 = asUInt(reset) node _T_92 = eq(_T_91, UInt<1>(0h0)) when _T_92 : node _T_93 = eq(_T_90, UInt<1>(0h0)) when _T_93 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_90, UInt<1>(0h1), "") : assert_8 node _T_94 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_95 = asUInt(reset) node _T_96 = eq(_T_95, UInt<1>(0h0)) when _T_96 : node _T_97 = eq(_T_94, UInt<1>(0h0)) when _T_97 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_94, UInt<1>(0h1), "") : assert_9 node _T_98 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_98 : node _T_99 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_100 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_101 = and(_T_99, _T_100) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 3, 0) node _T_102 = shr(io.in.a.bits.source, 4) node _T_103 = eq(_T_102, UInt<1>(0h0)) node _T_104 = leq(UInt<1>(0h0), uncommonBits_2) node _T_105 = and(_T_103, _T_104) node _T_106 = leq(uncommonBits_2, UInt<4>(0h9)) node _T_107 = and(_T_105, _T_106) node _T_108 = and(_T_101, _T_107) node _T_109 = or(UInt<1>(0h0), _T_108) node _T_110 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_111 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_112 = and(_T_110, _T_111) node _T_113 = or(UInt<1>(0h0), _T_112) node _T_114 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_115 = cvt(_T_114) node _T_116 = and(_T_115, asSInt(UInt<17>(0h10000))) node _T_117 = asSInt(_T_116) node _T_118 = eq(_T_117, asSInt(UInt<1>(0h0))) node _T_119 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_120 = cvt(_T_119) node _T_121 = and(_T_120, asSInt(UInt<29>(0h10000000))) node _T_122 = asSInt(_T_121) node _T_123 = eq(_T_122, asSInt(UInt<1>(0h0))) node _T_124 = or(_T_118, _T_123) node _T_125 = and(_T_113, _T_124) node _T_126 = or(UInt<1>(0h0), _T_125) node _T_127 = and(_T_109, _T_126) node _T_128 = asUInt(reset) node _T_129 = eq(_T_128, UInt<1>(0h0)) when _T_129 : node _T_130 = eq(_T_127, UInt<1>(0h0)) when _T_130 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_127, UInt<1>(0h1), "") : assert_10 node _T_131 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_132 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_133 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_134 = and(_T_132, _T_133) node _T_135 = or(UInt<1>(0h0), _T_134) node _T_136 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_137 = cvt(_T_136) node _T_138 = and(_T_137, asSInt(UInt<17>(0h10000))) node _T_139 = asSInt(_T_138) node _T_140 = eq(_T_139, asSInt(UInt<1>(0h0))) node _T_141 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_142 = cvt(_T_141) node _T_143 = and(_T_142, asSInt(UInt<29>(0h10000000))) node _T_144 = asSInt(_T_143) node _T_145 = eq(_T_144, asSInt(UInt<1>(0h0))) node _T_146 = or(_T_140, _T_145) node _T_147 = and(_T_135, _T_146) node _T_148 = or(UInt<1>(0h0), _T_147) node _T_149 = and(_T_131, _T_148) node _T_150 = asUInt(reset) node _T_151 = eq(_T_150, UInt<1>(0h0)) when _T_151 : node _T_152 = eq(_T_149, UInt<1>(0h0)) when _T_152 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_149, UInt<1>(0h1), "") : assert_11 node _T_153 = asUInt(reset) node _T_154 = eq(_T_153, UInt<1>(0h0)) when _T_154 : node _T_155 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_155 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_12 node _T_156 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_157 = asUInt(reset) node _T_158 = eq(_T_157, UInt<1>(0h0)) when _T_158 : node _T_159 = eq(_T_156, UInt<1>(0h0)) when _T_159 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_156, UInt<1>(0h1), "") : assert_13 node _T_160 = asUInt(reset) node _T_161 = eq(_T_160, UInt<1>(0h0)) when _T_161 : node _T_162 = eq(is_aligned, UInt<1>(0h0)) when _T_162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_163 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_164 = asUInt(reset) node _T_165 = eq(_T_164, UInt<1>(0h0)) when _T_165 : node _T_166 = eq(_T_163, UInt<1>(0h0)) when _T_166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_163, UInt<1>(0h1), "") : assert_15 node _T_167 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_168 = asUInt(reset) node _T_169 = eq(_T_168, UInt<1>(0h0)) when _T_169 : node _T_170 = eq(_T_167, UInt<1>(0h0)) when _T_170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_167, UInt<1>(0h1), "") : assert_16 node _T_171 = not(io.in.a.bits.mask) node _T_172 = eq(_T_171, UInt<1>(0h0)) node _T_173 = asUInt(reset) node _T_174 = eq(_T_173, UInt<1>(0h0)) when _T_174 : node _T_175 = eq(_T_172, UInt<1>(0h0)) when _T_175 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_172, UInt<1>(0h1), "") : assert_17 node _T_176 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_177 = asUInt(reset) node _T_178 = eq(_T_177, UInt<1>(0h0)) when _T_178 : node _T_179 = eq(_T_176, UInt<1>(0h0)) when _T_179 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_176, UInt<1>(0h1), "") : assert_18 node _T_180 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_180 : node _T_181 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_182 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_183 = and(_T_181, _T_182) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 3, 0) node _T_184 = shr(io.in.a.bits.source, 4) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = leq(UInt<1>(0h0), uncommonBits_3) node _T_187 = and(_T_185, _T_186) node _T_188 = leq(uncommonBits_3, UInt<4>(0h9)) node _T_189 = and(_T_187, _T_188) node _T_190 = and(_T_183, _T_189) node _T_191 = or(UInt<1>(0h0), _T_190) node _T_192 = asUInt(reset) node _T_193 = eq(_T_192, UInt<1>(0h0)) when _T_193 : node _T_194 = eq(_T_191, UInt<1>(0h0)) when _T_194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_191, UInt<1>(0h1), "") : assert_19 node _T_195 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_196 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_197 = and(_T_195, _T_196) node _T_198 = or(UInt<1>(0h0), _T_197) node _T_199 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_200 = cvt(_T_199) node _T_201 = and(_T_200, asSInt(UInt<17>(0h10000))) node _T_202 = asSInt(_T_201) node _T_203 = eq(_T_202, asSInt(UInt<1>(0h0))) node _T_204 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_205 = cvt(_T_204) node _T_206 = and(_T_205, asSInt(UInt<29>(0h10000000))) node _T_207 = asSInt(_T_206) node _T_208 = eq(_T_207, asSInt(UInt<1>(0h0))) node _T_209 = or(_T_203, _T_208) node _T_210 = and(_T_198, _T_209) node _T_211 = or(UInt<1>(0h0), _T_210) node _T_212 = asUInt(reset) node _T_213 = eq(_T_212, UInt<1>(0h0)) when _T_213 : node _T_214 = eq(_T_211, UInt<1>(0h0)) when _T_214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_211, UInt<1>(0h1), "") : assert_20 node _T_215 = asUInt(reset) node _T_216 = eq(_T_215, UInt<1>(0h0)) when _T_216 : node _T_217 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_217 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_21 node _T_218 = asUInt(reset) node _T_219 = eq(_T_218, UInt<1>(0h0)) when _T_219 : node _T_220 = eq(is_aligned, UInt<1>(0h0)) when _T_220 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_221 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_222 = asUInt(reset) node _T_223 = eq(_T_222, UInt<1>(0h0)) when _T_223 : node _T_224 = eq(_T_221, UInt<1>(0h0)) when _T_224 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_221, UInt<1>(0h1), "") : assert_23 node _T_225 = eq(io.in.a.bits.mask, mask) node _T_226 = asUInt(reset) node _T_227 = eq(_T_226, UInt<1>(0h0)) when _T_227 : node _T_228 = eq(_T_225, UInt<1>(0h0)) when _T_228 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_225, UInt<1>(0h1), "") : assert_24 node _T_229 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_230 = asUInt(reset) node _T_231 = eq(_T_230, UInt<1>(0h0)) when _T_231 : node _T_232 = eq(_T_229, UInt<1>(0h0)) when _T_232 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_229, UInt<1>(0h1), "") : assert_25 node _T_233 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_233 : node _T_234 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_235 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_236 = and(_T_234, _T_235) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 3, 0) node _T_237 = shr(io.in.a.bits.source, 4) node _T_238 = eq(_T_237, UInt<1>(0h0)) node _T_239 = leq(UInt<1>(0h0), uncommonBits_4) node _T_240 = and(_T_238, _T_239) node _T_241 = leq(uncommonBits_4, UInt<4>(0h9)) node _T_242 = and(_T_240, _T_241) node _T_243 = and(_T_236, _T_242) node _T_244 = or(UInt<1>(0h0), _T_243) node _T_245 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_246 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_247 = and(_T_245, _T_246) node _T_248 = or(UInt<1>(0h0), _T_247) node _T_249 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_250 = cvt(_T_249) node _T_251 = and(_T_250, asSInt(UInt<17>(0h10000))) node _T_252 = asSInt(_T_251) node _T_253 = eq(_T_252, asSInt(UInt<1>(0h0))) node _T_254 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_255 = cvt(_T_254) node _T_256 = and(_T_255, asSInt(UInt<29>(0h10000000))) node _T_257 = asSInt(_T_256) node _T_258 = eq(_T_257, asSInt(UInt<1>(0h0))) node _T_259 = or(_T_253, _T_258) node _T_260 = and(_T_248, _T_259) node _T_261 = or(UInt<1>(0h0), _T_260) node _T_262 = and(_T_244, _T_261) node _T_263 = asUInt(reset) node _T_264 = eq(_T_263, UInt<1>(0h0)) when _T_264 : node _T_265 = eq(_T_262, UInt<1>(0h0)) when _T_265 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_262, UInt<1>(0h1), "") : assert_26 node _T_266 = asUInt(reset) node _T_267 = eq(_T_266, UInt<1>(0h0)) when _T_267 : node _T_268 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_268 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_27 node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(is_aligned, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_272 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_272, UInt<1>(0h1), "") : assert_29 node _T_276 = eq(io.in.a.bits.mask, mask) node _T_277 = asUInt(reset) node _T_278 = eq(_T_277, UInt<1>(0h0)) when _T_278 : node _T_279 = eq(_T_276, UInt<1>(0h0)) when _T_279 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_276, UInt<1>(0h1), "") : assert_30 node _T_280 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_280 : node _T_281 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_282 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_283 = and(_T_281, _T_282) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 3, 0) node _T_284 = shr(io.in.a.bits.source, 4) node _T_285 = eq(_T_284, UInt<1>(0h0)) node _T_286 = leq(UInt<1>(0h0), uncommonBits_5) node _T_287 = and(_T_285, _T_286) node _T_288 = leq(uncommonBits_5, UInt<4>(0h9)) node _T_289 = and(_T_287, _T_288) node _T_290 = and(_T_283, _T_289) node _T_291 = or(UInt<1>(0h0), _T_290) node _T_292 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_293 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_294 = and(_T_292, _T_293) node _T_295 = or(UInt<1>(0h0), _T_294) node _T_296 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_297 = cvt(_T_296) node _T_298 = and(_T_297, asSInt(UInt<17>(0h10000))) node _T_299 = asSInt(_T_298) node _T_300 = eq(_T_299, asSInt(UInt<1>(0h0))) node _T_301 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_302 = cvt(_T_301) node _T_303 = and(_T_302, asSInt(UInt<29>(0h10000000))) node _T_304 = asSInt(_T_303) node _T_305 = eq(_T_304, asSInt(UInt<1>(0h0))) node _T_306 = or(_T_300, _T_305) node _T_307 = and(_T_295, _T_306) node _T_308 = or(UInt<1>(0h0), _T_307) node _T_309 = and(_T_291, _T_308) node _T_310 = asUInt(reset) node _T_311 = eq(_T_310, UInt<1>(0h0)) when _T_311 : node _T_312 = eq(_T_309, UInt<1>(0h0)) when _T_312 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_309, UInt<1>(0h1), "") : assert_31 node _T_313 = asUInt(reset) node _T_314 = eq(_T_313, UInt<1>(0h0)) when _T_314 : node _T_315 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_315 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_32 node _T_316 = asUInt(reset) node _T_317 = eq(_T_316, UInt<1>(0h0)) when _T_317 : node _T_318 = eq(is_aligned, UInt<1>(0h0)) when _T_318 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_319 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_320 = asUInt(reset) node _T_321 = eq(_T_320, UInt<1>(0h0)) when _T_321 : node _T_322 = eq(_T_319, UInt<1>(0h0)) when _T_322 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_319, UInt<1>(0h1), "") : assert_34 node _T_323 = not(mask) node _T_324 = and(io.in.a.bits.mask, _T_323) node _T_325 = eq(_T_324, UInt<1>(0h0)) node _T_326 = asUInt(reset) node _T_327 = eq(_T_326, UInt<1>(0h0)) when _T_327 : node _T_328 = eq(_T_325, UInt<1>(0h0)) when _T_328 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_325, UInt<1>(0h1), "") : assert_35 node _T_329 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_329 : node _T_330 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_331 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_332 = and(_T_330, _T_331) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 3, 0) node _T_333 = shr(io.in.a.bits.source, 4) node _T_334 = eq(_T_333, UInt<1>(0h0)) node _T_335 = leq(UInt<1>(0h0), uncommonBits_6) node _T_336 = and(_T_334, _T_335) node _T_337 = leq(uncommonBits_6, UInt<4>(0h9)) node _T_338 = and(_T_336, _T_337) node _T_339 = and(_T_332, _T_338) node _T_340 = or(UInt<1>(0h0), _T_339) node _T_341 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_342 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_343 = cvt(_T_342) node _T_344 = and(_T_343, asSInt(UInt<17>(0h10000))) node _T_345 = asSInt(_T_344) node _T_346 = eq(_T_345, asSInt(UInt<1>(0h0))) node _T_347 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_348 = cvt(_T_347) node _T_349 = and(_T_348, asSInt(UInt<29>(0h10000000))) node _T_350 = asSInt(_T_349) node _T_351 = eq(_T_350, asSInt(UInt<1>(0h0))) node _T_352 = or(_T_346, _T_351) node _T_353 = and(_T_341, _T_352) node _T_354 = or(UInt<1>(0h0), _T_353) node _T_355 = and(_T_340, _T_354) node _T_356 = asUInt(reset) node _T_357 = eq(_T_356, UInt<1>(0h0)) when _T_357 : node _T_358 = eq(_T_355, UInt<1>(0h0)) when _T_358 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_355, UInt<1>(0h1), "") : assert_36 node _T_359 = asUInt(reset) node _T_360 = eq(_T_359, UInt<1>(0h0)) when _T_360 : node _T_361 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_361 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_37 node _T_362 = asUInt(reset) node _T_363 = eq(_T_362, UInt<1>(0h0)) when _T_363 : node _T_364 = eq(is_aligned, UInt<1>(0h0)) when _T_364 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_365 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_366 = asUInt(reset) node _T_367 = eq(_T_366, UInt<1>(0h0)) when _T_367 : node _T_368 = eq(_T_365, UInt<1>(0h0)) when _T_368 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_365, UInt<1>(0h1), "") : assert_39 node _T_369 = eq(io.in.a.bits.mask, mask) node _T_370 = asUInt(reset) node _T_371 = eq(_T_370, UInt<1>(0h0)) when _T_371 : node _T_372 = eq(_T_369, UInt<1>(0h0)) when _T_372 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_369, UInt<1>(0h1), "") : assert_40 node _T_373 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_373 : node _T_374 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_375 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_376 = and(_T_374, _T_375) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 3, 0) node _T_377 = shr(io.in.a.bits.source, 4) node _T_378 = eq(_T_377, UInt<1>(0h0)) node _T_379 = leq(UInt<1>(0h0), uncommonBits_7) node _T_380 = and(_T_378, _T_379) node _T_381 = leq(uncommonBits_7, UInt<4>(0h9)) node _T_382 = and(_T_380, _T_381) node _T_383 = and(_T_376, _T_382) node _T_384 = or(UInt<1>(0h0), _T_383) node _T_385 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_386 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_387 = cvt(_T_386) node _T_388 = and(_T_387, asSInt(UInt<17>(0h10000))) node _T_389 = asSInt(_T_388) node _T_390 = eq(_T_389, asSInt(UInt<1>(0h0))) node _T_391 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_392 = cvt(_T_391) node _T_393 = and(_T_392, asSInt(UInt<29>(0h10000000))) node _T_394 = asSInt(_T_393) node _T_395 = eq(_T_394, asSInt(UInt<1>(0h0))) node _T_396 = or(_T_390, _T_395) node _T_397 = and(_T_385, _T_396) node _T_398 = or(UInt<1>(0h0), _T_397) node _T_399 = and(_T_384, _T_398) node _T_400 = asUInt(reset) node _T_401 = eq(_T_400, UInt<1>(0h0)) when _T_401 : node _T_402 = eq(_T_399, UInt<1>(0h0)) when _T_402 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_399, UInt<1>(0h1), "") : assert_41 node _T_403 = asUInt(reset) node _T_404 = eq(_T_403, UInt<1>(0h0)) when _T_404 : node _T_405 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_405 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_42 node _T_406 = asUInt(reset) node _T_407 = eq(_T_406, UInt<1>(0h0)) when _T_407 : node _T_408 = eq(is_aligned, UInt<1>(0h0)) when _T_408 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_409 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_410 = asUInt(reset) node _T_411 = eq(_T_410, UInt<1>(0h0)) when _T_411 : node _T_412 = eq(_T_409, UInt<1>(0h0)) when _T_412 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_409, UInt<1>(0h1), "") : assert_44 node _T_413 = eq(io.in.a.bits.mask, mask) node _T_414 = asUInt(reset) node _T_415 = eq(_T_414, UInt<1>(0h0)) when _T_415 : node _T_416 = eq(_T_413, UInt<1>(0h0)) when _T_416 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_413, UInt<1>(0h1), "") : assert_45 node _T_417 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_417 : node _T_418 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_419 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_420 = and(_T_418, _T_419) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<4>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 3, 0) node _T_421 = shr(io.in.a.bits.source, 4) node _T_422 = eq(_T_421, UInt<1>(0h0)) node _T_423 = leq(UInt<1>(0h0), uncommonBits_8) node _T_424 = and(_T_422, _T_423) node _T_425 = leq(uncommonBits_8, UInt<4>(0h9)) node _T_426 = and(_T_424, _T_425) node _T_427 = and(_T_420, _T_426) node _T_428 = or(UInt<1>(0h0), _T_427) node _T_429 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_430 = xor(io.in.a.bits.address, UInt<28>(0h8000000)) node _T_431 = cvt(_T_430) node _T_432 = and(_T_431, asSInt(UInt<17>(0h10000))) node _T_433 = asSInt(_T_432) node _T_434 = eq(_T_433, asSInt(UInt<1>(0h0))) node _T_435 = xor(io.in.a.bits.address, UInt<32>(0h80000000)) node _T_436 = cvt(_T_435) node _T_437 = and(_T_436, asSInt(UInt<29>(0h10000000))) node _T_438 = asSInt(_T_437) node _T_439 = eq(_T_438, asSInt(UInt<1>(0h0))) node _T_440 = or(_T_434, _T_439) node _T_441 = and(_T_429, _T_440) node _T_442 = or(UInt<1>(0h0), _T_441) node _T_443 = and(_T_428, _T_442) node _T_444 = asUInt(reset) node _T_445 = eq(_T_444, UInt<1>(0h0)) when _T_445 : node _T_446 = eq(_T_443, UInt<1>(0h0)) when _T_446 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_443, UInt<1>(0h1), "") : assert_46 node _T_447 = asUInt(reset) node _T_448 = eq(_T_447, UInt<1>(0h0)) when _T_448 : node _T_449 = eq(_source_ok_WIRE[0], UInt<1>(0h0)) when _T_449 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, _source_ok_WIRE[0], UInt<1>(0h1), "") : assert_47 node _T_450 = asUInt(reset) node _T_451 = eq(_T_450, UInt<1>(0h0)) when _T_451 : node _T_452 = eq(is_aligned, UInt<1>(0h0)) when _T_452 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_453 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_454 = asUInt(reset) node _T_455 = eq(_T_454, UInt<1>(0h0)) when _T_455 : node _T_456 = eq(_T_453, UInt<1>(0h0)) when _T_456 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_453, UInt<1>(0h1), "") : assert_49 node _T_457 = eq(io.in.a.bits.mask, mask) node _T_458 = asUInt(reset) node _T_459 = eq(_T_458, UInt<1>(0h0)) when _T_459 : node _T_460 = eq(_T_457, UInt<1>(0h0)) when _T_460 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_457, UInt<1>(0h1), "") : assert_50 node _T_461 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_462 = asUInt(reset) node _T_463 = eq(_T_462, UInt<1>(0h0)) when _T_463 : node _T_464 = eq(_T_461, UInt<1>(0h0)) when _T_464 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_461, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_465 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_466 = asUInt(reset) node _T_467 = eq(_T_466, UInt<1>(0h0)) when _T_467 : node _T_468 = eq(_T_465, UInt<1>(0h0)) when _T_468 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_465, UInt<1>(0h1), "") : assert_52 node _source_ok_uncommonBits_T_1 = or(io.in.d.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 3, 0) node _source_ok_T_6 = shr(io.in.d.bits.source, 4) node _source_ok_T_7 = eq(_source_ok_T_6, UInt<1>(0h0)) node _source_ok_T_8 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_9 = and(_source_ok_T_7, _source_ok_T_8) node _source_ok_T_10 = leq(source_ok_uncommonBits_1, UInt<4>(0h9)) node _source_ok_T_11 = and(_source_ok_T_9, _source_ok_T_10) wire _source_ok_WIRE_1 : UInt<1>[1] connect _source_ok_WIRE_1[0], _source_ok_T_11 node sink_ok = lt(io.in.d.bits.sink, UInt<4>(0h8)) node _T_469 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_469 : node _T_470 = asUInt(reset) node _T_471 = eq(_T_470, UInt<1>(0h0)) when _T_471 : node _T_472 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_472 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_53 node _T_473 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_474 = asUInt(reset) node _T_475 = eq(_T_474, UInt<1>(0h0)) when _T_475 : node _T_476 = eq(_T_473, UInt<1>(0h0)) when _T_476 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_473, UInt<1>(0h1), "") : assert_54 node _T_477 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_478 = asUInt(reset) node _T_479 = eq(_T_478, UInt<1>(0h0)) when _T_479 : node _T_480 = eq(_T_477, UInt<1>(0h0)) when _T_480 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_477, UInt<1>(0h1), "") : assert_55 node _T_481 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_482 = asUInt(reset) node _T_483 = eq(_T_482, UInt<1>(0h0)) when _T_483 : node _T_484 = eq(_T_481, UInt<1>(0h0)) when _T_484 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_481, UInt<1>(0h1), "") : assert_56 node _T_485 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_486 = asUInt(reset) node _T_487 = eq(_T_486, UInt<1>(0h0)) when _T_487 : node _T_488 = eq(_T_485, UInt<1>(0h0)) when _T_488 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_485, UInt<1>(0h1), "") : assert_57 node _T_489 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_489 : node _T_490 = asUInt(reset) node _T_491 = eq(_T_490, UInt<1>(0h0)) when _T_491 : node _T_492 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_492 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_58 node _T_493 = asUInt(reset) node _T_494 = eq(_T_493, UInt<1>(0h0)) when _T_494 : node _T_495 = eq(sink_ok, UInt<1>(0h0)) when _T_495 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_496 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_497 = asUInt(reset) node _T_498 = eq(_T_497, UInt<1>(0h0)) when _T_498 : node _T_499 = eq(_T_496, UInt<1>(0h0)) when _T_499 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_496, UInt<1>(0h1), "") : assert_60 node _T_500 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_501 = asUInt(reset) node _T_502 = eq(_T_501, UInt<1>(0h0)) when _T_502 : node _T_503 = eq(_T_500, UInt<1>(0h0)) when _T_503 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_500, UInt<1>(0h1), "") : assert_61 node _T_504 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(_T_504, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_504, UInt<1>(0h1), "") : assert_62 node _T_508 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_508, UInt<1>(0h1), "") : assert_63 node _T_512 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_513 = or(UInt<1>(0h1), _T_512) node _T_514 = asUInt(reset) node _T_515 = eq(_T_514, UInt<1>(0h0)) when _T_515 : node _T_516 = eq(_T_513, UInt<1>(0h0)) when _T_516 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_513, UInt<1>(0h1), "") : assert_64 node _T_517 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_517 : node _T_518 = asUInt(reset) node _T_519 = eq(_T_518, UInt<1>(0h0)) when _T_519 : node _T_520 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_520 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_65 node _T_521 = asUInt(reset) node _T_522 = eq(_T_521, UInt<1>(0h0)) when _T_522 : node _T_523 = eq(sink_ok, UInt<1>(0h0)) when _T_523 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_524 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_525 = asUInt(reset) node _T_526 = eq(_T_525, UInt<1>(0h0)) when _T_526 : node _T_527 = eq(_T_524, UInt<1>(0h0)) when _T_527 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_524, UInt<1>(0h1), "") : assert_67 node _T_528 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_529 = asUInt(reset) node _T_530 = eq(_T_529, UInt<1>(0h0)) when _T_530 : node _T_531 = eq(_T_528, UInt<1>(0h0)) when _T_531 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_528, UInt<1>(0h1), "") : assert_68 node _T_532 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_533 = asUInt(reset) node _T_534 = eq(_T_533, UInt<1>(0h0)) when _T_534 : node _T_535 = eq(_T_532, UInt<1>(0h0)) when _T_535 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_532, UInt<1>(0h1), "") : assert_69 node _T_536 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_537 = or(_T_536, io.in.d.bits.corrupt) node _T_538 = asUInt(reset) node _T_539 = eq(_T_538, UInt<1>(0h0)) when _T_539 : node _T_540 = eq(_T_537, UInt<1>(0h0)) when _T_540 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_537, UInt<1>(0h1), "") : assert_70 node _T_541 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_542 = or(UInt<1>(0h1), _T_541) node _T_543 = asUInt(reset) node _T_544 = eq(_T_543, UInt<1>(0h0)) when _T_544 : node _T_545 = eq(_T_542, UInt<1>(0h0)) when _T_545 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_542, UInt<1>(0h1), "") : assert_71 node _T_546 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_546 : node _T_547 = asUInt(reset) node _T_548 = eq(_T_547, UInt<1>(0h0)) when _T_548 : node _T_549 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_549 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_72 node _T_550 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_551 = asUInt(reset) node _T_552 = eq(_T_551, UInt<1>(0h0)) when _T_552 : node _T_553 = eq(_T_550, UInt<1>(0h0)) when _T_553 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_550, UInt<1>(0h1), "") : assert_73 node _T_554 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_555 = asUInt(reset) node _T_556 = eq(_T_555, UInt<1>(0h0)) when _T_556 : node _T_557 = eq(_T_554, UInt<1>(0h0)) when _T_557 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_554, UInt<1>(0h1), "") : assert_74 node _T_558 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_559 = or(UInt<1>(0h1), _T_558) node _T_560 = asUInt(reset) node _T_561 = eq(_T_560, UInt<1>(0h0)) when _T_561 : node _T_562 = eq(_T_559, UInt<1>(0h0)) when _T_562 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_559, UInt<1>(0h1), "") : assert_75 node _T_563 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_563 : node _T_564 = asUInt(reset) node _T_565 = eq(_T_564, UInt<1>(0h0)) when _T_565 : node _T_566 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_566 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_76 node _T_567 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_568 = asUInt(reset) node _T_569 = eq(_T_568, UInt<1>(0h0)) when _T_569 : node _T_570 = eq(_T_567, UInt<1>(0h0)) when _T_570 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_567, UInt<1>(0h1), "") : assert_77 node _T_571 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_572 = or(_T_571, io.in.d.bits.corrupt) node _T_573 = asUInt(reset) node _T_574 = eq(_T_573, UInt<1>(0h0)) when _T_574 : node _T_575 = eq(_T_572, UInt<1>(0h0)) when _T_575 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_572, UInt<1>(0h1), "") : assert_78 node _T_576 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_577 = or(UInt<1>(0h1), _T_576) node _T_578 = asUInt(reset) node _T_579 = eq(_T_578, UInt<1>(0h0)) when _T_579 : node _T_580 = eq(_T_577, UInt<1>(0h0)) when _T_580 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_577, UInt<1>(0h1), "") : assert_79 node _T_581 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_581 : node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_source_ok_WIRE_1[0], UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, _source_ok_WIRE_1[0], UInt<1>(0h1), "") : assert_80 node _T_585 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_586 = asUInt(reset) node _T_587 = eq(_T_586, UInt<1>(0h0)) when _T_587 : node _T_588 = eq(_T_585, UInt<1>(0h0)) when _T_588 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_585, UInt<1>(0h1), "") : assert_81 node _T_589 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_590 = asUInt(reset) node _T_591 = eq(_T_590, UInt<1>(0h0)) when _T_591 : node _T_592 = eq(_T_589, UInt<1>(0h0)) when _T_592 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_589, UInt<1>(0h1), "") : assert_82 node _T_593 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_594 = or(UInt<1>(0h1), _T_593) node _T_595 = asUInt(reset) node _T_596 = eq(_T_595, UInt<1>(0h0)) when _T_596 : node _T_597 = eq(_T_594, UInt<1>(0h0)) when _T_597 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_594, UInt<1>(0h1), "") : assert_83 when io.in.b.valid : node _T_598 = leq(io.in.b.bits.opcode, UInt<3>(0h6)) node _T_599 = asUInt(reset) node _T_600 = eq(_T_599, UInt<1>(0h0)) when _T_600 : node _T_601 = eq(_T_598, UInt<1>(0h0)) when _T_601 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_598, UInt<1>(0h1), "") : assert_84 node _uncommonBits_T_9 = or(io.in.b.bits.source, UInt<4>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 3, 0) node _T_602 = shr(io.in.b.bits.source, 4) node _T_603 = eq(_T_602, UInt<1>(0h0)) node _T_604 = leq(UInt<1>(0h0), uncommonBits_9) node _T_605 = and(_T_603, _T_604) node _T_606 = leq(uncommonBits_9, UInt<4>(0h9)) node _T_607 = and(_T_605, _T_606) node _T_608 = eq(_T_607, UInt<1>(0h0)) node _T_609 = xor(io.in.b.bits.address, UInt<1>(0h0)) node _T_610 = cvt(_T_609) node _T_611 = and(_T_610, asSInt(UInt<1>(0h0))) node _T_612 = asSInt(_T_611) node _T_613 = eq(_T_612, asSInt(UInt<1>(0h0))) node _T_614 = or(_T_608, _T_613) node _T_615 = asUInt(reset) node _T_616 = eq(_T_615, UInt<1>(0h0)) when _T_616 : node _T_617 = eq(_T_614, UInt<1>(0h0)) when _T_617 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_614, UInt<1>(0h1), "") : assert_85 node _address_ok_T = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _address_ok_T_1 = cvt(_address_ok_T) node _address_ok_T_2 = and(_address_ok_T_1, asSInt(UInt<17>(0h10000))) node _address_ok_T_3 = asSInt(_address_ok_T_2) node _address_ok_T_4 = eq(_address_ok_T_3, asSInt(UInt<1>(0h0))) node _address_ok_T_5 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _address_ok_T_6 = cvt(_address_ok_T_5) node _address_ok_T_7 = and(_address_ok_T_6, asSInt(UInt<29>(0h10000000))) node _address_ok_T_8 = asSInt(_address_ok_T_7) node _address_ok_T_9 = eq(_address_ok_T_8, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE : UInt<1>[2] connect _address_ok_WIRE[0], _address_ok_T_4 connect _address_ok_WIRE[1], _address_ok_T_9 node address_ok = or(_address_ok_WIRE[0], _address_ok_WIRE[1]) node _is_aligned_mask_T_2 = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _is_aligned_mask_T_3 = bits(_is_aligned_mask_T_2, 5, 0) node is_aligned_mask_1 = not(_is_aligned_mask_T_3) node _is_aligned_T_1 = and(io.in.b.bits.address, is_aligned_mask_1) node is_aligned_1 = eq(_is_aligned_T_1, UInt<1>(0h0)) node _mask_sizeOH_T_3 = or(io.in.b.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount_1 = bits(_mask_sizeOH_T_3, 1, 0) node _mask_sizeOH_T_4 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount_1) node _mask_sizeOH_T_5 = bits(_mask_sizeOH_T_4, 2, 0) node mask_sizeOH_1 = or(_mask_sizeOH_T_5, UInt<1>(0h1)) node mask_sub_sub_sub_0_1_1 = geq(io.in.b.bits.size, UInt<2>(0h3)) node mask_sub_sub_size_1 = bits(mask_sizeOH_1, 2, 2) node mask_sub_sub_bit_1 = bits(io.in.b.bits.address, 2, 2) node mask_sub_sub_nbit_1 = eq(mask_sub_sub_bit_1, UInt<1>(0h0)) node mask_sub_sub_0_2_1 = and(UInt<1>(0h1), mask_sub_sub_nbit_1) node _mask_sub_sub_acc_T_2 = and(mask_sub_sub_size_1, mask_sub_sub_0_2_1) node mask_sub_sub_0_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_2) node mask_sub_sub_1_2_1 = and(UInt<1>(0h1), mask_sub_sub_bit_1) node _mask_sub_sub_acc_T_3 = and(mask_sub_sub_size_1, mask_sub_sub_1_2_1) node mask_sub_sub_1_1_1 = or(mask_sub_sub_sub_0_1_1, _mask_sub_sub_acc_T_3) node mask_sub_size_1 = bits(mask_sizeOH_1, 1, 1) node mask_sub_bit_1 = bits(io.in.b.bits.address, 1, 1) node mask_sub_nbit_1 = eq(mask_sub_bit_1, UInt<1>(0h0)) node mask_sub_0_2_1 = and(mask_sub_sub_0_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_4 = and(mask_sub_size_1, mask_sub_0_2_1) node mask_sub_0_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_4) node mask_sub_1_2_1 = and(mask_sub_sub_0_2_1, mask_sub_bit_1) node _mask_sub_acc_T_5 = and(mask_sub_size_1, mask_sub_1_2_1) node mask_sub_1_1_1 = or(mask_sub_sub_0_1_1, _mask_sub_acc_T_5) node mask_sub_2_2_1 = and(mask_sub_sub_1_2_1, mask_sub_nbit_1) node _mask_sub_acc_T_6 = and(mask_sub_size_1, mask_sub_2_2_1) node mask_sub_2_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_6) node mask_sub_3_2_1 = and(mask_sub_sub_1_2_1, mask_sub_bit_1) node _mask_sub_acc_T_7 = and(mask_sub_size_1, mask_sub_3_2_1) node mask_sub_3_1_1 = or(mask_sub_sub_1_1_1, _mask_sub_acc_T_7) node mask_size_1 = bits(mask_sizeOH_1, 0, 0) node mask_bit_1 = bits(io.in.b.bits.address, 0, 0) node mask_nbit_1 = eq(mask_bit_1, UInt<1>(0h0)) node mask_eq_8 = and(mask_sub_0_2_1, mask_nbit_1) node _mask_acc_T_8 = and(mask_size_1, mask_eq_8) node mask_acc_8 = or(mask_sub_0_1_1, _mask_acc_T_8) node mask_eq_9 = and(mask_sub_0_2_1, mask_bit_1) node _mask_acc_T_9 = and(mask_size_1, mask_eq_9) node mask_acc_9 = or(mask_sub_0_1_1, _mask_acc_T_9) node mask_eq_10 = and(mask_sub_1_2_1, mask_nbit_1) node _mask_acc_T_10 = and(mask_size_1, mask_eq_10) node mask_acc_10 = or(mask_sub_1_1_1, _mask_acc_T_10) node mask_eq_11 = and(mask_sub_1_2_1, mask_bit_1) node _mask_acc_T_11 = and(mask_size_1, mask_eq_11) node mask_acc_11 = or(mask_sub_1_1_1, _mask_acc_T_11) node mask_eq_12 = and(mask_sub_2_2_1, mask_nbit_1) node _mask_acc_T_12 = and(mask_size_1, mask_eq_12) node mask_acc_12 = or(mask_sub_2_1_1, _mask_acc_T_12) node mask_eq_13 = and(mask_sub_2_2_1, mask_bit_1) node _mask_acc_T_13 = and(mask_size_1, mask_eq_13) node mask_acc_13 = or(mask_sub_2_1_1, _mask_acc_T_13) node mask_eq_14 = and(mask_sub_3_2_1, mask_nbit_1) node _mask_acc_T_14 = and(mask_size_1, mask_eq_14) node mask_acc_14 = or(mask_sub_3_1_1, _mask_acc_T_14) node mask_eq_15 = and(mask_sub_3_2_1, mask_bit_1) node _mask_acc_T_15 = and(mask_size_1, mask_eq_15) node mask_acc_15 = or(mask_sub_3_1_1, _mask_acc_T_15) node mask_lo_lo_1 = cat(mask_acc_9, mask_acc_8) node mask_lo_hi_1 = cat(mask_acc_11, mask_acc_10) node mask_lo_1 = cat(mask_lo_hi_1, mask_lo_lo_1) node mask_hi_lo_1 = cat(mask_acc_13, mask_acc_12) node mask_hi_hi_1 = cat(mask_acc_15, mask_acc_14) node mask_hi_1 = cat(mask_hi_hi_1, mask_hi_lo_1) node mask_1 = cat(mask_hi_1, mask_lo_1) node _legal_source_uncommonBits_T = or(io.in.b.bits.source, UInt<4>(0h0)) node legal_source_uncommonBits = bits(_legal_source_uncommonBits_T, 3, 0) node _legal_source_T = shr(io.in.b.bits.source, 4) node _legal_source_T_1 = eq(_legal_source_T, UInt<1>(0h0)) node _legal_source_T_2 = leq(UInt<1>(0h0), legal_source_uncommonBits) node _legal_source_T_3 = and(_legal_source_T_1, _legal_source_T_2) node _legal_source_T_4 = leq(legal_source_uncommonBits, UInt<4>(0h9)) node _legal_source_T_5 = and(_legal_source_T_3, _legal_source_T_4) wire _legal_source_WIRE : UInt<1>[1] connect _legal_source_WIRE[0], _legal_source_T_5 node legal_source = eq(UInt<1>(0h0), io.in.b.bits.source) node _T_618 = eq(io.in.b.bits.opcode, UInt<3>(0h6)) when _T_618 : node _T_619 = eq(UInt<3>(0h6), io.in.b.bits.size) node _T_620 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_621 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_622 = and(_T_620, _T_621) node _T_623 = or(UInt<1>(0h0), _T_622) node _T_624 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_625 = cvt(_T_624) node _T_626 = and(_T_625, asSInt(UInt<17>(0h10000))) node _T_627 = asSInt(_T_626) node _T_628 = eq(_T_627, asSInt(UInt<1>(0h0))) node _T_629 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_630 = cvt(_T_629) node _T_631 = and(_T_630, asSInt(UInt<29>(0h10000000))) node _T_632 = asSInt(_T_631) node _T_633 = eq(_T_632, asSInt(UInt<1>(0h0))) node _T_634 = or(_T_628, _T_633) node _T_635 = and(_T_623, _T_634) node _T_636 = or(UInt<1>(0h0), _T_635) node _T_637 = and(_T_619, _T_636) node _T_638 = asUInt(reset) node _T_639 = eq(_T_638, UInt<1>(0h0)) when _T_639 : node _T_640 = eq(_T_637, UInt<1>(0h0)) when _T_640 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Probe type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_86 assert(clock, _T_637, UInt<1>(0h1), "") : assert_86 node _T_641 = asUInt(reset) node _T_642 = eq(_T_641, UInt<1>(0h0)) when _T_642 : node _T_643 = eq(address_ok, UInt<1>(0h0)) when _T_643 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_87 assert(clock, address_ok, UInt<1>(0h1), "") : assert_87 node _T_644 = asUInt(reset) node _T_645 = eq(_T_644, UInt<1>(0h0)) when _T_645 : node _T_646 = eq(legal_source, UInt<1>(0h0)) when _T_646 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_88 assert(clock, legal_source, UInt<1>(0h1), "") : assert_88 node _T_647 = asUInt(reset) node _T_648 = eq(_T_647, UInt<1>(0h0)) when _T_648 : node _T_649 = eq(is_aligned_1, UInt<1>(0h0)) when _T_649 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_89 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_89 node _T_650 = leq(io.in.b.bits.param, UInt<2>(0h2)) node _T_651 = asUInt(reset) node _T_652 = eq(_T_651, UInt<1>(0h0)) when _T_652 : node _T_653 = eq(_T_650, UInt<1>(0h0)) when _T_653 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe carries invalid cap param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_90 assert(clock, _T_650, UInt<1>(0h1), "") : assert_90 node _T_654 = eq(io.in.b.bits.mask, mask_1) node _T_655 = asUInt(reset) node _T_656 = eq(_T_655, UInt<1>(0h0)) when _T_656 : node _T_657 = eq(_T_654, UInt<1>(0h0)) when _T_657 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_91 assert(clock, _T_654, UInt<1>(0h1), "") : assert_91 node _T_658 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_659 = asUInt(reset) node _T_660 = eq(_T_659, UInt<1>(0h0)) when _T_660 : node _T_661 = eq(_T_658, UInt<1>(0h0)) when _T_661 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Probe is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_658, UInt<1>(0h1), "") : assert_92 node _T_662 = eq(io.in.b.bits.opcode, UInt<3>(0h4)) when _T_662 : node _T_663 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_664 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_665 = and(_T_663, _T_664) node _T_666 = or(UInt<1>(0h0), _T_665) node _T_667 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_668 = cvt(_T_667) node _T_669 = and(_T_668, asSInt(UInt<17>(0h10000))) node _T_670 = asSInt(_T_669) node _T_671 = eq(_T_670, asSInt(UInt<1>(0h0))) node _T_672 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_673 = cvt(_T_672) node _T_674 = and(_T_673, asSInt(UInt<29>(0h10000000))) node _T_675 = asSInt(_T_674) node _T_676 = eq(_T_675, asSInt(UInt<1>(0h0))) node _T_677 = or(_T_671, _T_676) node _T_678 = and(_T_666, _T_677) node _T_679 = or(UInt<1>(0h0), _T_678) node _T_680 = and(UInt<1>(0h0), _T_679) node _T_681 = asUInt(reset) node _T_682 = eq(_T_681, UInt<1>(0h0)) when _T_682 : node _T_683 = eq(_T_680, UInt<1>(0h0)) when _T_683 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Get type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_93 assert(clock, _T_680, UInt<1>(0h1), "") : assert_93 node _T_684 = asUInt(reset) node _T_685 = eq(_T_684, UInt<1>(0h0)) when _T_685 : node _T_686 = eq(address_ok, UInt<1>(0h0)) when _T_686 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_94 assert(clock, address_ok, UInt<1>(0h1), "") : assert_94 node _T_687 = asUInt(reset) node _T_688 = eq(_T_687, UInt<1>(0h0)) when _T_688 : node _T_689 = eq(legal_source, UInt<1>(0h0)) when _T_689 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_95 assert(clock, legal_source, UInt<1>(0h1), "") : assert_95 node _T_690 = asUInt(reset) node _T_691 = eq(_T_690, UInt<1>(0h0)) when _T_691 : node _T_692 = eq(is_aligned_1, UInt<1>(0h0)) when _T_692 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_96 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_96 node _T_693 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_694 = asUInt(reset) node _T_695 = eq(_T_694, UInt<1>(0h0)) when _T_695 : node _T_696 = eq(_T_693, UInt<1>(0h0)) when _T_696 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_97 assert(clock, _T_693, UInt<1>(0h1), "") : assert_97 node _T_697 = eq(io.in.b.bits.mask, mask_1) node _T_698 = asUInt(reset) node _T_699 = eq(_T_698, UInt<1>(0h0)) when _T_699 : node _T_700 = eq(_T_697, UInt<1>(0h0)) when _T_700 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_697, UInt<1>(0h1), "") : assert_98 node _T_701 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_702 = asUInt(reset) node _T_703 = eq(_T_702, UInt<1>(0h0)) when _T_703 : node _T_704 = eq(_T_701, UInt<1>(0h0)) when _T_704 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Get is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_99 assert(clock, _T_701, UInt<1>(0h1), "") : assert_99 node _T_705 = eq(io.in.b.bits.opcode, UInt<1>(0h0)) when _T_705 : node _T_706 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_707 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_708 = and(_T_706, _T_707) node _T_709 = or(UInt<1>(0h0), _T_708) node _T_710 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_711 = cvt(_T_710) node _T_712 = and(_T_711, asSInt(UInt<17>(0h10000))) node _T_713 = asSInt(_T_712) node _T_714 = eq(_T_713, asSInt(UInt<1>(0h0))) node _T_715 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_716 = cvt(_T_715) node _T_717 = and(_T_716, asSInt(UInt<29>(0h10000000))) node _T_718 = asSInt(_T_717) node _T_719 = eq(_T_718, asSInt(UInt<1>(0h0))) node _T_720 = or(_T_714, _T_719) node _T_721 = and(_T_709, _T_720) node _T_722 = or(UInt<1>(0h0), _T_721) node _T_723 = and(UInt<1>(0h0), _T_722) node _T_724 = asUInt(reset) node _T_725 = eq(_T_724, UInt<1>(0h0)) when _T_725 : node _T_726 = eq(_T_723, UInt<1>(0h0)) when _T_726 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_100 assert(clock, _T_723, UInt<1>(0h1), "") : assert_100 node _T_727 = asUInt(reset) node _T_728 = eq(_T_727, UInt<1>(0h0)) when _T_728 : node _T_729 = eq(address_ok, UInt<1>(0h0)) when _T_729 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_101 assert(clock, address_ok, UInt<1>(0h1), "") : assert_101 node _T_730 = asUInt(reset) node _T_731 = eq(_T_730, UInt<1>(0h0)) when _T_731 : node _T_732 = eq(legal_source, UInt<1>(0h0)) when _T_732 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_102 assert(clock, legal_source, UInt<1>(0h1), "") : assert_102 node _T_733 = asUInt(reset) node _T_734 = eq(_T_733, UInt<1>(0h0)) when _T_734 : node _T_735 = eq(is_aligned_1, UInt<1>(0h0)) when _T_735 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_103 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_103 node _T_736 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_737 = asUInt(reset) node _T_738 = eq(_T_737, UInt<1>(0h0)) when _T_738 : node _T_739 = eq(_T_736, UInt<1>(0h0)) when _T_739 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_104 assert(clock, _T_736, UInt<1>(0h1), "") : assert_104 node _T_740 = eq(io.in.b.bits.mask, mask_1) node _T_741 = asUInt(reset) node _T_742 = eq(_T_741, UInt<1>(0h0)) when _T_742 : node _T_743 = eq(_T_740, UInt<1>(0h0)) when _T_743 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutFull contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_740, UInt<1>(0h1), "") : assert_105 node _T_744 = eq(io.in.b.bits.opcode, UInt<1>(0h1)) when _T_744 : node _T_745 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_746 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_747 = and(_T_745, _T_746) node _T_748 = or(UInt<1>(0h0), _T_747) node _T_749 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_750 = cvt(_T_749) node _T_751 = and(_T_750, asSInt(UInt<17>(0h10000))) node _T_752 = asSInt(_T_751) node _T_753 = eq(_T_752, asSInt(UInt<1>(0h0))) node _T_754 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_755 = cvt(_T_754) node _T_756 = and(_T_755, asSInt(UInt<29>(0h10000000))) node _T_757 = asSInt(_T_756) node _T_758 = eq(_T_757, asSInt(UInt<1>(0h0))) node _T_759 = or(_T_753, _T_758) node _T_760 = and(_T_748, _T_759) node _T_761 = or(UInt<1>(0h0), _T_760) node _T_762 = and(UInt<1>(0h0), _T_761) node _T_763 = asUInt(reset) node _T_764 = eq(_T_763, UInt<1>(0h0)) when _T_764 : node _T_765 = eq(_T_762, UInt<1>(0h0)) when _T_765 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_762, UInt<1>(0h1), "") : assert_106 node _T_766 = asUInt(reset) node _T_767 = eq(_T_766, UInt<1>(0h0)) when _T_767 : node _T_768 = eq(address_ok, UInt<1>(0h0)) when _T_768 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_107 assert(clock, address_ok, UInt<1>(0h1), "") : assert_107 node _T_769 = asUInt(reset) node _T_770 = eq(_T_769, UInt<1>(0h0)) when _T_770 : node _T_771 = eq(legal_source, UInt<1>(0h0)) when _T_771 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_108 assert(clock, legal_source, UInt<1>(0h1), "") : assert_108 node _T_772 = asUInt(reset) node _T_773 = eq(_T_772, UInt<1>(0h0)) when _T_773 : node _T_774 = eq(is_aligned_1, UInt<1>(0h0)) when _T_774 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_109 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_109 node _T_775 = eq(io.in.b.bits.param, UInt<1>(0h0)) node _T_776 = asUInt(reset) node _T_777 = eq(_T_776, UInt<1>(0h0)) when _T_777 : node _T_778 = eq(_T_775, UInt<1>(0h0)) when _T_778 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_110 assert(clock, _T_775, UInt<1>(0h1), "") : assert_110 node _T_779 = not(mask_1) node _T_780 = and(io.in.b.bits.mask, _T_779) node _T_781 = eq(_T_780, UInt<1>(0h0)) node _T_782 = asUInt(reset) node _T_783 = eq(_T_782, UInt<1>(0h0)) when _T_783 : node _T_784 = eq(_T_781, UInt<1>(0h0)) when _T_784 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel PutPartial contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_781, UInt<1>(0h1), "") : assert_111 node _T_785 = eq(io.in.b.bits.opcode, UInt<2>(0h2)) when _T_785 : node _T_786 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_787 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_788 = and(_T_786, _T_787) node _T_789 = or(UInt<1>(0h0), _T_788) node _T_790 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_791 = cvt(_T_790) node _T_792 = and(_T_791, asSInt(UInt<17>(0h10000))) node _T_793 = asSInt(_T_792) node _T_794 = eq(_T_793, asSInt(UInt<1>(0h0))) node _T_795 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_796 = cvt(_T_795) node _T_797 = and(_T_796, asSInt(UInt<29>(0h10000000))) node _T_798 = asSInt(_T_797) node _T_799 = eq(_T_798, asSInt(UInt<1>(0h0))) node _T_800 = or(_T_794, _T_799) node _T_801 = and(_T_789, _T_800) node _T_802 = or(UInt<1>(0h0), _T_801) node _T_803 = and(UInt<1>(0h0), _T_802) node _T_804 = asUInt(reset) node _T_805 = eq(_T_804, UInt<1>(0h0)) when _T_805 : node _T_806 = eq(_T_803, UInt<1>(0h0)) when _T_806 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Arithmetic type unsupported by master (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_112 assert(clock, _T_803, UInt<1>(0h1), "") : assert_112 node _T_807 = asUInt(reset) node _T_808 = eq(_T_807, UInt<1>(0h0)) when _T_808 : node _T_809 = eq(address_ok, UInt<1>(0h0)) when _T_809 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_113 assert(clock, address_ok, UInt<1>(0h1), "") : assert_113 node _T_810 = asUInt(reset) node _T_811 = eq(_T_810, UInt<1>(0h0)) when _T_811 : node _T_812 = eq(legal_source, UInt<1>(0h0)) when _T_812 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_114 assert(clock, legal_source, UInt<1>(0h1), "") : assert_114 node _T_813 = asUInt(reset) node _T_814 = eq(_T_813, UInt<1>(0h0)) when _T_814 : node _T_815 = eq(is_aligned_1, UInt<1>(0h0)) when _T_815 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_115 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_115 node _T_816 = leq(io.in.b.bits.param, UInt<3>(0h4)) node _T_817 = asUInt(reset) node _T_818 = eq(_T_817, UInt<1>(0h0)) when _T_818 : node _T_819 = eq(_T_816, UInt<1>(0h0)) when _T_819 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_116 assert(clock, _T_816, UInt<1>(0h1), "") : assert_116 node _T_820 = eq(io.in.b.bits.mask, mask_1) node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(_T_820, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Arithmetic contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_117 assert(clock, _T_820, UInt<1>(0h1), "") : assert_117 node _T_824 = eq(io.in.b.bits.opcode, UInt<2>(0h3)) when _T_824 : node _T_825 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_826 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_827 = and(_T_825, _T_826) node _T_828 = or(UInt<1>(0h0), _T_827) node _T_829 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_830 = cvt(_T_829) node _T_831 = and(_T_830, asSInt(UInt<17>(0h10000))) node _T_832 = asSInt(_T_831) node _T_833 = eq(_T_832, asSInt(UInt<1>(0h0))) node _T_834 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_835 = cvt(_T_834) node _T_836 = and(_T_835, asSInt(UInt<29>(0h10000000))) node _T_837 = asSInt(_T_836) node _T_838 = eq(_T_837, asSInt(UInt<1>(0h0))) node _T_839 = or(_T_833, _T_838) node _T_840 = and(_T_828, _T_839) node _T_841 = or(UInt<1>(0h0), _T_840) node _T_842 = and(UInt<1>(0h0), _T_841) node _T_843 = asUInt(reset) node _T_844 = eq(_T_843, UInt<1>(0h0)) when _T_844 : node _T_845 = eq(_T_842, UInt<1>(0h0)) when _T_845 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Logical type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_118 assert(clock, _T_842, UInt<1>(0h1), "") : assert_118 node _T_846 = asUInt(reset) node _T_847 = eq(_T_846, UInt<1>(0h0)) when _T_847 : node _T_848 = eq(address_ok, UInt<1>(0h0)) when _T_848 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_119 assert(clock, address_ok, UInt<1>(0h1), "") : assert_119 node _T_849 = asUInt(reset) node _T_850 = eq(_T_849, UInt<1>(0h0)) when _T_850 : node _T_851 = eq(legal_source, UInt<1>(0h0)) when _T_851 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_120 assert(clock, legal_source, UInt<1>(0h1), "") : assert_120 node _T_852 = asUInt(reset) node _T_853 = eq(_T_852, UInt<1>(0h0)) when _T_853 : node _T_854 = eq(is_aligned_1, UInt<1>(0h0)) when _T_854 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_121 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_121 node _T_855 = leq(io.in.b.bits.param, UInt<3>(0h3)) node _T_856 = asUInt(reset) node _T_857 = eq(_T_856, UInt<1>(0h0)) when _T_857 : node _T_858 = eq(_T_855, UInt<1>(0h0)) when _T_858 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical carries invalid opcode param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_122 assert(clock, _T_855, UInt<1>(0h1), "") : assert_122 node _T_859 = eq(io.in.b.bits.mask, mask_1) node _T_860 = asUInt(reset) node _T_861 = eq(_T_860, UInt<1>(0h0)) when _T_861 : node _T_862 = eq(_T_859, UInt<1>(0h0)) when _T_862 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Logical contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_123 assert(clock, _T_859, UInt<1>(0h1), "") : assert_123 node _T_863 = eq(io.in.b.bits.opcode, UInt<3>(0h5)) when _T_863 : node _T_864 = leq(UInt<1>(0h0), io.in.b.bits.size) node _T_865 = leq(io.in.b.bits.size, UInt<4>(0hc)) node _T_866 = and(_T_864, _T_865) node _T_867 = or(UInt<1>(0h0), _T_866) node _T_868 = xor(io.in.b.bits.address, UInt<28>(0h8000000)) node _T_869 = cvt(_T_868) node _T_870 = and(_T_869, asSInt(UInt<17>(0h10000))) node _T_871 = asSInt(_T_870) node _T_872 = eq(_T_871, asSInt(UInt<1>(0h0))) node _T_873 = xor(io.in.b.bits.address, UInt<32>(0h80000000)) node _T_874 = cvt(_T_873) node _T_875 = and(_T_874, asSInt(UInt<29>(0h10000000))) node _T_876 = asSInt(_T_875) node _T_877 = eq(_T_876, asSInt(UInt<1>(0h0))) node _T_878 = or(_T_872, _T_877) node _T_879 = and(_T_867, _T_878) node _T_880 = or(UInt<1>(0h0), _T_879) node _T_881 = and(UInt<1>(0h0), _T_880) node _T_882 = asUInt(reset) node _T_883 = eq(_T_882, UInt<1>(0h0)) when _T_883 : node _T_884 = eq(_T_881, UInt<1>(0h0)) when _T_884 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel carries Hint type unsupported by client (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_124 assert(clock, _T_881, UInt<1>(0h1), "") : assert_124 node _T_885 = asUInt(reset) node _T_886 = eq(_T_885, UInt<1>(0h0)) when _T_886 : node _T_887 = eq(address_ok, UInt<1>(0h0)) when _T_887 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_125 assert(clock, address_ok, UInt<1>(0h1), "") : assert_125 node _T_888 = asUInt(reset) node _T_889 = eq(_T_888, UInt<1>(0h0)) when _T_889 : node _T_890 = eq(legal_source, UInt<1>(0h0)) when _T_890 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint carries source that is not first source (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_126 assert(clock, legal_source, UInt<1>(0h1), "") : assert_126 node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(is_aligned_1, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_127 assert(clock, is_aligned_1, UInt<1>(0h1), "") : assert_127 node _T_894 = eq(io.in.b.bits.mask, mask_1) node _T_895 = asUInt(reset) node _T_896 = eq(_T_895, UInt<1>(0h0)) when _T_896 : node _T_897 = eq(_T_894, UInt<1>(0h0)) when _T_897 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint contains invalid mask (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_128 assert(clock, _T_894, UInt<1>(0h1), "") : assert_128 node _T_898 = eq(io.in.b.bits.corrupt, UInt<1>(0h0)) node _T_899 = asUInt(reset) node _T_900 = eq(_T_899, UInt<1>(0h0)) when _T_900 : node _T_901 = eq(_T_898, UInt<1>(0h0)) when _T_901 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel Hint is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_129 assert(clock, _T_898, UInt<1>(0h1), "") : assert_129 when io.in.c.valid : node _T_902 = leq(io.in.c.bits.opcode, UInt<3>(0h7)) node _T_903 = asUInt(reset) node _T_904 = eq(_T_903, UInt<1>(0h0)) when _T_904 : node _T_905 = eq(_T_902, UInt<1>(0h0)) when _T_905 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel has invalid opcode (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_130 assert(clock, _T_902, UInt<1>(0h1), "") : assert_130 node _source_ok_uncommonBits_T_2 = or(io.in.c.bits.source, UInt<4>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 3, 0) node _source_ok_T_12 = shr(io.in.c.bits.source, 4) node _source_ok_T_13 = eq(_source_ok_T_12, UInt<1>(0h0)) node _source_ok_T_14 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_15 = and(_source_ok_T_13, _source_ok_T_14) node _source_ok_T_16 = leq(source_ok_uncommonBits_2, UInt<4>(0h9)) node _source_ok_T_17 = and(_source_ok_T_15, _source_ok_T_16) wire _source_ok_WIRE_2 : UInt<1>[1] connect _source_ok_WIRE_2[0], _source_ok_T_17 node _is_aligned_mask_T_4 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _is_aligned_mask_T_5 = bits(_is_aligned_mask_T_4, 5, 0) node is_aligned_mask_2 = not(_is_aligned_mask_T_5) node _is_aligned_T_2 = and(io.in.c.bits.address, is_aligned_mask_2) node is_aligned_2 = eq(_is_aligned_T_2, UInt<1>(0h0)) node _address_ok_T_10 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _address_ok_T_11 = cvt(_address_ok_T_10) node _address_ok_T_12 = and(_address_ok_T_11, asSInt(UInt<17>(0h10000))) node _address_ok_T_13 = asSInt(_address_ok_T_12) node _address_ok_T_14 = eq(_address_ok_T_13, asSInt(UInt<1>(0h0))) node _address_ok_T_15 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _address_ok_T_16 = cvt(_address_ok_T_15) node _address_ok_T_17 = and(_address_ok_T_16, asSInt(UInt<29>(0h10000000))) node _address_ok_T_18 = asSInt(_address_ok_T_17) node _address_ok_T_19 = eq(_address_ok_T_18, asSInt(UInt<1>(0h0))) wire _address_ok_WIRE_1 : UInt<1>[2] connect _address_ok_WIRE_1[0], _address_ok_T_14 connect _address_ok_WIRE_1[1], _address_ok_T_19 node address_ok_1 = or(_address_ok_WIRE_1[0], _address_ok_WIRE_1[1]) node _uncommonBits_T_10 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 3, 0) node _T_906 = shr(io.in.c.bits.source, 4) node _T_907 = eq(_T_906, UInt<1>(0h0)) node _T_908 = leq(UInt<1>(0h0), uncommonBits_10) node _T_909 = and(_T_907, _T_908) node _T_910 = leq(uncommonBits_10, UInt<4>(0h9)) node _T_911 = and(_T_909, _T_910) node _T_912 = eq(_T_911, UInt<1>(0h0)) node _T_913 = xor(io.in.c.bits.address, UInt<1>(0h0)) node _T_914 = cvt(_T_913) node _T_915 = and(_T_914, asSInt(UInt<1>(0h0))) node _T_916 = asSInt(_T_915) node _T_917 = eq(_T_916, asSInt(UInt<1>(0h0))) node _T_918 = or(_T_912, _T_917) node _T_919 = asUInt(reset) node _T_920 = eq(_T_919, UInt<1>(0h0)) when _T_920 : node _T_921 = eq(_T_918, UInt<1>(0h0)) when _T_921 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_131 assert(clock, _T_918, UInt<1>(0h1), "") : assert_131 node _T_922 = eq(io.in.c.bits.opcode, UInt<3>(0h4)) when _T_922 : node _T_923 = asUInt(reset) node _T_924 = eq(_T_923, UInt<1>(0h0)) when _T_924 : node _T_925 = eq(address_ok_1, UInt<1>(0h0)) when _T_925 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_132 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_132 node _T_926 = asUInt(reset) node _T_927 = eq(_T_926, UInt<1>(0h0)) when _T_927 : node _T_928 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_928 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_133 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_133 node _T_929 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_930 = asUInt(reset) node _T_931 = eq(_T_930, UInt<1>(0h0)) when _T_931 : node _T_932 = eq(_T_929, UInt<1>(0h0)) when _T_932 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_134 assert(clock, _T_929, UInt<1>(0h1), "") : assert_134 node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(is_aligned_2, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_135 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_135 node _T_936 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(_T_936, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_136 assert(clock, _T_936, UInt<1>(0h1), "") : assert_136 node _T_940 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_941 = asUInt(reset) node _T_942 = eq(_T_941, UInt<1>(0h0)) when _T_942 : node _T_943 = eq(_T_940, UInt<1>(0h0)) when _T_943 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_137 assert(clock, _T_940, UInt<1>(0h1), "") : assert_137 node _T_944 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) when _T_944 : node _T_945 = asUInt(reset) node _T_946 = eq(_T_945, UInt<1>(0h0)) when _T_946 : node _T_947 = eq(address_ok_1, UInt<1>(0h0)) when _T_947 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_138 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_138 node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_139 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_139 node _T_951 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_140 assert(clock, _T_951, UInt<1>(0h1), "") : assert_140 node _T_955 = asUInt(reset) node _T_956 = eq(_T_955, UInt<1>(0h0)) when _T_956 : node _T_957 = eq(is_aligned_2, UInt<1>(0h0)) when _T_957 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_141 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_141 node _T_958 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_959 = asUInt(reset) node _T_960 = eq(_T_959, UInt<1>(0h0)) when _T_960 : node _T_961 = eq(_T_958, UInt<1>(0h0)) when _T_961 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ProbeAckData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_142 assert(clock, _T_958, UInt<1>(0h1), "") : assert_142 node _T_962 = eq(io.in.c.bits.opcode, UInt<3>(0h6)) when _T_962 : node _T_963 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_964 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_965 = and(_T_963, _T_964) node _uncommonBits_T_11 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 3, 0) node _T_966 = shr(io.in.c.bits.source, 4) node _T_967 = eq(_T_966, UInt<1>(0h0)) node _T_968 = leq(UInt<1>(0h0), uncommonBits_11) node _T_969 = and(_T_967, _T_968) node _T_970 = leq(uncommonBits_11, UInt<4>(0h9)) node _T_971 = and(_T_969, _T_970) node _T_972 = and(_T_965, _T_971) node _T_973 = or(UInt<1>(0h0), _T_972) node _T_974 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_975 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_976 = and(_T_974, _T_975) node _T_977 = or(UInt<1>(0h0), _T_976) node _T_978 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_979 = cvt(_T_978) node _T_980 = and(_T_979, asSInt(UInt<17>(0h10000))) node _T_981 = asSInt(_T_980) node _T_982 = eq(_T_981, asSInt(UInt<1>(0h0))) node _T_983 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_984 = cvt(_T_983) node _T_985 = and(_T_984, asSInt(UInt<29>(0h10000000))) node _T_986 = asSInt(_T_985) node _T_987 = eq(_T_986, asSInt(UInt<1>(0h0))) node _T_988 = or(_T_982, _T_987) node _T_989 = and(_T_977, _T_988) node _T_990 = or(UInt<1>(0h0), _T_989) node _T_991 = and(_T_973, _T_990) node _T_992 = asUInt(reset) node _T_993 = eq(_T_992, UInt<1>(0h0)) when _T_993 : node _T_994 = eq(_T_991, UInt<1>(0h0)) when _T_994 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_143 assert(clock, _T_991, UInt<1>(0h1), "") : assert_143 node _T_995 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_996 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_997 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_998 = and(_T_996, _T_997) node _T_999 = or(UInt<1>(0h0), _T_998) node _T_1000 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1001 = cvt(_T_1000) node _T_1002 = and(_T_1001, asSInt(UInt<17>(0h10000))) node _T_1003 = asSInt(_T_1002) node _T_1004 = eq(_T_1003, asSInt(UInt<1>(0h0))) node _T_1005 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1006 = cvt(_T_1005) node _T_1007 = and(_T_1006, asSInt(UInt<29>(0h10000000))) node _T_1008 = asSInt(_T_1007) node _T_1009 = eq(_T_1008, asSInt(UInt<1>(0h0))) node _T_1010 = or(_T_1004, _T_1009) node _T_1011 = and(_T_999, _T_1010) node _T_1012 = or(UInt<1>(0h0), _T_1011) node _T_1013 = and(_T_995, _T_1012) node _T_1014 = asUInt(reset) node _T_1015 = eq(_T_1014, UInt<1>(0h0)) when _T_1015 : node _T_1016 = eq(_T_1013, UInt<1>(0h0)) when _T_1016 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_144 assert(clock, _T_1013, UInt<1>(0h1), "") : assert_144 node _T_1017 = asUInt(reset) node _T_1018 = eq(_T_1017, UInt<1>(0h0)) when _T_1018 : node _T_1019 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1019 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_145 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_145 node _T_1020 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1021 = asUInt(reset) node _T_1022 = eq(_T_1021, UInt<1>(0h0)) when _T_1022 : node _T_1023 = eq(_T_1020, UInt<1>(0h0)) when _T_1023 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_146 assert(clock, _T_1020, UInt<1>(0h1), "") : assert_146 node _T_1024 = asUInt(reset) node _T_1025 = eq(_T_1024, UInt<1>(0h0)) when _T_1025 : node _T_1026 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1026 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_147 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_147 node _T_1027 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1028 = asUInt(reset) node _T_1029 = eq(_T_1028, UInt<1>(0h0)) when _T_1029 : node _T_1030 = eq(_T_1027, UInt<1>(0h0)) when _T_1030 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_148 assert(clock, _T_1027, UInt<1>(0h1), "") : assert_148 node _T_1031 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1032 = asUInt(reset) node _T_1033 = eq(_T_1032, UInt<1>(0h0)) when _T_1033 : node _T_1034 = eq(_T_1031, UInt<1>(0h0)) when _T_1034 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel Release is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_149 assert(clock, _T_1031, UInt<1>(0h1), "") : assert_149 node _T_1035 = eq(io.in.c.bits.opcode, UInt<3>(0h7)) when _T_1035 : node _T_1036 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1037 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1038 = and(_T_1036, _T_1037) node _uncommonBits_T_12 = or(io.in.c.bits.source, UInt<4>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 3, 0) node _T_1039 = shr(io.in.c.bits.source, 4) node _T_1040 = eq(_T_1039, UInt<1>(0h0)) node _T_1041 = leq(UInt<1>(0h0), uncommonBits_12) node _T_1042 = and(_T_1040, _T_1041) node _T_1043 = leq(uncommonBits_12, UInt<4>(0h9)) node _T_1044 = and(_T_1042, _T_1043) node _T_1045 = and(_T_1038, _T_1044) node _T_1046 = or(UInt<1>(0h0), _T_1045) node _T_1047 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1048 = leq(io.in.c.bits.size, UInt<3>(0h6)) node _T_1049 = and(_T_1047, _T_1048) node _T_1050 = or(UInt<1>(0h0), _T_1049) node _T_1051 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1052 = cvt(_T_1051) node _T_1053 = and(_T_1052, asSInt(UInt<17>(0h10000))) node _T_1054 = asSInt(_T_1053) node _T_1055 = eq(_T_1054, asSInt(UInt<1>(0h0))) node _T_1056 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1057 = cvt(_T_1056) node _T_1058 = and(_T_1057, asSInt(UInt<29>(0h10000000))) node _T_1059 = asSInt(_T_1058) node _T_1060 = eq(_T_1059, asSInt(UInt<1>(0h0))) node _T_1061 = or(_T_1055, _T_1060) node _T_1062 = and(_T_1050, _T_1061) node _T_1063 = or(UInt<1>(0h0), _T_1062) node _T_1064 = and(_T_1046, _T_1063) node _T_1065 = asUInt(reset) node _T_1066 = eq(_T_1065, UInt<1>(0h0)) when _T_1066 : node _T_1067 = eq(_T_1064, UInt<1>(0h0)) when _T_1067 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries ReleaseData type unsupported by manager (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_150 assert(clock, _T_1064, UInt<1>(0h1), "") : assert_150 node _T_1068 = eq(UInt<3>(0h6), io.in.c.bits.size) node _T_1069 = leq(UInt<1>(0h0), io.in.c.bits.size) node _T_1070 = leq(io.in.c.bits.size, UInt<4>(0hc)) node _T_1071 = and(_T_1069, _T_1070) node _T_1072 = or(UInt<1>(0h0), _T_1071) node _T_1073 = xor(io.in.c.bits.address, UInt<28>(0h8000000)) node _T_1074 = cvt(_T_1073) node _T_1075 = and(_T_1074, asSInt(UInt<17>(0h10000))) node _T_1076 = asSInt(_T_1075) node _T_1077 = eq(_T_1076, asSInt(UInt<1>(0h0))) node _T_1078 = xor(io.in.c.bits.address, UInt<32>(0h80000000)) node _T_1079 = cvt(_T_1078) node _T_1080 = and(_T_1079, asSInt(UInt<29>(0h10000000))) node _T_1081 = asSInt(_T_1080) node _T_1082 = eq(_T_1081, asSInt(UInt<1>(0h0))) node _T_1083 = or(_T_1077, _T_1082) node _T_1084 = and(_T_1072, _T_1083) node _T_1085 = or(UInt<1>(0h0), _T_1084) node _T_1086 = and(_T_1068, _T_1085) node _T_1087 = asUInt(reset) node _T_1088 = eq(_T_1087, UInt<1>(0h0)) when _T_1088 : node _T_1089 = eq(_T_1086, UInt<1>(0h0)) when _T_1089 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel carries Release from a client which does not support Probe (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_151 assert(clock, _T_1086, UInt<1>(0h1), "") : assert_151 node _T_1090 = asUInt(reset) node _T_1091 = eq(_T_1090, UInt<1>(0h0)) when _T_1091 : node _T_1092 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1092 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_152 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_152 node _T_1093 = geq(io.in.c.bits.size, UInt<2>(0h3)) node _T_1094 = asUInt(reset) node _T_1095 = eq(_T_1094, UInt<1>(0h0)) when _T_1095 : node _T_1096 = eq(_T_1093, UInt<1>(0h0)) when _T_1096 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData smaller than a beat (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_153 assert(clock, _T_1093, UInt<1>(0h1), "") : assert_153 node _T_1097 = asUInt(reset) node _T_1098 = eq(_T_1097, UInt<1>(0h0)) when _T_1098 : node _T_1099 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1099 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_154 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_154 node _T_1100 = leq(io.in.c.bits.param, UInt<3>(0h5)) node _T_1101 = asUInt(reset) node _T_1102 = eq(_T_1101, UInt<1>(0h0)) when _T_1102 : node _T_1103 = eq(_T_1100, UInt<1>(0h0)) when _T_1103 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel ReleaseData carries invalid report param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_155 assert(clock, _T_1100, UInt<1>(0h1), "") : assert_155 node _T_1104 = eq(io.in.c.bits.opcode, UInt<1>(0h0)) when _T_1104 : node _T_1105 = asUInt(reset) node _T_1106 = eq(_T_1105, UInt<1>(0h0)) when _T_1106 : node _T_1107 = eq(address_ok_1, UInt<1>(0h0)) when _T_1107 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_156 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_156 node _T_1108 = asUInt(reset) node _T_1109 = eq(_T_1108, UInt<1>(0h0)) when _T_1109 : node _T_1110 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1110 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_157 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_157 node _T_1111 = asUInt(reset) node _T_1112 = eq(_T_1111, UInt<1>(0h0)) when _T_1112 : node _T_1113 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1113 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_158 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_158 node _T_1114 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1115 = asUInt(reset) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) when _T_1116 : node _T_1117 = eq(_T_1114, UInt<1>(0h0)) when _T_1117 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_159 assert(clock, _T_1114, UInt<1>(0h1), "") : assert_159 node _T_1118 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1119 = asUInt(reset) node _T_1120 = eq(_T_1119, UInt<1>(0h0)) when _T_1120 : node _T_1121 = eq(_T_1118, UInt<1>(0h0)) when _T_1121 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_160 assert(clock, _T_1118, UInt<1>(0h1), "") : assert_160 node _T_1122 = eq(io.in.c.bits.opcode, UInt<1>(0h1)) when _T_1122 : node _T_1123 = asUInt(reset) node _T_1124 = eq(_T_1123, UInt<1>(0h0)) when _T_1124 : node _T_1125 = eq(address_ok_1, UInt<1>(0h0)) when _T_1125 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_161 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_161 node _T_1126 = asUInt(reset) node _T_1127 = eq(_T_1126, UInt<1>(0h0)) when _T_1127 : node _T_1128 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1128 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_162 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_162 node _T_1129 = asUInt(reset) node _T_1130 = eq(_T_1129, UInt<1>(0h0)) when _T_1130 : node _T_1131 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1131 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_163 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_163 node _T_1132 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1133 = asUInt(reset) node _T_1134 = eq(_T_1133, UInt<1>(0h0)) when _T_1134 : node _T_1135 = eq(_T_1132, UInt<1>(0h0)) when _T_1135 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel AccessAckData carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_164 assert(clock, _T_1132, UInt<1>(0h1), "") : assert_164 node _T_1136 = eq(io.in.c.bits.opcode, UInt<2>(0h2)) when _T_1136 : node _T_1137 = asUInt(reset) node _T_1138 = eq(_T_1137, UInt<1>(0h0)) when _T_1138 : node _T_1139 = eq(address_ok_1, UInt<1>(0h0)) when _T_1139 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries unmanaged address (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_165 assert(clock, address_ok_1, UInt<1>(0h1), "") : assert_165 node _T_1140 = asUInt(reset) node _T_1141 = eq(_T_1140, UInt<1>(0h0)) when _T_1141 : node _T_1142 = eq(_source_ok_WIRE_2[0], UInt<1>(0h0)) when _T_1142 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_166 assert(clock, _source_ok_WIRE_2[0], UInt<1>(0h1), "") : assert_166 node _T_1143 = asUInt(reset) node _T_1144 = eq(_T_1143, UInt<1>(0h0)) when _T_1144 : node _T_1145 = eq(is_aligned_2, UInt<1>(0h0)) when _T_1145 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck address not aligned to size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_167 assert(clock, is_aligned_2, UInt<1>(0h1), "") : assert_167 node _T_1146 = eq(io.in.c.bits.param, UInt<1>(0h0)) node _T_1147 = asUInt(reset) node _T_1148 = eq(_T_1147, UInt<1>(0h0)) when _T_1148 : node _T_1149 = eq(_T_1146, UInt<1>(0h0)) when _T_1149 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck carries invalid param (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_168 assert(clock, _T_1146, UInt<1>(0h1), "") : assert_168 node _T_1150 = eq(io.in.c.bits.corrupt, UInt<1>(0h0)) node _T_1151 = asUInt(reset) node _T_1152 = eq(_T_1151, UInt<1>(0h0)) when _T_1152 : node _T_1153 = eq(_T_1150, UInt<1>(0h0)) when _T_1153 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel HintAck is corrupt (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_169 assert(clock, _T_1150, UInt<1>(0h1), "") : assert_169 when io.in.e.valid : node sink_ok_1 = lt(io.in.e.bits.sink, UInt<4>(0h8)) node _T_1154 = asUInt(reset) node _T_1155 = eq(_T_1154, UInt<1>(0h0)) when _T_1155 : node _T_1156 = eq(sink_ok_1, UInt<1>(0h0)) when _T_1156 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channels carries invalid sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_170 assert(clock, sink_ok_1, UInt<1>(0h1), "") : assert_170 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1157 = eq(a_first, UInt<1>(0h0)) node _T_1158 = and(io.in.a.valid, _T_1157) when _T_1158 : node _T_1159 = eq(io.in.a.bits.opcode, opcode) node _T_1160 = asUInt(reset) node _T_1161 = eq(_T_1160, UInt<1>(0h0)) when _T_1161 : node _T_1162 = eq(_T_1159, UInt<1>(0h0)) when _T_1162 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_171 assert(clock, _T_1159, UInt<1>(0h1), "") : assert_171 node _T_1163 = eq(io.in.a.bits.param, param) node _T_1164 = asUInt(reset) node _T_1165 = eq(_T_1164, UInt<1>(0h0)) when _T_1165 : node _T_1166 = eq(_T_1163, UInt<1>(0h0)) when _T_1166 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_172 assert(clock, _T_1163, UInt<1>(0h1), "") : assert_172 node _T_1167 = eq(io.in.a.bits.size, size) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_173 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_173 node _T_1171 = eq(io.in.a.bits.source, source) node _T_1172 = asUInt(reset) node _T_1173 = eq(_T_1172, UInt<1>(0h0)) when _T_1173 : node _T_1174 = eq(_T_1171, UInt<1>(0h0)) when _T_1174 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_174 assert(clock, _T_1171, UInt<1>(0h1), "") : assert_174 node _T_1175 = eq(io.in.a.bits.address, address) node _T_1176 = asUInt(reset) node _T_1177 = eq(_T_1176, UInt<1>(0h0)) when _T_1177 : node _T_1178 = eq(_T_1175, UInt<1>(0h0)) when _T_1178 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_175 assert(clock, _T_1175, UInt<1>(0h1), "") : assert_175 node _T_1179 = and(io.in.a.ready, io.in.a.valid) node _T_1180 = and(_T_1179, a_first) when _T_1180 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1181 = eq(d_first, UInt<1>(0h0)) node _T_1182 = and(io.in.d.valid, _T_1181) when _T_1182 : node _T_1183 = eq(io.in.d.bits.opcode, opcode_1) node _T_1184 = asUInt(reset) node _T_1185 = eq(_T_1184, UInt<1>(0h0)) when _T_1185 : node _T_1186 = eq(_T_1183, UInt<1>(0h0)) when _T_1186 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_176 assert(clock, _T_1183, UInt<1>(0h1), "") : assert_176 node _T_1187 = eq(io.in.d.bits.param, param_1) node _T_1188 = asUInt(reset) node _T_1189 = eq(_T_1188, UInt<1>(0h0)) when _T_1189 : node _T_1190 = eq(_T_1187, UInt<1>(0h0)) when _T_1190 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_177 assert(clock, _T_1187, UInt<1>(0h1), "") : assert_177 node _T_1191 = eq(io.in.d.bits.size, size_1) node _T_1192 = asUInt(reset) node _T_1193 = eq(_T_1192, UInt<1>(0h0)) when _T_1193 : node _T_1194 = eq(_T_1191, UInt<1>(0h0)) when _T_1194 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_178 assert(clock, _T_1191, UInt<1>(0h1), "") : assert_178 node _T_1195 = eq(io.in.d.bits.source, source_1) node _T_1196 = asUInt(reset) node _T_1197 = eq(_T_1196, UInt<1>(0h0)) when _T_1197 : node _T_1198 = eq(_T_1195, UInt<1>(0h0)) when _T_1198 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_179 assert(clock, _T_1195, UInt<1>(0h1), "") : assert_179 node _T_1199 = eq(io.in.d.bits.sink, sink) node _T_1200 = asUInt(reset) node _T_1201 = eq(_T_1200, UInt<1>(0h0)) when _T_1201 : node _T_1202 = eq(_T_1199, UInt<1>(0h0)) when _T_1202 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_180 assert(clock, _T_1199, UInt<1>(0h1), "") : assert_180 node _T_1203 = eq(io.in.d.bits.denied, denied) node _T_1204 = asUInt(reset) node _T_1205 = eq(_T_1204, UInt<1>(0h0)) when _T_1205 : node _T_1206 = eq(_T_1203, UInt<1>(0h0)) when _T_1206 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_181 assert(clock, _T_1203, UInt<1>(0h1), "") : assert_181 node _T_1207 = and(io.in.d.ready, io.in.d.valid) node _T_1208 = and(_T_1207, d_first) when _T_1208 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied node _b_first_T = and(io.in.b.ready, io.in.b.valid) node _b_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.b.bits.size) node _b_first_beats1_decode_T_1 = bits(_b_first_beats1_decode_T, 5, 0) node _b_first_beats1_decode_T_2 = not(_b_first_beats1_decode_T_1) node b_first_beats1_decode = shr(_b_first_beats1_decode_T_2, 3) node _b_first_beats1_opdata_T = bits(io.in.b.bits.opcode, 2, 2) node b_first_beats1_opdata = eq(_b_first_beats1_opdata_T, UInt<1>(0h0)) node b_first_beats1 = mux(UInt<1>(0h0), b_first_beats1_decode, UInt<1>(0h0)) regreset b_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _b_first_counter1_T = sub(b_first_counter, UInt<1>(0h1)) node b_first_counter1 = tail(_b_first_counter1_T, 1) node b_first = eq(b_first_counter, UInt<1>(0h0)) node _b_first_last_T = eq(b_first_counter, UInt<1>(0h1)) node _b_first_last_T_1 = eq(b_first_beats1, UInt<1>(0h0)) node b_first_last = or(_b_first_last_T, _b_first_last_T_1) node b_first_done = and(b_first_last, _b_first_T) node _b_first_count_T = not(b_first_counter1) node b_first_count = and(b_first_beats1, _b_first_count_T) when _b_first_T : node _b_first_counter_T = mux(b_first, b_first_beats1, b_first_counter1) connect b_first_counter, _b_first_counter_T reg opcode_2 : UInt, clock reg param_2 : UInt, clock reg size_2 : UInt, clock reg source_2 : UInt, clock reg address_1 : UInt, clock node _T_1209 = eq(b_first, UInt<1>(0h0)) node _T_1210 = and(io.in.b.valid, _T_1209) when _T_1210 : node _T_1211 = eq(io.in.b.bits.opcode, opcode_2) node _T_1212 = asUInt(reset) node _T_1213 = eq(_T_1212, UInt<1>(0h0)) when _T_1213 : node _T_1214 = eq(_T_1211, UInt<1>(0h0)) when _T_1214 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_182 assert(clock, _T_1211, UInt<1>(0h1), "") : assert_182 node _T_1215 = eq(io.in.b.bits.param, param_2) node _T_1216 = asUInt(reset) node _T_1217 = eq(_T_1216, UInt<1>(0h0)) when _T_1217 : node _T_1218 = eq(_T_1215, UInt<1>(0h0)) when _T_1218 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_183 assert(clock, _T_1215, UInt<1>(0h1), "") : assert_183 node _T_1219 = eq(io.in.b.bits.size, size_2) node _T_1220 = asUInt(reset) node _T_1221 = eq(_T_1220, UInt<1>(0h0)) when _T_1221 : node _T_1222 = eq(_T_1219, UInt<1>(0h0)) when _T_1222 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_184 assert(clock, _T_1219, UInt<1>(0h1), "") : assert_184 node _T_1223 = eq(io.in.b.bits.source, source_2) node _T_1224 = asUInt(reset) node _T_1225 = eq(_T_1224, UInt<1>(0h0)) when _T_1225 : node _T_1226 = eq(_T_1223, UInt<1>(0h0)) when _T_1226 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_185 assert(clock, _T_1223, UInt<1>(0h1), "") : assert_185 node _T_1227 = eq(io.in.b.bits.address, address_1) node _T_1228 = asUInt(reset) node _T_1229 = eq(_T_1228, UInt<1>(0h0)) when _T_1229 : node _T_1230 = eq(_T_1227, UInt<1>(0h0)) when _T_1230 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel addresss changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_186 assert(clock, _T_1227, UInt<1>(0h1), "") : assert_186 node _T_1231 = and(io.in.b.ready, io.in.b.valid) node _T_1232 = and(_T_1231, b_first) when _T_1232 : connect opcode_2, io.in.b.bits.opcode connect param_2, io.in.b.bits.param connect size_2, io.in.b.bits.size connect source_2, io.in.b.bits.source connect address_1, io.in.b.bits.address node _c_first_T = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T reg opcode_3 : UInt, clock reg param_3 : UInt, clock reg size_3 : UInt, clock reg source_3 : UInt, clock reg address_2 : UInt, clock node _T_1233 = eq(c_first, UInt<1>(0h0)) node _T_1234 = and(io.in.c.valid, _T_1233) when _T_1234 : node _T_1235 = eq(io.in.c.bits.opcode, opcode_3) node _T_1236 = asUInt(reset) node _T_1237 = eq(_T_1236, UInt<1>(0h0)) when _T_1237 : node _T_1238 = eq(_T_1235, UInt<1>(0h0)) when _T_1238 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel opcode changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_187 assert(clock, _T_1235, UInt<1>(0h1), "") : assert_187 node _T_1239 = eq(io.in.c.bits.param, param_3) node _T_1240 = asUInt(reset) node _T_1241 = eq(_T_1240, UInt<1>(0h0)) when _T_1241 : node _T_1242 = eq(_T_1239, UInt<1>(0h0)) when _T_1242 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel param changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_188 assert(clock, _T_1239, UInt<1>(0h1), "") : assert_188 node _T_1243 = eq(io.in.c.bits.size, size_3) node _T_1244 = asUInt(reset) node _T_1245 = eq(_T_1244, UInt<1>(0h0)) when _T_1245 : node _T_1246 = eq(_T_1243, UInt<1>(0h0)) when _T_1246 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel size changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_189 assert(clock, _T_1243, UInt<1>(0h1), "") : assert_189 node _T_1247 = eq(io.in.c.bits.source, source_3) node _T_1248 = asUInt(reset) node _T_1249 = eq(_T_1248, UInt<1>(0h0)) when _T_1249 : node _T_1250 = eq(_T_1247, UInt<1>(0h0)) when _T_1250 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel source changed within multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_190 assert(clock, _T_1247, UInt<1>(0h1), "") : assert_190 node _T_1251 = eq(io.in.c.bits.address, address_2) node _T_1252 = asUInt(reset) node _T_1253 = eq(_T_1252, UInt<1>(0h0)) when _T_1253 : node _T_1254 = eq(_T_1251, UInt<1>(0h0)) when _T_1254 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel address changed with multibeat operation (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_191 assert(clock, _T_1251, UInt<1>(0h1), "") : assert_191 node _T_1255 = and(io.in.c.ready, io.in.c.valid) node _T_1256 = and(_T_1255, c_first) when _T_1256 : connect opcode_3, io.in.c.bits.opcode connect param_3, io.in.c.bits.param connect size_3, io.in.c.bits.size connect source_3, io.in.c.bits.source connect address_2, io.in.c.bits.address regreset inflight : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes : UInt<40>, clock, reset, UInt<40>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<10> connect a_set, UInt<10>(0h0) wire a_set_wo_ready : UInt<10> connect a_set_wo_ready, UInt<10>(0h0) wire a_opcodes_set : UInt<40> connect a_opcodes_set, UInt<40>(0h0) wire a_sizes_set : UInt<40> connect a_sizes_set, UInt<40>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1257 = and(io.in.a.valid, a_first_1) node _T_1258 = and(_T_1257, UInt<1>(0h1)) when _T_1258 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1259 = and(io.in.a.ready, io.in.a.valid) node _T_1260 = and(_T_1259, a_first_1) node _T_1261 = and(_T_1260, UInt<1>(0h1)) when _T_1261 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1262 = dshr(inflight, io.in.a.bits.source) node _T_1263 = bits(_T_1262, 0, 0) node _T_1264 = eq(_T_1263, UInt<1>(0h0)) node _T_1265 = asUInt(reset) node _T_1266 = eq(_T_1265, UInt<1>(0h0)) when _T_1266 : node _T_1267 = eq(_T_1264, UInt<1>(0h0)) when _T_1267 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_192 assert(clock, _T_1264, UInt<1>(0h1), "") : assert_192 wire d_clr : UInt<10> connect d_clr, UInt<10>(0h0) wire d_clr_wo_ready : UInt<10> connect d_clr_wo_ready, UInt<10>(0h0) wire d_opcodes_clr : UInt<40> connect d_opcodes_clr, UInt<40>(0h0) wire d_sizes_clr : UInt<40> connect d_sizes_clr, UInt<40>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1268 = and(io.in.d.valid, d_first_1) node _T_1269 = and(_T_1268, UInt<1>(0h1)) node _T_1270 = eq(d_release_ack, UInt<1>(0h0)) node _T_1271 = and(_T_1269, _T_1270) when _T_1271 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1272 = and(io.in.d.ready, io.in.d.valid) node _T_1273 = and(_T_1272, d_first_1) node _T_1274 = and(_T_1273, UInt<1>(0h1)) node _T_1275 = eq(d_release_ack, UInt<1>(0h0)) node _T_1276 = and(_T_1274, _T_1275) when _T_1276 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1277 = and(io.in.d.valid, d_first_1) node _T_1278 = and(_T_1277, UInt<1>(0h1)) node _T_1279 = eq(d_release_ack, UInt<1>(0h0)) node _T_1280 = and(_T_1278, _T_1279) when _T_1280 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1281 = dshr(inflight, io.in.d.bits.source) node _T_1282 = bits(_T_1281, 0, 0) node _T_1283 = or(_T_1282, same_cycle_resp) node _T_1284 = asUInt(reset) node _T_1285 = eq(_T_1284, UInt<1>(0h0)) when _T_1285 : node _T_1286 = eq(_T_1283, UInt<1>(0h0)) when _T_1286 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_193 assert(clock, _T_1283, UInt<1>(0h1), "") : assert_193 when same_cycle_resp : node _T_1287 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1288 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1289 = or(_T_1287, _T_1288) node _T_1290 = asUInt(reset) node _T_1291 = eq(_T_1290, UInt<1>(0h0)) when _T_1291 : node _T_1292 = eq(_T_1289, UInt<1>(0h0)) when _T_1292 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_194 assert(clock, _T_1289, UInt<1>(0h1), "") : assert_194 node _T_1293 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1294 = asUInt(reset) node _T_1295 = eq(_T_1294, UInt<1>(0h0)) when _T_1295 : node _T_1296 = eq(_T_1293, UInt<1>(0h0)) when _T_1296 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_195 assert(clock, _T_1293, UInt<1>(0h1), "") : assert_195 else : node _T_1297 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1298 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1299 = or(_T_1297, _T_1298) node _T_1300 = asUInt(reset) node _T_1301 = eq(_T_1300, UInt<1>(0h0)) when _T_1301 : node _T_1302 = eq(_T_1299, UInt<1>(0h0)) when _T_1302 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_196 assert(clock, _T_1299, UInt<1>(0h1), "") : assert_196 node _T_1303 = eq(io.in.d.bits.size, a_size_lookup) node _T_1304 = asUInt(reset) node _T_1305 = eq(_T_1304, UInt<1>(0h0)) when _T_1305 : node _T_1306 = eq(_T_1303, UInt<1>(0h0)) when _T_1306 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_197 assert(clock, _T_1303, UInt<1>(0h1), "") : assert_197 node _T_1307 = and(io.in.d.valid, d_first_1) node _T_1308 = and(_T_1307, a_first_1) node _T_1309 = and(_T_1308, io.in.a.valid) node _T_1310 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1311 = and(_T_1309, _T_1310) node _T_1312 = eq(d_release_ack, UInt<1>(0h0)) node _T_1313 = and(_T_1311, _T_1312) when _T_1313 : node _T_1314 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1315 = or(_T_1314, io.in.a.ready) node _T_1316 = asUInt(reset) node _T_1317 = eq(_T_1316, UInt<1>(0h0)) when _T_1317 : node _T_1318 = eq(_T_1315, UInt<1>(0h0)) when _T_1318 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_198 assert(clock, _T_1315, UInt<1>(0h1), "") : assert_198 node _T_1319 = neq(a_set_wo_ready, d_clr_wo_ready) node _T_1320 = orr(a_set_wo_ready) node _T_1321 = eq(_T_1320, UInt<1>(0h0)) node _T_1322 = or(_T_1319, _T_1321) node _T_1323 = asUInt(reset) node _T_1324 = eq(_T_1323, UInt<1>(0h0)) when _T_1324 : node _T_1325 = eq(_T_1322, UInt<1>(0h0)) when _T_1325 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_199 assert(clock, _T_1322, UInt<1>(0h1), "") : assert_199 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_82 node _T_1326 = orr(inflight) node _T_1327 = eq(_T_1326, UInt<1>(0h0)) node _T_1328 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1329 = or(_T_1327, _T_1328) node _T_1330 = lt(watchdog, plusarg_reader.out) node _T_1331 = or(_T_1329, _T_1330) node _T_1332 = asUInt(reset) node _T_1333 = eq(_T_1332, UInt<1>(0h0)) when _T_1333 : node _T_1334 = eq(_T_1331, UInt<1>(0h0)) when _T_1334 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_200 assert(clock, _T_1331, UInt<1>(0h1), "") : assert_200 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1335 = and(io.in.a.ready, io.in.a.valid) node _T_1336 = and(io.in.d.ready, io.in.d.valid) node _T_1337 = or(_T_1335, _T_1336) when _T_1337 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<10>, clock, reset, UInt<10>(0h0) regreset inflight_opcodes_1 : UInt<40>, clock, reset, UInt<40>(0h0) regreset inflight_sizes_1 : UInt<40>, clock, reset, UInt<40>(0h0) node _c_first_T_1 = and(io.in.c.ready, io.in.c.valid) node _c_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.c.bits.size) node _c_first_beats1_decode_T_4 = bits(_c_first_beats1_decode_T_3, 5, 0) node _c_first_beats1_decode_T_5 = not(_c_first_beats1_decode_T_4) node c_first_beats1_decode_1 = shr(_c_first_beats1_decode_T_5, 3) node c_first_beats1_opdata_1 = bits(io.in.c.bits.opcode, 0, 0) node c_first_beats1_1 = mux(c_first_beats1_opdata_1, c_first_beats1_decode_1, UInt<1>(0h0)) regreset c_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T_1 = sub(c_first_counter_1, UInt<1>(0h1)) node c_first_counter1_1 = tail(_c_first_counter1_T_1, 1) node c_first_1 = eq(c_first_counter_1, UInt<1>(0h0)) node _c_first_last_T_2 = eq(c_first_counter_1, UInt<1>(0h1)) node _c_first_last_T_3 = eq(c_first_beats1_1, UInt<1>(0h0)) node c_first_last_1 = or(_c_first_last_T_2, _c_first_last_T_3) node c_first_done_1 = and(c_first_last_1, _c_first_T_1) node _c_first_count_T_1 = not(c_first_counter1_1) node c_first_count_1 = and(c_first_beats1_1, _c_first_count_T_1) when _c_first_T_1 : node _c_first_counter_T_1 = mux(c_first_1, c_first_beats1_1, c_first_counter1_1) connect c_first_counter_1, _c_first_counter_T_1 node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<10> connect c_set, UInt<10>(0h0) wire c_set_wo_ready : UInt<10> connect c_set_wo_ready, UInt<10>(0h0) wire c_opcodes_set : UInt<40> connect c_opcodes_set, UInt<40>(0h0) wire c_sizes_set : UInt<40> connect c_sizes_set, UInt<40>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) node _T_1338 = and(io.in.c.valid, c_first_1) node _T_1339 = bits(io.in.c.bits.opcode, 2, 2) node _T_1340 = bits(io.in.c.bits.opcode, 1, 1) node _T_1341 = and(_T_1339, _T_1340) node _T_1342 = and(_T_1338, _T_1341) when _T_1342 : node _c_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T node _T_1343 = and(io.in.c.ready, io.in.c.valid) node _T_1344 = and(_T_1343, c_first_1) node _T_1345 = bits(io.in.c.bits.opcode, 2, 2) node _T_1346 = bits(io.in.c.bits.opcode, 1, 1) node _T_1347 = and(_T_1345, _T_1346) node _T_1348 = and(_T_1344, _T_1347) when _T_1348 : node _c_set_T = dshl(UInt<1>(0h1), io.in.c.bits.source) connect c_set, _c_set_T node _c_opcodes_set_interm_T = dshl(io.in.c.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 node _c_sizes_set_interm_T = dshl(io.in.c.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 node _c_opcodes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 node _c_sizes_set_T = dshl(io.in.c.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 node _T_1349 = dshr(inflight_1, io.in.c.bits.source) node _T_1350 = bits(_T_1349, 0, 0) node _T_1351 = eq(_T_1350, UInt<1>(0h0)) node _T_1352 = asUInt(reset) node _T_1353 = eq(_T_1352, UInt<1>(0h0)) when _T_1353 : node _T_1354 = eq(_T_1351, UInt<1>(0h0)) when _T_1354 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_201 assert(clock, _T_1351, UInt<1>(0h1), "") : assert_201 node _c_probe_ack_T = eq(io.in.c.bits.opcode, UInt<3>(0h4)) node _c_probe_ack_T_1 = eq(io.in.c.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<10> connect d_clr_1, UInt<10>(0h0) wire d_clr_wo_ready_1 : UInt<10> connect d_clr_wo_ready_1, UInt<10>(0h0) wire d_opcodes_clr_1 : UInt<40> connect d_opcodes_clr_1, UInt<40>(0h0) wire d_sizes_clr_1 : UInt<40> connect d_sizes_clr_1, UInt<40>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1355 = and(io.in.d.valid, d_first_2) node _T_1356 = and(_T_1355, UInt<1>(0h1)) node _T_1357 = and(_T_1356, d_release_ack_1) when _T_1357 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1358 = and(io.in.d.ready, io.in.d.valid) node _T_1359 = and(_T_1358, d_first_2) node _T_1360 = and(_T_1359, UInt<1>(0h1)) node _T_1361 = and(_T_1360, d_release_ack_1) when _T_1361 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1362 = and(io.in.d.valid, d_first_2) node _T_1363 = and(_T_1362, UInt<1>(0h1)) node _T_1364 = and(_T_1363, d_release_ack_1) when _T_1364 : node _same_cycle_resp_T_3 = and(io.in.c.valid, c_first_1) node _same_cycle_resp_T_4 = bits(io.in.c.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(io.in.c.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) node _same_cycle_resp_T_8 = eq(io.in.c.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1365 = dshr(inflight_1, io.in.d.bits.source) node _T_1366 = bits(_T_1365, 0, 0) node _T_1367 = or(_T_1366, same_cycle_resp_1) node _T_1368 = asUInt(reset) node _T_1369 = eq(_T_1368, UInt<1>(0h0)) when _T_1369 : node _T_1370 = eq(_T_1367, UInt<1>(0h0)) when _T_1370 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_202 assert(clock, _T_1367, UInt<1>(0h1), "") : assert_202 when same_cycle_resp_1 : node _T_1371 = eq(io.in.d.bits.size, io.in.c.bits.size) node _T_1372 = asUInt(reset) node _T_1373 = eq(_T_1372, UInt<1>(0h0)) when _T_1373 : node _T_1374 = eq(_T_1371, UInt<1>(0h0)) when _T_1374 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_203 assert(clock, _T_1371, UInt<1>(0h1), "") : assert_203 else : node _T_1375 = eq(io.in.d.bits.size, c_size_lookup) node _T_1376 = asUInt(reset) node _T_1377 = eq(_T_1376, UInt<1>(0h0)) when _T_1377 : node _T_1378 = eq(_T_1375, UInt<1>(0h0)) when _T_1378 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_204 assert(clock, _T_1375, UInt<1>(0h1), "") : assert_204 node _T_1379 = and(io.in.d.valid, d_first_2) node _T_1380 = and(_T_1379, c_first_1) node _T_1381 = and(_T_1380, io.in.c.valid) node _T_1382 = eq(io.in.c.bits.source, io.in.d.bits.source) node _T_1383 = and(_T_1381, _T_1382) node _T_1384 = and(_T_1383, d_release_ack_1) node _T_1385 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1386 = and(_T_1384, _T_1385) when _T_1386 : node _T_1387 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1388 = or(_T_1387, io.in.c.ready) node _T_1389 = asUInt(reset) node _T_1390 = eq(_T_1389, UInt<1>(0h0)) when _T_1390 : node _T_1391 = eq(_T_1388, UInt<1>(0h0)) when _T_1391 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_205 assert(clock, _T_1388, UInt<1>(0h1), "") : assert_205 node _T_1392 = orr(c_set_wo_ready) when _T_1392 : node _T_1393 = neq(c_set_wo_ready, d_clr_wo_ready_1) node _T_1394 = asUInt(reset) node _T_1395 = eq(_T_1394, UInt<1>(0h0)) when _T_1395 : node _T_1396 = eq(_T_1393, UInt<1>(0h0)) when _T_1396 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' and 'D' concurrent, despite minlatency > 0 (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_206 assert(clock, _T_1393, UInt<1>(0h1), "") : assert_206 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_83 node _T_1397 = orr(inflight_1) node _T_1398 = eq(_T_1397, UInt<1>(0h0)) node _T_1399 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1400 = or(_T_1398, _T_1399) node _T_1401 = lt(watchdog_1, plusarg_reader_1.out) node _T_1402 = or(_T_1400, _T_1401) node _T_1403 = asUInt(reset) node _T_1404 = eq(_T_1403, UInt<1>(0h0)) when _T_1404 : node _T_1405 = eq(_T_1402, UInt<1>(0h0)) when _T_1405 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_207 assert(clock, _T_1402, UInt<1>(0h1), "") : assert_207 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 node _T_1406 = and(io.in.c.ready, io.in.c.valid) node _T_1407 = and(io.in.d.ready, io.in.d.valid) node _T_1408 = or(_T_1406, _T_1407) when _T_1408 : connect watchdog_1, UInt<1>(0h0) regreset inflight_2 : UInt<8>, clock, reset, UInt<8>(0h0) node _d_first_T_3 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_9 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_10 = bits(_d_first_beats1_decode_T_9, 5, 0) node _d_first_beats1_decode_T_11 = not(_d_first_beats1_decode_T_10) node d_first_beats1_decode_3 = shr(_d_first_beats1_decode_T_11, 3) node d_first_beats1_opdata_3 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_3 = mux(d_first_beats1_opdata_3, d_first_beats1_decode_3, UInt<1>(0h0)) regreset d_first_counter_3 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_3 = sub(d_first_counter_3, UInt<1>(0h1)) node d_first_counter1_3 = tail(_d_first_counter1_T_3, 1) node d_first_3 = eq(d_first_counter_3, UInt<1>(0h0)) node _d_first_last_T_6 = eq(d_first_counter_3, UInt<1>(0h1)) node _d_first_last_T_7 = eq(d_first_beats1_3, UInt<1>(0h0)) node d_first_last_3 = or(_d_first_last_T_6, _d_first_last_T_7) node d_first_done_3 = and(d_first_last_3, _d_first_T_3) node _d_first_count_T_3 = not(d_first_counter1_3) node d_first_count_3 = and(d_first_beats1_3, _d_first_count_T_3) when _d_first_T_3 : node _d_first_counter_T_3 = mux(d_first_3, d_first_beats1_3, d_first_counter1_3) connect d_first_counter_3, _d_first_counter_T_3 wire d_set : UInt<8> connect d_set, UInt<8>(0h0) node _T_1409 = and(io.in.d.ready, io.in.d.valid) node _T_1410 = and(_T_1409, d_first_3) node _T_1411 = bits(io.in.d.bits.opcode, 2, 2) node _T_1412 = bits(io.in.d.bits.opcode, 1, 1) node _T_1413 = eq(_T_1412, UInt<1>(0h0)) node _T_1414 = and(_T_1411, _T_1413) node _T_1415 = and(_T_1410, _T_1414) when _T_1415 : node _d_set_T = dshl(UInt<1>(0h1), io.in.d.bits.sink) connect d_set, _d_set_T node _T_1416 = dshr(inflight_2, io.in.d.bits.sink) node _T_1417 = bits(_T_1416, 0, 0) node _T_1418 = eq(_T_1417, UInt<1>(0h0)) node _T_1419 = asUInt(reset) node _T_1420 = eq(_T_1419, UInt<1>(0h0)) when _T_1420 : node _T_1421 = eq(_T_1418, UInt<1>(0h0)) when _T_1421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel re-used a sink ID (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:52 assert(cond, message)\n") : printf_208 assert(clock, _T_1418, UInt<1>(0h1), "") : assert_208 wire e_clr : UInt<8> connect e_clr, UInt<8>(0h0) node _T_1422 = and(io.in.e.ready, io.in.e.valid) node _T_1423 = and(_T_1422, UInt<1>(0h1)) node _T_1424 = and(_T_1423, UInt<1>(0h1)) when _T_1424 : node _e_clr_T = dshl(UInt<1>(0h1), io.in.e.bits.sink) connect e_clr, _e_clr_T node _T_1425 = or(d_set, inflight_2) node _T_1426 = dshr(_T_1425, io.in.e.bits.sink) node _T_1427 = bits(_T_1426, 0, 0) node _T_1428 = asUInt(reset) node _T_1429 = eq(_T_1428, UInt<1>(0h0)) when _T_1429 : node _T_1430 = eq(_T_1427, UInt<1>(0h0)) when _T_1430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel acknowledged for nothing inflight (connected at generators/rocket-chip-inclusive-cache/design/craft/inclusivecache/src/Configs.scala:132:34)\n at Monitor.scala:45 assert(cond, message)\n") : printf_209 assert(clock, _T_1427, UInt<1>(0h1), "") : assert_209 node _inflight_T_6 = or(inflight_2, d_set) node _inflight_T_7 = not(e_clr) node _inflight_T_8 = and(_inflight_T_6, _inflight_T_7) connect inflight_2, _inflight_T_8
module TLMonitor_41( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_c_ready, // @[Monitor.scala:20:14] input io_in_c_valid, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_c_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_c_bits_source, // @[Monitor.scala:20:14] input [31:0] io_in_c_bits_address, // @[Monitor.scala:20:14] input [63:0] io_in_c_bits_data, // @[Monitor.scala:20:14] input io_in_c_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [1:0] io_in_d_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [3:0] io_in_d_bits_source, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_sink, // @[Monitor.scala:20:14] input io_in_d_bits_denied, // @[Monitor.scala:20:14] input [63:0] io_in_d_bits_data, // @[Monitor.scala:20:14] input io_in_d_bits_corrupt, // @[Monitor.scala:20:14] input io_in_e_valid, // @[Monitor.scala:20:14] input [2:0] io_in_e_bits_sink // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_c_ready_0 = io_in_c_ready; // @[Monitor.scala:36:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Monitor.scala:36:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Monitor.scala:36:7] wire [63:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Monitor.scala:36:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [1:0] io_in_d_bits_param_0 = io_in_d_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [3:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_sink_0 = io_in_d_bits_sink; // @[Monitor.scala:36:7] wire io_in_d_bits_denied_0 = io_in_d_bits_denied; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data_0 = io_in_d_bits_data; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt_0 = io_in_d_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_opcode = 3'h0; // @[Monitor.scala:36:7] wire [2:0] io_in_b_bits_size = 3'h0; // @[Monitor.scala:36:7] wire [2:0] _mask_sizeOH_T_3 = 3'h0; // @[Misc.scala:202:34] wire [2:0] b_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] b_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _b_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] b_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _b_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire io_in_b_valid = 1'h0; // @[Monitor.scala:36:7] wire io_in_b_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire _source_ok_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_6 = 1'h0; // @[Parameters.scala:54:10] wire _address_ok_T_4 = 1'h0; // @[Parameters.scala:137:59] wire _address_ok_T_9 = 1'h0; // @[Parameters.scala:137:59] wire _address_ok_WIRE_0 = 1'h0; // @[Parameters.scala:612:40] wire _address_ok_WIRE_1 = 1'h0; // @[Parameters.scala:612:40] wire address_ok = 1'h0; // @[Parameters.scala:636:64] wire mask_sub_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:206:21] wire mask_sub_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire mask_sub_sub_bit_1 = 1'h0; // @[Misc.scala:210:26] wire _mask_sub_sub_acc_T_2 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_sub_acc_T_3 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_size_1 = 1'h0; // @[Misc.scala:209:26] wire mask_sub_bit_1 = 1'h0; // @[Misc.scala:210:26] wire _mask_sub_acc_T_4 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_0_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_1_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_5 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_1_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_2_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_6 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_2_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_sub_3_2_1 = 1'h0; // @[Misc.scala:214:27] wire _mask_sub_acc_T_7 = 1'h0; // @[Misc.scala:215:38] wire mask_sub_3_1_1 = 1'h0; // @[Misc.scala:215:29] wire mask_bit_1 = 1'h0; // @[Misc.scala:210:26] wire mask_eq_9 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_9 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_9 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_10 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_10 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_10 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_11 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_11 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_11 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_12 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_12 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_12 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_13 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_13 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_13 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_14 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_14 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_14 = 1'h0; // @[Misc.scala:215:29] wire mask_eq_15 = 1'h0; // @[Misc.scala:214:27] wire _mask_acc_T_15 = 1'h0; // @[Misc.scala:215:38] wire mask_acc_15 = 1'h0; // @[Misc.scala:215:29] wire _legal_source_T = 1'h0; // @[Parameters.scala:54:10] wire _source_ok_T_12 = 1'h0; // @[Parameters.scala:54:10] wire _b_first_T = 1'h0; // @[Decoupled.scala:51:35] wire _b_first_beats1_opdata_T = 1'h0; // @[Edges.scala:97:37] wire _b_first_last_T = 1'h0; // @[Edges.scala:232:25] wire b_first_done = 1'h0; // @[Edges.scala:233:22] wire io_in_b_ready = 1'h1; // @[Monitor.scala:36:7] wire io_in_e_ready = 1'h1; // @[Monitor.scala:36:7] wire _source_ok_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _source_ok_T_7 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_8 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok = 1'h1; // @[Monitor.scala:309:31] wire is_aligned_1 = 1'h1; // @[Edges.scala:21:24] wire mask_sub_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_sub_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire mask_sub_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_sub_0_2_1 = 1'h1; // @[Misc.scala:214:27] wire mask_size_1 = 1'h1; // @[Misc.scala:209:26] wire mask_nbit_1 = 1'h1; // @[Misc.scala:211:20] wire mask_eq_8 = 1'h1; // @[Misc.scala:214:27] wire _mask_acc_T_8 = 1'h1; // @[Misc.scala:215:38] wire mask_acc_8 = 1'h1; // @[Misc.scala:215:29] wire _legal_source_T_1 = 1'h1; // @[Parameters.scala:54:32] wire _legal_source_T_2 = 1'h1; // @[Parameters.scala:56:32] wire _legal_source_T_3 = 1'h1; // @[Parameters.scala:54:67] wire _legal_source_T_4 = 1'h1; // @[Parameters.scala:57:20] wire _legal_source_T_5 = 1'h1; // @[Parameters.scala:56:48] wire _legal_source_WIRE_0 = 1'h1; // @[Parameters.scala:1138:31] wire legal_source = 1'h1; // @[Monitor.scala:168:113] wire _source_ok_T_13 = 1'h1; // @[Parameters.scala:54:32] wire _source_ok_T_14 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:54:67] wire sink_ok_1 = 1'h1; // @[Monitor.scala:367:31] wire b_first_beats1_opdata = 1'h1; // @[Edges.scala:97:28] wire b_first = 1'h1; // @[Edges.scala:231:25] wire _b_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire b_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] b_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _b_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [31:0] io_in_b_bits_address = 32'h0; // @[Monitor.scala:36:7] wire [31:0] _is_aligned_T_1 = 32'h0; // @[Edges.scala:21:16] wire [3:0] io_in_b_bits_source = 4'h0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_9 = 4'h0; // @[Parameters.scala:52:29] wire [3:0] uncommonBits_9 = 4'h0; // @[Parameters.scala:52:56] wire [3:0] mask_hi_1 = 4'h0; // @[Misc.scala:222:10] wire [3:0] _legal_source_uncommonBits_T = 4'h0; // @[Parameters.scala:52:29] wire [3:0] legal_source_uncommonBits = 4'h0; // @[Parameters.scala:52:56] wire [1:0] io_in_b_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [1:0] mask_sizeOH_shiftAmount_1 = 2'h0; // @[OneHot.scala:64:49] wire [1:0] mask_lo_hi_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo_1 = 2'h0; // @[Misc.scala:222:10] wire [1:0] mask_hi_hi_1 = 2'h0; // @[Misc.scala:222:10] wire [7:0] io_in_b_bits_mask = 8'h0; // @[Monitor.scala:36:7] wire [63:0] io_in_b_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] _mask_sizeOH_T_5 = 3'h1; // @[OneHot.scala:65:27] wire [2:0] mask_sizeOH_1 = 3'h1; // @[Misc.scala:202:81] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [5:0] is_aligned_mask_1 = 6'h0; // @[package.scala:243:46] wire [5:0] _b_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _is_aligned_mask_T_3 = 6'h3F; // @[package.scala:243:76] wire [5:0] _b_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _is_aligned_mask_T_2 = 13'h3F; // @[package.scala:243:71] wire [12:0] _b_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [7:0] mask_1 = 8'h1; // @[Misc.scala:222:10] wire [3:0] _mask_sizeOH_T_4 = 4'h1; // @[OneHot.scala:65:12] wire [3:0] mask_lo_1 = 4'h1; // @[Misc.scala:222:10] wire [1:0] mask_lo_lo_1 = 2'h1; // @[Misc.scala:222:10] wire [32:0] _address_ok_T_6 = 33'h80000000; // @[Parameters.scala:137:41] wire [32:0] _address_ok_T_7 = 33'h80000000; // @[Parameters.scala:137:46] wire [32:0] _address_ok_T_8 = 33'h80000000; // @[Parameters.scala:137:46] wire [31:0] _address_ok_T_5 = 32'h80000000; // @[Parameters.scala:137:31] wire [32:0] _address_ok_T_1 = 33'h8000000; // @[Parameters.scala:137:41] wire [32:0] _address_ok_T_2 = 33'h8000000; // @[Parameters.scala:137:46] wire [32:0] _address_ok_T_3 = 33'h8000000; // @[Parameters.scala:137:46] wire [31:0] _address_ok_T = 32'h8000000; // @[Parameters.scala:137:31] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [3:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_2 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_10 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_11 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _uncommonBits_T_12 = io_in_c_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] _source_ok_uncommonBits_T_1 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [3:0] source_ok_uncommonBits = _source_ok_uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_4 = source_ok_uncommonBits < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_5 = _source_ok_T_4; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_0 = _source_ok_T_5; // @[Parameters.scala:1138:31] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T = {26'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 32'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [3:0] uncommonBits = _uncommonBits_T; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_1 = _uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_2 = _uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_3 = _uncommonBits_T_3; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_4 = _uncommonBits_T_4; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_5 = _uncommonBits_T_5; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_6 = _uncommonBits_T_6; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_7 = _uncommonBits_T_7; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_8 = _uncommonBits_T_8; // @[Parameters.scala:52:{29,56}] wire [3:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_10 = source_ok_uncommonBits_1 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_11 = _source_ok_T_10; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_1_0 = _source_ok_T_11; // @[Parameters.scala:1138:31] wire [3:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_16 = source_ok_uncommonBits_2 < 4'hA; // @[Parameters.scala:52:56, :57:20] wire _source_ok_T_17 = _source_ok_T_16; // @[Parameters.scala:56:48, :57:20] wire _source_ok_WIRE_2_0 = _source_ok_T_17; // @[Parameters.scala:1138:31] wire [12:0] _GEN_0 = 13'h3F << io_in_c_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T_4; // @[package.scala:243:71] assign _is_aligned_mask_T_4 = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T; // @[package.scala:243:71] assign _c_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _c_first_beats1_decode_T_3; // @[package.scala:243:71] assign _c_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_5 = _is_aligned_mask_T_4[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask_2 = ~_is_aligned_mask_T_5; // @[package.scala:243:{46,76}] wire [31:0] _is_aligned_T_2 = {26'h0, io_in_c_bits_address_0[5:0] & is_aligned_mask_2}; // @[package.scala:243:46] wire is_aligned_2 = _is_aligned_T_2 == 32'h0; // @[Edges.scala:21:{16,24}] wire [27:0] _GEN_1 = io_in_c_bits_address_0[27:0] ^ 28'h8000000; // @[Monitor.scala:36:7] wire [31:0] _address_ok_T_10 = {io_in_c_bits_address_0[31:28], _GEN_1}; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_11 = {1'h0, _address_ok_T_10}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_12 = _address_ok_T_11 & 33'h1FFFF0000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_13 = _address_ok_T_12; // @[Parameters.scala:137:46] wire _address_ok_T_14 = _address_ok_T_13 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_0 = _address_ok_T_14; // @[Parameters.scala:612:40] wire [31:0] _address_ok_T_15 = io_in_c_bits_address_0 ^ 32'h80000000; // @[Monitor.scala:36:7] wire [32:0] _address_ok_T_16 = {1'h0, _address_ok_T_15}; // @[Parameters.scala:137:{31,41}] wire [32:0] _address_ok_T_17 = _address_ok_T_16 & 33'h1F0000000; // @[Parameters.scala:137:{41,46}] wire [32:0] _address_ok_T_18 = _address_ok_T_17; // @[Parameters.scala:137:46] wire _address_ok_T_19 = _address_ok_T_18 == 33'h0; // @[Parameters.scala:137:{46,59}] wire _address_ok_WIRE_1_1 = _address_ok_T_19; // @[Parameters.scala:612:40] wire address_ok_1 = _address_ok_WIRE_1_0 | _address_ok_WIRE_1_1; // @[Parameters.scala:612:40, :636:64] wire [3:0] uncommonBits_10 = _uncommonBits_T_10; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_11 = _uncommonBits_T_11; // @[Parameters.scala:52:{29,56}] wire [3:0] uncommonBits_12 = _uncommonBits_T_12; // @[Parameters.scala:52:{29,56}] wire _T_1335 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1335; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1335; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [3:0] source; // @[Monitor.scala:390:22] reg [31:0] address; // @[Monitor.scala:391:22] wire _T_1409 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1409; // @[Decoupled.scala:51:35] wire _d_first_T_3; // @[Decoupled.scala:51:35] assign _d_first_T_3 = _T_1409; // @[Decoupled.scala:51:35] wire [12:0] _GEN_2 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_2; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_9; // @[package.scala:243:71] assign _d_first_beats1_decode_T_9 = _GEN_2; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_3 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [1:0] param_1; // @[Monitor.scala:539:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [3:0] source_1; // @[Monitor.scala:541:22] reg [2:0] sink; // @[Monitor.scala:542:22] reg denied; // @[Monitor.scala:543:22] wire _T_1406 = io_in_c_ready_0 & io_in_c_valid_0; // @[Decoupled.scala:51:35] wire _c_first_T; // @[Decoupled.scala:51:35] assign _c_first_T = _T_1406; // @[Decoupled.scala:51:35] wire _c_first_T_1; // @[Decoupled.scala:51:35] assign _c_first_T_1 = _T_1406; // @[Decoupled.scala:51:35] wire [5:0] _c_first_beats1_decode_T_1 = _c_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_2 = ~_c_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode = _c_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire c_first_beats1_opdata = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire c_first_beats1_opdata_1 = io_in_c_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] c_first_beats1 = c_first_beats1_opdata ? c_first_beats1_decode : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T = {1'h0, c_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1 = _c_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire c_first = c_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T = c_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_1 = c_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last = _c_first_last_T | _c_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire c_first_done = c_first_last & _c_first_T; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T = ~c_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count = c_first_beats1 & _c_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T = c_first ? c_first_beats1 : c_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_3; // @[Monitor.scala:515:22] reg [2:0] param_3; // @[Monitor.scala:516:22] reg [2:0] size_3; // @[Monitor.scala:517:22] reg [3:0] source_3; // @[Monitor.scala:518:22] reg [31:0] address_2; // @[Monitor.scala:519:22] reg [9:0] inflight; // @[Monitor.scala:614:27] reg [39:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [39:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] a_set; // @[Monitor.scala:626:34] wire [9:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [39:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [39:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [6:0] _GEN_3 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [6:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69] wire [6:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :641:65] wire [6:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :680:101] wire [6:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_3; // @[Monitor.scala:637:69, :681:99] wire [6:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :749:69] wire [6:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_3; // @[Monitor.scala:637:69, :750:67] wire [6:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :790:101] wire [6:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_3; // @[Monitor.scala:637:69, :791:99] wire [39:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [39:0] _a_opcode_lookup_T_6 = {36'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [39:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [39:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [39:0] _a_size_lookup_T_6 = {36'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [39:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[39:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [15:0] _GEN_4 = 16'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_4; // @[OneHot.scala:58:35] wire [15:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_4; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1261 = _T_1335 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1261 ? _a_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1261 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1261 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [6:0] _GEN_5 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [6:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_5; // @[Monitor.scala:659:79] wire [6:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_5; // @[Monitor.scala:659:79, :660:77] wire [130:0] _a_opcodes_set_T_1 = {127'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1261 ? _a_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [130:0] _a_sizes_set_T_1 = {127'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1261 ? _a_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [9:0] d_clr; // @[Monitor.scala:664:34] wire [9:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [39:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [39:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_6 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_6; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_6; // @[Monitor.scala:673:46, :783:46] wire _T_1307 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [15:0] _GEN_7 = 16'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_7; // @[OneHot.scala:58:35] wire [15:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_7; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1307 & ~d_release_ack ? _d_clr_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1276 = _T_1409 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1276 ? _d_clr_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_5 = 143'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1276 ? _d_opcodes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [142:0] _d_sizes_clr_T_5 = 143'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1276 ? _d_sizes_clr_T_5[39:0] : 40'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [9:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [9:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [9:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [39:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [39:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [39:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [39:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [39:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [39:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [9:0] inflight_1; // @[Monitor.scala:726:35] reg [39:0] inflight_opcodes_1; // @[Monitor.scala:727:35] reg [39:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [5:0] _c_first_beats1_decode_T_4 = _c_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _c_first_beats1_decode_T_5 = ~_c_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] c_first_beats1_decode_1 = _c_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] c_first_beats1_1 = c_first_beats1_opdata_1 ? c_first_beats1_decode_1 : 3'h0; // @[Edges.scala:102:36, :220:59, :221:14] reg [2:0] c_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _c_first_counter1_T_1 = {1'h0, c_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] c_first_counter1_1 = _c_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire c_first_1 = c_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _c_first_last_T_2 = c_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _c_first_last_T_3 = c_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire c_first_last_1 = _c_first_last_T_2 | _c_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire c_first_done_1 = c_first_last_1 & _c_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _c_first_count_T_1 = ~c_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] c_first_count_1 = c_first_beats1_1 & _c_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _c_first_counter_T_1 = c_first_1 ? c_first_beats1_1 : c_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [9:0] c_set; // @[Monitor.scala:738:34] wire [9:0] c_set_wo_ready; // @[Monitor.scala:739:34] wire [39:0] c_opcodes_set; // @[Monitor.scala:740:34] wire [39:0] c_sizes_set; // @[Monitor.scala:741:34] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [39:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [39:0] _c_opcode_lookup_T_6 = {36'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [39:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[39:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [39:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [39:0] _c_size_lookup_T_6 = {36'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [39:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[39:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [3:0] c_opcodes_set_interm; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm; // @[Monitor.scala:755:40] wire _same_cycle_resp_T_3 = io_in_c_valid_0 & c_first_1; // @[Monitor.scala:36:7, :759:26, :795:44] wire _same_cycle_resp_T_4 = io_in_c_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _same_cycle_resp_T_5 = io_in_c_bits_opcode_0[1]; // @[Monitor.scala:36:7] wire [15:0] _GEN_8 = 16'h1 << io_in_c_bits_source_0; // @[OneHot.scala:58:35] wire [15:0] _c_set_wo_ready_T; // @[OneHot.scala:58:35] assign _c_set_wo_ready_T = _GEN_8; // @[OneHot.scala:58:35] wire [15:0] _c_set_T; // @[OneHot.scala:58:35] assign _c_set_T = _GEN_8; // @[OneHot.scala:58:35] assign c_set_wo_ready = _same_cycle_resp_T_3 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5 ? _c_set_wo_ready_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1348 = _T_1406 & c_first_1 & _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Decoupled.scala:51:35] assign c_set = _T_1348 ? _c_set_T[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [3:0] _c_opcodes_set_interm_T = {io_in_c_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :765:53] wire [3:0] _c_opcodes_set_interm_T_1 = {_c_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:765:{53,61}] assign c_opcodes_set_interm = _T_1348 ? _c_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:754:40, :763:{25,36,70}, :765:{28,61}] wire [3:0] _c_sizes_set_interm_T = {io_in_c_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :766:51] wire [3:0] _c_sizes_set_interm_T_1 = {_c_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:766:{51,59}] assign c_sizes_set_interm = _T_1348 ? _c_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:755:40, :763:{25,36,70}, :766:{28,59}] wire [6:0] _GEN_9 = {1'h0, io_in_c_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :767:79] wire [6:0] _c_opcodes_set_T; // @[Monitor.scala:767:79] assign _c_opcodes_set_T = _GEN_9; // @[Monitor.scala:767:79] wire [6:0] _c_sizes_set_T; // @[Monitor.scala:768:77] assign _c_sizes_set_T = _GEN_9; // @[Monitor.scala:767:79, :768:77] wire [130:0] _c_opcodes_set_T_1 = {127'h0, c_opcodes_set_interm} << _c_opcodes_set_T; // @[Monitor.scala:659:54, :754:40, :767:{54,79}] assign c_opcodes_set = _T_1348 ? _c_opcodes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:740:34, :763:{25,36,70}, :767:{28,54}] wire [130:0] _c_sizes_set_T_1 = {127'h0, c_sizes_set_interm} << _c_sizes_set_T; // @[Monitor.scala:659:54, :755:40, :768:{52,77}] assign c_sizes_set = _T_1348 ? _c_sizes_set_T_1[39:0] : 40'h0; // @[Monitor.scala:741:34, :763:{25,36,70}, :768:{28,52}] wire _c_probe_ack_T = io_in_c_bits_opcode_0 == 3'h4; // @[Monitor.scala:36:7, :772:47] wire _c_probe_ack_T_1 = io_in_c_bits_opcode_0 == 3'h5; // @[Monitor.scala:36:7, :772:95] wire c_probe_ack = _c_probe_ack_T | _c_probe_ack_T_1; // @[Monitor.scala:772:{47,71,95}] wire [9:0] d_clr_1; // @[Monitor.scala:774:34] wire [9:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [39:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [39:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1379 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1379 & d_release_ack_1 ? _d_clr_wo_ready_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire _T_1361 = _T_1409 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1361 ? _d_clr_T_1[9:0] : 10'h0; // @[OneHot.scala:58:35] wire [142:0] _d_opcodes_clr_T_11 = 143'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1361 ? _d_opcodes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [142:0] _d_sizes_clr_T_11 = 143'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1361 ? _d_sizes_clr_T_11[39:0] : 40'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_6 = _same_cycle_resp_T_4 & _same_cycle_resp_T_5; // @[Edges.scala:68:{36,40,51}] wire _same_cycle_resp_T_7 = _same_cycle_resp_T_3 & _same_cycle_resp_T_6; // @[Monitor.scala:795:{44,55}] wire _same_cycle_resp_T_8 = io_in_c_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :795:113] wire same_cycle_resp_1 = _same_cycle_resp_T_7 & _same_cycle_resp_T_8; // @[Monitor.scala:795:{55,88,113}] wire [9:0] _inflight_T_3 = inflight_1 | c_set; // @[Monitor.scala:726:35, :738:34, :814:35] wire [9:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [9:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [39:0] _inflight_opcodes_T_3 = inflight_opcodes_1 | c_opcodes_set; // @[Monitor.scala:727:35, :740:34, :815:43] wire [39:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [39:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [39:0] _inflight_sizes_T_3 = inflight_sizes_1 | c_sizes_set; // @[Monitor.scala:728:35, :741:34, :816:41] wire [39:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [39:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27] wire [32:0] _watchdog_T_2 = {1'h0, watchdog_1} + 33'h1; // @[Monitor.scala:818:27, :823:26] wire [31:0] _watchdog_T_3 = _watchdog_T_2[31:0]; // @[Monitor.scala:823:26] reg [7:0] inflight_2; // @[Monitor.scala:828:27] wire [5:0] _d_first_beats1_decode_T_10 = _d_first_beats1_decode_T_9[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_11 = ~_d_first_beats1_decode_T_10; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_3 = _d_first_beats1_decode_T_11[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_3 = d_first_beats1_opdata_3 ? d_first_beats1_decode_3 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_3; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_3 = {1'h0, d_first_counter_3} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_3 = _d_first_counter1_T_3[2:0]; // @[Edges.scala:230:28] wire d_first_3 = d_first_counter_3 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_6 = d_first_counter_3 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_7 = d_first_beats1_3 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_3 = _d_first_last_T_6 | _d_first_last_T_7; // @[Edges.scala:232:{25,33,43}] wire d_first_done_3 = d_first_last_3 & _d_first_T_3; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_3 = ~d_first_counter1_3; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_3 = d_first_beats1_3 & _d_first_count_T_3; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_3 = d_first_3 ? d_first_beats1_3 : d_first_counter1_3; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [7:0] d_set; // @[Monitor.scala:833:25] wire _T_1415 = _T_1409 & d_first_3 & io_in_d_bits_opcode_0[2] & ~(io_in_d_bits_opcode_0[1]); // @[Decoupled.scala:51:35] wire [7:0] _GEN_10 = {5'h0, io_in_d_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _d_set_T = 8'h1 << _GEN_10; // @[OneHot.scala:58:35] assign d_set = _T_1415 ? _d_set_T : 8'h0; // @[OneHot.scala:58:35] wire [7:0] e_clr; // @[Monitor.scala:839:25] wire [7:0] _GEN_11 = {5'h0, io_in_e_bits_sink_0}; // @[OneHot.scala:58:35] wire [7:0] _e_clr_T = 8'h1 << _GEN_11; // @[OneHot.scala:58:35] assign e_clr = io_in_e_valid_0 ? _e_clr_T : 8'h0; // @[OneHot.scala:58:35]
Generate the Verilog code corresponding to this FIRRTL code module ReRoCCMsgArbiter_5 : input clock : Clock input reset : Reset output io : { flip in : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}[5], out : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, client_id : UInt<4>, manager_id : UInt<1>, data : UInt<64>}}} regreset lockIdx : UInt<3>, clock, reset, UInt<3>(0h0) regreset locked : UInt<1>, clock, reset, UInt<1>(0h0) node _choice_T = mux(io.in[3].valid, UInt<2>(0h3), UInt<3>(0h4)) node _choice_T_1 = mux(io.in[2].valid, UInt<2>(0h2), _choice_T) node _choice_T_2 = mux(io.in[1].valid, UInt<1>(0h1), _choice_T_1) node choice = mux(io.in[0].valid, UInt<1>(0h0), _choice_T_2) node chosen = mux(locked, lockIdx, choice) node _io_in_0_ready_T = eq(chosen, UInt<1>(0h0)) node _io_in_0_ready_T_1 = and(io.out.ready, _io_in_0_ready_T) connect io.in[0].ready, _io_in_0_ready_T_1 node _io_in_1_ready_T = eq(chosen, UInt<1>(0h1)) node _io_in_1_ready_T_1 = and(io.out.ready, _io_in_1_ready_T) connect io.in[1].ready, _io_in_1_ready_T_1 node _io_in_2_ready_T = eq(chosen, UInt<2>(0h2)) node _io_in_2_ready_T_1 = and(io.out.ready, _io_in_2_ready_T) connect io.in[2].ready, _io_in_2_ready_T_1 node _io_in_3_ready_T = eq(chosen, UInt<2>(0h3)) node _io_in_3_ready_T_1 = and(io.out.ready, _io_in_3_ready_T) connect io.in[3].ready, _io_in_3_ready_T_1 node _io_in_4_ready_T = eq(chosen, UInt<3>(0h4)) node _io_in_4_ready_T_1 = and(io.out.ready, _io_in_4_ready_T) connect io.in[4].ready, _io_in_4_ready_T_1 connect io.out.valid, io.in[chosen].valid connect io.out.bits, io.in[chosen].bits node _T = and(io.out.ready, io.out.valid) when _T : node _T_1 = eq(locked, UInt<1>(0h0)) when _T_1 : connect lockIdx, choice connect locked, UInt<1>(0h1) regreset beat : UInt<2>, clock, reset, UInt<2>(0h0) regreset max_beat : UInt<2>, clock, reset, UInt<2>(0h0) node first = eq(beat, UInt<1>(0h0)) wire last : UInt<1> wire inst : { funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} wire _inst_WIRE : UInt<32> connect _inst_WIRE, io.out.bits.data node _inst_T = bits(_inst_WIRE, 6, 0) connect inst.opcode, _inst_T node _inst_T_1 = bits(_inst_WIRE, 11, 7) connect inst.rd, _inst_T_1 node _inst_T_2 = bits(_inst_WIRE, 12, 12) connect inst.xs2, _inst_T_2 node _inst_T_3 = bits(_inst_WIRE, 13, 13) connect inst.xs1, _inst_T_3 node _inst_T_4 = bits(_inst_WIRE, 14, 14) connect inst.xd, _inst_T_4 node _inst_T_5 = bits(_inst_WIRE, 19, 15) connect inst.rs1, _inst_T_5 node _inst_T_6 = bits(_inst_WIRE, 24, 20) connect inst.rs2, _inst_T_6 node _inst_T_7 = bits(_inst_WIRE, 31, 25) connect inst.funct, _inst_T_7 node _T_2 = and(io.out.ready, io.out.valid) node _T_3 = and(_T_2, first) when _T_3 : connect max_beat, UInt<1>(0h0) node _T_4 = eq(io.out.bits.opcode, UInt<3>(0h2)) when _T_4 : connect max_beat, UInt<1>(0h1) connect last, UInt<1>(0h1) node _T_5 = eq(io.out.bits.opcode, UInt<3>(0h2)) when _T_5 : node _last_T = eq(beat, max_beat) node _last_T_1 = eq(first, UInt<1>(0h0)) node _last_T_2 = and(_last_T, _last_T_1) connect last, _last_T_2 node _T_6 = and(io.out.ready, io.out.valid) when _T_6 : node _beat_T = add(beat, UInt<1>(0h1)) node _beat_T_1 = tail(_beat_T, 1) connect beat, _beat_T_1 node _T_7 = and(io.out.ready, io.out.valid) node _T_8 = and(_T_7, last) when _T_8 : connect max_beat, UInt<1>(0h0) connect beat, UInt<1>(0h0) when last : connect locked, UInt<1>(0h0)
module ReRoCCMsgArbiter_5( // @[Arbiter.scala:7:7] input clock, // @[Arbiter.scala:7:7] input reset, // @[Arbiter.scala:7:7] output io_in_0_ready, // @[Arbiters.scala:14:14] input io_in_0_valid, // @[Arbiters.scala:14:14] input [3:0] io_in_0_bits_client_id, // @[Arbiters.scala:14:14] input io_in_0_bits_manager_id, // @[Arbiters.scala:14:14] input [63:0] io_in_0_bits_data, // @[Arbiters.scala:14:14] output io_in_1_ready, // @[Arbiters.scala:14:14] input io_in_1_valid, // @[Arbiters.scala:14:14] input [3:0] io_in_1_bits_client_id, // @[Arbiters.scala:14:14] input io_in_1_bits_manager_id, // @[Arbiters.scala:14:14] output io_in_2_ready, // @[Arbiters.scala:14:14] input io_in_2_valid, // @[Arbiters.scala:14:14] input [3:0] io_in_2_bits_client_id, // @[Arbiters.scala:14:14] input io_in_2_bits_manager_id, // @[Arbiters.scala:14:14] input [63:0] io_in_2_bits_data, // @[Arbiters.scala:14:14] output io_in_3_ready, // @[Arbiters.scala:14:14] input io_in_3_valid, // @[Arbiters.scala:14:14] input [3:0] io_in_3_bits_client_id, // @[Arbiters.scala:14:14] input io_in_3_bits_manager_id, // @[Arbiters.scala:14:14] output io_in_4_ready, // @[Arbiters.scala:14:14] input io_in_4_valid, // @[Arbiters.scala:14:14] input [3:0] io_in_4_bits_client_id, // @[Arbiters.scala:14:14] input io_in_4_bits_manager_id, // @[Arbiters.scala:14:14] input io_out_ready, // @[Arbiters.scala:14:14] output io_out_valid, // @[Arbiters.scala:14:14] output [2:0] io_out_bits_opcode, // @[Arbiters.scala:14:14] output [3:0] io_out_bits_client_id, // @[Arbiters.scala:14:14] output io_out_bits_manager_id, // @[Arbiters.scala:14:14] output [63:0] io_out_bits_data // @[Arbiters.scala:14:14] ); wire io_in_0_valid_0 = io_in_0_valid; // @[Arbiter.scala:7:7] wire [3:0] io_in_0_bits_client_id_0 = io_in_0_bits_client_id; // @[Arbiter.scala:7:7] wire io_in_0_bits_manager_id_0 = io_in_0_bits_manager_id; // @[Arbiter.scala:7:7] wire [63:0] io_in_0_bits_data_0 = io_in_0_bits_data; // @[Arbiter.scala:7:7] wire io_in_1_valid_0 = io_in_1_valid; // @[Arbiter.scala:7:7] wire [3:0] io_in_1_bits_client_id_0 = io_in_1_bits_client_id; // @[Arbiter.scala:7:7] wire io_in_1_bits_manager_id_0 = io_in_1_bits_manager_id; // @[Arbiter.scala:7:7] wire io_in_2_valid_0 = io_in_2_valid; // @[Arbiter.scala:7:7] wire [3:0] io_in_2_bits_client_id_0 = io_in_2_bits_client_id; // @[Arbiter.scala:7:7] wire io_in_2_bits_manager_id_0 = io_in_2_bits_manager_id; // @[Arbiter.scala:7:7] wire [63:0] io_in_2_bits_data_0 = io_in_2_bits_data; // @[Arbiter.scala:7:7] wire io_in_3_valid_0 = io_in_3_valid; // @[Arbiter.scala:7:7] wire [3:0] io_in_3_bits_client_id_0 = io_in_3_bits_client_id; // @[Arbiter.scala:7:7] wire io_in_3_bits_manager_id_0 = io_in_3_bits_manager_id; // @[Arbiter.scala:7:7] wire io_in_4_valid_0 = io_in_4_valid; // @[Arbiter.scala:7:7] wire [3:0] io_in_4_bits_client_id_0 = io_in_4_bits_client_id; // @[Arbiter.scala:7:7] wire io_in_4_bits_manager_id_0 = io_in_4_bits_manager_id; // @[Arbiter.scala:7:7] wire io_out_ready_0 = io_out_ready; // @[Arbiter.scala:7:7] wire [7:0][2:0] _GEN = '{3'h0, 3'h0, 3'h0, 3'h4, 3'h3, 3'h2, 3'h1, 3'h0}; wire [2:0] io_in_4_bits_opcode = 3'h4; // @[Arbiter.scala:7:7] wire [2:0] io_in_3_bits_opcode = 3'h3; // @[Arbiters.scala:40:46] wire [2:0] io_in_2_bits_opcode = 3'h2; // @[Arbiters.scala:40:46] wire [63:0] io_in_1_bits_data = 64'h0; // @[Arbiters.scala:14:14] wire [63:0] io_in_3_bits_data = 64'h0; // @[Arbiters.scala:14:14] wire [63:0] io_in_4_bits_data = 64'h0; // @[Arbiters.scala:14:14] wire [2:0] io_in_1_bits_opcode = 3'h1; // @[Arbiters.scala:40:46] wire [2:0] io_in_0_bits_opcode = 3'h0; // @[Arbiter.scala:7:7] wire _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_1_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_2_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_3_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_4_ready_T_1; // @[Arbiters.scala:40:36] wire io_in_0_ready_0; // @[Arbiter.scala:7:7] wire io_in_1_ready_0; // @[Arbiter.scala:7:7] wire io_in_2_ready_0; // @[Arbiter.scala:7:7] wire io_in_3_ready_0; // @[Arbiter.scala:7:7] wire io_in_4_ready_0; // @[Arbiter.scala:7:7] wire [2:0] io_out_bits_opcode_0; // @[Arbiter.scala:7:7] wire [3:0] io_out_bits_client_id_0; // @[Arbiter.scala:7:7] wire io_out_bits_manager_id_0; // @[Arbiter.scala:7:7] wire [63:0] io_out_bits_data_0; // @[Arbiter.scala:7:7] wire io_out_valid_0; // @[Arbiter.scala:7:7] reg [2:0] lockIdx; // @[Arbiters.scala:26:24] reg locked; // @[Arbiters.scala:27:23] wire [2:0] _choice_T = io_in_3_valid_0 ? 3'h3 : 3'h4; // @[Mux.scala:50:70] wire [2:0] _choice_T_1 = io_in_2_valid_0 ? 3'h2 : _choice_T; // @[Mux.scala:50:70] wire [2:0] _choice_T_2 = io_in_1_valid_0 ? 3'h1 : _choice_T_1; // @[Mux.scala:50:70] wire [2:0] choice = io_in_0_valid_0 ? 3'h0 : _choice_T_2; // @[Mux.scala:50:70] wire [2:0] chosen = locked ? lockIdx : choice; // @[Mux.scala:50:70] wire _io_in_0_ready_T = chosen == 3'h0; // @[Arbiters.scala:37:19, :40:46] assign _io_in_0_ready_T_1 = io_out_ready_0 & _io_in_0_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_0_ready_0 = _io_in_0_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_1_ready_T = chosen == 3'h1; // @[Arbiters.scala:37:19, :40:46] assign _io_in_1_ready_T_1 = io_out_ready_0 & _io_in_1_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_1_ready_0 = _io_in_1_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_2_ready_T = chosen == 3'h2; // @[Arbiters.scala:37:19, :40:46] assign _io_in_2_ready_T_1 = io_out_ready_0 & _io_in_2_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_2_ready_0 = _io_in_2_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_3_ready_T = chosen == 3'h3; // @[Arbiters.scala:37:19, :40:46] assign _io_in_3_ready_T_1 = io_out_ready_0 & _io_in_3_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_3_ready_0 = _io_in_3_ready_T_1; // @[Arbiters.scala:40:36] wire _io_in_4_ready_T = chosen == 3'h4; // @[Arbiters.scala:37:19, :40:46] assign _io_in_4_ready_T_1 = io_out_ready_0 & _io_in_4_ready_T; // @[Arbiters.scala:40:{36,46}] assign io_in_4_ready_0 = _io_in_4_ready_T_1; // @[Arbiters.scala:40:36] wire [7:0] _GEN_0 = {{io_in_0_valid_0}, {io_in_0_valid_0}, {io_in_0_valid_0}, {io_in_4_valid_0}, {io_in_3_valid_0}, {io_in_2_valid_0}, {io_in_1_valid_0}, {io_in_0_valid_0}}; // @[Arbiters.scala:43:16] assign io_out_valid_0 = _GEN_0[chosen]; // @[Arbiters.scala:37:19, :43:16] assign io_out_bits_opcode_0 = _GEN[chosen]; // @[Arbiters.scala:37:19, :43:16] wire [7:0][3:0] _GEN_1 = {{io_in_0_bits_client_id_0}, {io_in_0_bits_client_id_0}, {io_in_0_bits_client_id_0}, {io_in_4_bits_client_id_0}, {io_in_3_bits_client_id_0}, {io_in_2_bits_client_id_0}, {io_in_1_bits_client_id_0}, {io_in_0_bits_client_id_0}}; // @[Arbiters.scala:43:16] assign io_out_bits_client_id_0 = _GEN_1[chosen]; // @[Arbiters.scala:37:19, :43:16] wire [7:0] _GEN_2 = {{io_in_0_bits_manager_id_0}, {io_in_0_bits_manager_id_0}, {io_in_0_bits_manager_id_0}, {io_in_4_bits_manager_id_0}, {io_in_3_bits_manager_id_0}, {io_in_2_bits_manager_id_0}, {io_in_1_bits_manager_id_0}, {io_in_0_bits_manager_id_0}}; // @[Arbiters.scala:43:16] assign io_out_bits_manager_id_0 = _GEN_2[chosen]; // @[Arbiters.scala:37:19, :43:16] wire [7:0][63:0] _GEN_3 = {{io_in_0_bits_data_0}, {io_in_0_bits_data_0}, {io_in_0_bits_data_0}, {64'h0}, {64'h0}, {io_in_2_bits_data_0}, {64'h0}, {io_in_0_bits_data_0}}; // @[Arbiters.scala:14:14, :43:16] assign io_out_bits_data_0 = _GEN_3[chosen]; // @[Arbiters.scala:37:19, :43:16] reg [1:0] beat; // @[Protocol.scala:54:23] reg [1:0] max_beat; // @[Protocol.scala:55:27] wire first = beat == 2'h0; // @[Protocol.scala:54:23, :56:22] wire last; // @[Protocol.scala:57:20] wire [6:0] _inst_T_7; // @[Protocol.scala:58:36] wire [4:0] _inst_T_6; // @[Protocol.scala:58:36] wire [4:0] _inst_T_5; // @[Protocol.scala:58:36] wire _inst_T_4; // @[Protocol.scala:58:36] wire _inst_T_3; // @[Protocol.scala:58:36] wire _inst_T_2; // @[Protocol.scala:58:36] wire [4:0] _inst_T_1; // @[Protocol.scala:58:36] wire [6:0] _inst_T; // @[Protocol.scala:58:36] wire [6:0] inst_funct; // @[Protocol.scala:58:36] wire [4:0] inst_rs2; // @[Protocol.scala:58:36] wire [4:0] inst_rs1; // @[Protocol.scala:58:36] wire inst_xd; // @[Protocol.scala:58:36] wire inst_xs1; // @[Protocol.scala:58:36] wire inst_xs2; // @[Protocol.scala:58:36] wire [4:0] inst_rd; // @[Protocol.scala:58:36] wire [6:0] inst_opcode; // @[Protocol.scala:58:36] wire [31:0] _inst_WIRE = io_out_bits_data_0[31:0]; // @[Protocol.scala:58:36] assign _inst_T = _inst_WIRE[6:0]; // @[Protocol.scala:58:36] assign inst_opcode = _inst_T; // @[Protocol.scala:58:36] assign _inst_T_1 = _inst_WIRE[11:7]; // @[Protocol.scala:58:36] assign inst_rd = _inst_T_1; // @[Protocol.scala:58:36] assign _inst_T_2 = _inst_WIRE[12]; // @[Protocol.scala:58:36] assign inst_xs2 = _inst_T_2; // @[Protocol.scala:58:36] assign _inst_T_3 = _inst_WIRE[13]; // @[Protocol.scala:58:36] assign inst_xs1 = _inst_T_3; // @[Protocol.scala:58:36] assign _inst_T_4 = _inst_WIRE[14]; // @[Protocol.scala:58:36] assign inst_xd = _inst_T_4; // @[Protocol.scala:58:36] assign _inst_T_5 = _inst_WIRE[19:15]; // @[Protocol.scala:58:36] assign inst_rs1 = _inst_T_5; // @[Protocol.scala:58:36] assign _inst_T_6 = _inst_WIRE[24:20]; // @[Protocol.scala:58:36] assign inst_rs2 = _inst_T_6; // @[Protocol.scala:58:36] assign _inst_T_7 = _inst_WIRE[31:25]; // @[Protocol.scala:58:36] assign inst_funct = _inst_T_7; // @[Protocol.scala:58:36] wire _last_T = beat == max_beat; // @[Protocol.scala:54:23, :55:27, :83:22] wire _last_T_1 = ~first; // @[Protocol.scala:56:22, :83:38] wire _last_T_2 = _last_T & _last_T_1; // @[Protocol.scala:83:{22,35,38}] assign last = io_out_bits_opcode_0 != 3'h2 | _last_T_2; // @[Arbiters.scala:40:46] wire [2:0] _beat_T = {1'h0, beat} + 3'h1; // @[Arbiters.scala:40:46] wire [1:0] _beat_T_1 = _beat_T[1:0]; // @[Protocol.scala:87:34] wire _T_7 = io_out_ready_0 & io_out_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[Arbiter.scala:7:7] if (reset) begin // @[Arbiter.scala:7:7] lockIdx <= 3'h0; // @[Arbiters.scala:26:24] locked <= 1'h0; // @[Arbiters.scala:27:23] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Arbiter.scala:7:7] if (_T_7 & ~locked) // @[Decoupled.scala:51:35] lockIdx <= choice; // @[Mux.scala:50:70] if (_T_7) // @[Decoupled.scala:51:35] locked <= ~last; // @[Arbiters.scala:27:23] if (_T_7 & last) begin // @[Decoupled.scala:51:35] beat <= 2'h0; // @[Protocol.scala:54:23] max_beat <= 2'h0; // @[Protocol.scala:55:27] end else begin // @[Protocol.scala:88:18] if (_T_7) // @[Decoupled.scala:51:35] beat <= _beat_T_1; // @[Protocol.scala:54:23, :87:34] if (_T_7 & first) // @[Decoupled.scala:51:35] max_beat <= {1'h0, io_out_bits_opcode_0 == 3'h2}; // @[Arbiters.scala:40:46] end end always @(posedge) assign io_in_0_ready = io_in_0_ready_0; // @[Arbiter.scala:7:7] assign io_in_1_ready = io_in_1_ready_0; // @[Arbiter.scala:7:7] assign io_in_2_ready = io_in_2_ready_0; // @[Arbiter.scala:7:7] assign io_in_3_ready = io_in_3_ready_0; // @[Arbiter.scala:7:7] assign io_in_4_ready = io_in_4_ready_0; // @[Arbiter.scala:7:7] assign io_out_valid = io_out_valid_0; // @[Arbiter.scala:7:7] assign io_out_bits_opcode = io_out_bits_opcode_0; // @[Arbiter.scala:7:7] assign io_out_bits_client_id = io_out_bits_client_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_manager_id = io_out_bits_manager_id_0; // @[Arbiter.scala:7:7] assign io_out_bits_data = io_out_bits_data_0; // @[Arbiter.scala:7:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerShiftReg_w1_d3_i0_139 : input clock : Clock input reset : Reset output io : { flip d : UInt<1>, q : UInt<1>} node _output_T = asAsyncReset(reset) node _output_T_1 = bits(io.d, 0, 0) inst output_chain of AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_235 connect output_chain.clock, clock connect output_chain.reset, _output_T connect output_chain.io.d, _output_T_1 wire output_0 : UInt<1> connect output_0, output_chain.io.q connect io.q, output_0
module AsyncResetSynchronizerShiftReg_w1_d3_i0_139( // @[SynchronizerReg.scala:80:7] input clock, // @[SynchronizerReg.scala:80:7] input reset, // @[SynchronizerReg.scala:80:7] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:80:7] wire _output_T = reset; // @[SynchronizerReg.scala:86:21] wire _output_T_1 = io_d_0; // @[SynchronizerReg.scala:80:7, :87:41] wire output_0; // @[ShiftReg.scala:48:24] wire io_q_0; // @[SynchronizerReg.scala:80:7] assign io_q_0 = output_0; // @[SynchronizerReg.scala:80:7] AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_235 output_chain ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (_output_T), // @[SynchronizerReg.scala:86:21] .io_d (_output_T_1), // @[SynchronizerReg.scala:87:41] .io_q (output_0) ); // @[ShiftReg.scala:45:23] assign io_q = io_q_0; // @[SynchronizerReg.scala:80:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_489 : input clock : Clock input reset : AsyncReset output io : { flip d : UInt<1>, q : UInt<1>} regreset sync_0 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_1 : UInt<1>, clock, reset, UInt<1>(0h0) regreset sync_2 : UInt<1>, clock, reset, UInt<1>(0h0) node _sync_2_T = bits(io.d, 0, 0) connect sync_2, _sync_2_T connect sync_0, sync_1 connect sync_1, sync_2 connect io.q, sync_0
module AsyncResetSynchronizerPrimitiveShiftReg_d3_i0_489( // @[SynchronizerReg.scala:68:19] input clock, // @[SynchronizerReg.scala:68:19] input reset, // @[SynchronizerReg.scala:68:19] input io_d, // @[ShiftReg.scala:36:14] output io_q // @[ShiftReg.scala:36:14] ); wire io_d_0 = io_d; // @[SynchronizerReg.scala:68:19] wire _sync_2_T = io_d_0; // @[SynchronizerReg.scala:54:22, :68:19] wire io_q_0; // @[SynchronizerReg.scala:68:19] reg sync_0; // @[SynchronizerReg.scala:51:87] assign io_q_0 = sync_0; // @[SynchronizerReg.scala:51:87, :68:19] reg sync_1; // @[SynchronizerReg.scala:51:87] reg sync_2; // @[SynchronizerReg.scala:51:87] always @(posedge clock or posedge reset) begin // @[SynchronizerReg.scala:68:19] if (reset) begin // @[SynchronizerReg.scala:68:19] sync_0 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_1 <= 1'h0; // @[SynchronizerReg.scala:51:87] sync_2 <= 1'h0; // @[SynchronizerReg.scala:51:87] end else begin // @[SynchronizerReg.scala:68:19] sync_0 <= sync_1; // @[SynchronizerReg.scala:51:87] sync_1 <= sync_2; // @[SynchronizerReg.scala:51:87] sync_2 <= _sync_2_T; // @[SynchronizerReg.scala:51:87, :54:22] end always @(posedge, posedge)
Generate the Verilog code corresponding to this FIRRTL code module MemLoader_1 : input clock : Clock input reset : Reset output io : { l2helperUser : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt, size : UInt, data : UInt<256>, cmd : UInt}}, flip resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { data : UInt<256>}}, flip no_memops_inflight : UInt<1>}, flip src_info : { flip ready : UInt<1>, valid : UInt<1>, bits : { ip : UInt<64>, isize : UInt<64>}}, consumer : { flip user_consumed_bytes : UInt<6>, available_output_bytes : UInt<6>, output_valid : UInt<1>, flip output_ready : UInt<1>, output_data : UInt<256>, output_last_chunk : UInt<1>}} inst buf_info_queue of Queue16_BufInfoBundle_2 connect buf_info_queue.clock, clock connect buf_info_queue.reset, reset inst load_info_queue of Queue256_LoadInfoBundle_3 connect load_info_queue.clock, clock connect load_info_queue.reset, reset node base_addr_start_index = and(io.src_info.bits.ip, UInt<5>(0h1f)) node _aligned_loadlen_T = add(io.src_info.bits.isize, base_addr_start_index) node aligned_loadlen = tail(_aligned_loadlen_T, 1) node _base_addr_end_index_T = add(io.src_info.bits.isize, base_addr_start_index) node _base_addr_end_index_T_1 = tail(_base_addr_end_index_T, 1) node base_addr_end_index = and(_base_addr_end_index_T_1, UInt<5>(0h1f)) node _base_addr_end_index_inclusive_T = add(io.src_info.bits.isize, base_addr_start_index) node _base_addr_end_index_inclusive_T_1 = tail(_base_addr_end_index_inclusive_T, 1) node _base_addr_end_index_inclusive_T_2 = sub(_base_addr_end_index_inclusive_T_1, UInt<1>(0h1)) node _base_addr_end_index_inclusive_T_3 = tail(_base_addr_end_index_inclusive_T_2, 1) node base_addr_end_index_inclusive = and(_base_addr_end_index_inclusive_T_3, UInt<5>(0h1f)) node _extra_word_T = and(aligned_loadlen, UInt<5>(0h1f)) node extra_word = neq(_extra_word_T, UInt<1>(0h0)) node _base_addr_bytes_aligned_T = dshr(io.src_info.bits.ip, UInt<3>(0h5)) node base_addr_bytes_aligned = dshl(_base_addr_bytes_aligned_T, UInt<3>(0h5)) node _words_to_load_T = dshr(aligned_loadlen, UInt<3>(0h5)) node _words_to_load_T_1 = add(_words_to_load_T, extra_word) node words_to_load = tail(_words_to_load_T_1, 1) node _words_to_load_minus_one_T = sub(words_to_load, UInt<1>(0h1)) node words_to_load_minus_one = tail(_words_to_load_minus_one_T, 1) regreset print_not_done : UInt<1>, clock, reset, UInt<1>(0h1) node _T = and(io.src_info.valid, print_not_done) when _T : regreset loginfo_cycles : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T = add(loginfo_cycles, UInt<1>(0h1)) node _loginfo_cycles_T_1 = tail(_loginfo_cycles_T, 1) connect loginfo_cycles, _loginfo_cycles_T_1 node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles) : printf node _T_3 = asUInt(reset) node _T_4 = eq(_T_3, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "base_addr_bytes: %x\n", io.src_info.bits.ip) : printf_1 regreset loginfo_cycles_1 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_2 = add(loginfo_cycles_1, UInt<1>(0h1)) node _loginfo_cycles_T_3 = tail(_loginfo_cycles_T_2, 1) connect loginfo_cycles_1, _loginfo_cycles_T_3 node _T_5 = asUInt(reset) node _T_6 = eq(_T_5, UInt<1>(0h0)) when _T_6 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_1) : printf_2 node _T_7 = asUInt(reset) node _T_8 = eq(_T_7, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "base_len: %x\n", io.src_info.bits.isize) : printf_3 regreset loginfo_cycles_2 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_4 = add(loginfo_cycles_2, UInt<1>(0h1)) node _loginfo_cycles_T_5 = tail(_loginfo_cycles_T_4, 1) connect loginfo_cycles_2, _loginfo_cycles_T_5 node _T_9 = asUInt(reset) node _T_10 = eq(_T_9, UInt<1>(0h0)) when _T_10 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_2) : printf_4 node _T_11 = asUInt(reset) node _T_12 = eq(_T_11, UInt<1>(0h0)) when _T_12 : printf(clock, UInt<1>(0h1), "base_addr_start_index: %x\n", base_addr_start_index) : printf_5 regreset loginfo_cycles_3 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_6 = add(loginfo_cycles_3, UInt<1>(0h1)) node _loginfo_cycles_T_7 = tail(_loginfo_cycles_T_6, 1) connect loginfo_cycles_3, _loginfo_cycles_T_7 node _T_13 = asUInt(reset) node _T_14 = eq(_T_13, UInt<1>(0h0)) when _T_14 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_3) : printf_6 node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : printf(clock, UInt<1>(0h1), "aligned_loadlen: %x\n", aligned_loadlen) : printf_7 regreset loginfo_cycles_4 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_8 = add(loginfo_cycles_4, UInt<1>(0h1)) node _loginfo_cycles_T_9 = tail(_loginfo_cycles_T_8, 1) connect loginfo_cycles_4, _loginfo_cycles_T_9 node _T_17 = asUInt(reset) node _T_18 = eq(_T_17, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_4) : printf_8 node _T_19 = asUInt(reset) node _T_20 = eq(_T_19, UInt<1>(0h0)) when _T_20 : printf(clock, UInt<1>(0h1), "base_addr_end_index: %x\n", base_addr_end_index) : printf_9 regreset loginfo_cycles_5 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_10 = add(loginfo_cycles_5, UInt<1>(0h1)) node _loginfo_cycles_T_11 = tail(_loginfo_cycles_T_10, 1) connect loginfo_cycles_5, _loginfo_cycles_T_11 node _T_21 = asUInt(reset) node _T_22 = eq(_T_21, UInt<1>(0h0)) when _T_22 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_5) : printf_10 node _T_23 = asUInt(reset) node _T_24 = eq(_T_23, UInt<1>(0h0)) when _T_24 : printf(clock, UInt<1>(0h1), "base_addr_end_index_inclusive: %x\n", base_addr_end_index_inclusive) : printf_11 regreset loginfo_cycles_6 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_12 = add(loginfo_cycles_6, UInt<1>(0h1)) node _loginfo_cycles_T_13 = tail(_loginfo_cycles_T_12, 1) connect loginfo_cycles_6, _loginfo_cycles_T_13 node _T_25 = asUInt(reset) node _T_26 = eq(_T_25, UInt<1>(0h0)) when _T_26 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_6) : printf_12 node _T_27 = asUInt(reset) node _T_28 = eq(_T_27, UInt<1>(0h0)) when _T_28 : printf(clock, UInt<1>(0h1), "extra_word: %x\n", extra_word) : printf_13 regreset loginfo_cycles_7 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_14 = add(loginfo_cycles_7, UInt<1>(0h1)) node _loginfo_cycles_T_15 = tail(_loginfo_cycles_T_14, 1) connect loginfo_cycles_7, _loginfo_cycles_T_15 node _T_29 = asUInt(reset) node _T_30 = eq(_T_29, UInt<1>(0h0)) when _T_30 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_7) : printf_14 node _T_31 = asUInt(reset) node _T_32 = eq(_T_31, UInt<1>(0h0)) when _T_32 : printf(clock, UInt<1>(0h1), "base_addr_bytes_aligned: %x\n", base_addr_bytes_aligned) : printf_15 regreset loginfo_cycles_8 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_16 = add(loginfo_cycles_8, UInt<1>(0h1)) node _loginfo_cycles_T_17 = tail(_loginfo_cycles_T_16, 1) connect loginfo_cycles_8, _loginfo_cycles_T_17 node _T_33 = asUInt(reset) node _T_34 = eq(_T_33, UInt<1>(0h0)) when _T_34 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_8) : printf_16 node _T_35 = asUInt(reset) node _T_36 = eq(_T_35, UInt<1>(0h0)) when _T_36 : printf(clock, UInt<1>(0h1), "words_to_load: %x\n", words_to_load) : printf_17 regreset loginfo_cycles_9 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_18 = add(loginfo_cycles_9, UInt<1>(0h1)) node _loginfo_cycles_T_19 = tail(_loginfo_cycles_T_18, 1) connect loginfo_cycles_9, _loginfo_cycles_T_19 node _T_37 = asUInt(reset) node _T_38 = eq(_T_37, UInt<1>(0h0)) when _T_38 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_9) : printf_18 node _T_39 = asUInt(reset) node _T_40 = eq(_T_39, UInt<1>(0h0)) when _T_40 : printf(clock, UInt<1>(0h1), "words_to_load_minus_one: %x\n", words_to_load_minus_one) : printf_19 when io.src_info.ready : connect print_not_done, UInt<1>(0h1) else : connect print_not_done, UInt<1>(0h0) connect io.l2helperUser.req.bits.cmd, UInt<1>(0h0) connect io.l2helperUser.req.bits.size, UInt<3>(0h5) connect io.l2helperUser.req.bits.data, UInt<1>(0h0) regreset addrinc : UInt<64>, clock, reset, UInt<64>(0h0) node _load_info_queue_io_enq_bits_start_byte_T = eq(addrinc, UInt<1>(0h0)) node _load_info_queue_io_enq_bits_start_byte_T_1 = mux(_load_info_queue_io_enq_bits_start_byte_T, base_addr_start_index, UInt<1>(0h0)) connect load_info_queue.io.enq.bits.start_byte, _load_info_queue_io_enq_bits_start_byte_T_1 node _load_info_queue_io_enq_bits_end_byte_T = eq(addrinc, words_to_load_minus_one) node _load_info_queue_io_enq_bits_end_byte_T_1 = mux(_load_info_queue_io_enq_bits_end_byte_T, base_addr_end_index_inclusive, UInt<5>(0h1f)) connect load_info_queue.io.enq.bits.end_byte, _load_info_queue_io_enq_bits_end_byte_T_1 node _T_41 = and(io.l2helperUser.req.ready, io.src_info.valid) node _T_42 = and(_T_41, buf_info_queue.io.enq.ready) node _T_43 = and(_T_42, load_info_queue.io.enq.ready) node _T_44 = eq(addrinc, words_to_load_minus_one) node _T_45 = and(_T_43, _T_44) when _T_45 : connect addrinc, UInt<1>(0h0) else : node _T_46 = and(io.l2helperUser.req.ready, io.src_info.valid) node _T_47 = and(_T_46, buf_info_queue.io.enq.ready) node _T_48 = and(_T_47, load_info_queue.io.enq.ready) when _T_48 : node _addrinc_T = add(addrinc, UInt<1>(0h1)) node _addrinc_T_1 = tail(_addrinc_T, 1) connect addrinc, _addrinc_T_1 node _T_49 = and(io.src_info.ready, io.src_info.valid) when _T_49 : regreset loginfo_cycles_10 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_20 = add(loginfo_cycles_10, UInt<1>(0h1)) node _loginfo_cycles_T_21 = tail(_loginfo_cycles_T_20, 1) connect loginfo_cycles_10, _loginfo_cycles_T_21 node _T_50 = asUInt(reset) node _T_51 = eq(_T_50, UInt<1>(0h0)) when _T_51 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_10) : printf_20 node _T_52 = asUInt(reset) node _T_53 = eq(_T_52, UInt<1>(0h0)) when _T_53 : printf(clock, UInt<1>(0h1), "COMPLETED INPUT LOAD FOR DECOMPRESSION\n") : printf_21 node _io_src_info_ready_T = eq(addrinc, words_to_load_minus_one) node _io_src_info_ready_T_1 = and(io.l2helperUser.req.ready, buf_info_queue.io.enq.ready) node _io_src_info_ready_T_2 = and(_io_src_info_ready_T_1, load_info_queue.io.enq.ready) node _io_src_info_ready_T_3 = and(_io_src_info_ready_T_2, _io_src_info_ready_T) connect io.src_info.ready, _io_src_info_ready_T_3 node _buf_info_queue_io_enq_valid_T = eq(addrinc, UInt<1>(0h0)) node _buf_info_queue_io_enq_valid_T_1 = and(io.l2helperUser.req.ready, io.src_info.valid) node _buf_info_queue_io_enq_valid_T_2 = and(_buf_info_queue_io_enq_valid_T_1, load_info_queue.io.enq.ready) node _buf_info_queue_io_enq_valid_T_3 = and(_buf_info_queue_io_enq_valid_T_2, _buf_info_queue_io_enq_valid_T) connect buf_info_queue.io.enq.valid, _buf_info_queue_io_enq_valid_T_3 node _load_info_queue_io_enq_valid_T = and(io.l2helperUser.req.ready, io.src_info.valid) node _load_info_queue_io_enq_valid_T_1 = and(_load_info_queue_io_enq_valid_T, buf_info_queue.io.enq.ready) connect load_info_queue.io.enq.valid, _load_info_queue_io_enq_valid_T_1 connect buf_info_queue.io.enq.bits.len_bytes, io.src_info.bits.isize node _io_l2helperUser_req_bits_addr_T = shl(addrinc, 5) node _io_l2helperUser_req_bits_addr_T_1 = add(base_addr_bytes_aligned, _io_l2helperUser_req_bits_addr_T) node _io_l2helperUser_req_bits_addr_T_2 = tail(_io_l2helperUser_req_bits_addr_T_1, 1) connect io.l2helperUser.req.bits.addr, _io_l2helperUser_req_bits_addr_T_2 node _io_l2helperUser_req_valid_T = and(io.src_info.valid, buf_info_queue.io.enq.ready) node _io_l2helperUser_req_valid_T_1 = and(_io_l2helperUser_req_valid_T, load_info_queue.io.enq.ready) connect io.l2helperUser.req.valid, _io_l2helperUser_req_valid_T_1 regreset write_start_index : UInt<6>, clock, reset, UInt<6>(0h0) inst Queue64_UInt8 of Queue64_UInt8_128 connect Queue64_UInt8.clock, clock connect Queue64_UInt8.reset, reset inst Queue64_UInt8_1 of Queue64_UInt8_129 connect Queue64_UInt8_1.clock, clock connect Queue64_UInt8_1.reset, reset inst Queue64_UInt8_2 of Queue64_UInt8_130 connect Queue64_UInt8_2.clock, clock connect Queue64_UInt8_2.reset, reset inst Queue64_UInt8_3 of Queue64_UInt8_131 connect Queue64_UInt8_3.clock, clock connect Queue64_UInt8_3.reset, reset inst Queue64_UInt8_4 of Queue64_UInt8_132 connect Queue64_UInt8_4.clock, clock connect Queue64_UInt8_4.reset, reset inst Queue64_UInt8_5 of Queue64_UInt8_133 connect Queue64_UInt8_5.clock, clock connect Queue64_UInt8_5.reset, reset inst Queue64_UInt8_6 of Queue64_UInt8_134 connect Queue64_UInt8_6.clock, clock connect Queue64_UInt8_6.reset, reset inst Queue64_UInt8_7 of Queue64_UInt8_135 connect Queue64_UInt8_7.clock, clock connect Queue64_UInt8_7.reset, reset inst Queue64_UInt8_8 of Queue64_UInt8_136 connect Queue64_UInt8_8.clock, clock connect Queue64_UInt8_8.reset, reset inst Queue64_UInt8_9 of Queue64_UInt8_137 connect Queue64_UInt8_9.clock, clock connect Queue64_UInt8_9.reset, reset inst Queue64_UInt8_10 of Queue64_UInt8_138 connect Queue64_UInt8_10.clock, clock connect Queue64_UInt8_10.reset, reset inst Queue64_UInt8_11 of Queue64_UInt8_139 connect Queue64_UInt8_11.clock, clock connect Queue64_UInt8_11.reset, reset inst Queue64_UInt8_12 of Queue64_UInt8_140 connect Queue64_UInt8_12.clock, clock connect Queue64_UInt8_12.reset, reset inst Queue64_UInt8_13 of Queue64_UInt8_141 connect Queue64_UInt8_13.clock, clock connect Queue64_UInt8_13.reset, reset inst Queue64_UInt8_14 of Queue64_UInt8_142 connect Queue64_UInt8_14.clock, clock connect Queue64_UInt8_14.reset, reset inst Queue64_UInt8_15 of Queue64_UInt8_143 connect Queue64_UInt8_15.clock, clock connect Queue64_UInt8_15.reset, reset inst Queue64_UInt8_16 of Queue64_UInt8_144 connect Queue64_UInt8_16.clock, clock connect Queue64_UInt8_16.reset, reset inst Queue64_UInt8_17 of Queue64_UInt8_145 connect Queue64_UInt8_17.clock, clock connect Queue64_UInt8_17.reset, reset inst Queue64_UInt8_18 of Queue64_UInt8_146 connect Queue64_UInt8_18.clock, clock connect Queue64_UInt8_18.reset, reset inst Queue64_UInt8_19 of Queue64_UInt8_147 connect Queue64_UInt8_19.clock, clock connect Queue64_UInt8_19.reset, reset inst Queue64_UInt8_20 of Queue64_UInt8_148 connect Queue64_UInt8_20.clock, clock connect Queue64_UInt8_20.reset, reset inst Queue64_UInt8_21 of Queue64_UInt8_149 connect Queue64_UInt8_21.clock, clock connect Queue64_UInt8_21.reset, reset inst Queue64_UInt8_22 of Queue64_UInt8_150 connect Queue64_UInt8_22.clock, clock connect Queue64_UInt8_22.reset, reset inst Queue64_UInt8_23 of Queue64_UInt8_151 connect Queue64_UInt8_23.clock, clock connect Queue64_UInt8_23.reset, reset inst Queue64_UInt8_24 of Queue64_UInt8_152 connect Queue64_UInt8_24.clock, clock connect Queue64_UInt8_24.reset, reset inst Queue64_UInt8_25 of Queue64_UInt8_153 connect Queue64_UInt8_25.clock, clock connect Queue64_UInt8_25.reset, reset inst Queue64_UInt8_26 of Queue64_UInt8_154 connect Queue64_UInt8_26.clock, clock connect Queue64_UInt8_26.reset, reset inst Queue64_UInt8_27 of Queue64_UInt8_155 connect Queue64_UInt8_27.clock, clock connect Queue64_UInt8_27.reset, reset inst Queue64_UInt8_28 of Queue64_UInt8_156 connect Queue64_UInt8_28.clock, clock connect Queue64_UInt8_28.reset, reset inst Queue64_UInt8_29 of Queue64_UInt8_157 connect Queue64_UInt8_29.clock, clock connect Queue64_UInt8_29.reset, reset inst Queue64_UInt8_30 of Queue64_UInt8_158 connect Queue64_UInt8_30.clock, clock connect Queue64_UInt8_30.reset, reset inst Queue64_UInt8_31 of Queue64_UInt8_159 connect Queue64_UInt8_31.clock, clock connect Queue64_UInt8_31.reset, reset node align_shamt = shl(load_info_queue.io.deq.bits.start_byte, 3) node memresp_bits_shifted = dshr(io.l2helperUser.resp.bits.data, align_shamt) connect Queue64_UInt8.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_1.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_2.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_3.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_4.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_5.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_6.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_7.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_8.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_9.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_10.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_11.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_12.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_13.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_14.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_15.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_16.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_17.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_18.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_19.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_20.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_21.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_22.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_23.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_24.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_25.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_26.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_27.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_28.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_29.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_30.io.enq.bits, UInt<1>(0h0) connect Queue64_UInt8_31.io.enq.bits, UInt<1>(0h0) node _idx_T = add(write_start_index, UInt<1>(0h0)) node idx = rem(_idx_T, UInt<6>(0h20)) node _T_54 = eq(UInt<1>(0h0), idx) when _T_54 : node _T_55 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8.io.enq.bits, _T_55 node _T_56 = eq(UInt<1>(0h1), idx) when _T_56 : node _T_57 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_1.io.enq.bits, _T_57 node _T_58 = eq(UInt<2>(0h2), idx) when _T_58 : node _T_59 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_2.io.enq.bits, _T_59 node _T_60 = eq(UInt<2>(0h3), idx) when _T_60 : node _T_61 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_3.io.enq.bits, _T_61 node _T_62 = eq(UInt<3>(0h4), idx) when _T_62 : node _T_63 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_4.io.enq.bits, _T_63 node _T_64 = eq(UInt<3>(0h5), idx) when _T_64 : node _T_65 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_5.io.enq.bits, _T_65 node _T_66 = eq(UInt<3>(0h6), idx) when _T_66 : node _T_67 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_6.io.enq.bits, _T_67 node _T_68 = eq(UInt<3>(0h7), idx) when _T_68 : node _T_69 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_7.io.enq.bits, _T_69 node _T_70 = eq(UInt<4>(0h8), idx) when _T_70 : node _T_71 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_8.io.enq.bits, _T_71 node _T_72 = eq(UInt<4>(0h9), idx) when _T_72 : node _T_73 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_9.io.enq.bits, _T_73 node _T_74 = eq(UInt<4>(0ha), idx) when _T_74 : node _T_75 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_10.io.enq.bits, _T_75 node _T_76 = eq(UInt<4>(0hb), idx) when _T_76 : node _T_77 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_11.io.enq.bits, _T_77 node _T_78 = eq(UInt<4>(0hc), idx) when _T_78 : node _T_79 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_12.io.enq.bits, _T_79 node _T_80 = eq(UInt<4>(0hd), idx) when _T_80 : node _T_81 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_13.io.enq.bits, _T_81 node _T_82 = eq(UInt<4>(0he), idx) when _T_82 : node _T_83 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_14.io.enq.bits, _T_83 node _T_84 = eq(UInt<4>(0hf), idx) when _T_84 : node _T_85 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_15.io.enq.bits, _T_85 node _T_86 = eq(UInt<5>(0h10), idx) when _T_86 : node _T_87 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_16.io.enq.bits, _T_87 node _T_88 = eq(UInt<5>(0h11), idx) when _T_88 : node _T_89 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_17.io.enq.bits, _T_89 node _T_90 = eq(UInt<5>(0h12), idx) when _T_90 : node _T_91 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_18.io.enq.bits, _T_91 node _T_92 = eq(UInt<5>(0h13), idx) when _T_92 : node _T_93 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_19.io.enq.bits, _T_93 node _T_94 = eq(UInt<5>(0h14), idx) when _T_94 : node _T_95 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_20.io.enq.bits, _T_95 node _T_96 = eq(UInt<5>(0h15), idx) when _T_96 : node _T_97 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_21.io.enq.bits, _T_97 node _T_98 = eq(UInt<5>(0h16), idx) when _T_98 : node _T_99 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_22.io.enq.bits, _T_99 node _T_100 = eq(UInt<5>(0h17), idx) when _T_100 : node _T_101 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_23.io.enq.bits, _T_101 node _T_102 = eq(UInt<5>(0h18), idx) when _T_102 : node _T_103 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_24.io.enq.bits, _T_103 node _T_104 = eq(UInt<5>(0h19), idx) when _T_104 : node _T_105 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_25.io.enq.bits, _T_105 node _T_106 = eq(UInt<5>(0h1a), idx) when _T_106 : node _T_107 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_26.io.enq.bits, _T_107 node _T_108 = eq(UInt<5>(0h1b), idx) when _T_108 : node _T_109 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_27.io.enq.bits, _T_109 node _T_110 = eq(UInt<5>(0h1c), idx) when _T_110 : node _T_111 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_28.io.enq.bits, _T_111 node _T_112 = eq(UInt<5>(0h1d), idx) when _T_112 : node _T_113 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_29.io.enq.bits, _T_113 node _T_114 = eq(UInt<5>(0h1e), idx) when _T_114 : node _T_115 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_30.io.enq.bits, _T_115 node _T_116 = eq(UInt<5>(0h1f), idx) when _T_116 : node _T_117 = shr(memresp_bits_shifted, 0) connect Queue64_UInt8_31.io.enq.bits, _T_117 node _idx_T_1 = add(write_start_index, UInt<1>(0h1)) node idx_1 = rem(_idx_T_1, UInt<6>(0h20)) node _T_118 = eq(UInt<1>(0h0), idx_1) when _T_118 : node _T_119 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8.io.enq.bits, _T_119 node _T_120 = eq(UInt<1>(0h1), idx_1) when _T_120 : node _T_121 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_1.io.enq.bits, _T_121 node _T_122 = eq(UInt<2>(0h2), idx_1) when _T_122 : node _T_123 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_2.io.enq.bits, _T_123 node _T_124 = eq(UInt<2>(0h3), idx_1) when _T_124 : node _T_125 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_3.io.enq.bits, _T_125 node _T_126 = eq(UInt<3>(0h4), idx_1) when _T_126 : node _T_127 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_4.io.enq.bits, _T_127 node _T_128 = eq(UInt<3>(0h5), idx_1) when _T_128 : node _T_129 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_5.io.enq.bits, _T_129 node _T_130 = eq(UInt<3>(0h6), idx_1) when _T_130 : node _T_131 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_6.io.enq.bits, _T_131 node _T_132 = eq(UInt<3>(0h7), idx_1) when _T_132 : node _T_133 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_7.io.enq.bits, _T_133 node _T_134 = eq(UInt<4>(0h8), idx_1) when _T_134 : node _T_135 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_8.io.enq.bits, _T_135 node _T_136 = eq(UInt<4>(0h9), idx_1) when _T_136 : node _T_137 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_9.io.enq.bits, _T_137 node _T_138 = eq(UInt<4>(0ha), idx_1) when _T_138 : node _T_139 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_10.io.enq.bits, _T_139 node _T_140 = eq(UInt<4>(0hb), idx_1) when _T_140 : node _T_141 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_11.io.enq.bits, _T_141 node _T_142 = eq(UInt<4>(0hc), idx_1) when _T_142 : node _T_143 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_12.io.enq.bits, _T_143 node _T_144 = eq(UInt<4>(0hd), idx_1) when _T_144 : node _T_145 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_13.io.enq.bits, _T_145 node _T_146 = eq(UInt<4>(0he), idx_1) when _T_146 : node _T_147 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_14.io.enq.bits, _T_147 node _T_148 = eq(UInt<4>(0hf), idx_1) when _T_148 : node _T_149 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_15.io.enq.bits, _T_149 node _T_150 = eq(UInt<5>(0h10), idx_1) when _T_150 : node _T_151 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_16.io.enq.bits, _T_151 node _T_152 = eq(UInt<5>(0h11), idx_1) when _T_152 : node _T_153 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_17.io.enq.bits, _T_153 node _T_154 = eq(UInt<5>(0h12), idx_1) when _T_154 : node _T_155 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_18.io.enq.bits, _T_155 node _T_156 = eq(UInt<5>(0h13), idx_1) when _T_156 : node _T_157 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_19.io.enq.bits, _T_157 node _T_158 = eq(UInt<5>(0h14), idx_1) when _T_158 : node _T_159 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_20.io.enq.bits, _T_159 node _T_160 = eq(UInt<5>(0h15), idx_1) when _T_160 : node _T_161 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_21.io.enq.bits, _T_161 node _T_162 = eq(UInt<5>(0h16), idx_1) when _T_162 : node _T_163 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_22.io.enq.bits, _T_163 node _T_164 = eq(UInt<5>(0h17), idx_1) when _T_164 : node _T_165 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_23.io.enq.bits, _T_165 node _T_166 = eq(UInt<5>(0h18), idx_1) when _T_166 : node _T_167 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_24.io.enq.bits, _T_167 node _T_168 = eq(UInt<5>(0h19), idx_1) when _T_168 : node _T_169 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_25.io.enq.bits, _T_169 node _T_170 = eq(UInt<5>(0h1a), idx_1) when _T_170 : node _T_171 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_26.io.enq.bits, _T_171 node _T_172 = eq(UInt<5>(0h1b), idx_1) when _T_172 : node _T_173 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_27.io.enq.bits, _T_173 node _T_174 = eq(UInt<5>(0h1c), idx_1) when _T_174 : node _T_175 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_28.io.enq.bits, _T_175 node _T_176 = eq(UInt<5>(0h1d), idx_1) when _T_176 : node _T_177 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_29.io.enq.bits, _T_177 node _T_178 = eq(UInt<5>(0h1e), idx_1) when _T_178 : node _T_179 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_30.io.enq.bits, _T_179 node _T_180 = eq(UInt<5>(0h1f), idx_1) when _T_180 : node _T_181 = shr(memresp_bits_shifted, 8) connect Queue64_UInt8_31.io.enq.bits, _T_181 node _idx_T_2 = add(write_start_index, UInt<2>(0h2)) node idx_2 = rem(_idx_T_2, UInt<6>(0h20)) node _T_182 = eq(UInt<1>(0h0), idx_2) when _T_182 : node _T_183 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8.io.enq.bits, _T_183 node _T_184 = eq(UInt<1>(0h1), idx_2) when _T_184 : node _T_185 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_1.io.enq.bits, _T_185 node _T_186 = eq(UInt<2>(0h2), idx_2) when _T_186 : node _T_187 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_2.io.enq.bits, _T_187 node _T_188 = eq(UInt<2>(0h3), idx_2) when _T_188 : node _T_189 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_3.io.enq.bits, _T_189 node _T_190 = eq(UInt<3>(0h4), idx_2) when _T_190 : node _T_191 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_4.io.enq.bits, _T_191 node _T_192 = eq(UInt<3>(0h5), idx_2) when _T_192 : node _T_193 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_5.io.enq.bits, _T_193 node _T_194 = eq(UInt<3>(0h6), idx_2) when _T_194 : node _T_195 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_6.io.enq.bits, _T_195 node _T_196 = eq(UInt<3>(0h7), idx_2) when _T_196 : node _T_197 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_7.io.enq.bits, _T_197 node _T_198 = eq(UInt<4>(0h8), idx_2) when _T_198 : node _T_199 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_8.io.enq.bits, _T_199 node _T_200 = eq(UInt<4>(0h9), idx_2) when _T_200 : node _T_201 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_9.io.enq.bits, _T_201 node _T_202 = eq(UInt<4>(0ha), idx_2) when _T_202 : node _T_203 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_10.io.enq.bits, _T_203 node _T_204 = eq(UInt<4>(0hb), idx_2) when _T_204 : node _T_205 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_11.io.enq.bits, _T_205 node _T_206 = eq(UInt<4>(0hc), idx_2) when _T_206 : node _T_207 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_12.io.enq.bits, _T_207 node _T_208 = eq(UInt<4>(0hd), idx_2) when _T_208 : node _T_209 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_13.io.enq.bits, _T_209 node _T_210 = eq(UInt<4>(0he), idx_2) when _T_210 : node _T_211 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_14.io.enq.bits, _T_211 node _T_212 = eq(UInt<4>(0hf), idx_2) when _T_212 : node _T_213 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_15.io.enq.bits, _T_213 node _T_214 = eq(UInt<5>(0h10), idx_2) when _T_214 : node _T_215 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_16.io.enq.bits, _T_215 node _T_216 = eq(UInt<5>(0h11), idx_2) when _T_216 : node _T_217 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_17.io.enq.bits, _T_217 node _T_218 = eq(UInt<5>(0h12), idx_2) when _T_218 : node _T_219 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_18.io.enq.bits, _T_219 node _T_220 = eq(UInt<5>(0h13), idx_2) when _T_220 : node _T_221 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_19.io.enq.bits, _T_221 node _T_222 = eq(UInt<5>(0h14), idx_2) when _T_222 : node _T_223 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_20.io.enq.bits, _T_223 node _T_224 = eq(UInt<5>(0h15), idx_2) when _T_224 : node _T_225 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_21.io.enq.bits, _T_225 node _T_226 = eq(UInt<5>(0h16), idx_2) when _T_226 : node _T_227 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_22.io.enq.bits, _T_227 node _T_228 = eq(UInt<5>(0h17), idx_2) when _T_228 : node _T_229 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_23.io.enq.bits, _T_229 node _T_230 = eq(UInt<5>(0h18), idx_2) when _T_230 : node _T_231 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_24.io.enq.bits, _T_231 node _T_232 = eq(UInt<5>(0h19), idx_2) when _T_232 : node _T_233 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_25.io.enq.bits, _T_233 node _T_234 = eq(UInt<5>(0h1a), idx_2) when _T_234 : node _T_235 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_26.io.enq.bits, _T_235 node _T_236 = eq(UInt<5>(0h1b), idx_2) when _T_236 : node _T_237 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_27.io.enq.bits, _T_237 node _T_238 = eq(UInt<5>(0h1c), idx_2) when _T_238 : node _T_239 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_28.io.enq.bits, _T_239 node _T_240 = eq(UInt<5>(0h1d), idx_2) when _T_240 : node _T_241 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_29.io.enq.bits, _T_241 node _T_242 = eq(UInt<5>(0h1e), idx_2) when _T_242 : node _T_243 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_30.io.enq.bits, _T_243 node _T_244 = eq(UInt<5>(0h1f), idx_2) when _T_244 : node _T_245 = shr(memresp_bits_shifted, 16) connect Queue64_UInt8_31.io.enq.bits, _T_245 node _idx_T_3 = add(write_start_index, UInt<2>(0h3)) node idx_3 = rem(_idx_T_3, UInt<6>(0h20)) node _T_246 = eq(UInt<1>(0h0), idx_3) when _T_246 : node _T_247 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8.io.enq.bits, _T_247 node _T_248 = eq(UInt<1>(0h1), idx_3) when _T_248 : node _T_249 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_1.io.enq.bits, _T_249 node _T_250 = eq(UInt<2>(0h2), idx_3) when _T_250 : node _T_251 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_2.io.enq.bits, _T_251 node _T_252 = eq(UInt<2>(0h3), idx_3) when _T_252 : node _T_253 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_3.io.enq.bits, _T_253 node _T_254 = eq(UInt<3>(0h4), idx_3) when _T_254 : node _T_255 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_4.io.enq.bits, _T_255 node _T_256 = eq(UInt<3>(0h5), idx_3) when _T_256 : node _T_257 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_5.io.enq.bits, _T_257 node _T_258 = eq(UInt<3>(0h6), idx_3) when _T_258 : node _T_259 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_6.io.enq.bits, _T_259 node _T_260 = eq(UInt<3>(0h7), idx_3) when _T_260 : node _T_261 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_7.io.enq.bits, _T_261 node _T_262 = eq(UInt<4>(0h8), idx_3) when _T_262 : node _T_263 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_8.io.enq.bits, _T_263 node _T_264 = eq(UInt<4>(0h9), idx_3) when _T_264 : node _T_265 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_9.io.enq.bits, _T_265 node _T_266 = eq(UInt<4>(0ha), idx_3) when _T_266 : node _T_267 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_10.io.enq.bits, _T_267 node _T_268 = eq(UInt<4>(0hb), idx_3) when _T_268 : node _T_269 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_11.io.enq.bits, _T_269 node _T_270 = eq(UInt<4>(0hc), idx_3) when _T_270 : node _T_271 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_12.io.enq.bits, _T_271 node _T_272 = eq(UInt<4>(0hd), idx_3) when _T_272 : node _T_273 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_13.io.enq.bits, _T_273 node _T_274 = eq(UInt<4>(0he), idx_3) when _T_274 : node _T_275 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_14.io.enq.bits, _T_275 node _T_276 = eq(UInt<4>(0hf), idx_3) when _T_276 : node _T_277 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_15.io.enq.bits, _T_277 node _T_278 = eq(UInt<5>(0h10), idx_3) when _T_278 : node _T_279 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_16.io.enq.bits, _T_279 node _T_280 = eq(UInt<5>(0h11), idx_3) when _T_280 : node _T_281 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_17.io.enq.bits, _T_281 node _T_282 = eq(UInt<5>(0h12), idx_3) when _T_282 : node _T_283 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_18.io.enq.bits, _T_283 node _T_284 = eq(UInt<5>(0h13), idx_3) when _T_284 : node _T_285 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_19.io.enq.bits, _T_285 node _T_286 = eq(UInt<5>(0h14), idx_3) when _T_286 : node _T_287 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_20.io.enq.bits, _T_287 node _T_288 = eq(UInt<5>(0h15), idx_3) when _T_288 : node _T_289 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_21.io.enq.bits, _T_289 node _T_290 = eq(UInt<5>(0h16), idx_3) when _T_290 : node _T_291 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_22.io.enq.bits, _T_291 node _T_292 = eq(UInt<5>(0h17), idx_3) when _T_292 : node _T_293 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_23.io.enq.bits, _T_293 node _T_294 = eq(UInt<5>(0h18), idx_3) when _T_294 : node _T_295 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_24.io.enq.bits, _T_295 node _T_296 = eq(UInt<5>(0h19), idx_3) when _T_296 : node _T_297 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_25.io.enq.bits, _T_297 node _T_298 = eq(UInt<5>(0h1a), idx_3) when _T_298 : node _T_299 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_26.io.enq.bits, _T_299 node _T_300 = eq(UInt<5>(0h1b), idx_3) when _T_300 : node _T_301 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_27.io.enq.bits, _T_301 node _T_302 = eq(UInt<5>(0h1c), idx_3) when _T_302 : node _T_303 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_28.io.enq.bits, _T_303 node _T_304 = eq(UInt<5>(0h1d), idx_3) when _T_304 : node _T_305 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_29.io.enq.bits, _T_305 node _T_306 = eq(UInt<5>(0h1e), idx_3) when _T_306 : node _T_307 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_30.io.enq.bits, _T_307 node _T_308 = eq(UInt<5>(0h1f), idx_3) when _T_308 : node _T_309 = shr(memresp_bits_shifted, 24) connect Queue64_UInt8_31.io.enq.bits, _T_309 node _idx_T_4 = add(write_start_index, UInt<3>(0h4)) node idx_4 = rem(_idx_T_4, UInt<6>(0h20)) node _T_310 = eq(UInt<1>(0h0), idx_4) when _T_310 : node _T_311 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8.io.enq.bits, _T_311 node _T_312 = eq(UInt<1>(0h1), idx_4) when _T_312 : node _T_313 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_1.io.enq.bits, _T_313 node _T_314 = eq(UInt<2>(0h2), idx_4) when _T_314 : node _T_315 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_2.io.enq.bits, _T_315 node _T_316 = eq(UInt<2>(0h3), idx_4) when _T_316 : node _T_317 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_3.io.enq.bits, _T_317 node _T_318 = eq(UInt<3>(0h4), idx_4) when _T_318 : node _T_319 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_4.io.enq.bits, _T_319 node _T_320 = eq(UInt<3>(0h5), idx_4) when _T_320 : node _T_321 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_5.io.enq.bits, _T_321 node _T_322 = eq(UInt<3>(0h6), idx_4) when _T_322 : node _T_323 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_6.io.enq.bits, _T_323 node _T_324 = eq(UInt<3>(0h7), idx_4) when _T_324 : node _T_325 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_7.io.enq.bits, _T_325 node _T_326 = eq(UInt<4>(0h8), idx_4) when _T_326 : node _T_327 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_8.io.enq.bits, _T_327 node _T_328 = eq(UInt<4>(0h9), idx_4) when _T_328 : node _T_329 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_9.io.enq.bits, _T_329 node _T_330 = eq(UInt<4>(0ha), idx_4) when _T_330 : node _T_331 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_10.io.enq.bits, _T_331 node _T_332 = eq(UInt<4>(0hb), idx_4) when _T_332 : node _T_333 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_11.io.enq.bits, _T_333 node _T_334 = eq(UInt<4>(0hc), idx_4) when _T_334 : node _T_335 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_12.io.enq.bits, _T_335 node _T_336 = eq(UInt<4>(0hd), idx_4) when _T_336 : node _T_337 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_13.io.enq.bits, _T_337 node _T_338 = eq(UInt<4>(0he), idx_4) when _T_338 : node _T_339 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_14.io.enq.bits, _T_339 node _T_340 = eq(UInt<4>(0hf), idx_4) when _T_340 : node _T_341 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_15.io.enq.bits, _T_341 node _T_342 = eq(UInt<5>(0h10), idx_4) when _T_342 : node _T_343 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_16.io.enq.bits, _T_343 node _T_344 = eq(UInt<5>(0h11), idx_4) when _T_344 : node _T_345 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_17.io.enq.bits, _T_345 node _T_346 = eq(UInt<5>(0h12), idx_4) when _T_346 : node _T_347 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_18.io.enq.bits, _T_347 node _T_348 = eq(UInt<5>(0h13), idx_4) when _T_348 : node _T_349 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_19.io.enq.bits, _T_349 node _T_350 = eq(UInt<5>(0h14), idx_4) when _T_350 : node _T_351 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_20.io.enq.bits, _T_351 node _T_352 = eq(UInt<5>(0h15), idx_4) when _T_352 : node _T_353 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_21.io.enq.bits, _T_353 node _T_354 = eq(UInt<5>(0h16), idx_4) when _T_354 : node _T_355 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_22.io.enq.bits, _T_355 node _T_356 = eq(UInt<5>(0h17), idx_4) when _T_356 : node _T_357 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_23.io.enq.bits, _T_357 node _T_358 = eq(UInt<5>(0h18), idx_4) when _T_358 : node _T_359 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_24.io.enq.bits, _T_359 node _T_360 = eq(UInt<5>(0h19), idx_4) when _T_360 : node _T_361 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_25.io.enq.bits, _T_361 node _T_362 = eq(UInt<5>(0h1a), idx_4) when _T_362 : node _T_363 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_26.io.enq.bits, _T_363 node _T_364 = eq(UInt<5>(0h1b), idx_4) when _T_364 : node _T_365 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_27.io.enq.bits, _T_365 node _T_366 = eq(UInt<5>(0h1c), idx_4) when _T_366 : node _T_367 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_28.io.enq.bits, _T_367 node _T_368 = eq(UInt<5>(0h1d), idx_4) when _T_368 : node _T_369 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_29.io.enq.bits, _T_369 node _T_370 = eq(UInt<5>(0h1e), idx_4) when _T_370 : node _T_371 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_30.io.enq.bits, _T_371 node _T_372 = eq(UInt<5>(0h1f), idx_4) when _T_372 : node _T_373 = shr(memresp_bits_shifted, 32) connect Queue64_UInt8_31.io.enq.bits, _T_373 node _idx_T_5 = add(write_start_index, UInt<3>(0h5)) node idx_5 = rem(_idx_T_5, UInt<6>(0h20)) node _T_374 = eq(UInt<1>(0h0), idx_5) when _T_374 : node _T_375 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8.io.enq.bits, _T_375 node _T_376 = eq(UInt<1>(0h1), idx_5) when _T_376 : node _T_377 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_1.io.enq.bits, _T_377 node _T_378 = eq(UInt<2>(0h2), idx_5) when _T_378 : node _T_379 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_2.io.enq.bits, _T_379 node _T_380 = eq(UInt<2>(0h3), idx_5) when _T_380 : node _T_381 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_3.io.enq.bits, _T_381 node _T_382 = eq(UInt<3>(0h4), idx_5) when _T_382 : node _T_383 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_4.io.enq.bits, _T_383 node _T_384 = eq(UInt<3>(0h5), idx_5) when _T_384 : node _T_385 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_5.io.enq.bits, _T_385 node _T_386 = eq(UInt<3>(0h6), idx_5) when _T_386 : node _T_387 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_6.io.enq.bits, _T_387 node _T_388 = eq(UInt<3>(0h7), idx_5) when _T_388 : node _T_389 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_7.io.enq.bits, _T_389 node _T_390 = eq(UInt<4>(0h8), idx_5) when _T_390 : node _T_391 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_8.io.enq.bits, _T_391 node _T_392 = eq(UInt<4>(0h9), idx_5) when _T_392 : node _T_393 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_9.io.enq.bits, _T_393 node _T_394 = eq(UInt<4>(0ha), idx_5) when _T_394 : node _T_395 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_10.io.enq.bits, _T_395 node _T_396 = eq(UInt<4>(0hb), idx_5) when _T_396 : node _T_397 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_11.io.enq.bits, _T_397 node _T_398 = eq(UInt<4>(0hc), idx_5) when _T_398 : node _T_399 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_12.io.enq.bits, _T_399 node _T_400 = eq(UInt<4>(0hd), idx_5) when _T_400 : node _T_401 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_13.io.enq.bits, _T_401 node _T_402 = eq(UInt<4>(0he), idx_5) when _T_402 : node _T_403 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_14.io.enq.bits, _T_403 node _T_404 = eq(UInt<4>(0hf), idx_5) when _T_404 : node _T_405 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_15.io.enq.bits, _T_405 node _T_406 = eq(UInt<5>(0h10), idx_5) when _T_406 : node _T_407 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_16.io.enq.bits, _T_407 node _T_408 = eq(UInt<5>(0h11), idx_5) when _T_408 : node _T_409 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_17.io.enq.bits, _T_409 node _T_410 = eq(UInt<5>(0h12), idx_5) when _T_410 : node _T_411 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_18.io.enq.bits, _T_411 node _T_412 = eq(UInt<5>(0h13), idx_5) when _T_412 : node _T_413 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_19.io.enq.bits, _T_413 node _T_414 = eq(UInt<5>(0h14), idx_5) when _T_414 : node _T_415 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_20.io.enq.bits, _T_415 node _T_416 = eq(UInt<5>(0h15), idx_5) when _T_416 : node _T_417 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_21.io.enq.bits, _T_417 node _T_418 = eq(UInt<5>(0h16), idx_5) when _T_418 : node _T_419 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_22.io.enq.bits, _T_419 node _T_420 = eq(UInt<5>(0h17), idx_5) when _T_420 : node _T_421 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_23.io.enq.bits, _T_421 node _T_422 = eq(UInt<5>(0h18), idx_5) when _T_422 : node _T_423 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_24.io.enq.bits, _T_423 node _T_424 = eq(UInt<5>(0h19), idx_5) when _T_424 : node _T_425 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_25.io.enq.bits, _T_425 node _T_426 = eq(UInt<5>(0h1a), idx_5) when _T_426 : node _T_427 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_26.io.enq.bits, _T_427 node _T_428 = eq(UInt<5>(0h1b), idx_5) when _T_428 : node _T_429 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_27.io.enq.bits, _T_429 node _T_430 = eq(UInt<5>(0h1c), idx_5) when _T_430 : node _T_431 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_28.io.enq.bits, _T_431 node _T_432 = eq(UInt<5>(0h1d), idx_5) when _T_432 : node _T_433 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_29.io.enq.bits, _T_433 node _T_434 = eq(UInt<5>(0h1e), idx_5) when _T_434 : node _T_435 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_30.io.enq.bits, _T_435 node _T_436 = eq(UInt<5>(0h1f), idx_5) when _T_436 : node _T_437 = shr(memresp_bits_shifted, 40) connect Queue64_UInt8_31.io.enq.bits, _T_437 node _idx_T_6 = add(write_start_index, UInt<3>(0h6)) node idx_6 = rem(_idx_T_6, UInt<6>(0h20)) node _T_438 = eq(UInt<1>(0h0), idx_6) when _T_438 : node _T_439 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8.io.enq.bits, _T_439 node _T_440 = eq(UInt<1>(0h1), idx_6) when _T_440 : node _T_441 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_1.io.enq.bits, _T_441 node _T_442 = eq(UInt<2>(0h2), idx_6) when _T_442 : node _T_443 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_2.io.enq.bits, _T_443 node _T_444 = eq(UInt<2>(0h3), idx_6) when _T_444 : node _T_445 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_3.io.enq.bits, _T_445 node _T_446 = eq(UInt<3>(0h4), idx_6) when _T_446 : node _T_447 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_4.io.enq.bits, _T_447 node _T_448 = eq(UInt<3>(0h5), idx_6) when _T_448 : node _T_449 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_5.io.enq.bits, _T_449 node _T_450 = eq(UInt<3>(0h6), idx_6) when _T_450 : node _T_451 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_6.io.enq.bits, _T_451 node _T_452 = eq(UInt<3>(0h7), idx_6) when _T_452 : node _T_453 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_7.io.enq.bits, _T_453 node _T_454 = eq(UInt<4>(0h8), idx_6) when _T_454 : node _T_455 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_8.io.enq.bits, _T_455 node _T_456 = eq(UInt<4>(0h9), idx_6) when _T_456 : node _T_457 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_9.io.enq.bits, _T_457 node _T_458 = eq(UInt<4>(0ha), idx_6) when _T_458 : node _T_459 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_10.io.enq.bits, _T_459 node _T_460 = eq(UInt<4>(0hb), idx_6) when _T_460 : node _T_461 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_11.io.enq.bits, _T_461 node _T_462 = eq(UInt<4>(0hc), idx_6) when _T_462 : node _T_463 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_12.io.enq.bits, _T_463 node _T_464 = eq(UInt<4>(0hd), idx_6) when _T_464 : node _T_465 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_13.io.enq.bits, _T_465 node _T_466 = eq(UInt<4>(0he), idx_6) when _T_466 : node _T_467 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_14.io.enq.bits, _T_467 node _T_468 = eq(UInt<4>(0hf), idx_6) when _T_468 : node _T_469 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_15.io.enq.bits, _T_469 node _T_470 = eq(UInt<5>(0h10), idx_6) when _T_470 : node _T_471 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_16.io.enq.bits, _T_471 node _T_472 = eq(UInt<5>(0h11), idx_6) when _T_472 : node _T_473 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_17.io.enq.bits, _T_473 node _T_474 = eq(UInt<5>(0h12), idx_6) when _T_474 : node _T_475 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_18.io.enq.bits, _T_475 node _T_476 = eq(UInt<5>(0h13), idx_6) when _T_476 : node _T_477 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_19.io.enq.bits, _T_477 node _T_478 = eq(UInt<5>(0h14), idx_6) when _T_478 : node _T_479 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_20.io.enq.bits, _T_479 node _T_480 = eq(UInt<5>(0h15), idx_6) when _T_480 : node _T_481 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_21.io.enq.bits, _T_481 node _T_482 = eq(UInt<5>(0h16), idx_6) when _T_482 : node _T_483 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_22.io.enq.bits, _T_483 node _T_484 = eq(UInt<5>(0h17), idx_6) when _T_484 : node _T_485 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_23.io.enq.bits, _T_485 node _T_486 = eq(UInt<5>(0h18), idx_6) when _T_486 : node _T_487 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_24.io.enq.bits, _T_487 node _T_488 = eq(UInt<5>(0h19), idx_6) when _T_488 : node _T_489 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_25.io.enq.bits, _T_489 node _T_490 = eq(UInt<5>(0h1a), idx_6) when _T_490 : node _T_491 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_26.io.enq.bits, _T_491 node _T_492 = eq(UInt<5>(0h1b), idx_6) when _T_492 : node _T_493 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_27.io.enq.bits, _T_493 node _T_494 = eq(UInt<5>(0h1c), idx_6) when _T_494 : node _T_495 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_28.io.enq.bits, _T_495 node _T_496 = eq(UInt<5>(0h1d), idx_6) when _T_496 : node _T_497 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_29.io.enq.bits, _T_497 node _T_498 = eq(UInt<5>(0h1e), idx_6) when _T_498 : node _T_499 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_30.io.enq.bits, _T_499 node _T_500 = eq(UInt<5>(0h1f), idx_6) when _T_500 : node _T_501 = shr(memresp_bits_shifted, 48) connect Queue64_UInt8_31.io.enq.bits, _T_501 node _idx_T_7 = add(write_start_index, UInt<3>(0h7)) node idx_7 = rem(_idx_T_7, UInt<6>(0h20)) node _T_502 = eq(UInt<1>(0h0), idx_7) when _T_502 : node _T_503 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8.io.enq.bits, _T_503 node _T_504 = eq(UInt<1>(0h1), idx_7) when _T_504 : node _T_505 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_1.io.enq.bits, _T_505 node _T_506 = eq(UInt<2>(0h2), idx_7) when _T_506 : node _T_507 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_2.io.enq.bits, _T_507 node _T_508 = eq(UInt<2>(0h3), idx_7) when _T_508 : node _T_509 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_3.io.enq.bits, _T_509 node _T_510 = eq(UInt<3>(0h4), idx_7) when _T_510 : node _T_511 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_4.io.enq.bits, _T_511 node _T_512 = eq(UInt<3>(0h5), idx_7) when _T_512 : node _T_513 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_5.io.enq.bits, _T_513 node _T_514 = eq(UInt<3>(0h6), idx_7) when _T_514 : node _T_515 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_6.io.enq.bits, _T_515 node _T_516 = eq(UInt<3>(0h7), idx_7) when _T_516 : node _T_517 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_7.io.enq.bits, _T_517 node _T_518 = eq(UInt<4>(0h8), idx_7) when _T_518 : node _T_519 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_8.io.enq.bits, _T_519 node _T_520 = eq(UInt<4>(0h9), idx_7) when _T_520 : node _T_521 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_9.io.enq.bits, _T_521 node _T_522 = eq(UInt<4>(0ha), idx_7) when _T_522 : node _T_523 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_10.io.enq.bits, _T_523 node _T_524 = eq(UInt<4>(0hb), idx_7) when _T_524 : node _T_525 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_11.io.enq.bits, _T_525 node _T_526 = eq(UInt<4>(0hc), idx_7) when _T_526 : node _T_527 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_12.io.enq.bits, _T_527 node _T_528 = eq(UInt<4>(0hd), idx_7) when _T_528 : node _T_529 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_13.io.enq.bits, _T_529 node _T_530 = eq(UInt<4>(0he), idx_7) when _T_530 : node _T_531 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_14.io.enq.bits, _T_531 node _T_532 = eq(UInt<4>(0hf), idx_7) when _T_532 : node _T_533 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_15.io.enq.bits, _T_533 node _T_534 = eq(UInt<5>(0h10), idx_7) when _T_534 : node _T_535 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_16.io.enq.bits, _T_535 node _T_536 = eq(UInt<5>(0h11), idx_7) when _T_536 : node _T_537 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_17.io.enq.bits, _T_537 node _T_538 = eq(UInt<5>(0h12), idx_7) when _T_538 : node _T_539 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_18.io.enq.bits, _T_539 node _T_540 = eq(UInt<5>(0h13), idx_7) when _T_540 : node _T_541 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_19.io.enq.bits, _T_541 node _T_542 = eq(UInt<5>(0h14), idx_7) when _T_542 : node _T_543 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_20.io.enq.bits, _T_543 node _T_544 = eq(UInt<5>(0h15), idx_7) when _T_544 : node _T_545 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_21.io.enq.bits, _T_545 node _T_546 = eq(UInt<5>(0h16), idx_7) when _T_546 : node _T_547 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_22.io.enq.bits, _T_547 node _T_548 = eq(UInt<5>(0h17), idx_7) when _T_548 : node _T_549 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_23.io.enq.bits, _T_549 node _T_550 = eq(UInt<5>(0h18), idx_7) when _T_550 : node _T_551 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_24.io.enq.bits, _T_551 node _T_552 = eq(UInt<5>(0h19), idx_7) when _T_552 : node _T_553 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_25.io.enq.bits, _T_553 node _T_554 = eq(UInt<5>(0h1a), idx_7) when _T_554 : node _T_555 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_26.io.enq.bits, _T_555 node _T_556 = eq(UInt<5>(0h1b), idx_7) when _T_556 : node _T_557 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_27.io.enq.bits, _T_557 node _T_558 = eq(UInt<5>(0h1c), idx_7) when _T_558 : node _T_559 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_28.io.enq.bits, _T_559 node _T_560 = eq(UInt<5>(0h1d), idx_7) when _T_560 : node _T_561 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_29.io.enq.bits, _T_561 node _T_562 = eq(UInt<5>(0h1e), idx_7) when _T_562 : node _T_563 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_30.io.enq.bits, _T_563 node _T_564 = eq(UInt<5>(0h1f), idx_7) when _T_564 : node _T_565 = shr(memresp_bits_shifted, 56) connect Queue64_UInt8_31.io.enq.bits, _T_565 node _idx_T_8 = add(write_start_index, UInt<4>(0h8)) node idx_8 = rem(_idx_T_8, UInt<6>(0h20)) node _T_566 = eq(UInt<1>(0h0), idx_8) when _T_566 : node _T_567 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8.io.enq.bits, _T_567 node _T_568 = eq(UInt<1>(0h1), idx_8) when _T_568 : node _T_569 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_1.io.enq.bits, _T_569 node _T_570 = eq(UInt<2>(0h2), idx_8) when _T_570 : node _T_571 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_2.io.enq.bits, _T_571 node _T_572 = eq(UInt<2>(0h3), idx_8) when _T_572 : node _T_573 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_3.io.enq.bits, _T_573 node _T_574 = eq(UInt<3>(0h4), idx_8) when _T_574 : node _T_575 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_4.io.enq.bits, _T_575 node _T_576 = eq(UInt<3>(0h5), idx_8) when _T_576 : node _T_577 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_5.io.enq.bits, _T_577 node _T_578 = eq(UInt<3>(0h6), idx_8) when _T_578 : node _T_579 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_6.io.enq.bits, _T_579 node _T_580 = eq(UInt<3>(0h7), idx_8) when _T_580 : node _T_581 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_7.io.enq.bits, _T_581 node _T_582 = eq(UInt<4>(0h8), idx_8) when _T_582 : node _T_583 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_8.io.enq.bits, _T_583 node _T_584 = eq(UInt<4>(0h9), idx_8) when _T_584 : node _T_585 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_9.io.enq.bits, _T_585 node _T_586 = eq(UInt<4>(0ha), idx_8) when _T_586 : node _T_587 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_10.io.enq.bits, _T_587 node _T_588 = eq(UInt<4>(0hb), idx_8) when _T_588 : node _T_589 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_11.io.enq.bits, _T_589 node _T_590 = eq(UInt<4>(0hc), idx_8) when _T_590 : node _T_591 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_12.io.enq.bits, _T_591 node _T_592 = eq(UInt<4>(0hd), idx_8) when _T_592 : node _T_593 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_13.io.enq.bits, _T_593 node _T_594 = eq(UInt<4>(0he), idx_8) when _T_594 : node _T_595 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_14.io.enq.bits, _T_595 node _T_596 = eq(UInt<4>(0hf), idx_8) when _T_596 : node _T_597 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_15.io.enq.bits, _T_597 node _T_598 = eq(UInt<5>(0h10), idx_8) when _T_598 : node _T_599 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_16.io.enq.bits, _T_599 node _T_600 = eq(UInt<5>(0h11), idx_8) when _T_600 : node _T_601 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_17.io.enq.bits, _T_601 node _T_602 = eq(UInt<5>(0h12), idx_8) when _T_602 : node _T_603 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_18.io.enq.bits, _T_603 node _T_604 = eq(UInt<5>(0h13), idx_8) when _T_604 : node _T_605 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_19.io.enq.bits, _T_605 node _T_606 = eq(UInt<5>(0h14), idx_8) when _T_606 : node _T_607 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_20.io.enq.bits, _T_607 node _T_608 = eq(UInt<5>(0h15), idx_8) when _T_608 : node _T_609 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_21.io.enq.bits, _T_609 node _T_610 = eq(UInt<5>(0h16), idx_8) when _T_610 : node _T_611 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_22.io.enq.bits, _T_611 node _T_612 = eq(UInt<5>(0h17), idx_8) when _T_612 : node _T_613 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_23.io.enq.bits, _T_613 node _T_614 = eq(UInt<5>(0h18), idx_8) when _T_614 : node _T_615 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_24.io.enq.bits, _T_615 node _T_616 = eq(UInt<5>(0h19), idx_8) when _T_616 : node _T_617 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_25.io.enq.bits, _T_617 node _T_618 = eq(UInt<5>(0h1a), idx_8) when _T_618 : node _T_619 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_26.io.enq.bits, _T_619 node _T_620 = eq(UInt<5>(0h1b), idx_8) when _T_620 : node _T_621 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_27.io.enq.bits, _T_621 node _T_622 = eq(UInt<5>(0h1c), idx_8) when _T_622 : node _T_623 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_28.io.enq.bits, _T_623 node _T_624 = eq(UInt<5>(0h1d), idx_8) when _T_624 : node _T_625 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_29.io.enq.bits, _T_625 node _T_626 = eq(UInt<5>(0h1e), idx_8) when _T_626 : node _T_627 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_30.io.enq.bits, _T_627 node _T_628 = eq(UInt<5>(0h1f), idx_8) when _T_628 : node _T_629 = shr(memresp_bits_shifted, 64) connect Queue64_UInt8_31.io.enq.bits, _T_629 node _idx_T_9 = add(write_start_index, UInt<4>(0h9)) node idx_9 = rem(_idx_T_9, UInt<6>(0h20)) node _T_630 = eq(UInt<1>(0h0), idx_9) when _T_630 : node _T_631 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8.io.enq.bits, _T_631 node _T_632 = eq(UInt<1>(0h1), idx_9) when _T_632 : node _T_633 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_1.io.enq.bits, _T_633 node _T_634 = eq(UInt<2>(0h2), idx_9) when _T_634 : node _T_635 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_2.io.enq.bits, _T_635 node _T_636 = eq(UInt<2>(0h3), idx_9) when _T_636 : node _T_637 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_3.io.enq.bits, _T_637 node _T_638 = eq(UInt<3>(0h4), idx_9) when _T_638 : node _T_639 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_4.io.enq.bits, _T_639 node _T_640 = eq(UInt<3>(0h5), idx_9) when _T_640 : node _T_641 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_5.io.enq.bits, _T_641 node _T_642 = eq(UInt<3>(0h6), idx_9) when _T_642 : node _T_643 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_6.io.enq.bits, _T_643 node _T_644 = eq(UInt<3>(0h7), idx_9) when _T_644 : node _T_645 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_7.io.enq.bits, _T_645 node _T_646 = eq(UInt<4>(0h8), idx_9) when _T_646 : node _T_647 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_8.io.enq.bits, _T_647 node _T_648 = eq(UInt<4>(0h9), idx_9) when _T_648 : node _T_649 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_9.io.enq.bits, _T_649 node _T_650 = eq(UInt<4>(0ha), idx_9) when _T_650 : node _T_651 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_10.io.enq.bits, _T_651 node _T_652 = eq(UInt<4>(0hb), idx_9) when _T_652 : node _T_653 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_11.io.enq.bits, _T_653 node _T_654 = eq(UInt<4>(0hc), idx_9) when _T_654 : node _T_655 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_12.io.enq.bits, _T_655 node _T_656 = eq(UInt<4>(0hd), idx_9) when _T_656 : node _T_657 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_13.io.enq.bits, _T_657 node _T_658 = eq(UInt<4>(0he), idx_9) when _T_658 : node _T_659 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_14.io.enq.bits, _T_659 node _T_660 = eq(UInt<4>(0hf), idx_9) when _T_660 : node _T_661 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_15.io.enq.bits, _T_661 node _T_662 = eq(UInt<5>(0h10), idx_9) when _T_662 : node _T_663 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_16.io.enq.bits, _T_663 node _T_664 = eq(UInt<5>(0h11), idx_9) when _T_664 : node _T_665 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_17.io.enq.bits, _T_665 node _T_666 = eq(UInt<5>(0h12), idx_9) when _T_666 : node _T_667 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_18.io.enq.bits, _T_667 node _T_668 = eq(UInt<5>(0h13), idx_9) when _T_668 : node _T_669 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_19.io.enq.bits, _T_669 node _T_670 = eq(UInt<5>(0h14), idx_9) when _T_670 : node _T_671 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_20.io.enq.bits, _T_671 node _T_672 = eq(UInt<5>(0h15), idx_9) when _T_672 : node _T_673 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_21.io.enq.bits, _T_673 node _T_674 = eq(UInt<5>(0h16), idx_9) when _T_674 : node _T_675 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_22.io.enq.bits, _T_675 node _T_676 = eq(UInt<5>(0h17), idx_9) when _T_676 : node _T_677 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_23.io.enq.bits, _T_677 node _T_678 = eq(UInt<5>(0h18), idx_9) when _T_678 : node _T_679 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_24.io.enq.bits, _T_679 node _T_680 = eq(UInt<5>(0h19), idx_9) when _T_680 : node _T_681 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_25.io.enq.bits, _T_681 node _T_682 = eq(UInt<5>(0h1a), idx_9) when _T_682 : node _T_683 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_26.io.enq.bits, _T_683 node _T_684 = eq(UInt<5>(0h1b), idx_9) when _T_684 : node _T_685 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_27.io.enq.bits, _T_685 node _T_686 = eq(UInt<5>(0h1c), idx_9) when _T_686 : node _T_687 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_28.io.enq.bits, _T_687 node _T_688 = eq(UInt<5>(0h1d), idx_9) when _T_688 : node _T_689 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_29.io.enq.bits, _T_689 node _T_690 = eq(UInt<5>(0h1e), idx_9) when _T_690 : node _T_691 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_30.io.enq.bits, _T_691 node _T_692 = eq(UInt<5>(0h1f), idx_9) when _T_692 : node _T_693 = shr(memresp_bits_shifted, 72) connect Queue64_UInt8_31.io.enq.bits, _T_693 node _idx_T_10 = add(write_start_index, UInt<4>(0ha)) node idx_10 = rem(_idx_T_10, UInt<6>(0h20)) node _T_694 = eq(UInt<1>(0h0), idx_10) when _T_694 : node _T_695 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8.io.enq.bits, _T_695 node _T_696 = eq(UInt<1>(0h1), idx_10) when _T_696 : node _T_697 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_1.io.enq.bits, _T_697 node _T_698 = eq(UInt<2>(0h2), idx_10) when _T_698 : node _T_699 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_2.io.enq.bits, _T_699 node _T_700 = eq(UInt<2>(0h3), idx_10) when _T_700 : node _T_701 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_3.io.enq.bits, _T_701 node _T_702 = eq(UInt<3>(0h4), idx_10) when _T_702 : node _T_703 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_4.io.enq.bits, _T_703 node _T_704 = eq(UInt<3>(0h5), idx_10) when _T_704 : node _T_705 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_5.io.enq.bits, _T_705 node _T_706 = eq(UInt<3>(0h6), idx_10) when _T_706 : node _T_707 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_6.io.enq.bits, _T_707 node _T_708 = eq(UInt<3>(0h7), idx_10) when _T_708 : node _T_709 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_7.io.enq.bits, _T_709 node _T_710 = eq(UInt<4>(0h8), idx_10) when _T_710 : node _T_711 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_8.io.enq.bits, _T_711 node _T_712 = eq(UInt<4>(0h9), idx_10) when _T_712 : node _T_713 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_9.io.enq.bits, _T_713 node _T_714 = eq(UInt<4>(0ha), idx_10) when _T_714 : node _T_715 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_10.io.enq.bits, _T_715 node _T_716 = eq(UInt<4>(0hb), idx_10) when _T_716 : node _T_717 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_11.io.enq.bits, _T_717 node _T_718 = eq(UInt<4>(0hc), idx_10) when _T_718 : node _T_719 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_12.io.enq.bits, _T_719 node _T_720 = eq(UInt<4>(0hd), idx_10) when _T_720 : node _T_721 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_13.io.enq.bits, _T_721 node _T_722 = eq(UInt<4>(0he), idx_10) when _T_722 : node _T_723 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_14.io.enq.bits, _T_723 node _T_724 = eq(UInt<4>(0hf), idx_10) when _T_724 : node _T_725 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_15.io.enq.bits, _T_725 node _T_726 = eq(UInt<5>(0h10), idx_10) when _T_726 : node _T_727 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_16.io.enq.bits, _T_727 node _T_728 = eq(UInt<5>(0h11), idx_10) when _T_728 : node _T_729 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_17.io.enq.bits, _T_729 node _T_730 = eq(UInt<5>(0h12), idx_10) when _T_730 : node _T_731 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_18.io.enq.bits, _T_731 node _T_732 = eq(UInt<5>(0h13), idx_10) when _T_732 : node _T_733 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_19.io.enq.bits, _T_733 node _T_734 = eq(UInt<5>(0h14), idx_10) when _T_734 : node _T_735 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_20.io.enq.bits, _T_735 node _T_736 = eq(UInt<5>(0h15), idx_10) when _T_736 : node _T_737 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_21.io.enq.bits, _T_737 node _T_738 = eq(UInt<5>(0h16), idx_10) when _T_738 : node _T_739 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_22.io.enq.bits, _T_739 node _T_740 = eq(UInt<5>(0h17), idx_10) when _T_740 : node _T_741 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_23.io.enq.bits, _T_741 node _T_742 = eq(UInt<5>(0h18), idx_10) when _T_742 : node _T_743 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_24.io.enq.bits, _T_743 node _T_744 = eq(UInt<5>(0h19), idx_10) when _T_744 : node _T_745 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_25.io.enq.bits, _T_745 node _T_746 = eq(UInt<5>(0h1a), idx_10) when _T_746 : node _T_747 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_26.io.enq.bits, _T_747 node _T_748 = eq(UInt<5>(0h1b), idx_10) when _T_748 : node _T_749 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_27.io.enq.bits, _T_749 node _T_750 = eq(UInt<5>(0h1c), idx_10) when _T_750 : node _T_751 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_28.io.enq.bits, _T_751 node _T_752 = eq(UInt<5>(0h1d), idx_10) when _T_752 : node _T_753 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_29.io.enq.bits, _T_753 node _T_754 = eq(UInt<5>(0h1e), idx_10) when _T_754 : node _T_755 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_30.io.enq.bits, _T_755 node _T_756 = eq(UInt<5>(0h1f), idx_10) when _T_756 : node _T_757 = shr(memresp_bits_shifted, 80) connect Queue64_UInt8_31.io.enq.bits, _T_757 node _idx_T_11 = add(write_start_index, UInt<4>(0hb)) node idx_11 = rem(_idx_T_11, UInt<6>(0h20)) node _T_758 = eq(UInt<1>(0h0), idx_11) when _T_758 : node _T_759 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8.io.enq.bits, _T_759 node _T_760 = eq(UInt<1>(0h1), idx_11) when _T_760 : node _T_761 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_1.io.enq.bits, _T_761 node _T_762 = eq(UInt<2>(0h2), idx_11) when _T_762 : node _T_763 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_2.io.enq.bits, _T_763 node _T_764 = eq(UInt<2>(0h3), idx_11) when _T_764 : node _T_765 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_3.io.enq.bits, _T_765 node _T_766 = eq(UInt<3>(0h4), idx_11) when _T_766 : node _T_767 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_4.io.enq.bits, _T_767 node _T_768 = eq(UInt<3>(0h5), idx_11) when _T_768 : node _T_769 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_5.io.enq.bits, _T_769 node _T_770 = eq(UInt<3>(0h6), idx_11) when _T_770 : node _T_771 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_6.io.enq.bits, _T_771 node _T_772 = eq(UInt<3>(0h7), idx_11) when _T_772 : node _T_773 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_7.io.enq.bits, _T_773 node _T_774 = eq(UInt<4>(0h8), idx_11) when _T_774 : node _T_775 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_8.io.enq.bits, _T_775 node _T_776 = eq(UInt<4>(0h9), idx_11) when _T_776 : node _T_777 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_9.io.enq.bits, _T_777 node _T_778 = eq(UInt<4>(0ha), idx_11) when _T_778 : node _T_779 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_10.io.enq.bits, _T_779 node _T_780 = eq(UInt<4>(0hb), idx_11) when _T_780 : node _T_781 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_11.io.enq.bits, _T_781 node _T_782 = eq(UInt<4>(0hc), idx_11) when _T_782 : node _T_783 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_12.io.enq.bits, _T_783 node _T_784 = eq(UInt<4>(0hd), idx_11) when _T_784 : node _T_785 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_13.io.enq.bits, _T_785 node _T_786 = eq(UInt<4>(0he), idx_11) when _T_786 : node _T_787 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_14.io.enq.bits, _T_787 node _T_788 = eq(UInt<4>(0hf), idx_11) when _T_788 : node _T_789 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_15.io.enq.bits, _T_789 node _T_790 = eq(UInt<5>(0h10), idx_11) when _T_790 : node _T_791 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_16.io.enq.bits, _T_791 node _T_792 = eq(UInt<5>(0h11), idx_11) when _T_792 : node _T_793 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_17.io.enq.bits, _T_793 node _T_794 = eq(UInt<5>(0h12), idx_11) when _T_794 : node _T_795 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_18.io.enq.bits, _T_795 node _T_796 = eq(UInt<5>(0h13), idx_11) when _T_796 : node _T_797 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_19.io.enq.bits, _T_797 node _T_798 = eq(UInt<5>(0h14), idx_11) when _T_798 : node _T_799 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_20.io.enq.bits, _T_799 node _T_800 = eq(UInt<5>(0h15), idx_11) when _T_800 : node _T_801 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_21.io.enq.bits, _T_801 node _T_802 = eq(UInt<5>(0h16), idx_11) when _T_802 : node _T_803 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_22.io.enq.bits, _T_803 node _T_804 = eq(UInt<5>(0h17), idx_11) when _T_804 : node _T_805 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_23.io.enq.bits, _T_805 node _T_806 = eq(UInt<5>(0h18), idx_11) when _T_806 : node _T_807 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_24.io.enq.bits, _T_807 node _T_808 = eq(UInt<5>(0h19), idx_11) when _T_808 : node _T_809 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_25.io.enq.bits, _T_809 node _T_810 = eq(UInt<5>(0h1a), idx_11) when _T_810 : node _T_811 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_26.io.enq.bits, _T_811 node _T_812 = eq(UInt<5>(0h1b), idx_11) when _T_812 : node _T_813 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_27.io.enq.bits, _T_813 node _T_814 = eq(UInt<5>(0h1c), idx_11) when _T_814 : node _T_815 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_28.io.enq.bits, _T_815 node _T_816 = eq(UInt<5>(0h1d), idx_11) when _T_816 : node _T_817 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_29.io.enq.bits, _T_817 node _T_818 = eq(UInt<5>(0h1e), idx_11) when _T_818 : node _T_819 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_30.io.enq.bits, _T_819 node _T_820 = eq(UInt<5>(0h1f), idx_11) when _T_820 : node _T_821 = shr(memresp_bits_shifted, 88) connect Queue64_UInt8_31.io.enq.bits, _T_821 node _idx_T_12 = add(write_start_index, UInt<4>(0hc)) node idx_12 = rem(_idx_T_12, UInt<6>(0h20)) node _T_822 = eq(UInt<1>(0h0), idx_12) when _T_822 : node _T_823 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8.io.enq.bits, _T_823 node _T_824 = eq(UInt<1>(0h1), idx_12) when _T_824 : node _T_825 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_1.io.enq.bits, _T_825 node _T_826 = eq(UInt<2>(0h2), idx_12) when _T_826 : node _T_827 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_2.io.enq.bits, _T_827 node _T_828 = eq(UInt<2>(0h3), idx_12) when _T_828 : node _T_829 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_3.io.enq.bits, _T_829 node _T_830 = eq(UInt<3>(0h4), idx_12) when _T_830 : node _T_831 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_4.io.enq.bits, _T_831 node _T_832 = eq(UInt<3>(0h5), idx_12) when _T_832 : node _T_833 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_5.io.enq.bits, _T_833 node _T_834 = eq(UInt<3>(0h6), idx_12) when _T_834 : node _T_835 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_6.io.enq.bits, _T_835 node _T_836 = eq(UInt<3>(0h7), idx_12) when _T_836 : node _T_837 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_7.io.enq.bits, _T_837 node _T_838 = eq(UInt<4>(0h8), idx_12) when _T_838 : node _T_839 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_8.io.enq.bits, _T_839 node _T_840 = eq(UInt<4>(0h9), idx_12) when _T_840 : node _T_841 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_9.io.enq.bits, _T_841 node _T_842 = eq(UInt<4>(0ha), idx_12) when _T_842 : node _T_843 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_10.io.enq.bits, _T_843 node _T_844 = eq(UInt<4>(0hb), idx_12) when _T_844 : node _T_845 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_11.io.enq.bits, _T_845 node _T_846 = eq(UInt<4>(0hc), idx_12) when _T_846 : node _T_847 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_12.io.enq.bits, _T_847 node _T_848 = eq(UInt<4>(0hd), idx_12) when _T_848 : node _T_849 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_13.io.enq.bits, _T_849 node _T_850 = eq(UInt<4>(0he), idx_12) when _T_850 : node _T_851 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_14.io.enq.bits, _T_851 node _T_852 = eq(UInt<4>(0hf), idx_12) when _T_852 : node _T_853 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_15.io.enq.bits, _T_853 node _T_854 = eq(UInt<5>(0h10), idx_12) when _T_854 : node _T_855 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_16.io.enq.bits, _T_855 node _T_856 = eq(UInt<5>(0h11), idx_12) when _T_856 : node _T_857 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_17.io.enq.bits, _T_857 node _T_858 = eq(UInt<5>(0h12), idx_12) when _T_858 : node _T_859 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_18.io.enq.bits, _T_859 node _T_860 = eq(UInt<5>(0h13), idx_12) when _T_860 : node _T_861 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_19.io.enq.bits, _T_861 node _T_862 = eq(UInt<5>(0h14), idx_12) when _T_862 : node _T_863 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_20.io.enq.bits, _T_863 node _T_864 = eq(UInt<5>(0h15), idx_12) when _T_864 : node _T_865 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_21.io.enq.bits, _T_865 node _T_866 = eq(UInt<5>(0h16), idx_12) when _T_866 : node _T_867 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_22.io.enq.bits, _T_867 node _T_868 = eq(UInt<5>(0h17), idx_12) when _T_868 : node _T_869 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_23.io.enq.bits, _T_869 node _T_870 = eq(UInt<5>(0h18), idx_12) when _T_870 : node _T_871 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_24.io.enq.bits, _T_871 node _T_872 = eq(UInt<5>(0h19), idx_12) when _T_872 : node _T_873 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_25.io.enq.bits, _T_873 node _T_874 = eq(UInt<5>(0h1a), idx_12) when _T_874 : node _T_875 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_26.io.enq.bits, _T_875 node _T_876 = eq(UInt<5>(0h1b), idx_12) when _T_876 : node _T_877 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_27.io.enq.bits, _T_877 node _T_878 = eq(UInt<5>(0h1c), idx_12) when _T_878 : node _T_879 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_28.io.enq.bits, _T_879 node _T_880 = eq(UInt<5>(0h1d), idx_12) when _T_880 : node _T_881 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_29.io.enq.bits, _T_881 node _T_882 = eq(UInt<5>(0h1e), idx_12) when _T_882 : node _T_883 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_30.io.enq.bits, _T_883 node _T_884 = eq(UInt<5>(0h1f), idx_12) when _T_884 : node _T_885 = shr(memresp_bits_shifted, 96) connect Queue64_UInt8_31.io.enq.bits, _T_885 node _idx_T_13 = add(write_start_index, UInt<4>(0hd)) node idx_13 = rem(_idx_T_13, UInt<6>(0h20)) node _T_886 = eq(UInt<1>(0h0), idx_13) when _T_886 : node _T_887 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8.io.enq.bits, _T_887 node _T_888 = eq(UInt<1>(0h1), idx_13) when _T_888 : node _T_889 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_1.io.enq.bits, _T_889 node _T_890 = eq(UInt<2>(0h2), idx_13) when _T_890 : node _T_891 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_2.io.enq.bits, _T_891 node _T_892 = eq(UInt<2>(0h3), idx_13) when _T_892 : node _T_893 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_3.io.enq.bits, _T_893 node _T_894 = eq(UInt<3>(0h4), idx_13) when _T_894 : node _T_895 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_4.io.enq.bits, _T_895 node _T_896 = eq(UInt<3>(0h5), idx_13) when _T_896 : node _T_897 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_5.io.enq.bits, _T_897 node _T_898 = eq(UInt<3>(0h6), idx_13) when _T_898 : node _T_899 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_6.io.enq.bits, _T_899 node _T_900 = eq(UInt<3>(0h7), idx_13) when _T_900 : node _T_901 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_7.io.enq.bits, _T_901 node _T_902 = eq(UInt<4>(0h8), idx_13) when _T_902 : node _T_903 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_8.io.enq.bits, _T_903 node _T_904 = eq(UInt<4>(0h9), idx_13) when _T_904 : node _T_905 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_9.io.enq.bits, _T_905 node _T_906 = eq(UInt<4>(0ha), idx_13) when _T_906 : node _T_907 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_10.io.enq.bits, _T_907 node _T_908 = eq(UInt<4>(0hb), idx_13) when _T_908 : node _T_909 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_11.io.enq.bits, _T_909 node _T_910 = eq(UInt<4>(0hc), idx_13) when _T_910 : node _T_911 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_12.io.enq.bits, _T_911 node _T_912 = eq(UInt<4>(0hd), idx_13) when _T_912 : node _T_913 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_13.io.enq.bits, _T_913 node _T_914 = eq(UInt<4>(0he), idx_13) when _T_914 : node _T_915 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_14.io.enq.bits, _T_915 node _T_916 = eq(UInt<4>(0hf), idx_13) when _T_916 : node _T_917 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_15.io.enq.bits, _T_917 node _T_918 = eq(UInt<5>(0h10), idx_13) when _T_918 : node _T_919 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_16.io.enq.bits, _T_919 node _T_920 = eq(UInt<5>(0h11), idx_13) when _T_920 : node _T_921 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_17.io.enq.bits, _T_921 node _T_922 = eq(UInt<5>(0h12), idx_13) when _T_922 : node _T_923 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_18.io.enq.bits, _T_923 node _T_924 = eq(UInt<5>(0h13), idx_13) when _T_924 : node _T_925 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_19.io.enq.bits, _T_925 node _T_926 = eq(UInt<5>(0h14), idx_13) when _T_926 : node _T_927 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_20.io.enq.bits, _T_927 node _T_928 = eq(UInt<5>(0h15), idx_13) when _T_928 : node _T_929 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_21.io.enq.bits, _T_929 node _T_930 = eq(UInt<5>(0h16), idx_13) when _T_930 : node _T_931 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_22.io.enq.bits, _T_931 node _T_932 = eq(UInt<5>(0h17), idx_13) when _T_932 : node _T_933 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_23.io.enq.bits, _T_933 node _T_934 = eq(UInt<5>(0h18), idx_13) when _T_934 : node _T_935 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_24.io.enq.bits, _T_935 node _T_936 = eq(UInt<5>(0h19), idx_13) when _T_936 : node _T_937 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_25.io.enq.bits, _T_937 node _T_938 = eq(UInt<5>(0h1a), idx_13) when _T_938 : node _T_939 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_26.io.enq.bits, _T_939 node _T_940 = eq(UInt<5>(0h1b), idx_13) when _T_940 : node _T_941 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_27.io.enq.bits, _T_941 node _T_942 = eq(UInt<5>(0h1c), idx_13) when _T_942 : node _T_943 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_28.io.enq.bits, _T_943 node _T_944 = eq(UInt<5>(0h1d), idx_13) when _T_944 : node _T_945 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_29.io.enq.bits, _T_945 node _T_946 = eq(UInt<5>(0h1e), idx_13) when _T_946 : node _T_947 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_30.io.enq.bits, _T_947 node _T_948 = eq(UInt<5>(0h1f), idx_13) when _T_948 : node _T_949 = shr(memresp_bits_shifted, 104) connect Queue64_UInt8_31.io.enq.bits, _T_949 node _idx_T_14 = add(write_start_index, UInt<4>(0he)) node idx_14 = rem(_idx_T_14, UInt<6>(0h20)) node _T_950 = eq(UInt<1>(0h0), idx_14) when _T_950 : node _T_951 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8.io.enq.bits, _T_951 node _T_952 = eq(UInt<1>(0h1), idx_14) when _T_952 : node _T_953 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_1.io.enq.bits, _T_953 node _T_954 = eq(UInt<2>(0h2), idx_14) when _T_954 : node _T_955 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_2.io.enq.bits, _T_955 node _T_956 = eq(UInt<2>(0h3), idx_14) when _T_956 : node _T_957 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_3.io.enq.bits, _T_957 node _T_958 = eq(UInt<3>(0h4), idx_14) when _T_958 : node _T_959 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_4.io.enq.bits, _T_959 node _T_960 = eq(UInt<3>(0h5), idx_14) when _T_960 : node _T_961 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_5.io.enq.bits, _T_961 node _T_962 = eq(UInt<3>(0h6), idx_14) when _T_962 : node _T_963 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_6.io.enq.bits, _T_963 node _T_964 = eq(UInt<3>(0h7), idx_14) when _T_964 : node _T_965 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_7.io.enq.bits, _T_965 node _T_966 = eq(UInt<4>(0h8), idx_14) when _T_966 : node _T_967 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_8.io.enq.bits, _T_967 node _T_968 = eq(UInt<4>(0h9), idx_14) when _T_968 : node _T_969 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_9.io.enq.bits, _T_969 node _T_970 = eq(UInt<4>(0ha), idx_14) when _T_970 : node _T_971 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_10.io.enq.bits, _T_971 node _T_972 = eq(UInt<4>(0hb), idx_14) when _T_972 : node _T_973 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_11.io.enq.bits, _T_973 node _T_974 = eq(UInt<4>(0hc), idx_14) when _T_974 : node _T_975 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_12.io.enq.bits, _T_975 node _T_976 = eq(UInt<4>(0hd), idx_14) when _T_976 : node _T_977 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_13.io.enq.bits, _T_977 node _T_978 = eq(UInt<4>(0he), idx_14) when _T_978 : node _T_979 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_14.io.enq.bits, _T_979 node _T_980 = eq(UInt<4>(0hf), idx_14) when _T_980 : node _T_981 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_15.io.enq.bits, _T_981 node _T_982 = eq(UInt<5>(0h10), idx_14) when _T_982 : node _T_983 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_16.io.enq.bits, _T_983 node _T_984 = eq(UInt<5>(0h11), idx_14) when _T_984 : node _T_985 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_17.io.enq.bits, _T_985 node _T_986 = eq(UInt<5>(0h12), idx_14) when _T_986 : node _T_987 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_18.io.enq.bits, _T_987 node _T_988 = eq(UInt<5>(0h13), idx_14) when _T_988 : node _T_989 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_19.io.enq.bits, _T_989 node _T_990 = eq(UInt<5>(0h14), idx_14) when _T_990 : node _T_991 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_20.io.enq.bits, _T_991 node _T_992 = eq(UInt<5>(0h15), idx_14) when _T_992 : node _T_993 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_21.io.enq.bits, _T_993 node _T_994 = eq(UInt<5>(0h16), idx_14) when _T_994 : node _T_995 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_22.io.enq.bits, _T_995 node _T_996 = eq(UInt<5>(0h17), idx_14) when _T_996 : node _T_997 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_23.io.enq.bits, _T_997 node _T_998 = eq(UInt<5>(0h18), idx_14) when _T_998 : node _T_999 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_24.io.enq.bits, _T_999 node _T_1000 = eq(UInt<5>(0h19), idx_14) when _T_1000 : node _T_1001 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_25.io.enq.bits, _T_1001 node _T_1002 = eq(UInt<5>(0h1a), idx_14) when _T_1002 : node _T_1003 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_26.io.enq.bits, _T_1003 node _T_1004 = eq(UInt<5>(0h1b), idx_14) when _T_1004 : node _T_1005 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_27.io.enq.bits, _T_1005 node _T_1006 = eq(UInt<5>(0h1c), idx_14) when _T_1006 : node _T_1007 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_28.io.enq.bits, _T_1007 node _T_1008 = eq(UInt<5>(0h1d), idx_14) when _T_1008 : node _T_1009 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_29.io.enq.bits, _T_1009 node _T_1010 = eq(UInt<5>(0h1e), idx_14) when _T_1010 : node _T_1011 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_30.io.enq.bits, _T_1011 node _T_1012 = eq(UInt<5>(0h1f), idx_14) when _T_1012 : node _T_1013 = shr(memresp_bits_shifted, 112) connect Queue64_UInt8_31.io.enq.bits, _T_1013 node _idx_T_15 = add(write_start_index, UInt<4>(0hf)) node idx_15 = rem(_idx_T_15, UInt<6>(0h20)) node _T_1014 = eq(UInt<1>(0h0), idx_15) when _T_1014 : node _T_1015 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8.io.enq.bits, _T_1015 node _T_1016 = eq(UInt<1>(0h1), idx_15) when _T_1016 : node _T_1017 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_1.io.enq.bits, _T_1017 node _T_1018 = eq(UInt<2>(0h2), idx_15) when _T_1018 : node _T_1019 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_2.io.enq.bits, _T_1019 node _T_1020 = eq(UInt<2>(0h3), idx_15) when _T_1020 : node _T_1021 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_3.io.enq.bits, _T_1021 node _T_1022 = eq(UInt<3>(0h4), idx_15) when _T_1022 : node _T_1023 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_4.io.enq.bits, _T_1023 node _T_1024 = eq(UInt<3>(0h5), idx_15) when _T_1024 : node _T_1025 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_5.io.enq.bits, _T_1025 node _T_1026 = eq(UInt<3>(0h6), idx_15) when _T_1026 : node _T_1027 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_6.io.enq.bits, _T_1027 node _T_1028 = eq(UInt<3>(0h7), idx_15) when _T_1028 : node _T_1029 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_7.io.enq.bits, _T_1029 node _T_1030 = eq(UInt<4>(0h8), idx_15) when _T_1030 : node _T_1031 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_8.io.enq.bits, _T_1031 node _T_1032 = eq(UInt<4>(0h9), idx_15) when _T_1032 : node _T_1033 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_9.io.enq.bits, _T_1033 node _T_1034 = eq(UInt<4>(0ha), idx_15) when _T_1034 : node _T_1035 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_10.io.enq.bits, _T_1035 node _T_1036 = eq(UInt<4>(0hb), idx_15) when _T_1036 : node _T_1037 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_11.io.enq.bits, _T_1037 node _T_1038 = eq(UInt<4>(0hc), idx_15) when _T_1038 : node _T_1039 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_12.io.enq.bits, _T_1039 node _T_1040 = eq(UInt<4>(0hd), idx_15) when _T_1040 : node _T_1041 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_13.io.enq.bits, _T_1041 node _T_1042 = eq(UInt<4>(0he), idx_15) when _T_1042 : node _T_1043 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_14.io.enq.bits, _T_1043 node _T_1044 = eq(UInt<4>(0hf), idx_15) when _T_1044 : node _T_1045 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_15.io.enq.bits, _T_1045 node _T_1046 = eq(UInt<5>(0h10), idx_15) when _T_1046 : node _T_1047 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_16.io.enq.bits, _T_1047 node _T_1048 = eq(UInt<5>(0h11), idx_15) when _T_1048 : node _T_1049 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_17.io.enq.bits, _T_1049 node _T_1050 = eq(UInt<5>(0h12), idx_15) when _T_1050 : node _T_1051 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_18.io.enq.bits, _T_1051 node _T_1052 = eq(UInt<5>(0h13), idx_15) when _T_1052 : node _T_1053 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_19.io.enq.bits, _T_1053 node _T_1054 = eq(UInt<5>(0h14), idx_15) when _T_1054 : node _T_1055 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_20.io.enq.bits, _T_1055 node _T_1056 = eq(UInt<5>(0h15), idx_15) when _T_1056 : node _T_1057 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_21.io.enq.bits, _T_1057 node _T_1058 = eq(UInt<5>(0h16), idx_15) when _T_1058 : node _T_1059 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_22.io.enq.bits, _T_1059 node _T_1060 = eq(UInt<5>(0h17), idx_15) when _T_1060 : node _T_1061 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_23.io.enq.bits, _T_1061 node _T_1062 = eq(UInt<5>(0h18), idx_15) when _T_1062 : node _T_1063 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_24.io.enq.bits, _T_1063 node _T_1064 = eq(UInt<5>(0h19), idx_15) when _T_1064 : node _T_1065 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_25.io.enq.bits, _T_1065 node _T_1066 = eq(UInt<5>(0h1a), idx_15) when _T_1066 : node _T_1067 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_26.io.enq.bits, _T_1067 node _T_1068 = eq(UInt<5>(0h1b), idx_15) when _T_1068 : node _T_1069 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_27.io.enq.bits, _T_1069 node _T_1070 = eq(UInt<5>(0h1c), idx_15) when _T_1070 : node _T_1071 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_28.io.enq.bits, _T_1071 node _T_1072 = eq(UInt<5>(0h1d), idx_15) when _T_1072 : node _T_1073 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_29.io.enq.bits, _T_1073 node _T_1074 = eq(UInt<5>(0h1e), idx_15) when _T_1074 : node _T_1075 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_30.io.enq.bits, _T_1075 node _T_1076 = eq(UInt<5>(0h1f), idx_15) when _T_1076 : node _T_1077 = shr(memresp_bits_shifted, 120) connect Queue64_UInt8_31.io.enq.bits, _T_1077 node _idx_T_16 = add(write_start_index, UInt<5>(0h10)) node idx_16 = rem(_idx_T_16, UInt<6>(0h20)) node _T_1078 = eq(UInt<1>(0h0), idx_16) when _T_1078 : node _T_1079 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8.io.enq.bits, _T_1079 node _T_1080 = eq(UInt<1>(0h1), idx_16) when _T_1080 : node _T_1081 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_1.io.enq.bits, _T_1081 node _T_1082 = eq(UInt<2>(0h2), idx_16) when _T_1082 : node _T_1083 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_2.io.enq.bits, _T_1083 node _T_1084 = eq(UInt<2>(0h3), idx_16) when _T_1084 : node _T_1085 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_3.io.enq.bits, _T_1085 node _T_1086 = eq(UInt<3>(0h4), idx_16) when _T_1086 : node _T_1087 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_4.io.enq.bits, _T_1087 node _T_1088 = eq(UInt<3>(0h5), idx_16) when _T_1088 : node _T_1089 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_5.io.enq.bits, _T_1089 node _T_1090 = eq(UInt<3>(0h6), idx_16) when _T_1090 : node _T_1091 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_6.io.enq.bits, _T_1091 node _T_1092 = eq(UInt<3>(0h7), idx_16) when _T_1092 : node _T_1093 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_7.io.enq.bits, _T_1093 node _T_1094 = eq(UInt<4>(0h8), idx_16) when _T_1094 : node _T_1095 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_8.io.enq.bits, _T_1095 node _T_1096 = eq(UInt<4>(0h9), idx_16) when _T_1096 : node _T_1097 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_9.io.enq.bits, _T_1097 node _T_1098 = eq(UInt<4>(0ha), idx_16) when _T_1098 : node _T_1099 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_10.io.enq.bits, _T_1099 node _T_1100 = eq(UInt<4>(0hb), idx_16) when _T_1100 : node _T_1101 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_11.io.enq.bits, _T_1101 node _T_1102 = eq(UInt<4>(0hc), idx_16) when _T_1102 : node _T_1103 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_12.io.enq.bits, _T_1103 node _T_1104 = eq(UInt<4>(0hd), idx_16) when _T_1104 : node _T_1105 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_13.io.enq.bits, _T_1105 node _T_1106 = eq(UInt<4>(0he), idx_16) when _T_1106 : node _T_1107 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_14.io.enq.bits, _T_1107 node _T_1108 = eq(UInt<4>(0hf), idx_16) when _T_1108 : node _T_1109 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_15.io.enq.bits, _T_1109 node _T_1110 = eq(UInt<5>(0h10), idx_16) when _T_1110 : node _T_1111 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_16.io.enq.bits, _T_1111 node _T_1112 = eq(UInt<5>(0h11), idx_16) when _T_1112 : node _T_1113 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_17.io.enq.bits, _T_1113 node _T_1114 = eq(UInt<5>(0h12), idx_16) when _T_1114 : node _T_1115 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_18.io.enq.bits, _T_1115 node _T_1116 = eq(UInt<5>(0h13), idx_16) when _T_1116 : node _T_1117 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_19.io.enq.bits, _T_1117 node _T_1118 = eq(UInt<5>(0h14), idx_16) when _T_1118 : node _T_1119 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_20.io.enq.bits, _T_1119 node _T_1120 = eq(UInt<5>(0h15), idx_16) when _T_1120 : node _T_1121 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_21.io.enq.bits, _T_1121 node _T_1122 = eq(UInt<5>(0h16), idx_16) when _T_1122 : node _T_1123 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_22.io.enq.bits, _T_1123 node _T_1124 = eq(UInt<5>(0h17), idx_16) when _T_1124 : node _T_1125 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_23.io.enq.bits, _T_1125 node _T_1126 = eq(UInt<5>(0h18), idx_16) when _T_1126 : node _T_1127 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_24.io.enq.bits, _T_1127 node _T_1128 = eq(UInt<5>(0h19), idx_16) when _T_1128 : node _T_1129 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_25.io.enq.bits, _T_1129 node _T_1130 = eq(UInt<5>(0h1a), idx_16) when _T_1130 : node _T_1131 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_26.io.enq.bits, _T_1131 node _T_1132 = eq(UInt<5>(0h1b), idx_16) when _T_1132 : node _T_1133 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_27.io.enq.bits, _T_1133 node _T_1134 = eq(UInt<5>(0h1c), idx_16) when _T_1134 : node _T_1135 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_28.io.enq.bits, _T_1135 node _T_1136 = eq(UInt<5>(0h1d), idx_16) when _T_1136 : node _T_1137 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_29.io.enq.bits, _T_1137 node _T_1138 = eq(UInt<5>(0h1e), idx_16) when _T_1138 : node _T_1139 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_30.io.enq.bits, _T_1139 node _T_1140 = eq(UInt<5>(0h1f), idx_16) when _T_1140 : node _T_1141 = shr(memresp_bits_shifted, 128) connect Queue64_UInt8_31.io.enq.bits, _T_1141 node _idx_T_17 = add(write_start_index, UInt<5>(0h11)) node idx_17 = rem(_idx_T_17, UInt<6>(0h20)) node _T_1142 = eq(UInt<1>(0h0), idx_17) when _T_1142 : node _T_1143 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8.io.enq.bits, _T_1143 node _T_1144 = eq(UInt<1>(0h1), idx_17) when _T_1144 : node _T_1145 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_1.io.enq.bits, _T_1145 node _T_1146 = eq(UInt<2>(0h2), idx_17) when _T_1146 : node _T_1147 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_2.io.enq.bits, _T_1147 node _T_1148 = eq(UInt<2>(0h3), idx_17) when _T_1148 : node _T_1149 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_3.io.enq.bits, _T_1149 node _T_1150 = eq(UInt<3>(0h4), idx_17) when _T_1150 : node _T_1151 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_4.io.enq.bits, _T_1151 node _T_1152 = eq(UInt<3>(0h5), idx_17) when _T_1152 : node _T_1153 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_5.io.enq.bits, _T_1153 node _T_1154 = eq(UInt<3>(0h6), idx_17) when _T_1154 : node _T_1155 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_6.io.enq.bits, _T_1155 node _T_1156 = eq(UInt<3>(0h7), idx_17) when _T_1156 : node _T_1157 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_7.io.enq.bits, _T_1157 node _T_1158 = eq(UInt<4>(0h8), idx_17) when _T_1158 : node _T_1159 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_8.io.enq.bits, _T_1159 node _T_1160 = eq(UInt<4>(0h9), idx_17) when _T_1160 : node _T_1161 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_9.io.enq.bits, _T_1161 node _T_1162 = eq(UInt<4>(0ha), idx_17) when _T_1162 : node _T_1163 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_10.io.enq.bits, _T_1163 node _T_1164 = eq(UInt<4>(0hb), idx_17) when _T_1164 : node _T_1165 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_11.io.enq.bits, _T_1165 node _T_1166 = eq(UInt<4>(0hc), idx_17) when _T_1166 : node _T_1167 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_12.io.enq.bits, _T_1167 node _T_1168 = eq(UInt<4>(0hd), idx_17) when _T_1168 : node _T_1169 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_13.io.enq.bits, _T_1169 node _T_1170 = eq(UInt<4>(0he), idx_17) when _T_1170 : node _T_1171 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_14.io.enq.bits, _T_1171 node _T_1172 = eq(UInt<4>(0hf), idx_17) when _T_1172 : node _T_1173 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_15.io.enq.bits, _T_1173 node _T_1174 = eq(UInt<5>(0h10), idx_17) when _T_1174 : node _T_1175 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_16.io.enq.bits, _T_1175 node _T_1176 = eq(UInt<5>(0h11), idx_17) when _T_1176 : node _T_1177 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_17.io.enq.bits, _T_1177 node _T_1178 = eq(UInt<5>(0h12), idx_17) when _T_1178 : node _T_1179 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_18.io.enq.bits, _T_1179 node _T_1180 = eq(UInt<5>(0h13), idx_17) when _T_1180 : node _T_1181 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_19.io.enq.bits, _T_1181 node _T_1182 = eq(UInt<5>(0h14), idx_17) when _T_1182 : node _T_1183 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_20.io.enq.bits, _T_1183 node _T_1184 = eq(UInt<5>(0h15), idx_17) when _T_1184 : node _T_1185 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_21.io.enq.bits, _T_1185 node _T_1186 = eq(UInt<5>(0h16), idx_17) when _T_1186 : node _T_1187 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_22.io.enq.bits, _T_1187 node _T_1188 = eq(UInt<5>(0h17), idx_17) when _T_1188 : node _T_1189 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_23.io.enq.bits, _T_1189 node _T_1190 = eq(UInt<5>(0h18), idx_17) when _T_1190 : node _T_1191 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_24.io.enq.bits, _T_1191 node _T_1192 = eq(UInt<5>(0h19), idx_17) when _T_1192 : node _T_1193 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_25.io.enq.bits, _T_1193 node _T_1194 = eq(UInt<5>(0h1a), idx_17) when _T_1194 : node _T_1195 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_26.io.enq.bits, _T_1195 node _T_1196 = eq(UInt<5>(0h1b), idx_17) when _T_1196 : node _T_1197 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_27.io.enq.bits, _T_1197 node _T_1198 = eq(UInt<5>(0h1c), idx_17) when _T_1198 : node _T_1199 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_28.io.enq.bits, _T_1199 node _T_1200 = eq(UInt<5>(0h1d), idx_17) when _T_1200 : node _T_1201 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_29.io.enq.bits, _T_1201 node _T_1202 = eq(UInt<5>(0h1e), idx_17) when _T_1202 : node _T_1203 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_30.io.enq.bits, _T_1203 node _T_1204 = eq(UInt<5>(0h1f), idx_17) when _T_1204 : node _T_1205 = shr(memresp_bits_shifted, 136) connect Queue64_UInt8_31.io.enq.bits, _T_1205 node _idx_T_18 = add(write_start_index, UInt<5>(0h12)) node idx_18 = rem(_idx_T_18, UInt<6>(0h20)) node _T_1206 = eq(UInt<1>(0h0), idx_18) when _T_1206 : node _T_1207 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8.io.enq.bits, _T_1207 node _T_1208 = eq(UInt<1>(0h1), idx_18) when _T_1208 : node _T_1209 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_1.io.enq.bits, _T_1209 node _T_1210 = eq(UInt<2>(0h2), idx_18) when _T_1210 : node _T_1211 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_2.io.enq.bits, _T_1211 node _T_1212 = eq(UInt<2>(0h3), idx_18) when _T_1212 : node _T_1213 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_3.io.enq.bits, _T_1213 node _T_1214 = eq(UInt<3>(0h4), idx_18) when _T_1214 : node _T_1215 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_4.io.enq.bits, _T_1215 node _T_1216 = eq(UInt<3>(0h5), idx_18) when _T_1216 : node _T_1217 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_5.io.enq.bits, _T_1217 node _T_1218 = eq(UInt<3>(0h6), idx_18) when _T_1218 : node _T_1219 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_6.io.enq.bits, _T_1219 node _T_1220 = eq(UInt<3>(0h7), idx_18) when _T_1220 : node _T_1221 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_7.io.enq.bits, _T_1221 node _T_1222 = eq(UInt<4>(0h8), idx_18) when _T_1222 : node _T_1223 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_8.io.enq.bits, _T_1223 node _T_1224 = eq(UInt<4>(0h9), idx_18) when _T_1224 : node _T_1225 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_9.io.enq.bits, _T_1225 node _T_1226 = eq(UInt<4>(0ha), idx_18) when _T_1226 : node _T_1227 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_10.io.enq.bits, _T_1227 node _T_1228 = eq(UInt<4>(0hb), idx_18) when _T_1228 : node _T_1229 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_11.io.enq.bits, _T_1229 node _T_1230 = eq(UInt<4>(0hc), idx_18) when _T_1230 : node _T_1231 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_12.io.enq.bits, _T_1231 node _T_1232 = eq(UInt<4>(0hd), idx_18) when _T_1232 : node _T_1233 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_13.io.enq.bits, _T_1233 node _T_1234 = eq(UInt<4>(0he), idx_18) when _T_1234 : node _T_1235 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_14.io.enq.bits, _T_1235 node _T_1236 = eq(UInt<4>(0hf), idx_18) when _T_1236 : node _T_1237 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_15.io.enq.bits, _T_1237 node _T_1238 = eq(UInt<5>(0h10), idx_18) when _T_1238 : node _T_1239 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_16.io.enq.bits, _T_1239 node _T_1240 = eq(UInt<5>(0h11), idx_18) when _T_1240 : node _T_1241 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_17.io.enq.bits, _T_1241 node _T_1242 = eq(UInt<5>(0h12), idx_18) when _T_1242 : node _T_1243 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_18.io.enq.bits, _T_1243 node _T_1244 = eq(UInt<5>(0h13), idx_18) when _T_1244 : node _T_1245 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_19.io.enq.bits, _T_1245 node _T_1246 = eq(UInt<5>(0h14), idx_18) when _T_1246 : node _T_1247 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_20.io.enq.bits, _T_1247 node _T_1248 = eq(UInt<5>(0h15), idx_18) when _T_1248 : node _T_1249 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_21.io.enq.bits, _T_1249 node _T_1250 = eq(UInt<5>(0h16), idx_18) when _T_1250 : node _T_1251 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_22.io.enq.bits, _T_1251 node _T_1252 = eq(UInt<5>(0h17), idx_18) when _T_1252 : node _T_1253 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_23.io.enq.bits, _T_1253 node _T_1254 = eq(UInt<5>(0h18), idx_18) when _T_1254 : node _T_1255 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_24.io.enq.bits, _T_1255 node _T_1256 = eq(UInt<5>(0h19), idx_18) when _T_1256 : node _T_1257 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_25.io.enq.bits, _T_1257 node _T_1258 = eq(UInt<5>(0h1a), idx_18) when _T_1258 : node _T_1259 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_26.io.enq.bits, _T_1259 node _T_1260 = eq(UInt<5>(0h1b), idx_18) when _T_1260 : node _T_1261 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_27.io.enq.bits, _T_1261 node _T_1262 = eq(UInt<5>(0h1c), idx_18) when _T_1262 : node _T_1263 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_28.io.enq.bits, _T_1263 node _T_1264 = eq(UInt<5>(0h1d), idx_18) when _T_1264 : node _T_1265 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_29.io.enq.bits, _T_1265 node _T_1266 = eq(UInt<5>(0h1e), idx_18) when _T_1266 : node _T_1267 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_30.io.enq.bits, _T_1267 node _T_1268 = eq(UInt<5>(0h1f), idx_18) when _T_1268 : node _T_1269 = shr(memresp_bits_shifted, 144) connect Queue64_UInt8_31.io.enq.bits, _T_1269 node _idx_T_19 = add(write_start_index, UInt<5>(0h13)) node idx_19 = rem(_idx_T_19, UInt<6>(0h20)) node _T_1270 = eq(UInt<1>(0h0), idx_19) when _T_1270 : node _T_1271 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8.io.enq.bits, _T_1271 node _T_1272 = eq(UInt<1>(0h1), idx_19) when _T_1272 : node _T_1273 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_1.io.enq.bits, _T_1273 node _T_1274 = eq(UInt<2>(0h2), idx_19) when _T_1274 : node _T_1275 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_2.io.enq.bits, _T_1275 node _T_1276 = eq(UInt<2>(0h3), idx_19) when _T_1276 : node _T_1277 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_3.io.enq.bits, _T_1277 node _T_1278 = eq(UInt<3>(0h4), idx_19) when _T_1278 : node _T_1279 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_4.io.enq.bits, _T_1279 node _T_1280 = eq(UInt<3>(0h5), idx_19) when _T_1280 : node _T_1281 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_5.io.enq.bits, _T_1281 node _T_1282 = eq(UInt<3>(0h6), idx_19) when _T_1282 : node _T_1283 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_6.io.enq.bits, _T_1283 node _T_1284 = eq(UInt<3>(0h7), idx_19) when _T_1284 : node _T_1285 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_7.io.enq.bits, _T_1285 node _T_1286 = eq(UInt<4>(0h8), idx_19) when _T_1286 : node _T_1287 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_8.io.enq.bits, _T_1287 node _T_1288 = eq(UInt<4>(0h9), idx_19) when _T_1288 : node _T_1289 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_9.io.enq.bits, _T_1289 node _T_1290 = eq(UInt<4>(0ha), idx_19) when _T_1290 : node _T_1291 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_10.io.enq.bits, _T_1291 node _T_1292 = eq(UInt<4>(0hb), idx_19) when _T_1292 : node _T_1293 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_11.io.enq.bits, _T_1293 node _T_1294 = eq(UInt<4>(0hc), idx_19) when _T_1294 : node _T_1295 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_12.io.enq.bits, _T_1295 node _T_1296 = eq(UInt<4>(0hd), idx_19) when _T_1296 : node _T_1297 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_13.io.enq.bits, _T_1297 node _T_1298 = eq(UInt<4>(0he), idx_19) when _T_1298 : node _T_1299 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_14.io.enq.bits, _T_1299 node _T_1300 = eq(UInt<4>(0hf), idx_19) when _T_1300 : node _T_1301 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_15.io.enq.bits, _T_1301 node _T_1302 = eq(UInt<5>(0h10), idx_19) when _T_1302 : node _T_1303 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_16.io.enq.bits, _T_1303 node _T_1304 = eq(UInt<5>(0h11), idx_19) when _T_1304 : node _T_1305 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_17.io.enq.bits, _T_1305 node _T_1306 = eq(UInt<5>(0h12), idx_19) when _T_1306 : node _T_1307 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_18.io.enq.bits, _T_1307 node _T_1308 = eq(UInt<5>(0h13), idx_19) when _T_1308 : node _T_1309 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_19.io.enq.bits, _T_1309 node _T_1310 = eq(UInt<5>(0h14), idx_19) when _T_1310 : node _T_1311 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_20.io.enq.bits, _T_1311 node _T_1312 = eq(UInt<5>(0h15), idx_19) when _T_1312 : node _T_1313 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_21.io.enq.bits, _T_1313 node _T_1314 = eq(UInt<5>(0h16), idx_19) when _T_1314 : node _T_1315 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_22.io.enq.bits, _T_1315 node _T_1316 = eq(UInt<5>(0h17), idx_19) when _T_1316 : node _T_1317 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_23.io.enq.bits, _T_1317 node _T_1318 = eq(UInt<5>(0h18), idx_19) when _T_1318 : node _T_1319 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_24.io.enq.bits, _T_1319 node _T_1320 = eq(UInt<5>(0h19), idx_19) when _T_1320 : node _T_1321 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_25.io.enq.bits, _T_1321 node _T_1322 = eq(UInt<5>(0h1a), idx_19) when _T_1322 : node _T_1323 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_26.io.enq.bits, _T_1323 node _T_1324 = eq(UInt<5>(0h1b), idx_19) when _T_1324 : node _T_1325 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_27.io.enq.bits, _T_1325 node _T_1326 = eq(UInt<5>(0h1c), idx_19) when _T_1326 : node _T_1327 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_28.io.enq.bits, _T_1327 node _T_1328 = eq(UInt<5>(0h1d), idx_19) when _T_1328 : node _T_1329 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_29.io.enq.bits, _T_1329 node _T_1330 = eq(UInt<5>(0h1e), idx_19) when _T_1330 : node _T_1331 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_30.io.enq.bits, _T_1331 node _T_1332 = eq(UInt<5>(0h1f), idx_19) when _T_1332 : node _T_1333 = shr(memresp_bits_shifted, 152) connect Queue64_UInt8_31.io.enq.bits, _T_1333 node _idx_T_20 = add(write_start_index, UInt<5>(0h14)) node idx_20 = rem(_idx_T_20, UInt<6>(0h20)) node _T_1334 = eq(UInt<1>(0h0), idx_20) when _T_1334 : node _T_1335 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8.io.enq.bits, _T_1335 node _T_1336 = eq(UInt<1>(0h1), idx_20) when _T_1336 : node _T_1337 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_1.io.enq.bits, _T_1337 node _T_1338 = eq(UInt<2>(0h2), idx_20) when _T_1338 : node _T_1339 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_2.io.enq.bits, _T_1339 node _T_1340 = eq(UInt<2>(0h3), idx_20) when _T_1340 : node _T_1341 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_3.io.enq.bits, _T_1341 node _T_1342 = eq(UInt<3>(0h4), idx_20) when _T_1342 : node _T_1343 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_4.io.enq.bits, _T_1343 node _T_1344 = eq(UInt<3>(0h5), idx_20) when _T_1344 : node _T_1345 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_5.io.enq.bits, _T_1345 node _T_1346 = eq(UInt<3>(0h6), idx_20) when _T_1346 : node _T_1347 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_6.io.enq.bits, _T_1347 node _T_1348 = eq(UInt<3>(0h7), idx_20) when _T_1348 : node _T_1349 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_7.io.enq.bits, _T_1349 node _T_1350 = eq(UInt<4>(0h8), idx_20) when _T_1350 : node _T_1351 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_8.io.enq.bits, _T_1351 node _T_1352 = eq(UInt<4>(0h9), idx_20) when _T_1352 : node _T_1353 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_9.io.enq.bits, _T_1353 node _T_1354 = eq(UInt<4>(0ha), idx_20) when _T_1354 : node _T_1355 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_10.io.enq.bits, _T_1355 node _T_1356 = eq(UInt<4>(0hb), idx_20) when _T_1356 : node _T_1357 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_11.io.enq.bits, _T_1357 node _T_1358 = eq(UInt<4>(0hc), idx_20) when _T_1358 : node _T_1359 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_12.io.enq.bits, _T_1359 node _T_1360 = eq(UInt<4>(0hd), idx_20) when _T_1360 : node _T_1361 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_13.io.enq.bits, _T_1361 node _T_1362 = eq(UInt<4>(0he), idx_20) when _T_1362 : node _T_1363 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_14.io.enq.bits, _T_1363 node _T_1364 = eq(UInt<4>(0hf), idx_20) when _T_1364 : node _T_1365 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_15.io.enq.bits, _T_1365 node _T_1366 = eq(UInt<5>(0h10), idx_20) when _T_1366 : node _T_1367 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_16.io.enq.bits, _T_1367 node _T_1368 = eq(UInt<5>(0h11), idx_20) when _T_1368 : node _T_1369 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_17.io.enq.bits, _T_1369 node _T_1370 = eq(UInt<5>(0h12), idx_20) when _T_1370 : node _T_1371 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_18.io.enq.bits, _T_1371 node _T_1372 = eq(UInt<5>(0h13), idx_20) when _T_1372 : node _T_1373 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_19.io.enq.bits, _T_1373 node _T_1374 = eq(UInt<5>(0h14), idx_20) when _T_1374 : node _T_1375 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_20.io.enq.bits, _T_1375 node _T_1376 = eq(UInt<5>(0h15), idx_20) when _T_1376 : node _T_1377 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_21.io.enq.bits, _T_1377 node _T_1378 = eq(UInt<5>(0h16), idx_20) when _T_1378 : node _T_1379 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_22.io.enq.bits, _T_1379 node _T_1380 = eq(UInt<5>(0h17), idx_20) when _T_1380 : node _T_1381 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_23.io.enq.bits, _T_1381 node _T_1382 = eq(UInt<5>(0h18), idx_20) when _T_1382 : node _T_1383 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_24.io.enq.bits, _T_1383 node _T_1384 = eq(UInt<5>(0h19), idx_20) when _T_1384 : node _T_1385 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_25.io.enq.bits, _T_1385 node _T_1386 = eq(UInt<5>(0h1a), idx_20) when _T_1386 : node _T_1387 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_26.io.enq.bits, _T_1387 node _T_1388 = eq(UInt<5>(0h1b), idx_20) when _T_1388 : node _T_1389 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_27.io.enq.bits, _T_1389 node _T_1390 = eq(UInt<5>(0h1c), idx_20) when _T_1390 : node _T_1391 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_28.io.enq.bits, _T_1391 node _T_1392 = eq(UInt<5>(0h1d), idx_20) when _T_1392 : node _T_1393 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_29.io.enq.bits, _T_1393 node _T_1394 = eq(UInt<5>(0h1e), idx_20) when _T_1394 : node _T_1395 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_30.io.enq.bits, _T_1395 node _T_1396 = eq(UInt<5>(0h1f), idx_20) when _T_1396 : node _T_1397 = shr(memresp_bits_shifted, 160) connect Queue64_UInt8_31.io.enq.bits, _T_1397 node _idx_T_21 = add(write_start_index, UInt<5>(0h15)) node idx_21 = rem(_idx_T_21, UInt<6>(0h20)) node _T_1398 = eq(UInt<1>(0h0), idx_21) when _T_1398 : node _T_1399 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8.io.enq.bits, _T_1399 node _T_1400 = eq(UInt<1>(0h1), idx_21) when _T_1400 : node _T_1401 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_1.io.enq.bits, _T_1401 node _T_1402 = eq(UInt<2>(0h2), idx_21) when _T_1402 : node _T_1403 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_2.io.enq.bits, _T_1403 node _T_1404 = eq(UInt<2>(0h3), idx_21) when _T_1404 : node _T_1405 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_3.io.enq.bits, _T_1405 node _T_1406 = eq(UInt<3>(0h4), idx_21) when _T_1406 : node _T_1407 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_4.io.enq.bits, _T_1407 node _T_1408 = eq(UInt<3>(0h5), idx_21) when _T_1408 : node _T_1409 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_5.io.enq.bits, _T_1409 node _T_1410 = eq(UInt<3>(0h6), idx_21) when _T_1410 : node _T_1411 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_6.io.enq.bits, _T_1411 node _T_1412 = eq(UInt<3>(0h7), idx_21) when _T_1412 : node _T_1413 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_7.io.enq.bits, _T_1413 node _T_1414 = eq(UInt<4>(0h8), idx_21) when _T_1414 : node _T_1415 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_8.io.enq.bits, _T_1415 node _T_1416 = eq(UInt<4>(0h9), idx_21) when _T_1416 : node _T_1417 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_9.io.enq.bits, _T_1417 node _T_1418 = eq(UInt<4>(0ha), idx_21) when _T_1418 : node _T_1419 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_10.io.enq.bits, _T_1419 node _T_1420 = eq(UInt<4>(0hb), idx_21) when _T_1420 : node _T_1421 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_11.io.enq.bits, _T_1421 node _T_1422 = eq(UInt<4>(0hc), idx_21) when _T_1422 : node _T_1423 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_12.io.enq.bits, _T_1423 node _T_1424 = eq(UInt<4>(0hd), idx_21) when _T_1424 : node _T_1425 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_13.io.enq.bits, _T_1425 node _T_1426 = eq(UInt<4>(0he), idx_21) when _T_1426 : node _T_1427 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_14.io.enq.bits, _T_1427 node _T_1428 = eq(UInt<4>(0hf), idx_21) when _T_1428 : node _T_1429 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_15.io.enq.bits, _T_1429 node _T_1430 = eq(UInt<5>(0h10), idx_21) when _T_1430 : node _T_1431 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_16.io.enq.bits, _T_1431 node _T_1432 = eq(UInt<5>(0h11), idx_21) when _T_1432 : node _T_1433 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_17.io.enq.bits, _T_1433 node _T_1434 = eq(UInt<5>(0h12), idx_21) when _T_1434 : node _T_1435 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_18.io.enq.bits, _T_1435 node _T_1436 = eq(UInt<5>(0h13), idx_21) when _T_1436 : node _T_1437 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_19.io.enq.bits, _T_1437 node _T_1438 = eq(UInt<5>(0h14), idx_21) when _T_1438 : node _T_1439 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_20.io.enq.bits, _T_1439 node _T_1440 = eq(UInt<5>(0h15), idx_21) when _T_1440 : node _T_1441 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_21.io.enq.bits, _T_1441 node _T_1442 = eq(UInt<5>(0h16), idx_21) when _T_1442 : node _T_1443 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_22.io.enq.bits, _T_1443 node _T_1444 = eq(UInt<5>(0h17), idx_21) when _T_1444 : node _T_1445 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_23.io.enq.bits, _T_1445 node _T_1446 = eq(UInt<5>(0h18), idx_21) when _T_1446 : node _T_1447 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_24.io.enq.bits, _T_1447 node _T_1448 = eq(UInt<5>(0h19), idx_21) when _T_1448 : node _T_1449 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_25.io.enq.bits, _T_1449 node _T_1450 = eq(UInt<5>(0h1a), idx_21) when _T_1450 : node _T_1451 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_26.io.enq.bits, _T_1451 node _T_1452 = eq(UInt<5>(0h1b), idx_21) when _T_1452 : node _T_1453 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_27.io.enq.bits, _T_1453 node _T_1454 = eq(UInt<5>(0h1c), idx_21) when _T_1454 : node _T_1455 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_28.io.enq.bits, _T_1455 node _T_1456 = eq(UInt<5>(0h1d), idx_21) when _T_1456 : node _T_1457 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_29.io.enq.bits, _T_1457 node _T_1458 = eq(UInt<5>(0h1e), idx_21) when _T_1458 : node _T_1459 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_30.io.enq.bits, _T_1459 node _T_1460 = eq(UInt<5>(0h1f), idx_21) when _T_1460 : node _T_1461 = shr(memresp_bits_shifted, 168) connect Queue64_UInt8_31.io.enq.bits, _T_1461 node _idx_T_22 = add(write_start_index, UInt<5>(0h16)) node idx_22 = rem(_idx_T_22, UInt<6>(0h20)) node _T_1462 = eq(UInt<1>(0h0), idx_22) when _T_1462 : node _T_1463 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8.io.enq.bits, _T_1463 node _T_1464 = eq(UInt<1>(0h1), idx_22) when _T_1464 : node _T_1465 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_1.io.enq.bits, _T_1465 node _T_1466 = eq(UInt<2>(0h2), idx_22) when _T_1466 : node _T_1467 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_2.io.enq.bits, _T_1467 node _T_1468 = eq(UInt<2>(0h3), idx_22) when _T_1468 : node _T_1469 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_3.io.enq.bits, _T_1469 node _T_1470 = eq(UInt<3>(0h4), idx_22) when _T_1470 : node _T_1471 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_4.io.enq.bits, _T_1471 node _T_1472 = eq(UInt<3>(0h5), idx_22) when _T_1472 : node _T_1473 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_5.io.enq.bits, _T_1473 node _T_1474 = eq(UInt<3>(0h6), idx_22) when _T_1474 : node _T_1475 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_6.io.enq.bits, _T_1475 node _T_1476 = eq(UInt<3>(0h7), idx_22) when _T_1476 : node _T_1477 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_7.io.enq.bits, _T_1477 node _T_1478 = eq(UInt<4>(0h8), idx_22) when _T_1478 : node _T_1479 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_8.io.enq.bits, _T_1479 node _T_1480 = eq(UInt<4>(0h9), idx_22) when _T_1480 : node _T_1481 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_9.io.enq.bits, _T_1481 node _T_1482 = eq(UInt<4>(0ha), idx_22) when _T_1482 : node _T_1483 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_10.io.enq.bits, _T_1483 node _T_1484 = eq(UInt<4>(0hb), idx_22) when _T_1484 : node _T_1485 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_11.io.enq.bits, _T_1485 node _T_1486 = eq(UInt<4>(0hc), idx_22) when _T_1486 : node _T_1487 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_12.io.enq.bits, _T_1487 node _T_1488 = eq(UInt<4>(0hd), idx_22) when _T_1488 : node _T_1489 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_13.io.enq.bits, _T_1489 node _T_1490 = eq(UInt<4>(0he), idx_22) when _T_1490 : node _T_1491 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_14.io.enq.bits, _T_1491 node _T_1492 = eq(UInt<4>(0hf), idx_22) when _T_1492 : node _T_1493 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_15.io.enq.bits, _T_1493 node _T_1494 = eq(UInt<5>(0h10), idx_22) when _T_1494 : node _T_1495 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_16.io.enq.bits, _T_1495 node _T_1496 = eq(UInt<5>(0h11), idx_22) when _T_1496 : node _T_1497 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_17.io.enq.bits, _T_1497 node _T_1498 = eq(UInt<5>(0h12), idx_22) when _T_1498 : node _T_1499 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_18.io.enq.bits, _T_1499 node _T_1500 = eq(UInt<5>(0h13), idx_22) when _T_1500 : node _T_1501 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_19.io.enq.bits, _T_1501 node _T_1502 = eq(UInt<5>(0h14), idx_22) when _T_1502 : node _T_1503 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_20.io.enq.bits, _T_1503 node _T_1504 = eq(UInt<5>(0h15), idx_22) when _T_1504 : node _T_1505 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_21.io.enq.bits, _T_1505 node _T_1506 = eq(UInt<5>(0h16), idx_22) when _T_1506 : node _T_1507 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_22.io.enq.bits, _T_1507 node _T_1508 = eq(UInt<5>(0h17), idx_22) when _T_1508 : node _T_1509 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_23.io.enq.bits, _T_1509 node _T_1510 = eq(UInt<5>(0h18), idx_22) when _T_1510 : node _T_1511 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_24.io.enq.bits, _T_1511 node _T_1512 = eq(UInt<5>(0h19), idx_22) when _T_1512 : node _T_1513 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_25.io.enq.bits, _T_1513 node _T_1514 = eq(UInt<5>(0h1a), idx_22) when _T_1514 : node _T_1515 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_26.io.enq.bits, _T_1515 node _T_1516 = eq(UInt<5>(0h1b), idx_22) when _T_1516 : node _T_1517 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_27.io.enq.bits, _T_1517 node _T_1518 = eq(UInt<5>(0h1c), idx_22) when _T_1518 : node _T_1519 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_28.io.enq.bits, _T_1519 node _T_1520 = eq(UInt<5>(0h1d), idx_22) when _T_1520 : node _T_1521 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_29.io.enq.bits, _T_1521 node _T_1522 = eq(UInt<5>(0h1e), idx_22) when _T_1522 : node _T_1523 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_30.io.enq.bits, _T_1523 node _T_1524 = eq(UInt<5>(0h1f), idx_22) when _T_1524 : node _T_1525 = shr(memresp_bits_shifted, 176) connect Queue64_UInt8_31.io.enq.bits, _T_1525 node _idx_T_23 = add(write_start_index, UInt<5>(0h17)) node idx_23 = rem(_idx_T_23, UInt<6>(0h20)) node _T_1526 = eq(UInt<1>(0h0), idx_23) when _T_1526 : node _T_1527 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8.io.enq.bits, _T_1527 node _T_1528 = eq(UInt<1>(0h1), idx_23) when _T_1528 : node _T_1529 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_1.io.enq.bits, _T_1529 node _T_1530 = eq(UInt<2>(0h2), idx_23) when _T_1530 : node _T_1531 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_2.io.enq.bits, _T_1531 node _T_1532 = eq(UInt<2>(0h3), idx_23) when _T_1532 : node _T_1533 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_3.io.enq.bits, _T_1533 node _T_1534 = eq(UInt<3>(0h4), idx_23) when _T_1534 : node _T_1535 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_4.io.enq.bits, _T_1535 node _T_1536 = eq(UInt<3>(0h5), idx_23) when _T_1536 : node _T_1537 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_5.io.enq.bits, _T_1537 node _T_1538 = eq(UInt<3>(0h6), idx_23) when _T_1538 : node _T_1539 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_6.io.enq.bits, _T_1539 node _T_1540 = eq(UInt<3>(0h7), idx_23) when _T_1540 : node _T_1541 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_7.io.enq.bits, _T_1541 node _T_1542 = eq(UInt<4>(0h8), idx_23) when _T_1542 : node _T_1543 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_8.io.enq.bits, _T_1543 node _T_1544 = eq(UInt<4>(0h9), idx_23) when _T_1544 : node _T_1545 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_9.io.enq.bits, _T_1545 node _T_1546 = eq(UInt<4>(0ha), idx_23) when _T_1546 : node _T_1547 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_10.io.enq.bits, _T_1547 node _T_1548 = eq(UInt<4>(0hb), idx_23) when _T_1548 : node _T_1549 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_11.io.enq.bits, _T_1549 node _T_1550 = eq(UInt<4>(0hc), idx_23) when _T_1550 : node _T_1551 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_12.io.enq.bits, _T_1551 node _T_1552 = eq(UInt<4>(0hd), idx_23) when _T_1552 : node _T_1553 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_13.io.enq.bits, _T_1553 node _T_1554 = eq(UInt<4>(0he), idx_23) when _T_1554 : node _T_1555 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_14.io.enq.bits, _T_1555 node _T_1556 = eq(UInt<4>(0hf), idx_23) when _T_1556 : node _T_1557 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_15.io.enq.bits, _T_1557 node _T_1558 = eq(UInt<5>(0h10), idx_23) when _T_1558 : node _T_1559 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_16.io.enq.bits, _T_1559 node _T_1560 = eq(UInt<5>(0h11), idx_23) when _T_1560 : node _T_1561 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_17.io.enq.bits, _T_1561 node _T_1562 = eq(UInt<5>(0h12), idx_23) when _T_1562 : node _T_1563 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_18.io.enq.bits, _T_1563 node _T_1564 = eq(UInt<5>(0h13), idx_23) when _T_1564 : node _T_1565 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_19.io.enq.bits, _T_1565 node _T_1566 = eq(UInt<5>(0h14), idx_23) when _T_1566 : node _T_1567 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_20.io.enq.bits, _T_1567 node _T_1568 = eq(UInt<5>(0h15), idx_23) when _T_1568 : node _T_1569 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_21.io.enq.bits, _T_1569 node _T_1570 = eq(UInt<5>(0h16), idx_23) when _T_1570 : node _T_1571 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_22.io.enq.bits, _T_1571 node _T_1572 = eq(UInt<5>(0h17), idx_23) when _T_1572 : node _T_1573 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_23.io.enq.bits, _T_1573 node _T_1574 = eq(UInt<5>(0h18), idx_23) when _T_1574 : node _T_1575 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_24.io.enq.bits, _T_1575 node _T_1576 = eq(UInt<5>(0h19), idx_23) when _T_1576 : node _T_1577 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_25.io.enq.bits, _T_1577 node _T_1578 = eq(UInt<5>(0h1a), idx_23) when _T_1578 : node _T_1579 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_26.io.enq.bits, _T_1579 node _T_1580 = eq(UInt<5>(0h1b), idx_23) when _T_1580 : node _T_1581 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_27.io.enq.bits, _T_1581 node _T_1582 = eq(UInt<5>(0h1c), idx_23) when _T_1582 : node _T_1583 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_28.io.enq.bits, _T_1583 node _T_1584 = eq(UInt<5>(0h1d), idx_23) when _T_1584 : node _T_1585 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_29.io.enq.bits, _T_1585 node _T_1586 = eq(UInt<5>(0h1e), idx_23) when _T_1586 : node _T_1587 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_30.io.enq.bits, _T_1587 node _T_1588 = eq(UInt<5>(0h1f), idx_23) when _T_1588 : node _T_1589 = shr(memresp_bits_shifted, 184) connect Queue64_UInt8_31.io.enq.bits, _T_1589 node _idx_T_24 = add(write_start_index, UInt<5>(0h18)) node idx_24 = rem(_idx_T_24, UInt<6>(0h20)) node _T_1590 = eq(UInt<1>(0h0), idx_24) when _T_1590 : node _T_1591 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8.io.enq.bits, _T_1591 node _T_1592 = eq(UInt<1>(0h1), idx_24) when _T_1592 : node _T_1593 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_1.io.enq.bits, _T_1593 node _T_1594 = eq(UInt<2>(0h2), idx_24) when _T_1594 : node _T_1595 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_2.io.enq.bits, _T_1595 node _T_1596 = eq(UInt<2>(0h3), idx_24) when _T_1596 : node _T_1597 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_3.io.enq.bits, _T_1597 node _T_1598 = eq(UInt<3>(0h4), idx_24) when _T_1598 : node _T_1599 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_4.io.enq.bits, _T_1599 node _T_1600 = eq(UInt<3>(0h5), idx_24) when _T_1600 : node _T_1601 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_5.io.enq.bits, _T_1601 node _T_1602 = eq(UInt<3>(0h6), idx_24) when _T_1602 : node _T_1603 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_6.io.enq.bits, _T_1603 node _T_1604 = eq(UInt<3>(0h7), idx_24) when _T_1604 : node _T_1605 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_7.io.enq.bits, _T_1605 node _T_1606 = eq(UInt<4>(0h8), idx_24) when _T_1606 : node _T_1607 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_8.io.enq.bits, _T_1607 node _T_1608 = eq(UInt<4>(0h9), idx_24) when _T_1608 : node _T_1609 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_9.io.enq.bits, _T_1609 node _T_1610 = eq(UInt<4>(0ha), idx_24) when _T_1610 : node _T_1611 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_10.io.enq.bits, _T_1611 node _T_1612 = eq(UInt<4>(0hb), idx_24) when _T_1612 : node _T_1613 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_11.io.enq.bits, _T_1613 node _T_1614 = eq(UInt<4>(0hc), idx_24) when _T_1614 : node _T_1615 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_12.io.enq.bits, _T_1615 node _T_1616 = eq(UInt<4>(0hd), idx_24) when _T_1616 : node _T_1617 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_13.io.enq.bits, _T_1617 node _T_1618 = eq(UInt<4>(0he), idx_24) when _T_1618 : node _T_1619 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_14.io.enq.bits, _T_1619 node _T_1620 = eq(UInt<4>(0hf), idx_24) when _T_1620 : node _T_1621 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_15.io.enq.bits, _T_1621 node _T_1622 = eq(UInt<5>(0h10), idx_24) when _T_1622 : node _T_1623 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_16.io.enq.bits, _T_1623 node _T_1624 = eq(UInt<5>(0h11), idx_24) when _T_1624 : node _T_1625 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_17.io.enq.bits, _T_1625 node _T_1626 = eq(UInt<5>(0h12), idx_24) when _T_1626 : node _T_1627 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_18.io.enq.bits, _T_1627 node _T_1628 = eq(UInt<5>(0h13), idx_24) when _T_1628 : node _T_1629 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_19.io.enq.bits, _T_1629 node _T_1630 = eq(UInt<5>(0h14), idx_24) when _T_1630 : node _T_1631 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_20.io.enq.bits, _T_1631 node _T_1632 = eq(UInt<5>(0h15), idx_24) when _T_1632 : node _T_1633 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_21.io.enq.bits, _T_1633 node _T_1634 = eq(UInt<5>(0h16), idx_24) when _T_1634 : node _T_1635 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_22.io.enq.bits, _T_1635 node _T_1636 = eq(UInt<5>(0h17), idx_24) when _T_1636 : node _T_1637 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_23.io.enq.bits, _T_1637 node _T_1638 = eq(UInt<5>(0h18), idx_24) when _T_1638 : node _T_1639 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_24.io.enq.bits, _T_1639 node _T_1640 = eq(UInt<5>(0h19), idx_24) when _T_1640 : node _T_1641 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_25.io.enq.bits, _T_1641 node _T_1642 = eq(UInt<5>(0h1a), idx_24) when _T_1642 : node _T_1643 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_26.io.enq.bits, _T_1643 node _T_1644 = eq(UInt<5>(0h1b), idx_24) when _T_1644 : node _T_1645 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_27.io.enq.bits, _T_1645 node _T_1646 = eq(UInt<5>(0h1c), idx_24) when _T_1646 : node _T_1647 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_28.io.enq.bits, _T_1647 node _T_1648 = eq(UInt<5>(0h1d), idx_24) when _T_1648 : node _T_1649 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_29.io.enq.bits, _T_1649 node _T_1650 = eq(UInt<5>(0h1e), idx_24) when _T_1650 : node _T_1651 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_30.io.enq.bits, _T_1651 node _T_1652 = eq(UInt<5>(0h1f), idx_24) when _T_1652 : node _T_1653 = shr(memresp_bits_shifted, 192) connect Queue64_UInt8_31.io.enq.bits, _T_1653 node _idx_T_25 = add(write_start_index, UInt<5>(0h19)) node idx_25 = rem(_idx_T_25, UInt<6>(0h20)) node _T_1654 = eq(UInt<1>(0h0), idx_25) when _T_1654 : node _T_1655 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8.io.enq.bits, _T_1655 node _T_1656 = eq(UInt<1>(0h1), idx_25) when _T_1656 : node _T_1657 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_1.io.enq.bits, _T_1657 node _T_1658 = eq(UInt<2>(0h2), idx_25) when _T_1658 : node _T_1659 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_2.io.enq.bits, _T_1659 node _T_1660 = eq(UInt<2>(0h3), idx_25) when _T_1660 : node _T_1661 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_3.io.enq.bits, _T_1661 node _T_1662 = eq(UInt<3>(0h4), idx_25) when _T_1662 : node _T_1663 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_4.io.enq.bits, _T_1663 node _T_1664 = eq(UInt<3>(0h5), idx_25) when _T_1664 : node _T_1665 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_5.io.enq.bits, _T_1665 node _T_1666 = eq(UInt<3>(0h6), idx_25) when _T_1666 : node _T_1667 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_6.io.enq.bits, _T_1667 node _T_1668 = eq(UInt<3>(0h7), idx_25) when _T_1668 : node _T_1669 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_7.io.enq.bits, _T_1669 node _T_1670 = eq(UInt<4>(0h8), idx_25) when _T_1670 : node _T_1671 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_8.io.enq.bits, _T_1671 node _T_1672 = eq(UInt<4>(0h9), idx_25) when _T_1672 : node _T_1673 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_9.io.enq.bits, _T_1673 node _T_1674 = eq(UInt<4>(0ha), idx_25) when _T_1674 : node _T_1675 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_10.io.enq.bits, _T_1675 node _T_1676 = eq(UInt<4>(0hb), idx_25) when _T_1676 : node _T_1677 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_11.io.enq.bits, _T_1677 node _T_1678 = eq(UInt<4>(0hc), idx_25) when _T_1678 : node _T_1679 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_12.io.enq.bits, _T_1679 node _T_1680 = eq(UInt<4>(0hd), idx_25) when _T_1680 : node _T_1681 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_13.io.enq.bits, _T_1681 node _T_1682 = eq(UInt<4>(0he), idx_25) when _T_1682 : node _T_1683 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_14.io.enq.bits, _T_1683 node _T_1684 = eq(UInt<4>(0hf), idx_25) when _T_1684 : node _T_1685 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_15.io.enq.bits, _T_1685 node _T_1686 = eq(UInt<5>(0h10), idx_25) when _T_1686 : node _T_1687 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_16.io.enq.bits, _T_1687 node _T_1688 = eq(UInt<5>(0h11), idx_25) when _T_1688 : node _T_1689 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_17.io.enq.bits, _T_1689 node _T_1690 = eq(UInt<5>(0h12), idx_25) when _T_1690 : node _T_1691 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_18.io.enq.bits, _T_1691 node _T_1692 = eq(UInt<5>(0h13), idx_25) when _T_1692 : node _T_1693 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_19.io.enq.bits, _T_1693 node _T_1694 = eq(UInt<5>(0h14), idx_25) when _T_1694 : node _T_1695 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_20.io.enq.bits, _T_1695 node _T_1696 = eq(UInt<5>(0h15), idx_25) when _T_1696 : node _T_1697 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_21.io.enq.bits, _T_1697 node _T_1698 = eq(UInt<5>(0h16), idx_25) when _T_1698 : node _T_1699 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_22.io.enq.bits, _T_1699 node _T_1700 = eq(UInt<5>(0h17), idx_25) when _T_1700 : node _T_1701 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_23.io.enq.bits, _T_1701 node _T_1702 = eq(UInt<5>(0h18), idx_25) when _T_1702 : node _T_1703 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_24.io.enq.bits, _T_1703 node _T_1704 = eq(UInt<5>(0h19), idx_25) when _T_1704 : node _T_1705 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_25.io.enq.bits, _T_1705 node _T_1706 = eq(UInt<5>(0h1a), idx_25) when _T_1706 : node _T_1707 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_26.io.enq.bits, _T_1707 node _T_1708 = eq(UInt<5>(0h1b), idx_25) when _T_1708 : node _T_1709 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_27.io.enq.bits, _T_1709 node _T_1710 = eq(UInt<5>(0h1c), idx_25) when _T_1710 : node _T_1711 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_28.io.enq.bits, _T_1711 node _T_1712 = eq(UInt<5>(0h1d), idx_25) when _T_1712 : node _T_1713 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_29.io.enq.bits, _T_1713 node _T_1714 = eq(UInt<5>(0h1e), idx_25) when _T_1714 : node _T_1715 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_30.io.enq.bits, _T_1715 node _T_1716 = eq(UInt<5>(0h1f), idx_25) when _T_1716 : node _T_1717 = shr(memresp_bits_shifted, 200) connect Queue64_UInt8_31.io.enq.bits, _T_1717 node _idx_T_26 = add(write_start_index, UInt<5>(0h1a)) node idx_26 = rem(_idx_T_26, UInt<6>(0h20)) node _T_1718 = eq(UInt<1>(0h0), idx_26) when _T_1718 : node _T_1719 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8.io.enq.bits, _T_1719 node _T_1720 = eq(UInt<1>(0h1), idx_26) when _T_1720 : node _T_1721 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_1.io.enq.bits, _T_1721 node _T_1722 = eq(UInt<2>(0h2), idx_26) when _T_1722 : node _T_1723 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_2.io.enq.bits, _T_1723 node _T_1724 = eq(UInt<2>(0h3), idx_26) when _T_1724 : node _T_1725 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_3.io.enq.bits, _T_1725 node _T_1726 = eq(UInt<3>(0h4), idx_26) when _T_1726 : node _T_1727 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_4.io.enq.bits, _T_1727 node _T_1728 = eq(UInt<3>(0h5), idx_26) when _T_1728 : node _T_1729 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_5.io.enq.bits, _T_1729 node _T_1730 = eq(UInt<3>(0h6), idx_26) when _T_1730 : node _T_1731 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_6.io.enq.bits, _T_1731 node _T_1732 = eq(UInt<3>(0h7), idx_26) when _T_1732 : node _T_1733 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_7.io.enq.bits, _T_1733 node _T_1734 = eq(UInt<4>(0h8), idx_26) when _T_1734 : node _T_1735 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_8.io.enq.bits, _T_1735 node _T_1736 = eq(UInt<4>(0h9), idx_26) when _T_1736 : node _T_1737 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_9.io.enq.bits, _T_1737 node _T_1738 = eq(UInt<4>(0ha), idx_26) when _T_1738 : node _T_1739 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_10.io.enq.bits, _T_1739 node _T_1740 = eq(UInt<4>(0hb), idx_26) when _T_1740 : node _T_1741 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_11.io.enq.bits, _T_1741 node _T_1742 = eq(UInt<4>(0hc), idx_26) when _T_1742 : node _T_1743 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_12.io.enq.bits, _T_1743 node _T_1744 = eq(UInt<4>(0hd), idx_26) when _T_1744 : node _T_1745 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_13.io.enq.bits, _T_1745 node _T_1746 = eq(UInt<4>(0he), idx_26) when _T_1746 : node _T_1747 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_14.io.enq.bits, _T_1747 node _T_1748 = eq(UInt<4>(0hf), idx_26) when _T_1748 : node _T_1749 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_15.io.enq.bits, _T_1749 node _T_1750 = eq(UInt<5>(0h10), idx_26) when _T_1750 : node _T_1751 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_16.io.enq.bits, _T_1751 node _T_1752 = eq(UInt<5>(0h11), idx_26) when _T_1752 : node _T_1753 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_17.io.enq.bits, _T_1753 node _T_1754 = eq(UInt<5>(0h12), idx_26) when _T_1754 : node _T_1755 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_18.io.enq.bits, _T_1755 node _T_1756 = eq(UInt<5>(0h13), idx_26) when _T_1756 : node _T_1757 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_19.io.enq.bits, _T_1757 node _T_1758 = eq(UInt<5>(0h14), idx_26) when _T_1758 : node _T_1759 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_20.io.enq.bits, _T_1759 node _T_1760 = eq(UInt<5>(0h15), idx_26) when _T_1760 : node _T_1761 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_21.io.enq.bits, _T_1761 node _T_1762 = eq(UInt<5>(0h16), idx_26) when _T_1762 : node _T_1763 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_22.io.enq.bits, _T_1763 node _T_1764 = eq(UInt<5>(0h17), idx_26) when _T_1764 : node _T_1765 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_23.io.enq.bits, _T_1765 node _T_1766 = eq(UInt<5>(0h18), idx_26) when _T_1766 : node _T_1767 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_24.io.enq.bits, _T_1767 node _T_1768 = eq(UInt<5>(0h19), idx_26) when _T_1768 : node _T_1769 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_25.io.enq.bits, _T_1769 node _T_1770 = eq(UInt<5>(0h1a), idx_26) when _T_1770 : node _T_1771 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_26.io.enq.bits, _T_1771 node _T_1772 = eq(UInt<5>(0h1b), idx_26) when _T_1772 : node _T_1773 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_27.io.enq.bits, _T_1773 node _T_1774 = eq(UInt<5>(0h1c), idx_26) when _T_1774 : node _T_1775 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_28.io.enq.bits, _T_1775 node _T_1776 = eq(UInt<5>(0h1d), idx_26) when _T_1776 : node _T_1777 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_29.io.enq.bits, _T_1777 node _T_1778 = eq(UInt<5>(0h1e), idx_26) when _T_1778 : node _T_1779 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_30.io.enq.bits, _T_1779 node _T_1780 = eq(UInt<5>(0h1f), idx_26) when _T_1780 : node _T_1781 = shr(memresp_bits_shifted, 208) connect Queue64_UInt8_31.io.enq.bits, _T_1781 node _idx_T_27 = add(write_start_index, UInt<5>(0h1b)) node idx_27 = rem(_idx_T_27, UInt<6>(0h20)) node _T_1782 = eq(UInt<1>(0h0), idx_27) when _T_1782 : node _T_1783 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8.io.enq.bits, _T_1783 node _T_1784 = eq(UInt<1>(0h1), idx_27) when _T_1784 : node _T_1785 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_1.io.enq.bits, _T_1785 node _T_1786 = eq(UInt<2>(0h2), idx_27) when _T_1786 : node _T_1787 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_2.io.enq.bits, _T_1787 node _T_1788 = eq(UInt<2>(0h3), idx_27) when _T_1788 : node _T_1789 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_3.io.enq.bits, _T_1789 node _T_1790 = eq(UInt<3>(0h4), idx_27) when _T_1790 : node _T_1791 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_4.io.enq.bits, _T_1791 node _T_1792 = eq(UInt<3>(0h5), idx_27) when _T_1792 : node _T_1793 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_5.io.enq.bits, _T_1793 node _T_1794 = eq(UInt<3>(0h6), idx_27) when _T_1794 : node _T_1795 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_6.io.enq.bits, _T_1795 node _T_1796 = eq(UInt<3>(0h7), idx_27) when _T_1796 : node _T_1797 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_7.io.enq.bits, _T_1797 node _T_1798 = eq(UInt<4>(0h8), idx_27) when _T_1798 : node _T_1799 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_8.io.enq.bits, _T_1799 node _T_1800 = eq(UInt<4>(0h9), idx_27) when _T_1800 : node _T_1801 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_9.io.enq.bits, _T_1801 node _T_1802 = eq(UInt<4>(0ha), idx_27) when _T_1802 : node _T_1803 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_10.io.enq.bits, _T_1803 node _T_1804 = eq(UInt<4>(0hb), idx_27) when _T_1804 : node _T_1805 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_11.io.enq.bits, _T_1805 node _T_1806 = eq(UInt<4>(0hc), idx_27) when _T_1806 : node _T_1807 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_12.io.enq.bits, _T_1807 node _T_1808 = eq(UInt<4>(0hd), idx_27) when _T_1808 : node _T_1809 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_13.io.enq.bits, _T_1809 node _T_1810 = eq(UInt<4>(0he), idx_27) when _T_1810 : node _T_1811 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_14.io.enq.bits, _T_1811 node _T_1812 = eq(UInt<4>(0hf), idx_27) when _T_1812 : node _T_1813 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_15.io.enq.bits, _T_1813 node _T_1814 = eq(UInt<5>(0h10), idx_27) when _T_1814 : node _T_1815 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_16.io.enq.bits, _T_1815 node _T_1816 = eq(UInt<5>(0h11), idx_27) when _T_1816 : node _T_1817 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_17.io.enq.bits, _T_1817 node _T_1818 = eq(UInt<5>(0h12), idx_27) when _T_1818 : node _T_1819 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_18.io.enq.bits, _T_1819 node _T_1820 = eq(UInt<5>(0h13), idx_27) when _T_1820 : node _T_1821 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_19.io.enq.bits, _T_1821 node _T_1822 = eq(UInt<5>(0h14), idx_27) when _T_1822 : node _T_1823 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_20.io.enq.bits, _T_1823 node _T_1824 = eq(UInt<5>(0h15), idx_27) when _T_1824 : node _T_1825 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_21.io.enq.bits, _T_1825 node _T_1826 = eq(UInt<5>(0h16), idx_27) when _T_1826 : node _T_1827 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_22.io.enq.bits, _T_1827 node _T_1828 = eq(UInt<5>(0h17), idx_27) when _T_1828 : node _T_1829 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_23.io.enq.bits, _T_1829 node _T_1830 = eq(UInt<5>(0h18), idx_27) when _T_1830 : node _T_1831 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_24.io.enq.bits, _T_1831 node _T_1832 = eq(UInt<5>(0h19), idx_27) when _T_1832 : node _T_1833 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_25.io.enq.bits, _T_1833 node _T_1834 = eq(UInt<5>(0h1a), idx_27) when _T_1834 : node _T_1835 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_26.io.enq.bits, _T_1835 node _T_1836 = eq(UInt<5>(0h1b), idx_27) when _T_1836 : node _T_1837 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_27.io.enq.bits, _T_1837 node _T_1838 = eq(UInt<5>(0h1c), idx_27) when _T_1838 : node _T_1839 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_28.io.enq.bits, _T_1839 node _T_1840 = eq(UInt<5>(0h1d), idx_27) when _T_1840 : node _T_1841 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_29.io.enq.bits, _T_1841 node _T_1842 = eq(UInt<5>(0h1e), idx_27) when _T_1842 : node _T_1843 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_30.io.enq.bits, _T_1843 node _T_1844 = eq(UInt<5>(0h1f), idx_27) when _T_1844 : node _T_1845 = shr(memresp_bits_shifted, 216) connect Queue64_UInt8_31.io.enq.bits, _T_1845 node _idx_T_28 = add(write_start_index, UInt<5>(0h1c)) node idx_28 = rem(_idx_T_28, UInt<6>(0h20)) node _T_1846 = eq(UInt<1>(0h0), idx_28) when _T_1846 : node _T_1847 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8.io.enq.bits, _T_1847 node _T_1848 = eq(UInt<1>(0h1), idx_28) when _T_1848 : node _T_1849 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_1.io.enq.bits, _T_1849 node _T_1850 = eq(UInt<2>(0h2), idx_28) when _T_1850 : node _T_1851 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_2.io.enq.bits, _T_1851 node _T_1852 = eq(UInt<2>(0h3), idx_28) when _T_1852 : node _T_1853 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_3.io.enq.bits, _T_1853 node _T_1854 = eq(UInt<3>(0h4), idx_28) when _T_1854 : node _T_1855 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_4.io.enq.bits, _T_1855 node _T_1856 = eq(UInt<3>(0h5), idx_28) when _T_1856 : node _T_1857 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_5.io.enq.bits, _T_1857 node _T_1858 = eq(UInt<3>(0h6), idx_28) when _T_1858 : node _T_1859 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_6.io.enq.bits, _T_1859 node _T_1860 = eq(UInt<3>(0h7), idx_28) when _T_1860 : node _T_1861 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_7.io.enq.bits, _T_1861 node _T_1862 = eq(UInt<4>(0h8), idx_28) when _T_1862 : node _T_1863 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_8.io.enq.bits, _T_1863 node _T_1864 = eq(UInt<4>(0h9), idx_28) when _T_1864 : node _T_1865 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_9.io.enq.bits, _T_1865 node _T_1866 = eq(UInt<4>(0ha), idx_28) when _T_1866 : node _T_1867 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_10.io.enq.bits, _T_1867 node _T_1868 = eq(UInt<4>(0hb), idx_28) when _T_1868 : node _T_1869 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_11.io.enq.bits, _T_1869 node _T_1870 = eq(UInt<4>(0hc), idx_28) when _T_1870 : node _T_1871 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_12.io.enq.bits, _T_1871 node _T_1872 = eq(UInt<4>(0hd), idx_28) when _T_1872 : node _T_1873 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_13.io.enq.bits, _T_1873 node _T_1874 = eq(UInt<4>(0he), idx_28) when _T_1874 : node _T_1875 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_14.io.enq.bits, _T_1875 node _T_1876 = eq(UInt<4>(0hf), idx_28) when _T_1876 : node _T_1877 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_15.io.enq.bits, _T_1877 node _T_1878 = eq(UInt<5>(0h10), idx_28) when _T_1878 : node _T_1879 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_16.io.enq.bits, _T_1879 node _T_1880 = eq(UInt<5>(0h11), idx_28) when _T_1880 : node _T_1881 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_17.io.enq.bits, _T_1881 node _T_1882 = eq(UInt<5>(0h12), idx_28) when _T_1882 : node _T_1883 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_18.io.enq.bits, _T_1883 node _T_1884 = eq(UInt<5>(0h13), idx_28) when _T_1884 : node _T_1885 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_19.io.enq.bits, _T_1885 node _T_1886 = eq(UInt<5>(0h14), idx_28) when _T_1886 : node _T_1887 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_20.io.enq.bits, _T_1887 node _T_1888 = eq(UInt<5>(0h15), idx_28) when _T_1888 : node _T_1889 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_21.io.enq.bits, _T_1889 node _T_1890 = eq(UInt<5>(0h16), idx_28) when _T_1890 : node _T_1891 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_22.io.enq.bits, _T_1891 node _T_1892 = eq(UInt<5>(0h17), idx_28) when _T_1892 : node _T_1893 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_23.io.enq.bits, _T_1893 node _T_1894 = eq(UInt<5>(0h18), idx_28) when _T_1894 : node _T_1895 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_24.io.enq.bits, _T_1895 node _T_1896 = eq(UInt<5>(0h19), idx_28) when _T_1896 : node _T_1897 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_25.io.enq.bits, _T_1897 node _T_1898 = eq(UInt<5>(0h1a), idx_28) when _T_1898 : node _T_1899 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_26.io.enq.bits, _T_1899 node _T_1900 = eq(UInt<5>(0h1b), idx_28) when _T_1900 : node _T_1901 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_27.io.enq.bits, _T_1901 node _T_1902 = eq(UInt<5>(0h1c), idx_28) when _T_1902 : node _T_1903 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_28.io.enq.bits, _T_1903 node _T_1904 = eq(UInt<5>(0h1d), idx_28) when _T_1904 : node _T_1905 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_29.io.enq.bits, _T_1905 node _T_1906 = eq(UInt<5>(0h1e), idx_28) when _T_1906 : node _T_1907 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_30.io.enq.bits, _T_1907 node _T_1908 = eq(UInt<5>(0h1f), idx_28) when _T_1908 : node _T_1909 = shr(memresp_bits_shifted, 224) connect Queue64_UInt8_31.io.enq.bits, _T_1909 node _idx_T_29 = add(write_start_index, UInt<5>(0h1d)) node idx_29 = rem(_idx_T_29, UInt<6>(0h20)) node _T_1910 = eq(UInt<1>(0h0), idx_29) when _T_1910 : node _T_1911 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8.io.enq.bits, _T_1911 node _T_1912 = eq(UInt<1>(0h1), idx_29) when _T_1912 : node _T_1913 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_1.io.enq.bits, _T_1913 node _T_1914 = eq(UInt<2>(0h2), idx_29) when _T_1914 : node _T_1915 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_2.io.enq.bits, _T_1915 node _T_1916 = eq(UInt<2>(0h3), idx_29) when _T_1916 : node _T_1917 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_3.io.enq.bits, _T_1917 node _T_1918 = eq(UInt<3>(0h4), idx_29) when _T_1918 : node _T_1919 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_4.io.enq.bits, _T_1919 node _T_1920 = eq(UInt<3>(0h5), idx_29) when _T_1920 : node _T_1921 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_5.io.enq.bits, _T_1921 node _T_1922 = eq(UInt<3>(0h6), idx_29) when _T_1922 : node _T_1923 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_6.io.enq.bits, _T_1923 node _T_1924 = eq(UInt<3>(0h7), idx_29) when _T_1924 : node _T_1925 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_7.io.enq.bits, _T_1925 node _T_1926 = eq(UInt<4>(0h8), idx_29) when _T_1926 : node _T_1927 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_8.io.enq.bits, _T_1927 node _T_1928 = eq(UInt<4>(0h9), idx_29) when _T_1928 : node _T_1929 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_9.io.enq.bits, _T_1929 node _T_1930 = eq(UInt<4>(0ha), idx_29) when _T_1930 : node _T_1931 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_10.io.enq.bits, _T_1931 node _T_1932 = eq(UInt<4>(0hb), idx_29) when _T_1932 : node _T_1933 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_11.io.enq.bits, _T_1933 node _T_1934 = eq(UInt<4>(0hc), idx_29) when _T_1934 : node _T_1935 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_12.io.enq.bits, _T_1935 node _T_1936 = eq(UInt<4>(0hd), idx_29) when _T_1936 : node _T_1937 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_13.io.enq.bits, _T_1937 node _T_1938 = eq(UInt<4>(0he), idx_29) when _T_1938 : node _T_1939 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_14.io.enq.bits, _T_1939 node _T_1940 = eq(UInt<4>(0hf), idx_29) when _T_1940 : node _T_1941 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_15.io.enq.bits, _T_1941 node _T_1942 = eq(UInt<5>(0h10), idx_29) when _T_1942 : node _T_1943 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_16.io.enq.bits, _T_1943 node _T_1944 = eq(UInt<5>(0h11), idx_29) when _T_1944 : node _T_1945 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_17.io.enq.bits, _T_1945 node _T_1946 = eq(UInt<5>(0h12), idx_29) when _T_1946 : node _T_1947 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_18.io.enq.bits, _T_1947 node _T_1948 = eq(UInt<5>(0h13), idx_29) when _T_1948 : node _T_1949 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_19.io.enq.bits, _T_1949 node _T_1950 = eq(UInt<5>(0h14), idx_29) when _T_1950 : node _T_1951 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_20.io.enq.bits, _T_1951 node _T_1952 = eq(UInt<5>(0h15), idx_29) when _T_1952 : node _T_1953 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_21.io.enq.bits, _T_1953 node _T_1954 = eq(UInt<5>(0h16), idx_29) when _T_1954 : node _T_1955 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_22.io.enq.bits, _T_1955 node _T_1956 = eq(UInt<5>(0h17), idx_29) when _T_1956 : node _T_1957 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_23.io.enq.bits, _T_1957 node _T_1958 = eq(UInt<5>(0h18), idx_29) when _T_1958 : node _T_1959 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_24.io.enq.bits, _T_1959 node _T_1960 = eq(UInt<5>(0h19), idx_29) when _T_1960 : node _T_1961 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_25.io.enq.bits, _T_1961 node _T_1962 = eq(UInt<5>(0h1a), idx_29) when _T_1962 : node _T_1963 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_26.io.enq.bits, _T_1963 node _T_1964 = eq(UInt<5>(0h1b), idx_29) when _T_1964 : node _T_1965 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_27.io.enq.bits, _T_1965 node _T_1966 = eq(UInt<5>(0h1c), idx_29) when _T_1966 : node _T_1967 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_28.io.enq.bits, _T_1967 node _T_1968 = eq(UInt<5>(0h1d), idx_29) when _T_1968 : node _T_1969 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_29.io.enq.bits, _T_1969 node _T_1970 = eq(UInt<5>(0h1e), idx_29) when _T_1970 : node _T_1971 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_30.io.enq.bits, _T_1971 node _T_1972 = eq(UInt<5>(0h1f), idx_29) when _T_1972 : node _T_1973 = shr(memresp_bits_shifted, 232) connect Queue64_UInt8_31.io.enq.bits, _T_1973 node _idx_T_30 = add(write_start_index, UInt<5>(0h1e)) node idx_30 = rem(_idx_T_30, UInt<6>(0h20)) node _T_1974 = eq(UInt<1>(0h0), idx_30) when _T_1974 : node _T_1975 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8.io.enq.bits, _T_1975 node _T_1976 = eq(UInt<1>(0h1), idx_30) when _T_1976 : node _T_1977 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_1.io.enq.bits, _T_1977 node _T_1978 = eq(UInt<2>(0h2), idx_30) when _T_1978 : node _T_1979 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_2.io.enq.bits, _T_1979 node _T_1980 = eq(UInt<2>(0h3), idx_30) when _T_1980 : node _T_1981 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_3.io.enq.bits, _T_1981 node _T_1982 = eq(UInt<3>(0h4), idx_30) when _T_1982 : node _T_1983 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_4.io.enq.bits, _T_1983 node _T_1984 = eq(UInt<3>(0h5), idx_30) when _T_1984 : node _T_1985 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_5.io.enq.bits, _T_1985 node _T_1986 = eq(UInt<3>(0h6), idx_30) when _T_1986 : node _T_1987 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_6.io.enq.bits, _T_1987 node _T_1988 = eq(UInt<3>(0h7), idx_30) when _T_1988 : node _T_1989 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_7.io.enq.bits, _T_1989 node _T_1990 = eq(UInt<4>(0h8), idx_30) when _T_1990 : node _T_1991 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_8.io.enq.bits, _T_1991 node _T_1992 = eq(UInt<4>(0h9), idx_30) when _T_1992 : node _T_1993 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_9.io.enq.bits, _T_1993 node _T_1994 = eq(UInt<4>(0ha), idx_30) when _T_1994 : node _T_1995 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_10.io.enq.bits, _T_1995 node _T_1996 = eq(UInt<4>(0hb), idx_30) when _T_1996 : node _T_1997 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_11.io.enq.bits, _T_1997 node _T_1998 = eq(UInt<4>(0hc), idx_30) when _T_1998 : node _T_1999 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_12.io.enq.bits, _T_1999 node _T_2000 = eq(UInt<4>(0hd), idx_30) when _T_2000 : node _T_2001 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_13.io.enq.bits, _T_2001 node _T_2002 = eq(UInt<4>(0he), idx_30) when _T_2002 : node _T_2003 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_14.io.enq.bits, _T_2003 node _T_2004 = eq(UInt<4>(0hf), idx_30) when _T_2004 : node _T_2005 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_15.io.enq.bits, _T_2005 node _T_2006 = eq(UInt<5>(0h10), idx_30) when _T_2006 : node _T_2007 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_16.io.enq.bits, _T_2007 node _T_2008 = eq(UInt<5>(0h11), idx_30) when _T_2008 : node _T_2009 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_17.io.enq.bits, _T_2009 node _T_2010 = eq(UInt<5>(0h12), idx_30) when _T_2010 : node _T_2011 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_18.io.enq.bits, _T_2011 node _T_2012 = eq(UInt<5>(0h13), idx_30) when _T_2012 : node _T_2013 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_19.io.enq.bits, _T_2013 node _T_2014 = eq(UInt<5>(0h14), idx_30) when _T_2014 : node _T_2015 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_20.io.enq.bits, _T_2015 node _T_2016 = eq(UInt<5>(0h15), idx_30) when _T_2016 : node _T_2017 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_21.io.enq.bits, _T_2017 node _T_2018 = eq(UInt<5>(0h16), idx_30) when _T_2018 : node _T_2019 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_22.io.enq.bits, _T_2019 node _T_2020 = eq(UInt<5>(0h17), idx_30) when _T_2020 : node _T_2021 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_23.io.enq.bits, _T_2021 node _T_2022 = eq(UInt<5>(0h18), idx_30) when _T_2022 : node _T_2023 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_24.io.enq.bits, _T_2023 node _T_2024 = eq(UInt<5>(0h19), idx_30) when _T_2024 : node _T_2025 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_25.io.enq.bits, _T_2025 node _T_2026 = eq(UInt<5>(0h1a), idx_30) when _T_2026 : node _T_2027 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_26.io.enq.bits, _T_2027 node _T_2028 = eq(UInt<5>(0h1b), idx_30) when _T_2028 : node _T_2029 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_27.io.enq.bits, _T_2029 node _T_2030 = eq(UInt<5>(0h1c), idx_30) when _T_2030 : node _T_2031 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_28.io.enq.bits, _T_2031 node _T_2032 = eq(UInt<5>(0h1d), idx_30) when _T_2032 : node _T_2033 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_29.io.enq.bits, _T_2033 node _T_2034 = eq(UInt<5>(0h1e), idx_30) when _T_2034 : node _T_2035 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_30.io.enq.bits, _T_2035 node _T_2036 = eq(UInt<5>(0h1f), idx_30) when _T_2036 : node _T_2037 = shr(memresp_bits_shifted, 240) connect Queue64_UInt8_31.io.enq.bits, _T_2037 node _idx_T_31 = add(write_start_index, UInt<5>(0h1f)) node idx_31 = rem(_idx_T_31, UInt<6>(0h20)) node _T_2038 = eq(UInt<1>(0h0), idx_31) when _T_2038 : node _T_2039 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8.io.enq.bits, _T_2039 node _T_2040 = eq(UInt<1>(0h1), idx_31) when _T_2040 : node _T_2041 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_1.io.enq.bits, _T_2041 node _T_2042 = eq(UInt<2>(0h2), idx_31) when _T_2042 : node _T_2043 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_2.io.enq.bits, _T_2043 node _T_2044 = eq(UInt<2>(0h3), idx_31) when _T_2044 : node _T_2045 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_3.io.enq.bits, _T_2045 node _T_2046 = eq(UInt<3>(0h4), idx_31) when _T_2046 : node _T_2047 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_4.io.enq.bits, _T_2047 node _T_2048 = eq(UInt<3>(0h5), idx_31) when _T_2048 : node _T_2049 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_5.io.enq.bits, _T_2049 node _T_2050 = eq(UInt<3>(0h6), idx_31) when _T_2050 : node _T_2051 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_6.io.enq.bits, _T_2051 node _T_2052 = eq(UInt<3>(0h7), idx_31) when _T_2052 : node _T_2053 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_7.io.enq.bits, _T_2053 node _T_2054 = eq(UInt<4>(0h8), idx_31) when _T_2054 : node _T_2055 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_8.io.enq.bits, _T_2055 node _T_2056 = eq(UInt<4>(0h9), idx_31) when _T_2056 : node _T_2057 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_9.io.enq.bits, _T_2057 node _T_2058 = eq(UInt<4>(0ha), idx_31) when _T_2058 : node _T_2059 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_10.io.enq.bits, _T_2059 node _T_2060 = eq(UInt<4>(0hb), idx_31) when _T_2060 : node _T_2061 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_11.io.enq.bits, _T_2061 node _T_2062 = eq(UInt<4>(0hc), idx_31) when _T_2062 : node _T_2063 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_12.io.enq.bits, _T_2063 node _T_2064 = eq(UInt<4>(0hd), idx_31) when _T_2064 : node _T_2065 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_13.io.enq.bits, _T_2065 node _T_2066 = eq(UInt<4>(0he), idx_31) when _T_2066 : node _T_2067 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_14.io.enq.bits, _T_2067 node _T_2068 = eq(UInt<4>(0hf), idx_31) when _T_2068 : node _T_2069 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_15.io.enq.bits, _T_2069 node _T_2070 = eq(UInt<5>(0h10), idx_31) when _T_2070 : node _T_2071 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_16.io.enq.bits, _T_2071 node _T_2072 = eq(UInt<5>(0h11), idx_31) when _T_2072 : node _T_2073 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_17.io.enq.bits, _T_2073 node _T_2074 = eq(UInt<5>(0h12), idx_31) when _T_2074 : node _T_2075 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_18.io.enq.bits, _T_2075 node _T_2076 = eq(UInt<5>(0h13), idx_31) when _T_2076 : node _T_2077 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_19.io.enq.bits, _T_2077 node _T_2078 = eq(UInt<5>(0h14), idx_31) when _T_2078 : node _T_2079 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_20.io.enq.bits, _T_2079 node _T_2080 = eq(UInt<5>(0h15), idx_31) when _T_2080 : node _T_2081 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_21.io.enq.bits, _T_2081 node _T_2082 = eq(UInt<5>(0h16), idx_31) when _T_2082 : node _T_2083 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_22.io.enq.bits, _T_2083 node _T_2084 = eq(UInt<5>(0h17), idx_31) when _T_2084 : node _T_2085 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_23.io.enq.bits, _T_2085 node _T_2086 = eq(UInt<5>(0h18), idx_31) when _T_2086 : node _T_2087 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_24.io.enq.bits, _T_2087 node _T_2088 = eq(UInt<5>(0h19), idx_31) when _T_2088 : node _T_2089 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_25.io.enq.bits, _T_2089 node _T_2090 = eq(UInt<5>(0h1a), idx_31) when _T_2090 : node _T_2091 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_26.io.enq.bits, _T_2091 node _T_2092 = eq(UInt<5>(0h1b), idx_31) when _T_2092 : node _T_2093 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_27.io.enq.bits, _T_2093 node _T_2094 = eq(UInt<5>(0h1c), idx_31) when _T_2094 : node _T_2095 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_28.io.enq.bits, _T_2095 node _T_2096 = eq(UInt<5>(0h1d), idx_31) when _T_2096 : node _T_2097 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_29.io.enq.bits, _T_2097 node _T_2098 = eq(UInt<5>(0h1e), idx_31) when _T_2098 : node _T_2099 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_30.io.enq.bits, _T_2099 node _T_2100 = eq(UInt<5>(0h1f), idx_31) when _T_2100 : node _T_2101 = shr(memresp_bits_shifted, 248) connect Queue64_UInt8_31.io.enq.bits, _T_2101 node _len_to_write_T = sub(load_info_queue.io.deq.bits.end_byte, load_info_queue.io.deq.bits.start_byte) node _len_to_write_T_1 = tail(_len_to_write_T, 1) node len_to_write = add(_len_to_write_T_1, UInt<1>(0h1)) node wrap_len_index_wide = add(write_start_index, len_to_write) node wrap_len_index_end = rem(wrap_len_index_wide, UInt<6>(0h20)) node wrapped = geq(wrap_len_index_wide, UInt<6>(0h20)) when load_info_queue.io.deq.valid : regreset loginfo_cycles_11 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_22 = add(loginfo_cycles_11, UInt<1>(0h1)) node _loginfo_cycles_T_23 = tail(_loginfo_cycles_T_22, 1) connect loginfo_cycles_11, _loginfo_cycles_T_23 node _T_2102 = asUInt(reset) node _T_2103 = eq(_T_2102, UInt<1>(0h0)) when _T_2103 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_11) : printf_22 node _T_2104 = asUInt(reset) node _T_2105 = eq(_T_2104, UInt<1>(0h0)) when _T_2105 : printf(clock, UInt<1>(0h1), "memloader start %x, end %x\n", load_info_queue.io.deq.bits.start_byte, load_info_queue.io.deq.bits.end_byte) : printf_23 node _all_queues_ready_T = and(Queue64_UInt8.io.enq.ready, Queue64_UInt8_1.io.enq.ready) node _all_queues_ready_T_1 = and(_all_queues_ready_T, Queue64_UInt8_2.io.enq.ready) node _all_queues_ready_T_2 = and(_all_queues_ready_T_1, Queue64_UInt8_3.io.enq.ready) node _all_queues_ready_T_3 = and(_all_queues_ready_T_2, Queue64_UInt8_4.io.enq.ready) node _all_queues_ready_T_4 = and(_all_queues_ready_T_3, Queue64_UInt8_5.io.enq.ready) node _all_queues_ready_T_5 = and(_all_queues_ready_T_4, Queue64_UInt8_6.io.enq.ready) node _all_queues_ready_T_6 = and(_all_queues_ready_T_5, Queue64_UInt8_7.io.enq.ready) node _all_queues_ready_T_7 = and(_all_queues_ready_T_6, Queue64_UInt8_8.io.enq.ready) node _all_queues_ready_T_8 = and(_all_queues_ready_T_7, Queue64_UInt8_9.io.enq.ready) node _all_queues_ready_T_9 = and(_all_queues_ready_T_8, Queue64_UInt8_10.io.enq.ready) node _all_queues_ready_T_10 = and(_all_queues_ready_T_9, Queue64_UInt8_11.io.enq.ready) node _all_queues_ready_T_11 = and(_all_queues_ready_T_10, Queue64_UInt8_12.io.enq.ready) node _all_queues_ready_T_12 = and(_all_queues_ready_T_11, Queue64_UInt8_13.io.enq.ready) node _all_queues_ready_T_13 = and(_all_queues_ready_T_12, Queue64_UInt8_14.io.enq.ready) node _all_queues_ready_T_14 = and(_all_queues_ready_T_13, Queue64_UInt8_15.io.enq.ready) node _all_queues_ready_T_15 = and(_all_queues_ready_T_14, Queue64_UInt8_16.io.enq.ready) node _all_queues_ready_T_16 = and(_all_queues_ready_T_15, Queue64_UInt8_17.io.enq.ready) node _all_queues_ready_T_17 = and(_all_queues_ready_T_16, Queue64_UInt8_18.io.enq.ready) node _all_queues_ready_T_18 = and(_all_queues_ready_T_17, Queue64_UInt8_19.io.enq.ready) node _all_queues_ready_T_19 = and(_all_queues_ready_T_18, Queue64_UInt8_20.io.enq.ready) node _all_queues_ready_T_20 = and(_all_queues_ready_T_19, Queue64_UInt8_21.io.enq.ready) node _all_queues_ready_T_21 = and(_all_queues_ready_T_20, Queue64_UInt8_22.io.enq.ready) node _all_queues_ready_T_22 = and(_all_queues_ready_T_21, Queue64_UInt8_23.io.enq.ready) node _all_queues_ready_T_23 = and(_all_queues_ready_T_22, Queue64_UInt8_24.io.enq.ready) node _all_queues_ready_T_24 = and(_all_queues_ready_T_23, Queue64_UInt8_25.io.enq.ready) node _all_queues_ready_T_25 = and(_all_queues_ready_T_24, Queue64_UInt8_26.io.enq.ready) node _all_queues_ready_T_26 = and(_all_queues_ready_T_25, Queue64_UInt8_27.io.enq.ready) node _all_queues_ready_T_27 = and(_all_queues_ready_T_26, Queue64_UInt8_28.io.enq.ready) node _all_queues_ready_T_28 = and(_all_queues_ready_T_27, Queue64_UInt8_29.io.enq.ready) node _all_queues_ready_T_29 = and(_all_queues_ready_T_28, Queue64_UInt8_30.io.enq.ready) node all_queues_ready = and(_all_queues_ready_T_29, Queue64_UInt8_31.io.enq.ready) node _load_info_queue_io_deq_ready_T = and(io.l2helperUser.resp.valid, all_queues_ready) connect load_info_queue.io.deq.ready, _load_info_queue_io_deq_ready_T node _io_l2helperUser_resp_ready_T = and(load_info_queue.io.deq.valid, all_queues_ready) connect io.l2helperUser.resp.ready, _io_l2helperUser_resp_ready_T node _resp_fire_allqueues_T = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node resp_fire_allqueues = and(_resp_fire_allqueues_T, all_queues_ready) when resp_fire_allqueues : connect write_start_index, wrap_len_index_end node _use_this_queue_T = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_1 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_2 = or(_use_this_queue_T, _use_this_queue_T_1) node _use_this_queue_T_3 = geq(UInt<1>(0h0), write_start_index) node _use_this_queue_T_4 = lt(UInt<1>(0h0), wrap_len_index_end) node _use_this_queue_T_5 = and(_use_this_queue_T_3, _use_this_queue_T_4) node use_this_queue = mux(wrapped, _use_this_queue_T_2, _use_this_queue_T_5) node _T_2106 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2107 = and(_T_2106, use_this_queue) node _T_2108 = and(_T_2107, all_queues_ready) connect Queue64_UInt8.io.enq.valid, _T_2108 node _use_this_queue_T_6 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_7 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_8 = or(_use_this_queue_T_6, _use_this_queue_T_7) node _use_this_queue_T_9 = geq(UInt<1>(0h1), write_start_index) node _use_this_queue_T_10 = lt(UInt<1>(0h1), wrap_len_index_end) node _use_this_queue_T_11 = and(_use_this_queue_T_9, _use_this_queue_T_10) node use_this_queue_1 = mux(wrapped, _use_this_queue_T_8, _use_this_queue_T_11) node _T_2109 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2110 = and(_T_2109, use_this_queue_1) node _T_2111 = and(_T_2110, all_queues_ready) connect Queue64_UInt8_1.io.enq.valid, _T_2111 node _use_this_queue_T_12 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_13 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_14 = or(_use_this_queue_T_12, _use_this_queue_T_13) node _use_this_queue_T_15 = geq(UInt<2>(0h2), write_start_index) node _use_this_queue_T_16 = lt(UInt<2>(0h2), wrap_len_index_end) node _use_this_queue_T_17 = and(_use_this_queue_T_15, _use_this_queue_T_16) node use_this_queue_2 = mux(wrapped, _use_this_queue_T_14, _use_this_queue_T_17) node _T_2112 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2113 = and(_T_2112, use_this_queue_2) node _T_2114 = and(_T_2113, all_queues_ready) connect Queue64_UInt8_2.io.enq.valid, _T_2114 node _use_this_queue_T_18 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_19 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_20 = or(_use_this_queue_T_18, _use_this_queue_T_19) node _use_this_queue_T_21 = geq(UInt<2>(0h3), write_start_index) node _use_this_queue_T_22 = lt(UInt<2>(0h3), wrap_len_index_end) node _use_this_queue_T_23 = and(_use_this_queue_T_21, _use_this_queue_T_22) node use_this_queue_3 = mux(wrapped, _use_this_queue_T_20, _use_this_queue_T_23) node _T_2115 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2116 = and(_T_2115, use_this_queue_3) node _T_2117 = and(_T_2116, all_queues_ready) connect Queue64_UInt8_3.io.enq.valid, _T_2117 node _use_this_queue_T_24 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_25 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_26 = or(_use_this_queue_T_24, _use_this_queue_T_25) node _use_this_queue_T_27 = geq(UInt<3>(0h4), write_start_index) node _use_this_queue_T_28 = lt(UInt<3>(0h4), wrap_len_index_end) node _use_this_queue_T_29 = and(_use_this_queue_T_27, _use_this_queue_T_28) node use_this_queue_4 = mux(wrapped, _use_this_queue_T_26, _use_this_queue_T_29) node _T_2118 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2119 = and(_T_2118, use_this_queue_4) node _T_2120 = and(_T_2119, all_queues_ready) connect Queue64_UInt8_4.io.enq.valid, _T_2120 node _use_this_queue_T_30 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_31 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_32 = or(_use_this_queue_T_30, _use_this_queue_T_31) node _use_this_queue_T_33 = geq(UInt<3>(0h5), write_start_index) node _use_this_queue_T_34 = lt(UInt<3>(0h5), wrap_len_index_end) node _use_this_queue_T_35 = and(_use_this_queue_T_33, _use_this_queue_T_34) node use_this_queue_5 = mux(wrapped, _use_this_queue_T_32, _use_this_queue_T_35) node _T_2121 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2122 = and(_T_2121, use_this_queue_5) node _T_2123 = and(_T_2122, all_queues_ready) connect Queue64_UInt8_5.io.enq.valid, _T_2123 node _use_this_queue_T_36 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_37 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_38 = or(_use_this_queue_T_36, _use_this_queue_T_37) node _use_this_queue_T_39 = geq(UInt<3>(0h6), write_start_index) node _use_this_queue_T_40 = lt(UInt<3>(0h6), wrap_len_index_end) node _use_this_queue_T_41 = and(_use_this_queue_T_39, _use_this_queue_T_40) node use_this_queue_6 = mux(wrapped, _use_this_queue_T_38, _use_this_queue_T_41) node _T_2124 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2125 = and(_T_2124, use_this_queue_6) node _T_2126 = and(_T_2125, all_queues_ready) connect Queue64_UInt8_6.io.enq.valid, _T_2126 node _use_this_queue_T_42 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_43 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_44 = or(_use_this_queue_T_42, _use_this_queue_T_43) node _use_this_queue_T_45 = geq(UInt<3>(0h7), write_start_index) node _use_this_queue_T_46 = lt(UInt<3>(0h7), wrap_len_index_end) node _use_this_queue_T_47 = and(_use_this_queue_T_45, _use_this_queue_T_46) node use_this_queue_7 = mux(wrapped, _use_this_queue_T_44, _use_this_queue_T_47) node _T_2127 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2128 = and(_T_2127, use_this_queue_7) node _T_2129 = and(_T_2128, all_queues_ready) connect Queue64_UInt8_7.io.enq.valid, _T_2129 node _use_this_queue_T_48 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_49 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_50 = or(_use_this_queue_T_48, _use_this_queue_T_49) node _use_this_queue_T_51 = geq(UInt<4>(0h8), write_start_index) node _use_this_queue_T_52 = lt(UInt<4>(0h8), wrap_len_index_end) node _use_this_queue_T_53 = and(_use_this_queue_T_51, _use_this_queue_T_52) node use_this_queue_8 = mux(wrapped, _use_this_queue_T_50, _use_this_queue_T_53) node _T_2130 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2131 = and(_T_2130, use_this_queue_8) node _T_2132 = and(_T_2131, all_queues_ready) connect Queue64_UInt8_8.io.enq.valid, _T_2132 node _use_this_queue_T_54 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_55 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_56 = or(_use_this_queue_T_54, _use_this_queue_T_55) node _use_this_queue_T_57 = geq(UInt<4>(0h9), write_start_index) node _use_this_queue_T_58 = lt(UInt<4>(0h9), wrap_len_index_end) node _use_this_queue_T_59 = and(_use_this_queue_T_57, _use_this_queue_T_58) node use_this_queue_9 = mux(wrapped, _use_this_queue_T_56, _use_this_queue_T_59) node _T_2133 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2134 = and(_T_2133, use_this_queue_9) node _T_2135 = and(_T_2134, all_queues_ready) connect Queue64_UInt8_9.io.enq.valid, _T_2135 node _use_this_queue_T_60 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_61 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_62 = or(_use_this_queue_T_60, _use_this_queue_T_61) node _use_this_queue_T_63 = geq(UInt<4>(0ha), write_start_index) node _use_this_queue_T_64 = lt(UInt<4>(0ha), wrap_len_index_end) node _use_this_queue_T_65 = and(_use_this_queue_T_63, _use_this_queue_T_64) node use_this_queue_10 = mux(wrapped, _use_this_queue_T_62, _use_this_queue_T_65) node _T_2136 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2137 = and(_T_2136, use_this_queue_10) node _T_2138 = and(_T_2137, all_queues_ready) connect Queue64_UInt8_10.io.enq.valid, _T_2138 node _use_this_queue_T_66 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_67 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_68 = or(_use_this_queue_T_66, _use_this_queue_T_67) node _use_this_queue_T_69 = geq(UInt<4>(0hb), write_start_index) node _use_this_queue_T_70 = lt(UInt<4>(0hb), wrap_len_index_end) node _use_this_queue_T_71 = and(_use_this_queue_T_69, _use_this_queue_T_70) node use_this_queue_11 = mux(wrapped, _use_this_queue_T_68, _use_this_queue_T_71) node _T_2139 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2140 = and(_T_2139, use_this_queue_11) node _T_2141 = and(_T_2140, all_queues_ready) connect Queue64_UInt8_11.io.enq.valid, _T_2141 node _use_this_queue_T_72 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_73 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_74 = or(_use_this_queue_T_72, _use_this_queue_T_73) node _use_this_queue_T_75 = geq(UInt<4>(0hc), write_start_index) node _use_this_queue_T_76 = lt(UInt<4>(0hc), wrap_len_index_end) node _use_this_queue_T_77 = and(_use_this_queue_T_75, _use_this_queue_T_76) node use_this_queue_12 = mux(wrapped, _use_this_queue_T_74, _use_this_queue_T_77) node _T_2142 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2143 = and(_T_2142, use_this_queue_12) node _T_2144 = and(_T_2143, all_queues_ready) connect Queue64_UInt8_12.io.enq.valid, _T_2144 node _use_this_queue_T_78 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_79 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_80 = or(_use_this_queue_T_78, _use_this_queue_T_79) node _use_this_queue_T_81 = geq(UInt<4>(0hd), write_start_index) node _use_this_queue_T_82 = lt(UInt<4>(0hd), wrap_len_index_end) node _use_this_queue_T_83 = and(_use_this_queue_T_81, _use_this_queue_T_82) node use_this_queue_13 = mux(wrapped, _use_this_queue_T_80, _use_this_queue_T_83) node _T_2145 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2146 = and(_T_2145, use_this_queue_13) node _T_2147 = and(_T_2146, all_queues_ready) connect Queue64_UInt8_13.io.enq.valid, _T_2147 node _use_this_queue_T_84 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_85 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_86 = or(_use_this_queue_T_84, _use_this_queue_T_85) node _use_this_queue_T_87 = geq(UInt<4>(0he), write_start_index) node _use_this_queue_T_88 = lt(UInt<4>(0he), wrap_len_index_end) node _use_this_queue_T_89 = and(_use_this_queue_T_87, _use_this_queue_T_88) node use_this_queue_14 = mux(wrapped, _use_this_queue_T_86, _use_this_queue_T_89) node _T_2148 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2149 = and(_T_2148, use_this_queue_14) node _T_2150 = and(_T_2149, all_queues_ready) connect Queue64_UInt8_14.io.enq.valid, _T_2150 node _use_this_queue_T_90 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_91 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_92 = or(_use_this_queue_T_90, _use_this_queue_T_91) node _use_this_queue_T_93 = geq(UInt<4>(0hf), write_start_index) node _use_this_queue_T_94 = lt(UInt<4>(0hf), wrap_len_index_end) node _use_this_queue_T_95 = and(_use_this_queue_T_93, _use_this_queue_T_94) node use_this_queue_15 = mux(wrapped, _use_this_queue_T_92, _use_this_queue_T_95) node _T_2151 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2152 = and(_T_2151, use_this_queue_15) node _T_2153 = and(_T_2152, all_queues_ready) connect Queue64_UInt8_15.io.enq.valid, _T_2153 node _use_this_queue_T_96 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_97 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_98 = or(_use_this_queue_T_96, _use_this_queue_T_97) node _use_this_queue_T_99 = geq(UInt<5>(0h10), write_start_index) node _use_this_queue_T_100 = lt(UInt<5>(0h10), wrap_len_index_end) node _use_this_queue_T_101 = and(_use_this_queue_T_99, _use_this_queue_T_100) node use_this_queue_16 = mux(wrapped, _use_this_queue_T_98, _use_this_queue_T_101) node _T_2154 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2155 = and(_T_2154, use_this_queue_16) node _T_2156 = and(_T_2155, all_queues_ready) connect Queue64_UInt8_16.io.enq.valid, _T_2156 node _use_this_queue_T_102 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_103 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_104 = or(_use_this_queue_T_102, _use_this_queue_T_103) node _use_this_queue_T_105 = geq(UInt<5>(0h11), write_start_index) node _use_this_queue_T_106 = lt(UInt<5>(0h11), wrap_len_index_end) node _use_this_queue_T_107 = and(_use_this_queue_T_105, _use_this_queue_T_106) node use_this_queue_17 = mux(wrapped, _use_this_queue_T_104, _use_this_queue_T_107) node _T_2157 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2158 = and(_T_2157, use_this_queue_17) node _T_2159 = and(_T_2158, all_queues_ready) connect Queue64_UInt8_17.io.enq.valid, _T_2159 node _use_this_queue_T_108 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_109 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_110 = or(_use_this_queue_T_108, _use_this_queue_T_109) node _use_this_queue_T_111 = geq(UInt<5>(0h12), write_start_index) node _use_this_queue_T_112 = lt(UInt<5>(0h12), wrap_len_index_end) node _use_this_queue_T_113 = and(_use_this_queue_T_111, _use_this_queue_T_112) node use_this_queue_18 = mux(wrapped, _use_this_queue_T_110, _use_this_queue_T_113) node _T_2160 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2161 = and(_T_2160, use_this_queue_18) node _T_2162 = and(_T_2161, all_queues_ready) connect Queue64_UInt8_18.io.enq.valid, _T_2162 node _use_this_queue_T_114 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_115 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_116 = or(_use_this_queue_T_114, _use_this_queue_T_115) node _use_this_queue_T_117 = geq(UInt<5>(0h13), write_start_index) node _use_this_queue_T_118 = lt(UInt<5>(0h13), wrap_len_index_end) node _use_this_queue_T_119 = and(_use_this_queue_T_117, _use_this_queue_T_118) node use_this_queue_19 = mux(wrapped, _use_this_queue_T_116, _use_this_queue_T_119) node _T_2163 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2164 = and(_T_2163, use_this_queue_19) node _T_2165 = and(_T_2164, all_queues_ready) connect Queue64_UInt8_19.io.enq.valid, _T_2165 node _use_this_queue_T_120 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_121 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_122 = or(_use_this_queue_T_120, _use_this_queue_T_121) node _use_this_queue_T_123 = geq(UInt<5>(0h14), write_start_index) node _use_this_queue_T_124 = lt(UInt<5>(0h14), wrap_len_index_end) node _use_this_queue_T_125 = and(_use_this_queue_T_123, _use_this_queue_T_124) node use_this_queue_20 = mux(wrapped, _use_this_queue_T_122, _use_this_queue_T_125) node _T_2166 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2167 = and(_T_2166, use_this_queue_20) node _T_2168 = and(_T_2167, all_queues_ready) connect Queue64_UInt8_20.io.enq.valid, _T_2168 node _use_this_queue_T_126 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_127 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_128 = or(_use_this_queue_T_126, _use_this_queue_T_127) node _use_this_queue_T_129 = geq(UInt<5>(0h15), write_start_index) node _use_this_queue_T_130 = lt(UInt<5>(0h15), wrap_len_index_end) node _use_this_queue_T_131 = and(_use_this_queue_T_129, _use_this_queue_T_130) node use_this_queue_21 = mux(wrapped, _use_this_queue_T_128, _use_this_queue_T_131) node _T_2169 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2170 = and(_T_2169, use_this_queue_21) node _T_2171 = and(_T_2170, all_queues_ready) connect Queue64_UInt8_21.io.enq.valid, _T_2171 node _use_this_queue_T_132 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_133 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_134 = or(_use_this_queue_T_132, _use_this_queue_T_133) node _use_this_queue_T_135 = geq(UInt<5>(0h16), write_start_index) node _use_this_queue_T_136 = lt(UInt<5>(0h16), wrap_len_index_end) node _use_this_queue_T_137 = and(_use_this_queue_T_135, _use_this_queue_T_136) node use_this_queue_22 = mux(wrapped, _use_this_queue_T_134, _use_this_queue_T_137) node _T_2172 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2173 = and(_T_2172, use_this_queue_22) node _T_2174 = and(_T_2173, all_queues_ready) connect Queue64_UInt8_22.io.enq.valid, _T_2174 node _use_this_queue_T_138 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_139 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_140 = or(_use_this_queue_T_138, _use_this_queue_T_139) node _use_this_queue_T_141 = geq(UInt<5>(0h17), write_start_index) node _use_this_queue_T_142 = lt(UInt<5>(0h17), wrap_len_index_end) node _use_this_queue_T_143 = and(_use_this_queue_T_141, _use_this_queue_T_142) node use_this_queue_23 = mux(wrapped, _use_this_queue_T_140, _use_this_queue_T_143) node _T_2175 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2176 = and(_T_2175, use_this_queue_23) node _T_2177 = and(_T_2176, all_queues_ready) connect Queue64_UInt8_23.io.enq.valid, _T_2177 node _use_this_queue_T_144 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_145 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_146 = or(_use_this_queue_T_144, _use_this_queue_T_145) node _use_this_queue_T_147 = geq(UInt<5>(0h18), write_start_index) node _use_this_queue_T_148 = lt(UInt<5>(0h18), wrap_len_index_end) node _use_this_queue_T_149 = and(_use_this_queue_T_147, _use_this_queue_T_148) node use_this_queue_24 = mux(wrapped, _use_this_queue_T_146, _use_this_queue_T_149) node _T_2178 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2179 = and(_T_2178, use_this_queue_24) node _T_2180 = and(_T_2179, all_queues_ready) connect Queue64_UInt8_24.io.enq.valid, _T_2180 node _use_this_queue_T_150 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_151 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_152 = or(_use_this_queue_T_150, _use_this_queue_T_151) node _use_this_queue_T_153 = geq(UInt<5>(0h19), write_start_index) node _use_this_queue_T_154 = lt(UInt<5>(0h19), wrap_len_index_end) node _use_this_queue_T_155 = and(_use_this_queue_T_153, _use_this_queue_T_154) node use_this_queue_25 = mux(wrapped, _use_this_queue_T_152, _use_this_queue_T_155) node _T_2181 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2182 = and(_T_2181, use_this_queue_25) node _T_2183 = and(_T_2182, all_queues_ready) connect Queue64_UInt8_25.io.enq.valid, _T_2183 node _use_this_queue_T_156 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_157 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_158 = or(_use_this_queue_T_156, _use_this_queue_T_157) node _use_this_queue_T_159 = geq(UInt<5>(0h1a), write_start_index) node _use_this_queue_T_160 = lt(UInt<5>(0h1a), wrap_len_index_end) node _use_this_queue_T_161 = and(_use_this_queue_T_159, _use_this_queue_T_160) node use_this_queue_26 = mux(wrapped, _use_this_queue_T_158, _use_this_queue_T_161) node _T_2184 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2185 = and(_T_2184, use_this_queue_26) node _T_2186 = and(_T_2185, all_queues_ready) connect Queue64_UInt8_26.io.enq.valid, _T_2186 node _use_this_queue_T_162 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_163 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_164 = or(_use_this_queue_T_162, _use_this_queue_T_163) node _use_this_queue_T_165 = geq(UInt<5>(0h1b), write_start_index) node _use_this_queue_T_166 = lt(UInt<5>(0h1b), wrap_len_index_end) node _use_this_queue_T_167 = and(_use_this_queue_T_165, _use_this_queue_T_166) node use_this_queue_27 = mux(wrapped, _use_this_queue_T_164, _use_this_queue_T_167) node _T_2187 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2188 = and(_T_2187, use_this_queue_27) node _T_2189 = and(_T_2188, all_queues_ready) connect Queue64_UInt8_27.io.enq.valid, _T_2189 node _use_this_queue_T_168 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_169 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_170 = or(_use_this_queue_T_168, _use_this_queue_T_169) node _use_this_queue_T_171 = geq(UInt<5>(0h1c), write_start_index) node _use_this_queue_T_172 = lt(UInt<5>(0h1c), wrap_len_index_end) node _use_this_queue_T_173 = and(_use_this_queue_T_171, _use_this_queue_T_172) node use_this_queue_28 = mux(wrapped, _use_this_queue_T_170, _use_this_queue_T_173) node _T_2190 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2191 = and(_T_2190, use_this_queue_28) node _T_2192 = and(_T_2191, all_queues_ready) connect Queue64_UInt8_28.io.enq.valid, _T_2192 node _use_this_queue_T_174 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_175 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_176 = or(_use_this_queue_T_174, _use_this_queue_T_175) node _use_this_queue_T_177 = geq(UInt<5>(0h1d), write_start_index) node _use_this_queue_T_178 = lt(UInt<5>(0h1d), wrap_len_index_end) node _use_this_queue_T_179 = and(_use_this_queue_T_177, _use_this_queue_T_178) node use_this_queue_29 = mux(wrapped, _use_this_queue_T_176, _use_this_queue_T_179) node _T_2193 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2194 = and(_T_2193, use_this_queue_29) node _T_2195 = and(_T_2194, all_queues_ready) connect Queue64_UInt8_29.io.enq.valid, _T_2195 node _use_this_queue_T_180 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_181 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_182 = or(_use_this_queue_T_180, _use_this_queue_T_181) node _use_this_queue_T_183 = geq(UInt<5>(0h1e), write_start_index) node _use_this_queue_T_184 = lt(UInt<5>(0h1e), wrap_len_index_end) node _use_this_queue_T_185 = and(_use_this_queue_T_183, _use_this_queue_T_184) node use_this_queue_30 = mux(wrapped, _use_this_queue_T_182, _use_this_queue_T_185) node _T_2196 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2197 = and(_T_2196, use_this_queue_30) node _T_2198 = and(_T_2197, all_queues_ready) connect Queue64_UInt8_30.io.enq.valid, _T_2198 node _use_this_queue_T_186 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_187 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_188 = or(_use_this_queue_T_186, _use_this_queue_T_187) node _use_this_queue_T_189 = geq(UInt<5>(0h1f), write_start_index) node _use_this_queue_T_190 = lt(UInt<5>(0h1f), wrap_len_index_end) node _use_this_queue_T_191 = and(_use_this_queue_T_189, _use_this_queue_T_190) node use_this_queue_31 = mux(wrapped, _use_this_queue_T_188, _use_this_queue_T_191) node _T_2199 = and(io.l2helperUser.resp.valid, load_info_queue.io.deq.valid) node _T_2200 = and(_T_2199, use_this_queue_31) node _T_2201 = and(_T_2200, all_queues_ready) connect Queue64_UInt8_31.io.enq.valid, _T_2201 when Queue64_UInt8.io.deq.valid : regreset loginfo_cycles_12 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_24 = add(loginfo_cycles_12, UInt<1>(0h1)) node _loginfo_cycles_T_25 = tail(_loginfo_cycles_T_24, 1) connect loginfo_cycles_12, _loginfo_cycles_T_25 node _T_2202 = asUInt(reset) node _T_2203 = eq(_T_2202, UInt<1>(0h0)) when _T_2203 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_12) : printf_24 node _T_2204 = asUInt(reset) node _T_2205 = eq(_T_2204, UInt<1>(0h0)) when _T_2205 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<1>(0h0), Queue64_UInt8.io.deq.bits) : printf_25 when Queue64_UInt8_1.io.deq.valid : regreset loginfo_cycles_13 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_26 = add(loginfo_cycles_13, UInt<1>(0h1)) node _loginfo_cycles_T_27 = tail(_loginfo_cycles_T_26, 1) connect loginfo_cycles_13, _loginfo_cycles_T_27 node _T_2206 = asUInt(reset) node _T_2207 = eq(_T_2206, UInt<1>(0h0)) when _T_2207 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_13) : printf_26 node _T_2208 = asUInt(reset) node _T_2209 = eq(_T_2208, UInt<1>(0h0)) when _T_2209 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<1>(0h1), Queue64_UInt8_1.io.deq.bits) : printf_27 when Queue64_UInt8_2.io.deq.valid : regreset loginfo_cycles_14 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_28 = add(loginfo_cycles_14, UInt<1>(0h1)) node _loginfo_cycles_T_29 = tail(_loginfo_cycles_T_28, 1) connect loginfo_cycles_14, _loginfo_cycles_T_29 node _T_2210 = asUInt(reset) node _T_2211 = eq(_T_2210, UInt<1>(0h0)) when _T_2211 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_14) : printf_28 node _T_2212 = asUInt(reset) node _T_2213 = eq(_T_2212, UInt<1>(0h0)) when _T_2213 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<2>(0h2), Queue64_UInt8_2.io.deq.bits) : printf_29 when Queue64_UInt8_3.io.deq.valid : regreset loginfo_cycles_15 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_30 = add(loginfo_cycles_15, UInt<1>(0h1)) node _loginfo_cycles_T_31 = tail(_loginfo_cycles_T_30, 1) connect loginfo_cycles_15, _loginfo_cycles_T_31 node _T_2214 = asUInt(reset) node _T_2215 = eq(_T_2214, UInt<1>(0h0)) when _T_2215 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_15) : printf_30 node _T_2216 = asUInt(reset) node _T_2217 = eq(_T_2216, UInt<1>(0h0)) when _T_2217 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<2>(0h3), Queue64_UInt8_3.io.deq.bits) : printf_31 when Queue64_UInt8_4.io.deq.valid : regreset loginfo_cycles_16 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_32 = add(loginfo_cycles_16, UInt<1>(0h1)) node _loginfo_cycles_T_33 = tail(_loginfo_cycles_T_32, 1) connect loginfo_cycles_16, _loginfo_cycles_T_33 node _T_2218 = asUInt(reset) node _T_2219 = eq(_T_2218, UInt<1>(0h0)) when _T_2219 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_16) : printf_32 node _T_2220 = asUInt(reset) node _T_2221 = eq(_T_2220, UInt<1>(0h0)) when _T_2221 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h4), Queue64_UInt8_4.io.deq.bits) : printf_33 when Queue64_UInt8_5.io.deq.valid : regreset loginfo_cycles_17 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_34 = add(loginfo_cycles_17, UInt<1>(0h1)) node _loginfo_cycles_T_35 = tail(_loginfo_cycles_T_34, 1) connect loginfo_cycles_17, _loginfo_cycles_T_35 node _T_2222 = asUInt(reset) node _T_2223 = eq(_T_2222, UInt<1>(0h0)) when _T_2223 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_17) : printf_34 node _T_2224 = asUInt(reset) node _T_2225 = eq(_T_2224, UInt<1>(0h0)) when _T_2225 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h5), Queue64_UInt8_5.io.deq.bits) : printf_35 when Queue64_UInt8_6.io.deq.valid : regreset loginfo_cycles_18 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_36 = add(loginfo_cycles_18, UInt<1>(0h1)) node _loginfo_cycles_T_37 = tail(_loginfo_cycles_T_36, 1) connect loginfo_cycles_18, _loginfo_cycles_T_37 node _T_2226 = asUInt(reset) node _T_2227 = eq(_T_2226, UInt<1>(0h0)) when _T_2227 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_18) : printf_36 node _T_2228 = asUInt(reset) node _T_2229 = eq(_T_2228, UInt<1>(0h0)) when _T_2229 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h6), Queue64_UInt8_6.io.deq.bits) : printf_37 when Queue64_UInt8_7.io.deq.valid : regreset loginfo_cycles_19 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_38 = add(loginfo_cycles_19, UInt<1>(0h1)) node _loginfo_cycles_T_39 = tail(_loginfo_cycles_T_38, 1) connect loginfo_cycles_19, _loginfo_cycles_T_39 node _T_2230 = asUInt(reset) node _T_2231 = eq(_T_2230, UInt<1>(0h0)) when _T_2231 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_19) : printf_38 node _T_2232 = asUInt(reset) node _T_2233 = eq(_T_2232, UInt<1>(0h0)) when _T_2233 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<3>(0h7), Queue64_UInt8_7.io.deq.bits) : printf_39 when Queue64_UInt8_8.io.deq.valid : regreset loginfo_cycles_20 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_40 = add(loginfo_cycles_20, UInt<1>(0h1)) node _loginfo_cycles_T_41 = tail(_loginfo_cycles_T_40, 1) connect loginfo_cycles_20, _loginfo_cycles_T_41 node _T_2234 = asUInt(reset) node _T_2235 = eq(_T_2234, UInt<1>(0h0)) when _T_2235 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_20) : printf_40 node _T_2236 = asUInt(reset) node _T_2237 = eq(_T_2236, UInt<1>(0h0)) when _T_2237 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0h8), Queue64_UInt8_8.io.deq.bits) : printf_41 when Queue64_UInt8_9.io.deq.valid : regreset loginfo_cycles_21 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_42 = add(loginfo_cycles_21, UInt<1>(0h1)) node _loginfo_cycles_T_43 = tail(_loginfo_cycles_T_42, 1) connect loginfo_cycles_21, _loginfo_cycles_T_43 node _T_2238 = asUInt(reset) node _T_2239 = eq(_T_2238, UInt<1>(0h0)) when _T_2239 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_21) : printf_42 node _T_2240 = asUInt(reset) node _T_2241 = eq(_T_2240, UInt<1>(0h0)) when _T_2241 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0h9), Queue64_UInt8_9.io.deq.bits) : printf_43 when Queue64_UInt8_10.io.deq.valid : regreset loginfo_cycles_22 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_44 = add(loginfo_cycles_22, UInt<1>(0h1)) node _loginfo_cycles_T_45 = tail(_loginfo_cycles_T_44, 1) connect loginfo_cycles_22, _loginfo_cycles_T_45 node _T_2242 = asUInt(reset) node _T_2243 = eq(_T_2242, UInt<1>(0h0)) when _T_2243 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_22) : printf_44 node _T_2244 = asUInt(reset) node _T_2245 = eq(_T_2244, UInt<1>(0h0)) when _T_2245 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0ha), Queue64_UInt8_10.io.deq.bits) : printf_45 when Queue64_UInt8_11.io.deq.valid : regreset loginfo_cycles_23 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_46 = add(loginfo_cycles_23, UInt<1>(0h1)) node _loginfo_cycles_T_47 = tail(_loginfo_cycles_T_46, 1) connect loginfo_cycles_23, _loginfo_cycles_T_47 node _T_2246 = asUInt(reset) node _T_2247 = eq(_T_2246, UInt<1>(0h0)) when _T_2247 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_23) : printf_46 node _T_2248 = asUInt(reset) node _T_2249 = eq(_T_2248, UInt<1>(0h0)) when _T_2249 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hb), Queue64_UInt8_11.io.deq.bits) : printf_47 when Queue64_UInt8_12.io.deq.valid : regreset loginfo_cycles_24 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_48 = add(loginfo_cycles_24, UInt<1>(0h1)) node _loginfo_cycles_T_49 = tail(_loginfo_cycles_T_48, 1) connect loginfo_cycles_24, _loginfo_cycles_T_49 node _T_2250 = asUInt(reset) node _T_2251 = eq(_T_2250, UInt<1>(0h0)) when _T_2251 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_24) : printf_48 node _T_2252 = asUInt(reset) node _T_2253 = eq(_T_2252, UInt<1>(0h0)) when _T_2253 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hc), Queue64_UInt8_12.io.deq.bits) : printf_49 when Queue64_UInt8_13.io.deq.valid : regreset loginfo_cycles_25 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_50 = add(loginfo_cycles_25, UInt<1>(0h1)) node _loginfo_cycles_T_51 = tail(_loginfo_cycles_T_50, 1) connect loginfo_cycles_25, _loginfo_cycles_T_51 node _T_2254 = asUInt(reset) node _T_2255 = eq(_T_2254, UInt<1>(0h0)) when _T_2255 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_25) : printf_50 node _T_2256 = asUInt(reset) node _T_2257 = eq(_T_2256, UInt<1>(0h0)) when _T_2257 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hd), Queue64_UInt8_13.io.deq.bits) : printf_51 when Queue64_UInt8_14.io.deq.valid : regreset loginfo_cycles_26 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_52 = add(loginfo_cycles_26, UInt<1>(0h1)) node _loginfo_cycles_T_53 = tail(_loginfo_cycles_T_52, 1) connect loginfo_cycles_26, _loginfo_cycles_T_53 node _T_2258 = asUInt(reset) node _T_2259 = eq(_T_2258, UInt<1>(0h0)) when _T_2259 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_26) : printf_52 node _T_2260 = asUInt(reset) node _T_2261 = eq(_T_2260, UInt<1>(0h0)) when _T_2261 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0he), Queue64_UInt8_14.io.deq.bits) : printf_53 when Queue64_UInt8_15.io.deq.valid : regreset loginfo_cycles_27 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_54 = add(loginfo_cycles_27, UInt<1>(0h1)) node _loginfo_cycles_T_55 = tail(_loginfo_cycles_T_54, 1) connect loginfo_cycles_27, _loginfo_cycles_T_55 node _T_2262 = asUInt(reset) node _T_2263 = eq(_T_2262, UInt<1>(0h0)) when _T_2263 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_27) : printf_54 node _T_2264 = asUInt(reset) node _T_2265 = eq(_T_2264, UInt<1>(0h0)) when _T_2265 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<4>(0hf), Queue64_UInt8_15.io.deq.bits) : printf_55 when Queue64_UInt8_16.io.deq.valid : regreset loginfo_cycles_28 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_56 = add(loginfo_cycles_28, UInt<1>(0h1)) node _loginfo_cycles_T_57 = tail(_loginfo_cycles_T_56, 1) connect loginfo_cycles_28, _loginfo_cycles_T_57 node _T_2266 = asUInt(reset) node _T_2267 = eq(_T_2266, UInt<1>(0h0)) when _T_2267 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_28) : printf_56 node _T_2268 = asUInt(reset) node _T_2269 = eq(_T_2268, UInt<1>(0h0)) when _T_2269 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h10), Queue64_UInt8_16.io.deq.bits) : printf_57 when Queue64_UInt8_17.io.deq.valid : regreset loginfo_cycles_29 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_58 = add(loginfo_cycles_29, UInt<1>(0h1)) node _loginfo_cycles_T_59 = tail(_loginfo_cycles_T_58, 1) connect loginfo_cycles_29, _loginfo_cycles_T_59 node _T_2270 = asUInt(reset) node _T_2271 = eq(_T_2270, UInt<1>(0h0)) when _T_2271 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_29) : printf_58 node _T_2272 = asUInt(reset) node _T_2273 = eq(_T_2272, UInt<1>(0h0)) when _T_2273 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h11), Queue64_UInt8_17.io.deq.bits) : printf_59 when Queue64_UInt8_18.io.deq.valid : regreset loginfo_cycles_30 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_60 = add(loginfo_cycles_30, UInt<1>(0h1)) node _loginfo_cycles_T_61 = tail(_loginfo_cycles_T_60, 1) connect loginfo_cycles_30, _loginfo_cycles_T_61 node _T_2274 = asUInt(reset) node _T_2275 = eq(_T_2274, UInt<1>(0h0)) when _T_2275 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_30) : printf_60 node _T_2276 = asUInt(reset) node _T_2277 = eq(_T_2276, UInt<1>(0h0)) when _T_2277 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h12), Queue64_UInt8_18.io.deq.bits) : printf_61 when Queue64_UInt8_19.io.deq.valid : regreset loginfo_cycles_31 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_62 = add(loginfo_cycles_31, UInt<1>(0h1)) node _loginfo_cycles_T_63 = tail(_loginfo_cycles_T_62, 1) connect loginfo_cycles_31, _loginfo_cycles_T_63 node _T_2278 = asUInt(reset) node _T_2279 = eq(_T_2278, UInt<1>(0h0)) when _T_2279 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_31) : printf_62 node _T_2280 = asUInt(reset) node _T_2281 = eq(_T_2280, UInt<1>(0h0)) when _T_2281 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h13), Queue64_UInt8_19.io.deq.bits) : printf_63 when Queue64_UInt8_20.io.deq.valid : regreset loginfo_cycles_32 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_64 = add(loginfo_cycles_32, UInt<1>(0h1)) node _loginfo_cycles_T_65 = tail(_loginfo_cycles_T_64, 1) connect loginfo_cycles_32, _loginfo_cycles_T_65 node _T_2282 = asUInt(reset) node _T_2283 = eq(_T_2282, UInt<1>(0h0)) when _T_2283 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_32) : printf_64 node _T_2284 = asUInt(reset) node _T_2285 = eq(_T_2284, UInt<1>(0h0)) when _T_2285 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h14), Queue64_UInt8_20.io.deq.bits) : printf_65 when Queue64_UInt8_21.io.deq.valid : regreset loginfo_cycles_33 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_66 = add(loginfo_cycles_33, UInt<1>(0h1)) node _loginfo_cycles_T_67 = tail(_loginfo_cycles_T_66, 1) connect loginfo_cycles_33, _loginfo_cycles_T_67 node _T_2286 = asUInt(reset) node _T_2287 = eq(_T_2286, UInt<1>(0h0)) when _T_2287 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_33) : printf_66 node _T_2288 = asUInt(reset) node _T_2289 = eq(_T_2288, UInt<1>(0h0)) when _T_2289 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h15), Queue64_UInt8_21.io.deq.bits) : printf_67 when Queue64_UInt8_22.io.deq.valid : regreset loginfo_cycles_34 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_68 = add(loginfo_cycles_34, UInt<1>(0h1)) node _loginfo_cycles_T_69 = tail(_loginfo_cycles_T_68, 1) connect loginfo_cycles_34, _loginfo_cycles_T_69 node _T_2290 = asUInt(reset) node _T_2291 = eq(_T_2290, UInt<1>(0h0)) when _T_2291 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_34) : printf_68 node _T_2292 = asUInt(reset) node _T_2293 = eq(_T_2292, UInt<1>(0h0)) when _T_2293 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h16), Queue64_UInt8_22.io.deq.bits) : printf_69 when Queue64_UInt8_23.io.deq.valid : regreset loginfo_cycles_35 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_70 = add(loginfo_cycles_35, UInt<1>(0h1)) node _loginfo_cycles_T_71 = tail(_loginfo_cycles_T_70, 1) connect loginfo_cycles_35, _loginfo_cycles_T_71 node _T_2294 = asUInt(reset) node _T_2295 = eq(_T_2294, UInt<1>(0h0)) when _T_2295 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_35) : printf_70 node _T_2296 = asUInt(reset) node _T_2297 = eq(_T_2296, UInt<1>(0h0)) when _T_2297 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h17), Queue64_UInt8_23.io.deq.bits) : printf_71 when Queue64_UInt8_24.io.deq.valid : regreset loginfo_cycles_36 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_72 = add(loginfo_cycles_36, UInt<1>(0h1)) node _loginfo_cycles_T_73 = tail(_loginfo_cycles_T_72, 1) connect loginfo_cycles_36, _loginfo_cycles_T_73 node _T_2298 = asUInt(reset) node _T_2299 = eq(_T_2298, UInt<1>(0h0)) when _T_2299 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_36) : printf_72 node _T_2300 = asUInt(reset) node _T_2301 = eq(_T_2300, UInt<1>(0h0)) when _T_2301 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h18), Queue64_UInt8_24.io.deq.bits) : printf_73 when Queue64_UInt8_25.io.deq.valid : regreset loginfo_cycles_37 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_74 = add(loginfo_cycles_37, UInt<1>(0h1)) node _loginfo_cycles_T_75 = tail(_loginfo_cycles_T_74, 1) connect loginfo_cycles_37, _loginfo_cycles_T_75 node _T_2302 = asUInt(reset) node _T_2303 = eq(_T_2302, UInt<1>(0h0)) when _T_2303 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_37) : printf_74 node _T_2304 = asUInt(reset) node _T_2305 = eq(_T_2304, UInt<1>(0h0)) when _T_2305 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h19), Queue64_UInt8_25.io.deq.bits) : printf_75 when Queue64_UInt8_26.io.deq.valid : regreset loginfo_cycles_38 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_76 = add(loginfo_cycles_38, UInt<1>(0h1)) node _loginfo_cycles_T_77 = tail(_loginfo_cycles_T_76, 1) connect loginfo_cycles_38, _loginfo_cycles_T_77 node _T_2306 = asUInt(reset) node _T_2307 = eq(_T_2306, UInt<1>(0h0)) when _T_2307 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_38) : printf_76 node _T_2308 = asUInt(reset) node _T_2309 = eq(_T_2308, UInt<1>(0h0)) when _T_2309 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1a), Queue64_UInt8_26.io.deq.bits) : printf_77 when Queue64_UInt8_27.io.deq.valid : regreset loginfo_cycles_39 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_78 = add(loginfo_cycles_39, UInt<1>(0h1)) node _loginfo_cycles_T_79 = tail(_loginfo_cycles_T_78, 1) connect loginfo_cycles_39, _loginfo_cycles_T_79 node _T_2310 = asUInt(reset) node _T_2311 = eq(_T_2310, UInt<1>(0h0)) when _T_2311 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_39) : printf_78 node _T_2312 = asUInt(reset) node _T_2313 = eq(_T_2312, UInt<1>(0h0)) when _T_2313 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1b), Queue64_UInt8_27.io.deq.bits) : printf_79 when Queue64_UInt8_28.io.deq.valid : regreset loginfo_cycles_40 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_80 = add(loginfo_cycles_40, UInt<1>(0h1)) node _loginfo_cycles_T_81 = tail(_loginfo_cycles_T_80, 1) connect loginfo_cycles_40, _loginfo_cycles_T_81 node _T_2314 = asUInt(reset) node _T_2315 = eq(_T_2314, UInt<1>(0h0)) when _T_2315 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_40) : printf_80 node _T_2316 = asUInt(reset) node _T_2317 = eq(_T_2316, UInt<1>(0h0)) when _T_2317 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1c), Queue64_UInt8_28.io.deq.bits) : printf_81 when Queue64_UInt8_29.io.deq.valid : regreset loginfo_cycles_41 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_82 = add(loginfo_cycles_41, UInt<1>(0h1)) node _loginfo_cycles_T_83 = tail(_loginfo_cycles_T_82, 1) connect loginfo_cycles_41, _loginfo_cycles_T_83 node _T_2318 = asUInt(reset) node _T_2319 = eq(_T_2318, UInt<1>(0h0)) when _T_2319 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_41) : printf_82 node _T_2320 = asUInt(reset) node _T_2321 = eq(_T_2320, UInt<1>(0h0)) when _T_2321 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1d), Queue64_UInt8_29.io.deq.bits) : printf_83 when Queue64_UInt8_30.io.deq.valid : regreset loginfo_cycles_42 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_84 = add(loginfo_cycles_42, UInt<1>(0h1)) node _loginfo_cycles_T_85 = tail(_loginfo_cycles_T_84, 1) connect loginfo_cycles_42, _loginfo_cycles_T_85 node _T_2322 = asUInt(reset) node _T_2323 = eq(_T_2322, UInt<1>(0h0)) when _T_2323 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_42) : printf_84 node _T_2324 = asUInt(reset) node _T_2325 = eq(_T_2324, UInt<1>(0h0)) when _T_2325 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1e), Queue64_UInt8_30.io.deq.bits) : printf_85 when Queue64_UInt8_31.io.deq.valid : regreset loginfo_cycles_43 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_86 = add(loginfo_cycles_43, UInt<1>(0h1)) node _loginfo_cycles_T_87 = tail(_loginfo_cycles_T_86, 1) connect loginfo_cycles_43, _loginfo_cycles_T_87 node _T_2326 = asUInt(reset) node _T_2327 = eq(_T_2326, UInt<1>(0h0)) when _T_2327 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_43) : printf_86 node _T_2328 = asUInt(reset) node _T_2329 = eq(_T_2328, UInt<1>(0h0)) when _T_2329 : printf(clock, UInt<1>(0h1), "queueind %d, val %x\n", UInt<5>(0h1f), Queue64_UInt8_31.io.deq.bits) : printf_87 regreset read_start_index : UInt<6>, clock, reset, UInt<6>(0h0) regreset len_already_consumed : UInt<64>, clock, reset, UInt<64>(0h0) wire remapVecData : UInt<8>[32] wire remapVecValids : UInt<1>[32] wire remapVecReadys : UInt<1>[32] connect remapVecData[0], UInt<1>(0h0) connect remapVecValids[0], UInt<1>(0h0) connect Queue64_UInt8.io.deq.ready, UInt<1>(0h0) connect remapVecData[1], UInt<1>(0h0) connect remapVecValids[1], UInt<1>(0h0) connect Queue64_UInt8_1.io.deq.ready, UInt<1>(0h0) connect remapVecData[2], UInt<1>(0h0) connect remapVecValids[2], UInt<1>(0h0) connect Queue64_UInt8_2.io.deq.ready, UInt<1>(0h0) connect remapVecData[3], UInt<1>(0h0) connect remapVecValids[3], UInt<1>(0h0) connect Queue64_UInt8_3.io.deq.ready, UInt<1>(0h0) connect remapVecData[4], UInt<1>(0h0) connect remapVecValids[4], UInt<1>(0h0) connect Queue64_UInt8_4.io.deq.ready, UInt<1>(0h0) connect remapVecData[5], UInt<1>(0h0) connect remapVecValids[5], UInt<1>(0h0) connect Queue64_UInt8_5.io.deq.ready, UInt<1>(0h0) connect remapVecData[6], UInt<1>(0h0) connect remapVecValids[6], UInt<1>(0h0) connect Queue64_UInt8_6.io.deq.ready, UInt<1>(0h0) connect remapVecData[7], UInt<1>(0h0) connect remapVecValids[7], UInt<1>(0h0) connect Queue64_UInt8_7.io.deq.ready, UInt<1>(0h0) connect remapVecData[8], UInt<1>(0h0) connect remapVecValids[8], UInt<1>(0h0) connect Queue64_UInt8_8.io.deq.ready, UInt<1>(0h0) connect remapVecData[9], UInt<1>(0h0) connect remapVecValids[9], UInt<1>(0h0) connect Queue64_UInt8_9.io.deq.ready, UInt<1>(0h0) connect remapVecData[10], UInt<1>(0h0) connect remapVecValids[10], UInt<1>(0h0) connect Queue64_UInt8_10.io.deq.ready, UInt<1>(0h0) connect remapVecData[11], UInt<1>(0h0) connect remapVecValids[11], UInt<1>(0h0) connect Queue64_UInt8_11.io.deq.ready, UInt<1>(0h0) connect remapVecData[12], UInt<1>(0h0) connect remapVecValids[12], UInt<1>(0h0) connect Queue64_UInt8_12.io.deq.ready, UInt<1>(0h0) connect remapVecData[13], UInt<1>(0h0) connect remapVecValids[13], UInt<1>(0h0) connect Queue64_UInt8_13.io.deq.ready, UInt<1>(0h0) connect remapVecData[14], UInt<1>(0h0) connect remapVecValids[14], UInt<1>(0h0) connect Queue64_UInt8_14.io.deq.ready, UInt<1>(0h0) connect remapVecData[15], UInt<1>(0h0) connect remapVecValids[15], UInt<1>(0h0) connect Queue64_UInt8_15.io.deq.ready, UInt<1>(0h0) connect remapVecData[16], UInt<1>(0h0) connect remapVecValids[16], UInt<1>(0h0) connect Queue64_UInt8_16.io.deq.ready, UInt<1>(0h0) connect remapVecData[17], UInt<1>(0h0) connect remapVecValids[17], UInt<1>(0h0) connect Queue64_UInt8_17.io.deq.ready, UInt<1>(0h0) connect remapVecData[18], UInt<1>(0h0) connect remapVecValids[18], UInt<1>(0h0) connect Queue64_UInt8_18.io.deq.ready, UInt<1>(0h0) connect remapVecData[19], UInt<1>(0h0) connect remapVecValids[19], UInt<1>(0h0) connect Queue64_UInt8_19.io.deq.ready, UInt<1>(0h0) connect remapVecData[20], UInt<1>(0h0) connect remapVecValids[20], UInt<1>(0h0) connect Queue64_UInt8_20.io.deq.ready, UInt<1>(0h0) connect remapVecData[21], UInt<1>(0h0) connect remapVecValids[21], UInt<1>(0h0) connect Queue64_UInt8_21.io.deq.ready, UInt<1>(0h0) connect remapVecData[22], UInt<1>(0h0) connect remapVecValids[22], UInt<1>(0h0) connect Queue64_UInt8_22.io.deq.ready, UInt<1>(0h0) connect remapVecData[23], UInt<1>(0h0) connect remapVecValids[23], UInt<1>(0h0) connect Queue64_UInt8_23.io.deq.ready, UInt<1>(0h0) connect remapVecData[24], UInt<1>(0h0) connect remapVecValids[24], UInt<1>(0h0) connect Queue64_UInt8_24.io.deq.ready, UInt<1>(0h0) connect remapVecData[25], UInt<1>(0h0) connect remapVecValids[25], UInt<1>(0h0) connect Queue64_UInt8_25.io.deq.ready, UInt<1>(0h0) connect remapVecData[26], UInt<1>(0h0) connect remapVecValids[26], UInt<1>(0h0) connect Queue64_UInt8_26.io.deq.ready, UInt<1>(0h0) connect remapVecData[27], UInt<1>(0h0) connect remapVecValids[27], UInt<1>(0h0) connect Queue64_UInt8_27.io.deq.ready, UInt<1>(0h0) connect remapVecData[28], UInt<1>(0h0) connect remapVecValids[28], UInt<1>(0h0) connect Queue64_UInt8_28.io.deq.ready, UInt<1>(0h0) connect remapVecData[29], UInt<1>(0h0) connect remapVecValids[29], UInt<1>(0h0) connect Queue64_UInt8_29.io.deq.ready, UInt<1>(0h0) connect remapVecData[30], UInt<1>(0h0) connect remapVecValids[30], UInt<1>(0h0) connect Queue64_UInt8_30.io.deq.ready, UInt<1>(0h0) connect remapVecData[31], UInt<1>(0h0) connect remapVecValids[31], UInt<1>(0h0) connect Queue64_UInt8_31.io.deq.ready, UInt<1>(0h0) node _remapindex_T = add(UInt<1>(0h0), read_start_index) node remapindex = rem(_remapindex_T, UInt<6>(0h20)) node _T_2330 = eq(UInt<1>(0h0), remapindex) when _T_2330 : connect remapVecData[0], Queue64_UInt8.io.deq.bits connect remapVecValids[0], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[0] node _T_2331 = eq(UInt<1>(0h1), remapindex) when _T_2331 : connect remapVecData[0], Queue64_UInt8_1.io.deq.bits connect remapVecValids[0], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[0] node _T_2332 = eq(UInt<2>(0h2), remapindex) when _T_2332 : connect remapVecData[0], Queue64_UInt8_2.io.deq.bits connect remapVecValids[0], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[0] node _T_2333 = eq(UInt<2>(0h3), remapindex) when _T_2333 : connect remapVecData[0], Queue64_UInt8_3.io.deq.bits connect remapVecValids[0], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[0] node _T_2334 = eq(UInt<3>(0h4), remapindex) when _T_2334 : connect remapVecData[0], Queue64_UInt8_4.io.deq.bits connect remapVecValids[0], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[0] node _T_2335 = eq(UInt<3>(0h5), remapindex) when _T_2335 : connect remapVecData[0], Queue64_UInt8_5.io.deq.bits connect remapVecValids[0], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[0] node _T_2336 = eq(UInt<3>(0h6), remapindex) when _T_2336 : connect remapVecData[0], Queue64_UInt8_6.io.deq.bits connect remapVecValids[0], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[0] node _T_2337 = eq(UInt<3>(0h7), remapindex) when _T_2337 : connect remapVecData[0], Queue64_UInt8_7.io.deq.bits connect remapVecValids[0], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[0] node _T_2338 = eq(UInt<4>(0h8), remapindex) when _T_2338 : connect remapVecData[0], Queue64_UInt8_8.io.deq.bits connect remapVecValids[0], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[0] node _T_2339 = eq(UInt<4>(0h9), remapindex) when _T_2339 : connect remapVecData[0], Queue64_UInt8_9.io.deq.bits connect remapVecValids[0], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[0] node _T_2340 = eq(UInt<4>(0ha), remapindex) when _T_2340 : connect remapVecData[0], Queue64_UInt8_10.io.deq.bits connect remapVecValids[0], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[0] node _T_2341 = eq(UInt<4>(0hb), remapindex) when _T_2341 : connect remapVecData[0], Queue64_UInt8_11.io.deq.bits connect remapVecValids[0], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[0] node _T_2342 = eq(UInt<4>(0hc), remapindex) when _T_2342 : connect remapVecData[0], Queue64_UInt8_12.io.deq.bits connect remapVecValids[0], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[0] node _T_2343 = eq(UInt<4>(0hd), remapindex) when _T_2343 : connect remapVecData[0], Queue64_UInt8_13.io.deq.bits connect remapVecValids[0], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[0] node _T_2344 = eq(UInt<4>(0he), remapindex) when _T_2344 : connect remapVecData[0], Queue64_UInt8_14.io.deq.bits connect remapVecValids[0], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[0] node _T_2345 = eq(UInt<4>(0hf), remapindex) when _T_2345 : connect remapVecData[0], Queue64_UInt8_15.io.deq.bits connect remapVecValids[0], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[0] node _T_2346 = eq(UInt<5>(0h10), remapindex) when _T_2346 : connect remapVecData[0], Queue64_UInt8_16.io.deq.bits connect remapVecValids[0], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[0] node _T_2347 = eq(UInt<5>(0h11), remapindex) when _T_2347 : connect remapVecData[0], Queue64_UInt8_17.io.deq.bits connect remapVecValids[0], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[0] node _T_2348 = eq(UInt<5>(0h12), remapindex) when _T_2348 : connect remapVecData[0], Queue64_UInt8_18.io.deq.bits connect remapVecValids[0], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[0] node _T_2349 = eq(UInt<5>(0h13), remapindex) when _T_2349 : connect remapVecData[0], Queue64_UInt8_19.io.deq.bits connect remapVecValids[0], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[0] node _T_2350 = eq(UInt<5>(0h14), remapindex) when _T_2350 : connect remapVecData[0], Queue64_UInt8_20.io.deq.bits connect remapVecValids[0], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[0] node _T_2351 = eq(UInt<5>(0h15), remapindex) when _T_2351 : connect remapVecData[0], Queue64_UInt8_21.io.deq.bits connect remapVecValids[0], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[0] node _T_2352 = eq(UInt<5>(0h16), remapindex) when _T_2352 : connect remapVecData[0], Queue64_UInt8_22.io.deq.bits connect remapVecValids[0], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[0] node _T_2353 = eq(UInt<5>(0h17), remapindex) when _T_2353 : connect remapVecData[0], Queue64_UInt8_23.io.deq.bits connect remapVecValids[0], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[0] node _T_2354 = eq(UInt<5>(0h18), remapindex) when _T_2354 : connect remapVecData[0], Queue64_UInt8_24.io.deq.bits connect remapVecValids[0], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[0] node _T_2355 = eq(UInt<5>(0h19), remapindex) when _T_2355 : connect remapVecData[0], Queue64_UInt8_25.io.deq.bits connect remapVecValids[0], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[0] node _T_2356 = eq(UInt<5>(0h1a), remapindex) when _T_2356 : connect remapVecData[0], Queue64_UInt8_26.io.deq.bits connect remapVecValids[0], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[0] node _T_2357 = eq(UInt<5>(0h1b), remapindex) when _T_2357 : connect remapVecData[0], Queue64_UInt8_27.io.deq.bits connect remapVecValids[0], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[0] node _T_2358 = eq(UInt<5>(0h1c), remapindex) when _T_2358 : connect remapVecData[0], Queue64_UInt8_28.io.deq.bits connect remapVecValids[0], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[0] node _T_2359 = eq(UInt<5>(0h1d), remapindex) when _T_2359 : connect remapVecData[0], Queue64_UInt8_29.io.deq.bits connect remapVecValids[0], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[0] node _T_2360 = eq(UInt<5>(0h1e), remapindex) when _T_2360 : connect remapVecData[0], Queue64_UInt8_30.io.deq.bits connect remapVecValids[0], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[0] node _T_2361 = eq(UInt<5>(0h1f), remapindex) when _T_2361 : connect remapVecData[0], Queue64_UInt8_31.io.deq.bits connect remapVecValids[0], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[0] node _remapindex_T_1 = add(UInt<1>(0h1), read_start_index) node remapindex_1 = rem(_remapindex_T_1, UInt<6>(0h20)) node _T_2362 = eq(UInt<1>(0h0), remapindex_1) when _T_2362 : connect remapVecData[1], Queue64_UInt8.io.deq.bits connect remapVecValids[1], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[1] node _T_2363 = eq(UInt<1>(0h1), remapindex_1) when _T_2363 : connect remapVecData[1], Queue64_UInt8_1.io.deq.bits connect remapVecValids[1], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[1] node _T_2364 = eq(UInt<2>(0h2), remapindex_1) when _T_2364 : connect remapVecData[1], Queue64_UInt8_2.io.deq.bits connect remapVecValids[1], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[1] node _T_2365 = eq(UInt<2>(0h3), remapindex_1) when _T_2365 : connect remapVecData[1], Queue64_UInt8_3.io.deq.bits connect remapVecValids[1], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[1] node _T_2366 = eq(UInt<3>(0h4), remapindex_1) when _T_2366 : connect remapVecData[1], Queue64_UInt8_4.io.deq.bits connect remapVecValids[1], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[1] node _T_2367 = eq(UInt<3>(0h5), remapindex_1) when _T_2367 : connect remapVecData[1], Queue64_UInt8_5.io.deq.bits connect remapVecValids[1], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[1] node _T_2368 = eq(UInt<3>(0h6), remapindex_1) when _T_2368 : connect remapVecData[1], Queue64_UInt8_6.io.deq.bits connect remapVecValids[1], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[1] node _T_2369 = eq(UInt<3>(0h7), remapindex_1) when _T_2369 : connect remapVecData[1], Queue64_UInt8_7.io.deq.bits connect remapVecValids[1], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[1] node _T_2370 = eq(UInt<4>(0h8), remapindex_1) when _T_2370 : connect remapVecData[1], Queue64_UInt8_8.io.deq.bits connect remapVecValids[1], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[1] node _T_2371 = eq(UInt<4>(0h9), remapindex_1) when _T_2371 : connect remapVecData[1], Queue64_UInt8_9.io.deq.bits connect remapVecValids[1], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[1] node _T_2372 = eq(UInt<4>(0ha), remapindex_1) when _T_2372 : connect remapVecData[1], Queue64_UInt8_10.io.deq.bits connect remapVecValids[1], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[1] node _T_2373 = eq(UInt<4>(0hb), remapindex_1) when _T_2373 : connect remapVecData[1], Queue64_UInt8_11.io.deq.bits connect remapVecValids[1], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[1] node _T_2374 = eq(UInt<4>(0hc), remapindex_1) when _T_2374 : connect remapVecData[1], Queue64_UInt8_12.io.deq.bits connect remapVecValids[1], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[1] node _T_2375 = eq(UInt<4>(0hd), remapindex_1) when _T_2375 : connect remapVecData[1], Queue64_UInt8_13.io.deq.bits connect remapVecValids[1], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[1] node _T_2376 = eq(UInt<4>(0he), remapindex_1) when _T_2376 : connect remapVecData[1], Queue64_UInt8_14.io.deq.bits connect remapVecValids[1], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[1] node _T_2377 = eq(UInt<4>(0hf), remapindex_1) when _T_2377 : connect remapVecData[1], Queue64_UInt8_15.io.deq.bits connect remapVecValids[1], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[1] node _T_2378 = eq(UInt<5>(0h10), remapindex_1) when _T_2378 : connect remapVecData[1], Queue64_UInt8_16.io.deq.bits connect remapVecValids[1], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[1] node _T_2379 = eq(UInt<5>(0h11), remapindex_1) when _T_2379 : connect remapVecData[1], Queue64_UInt8_17.io.deq.bits connect remapVecValids[1], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[1] node _T_2380 = eq(UInt<5>(0h12), remapindex_1) when _T_2380 : connect remapVecData[1], Queue64_UInt8_18.io.deq.bits connect remapVecValids[1], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[1] node _T_2381 = eq(UInt<5>(0h13), remapindex_1) when _T_2381 : connect remapVecData[1], Queue64_UInt8_19.io.deq.bits connect remapVecValids[1], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[1] node _T_2382 = eq(UInt<5>(0h14), remapindex_1) when _T_2382 : connect remapVecData[1], Queue64_UInt8_20.io.deq.bits connect remapVecValids[1], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[1] node _T_2383 = eq(UInt<5>(0h15), remapindex_1) when _T_2383 : connect remapVecData[1], Queue64_UInt8_21.io.deq.bits connect remapVecValids[1], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[1] node _T_2384 = eq(UInt<5>(0h16), remapindex_1) when _T_2384 : connect remapVecData[1], Queue64_UInt8_22.io.deq.bits connect remapVecValids[1], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[1] node _T_2385 = eq(UInt<5>(0h17), remapindex_1) when _T_2385 : connect remapVecData[1], Queue64_UInt8_23.io.deq.bits connect remapVecValids[1], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[1] node _T_2386 = eq(UInt<5>(0h18), remapindex_1) when _T_2386 : connect remapVecData[1], Queue64_UInt8_24.io.deq.bits connect remapVecValids[1], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[1] node _T_2387 = eq(UInt<5>(0h19), remapindex_1) when _T_2387 : connect remapVecData[1], Queue64_UInt8_25.io.deq.bits connect remapVecValids[1], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[1] node _T_2388 = eq(UInt<5>(0h1a), remapindex_1) when _T_2388 : connect remapVecData[1], Queue64_UInt8_26.io.deq.bits connect remapVecValids[1], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[1] node _T_2389 = eq(UInt<5>(0h1b), remapindex_1) when _T_2389 : connect remapVecData[1], Queue64_UInt8_27.io.deq.bits connect remapVecValids[1], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[1] node _T_2390 = eq(UInt<5>(0h1c), remapindex_1) when _T_2390 : connect remapVecData[1], Queue64_UInt8_28.io.deq.bits connect remapVecValids[1], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[1] node _T_2391 = eq(UInt<5>(0h1d), remapindex_1) when _T_2391 : connect remapVecData[1], Queue64_UInt8_29.io.deq.bits connect remapVecValids[1], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[1] node _T_2392 = eq(UInt<5>(0h1e), remapindex_1) when _T_2392 : connect remapVecData[1], Queue64_UInt8_30.io.deq.bits connect remapVecValids[1], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[1] node _T_2393 = eq(UInt<5>(0h1f), remapindex_1) when _T_2393 : connect remapVecData[1], Queue64_UInt8_31.io.deq.bits connect remapVecValids[1], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[1] node _remapindex_T_2 = add(UInt<2>(0h2), read_start_index) node remapindex_2 = rem(_remapindex_T_2, UInt<6>(0h20)) node _T_2394 = eq(UInt<1>(0h0), remapindex_2) when _T_2394 : connect remapVecData[2], Queue64_UInt8.io.deq.bits connect remapVecValids[2], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[2] node _T_2395 = eq(UInt<1>(0h1), remapindex_2) when _T_2395 : connect remapVecData[2], Queue64_UInt8_1.io.deq.bits connect remapVecValids[2], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[2] node _T_2396 = eq(UInt<2>(0h2), remapindex_2) when _T_2396 : connect remapVecData[2], Queue64_UInt8_2.io.deq.bits connect remapVecValids[2], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[2] node _T_2397 = eq(UInt<2>(0h3), remapindex_2) when _T_2397 : connect remapVecData[2], Queue64_UInt8_3.io.deq.bits connect remapVecValids[2], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[2] node _T_2398 = eq(UInt<3>(0h4), remapindex_2) when _T_2398 : connect remapVecData[2], Queue64_UInt8_4.io.deq.bits connect remapVecValids[2], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[2] node _T_2399 = eq(UInt<3>(0h5), remapindex_2) when _T_2399 : connect remapVecData[2], Queue64_UInt8_5.io.deq.bits connect remapVecValids[2], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[2] node _T_2400 = eq(UInt<3>(0h6), remapindex_2) when _T_2400 : connect remapVecData[2], Queue64_UInt8_6.io.deq.bits connect remapVecValids[2], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[2] node _T_2401 = eq(UInt<3>(0h7), remapindex_2) when _T_2401 : connect remapVecData[2], Queue64_UInt8_7.io.deq.bits connect remapVecValids[2], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[2] node _T_2402 = eq(UInt<4>(0h8), remapindex_2) when _T_2402 : connect remapVecData[2], Queue64_UInt8_8.io.deq.bits connect remapVecValids[2], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[2] node _T_2403 = eq(UInt<4>(0h9), remapindex_2) when _T_2403 : connect remapVecData[2], Queue64_UInt8_9.io.deq.bits connect remapVecValids[2], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[2] node _T_2404 = eq(UInt<4>(0ha), remapindex_2) when _T_2404 : connect remapVecData[2], Queue64_UInt8_10.io.deq.bits connect remapVecValids[2], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[2] node _T_2405 = eq(UInt<4>(0hb), remapindex_2) when _T_2405 : connect remapVecData[2], Queue64_UInt8_11.io.deq.bits connect remapVecValids[2], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[2] node _T_2406 = eq(UInt<4>(0hc), remapindex_2) when _T_2406 : connect remapVecData[2], Queue64_UInt8_12.io.deq.bits connect remapVecValids[2], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[2] node _T_2407 = eq(UInt<4>(0hd), remapindex_2) when _T_2407 : connect remapVecData[2], Queue64_UInt8_13.io.deq.bits connect remapVecValids[2], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[2] node _T_2408 = eq(UInt<4>(0he), remapindex_2) when _T_2408 : connect remapVecData[2], Queue64_UInt8_14.io.deq.bits connect remapVecValids[2], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[2] node _T_2409 = eq(UInt<4>(0hf), remapindex_2) when _T_2409 : connect remapVecData[2], Queue64_UInt8_15.io.deq.bits connect remapVecValids[2], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[2] node _T_2410 = eq(UInt<5>(0h10), remapindex_2) when _T_2410 : connect remapVecData[2], Queue64_UInt8_16.io.deq.bits connect remapVecValids[2], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[2] node _T_2411 = eq(UInt<5>(0h11), remapindex_2) when _T_2411 : connect remapVecData[2], Queue64_UInt8_17.io.deq.bits connect remapVecValids[2], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[2] node _T_2412 = eq(UInt<5>(0h12), remapindex_2) when _T_2412 : connect remapVecData[2], Queue64_UInt8_18.io.deq.bits connect remapVecValids[2], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[2] node _T_2413 = eq(UInt<5>(0h13), remapindex_2) when _T_2413 : connect remapVecData[2], Queue64_UInt8_19.io.deq.bits connect remapVecValids[2], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[2] node _T_2414 = eq(UInt<5>(0h14), remapindex_2) when _T_2414 : connect remapVecData[2], Queue64_UInt8_20.io.deq.bits connect remapVecValids[2], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[2] node _T_2415 = eq(UInt<5>(0h15), remapindex_2) when _T_2415 : connect remapVecData[2], Queue64_UInt8_21.io.deq.bits connect remapVecValids[2], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[2] node _T_2416 = eq(UInt<5>(0h16), remapindex_2) when _T_2416 : connect remapVecData[2], Queue64_UInt8_22.io.deq.bits connect remapVecValids[2], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[2] node _T_2417 = eq(UInt<5>(0h17), remapindex_2) when _T_2417 : connect remapVecData[2], Queue64_UInt8_23.io.deq.bits connect remapVecValids[2], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[2] node _T_2418 = eq(UInt<5>(0h18), remapindex_2) when _T_2418 : connect remapVecData[2], Queue64_UInt8_24.io.deq.bits connect remapVecValids[2], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[2] node _T_2419 = eq(UInt<5>(0h19), remapindex_2) when _T_2419 : connect remapVecData[2], Queue64_UInt8_25.io.deq.bits connect remapVecValids[2], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[2] node _T_2420 = eq(UInt<5>(0h1a), remapindex_2) when _T_2420 : connect remapVecData[2], Queue64_UInt8_26.io.deq.bits connect remapVecValids[2], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[2] node _T_2421 = eq(UInt<5>(0h1b), remapindex_2) when _T_2421 : connect remapVecData[2], Queue64_UInt8_27.io.deq.bits connect remapVecValids[2], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[2] node _T_2422 = eq(UInt<5>(0h1c), remapindex_2) when _T_2422 : connect remapVecData[2], Queue64_UInt8_28.io.deq.bits connect remapVecValids[2], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[2] node _T_2423 = eq(UInt<5>(0h1d), remapindex_2) when _T_2423 : connect remapVecData[2], Queue64_UInt8_29.io.deq.bits connect remapVecValids[2], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[2] node _T_2424 = eq(UInt<5>(0h1e), remapindex_2) when _T_2424 : connect remapVecData[2], Queue64_UInt8_30.io.deq.bits connect remapVecValids[2], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[2] node _T_2425 = eq(UInt<5>(0h1f), remapindex_2) when _T_2425 : connect remapVecData[2], Queue64_UInt8_31.io.deq.bits connect remapVecValids[2], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[2] node _remapindex_T_3 = add(UInt<2>(0h3), read_start_index) node remapindex_3 = rem(_remapindex_T_3, UInt<6>(0h20)) node _T_2426 = eq(UInt<1>(0h0), remapindex_3) when _T_2426 : connect remapVecData[3], Queue64_UInt8.io.deq.bits connect remapVecValids[3], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[3] node _T_2427 = eq(UInt<1>(0h1), remapindex_3) when _T_2427 : connect remapVecData[3], Queue64_UInt8_1.io.deq.bits connect remapVecValids[3], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[3] node _T_2428 = eq(UInt<2>(0h2), remapindex_3) when _T_2428 : connect remapVecData[3], Queue64_UInt8_2.io.deq.bits connect remapVecValids[3], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[3] node _T_2429 = eq(UInt<2>(0h3), remapindex_3) when _T_2429 : connect remapVecData[3], Queue64_UInt8_3.io.deq.bits connect remapVecValids[3], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[3] node _T_2430 = eq(UInt<3>(0h4), remapindex_3) when _T_2430 : connect remapVecData[3], Queue64_UInt8_4.io.deq.bits connect remapVecValids[3], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[3] node _T_2431 = eq(UInt<3>(0h5), remapindex_3) when _T_2431 : connect remapVecData[3], Queue64_UInt8_5.io.deq.bits connect remapVecValids[3], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[3] node _T_2432 = eq(UInt<3>(0h6), remapindex_3) when _T_2432 : connect remapVecData[3], Queue64_UInt8_6.io.deq.bits connect remapVecValids[3], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[3] node _T_2433 = eq(UInt<3>(0h7), remapindex_3) when _T_2433 : connect remapVecData[3], Queue64_UInt8_7.io.deq.bits connect remapVecValids[3], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[3] node _T_2434 = eq(UInt<4>(0h8), remapindex_3) when _T_2434 : connect remapVecData[3], Queue64_UInt8_8.io.deq.bits connect remapVecValids[3], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[3] node _T_2435 = eq(UInt<4>(0h9), remapindex_3) when _T_2435 : connect remapVecData[3], Queue64_UInt8_9.io.deq.bits connect remapVecValids[3], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[3] node _T_2436 = eq(UInt<4>(0ha), remapindex_3) when _T_2436 : connect remapVecData[3], Queue64_UInt8_10.io.deq.bits connect remapVecValids[3], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[3] node _T_2437 = eq(UInt<4>(0hb), remapindex_3) when _T_2437 : connect remapVecData[3], Queue64_UInt8_11.io.deq.bits connect remapVecValids[3], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[3] node _T_2438 = eq(UInt<4>(0hc), remapindex_3) when _T_2438 : connect remapVecData[3], Queue64_UInt8_12.io.deq.bits connect remapVecValids[3], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[3] node _T_2439 = eq(UInt<4>(0hd), remapindex_3) when _T_2439 : connect remapVecData[3], Queue64_UInt8_13.io.deq.bits connect remapVecValids[3], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[3] node _T_2440 = eq(UInt<4>(0he), remapindex_3) when _T_2440 : connect remapVecData[3], Queue64_UInt8_14.io.deq.bits connect remapVecValids[3], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[3] node _T_2441 = eq(UInt<4>(0hf), remapindex_3) when _T_2441 : connect remapVecData[3], Queue64_UInt8_15.io.deq.bits connect remapVecValids[3], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[3] node _T_2442 = eq(UInt<5>(0h10), remapindex_3) when _T_2442 : connect remapVecData[3], Queue64_UInt8_16.io.deq.bits connect remapVecValids[3], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[3] node _T_2443 = eq(UInt<5>(0h11), remapindex_3) when _T_2443 : connect remapVecData[3], Queue64_UInt8_17.io.deq.bits connect remapVecValids[3], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[3] node _T_2444 = eq(UInt<5>(0h12), remapindex_3) when _T_2444 : connect remapVecData[3], Queue64_UInt8_18.io.deq.bits connect remapVecValids[3], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[3] node _T_2445 = eq(UInt<5>(0h13), remapindex_3) when _T_2445 : connect remapVecData[3], Queue64_UInt8_19.io.deq.bits connect remapVecValids[3], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[3] node _T_2446 = eq(UInt<5>(0h14), remapindex_3) when _T_2446 : connect remapVecData[3], Queue64_UInt8_20.io.deq.bits connect remapVecValids[3], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[3] node _T_2447 = eq(UInt<5>(0h15), remapindex_3) when _T_2447 : connect remapVecData[3], Queue64_UInt8_21.io.deq.bits connect remapVecValids[3], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[3] node _T_2448 = eq(UInt<5>(0h16), remapindex_3) when _T_2448 : connect remapVecData[3], Queue64_UInt8_22.io.deq.bits connect remapVecValids[3], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[3] node _T_2449 = eq(UInt<5>(0h17), remapindex_3) when _T_2449 : connect remapVecData[3], Queue64_UInt8_23.io.deq.bits connect remapVecValids[3], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[3] node _T_2450 = eq(UInt<5>(0h18), remapindex_3) when _T_2450 : connect remapVecData[3], Queue64_UInt8_24.io.deq.bits connect remapVecValids[3], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[3] node _T_2451 = eq(UInt<5>(0h19), remapindex_3) when _T_2451 : connect remapVecData[3], Queue64_UInt8_25.io.deq.bits connect remapVecValids[3], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[3] node _T_2452 = eq(UInt<5>(0h1a), remapindex_3) when _T_2452 : connect remapVecData[3], Queue64_UInt8_26.io.deq.bits connect remapVecValids[3], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[3] node _T_2453 = eq(UInt<5>(0h1b), remapindex_3) when _T_2453 : connect remapVecData[3], Queue64_UInt8_27.io.deq.bits connect remapVecValids[3], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[3] node _T_2454 = eq(UInt<5>(0h1c), remapindex_3) when _T_2454 : connect remapVecData[3], Queue64_UInt8_28.io.deq.bits connect remapVecValids[3], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[3] node _T_2455 = eq(UInt<5>(0h1d), remapindex_3) when _T_2455 : connect remapVecData[3], Queue64_UInt8_29.io.deq.bits connect remapVecValids[3], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[3] node _T_2456 = eq(UInt<5>(0h1e), remapindex_3) when _T_2456 : connect remapVecData[3], Queue64_UInt8_30.io.deq.bits connect remapVecValids[3], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[3] node _T_2457 = eq(UInt<5>(0h1f), remapindex_3) when _T_2457 : connect remapVecData[3], Queue64_UInt8_31.io.deq.bits connect remapVecValids[3], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[3] node _remapindex_T_4 = add(UInt<3>(0h4), read_start_index) node remapindex_4 = rem(_remapindex_T_4, UInt<6>(0h20)) node _T_2458 = eq(UInt<1>(0h0), remapindex_4) when _T_2458 : connect remapVecData[4], Queue64_UInt8.io.deq.bits connect remapVecValids[4], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[4] node _T_2459 = eq(UInt<1>(0h1), remapindex_4) when _T_2459 : connect remapVecData[4], Queue64_UInt8_1.io.deq.bits connect remapVecValids[4], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[4] node _T_2460 = eq(UInt<2>(0h2), remapindex_4) when _T_2460 : connect remapVecData[4], Queue64_UInt8_2.io.deq.bits connect remapVecValids[4], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[4] node _T_2461 = eq(UInt<2>(0h3), remapindex_4) when _T_2461 : connect remapVecData[4], Queue64_UInt8_3.io.deq.bits connect remapVecValids[4], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[4] node _T_2462 = eq(UInt<3>(0h4), remapindex_4) when _T_2462 : connect remapVecData[4], Queue64_UInt8_4.io.deq.bits connect remapVecValids[4], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[4] node _T_2463 = eq(UInt<3>(0h5), remapindex_4) when _T_2463 : connect remapVecData[4], Queue64_UInt8_5.io.deq.bits connect remapVecValids[4], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[4] node _T_2464 = eq(UInt<3>(0h6), remapindex_4) when _T_2464 : connect remapVecData[4], Queue64_UInt8_6.io.deq.bits connect remapVecValids[4], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[4] node _T_2465 = eq(UInt<3>(0h7), remapindex_4) when _T_2465 : connect remapVecData[4], Queue64_UInt8_7.io.deq.bits connect remapVecValids[4], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[4] node _T_2466 = eq(UInt<4>(0h8), remapindex_4) when _T_2466 : connect remapVecData[4], Queue64_UInt8_8.io.deq.bits connect remapVecValids[4], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[4] node _T_2467 = eq(UInt<4>(0h9), remapindex_4) when _T_2467 : connect remapVecData[4], Queue64_UInt8_9.io.deq.bits connect remapVecValids[4], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[4] node _T_2468 = eq(UInt<4>(0ha), remapindex_4) when _T_2468 : connect remapVecData[4], Queue64_UInt8_10.io.deq.bits connect remapVecValids[4], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[4] node _T_2469 = eq(UInt<4>(0hb), remapindex_4) when _T_2469 : connect remapVecData[4], Queue64_UInt8_11.io.deq.bits connect remapVecValids[4], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[4] node _T_2470 = eq(UInt<4>(0hc), remapindex_4) when _T_2470 : connect remapVecData[4], Queue64_UInt8_12.io.deq.bits connect remapVecValids[4], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[4] node _T_2471 = eq(UInt<4>(0hd), remapindex_4) when _T_2471 : connect remapVecData[4], Queue64_UInt8_13.io.deq.bits connect remapVecValids[4], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[4] node _T_2472 = eq(UInt<4>(0he), remapindex_4) when _T_2472 : connect remapVecData[4], Queue64_UInt8_14.io.deq.bits connect remapVecValids[4], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[4] node _T_2473 = eq(UInt<4>(0hf), remapindex_4) when _T_2473 : connect remapVecData[4], Queue64_UInt8_15.io.deq.bits connect remapVecValids[4], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[4] node _T_2474 = eq(UInt<5>(0h10), remapindex_4) when _T_2474 : connect remapVecData[4], Queue64_UInt8_16.io.deq.bits connect remapVecValids[4], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[4] node _T_2475 = eq(UInt<5>(0h11), remapindex_4) when _T_2475 : connect remapVecData[4], Queue64_UInt8_17.io.deq.bits connect remapVecValids[4], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[4] node _T_2476 = eq(UInt<5>(0h12), remapindex_4) when _T_2476 : connect remapVecData[4], Queue64_UInt8_18.io.deq.bits connect remapVecValids[4], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[4] node _T_2477 = eq(UInt<5>(0h13), remapindex_4) when _T_2477 : connect remapVecData[4], Queue64_UInt8_19.io.deq.bits connect remapVecValids[4], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[4] node _T_2478 = eq(UInt<5>(0h14), remapindex_4) when _T_2478 : connect remapVecData[4], Queue64_UInt8_20.io.deq.bits connect remapVecValids[4], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[4] node _T_2479 = eq(UInt<5>(0h15), remapindex_4) when _T_2479 : connect remapVecData[4], Queue64_UInt8_21.io.deq.bits connect remapVecValids[4], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[4] node _T_2480 = eq(UInt<5>(0h16), remapindex_4) when _T_2480 : connect remapVecData[4], Queue64_UInt8_22.io.deq.bits connect remapVecValids[4], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[4] node _T_2481 = eq(UInt<5>(0h17), remapindex_4) when _T_2481 : connect remapVecData[4], Queue64_UInt8_23.io.deq.bits connect remapVecValids[4], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[4] node _T_2482 = eq(UInt<5>(0h18), remapindex_4) when _T_2482 : connect remapVecData[4], Queue64_UInt8_24.io.deq.bits connect remapVecValids[4], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[4] node _T_2483 = eq(UInt<5>(0h19), remapindex_4) when _T_2483 : connect remapVecData[4], Queue64_UInt8_25.io.deq.bits connect remapVecValids[4], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[4] node _T_2484 = eq(UInt<5>(0h1a), remapindex_4) when _T_2484 : connect remapVecData[4], Queue64_UInt8_26.io.deq.bits connect remapVecValids[4], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[4] node _T_2485 = eq(UInt<5>(0h1b), remapindex_4) when _T_2485 : connect remapVecData[4], Queue64_UInt8_27.io.deq.bits connect remapVecValids[4], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[4] node _T_2486 = eq(UInt<5>(0h1c), remapindex_4) when _T_2486 : connect remapVecData[4], Queue64_UInt8_28.io.deq.bits connect remapVecValids[4], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[4] node _T_2487 = eq(UInt<5>(0h1d), remapindex_4) when _T_2487 : connect remapVecData[4], Queue64_UInt8_29.io.deq.bits connect remapVecValids[4], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[4] node _T_2488 = eq(UInt<5>(0h1e), remapindex_4) when _T_2488 : connect remapVecData[4], Queue64_UInt8_30.io.deq.bits connect remapVecValids[4], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[4] node _T_2489 = eq(UInt<5>(0h1f), remapindex_4) when _T_2489 : connect remapVecData[4], Queue64_UInt8_31.io.deq.bits connect remapVecValids[4], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[4] node _remapindex_T_5 = add(UInt<3>(0h5), read_start_index) node remapindex_5 = rem(_remapindex_T_5, UInt<6>(0h20)) node _T_2490 = eq(UInt<1>(0h0), remapindex_5) when _T_2490 : connect remapVecData[5], Queue64_UInt8.io.deq.bits connect remapVecValids[5], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[5] node _T_2491 = eq(UInt<1>(0h1), remapindex_5) when _T_2491 : connect remapVecData[5], Queue64_UInt8_1.io.deq.bits connect remapVecValids[5], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[5] node _T_2492 = eq(UInt<2>(0h2), remapindex_5) when _T_2492 : connect remapVecData[5], Queue64_UInt8_2.io.deq.bits connect remapVecValids[5], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[5] node _T_2493 = eq(UInt<2>(0h3), remapindex_5) when _T_2493 : connect remapVecData[5], Queue64_UInt8_3.io.deq.bits connect remapVecValids[5], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[5] node _T_2494 = eq(UInt<3>(0h4), remapindex_5) when _T_2494 : connect remapVecData[5], Queue64_UInt8_4.io.deq.bits connect remapVecValids[5], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[5] node _T_2495 = eq(UInt<3>(0h5), remapindex_5) when _T_2495 : connect remapVecData[5], Queue64_UInt8_5.io.deq.bits connect remapVecValids[5], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[5] node _T_2496 = eq(UInt<3>(0h6), remapindex_5) when _T_2496 : connect remapVecData[5], Queue64_UInt8_6.io.deq.bits connect remapVecValids[5], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[5] node _T_2497 = eq(UInt<3>(0h7), remapindex_5) when _T_2497 : connect remapVecData[5], Queue64_UInt8_7.io.deq.bits connect remapVecValids[5], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[5] node _T_2498 = eq(UInt<4>(0h8), remapindex_5) when _T_2498 : connect remapVecData[5], Queue64_UInt8_8.io.deq.bits connect remapVecValids[5], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[5] node _T_2499 = eq(UInt<4>(0h9), remapindex_5) when _T_2499 : connect remapVecData[5], Queue64_UInt8_9.io.deq.bits connect remapVecValids[5], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[5] node _T_2500 = eq(UInt<4>(0ha), remapindex_5) when _T_2500 : connect remapVecData[5], Queue64_UInt8_10.io.deq.bits connect remapVecValids[5], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[5] node _T_2501 = eq(UInt<4>(0hb), remapindex_5) when _T_2501 : connect remapVecData[5], Queue64_UInt8_11.io.deq.bits connect remapVecValids[5], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[5] node _T_2502 = eq(UInt<4>(0hc), remapindex_5) when _T_2502 : connect remapVecData[5], Queue64_UInt8_12.io.deq.bits connect remapVecValids[5], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[5] node _T_2503 = eq(UInt<4>(0hd), remapindex_5) when _T_2503 : connect remapVecData[5], Queue64_UInt8_13.io.deq.bits connect remapVecValids[5], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[5] node _T_2504 = eq(UInt<4>(0he), remapindex_5) when _T_2504 : connect remapVecData[5], Queue64_UInt8_14.io.deq.bits connect remapVecValids[5], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[5] node _T_2505 = eq(UInt<4>(0hf), remapindex_5) when _T_2505 : connect remapVecData[5], Queue64_UInt8_15.io.deq.bits connect remapVecValids[5], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[5] node _T_2506 = eq(UInt<5>(0h10), remapindex_5) when _T_2506 : connect remapVecData[5], Queue64_UInt8_16.io.deq.bits connect remapVecValids[5], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[5] node _T_2507 = eq(UInt<5>(0h11), remapindex_5) when _T_2507 : connect remapVecData[5], Queue64_UInt8_17.io.deq.bits connect remapVecValids[5], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[5] node _T_2508 = eq(UInt<5>(0h12), remapindex_5) when _T_2508 : connect remapVecData[5], Queue64_UInt8_18.io.deq.bits connect remapVecValids[5], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[5] node _T_2509 = eq(UInt<5>(0h13), remapindex_5) when _T_2509 : connect remapVecData[5], Queue64_UInt8_19.io.deq.bits connect remapVecValids[5], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[5] node _T_2510 = eq(UInt<5>(0h14), remapindex_5) when _T_2510 : connect remapVecData[5], Queue64_UInt8_20.io.deq.bits connect remapVecValids[5], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[5] node _T_2511 = eq(UInt<5>(0h15), remapindex_5) when _T_2511 : connect remapVecData[5], Queue64_UInt8_21.io.deq.bits connect remapVecValids[5], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[5] node _T_2512 = eq(UInt<5>(0h16), remapindex_5) when _T_2512 : connect remapVecData[5], Queue64_UInt8_22.io.deq.bits connect remapVecValids[5], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[5] node _T_2513 = eq(UInt<5>(0h17), remapindex_5) when _T_2513 : connect remapVecData[5], Queue64_UInt8_23.io.deq.bits connect remapVecValids[5], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[5] node _T_2514 = eq(UInt<5>(0h18), remapindex_5) when _T_2514 : connect remapVecData[5], Queue64_UInt8_24.io.deq.bits connect remapVecValids[5], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[5] node _T_2515 = eq(UInt<5>(0h19), remapindex_5) when _T_2515 : connect remapVecData[5], Queue64_UInt8_25.io.deq.bits connect remapVecValids[5], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[5] node _T_2516 = eq(UInt<5>(0h1a), remapindex_5) when _T_2516 : connect remapVecData[5], Queue64_UInt8_26.io.deq.bits connect remapVecValids[5], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[5] node _T_2517 = eq(UInt<5>(0h1b), remapindex_5) when _T_2517 : connect remapVecData[5], Queue64_UInt8_27.io.deq.bits connect remapVecValids[5], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[5] node _T_2518 = eq(UInt<5>(0h1c), remapindex_5) when _T_2518 : connect remapVecData[5], Queue64_UInt8_28.io.deq.bits connect remapVecValids[5], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[5] node _T_2519 = eq(UInt<5>(0h1d), remapindex_5) when _T_2519 : connect remapVecData[5], Queue64_UInt8_29.io.deq.bits connect remapVecValids[5], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[5] node _T_2520 = eq(UInt<5>(0h1e), remapindex_5) when _T_2520 : connect remapVecData[5], Queue64_UInt8_30.io.deq.bits connect remapVecValids[5], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[5] node _T_2521 = eq(UInt<5>(0h1f), remapindex_5) when _T_2521 : connect remapVecData[5], Queue64_UInt8_31.io.deq.bits connect remapVecValids[5], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[5] node _remapindex_T_6 = add(UInt<3>(0h6), read_start_index) node remapindex_6 = rem(_remapindex_T_6, UInt<6>(0h20)) node _T_2522 = eq(UInt<1>(0h0), remapindex_6) when _T_2522 : connect remapVecData[6], Queue64_UInt8.io.deq.bits connect remapVecValids[6], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[6] node _T_2523 = eq(UInt<1>(0h1), remapindex_6) when _T_2523 : connect remapVecData[6], Queue64_UInt8_1.io.deq.bits connect remapVecValids[6], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[6] node _T_2524 = eq(UInt<2>(0h2), remapindex_6) when _T_2524 : connect remapVecData[6], Queue64_UInt8_2.io.deq.bits connect remapVecValids[6], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[6] node _T_2525 = eq(UInt<2>(0h3), remapindex_6) when _T_2525 : connect remapVecData[6], Queue64_UInt8_3.io.deq.bits connect remapVecValids[6], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[6] node _T_2526 = eq(UInt<3>(0h4), remapindex_6) when _T_2526 : connect remapVecData[6], Queue64_UInt8_4.io.deq.bits connect remapVecValids[6], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[6] node _T_2527 = eq(UInt<3>(0h5), remapindex_6) when _T_2527 : connect remapVecData[6], Queue64_UInt8_5.io.deq.bits connect remapVecValids[6], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[6] node _T_2528 = eq(UInt<3>(0h6), remapindex_6) when _T_2528 : connect remapVecData[6], Queue64_UInt8_6.io.deq.bits connect remapVecValids[6], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[6] node _T_2529 = eq(UInt<3>(0h7), remapindex_6) when _T_2529 : connect remapVecData[6], Queue64_UInt8_7.io.deq.bits connect remapVecValids[6], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[6] node _T_2530 = eq(UInt<4>(0h8), remapindex_6) when _T_2530 : connect remapVecData[6], Queue64_UInt8_8.io.deq.bits connect remapVecValids[6], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[6] node _T_2531 = eq(UInt<4>(0h9), remapindex_6) when _T_2531 : connect remapVecData[6], Queue64_UInt8_9.io.deq.bits connect remapVecValids[6], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[6] node _T_2532 = eq(UInt<4>(0ha), remapindex_6) when _T_2532 : connect remapVecData[6], Queue64_UInt8_10.io.deq.bits connect remapVecValids[6], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[6] node _T_2533 = eq(UInt<4>(0hb), remapindex_6) when _T_2533 : connect remapVecData[6], Queue64_UInt8_11.io.deq.bits connect remapVecValids[6], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[6] node _T_2534 = eq(UInt<4>(0hc), remapindex_6) when _T_2534 : connect remapVecData[6], Queue64_UInt8_12.io.deq.bits connect remapVecValids[6], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[6] node _T_2535 = eq(UInt<4>(0hd), remapindex_6) when _T_2535 : connect remapVecData[6], Queue64_UInt8_13.io.deq.bits connect remapVecValids[6], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[6] node _T_2536 = eq(UInt<4>(0he), remapindex_6) when _T_2536 : connect remapVecData[6], Queue64_UInt8_14.io.deq.bits connect remapVecValids[6], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[6] node _T_2537 = eq(UInt<4>(0hf), remapindex_6) when _T_2537 : connect remapVecData[6], Queue64_UInt8_15.io.deq.bits connect remapVecValids[6], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[6] node _T_2538 = eq(UInt<5>(0h10), remapindex_6) when _T_2538 : connect remapVecData[6], Queue64_UInt8_16.io.deq.bits connect remapVecValids[6], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[6] node _T_2539 = eq(UInt<5>(0h11), remapindex_6) when _T_2539 : connect remapVecData[6], Queue64_UInt8_17.io.deq.bits connect remapVecValids[6], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[6] node _T_2540 = eq(UInt<5>(0h12), remapindex_6) when _T_2540 : connect remapVecData[6], Queue64_UInt8_18.io.deq.bits connect remapVecValids[6], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[6] node _T_2541 = eq(UInt<5>(0h13), remapindex_6) when _T_2541 : connect remapVecData[6], Queue64_UInt8_19.io.deq.bits connect remapVecValids[6], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[6] node _T_2542 = eq(UInt<5>(0h14), remapindex_6) when _T_2542 : connect remapVecData[6], Queue64_UInt8_20.io.deq.bits connect remapVecValids[6], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[6] node _T_2543 = eq(UInt<5>(0h15), remapindex_6) when _T_2543 : connect remapVecData[6], Queue64_UInt8_21.io.deq.bits connect remapVecValids[6], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[6] node _T_2544 = eq(UInt<5>(0h16), remapindex_6) when _T_2544 : connect remapVecData[6], Queue64_UInt8_22.io.deq.bits connect remapVecValids[6], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[6] node _T_2545 = eq(UInt<5>(0h17), remapindex_6) when _T_2545 : connect remapVecData[6], Queue64_UInt8_23.io.deq.bits connect remapVecValids[6], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[6] node _T_2546 = eq(UInt<5>(0h18), remapindex_6) when _T_2546 : connect remapVecData[6], Queue64_UInt8_24.io.deq.bits connect remapVecValids[6], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[6] node _T_2547 = eq(UInt<5>(0h19), remapindex_6) when _T_2547 : connect remapVecData[6], Queue64_UInt8_25.io.deq.bits connect remapVecValids[6], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[6] node _T_2548 = eq(UInt<5>(0h1a), remapindex_6) when _T_2548 : connect remapVecData[6], Queue64_UInt8_26.io.deq.bits connect remapVecValids[6], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[6] node _T_2549 = eq(UInt<5>(0h1b), remapindex_6) when _T_2549 : connect remapVecData[6], Queue64_UInt8_27.io.deq.bits connect remapVecValids[6], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[6] node _T_2550 = eq(UInt<5>(0h1c), remapindex_6) when _T_2550 : connect remapVecData[6], Queue64_UInt8_28.io.deq.bits connect remapVecValids[6], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[6] node _T_2551 = eq(UInt<5>(0h1d), remapindex_6) when _T_2551 : connect remapVecData[6], Queue64_UInt8_29.io.deq.bits connect remapVecValids[6], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[6] node _T_2552 = eq(UInt<5>(0h1e), remapindex_6) when _T_2552 : connect remapVecData[6], Queue64_UInt8_30.io.deq.bits connect remapVecValids[6], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[6] node _T_2553 = eq(UInt<5>(0h1f), remapindex_6) when _T_2553 : connect remapVecData[6], Queue64_UInt8_31.io.deq.bits connect remapVecValids[6], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[6] node _remapindex_T_7 = add(UInt<3>(0h7), read_start_index) node remapindex_7 = rem(_remapindex_T_7, UInt<6>(0h20)) node _T_2554 = eq(UInt<1>(0h0), remapindex_7) when _T_2554 : connect remapVecData[7], Queue64_UInt8.io.deq.bits connect remapVecValids[7], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[7] node _T_2555 = eq(UInt<1>(0h1), remapindex_7) when _T_2555 : connect remapVecData[7], Queue64_UInt8_1.io.deq.bits connect remapVecValids[7], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[7] node _T_2556 = eq(UInt<2>(0h2), remapindex_7) when _T_2556 : connect remapVecData[7], Queue64_UInt8_2.io.deq.bits connect remapVecValids[7], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[7] node _T_2557 = eq(UInt<2>(0h3), remapindex_7) when _T_2557 : connect remapVecData[7], Queue64_UInt8_3.io.deq.bits connect remapVecValids[7], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[7] node _T_2558 = eq(UInt<3>(0h4), remapindex_7) when _T_2558 : connect remapVecData[7], Queue64_UInt8_4.io.deq.bits connect remapVecValids[7], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[7] node _T_2559 = eq(UInt<3>(0h5), remapindex_7) when _T_2559 : connect remapVecData[7], Queue64_UInt8_5.io.deq.bits connect remapVecValids[7], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[7] node _T_2560 = eq(UInt<3>(0h6), remapindex_7) when _T_2560 : connect remapVecData[7], Queue64_UInt8_6.io.deq.bits connect remapVecValids[7], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[7] node _T_2561 = eq(UInt<3>(0h7), remapindex_7) when _T_2561 : connect remapVecData[7], Queue64_UInt8_7.io.deq.bits connect remapVecValids[7], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[7] node _T_2562 = eq(UInt<4>(0h8), remapindex_7) when _T_2562 : connect remapVecData[7], Queue64_UInt8_8.io.deq.bits connect remapVecValids[7], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[7] node _T_2563 = eq(UInt<4>(0h9), remapindex_7) when _T_2563 : connect remapVecData[7], Queue64_UInt8_9.io.deq.bits connect remapVecValids[7], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[7] node _T_2564 = eq(UInt<4>(0ha), remapindex_7) when _T_2564 : connect remapVecData[7], Queue64_UInt8_10.io.deq.bits connect remapVecValids[7], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[7] node _T_2565 = eq(UInt<4>(0hb), remapindex_7) when _T_2565 : connect remapVecData[7], Queue64_UInt8_11.io.deq.bits connect remapVecValids[7], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[7] node _T_2566 = eq(UInt<4>(0hc), remapindex_7) when _T_2566 : connect remapVecData[7], Queue64_UInt8_12.io.deq.bits connect remapVecValids[7], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[7] node _T_2567 = eq(UInt<4>(0hd), remapindex_7) when _T_2567 : connect remapVecData[7], Queue64_UInt8_13.io.deq.bits connect remapVecValids[7], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[7] node _T_2568 = eq(UInt<4>(0he), remapindex_7) when _T_2568 : connect remapVecData[7], Queue64_UInt8_14.io.deq.bits connect remapVecValids[7], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[7] node _T_2569 = eq(UInt<4>(0hf), remapindex_7) when _T_2569 : connect remapVecData[7], Queue64_UInt8_15.io.deq.bits connect remapVecValids[7], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[7] node _T_2570 = eq(UInt<5>(0h10), remapindex_7) when _T_2570 : connect remapVecData[7], Queue64_UInt8_16.io.deq.bits connect remapVecValids[7], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[7] node _T_2571 = eq(UInt<5>(0h11), remapindex_7) when _T_2571 : connect remapVecData[7], Queue64_UInt8_17.io.deq.bits connect remapVecValids[7], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[7] node _T_2572 = eq(UInt<5>(0h12), remapindex_7) when _T_2572 : connect remapVecData[7], Queue64_UInt8_18.io.deq.bits connect remapVecValids[7], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[7] node _T_2573 = eq(UInt<5>(0h13), remapindex_7) when _T_2573 : connect remapVecData[7], Queue64_UInt8_19.io.deq.bits connect remapVecValids[7], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[7] node _T_2574 = eq(UInt<5>(0h14), remapindex_7) when _T_2574 : connect remapVecData[7], Queue64_UInt8_20.io.deq.bits connect remapVecValids[7], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[7] node _T_2575 = eq(UInt<5>(0h15), remapindex_7) when _T_2575 : connect remapVecData[7], Queue64_UInt8_21.io.deq.bits connect remapVecValids[7], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[7] node _T_2576 = eq(UInt<5>(0h16), remapindex_7) when _T_2576 : connect remapVecData[7], Queue64_UInt8_22.io.deq.bits connect remapVecValids[7], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[7] node _T_2577 = eq(UInt<5>(0h17), remapindex_7) when _T_2577 : connect remapVecData[7], Queue64_UInt8_23.io.deq.bits connect remapVecValids[7], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[7] node _T_2578 = eq(UInt<5>(0h18), remapindex_7) when _T_2578 : connect remapVecData[7], Queue64_UInt8_24.io.deq.bits connect remapVecValids[7], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[7] node _T_2579 = eq(UInt<5>(0h19), remapindex_7) when _T_2579 : connect remapVecData[7], Queue64_UInt8_25.io.deq.bits connect remapVecValids[7], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[7] node _T_2580 = eq(UInt<5>(0h1a), remapindex_7) when _T_2580 : connect remapVecData[7], Queue64_UInt8_26.io.deq.bits connect remapVecValids[7], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[7] node _T_2581 = eq(UInt<5>(0h1b), remapindex_7) when _T_2581 : connect remapVecData[7], Queue64_UInt8_27.io.deq.bits connect remapVecValids[7], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[7] node _T_2582 = eq(UInt<5>(0h1c), remapindex_7) when _T_2582 : connect remapVecData[7], Queue64_UInt8_28.io.deq.bits connect remapVecValids[7], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[7] node _T_2583 = eq(UInt<5>(0h1d), remapindex_7) when _T_2583 : connect remapVecData[7], Queue64_UInt8_29.io.deq.bits connect remapVecValids[7], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[7] node _T_2584 = eq(UInt<5>(0h1e), remapindex_7) when _T_2584 : connect remapVecData[7], Queue64_UInt8_30.io.deq.bits connect remapVecValids[7], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[7] node _T_2585 = eq(UInt<5>(0h1f), remapindex_7) when _T_2585 : connect remapVecData[7], Queue64_UInt8_31.io.deq.bits connect remapVecValids[7], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[7] node _remapindex_T_8 = add(UInt<4>(0h8), read_start_index) node remapindex_8 = rem(_remapindex_T_8, UInt<6>(0h20)) node _T_2586 = eq(UInt<1>(0h0), remapindex_8) when _T_2586 : connect remapVecData[8], Queue64_UInt8.io.deq.bits connect remapVecValids[8], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[8] node _T_2587 = eq(UInt<1>(0h1), remapindex_8) when _T_2587 : connect remapVecData[8], Queue64_UInt8_1.io.deq.bits connect remapVecValids[8], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[8] node _T_2588 = eq(UInt<2>(0h2), remapindex_8) when _T_2588 : connect remapVecData[8], Queue64_UInt8_2.io.deq.bits connect remapVecValids[8], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[8] node _T_2589 = eq(UInt<2>(0h3), remapindex_8) when _T_2589 : connect remapVecData[8], Queue64_UInt8_3.io.deq.bits connect remapVecValids[8], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[8] node _T_2590 = eq(UInt<3>(0h4), remapindex_8) when _T_2590 : connect remapVecData[8], Queue64_UInt8_4.io.deq.bits connect remapVecValids[8], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[8] node _T_2591 = eq(UInt<3>(0h5), remapindex_8) when _T_2591 : connect remapVecData[8], Queue64_UInt8_5.io.deq.bits connect remapVecValids[8], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[8] node _T_2592 = eq(UInt<3>(0h6), remapindex_8) when _T_2592 : connect remapVecData[8], Queue64_UInt8_6.io.deq.bits connect remapVecValids[8], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[8] node _T_2593 = eq(UInt<3>(0h7), remapindex_8) when _T_2593 : connect remapVecData[8], Queue64_UInt8_7.io.deq.bits connect remapVecValids[8], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[8] node _T_2594 = eq(UInt<4>(0h8), remapindex_8) when _T_2594 : connect remapVecData[8], Queue64_UInt8_8.io.deq.bits connect remapVecValids[8], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[8] node _T_2595 = eq(UInt<4>(0h9), remapindex_8) when _T_2595 : connect remapVecData[8], Queue64_UInt8_9.io.deq.bits connect remapVecValids[8], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[8] node _T_2596 = eq(UInt<4>(0ha), remapindex_8) when _T_2596 : connect remapVecData[8], Queue64_UInt8_10.io.deq.bits connect remapVecValids[8], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[8] node _T_2597 = eq(UInt<4>(0hb), remapindex_8) when _T_2597 : connect remapVecData[8], Queue64_UInt8_11.io.deq.bits connect remapVecValids[8], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[8] node _T_2598 = eq(UInt<4>(0hc), remapindex_8) when _T_2598 : connect remapVecData[8], Queue64_UInt8_12.io.deq.bits connect remapVecValids[8], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[8] node _T_2599 = eq(UInt<4>(0hd), remapindex_8) when _T_2599 : connect remapVecData[8], Queue64_UInt8_13.io.deq.bits connect remapVecValids[8], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[8] node _T_2600 = eq(UInt<4>(0he), remapindex_8) when _T_2600 : connect remapVecData[8], Queue64_UInt8_14.io.deq.bits connect remapVecValids[8], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[8] node _T_2601 = eq(UInt<4>(0hf), remapindex_8) when _T_2601 : connect remapVecData[8], Queue64_UInt8_15.io.deq.bits connect remapVecValids[8], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[8] node _T_2602 = eq(UInt<5>(0h10), remapindex_8) when _T_2602 : connect remapVecData[8], Queue64_UInt8_16.io.deq.bits connect remapVecValids[8], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[8] node _T_2603 = eq(UInt<5>(0h11), remapindex_8) when _T_2603 : connect remapVecData[8], Queue64_UInt8_17.io.deq.bits connect remapVecValids[8], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[8] node _T_2604 = eq(UInt<5>(0h12), remapindex_8) when _T_2604 : connect remapVecData[8], Queue64_UInt8_18.io.deq.bits connect remapVecValids[8], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[8] node _T_2605 = eq(UInt<5>(0h13), remapindex_8) when _T_2605 : connect remapVecData[8], Queue64_UInt8_19.io.deq.bits connect remapVecValids[8], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[8] node _T_2606 = eq(UInt<5>(0h14), remapindex_8) when _T_2606 : connect remapVecData[8], Queue64_UInt8_20.io.deq.bits connect remapVecValids[8], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[8] node _T_2607 = eq(UInt<5>(0h15), remapindex_8) when _T_2607 : connect remapVecData[8], Queue64_UInt8_21.io.deq.bits connect remapVecValids[8], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[8] node _T_2608 = eq(UInt<5>(0h16), remapindex_8) when _T_2608 : connect remapVecData[8], Queue64_UInt8_22.io.deq.bits connect remapVecValids[8], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[8] node _T_2609 = eq(UInt<5>(0h17), remapindex_8) when _T_2609 : connect remapVecData[8], Queue64_UInt8_23.io.deq.bits connect remapVecValids[8], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[8] node _T_2610 = eq(UInt<5>(0h18), remapindex_8) when _T_2610 : connect remapVecData[8], Queue64_UInt8_24.io.deq.bits connect remapVecValids[8], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[8] node _T_2611 = eq(UInt<5>(0h19), remapindex_8) when _T_2611 : connect remapVecData[8], Queue64_UInt8_25.io.deq.bits connect remapVecValids[8], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[8] node _T_2612 = eq(UInt<5>(0h1a), remapindex_8) when _T_2612 : connect remapVecData[8], Queue64_UInt8_26.io.deq.bits connect remapVecValids[8], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[8] node _T_2613 = eq(UInt<5>(0h1b), remapindex_8) when _T_2613 : connect remapVecData[8], Queue64_UInt8_27.io.deq.bits connect remapVecValids[8], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[8] node _T_2614 = eq(UInt<5>(0h1c), remapindex_8) when _T_2614 : connect remapVecData[8], Queue64_UInt8_28.io.deq.bits connect remapVecValids[8], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[8] node _T_2615 = eq(UInt<5>(0h1d), remapindex_8) when _T_2615 : connect remapVecData[8], Queue64_UInt8_29.io.deq.bits connect remapVecValids[8], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[8] node _T_2616 = eq(UInt<5>(0h1e), remapindex_8) when _T_2616 : connect remapVecData[8], Queue64_UInt8_30.io.deq.bits connect remapVecValids[8], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[8] node _T_2617 = eq(UInt<5>(0h1f), remapindex_8) when _T_2617 : connect remapVecData[8], Queue64_UInt8_31.io.deq.bits connect remapVecValids[8], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[8] node _remapindex_T_9 = add(UInt<4>(0h9), read_start_index) node remapindex_9 = rem(_remapindex_T_9, UInt<6>(0h20)) node _T_2618 = eq(UInt<1>(0h0), remapindex_9) when _T_2618 : connect remapVecData[9], Queue64_UInt8.io.deq.bits connect remapVecValids[9], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[9] node _T_2619 = eq(UInt<1>(0h1), remapindex_9) when _T_2619 : connect remapVecData[9], Queue64_UInt8_1.io.deq.bits connect remapVecValids[9], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[9] node _T_2620 = eq(UInt<2>(0h2), remapindex_9) when _T_2620 : connect remapVecData[9], Queue64_UInt8_2.io.deq.bits connect remapVecValids[9], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[9] node _T_2621 = eq(UInt<2>(0h3), remapindex_9) when _T_2621 : connect remapVecData[9], Queue64_UInt8_3.io.deq.bits connect remapVecValids[9], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[9] node _T_2622 = eq(UInt<3>(0h4), remapindex_9) when _T_2622 : connect remapVecData[9], Queue64_UInt8_4.io.deq.bits connect remapVecValids[9], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[9] node _T_2623 = eq(UInt<3>(0h5), remapindex_9) when _T_2623 : connect remapVecData[9], Queue64_UInt8_5.io.deq.bits connect remapVecValids[9], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[9] node _T_2624 = eq(UInt<3>(0h6), remapindex_9) when _T_2624 : connect remapVecData[9], Queue64_UInt8_6.io.deq.bits connect remapVecValids[9], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[9] node _T_2625 = eq(UInt<3>(0h7), remapindex_9) when _T_2625 : connect remapVecData[9], Queue64_UInt8_7.io.deq.bits connect remapVecValids[9], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[9] node _T_2626 = eq(UInt<4>(0h8), remapindex_9) when _T_2626 : connect remapVecData[9], Queue64_UInt8_8.io.deq.bits connect remapVecValids[9], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[9] node _T_2627 = eq(UInt<4>(0h9), remapindex_9) when _T_2627 : connect remapVecData[9], Queue64_UInt8_9.io.deq.bits connect remapVecValids[9], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[9] node _T_2628 = eq(UInt<4>(0ha), remapindex_9) when _T_2628 : connect remapVecData[9], Queue64_UInt8_10.io.deq.bits connect remapVecValids[9], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[9] node _T_2629 = eq(UInt<4>(0hb), remapindex_9) when _T_2629 : connect remapVecData[9], Queue64_UInt8_11.io.deq.bits connect remapVecValids[9], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[9] node _T_2630 = eq(UInt<4>(0hc), remapindex_9) when _T_2630 : connect remapVecData[9], Queue64_UInt8_12.io.deq.bits connect remapVecValids[9], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[9] node _T_2631 = eq(UInt<4>(0hd), remapindex_9) when _T_2631 : connect remapVecData[9], Queue64_UInt8_13.io.deq.bits connect remapVecValids[9], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[9] node _T_2632 = eq(UInt<4>(0he), remapindex_9) when _T_2632 : connect remapVecData[9], Queue64_UInt8_14.io.deq.bits connect remapVecValids[9], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[9] node _T_2633 = eq(UInt<4>(0hf), remapindex_9) when _T_2633 : connect remapVecData[9], Queue64_UInt8_15.io.deq.bits connect remapVecValids[9], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[9] node _T_2634 = eq(UInt<5>(0h10), remapindex_9) when _T_2634 : connect remapVecData[9], Queue64_UInt8_16.io.deq.bits connect remapVecValids[9], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[9] node _T_2635 = eq(UInt<5>(0h11), remapindex_9) when _T_2635 : connect remapVecData[9], Queue64_UInt8_17.io.deq.bits connect remapVecValids[9], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[9] node _T_2636 = eq(UInt<5>(0h12), remapindex_9) when _T_2636 : connect remapVecData[9], Queue64_UInt8_18.io.deq.bits connect remapVecValids[9], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[9] node _T_2637 = eq(UInt<5>(0h13), remapindex_9) when _T_2637 : connect remapVecData[9], Queue64_UInt8_19.io.deq.bits connect remapVecValids[9], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[9] node _T_2638 = eq(UInt<5>(0h14), remapindex_9) when _T_2638 : connect remapVecData[9], Queue64_UInt8_20.io.deq.bits connect remapVecValids[9], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[9] node _T_2639 = eq(UInt<5>(0h15), remapindex_9) when _T_2639 : connect remapVecData[9], Queue64_UInt8_21.io.deq.bits connect remapVecValids[9], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[9] node _T_2640 = eq(UInt<5>(0h16), remapindex_9) when _T_2640 : connect remapVecData[9], Queue64_UInt8_22.io.deq.bits connect remapVecValids[9], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[9] node _T_2641 = eq(UInt<5>(0h17), remapindex_9) when _T_2641 : connect remapVecData[9], Queue64_UInt8_23.io.deq.bits connect remapVecValids[9], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[9] node _T_2642 = eq(UInt<5>(0h18), remapindex_9) when _T_2642 : connect remapVecData[9], Queue64_UInt8_24.io.deq.bits connect remapVecValids[9], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[9] node _T_2643 = eq(UInt<5>(0h19), remapindex_9) when _T_2643 : connect remapVecData[9], Queue64_UInt8_25.io.deq.bits connect remapVecValids[9], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[9] node _T_2644 = eq(UInt<5>(0h1a), remapindex_9) when _T_2644 : connect remapVecData[9], Queue64_UInt8_26.io.deq.bits connect remapVecValids[9], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[9] node _T_2645 = eq(UInt<5>(0h1b), remapindex_9) when _T_2645 : connect remapVecData[9], Queue64_UInt8_27.io.deq.bits connect remapVecValids[9], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[9] node _T_2646 = eq(UInt<5>(0h1c), remapindex_9) when _T_2646 : connect remapVecData[9], Queue64_UInt8_28.io.deq.bits connect remapVecValids[9], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[9] node _T_2647 = eq(UInt<5>(0h1d), remapindex_9) when _T_2647 : connect remapVecData[9], Queue64_UInt8_29.io.deq.bits connect remapVecValids[9], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[9] node _T_2648 = eq(UInt<5>(0h1e), remapindex_9) when _T_2648 : connect remapVecData[9], Queue64_UInt8_30.io.deq.bits connect remapVecValids[9], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[9] node _T_2649 = eq(UInt<5>(0h1f), remapindex_9) when _T_2649 : connect remapVecData[9], Queue64_UInt8_31.io.deq.bits connect remapVecValids[9], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[9] node _remapindex_T_10 = add(UInt<4>(0ha), read_start_index) node remapindex_10 = rem(_remapindex_T_10, UInt<6>(0h20)) node _T_2650 = eq(UInt<1>(0h0), remapindex_10) when _T_2650 : connect remapVecData[10], Queue64_UInt8.io.deq.bits connect remapVecValids[10], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[10] node _T_2651 = eq(UInt<1>(0h1), remapindex_10) when _T_2651 : connect remapVecData[10], Queue64_UInt8_1.io.deq.bits connect remapVecValids[10], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[10] node _T_2652 = eq(UInt<2>(0h2), remapindex_10) when _T_2652 : connect remapVecData[10], Queue64_UInt8_2.io.deq.bits connect remapVecValids[10], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[10] node _T_2653 = eq(UInt<2>(0h3), remapindex_10) when _T_2653 : connect remapVecData[10], Queue64_UInt8_3.io.deq.bits connect remapVecValids[10], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[10] node _T_2654 = eq(UInt<3>(0h4), remapindex_10) when _T_2654 : connect remapVecData[10], Queue64_UInt8_4.io.deq.bits connect remapVecValids[10], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[10] node _T_2655 = eq(UInt<3>(0h5), remapindex_10) when _T_2655 : connect remapVecData[10], Queue64_UInt8_5.io.deq.bits connect remapVecValids[10], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[10] node _T_2656 = eq(UInt<3>(0h6), remapindex_10) when _T_2656 : connect remapVecData[10], Queue64_UInt8_6.io.deq.bits connect remapVecValids[10], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[10] node _T_2657 = eq(UInt<3>(0h7), remapindex_10) when _T_2657 : connect remapVecData[10], Queue64_UInt8_7.io.deq.bits connect remapVecValids[10], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[10] node _T_2658 = eq(UInt<4>(0h8), remapindex_10) when _T_2658 : connect remapVecData[10], Queue64_UInt8_8.io.deq.bits connect remapVecValids[10], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[10] node _T_2659 = eq(UInt<4>(0h9), remapindex_10) when _T_2659 : connect remapVecData[10], Queue64_UInt8_9.io.deq.bits connect remapVecValids[10], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[10] node _T_2660 = eq(UInt<4>(0ha), remapindex_10) when _T_2660 : connect remapVecData[10], Queue64_UInt8_10.io.deq.bits connect remapVecValids[10], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[10] node _T_2661 = eq(UInt<4>(0hb), remapindex_10) when _T_2661 : connect remapVecData[10], Queue64_UInt8_11.io.deq.bits connect remapVecValids[10], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[10] node _T_2662 = eq(UInt<4>(0hc), remapindex_10) when _T_2662 : connect remapVecData[10], Queue64_UInt8_12.io.deq.bits connect remapVecValids[10], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[10] node _T_2663 = eq(UInt<4>(0hd), remapindex_10) when _T_2663 : connect remapVecData[10], Queue64_UInt8_13.io.deq.bits connect remapVecValids[10], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[10] node _T_2664 = eq(UInt<4>(0he), remapindex_10) when _T_2664 : connect remapVecData[10], Queue64_UInt8_14.io.deq.bits connect remapVecValids[10], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[10] node _T_2665 = eq(UInt<4>(0hf), remapindex_10) when _T_2665 : connect remapVecData[10], Queue64_UInt8_15.io.deq.bits connect remapVecValids[10], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[10] node _T_2666 = eq(UInt<5>(0h10), remapindex_10) when _T_2666 : connect remapVecData[10], Queue64_UInt8_16.io.deq.bits connect remapVecValids[10], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[10] node _T_2667 = eq(UInt<5>(0h11), remapindex_10) when _T_2667 : connect remapVecData[10], Queue64_UInt8_17.io.deq.bits connect remapVecValids[10], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[10] node _T_2668 = eq(UInt<5>(0h12), remapindex_10) when _T_2668 : connect remapVecData[10], Queue64_UInt8_18.io.deq.bits connect remapVecValids[10], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[10] node _T_2669 = eq(UInt<5>(0h13), remapindex_10) when _T_2669 : connect remapVecData[10], Queue64_UInt8_19.io.deq.bits connect remapVecValids[10], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[10] node _T_2670 = eq(UInt<5>(0h14), remapindex_10) when _T_2670 : connect remapVecData[10], Queue64_UInt8_20.io.deq.bits connect remapVecValids[10], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[10] node _T_2671 = eq(UInt<5>(0h15), remapindex_10) when _T_2671 : connect remapVecData[10], Queue64_UInt8_21.io.deq.bits connect remapVecValids[10], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[10] node _T_2672 = eq(UInt<5>(0h16), remapindex_10) when _T_2672 : connect remapVecData[10], Queue64_UInt8_22.io.deq.bits connect remapVecValids[10], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[10] node _T_2673 = eq(UInt<5>(0h17), remapindex_10) when _T_2673 : connect remapVecData[10], Queue64_UInt8_23.io.deq.bits connect remapVecValids[10], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[10] node _T_2674 = eq(UInt<5>(0h18), remapindex_10) when _T_2674 : connect remapVecData[10], Queue64_UInt8_24.io.deq.bits connect remapVecValids[10], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[10] node _T_2675 = eq(UInt<5>(0h19), remapindex_10) when _T_2675 : connect remapVecData[10], Queue64_UInt8_25.io.deq.bits connect remapVecValids[10], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[10] node _T_2676 = eq(UInt<5>(0h1a), remapindex_10) when _T_2676 : connect remapVecData[10], Queue64_UInt8_26.io.deq.bits connect remapVecValids[10], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[10] node _T_2677 = eq(UInt<5>(0h1b), remapindex_10) when _T_2677 : connect remapVecData[10], Queue64_UInt8_27.io.deq.bits connect remapVecValids[10], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[10] node _T_2678 = eq(UInt<5>(0h1c), remapindex_10) when _T_2678 : connect remapVecData[10], Queue64_UInt8_28.io.deq.bits connect remapVecValids[10], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[10] node _T_2679 = eq(UInt<5>(0h1d), remapindex_10) when _T_2679 : connect remapVecData[10], Queue64_UInt8_29.io.deq.bits connect remapVecValids[10], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[10] node _T_2680 = eq(UInt<5>(0h1e), remapindex_10) when _T_2680 : connect remapVecData[10], Queue64_UInt8_30.io.deq.bits connect remapVecValids[10], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[10] node _T_2681 = eq(UInt<5>(0h1f), remapindex_10) when _T_2681 : connect remapVecData[10], Queue64_UInt8_31.io.deq.bits connect remapVecValids[10], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[10] node _remapindex_T_11 = add(UInt<4>(0hb), read_start_index) node remapindex_11 = rem(_remapindex_T_11, UInt<6>(0h20)) node _T_2682 = eq(UInt<1>(0h0), remapindex_11) when _T_2682 : connect remapVecData[11], Queue64_UInt8.io.deq.bits connect remapVecValids[11], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[11] node _T_2683 = eq(UInt<1>(0h1), remapindex_11) when _T_2683 : connect remapVecData[11], Queue64_UInt8_1.io.deq.bits connect remapVecValids[11], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[11] node _T_2684 = eq(UInt<2>(0h2), remapindex_11) when _T_2684 : connect remapVecData[11], Queue64_UInt8_2.io.deq.bits connect remapVecValids[11], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[11] node _T_2685 = eq(UInt<2>(0h3), remapindex_11) when _T_2685 : connect remapVecData[11], Queue64_UInt8_3.io.deq.bits connect remapVecValids[11], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[11] node _T_2686 = eq(UInt<3>(0h4), remapindex_11) when _T_2686 : connect remapVecData[11], Queue64_UInt8_4.io.deq.bits connect remapVecValids[11], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[11] node _T_2687 = eq(UInt<3>(0h5), remapindex_11) when _T_2687 : connect remapVecData[11], Queue64_UInt8_5.io.deq.bits connect remapVecValids[11], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[11] node _T_2688 = eq(UInt<3>(0h6), remapindex_11) when _T_2688 : connect remapVecData[11], Queue64_UInt8_6.io.deq.bits connect remapVecValids[11], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[11] node _T_2689 = eq(UInt<3>(0h7), remapindex_11) when _T_2689 : connect remapVecData[11], Queue64_UInt8_7.io.deq.bits connect remapVecValids[11], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[11] node _T_2690 = eq(UInt<4>(0h8), remapindex_11) when _T_2690 : connect remapVecData[11], Queue64_UInt8_8.io.deq.bits connect remapVecValids[11], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[11] node _T_2691 = eq(UInt<4>(0h9), remapindex_11) when _T_2691 : connect remapVecData[11], Queue64_UInt8_9.io.deq.bits connect remapVecValids[11], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[11] node _T_2692 = eq(UInt<4>(0ha), remapindex_11) when _T_2692 : connect remapVecData[11], Queue64_UInt8_10.io.deq.bits connect remapVecValids[11], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[11] node _T_2693 = eq(UInt<4>(0hb), remapindex_11) when _T_2693 : connect remapVecData[11], Queue64_UInt8_11.io.deq.bits connect remapVecValids[11], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[11] node _T_2694 = eq(UInt<4>(0hc), remapindex_11) when _T_2694 : connect remapVecData[11], Queue64_UInt8_12.io.deq.bits connect remapVecValids[11], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[11] node _T_2695 = eq(UInt<4>(0hd), remapindex_11) when _T_2695 : connect remapVecData[11], Queue64_UInt8_13.io.deq.bits connect remapVecValids[11], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[11] node _T_2696 = eq(UInt<4>(0he), remapindex_11) when _T_2696 : connect remapVecData[11], Queue64_UInt8_14.io.deq.bits connect remapVecValids[11], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[11] node _T_2697 = eq(UInt<4>(0hf), remapindex_11) when _T_2697 : connect remapVecData[11], Queue64_UInt8_15.io.deq.bits connect remapVecValids[11], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[11] node _T_2698 = eq(UInt<5>(0h10), remapindex_11) when _T_2698 : connect remapVecData[11], Queue64_UInt8_16.io.deq.bits connect remapVecValids[11], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[11] node _T_2699 = eq(UInt<5>(0h11), remapindex_11) when _T_2699 : connect remapVecData[11], Queue64_UInt8_17.io.deq.bits connect remapVecValids[11], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[11] node _T_2700 = eq(UInt<5>(0h12), remapindex_11) when _T_2700 : connect remapVecData[11], Queue64_UInt8_18.io.deq.bits connect remapVecValids[11], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[11] node _T_2701 = eq(UInt<5>(0h13), remapindex_11) when _T_2701 : connect remapVecData[11], Queue64_UInt8_19.io.deq.bits connect remapVecValids[11], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[11] node _T_2702 = eq(UInt<5>(0h14), remapindex_11) when _T_2702 : connect remapVecData[11], Queue64_UInt8_20.io.deq.bits connect remapVecValids[11], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[11] node _T_2703 = eq(UInt<5>(0h15), remapindex_11) when _T_2703 : connect remapVecData[11], Queue64_UInt8_21.io.deq.bits connect remapVecValids[11], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[11] node _T_2704 = eq(UInt<5>(0h16), remapindex_11) when _T_2704 : connect remapVecData[11], Queue64_UInt8_22.io.deq.bits connect remapVecValids[11], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[11] node _T_2705 = eq(UInt<5>(0h17), remapindex_11) when _T_2705 : connect remapVecData[11], Queue64_UInt8_23.io.deq.bits connect remapVecValids[11], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[11] node _T_2706 = eq(UInt<5>(0h18), remapindex_11) when _T_2706 : connect remapVecData[11], Queue64_UInt8_24.io.deq.bits connect remapVecValids[11], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[11] node _T_2707 = eq(UInt<5>(0h19), remapindex_11) when _T_2707 : connect remapVecData[11], Queue64_UInt8_25.io.deq.bits connect remapVecValids[11], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[11] node _T_2708 = eq(UInt<5>(0h1a), remapindex_11) when _T_2708 : connect remapVecData[11], Queue64_UInt8_26.io.deq.bits connect remapVecValids[11], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[11] node _T_2709 = eq(UInt<5>(0h1b), remapindex_11) when _T_2709 : connect remapVecData[11], Queue64_UInt8_27.io.deq.bits connect remapVecValids[11], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[11] node _T_2710 = eq(UInt<5>(0h1c), remapindex_11) when _T_2710 : connect remapVecData[11], Queue64_UInt8_28.io.deq.bits connect remapVecValids[11], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[11] node _T_2711 = eq(UInt<5>(0h1d), remapindex_11) when _T_2711 : connect remapVecData[11], Queue64_UInt8_29.io.deq.bits connect remapVecValids[11], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[11] node _T_2712 = eq(UInt<5>(0h1e), remapindex_11) when _T_2712 : connect remapVecData[11], Queue64_UInt8_30.io.deq.bits connect remapVecValids[11], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[11] node _T_2713 = eq(UInt<5>(0h1f), remapindex_11) when _T_2713 : connect remapVecData[11], Queue64_UInt8_31.io.deq.bits connect remapVecValids[11], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[11] node _remapindex_T_12 = add(UInt<4>(0hc), read_start_index) node remapindex_12 = rem(_remapindex_T_12, UInt<6>(0h20)) node _T_2714 = eq(UInt<1>(0h0), remapindex_12) when _T_2714 : connect remapVecData[12], Queue64_UInt8.io.deq.bits connect remapVecValids[12], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[12] node _T_2715 = eq(UInt<1>(0h1), remapindex_12) when _T_2715 : connect remapVecData[12], Queue64_UInt8_1.io.deq.bits connect remapVecValids[12], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[12] node _T_2716 = eq(UInt<2>(0h2), remapindex_12) when _T_2716 : connect remapVecData[12], Queue64_UInt8_2.io.deq.bits connect remapVecValids[12], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[12] node _T_2717 = eq(UInt<2>(0h3), remapindex_12) when _T_2717 : connect remapVecData[12], Queue64_UInt8_3.io.deq.bits connect remapVecValids[12], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[12] node _T_2718 = eq(UInt<3>(0h4), remapindex_12) when _T_2718 : connect remapVecData[12], Queue64_UInt8_4.io.deq.bits connect remapVecValids[12], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[12] node _T_2719 = eq(UInt<3>(0h5), remapindex_12) when _T_2719 : connect remapVecData[12], Queue64_UInt8_5.io.deq.bits connect remapVecValids[12], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[12] node _T_2720 = eq(UInt<3>(0h6), remapindex_12) when _T_2720 : connect remapVecData[12], Queue64_UInt8_6.io.deq.bits connect remapVecValids[12], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[12] node _T_2721 = eq(UInt<3>(0h7), remapindex_12) when _T_2721 : connect remapVecData[12], Queue64_UInt8_7.io.deq.bits connect remapVecValids[12], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[12] node _T_2722 = eq(UInt<4>(0h8), remapindex_12) when _T_2722 : connect remapVecData[12], Queue64_UInt8_8.io.deq.bits connect remapVecValids[12], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[12] node _T_2723 = eq(UInt<4>(0h9), remapindex_12) when _T_2723 : connect remapVecData[12], Queue64_UInt8_9.io.deq.bits connect remapVecValids[12], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[12] node _T_2724 = eq(UInt<4>(0ha), remapindex_12) when _T_2724 : connect remapVecData[12], Queue64_UInt8_10.io.deq.bits connect remapVecValids[12], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[12] node _T_2725 = eq(UInt<4>(0hb), remapindex_12) when _T_2725 : connect remapVecData[12], Queue64_UInt8_11.io.deq.bits connect remapVecValids[12], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[12] node _T_2726 = eq(UInt<4>(0hc), remapindex_12) when _T_2726 : connect remapVecData[12], Queue64_UInt8_12.io.deq.bits connect remapVecValids[12], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[12] node _T_2727 = eq(UInt<4>(0hd), remapindex_12) when _T_2727 : connect remapVecData[12], Queue64_UInt8_13.io.deq.bits connect remapVecValids[12], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[12] node _T_2728 = eq(UInt<4>(0he), remapindex_12) when _T_2728 : connect remapVecData[12], Queue64_UInt8_14.io.deq.bits connect remapVecValids[12], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[12] node _T_2729 = eq(UInt<4>(0hf), remapindex_12) when _T_2729 : connect remapVecData[12], Queue64_UInt8_15.io.deq.bits connect remapVecValids[12], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[12] node _T_2730 = eq(UInt<5>(0h10), remapindex_12) when _T_2730 : connect remapVecData[12], Queue64_UInt8_16.io.deq.bits connect remapVecValids[12], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[12] node _T_2731 = eq(UInt<5>(0h11), remapindex_12) when _T_2731 : connect remapVecData[12], Queue64_UInt8_17.io.deq.bits connect remapVecValids[12], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[12] node _T_2732 = eq(UInt<5>(0h12), remapindex_12) when _T_2732 : connect remapVecData[12], Queue64_UInt8_18.io.deq.bits connect remapVecValids[12], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[12] node _T_2733 = eq(UInt<5>(0h13), remapindex_12) when _T_2733 : connect remapVecData[12], Queue64_UInt8_19.io.deq.bits connect remapVecValids[12], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[12] node _T_2734 = eq(UInt<5>(0h14), remapindex_12) when _T_2734 : connect remapVecData[12], Queue64_UInt8_20.io.deq.bits connect remapVecValids[12], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[12] node _T_2735 = eq(UInt<5>(0h15), remapindex_12) when _T_2735 : connect remapVecData[12], Queue64_UInt8_21.io.deq.bits connect remapVecValids[12], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[12] node _T_2736 = eq(UInt<5>(0h16), remapindex_12) when _T_2736 : connect remapVecData[12], Queue64_UInt8_22.io.deq.bits connect remapVecValids[12], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[12] node _T_2737 = eq(UInt<5>(0h17), remapindex_12) when _T_2737 : connect remapVecData[12], Queue64_UInt8_23.io.deq.bits connect remapVecValids[12], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[12] node _T_2738 = eq(UInt<5>(0h18), remapindex_12) when _T_2738 : connect remapVecData[12], Queue64_UInt8_24.io.deq.bits connect remapVecValids[12], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[12] node _T_2739 = eq(UInt<5>(0h19), remapindex_12) when _T_2739 : connect remapVecData[12], Queue64_UInt8_25.io.deq.bits connect remapVecValids[12], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[12] node _T_2740 = eq(UInt<5>(0h1a), remapindex_12) when _T_2740 : connect remapVecData[12], Queue64_UInt8_26.io.deq.bits connect remapVecValids[12], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[12] node _T_2741 = eq(UInt<5>(0h1b), remapindex_12) when _T_2741 : connect remapVecData[12], Queue64_UInt8_27.io.deq.bits connect remapVecValids[12], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[12] node _T_2742 = eq(UInt<5>(0h1c), remapindex_12) when _T_2742 : connect remapVecData[12], Queue64_UInt8_28.io.deq.bits connect remapVecValids[12], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[12] node _T_2743 = eq(UInt<5>(0h1d), remapindex_12) when _T_2743 : connect remapVecData[12], Queue64_UInt8_29.io.deq.bits connect remapVecValids[12], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[12] node _T_2744 = eq(UInt<5>(0h1e), remapindex_12) when _T_2744 : connect remapVecData[12], Queue64_UInt8_30.io.deq.bits connect remapVecValids[12], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[12] node _T_2745 = eq(UInt<5>(0h1f), remapindex_12) when _T_2745 : connect remapVecData[12], Queue64_UInt8_31.io.deq.bits connect remapVecValids[12], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[12] node _remapindex_T_13 = add(UInt<4>(0hd), read_start_index) node remapindex_13 = rem(_remapindex_T_13, UInt<6>(0h20)) node _T_2746 = eq(UInt<1>(0h0), remapindex_13) when _T_2746 : connect remapVecData[13], Queue64_UInt8.io.deq.bits connect remapVecValids[13], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[13] node _T_2747 = eq(UInt<1>(0h1), remapindex_13) when _T_2747 : connect remapVecData[13], Queue64_UInt8_1.io.deq.bits connect remapVecValids[13], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[13] node _T_2748 = eq(UInt<2>(0h2), remapindex_13) when _T_2748 : connect remapVecData[13], Queue64_UInt8_2.io.deq.bits connect remapVecValids[13], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[13] node _T_2749 = eq(UInt<2>(0h3), remapindex_13) when _T_2749 : connect remapVecData[13], Queue64_UInt8_3.io.deq.bits connect remapVecValids[13], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[13] node _T_2750 = eq(UInt<3>(0h4), remapindex_13) when _T_2750 : connect remapVecData[13], Queue64_UInt8_4.io.deq.bits connect remapVecValids[13], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[13] node _T_2751 = eq(UInt<3>(0h5), remapindex_13) when _T_2751 : connect remapVecData[13], Queue64_UInt8_5.io.deq.bits connect remapVecValids[13], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[13] node _T_2752 = eq(UInt<3>(0h6), remapindex_13) when _T_2752 : connect remapVecData[13], Queue64_UInt8_6.io.deq.bits connect remapVecValids[13], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[13] node _T_2753 = eq(UInt<3>(0h7), remapindex_13) when _T_2753 : connect remapVecData[13], Queue64_UInt8_7.io.deq.bits connect remapVecValids[13], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[13] node _T_2754 = eq(UInt<4>(0h8), remapindex_13) when _T_2754 : connect remapVecData[13], Queue64_UInt8_8.io.deq.bits connect remapVecValids[13], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[13] node _T_2755 = eq(UInt<4>(0h9), remapindex_13) when _T_2755 : connect remapVecData[13], Queue64_UInt8_9.io.deq.bits connect remapVecValids[13], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[13] node _T_2756 = eq(UInt<4>(0ha), remapindex_13) when _T_2756 : connect remapVecData[13], Queue64_UInt8_10.io.deq.bits connect remapVecValids[13], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[13] node _T_2757 = eq(UInt<4>(0hb), remapindex_13) when _T_2757 : connect remapVecData[13], Queue64_UInt8_11.io.deq.bits connect remapVecValids[13], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[13] node _T_2758 = eq(UInt<4>(0hc), remapindex_13) when _T_2758 : connect remapVecData[13], Queue64_UInt8_12.io.deq.bits connect remapVecValids[13], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[13] node _T_2759 = eq(UInt<4>(0hd), remapindex_13) when _T_2759 : connect remapVecData[13], Queue64_UInt8_13.io.deq.bits connect remapVecValids[13], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[13] node _T_2760 = eq(UInt<4>(0he), remapindex_13) when _T_2760 : connect remapVecData[13], Queue64_UInt8_14.io.deq.bits connect remapVecValids[13], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[13] node _T_2761 = eq(UInt<4>(0hf), remapindex_13) when _T_2761 : connect remapVecData[13], Queue64_UInt8_15.io.deq.bits connect remapVecValids[13], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[13] node _T_2762 = eq(UInt<5>(0h10), remapindex_13) when _T_2762 : connect remapVecData[13], Queue64_UInt8_16.io.deq.bits connect remapVecValids[13], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[13] node _T_2763 = eq(UInt<5>(0h11), remapindex_13) when _T_2763 : connect remapVecData[13], Queue64_UInt8_17.io.deq.bits connect remapVecValids[13], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[13] node _T_2764 = eq(UInt<5>(0h12), remapindex_13) when _T_2764 : connect remapVecData[13], Queue64_UInt8_18.io.deq.bits connect remapVecValids[13], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[13] node _T_2765 = eq(UInt<5>(0h13), remapindex_13) when _T_2765 : connect remapVecData[13], Queue64_UInt8_19.io.deq.bits connect remapVecValids[13], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[13] node _T_2766 = eq(UInt<5>(0h14), remapindex_13) when _T_2766 : connect remapVecData[13], Queue64_UInt8_20.io.deq.bits connect remapVecValids[13], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[13] node _T_2767 = eq(UInt<5>(0h15), remapindex_13) when _T_2767 : connect remapVecData[13], Queue64_UInt8_21.io.deq.bits connect remapVecValids[13], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[13] node _T_2768 = eq(UInt<5>(0h16), remapindex_13) when _T_2768 : connect remapVecData[13], Queue64_UInt8_22.io.deq.bits connect remapVecValids[13], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[13] node _T_2769 = eq(UInt<5>(0h17), remapindex_13) when _T_2769 : connect remapVecData[13], Queue64_UInt8_23.io.deq.bits connect remapVecValids[13], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[13] node _T_2770 = eq(UInt<5>(0h18), remapindex_13) when _T_2770 : connect remapVecData[13], Queue64_UInt8_24.io.deq.bits connect remapVecValids[13], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[13] node _T_2771 = eq(UInt<5>(0h19), remapindex_13) when _T_2771 : connect remapVecData[13], Queue64_UInt8_25.io.deq.bits connect remapVecValids[13], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[13] node _T_2772 = eq(UInt<5>(0h1a), remapindex_13) when _T_2772 : connect remapVecData[13], Queue64_UInt8_26.io.deq.bits connect remapVecValids[13], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[13] node _T_2773 = eq(UInt<5>(0h1b), remapindex_13) when _T_2773 : connect remapVecData[13], Queue64_UInt8_27.io.deq.bits connect remapVecValids[13], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[13] node _T_2774 = eq(UInt<5>(0h1c), remapindex_13) when _T_2774 : connect remapVecData[13], Queue64_UInt8_28.io.deq.bits connect remapVecValids[13], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[13] node _T_2775 = eq(UInt<5>(0h1d), remapindex_13) when _T_2775 : connect remapVecData[13], Queue64_UInt8_29.io.deq.bits connect remapVecValids[13], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[13] node _T_2776 = eq(UInt<5>(0h1e), remapindex_13) when _T_2776 : connect remapVecData[13], Queue64_UInt8_30.io.deq.bits connect remapVecValids[13], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[13] node _T_2777 = eq(UInt<5>(0h1f), remapindex_13) when _T_2777 : connect remapVecData[13], Queue64_UInt8_31.io.deq.bits connect remapVecValids[13], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[13] node _remapindex_T_14 = add(UInt<4>(0he), read_start_index) node remapindex_14 = rem(_remapindex_T_14, UInt<6>(0h20)) node _T_2778 = eq(UInt<1>(0h0), remapindex_14) when _T_2778 : connect remapVecData[14], Queue64_UInt8.io.deq.bits connect remapVecValids[14], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[14] node _T_2779 = eq(UInt<1>(0h1), remapindex_14) when _T_2779 : connect remapVecData[14], Queue64_UInt8_1.io.deq.bits connect remapVecValids[14], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[14] node _T_2780 = eq(UInt<2>(0h2), remapindex_14) when _T_2780 : connect remapVecData[14], Queue64_UInt8_2.io.deq.bits connect remapVecValids[14], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[14] node _T_2781 = eq(UInt<2>(0h3), remapindex_14) when _T_2781 : connect remapVecData[14], Queue64_UInt8_3.io.deq.bits connect remapVecValids[14], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[14] node _T_2782 = eq(UInt<3>(0h4), remapindex_14) when _T_2782 : connect remapVecData[14], Queue64_UInt8_4.io.deq.bits connect remapVecValids[14], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[14] node _T_2783 = eq(UInt<3>(0h5), remapindex_14) when _T_2783 : connect remapVecData[14], Queue64_UInt8_5.io.deq.bits connect remapVecValids[14], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[14] node _T_2784 = eq(UInt<3>(0h6), remapindex_14) when _T_2784 : connect remapVecData[14], Queue64_UInt8_6.io.deq.bits connect remapVecValids[14], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[14] node _T_2785 = eq(UInt<3>(0h7), remapindex_14) when _T_2785 : connect remapVecData[14], Queue64_UInt8_7.io.deq.bits connect remapVecValids[14], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[14] node _T_2786 = eq(UInt<4>(0h8), remapindex_14) when _T_2786 : connect remapVecData[14], Queue64_UInt8_8.io.deq.bits connect remapVecValids[14], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[14] node _T_2787 = eq(UInt<4>(0h9), remapindex_14) when _T_2787 : connect remapVecData[14], Queue64_UInt8_9.io.deq.bits connect remapVecValids[14], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[14] node _T_2788 = eq(UInt<4>(0ha), remapindex_14) when _T_2788 : connect remapVecData[14], Queue64_UInt8_10.io.deq.bits connect remapVecValids[14], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[14] node _T_2789 = eq(UInt<4>(0hb), remapindex_14) when _T_2789 : connect remapVecData[14], Queue64_UInt8_11.io.deq.bits connect remapVecValids[14], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[14] node _T_2790 = eq(UInt<4>(0hc), remapindex_14) when _T_2790 : connect remapVecData[14], Queue64_UInt8_12.io.deq.bits connect remapVecValids[14], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[14] node _T_2791 = eq(UInt<4>(0hd), remapindex_14) when _T_2791 : connect remapVecData[14], Queue64_UInt8_13.io.deq.bits connect remapVecValids[14], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[14] node _T_2792 = eq(UInt<4>(0he), remapindex_14) when _T_2792 : connect remapVecData[14], Queue64_UInt8_14.io.deq.bits connect remapVecValids[14], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[14] node _T_2793 = eq(UInt<4>(0hf), remapindex_14) when _T_2793 : connect remapVecData[14], Queue64_UInt8_15.io.deq.bits connect remapVecValids[14], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[14] node _T_2794 = eq(UInt<5>(0h10), remapindex_14) when _T_2794 : connect remapVecData[14], Queue64_UInt8_16.io.deq.bits connect remapVecValids[14], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[14] node _T_2795 = eq(UInt<5>(0h11), remapindex_14) when _T_2795 : connect remapVecData[14], Queue64_UInt8_17.io.deq.bits connect remapVecValids[14], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[14] node _T_2796 = eq(UInt<5>(0h12), remapindex_14) when _T_2796 : connect remapVecData[14], Queue64_UInt8_18.io.deq.bits connect remapVecValids[14], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[14] node _T_2797 = eq(UInt<5>(0h13), remapindex_14) when _T_2797 : connect remapVecData[14], Queue64_UInt8_19.io.deq.bits connect remapVecValids[14], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[14] node _T_2798 = eq(UInt<5>(0h14), remapindex_14) when _T_2798 : connect remapVecData[14], Queue64_UInt8_20.io.deq.bits connect remapVecValids[14], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[14] node _T_2799 = eq(UInt<5>(0h15), remapindex_14) when _T_2799 : connect remapVecData[14], Queue64_UInt8_21.io.deq.bits connect remapVecValids[14], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[14] node _T_2800 = eq(UInt<5>(0h16), remapindex_14) when _T_2800 : connect remapVecData[14], Queue64_UInt8_22.io.deq.bits connect remapVecValids[14], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[14] node _T_2801 = eq(UInt<5>(0h17), remapindex_14) when _T_2801 : connect remapVecData[14], Queue64_UInt8_23.io.deq.bits connect remapVecValids[14], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[14] node _T_2802 = eq(UInt<5>(0h18), remapindex_14) when _T_2802 : connect remapVecData[14], Queue64_UInt8_24.io.deq.bits connect remapVecValids[14], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[14] node _T_2803 = eq(UInt<5>(0h19), remapindex_14) when _T_2803 : connect remapVecData[14], Queue64_UInt8_25.io.deq.bits connect remapVecValids[14], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[14] node _T_2804 = eq(UInt<5>(0h1a), remapindex_14) when _T_2804 : connect remapVecData[14], Queue64_UInt8_26.io.deq.bits connect remapVecValids[14], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[14] node _T_2805 = eq(UInt<5>(0h1b), remapindex_14) when _T_2805 : connect remapVecData[14], Queue64_UInt8_27.io.deq.bits connect remapVecValids[14], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[14] node _T_2806 = eq(UInt<5>(0h1c), remapindex_14) when _T_2806 : connect remapVecData[14], Queue64_UInt8_28.io.deq.bits connect remapVecValids[14], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[14] node _T_2807 = eq(UInt<5>(0h1d), remapindex_14) when _T_2807 : connect remapVecData[14], Queue64_UInt8_29.io.deq.bits connect remapVecValids[14], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[14] node _T_2808 = eq(UInt<5>(0h1e), remapindex_14) when _T_2808 : connect remapVecData[14], Queue64_UInt8_30.io.deq.bits connect remapVecValids[14], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[14] node _T_2809 = eq(UInt<5>(0h1f), remapindex_14) when _T_2809 : connect remapVecData[14], Queue64_UInt8_31.io.deq.bits connect remapVecValids[14], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[14] node _remapindex_T_15 = add(UInt<4>(0hf), read_start_index) node remapindex_15 = rem(_remapindex_T_15, UInt<6>(0h20)) node _T_2810 = eq(UInt<1>(0h0), remapindex_15) when _T_2810 : connect remapVecData[15], Queue64_UInt8.io.deq.bits connect remapVecValids[15], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[15] node _T_2811 = eq(UInt<1>(0h1), remapindex_15) when _T_2811 : connect remapVecData[15], Queue64_UInt8_1.io.deq.bits connect remapVecValids[15], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[15] node _T_2812 = eq(UInt<2>(0h2), remapindex_15) when _T_2812 : connect remapVecData[15], Queue64_UInt8_2.io.deq.bits connect remapVecValids[15], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[15] node _T_2813 = eq(UInt<2>(0h3), remapindex_15) when _T_2813 : connect remapVecData[15], Queue64_UInt8_3.io.deq.bits connect remapVecValids[15], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[15] node _T_2814 = eq(UInt<3>(0h4), remapindex_15) when _T_2814 : connect remapVecData[15], Queue64_UInt8_4.io.deq.bits connect remapVecValids[15], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[15] node _T_2815 = eq(UInt<3>(0h5), remapindex_15) when _T_2815 : connect remapVecData[15], Queue64_UInt8_5.io.deq.bits connect remapVecValids[15], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[15] node _T_2816 = eq(UInt<3>(0h6), remapindex_15) when _T_2816 : connect remapVecData[15], Queue64_UInt8_6.io.deq.bits connect remapVecValids[15], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[15] node _T_2817 = eq(UInt<3>(0h7), remapindex_15) when _T_2817 : connect remapVecData[15], Queue64_UInt8_7.io.deq.bits connect remapVecValids[15], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[15] node _T_2818 = eq(UInt<4>(0h8), remapindex_15) when _T_2818 : connect remapVecData[15], Queue64_UInt8_8.io.deq.bits connect remapVecValids[15], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[15] node _T_2819 = eq(UInt<4>(0h9), remapindex_15) when _T_2819 : connect remapVecData[15], Queue64_UInt8_9.io.deq.bits connect remapVecValids[15], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[15] node _T_2820 = eq(UInt<4>(0ha), remapindex_15) when _T_2820 : connect remapVecData[15], Queue64_UInt8_10.io.deq.bits connect remapVecValids[15], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[15] node _T_2821 = eq(UInt<4>(0hb), remapindex_15) when _T_2821 : connect remapVecData[15], Queue64_UInt8_11.io.deq.bits connect remapVecValids[15], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[15] node _T_2822 = eq(UInt<4>(0hc), remapindex_15) when _T_2822 : connect remapVecData[15], Queue64_UInt8_12.io.deq.bits connect remapVecValids[15], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[15] node _T_2823 = eq(UInt<4>(0hd), remapindex_15) when _T_2823 : connect remapVecData[15], Queue64_UInt8_13.io.deq.bits connect remapVecValids[15], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[15] node _T_2824 = eq(UInt<4>(0he), remapindex_15) when _T_2824 : connect remapVecData[15], Queue64_UInt8_14.io.deq.bits connect remapVecValids[15], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[15] node _T_2825 = eq(UInt<4>(0hf), remapindex_15) when _T_2825 : connect remapVecData[15], Queue64_UInt8_15.io.deq.bits connect remapVecValids[15], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[15] node _T_2826 = eq(UInt<5>(0h10), remapindex_15) when _T_2826 : connect remapVecData[15], Queue64_UInt8_16.io.deq.bits connect remapVecValids[15], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[15] node _T_2827 = eq(UInt<5>(0h11), remapindex_15) when _T_2827 : connect remapVecData[15], Queue64_UInt8_17.io.deq.bits connect remapVecValids[15], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[15] node _T_2828 = eq(UInt<5>(0h12), remapindex_15) when _T_2828 : connect remapVecData[15], Queue64_UInt8_18.io.deq.bits connect remapVecValids[15], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[15] node _T_2829 = eq(UInt<5>(0h13), remapindex_15) when _T_2829 : connect remapVecData[15], Queue64_UInt8_19.io.deq.bits connect remapVecValids[15], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[15] node _T_2830 = eq(UInt<5>(0h14), remapindex_15) when _T_2830 : connect remapVecData[15], Queue64_UInt8_20.io.deq.bits connect remapVecValids[15], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[15] node _T_2831 = eq(UInt<5>(0h15), remapindex_15) when _T_2831 : connect remapVecData[15], Queue64_UInt8_21.io.deq.bits connect remapVecValids[15], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[15] node _T_2832 = eq(UInt<5>(0h16), remapindex_15) when _T_2832 : connect remapVecData[15], Queue64_UInt8_22.io.deq.bits connect remapVecValids[15], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[15] node _T_2833 = eq(UInt<5>(0h17), remapindex_15) when _T_2833 : connect remapVecData[15], Queue64_UInt8_23.io.deq.bits connect remapVecValids[15], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[15] node _T_2834 = eq(UInt<5>(0h18), remapindex_15) when _T_2834 : connect remapVecData[15], Queue64_UInt8_24.io.deq.bits connect remapVecValids[15], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[15] node _T_2835 = eq(UInt<5>(0h19), remapindex_15) when _T_2835 : connect remapVecData[15], Queue64_UInt8_25.io.deq.bits connect remapVecValids[15], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[15] node _T_2836 = eq(UInt<5>(0h1a), remapindex_15) when _T_2836 : connect remapVecData[15], Queue64_UInt8_26.io.deq.bits connect remapVecValids[15], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[15] node _T_2837 = eq(UInt<5>(0h1b), remapindex_15) when _T_2837 : connect remapVecData[15], Queue64_UInt8_27.io.deq.bits connect remapVecValids[15], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[15] node _T_2838 = eq(UInt<5>(0h1c), remapindex_15) when _T_2838 : connect remapVecData[15], Queue64_UInt8_28.io.deq.bits connect remapVecValids[15], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[15] node _T_2839 = eq(UInt<5>(0h1d), remapindex_15) when _T_2839 : connect remapVecData[15], Queue64_UInt8_29.io.deq.bits connect remapVecValids[15], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[15] node _T_2840 = eq(UInt<5>(0h1e), remapindex_15) when _T_2840 : connect remapVecData[15], Queue64_UInt8_30.io.deq.bits connect remapVecValids[15], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[15] node _T_2841 = eq(UInt<5>(0h1f), remapindex_15) when _T_2841 : connect remapVecData[15], Queue64_UInt8_31.io.deq.bits connect remapVecValids[15], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[15] node _remapindex_T_16 = add(UInt<5>(0h10), read_start_index) node remapindex_16 = rem(_remapindex_T_16, UInt<6>(0h20)) node _T_2842 = eq(UInt<1>(0h0), remapindex_16) when _T_2842 : connect remapVecData[16], Queue64_UInt8.io.deq.bits connect remapVecValids[16], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[16] node _T_2843 = eq(UInt<1>(0h1), remapindex_16) when _T_2843 : connect remapVecData[16], Queue64_UInt8_1.io.deq.bits connect remapVecValids[16], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[16] node _T_2844 = eq(UInt<2>(0h2), remapindex_16) when _T_2844 : connect remapVecData[16], Queue64_UInt8_2.io.deq.bits connect remapVecValids[16], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[16] node _T_2845 = eq(UInt<2>(0h3), remapindex_16) when _T_2845 : connect remapVecData[16], Queue64_UInt8_3.io.deq.bits connect remapVecValids[16], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[16] node _T_2846 = eq(UInt<3>(0h4), remapindex_16) when _T_2846 : connect remapVecData[16], Queue64_UInt8_4.io.deq.bits connect remapVecValids[16], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[16] node _T_2847 = eq(UInt<3>(0h5), remapindex_16) when _T_2847 : connect remapVecData[16], Queue64_UInt8_5.io.deq.bits connect remapVecValids[16], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[16] node _T_2848 = eq(UInt<3>(0h6), remapindex_16) when _T_2848 : connect remapVecData[16], Queue64_UInt8_6.io.deq.bits connect remapVecValids[16], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[16] node _T_2849 = eq(UInt<3>(0h7), remapindex_16) when _T_2849 : connect remapVecData[16], Queue64_UInt8_7.io.deq.bits connect remapVecValids[16], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[16] node _T_2850 = eq(UInt<4>(0h8), remapindex_16) when _T_2850 : connect remapVecData[16], Queue64_UInt8_8.io.deq.bits connect remapVecValids[16], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[16] node _T_2851 = eq(UInt<4>(0h9), remapindex_16) when _T_2851 : connect remapVecData[16], Queue64_UInt8_9.io.deq.bits connect remapVecValids[16], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[16] node _T_2852 = eq(UInt<4>(0ha), remapindex_16) when _T_2852 : connect remapVecData[16], Queue64_UInt8_10.io.deq.bits connect remapVecValids[16], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[16] node _T_2853 = eq(UInt<4>(0hb), remapindex_16) when _T_2853 : connect remapVecData[16], Queue64_UInt8_11.io.deq.bits connect remapVecValids[16], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[16] node _T_2854 = eq(UInt<4>(0hc), remapindex_16) when _T_2854 : connect remapVecData[16], Queue64_UInt8_12.io.deq.bits connect remapVecValids[16], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[16] node _T_2855 = eq(UInt<4>(0hd), remapindex_16) when _T_2855 : connect remapVecData[16], Queue64_UInt8_13.io.deq.bits connect remapVecValids[16], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[16] node _T_2856 = eq(UInt<4>(0he), remapindex_16) when _T_2856 : connect remapVecData[16], Queue64_UInt8_14.io.deq.bits connect remapVecValids[16], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[16] node _T_2857 = eq(UInt<4>(0hf), remapindex_16) when _T_2857 : connect remapVecData[16], Queue64_UInt8_15.io.deq.bits connect remapVecValids[16], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[16] node _T_2858 = eq(UInt<5>(0h10), remapindex_16) when _T_2858 : connect remapVecData[16], Queue64_UInt8_16.io.deq.bits connect remapVecValids[16], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[16] node _T_2859 = eq(UInt<5>(0h11), remapindex_16) when _T_2859 : connect remapVecData[16], Queue64_UInt8_17.io.deq.bits connect remapVecValids[16], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[16] node _T_2860 = eq(UInt<5>(0h12), remapindex_16) when _T_2860 : connect remapVecData[16], Queue64_UInt8_18.io.deq.bits connect remapVecValids[16], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[16] node _T_2861 = eq(UInt<5>(0h13), remapindex_16) when _T_2861 : connect remapVecData[16], Queue64_UInt8_19.io.deq.bits connect remapVecValids[16], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[16] node _T_2862 = eq(UInt<5>(0h14), remapindex_16) when _T_2862 : connect remapVecData[16], Queue64_UInt8_20.io.deq.bits connect remapVecValids[16], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[16] node _T_2863 = eq(UInt<5>(0h15), remapindex_16) when _T_2863 : connect remapVecData[16], Queue64_UInt8_21.io.deq.bits connect remapVecValids[16], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[16] node _T_2864 = eq(UInt<5>(0h16), remapindex_16) when _T_2864 : connect remapVecData[16], Queue64_UInt8_22.io.deq.bits connect remapVecValids[16], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[16] node _T_2865 = eq(UInt<5>(0h17), remapindex_16) when _T_2865 : connect remapVecData[16], Queue64_UInt8_23.io.deq.bits connect remapVecValids[16], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[16] node _T_2866 = eq(UInt<5>(0h18), remapindex_16) when _T_2866 : connect remapVecData[16], Queue64_UInt8_24.io.deq.bits connect remapVecValids[16], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[16] node _T_2867 = eq(UInt<5>(0h19), remapindex_16) when _T_2867 : connect remapVecData[16], Queue64_UInt8_25.io.deq.bits connect remapVecValids[16], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[16] node _T_2868 = eq(UInt<5>(0h1a), remapindex_16) when _T_2868 : connect remapVecData[16], Queue64_UInt8_26.io.deq.bits connect remapVecValids[16], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[16] node _T_2869 = eq(UInt<5>(0h1b), remapindex_16) when _T_2869 : connect remapVecData[16], Queue64_UInt8_27.io.deq.bits connect remapVecValids[16], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[16] node _T_2870 = eq(UInt<5>(0h1c), remapindex_16) when _T_2870 : connect remapVecData[16], Queue64_UInt8_28.io.deq.bits connect remapVecValids[16], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[16] node _T_2871 = eq(UInt<5>(0h1d), remapindex_16) when _T_2871 : connect remapVecData[16], Queue64_UInt8_29.io.deq.bits connect remapVecValids[16], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[16] node _T_2872 = eq(UInt<5>(0h1e), remapindex_16) when _T_2872 : connect remapVecData[16], Queue64_UInt8_30.io.deq.bits connect remapVecValids[16], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[16] node _T_2873 = eq(UInt<5>(0h1f), remapindex_16) when _T_2873 : connect remapVecData[16], Queue64_UInt8_31.io.deq.bits connect remapVecValids[16], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[16] node _remapindex_T_17 = add(UInt<5>(0h11), read_start_index) node remapindex_17 = rem(_remapindex_T_17, UInt<6>(0h20)) node _T_2874 = eq(UInt<1>(0h0), remapindex_17) when _T_2874 : connect remapVecData[17], Queue64_UInt8.io.deq.bits connect remapVecValids[17], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[17] node _T_2875 = eq(UInt<1>(0h1), remapindex_17) when _T_2875 : connect remapVecData[17], Queue64_UInt8_1.io.deq.bits connect remapVecValids[17], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[17] node _T_2876 = eq(UInt<2>(0h2), remapindex_17) when _T_2876 : connect remapVecData[17], Queue64_UInt8_2.io.deq.bits connect remapVecValids[17], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[17] node _T_2877 = eq(UInt<2>(0h3), remapindex_17) when _T_2877 : connect remapVecData[17], Queue64_UInt8_3.io.deq.bits connect remapVecValids[17], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[17] node _T_2878 = eq(UInt<3>(0h4), remapindex_17) when _T_2878 : connect remapVecData[17], Queue64_UInt8_4.io.deq.bits connect remapVecValids[17], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[17] node _T_2879 = eq(UInt<3>(0h5), remapindex_17) when _T_2879 : connect remapVecData[17], Queue64_UInt8_5.io.deq.bits connect remapVecValids[17], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[17] node _T_2880 = eq(UInt<3>(0h6), remapindex_17) when _T_2880 : connect remapVecData[17], Queue64_UInt8_6.io.deq.bits connect remapVecValids[17], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[17] node _T_2881 = eq(UInt<3>(0h7), remapindex_17) when _T_2881 : connect remapVecData[17], Queue64_UInt8_7.io.deq.bits connect remapVecValids[17], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[17] node _T_2882 = eq(UInt<4>(0h8), remapindex_17) when _T_2882 : connect remapVecData[17], Queue64_UInt8_8.io.deq.bits connect remapVecValids[17], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[17] node _T_2883 = eq(UInt<4>(0h9), remapindex_17) when _T_2883 : connect remapVecData[17], Queue64_UInt8_9.io.deq.bits connect remapVecValids[17], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[17] node _T_2884 = eq(UInt<4>(0ha), remapindex_17) when _T_2884 : connect remapVecData[17], Queue64_UInt8_10.io.deq.bits connect remapVecValids[17], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[17] node _T_2885 = eq(UInt<4>(0hb), remapindex_17) when _T_2885 : connect remapVecData[17], Queue64_UInt8_11.io.deq.bits connect remapVecValids[17], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[17] node _T_2886 = eq(UInt<4>(0hc), remapindex_17) when _T_2886 : connect remapVecData[17], Queue64_UInt8_12.io.deq.bits connect remapVecValids[17], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[17] node _T_2887 = eq(UInt<4>(0hd), remapindex_17) when _T_2887 : connect remapVecData[17], Queue64_UInt8_13.io.deq.bits connect remapVecValids[17], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[17] node _T_2888 = eq(UInt<4>(0he), remapindex_17) when _T_2888 : connect remapVecData[17], Queue64_UInt8_14.io.deq.bits connect remapVecValids[17], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[17] node _T_2889 = eq(UInt<4>(0hf), remapindex_17) when _T_2889 : connect remapVecData[17], Queue64_UInt8_15.io.deq.bits connect remapVecValids[17], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[17] node _T_2890 = eq(UInt<5>(0h10), remapindex_17) when _T_2890 : connect remapVecData[17], Queue64_UInt8_16.io.deq.bits connect remapVecValids[17], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[17] node _T_2891 = eq(UInt<5>(0h11), remapindex_17) when _T_2891 : connect remapVecData[17], Queue64_UInt8_17.io.deq.bits connect remapVecValids[17], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[17] node _T_2892 = eq(UInt<5>(0h12), remapindex_17) when _T_2892 : connect remapVecData[17], Queue64_UInt8_18.io.deq.bits connect remapVecValids[17], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[17] node _T_2893 = eq(UInt<5>(0h13), remapindex_17) when _T_2893 : connect remapVecData[17], Queue64_UInt8_19.io.deq.bits connect remapVecValids[17], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[17] node _T_2894 = eq(UInt<5>(0h14), remapindex_17) when _T_2894 : connect remapVecData[17], Queue64_UInt8_20.io.deq.bits connect remapVecValids[17], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[17] node _T_2895 = eq(UInt<5>(0h15), remapindex_17) when _T_2895 : connect remapVecData[17], Queue64_UInt8_21.io.deq.bits connect remapVecValids[17], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[17] node _T_2896 = eq(UInt<5>(0h16), remapindex_17) when _T_2896 : connect remapVecData[17], Queue64_UInt8_22.io.deq.bits connect remapVecValids[17], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[17] node _T_2897 = eq(UInt<5>(0h17), remapindex_17) when _T_2897 : connect remapVecData[17], Queue64_UInt8_23.io.deq.bits connect remapVecValids[17], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[17] node _T_2898 = eq(UInt<5>(0h18), remapindex_17) when _T_2898 : connect remapVecData[17], Queue64_UInt8_24.io.deq.bits connect remapVecValids[17], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[17] node _T_2899 = eq(UInt<5>(0h19), remapindex_17) when _T_2899 : connect remapVecData[17], Queue64_UInt8_25.io.deq.bits connect remapVecValids[17], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[17] node _T_2900 = eq(UInt<5>(0h1a), remapindex_17) when _T_2900 : connect remapVecData[17], Queue64_UInt8_26.io.deq.bits connect remapVecValids[17], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[17] node _T_2901 = eq(UInt<5>(0h1b), remapindex_17) when _T_2901 : connect remapVecData[17], Queue64_UInt8_27.io.deq.bits connect remapVecValids[17], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[17] node _T_2902 = eq(UInt<5>(0h1c), remapindex_17) when _T_2902 : connect remapVecData[17], Queue64_UInt8_28.io.deq.bits connect remapVecValids[17], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[17] node _T_2903 = eq(UInt<5>(0h1d), remapindex_17) when _T_2903 : connect remapVecData[17], Queue64_UInt8_29.io.deq.bits connect remapVecValids[17], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[17] node _T_2904 = eq(UInt<5>(0h1e), remapindex_17) when _T_2904 : connect remapVecData[17], Queue64_UInt8_30.io.deq.bits connect remapVecValids[17], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[17] node _T_2905 = eq(UInt<5>(0h1f), remapindex_17) when _T_2905 : connect remapVecData[17], Queue64_UInt8_31.io.deq.bits connect remapVecValids[17], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[17] node _remapindex_T_18 = add(UInt<5>(0h12), read_start_index) node remapindex_18 = rem(_remapindex_T_18, UInt<6>(0h20)) node _T_2906 = eq(UInt<1>(0h0), remapindex_18) when _T_2906 : connect remapVecData[18], Queue64_UInt8.io.deq.bits connect remapVecValids[18], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[18] node _T_2907 = eq(UInt<1>(0h1), remapindex_18) when _T_2907 : connect remapVecData[18], Queue64_UInt8_1.io.deq.bits connect remapVecValids[18], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[18] node _T_2908 = eq(UInt<2>(0h2), remapindex_18) when _T_2908 : connect remapVecData[18], Queue64_UInt8_2.io.deq.bits connect remapVecValids[18], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[18] node _T_2909 = eq(UInt<2>(0h3), remapindex_18) when _T_2909 : connect remapVecData[18], Queue64_UInt8_3.io.deq.bits connect remapVecValids[18], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[18] node _T_2910 = eq(UInt<3>(0h4), remapindex_18) when _T_2910 : connect remapVecData[18], Queue64_UInt8_4.io.deq.bits connect remapVecValids[18], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[18] node _T_2911 = eq(UInt<3>(0h5), remapindex_18) when _T_2911 : connect remapVecData[18], Queue64_UInt8_5.io.deq.bits connect remapVecValids[18], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[18] node _T_2912 = eq(UInt<3>(0h6), remapindex_18) when _T_2912 : connect remapVecData[18], Queue64_UInt8_6.io.deq.bits connect remapVecValids[18], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[18] node _T_2913 = eq(UInt<3>(0h7), remapindex_18) when _T_2913 : connect remapVecData[18], Queue64_UInt8_7.io.deq.bits connect remapVecValids[18], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[18] node _T_2914 = eq(UInt<4>(0h8), remapindex_18) when _T_2914 : connect remapVecData[18], Queue64_UInt8_8.io.deq.bits connect remapVecValids[18], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[18] node _T_2915 = eq(UInt<4>(0h9), remapindex_18) when _T_2915 : connect remapVecData[18], Queue64_UInt8_9.io.deq.bits connect remapVecValids[18], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[18] node _T_2916 = eq(UInt<4>(0ha), remapindex_18) when _T_2916 : connect remapVecData[18], Queue64_UInt8_10.io.deq.bits connect remapVecValids[18], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[18] node _T_2917 = eq(UInt<4>(0hb), remapindex_18) when _T_2917 : connect remapVecData[18], Queue64_UInt8_11.io.deq.bits connect remapVecValids[18], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[18] node _T_2918 = eq(UInt<4>(0hc), remapindex_18) when _T_2918 : connect remapVecData[18], Queue64_UInt8_12.io.deq.bits connect remapVecValids[18], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[18] node _T_2919 = eq(UInt<4>(0hd), remapindex_18) when _T_2919 : connect remapVecData[18], Queue64_UInt8_13.io.deq.bits connect remapVecValids[18], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[18] node _T_2920 = eq(UInt<4>(0he), remapindex_18) when _T_2920 : connect remapVecData[18], Queue64_UInt8_14.io.deq.bits connect remapVecValids[18], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[18] node _T_2921 = eq(UInt<4>(0hf), remapindex_18) when _T_2921 : connect remapVecData[18], Queue64_UInt8_15.io.deq.bits connect remapVecValids[18], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[18] node _T_2922 = eq(UInt<5>(0h10), remapindex_18) when _T_2922 : connect remapVecData[18], Queue64_UInt8_16.io.deq.bits connect remapVecValids[18], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[18] node _T_2923 = eq(UInt<5>(0h11), remapindex_18) when _T_2923 : connect remapVecData[18], Queue64_UInt8_17.io.deq.bits connect remapVecValids[18], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[18] node _T_2924 = eq(UInt<5>(0h12), remapindex_18) when _T_2924 : connect remapVecData[18], Queue64_UInt8_18.io.deq.bits connect remapVecValids[18], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[18] node _T_2925 = eq(UInt<5>(0h13), remapindex_18) when _T_2925 : connect remapVecData[18], Queue64_UInt8_19.io.deq.bits connect remapVecValids[18], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[18] node _T_2926 = eq(UInt<5>(0h14), remapindex_18) when _T_2926 : connect remapVecData[18], Queue64_UInt8_20.io.deq.bits connect remapVecValids[18], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[18] node _T_2927 = eq(UInt<5>(0h15), remapindex_18) when _T_2927 : connect remapVecData[18], Queue64_UInt8_21.io.deq.bits connect remapVecValids[18], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[18] node _T_2928 = eq(UInt<5>(0h16), remapindex_18) when _T_2928 : connect remapVecData[18], Queue64_UInt8_22.io.deq.bits connect remapVecValids[18], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[18] node _T_2929 = eq(UInt<5>(0h17), remapindex_18) when _T_2929 : connect remapVecData[18], Queue64_UInt8_23.io.deq.bits connect remapVecValids[18], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[18] node _T_2930 = eq(UInt<5>(0h18), remapindex_18) when _T_2930 : connect remapVecData[18], Queue64_UInt8_24.io.deq.bits connect remapVecValids[18], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[18] node _T_2931 = eq(UInt<5>(0h19), remapindex_18) when _T_2931 : connect remapVecData[18], Queue64_UInt8_25.io.deq.bits connect remapVecValids[18], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[18] node _T_2932 = eq(UInt<5>(0h1a), remapindex_18) when _T_2932 : connect remapVecData[18], Queue64_UInt8_26.io.deq.bits connect remapVecValids[18], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[18] node _T_2933 = eq(UInt<5>(0h1b), remapindex_18) when _T_2933 : connect remapVecData[18], Queue64_UInt8_27.io.deq.bits connect remapVecValids[18], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[18] node _T_2934 = eq(UInt<5>(0h1c), remapindex_18) when _T_2934 : connect remapVecData[18], Queue64_UInt8_28.io.deq.bits connect remapVecValids[18], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[18] node _T_2935 = eq(UInt<5>(0h1d), remapindex_18) when _T_2935 : connect remapVecData[18], Queue64_UInt8_29.io.deq.bits connect remapVecValids[18], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[18] node _T_2936 = eq(UInt<5>(0h1e), remapindex_18) when _T_2936 : connect remapVecData[18], Queue64_UInt8_30.io.deq.bits connect remapVecValids[18], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[18] node _T_2937 = eq(UInt<5>(0h1f), remapindex_18) when _T_2937 : connect remapVecData[18], Queue64_UInt8_31.io.deq.bits connect remapVecValids[18], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[18] node _remapindex_T_19 = add(UInt<5>(0h13), read_start_index) node remapindex_19 = rem(_remapindex_T_19, UInt<6>(0h20)) node _T_2938 = eq(UInt<1>(0h0), remapindex_19) when _T_2938 : connect remapVecData[19], Queue64_UInt8.io.deq.bits connect remapVecValids[19], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[19] node _T_2939 = eq(UInt<1>(0h1), remapindex_19) when _T_2939 : connect remapVecData[19], Queue64_UInt8_1.io.deq.bits connect remapVecValids[19], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[19] node _T_2940 = eq(UInt<2>(0h2), remapindex_19) when _T_2940 : connect remapVecData[19], Queue64_UInt8_2.io.deq.bits connect remapVecValids[19], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[19] node _T_2941 = eq(UInt<2>(0h3), remapindex_19) when _T_2941 : connect remapVecData[19], Queue64_UInt8_3.io.deq.bits connect remapVecValids[19], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[19] node _T_2942 = eq(UInt<3>(0h4), remapindex_19) when _T_2942 : connect remapVecData[19], Queue64_UInt8_4.io.deq.bits connect remapVecValids[19], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[19] node _T_2943 = eq(UInt<3>(0h5), remapindex_19) when _T_2943 : connect remapVecData[19], Queue64_UInt8_5.io.deq.bits connect remapVecValids[19], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[19] node _T_2944 = eq(UInt<3>(0h6), remapindex_19) when _T_2944 : connect remapVecData[19], Queue64_UInt8_6.io.deq.bits connect remapVecValids[19], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[19] node _T_2945 = eq(UInt<3>(0h7), remapindex_19) when _T_2945 : connect remapVecData[19], Queue64_UInt8_7.io.deq.bits connect remapVecValids[19], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[19] node _T_2946 = eq(UInt<4>(0h8), remapindex_19) when _T_2946 : connect remapVecData[19], Queue64_UInt8_8.io.deq.bits connect remapVecValids[19], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[19] node _T_2947 = eq(UInt<4>(0h9), remapindex_19) when _T_2947 : connect remapVecData[19], Queue64_UInt8_9.io.deq.bits connect remapVecValids[19], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[19] node _T_2948 = eq(UInt<4>(0ha), remapindex_19) when _T_2948 : connect remapVecData[19], Queue64_UInt8_10.io.deq.bits connect remapVecValids[19], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[19] node _T_2949 = eq(UInt<4>(0hb), remapindex_19) when _T_2949 : connect remapVecData[19], Queue64_UInt8_11.io.deq.bits connect remapVecValids[19], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[19] node _T_2950 = eq(UInt<4>(0hc), remapindex_19) when _T_2950 : connect remapVecData[19], Queue64_UInt8_12.io.deq.bits connect remapVecValids[19], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[19] node _T_2951 = eq(UInt<4>(0hd), remapindex_19) when _T_2951 : connect remapVecData[19], Queue64_UInt8_13.io.deq.bits connect remapVecValids[19], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[19] node _T_2952 = eq(UInt<4>(0he), remapindex_19) when _T_2952 : connect remapVecData[19], Queue64_UInt8_14.io.deq.bits connect remapVecValids[19], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[19] node _T_2953 = eq(UInt<4>(0hf), remapindex_19) when _T_2953 : connect remapVecData[19], Queue64_UInt8_15.io.deq.bits connect remapVecValids[19], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[19] node _T_2954 = eq(UInt<5>(0h10), remapindex_19) when _T_2954 : connect remapVecData[19], Queue64_UInt8_16.io.deq.bits connect remapVecValids[19], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[19] node _T_2955 = eq(UInt<5>(0h11), remapindex_19) when _T_2955 : connect remapVecData[19], Queue64_UInt8_17.io.deq.bits connect remapVecValids[19], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[19] node _T_2956 = eq(UInt<5>(0h12), remapindex_19) when _T_2956 : connect remapVecData[19], Queue64_UInt8_18.io.deq.bits connect remapVecValids[19], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[19] node _T_2957 = eq(UInt<5>(0h13), remapindex_19) when _T_2957 : connect remapVecData[19], Queue64_UInt8_19.io.deq.bits connect remapVecValids[19], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[19] node _T_2958 = eq(UInt<5>(0h14), remapindex_19) when _T_2958 : connect remapVecData[19], Queue64_UInt8_20.io.deq.bits connect remapVecValids[19], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[19] node _T_2959 = eq(UInt<5>(0h15), remapindex_19) when _T_2959 : connect remapVecData[19], Queue64_UInt8_21.io.deq.bits connect remapVecValids[19], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[19] node _T_2960 = eq(UInt<5>(0h16), remapindex_19) when _T_2960 : connect remapVecData[19], Queue64_UInt8_22.io.deq.bits connect remapVecValids[19], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[19] node _T_2961 = eq(UInt<5>(0h17), remapindex_19) when _T_2961 : connect remapVecData[19], Queue64_UInt8_23.io.deq.bits connect remapVecValids[19], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[19] node _T_2962 = eq(UInt<5>(0h18), remapindex_19) when _T_2962 : connect remapVecData[19], Queue64_UInt8_24.io.deq.bits connect remapVecValids[19], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[19] node _T_2963 = eq(UInt<5>(0h19), remapindex_19) when _T_2963 : connect remapVecData[19], Queue64_UInt8_25.io.deq.bits connect remapVecValids[19], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[19] node _T_2964 = eq(UInt<5>(0h1a), remapindex_19) when _T_2964 : connect remapVecData[19], Queue64_UInt8_26.io.deq.bits connect remapVecValids[19], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[19] node _T_2965 = eq(UInt<5>(0h1b), remapindex_19) when _T_2965 : connect remapVecData[19], Queue64_UInt8_27.io.deq.bits connect remapVecValids[19], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[19] node _T_2966 = eq(UInt<5>(0h1c), remapindex_19) when _T_2966 : connect remapVecData[19], Queue64_UInt8_28.io.deq.bits connect remapVecValids[19], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[19] node _T_2967 = eq(UInt<5>(0h1d), remapindex_19) when _T_2967 : connect remapVecData[19], Queue64_UInt8_29.io.deq.bits connect remapVecValids[19], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[19] node _T_2968 = eq(UInt<5>(0h1e), remapindex_19) when _T_2968 : connect remapVecData[19], Queue64_UInt8_30.io.deq.bits connect remapVecValids[19], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[19] node _T_2969 = eq(UInt<5>(0h1f), remapindex_19) when _T_2969 : connect remapVecData[19], Queue64_UInt8_31.io.deq.bits connect remapVecValids[19], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[19] node _remapindex_T_20 = add(UInt<5>(0h14), read_start_index) node remapindex_20 = rem(_remapindex_T_20, UInt<6>(0h20)) node _T_2970 = eq(UInt<1>(0h0), remapindex_20) when _T_2970 : connect remapVecData[20], Queue64_UInt8.io.deq.bits connect remapVecValids[20], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[20] node _T_2971 = eq(UInt<1>(0h1), remapindex_20) when _T_2971 : connect remapVecData[20], Queue64_UInt8_1.io.deq.bits connect remapVecValids[20], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[20] node _T_2972 = eq(UInt<2>(0h2), remapindex_20) when _T_2972 : connect remapVecData[20], Queue64_UInt8_2.io.deq.bits connect remapVecValids[20], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[20] node _T_2973 = eq(UInt<2>(0h3), remapindex_20) when _T_2973 : connect remapVecData[20], Queue64_UInt8_3.io.deq.bits connect remapVecValids[20], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[20] node _T_2974 = eq(UInt<3>(0h4), remapindex_20) when _T_2974 : connect remapVecData[20], Queue64_UInt8_4.io.deq.bits connect remapVecValids[20], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[20] node _T_2975 = eq(UInt<3>(0h5), remapindex_20) when _T_2975 : connect remapVecData[20], Queue64_UInt8_5.io.deq.bits connect remapVecValids[20], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[20] node _T_2976 = eq(UInt<3>(0h6), remapindex_20) when _T_2976 : connect remapVecData[20], Queue64_UInt8_6.io.deq.bits connect remapVecValids[20], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[20] node _T_2977 = eq(UInt<3>(0h7), remapindex_20) when _T_2977 : connect remapVecData[20], Queue64_UInt8_7.io.deq.bits connect remapVecValids[20], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[20] node _T_2978 = eq(UInt<4>(0h8), remapindex_20) when _T_2978 : connect remapVecData[20], Queue64_UInt8_8.io.deq.bits connect remapVecValids[20], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[20] node _T_2979 = eq(UInt<4>(0h9), remapindex_20) when _T_2979 : connect remapVecData[20], Queue64_UInt8_9.io.deq.bits connect remapVecValids[20], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[20] node _T_2980 = eq(UInt<4>(0ha), remapindex_20) when _T_2980 : connect remapVecData[20], Queue64_UInt8_10.io.deq.bits connect remapVecValids[20], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[20] node _T_2981 = eq(UInt<4>(0hb), remapindex_20) when _T_2981 : connect remapVecData[20], Queue64_UInt8_11.io.deq.bits connect remapVecValids[20], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[20] node _T_2982 = eq(UInt<4>(0hc), remapindex_20) when _T_2982 : connect remapVecData[20], Queue64_UInt8_12.io.deq.bits connect remapVecValids[20], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[20] node _T_2983 = eq(UInt<4>(0hd), remapindex_20) when _T_2983 : connect remapVecData[20], Queue64_UInt8_13.io.deq.bits connect remapVecValids[20], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[20] node _T_2984 = eq(UInt<4>(0he), remapindex_20) when _T_2984 : connect remapVecData[20], Queue64_UInt8_14.io.deq.bits connect remapVecValids[20], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[20] node _T_2985 = eq(UInt<4>(0hf), remapindex_20) when _T_2985 : connect remapVecData[20], Queue64_UInt8_15.io.deq.bits connect remapVecValids[20], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[20] node _T_2986 = eq(UInt<5>(0h10), remapindex_20) when _T_2986 : connect remapVecData[20], Queue64_UInt8_16.io.deq.bits connect remapVecValids[20], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[20] node _T_2987 = eq(UInt<5>(0h11), remapindex_20) when _T_2987 : connect remapVecData[20], Queue64_UInt8_17.io.deq.bits connect remapVecValids[20], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[20] node _T_2988 = eq(UInt<5>(0h12), remapindex_20) when _T_2988 : connect remapVecData[20], Queue64_UInt8_18.io.deq.bits connect remapVecValids[20], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[20] node _T_2989 = eq(UInt<5>(0h13), remapindex_20) when _T_2989 : connect remapVecData[20], Queue64_UInt8_19.io.deq.bits connect remapVecValids[20], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[20] node _T_2990 = eq(UInt<5>(0h14), remapindex_20) when _T_2990 : connect remapVecData[20], Queue64_UInt8_20.io.deq.bits connect remapVecValids[20], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[20] node _T_2991 = eq(UInt<5>(0h15), remapindex_20) when _T_2991 : connect remapVecData[20], Queue64_UInt8_21.io.deq.bits connect remapVecValids[20], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[20] node _T_2992 = eq(UInt<5>(0h16), remapindex_20) when _T_2992 : connect remapVecData[20], Queue64_UInt8_22.io.deq.bits connect remapVecValids[20], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[20] node _T_2993 = eq(UInt<5>(0h17), remapindex_20) when _T_2993 : connect remapVecData[20], Queue64_UInt8_23.io.deq.bits connect remapVecValids[20], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[20] node _T_2994 = eq(UInt<5>(0h18), remapindex_20) when _T_2994 : connect remapVecData[20], Queue64_UInt8_24.io.deq.bits connect remapVecValids[20], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[20] node _T_2995 = eq(UInt<5>(0h19), remapindex_20) when _T_2995 : connect remapVecData[20], Queue64_UInt8_25.io.deq.bits connect remapVecValids[20], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[20] node _T_2996 = eq(UInt<5>(0h1a), remapindex_20) when _T_2996 : connect remapVecData[20], Queue64_UInt8_26.io.deq.bits connect remapVecValids[20], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[20] node _T_2997 = eq(UInt<5>(0h1b), remapindex_20) when _T_2997 : connect remapVecData[20], Queue64_UInt8_27.io.deq.bits connect remapVecValids[20], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[20] node _T_2998 = eq(UInt<5>(0h1c), remapindex_20) when _T_2998 : connect remapVecData[20], Queue64_UInt8_28.io.deq.bits connect remapVecValids[20], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[20] node _T_2999 = eq(UInt<5>(0h1d), remapindex_20) when _T_2999 : connect remapVecData[20], Queue64_UInt8_29.io.deq.bits connect remapVecValids[20], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[20] node _T_3000 = eq(UInt<5>(0h1e), remapindex_20) when _T_3000 : connect remapVecData[20], Queue64_UInt8_30.io.deq.bits connect remapVecValids[20], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[20] node _T_3001 = eq(UInt<5>(0h1f), remapindex_20) when _T_3001 : connect remapVecData[20], Queue64_UInt8_31.io.deq.bits connect remapVecValids[20], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[20] node _remapindex_T_21 = add(UInt<5>(0h15), read_start_index) node remapindex_21 = rem(_remapindex_T_21, UInt<6>(0h20)) node _T_3002 = eq(UInt<1>(0h0), remapindex_21) when _T_3002 : connect remapVecData[21], Queue64_UInt8.io.deq.bits connect remapVecValids[21], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[21] node _T_3003 = eq(UInt<1>(0h1), remapindex_21) when _T_3003 : connect remapVecData[21], Queue64_UInt8_1.io.deq.bits connect remapVecValids[21], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[21] node _T_3004 = eq(UInt<2>(0h2), remapindex_21) when _T_3004 : connect remapVecData[21], Queue64_UInt8_2.io.deq.bits connect remapVecValids[21], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[21] node _T_3005 = eq(UInt<2>(0h3), remapindex_21) when _T_3005 : connect remapVecData[21], Queue64_UInt8_3.io.deq.bits connect remapVecValids[21], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[21] node _T_3006 = eq(UInt<3>(0h4), remapindex_21) when _T_3006 : connect remapVecData[21], Queue64_UInt8_4.io.deq.bits connect remapVecValids[21], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[21] node _T_3007 = eq(UInt<3>(0h5), remapindex_21) when _T_3007 : connect remapVecData[21], Queue64_UInt8_5.io.deq.bits connect remapVecValids[21], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[21] node _T_3008 = eq(UInt<3>(0h6), remapindex_21) when _T_3008 : connect remapVecData[21], Queue64_UInt8_6.io.deq.bits connect remapVecValids[21], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[21] node _T_3009 = eq(UInt<3>(0h7), remapindex_21) when _T_3009 : connect remapVecData[21], Queue64_UInt8_7.io.deq.bits connect remapVecValids[21], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[21] node _T_3010 = eq(UInt<4>(0h8), remapindex_21) when _T_3010 : connect remapVecData[21], Queue64_UInt8_8.io.deq.bits connect remapVecValids[21], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[21] node _T_3011 = eq(UInt<4>(0h9), remapindex_21) when _T_3011 : connect remapVecData[21], Queue64_UInt8_9.io.deq.bits connect remapVecValids[21], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[21] node _T_3012 = eq(UInt<4>(0ha), remapindex_21) when _T_3012 : connect remapVecData[21], Queue64_UInt8_10.io.deq.bits connect remapVecValids[21], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[21] node _T_3013 = eq(UInt<4>(0hb), remapindex_21) when _T_3013 : connect remapVecData[21], Queue64_UInt8_11.io.deq.bits connect remapVecValids[21], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[21] node _T_3014 = eq(UInt<4>(0hc), remapindex_21) when _T_3014 : connect remapVecData[21], Queue64_UInt8_12.io.deq.bits connect remapVecValids[21], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[21] node _T_3015 = eq(UInt<4>(0hd), remapindex_21) when _T_3015 : connect remapVecData[21], Queue64_UInt8_13.io.deq.bits connect remapVecValids[21], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[21] node _T_3016 = eq(UInt<4>(0he), remapindex_21) when _T_3016 : connect remapVecData[21], Queue64_UInt8_14.io.deq.bits connect remapVecValids[21], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[21] node _T_3017 = eq(UInt<4>(0hf), remapindex_21) when _T_3017 : connect remapVecData[21], Queue64_UInt8_15.io.deq.bits connect remapVecValids[21], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[21] node _T_3018 = eq(UInt<5>(0h10), remapindex_21) when _T_3018 : connect remapVecData[21], Queue64_UInt8_16.io.deq.bits connect remapVecValids[21], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[21] node _T_3019 = eq(UInt<5>(0h11), remapindex_21) when _T_3019 : connect remapVecData[21], Queue64_UInt8_17.io.deq.bits connect remapVecValids[21], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[21] node _T_3020 = eq(UInt<5>(0h12), remapindex_21) when _T_3020 : connect remapVecData[21], Queue64_UInt8_18.io.deq.bits connect remapVecValids[21], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[21] node _T_3021 = eq(UInt<5>(0h13), remapindex_21) when _T_3021 : connect remapVecData[21], Queue64_UInt8_19.io.deq.bits connect remapVecValids[21], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[21] node _T_3022 = eq(UInt<5>(0h14), remapindex_21) when _T_3022 : connect remapVecData[21], Queue64_UInt8_20.io.deq.bits connect remapVecValids[21], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[21] node _T_3023 = eq(UInt<5>(0h15), remapindex_21) when _T_3023 : connect remapVecData[21], Queue64_UInt8_21.io.deq.bits connect remapVecValids[21], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[21] node _T_3024 = eq(UInt<5>(0h16), remapindex_21) when _T_3024 : connect remapVecData[21], Queue64_UInt8_22.io.deq.bits connect remapVecValids[21], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[21] node _T_3025 = eq(UInt<5>(0h17), remapindex_21) when _T_3025 : connect remapVecData[21], Queue64_UInt8_23.io.deq.bits connect remapVecValids[21], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[21] node _T_3026 = eq(UInt<5>(0h18), remapindex_21) when _T_3026 : connect remapVecData[21], Queue64_UInt8_24.io.deq.bits connect remapVecValids[21], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[21] node _T_3027 = eq(UInt<5>(0h19), remapindex_21) when _T_3027 : connect remapVecData[21], Queue64_UInt8_25.io.deq.bits connect remapVecValids[21], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[21] node _T_3028 = eq(UInt<5>(0h1a), remapindex_21) when _T_3028 : connect remapVecData[21], Queue64_UInt8_26.io.deq.bits connect remapVecValids[21], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[21] node _T_3029 = eq(UInt<5>(0h1b), remapindex_21) when _T_3029 : connect remapVecData[21], Queue64_UInt8_27.io.deq.bits connect remapVecValids[21], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[21] node _T_3030 = eq(UInt<5>(0h1c), remapindex_21) when _T_3030 : connect remapVecData[21], Queue64_UInt8_28.io.deq.bits connect remapVecValids[21], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[21] node _T_3031 = eq(UInt<5>(0h1d), remapindex_21) when _T_3031 : connect remapVecData[21], Queue64_UInt8_29.io.deq.bits connect remapVecValids[21], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[21] node _T_3032 = eq(UInt<5>(0h1e), remapindex_21) when _T_3032 : connect remapVecData[21], Queue64_UInt8_30.io.deq.bits connect remapVecValids[21], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[21] node _T_3033 = eq(UInt<5>(0h1f), remapindex_21) when _T_3033 : connect remapVecData[21], Queue64_UInt8_31.io.deq.bits connect remapVecValids[21], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[21] node _remapindex_T_22 = add(UInt<5>(0h16), read_start_index) node remapindex_22 = rem(_remapindex_T_22, UInt<6>(0h20)) node _T_3034 = eq(UInt<1>(0h0), remapindex_22) when _T_3034 : connect remapVecData[22], Queue64_UInt8.io.deq.bits connect remapVecValids[22], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[22] node _T_3035 = eq(UInt<1>(0h1), remapindex_22) when _T_3035 : connect remapVecData[22], Queue64_UInt8_1.io.deq.bits connect remapVecValids[22], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[22] node _T_3036 = eq(UInt<2>(0h2), remapindex_22) when _T_3036 : connect remapVecData[22], Queue64_UInt8_2.io.deq.bits connect remapVecValids[22], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[22] node _T_3037 = eq(UInt<2>(0h3), remapindex_22) when _T_3037 : connect remapVecData[22], Queue64_UInt8_3.io.deq.bits connect remapVecValids[22], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[22] node _T_3038 = eq(UInt<3>(0h4), remapindex_22) when _T_3038 : connect remapVecData[22], Queue64_UInt8_4.io.deq.bits connect remapVecValids[22], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[22] node _T_3039 = eq(UInt<3>(0h5), remapindex_22) when _T_3039 : connect remapVecData[22], Queue64_UInt8_5.io.deq.bits connect remapVecValids[22], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[22] node _T_3040 = eq(UInt<3>(0h6), remapindex_22) when _T_3040 : connect remapVecData[22], Queue64_UInt8_6.io.deq.bits connect remapVecValids[22], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[22] node _T_3041 = eq(UInt<3>(0h7), remapindex_22) when _T_3041 : connect remapVecData[22], Queue64_UInt8_7.io.deq.bits connect remapVecValids[22], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[22] node _T_3042 = eq(UInt<4>(0h8), remapindex_22) when _T_3042 : connect remapVecData[22], Queue64_UInt8_8.io.deq.bits connect remapVecValids[22], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[22] node _T_3043 = eq(UInt<4>(0h9), remapindex_22) when _T_3043 : connect remapVecData[22], Queue64_UInt8_9.io.deq.bits connect remapVecValids[22], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[22] node _T_3044 = eq(UInt<4>(0ha), remapindex_22) when _T_3044 : connect remapVecData[22], Queue64_UInt8_10.io.deq.bits connect remapVecValids[22], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[22] node _T_3045 = eq(UInt<4>(0hb), remapindex_22) when _T_3045 : connect remapVecData[22], Queue64_UInt8_11.io.deq.bits connect remapVecValids[22], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[22] node _T_3046 = eq(UInt<4>(0hc), remapindex_22) when _T_3046 : connect remapVecData[22], Queue64_UInt8_12.io.deq.bits connect remapVecValids[22], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[22] node _T_3047 = eq(UInt<4>(0hd), remapindex_22) when _T_3047 : connect remapVecData[22], Queue64_UInt8_13.io.deq.bits connect remapVecValids[22], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[22] node _T_3048 = eq(UInt<4>(0he), remapindex_22) when _T_3048 : connect remapVecData[22], Queue64_UInt8_14.io.deq.bits connect remapVecValids[22], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[22] node _T_3049 = eq(UInt<4>(0hf), remapindex_22) when _T_3049 : connect remapVecData[22], Queue64_UInt8_15.io.deq.bits connect remapVecValids[22], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[22] node _T_3050 = eq(UInt<5>(0h10), remapindex_22) when _T_3050 : connect remapVecData[22], Queue64_UInt8_16.io.deq.bits connect remapVecValids[22], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[22] node _T_3051 = eq(UInt<5>(0h11), remapindex_22) when _T_3051 : connect remapVecData[22], Queue64_UInt8_17.io.deq.bits connect remapVecValids[22], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[22] node _T_3052 = eq(UInt<5>(0h12), remapindex_22) when _T_3052 : connect remapVecData[22], Queue64_UInt8_18.io.deq.bits connect remapVecValids[22], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[22] node _T_3053 = eq(UInt<5>(0h13), remapindex_22) when _T_3053 : connect remapVecData[22], Queue64_UInt8_19.io.deq.bits connect remapVecValids[22], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[22] node _T_3054 = eq(UInt<5>(0h14), remapindex_22) when _T_3054 : connect remapVecData[22], Queue64_UInt8_20.io.deq.bits connect remapVecValids[22], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[22] node _T_3055 = eq(UInt<5>(0h15), remapindex_22) when _T_3055 : connect remapVecData[22], Queue64_UInt8_21.io.deq.bits connect remapVecValids[22], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[22] node _T_3056 = eq(UInt<5>(0h16), remapindex_22) when _T_3056 : connect remapVecData[22], Queue64_UInt8_22.io.deq.bits connect remapVecValids[22], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[22] node _T_3057 = eq(UInt<5>(0h17), remapindex_22) when _T_3057 : connect remapVecData[22], Queue64_UInt8_23.io.deq.bits connect remapVecValids[22], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[22] node _T_3058 = eq(UInt<5>(0h18), remapindex_22) when _T_3058 : connect remapVecData[22], Queue64_UInt8_24.io.deq.bits connect remapVecValids[22], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[22] node _T_3059 = eq(UInt<5>(0h19), remapindex_22) when _T_3059 : connect remapVecData[22], Queue64_UInt8_25.io.deq.bits connect remapVecValids[22], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[22] node _T_3060 = eq(UInt<5>(0h1a), remapindex_22) when _T_3060 : connect remapVecData[22], Queue64_UInt8_26.io.deq.bits connect remapVecValids[22], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[22] node _T_3061 = eq(UInt<5>(0h1b), remapindex_22) when _T_3061 : connect remapVecData[22], Queue64_UInt8_27.io.deq.bits connect remapVecValids[22], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[22] node _T_3062 = eq(UInt<5>(0h1c), remapindex_22) when _T_3062 : connect remapVecData[22], Queue64_UInt8_28.io.deq.bits connect remapVecValids[22], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[22] node _T_3063 = eq(UInt<5>(0h1d), remapindex_22) when _T_3063 : connect remapVecData[22], Queue64_UInt8_29.io.deq.bits connect remapVecValids[22], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[22] node _T_3064 = eq(UInt<5>(0h1e), remapindex_22) when _T_3064 : connect remapVecData[22], Queue64_UInt8_30.io.deq.bits connect remapVecValids[22], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[22] node _T_3065 = eq(UInt<5>(0h1f), remapindex_22) when _T_3065 : connect remapVecData[22], Queue64_UInt8_31.io.deq.bits connect remapVecValids[22], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[22] node _remapindex_T_23 = add(UInt<5>(0h17), read_start_index) node remapindex_23 = rem(_remapindex_T_23, UInt<6>(0h20)) node _T_3066 = eq(UInt<1>(0h0), remapindex_23) when _T_3066 : connect remapVecData[23], Queue64_UInt8.io.deq.bits connect remapVecValids[23], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[23] node _T_3067 = eq(UInt<1>(0h1), remapindex_23) when _T_3067 : connect remapVecData[23], Queue64_UInt8_1.io.deq.bits connect remapVecValids[23], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[23] node _T_3068 = eq(UInt<2>(0h2), remapindex_23) when _T_3068 : connect remapVecData[23], Queue64_UInt8_2.io.deq.bits connect remapVecValids[23], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[23] node _T_3069 = eq(UInt<2>(0h3), remapindex_23) when _T_3069 : connect remapVecData[23], Queue64_UInt8_3.io.deq.bits connect remapVecValids[23], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[23] node _T_3070 = eq(UInt<3>(0h4), remapindex_23) when _T_3070 : connect remapVecData[23], Queue64_UInt8_4.io.deq.bits connect remapVecValids[23], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[23] node _T_3071 = eq(UInt<3>(0h5), remapindex_23) when _T_3071 : connect remapVecData[23], Queue64_UInt8_5.io.deq.bits connect remapVecValids[23], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[23] node _T_3072 = eq(UInt<3>(0h6), remapindex_23) when _T_3072 : connect remapVecData[23], Queue64_UInt8_6.io.deq.bits connect remapVecValids[23], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[23] node _T_3073 = eq(UInt<3>(0h7), remapindex_23) when _T_3073 : connect remapVecData[23], Queue64_UInt8_7.io.deq.bits connect remapVecValids[23], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[23] node _T_3074 = eq(UInt<4>(0h8), remapindex_23) when _T_3074 : connect remapVecData[23], Queue64_UInt8_8.io.deq.bits connect remapVecValids[23], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[23] node _T_3075 = eq(UInt<4>(0h9), remapindex_23) when _T_3075 : connect remapVecData[23], Queue64_UInt8_9.io.deq.bits connect remapVecValids[23], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[23] node _T_3076 = eq(UInt<4>(0ha), remapindex_23) when _T_3076 : connect remapVecData[23], Queue64_UInt8_10.io.deq.bits connect remapVecValids[23], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[23] node _T_3077 = eq(UInt<4>(0hb), remapindex_23) when _T_3077 : connect remapVecData[23], Queue64_UInt8_11.io.deq.bits connect remapVecValids[23], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[23] node _T_3078 = eq(UInt<4>(0hc), remapindex_23) when _T_3078 : connect remapVecData[23], Queue64_UInt8_12.io.deq.bits connect remapVecValids[23], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[23] node _T_3079 = eq(UInt<4>(0hd), remapindex_23) when _T_3079 : connect remapVecData[23], Queue64_UInt8_13.io.deq.bits connect remapVecValids[23], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[23] node _T_3080 = eq(UInt<4>(0he), remapindex_23) when _T_3080 : connect remapVecData[23], Queue64_UInt8_14.io.deq.bits connect remapVecValids[23], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[23] node _T_3081 = eq(UInt<4>(0hf), remapindex_23) when _T_3081 : connect remapVecData[23], Queue64_UInt8_15.io.deq.bits connect remapVecValids[23], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[23] node _T_3082 = eq(UInt<5>(0h10), remapindex_23) when _T_3082 : connect remapVecData[23], Queue64_UInt8_16.io.deq.bits connect remapVecValids[23], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[23] node _T_3083 = eq(UInt<5>(0h11), remapindex_23) when _T_3083 : connect remapVecData[23], Queue64_UInt8_17.io.deq.bits connect remapVecValids[23], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[23] node _T_3084 = eq(UInt<5>(0h12), remapindex_23) when _T_3084 : connect remapVecData[23], Queue64_UInt8_18.io.deq.bits connect remapVecValids[23], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[23] node _T_3085 = eq(UInt<5>(0h13), remapindex_23) when _T_3085 : connect remapVecData[23], Queue64_UInt8_19.io.deq.bits connect remapVecValids[23], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[23] node _T_3086 = eq(UInt<5>(0h14), remapindex_23) when _T_3086 : connect remapVecData[23], Queue64_UInt8_20.io.deq.bits connect remapVecValids[23], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[23] node _T_3087 = eq(UInt<5>(0h15), remapindex_23) when _T_3087 : connect remapVecData[23], Queue64_UInt8_21.io.deq.bits connect remapVecValids[23], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[23] node _T_3088 = eq(UInt<5>(0h16), remapindex_23) when _T_3088 : connect remapVecData[23], Queue64_UInt8_22.io.deq.bits connect remapVecValids[23], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[23] node _T_3089 = eq(UInt<5>(0h17), remapindex_23) when _T_3089 : connect remapVecData[23], Queue64_UInt8_23.io.deq.bits connect remapVecValids[23], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[23] node _T_3090 = eq(UInt<5>(0h18), remapindex_23) when _T_3090 : connect remapVecData[23], Queue64_UInt8_24.io.deq.bits connect remapVecValids[23], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[23] node _T_3091 = eq(UInt<5>(0h19), remapindex_23) when _T_3091 : connect remapVecData[23], Queue64_UInt8_25.io.deq.bits connect remapVecValids[23], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[23] node _T_3092 = eq(UInt<5>(0h1a), remapindex_23) when _T_3092 : connect remapVecData[23], Queue64_UInt8_26.io.deq.bits connect remapVecValids[23], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[23] node _T_3093 = eq(UInt<5>(0h1b), remapindex_23) when _T_3093 : connect remapVecData[23], Queue64_UInt8_27.io.deq.bits connect remapVecValids[23], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[23] node _T_3094 = eq(UInt<5>(0h1c), remapindex_23) when _T_3094 : connect remapVecData[23], Queue64_UInt8_28.io.deq.bits connect remapVecValids[23], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[23] node _T_3095 = eq(UInt<5>(0h1d), remapindex_23) when _T_3095 : connect remapVecData[23], Queue64_UInt8_29.io.deq.bits connect remapVecValids[23], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[23] node _T_3096 = eq(UInt<5>(0h1e), remapindex_23) when _T_3096 : connect remapVecData[23], Queue64_UInt8_30.io.deq.bits connect remapVecValids[23], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[23] node _T_3097 = eq(UInt<5>(0h1f), remapindex_23) when _T_3097 : connect remapVecData[23], Queue64_UInt8_31.io.deq.bits connect remapVecValids[23], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[23] node _remapindex_T_24 = add(UInt<5>(0h18), read_start_index) node remapindex_24 = rem(_remapindex_T_24, UInt<6>(0h20)) node _T_3098 = eq(UInt<1>(0h0), remapindex_24) when _T_3098 : connect remapVecData[24], Queue64_UInt8.io.deq.bits connect remapVecValids[24], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[24] node _T_3099 = eq(UInt<1>(0h1), remapindex_24) when _T_3099 : connect remapVecData[24], Queue64_UInt8_1.io.deq.bits connect remapVecValids[24], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[24] node _T_3100 = eq(UInt<2>(0h2), remapindex_24) when _T_3100 : connect remapVecData[24], Queue64_UInt8_2.io.deq.bits connect remapVecValids[24], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[24] node _T_3101 = eq(UInt<2>(0h3), remapindex_24) when _T_3101 : connect remapVecData[24], Queue64_UInt8_3.io.deq.bits connect remapVecValids[24], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[24] node _T_3102 = eq(UInt<3>(0h4), remapindex_24) when _T_3102 : connect remapVecData[24], Queue64_UInt8_4.io.deq.bits connect remapVecValids[24], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[24] node _T_3103 = eq(UInt<3>(0h5), remapindex_24) when _T_3103 : connect remapVecData[24], Queue64_UInt8_5.io.deq.bits connect remapVecValids[24], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[24] node _T_3104 = eq(UInt<3>(0h6), remapindex_24) when _T_3104 : connect remapVecData[24], Queue64_UInt8_6.io.deq.bits connect remapVecValids[24], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[24] node _T_3105 = eq(UInt<3>(0h7), remapindex_24) when _T_3105 : connect remapVecData[24], Queue64_UInt8_7.io.deq.bits connect remapVecValids[24], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[24] node _T_3106 = eq(UInt<4>(0h8), remapindex_24) when _T_3106 : connect remapVecData[24], Queue64_UInt8_8.io.deq.bits connect remapVecValids[24], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[24] node _T_3107 = eq(UInt<4>(0h9), remapindex_24) when _T_3107 : connect remapVecData[24], Queue64_UInt8_9.io.deq.bits connect remapVecValids[24], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[24] node _T_3108 = eq(UInt<4>(0ha), remapindex_24) when _T_3108 : connect remapVecData[24], Queue64_UInt8_10.io.deq.bits connect remapVecValids[24], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[24] node _T_3109 = eq(UInt<4>(0hb), remapindex_24) when _T_3109 : connect remapVecData[24], Queue64_UInt8_11.io.deq.bits connect remapVecValids[24], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[24] node _T_3110 = eq(UInt<4>(0hc), remapindex_24) when _T_3110 : connect remapVecData[24], Queue64_UInt8_12.io.deq.bits connect remapVecValids[24], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[24] node _T_3111 = eq(UInt<4>(0hd), remapindex_24) when _T_3111 : connect remapVecData[24], Queue64_UInt8_13.io.deq.bits connect remapVecValids[24], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[24] node _T_3112 = eq(UInt<4>(0he), remapindex_24) when _T_3112 : connect remapVecData[24], Queue64_UInt8_14.io.deq.bits connect remapVecValids[24], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[24] node _T_3113 = eq(UInt<4>(0hf), remapindex_24) when _T_3113 : connect remapVecData[24], Queue64_UInt8_15.io.deq.bits connect remapVecValids[24], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[24] node _T_3114 = eq(UInt<5>(0h10), remapindex_24) when _T_3114 : connect remapVecData[24], Queue64_UInt8_16.io.deq.bits connect remapVecValids[24], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[24] node _T_3115 = eq(UInt<5>(0h11), remapindex_24) when _T_3115 : connect remapVecData[24], Queue64_UInt8_17.io.deq.bits connect remapVecValids[24], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[24] node _T_3116 = eq(UInt<5>(0h12), remapindex_24) when _T_3116 : connect remapVecData[24], Queue64_UInt8_18.io.deq.bits connect remapVecValids[24], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[24] node _T_3117 = eq(UInt<5>(0h13), remapindex_24) when _T_3117 : connect remapVecData[24], Queue64_UInt8_19.io.deq.bits connect remapVecValids[24], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[24] node _T_3118 = eq(UInt<5>(0h14), remapindex_24) when _T_3118 : connect remapVecData[24], Queue64_UInt8_20.io.deq.bits connect remapVecValids[24], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[24] node _T_3119 = eq(UInt<5>(0h15), remapindex_24) when _T_3119 : connect remapVecData[24], Queue64_UInt8_21.io.deq.bits connect remapVecValids[24], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[24] node _T_3120 = eq(UInt<5>(0h16), remapindex_24) when _T_3120 : connect remapVecData[24], Queue64_UInt8_22.io.deq.bits connect remapVecValids[24], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[24] node _T_3121 = eq(UInt<5>(0h17), remapindex_24) when _T_3121 : connect remapVecData[24], Queue64_UInt8_23.io.deq.bits connect remapVecValids[24], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[24] node _T_3122 = eq(UInt<5>(0h18), remapindex_24) when _T_3122 : connect remapVecData[24], Queue64_UInt8_24.io.deq.bits connect remapVecValids[24], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[24] node _T_3123 = eq(UInt<5>(0h19), remapindex_24) when _T_3123 : connect remapVecData[24], Queue64_UInt8_25.io.deq.bits connect remapVecValids[24], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[24] node _T_3124 = eq(UInt<5>(0h1a), remapindex_24) when _T_3124 : connect remapVecData[24], Queue64_UInt8_26.io.deq.bits connect remapVecValids[24], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[24] node _T_3125 = eq(UInt<5>(0h1b), remapindex_24) when _T_3125 : connect remapVecData[24], Queue64_UInt8_27.io.deq.bits connect remapVecValids[24], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[24] node _T_3126 = eq(UInt<5>(0h1c), remapindex_24) when _T_3126 : connect remapVecData[24], Queue64_UInt8_28.io.deq.bits connect remapVecValids[24], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[24] node _T_3127 = eq(UInt<5>(0h1d), remapindex_24) when _T_3127 : connect remapVecData[24], Queue64_UInt8_29.io.deq.bits connect remapVecValids[24], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[24] node _T_3128 = eq(UInt<5>(0h1e), remapindex_24) when _T_3128 : connect remapVecData[24], Queue64_UInt8_30.io.deq.bits connect remapVecValids[24], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[24] node _T_3129 = eq(UInt<5>(0h1f), remapindex_24) when _T_3129 : connect remapVecData[24], Queue64_UInt8_31.io.deq.bits connect remapVecValids[24], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[24] node _remapindex_T_25 = add(UInt<5>(0h19), read_start_index) node remapindex_25 = rem(_remapindex_T_25, UInt<6>(0h20)) node _T_3130 = eq(UInt<1>(0h0), remapindex_25) when _T_3130 : connect remapVecData[25], Queue64_UInt8.io.deq.bits connect remapVecValids[25], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[25] node _T_3131 = eq(UInt<1>(0h1), remapindex_25) when _T_3131 : connect remapVecData[25], Queue64_UInt8_1.io.deq.bits connect remapVecValids[25], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[25] node _T_3132 = eq(UInt<2>(0h2), remapindex_25) when _T_3132 : connect remapVecData[25], Queue64_UInt8_2.io.deq.bits connect remapVecValids[25], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[25] node _T_3133 = eq(UInt<2>(0h3), remapindex_25) when _T_3133 : connect remapVecData[25], Queue64_UInt8_3.io.deq.bits connect remapVecValids[25], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[25] node _T_3134 = eq(UInt<3>(0h4), remapindex_25) when _T_3134 : connect remapVecData[25], Queue64_UInt8_4.io.deq.bits connect remapVecValids[25], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[25] node _T_3135 = eq(UInt<3>(0h5), remapindex_25) when _T_3135 : connect remapVecData[25], Queue64_UInt8_5.io.deq.bits connect remapVecValids[25], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[25] node _T_3136 = eq(UInt<3>(0h6), remapindex_25) when _T_3136 : connect remapVecData[25], Queue64_UInt8_6.io.deq.bits connect remapVecValids[25], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[25] node _T_3137 = eq(UInt<3>(0h7), remapindex_25) when _T_3137 : connect remapVecData[25], Queue64_UInt8_7.io.deq.bits connect remapVecValids[25], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[25] node _T_3138 = eq(UInt<4>(0h8), remapindex_25) when _T_3138 : connect remapVecData[25], Queue64_UInt8_8.io.deq.bits connect remapVecValids[25], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[25] node _T_3139 = eq(UInt<4>(0h9), remapindex_25) when _T_3139 : connect remapVecData[25], Queue64_UInt8_9.io.deq.bits connect remapVecValids[25], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[25] node _T_3140 = eq(UInt<4>(0ha), remapindex_25) when _T_3140 : connect remapVecData[25], Queue64_UInt8_10.io.deq.bits connect remapVecValids[25], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[25] node _T_3141 = eq(UInt<4>(0hb), remapindex_25) when _T_3141 : connect remapVecData[25], Queue64_UInt8_11.io.deq.bits connect remapVecValids[25], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[25] node _T_3142 = eq(UInt<4>(0hc), remapindex_25) when _T_3142 : connect remapVecData[25], Queue64_UInt8_12.io.deq.bits connect remapVecValids[25], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[25] node _T_3143 = eq(UInt<4>(0hd), remapindex_25) when _T_3143 : connect remapVecData[25], Queue64_UInt8_13.io.deq.bits connect remapVecValids[25], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[25] node _T_3144 = eq(UInt<4>(0he), remapindex_25) when _T_3144 : connect remapVecData[25], Queue64_UInt8_14.io.deq.bits connect remapVecValids[25], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[25] node _T_3145 = eq(UInt<4>(0hf), remapindex_25) when _T_3145 : connect remapVecData[25], Queue64_UInt8_15.io.deq.bits connect remapVecValids[25], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[25] node _T_3146 = eq(UInt<5>(0h10), remapindex_25) when _T_3146 : connect remapVecData[25], Queue64_UInt8_16.io.deq.bits connect remapVecValids[25], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[25] node _T_3147 = eq(UInt<5>(0h11), remapindex_25) when _T_3147 : connect remapVecData[25], Queue64_UInt8_17.io.deq.bits connect remapVecValids[25], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[25] node _T_3148 = eq(UInt<5>(0h12), remapindex_25) when _T_3148 : connect remapVecData[25], Queue64_UInt8_18.io.deq.bits connect remapVecValids[25], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[25] node _T_3149 = eq(UInt<5>(0h13), remapindex_25) when _T_3149 : connect remapVecData[25], Queue64_UInt8_19.io.deq.bits connect remapVecValids[25], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[25] node _T_3150 = eq(UInt<5>(0h14), remapindex_25) when _T_3150 : connect remapVecData[25], Queue64_UInt8_20.io.deq.bits connect remapVecValids[25], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[25] node _T_3151 = eq(UInt<5>(0h15), remapindex_25) when _T_3151 : connect remapVecData[25], Queue64_UInt8_21.io.deq.bits connect remapVecValids[25], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[25] node _T_3152 = eq(UInt<5>(0h16), remapindex_25) when _T_3152 : connect remapVecData[25], Queue64_UInt8_22.io.deq.bits connect remapVecValids[25], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[25] node _T_3153 = eq(UInt<5>(0h17), remapindex_25) when _T_3153 : connect remapVecData[25], Queue64_UInt8_23.io.deq.bits connect remapVecValids[25], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[25] node _T_3154 = eq(UInt<5>(0h18), remapindex_25) when _T_3154 : connect remapVecData[25], Queue64_UInt8_24.io.deq.bits connect remapVecValids[25], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[25] node _T_3155 = eq(UInt<5>(0h19), remapindex_25) when _T_3155 : connect remapVecData[25], Queue64_UInt8_25.io.deq.bits connect remapVecValids[25], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[25] node _T_3156 = eq(UInt<5>(0h1a), remapindex_25) when _T_3156 : connect remapVecData[25], Queue64_UInt8_26.io.deq.bits connect remapVecValids[25], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[25] node _T_3157 = eq(UInt<5>(0h1b), remapindex_25) when _T_3157 : connect remapVecData[25], Queue64_UInt8_27.io.deq.bits connect remapVecValids[25], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[25] node _T_3158 = eq(UInt<5>(0h1c), remapindex_25) when _T_3158 : connect remapVecData[25], Queue64_UInt8_28.io.deq.bits connect remapVecValids[25], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[25] node _T_3159 = eq(UInt<5>(0h1d), remapindex_25) when _T_3159 : connect remapVecData[25], Queue64_UInt8_29.io.deq.bits connect remapVecValids[25], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[25] node _T_3160 = eq(UInt<5>(0h1e), remapindex_25) when _T_3160 : connect remapVecData[25], Queue64_UInt8_30.io.deq.bits connect remapVecValids[25], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[25] node _T_3161 = eq(UInt<5>(0h1f), remapindex_25) when _T_3161 : connect remapVecData[25], Queue64_UInt8_31.io.deq.bits connect remapVecValids[25], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[25] node _remapindex_T_26 = add(UInt<5>(0h1a), read_start_index) node remapindex_26 = rem(_remapindex_T_26, UInt<6>(0h20)) node _T_3162 = eq(UInt<1>(0h0), remapindex_26) when _T_3162 : connect remapVecData[26], Queue64_UInt8.io.deq.bits connect remapVecValids[26], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[26] node _T_3163 = eq(UInt<1>(0h1), remapindex_26) when _T_3163 : connect remapVecData[26], Queue64_UInt8_1.io.deq.bits connect remapVecValids[26], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[26] node _T_3164 = eq(UInt<2>(0h2), remapindex_26) when _T_3164 : connect remapVecData[26], Queue64_UInt8_2.io.deq.bits connect remapVecValids[26], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[26] node _T_3165 = eq(UInt<2>(0h3), remapindex_26) when _T_3165 : connect remapVecData[26], Queue64_UInt8_3.io.deq.bits connect remapVecValids[26], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[26] node _T_3166 = eq(UInt<3>(0h4), remapindex_26) when _T_3166 : connect remapVecData[26], Queue64_UInt8_4.io.deq.bits connect remapVecValids[26], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[26] node _T_3167 = eq(UInt<3>(0h5), remapindex_26) when _T_3167 : connect remapVecData[26], Queue64_UInt8_5.io.deq.bits connect remapVecValids[26], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[26] node _T_3168 = eq(UInt<3>(0h6), remapindex_26) when _T_3168 : connect remapVecData[26], Queue64_UInt8_6.io.deq.bits connect remapVecValids[26], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[26] node _T_3169 = eq(UInt<3>(0h7), remapindex_26) when _T_3169 : connect remapVecData[26], Queue64_UInt8_7.io.deq.bits connect remapVecValids[26], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[26] node _T_3170 = eq(UInt<4>(0h8), remapindex_26) when _T_3170 : connect remapVecData[26], Queue64_UInt8_8.io.deq.bits connect remapVecValids[26], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[26] node _T_3171 = eq(UInt<4>(0h9), remapindex_26) when _T_3171 : connect remapVecData[26], Queue64_UInt8_9.io.deq.bits connect remapVecValids[26], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[26] node _T_3172 = eq(UInt<4>(0ha), remapindex_26) when _T_3172 : connect remapVecData[26], Queue64_UInt8_10.io.deq.bits connect remapVecValids[26], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[26] node _T_3173 = eq(UInt<4>(0hb), remapindex_26) when _T_3173 : connect remapVecData[26], Queue64_UInt8_11.io.deq.bits connect remapVecValids[26], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[26] node _T_3174 = eq(UInt<4>(0hc), remapindex_26) when _T_3174 : connect remapVecData[26], Queue64_UInt8_12.io.deq.bits connect remapVecValids[26], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[26] node _T_3175 = eq(UInt<4>(0hd), remapindex_26) when _T_3175 : connect remapVecData[26], Queue64_UInt8_13.io.deq.bits connect remapVecValids[26], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[26] node _T_3176 = eq(UInt<4>(0he), remapindex_26) when _T_3176 : connect remapVecData[26], Queue64_UInt8_14.io.deq.bits connect remapVecValids[26], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[26] node _T_3177 = eq(UInt<4>(0hf), remapindex_26) when _T_3177 : connect remapVecData[26], Queue64_UInt8_15.io.deq.bits connect remapVecValids[26], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[26] node _T_3178 = eq(UInt<5>(0h10), remapindex_26) when _T_3178 : connect remapVecData[26], Queue64_UInt8_16.io.deq.bits connect remapVecValids[26], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[26] node _T_3179 = eq(UInt<5>(0h11), remapindex_26) when _T_3179 : connect remapVecData[26], Queue64_UInt8_17.io.deq.bits connect remapVecValids[26], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[26] node _T_3180 = eq(UInt<5>(0h12), remapindex_26) when _T_3180 : connect remapVecData[26], Queue64_UInt8_18.io.deq.bits connect remapVecValids[26], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[26] node _T_3181 = eq(UInt<5>(0h13), remapindex_26) when _T_3181 : connect remapVecData[26], Queue64_UInt8_19.io.deq.bits connect remapVecValids[26], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[26] node _T_3182 = eq(UInt<5>(0h14), remapindex_26) when _T_3182 : connect remapVecData[26], Queue64_UInt8_20.io.deq.bits connect remapVecValids[26], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[26] node _T_3183 = eq(UInt<5>(0h15), remapindex_26) when _T_3183 : connect remapVecData[26], Queue64_UInt8_21.io.deq.bits connect remapVecValids[26], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[26] node _T_3184 = eq(UInt<5>(0h16), remapindex_26) when _T_3184 : connect remapVecData[26], Queue64_UInt8_22.io.deq.bits connect remapVecValids[26], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[26] node _T_3185 = eq(UInt<5>(0h17), remapindex_26) when _T_3185 : connect remapVecData[26], Queue64_UInt8_23.io.deq.bits connect remapVecValids[26], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[26] node _T_3186 = eq(UInt<5>(0h18), remapindex_26) when _T_3186 : connect remapVecData[26], Queue64_UInt8_24.io.deq.bits connect remapVecValids[26], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[26] node _T_3187 = eq(UInt<5>(0h19), remapindex_26) when _T_3187 : connect remapVecData[26], Queue64_UInt8_25.io.deq.bits connect remapVecValids[26], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[26] node _T_3188 = eq(UInt<5>(0h1a), remapindex_26) when _T_3188 : connect remapVecData[26], Queue64_UInt8_26.io.deq.bits connect remapVecValids[26], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[26] node _T_3189 = eq(UInt<5>(0h1b), remapindex_26) when _T_3189 : connect remapVecData[26], Queue64_UInt8_27.io.deq.bits connect remapVecValids[26], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[26] node _T_3190 = eq(UInt<5>(0h1c), remapindex_26) when _T_3190 : connect remapVecData[26], Queue64_UInt8_28.io.deq.bits connect remapVecValids[26], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[26] node _T_3191 = eq(UInt<5>(0h1d), remapindex_26) when _T_3191 : connect remapVecData[26], Queue64_UInt8_29.io.deq.bits connect remapVecValids[26], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[26] node _T_3192 = eq(UInt<5>(0h1e), remapindex_26) when _T_3192 : connect remapVecData[26], Queue64_UInt8_30.io.deq.bits connect remapVecValids[26], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[26] node _T_3193 = eq(UInt<5>(0h1f), remapindex_26) when _T_3193 : connect remapVecData[26], Queue64_UInt8_31.io.deq.bits connect remapVecValids[26], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[26] node _remapindex_T_27 = add(UInt<5>(0h1b), read_start_index) node remapindex_27 = rem(_remapindex_T_27, UInt<6>(0h20)) node _T_3194 = eq(UInt<1>(0h0), remapindex_27) when _T_3194 : connect remapVecData[27], Queue64_UInt8.io.deq.bits connect remapVecValids[27], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[27] node _T_3195 = eq(UInt<1>(0h1), remapindex_27) when _T_3195 : connect remapVecData[27], Queue64_UInt8_1.io.deq.bits connect remapVecValids[27], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[27] node _T_3196 = eq(UInt<2>(0h2), remapindex_27) when _T_3196 : connect remapVecData[27], Queue64_UInt8_2.io.deq.bits connect remapVecValids[27], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[27] node _T_3197 = eq(UInt<2>(0h3), remapindex_27) when _T_3197 : connect remapVecData[27], Queue64_UInt8_3.io.deq.bits connect remapVecValids[27], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[27] node _T_3198 = eq(UInt<3>(0h4), remapindex_27) when _T_3198 : connect remapVecData[27], Queue64_UInt8_4.io.deq.bits connect remapVecValids[27], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[27] node _T_3199 = eq(UInt<3>(0h5), remapindex_27) when _T_3199 : connect remapVecData[27], Queue64_UInt8_5.io.deq.bits connect remapVecValids[27], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[27] node _T_3200 = eq(UInt<3>(0h6), remapindex_27) when _T_3200 : connect remapVecData[27], Queue64_UInt8_6.io.deq.bits connect remapVecValids[27], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[27] node _T_3201 = eq(UInt<3>(0h7), remapindex_27) when _T_3201 : connect remapVecData[27], Queue64_UInt8_7.io.deq.bits connect remapVecValids[27], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[27] node _T_3202 = eq(UInt<4>(0h8), remapindex_27) when _T_3202 : connect remapVecData[27], Queue64_UInt8_8.io.deq.bits connect remapVecValids[27], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[27] node _T_3203 = eq(UInt<4>(0h9), remapindex_27) when _T_3203 : connect remapVecData[27], Queue64_UInt8_9.io.deq.bits connect remapVecValids[27], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[27] node _T_3204 = eq(UInt<4>(0ha), remapindex_27) when _T_3204 : connect remapVecData[27], Queue64_UInt8_10.io.deq.bits connect remapVecValids[27], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[27] node _T_3205 = eq(UInt<4>(0hb), remapindex_27) when _T_3205 : connect remapVecData[27], Queue64_UInt8_11.io.deq.bits connect remapVecValids[27], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[27] node _T_3206 = eq(UInt<4>(0hc), remapindex_27) when _T_3206 : connect remapVecData[27], Queue64_UInt8_12.io.deq.bits connect remapVecValids[27], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[27] node _T_3207 = eq(UInt<4>(0hd), remapindex_27) when _T_3207 : connect remapVecData[27], Queue64_UInt8_13.io.deq.bits connect remapVecValids[27], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[27] node _T_3208 = eq(UInt<4>(0he), remapindex_27) when _T_3208 : connect remapVecData[27], Queue64_UInt8_14.io.deq.bits connect remapVecValids[27], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[27] node _T_3209 = eq(UInt<4>(0hf), remapindex_27) when _T_3209 : connect remapVecData[27], Queue64_UInt8_15.io.deq.bits connect remapVecValids[27], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[27] node _T_3210 = eq(UInt<5>(0h10), remapindex_27) when _T_3210 : connect remapVecData[27], Queue64_UInt8_16.io.deq.bits connect remapVecValids[27], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[27] node _T_3211 = eq(UInt<5>(0h11), remapindex_27) when _T_3211 : connect remapVecData[27], Queue64_UInt8_17.io.deq.bits connect remapVecValids[27], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[27] node _T_3212 = eq(UInt<5>(0h12), remapindex_27) when _T_3212 : connect remapVecData[27], Queue64_UInt8_18.io.deq.bits connect remapVecValids[27], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[27] node _T_3213 = eq(UInt<5>(0h13), remapindex_27) when _T_3213 : connect remapVecData[27], Queue64_UInt8_19.io.deq.bits connect remapVecValids[27], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[27] node _T_3214 = eq(UInt<5>(0h14), remapindex_27) when _T_3214 : connect remapVecData[27], Queue64_UInt8_20.io.deq.bits connect remapVecValids[27], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[27] node _T_3215 = eq(UInt<5>(0h15), remapindex_27) when _T_3215 : connect remapVecData[27], Queue64_UInt8_21.io.deq.bits connect remapVecValids[27], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[27] node _T_3216 = eq(UInt<5>(0h16), remapindex_27) when _T_3216 : connect remapVecData[27], Queue64_UInt8_22.io.deq.bits connect remapVecValids[27], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[27] node _T_3217 = eq(UInt<5>(0h17), remapindex_27) when _T_3217 : connect remapVecData[27], Queue64_UInt8_23.io.deq.bits connect remapVecValids[27], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[27] node _T_3218 = eq(UInt<5>(0h18), remapindex_27) when _T_3218 : connect remapVecData[27], Queue64_UInt8_24.io.deq.bits connect remapVecValids[27], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[27] node _T_3219 = eq(UInt<5>(0h19), remapindex_27) when _T_3219 : connect remapVecData[27], Queue64_UInt8_25.io.deq.bits connect remapVecValids[27], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[27] node _T_3220 = eq(UInt<5>(0h1a), remapindex_27) when _T_3220 : connect remapVecData[27], Queue64_UInt8_26.io.deq.bits connect remapVecValids[27], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[27] node _T_3221 = eq(UInt<5>(0h1b), remapindex_27) when _T_3221 : connect remapVecData[27], Queue64_UInt8_27.io.deq.bits connect remapVecValids[27], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[27] node _T_3222 = eq(UInt<5>(0h1c), remapindex_27) when _T_3222 : connect remapVecData[27], Queue64_UInt8_28.io.deq.bits connect remapVecValids[27], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[27] node _T_3223 = eq(UInt<5>(0h1d), remapindex_27) when _T_3223 : connect remapVecData[27], Queue64_UInt8_29.io.deq.bits connect remapVecValids[27], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[27] node _T_3224 = eq(UInt<5>(0h1e), remapindex_27) when _T_3224 : connect remapVecData[27], Queue64_UInt8_30.io.deq.bits connect remapVecValids[27], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[27] node _T_3225 = eq(UInt<5>(0h1f), remapindex_27) when _T_3225 : connect remapVecData[27], Queue64_UInt8_31.io.deq.bits connect remapVecValids[27], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[27] node _remapindex_T_28 = add(UInt<5>(0h1c), read_start_index) node remapindex_28 = rem(_remapindex_T_28, UInt<6>(0h20)) node _T_3226 = eq(UInt<1>(0h0), remapindex_28) when _T_3226 : connect remapVecData[28], Queue64_UInt8.io.deq.bits connect remapVecValids[28], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[28] node _T_3227 = eq(UInt<1>(0h1), remapindex_28) when _T_3227 : connect remapVecData[28], Queue64_UInt8_1.io.deq.bits connect remapVecValids[28], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[28] node _T_3228 = eq(UInt<2>(0h2), remapindex_28) when _T_3228 : connect remapVecData[28], Queue64_UInt8_2.io.deq.bits connect remapVecValids[28], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[28] node _T_3229 = eq(UInt<2>(0h3), remapindex_28) when _T_3229 : connect remapVecData[28], Queue64_UInt8_3.io.deq.bits connect remapVecValids[28], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[28] node _T_3230 = eq(UInt<3>(0h4), remapindex_28) when _T_3230 : connect remapVecData[28], Queue64_UInt8_4.io.deq.bits connect remapVecValids[28], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[28] node _T_3231 = eq(UInt<3>(0h5), remapindex_28) when _T_3231 : connect remapVecData[28], Queue64_UInt8_5.io.deq.bits connect remapVecValids[28], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[28] node _T_3232 = eq(UInt<3>(0h6), remapindex_28) when _T_3232 : connect remapVecData[28], Queue64_UInt8_6.io.deq.bits connect remapVecValids[28], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[28] node _T_3233 = eq(UInt<3>(0h7), remapindex_28) when _T_3233 : connect remapVecData[28], Queue64_UInt8_7.io.deq.bits connect remapVecValids[28], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[28] node _T_3234 = eq(UInt<4>(0h8), remapindex_28) when _T_3234 : connect remapVecData[28], Queue64_UInt8_8.io.deq.bits connect remapVecValids[28], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[28] node _T_3235 = eq(UInt<4>(0h9), remapindex_28) when _T_3235 : connect remapVecData[28], Queue64_UInt8_9.io.deq.bits connect remapVecValids[28], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[28] node _T_3236 = eq(UInt<4>(0ha), remapindex_28) when _T_3236 : connect remapVecData[28], Queue64_UInt8_10.io.deq.bits connect remapVecValids[28], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[28] node _T_3237 = eq(UInt<4>(0hb), remapindex_28) when _T_3237 : connect remapVecData[28], Queue64_UInt8_11.io.deq.bits connect remapVecValids[28], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[28] node _T_3238 = eq(UInt<4>(0hc), remapindex_28) when _T_3238 : connect remapVecData[28], Queue64_UInt8_12.io.deq.bits connect remapVecValids[28], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[28] node _T_3239 = eq(UInt<4>(0hd), remapindex_28) when _T_3239 : connect remapVecData[28], Queue64_UInt8_13.io.deq.bits connect remapVecValids[28], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[28] node _T_3240 = eq(UInt<4>(0he), remapindex_28) when _T_3240 : connect remapVecData[28], Queue64_UInt8_14.io.deq.bits connect remapVecValids[28], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[28] node _T_3241 = eq(UInt<4>(0hf), remapindex_28) when _T_3241 : connect remapVecData[28], Queue64_UInt8_15.io.deq.bits connect remapVecValids[28], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[28] node _T_3242 = eq(UInt<5>(0h10), remapindex_28) when _T_3242 : connect remapVecData[28], Queue64_UInt8_16.io.deq.bits connect remapVecValids[28], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[28] node _T_3243 = eq(UInt<5>(0h11), remapindex_28) when _T_3243 : connect remapVecData[28], Queue64_UInt8_17.io.deq.bits connect remapVecValids[28], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[28] node _T_3244 = eq(UInt<5>(0h12), remapindex_28) when _T_3244 : connect remapVecData[28], Queue64_UInt8_18.io.deq.bits connect remapVecValids[28], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[28] node _T_3245 = eq(UInt<5>(0h13), remapindex_28) when _T_3245 : connect remapVecData[28], Queue64_UInt8_19.io.deq.bits connect remapVecValids[28], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[28] node _T_3246 = eq(UInt<5>(0h14), remapindex_28) when _T_3246 : connect remapVecData[28], Queue64_UInt8_20.io.deq.bits connect remapVecValids[28], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[28] node _T_3247 = eq(UInt<5>(0h15), remapindex_28) when _T_3247 : connect remapVecData[28], Queue64_UInt8_21.io.deq.bits connect remapVecValids[28], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[28] node _T_3248 = eq(UInt<5>(0h16), remapindex_28) when _T_3248 : connect remapVecData[28], Queue64_UInt8_22.io.deq.bits connect remapVecValids[28], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[28] node _T_3249 = eq(UInt<5>(0h17), remapindex_28) when _T_3249 : connect remapVecData[28], Queue64_UInt8_23.io.deq.bits connect remapVecValids[28], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[28] node _T_3250 = eq(UInt<5>(0h18), remapindex_28) when _T_3250 : connect remapVecData[28], Queue64_UInt8_24.io.deq.bits connect remapVecValids[28], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[28] node _T_3251 = eq(UInt<5>(0h19), remapindex_28) when _T_3251 : connect remapVecData[28], Queue64_UInt8_25.io.deq.bits connect remapVecValids[28], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[28] node _T_3252 = eq(UInt<5>(0h1a), remapindex_28) when _T_3252 : connect remapVecData[28], Queue64_UInt8_26.io.deq.bits connect remapVecValids[28], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[28] node _T_3253 = eq(UInt<5>(0h1b), remapindex_28) when _T_3253 : connect remapVecData[28], Queue64_UInt8_27.io.deq.bits connect remapVecValids[28], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[28] node _T_3254 = eq(UInt<5>(0h1c), remapindex_28) when _T_3254 : connect remapVecData[28], Queue64_UInt8_28.io.deq.bits connect remapVecValids[28], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[28] node _T_3255 = eq(UInt<5>(0h1d), remapindex_28) when _T_3255 : connect remapVecData[28], Queue64_UInt8_29.io.deq.bits connect remapVecValids[28], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[28] node _T_3256 = eq(UInt<5>(0h1e), remapindex_28) when _T_3256 : connect remapVecData[28], Queue64_UInt8_30.io.deq.bits connect remapVecValids[28], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[28] node _T_3257 = eq(UInt<5>(0h1f), remapindex_28) when _T_3257 : connect remapVecData[28], Queue64_UInt8_31.io.deq.bits connect remapVecValids[28], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[28] node _remapindex_T_29 = add(UInt<5>(0h1d), read_start_index) node remapindex_29 = rem(_remapindex_T_29, UInt<6>(0h20)) node _T_3258 = eq(UInt<1>(0h0), remapindex_29) when _T_3258 : connect remapVecData[29], Queue64_UInt8.io.deq.bits connect remapVecValids[29], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[29] node _T_3259 = eq(UInt<1>(0h1), remapindex_29) when _T_3259 : connect remapVecData[29], Queue64_UInt8_1.io.deq.bits connect remapVecValids[29], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[29] node _T_3260 = eq(UInt<2>(0h2), remapindex_29) when _T_3260 : connect remapVecData[29], Queue64_UInt8_2.io.deq.bits connect remapVecValids[29], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[29] node _T_3261 = eq(UInt<2>(0h3), remapindex_29) when _T_3261 : connect remapVecData[29], Queue64_UInt8_3.io.deq.bits connect remapVecValids[29], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[29] node _T_3262 = eq(UInt<3>(0h4), remapindex_29) when _T_3262 : connect remapVecData[29], Queue64_UInt8_4.io.deq.bits connect remapVecValids[29], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[29] node _T_3263 = eq(UInt<3>(0h5), remapindex_29) when _T_3263 : connect remapVecData[29], Queue64_UInt8_5.io.deq.bits connect remapVecValids[29], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[29] node _T_3264 = eq(UInt<3>(0h6), remapindex_29) when _T_3264 : connect remapVecData[29], Queue64_UInt8_6.io.deq.bits connect remapVecValids[29], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[29] node _T_3265 = eq(UInt<3>(0h7), remapindex_29) when _T_3265 : connect remapVecData[29], Queue64_UInt8_7.io.deq.bits connect remapVecValids[29], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[29] node _T_3266 = eq(UInt<4>(0h8), remapindex_29) when _T_3266 : connect remapVecData[29], Queue64_UInt8_8.io.deq.bits connect remapVecValids[29], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[29] node _T_3267 = eq(UInt<4>(0h9), remapindex_29) when _T_3267 : connect remapVecData[29], Queue64_UInt8_9.io.deq.bits connect remapVecValids[29], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[29] node _T_3268 = eq(UInt<4>(0ha), remapindex_29) when _T_3268 : connect remapVecData[29], Queue64_UInt8_10.io.deq.bits connect remapVecValids[29], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[29] node _T_3269 = eq(UInt<4>(0hb), remapindex_29) when _T_3269 : connect remapVecData[29], Queue64_UInt8_11.io.deq.bits connect remapVecValids[29], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[29] node _T_3270 = eq(UInt<4>(0hc), remapindex_29) when _T_3270 : connect remapVecData[29], Queue64_UInt8_12.io.deq.bits connect remapVecValids[29], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[29] node _T_3271 = eq(UInt<4>(0hd), remapindex_29) when _T_3271 : connect remapVecData[29], Queue64_UInt8_13.io.deq.bits connect remapVecValids[29], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[29] node _T_3272 = eq(UInt<4>(0he), remapindex_29) when _T_3272 : connect remapVecData[29], Queue64_UInt8_14.io.deq.bits connect remapVecValids[29], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[29] node _T_3273 = eq(UInt<4>(0hf), remapindex_29) when _T_3273 : connect remapVecData[29], Queue64_UInt8_15.io.deq.bits connect remapVecValids[29], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[29] node _T_3274 = eq(UInt<5>(0h10), remapindex_29) when _T_3274 : connect remapVecData[29], Queue64_UInt8_16.io.deq.bits connect remapVecValids[29], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[29] node _T_3275 = eq(UInt<5>(0h11), remapindex_29) when _T_3275 : connect remapVecData[29], Queue64_UInt8_17.io.deq.bits connect remapVecValids[29], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[29] node _T_3276 = eq(UInt<5>(0h12), remapindex_29) when _T_3276 : connect remapVecData[29], Queue64_UInt8_18.io.deq.bits connect remapVecValids[29], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[29] node _T_3277 = eq(UInt<5>(0h13), remapindex_29) when _T_3277 : connect remapVecData[29], Queue64_UInt8_19.io.deq.bits connect remapVecValids[29], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[29] node _T_3278 = eq(UInt<5>(0h14), remapindex_29) when _T_3278 : connect remapVecData[29], Queue64_UInt8_20.io.deq.bits connect remapVecValids[29], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[29] node _T_3279 = eq(UInt<5>(0h15), remapindex_29) when _T_3279 : connect remapVecData[29], Queue64_UInt8_21.io.deq.bits connect remapVecValids[29], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[29] node _T_3280 = eq(UInt<5>(0h16), remapindex_29) when _T_3280 : connect remapVecData[29], Queue64_UInt8_22.io.deq.bits connect remapVecValids[29], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[29] node _T_3281 = eq(UInt<5>(0h17), remapindex_29) when _T_3281 : connect remapVecData[29], Queue64_UInt8_23.io.deq.bits connect remapVecValids[29], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[29] node _T_3282 = eq(UInt<5>(0h18), remapindex_29) when _T_3282 : connect remapVecData[29], Queue64_UInt8_24.io.deq.bits connect remapVecValids[29], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[29] node _T_3283 = eq(UInt<5>(0h19), remapindex_29) when _T_3283 : connect remapVecData[29], Queue64_UInt8_25.io.deq.bits connect remapVecValids[29], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[29] node _T_3284 = eq(UInt<5>(0h1a), remapindex_29) when _T_3284 : connect remapVecData[29], Queue64_UInt8_26.io.deq.bits connect remapVecValids[29], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[29] node _T_3285 = eq(UInt<5>(0h1b), remapindex_29) when _T_3285 : connect remapVecData[29], Queue64_UInt8_27.io.deq.bits connect remapVecValids[29], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[29] node _T_3286 = eq(UInt<5>(0h1c), remapindex_29) when _T_3286 : connect remapVecData[29], Queue64_UInt8_28.io.deq.bits connect remapVecValids[29], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[29] node _T_3287 = eq(UInt<5>(0h1d), remapindex_29) when _T_3287 : connect remapVecData[29], Queue64_UInt8_29.io.deq.bits connect remapVecValids[29], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[29] node _T_3288 = eq(UInt<5>(0h1e), remapindex_29) when _T_3288 : connect remapVecData[29], Queue64_UInt8_30.io.deq.bits connect remapVecValids[29], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[29] node _T_3289 = eq(UInt<5>(0h1f), remapindex_29) when _T_3289 : connect remapVecData[29], Queue64_UInt8_31.io.deq.bits connect remapVecValids[29], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[29] node _remapindex_T_30 = add(UInt<5>(0h1e), read_start_index) node remapindex_30 = rem(_remapindex_T_30, UInt<6>(0h20)) node _T_3290 = eq(UInt<1>(0h0), remapindex_30) when _T_3290 : connect remapVecData[30], Queue64_UInt8.io.deq.bits connect remapVecValids[30], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[30] node _T_3291 = eq(UInt<1>(0h1), remapindex_30) when _T_3291 : connect remapVecData[30], Queue64_UInt8_1.io.deq.bits connect remapVecValids[30], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[30] node _T_3292 = eq(UInt<2>(0h2), remapindex_30) when _T_3292 : connect remapVecData[30], Queue64_UInt8_2.io.deq.bits connect remapVecValids[30], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[30] node _T_3293 = eq(UInt<2>(0h3), remapindex_30) when _T_3293 : connect remapVecData[30], Queue64_UInt8_3.io.deq.bits connect remapVecValids[30], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[30] node _T_3294 = eq(UInt<3>(0h4), remapindex_30) when _T_3294 : connect remapVecData[30], Queue64_UInt8_4.io.deq.bits connect remapVecValids[30], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[30] node _T_3295 = eq(UInt<3>(0h5), remapindex_30) when _T_3295 : connect remapVecData[30], Queue64_UInt8_5.io.deq.bits connect remapVecValids[30], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[30] node _T_3296 = eq(UInt<3>(0h6), remapindex_30) when _T_3296 : connect remapVecData[30], Queue64_UInt8_6.io.deq.bits connect remapVecValids[30], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[30] node _T_3297 = eq(UInt<3>(0h7), remapindex_30) when _T_3297 : connect remapVecData[30], Queue64_UInt8_7.io.deq.bits connect remapVecValids[30], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[30] node _T_3298 = eq(UInt<4>(0h8), remapindex_30) when _T_3298 : connect remapVecData[30], Queue64_UInt8_8.io.deq.bits connect remapVecValids[30], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[30] node _T_3299 = eq(UInt<4>(0h9), remapindex_30) when _T_3299 : connect remapVecData[30], Queue64_UInt8_9.io.deq.bits connect remapVecValids[30], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[30] node _T_3300 = eq(UInt<4>(0ha), remapindex_30) when _T_3300 : connect remapVecData[30], Queue64_UInt8_10.io.deq.bits connect remapVecValids[30], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[30] node _T_3301 = eq(UInt<4>(0hb), remapindex_30) when _T_3301 : connect remapVecData[30], Queue64_UInt8_11.io.deq.bits connect remapVecValids[30], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[30] node _T_3302 = eq(UInt<4>(0hc), remapindex_30) when _T_3302 : connect remapVecData[30], Queue64_UInt8_12.io.deq.bits connect remapVecValids[30], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[30] node _T_3303 = eq(UInt<4>(0hd), remapindex_30) when _T_3303 : connect remapVecData[30], Queue64_UInt8_13.io.deq.bits connect remapVecValids[30], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[30] node _T_3304 = eq(UInt<4>(0he), remapindex_30) when _T_3304 : connect remapVecData[30], Queue64_UInt8_14.io.deq.bits connect remapVecValids[30], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[30] node _T_3305 = eq(UInt<4>(0hf), remapindex_30) when _T_3305 : connect remapVecData[30], Queue64_UInt8_15.io.deq.bits connect remapVecValids[30], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[30] node _T_3306 = eq(UInt<5>(0h10), remapindex_30) when _T_3306 : connect remapVecData[30], Queue64_UInt8_16.io.deq.bits connect remapVecValids[30], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[30] node _T_3307 = eq(UInt<5>(0h11), remapindex_30) when _T_3307 : connect remapVecData[30], Queue64_UInt8_17.io.deq.bits connect remapVecValids[30], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[30] node _T_3308 = eq(UInt<5>(0h12), remapindex_30) when _T_3308 : connect remapVecData[30], Queue64_UInt8_18.io.deq.bits connect remapVecValids[30], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[30] node _T_3309 = eq(UInt<5>(0h13), remapindex_30) when _T_3309 : connect remapVecData[30], Queue64_UInt8_19.io.deq.bits connect remapVecValids[30], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[30] node _T_3310 = eq(UInt<5>(0h14), remapindex_30) when _T_3310 : connect remapVecData[30], Queue64_UInt8_20.io.deq.bits connect remapVecValids[30], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[30] node _T_3311 = eq(UInt<5>(0h15), remapindex_30) when _T_3311 : connect remapVecData[30], Queue64_UInt8_21.io.deq.bits connect remapVecValids[30], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[30] node _T_3312 = eq(UInt<5>(0h16), remapindex_30) when _T_3312 : connect remapVecData[30], Queue64_UInt8_22.io.deq.bits connect remapVecValids[30], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[30] node _T_3313 = eq(UInt<5>(0h17), remapindex_30) when _T_3313 : connect remapVecData[30], Queue64_UInt8_23.io.deq.bits connect remapVecValids[30], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[30] node _T_3314 = eq(UInt<5>(0h18), remapindex_30) when _T_3314 : connect remapVecData[30], Queue64_UInt8_24.io.deq.bits connect remapVecValids[30], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[30] node _T_3315 = eq(UInt<5>(0h19), remapindex_30) when _T_3315 : connect remapVecData[30], Queue64_UInt8_25.io.deq.bits connect remapVecValids[30], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[30] node _T_3316 = eq(UInt<5>(0h1a), remapindex_30) when _T_3316 : connect remapVecData[30], Queue64_UInt8_26.io.deq.bits connect remapVecValids[30], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[30] node _T_3317 = eq(UInt<5>(0h1b), remapindex_30) when _T_3317 : connect remapVecData[30], Queue64_UInt8_27.io.deq.bits connect remapVecValids[30], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[30] node _T_3318 = eq(UInt<5>(0h1c), remapindex_30) when _T_3318 : connect remapVecData[30], Queue64_UInt8_28.io.deq.bits connect remapVecValids[30], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[30] node _T_3319 = eq(UInt<5>(0h1d), remapindex_30) when _T_3319 : connect remapVecData[30], Queue64_UInt8_29.io.deq.bits connect remapVecValids[30], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[30] node _T_3320 = eq(UInt<5>(0h1e), remapindex_30) when _T_3320 : connect remapVecData[30], Queue64_UInt8_30.io.deq.bits connect remapVecValids[30], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[30] node _T_3321 = eq(UInt<5>(0h1f), remapindex_30) when _T_3321 : connect remapVecData[30], Queue64_UInt8_31.io.deq.bits connect remapVecValids[30], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[30] node _remapindex_T_31 = add(UInt<5>(0h1f), read_start_index) node remapindex_31 = rem(_remapindex_T_31, UInt<6>(0h20)) node _T_3322 = eq(UInt<1>(0h0), remapindex_31) when _T_3322 : connect remapVecData[31], Queue64_UInt8.io.deq.bits connect remapVecValids[31], Queue64_UInt8.io.deq.valid connect Queue64_UInt8.io.deq.ready, remapVecReadys[31] node _T_3323 = eq(UInt<1>(0h1), remapindex_31) when _T_3323 : connect remapVecData[31], Queue64_UInt8_1.io.deq.bits connect remapVecValids[31], Queue64_UInt8_1.io.deq.valid connect Queue64_UInt8_1.io.deq.ready, remapVecReadys[31] node _T_3324 = eq(UInt<2>(0h2), remapindex_31) when _T_3324 : connect remapVecData[31], Queue64_UInt8_2.io.deq.bits connect remapVecValids[31], Queue64_UInt8_2.io.deq.valid connect Queue64_UInt8_2.io.deq.ready, remapVecReadys[31] node _T_3325 = eq(UInt<2>(0h3), remapindex_31) when _T_3325 : connect remapVecData[31], Queue64_UInt8_3.io.deq.bits connect remapVecValids[31], Queue64_UInt8_3.io.deq.valid connect Queue64_UInt8_3.io.deq.ready, remapVecReadys[31] node _T_3326 = eq(UInt<3>(0h4), remapindex_31) when _T_3326 : connect remapVecData[31], Queue64_UInt8_4.io.deq.bits connect remapVecValids[31], Queue64_UInt8_4.io.deq.valid connect Queue64_UInt8_4.io.deq.ready, remapVecReadys[31] node _T_3327 = eq(UInt<3>(0h5), remapindex_31) when _T_3327 : connect remapVecData[31], Queue64_UInt8_5.io.deq.bits connect remapVecValids[31], Queue64_UInt8_5.io.deq.valid connect Queue64_UInt8_5.io.deq.ready, remapVecReadys[31] node _T_3328 = eq(UInt<3>(0h6), remapindex_31) when _T_3328 : connect remapVecData[31], Queue64_UInt8_6.io.deq.bits connect remapVecValids[31], Queue64_UInt8_6.io.deq.valid connect Queue64_UInt8_6.io.deq.ready, remapVecReadys[31] node _T_3329 = eq(UInt<3>(0h7), remapindex_31) when _T_3329 : connect remapVecData[31], Queue64_UInt8_7.io.deq.bits connect remapVecValids[31], Queue64_UInt8_7.io.deq.valid connect Queue64_UInt8_7.io.deq.ready, remapVecReadys[31] node _T_3330 = eq(UInt<4>(0h8), remapindex_31) when _T_3330 : connect remapVecData[31], Queue64_UInt8_8.io.deq.bits connect remapVecValids[31], Queue64_UInt8_8.io.deq.valid connect Queue64_UInt8_8.io.deq.ready, remapVecReadys[31] node _T_3331 = eq(UInt<4>(0h9), remapindex_31) when _T_3331 : connect remapVecData[31], Queue64_UInt8_9.io.deq.bits connect remapVecValids[31], Queue64_UInt8_9.io.deq.valid connect Queue64_UInt8_9.io.deq.ready, remapVecReadys[31] node _T_3332 = eq(UInt<4>(0ha), remapindex_31) when _T_3332 : connect remapVecData[31], Queue64_UInt8_10.io.deq.bits connect remapVecValids[31], Queue64_UInt8_10.io.deq.valid connect Queue64_UInt8_10.io.deq.ready, remapVecReadys[31] node _T_3333 = eq(UInt<4>(0hb), remapindex_31) when _T_3333 : connect remapVecData[31], Queue64_UInt8_11.io.deq.bits connect remapVecValids[31], Queue64_UInt8_11.io.deq.valid connect Queue64_UInt8_11.io.deq.ready, remapVecReadys[31] node _T_3334 = eq(UInt<4>(0hc), remapindex_31) when _T_3334 : connect remapVecData[31], Queue64_UInt8_12.io.deq.bits connect remapVecValids[31], Queue64_UInt8_12.io.deq.valid connect Queue64_UInt8_12.io.deq.ready, remapVecReadys[31] node _T_3335 = eq(UInt<4>(0hd), remapindex_31) when _T_3335 : connect remapVecData[31], Queue64_UInt8_13.io.deq.bits connect remapVecValids[31], Queue64_UInt8_13.io.deq.valid connect Queue64_UInt8_13.io.deq.ready, remapVecReadys[31] node _T_3336 = eq(UInt<4>(0he), remapindex_31) when _T_3336 : connect remapVecData[31], Queue64_UInt8_14.io.deq.bits connect remapVecValids[31], Queue64_UInt8_14.io.deq.valid connect Queue64_UInt8_14.io.deq.ready, remapVecReadys[31] node _T_3337 = eq(UInt<4>(0hf), remapindex_31) when _T_3337 : connect remapVecData[31], Queue64_UInt8_15.io.deq.bits connect remapVecValids[31], Queue64_UInt8_15.io.deq.valid connect Queue64_UInt8_15.io.deq.ready, remapVecReadys[31] node _T_3338 = eq(UInt<5>(0h10), remapindex_31) when _T_3338 : connect remapVecData[31], Queue64_UInt8_16.io.deq.bits connect remapVecValids[31], Queue64_UInt8_16.io.deq.valid connect Queue64_UInt8_16.io.deq.ready, remapVecReadys[31] node _T_3339 = eq(UInt<5>(0h11), remapindex_31) when _T_3339 : connect remapVecData[31], Queue64_UInt8_17.io.deq.bits connect remapVecValids[31], Queue64_UInt8_17.io.deq.valid connect Queue64_UInt8_17.io.deq.ready, remapVecReadys[31] node _T_3340 = eq(UInt<5>(0h12), remapindex_31) when _T_3340 : connect remapVecData[31], Queue64_UInt8_18.io.deq.bits connect remapVecValids[31], Queue64_UInt8_18.io.deq.valid connect Queue64_UInt8_18.io.deq.ready, remapVecReadys[31] node _T_3341 = eq(UInt<5>(0h13), remapindex_31) when _T_3341 : connect remapVecData[31], Queue64_UInt8_19.io.deq.bits connect remapVecValids[31], Queue64_UInt8_19.io.deq.valid connect Queue64_UInt8_19.io.deq.ready, remapVecReadys[31] node _T_3342 = eq(UInt<5>(0h14), remapindex_31) when _T_3342 : connect remapVecData[31], Queue64_UInt8_20.io.deq.bits connect remapVecValids[31], Queue64_UInt8_20.io.deq.valid connect Queue64_UInt8_20.io.deq.ready, remapVecReadys[31] node _T_3343 = eq(UInt<5>(0h15), remapindex_31) when _T_3343 : connect remapVecData[31], Queue64_UInt8_21.io.deq.bits connect remapVecValids[31], Queue64_UInt8_21.io.deq.valid connect Queue64_UInt8_21.io.deq.ready, remapVecReadys[31] node _T_3344 = eq(UInt<5>(0h16), remapindex_31) when _T_3344 : connect remapVecData[31], Queue64_UInt8_22.io.deq.bits connect remapVecValids[31], Queue64_UInt8_22.io.deq.valid connect Queue64_UInt8_22.io.deq.ready, remapVecReadys[31] node _T_3345 = eq(UInt<5>(0h17), remapindex_31) when _T_3345 : connect remapVecData[31], Queue64_UInt8_23.io.deq.bits connect remapVecValids[31], Queue64_UInt8_23.io.deq.valid connect Queue64_UInt8_23.io.deq.ready, remapVecReadys[31] node _T_3346 = eq(UInt<5>(0h18), remapindex_31) when _T_3346 : connect remapVecData[31], Queue64_UInt8_24.io.deq.bits connect remapVecValids[31], Queue64_UInt8_24.io.deq.valid connect Queue64_UInt8_24.io.deq.ready, remapVecReadys[31] node _T_3347 = eq(UInt<5>(0h19), remapindex_31) when _T_3347 : connect remapVecData[31], Queue64_UInt8_25.io.deq.bits connect remapVecValids[31], Queue64_UInt8_25.io.deq.valid connect Queue64_UInt8_25.io.deq.ready, remapVecReadys[31] node _T_3348 = eq(UInt<5>(0h1a), remapindex_31) when _T_3348 : connect remapVecData[31], Queue64_UInt8_26.io.deq.bits connect remapVecValids[31], Queue64_UInt8_26.io.deq.valid connect Queue64_UInt8_26.io.deq.ready, remapVecReadys[31] node _T_3349 = eq(UInt<5>(0h1b), remapindex_31) when _T_3349 : connect remapVecData[31], Queue64_UInt8_27.io.deq.bits connect remapVecValids[31], Queue64_UInt8_27.io.deq.valid connect Queue64_UInt8_27.io.deq.ready, remapVecReadys[31] node _T_3350 = eq(UInt<5>(0h1c), remapindex_31) when _T_3350 : connect remapVecData[31], Queue64_UInt8_28.io.deq.bits connect remapVecValids[31], Queue64_UInt8_28.io.deq.valid connect Queue64_UInt8_28.io.deq.ready, remapVecReadys[31] node _T_3351 = eq(UInt<5>(0h1d), remapindex_31) when _T_3351 : connect remapVecData[31], Queue64_UInt8_29.io.deq.bits connect remapVecValids[31], Queue64_UInt8_29.io.deq.valid connect Queue64_UInt8_29.io.deq.ready, remapVecReadys[31] node _T_3352 = eq(UInt<5>(0h1e), remapindex_31) when _T_3352 : connect remapVecData[31], Queue64_UInt8_30.io.deq.bits connect remapVecValids[31], Queue64_UInt8_30.io.deq.valid connect Queue64_UInt8_30.io.deq.ready, remapVecReadys[31] node _T_3353 = eq(UInt<5>(0h1f), remapindex_31) when _T_3353 : connect remapVecData[31], Queue64_UInt8_31.io.deq.bits connect remapVecValids[31], Queue64_UInt8_31.io.deq.valid connect Queue64_UInt8_31.io.deq.ready, remapVecReadys[31] node io_consumer_output_data_lo_lo_lo_lo = cat(remapVecData[1], remapVecData[0]) node io_consumer_output_data_lo_lo_lo_hi = cat(remapVecData[3], remapVecData[2]) node io_consumer_output_data_lo_lo_lo = cat(io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo) node io_consumer_output_data_lo_lo_hi_lo = cat(remapVecData[5], remapVecData[4]) node io_consumer_output_data_lo_lo_hi_hi = cat(remapVecData[7], remapVecData[6]) node io_consumer_output_data_lo_lo_hi = cat(io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo) node io_consumer_output_data_lo_lo = cat(io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo) node io_consumer_output_data_lo_hi_lo_lo = cat(remapVecData[9], remapVecData[8]) node io_consumer_output_data_lo_hi_lo_hi = cat(remapVecData[11], remapVecData[10]) node io_consumer_output_data_lo_hi_lo = cat(io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo) node io_consumer_output_data_lo_hi_hi_lo = cat(remapVecData[13], remapVecData[12]) node io_consumer_output_data_lo_hi_hi_hi = cat(remapVecData[15], remapVecData[14]) node io_consumer_output_data_lo_hi_hi = cat(io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo) node io_consumer_output_data_lo_hi = cat(io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo) node io_consumer_output_data_lo = cat(io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo) node io_consumer_output_data_hi_lo_lo_lo = cat(remapVecData[17], remapVecData[16]) node io_consumer_output_data_hi_lo_lo_hi = cat(remapVecData[19], remapVecData[18]) node io_consumer_output_data_hi_lo_lo = cat(io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo) node io_consumer_output_data_hi_lo_hi_lo = cat(remapVecData[21], remapVecData[20]) node io_consumer_output_data_hi_lo_hi_hi = cat(remapVecData[23], remapVecData[22]) node io_consumer_output_data_hi_lo_hi = cat(io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo) node io_consumer_output_data_hi_lo = cat(io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo) node io_consumer_output_data_hi_hi_lo_lo = cat(remapVecData[25], remapVecData[24]) node io_consumer_output_data_hi_hi_lo_hi = cat(remapVecData[27], remapVecData[26]) node io_consumer_output_data_hi_hi_lo = cat(io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo) node io_consumer_output_data_hi_hi_hi_lo = cat(remapVecData[29], remapVecData[28]) node io_consumer_output_data_hi_hi_hi_hi = cat(remapVecData[31], remapVecData[30]) node io_consumer_output_data_hi_hi_hi = cat(io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo) node io_consumer_output_data_hi_hi = cat(io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo) node io_consumer_output_data_hi = cat(io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo) node _io_consumer_output_data_T = cat(io_consumer_output_data_hi, io_consumer_output_data_lo) connect io.consumer.output_data, _io_consumer_output_data_T node _buf_last_T = add(len_already_consumed, io.consumer.user_consumed_bytes) node _buf_last_T_1 = tail(_buf_last_T, 1) node buf_last = eq(_buf_last_T_1, buf_info_queue.io.deq.bits.len_bytes) node _count_valids_T = add(remapVecValids[0], remapVecValids[1]) node _count_valids_T_1 = add(_count_valids_T, remapVecValids[2]) node _count_valids_T_2 = add(_count_valids_T_1, remapVecValids[3]) node _count_valids_T_3 = add(_count_valids_T_2, remapVecValids[4]) node _count_valids_T_4 = add(_count_valids_T_3, remapVecValids[5]) node _count_valids_T_5 = add(_count_valids_T_4, remapVecValids[6]) node _count_valids_T_6 = add(_count_valids_T_5, remapVecValids[7]) node _count_valids_T_7 = add(_count_valids_T_6, remapVecValids[8]) node _count_valids_T_8 = add(_count_valids_T_7, remapVecValids[9]) node _count_valids_T_9 = add(_count_valids_T_8, remapVecValids[10]) node _count_valids_T_10 = add(_count_valids_T_9, remapVecValids[11]) node _count_valids_T_11 = add(_count_valids_T_10, remapVecValids[12]) node _count_valids_T_12 = add(_count_valids_T_11, remapVecValids[13]) node _count_valids_T_13 = add(_count_valids_T_12, remapVecValids[14]) node _count_valids_T_14 = add(_count_valids_T_13, remapVecValids[15]) node _count_valids_T_15 = add(_count_valids_T_14, remapVecValids[16]) node _count_valids_T_16 = add(_count_valids_T_15, remapVecValids[17]) node _count_valids_T_17 = add(_count_valids_T_16, remapVecValids[18]) node _count_valids_T_18 = add(_count_valids_T_17, remapVecValids[19]) node _count_valids_T_19 = add(_count_valids_T_18, remapVecValids[20]) node _count_valids_T_20 = add(_count_valids_T_19, remapVecValids[21]) node _count_valids_T_21 = add(_count_valids_T_20, remapVecValids[22]) node _count_valids_T_22 = add(_count_valids_T_21, remapVecValids[23]) node _count_valids_T_23 = add(_count_valids_T_22, remapVecValids[24]) node _count_valids_T_24 = add(_count_valids_T_23, remapVecValids[25]) node _count_valids_T_25 = add(_count_valids_T_24, remapVecValids[26]) node _count_valids_T_26 = add(_count_valids_T_25, remapVecValids[27]) node _count_valids_T_27 = add(_count_valids_T_26, remapVecValids[28]) node _count_valids_T_28 = add(_count_valids_T_27, remapVecValids[29]) node _count_valids_T_29 = add(_count_valids_T_28, remapVecValids[30]) node count_valids = add(_count_valids_T_29, remapVecValids[31]) node _unconsumed_bytes_so_far_T = sub(buf_info_queue.io.deq.bits.len_bytes, len_already_consumed) node unconsumed_bytes_so_far = tail(_unconsumed_bytes_so_far_T, 1) node _enough_data_T = geq(unconsumed_bytes_so_far, UInt<6>(0h20)) node _enough_data_T_1 = eq(count_valids, UInt<6>(0h20)) node _enough_data_T_2 = geq(count_valids, unconsumed_bytes_so_far) node enough_data = mux(_enough_data_T, _enough_data_T_1, _enough_data_T_2) node _io_consumer_available_output_bytes_T = geq(unconsumed_bytes_so_far, UInt<6>(0h20)) node _io_consumer_available_output_bytes_T_1 = mux(_io_consumer_available_output_bytes_T, UInt<6>(0h20), unconsumed_bytes_so_far) connect io.consumer.available_output_bytes, _io_consumer_available_output_bytes_T_1 node _io_consumer_output_last_chunk_T = leq(unconsumed_bytes_so_far, UInt<6>(0h20)) connect io.consumer.output_last_chunk, _io_consumer_output_last_chunk_T node _T_3354 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _T_3355 = and(_T_3354, enough_data) when _T_3355 : regreset loginfo_cycles_44 : UInt<64>, clock, reset, UInt<64>(0h0) node _loginfo_cycles_T_88 = add(loginfo_cycles_44, UInt<1>(0h1)) node _loginfo_cycles_T_89 = tail(_loginfo_cycles_T_88, 1) connect loginfo_cycles_44, _loginfo_cycles_T_89 node _T_3356 = asUInt(reset) node _T_3357 = eq(_T_3356, UInt<1>(0h0)) when _T_3357 : printf(clock, UInt<1>(0h1), "cy: %d, ", loginfo_cycles_44) : printf_88 node _T_3358 = asUInt(reset) node _T_3359 = eq(_T_3358, UInt<1>(0h0)) when _T_3359 : printf(clock, UInt<1>(0h1), "MEMLOADER READ: bytesread %d\n", io.consumer.user_consumed_bytes) : printf_89 node _io_consumer_output_valid_T = and(buf_info_queue.io.deq.valid, enough_data) connect io.consumer.output_valid, _io_consumer_output_valid_T node _remapVecReadys_0_T = lt(UInt<1>(0h0), io.consumer.user_consumed_bytes) node _remapVecReadys_0_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_0_T_2 = and(_remapVecReadys_0_T_1, enough_data) node _remapVecReadys_0_T_3 = and(_remapVecReadys_0_T, _remapVecReadys_0_T_2) connect remapVecReadys[0], _remapVecReadys_0_T_3 node _remapVecReadys_1_T = lt(UInt<1>(0h1), io.consumer.user_consumed_bytes) node _remapVecReadys_1_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_1_T_2 = and(_remapVecReadys_1_T_1, enough_data) node _remapVecReadys_1_T_3 = and(_remapVecReadys_1_T, _remapVecReadys_1_T_2) connect remapVecReadys[1], _remapVecReadys_1_T_3 node _remapVecReadys_2_T = lt(UInt<2>(0h2), io.consumer.user_consumed_bytes) node _remapVecReadys_2_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_2_T_2 = and(_remapVecReadys_2_T_1, enough_data) node _remapVecReadys_2_T_3 = and(_remapVecReadys_2_T, _remapVecReadys_2_T_2) connect remapVecReadys[2], _remapVecReadys_2_T_3 node _remapVecReadys_3_T = lt(UInt<2>(0h3), io.consumer.user_consumed_bytes) node _remapVecReadys_3_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_3_T_2 = and(_remapVecReadys_3_T_1, enough_data) node _remapVecReadys_3_T_3 = and(_remapVecReadys_3_T, _remapVecReadys_3_T_2) connect remapVecReadys[3], _remapVecReadys_3_T_3 node _remapVecReadys_4_T = lt(UInt<3>(0h4), io.consumer.user_consumed_bytes) node _remapVecReadys_4_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_4_T_2 = and(_remapVecReadys_4_T_1, enough_data) node _remapVecReadys_4_T_3 = and(_remapVecReadys_4_T, _remapVecReadys_4_T_2) connect remapVecReadys[4], _remapVecReadys_4_T_3 node _remapVecReadys_5_T = lt(UInt<3>(0h5), io.consumer.user_consumed_bytes) node _remapVecReadys_5_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_5_T_2 = and(_remapVecReadys_5_T_1, enough_data) node _remapVecReadys_5_T_3 = and(_remapVecReadys_5_T, _remapVecReadys_5_T_2) connect remapVecReadys[5], _remapVecReadys_5_T_3 node _remapVecReadys_6_T = lt(UInt<3>(0h6), io.consumer.user_consumed_bytes) node _remapVecReadys_6_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_6_T_2 = and(_remapVecReadys_6_T_1, enough_data) node _remapVecReadys_6_T_3 = and(_remapVecReadys_6_T, _remapVecReadys_6_T_2) connect remapVecReadys[6], _remapVecReadys_6_T_3 node _remapVecReadys_7_T = lt(UInt<3>(0h7), io.consumer.user_consumed_bytes) node _remapVecReadys_7_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_7_T_2 = and(_remapVecReadys_7_T_1, enough_data) node _remapVecReadys_7_T_3 = and(_remapVecReadys_7_T, _remapVecReadys_7_T_2) connect remapVecReadys[7], _remapVecReadys_7_T_3 node _remapVecReadys_8_T = lt(UInt<4>(0h8), io.consumer.user_consumed_bytes) node _remapVecReadys_8_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_8_T_2 = and(_remapVecReadys_8_T_1, enough_data) node _remapVecReadys_8_T_3 = and(_remapVecReadys_8_T, _remapVecReadys_8_T_2) connect remapVecReadys[8], _remapVecReadys_8_T_3 node _remapVecReadys_9_T = lt(UInt<4>(0h9), io.consumer.user_consumed_bytes) node _remapVecReadys_9_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_9_T_2 = and(_remapVecReadys_9_T_1, enough_data) node _remapVecReadys_9_T_3 = and(_remapVecReadys_9_T, _remapVecReadys_9_T_2) connect remapVecReadys[9], _remapVecReadys_9_T_3 node _remapVecReadys_10_T = lt(UInt<4>(0ha), io.consumer.user_consumed_bytes) node _remapVecReadys_10_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_10_T_2 = and(_remapVecReadys_10_T_1, enough_data) node _remapVecReadys_10_T_3 = and(_remapVecReadys_10_T, _remapVecReadys_10_T_2) connect remapVecReadys[10], _remapVecReadys_10_T_3 node _remapVecReadys_11_T = lt(UInt<4>(0hb), io.consumer.user_consumed_bytes) node _remapVecReadys_11_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_11_T_2 = and(_remapVecReadys_11_T_1, enough_data) node _remapVecReadys_11_T_3 = and(_remapVecReadys_11_T, _remapVecReadys_11_T_2) connect remapVecReadys[11], _remapVecReadys_11_T_3 node _remapVecReadys_12_T = lt(UInt<4>(0hc), io.consumer.user_consumed_bytes) node _remapVecReadys_12_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_12_T_2 = and(_remapVecReadys_12_T_1, enough_data) node _remapVecReadys_12_T_3 = and(_remapVecReadys_12_T, _remapVecReadys_12_T_2) connect remapVecReadys[12], _remapVecReadys_12_T_3 node _remapVecReadys_13_T = lt(UInt<4>(0hd), io.consumer.user_consumed_bytes) node _remapVecReadys_13_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_13_T_2 = and(_remapVecReadys_13_T_1, enough_data) node _remapVecReadys_13_T_3 = and(_remapVecReadys_13_T, _remapVecReadys_13_T_2) connect remapVecReadys[13], _remapVecReadys_13_T_3 node _remapVecReadys_14_T = lt(UInt<4>(0he), io.consumer.user_consumed_bytes) node _remapVecReadys_14_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_14_T_2 = and(_remapVecReadys_14_T_1, enough_data) node _remapVecReadys_14_T_3 = and(_remapVecReadys_14_T, _remapVecReadys_14_T_2) connect remapVecReadys[14], _remapVecReadys_14_T_3 node _remapVecReadys_15_T = lt(UInt<4>(0hf), io.consumer.user_consumed_bytes) node _remapVecReadys_15_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_15_T_2 = and(_remapVecReadys_15_T_1, enough_data) node _remapVecReadys_15_T_3 = and(_remapVecReadys_15_T, _remapVecReadys_15_T_2) connect remapVecReadys[15], _remapVecReadys_15_T_3 node _remapVecReadys_16_T = lt(UInt<5>(0h10), io.consumer.user_consumed_bytes) node _remapVecReadys_16_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_16_T_2 = and(_remapVecReadys_16_T_1, enough_data) node _remapVecReadys_16_T_3 = and(_remapVecReadys_16_T, _remapVecReadys_16_T_2) connect remapVecReadys[16], _remapVecReadys_16_T_3 node _remapVecReadys_17_T = lt(UInt<5>(0h11), io.consumer.user_consumed_bytes) node _remapVecReadys_17_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_17_T_2 = and(_remapVecReadys_17_T_1, enough_data) node _remapVecReadys_17_T_3 = and(_remapVecReadys_17_T, _remapVecReadys_17_T_2) connect remapVecReadys[17], _remapVecReadys_17_T_3 node _remapVecReadys_18_T = lt(UInt<5>(0h12), io.consumer.user_consumed_bytes) node _remapVecReadys_18_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_18_T_2 = and(_remapVecReadys_18_T_1, enough_data) node _remapVecReadys_18_T_3 = and(_remapVecReadys_18_T, _remapVecReadys_18_T_2) connect remapVecReadys[18], _remapVecReadys_18_T_3 node _remapVecReadys_19_T = lt(UInt<5>(0h13), io.consumer.user_consumed_bytes) node _remapVecReadys_19_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_19_T_2 = and(_remapVecReadys_19_T_1, enough_data) node _remapVecReadys_19_T_3 = and(_remapVecReadys_19_T, _remapVecReadys_19_T_2) connect remapVecReadys[19], _remapVecReadys_19_T_3 node _remapVecReadys_20_T = lt(UInt<5>(0h14), io.consumer.user_consumed_bytes) node _remapVecReadys_20_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_20_T_2 = and(_remapVecReadys_20_T_1, enough_data) node _remapVecReadys_20_T_3 = and(_remapVecReadys_20_T, _remapVecReadys_20_T_2) connect remapVecReadys[20], _remapVecReadys_20_T_3 node _remapVecReadys_21_T = lt(UInt<5>(0h15), io.consumer.user_consumed_bytes) node _remapVecReadys_21_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_21_T_2 = and(_remapVecReadys_21_T_1, enough_data) node _remapVecReadys_21_T_3 = and(_remapVecReadys_21_T, _remapVecReadys_21_T_2) connect remapVecReadys[21], _remapVecReadys_21_T_3 node _remapVecReadys_22_T = lt(UInt<5>(0h16), io.consumer.user_consumed_bytes) node _remapVecReadys_22_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_22_T_2 = and(_remapVecReadys_22_T_1, enough_data) node _remapVecReadys_22_T_3 = and(_remapVecReadys_22_T, _remapVecReadys_22_T_2) connect remapVecReadys[22], _remapVecReadys_22_T_3 node _remapVecReadys_23_T = lt(UInt<5>(0h17), io.consumer.user_consumed_bytes) node _remapVecReadys_23_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_23_T_2 = and(_remapVecReadys_23_T_1, enough_data) node _remapVecReadys_23_T_3 = and(_remapVecReadys_23_T, _remapVecReadys_23_T_2) connect remapVecReadys[23], _remapVecReadys_23_T_3 node _remapVecReadys_24_T = lt(UInt<5>(0h18), io.consumer.user_consumed_bytes) node _remapVecReadys_24_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_24_T_2 = and(_remapVecReadys_24_T_1, enough_data) node _remapVecReadys_24_T_3 = and(_remapVecReadys_24_T, _remapVecReadys_24_T_2) connect remapVecReadys[24], _remapVecReadys_24_T_3 node _remapVecReadys_25_T = lt(UInt<5>(0h19), io.consumer.user_consumed_bytes) node _remapVecReadys_25_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_25_T_2 = and(_remapVecReadys_25_T_1, enough_data) node _remapVecReadys_25_T_3 = and(_remapVecReadys_25_T, _remapVecReadys_25_T_2) connect remapVecReadys[25], _remapVecReadys_25_T_3 node _remapVecReadys_26_T = lt(UInt<5>(0h1a), io.consumer.user_consumed_bytes) node _remapVecReadys_26_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_26_T_2 = and(_remapVecReadys_26_T_1, enough_data) node _remapVecReadys_26_T_3 = and(_remapVecReadys_26_T, _remapVecReadys_26_T_2) connect remapVecReadys[26], _remapVecReadys_26_T_3 node _remapVecReadys_27_T = lt(UInt<5>(0h1b), io.consumer.user_consumed_bytes) node _remapVecReadys_27_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_27_T_2 = and(_remapVecReadys_27_T_1, enough_data) node _remapVecReadys_27_T_3 = and(_remapVecReadys_27_T, _remapVecReadys_27_T_2) connect remapVecReadys[27], _remapVecReadys_27_T_3 node _remapVecReadys_28_T = lt(UInt<5>(0h1c), io.consumer.user_consumed_bytes) node _remapVecReadys_28_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_28_T_2 = and(_remapVecReadys_28_T_1, enough_data) node _remapVecReadys_28_T_3 = and(_remapVecReadys_28_T, _remapVecReadys_28_T_2) connect remapVecReadys[28], _remapVecReadys_28_T_3 node _remapVecReadys_29_T = lt(UInt<5>(0h1d), io.consumer.user_consumed_bytes) node _remapVecReadys_29_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_29_T_2 = and(_remapVecReadys_29_T_1, enough_data) node _remapVecReadys_29_T_3 = and(_remapVecReadys_29_T, _remapVecReadys_29_T_2) connect remapVecReadys[29], _remapVecReadys_29_T_3 node _remapVecReadys_30_T = lt(UInt<5>(0h1e), io.consumer.user_consumed_bytes) node _remapVecReadys_30_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_30_T_2 = and(_remapVecReadys_30_T_1, enough_data) node _remapVecReadys_30_T_3 = and(_remapVecReadys_30_T, _remapVecReadys_30_T_2) connect remapVecReadys[30], _remapVecReadys_30_T_3 node _remapVecReadys_31_T = lt(UInt<5>(0h1f), io.consumer.user_consumed_bytes) node _remapVecReadys_31_T_1 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _remapVecReadys_31_T_2 = and(_remapVecReadys_31_T_1, enough_data) node _remapVecReadys_31_T_3 = and(_remapVecReadys_31_T, _remapVecReadys_31_T_2) connect remapVecReadys[31], _remapVecReadys_31_T_3 node _T_3360 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _T_3361 = and(_T_3360, enough_data) when _T_3361 : node _read_start_index_T = add(read_start_index, io.consumer.user_consumed_bytes) node _read_start_index_T_1 = rem(_read_start_index_T, UInt<6>(0h20)) connect read_start_index, _read_start_index_T_1 node _buf_info_queue_io_deq_ready_T = and(io.consumer.output_ready, enough_data) node _buf_info_queue_io_deq_ready_T_1 = and(_buf_info_queue_io_deq_ready_T, buf_last) connect buf_info_queue.io.deq.ready, _buf_info_queue_io_deq_ready_T_1 node _T_3362 = and(io.consumer.output_ready, buf_info_queue.io.deq.valid) node _T_3363 = and(_T_3362, enough_data) when _T_3363 : when buf_last : connect len_already_consumed, UInt<1>(0h0) else : node _len_already_consumed_T = add(len_already_consumed, io.consumer.user_consumed_bytes) node _len_already_consumed_T_1 = tail(_len_already_consumed_T, 1) connect len_already_consumed, _len_already_consumed_T_1
module MemLoader_1( // @[MemLoader.scala:15:7] input clock, // @[MemLoader.scala:15:7] input reset, // @[MemLoader.scala:15:7] input io_l2helperUser_req_ready, // @[MemLoader.scala:18:14] output io_l2helperUser_req_valid, // @[MemLoader.scala:18:14] output [70:0] io_l2helperUser_req_bits_addr, // @[MemLoader.scala:18:14] output io_l2helperUser_resp_ready, // @[MemLoader.scala:18:14] input io_l2helperUser_resp_valid, // @[MemLoader.scala:18:14] input [255:0] io_l2helperUser_resp_bits_data, // @[MemLoader.scala:18:14] input io_l2helperUser_no_memops_inflight, // @[MemLoader.scala:18:14] output io_src_info_ready, // @[MemLoader.scala:18:14] input io_src_info_valid, // @[MemLoader.scala:18:14] input [63:0] io_src_info_bits_ip, // @[MemLoader.scala:18:14] input [63:0] io_src_info_bits_isize, // @[MemLoader.scala:18:14] input [5:0] io_consumer_user_consumed_bytes, // @[MemLoader.scala:18:14] output [5:0] io_consumer_available_output_bytes, // @[MemLoader.scala:18:14] output io_consumer_output_valid, // @[MemLoader.scala:18:14] input io_consumer_output_ready, // @[MemLoader.scala:18:14] output [255:0] io_consumer_output_data, // @[MemLoader.scala:18:14] output io_consumer_output_last_chunk // @[MemLoader.scala:18:14] ); wire _Queue64_UInt8_31_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_31_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_31_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_30_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_30_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_30_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_29_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_29_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_29_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_28_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_28_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_28_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_27_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_27_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_27_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_26_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_26_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_26_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_25_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_25_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_25_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_24_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_24_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_24_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_23_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_23_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_23_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_22_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_22_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_22_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_21_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_21_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_21_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_20_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_20_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_20_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_19_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_19_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_19_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_18_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_18_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_18_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_17_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_17_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_17_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_16_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_16_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_16_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_15_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_15_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_15_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_14_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_14_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_14_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_13_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_13_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_13_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_12_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_12_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_12_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_11_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_11_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_11_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_10_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_10_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_10_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_9_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_9_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_9_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_8_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_8_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_8_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_7_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_7_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_7_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_6_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_6_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_6_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_5_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_5_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_5_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_4_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_4_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_4_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_3_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_3_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_3_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_2_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_2_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_2_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_1_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_1_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_1_io_deq_bits; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_io_enq_ready; // @[MemLoader.scala:106:52] wire _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52] wire [7:0] _Queue64_UInt8_io_deq_bits; // @[MemLoader.scala:106:52] wire _load_info_queue_io_enq_ready; // @[MemLoader.scala:28:31] wire _load_info_queue_io_deq_valid; // @[MemLoader.scala:28:31] wire [4:0] _load_info_queue_io_deq_bits_start_byte; // @[MemLoader.scala:28:31] wire [4:0] _load_info_queue_io_deq_bits_end_byte; // @[MemLoader.scala:28:31] wire _buf_info_queue_io_enq_ready; // @[MemLoader.scala:26:30] wire _buf_info_queue_io_deq_valid; // @[MemLoader.scala:26:30] wire [63:0] _buf_info_queue_io_deq_bits_len_bytes; // @[MemLoader.scala:26:30] wire io_l2helperUser_req_ready_0 = io_l2helperUser_req_ready; // @[MemLoader.scala:15:7] wire io_l2helperUser_resp_valid_0 = io_l2helperUser_resp_valid; // @[MemLoader.scala:15:7] wire [255:0] io_l2helperUser_resp_bits_data_0 = io_l2helperUser_resp_bits_data; // @[MemLoader.scala:15:7] wire io_l2helperUser_no_memops_inflight_0 = io_l2helperUser_no_memops_inflight; // @[MemLoader.scala:15:7] wire io_src_info_valid_0 = io_src_info_valid; // @[MemLoader.scala:15:7] wire [63:0] io_src_info_bits_ip_0 = io_src_info_bits_ip; // @[MemLoader.scala:15:7] wire [63:0] io_src_info_bits_isize_0 = io_src_info_bits_isize; // @[MemLoader.scala:15:7] wire [5:0] io_consumer_user_consumed_bytes_0 = io_consumer_user_consumed_bytes; // @[MemLoader.scala:15:7] wire io_consumer_output_ready_0 = io_consumer_output_ready; // @[MemLoader.scala:15:7] wire [2:0] io_l2helperUser_req_bits_size = 3'h5; // @[MemLoader.scala:15:7] wire [255:0] io_l2helperUser_req_bits_data = 256'h0; // @[MemLoader.scala:15:7] wire io_l2helperUser_req_bits_cmd = 1'h0; // @[MemLoader.scala:15:7] wire _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53] wire [70:0] _io_l2helperUser_req_bits_addr_T_2; // @[MemLoader.scala:100:62] wire _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53] wire _io_src_info_ready_T_3; // @[Misc.scala:26:53] wire _io_consumer_output_valid_T; // @[Misc.scala:26:53] wire [255:0] _io_consumer_output_data_T; // @[MemLoader.scala:186:33] wire _io_consumer_output_last_chunk_T; // @[MemLoader.scala:201:61] wire [70:0] io_l2helperUser_req_bits_addr_0; // @[MemLoader.scala:15:7] wire io_l2helperUser_req_valid_0; // @[MemLoader.scala:15:7] wire io_l2helperUser_resp_ready_0; // @[MemLoader.scala:15:7] wire io_src_info_ready_0; // @[MemLoader.scala:15:7] wire [5:0] io_consumer_available_output_bytes_0; // @[MemLoader.scala:15:7] wire io_consumer_output_valid_0; // @[MemLoader.scala:15:7] wire [255:0] io_consumer_output_data_0; // @[MemLoader.scala:15:7] wire io_consumer_output_last_chunk_0; // @[MemLoader.scala:15:7] wire [63:0] base_addr_start_index = {59'h0, io_src_info_bits_ip_0[4:0]}; // @[MemLoader.scala:15:7, :32:51] wire [64:0] _GEN = {1'h0, io_src_info_bits_isize_0} + {1'h0, base_addr_start_index}; // @[MemLoader.scala:15:7, :32:51, :33:35] wire [64:0] _aligned_loadlen_T; // @[MemLoader.scala:33:35] assign _aligned_loadlen_T = _GEN; // @[MemLoader.scala:33:35] wire [64:0] _base_addr_end_index_T; // @[MemLoader.scala:34:39] assign _base_addr_end_index_T = _GEN; // @[MemLoader.scala:33:35, :34:39] wire [64:0] _base_addr_end_index_inclusive_T; // @[MemLoader.scala:35:49] assign _base_addr_end_index_inclusive_T = _GEN; // @[MemLoader.scala:33:35, :35:49] wire [63:0] aligned_loadlen = _aligned_loadlen_T[63:0]; // @[MemLoader.scala:33:35] wire [63:0] _base_addr_end_index_T_1 = _base_addr_end_index_T[63:0]; // @[MemLoader.scala:34:39] wire [63:0] base_addr_end_index = {59'h0, _base_addr_end_index_T_1[4:0]}; // @[MemLoader.scala:34:{39,64}] wire [63:0] _base_addr_end_index_inclusive_T_1 = _base_addr_end_index_inclusive_T[63:0]; // @[MemLoader.scala:35:49] wire [64:0] _base_addr_end_index_inclusive_T_2 = {1'h0, _base_addr_end_index_inclusive_T_1} - 65'h1; // @[MemLoader.scala:35:{49,73}] wire [63:0] _base_addr_end_index_inclusive_T_3 = _base_addr_end_index_inclusive_T_2[63:0]; // @[MemLoader.scala:35:73] wire [63:0] base_addr_end_index_inclusive = {59'h0, _base_addr_end_index_inclusive_T_3[4:0]}; // @[MemLoader.scala:35:{73,80}] wire [63:0] _extra_word_T = {59'h0, aligned_loadlen[4:0]}; // @[MemLoader.scala:33:35, :36:38] wire extra_word = |_extra_word_T; // @[MemLoader.scala:36:{38,48}] wire [63:0] _base_addr_bytes_aligned_T = {5'h0, io_src_info_bits_ip_0[63:5]}; // @[MemLoader.scala:15:7, :38:50] wire [70:0] base_addr_bytes_aligned = {2'h0, _base_addr_bytes_aligned_T, 5'h0}; // @[MemLoader.scala:38:{50,58}] wire [63:0] _words_to_load_T = {5'h0, aligned_loadlen[63:5]}; // @[MemLoader.scala:33:35, :39:40] wire [64:0] _words_to_load_T_1 = {1'h0, _words_to_load_T} + {64'h0, extra_word}; // @[MemLoader.scala:36:48, :39:{40,48}] wire [63:0] words_to_load = _words_to_load_T_1[63:0]; // @[MemLoader.scala:39:48] wire [64:0] _words_to_load_minus_one_T = {1'h0, words_to_load} - 65'h1; // @[MemLoader.scala:39:48, :40:47] wire [63:0] words_to_load_minus_one = _words_to_load_minus_one_T[63:0]; // @[MemLoader.scala:40:47] reg print_not_done; // @[MemLoader.scala:43:31] wire _T = io_src_info_valid_0 & print_not_done; // @[MemLoader.scala:15:7, :43:31, :45:27] reg [63:0] loginfo_cycles; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T = {1'h0, loginfo_cycles} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_1 = _loginfo_cycles_T[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_1; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_2 = {1'h0, loginfo_cycles_1} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_3 = _loginfo_cycles_T_2[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_2; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_4 = {1'h0, loginfo_cycles_2} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_5 = _loginfo_cycles_T_4[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_3; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_6 = {1'h0, loginfo_cycles_3} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_7 = _loginfo_cycles_T_6[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_4; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_8 = {1'h0, loginfo_cycles_4} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_9 = _loginfo_cycles_T_8[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_5; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_10 = {1'h0, loginfo_cycles_5} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_11 = _loginfo_cycles_T_10[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_6; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_12 = {1'h0, loginfo_cycles_6} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_13 = _loginfo_cycles_T_12[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_7; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_14 = {1'h0, loginfo_cycles_7} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_15 = _loginfo_cycles_T_14[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_8; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_16 = {1'h0, loginfo_cycles_8} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_17 = _loginfo_cycles_T_16[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_9; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_18 = {1'h0, loginfo_cycles_9} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_19 = _loginfo_cycles_T_18[63:0]; // @[Util.scala:19:38] reg [63:0] addrinc; // @[MemLoader.scala:74:24] wire _GEN_0 = addrinc == 64'h0; // @[MemLoader.scala:74:24, :76:57] wire _load_info_queue_io_enq_bits_start_byte_T; // @[MemLoader.scala:76:57] assign _load_info_queue_io_enq_bits_start_byte_T = _GEN_0; // @[MemLoader.scala:76:57] wire _buf_info_queue_io_enq_valid_T; // @[MemLoader.scala:95:53] assign _buf_info_queue_io_enq_valid_T = _GEN_0; // @[MemLoader.scala:76:57, :95:53] wire [63:0] _load_info_queue_io_enq_bits_start_byte_T_1 = _load_info_queue_io_enq_bits_start_byte_T ? base_addr_start_index : 64'h0; // @[MemLoader.scala:32:51, :76:{48,57}] wire _T_44 = addrinc == words_to_load_minus_one; // @[MemLoader.scala:40:47, :74:24, :77:55] wire _load_info_queue_io_enq_bits_end_byte_T; // @[MemLoader.scala:77:55] assign _load_info_queue_io_enq_bits_end_byte_T = _T_44; // @[MemLoader.scala:77:55] wire _io_src_info_ready_T; // @[MemLoader.scala:92:53] assign _io_src_info_ready_T = _T_44; // @[MemLoader.scala:77:55, :92:53] wire [63:0] _load_info_queue_io_enq_bits_end_byte_T_1 = _load_info_queue_io_enq_bits_end_byte_T ? base_addr_end_index_inclusive : 64'h1F; // @[MemLoader.scala:35:80, :77:{46,55}] wire _T_46 = io_l2helperUser_req_ready_0 & io_src_info_valid_0; // @[Misc.scala:29:18] wire _buf_info_queue_io_enq_valid_T_1; // @[Misc.scala:26:53] assign _buf_info_queue_io_enq_valid_T_1 = _T_46; // @[Misc.scala:26:53, :29:18] wire _load_info_queue_io_enq_valid_T; // @[Misc.scala:26:53] assign _load_info_queue_io_enq_valid_T = _T_46; // @[Misc.scala:26:53, :29:18] wire [64:0] _addrinc_T = {1'h0, addrinc} + 65'h1; // @[MemLoader.scala:74:24, :83:24] wire [63:0] _addrinc_T_1 = _addrinc_T[63:0]; // @[MemLoader.scala:83:24] reg [63:0] loginfo_cycles_10; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_20 = {1'h0, loginfo_cycles_10} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_21 = _loginfo_cycles_T_20[63:0]; // @[Util.scala:19:38] wire _io_src_info_ready_T_1 = io_l2helperUser_req_ready_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53] wire _io_src_info_ready_T_2 = _io_src_info_ready_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53] assign _io_src_info_ready_T_3 = _io_src_info_ready_T_2 & _io_src_info_ready_T; // @[Misc.scala:26:53] assign io_src_info_ready_0 = _io_src_info_ready_T_3; // @[Misc.scala:26:53] wire _buf_info_queue_io_enq_valid_T_2 = _buf_info_queue_io_enq_valid_T_1 & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53] wire _buf_info_queue_io_enq_valid_T_3 = _buf_info_queue_io_enq_valid_T_2 & _buf_info_queue_io_enq_valid_T; // @[Misc.scala:26:53] wire _load_info_queue_io_enq_valid_T_1 = _load_info_queue_io_enq_valid_T & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53] wire [68:0] _io_l2helperUser_req_bits_addr_T = {addrinc, 5'h0}; // @[MemLoader.scala:74:24, :100:73] wire [71:0] _io_l2helperUser_req_bits_addr_T_1 = {1'h0, base_addr_bytes_aligned} + {3'h0, _io_l2helperUser_req_bits_addr_T}; // @[MemLoader.scala:38:58, :100:{62,73}] assign _io_l2helperUser_req_bits_addr_T_2 = _io_l2helperUser_req_bits_addr_T_1[70:0]; // @[MemLoader.scala:100:62] assign io_l2helperUser_req_bits_addr_0 = _io_l2helperUser_req_bits_addr_T_2; // @[MemLoader.scala:15:7, :100:62] wire _io_l2helperUser_req_valid_T = io_src_info_valid_0 & _buf_info_queue_io_enq_ready; // @[Misc.scala:26:53] assign _io_l2helperUser_req_valid_T_1 = _io_l2helperUser_req_valid_T & _load_info_queue_io_enq_ready; // @[Misc.scala:26:53] assign io_l2helperUser_req_valid_0 = _io_l2helperUser_req_valid_T_1; // @[Misc.scala:26:53] reg [5:0] write_start_index; // @[MemLoader.scala:105:34] wire [7:0] align_shamt = {_load_info_queue_io_deq_bits_start_byte, 3'h0}; // @[MemLoader.scala:28:31, :108:61] wire [255:0] memresp_bits_shifted = io_l2helperUser_resp_bits_data_0 >> align_shamt; // @[MemLoader.scala:15:7, :108:61, :109:61] wire [6:0] _idx_T = {1'h0, write_start_index}; // @[MemLoader.scala:105:34, :116:34] wire [6:0] _GEN_1 = _idx_T % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx = _GEN_1[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_1 = _idx_T + 7'h1; // @[MemLoader.scala:116:34] wire [6:0] _GEN_2 = _idx_T_1 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_1 = _GEN_2[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_2 = _idx_T + 7'h2; // @[MemLoader.scala:116:34] wire [6:0] _GEN_3 = _idx_T_2 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_2 = _GEN_3[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_3 = _idx_T + 7'h3; // @[MemLoader.scala:116:34] wire [6:0] _GEN_4 = _idx_T_3 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_3 = _GEN_4[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_4 = _idx_T + 7'h4; // @[MemLoader.scala:116:34] wire [6:0] _GEN_5 = _idx_T_4 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_4 = _GEN_5[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_5 = _idx_T + 7'h5; // @[MemLoader.scala:116:34] wire [6:0] _GEN_6 = _idx_T_5 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_5 = _GEN_6[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_6 = _idx_T + 7'h6; // @[MemLoader.scala:116:34] wire [6:0] _GEN_7 = _idx_T_6 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_6 = _GEN_7[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_7 = _idx_T + 7'h7; // @[MemLoader.scala:116:34] wire [6:0] _GEN_8 = _idx_T_7 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_7 = _GEN_8[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_8 = _idx_T + 7'h8; // @[MemLoader.scala:116:34] wire [6:0] _GEN_9 = _idx_T_8 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_8 = _GEN_9[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_9 = _idx_T + 7'h9; // @[MemLoader.scala:116:34] wire [6:0] _GEN_10 = _idx_T_9 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_9 = _GEN_10[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_10 = _idx_T + 7'hA; // @[MemLoader.scala:116:34] wire [6:0] _GEN_11 = _idx_T_10 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_10 = _GEN_11[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_11 = _idx_T + 7'hB; // @[MemLoader.scala:116:34] wire [6:0] _GEN_12 = _idx_T_11 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_11 = _GEN_12[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_12 = _idx_T + 7'hC; // @[MemLoader.scala:116:34] wire [6:0] _GEN_13 = _idx_T_12 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_12 = _GEN_13[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_13 = _idx_T + 7'hD; // @[MemLoader.scala:116:34] wire [6:0] _GEN_14 = _idx_T_13 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_13 = _GEN_14[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_14 = _idx_T + 7'hE; // @[MemLoader.scala:116:34] wire [6:0] _GEN_15 = _idx_T_14 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_14 = _GEN_15[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_15 = _idx_T + 7'hF; // @[MemLoader.scala:116:34] wire [6:0] _GEN_16 = _idx_T_15 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_15 = _GEN_16[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_16 = _idx_T + 7'h10; // @[MemLoader.scala:116:34] wire [6:0] _GEN_17 = _idx_T_16 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_16 = _GEN_17[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_17 = _idx_T + 7'h11; // @[MemLoader.scala:116:34] wire [6:0] _GEN_18 = _idx_T_17 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_17 = _GEN_18[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_18 = _idx_T + 7'h12; // @[MemLoader.scala:116:34] wire [6:0] _GEN_19 = _idx_T_18 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_18 = _GEN_19[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_19 = _idx_T + 7'h13; // @[MemLoader.scala:116:34] wire [6:0] _GEN_20 = _idx_T_19 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_19 = _GEN_20[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_20 = _idx_T + 7'h14; // @[MemLoader.scala:116:34] wire [6:0] _GEN_21 = _idx_T_20 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_20 = _GEN_21[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_21 = _idx_T + 7'h15; // @[MemLoader.scala:116:34] wire [6:0] _GEN_22 = _idx_T_21 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_21 = _GEN_22[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_22 = _idx_T + 7'h16; // @[MemLoader.scala:116:34] wire [6:0] _GEN_23 = _idx_T_22 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_22 = _GEN_23[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_23 = _idx_T + 7'h17; // @[MemLoader.scala:116:34] wire [6:0] _GEN_24 = _idx_T_23 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_23 = _GEN_24[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_24 = _idx_T + 7'h18; // @[MemLoader.scala:116:34] wire [6:0] _GEN_25 = _idx_T_24 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_24 = _GEN_25[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_25 = _idx_T + 7'h19; // @[MemLoader.scala:116:34] wire [6:0] _GEN_26 = _idx_T_25 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_25 = _GEN_26[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_26 = _idx_T + 7'h1A; // @[MemLoader.scala:116:34] wire [6:0] _GEN_27 = _idx_T_26 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_26 = _GEN_27[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_27 = _idx_T + 7'h1B; // @[MemLoader.scala:116:34] wire [6:0] _GEN_28 = _idx_T_27 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_27 = _GEN_28[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_28 = _idx_T + 7'h1C; // @[MemLoader.scala:116:34] wire [6:0] _GEN_29 = _idx_T_28 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_28 = _GEN_29[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_29 = _idx_T + 7'h1D; // @[MemLoader.scala:116:34] wire [6:0] _GEN_30 = _idx_T_29 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_29 = _GEN_30[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_30 = _idx_T + 7'h1E; // @[MemLoader.scala:116:34] wire [6:0] _GEN_31 = _idx_T_30 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_30 = _GEN_31[5:0]; // @[MemLoader.scala:116:48] wire [6:0] _idx_T_31 = _idx_T + 7'h1F; // @[MemLoader.scala:116:34] wire [6:0] _GEN_32 = _idx_T_31 % 7'h20; // @[MemLoader.scala:116:{34,48}] wire [5:0] idx_31 = _GEN_32[5:0]; // @[MemLoader.scala:116:48] wire [5:0] _len_to_write_T = {1'h0, _load_info_queue_io_deq_bits_end_byte} - {1'h0, _load_info_queue_io_deq_bits_start_byte}; // @[MemLoader.scala:28:31, :124:60] wire [4:0] _len_to_write_T_1 = _len_to_write_T[4:0]; // @[MemLoader.scala:124:60] wire [5:0] len_to_write = {1'h0, _len_to_write_T_1} + 6'h1; // @[MemLoader.scala:124:{60,102}] wire [6:0] wrap_len_index_wide = _idx_T + {1'h0, len_to_write}; // @[MemLoader.scala:116:34, :124:102, :126:47] wire [6:0] _GEN_33 = wrap_len_index_wide % 7'h20; // @[MemLoader.scala:126:47, :127:48] wire [5:0] wrap_len_index_end = _GEN_33[5:0]; // @[MemLoader.scala:127:48] wire wrapped = |(wrap_len_index_wide[6:5]); // @[MemLoader.scala:126:47, :128:37] reg [63:0] loginfo_cycles_11; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_22 = {1'h0, loginfo_cycles_11} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_23 = _loginfo_cycles_T_22[63:0]; // @[Util.scala:19:38] wire _all_queues_ready_T = _Queue64_UInt8_io_enq_ready & _Queue64_UInt8_1_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_1 = _all_queues_ready_T & _Queue64_UInt8_2_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_2 = _all_queues_ready_T_1 & _Queue64_UInt8_3_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_3 = _all_queues_ready_T_2 & _Queue64_UInt8_4_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_4 = _all_queues_ready_T_3 & _Queue64_UInt8_5_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_5 = _all_queues_ready_T_4 & _Queue64_UInt8_6_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_6 = _all_queues_ready_T_5 & _Queue64_UInt8_7_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_7 = _all_queues_ready_T_6 & _Queue64_UInt8_8_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_8 = _all_queues_ready_T_7 & _Queue64_UInt8_9_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_9 = _all_queues_ready_T_8 & _Queue64_UInt8_10_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_10 = _all_queues_ready_T_9 & _Queue64_UInt8_11_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_11 = _all_queues_ready_T_10 & _Queue64_UInt8_12_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_12 = _all_queues_ready_T_11 & _Queue64_UInt8_13_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_13 = _all_queues_ready_T_12 & _Queue64_UInt8_14_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_14 = _all_queues_ready_T_13 & _Queue64_UInt8_15_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_15 = _all_queues_ready_T_14 & _Queue64_UInt8_16_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_16 = _all_queues_ready_T_15 & _Queue64_UInt8_17_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_17 = _all_queues_ready_T_16 & _Queue64_UInt8_18_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_18 = _all_queues_ready_T_17 & _Queue64_UInt8_19_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_19 = _all_queues_ready_T_18 & _Queue64_UInt8_20_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_20 = _all_queues_ready_T_19 & _Queue64_UInt8_21_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_21 = _all_queues_ready_T_20 & _Queue64_UInt8_22_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_22 = _all_queues_ready_T_21 & _Queue64_UInt8_23_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_23 = _all_queues_ready_T_22 & _Queue64_UInt8_24_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_24 = _all_queues_ready_T_23 & _Queue64_UInt8_25_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_25 = _all_queues_ready_T_24 & _Queue64_UInt8_26_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_26 = _all_queues_ready_T_25 & _Queue64_UInt8_27_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_27 = _all_queues_ready_T_26 & _Queue64_UInt8_28_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_28 = _all_queues_ready_T_27 & _Queue64_UInt8_29_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _all_queues_ready_T_29 = _all_queues_ready_T_28 & _Queue64_UInt8_30_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire all_queues_ready = _all_queues_ready_T_29 & _Queue64_UInt8_31_io_enq_ready; // @[MemLoader.scala:106:52, :139:68] wire _load_info_queue_io_deq_ready_T = io_l2helperUser_resp_valid_0 & all_queues_ready; // @[Misc.scala:26:53] assign _io_l2helperUser_resp_ready_T = _load_info_queue_io_deq_valid & all_queues_ready; // @[Misc.scala:26:53] assign io_l2helperUser_resp_ready_0 = _io_l2helperUser_resp_ready_T; // @[Misc.scala:26:53] wire _resp_fire_allqueues_T = io_l2helperUser_resp_valid_0 & _load_info_queue_io_deq_valid; // @[Misc.scala:29:18] wire resp_fire_allqueues = _resp_fire_allqueues_T & all_queues_ready; // @[Misc.scala:29:18] wire _GEN_34 = write_start_index == 6'h0; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T; // @[MemLoader.scala:151:41] assign _use_this_queue_T = _GEN_34; // @[MemLoader.scala:151:41] wire _use_this_queue_T_3; // @[MemLoader.scala:152:41] assign _use_this_queue_T_3 = _GEN_34; // @[MemLoader.scala:151:41, :152:41] wire _use_this_queue_T_1 = |wrap_len_index_end; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_2 = _use_this_queue_T | _use_this_queue_T_1; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_4 = |wrap_len_index_end; // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_5 = _use_this_queue_T_3 & _use_this_queue_T_4; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue = wrapped ? _use_this_queue_T_2 : _use_this_queue_T_5; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_35 = write_start_index < 6'h2; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_6; // @[MemLoader.scala:151:41] assign _use_this_queue_T_6 = _GEN_35; // @[MemLoader.scala:151:41] wire _use_this_queue_T_9; // @[MemLoader.scala:152:41] assign _use_this_queue_T_9 = _GEN_35; // @[MemLoader.scala:151:41, :152:41] wire _use_this_queue_T_7 = |(wrap_len_index_end[5:1]); // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_8 = _use_this_queue_T_6 | _use_this_queue_T_7; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_10 = |(wrap_len_index_end[5:1]); // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_11 = _use_this_queue_T_9 & _use_this_queue_T_10; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_1 = wrapped ? _use_this_queue_T_8 : _use_this_queue_T_11; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_36 = write_start_index < 6'h3; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_12; // @[MemLoader.scala:151:41] assign _use_this_queue_T_12 = _GEN_36; // @[MemLoader.scala:151:41] wire _use_this_queue_T_15; // @[MemLoader.scala:152:41] assign _use_this_queue_T_15 = _GEN_36; // @[MemLoader.scala:151:41, :152:41] wire _GEN_37 = wrap_len_index_end > 6'h2; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_13; // @[MemLoader.scala:151:77] assign _use_this_queue_T_13 = _GEN_37; // @[MemLoader.scala:151:77] wire _use_this_queue_T_16; // @[MemLoader.scala:152:77] assign _use_this_queue_T_16 = _GEN_37; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_14 = _use_this_queue_T_12 | _use_this_queue_T_13; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_17 = _use_this_queue_T_15 & _use_this_queue_T_16; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_2 = wrapped ? _use_this_queue_T_14 : _use_this_queue_T_17; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_38 = write_start_index < 6'h4; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_18; // @[MemLoader.scala:151:41] assign _use_this_queue_T_18 = _GEN_38; // @[MemLoader.scala:151:41] wire _use_this_queue_T_21; // @[MemLoader.scala:152:41] assign _use_this_queue_T_21 = _GEN_38; // @[MemLoader.scala:151:41, :152:41] wire _use_this_queue_T_19 = |(wrap_len_index_end[5:2]); // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_20 = _use_this_queue_T_18 | _use_this_queue_T_19; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_22 = |(wrap_len_index_end[5:2]); // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_23 = _use_this_queue_T_21 & _use_this_queue_T_22; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_3 = wrapped ? _use_this_queue_T_20 : _use_this_queue_T_23; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_39 = write_start_index < 6'h5; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_24; // @[MemLoader.scala:151:41] assign _use_this_queue_T_24 = _GEN_39; // @[MemLoader.scala:151:41] wire _use_this_queue_T_27; // @[MemLoader.scala:152:41] assign _use_this_queue_T_27 = _GEN_39; // @[MemLoader.scala:151:41, :152:41] wire _GEN_40 = wrap_len_index_end > 6'h4; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_25; // @[MemLoader.scala:151:77] assign _use_this_queue_T_25 = _GEN_40; // @[MemLoader.scala:151:77] wire _use_this_queue_T_28; // @[MemLoader.scala:152:77] assign _use_this_queue_T_28 = _GEN_40; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_26 = _use_this_queue_T_24 | _use_this_queue_T_25; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_29 = _use_this_queue_T_27 & _use_this_queue_T_28; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_4 = wrapped ? _use_this_queue_T_26 : _use_this_queue_T_29; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_41 = write_start_index < 6'h6; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_30; // @[MemLoader.scala:151:41] assign _use_this_queue_T_30 = _GEN_41; // @[MemLoader.scala:151:41] wire _use_this_queue_T_33; // @[MemLoader.scala:152:41] assign _use_this_queue_T_33 = _GEN_41; // @[MemLoader.scala:151:41, :152:41] wire _GEN_42 = wrap_len_index_end > 6'h5; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_31; // @[MemLoader.scala:151:77] assign _use_this_queue_T_31 = _GEN_42; // @[MemLoader.scala:151:77] wire _use_this_queue_T_34; // @[MemLoader.scala:152:77] assign _use_this_queue_T_34 = _GEN_42; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_32 = _use_this_queue_T_30 | _use_this_queue_T_31; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_35 = _use_this_queue_T_33 & _use_this_queue_T_34; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_5 = wrapped ? _use_this_queue_T_32 : _use_this_queue_T_35; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_43 = write_start_index < 6'h7; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_36; // @[MemLoader.scala:151:41] assign _use_this_queue_T_36 = _GEN_43; // @[MemLoader.scala:151:41] wire _use_this_queue_T_39; // @[MemLoader.scala:152:41] assign _use_this_queue_T_39 = _GEN_43; // @[MemLoader.scala:151:41, :152:41] wire _GEN_44 = wrap_len_index_end > 6'h6; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_37; // @[MemLoader.scala:151:77] assign _use_this_queue_T_37 = _GEN_44; // @[MemLoader.scala:151:77] wire _use_this_queue_T_40; // @[MemLoader.scala:152:77] assign _use_this_queue_T_40 = _GEN_44; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_38 = _use_this_queue_T_36 | _use_this_queue_T_37; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_41 = _use_this_queue_T_39 & _use_this_queue_T_40; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_6 = wrapped ? _use_this_queue_T_38 : _use_this_queue_T_41; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_45 = write_start_index < 6'h8; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_42; // @[MemLoader.scala:151:41] assign _use_this_queue_T_42 = _GEN_45; // @[MemLoader.scala:151:41] wire _use_this_queue_T_45; // @[MemLoader.scala:152:41] assign _use_this_queue_T_45 = _GEN_45; // @[MemLoader.scala:151:41, :152:41] wire _use_this_queue_T_43 = |(wrap_len_index_end[5:3]); // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_44 = _use_this_queue_T_42 | _use_this_queue_T_43; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_46 = |(wrap_len_index_end[5:3]); // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_47 = _use_this_queue_T_45 & _use_this_queue_T_46; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_7 = wrapped ? _use_this_queue_T_44 : _use_this_queue_T_47; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_46 = write_start_index < 6'h9; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_48; // @[MemLoader.scala:151:41] assign _use_this_queue_T_48 = _GEN_46; // @[MemLoader.scala:151:41] wire _use_this_queue_T_51; // @[MemLoader.scala:152:41] assign _use_this_queue_T_51 = _GEN_46; // @[MemLoader.scala:151:41, :152:41] wire _GEN_47 = wrap_len_index_end > 6'h8; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_49; // @[MemLoader.scala:151:77] assign _use_this_queue_T_49 = _GEN_47; // @[MemLoader.scala:151:77] wire _use_this_queue_T_52; // @[MemLoader.scala:152:77] assign _use_this_queue_T_52 = _GEN_47; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_50 = _use_this_queue_T_48 | _use_this_queue_T_49; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_53 = _use_this_queue_T_51 & _use_this_queue_T_52; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_8 = wrapped ? _use_this_queue_T_50 : _use_this_queue_T_53; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_48 = write_start_index < 6'hA; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_54; // @[MemLoader.scala:151:41] assign _use_this_queue_T_54 = _GEN_48; // @[MemLoader.scala:151:41] wire _use_this_queue_T_57; // @[MemLoader.scala:152:41] assign _use_this_queue_T_57 = _GEN_48; // @[MemLoader.scala:151:41, :152:41] wire _GEN_49 = wrap_len_index_end > 6'h9; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_55; // @[MemLoader.scala:151:77] assign _use_this_queue_T_55 = _GEN_49; // @[MemLoader.scala:151:77] wire _use_this_queue_T_58; // @[MemLoader.scala:152:77] assign _use_this_queue_T_58 = _GEN_49; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_56 = _use_this_queue_T_54 | _use_this_queue_T_55; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_59 = _use_this_queue_T_57 & _use_this_queue_T_58; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_9 = wrapped ? _use_this_queue_T_56 : _use_this_queue_T_59; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_50 = write_start_index < 6'hB; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_60; // @[MemLoader.scala:151:41] assign _use_this_queue_T_60 = _GEN_50; // @[MemLoader.scala:151:41] wire _use_this_queue_T_63; // @[MemLoader.scala:152:41] assign _use_this_queue_T_63 = _GEN_50; // @[MemLoader.scala:151:41, :152:41] wire _GEN_51 = wrap_len_index_end > 6'hA; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_61; // @[MemLoader.scala:151:77] assign _use_this_queue_T_61 = _GEN_51; // @[MemLoader.scala:151:77] wire _use_this_queue_T_64; // @[MemLoader.scala:152:77] assign _use_this_queue_T_64 = _GEN_51; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_62 = _use_this_queue_T_60 | _use_this_queue_T_61; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_65 = _use_this_queue_T_63 & _use_this_queue_T_64; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_10 = wrapped ? _use_this_queue_T_62 : _use_this_queue_T_65; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_52 = write_start_index < 6'hC; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_66; // @[MemLoader.scala:151:41] assign _use_this_queue_T_66 = _GEN_52; // @[MemLoader.scala:151:41] wire _use_this_queue_T_69; // @[MemLoader.scala:152:41] assign _use_this_queue_T_69 = _GEN_52; // @[MemLoader.scala:151:41, :152:41] wire _GEN_53 = wrap_len_index_end > 6'hB; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_67; // @[MemLoader.scala:151:77] assign _use_this_queue_T_67 = _GEN_53; // @[MemLoader.scala:151:77] wire _use_this_queue_T_70; // @[MemLoader.scala:152:77] assign _use_this_queue_T_70 = _GEN_53; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_68 = _use_this_queue_T_66 | _use_this_queue_T_67; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_71 = _use_this_queue_T_69 & _use_this_queue_T_70; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_11 = wrapped ? _use_this_queue_T_68 : _use_this_queue_T_71; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_54 = write_start_index < 6'hD; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_72; // @[MemLoader.scala:151:41] assign _use_this_queue_T_72 = _GEN_54; // @[MemLoader.scala:151:41] wire _use_this_queue_T_75; // @[MemLoader.scala:152:41] assign _use_this_queue_T_75 = _GEN_54; // @[MemLoader.scala:151:41, :152:41] wire _GEN_55 = wrap_len_index_end > 6'hC; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_73; // @[MemLoader.scala:151:77] assign _use_this_queue_T_73 = _GEN_55; // @[MemLoader.scala:151:77] wire _use_this_queue_T_76; // @[MemLoader.scala:152:77] assign _use_this_queue_T_76 = _GEN_55; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_74 = _use_this_queue_T_72 | _use_this_queue_T_73; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_77 = _use_this_queue_T_75 & _use_this_queue_T_76; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_12 = wrapped ? _use_this_queue_T_74 : _use_this_queue_T_77; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_56 = write_start_index < 6'hE; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_78; // @[MemLoader.scala:151:41] assign _use_this_queue_T_78 = _GEN_56; // @[MemLoader.scala:151:41] wire _use_this_queue_T_81; // @[MemLoader.scala:152:41] assign _use_this_queue_T_81 = _GEN_56; // @[MemLoader.scala:151:41, :152:41] wire _GEN_57 = wrap_len_index_end > 6'hD; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_79; // @[MemLoader.scala:151:77] assign _use_this_queue_T_79 = _GEN_57; // @[MemLoader.scala:151:77] wire _use_this_queue_T_82; // @[MemLoader.scala:152:77] assign _use_this_queue_T_82 = _GEN_57; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_80 = _use_this_queue_T_78 | _use_this_queue_T_79; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_83 = _use_this_queue_T_81 & _use_this_queue_T_82; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_13 = wrapped ? _use_this_queue_T_80 : _use_this_queue_T_83; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_58 = write_start_index < 6'hF; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_84; // @[MemLoader.scala:151:41] assign _use_this_queue_T_84 = _GEN_58; // @[MemLoader.scala:151:41] wire _use_this_queue_T_87; // @[MemLoader.scala:152:41] assign _use_this_queue_T_87 = _GEN_58; // @[MemLoader.scala:151:41, :152:41] wire _GEN_59 = wrap_len_index_end > 6'hE; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_85; // @[MemLoader.scala:151:77] assign _use_this_queue_T_85 = _GEN_59; // @[MemLoader.scala:151:77] wire _use_this_queue_T_88; // @[MemLoader.scala:152:77] assign _use_this_queue_T_88 = _GEN_59; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_86 = _use_this_queue_T_84 | _use_this_queue_T_85; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_89 = _use_this_queue_T_87 & _use_this_queue_T_88; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_14 = wrapped ? _use_this_queue_T_86 : _use_this_queue_T_89; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_60 = write_start_index < 6'h10; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_90; // @[MemLoader.scala:151:41] assign _use_this_queue_T_90 = _GEN_60; // @[MemLoader.scala:151:41] wire _use_this_queue_T_93; // @[MemLoader.scala:152:41] assign _use_this_queue_T_93 = _GEN_60; // @[MemLoader.scala:151:41, :152:41] wire _use_this_queue_T_91 = |(wrap_len_index_end[5:4]); // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_92 = _use_this_queue_T_90 | _use_this_queue_T_91; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_94 = |(wrap_len_index_end[5:4]); // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_95 = _use_this_queue_T_93 & _use_this_queue_T_94; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_15 = wrapped ? _use_this_queue_T_92 : _use_this_queue_T_95; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_61 = write_start_index < 6'h11; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_96; // @[MemLoader.scala:151:41] assign _use_this_queue_T_96 = _GEN_61; // @[MemLoader.scala:151:41] wire _use_this_queue_T_99; // @[MemLoader.scala:152:41] assign _use_this_queue_T_99 = _GEN_61; // @[MemLoader.scala:151:41, :152:41] wire _GEN_62 = wrap_len_index_end > 6'h10; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_97; // @[MemLoader.scala:151:77] assign _use_this_queue_T_97 = _GEN_62; // @[MemLoader.scala:151:77] wire _use_this_queue_T_100; // @[MemLoader.scala:152:77] assign _use_this_queue_T_100 = _GEN_62; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_98 = _use_this_queue_T_96 | _use_this_queue_T_97; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_101 = _use_this_queue_T_99 & _use_this_queue_T_100; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_16 = wrapped ? _use_this_queue_T_98 : _use_this_queue_T_101; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_63 = write_start_index < 6'h12; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_102; // @[MemLoader.scala:151:41] assign _use_this_queue_T_102 = _GEN_63; // @[MemLoader.scala:151:41] wire _use_this_queue_T_105; // @[MemLoader.scala:152:41] assign _use_this_queue_T_105 = _GEN_63; // @[MemLoader.scala:151:41, :152:41] wire _GEN_64 = wrap_len_index_end > 6'h11; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_103; // @[MemLoader.scala:151:77] assign _use_this_queue_T_103 = _GEN_64; // @[MemLoader.scala:151:77] wire _use_this_queue_T_106; // @[MemLoader.scala:152:77] assign _use_this_queue_T_106 = _GEN_64; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_104 = _use_this_queue_T_102 | _use_this_queue_T_103; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_107 = _use_this_queue_T_105 & _use_this_queue_T_106; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_17 = wrapped ? _use_this_queue_T_104 : _use_this_queue_T_107; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_65 = write_start_index < 6'h13; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_108; // @[MemLoader.scala:151:41] assign _use_this_queue_T_108 = _GEN_65; // @[MemLoader.scala:151:41] wire _use_this_queue_T_111; // @[MemLoader.scala:152:41] assign _use_this_queue_T_111 = _GEN_65; // @[MemLoader.scala:151:41, :152:41] wire _GEN_66 = wrap_len_index_end > 6'h12; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_109; // @[MemLoader.scala:151:77] assign _use_this_queue_T_109 = _GEN_66; // @[MemLoader.scala:151:77] wire _use_this_queue_T_112; // @[MemLoader.scala:152:77] assign _use_this_queue_T_112 = _GEN_66; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_110 = _use_this_queue_T_108 | _use_this_queue_T_109; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_113 = _use_this_queue_T_111 & _use_this_queue_T_112; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_18 = wrapped ? _use_this_queue_T_110 : _use_this_queue_T_113; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_67 = write_start_index < 6'h14; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_114; // @[MemLoader.scala:151:41] assign _use_this_queue_T_114 = _GEN_67; // @[MemLoader.scala:151:41] wire _use_this_queue_T_117; // @[MemLoader.scala:152:41] assign _use_this_queue_T_117 = _GEN_67; // @[MemLoader.scala:151:41, :152:41] wire _GEN_68 = wrap_len_index_end > 6'h13; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_115; // @[MemLoader.scala:151:77] assign _use_this_queue_T_115 = _GEN_68; // @[MemLoader.scala:151:77] wire _use_this_queue_T_118; // @[MemLoader.scala:152:77] assign _use_this_queue_T_118 = _GEN_68; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_116 = _use_this_queue_T_114 | _use_this_queue_T_115; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_119 = _use_this_queue_T_117 & _use_this_queue_T_118; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_19 = wrapped ? _use_this_queue_T_116 : _use_this_queue_T_119; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_69 = write_start_index < 6'h15; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_120; // @[MemLoader.scala:151:41] assign _use_this_queue_T_120 = _GEN_69; // @[MemLoader.scala:151:41] wire _use_this_queue_T_123; // @[MemLoader.scala:152:41] assign _use_this_queue_T_123 = _GEN_69; // @[MemLoader.scala:151:41, :152:41] wire _GEN_70 = wrap_len_index_end > 6'h14; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_121; // @[MemLoader.scala:151:77] assign _use_this_queue_T_121 = _GEN_70; // @[MemLoader.scala:151:77] wire _use_this_queue_T_124; // @[MemLoader.scala:152:77] assign _use_this_queue_T_124 = _GEN_70; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_122 = _use_this_queue_T_120 | _use_this_queue_T_121; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_125 = _use_this_queue_T_123 & _use_this_queue_T_124; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_20 = wrapped ? _use_this_queue_T_122 : _use_this_queue_T_125; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_71 = write_start_index < 6'h16; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_126; // @[MemLoader.scala:151:41] assign _use_this_queue_T_126 = _GEN_71; // @[MemLoader.scala:151:41] wire _use_this_queue_T_129; // @[MemLoader.scala:152:41] assign _use_this_queue_T_129 = _GEN_71; // @[MemLoader.scala:151:41, :152:41] wire _GEN_72 = wrap_len_index_end > 6'h15; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_127; // @[MemLoader.scala:151:77] assign _use_this_queue_T_127 = _GEN_72; // @[MemLoader.scala:151:77] wire _use_this_queue_T_130; // @[MemLoader.scala:152:77] assign _use_this_queue_T_130 = _GEN_72; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_128 = _use_this_queue_T_126 | _use_this_queue_T_127; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_131 = _use_this_queue_T_129 & _use_this_queue_T_130; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_21 = wrapped ? _use_this_queue_T_128 : _use_this_queue_T_131; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_73 = write_start_index < 6'h17; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_132; // @[MemLoader.scala:151:41] assign _use_this_queue_T_132 = _GEN_73; // @[MemLoader.scala:151:41] wire _use_this_queue_T_135; // @[MemLoader.scala:152:41] assign _use_this_queue_T_135 = _GEN_73; // @[MemLoader.scala:151:41, :152:41] wire _GEN_74 = wrap_len_index_end > 6'h16; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_133; // @[MemLoader.scala:151:77] assign _use_this_queue_T_133 = _GEN_74; // @[MemLoader.scala:151:77] wire _use_this_queue_T_136; // @[MemLoader.scala:152:77] assign _use_this_queue_T_136 = _GEN_74; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_134 = _use_this_queue_T_132 | _use_this_queue_T_133; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_137 = _use_this_queue_T_135 & _use_this_queue_T_136; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_22 = wrapped ? _use_this_queue_T_134 : _use_this_queue_T_137; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_75 = write_start_index < 6'h18; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_138; // @[MemLoader.scala:151:41] assign _use_this_queue_T_138 = _GEN_75; // @[MemLoader.scala:151:41] wire _use_this_queue_T_141; // @[MemLoader.scala:152:41] assign _use_this_queue_T_141 = _GEN_75; // @[MemLoader.scala:151:41, :152:41] wire _GEN_76 = wrap_len_index_end > 6'h17; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_139; // @[MemLoader.scala:151:77] assign _use_this_queue_T_139 = _GEN_76; // @[MemLoader.scala:151:77] wire _use_this_queue_T_142; // @[MemLoader.scala:152:77] assign _use_this_queue_T_142 = _GEN_76; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_140 = _use_this_queue_T_138 | _use_this_queue_T_139; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_143 = _use_this_queue_T_141 & _use_this_queue_T_142; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_23 = wrapped ? _use_this_queue_T_140 : _use_this_queue_T_143; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_77 = write_start_index < 6'h19; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_144; // @[MemLoader.scala:151:41] assign _use_this_queue_T_144 = _GEN_77; // @[MemLoader.scala:151:41] wire _use_this_queue_T_147; // @[MemLoader.scala:152:41] assign _use_this_queue_T_147 = _GEN_77; // @[MemLoader.scala:151:41, :152:41] wire _GEN_78 = wrap_len_index_end > 6'h18; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_145; // @[MemLoader.scala:151:77] assign _use_this_queue_T_145 = _GEN_78; // @[MemLoader.scala:151:77] wire _use_this_queue_T_148; // @[MemLoader.scala:152:77] assign _use_this_queue_T_148 = _GEN_78; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_146 = _use_this_queue_T_144 | _use_this_queue_T_145; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_149 = _use_this_queue_T_147 & _use_this_queue_T_148; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_24 = wrapped ? _use_this_queue_T_146 : _use_this_queue_T_149; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_79 = write_start_index < 6'h1A; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_150; // @[MemLoader.scala:151:41] assign _use_this_queue_T_150 = _GEN_79; // @[MemLoader.scala:151:41] wire _use_this_queue_T_153; // @[MemLoader.scala:152:41] assign _use_this_queue_T_153 = _GEN_79; // @[MemLoader.scala:151:41, :152:41] wire _GEN_80 = wrap_len_index_end > 6'h19; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_151; // @[MemLoader.scala:151:77] assign _use_this_queue_T_151 = _GEN_80; // @[MemLoader.scala:151:77] wire _use_this_queue_T_154; // @[MemLoader.scala:152:77] assign _use_this_queue_T_154 = _GEN_80; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_152 = _use_this_queue_T_150 | _use_this_queue_T_151; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_155 = _use_this_queue_T_153 & _use_this_queue_T_154; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_25 = wrapped ? _use_this_queue_T_152 : _use_this_queue_T_155; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_81 = write_start_index < 6'h1B; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_156; // @[MemLoader.scala:151:41] assign _use_this_queue_T_156 = _GEN_81; // @[MemLoader.scala:151:41] wire _use_this_queue_T_159; // @[MemLoader.scala:152:41] assign _use_this_queue_T_159 = _GEN_81; // @[MemLoader.scala:151:41, :152:41] wire _GEN_82 = wrap_len_index_end > 6'h1A; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_157; // @[MemLoader.scala:151:77] assign _use_this_queue_T_157 = _GEN_82; // @[MemLoader.scala:151:77] wire _use_this_queue_T_160; // @[MemLoader.scala:152:77] assign _use_this_queue_T_160 = _GEN_82; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_158 = _use_this_queue_T_156 | _use_this_queue_T_157; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_161 = _use_this_queue_T_159 & _use_this_queue_T_160; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_26 = wrapped ? _use_this_queue_T_158 : _use_this_queue_T_161; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_83 = write_start_index < 6'h1C; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_162; // @[MemLoader.scala:151:41] assign _use_this_queue_T_162 = _GEN_83; // @[MemLoader.scala:151:41] wire _use_this_queue_T_165; // @[MemLoader.scala:152:41] assign _use_this_queue_T_165 = _GEN_83; // @[MemLoader.scala:151:41, :152:41] wire _GEN_84 = wrap_len_index_end > 6'h1B; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_163; // @[MemLoader.scala:151:77] assign _use_this_queue_T_163 = _GEN_84; // @[MemLoader.scala:151:77] wire _use_this_queue_T_166; // @[MemLoader.scala:152:77] assign _use_this_queue_T_166 = _GEN_84; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_164 = _use_this_queue_T_162 | _use_this_queue_T_163; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_167 = _use_this_queue_T_165 & _use_this_queue_T_166; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_27 = wrapped ? _use_this_queue_T_164 : _use_this_queue_T_167; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_85 = write_start_index < 6'h1D; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_168; // @[MemLoader.scala:151:41] assign _use_this_queue_T_168 = _GEN_85; // @[MemLoader.scala:151:41] wire _use_this_queue_T_171; // @[MemLoader.scala:152:41] assign _use_this_queue_T_171 = _GEN_85; // @[MemLoader.scala:151:41, :152:41] wire _GEN_86 = wrap_len_index_end > 6'h1C; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_169; // @[MemLoader.scala:151:77] assign _use_this_queue_T_169 = _GEN_86; // @[MemLoader.scala:151:77] wire _use_this_queue_T_172; // @[MemLoader.scala:152:77] assign _use_this_queue_T_172 = _GEN_86; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_170 = _use_this_queue_T_168 | _use_this_queue_T_169; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_173 = _use_this_queue_T_171 & _use_this_queue_T_172; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_28 = wrapped ? _use_this_queue_T_170 : _use_this_queue_T_173; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_87 = write_start_index < 6'h1E; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_174; // @[MemLoader.scala:151:41] assign _use_this_queue_T_174 = _GEN_87; // @[MemLoader.scala:151:41] wire _use_this_queue_T_177; // @[MemLoader.scala:152:41] assign _use_this_queue_T_177 = _GEN_87; // @[MemLoader.scala:151:41, :152:41] wire _GEN_88 = wrap_len_index_end > 6'h1D; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_175; // @[MemLoader.scala:151:77] assign _use_this_queue_T_175 = _GEN_88; // @[MemLoader.scala:151:77] wire _use_this_queue_T_178; // @[MemLoader.scala:152:77] assign _use_this_queue_T_178 = _GEN_88; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_176 = _use_this_queue_T_174 | _use_this_queue_T_175; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_179 = _use_this_queue_T_177 & _use_this_queue_T_178; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_29 = wrapped ? _use_this_queue_T_176 : _use_this_queue_T_179; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _GEN_89 = write_start_index < 6'h1F; // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_180; // @[MemLoader.scala:151:41] assign _use_this_queue_T_180 = _GEN_89; // @[MemLoader.scala:151:41] wire _use_this_queue_T_183; // @[MemLoader.scala:152:41] assign _use_this_queue_T_183 = _GEN_89; // @[MemLoader.scala:151:41, :152:41] wire _GEN_90 = wrap_len_index_end > 6'h1E; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_181; // @[MemLoader.scala:151:77] assign _use_this_queue_T_181 = _GEN_90; // @[MemLoader.scala:151:77] wire _use_this_queue_T_184; // @[MemLoader.scala:152:77] assign _use_this_queue_T_184 = _GEN_90; // @[MemLoader.scala:151:77, :152:77] wire _use_this_queue_T_182 = _use_this_queue_T_180 | _use_this_queue_T_181; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_185 = _use_this_queue_T_183 & _use_this_queue_T_184; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_30 = wrapped ? _use_this_queue_T_182 : _use_this_queue_T_185; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] wire _use_this_queue_T_186 = ~(write_start_index[5]); // @[MemLoader.scala:105:34, :151:41] wire _use_this_queue_T_187 = wrap_len_index_end[5]; // @[MemLoader.scala:127:48, :151:77] wire _use_this_queue_T_190 = wrap_len_index_end[5]; // @[MemLoader.scala:127:48, :151:77, :152:77] wire _use_this_queue_T_188 = _use_this_queue_T_186 | _use_this_queue_T_187; // @[MemLoader.scala:151:{41,63,77}] wire _use_this_queue_T_189 = ~(write_start_index[5]); // @[MemLoader.scala:105:34, :151:41, :152:41] wire _use_this_queue_T_191 = _use_this_queue_T_189 & _use_this_queue_T_190; // @[MemLoader.scala:152:{41,63,77}] wire use_this_queue_31 = wrapped ? _use_this_queue_T_188 : _use_this_queue_T_191; // @[MemLoader.scala:128:37, :150:29, :151:63, :152:63] reg [63:0] loginfo_cycles_12; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_24 = {1'h0, loginfo_cycles_12} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_25 = _loginfo_cycles_T_24[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_13; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_26 = {1'h0, loginfo_cycles_13} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_27 = _loginfo_cycles_T_26[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_14; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_28 = {1'h0, loginfo_cycles_14} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_29 = _loginfo_cycles_T_28[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_15; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_30 = {1'h0, loginfo_cycles_15} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_31 = _loginfo_cycles_T_30[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_16; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_32 = {1'h0, loginfo_cycles_16} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_33 = _loginfo_cycles_T_32[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_17; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_34 = {1'h0, loginfo_cycles_17} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_35 = _loginfo_cycles_T_34[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_18; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_36 = {1'h0, loginfo_cycles_18} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_37 = _loginfo_cycles_T_36[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_19; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_38 = {1'h0, loginfo_cycles_19} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_39 = _loginfo_cycles_T_38[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_20; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_40 = {1'h0, loginfo_cycles_20} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_41 = _loginfo_cycles_T_40[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_21; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_42 = {1'h0, loginfo_cycles_21} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_43 = _loginfo_cycles_T_42[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_22; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_44 = {1'h0, loginfo_cycles_22} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_45 = _loginfo_cycles_T_44[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_23; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_46 = {1'h0, loginfo_cycles_23} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_47 = _loginfo_cycles_T_46[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_24; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_48 = {1'h0, loginfo_cycles_24} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_49 = _loginfo_cycles_T_48[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_25; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_50 = {1'h0, loginfo_cycles_25} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_51 = _loginfo_cycles_T_50[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_26; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_52 = {1'h0, loginfo_cycles_26} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_53 = _loginfo_cycles_T_52[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_27; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_54 = {1'h0, loginfo_cycles_27} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_55 = _loginfo_cycles_T_54[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_28; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_56 = {1'h0, loginfo_cycles_28} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_57 = _loginfo_cycles_T_56[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_29; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_58 = {1'h0, loginfo_cycles_29} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_59 = _loginfo_cycles_T_58[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_30; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_60 = {1'h0, loginfo_cycles_30} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_61 = _loginfo_cycles_T_60[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_31; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_62 = {1'h0, loginfo_cycles_31} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_63 = _loginfo_cycles_T_62[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_32; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_64 = {1'h0, loginfo_cycles_32} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_65 = _loginfo_cycles_T_64[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_33; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_66 = {1'h0, loginfo_cycles_33} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_67 = _loginfo_cycles_T_66[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_34; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_68 = {1'h0, loginfo_cycles_34} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_69 = _loginfo_cycles_T_68[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_35; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_70 = {1'h0, loginfo_cycles_35} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_71 = _loginfo_cycles_T_70[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_36; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_72 = {1'h0, loginfo_cycles_36} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_73 = _loginfo_cycles_T_72[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_37; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_74 = {1'h0, loginfo_cycles_37} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_75 = _loginfo_cycles_T_74[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_38; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_76 = {1'h0, loginfo_cycles_38} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_77 = _loginfo_cycles_T_76[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_39; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_78 = {1'h0, loginfo_cycles_39} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_79 = _loginfo_cycles_T_78[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_40; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_80 = {1'h0, loginfo_cycles_40} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_81 = _loginfo_cycles_T_80[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_41; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_82 = {1'h0, loginfo_cycles_41} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_83 = _loginfo_cycles_T_82[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_42; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_84 = {1'h0, loginfo_cycles_42} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_85 = _loginfo_cycles_T_84[63:0]; // @[Util.scala:19:38] reg [63:0] loginfo_cycles_43; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_86 = {1'h0, loginfo_cycles_43} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_87 = _loginfo_cycles_T_86[63:0]; // @[Util.scala:19:38] reg [5:0] read_start_index; // @[MemLoader.scala:163:33] reg [63:0] len_already_consumed; // @[MemLoader.scala:164:37] wire [7:0] remapVecData_0; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_1; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_2; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_3; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_4; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_5; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_6; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_7; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_8; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_9; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_10; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_11; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_12; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_13; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_14; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_15; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_16; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_17; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_18; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_19; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_20; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_21; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_22; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_23; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_24; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_25; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_26; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_27; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_28; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_29; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_30; // @[MemLoader.scala:166:26] wire [7:0] remapVecData_31; // @[MemLoader.scala:166:26] wire remapVecValids_0; // @[MemLoader.scala:167:28] wire remapVecValids_1; // @[MemLoader.scala:167:28] wire remapVecValids_2; // @[MemLoader.scala:167:28] wire remapVecValids_3; // @[MemLoader.scala:167:28] wire remapVecValids_4; // @[MemLoader.scala:167:28] wire remapVecValids_5; // @[MemLoader.scala:167:28] wire remapVecValids_6; // @[MemLoader.scala:167:28] wire remapVecValids_7; // @[MemLoader.scala:167:28] wire remapVecValids_8; // @[MemLoader.scala:167:28] wire remapVecValids_9; // @[MemLoader.scala:167:28] wire remapVecValids_10; // @[MemLoader.scala:167:28] wire remapVecValids_11; // @[MemLoader.scala:167:28] wire remapVecValids_12; // @[MemLoader.scala:167:28] wire remapVecValids_13; // @[MemLoader.scala:167:28] wire remapVecValids_14; // @[MemLoader.scala:167:28] wire remapVecValids_15; // @[MemLoader.scala:167:28] wire remapVecValids_16; // @[MemLoader.scala:167:28] wire remapVecValids_17; // @[MemLoader.scala:167:28] wire remapVecValids_18; // @[MemLoader.scala:167:28] wire remapVecValids_19; // @[MemLoader.scala:167:28] wire remapVecValids_20; // @[MemLoader.scala:167:28] wire remapVecValids_21; // @[MemLoader.scala:167:28] wire remapVecValids_22; // @[MemLoader.scala:167:28] wire remapVecValids_23; // @[MemLoader.scala:167:28] wire remapVecValids_24; // @[MemLoader.scala:167:28] wire remapVecValids_25; // @[MemLoader.scala:167:28] wire remapVecValids_26; // @[MemLoader.scala:167:28] wire remapVecValids_27; // @[MemLoader.scala:167:28] wire remapVecValids_28; // @[MemLoader.scala:167:28] wire remapVecValids_29; // @[MemLoader.scala:167:28] wire remapVecValids_30; // @[MemLoader.scala:167:28] wire remapVecValids_31; // @[MemLoader.scala:167:28] wire _remapVecReadys_0_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_1_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_2_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_3_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_4_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_5_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_6_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_7_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_8_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_9_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_10_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_11_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_12_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_13_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_14_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_15_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_16_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_17_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_18_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_19_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_20_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_21_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_22_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_23_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_24_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_25_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_26_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_27_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_28_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_29_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_30_T_3; // @[MemLoader.scala:217:78] wire _remapVecReadys_31_T_3; // @[MemLoader.scala:217:78] wire remapVecReadys_0; // @[MemLoader.scala:168:28] wire remapVecReadys_1; // @[MemLoader.scala:168:28] wire remapVecReadys_2; // @[MemLoader.scala:168:28] wire remapVecReadys_3; // @[MemLoader.scala:168:28] wire remapVecReadys_4; // @[MemLoader.scala:168:28] wire remapVecReadys_5; // @[MemLoader.scala:168:28] wire remapVecReadys_6; // @[MemLoader.scala:168:28] wire remapVecReadys_7; // @[MemLoader.scala:168:28] wire remapVecReadys_8; // @[MemLoader.scala:168:28] wire remapVecReadys_9; // @[MemLoader.scala:168:28] wire remapVecReadys_10; // @[MemLoader.scala:168:28] wire remapVecReadys_11; // @[MemLoader.scala:168:28] wire remapVecReadys_12; // @[MemLoader.scala:168:28] wire remapVecReadys_13; // @[MemLoader.scala:168:28] wire remapVecReadys_14; // @[MemLoader.scala:168:28] wire remapVecReadys_15; // @[MemLoader.scala:168:28] wire remapVecReadys_16; // @[MemLoader.scala:168:28] wire remapVecReadys_17; // @[MemLoader.scala:168:28] wire remapVecReadys_18; // @[MemLoader.scala:168:28] wire remapVecReadys_19; // @[MemLoader.scala:168:28] wire remapVecReadys_20; // @[MemLoader.scala:168:28] wire remapVecReadys_21; // @[MemLoader.scala:168:28] wire remapVecReadys_22; // @[MemLoader.scala:168:28] wire remapVecReadys_23; // @[MemLoader.scala:168:28] wire remapVecReadys_24; // @[MemLoader.scala:168:28] wire remapVecReadys_25; // @[MemLoader.scala:168:28] wire remapVecReadys_26; // @[MemLoader.scala:168:28] wire remapVecReadys_27; // @[MemLoader.scala:168:28] wire remapVecReadys_28; // @[MemLoader.scala:168:28] wire remapVecReadys_29; // @[MemLoader.scala:168:28] wire remapVecReadys_30; // @[MemLoader.scala:168:28] wire remapVecReadys_31; // @[MemLoader.scala:168:28] wire [6:0] _remapindex_T = {1'h0, read_start_index}; // @[MemLoader.scala:163:33, :177:33] wire [6:0] _GEN_91 = _remapindex_T % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex = _GEN_91[5:0]; // @[MemLoader.scala:177:54] wire _T_2330 = remapindex == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2331 = remapindex == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2332 = remapindex == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2333 = remapindex == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2334 = remapindex == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2335 = remapindex == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2336 = remapindex == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2337 = remapindex == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2338 = remapindex == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2339 = remapindex == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2340 = remapindex == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2341 = remapindex == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2342 = remapindex == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2343 = remapindex == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2344 = remapindex == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2345 = remapindex == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2346 = remapindex == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2347 = remapindex == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2348 = remapindex == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2349 = remapindex == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2350 = remapindex == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2351 = remapindex == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2352 = remapindex == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2353 = remapindex == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2354 = remapindex == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2355 = remapindex == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2356 = remapindex == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2357 = remapindex == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2358 = remapindex == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2359 = remapindex == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2360 = remapindex == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2361 = remapindex == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_0 = _T_2361 ? _Queue64_UInt8_31_io_deq_bits : _T_2360 ? _Queue64_UInt8_30_io_deq_bits : _T_2359 ? _Queue64_UInt8_29_io_deq_bits : _T_2358 ? _Queue64_UInt8_28_io_deq_bits : _T_2357 ? _Queue64_UInt8_27_io_deq_bits : _T_2356 ? _Queue64_UInt8_26_io_deq_bits : _T_2355 ? _Queue64_UInt8_25_io_deq_bits : _T_2354 ? _Queue64_UInt8_24_io_deq_bits : _T_2353 ? _Queue64_UInt8_23_io_deq_bits : _T_2352 ? _Queue64_UInt8_22_io_deq_bits : _T_2351 ? _Queue64_UInt8_21_io_deq_bits : _T_2350 ? _Queue64_UInt8_20_io_deq_bits : _T_2349 ? _Queue64_UInt8_19_io_deq_bits : _T_2348 ? _Queue64_UInt8_18_io_deq_bits : _T_2347 ? _Queue64_UInt8_17_io_deq_bits : _T_2346 ? _Queue64_UInt8_16_io_deq_bits : _T_2345 ? _Queue64_UInt8_15_io_deq_bits : _T_2344 ? _Queue64_UInt8_14_io_deq_bits : _T_2343 ? _Queue64_UInt8_13_io_deq_bits : _T_2342 ? _Queue64_UInt8_12_io_deq_bits : _T_2341 ? _Queue64_UInt8_11_io_deq_bits : _T_2340 ? _Queue64_UInt8_10_io_deq_bits : _T_2339 ? _Queue64_UInt8_9_io_deq_bits : _T_2338 ? _Queue64_UInt8_8_io_deq_bits : _T_2337 ? _Queue64_UInt8_7_io_deq_bits : _T_2336 ? _Queue64_UInt8_6_io_deq_bits : _T_2335 ? _Queue64_UInt8_5_io_deq_bits : _T_2334 ? _Queue64_UInt8_4_io_deq_bits : _T_2333 ? _Queue64_UInt8_3_io_deq_bits : _T_2332 ? _Queue64_UInt8_2_io_deq_bits : _T_2331 ? _Queue64_UInt8_1_io_deq_bits : _T_2330 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_0 = _T_2361 ? _Queue64_UInt8_31_io_deq_valid : _T_2360 ? _Queue64_UInt8_30_io_deq_valid : _T_2359 ? _Queue64_UInt8_29_io_deq_valid : _T_2358 ? _Queue64_UInt8_28_io_deq_valid : _T_2357 ? _Queue64_UInt8_27_io_deq_valid : _T_2356 ? _Queue64_UInt8_26_io_deq_valid : _T_2355 ? _Queue64_UInt8_25_io_deq_valid : _T_2354 ? _Queue64_UInt8_24_io_deq_valid : _T_2353 ? _Queue64_UInt8_23_io_deq_valid : _T_2352 ? _Queue64_UInt8_22_io_deq_valid : _T_2351 ? _Queue64_UInt8_21_io_deq_valid : _T_2350 ? _Queue64_UInt8_20_io_deq_valid : _T_2349 ? _Queue64_UInt8_19_io_deq_valid : _T_2348 ? _Queue64_UInt8_18_io_deq_valid : _T_2347 ? _Queue64_UInt8_17_io_deq_valid : _T_2346 ? _Queue64_UInt8_16_io_deq_valid : _T_2345 ? _Queue64_UInt8_15_io_deq_valid : _T_2344 ? _Queue64_UInt8_14_io_deq_valid : _T_2343 ? _Queue64_UInt8_13_io_deq_valid : _T_2342 ? _Queue64_UInt8_12_io_deq_valid : _T_2341 ? _Queue64_UInt8_11_io_deq_valid : _T_2340 ? _Queue64_UInt8_10_io_deq_valid : _T_2339 ? _Queue64_UInt8_9_io_deq_valid : _T_2338 ? _Queue64_UInt8_8_io_deq_valid : _T_2337 ? _Queue64_UInt8_7_io_deq_valid : _T_2336 ? _Queue64_UInt8_6_io_deq_valid : _T_2335 ? _Queue64_UInt8_5_io_deq_valid : _T_2334 ? _Queue64_UInt8_4_io_deq_valid : _T_2333 ? _Queue64_UInt8_3_io_deq_valid : _T_2332 ? _Queue64_UInt8_2_io_deq_valid : _T_2331 ? _Queue64_UInt8_1_io_deq_valid : _T_2330 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_1 = _remapindex_T + 7'h1; // @[MemLoader.scala:177:33] wire [6:0] _GEN_92 = _remapindex_T_1 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_1 = _GEN_92[5:0]; // @[MemLoader.scala:177:54] wire _T_2362 = remapindex_1 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2363 = remapindex_1 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2364 = remapindex_1 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2365 = remapindex_1 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2366 = remapindex_1 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2367 = remapindex_1 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2368 = remapindex_1 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2369 = remapindex_1 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2370 = remapindex_1 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2371 = remapindex_1 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2372 = remapindex_1 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2373 = remapindex_1 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2374 = remapindex_1 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2375 = remapindex_1 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2376 = remapindex_1 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2377 = remapindex_1 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2378 = remapindex_1 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2379 = remapindex_1 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2380 = remapindex_1 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2381 = remapindex_1 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2382 = remapindex_1 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2383 = remapindex_1 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2384 = remapindex_1 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2385 = remapindex_1 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2386 = remapindex_1 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2387 = remapindex_1 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2388 = remapindex_1 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2389 = remapindex_1 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2390 = remapindex_1 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2391 = remapindex_1 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2392 = remapindex_1 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2393 = remapindex_1 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_1 = _T_2393 ? _Queue64_UInt8_31_io_deq_bits : _T_2392 ? _Queue64_UInt8_30_io_deq_bits : _T_2391 ? _Queue64_UInt8_29_io_deq_bits : _T_2390 ? _Queue64_UInt8_28_io_deq_bits : _T_2389 ? _Queue64_UInt8_27_io_deq_bits : _T_2388 ? _Queue64_UInt8_26_io_deq_bits : _T_2387 ? _Queue64_UInt8_25_io_deq_bits : _T_2386 ? _Queue64_UInt8_24_io_deq_bits : _T_2385 ? _Queue64_UInt8_23_io_deq_bits : _T_2384 ? _Queue64_UInt8_22_io_deq_bits : _T_2383 ? _Queue64_UInt8_21_io_deq_bits : _T_2382 ? _Queue64_UInt8_20_io_deq_bits : _T_2381 ? _Queue64_UInt8_19_io_deq_bits : _T_2380 ? _Queue64_UInt8_18_io_deq_bits : _T_2379 ? _Queue64_UInt8_17_io_deq_bits : _T_2378 ? _Queue64_UInt8_16_io_deq_bits : _T_2377 ? _Queue64_UInt8_15_io_deq_bits : _T_2376 ? _Queue64_UInt8_14_io_deq_bits : _T_2375 ? _Queue64_UInt8_13_io_deq_bits : _T_2374 ? _Queue64_UInt8_12_io_deq_bits : _T_2373 ? _Queue64_UInt8_11_io_deq_bits : _T_2372 ? _Queue64_UInt8_10_io_deq_bits : _T_2371 ? _Queue64_UInt8_9_io_deq_bits : _T_2370 ? _Queue64_UInt8_8_io_deq_bits : _T_2369 ? _Queue64_UInt8_7_io_deq_bits : _T_2368 ? _Queue64_UInt8_6_io_deq_bits : _T_2367 ? _Queue64_UInt8_5_io_deq_bits : _T_2366 ? _Queue64_UInt8_4_io_deq_bits : _T_2365 ? _Queue64_UInt8_3_io_deq_bits : _T_2364 ? _Queue64_UInt8_2_io_deq_bits : _T_2363 ? _Queue64_UInt8_1_io_deq_bits : _T_2362 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_1 = _T_2393 ? _Queue64_UInt8_31_io_deq_valid : _T_2392 ? _Queue64_UInt8_30_io_deq_valid : _T_2391 ? _Queue64_UInt8_29_io_deq_valid : _T_2390 ? _Queue64_UInt8_28_io_deq_valid : _T_2389 ? _Queue64_UInt8_27_io_deq_valid : _T_2388 ? _Queue64_UInt8_26_io_deq_valid : _T_2387 ? _Queue64_UInt8_25_io_deq_valid : _T_2386 ? _Queue64_UInt8_24_io_deq_valid : _T_2385 ? _Queue64_UInt8_23_io_deq_valid : _T_2384 ? _Queue64_UInt8_22_io_deq_valid : _T_2383 ? _Queue64_UInt8_21_io_deq_valid : _T_2382 ? _Queue64_UInt8_20_io_deq_valid : _T_2381 ? _Queue64_UInt8_19_io_deq_valid : _T_2380 ? _Queue64_UInt8_18_io_deq_valid : _T_2379 ? _Queue64_UInt8_17_io_deq_valid : _T_2378 ? _Queue64_UInt8_16_io_deq_valid : _T_2377 ? _Queue64_UInt8_15_io_deq_valid : _T_2376 ? _Queue64_UInt8_14_io_deq_valid : _T_2375 ? _Queue64_UInt8_13_io_deq_valid : _T_2374 ? _Queue64_UInt8_12_io_deq_valid : _T_2373 ? _Queue64_UInt8_11_io_deq_valid : _T_2372 ? _Queue64_UInt8_10_io_deq_valid : _T_2371 ? _Queue64_UInt8_9_io_deq_valid : _T_2370 ? _Queue64_UInt8_8_io_deq_valid : _T_2369 ? _Queue64_UInt8_7_io_deq_valid : _T_2368 ? _Queue64_UInt8_6_io_deq_valid : _T_2367 ? _Queue64_UInt8_5_io_deq_valid : _T_2366 ? _Queue64_UInt8_4_io_deq_valid : _T_2365 ? _Queue64_UInt8_3_io_deq_valid : _T_2364 ? _Queue64_UInt8_2_io_deq_valid : _T_2363 ? _Queue64_UInt8_1_io_deq_valid : _T_2362 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_2 = _remapindex_T + 7'h2; // @[MemLoader.scala:177:33] wire [6:0] _GEN_93 = _remapindex_T_2 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_2 = _GEN_93[5:0]; // @[MemLoader.scala:177:54] wire _T_2394 = remapindex_2 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2395 = remapindex_2 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2396 = remapindex_2 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2397 = remapindex_2 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2398 = remapindex_2 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2399 = remapindex_2 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2400 = remapindex_2 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2401 = remapindex_2 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2402 = remapindex_2 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2403 = remapindex_2 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2404 = remapindex_2 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2405 = remapindex_2 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2406 = remapindex_2 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2407 = remapindex_2 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2408 = remapindex_2 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2409 = remapindex_2 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2410 = remapindex_2 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2411 = remapindex_2 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2412 = remapindex_2 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2413 = remapindex_2 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2414 = remapindex_2 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2415 = remapindex_2 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2416 = remapindex_2 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2417 = remapindex_2 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2418 = remapindex_2 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2419 = remapindex_2 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2420 = remapindex_2 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2421 = remapindex_2 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2422 = remapindex_2 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2423 = remapindex_2 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2424 = remapindex_2 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2425 = remapindex_2 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_2 = _T_2425 ? _Queue64_UInt8_31_io_deq_bits : _T_2424 ? _Queue64_UInt8_30_io_deq_bits : _T_2423 ? _Queue64_UInt8_29_io_deq_bits : _T_2422 ? _Queue64_UInt8_28_io_deq_bits : _T_2421 ? _Queue64_UInt8_27_io_deq_bits : _T_2420 ? _Queue64_UInt8_26_io_deq_bits : _T_2419 ? _Queue64_UInt8_25_io_deq_bits : _T_2418 ? _Queue64_UInt8_24_io_deq_bits : _T_2417 ? _Queue64_UInt8_23_io_deq_bits : _T_2416 ? _Queue64_UInt8_22_io_deq_bits : _T_2415 ? _Queue64_UInt8_21_io_deq_bits : _T_2414 ? _Queue64_UInt8_20_io_deq_bits : _T_2413 ? _Queue64_UInt8_19_io_deq_bits : _T_2412 ? _Queue64_UInt8_18_io_deq_bits : _T_2411 ? _Queue64_UInt8_17_io_deq_bits : _T_2410 ? _Queue64_UInt8_16_io_deq_bits : _T_2409 ? _Queue64_UInt8_15_io_deq_bits : _T_2408 ? _Queue64_UInt8_14_io_deq_bits : _T_2407 ? _Queue64_UInt8_13_io_deq_bits : _T_2406 ? _Queue64_UInt8_12_io_deq_bits : _T_2405 ? _Queue64_UInt8_11_io_deq_bits : _T_2404 ? _Queue64_UInt8_10_io_deq_bits : _T_2403 ? _Queue64_UInt8_9_io_deq_bits : _T_2402 ? _Queue64_UInt8_8_io_deq_bits : _T_2401 ? _Queue64_UInt8_7_io_deq_bits : _T_2400 ? _Queue64_UInt8_6_io_deq_bits : _T_2399 ? _Queue64_UInt8_5_io_deq_bits : _T_2398 ? _Queue64_UInt8_4_io_deq_bits : _T_2397 ? _Queue64_UInt8_3_io_deq_bits : _T_2396 ? _Queue64_UInt8_2_io_deq_bits : _T_2395 ? _Queue64_UInt8_1_io_deq_bits : _T_2394 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_2 = _T_2425 ? _Queue64_UInt8_31_io_deq_valid : _T_2424 ? _Queue64_UInt8_30_io_deq_valid : _T_2423 ? _Queue64_UInt8_29_io_deq_valid : _T_2422 ? _Queue64_UInt8_28_io_deq_valid : _T_2421 ? _Queue64_UInt8_27_io_deq_valid : _T_2420 ? _Queue64_UInt8_26_io_deq_valid : _T_2419 ? _Queue64_UInt8_25_io_deq_valid : _T_2418 ? _Queue64_UInt8_24_io_deq_valid : _T_2417 ? _Queue64_UInt8_23_io_deq_valid : _T_2416 ? _Queue64_UInt8_22_io_deq_valid : _T_2415 ? _Queue64_UInt8_21_io_deq_valid : _T_2414 ? _Queue64_UInt8_20_io_deq_valid : _T_2413 ? _Queue64_UInt8_19_io_deq_valid : _T_2412 ? _Queue64_UInt8_18_io_deq_valid : _T_2411 ? _Queue64_UInt8_17_io_deq_valid : _T_2410 ? _Queue64_UInt8_16_io_deq_valid : _T_2409 ? _Queue64_UInt8_15_io_deq_valid : _T_2408 ? _Queue64_UInt8_14_io_deq_valid : _T_2407 ? _Queue64_UInt8_13_io_deq_valid : _T_2406 ? _Queue64_UInt8_12_io_deq_valid : _T_2405 ? _Queue64_UInt8_11_io_deq_valid : _T_2404 ? _Queue64_UInt8_10_io_deq_valid : _T_2403 ? _Queue64_UInt8_9_io_deq_valid : _T_2402 ? _Queue64_UInt8_8_io_deq_valid : _T_2401 ? _Queue64_UInt8_7_io_deq_valid : _T_2400 ? _Queue64_UInt8_6_io_deq_valid : _T_2399 ? _Queue64_UInt8_5_io_deq_valid : _T_2398 ? _Queue64_UInt8_4_io_deq_valid : _T_2397 ? _Queue64_UInt8_3_io_deq_valid : _T_2396 ? _Queue64_UInt8_2_io_deq_valid : _T_2395 ? _Queue64_UInt8_1_io_deq_valid : _T_2394 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_3 = _remapindex_T + 7'h3; // @[MemLoader.scala:177:33] wire [6:0] _GEN_94 = _remapindex_T_3 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_3 = _GEN_94[5:0]; // @[MemLoader.scala:177:54] wire _T_2426 = remapindex_3 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2427 = remapindex_3 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2428 = remapindex_3 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2429 = remapindex_3 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2430 = remapindex_3 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2431 = remapindex_3 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2432 = remapindex_3 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2433 = remapindex_3 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2434 = remapindex_3 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2435 = remapindex_3 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2436 = remapindex_3 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2437 = remapindex_3 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2438 = remapindex_3 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2439 = remapindex_3 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2440 = remapindex_3 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2441 = remapindex_3 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2442 = remapindex_3 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2443 = remapindex_3 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2444 = remapindex_3 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2445 = remapindex_3 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2446 = remapindex_3 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2447 = remapindex_3 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2448 = remapindex_3 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2449 = remapindex_3 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2450 = remapindex_3 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2451 = remapindex_3 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2452 = remapindex_3 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2453 = remapindex_3 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2454 = remapindex_3 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2455 = remapindex_3 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2456 = remapindex_3 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2457 = remapindex_3 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_3 = _T_2457 ? _Queue64_UInt8_31_io_deq_bits : _T_2456 ? _Queue64_UInt8_30_io_deq_bits : _T_2455 ? _Queue64_UInt8_29_io_deq_bits : _T_2454 ? _Queue64_UInt8_28_io_deq_bits : _T_2453 ? _Queue64_UInt8_27_io_deq_bits : _T_2452 ? _Queue64_UInt8_26_io_deq_bits : _T_2451 ? _Queue64_UInt8_25_io_deq_bits : _T_2450 ? _Queue64_UInt8_24_io_deq_bits : _T_2449 ? _Queue64_UInt8_23_io_deq_bits : _T_2448 ? _Queue64_UInt8_22_io_deq_bits : _T_2447 ? _Queue64_UInt8_21_io_deq_bits : _T_2446 ? _Queue64_UInt8_20_io_deq_bits : _T_2445 ? _Queue64_UInt8_19_io_deq_bits : _T_2444 ? _Queue64_UInt8_18_io_deq_bits : _T_2443 ? _Queue64_UInt8_17_io_deq_bits : _T_2442 ? _Queue64_UInt8_16_io_deq_bits : _T_2441 ? _Queue64_UInt8_15_io_deq_bits : _T_2440 ? _Queue64_UInt8_14_io_deq_bits : _T_2439 ? _Queue64_UInt8_13_io_deq_bits : _T_2438 ? _Queue64_UInt8_12_io_deq_bits : _T_2437 ? _Queue64_UInt8_11_io_deq_bits : _T_2436 ? _Queue64_UInt8_10_io_deq_bits : _T_2435 ? _Queue64_UInt8_9_io_deq_bits : _T_2434 ? _Queue64_UInt8_8_io_deq_bits : _T_2433 ? _Queue64_UInt8_7_io_deq_bits : _T_2432 ? _Queue64_UInt8_6_io_deq_bits : _T_2431 ? _Queue64_UInt8_5_io_deq_bits : _T_2430 ? _Queue64_UInt8_4_io_deq_bits : _T_2429 ? _Queue64_UInt8_3_io_deq_bits : _T_2428 ? _Queue64_UInt8_2_io_deq_bits : _T_2427 ? _Queue64_UInt8_1_io_deq_bits : _T_2426 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_3 = _T_2457 ? _Queue64_UInt8_31_io_deq_valid : _T_2456 ? _Queue64_UInt8_30_io_deq_valid : _T_2455 ? _Queue64_UInt8_29_io_deq_valid : _T_2454 ? _Queue64_UInt8_28_io_deq_valid : _T_2453 ? _Queue64_UInt8_27_io_deq_valid : _T_2452 ? _Queue64_UInt8_26_io_deq_valid : _T_2451 ? _Queue64_UInt8_25_io_deq_valid : _T_2450 ? _Queue64_UInt8_24_io_deq_valid : _T_2449 ? _Queue64_UInt8_23_io_deq_valid : _T_2448 ? _Queue64_UInt8_22_io_deq_valid : _T_2447 ? _Queue64_UInt8_21_io_deq_valid : _T_2446 ? _Queue64_UInt8_20_io_deq_valid : _T_2445 ? _Queue64_UInt8_19_io_deq_valid : _T_2444 ? _Queue64_UInt8_18_io_deq_valid : _T_2443 ? _Queue64_UInt8_17_io_deq_valid : _T_2442 ? _Queue64_UInt8_16_io_deq_valid : _T_2441 ? _Queue64_UInt8_15_io_deq_valid : _T_2440 ? _Queue64_UInt8_14_io_deq_valid : _T_2439 ? _Queue64_UInt8_13_io_deq_valid : _T_2438 ? _Queue64_UInt8_12_io_deq_valid : _T_2437 ? _Queue64_UInt8_11_io_deq_valid : _T_2436 ? _Queue64_UInt8_10_io_deq_valid : _T_2435 ? _Queue64_UInt8_9_io_deq_valid : _T_2434 ? _Queue64_UInt8_8_io_deq_valid : _T_2433 ? _Queue64_UInt8_7_io_deq_valid : _T_2432 ? _Queue64_UInt8_6_io_deq_valid : _T_2431 ? _Queue64_UInt8_5_io_deq_valid : _T_2430 ? _Queue64_UInt8_4_io_deq_valid : _T_2429 ? _Queue64_UInt8_3_io_deq_valid : _T_2428 ? _Queue64_UInt8_2_io_deq_valid : _T_2427 ? _Queue64_UInt8_1_io_deq_valid : _T_2426 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_4 = _remapindex_T + 7'h4; // @[MemLoader.scala:177:33] wire [6:0] _GEN_95 = _remapindex_T_4 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_4 = _GEN_95[5:0]; // @[MemLoader.scala:177:54] wire _T_2458 = remapindex_4 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2459 = remapindex_4 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2460 = remapindex_4 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2461 = remapindex_4 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2462 = remapindex_4 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2463 = remapindex_4 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2464 = remapindex_4 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2465 = remapindex_4 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2466 = remapindex_4 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2467 = remapindex_4 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2468 = remapindex_4 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2469 = remapindex_4 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2470 = remapindex_4 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2471 = remapindex_4 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2472 = remapindex_4 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2473 = remapindex_4 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2474 = remapindex_4 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2475 = remapindex_4 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2476 = remapindex_4 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2477 = remapindex_4 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2478 = remapindex_4 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2479 = remapindex_4 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2480 = remapindex_4 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2481 = remapindex_4 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2482 = remapindex_4 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2483 = remapindex_4 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2484 = remapindex_4 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2485 = remapindex_4 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2486 = remapindex_4 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2487 = remapindex_4 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2488 = remapindex_4 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2489 = remapindex_4 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_4 = _T_2489 ? _Queue64_UInt8_31_io_deq_bits : _T_2488 ? _Queue64_UInt8_30_io_deq_bits : _T_2487 ? _Queue64_UInt8_29_io_deq_bits : _T_2486 ? _Queue64_UInt8_28_io_deq_bits : _T_2485 ? _Queue64_UInt8_27_io_deq_bits : _T_2484 ? _Queue64_UInt8_26_io_deq_bits : _T_2483 ? _Queue64_UInt8_25_io_deq_bits : _T_2482 ? _Queue64_UInt8_24_io_deq_bits : _T_2481 ? _Queue64_UInt8_23_io_deq_bits : _T_2480 ? _Queue64_UInt8_22_io_deq_bits : _T_2479 ? _Queue64_UInt8_21_io_deq_bits : _T_2478 ? _Queue64_UInt8_20_io_deq_bits : _T_2477 ? _Queue64_UInt8_19_io_deq_bits : _T_2476 ? _Queue64_UInt8_18_io_deq_bits : _T_2475 ? _Queue64_UInt8_17_io_deq_bits : _T_2474 ? _Queue64_UInt8_16_io_deq_bits : _T_2473 ? _Queue64_UInt8_15_io_deq_bits : _T_2472 ? _Queue64_UInt8_14_io_deq_bits : _T_2471 ? _Queue64_UInt8_13_io_deq_bits : _T_2470 ? _Queue64_UInt8_12_io_deq_bits : _T_2469 ? _Queue64_UInt8_11_io_deq_bits : _T_2468 ? _Queue64_UInt8_10_io_deq_bits : _T_2467 ? _Queue64_UInt8_9_io_deq_bits : _T_2466 ? _Queue64_UInt8_8_io_deq_bits : _T_2465 ? _Queue64_UInt8_7_io_deq_bits : _T_2464 ? _Queue64_UInt8_6_io_deq_bits : _T_2463 ? _Queue64_UInt8_5_io_deq_bits : _T_2462 ? _Queue64_UInt8_4_io_deq_bits : _T_2461 ? _Queue64_UInt8_3_io_deq_bits : _T_2460 ? _Queue64_UInt8_2_io_deq_bits : _T_2459 ? _Queue64_UInt8_1_io_deq_bits : _T_2458 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_4 = _T_2489 ? _Queue64_UInt8_31_io_deq_valid : _T_2488 ? _Queue64_UInt8_30_io_deq_valid : _T_2487 ? _Queue64_UInt8_29_io_deq_valid : _T_2486 ? _Queue64_UInt8_28_io_deq_valid : _T_2485 ? _Queue64_UInt8_27_io_deq_valid : _T_2484 ? _Queue64_UInt8_26_io_deq_valid : _T_2483 ? _Queue64_UInt8_25_io_deq_valid : _T_2482 ? _Queue64_UInt8_24_io_deq_valid : _T_2481 ? _Queue64_UInt8_23_io_deq_valid : _T_2480 ? _Queue64_UInt8_22_io_deq_valid : _T_2479 ? _Queue64_UInt8_21_io_deq_valid : _T_2478 ? _Queue64_UInt8_20_io_deq_valid : _T_2477 ? _Queue64_UInt8_19_io_deq_valid : _T_2476 ? _Queue64_UInt8_18_io_deq_valid : _T_2475 ? _Queue64_UInt8_17_io_deq_valid : _T_2474 ? _Queue64_UInt8_16_io_deq_valid : _T_2473 ? _Queue64_UInt8_15_io_deq_valid : _T_2472 ? _Queue64_UInt8_14_io_deq_valid : _T_2471 ? _Queue64_UInt8_13_io_deq_valid : _T_2470 ? _Queue64_UInt8_12_io_deq_valid : _T_2469 ? _Queue64_UInt8_11_io_deq_valid : _T_2468 ? _Queue64_UInt8_10_io_deq_valid : _T_2467 ? _Queue64_UInt8_9_io_deq_valid : _T_2466 ? _Queue64_UInt8_8_io_deq_valid : _T_2465 ? _Queue64_UInt8_7_io_deq_valid : _T_2464 ? _Queue64_UInt8_6_io_deq_valid : _T_2463 ? _Queue64_UInt8_5_io_deq_valid : _T_2462 ? _Queue64_UInt8_4_io_deq_valid : _T_2461 ? _Queue64_UInt8_3_io_deq_valid : _T_2460 ? _Queue64_UInt8_2_io_deq_valid : _T_2459 ? _Queue64_UInt8_1_io_deq_valid : _T_2458 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_5 = _remapindex_T + 7'h5; // @[MemLoader.scala:177:33] wire [6:0] _GEN_96 = _remapindex_T_5 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_5 = _GEN_96[5:0]; // @[MemLoader.scala:177:54] wire _T_2490 = remapindex_5 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2491 = remapindex_5 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2492 = remapindex_5 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2493 = remapindex_5 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2494 = remapindex_5 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2495 = remapindex_5 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2496 = remapindex_5 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2497 = remapindex_5 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2498 = remapindex_5 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2499 = remapindex_5 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2500 = remapindex_5 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2501 = remapindex_5 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2502 = remapindex_5 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2503 = remapindex_5 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2504 = remapindex_5 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2505 = remapindex_5 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2506 = remapindex_5 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2507 = remapindex_5 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2508 = remapindex_5 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2509 = remapindex_5 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2510 = remapindex_5 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2511 = remapindex_5 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2512 = remapindex_5 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2513 = remapindex_5 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2514 = remapindex_5 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2515 = remapindex_5 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2516 = remapindex_5 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2517 = remapindex_5 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2518 = remapindex_5 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2519 = remapindex_5 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2520 = remapindex_5 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2521 = remapindex_5 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_5 = _T_2521 ? _Queue64_UInt8_31_io_deq_bits : _T_2520 ? _Queue64_UInt8_30_io_deq_bits : _T_2519 ? _Queue64_UInt8_29_io_deq_bits : _T_2518 ? _Queue64_UInt8_28_io_deq_bits : _T_2517 ? _Queue64_UInt8_27_io_deq_bits : _T_2516 ? _Queue64_UInt8_26_io_deq_bits : _T_2515 ? _Queue64_UInt8_25_io_deq_bits : _T_2514 ? _Queue64_UInt8_24_io_deq_bits : _T_2513 ? _Queue64_UInt8_23_io_deq_bits : _T_2512 ? _Queue64_UInt8_22_io_deq_bits : _T_2511 ? _Queue64_UInt8_21_io_deq_bits : _T_2510 ? _Queue64_UInt8_20_io_deq_bits : _T_2509 ? _Queue64_UInt8_19_io_deq_bits : _T_2508 ? _Queue64_UInt8_18_io_deq_bits : _T_2507 ? _Queue64_UInt8_17_io_deq_bits : _T_2506 ? _Queue64_UInt8_16_io_deq_bits : _T_2505 ? _Queue64_UInt8_15_io_deq_bits : _T_2504 ? _Queue64_UInt8_14_io_deq_bits : _T_2503 ? _Queue64_UInt8_13_io_deq_bits : _T_2502 ? _Queue64_UInt8_12_io_deq_bits : _T_2501 ? _Queue64_UInt8_11_io_deq_bits : _T_2500 ? _Queue64_UInt8_10_io_deq_bits : _T_2499 ? _Queue64_UInt8_9_io_deq_bits : _T_2498 ? _Queue64_UInt8_8_io_deq_bits : _T_2497 ? _Queue64_UInt8_7_io_deq_bits : _T_2496 ? _Queue64_UInt8_6_io_deq_bits : _T_2495 ? _Queue64_UInt8_5_io_deq_bits : _T_2494 ? _Queue64_UInt8_4_io_deq_bits : _T_2493 ? _Queue64_UInt8_3_io_deq_bits : _T_2492 ? _Queue64_UInt8_2_io_deq_bits : _T_2491 ? _Queue64_UInt8_1_io_deq_bits : _T_2490 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_5 = _T_2521 ? _Queue64_UInt8_31_io_deq_valid : _T_2520 ? _Queue64_UInt8_30_io_deq_valid : _T_2519 ? _Queue64_UInt8_29_io_deq_valid : _T_2518 ? _Queue64_UInt8_28_io_deq_valid : _T_2517 ? _Queue64_UInt8_27_io_deq_valid : _T_2516 ? _Queue64_UInt8_26_io_deq_valid : _T_2515 ? _Queue64_UInt8_25_io_deq_valid : _T_2514 ? _Queue64_UInt8_24_io_deq_valid : _T_2513 ? _Queue64_UInt8_23_io_deq_valid : _T_2512 ? _Queue64_UInt8_22_io_deq_valid : _T_2511 ? _Queue64_UInt8_21_io_deq_valid : _T_2510 ? _Queue64_UInt8_20_io_deq_valid : _T_2509 ? _Queue64_UInt8_19_io_deq_valid : _T_2508 ? _Queue64_UInt8_18_io_deq_valid : _T_2507 ? _Queue64_UInt8_17_io_deq_valid : _T_2506 ? _Queue64_UInt8_16_io_deq_valid : _T_2505 ? _Queue64_UInt8_15_io_deq_valid : _T_2504 ? _Queue64_UInt8_14_io_deq_valid : _T_2503 ? _Queue64_UInt8_13_io_deq_valid : _T_2502 ? _Queue64_UInt8_12_io_deq_valid : _T_2501 ? _Queue64_UInt8_11_io_deq_valid : _T_2500 ? _Queue64_UInt8_10_io_deq_valid : _T_2499 ? _Queue64_UInt8_9_io_deq_valid : _T_2498 ? _Queue64_UInt8_8_io_deq_valid : _T_2497 ? _Queue64_UInt8_7_io_deq_valid : _T_2496 ? _Queue64_UInt8_6_io_deq_valid : _T_2495 ? _Queue64_UInt8_5_io_deq_valid : _T_2494 ? _Queue64_UInt8_4_io_deq_valid : _T_2493 ? _Queue64_UInt8_3_io_deq_valid : _T_2492 ? _Queue64_UInt8_2_io_deq_valid : _T_2491 ? _Queue64_UInt8_1_io_deq_valid : _T_2490 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_6 = _remapindex_T + 7'h6; // @[MemLoader.scala:177:33] wire [6:0] _GEN_97 = _remapindex_T_6 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_6 = _GEN_97[5:0]; // @[MemLoader.scala:177:54] wire _T_2522 = remapindex_6 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2523 = remapindex_6 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2524 = remapindex_6 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2525 = remapindex_6 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2526 = remapindex_6 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2527 = remapindex_6 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2528 = remapindex_6 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2529 = remapindex_6 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2530 = remapindex_6 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2531 = remapindex_6 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2532 = remapindex_6 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2533 = remapindex_6 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2534 = remapindex_6 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2535 = remapindex_6 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2536 = remapindex_6 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2537 = remapindex_6 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2538 = remapindex_6 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2539 = remapindex_6 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2540 = remapindex_6 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2541 = remapindex_6 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2542 = remapindex_6 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2543 = remapindex_6 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2544 = remapindex_6 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2545 = remapindex_6 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2546 = remapindex_6 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2547 = remapindex_6 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2548 = remapindex_6 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2549 = remapindex_6 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2550 = remapindex_6 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2551 = remapindex_6 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2552 = remapindex_6 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2553 = remapindex_6 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_6 = _T_2553 ? _Queue64_UInt8_31_io_deq_bits : _T_2552 ? _Queue64_UInt8_30_io_deq_bits : _T_2551 ? _Queue64_UInt8_29_io_deq_bits : _T_2550 ? _Queue64_UInt8_28_io_deq_bits : _T_2549 ? _Queue64_UInt8_27_io_deq_bits : _T_2548 ? _Queue64_UInt8_26_io_deq_bits : _T_2547 ? _Queue64_UInt8_25_io_deq_bits : _T_2546 ? _Queue64_UInt8_24_io_deq_bits : _T_2545 ? _Queue64_UInt8_23_io_deq_bits : _T_2544 ? _Queue64_UInt8_22_io_deq_bits : _T_2543 ? _Queue64_UInt8_21_io_deq_bits : _T_2542 ? _Queue64_UInt8_20_io_deq_bits : _T_2541 ? _Queue64_UInt8_19_io_deq_bits : _T_2540 ? _Queue64_UInt8_18_io_deq_bits : _T_2539 ? _Queue64_UInt8_17_io_deq_bits : _T_2538 ? _Queue64_UInt8_16_io_deq_bits : _T_2537 ? _Queue64_UInt8_15_io_deq_bits : _T_2536 ? _Queue64_UInt8_14_io_deq_bits : _T_2535 ? _Queue64_UInt8_13_io_deq_bits : _T_2534 ? _Queue64_UInt8_12_io_deq_bits : _T_2533 ? _Queue64_UInt8_11_io_deq_bits : _T_2532 ? _Queue64_UInt8_10_io_deq_bits : _T_2531 ? _Queue64_UInt8_9_io_deq_bits : _T_2530 ? _Queue64_UInt8_8_io_deq_bits : _T_2529 ? _Queue64_UInt8_7_io_deq_bits : _T_2528 ? _Queue64_UInt8_6_io_deq_bits : _T_2527 ? _Queue64_UInt8_5_io_deq_bits : _T_2526 ? _Queue64_UInt8_4_io_deq_bits : _T_2525 ? _Queue64_UInt8_3_io_deq_bits : _T_2524 ? _Queue64_UInt8_2_io_deq_bits : _T_2523 ? _Queue64_UInt8_1_io_deq_bits : _T_2522 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_6 = _T_2553 ? _Queue64_UInt8_31_io_deq_valid : _T_2552 ? _Queue64_UInt8_30_io_deq_valid : _T_2551 ? _Queue64_UInt8_29_io_deq_valid : _T_2550 ? _Queue64_UInt8_28_io_deq_valid : _T_2549 ? _Queue64_UInt8_27_io_deq_valid : _T_2548 ? _Queue64_UInt8_26_io_deq_valid : _T_2547 ? _Queue64_UInt8_25_io_deq_valid : _T_2546 ? _Queue64_UInt8_24_io_deq_valid : _T_2545 ? _Queue64_UInt8_23_io_deq_valid : _T_2544 ? _Queue64_UInt8_22_io_deq_valid : _T_2543 ? _Queue64_UInt8_21_io_deq_valid : _T_2542 ? _Queue64_UInt8_20_io_deq_valid : _T_2541 ? _Queue64_UInt8_19_io_deq_valid : _T_2540 ? _Queue64_UInt8_18_io_deq_valid : _T_2539 ? _Queue64_UInt8_17_io_deq_valid : _T_2538 ? _Queue64_UInt8_16_io_deq_valid : _T_2537 ? _Queue64_UInt8_15_io_deq_valid : _T_2536 ? _Queue64_UInt8_14_io_deq_valid : _T_2535 ? _Queue64_UInt8_13_io_deq_valid : _T_2534 ? _Queue64_UInt8_12_io_deq_valid : _T_2533 ? _Queue64_UInt8_11_io_deq_valid : _T_2532 ? _Queue64_UInt8_10_io_deq_valid : _T_2531 ? _Queue64_UInt8_9_io_deq_valid : _T_2530 ? _Queue64_UInt8_8_io_deq_valid : _T_2529 ? _Queue64_UInt8_7_io_deq_valid : _T_2528 ? _Queue64_UInt8_6_io_deq_valid : _T_2527 ? _Queue64_UInt8_5_io_deq_valid : _T_2526 ? _Queue64_UInt8_4_io_deq_valid : _T_2525 ? _Queue64_UInt8_3_io_deq_valid : _T_2524 ? _Queue64_UInt8_2_io_deq_valid : _T_2523 ? _Queue64_UInt8_1_io_deq_valid : _T_2522 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_7 = _remapindex_T + 7'h7; // @[MemLoader.scala:177:33] wire [6:0] _GEN_98 = _remapindex_T_7 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_7 = _GEN_98[5:0]; // @[MemLoader.scala:177:54] wire _T_2554 = remapindex_7 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2555 = remapindex_7 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2556 = remapindex_7 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2557 = remapindex_7 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2558 = remapindex_7 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2559 = remapindex_7 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2560 = remapindex_7 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2561 = remapindex_7 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2562 = remapindex_7 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2563 = remapindex_7 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2564 = remapindex_7 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2565 = remapindex_7 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2566 = remapindex_7 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2567 = remapindex_7 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2568 = remapindex_7 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2569 = remapindex_7 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2570 = remapindex_7 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2571 = remapindex_7 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2572 = remapindex_7 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2573 = remapindex_7 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2574 = remapindex_7 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2575 = remapindex_7 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2576 = remapindex_7 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2577 = remapindex_7 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2578 = remapindex_7 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2579 = remapindex_7 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2580 = remapindex_7 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2581 = remapindex_7 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2582 = remapindex_7 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2583 = remapindex_7 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2584 = remapindex_7 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2585 = remapindex_7 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_7 = _T_2585 ? _Queue64_UInt8_31_io_deq_bits : _T_2584 ? _Queue64_UInt8_30_io_deq_bits : _T_2583 ? _Queue64_UInt8_29_io_deq_bits : _T_2582 ? _Queue64_UInt8_28_io_deq_bits : _T_2581 ? _Queue64_UInt8_27_io_deq_bits : _T_2580 ? _Queue64_UInt8_26_io_deq_bits : _T_2579 ? _Queue64_UInt8_25_io_deq_bits : _T_2578 ? _Queue64_UInt8_24_io_deq_bits : _T_2577 ? _Queue64_UInt8_23_io_deq_bits : _T_2576 ? _Queue64_UInt8_22_io_deq_bits : _T_2575 ? _Queue64_UInt8_21_io_deq_bits : _T_2574 ? _Queue64_UInt8_20_io_deq_bits : _T_2573 ? _Queue64_UInt8_19_io_deq_bits : _T_2572 ? _Queue64_UInt8_18_io_deq_bits : _T_2571 ? _Queue64_UInt8_17_io_deq_bits : _T_2570 ? _Queue64_UInt8_16_io_deq_bits : _T_2569 ? _Queue64_UInt8_15_io_deq_bits : _T_2568 ? _Queue64_UInt8_14_io_deq_bits : _T_2567 ? _Queue64_UInt8_13_io_deq_bits : _T_2566 ? _Queue64_UInt8_12_io_deq_bits : _T_2565 ? _Queue64_UInt8_11_io_deq_bits : _T_2564 ? _Queue64_UInt8_10_io_deq_bits : _T_2563 ? _Queue64_UInt8_9_io_deq_bits : _T_2562 ? _Queue64_UInt8_8_io_deq_bits : _T_2561 ? _Queue64_UInt8_7_io_deq_bits : _T_2560 ? _Queue64_UInt8_6_io_deq_bits : _T_2559 ? _Queue64_UInt8_5_io_deq_bits : _T_2558 ? _Queue64_UInt8_4_io_deq_bits : _T_2557 ? _Queue64_UInt8_3_io_deq_bits : _T_2556 ? _Queue64_UInt8_2_io_deq_bits : _T_2555 ? _Queue64_UInt8_1_io_deq_bits : _T_2554 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_7 = _T_2585 ? _Queue64_UInt8_31_io_deq_valid : _T_2584 ? _Queue64_UInt8_30_io_deq_valid : _T_2583 ? _Queue64_UInt8_29_io_deq_valid : _T_2582 ? _Queue64_UInt8_28_io_deq_valid : _T_2581 ? _Queue64_UInt8_27_io_deq_valid : _T_2580 ? _Queue64_UInt8_26_io_deq_valid : _T_2579 ? _Queue64_UInt8_25_io_deq_valid : _T_2578 ? _Queue64_UInt8_24_io_deq_valid : _T_2577 ? _Queue64_UInt8_23_io_deq_valid : _T_2576 ? _Queue64_UInt8_22_io_deq_valid : _T_2575 ? _Queue64_UInt8_21_io_deq_valid : _T_2574 ? _Queue64_UInt8_20_io_deq_valid : _T_2573 ? _Queue64_UInt8_19_io_deq_valid : _T_2572 ? _Queue64_UInt8_18_io_deq_valid : _T_2571 ? _Queue64_UInt8_17_io_deq_valid : _T_2570 ? _Queue64_UInt8_16_io_deq_valid : _T_2569 ? _Queue64_UInt8_15_io_deq_valid : _T_2568 ? _Queue64_UInt8_14_io_deq_valid : _T_2567 ? _Queue64_UInt8_13_io_deq_valid : _T_2566 ? _Queue64_UInt8_12_io_deq_valid : _T_2565 ? _Queue64_UInt8_11_io_deq_valid : _T_2564 ? _Queue64_UInt8_10_io_deq_valid : _T_2563 ? _Queue64_UInt8_9_io_deq_valid : _T_2562 ? _Queue64_UInt8_8_io_deq_valid : _T_2561 ? _Queue64_UInt8_7_io_deq_valid : _T_2560 ? _Queue64_UInt8_6_io_deq_valid : _T_2559 ? _Queue64_UInt8_5_io_deq_valid : _T_2558 ? _Queue64_UInt8_4_io_deq_valid : _T_2557 ? _Queue64_UInt8_3_io_deq_valid : _T_2556 ? _Queue64_UInt8_2_io_deq_valid : _T_2555 ? _Queue64_UInt8_1_io_deq_valid : _T_2554 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_8 = _remapindex_T + 7'h8; // @[MemLoader.scala:177:33] wire [6:0] _GEN_99 = _remapindex_T_8 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_8 = _GEN_99[5:0]; // @[MemLoader.scala:177:54] wire _T_2586 = remapindex_8 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2587 = remapindex_8 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2588 = remapindex_8 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2589 = remapindex_8 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2590 = remapindex_8 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2591 = remapindex_8 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2592 = remapindex_8 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2593 = remapindex_8 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2594 = remapindex_8 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2595 = remapindex_8 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2596 = remapindex_8 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2597 = remapindex_8 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2598 = remapindex_8 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2599 = remapindex_8 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2600 = remapindex_8 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2601 = remapindex_8 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2602 = remapindex_8 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2603 = remapindex_8 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2604 = remapindex_8 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2605 = remapindex_8 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2606 = remapindex_8 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2607 = remapindex_8 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2608 = remapindex_8 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2609 = remapindex_8 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2610 = remapindex_8 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2611 = remapindex_8 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2612 = remapindex_8 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2613 = remapindex_8 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2614 = remapindex_8 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2615 = remapindex_8 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2616 = remapindex_8 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2617 = remapindex_8 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_8 = _T_2617 ? _Queue64_UInt8_31_io_deq_bits : _T_2616 ? _Queue64_UInt8_30_io_deq_bits : _T_2615 ? _Queue64_UInt8_29_io_deq_bits : _T_2614 ? _Queue64_UInt8_28_io_deq_bits : _T_2613 ? _Queue64_UInt8_27_io_deq_bits : _T_2612 ? _Queue64_UInt8_26_io_deq_bits : _T_2611 ? _Queue64_UInt8_25_io_deq_bits : _T_2610 ? _Queue64_UInt8_24_io_deq_bits : _T_2609 ? _Queue64_UInt8_23_io_deq_bits : _T_2608 ? _Queue64_UInt8_22_io_deq_bits : _T_2607 ? _Queue64_UInt8_21_io_deq_bits : _T_2606 ? _Queue64_UInt8_20_io_deq_bits : _T_2605 ? _Queue64_UInt8_19_io_deq_bits : _T_2604 ? _Queue64_UInt8_18_io_deq_bits : _T_2603 ? _Queue64_UInt8_17_io_deq_bits : _T_2602 ? _Queue64_UInt8_16_io_deq_bits : _T_2601 ? _Queue64_UInt8_15_io_deq_bits : _T_2600 ? _Queue64_UInt8_14_io_deq_bits : _T_2599 ? _Queue64_UInt8_13_io_deq_bits : _T_2598 ? _Queue64_UInt8_12_io_deq_bits : _T_2597 ? _Queue64_UInt8_11_io_deq_bits : _T_2596 ? _Queue64_UInt8_10_io_deq_bits : _T_2595 ? _Queue64_UInt8_9_io_deq_bits : _T_2594 ? _Queue64_UInt8_8_io_deq_bits : _T_2593 ? _Queue64_UInt8_7_io_deq_bits : _T_2592 ? _Queue64_UInt8_6_io_deq_bits : _T_2591 ? _Queue64_UInt8_5_io_deq_bits : _T_2590 ? _Queue64_UInt8_4_io_deq_bits : _T_2589 ? _Queue64_UInt8_3_io_deq_bits : _T_2588 ? _Queue64_UInt8_2_io_deq_bits : _T_2587 ? _Queue64_UInt8_1_io_deq_bits : _T_2586 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_8 = _T_2617 ? _Queue64_UInt8_31_io_deq_valid : _T_2616 ? _Queue64_UInt8_30_io_deq_valid : _T_2615 ? _Queue64_UInt8_29_io_deq_valid : _T_2614 ? _Queue64_UInt8_28_io_deq_valid : _T_2613 ? _Queue64_UInt8_27_io_deq_valid : _T_2612 ? _Queue64_UInt8_26_io_deq_valid : _T_2611 ? _Queue64_UInt8_25_io_deq_valid : _T_2610 ? _Queue64_UInt8_24_io_deq_valid : _T_2609 ? _Queue64_UInt8_23_io_deq_valid : _T_2608 ? _Queue64_UInt8_22_io_deq_valid : _T_2607 ? _Queue64_UInt8_21_io_deq_valid : _T_2606 ? _Queue64_UInt8_20_io_deq_valid : _T_2605 ? _Queue64_UInt8_19_io_deq_valid : _T_2604 ? _Queue64_UInt8_18_io_deq_valid : _T_2603 ? _Queue64_UInt8_17_io_deq_valid : _T_2602 ? _Queue64_UInt8_16_io_deq_valid : _T_2601 ? _Queue64_UInt8_15_io_deq_valid : _T_2600 ? _Queue64_UInt8_14_io_deq_valid : _T_2599 ? _Queue64_UInt8_13_io_deq_valid : _T_2598 ? _Queue64_UInt8_12_io_deq_valid : _T_2597 ? _Queue64_UInt8_11_io_deq_valid : _T_2596 ? _Queue64_UInt8_10_io_deq_valid : _T_2595 ? _Queue64_UInt8_9_io_deq_valid : _T_2594 ? _Queue64_UInt8_8_io_deq_valid : _T_2593 ? _Queue64_UInt8_7_io_deq_valid : _T_2592 ? _Queue64_UInt8_6_io_deq_valid : _T_2591 ? _Queue64_UInt8_5_io_deq_valid : _T_2590 ? _Queue64_UInt8_4_io_deq_valid : _T_2589 ? _Queue64_UInt8_3_io_deq_valid : _T_2588 ? _Queue64_UInt8_2_io_deq_valid : _T_2587 ? _Queue64_UInt8_1_io_deq_valid : _T_2586 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_9 = _remapindex_T + 7'h9; // @[MemLoader.scala:177:33] wire [6:0] _GEN_100 = _remapindex_T_9 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_9 = _GEN_100[5:0]; // @[MemLoader.scala:177:54] wire _T_2618 = remapindex_9 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2619 = remapindex_9 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2620 = remapindex_9 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2621 = remapindex_9 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2622 = remapindex_9 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2623 = remapindex_9 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2624 = remapindex_9 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2625 = remapindex_9 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2626 = remapindex_9 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2627 = remapindex_9 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2628 = remapindex_9 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2629 = remapindex_9 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2630 = remapindex_9 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2631 = remapindex_9 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2632 = remapindex_9 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2633 = remapindex_9 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2634 = remapindex_9 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2635 = remapindex_9 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2636 = remapindex_9 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2637 = remapindex_9 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2638 = remapindex_9 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2639 = remapindex_9 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2640 = remapindex_9 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2641 = remapindex_9 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2642 = remapindex_9 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2643 = remapindex_9 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2644 = remapindex_9 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2645 = remapindex_9 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2646 = remapindex_9 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2647 = remapindex_9 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2648 = remapindex_9 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2649 = remapindex_9 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_9 = _T_2649 ? _Queue64_UInt8_31_io_deq_bits : _T_2648 ? _Queue64_UInt8_30_io_deq_bits : _T_2647 ? _Queue64_UInt8_29_io_deq_bits : _T_2646 ? _Queue64_UInt8_28_io_deq_bits : _T_2645 ? _Queue64_UInt8_27_io_deq_bits : _T_2644 ? _Queue64_UInt8_26_io_deq_bits : _T_2643 ? _Queue64_UInt8_25_io_deq_bits : _T_2642 ? _Queue64_UInt8_24_io_deq_bits : _T_2641 ? _Queue64_UInt8_23_io_deq_bits : _T_2640 ? _Queue64_UInt8_22_io_deq_bits : _T_2639 ? _Queue64_UInt8_21_io_deq_bits : _T_2638 ? _Queue64_UInt8_20_io_deq_bits : _T_2637 ? _Queue64_UInt8_19_io_deq_bits : _T_2636 ? _Queue64_UInt8_18_io_deq_bits : _T_2635 ? _Queue64_UInt8_17_io_deq_bits : _T_2634 ? _Queue64_UInt8_16_io_deq_bits : _T_2633 ? _Queue64_UInt8_15_io_deq_bits : _T_2632 ? _Queue64_UInt8_14_io_deq_bits : _T_2631 ? _Queue64_UInt8_13_io_deq_bits : _T_2630 ? _Queue64_UInt8_12_io_deq_bits : _T_2629 ? _Queue64_UInt8_11_io_deq_bits : _T_2628 ? _Queue64_UInt8_10_io_deq_bits : _T_2627 ? _Queue64_UInt8_9_io_deq_bits : _T_2626 ? _Queue64_UInt8_8_io_deq_bits : _T_2625 ? _Queue64_UInt8_7_io_deq_bits : _T_2624 ? _Queue64_UInt8_6_io_deq_bits : _T_2623 ? _Queue64_UInt8_5_io_deq_bits : _T_2622 ? _Queue64_UInt8_4_io_deq_bits : _T_2621 ? _Queue64_UInt8_3_io_deq_bits : _T_2620 ? _Queue64_UInt8_2_io_deq_bits : _T_2619 ? _Queue64_UInt8_1_io_deq_bits : _T_2618 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_9 = _T_2649 ? _Queue64_UInt8_31_io_deq_valid : _T_2648 ? _Queue64_UInt8_30_io_deq_valid : _T_2647 ? _Queue64_UInt8_29_io_deq_valid : _T_2646 ? _Queue64_UInt8_28_io_deq_valid : _T_2645 ? _Queue64_UInt8_27_io_deq_valid : _T_2644 ? _Queue64_UInt8_26_io_deq_valid : _T_2643 ? _Queue64_UInt8_25_io_deq_valid : _T_2642 ? _Queue64_UInt8_24_io_deq_valid : _T_2641 ? _Queue64_UInt8_23_io_deq_valid : _T_2640 ? _Queue64_UInt8_22_io_deq_valid : _T_2639 ? _Queue64_UInt8_21_io_deq_valid : _T_2638 ? _Queue64_UInt8_20_io_deq_valid : _T_2637 ? _Queue64_UInt8_19_io_deq_valid : _T_2636 ? _Queue64_UInt8_18_io_deq_valid : _T_2635 ? _Queue64_UInt8_17_io_deq_valid : _T_2634 ? _Queue64_UInt8_16_io_deq_valid : _T_2633 ? _Queue64_UInt8_15_io_deq_valid : _T_2632 ? _Queue64_UInt8_14_io_deq_valid : _T_2631 ? _Queue64_UInt8_13_io_deq_valid : _T_2630 ? _Queue64_UInt8_12_io_deq_valid : _T_2629 ? _Queue64_UInt8_11_io_deq_valid : _T_2628 ? _Queue64_UInt8_10_io_deq_valid : _T_2627 ? _Queue64_UInt8_9_io_deq_valid : _T_2626 ? _Queue64_UInt8_8_io_deq_valid : _T_2625 ? _Queue64_UInt8_7_io_deq_valid : _T_2624 ? _Queue64_UInt8_6_io_deq_valid : _T_2623 ? _Queue64_UInt8_5_io_deq_valid : _T_2622 ? _Queue64_UInt8_4_io_deq_valid : _T_2621 ? _Queue64_UInt8_3_io_deq_valid : _T_2620 ? _Queue64_UInt8_2_io_deq_valid : _T_2619 ? _Queue64_UInt8_1_io_deq_valid : _T_2618 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_10 = _remapindex_T + 7'hA; // @[MemLoader.scala:177:33] wire [6:0] _GEN_101 = _remapindex_T_10 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_10 = _GEN_101[5:0]; // @[MemLoader.scala:177:54] wire _T_2650 = remapindex_10 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2651 = remapindex_10 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2652 = remapindex_10 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2653 = remapindex_10 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2654 = remapindex_10 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2655 = remapindex_10 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2656 = remapindex_10 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2657 = remapindex_10 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2658 = remapindex_10 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2659 = remapindex_10 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2660 = remapindex_10 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2661 = remapindex_10 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2662 = remapindex_10 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2663 = remapindex_10 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2664 = remapindex_10 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2665 = remapindex_10 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2666 = remapindex_10 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2667 = remapindex_10 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2668 = remapindex_10 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2669 = remapindex_10 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2670 = remapindex_10 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2671 = remapindex_10 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2672 = remapindex_10 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2673 = remapindex_10 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2674 = remapindex_10 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2675 = remapindex_10 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2676 = remapindex_10 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2677 = remapindex_10 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2678 = remapindex_10 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2679 = remapindex_10 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2680 = remapindex_10 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2681 = remapindex_10 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_10 = _T_2681 ? _Queue64_UInt8_31_io_deq_bits : _T_2680 ? _Queue64_UInt8_30_io_deq_bits : _T_2679 ? _Queue64_UInt8_29_io_deq_bits : _T_2678 ? _Queue64_UInt8_28_io_deq_bits : _T_2677 ? _Queue64_UInt8_27_io_deq_bits : _T_2676 ? _Queue64_UInt8_26_io_deq_bits : _T_2675 ? _Queue64_UInt8_25_io_deq_bits : _T_2674 ? _Queue64_UInt8_24_io_deq_bits : _T_2673 ? _Queue64_UInt8_23_io_deq_bits : _T_2672 ? _Queue64_UInt8_22_io_deq_bits : _T_2671 ? _Queue64_UInt8_21_io_deq_bits : _T_2670 ? _Queue64_UInt8_20_io_deq_bits : _T_2669 ? _Queue64_UInt8_19_io_deq_bits : _T_2668 ? _Queue64_UInt8_18_io_deq_bits : _T_2667 ? _Queue64_UInt8_17_io_deq_bits : _T_2666 ? _Queue64_UInt8_16_io_deq_bits : _T_2665 ? _Queue64_UInt8_15_io_deq_bits : _T_2664 ? _Queue64_UInt8_14_io_deq_bits : _T_2663 ? _Queue64_UInt8_13_io_deq_bits : _T_2662 ? _Queue64_UInt8_12_io_deq_bits : _T_2661 ? _Queue64_UInt8_11_io_deq_bits : _T_2660 ? _Queue64_UInt8_10_io_deq_bits : _T_2659 ? _Queue64_UInt8_9_io_deq_bits : _T_2658 ? _Queue64_UInt8_8_io_deq_bits : _T_2657 ? _Queue64_UInt8_7_io_deq_bits : _T_2656 ? _Queue64_UInt8_6_io_deq_bits : _T_2655 ? _Queue64_UInt8_5_io_deq_bits : _T_2654 ? _Queue64_UInt8_4_io_deq_bits : _T_2653 ? _Queue64_UInt8_3_io_deq_bits : _T_2652 ? _Queue64_UInt8_2_io_deq_bits : _T_2651 ? _Queue64_UInt8_1_io_deq_bits : _T_2650 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_10 = _T_2681 ? _Queue64_UInt8_31_io_deq_valid : _T_2680 ? _Queue64_UInt8_30_io_deq_valid : _T_2679 ? _Queue64_UInt8_29_io_deq_valid : _T_2678 ? _Queue64_UInt8_28_io_deq_valid : _T_2677 ? _Queue64_UInt8_27_io_deq_valid : _T_2676 ? _Queue64_UInt8_26_io_deq_valid : _T_2675 ? _Queue64_UInt8_25_io_deq_valid : _T_2674 ? _Queue64_UInt8_24_io_deq_valid : _T_2673 ? _Queue64_UInt8_23_io_deq_valid : _T_2672 ? _Queue64_UInt8_22_io_deq_valid : _T_2671 ? _Queue64_UInt8_21_io_deq_valid : _T_2670 ? _Queue64_UInt8_20_io_deq_valid : _T_2669 ? _Queue64_UInt8_19_io_deq_valid : _T_2668 ? _Queue64_UInt8_18_io_deq_valid : _T_2667 ? _Queue64_UInt8_17_io_deq_valid : _T_2666 ? _Queue64_UInt8_16_io_deq_valid : _T_2665 ? _Queue64_UInt8_15_io_deq_valid : _T_2664 ? _Queue64_UInt8_14_io_deq_valid : _T_2663 ? _Queue64_UInt8_13_io_deq_valid : _T_2662 ? _Queue64_UInt8_12_io_deq_valid : _T_2661 ? _Queue64_UInt8_11_io_deq_valid : _T_2660 ? _Queue64_UInt8_10_io_deq_valid : _T_2659 ? _Queue64_UInt8_9_io_deq_valid : _T_2658 ? _Queue64_UInt8_8_io_deq_valid : _T_2657 ? _Queue64_UInt8_7_io_deq_valid : _T_2656 ? _Queue64_UInt8_6_io_deq_valid : _T_2655 ? _Queue64_UInt8_5_io_deq_valid : _T_2654 ? _Queue64_UInt8_4_io_deq_valid : _T_2653 ? _Queue64_UInt8_3_io_deq_valid : _T_2652 ? _Queue64_UInt8_2_io_deq_valid : _T_2651 ? _Queue64_UInt8_1_io_deq_valid : _T_2650 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_11 = _remapindex_T + 7'hB; // @[MemLoader.scala:177:33] wire [6:0] _GEN_102 = _remapindex_T_11 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_11 = _GEN_102[5:0]; // @[MemLoader.scala:177:54] wire _T_2682 = remapindex_11 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2683 = remapindex_11 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2684 = remapindex_11 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2685 = remapindex_11 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2686 = remapindex_11 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2687 = remapindex_11 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2688 = remapindex_11 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2689 = remapindex_11 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2690 = remapindex_11 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2691 = remapindex_11 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2692 = remapindex_11 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2693 = remapindex_11 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2694 = remapindex_11 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2695 = remapindex_11 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2696 = remapindex_11 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2697 = remapindex_11 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2698 = remapindex_11 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2699 = remapindex_11 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2700 = remapindex_11 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2701 = remapindex_11 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2702 = remapindex_11 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2703 = remapindex_11 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2704 = remapindex_11 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2705 = remapindex_11 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2706 = remapindex_11 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2707 = remapindex_11 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2708 = remapindex_11 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2709 = remapindex_11 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2710 = remapindex_11 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2711 = remapindex_11 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2712 = remapindex_11 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2713 = remapindex_11 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_11 = _T_2713 ? _Queue64_UInt8_31_io_deq_bits : _T_2712 ? _Queue64_UInt8_30_io_deq_bits : _T_2711 ? _Queue64_UInt8_29_io_deq_bits : _T_2710 ? _Queue64_UInt8_28_io_deq_bits : _T_2709 ? _Queue64_UInt8_27_io_deq_bits : _T_2708 ? _Queue64_UInt8_26_io_deq_bits : _T_2707 ? _Queue64_UInt8_25_io_deq_bits : _T_2706 ? _Queue64_UInt8_24_io_deq_bits : _T_2705 ? _Queue64_UInt8_23_io_deq_bits : _T_2704 ? _Queue64_UInt8_22_io_deq_bits : _T_2703 ? _Queue64_UInt8_21_io_deq_bits : _T_2702 ? _Queue64_UInt8_20_io_deq_bits : _T_2701 ? _Queue64_UInt8_19_io_deq_bits : _T_2700 ? _Queue64_UInt8_18_io_deq_bits : _T_2699 ? _Queue64_UInt8_17_io_deq_bits : _T_2698 ? _Queue64_UInt8_16_io_deq_bits : _T_2697 ? _Queue64_UInt8_15_io_deq_bits : _T_2696 ? _Queue64_UInt8_14_io_deq_bits : _T_2695 ? _Queue64_UInt8_13_io_deq_bits : _T_2694 ? _Queue64_UInt8_12_io_deq_bits : _T_2693 ? _Queue64_UInt8_11_io_deq_bits : _T_2692 ? _Queue64_UInt8_10_io_deq_bits : _T_2691 ? _Queue64_UInt8_9_io_deq_bits : _T_2690 ? _Queue64_UInt8_8_io_deq_bits : _T_2689 ? _Queue64_UInt8_7_io_deq_bits : _T_2688 ? _Queue64_UInt8_6_io_deq_bits : _T_2687 ? _Queue64_UInt8_5_io_deq_bits : _T_2686 ? _Queue64_UInt8_4_io_deq_bits : _T_2685 ? _Queue64_UInt8_3_io_deq_bits : _T_2684 ? _Queue64_UInt8_2_io_deq_bits : _T_2683 ? _Queue64_UInt8_1_io_deq_bits : _T_2682 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_11 = _T_2713 ? _Queue64_UInt8_31_io_deq_valid : _T_2712 ? _Queue64_UInt8_30_io_deq_valid : _T_2711 ? _Queue64_UInt8_29_io_deq_valid : _T_2710 ? _Queue64_UInt8_28_io_deq_valid : _T_2709 ? _Queue64_UInt8_27_io_deq_valid : _T_2708 ? _Queue64_UInt8_26_io_deq_valid : _T_2707 ? _Queue64_UInt8_25_io_deq_valid : _T_2706 ? _Queue64_UInt8_24_io_deq_valid : _T_2705 ? _Queue64_UInt8_23_io_deq_valid : _T_2704 ? _Queue64_UInt8_22_io_deq_valid : _T_2703 ? _Queue64_UInt8_21_io_deq_valid : _T_2702 ? _Queue64_UInt8_20_io_deq_valid : _T_2701 ? _Queue64_UInt8_19_io_deq_valid : _T_2700 ? _Queue64_UInt8_18_io_deq_valid : _T_2699 ? _Queue64_UInt8_17_io_deq_valid : _T_2698 ? _Queue64_UInt8_16_io_deq_valid : _T_2697 ? _Queue64_UInt8_15_io_deq_valid : _T_2696 ? _Queue64_UInt8_14_io_deq_valid : _T_2695 ? _Queue64_UInt8_13_io_deq_valid : _T_2694 ? _Queue64_UInt8_12_io_deq_valid : _T_2693 ? _Queue64_UInt8_11_io_deq_valid : _T_2692 ? _Queue64_UInt8_10_io_deq_valid : _T_2691 ? _Queue64_UInt8_9_io_deq_valid : _T_2690 ? _Queue64_UInt8_8_io_deq_valid : _T_2689 ? _Queue64_UInt8_7_io_deq_valid : _T_2688 ? _Queue64_UInt8_6_io_deq_valid : _T_2687 ? _Queue64_UInt8_5_io_deq_valid : _T_2686 ? _Queue64_UInt8_4_io_deq_valid : _T_2685 ? _Queue64_UInt8_3_io_deq_valid : _T_2684 ? _Queue64_UInt8_2_io_deq_valid : _T_2683 ? _Queue64_UInt8_1_io_deq_valid : _T_2682 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_12 = _remapindex_T + 7'hC; // @[MemLoader.scala:177:33] wire [6:0] _GEN_103 = _remapindex_T_12 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_12 = _GEN_103[5:0]; // @[MemLoader.scala:177:54] wire _T_2714 = remapindex_12 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2715 = remapindex_12 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2716 = remapindex_12 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2717 = remapindex_12 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2718 = remapindex_12 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2719 = remapindex_12 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2720 = remapindex_12 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2721 = remapindex_12 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2722 = remapindex_12 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2723 = remapindex_12 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2724 = remapindex_12 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2725 = remapindex_12 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2726 = remapindex_12 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2727 = remapindex_12 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2728 = remapindex_12 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2729 = remapindex_12 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2730 = remapindex_12 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2731 = remapindex_12 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2732 = remapindex_12 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2733 = remapindex_12 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2734 = remapindex_12 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2735 = remapindex_12 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2736 = remapindex_12 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2737 = remapindex_12 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2738 = remapindex_12 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2739 = remapindex_12 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2740 = remapindex_12 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2741 = remapindex_12 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2742 = remapindex_12 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2743 = remapindex_12 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2744 = remapindex_12 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2745 = remapindex_12 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_12 = _T_2745 ? _Queue64_UInt8_31_io_deq_bits : _T_2744 ? _Queue64_UInt8_30_io_deq_bits : _T_2743 ? _Queue64_UInt8_29_io_deq_bits : _T_2742 ? _Queue64_UInt8_28_io_deq_bits : _T_2741 ? _Queue64_UInt8_27_io_deq_bits : _T_2740 ? _Queue64_UInt8_26_io_deq_bits : _T_2739 ? _Queue64_UInt8_25_io_deq_bits : _T_2738 ? _Queue64_UInt8_24_io_deq_bits : _T_2737 ? _Queue64_UInt8_23_io_deq_bits : _T_2736 ? _Queue64_UInt8_22_io_deq_bits : _T_2735 ? _Queue64_UInt8_21_io_deq_bits : _T_2734 ? _Queue64_UInt8_20_io_deq_bits : _T_2733 ? _Queue64_UInt8_19_io_deq_bits : _T_2732 ? _Queue64_UInt8_18_io_deq_bits : _T_2731 ? _Queue64_UInt8_17_io_deq_bits : _T_2730 ? _Queue64_UInt8_16_io_deq_bits : _T_2729 ? _Queue64_UInt8_15_io_deq_bits : _T_2728 ? _Queue64_UInt8_14_io_deq_bits : _T_2727 ? _Queue64_UInt8_13_io_deq_bits : _T_2726 ? _Queue64_UInt8_12_io_deq_bits : _T_2725 ? _Queue64_UInt8_11_io_deq_bits : _T_2724 ? _Queue64_UInt8_10_io_deq_bits : _T_2723 ? _Queue64_UInt8_9_io_deq_bits : _T_2722 ? _Queue64_UInt8_8_io_deq_bits : _T_2721 ? _Queue64_UInt8_7_io_deq_bits : _T_2720 ? _Queue64_UInt8_6_io_deq_bits : _T_2719 ? _Queue64_UInt8_5_io_deq_bits : _T_2718 ? _Queue64_UInt8_4_io_deq_bits : _T_2717 ? _Queue64_UInt8_3_io_deq_bits : _T_2716 ? _Queue64_UInt8_2_io_deq_bits : _T_2715 ? _Queue64_UInt8_1_io_deq_bits : _T_2714 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_12 = _T_2745 ? _Queue64_UInt8_31_io_deq_valid : _T_2744 ? _Queue64_UInt8_30_io_deq_valid : _T_2743 ? _Queue64_UInt8_29_io_deq_valid : _T_2742 ? _Queue64_UInt8_28_io_deq_valid : _T_2741 ? _Queue64_UInt8_27_io_deq_valid : _T_2740 ? _Queue64_UInt8_26_io_deq_valid : _T_2739 ? _Queue64_UInt8_25_io_deq_valid : _T_2738 ? _Queue64_UInt8_24_io_deq_valid : _T_2737 ? _Queue64_UInt8_23_io_deq_valid : _T_2736 ? _Queue64_UInt8_22_io_deq_valid : _T_2735 ? _Queue64_UInt8_21_io_deq_valid : _T_2734 ? _Queue64_UInt8_20_io_deq_valid : _T_2733 ? _Queue64_UInt8_19_io_deq_valid : _T_2732 ? _Queue64_UInt8_18_io_deq_valid : _T_2731 ? _Queue64_UInt8_17_io_deq_valid : _T_2730 ? _Queue64_UInt8_16_io_deq_valid : _T_2729 ? _Queue64_UInt8_15_io_deq_valid : _T_2728 ? _Queue64_UInt8_14_io_deq_valid : _T_2727 ? _Queue64_UInt8_13_io_deq_valid : _T_2726 ? _Queue64_UInt8_12_io_deq_valid : _T_2725 ? _Queue64_UInt8_11_io_deq_valid : _T_2724 ? _Queue64_UInt8_10_io_deq_valid : _T_2723 ? _Queue64_UInt8_9_io_deq_valid : _T_2722 ? _Queue64_UInt8_8_io_deq_valid : _T_2721 ? _Queue64_UInt8_7_io_deq_valid : _T_2720 ? _Queue64_UInt8_6_io_deq_valid : _T_2719 ? _Queue64_UInt8_5_io_deq_valid : _T_2718 ? _Queue64_UInt8_4_io_deq_valid : _T_2717 ? _Queue64_UInt8_3_io_deq_valid : _T_2716 ? _Queue64_UInt8_2_io_deq_valid : _T_2715 ? _Queue64_UInt8_1_io_deq_valid : _T_2714 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_13 = _remapindex_T + 7'hD; // @[MemLoader.scala:177:33] wire [6:0] _GEN_104 = _remapindex_T_13 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_13 = _GEN_104[5:0]; // @[MemLoader.scala:177:54] wire _T_2746 = remapindex_13 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2747 = remapindex_13 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2748 = remapindex_13 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2749 = remapindex_13 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2750 = remapindex_13 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2751 = remapindex_13 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2752 = remapindex_13 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2753 = remapindex_13 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2754 = remapindex_13 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2755 = remapindex_13 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2756 = remapindex_13 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2757 = remapindex_13 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2758 = remapindex_13 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2759 = remapindex_13 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2760 = remapindex_13 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2761 = remapindex_13 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2762 = remapindex_13 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2763 = remapindex_13 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2764 = remapindex_13 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2765 = remapindex_13 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2766 = remapindex_13 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2767 = remapindex_13 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2768 = remapindex_13 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2769 = remapindex_13 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2770 = remapindex_13 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2771 = remapindex_13 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2772 = remapindex_13 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2773 = remapindex_13 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2774 = remapindex_13 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2775 = remapindex_13 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2776 = remapindex_13 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2777 = remapindex_13 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_13 = _T_2777 ? _Queue64_UInt8_31_io_deq_bits : _T_2776 ? _Queue64_UInt8_30_io_deq_bits : _T_2775 ? _Queue64_UInt8_29_io_deq_bits : _T_2774 ? _Queue64_UInt8_28_io_deq_bits : _T_2773 ? _Queue64_UInt8_27_io_deq_bits : _T_2772 ? _Queue64_UInt8_26_io_deq_bits : _T_2771 ? _Queue64_UInt8_25_io_deq_bits : _T_2770 ? _Queue64_UInt8_24_io_deq_bits : _T_2769 ? _Queue64_UInt8_23_io_deq_bits : _T_2768 ? _Queue64_UInt8_22_io_deq_bits : _T_2767 ? _Queue64_UInt8_21_io_deq_bits : _T_2766 ? _Queue64_UInt8_20_io_deq_bits : _T_2765 ? _Queue64_UInt8_19_io_deq_bits : _T_2764 ? _Queue64_UInt8_18_io_deq_bits : _T_2763 ? _Queue64_UInt8_17_io_deq_bits : _T_2762 ? _Queue64_UInt8_16_io_deq_bits : _T_2761 ? _Queue64_UInt8_15_io_deq_bits : _T_2760 ? _Queue64_UInt8_14_io_deq_bits : _T_2759 ? _Queue64_UInt8_13_io_deq_bits : _T_2758 ? _Queue64_UInt8_12_io_deq_bits : _T_2757 ? _Queue64_UInt8_11_io_deq_bits : _T_2756 ? _Queue64_UInt8_10_io_deq_bits : _T_2755 ? _Queue64_UInt8_9_io_deq_bits : _T_2754 ? _Queue64_UInt8_8_io_deq_bits : _T_2753 ? _Queue64_UInt8_7_io_deq_bits : _T_2752 ? _Queue64_UInt8_6_io_deq_bits : _T_2751 ? _Queue64_UInt8_5_io_deq_bits : _T_2750 ? _Queue64_UInt8_4_io_deq_bits : _T_2749 ? _Queue64_UInt8_3_io_deq_bits : _T_2748 ? _Queue64_UInt8_2_io_deq_bits : _T_2747 ? _Queue64_UInt8_1_io_deq_bits : _T_2746 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_13 = _T_2777 ? _Queue64_UInt8_31_io_deq_valid : _T_2776 ? _Queue64_UInt8_30_io_deq_valid : _T_2775 ? _Queue64_UInt8_29_io_deq_valid : _T_2774 ? _Queue64_UInt8_28_io_deq_valid : _T_2773 ? _Queue64_UInt8_27_io_deq_valid : _T_2772 ? _Queue64_UInt8_26_io_deq_valid : _T_2771 ? _Queue64_UInt8_25_io_deq_valid : _T_2770 ? _Queue64_UInt8_24_io_deq_valid : _T_2769 ? _Queue64_UInt8_23_io_deq_valid : _T_2768 ? _Queue64_UInt8_22_io_deq_valid : _T_2767 ? _Queue64_UInt8_21_io_deq_valid : _T_2766 ? _Queue64_UInt8_20_io_deq_valid : _T_2765 ? _Queue64_UInt8_19_io_deq_valid : _T_2764 ? _Queue64_UInt8_18_io_deq_valid : _T_2763 ? _Queue64_UInt8_17_io_deq_valid : _T_2762 ? _Queue64_UInt8_16_io_deq_valid : _T_2761 ? _Queue64_UInt8_15_io_deq_valid : _T_2760 ? _Queue64_UInt8_14_io_deq_valid : _T_2759 ? _Queue64_UInt8_13_io_deq_valid : _T_2758 ? _Queue64_UInt8_12_io_deq_valid : _T_2757 ? _Queue64_UInt8_11_io_deq_valid : _T_2756 ? _Queue64_UInt8_10_io_deq_valid : _T_2755 ? _Queue64_UInt8_9_io_deq_valid : _T_2754 ? _Queue64_UInt8_8_io_deq_valid : _T_2753 ? _Queue64_UInt8_7_io_deq_valid : _T_2752 ? _Queue64_UInt8_6_io_deq_valid : _T_2751 ? _Queue64_UInt8_5_io_deq_valid : _T_2750 ? _Queue64_UInt8_4_io_deq_valid : _T_2749 ? _Queue64_UInt8_3_io_deq_valid : _T_2748 ? _Queue64_UInt8_2_io_deq_valid : _T_2747 ? _Queue64_UInt8_1_io_deq_valid : _T_2746 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_14 = _remapindex_T + 7'hE; // @[MemLoader.scala:177:33] wire [6:0] _GEN_105 = _remapindex_T_14 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_14 = _GEN_105[5:0]; // @[MemLoader.scala:177:54] wire _T_2778 = remapindex_14 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2779 = remapindex_14 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2780 = remapindex_14 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2781 = remapindex_14 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2782 = remapindex_14 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2783 = remapindex_14 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2784 = remapindex_14 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2785 = remapindex_14 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2786 = remapindex_14 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2787 = remapindex_14 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2788 = remapindex_14 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2789 = remapindex_14 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2790 = remapindex_14 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2791 = remapindex_14 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2792 = remapindex_14 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2793 = remapindex_14 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2794 = remapindex_14 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2795 = remapindex_14 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2796 = remapindex_14 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2797 = remapindex_14 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2798 = remapindex_14 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2799 = remapindex_14 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2800 = remapindex_14 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2801 = remapindex_14 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2802 = remapindex_14 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2803 = remapindex_14 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2804 = remapindex_14 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2805 = remapindex_14 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2806 = remapindex_14 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2807 = remapindex_14 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2808 = remapindex_14 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2809 = remapindex_14 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_14 = _T_2809 ? _Queue64_UInt8_31_io_deq_bits : _T_2808 ? _Queue64_UInt8_30_io_deq_bits : _T_2807 ? _Queue64_UInt8_29_io_deq_bits : _T_2806 ? _Queue64_UInt8_28_io_deq_bits : _T_2805 ? _Queue64_UInt8_27_io_deq_bits : _T_2804 ? _Queue64_UInt8_26_io_deq_bits : _T_2803 ? _Queue64_UInt8_25_io_deq_bits : _T_2802 ? _Queue64_UInt8_24_io_deq_bits : _T_2801 ? _Queue64_UInt8_23_io_deq_bits : _T_2800 ? _Queue64_UInt8_22_io_deq_bits : _T_2799 ? _Queue64_UInt8_21_io_deq_bits : _T_2798 ? _Queue64_UInt8_20_io_deq_bits : _T_2797 ? _Queue64_UInt8_19_io_deq_bits : _T_2796 ? _Queue64_UInt8_18_io_deq_bits : _T_2795 ? _Queue64_UInt8_17_io_deq_bits : _T_2794 ? _Queue64_UInt8_16_io_deq_bits : _T_2793 ? _Queue64_UInt8_15_io_deq_bits : _T_2792 ? _Queue64_UInt8_14_io_deq_bits : _T_2791 ? _Queue64_UInt8_13_io_deq_bits : _T_2790 ? _Queue64_UInt8_12_io_deq_bits : _T_2789 ? _Queue64_UInt8_11_io_deq_bits : _T_2788 ? _Queue64_UInt8_10_io_deq_bits : _T_2787 ? _Queue64_UInt8_9_io_deq_bits : _T_2786 ? _Queue64_UInt8_8_io_deq_bits : _T_2785 ? _Queue64_UInt8_7_io_deq_bits : _T_2784 ? _Queue64_UInt8_6_io_deq_bits : _T_2783 ? _Queue64_UInt8_5_io_deq_bits : _T_2782 ? _Queue64_UInt8_4_io_deq_bits : _T_2781 ? _Queue64_UInt8_3_io_deq_bits : _T_2780 ? _Queue64_UInt8_2_io_deq_bits : _T_2779 ? _Queue64_UInt8_1_io_deq_bits : _T_2778 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_14 = _T_2809 ? _Queue64_UInt8_31_io_deq_valid : _T_2808 ? _Queue64_UInt8_30_io_deq_valid : _T_2807 ? _Queue64_UInt8_29_io_deq_valid : _T_2806 ? _Queue64_UInt8_28_io_deq_valid : _T_2805 ? _Queue64_UInt8_27_io_deq_valid : _T_2804 ? _Queue64_UInt8_26_io_deq_valid : _T_2803 ? _Queue64_UInt8_25_io_deq_valid : _T_2802 ? _Queue64_UInt8_24_io_deq_valid : _T_2801 ? _Queue64_UInt8_23_io_deq_valid : _T_2800 ? _Queue64_UInt8_22_io_deq_valid : _T_2799 ? _Queue64_UInt8_21_io_deq_valid : _T_2798 ? _Queue64_UInt8_20_io_deq_valid : _T_2797 ? _Queue64_UInt8_19_io_deq_valid : _T_2796 ? _Queue64_UInt8_18_io_deq_valid : _T_2795 ? _Queue64_UInt8_17_io_deq_valid : _T_2794 ? _Queue64_UInt8_16_io_deq_valid : _T_2793 ? _Queue64_UInt8_15_io_deq_valid : _T_2792 ? _Queue64_UInt8_14_io_deq_valid : _T_2791 ? _Queue64_UInt8_13_io_deq_valid : _T_2790 ? _Queue64_UInt8_12_io_deq_valid : _T_2789 ? _Queue64_UInt8_11_io_deq_valid : _T_2788 ? _Queue64_UInt8_10_io_deq_valid : _T_2787 ? _Queue64_UInt8_9_io_deq_valid : _T_2786 ? _Queue64_UInt8_8_io_deq_valid : _T_2785 ? _Queue64_UInt8_7_io_deq_valid : _T_2784 ? _Queue64_UInt8_6_io_deq_valid : _T_2783 ? _Queue64_UInt8_5_io_deq_valid : _T_2782 ? _Queue64_UInt8_4_io_deq_valid : _T_2781 ? _Queue64_UInt8_3_io_deq_valid : _T_2780 ? _Queue64_UInt8_2_io_deq_valid : _T_2779 ? _Queue64_UInt8_1_io_deq_valid : _T_2778 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_15 = _remapindex_T + 7'hF; // @[MemLoader.scala:177:33] wire [6:0] _GEN_106 = _remapindex_T_15 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_15 = _GEN_106[5:0]; // @[MemLoader.scala:177:54] wire _T_2810 = remapindex_15 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2811 = remapindex_15 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2812 = remapindex_15 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2813 = remapindex_15 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2814 = remapindex_15 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2815 = remapindex_15 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2816 = remapindex_15 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2817 = remapindex_15 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2818 = remapindex_15 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2819 = remapindex_15 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2820 = remapindex_15 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2821 = remapindex_15 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2822 = remapindex_15 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2823 = remapindex_15 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2824 = remapindex_15 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2825 = remapindex_15 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2826 = remapindex_15 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2827 = remapindex_15 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2828 = remapindex_15 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2829 = remapindex_15 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2830 = remapindex_15 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2831 = remapindex_15 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2832 = remapindex_15 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2833 = remapindex_15 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2834 = remapindex_15 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2835 = remapindex_15 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2836 = remapindex_15 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2837 = remapindex_15 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2838 = remapindex_15 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2839 = remapindex_15 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2840 = remapindex_15 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2841 = remapindex_15 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_15 = _T_2841 ? _Queue64_UInt8_31_io_deq_bits : _T_2840 ? _Queue64_UInt8_30_io_deq_bits : _T_2839 ? _Queue64_UInt8_29_io_deq_bits : _T_2838 ? _Queue64_UInt8_28_io_deq_bits : _T_2837 ? _Queue64_UInt8_27_io_deq_bits : _T_2836 ? _Queue64_UInt8_26_io_deq_bits : _T_2835 ? _Queue64_UInt8_25_io_deq_bits : _T_2834 ? _Queue64_UInt8_24_io_deq_bits : _T_2833 ? _Queue64_UInt8_23_io_deq_bits : _T_2832 ? _Queue64_UInt8_22_io_deq_bits : _T_2831 ? _Queue64_UInt8_21_io_deq_bits : _T_2830 ? _Queue64_UInt8_20_io_deq_bits : _T_2829 ? _Queue64_UInt8_19_io_deq_bits : _T_2828 ? _Queue64_UInt8_18_io_deq_bits : _T_2827 ? _Queue64_UInt8_17_io_deq_bits : _T_2826 ? _Queue64_UInt8_16_io_deq_bits : _T_2825 ? _Queue64_UInt8_15_io_deq_bits : _T_2824 ? _Queue64_UInt8_14_io_deq_bits : _T_2823 ? _Queue64_UInt8_13_io_deq_bits : _T_2822 ? _Queue64_UInt8_12_io_deq_bits : _T_2821 ? _Queue64_UInt8_11_io_deq_bits : _T_2820 ? _Queue64_UInt8_10_io_deq_bits : _T_2819 ? _Queue64_UInt8_9_io_deq_bits : _T_2818 ? _Queue64_UInt8_8_io_deq_bits : _T_2817 ? _Queue64_UInt8_7_io_deq_bits : _T_2816 ? _Queue64_UInt8_6_io_deq_bits : _T_2815 ? _Queue64_UInt8_5_io_deq_bits : _T_2814 ? _Queue64_UInt8_4_io_deq_bits : _T_2813 ? _Queue64_UInt8_3_io_deq_bits : _T_2812 ? _Queue64_UInt8_2_io_deq_bits : _T_2811 ? _Queue64_UInt8_1_io_deq_bits : _T_2810 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_15 = _T_2841 ? _Queue64_UInt8_31_io_deq_valid : _T_2840 ? _Queue64_UInt8_30_io_deq_valid : _T_2839 ? _Queue64_UInt8_29_io_deq_valid : _T_2838 ? _Queue64_UInt8_28_io_deq_valid : _T_2837 ? _Queue64_UInt8_27_io_deq_valid : _T_2836 ? _Queue64_UInt8_26_io_deq_valid : _T_2835 ? _Queue64_UInt8_25_io_deq_valid : _T_2834 ? _Queue64_UInt8_24_io_deq_valid : _T_2833 ? _Queue64_UInt8_23_io_deq_valid : _T_2832 ? _Queue64_UInt8_22_io_deq_valid : _T_2831 ? _Queue64_UInt8_21_io_deq_valid : _T_2830 ? _Queue64_UInt8_20_io_deq_valid : _T_2829 ? _Queue64_UInt8_19_io_deq_valid : _T_2828 ? _Queue64_UInt8_18_io_deq_valid : _T_2827 ? _Queue64_UInt8_17_io_deq_valid : _T_2826 ? _Queue64_UInt8_16_io_deq_valid : _T_2825 ? _Queue64_UInt8_15_io_deq_valid : _T_2824 ? _Queue64_UInt8_14_io_deq_valid : _T_2823 ? _Queue64_UInt8_13_io_deq_valid : _T_2822 ? _Queue64_UInt8_12_io_deq_valid : _T_2821 ? _Queue64_UInt8_11_io_deq_valid : _T_2820 ? _Queue64_UInt8_10_io_deq_valid : _T_2819 ? _Queue64_UInt8_9_io_deq_valid : _T_2818 ? _Queue64_UInt8_8_io_deq_valid : _T_2817 ? _Queue64_UInt8_7_io_deq_valid : _T_2816 ? _Queue64_UInt8_6_io_deq_valid : _T_2815 ? _Queue64_UInt8_5_io_deq_valid : _T_2814 ? _Queue64_UInt8_4_io_deq_valid : _T_2813 ? _Queue64_UInt8_3_io_deq_valid : _T_2812 ? _Queue64_UInt8_2_io_deq_valid : _T_2811 ? _Queue64_UInt8_1_io_deq_valid : _T_2810 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_16 = _remapindex_T + 7'h10; // @[MemLoader.scala:177:33] wire [6:0] _GEN_107 = _remapindex_T_16 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_16 = _GEN_107[5:0]; // @[MemLoader.scala:177:54] wire _T_2842 = remapindex_16 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2843 = remapindex_16 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2844 = remapindex_16 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2845 = remapindex_16 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2846 = remapindex_16 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2847 = remapindex_16 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2848 = remapindex_16 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2849 = remapindex_16 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2850 = remapindex_16 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2851 = remapindex_16 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2852 = remapindex_16 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2853 = remapindex_16 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2854 = remapindex_16 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2855 = remapindex_16 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2856 = remapindex_16 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2857 = remapindex_16 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2858 = remapindex_16 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2859 = remapindex_16 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2860 = remapindex_16 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2861 = remapindex_16 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2862 = remapindex_16 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2863 = remapindex_16 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2864 = remapindex_16 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2865 = remapindex_16 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2866 = remapindex_16 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2867 = remapindex_16 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2868 = remapindex_16 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2869 = remapindex_16 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2870 = remapindex_16 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2871 = remapindex_16 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2872 = remapindex_16 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2873 = remapindex_16 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_16 = _T_2873 ? _Queue64_UInt8_31_io_deq_bits : _T_2872 ? _Queue64_UInt8_30_io_deq_bits : _T_2871 ? _Queue64_UInt8_29_io_deq_bits : _T_2870 ? _Queue64_UInt8_28_io_deq_bits : _T_2869 ? _Queue64_UInt8_27_io_deq_bits : _T_2868 ? _Queue64_UInt8_26_io_deq_bits : _T_2867 ? _Queue64_UInt8_25_io_deq_bits : _T_2866 ? _Queue64_UInt8_24_io_deq_bits : _T_2865 ? _Queue64_UInt8_23_io_deq_bits : _T_2864 ? _Queue64_UInt8_22_io_deq_bits : _T_2863 ? _Queue64_UInt8_21_io_deq_bits : _T_2862 ? _Queue64_UInt8_20_io_deq_bits : _T_2861 ? _Queue64_UInt8_19_io_deq_bits : _T_2860 ? _Queue64_UInt8_18_io_deq_bits : _T_2859 ? _Queue64_UInt8_17_io_deq_bits : _T_2858 ? _Queue64_UInt8_16_io_deq_bits : _T_2857 ? _Queue64_UInt8_15_io_deq_bits : _T_2856 ? _Queue64_UInt8_14_io_deq_bits : _T_2855 ? _Queue64_UInt8_13_io_deq_bits : _T_2854 ? _Queue64_UInt8_12_io_deq_bits : _T_2853 ? _Queue64_UInt8_11_io_deq_bits : _T_2852 ? _Queue64_UInt8_10_io_deq_bits : _T_2851 ? _Queue64_UInt8_9_io_deq_bits : _T_2850 ? _Queue64_UInt8_8_io_deq_bits : _T_2849 ? _Queue64_UInt8_7_io_deq_bits : _T_2848 ? _Queue64_UInt8_6_io_deq_bits : _T_2847 ? _Queue64_UInt8_5_io_deq_bits : _T_2846 ? _Queue64_UInt8_4_io_deq_bits : _T_2845 ? _Queue64_UInt8_3_io_deq_bits : _T_2844 ? _Queue64_UInt8_2_io_deq_bits : _T_2843 ? _Queue64_UInt8_1_io_deq_bits : _T_2842 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_16 = _T_2873 ? _Queue64_UInt8_31_io_deq_valid : _T_2872 ? _Queue64_UInt8_30_io_deq_valid : _T_2871 ? _Queue64_UInt8_29_io_deq_valid : _T_2870 ? _Queue64_UInt8_28_io_deq_valid : _T_2869 ? _Queue64_UInt8_27_io_deq_valid : _T_2868 ? _Queue64_UInt8_26_io_deq_valid : _T_2867 ? _Queue64_UInt8_25_io_deq_valid : _T_2866 ? _Queue64_UInt8_24_io_deq_valid : _T_2865 ? _Queue64_UInt8_23_io_deq_valid : _T_2864 ? _Queue64_UInt8_22_io_deq_valid : _T_2863 ? _Queue64_UInt8_21_io_deq_valid : _T_2862 ? _Queue64_UInt8_20_io_deq_valid : _T_2861 ? _Queue64_UInt8_19_io_deq_valid : _T_2860 ? _Queue64_UInt8_18_io_deq_valid : _T_2859 ? _Queue64_UInt8_17_io_deq_valid : _T_2858 ? _Queue64_UInt8_16_io_deq_valid : _T_2857 ? _Queue64_UInt8_15_io_deq_valid : _T_2856 ? _Queue64_UInt8_14_io_deq_valid : _T_2855 ? _Queue64_UInt8_13_io_deq_valid : _T_2854 ? _Queue64_UInt8_12_io_deq_valid : _T_2853 ? _Queue64_UInt8_11_io_deq_valid : _T_2852 ? _Queue64_UInt8_10_io_deq_valid : _T_2851 ? _Queue64_UInt8_9_io_deq_valid : _T_2850 ? _Queue64_UInt8_8_io_deq_valid : _T_2849 ? _Queue64_UInt8_7_io_deq_valid : _T_2848 ? _Queue64_UInt8_6_io_deq_valid : _T_2847 ? _Queue64_UInt8_5_io_deq_valid : _T_2846 ? _Queue64_UInt8_4_io_deq_valid : _T_2845 ? _Queue64_UInt8_3_io_deq_valid : _T_2844 ? _Queue64_UInt8_2_io_deq_valid : _T_2843 ? _Queue64_UInt8_1_io_deq_valid : _T_2842 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_17 = _remapindex_T + 7'h11; // @[MemLoader.scala:177:33] wire [6:0] _GEN_108 = _remapindex_T_17 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_17 = _GEN_108[5:0]; // @[MemLoader.scala:177:54] wire _T_2874 = remapindex_17 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2875 = remapindex_17 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2876 = remapindex_17 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2877 = remapindex_17 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2878 = remapindex_17 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2879 = remapindex_17 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2880 = remapindex_17 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2881 = remapindex_17 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2882 = remapindex_17 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2883 = remapindex_17 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2884 = remapindex_17 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2885 = remapindex_17 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2886 = remapindex_17 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2887 = remapindex_17 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2888 = remapindex_17 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2889 = remapindex_17 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2890 = remapindex_17 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2891 = remapindex_17 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2892 = remapindex_17 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2893 = remapindex_17 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2894 = remapindex_17 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2895 = remapindex_17 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2896 = remapindex_17 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2897 = remapindex_17 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2898 = remapindex_17 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2899 = remapindex_17 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2900 = remapindex_17 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2901 = remapindex_17 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2902 = remapindex_17 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2903 = remapindex_17 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2904 = remapindex_17 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2905 = remapindex_17 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_17 = _T_2905 ? _Queue64_UInt8_31_io_deq_bits : _T_2904 ? _Queue64_UInt8_30_io_deq_bits : _T_2903 ? _Queue64_UInt8_29_io_deq_bits : _T_2902 ? _Queue64_UInt8_28_io_deq_bits : _T_2901 ? _Queue64_UInt8_27_io_deq_bits : _T_2900 ? _Queue64_UInt8_26_io_deq_bits : _T_2899 ? _Queue64_UInt8_25_io_deq_bits : _T_2898 ? _Queue64_UInt8_24_io_deq_bits : _T_2897 ? _Queue64_UInt8_23_io_deq_bits : _T_2896 ? _Queue64_UInt8_22_io_deq_bits : _T_2895 ? _Queue64_UInt8_21_io_deq_bits : _T_2894 ? _Queue64_UInt8_20_io_deq_bits : _T_2893 ? _Queue64_UInt8_19_io_deq_bits : _T_2892 ? _Queue64_UInt8_18_io_deq_bits : _T_2891 ? _Queue64_UInt8_17_io_deq_bits : _T_2890 ? _Queue64_UInt8_16_io_deq_bits : _T_2889 ? _Queue64_UInt8_15_io_deq_bits : _T_2888 ? _Queue64_UInt8_14_io_deq_bits : _T_2887 ? _Queue64_UInt8_13_io_deq_bits : _T_2886 ? _Queue64_UInt8_12_io_deq_bits : _T_2885 ? _Queue64_UInt8_11_io_deq_bits : _T_2884 ? _Queue64_UInt8_10_io_deq_bits : _T_2883 ? _Queue64_UInt8_9_io_deq_bits : _T_2882 ? _Queue64_UInt8_8_io_deq_bits : _T_2881 ? _Queue64_UInt8_7_io_deq_bits : _T_2880 ? _Queue64_UInt8_6_io_deq_bits : _T_2879 ? _Queue64_UInt8_5_io_deq_bits : _T_2878 ? _Queue64_UInt8_4_io_deq_bits : _T_2877 ? _Queue64_UInt8_3_io_deq_bits : _T_2876 ? _Queue64_UInt8_2_io_deq_bits : _T_2875 ? _Queue64_UInt8_1_io_deq_bits : _T_2874 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_17 = _T_2905 ? _Queue64_UInt8_31_io_deq_valid : _T_2904 ? _Queue64_UInt8_30_io_deq_valid : _T_2903 ? _Queue64_UInt8_29_io_deq_valid : _T_2902 ? _Queue64_UInt8_28_io_deq_valid : _T_2901 ? _Queue64_UInt8_27_io_deq_valid : _T_2900 ? _Queue64_UInt8_26_io_deq_valid : _T_2899 ? _Queue64_UInt8_25_io_deq_valid : _T_2898 ? _Queue64_UInt8_24_io_deq_valid : _T_2897 ? _Queue64_UInt8_23_io_deq_valid : _T_2896 ? _Queue64_UInt8_22_io_deq_valid : _T_2895 ? _Queue64_UInt8_21_io_deq_valid : _T_2894 ? _Queue64_UInt8_20_io_deq_valid : _T_2893 ? _Queue64_UInt8_19_io_deq_valid : _T_2892 ? _Queue64_UInt8_18_io_deq_valid : _T_2891 ? _Queue64_UInt8_17_io_deq_valid : _T_2890 ? _Queue64_UInt8_16_io_deq_valid : _T_2889 ? _Queue64_UInt8_15_io_deq_valid : _T_2888 ? _Queue64_UInt8_14_io_deq_valid : _T_2887 ? _Queue64_UInt8_13_io_deq_valid : _T_2886 ? _Queue64_UInt8_12_io_deq_valid : _T_2885 ? _Queue64_UInt8_11_io_deq_valid : _T_2884 ? _Queue64_UInt8_10_io_deq_valid : _T_2883 ? _Queue64_UInt8_9_io_deq_valid : _T_2882 ? _Queue64_UInt8_8_io_deq_valid : _T_2881 ? _Queue64_UInt8_7_io_deq_valid : _T_2880 ? _Queue64_UInt8_6_io_deq_valid : _T_2879 ? _Queue64_UInt8_5_io_deq_valid : _T_2878 ? _Queue64_UInt8_4_io_deq_valid : _T_2877 ? _Queue64_UInt8_3_io_deq_valid : _T_2876 ? _Queue64_UInt8_2_io_deq_valid : _T_2875 ? _Queue64_UInt8_1_io_deq_valid : _T_2874 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_18 = _remapindex_T + 7'h12; // @[MemLoader.scala:177:33] wire [6:0] _GEN_109 = _remapindex_T_18 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_18 = _GEN_109[5:0]; // @[MemLoader.scala:177:54] wire _T_2906 = remapindex_18 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2907 = remapindex_18 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2908 = remapindex_18 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2909 = remapindex_18 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2910 = remapindex_18 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2911 = remapindex_18 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2912 = remapindex_18 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2913 = remapindex_18 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2914 = remapindex_18 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2915 = remapindex_18 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2916 = remapindex_18 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2917 = remapindex_18 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2918 = remapindex_18 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2919 = remapindex_18 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2920 = remapindex_18 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2921 = remapindex_18 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2922 = remapindex_18 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2923 = remapindex_18 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2924 = remapindex_18 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2925 = remapindex_18 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2926 = remapindex_18 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2927 = remapindex_18 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2928 = remapindex_18 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2929 = remapindex_18 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2930 = remapindex_18 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2931 = remapindex_18 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2932 = remapindex_18 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2933 = remapindex_18 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2934 = remapindex_18 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2935 = remapindex_18 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2936 = remapindex_18 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2937 = remapindex_18 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_18 = _T_2937 ? _Queue64_UInt8_31_io_deq_bits : _T_2936 ? _Queue64_UInt8_30_io_deq_bits : _T_2935 ? _Queue64_UInt8_29_io_deq_bits : _T_2934 ? _Queue64_UInt8_28_io_deq_bits : _T_2933 ? _Queue64_UInt8_27_io_deq_bits : _T_2932 ? _Queue64_UInt8_26_io_deq_bits : _T_2931 ? _Queue64_UInt8_25_io_deq_bits : _T_2930 ? _Queue64_UInt8_24_io_deq_bits : _T_2929 ? _Queue64_UInt8_23_io_deq_bits : _T_2928 ? _Queue64_UInt8_22_io_deq_bits : _T_2927 ? _Queue64_UInt8_21_io_deq_bits : _T_2926 ? _Queue64_UInt8_20_io_deq_bits : _T_2925 ? _Queue64_UInt8_19_io_deq_bits : _T_2924 ? _Queue64_UInt8_18_io_deq_bits : _T_2923 ? _Queue64_UInt8_17_io_deq_bits : _T_2922 ? _Queue64_UInt8_16_io_deq_bits : _T_2921 ? _Queue64_UInt8_15_io_deq_bits : _T_2920 ? _Queue64_UInt8_14_io_deq_bits : _T_2919 ? _Queue64_UInt8_13_io_deq_bits : _T_2918 ? _Queue64_UInt8_12_io_deq_bits : _T_2917 ? _Queue64_UInt8_11_io_deq_bits : _T_2916 ? _Queue64_UInt8_10_io_deq_bits : _T_2915 ? _Queue64_UInt8_9_io_deq_bits : _T_2914 ? _Queue64_UInt8_8_io_deq_bits : _T_2913 ? _Queue64_UInt8_7_io_deq_bits : _T_2912 ? _Queue64_UInt8_6_io_deq_bits : _T_2911 ? _Queue64_UInt8_5_io_deq_bits : _T_2910 ? _Queue64_UInt8_4_io_deq_bits : _T_2909 ? _Queue64_UInt8_3_io_deq_bits : _T_2908 ? _Queue64_UInt8_2_io_deq_bits : _T_2907 ? _Queue64_UInt8_1_io_deq_bits : _T_2906 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_18 = _T_2937 ? _Queue64_UInt8_31_io_deq_valid : _T_2936 ? _Queue64_UInt8_30_io_deq_valid : _T_2935 ? _Queue64_UInt8_29_io_deq_valid : _T_2934 ? _Queue64_UInt8_28_io_deq_valid : _T_2933 ? _Queue64_UInt8_27_io_deq_valid : _T_2932 ? _Queue64_UInt8_26_io_deq_valid : _T_2931 ? _Queue64_UInt8_25_io_deq_valid : _T_2930 ? _Queue64_UInt8_24_io_deq_valid : _T_2929 ? _Queue64_UInt8_23_io_deq_valid : _T_2928 ? _Queue64_UInt8_22_io_deq_valid : _T_2927 ? _Queue64_UInt8_21_io_deq_valid : _T_2926 ? _Queue64_UInt8_20_io_deq_valid : _T_2925 ? _Queue64_UInt8_19_io_deq_valid : _T_2924 ? _Queue64_UInt8_18_io_deq_valid : _T_2923 ? _Queue64_UInt8_17_io_deq_valid : _T_2922 ? _Queue64_UInt8_16_io_deq_valid : _T_2921 ? _Queue64_UInt8_15_io_deq_valid : _T_2920 ? _Queue64_UInt8_14_io_deq_valid : _T_2919 ? _Queue64_UInt8_13_io_deq_valid : _T_2918 ? _Queue64_UInt8_12_io_deq_valid : _T_2917 ? _Queue64_UInt8_11_io_deq_valid : _T_2916 ? _Queue64_UInt8_10_io_deq_valid : _T_2915 ? _Queue64_UInt8_9_io_deq_valid : _T_2914 ? _Queue64_UInt8_8_io_deq_valid : _T_2913 ? _Queue64_UInt8_7_io_deq_valid : _T_2912 ? _Queue64_UInt8_6_io_deq_valid : _T_2911 ? _Queue64_UInt8_5_io_deq_valid : _T_2910 ? _Queue64_UInt8_4_io_deq_valid : _T_2909 ? _Queue64_UInt8_3_io_deq_valid : _T_2908 ? _Queue64_UInt8_2_io_deq_valid : _T_2907 ? _Queue64_UInt8_1_io_deq_valid : _T_2906 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_19 = _remapindex_T + 7'h13; // @[MemLoader.scala:177:33] wire [6:0] _GEN_110 = _remapindex_T_19 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_19 = _GEN_110[5:0]; // @[MemLoader.scala:177:54] wire _T_2938 = remapindex_19 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2939 = remapindex_19 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2940 = remapindex_19 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2941 = remapindex_19 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2942 = remapindex_19 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2943 = remapindex_19 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2944 = remapindex_19 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2945 = remapindex_19 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2946 = remapindex_19 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2947 = remapindex_19 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2948 = remapindex_19 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2949 = remapindex_19 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2950 = remapindex_19 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2951 = remapindex_19 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2952 = remapindex_19 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2953 = remapindex_19 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2954 = remapindex_19 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2955 = remapindex_19 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2956 = remapindex_19 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2957 = remapindex_19 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2958 = remapindex_19 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2959 = remapindex_19 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2960 = remapindex_19 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2961 = remapindex_19 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2962 = remapindex_19 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2963 = remapindex_19 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2964 = remapindex_19 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2965 = remapindex_19 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2966 = remapindex_19 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2967 = remapindex_19 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_2968 = remapindex_19 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_2969 = remapindex_19 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_19 = _T_2969 ? _Queue64_UInt8_31_io_deq_bits : _T_2968 ? _Queue64_UInt8_30_io_deq_bits : _T_2967 ? _Queue64_UInt8_29_io_deq_bits : _T_2966 ? _Queue64_UInt8_28_io_deq_bits : _T_2965 ? _Queue64_UInt8_27_io_deq_bits : _T_2964 ? _Queue64_UInt8_26_io_deq_bits : _T_2963 ? _Queue64_UInt8_25_io_deq_bits : _T_2962 ? _Queue64_UInt8_24_io_deq_bits : _T_2961 ? _Queue64_UInt8_23_io_deq_bits : _T_2960 ? _Queue64_UInt8_22_io_deq_bits : _T_2959 ? _Queue64_UInt8_21_io_deq_bits : _T_2958 ? _Queue64_UInt8_20_io_deq_bits : _T_2957 ? _Queue64_UInt8_19_io_deq_bits : _T_2956 ? _Queue64_UInt8_18_io_deq_bits : _T_2955 ? _Queue64_UInt8_17_io_deq_bits : _T_2954 ? _Queue64_UInt8_16_io_deq_bits : _T_2953 ? _Queue64_UInt8_15_io_deq_bits : _T_2952 ? _Queue64_UInt8_14_io_deq_bits : _T_2951 ? _Queue64_UInt8_13_io_deq_bits : _T_2950 ? _Queue64_UInt8_12_io_deq_bits : _T_2949 ? _Queue64_UInt8_11_io_deq_bits : _T_2948 ? _Queue64_UInt8_10_io_deq_bits : _T_2947 ? _Queue64_UInt8_9_io_deq_bits : _T_2946 ? _Queue64_UInt8_8_io_deq_bits : _T_2945 ? _Queue64_UInt8_7_io_deq_bits : _T_2944 ? _Queue64_UInt8_6_io_deq_bits : _T_2943 ? _Queue64_UInt8_5_io_deq_bits : _T_2942 ? _Queue64_UInt8_4_io_deq_bits : _T_2941 ? _Queue64_UInt8_3_io_deq_bits : _T_2940 ? _Queue64_UInt8_2_io_deq_bits : _T_2939 ? _Queue64_UInt8_1_io_deq_bits : _T_2938 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_19 = _T_2969 ? _Queue64_UInt8_31_io_deq_valid : _T_2968 ? _Queue64_UInt8_30_io_deq_valid : _T_2967 ? _Queue64_UInt8_29_io_deq_valid : _T_2966 ? _Queue64_UInt8_28_io_deq_valid : _T_2965 ? _Queue64_UInt8_27_io_deq_valid : _T_2964 ? _Queue64_UInt8_26_io_deq_valid : _T_2963 ? _Queue64_UInt8_25_io_deq_valid : _T_2962 ? _Queue64_UInt8_24_io_deq_valid : _T_2961 ? _Queue64_UInt8_23_io_deq_valid : _T_2960 ? _Queue64_UInt8_22_io_deq_valid : _T_2959 ? _Queue64_UInt8_21_io_deq_valid : _T_2958 ? _Queue64_UInt8_20_io_deq_valid : _T_2957 ? _Queue64_UInt8_19_io_deq_valid : _T_2956 ? _Queue64_UInt8_18_io_deq_valid : _T_2955 ? _Queue64_UInt8_17_io_deq_valid : _T_2954 ? _Queue64_UInt8_16_io_deq_valid : _T_2953 ? _Queue64_UInt8_15_io_deq_valid : _T_2952 ? _Queue64_UInt8_14_io_deq_valid : _T_2951 ? _Queue64_UInt8_13_io_deq_valid : _T_2950 ? _Queue64_UInt8_12_io_deq_valid : _T_2949 ? _Queue64_UInt8_11_io_deq_valid : _T_2948 ? _Queue64_UInt8_10_io_deq_valid : _T_2947 ? _Queue64_UInt8_9_io_deq_valid : _T_2946 ? _Queue64_UInt8_8_io_deq_valid : _T_2945 ? _Queue64_UInt8_7_io_deq_valid : _T_2944 ? _Queue64_UInt8_6_io_deq_valid : _T_2943 ? _Queue64_UInt8_5_io_deq_valid : _T_2942 ? _Queue64_UInt8_4_io_deq_valid : _T_2941 ? _Queue64_UInt8_3_io_deq_valid : _T_2940 ? _Queue64_UInt8_2_io_deq_valid : _T_2939 ? _Queue64_UInt8_1_io_deq_valid : _T_2938 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_20 = _remapindex_T + 7'h14; // @[MemLoader.scala:177:33] wire [6:0] _GEN_111 = _remapindex_T_20 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_20 = _GEN_111[5:0]; // @[MemLoader.scala:177:54] wire _T_2970 = remapindex_20 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_2971 = remapindex_20 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_2972 = remapindex_20 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_2973 = remapindex_20 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_2974 = remapindex_20 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_2975 = remapindex_20 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_2976 = remapindex_20 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_2977 = remapindex_20 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_2978 = remapindex_20 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_2979 = remapindex_20 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_2980 = remapindex_20 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_2981 = remapindex_20 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_2982 = remapindex_20 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_2983 = remapindex_20 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_2984 = remapindex_20 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_2985 = remapindex_20 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_2986 = remapindex_20 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_2987 = remapindex_20 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_2988 = remapindex_20 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_2989 = remapindex_20 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_2990 = remapindex_20 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_2991 = remapindex_20 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_2992 = remapindex_20 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_2993 = remapindex_20 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_2994 = remapindex_20 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_2995 = remapindex_20 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_2996 = remapindex_20 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_2997 = remapindex_20 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_2998 = remapindex_20 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_2999 = remapindex_20 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3000 = remapindex_20 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3001 = remapindex_20 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_20 = _T_3001 ? _Queue64_UInt8_31_io_deq_bits : _T_3000 ? _Queue64_UInt8_30_io_deq_bits : _T_2999 ? _Queue64_UInt8_29_io_deq_bits : _T_2998 ? _Queue64_UInt8_28_io_deq_bits : _T_2997 ? _Queue64_UInt8_27_io_deq_bits : _T_2996 ? _Queue64_UInt8_26_io_deq_bits : _T_2995 ? _Queue64_UInt8_25_io_deq_bits : _T_2994 ? _Queue64_UInt8_24_io_deq_bits : _T_2993 ? _Queue64_UInt8_23_io_deq_bits : _T_2992 ? _Queue64_UInt8_22_io_deq_bits : _T_2991 ? _Queue64_UInt8_21_io_deq_bits : _T_2990 ? _Queue64_UInt8_20_io_deq_bits : _T_2989 ? _Queue64_UInt8_19_io_deq_bits : _T_2988 ? _Queue64_UInt8_18_io_deq_bits : _T_2987 ? _Queue64_UInt8_17_io_deq_bits : _T_2986 ? _Queue64_UInt8_16_io_deq_bits : _T_2985 ? _Queue64_UInt8_15_io_deq_bits : _T_2984 ? _Queue64_UInt8_14_io_deq_bits : _T_2983 ? _Queue64_UInt8_13_io_deq_bits : _T_2982 ? _Queue64_UInt8_12_io_deq_bits : _T_2981 ? _Queue64_UInt8_11_io_deq_bits : _T_2980 ? _Queue64_UInt8_10_io_deq_bits : _T_2979 ? _Queue64_UInt8_9_io_deq_bits : _T_2978 ? _Queue64_UInt8_8_io_deq_bits : _T_2977 ? _Queue64_UInt8_7_io_deq_bits : _T_2976 ? _Queue64_UInt8_6_io_deq_bits : _T_2975 ? _Queue64_UInt8_5_io_deq_bits : _T_2974 ? _Queue64_UInt8_4_io_deq_bits : _T_2973 ? _Queue64_UInt8_3_io_deq_bits : _T_2972 ? _Queue64_UInt8_2_io_deq_bits : _T_2971 ? _Queue64_UInt8_1_io_deq_bits : _T_2970 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_20 = _T_3001 ? _Queue64_UInt8_31_io_deq_valid : _T_3000 ? _Queue64_UInt8_30_io_deq_valid : _T_2999 ? _Queue64_UInt8_29_io_deq_valid : _T_2998 ? _Queue64_UInt8_28_io_deq_valid : _T_2997 ? _Queue64_UInt8_27_io_deq_valid : _T_2996 ? _Queue64_UInt8_26_io_deq_valid : _T_2995 ? _Queue64_UInt8_25_io_deq_valid : _T_2994 ? _Queue64_UInt8_24_io_deq_valid : _T_2993 ? _Queue64_UInt8_23_io_deq_valid : _T_2992 ? _Queue64_UInt8_22_io_deq_valid : _T_2991 ? _Queue64_UInt8_21_io_deq_valid : _T_2990 ? _Queue64_UInt8_20_io_deq_valid : _T_2989 ? _Queue64_UInt8_19_io_deq_valid : _T_2988 ? _Queue64_UInt8_18_io_deq_valid : _T_2987 ? _Queue64_UInt8_17_io_deq_valid : _T_2986 ? _Queue64_UInt8_16_io_deq_valid : _T_2985 ? _Queue64_UInt8_15_io_deq_valid : _T_2984 ? _Queue64_UInt8_14_io_deq_valid : _T_2983 ? _Queue64_UInt8_13_io_deq_valid : _T_2982 ? _Queue64_UInt8_12_io_deq_valid : _T_2981 ? _Queue64_UInt8_11_io_deq_valid : _T_2980 ? _Queue64_UInt8_10_io_deq_valid : _T_2979 ? _Queue64_UInt8_9_io_deq_valid : _T_2978 ? _Queue64_UInt8_8_io_deq_valid : _T_2977 ? _Queue64_UInt8_7_io_deq_valid : _T_2976 ? _Queue64_UInt8_6_io_deq_valid : _T_2975 ? _Queue64_UInt8_5_io_deq_valid : _T_2974 ? _Queue64_UInt8_4_io_deq_valid : _T_2973 ? _Queue64_UInt8_3_io_deq_valid : _T_2972 ? _Queue64_UInt8_2_io_deq_valid : _T_2971 ? _Queue64_UInt8_1_io_deq_valid : _T_2970 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_21 = _remapindex_T + 7'h15; // @[MemLoader.scala:177:33] wire [6:0] _GEN_112 = _remapindex_T_21 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_21 = _GEN_112[5:0]; // @[MemLoader.scala:177:54] wire _T_3002 = remapindex_21 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3003 = remapindex_21 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3004 = remapindex_21 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3005 = remapindex_21 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3006 = remapindex_21 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3007 = remapindex_21 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3008 = remapindex_21 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3009 = remapindex_21 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3010 = remapindex_21 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3011 = remapindex_21 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3012 = remapindex_21 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3013 = remapindex_21 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3014 = remapindex_21 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3015 = remapindex_21 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3016 = remapindex_21 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3017 = remapindex_21 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3018 = remapindex_21 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3019 = remapindex_21 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3020 = remapindex_21 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3021 = remapindex_21 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3022 = remapindex_21 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3023 = remapindex_21 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3024 = remapindex_21 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3025 = remapindex_21 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3026 = remapindex_21 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3027 = remapindex_21 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3028 = remapindex_21 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3029 = remapindex_21 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3030 = remapindex_21 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3031 = remapindex_21 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3032 = remapindex_21 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3033 = remapindex_21 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_21 = _T_3033 ? _Queue64_UInt8_31_io_deq_bits : _T_3032 ? _Queue64_UInt8_30_io_deq_bits : _T_3031 ? _Queue64_UInt8_29_io_deq_bits : _T_3030 ? _Queue64_UInt8_28_io_deq_bits : _T_3029 ? _Queue64_UInt8_27_io_deq_bits : _T_3028 ? _Queue64_UInt8_26_io_deq_bits : _T_3027 ? _Queue64_UInt8_25_io_deq_bits : _T_3026 ? _Queue64_UInt8_24_io_deq_bits : _T_3025 ? _Queue64_UInt8_23_io_deq_bits : _T_3024 ? _Queue64_UInt8_22_io_deq_bits : _T_3023 ? _Queue64_UInt8_21_io_deq_bits : _T_3022 ? _Queue64_UInt8_20_io_deq_bits : _T_3021 ? _Queue64_UInt8_19_io_deq_bits : _T_3020 ? _Queue64_UInt8_18_io_deq_bits : _T_3019 ? _Queue64_UInt8_17_io_deq_bits : _T_3018 ? _Queue64_UInt8_16_io_deq_bits : _T_3017 ? _Queue64_UInt8_15_io_deq_bits : _T_3016 ? _Queue64_UInt8_14_io_deq_bits : _T_3015 ? _Queue64_UInt8_13_io_deq_bits : _T_3014 ? _Queue64_UInt8_12_io_deq_bits : _T_3013 ? _Queue64_UInt8_11_io_deq_bits : _T_3012 ? _Queue64_UInt8_10_io_deq_bits : _T_3011 ? _Queue64_UInt8_9_io_deq_bits : _T_3010 ? _Queue64_UInt8_8_io_deq_bits : _T_3009 ? _Queue64_UInt8_7_io_deq_bits : _T_3008 ? _Queue64_UInt8_6_io_deq_bits : _T_3007 ? _Queue64_UInt8_5_io_deq_bits : _T_3006 ? _Queue64_UInt8_4_io_deq_bits : _T_3005 ? _Queue64_UInt8_3_io_deq_bits : _T_3004 ? _Queue64_UInt8_2_io_deq_bits : _T_3003 ? _Queue64_UInt8_1_io_deq_bits : _T_3002 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_21 = _T_3033 ? _Queue64_UInt8_31_io_deq_valid : _T_3032 ? _Queue64_UInt8_30_io_deq_valid : _T_3031 ? _Queue64_UInt8_29_io_deq_valid : _T_3030 ? _Queue64_UInt8_28_io_deq_valid : _T_3029 ? _Queue64_UInt8_27_io_deq_valid : _T_3028 ? _Queue64_UInt8_26_io_deq_valid : _T_3027 ? _Queue64_UInt8_25_io_deq_valid : _T_3026 ? _Queue64_UInt8_24_io_deq_valid : _T_3025 ? _Queue64_UInt8_23_io_deq_valid : _T_3024 ? _Queue64_UInt8_22_io_deq_valid : _T_3023 ? _Queue64_UInt8_21_io_deq_valid : _T_3022 ? _Queue64_UInt8_20_io_deq_valid : _T_3021 ? _Queue64_UInt8_19_io_deq_valid : _T_3020 ? _Queue64_UInt8_18_io_deq_valid : _T_3019 ? _Queue64_UInt8_17_io_deq_valid : _T_3018 ? _Queue64_UInt8_16_io_deq_valid : _T_3017 ? _Queue64_UInt8_15_io_deq_valid : _T_3016 ? _Queue64_UInt8_14_io_deq_valid : _T_3015 ? _Queue64_UInt8_13_io_deq_valid : _T_3014 ? _Queue64_UInt8_12_io_deq_valid : _T_3013 ? _Queue64_UInt8_11_io_deq_valid : _T_3012 ? _Queue64_UInt8_10_io_deq_valid : _T_3011 ? _Queue64_UInt8_9_io_deq_valid : _T_3010 ? _Queue64_UInt8_8_io_deq_valid : _T_3009 ? _Queue64_UInt8_7_io_deq_valid : _T_3008 ? _Queue64_UInt8_6_io_deq_valid : _T_3007 ? _Queue64_UInt8_5_io_deq_valid : _T_3006 ? _Queue64_UInt8_4_io_deq_valid : _T_3005 ? _Queue64_UInt8_3_io_deq_valid : _T_3004 ? _Queue64_UInt8_2_io_deq_valid : _T_3003 ? _Queue64_UInt8_1_io_deq_valid : _T_3002 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_22 = _remapindex_T + 7'h16; // @[MemLoader.scala:177:33] wire [6:0] _GEN_113 = _remapindex_T_22 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_22 = _GEN_113[5:0]; // @[MemLoader.scala:177:54] wire _T_3034 = remapindex_22 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3035 = remapindex_22 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3036 = remapindex_22 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3037 = remapindex_22 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3038 = remapindex_22 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3039 = remapindex_22 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3040 = remapindex_22 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3041 = remapindex_22 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3042 = remapindex_22 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3043 = remapindex_22 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3044 = remapindex_22 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3045 = remapindex_22 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3046 = remapindex_22 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3047 = remapindex_22 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3048 = remapindex_22 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3049 = remapindex_22 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3050 = remapindex_22 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3051 = remapindex_22 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3052 = remapindex_22 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3053 = remapindex_22 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3054 = remapindex_22 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3055 = remapindex_22 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3056 = remapindex_22 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3057 = remapindex_22 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3058 = remapindex_22 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3059 = remapindex_22 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3060 = remapindex_22 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3061 = remapindex_22 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3062 = remapindex_22 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3063 = remapindex_22 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3064 = remapindex_22 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3065 = remapindex_22 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_22 = _T_3065 ? _Queue64_UInt8_31_io_deq_bits : _T_3064 ? _Queue64_UInt8_30_io_deq_bits : _T_3063 ? _Queue64_UInt8_29_io_deq_bits : _T_3062 ? _Queue64_UInt8_28_io_deq_bits : _T_3061 ? _Queue64_UInt8_27_io_deq_bits : _T_3060 ? _Queue64_UInt8_26_io_deq_bits : _T_3059 ? _Queue64_UInt8_25_io_deq_bits : _T_3058 ? _Queue64_UInt8_24_io_deq_bits : _T_3057 ? _Queue64_UInt8_23_io_deq_bits : _T_3056 ? _Queue64_UInt8_22_io_deq_bits : _T_3055 ? _Queue64_UInt8_21_io_deq_bits : _T_3054 ? _Queue64_UInt8_20_io_deq_bits : _T_3053 ? _Queue64_UInt8_19_io_deq_bits : _T_3052 ? _Queue64_UInt8_18_io_deq_bits : _T_3051 ? _Queue64_UInt8_17_io_deq_bits : _T_3050 ? _Queue64_UInt8_16_io_deq_bits : _T_3049 ? _Queue64_UInt8_15_io_deq_bits : _T_3048 ? _Queue64_UInt8_14_io_deq_bits : _T_3047 ? _Queue64_UInt8_13_io_deq_bits : _T_3046 ? _Queue64_UInt8_12_io_deq_bits : _T_3045 ? _Queue64_UInt8_11_io_deq_bits : _T_3044 ? _Queue64_UInt8_10_io_deq_bits : _T_3043 ? _Queue64_UInt8_9_io_deq_bits : _T_3042 ? _Queue64_UInt8_8_io_deq_bits : _T_3041 ? _Queue64_UInt8_7_io_deq_bits : _T_3040 ? _Queue64_UInt8_6_io_deq_bits : _T_3039 ? _Queue64_UInt8_5_io_deq_bits : _T_3038 ? _Queue64_UInt8_4_io_deq_bits : _T_3037 ? _Queue64_UInt8_3_io_deq_bits : _T_3036 ? _Queue64_UInt8_2_io_deq_bits : _T_3035 ? _Queue64_UInt8_1_io_deq_bits : _T_3034 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_22 = _T_3065 ? _Queue64_UInt8_31_io_deq_valid : _T_3064 ? _Queue64_UInt8_30_io_deq_valid : _T_3063 ? _Queue64_UInt8_29_io_deq_valid : _T_3062 ? _Queue64_UInt8_28_io_deq_valid : _T_3061 ? _Queue64_UInt8_27_io_deq_valid : _T_3060 ? _Queue64_UInt8_26_io_deq_valid : _T_3059 ? _Queue64_UInt8_25_io_deq_valid : _T_3058 ? _Queue64_UInt8_24_io_deq_valid : _T_3057 ? _Queue64_UInt8_23_io_deq_valid : _T_3056 ? _Queue64_UInt8_22_io_deq_valid : _T_3055 ? _Queue64_UInt8_21_io_deq_valid : _T_3054 ? _Queue64_UInt8_20_io_deq_valid : _T_3053 ? _Queue64_UInt8_19_io_deq_valid : _T_3052 ? _Queue64_UInt8_18_io_deq_valid : _T_3051 ? _Queue64_UInt8_17_io_deq_valid : _T_3050 ? _Queue64_UInt8_16_io_deq_valid : _T_3049 ? _Queue64_UInt8_15_io_deq_valid : _T_3048 ? _Queue64_UInt8_14_io_deq_valid : _T_3047 ? _Queue64_UInt8_13_io_deq_valid : _T_3046 ? _Queue64_UInt8_12_io_deq_valid : _T_3045 ? _Queue64_UInt8_11_io_deq_valid : _T_3044 ? _Queue64_UInt8_10_io_deq_valid : _T_3043 ? _Queue64_UInt8_9_io_deq_valid : _T_3042 ? _Queue64_UInt8_8_io_deq_valid : _T_3041 ? _Queue64_UInt8_7_io_deq_valid : _T_3040 ? _Queue64_UInt8_6_io_deq_valid : _T_3039 ? _Queue64_UInt8_5_io_deq_valid : _T_3038 ? _Queue64_UInt8_4_io_deq_valid : _T_3037 ? _Queue64_UInt8_3_io_deq_valid : _T_3036 ? _Queue64_UInt8_2_io_deq_valid : _T_3035 ? _Queue64_UInt8_1_io_deq_valid : _T_3034 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_23 = _remapindex_T + 7'h17; // @[MemLoader.scala:177:33] wire [6:0] _GEN_114 = _remapindex_T_23 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_23 = _GEN_114[5:0]; // @[MemLoader.scala:177:54] wire _T_3066 = remapindex_23 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3067 = remapindex_23 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3068 = remapindex_23 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3069 = remapindex_23 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3070 = remapindex_23 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3071 = remapindex_23 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3072 = remapindex_23 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3073 = remapindex_23 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3074 = remapindex_23 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3075 = remapindex_23 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3076 = remapindex_23 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3077 = remapindex_23 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3078 = remapindex_23 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3079 = remapindex_23 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3080 = remapindex_23 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3081 = remapindex_23 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3082 = remapindex_23 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3083 = remapindex_23 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3084 = remapindex_23 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3085 = remapindex_23 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3086 = remapindex_23 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3087 = remapindex_23 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3088 = remapindex_23 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3089 = remapindex_23 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3090 = remapindex_23 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3091 = remapindex_23 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3092 = remapindex_23 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3093 = remapindex_23 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3094 = remapindex_23 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3095 = remapindex_23 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3096 = remapindex_23 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3097 = remapindex_23 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_23 = _T_3097 ? _Queue64_UInt8_31_io_deq_bits : _T_3096 ? _Queue64_UInt8_30_io_deq_bits : _T_3095 ? _Queue64_UInt8_29_io_deq_bits : _T_3094 ? _Queue64_UInt8_28_io_deq_bits : _T_3093 ? _Queue64_UInt8_27_io_deq_bits : _T_3092 ? _Queue64_UInt8_26_io_deq_bits : _T_3091 ? _Queue64_UInt8_25_io_deq_bits : _T_3090 ? _Queue64_UInt8_24_io_deq_bits : _T_3089 ? _Queue64_UInt8_23_io_deq_bits : _T_3088 ? _Queue64_UInt8_22_io_deq_bits : _T_3087 ? _Queue64_UInt8_21_io_deq_bits : _T_3086 ? _Queue64_UInt8_20_io_deq_bits : _T_3085 ? _Queue64_UInt8_19_io_deq_bits : _T_3084 ? _Queue64_UInt8_18_io_deq_bits : _T_3083 ? _Queue64_UInt8_17_io_deq_bits : _T_3082 ? _Queue64_UInt8_16_io_deq_bits : _T_3081 ? _Queue64_UInt8_15_io_deq_bits : _T_3080 ? _Queue64_UInt8_14_io_deq_bits : _T_3079 ? _Queue64_UInt8_13_io_deq_bits : _T_3078 ? _Queue64_UInt8_12_io_deq_bits : _T_3077 ? _Queue64_UInt8_11_io_deq_bits : _T_3076 ? _Queue64_UInt8_10_io_deq_bits : _T_3075 ? _Queue64_UInt8_9_io_deq_bits : _T_3074 ? _Queue64_UInt8_8_io_deq_bits : _T_3073 ? _Queue64_UInt8_7_io_deq_bits : _T_3072 ? _Queue64_UInt8_6_io_deq_bits : _T_3071 ? _Queue64_UInt8_5_io_deq_bits : _T_3070 ? _Queue64_UInt8_4_io_deq_bits : _T_3069 ? _Queue64_UInt8_3_io_deq_bits : _T_3068 ? _Queue64_UInt8_2_io_deq_bits : _T_3067 ? _Queue64_UInt8_1_io_deq_bits : _T_3066 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_23 = _T_3097 ? _Queue64_UInt8_31_io_deq_valid : _T_3096 ? _Queue64_UInt8_30_io_deq_valid : _T_3095 ? _Queue64_UInt8_29_io_deq_valid : _T_3094 ? _Queue64_UInt8_28_io_deq_valid : _T_3093 ? _Queue64_UInt8_27_io_deq_valid : _T_3092 ? _Queue64_UInt8_26_io_deq_valid : _T_3091 ? _Queue64_UInt8_25_io_deq_valid : _T_3090 ? _Queue64_UInt8_24_io_deq_valid : _T_3089 ? _Queue64_UInt8_23_io_deq_valid : _T_3088 ? _Queue64_UInt8_22_io_deq_valid : _T_3087 ? _Queue64_UInt8_21_io_deq_valid : _T_3086 ? _Queue64_UInt8_20_io_deq_valid : _T_3085 ? _Queue64_UInt8_19_io_deq_valid : _T_3084 ? _Queue64_UInt8_18_io_deq_valid : _T_3083 ? _Queue64_UInt8_17_io_deq_valid : _T_3082 ? _Queue64_UInt8_16_io_deq_valid : _T_3081 ? _Queue64_UInt8_15_io_deq_valid : _T_3080 ? _Queue64_UInt8_14_io_deq_valid : _T_3079 ? _Queue64_UInt8_13_io_deq_valid : _T_3078 ? _Queue64_UInt8_12_io_deq_valid : _T_3077 ? _Queue64_UInt8_11_io_deq_valid : _T_3076 ? _Queue64_UInt8_10_io_deq_valid : _T_3075 ? _Queue64_UInt8_9_io_deq_valid : _T_3074 ? _Queue64_UInt8_8_io_deq_valid : _T_3073 ? _Queue64_UInt8_7_io_deq_valid : _T_3072 ? _Queue64_UInt8_6_io_deq_valid : _T_3071 ? _Queue64_UInt8_5_io_deq_valid : _T_3070 ? _Queue64_UInt8_4_io_deq_valid : _T_3069 ? _Queue64_UInt8_3_io_deq_valid : _T_3068 ? _Queue64_UInt8_2_io_deq_valid : _T_3067 ? _Queue64_UInt8_1_io_deq_valid : _T_3066 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_24 = _remapindex_T + 7'h18; // @[MemLoader.scala:177:33] wire [6:0] _GEN_115 = _remapindex_T_24 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_24 = _GEN_115[5:0]; // @[MemLoader.scala:177:54] wire _T_3098 = remapindex_24 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3099 = remapindex_24 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3100 = remapindex_24 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3101 = remapindex_24 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3102 = remapindex_24 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3103 = remapindex_24 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3104 = remapindex_24 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3105 = remapindex_24 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3106 = remapindex_24 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3107 = remapindex_24 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3108 = remapindex_24 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3109 = remapindex_24 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3110 = remapindex_24 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3111 = remapindex_24 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3112 = remapindex_24 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3113 = remapindex_24 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3114 = remapindex_24 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3115 = remapindex_24 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3116 = remapindex_24 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3117 = remapindex_24 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3118 = remapindex_24 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3119 = remapindex_24 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3120 = remapindex_24 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3121 = remapindex_24 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3122 = remapindex_24 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3123 = remapindex_24 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3124 = remapindex_24 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3125 = remapindex_24 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3126 = remapindex_24 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3127 = remapindex_24 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3128 = remapindex_24 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3129 = remapindex_24 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_24 = _T_3129 ? _Queue64_UInt8_31_io_deq_bits : _T_3128 ? _Queue64_UInt8_30_io_deq_bits : _T_3127 ? _Queue64_UInt8_29_io_deq_bits : _T_3126 ? _Queue64_UInt8_28_io_deq_bits : _T_3125 ? _Queue64_UInt8_27_io_deq_bits : _T_3124 ? _Queue64_UInt8_26_io_deq_bits : _T_3123 ? _Queue64_UInt8_25_io_deq_bits : _T_3122 ? _Queue64_UInt8_24_io_deq_bits : _T_3121 ? _Queue64_UInt8_23_io_deq_bits : _T_3120 ? _Queue64_UInt8_22_io_deq_bits : _T_3119 ? _Queue64_UInt8_21_io_deq_bits : _T_3118 ? _Queue64_UInt8_20_io_deq_bits : _T_3117 ? _Queue64_UInt8_19_io_deq_bits : _T_3116 ? _Queue64_UInt8_18_io_deq_bits : _T_3115 ? _Queue64_UInt8_17_io_deq_bits : _T_3114 ? _Queue64_UInt8_16_io_deq_bits : _T_3113 ? _Queue64_UInt8_15_io_deq_bits : _T_3112 ? _Queue64_UInt8_14_io_deq_bits : _T_3111 ? _Queue64_UInt8_13_io_deq_bits : _T_3110 ? _Queue64_UInt8_12_io_deq_bits : _T_3109 ? _Queue64_UInt8_11_io_deq_bits : _T_3108 ? _Queue64_UInt8_10_io_deq_bits : _T_3107 ? _Queue64_UInt8_9_io_deq_bits : _T_3106 ? _Queue64_UInt8_8_io_deq_bits : _T_3105 ? _Queue64_UInt8_7_io_deq_bits : _T_3104 ? _Queue64_UInt8_6_io_deq_bits : _T_3103 ? _Queue64_UInt8_5_io_deq_bits : _T_3102 ? _Queue64_UInt8_4_io_deq_bits : _T_3101 ? _Queue64_UInt8_3_io_deq_bits : _T_3100 ? _Queue64_UInt8_2_io_deq_bits : _T_3099 ? _Queue64_UInt8_1_io_deq_bits : _T_3098 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_24 = _T_3129 ? _Queue64_UInt8_31_io_deq_valid : _T_3128 ? _Queue64_UInt8_30_io_deq_valid : _T_3127 ? _Queue64_UInt8_29_io_deq_valid : _T_3126 ? _Queue64_UInt8_28_io_deq_valid : _T_3125 ? _Queue64_UInt8_27_io_deq_valid : _T_3124 ? _Queue64_UInt8_26_io_deq_valid : _T_3123 ? _Queue64_UInt8_25_io_deq_valid : _T_3122 ? _Queue64_UInt8_24_io_deq_valid : _T_3121 ? _Queue64_UInt8_23_io_deq_valid : _T_3120 ? _Queue64_UInt8_22_io_deq_valid : _T_3119 ? _Queue64_UInt8_21_io_deq_valid : _T_3118 ? _Queue64_UInt8_20_io_deq_valid : _T_3117 ? _Queue64_UInt8_19_io_deq_valid : _T_3116 ? _Queue64_UInt8_18_io_deq_valid : _T_3115 ? _Queue64_UInt8_17_io_deq_valid : _T_3114 ? _Queue64_UInt8_16_io_deq_valid : _T_3113 ? _Queue64_UInt8_15_io_deq_valid : _T_3112 ? _Queue64_UInt8_14_io_deq_valid : _T_3111 ? _Queue64_UInt8_13_io_deq_valid : _T_3110 ? _Queue64_UInt8_12_io_deq_valid : _T_3109 ? _Queue64_UInt8_11_io_deq_valid : _T_3108 ? _Queue64_UInt8_10_io_deq_valid : _T_3107 ? _Queue64_UInt8_9_io_deq_valid : _T_3106 ? _Queue64_UInt8_8_io_deq_valid : _T_3105 ? _Queue64_UInt8_7_io_deq_valid : _T_3104 ? _Queue64_UInt8_6_io_deq_valid : _T_3103 ? _Queue64_UInt8_5_io_deq_valid : _T_3102 ? _Queue64_UInt8_4_io_deq_valid : _T_3101 ? _Queue64_UInt8_3_io_deq_valid : _T_3100 ? _Queue64_UInt8_2_io_deq_valid : _T_3099 ? _Queue64_UInt8_1_io_deq_valid : _T_3098 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_25 = _remapindex_T + 7'h19; // @[MemLoader.scala:177:33] wire [6:0] _GEN_116 = _remapindex_T_25 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_25 = _GEN_116[5:0]; // @[MemLoader.scala:177:54] wire _T_3130 = remapindex_25 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3131 = remapindex_25 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3132 = remapindex_25 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3133 = remapindex_25 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3134 = remapindex_25 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3135 = remapindex_25 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3136 = remapindex_25 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3137 = remapindex_25 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3138 = remapindex_25 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3139 = remapindex_25 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3140 = remapindex_25 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3141 = remapindex_25 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3142 = remapindex_25 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3143 = remapindex_25 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3144 = remapindex_25 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3145 = remapindex_25 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3146 = remapindex_25 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3147 = remapindex_25 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3148 = remapindex_25 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3149 = remapindex_25 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3150 = remapindex_25 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3151 = remapindex_25 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3152 = remapindex_25 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3153 = remapindex_25 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3154 = remapindex_25 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3155 = remapindex_25 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3156 = remapindex_25 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3157 = remapindex_25 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3158 = remapindex_25 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3159 = remapindex_25 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3160 = remapindex_25 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3161 = remapindex_25 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_25 = _T_3161 ? _Queue64_UInt8_31_io_deq_bits : _T_3160 ? _Queue64_UInt8_30_io_deq_bits : _T_3159 ? _Queue64_UInt8_29_io_deq_bits : _T_3158 ? _Queue64_UInt8_28_io_deq_bits : _T_3157 ? _Queue64_UInt8_27_io_deq_bits : _T_3156 ? _Queue64_UInt8_26_io_deq_bits : _T_3155 ? _Queue64_UInt8_25_io_deq_bits : _T_3154 ? _Queue64_UInt8_24_io_deq_bits : _T_3153 ? _Queue64_UInt8_23_io_deq_bits : _T_3152 ? _Queue64_UInt8_22_io_deq_bits : _T_3151 ? _Queue64_UInt8_21_io_deq_bits : _T_3150 ? _Queue64_UInt8_20_io_deq_bits : _T_3149 ? _Queue64_UInt8_19_io_deq_bits : _T_3148 ? _Queue64_UInt8_18_io_deq_bits : _T_3147 ? _Queue64_UInt8_17_io_deq_bits : _T_3146 ? _Queue64_UInt8_16_io_deq_bits : _T_3145 ? _Queue64_UInt8_15_io_deq_bits : _T_3144 ? _Queue64_UInt8_14_io_deq_bits : _T_3143 ? _Queue64_UInt8_13_io_deq_bits : _T_3142 ? _Queue64_UInt8_12_io_deq_bits : _T_3141 ? _Queue64_UInt8_11_io_deq_bits : _T_3140 ? _Queue64_UInt8_10_io_deq_bits : _T_3139 ? _Queue64_UInt8_9_io_deq_bits : _T_3138 ? _Queue64_UInt8_8_io_deq_bits : _T_3137 ? _Queue64_UInt8_7_io_deq_bits : _T_3136 ? _Queue64_UInt8_6_io_deq_bits : _T_3135 ? _Queue64_UInt8_5_io_deq_bits : _T_3134 ? _Queue64_UInt8_4_io_deq_bits : _T_3133 ? _Queue64_UInt8_3_io_deq_bits : _T_3132 ? _Queue64_UInt8_2_io_deq_bits : _T_3131 ? _Queue64_UInt8_1_io_deq_bits : _T_3130 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_25 = _T_3161 ? _Queue64_UInt8_31_io_deq_valid : _T_3160 ? _Queue64_UInt8_30_io_deq_valid : _T_3159 ? _Queue64_UInt8_29_io_deq_valid : _T_3158 ? _Queue64_UInt8_28_io_deq_valid : _T_3157 ? _Queue64_UInt8_27_io_deq_valid : _T_3156 ? _Queue64_UInt8_26_io_deq_valid : _T_3155 ? _Queue64_UInt8_25_io_deq_valid : _T_3154 ? _Queue64_UInt8_24_io_deq_valid : _T_3153 ? _Queue64_UInt8_23_io_deq_valid : _T_3152 ? _Queue64_UInt8_22_io_deq_valid : _T_3151 ? _Queue64_UInt8_21_io_deq_valid : _T_3150 ? _Queue64_UInt8_20_io_deq_valid : _T_3149 ? _Queue64_UInt8_19_io_deq_valid : _T_3148 ? _Queue64_UInt8_18_io_deq_valid : _T_3147 ? _Queue64_UInt8_17_io_deq_valid : _T_3146 ? _Queue64_UInt8_16_io_deq_valid : _T_3145 ? _Queue64_UInt8_15_io_deq_valid : _T_3144 ? _Queue64_UInt8_14_io_deq_valid : _T_3143 ? _Queue64_UInt8_13_io_deq_valid : _T_3142 ? _Queue64_UInt8_12_io_deq_valid : _T_3141 ? _Queue64_UInt8_11_io_deq_valid : _T_3140 ? _Queue64_UInt8_10_io_deq_valid : _T_3139 ? _Queue64_UInt8_9_io_deq_valid : _T_3138 ? _Queue64_UInt8_8_io_deq_valid : _T_3137 ? _Queue64_UInt8_7_io_deq_valid : _T_3136 ? _Queue64_UInt8_6_io_deq_valid : _T_3135 ? _Queue64_UInt8_5_io_deq_valid : _T_3134 ? _Queue64_UInt8_4_io_deq_valid : _T_3133 ? _Queue64_UInt8_3_io_deq_valid : _T_3132 ? _Queue64_UInt8_2_io_deq_valid : _T_3131 ? _Queue64_UInt8_1_io_deq_valid : _T_3130 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_26 = _remapindex_T + 7'h1A; // @[MemLoader.scala:177:33] wire [6:0] _GEN_117 = _remapindex_T_26 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_26 = _GEN_117[5:0]; // @[MemLoader.scala:177:54] wire _T_3162 = remapindex_26 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3163 = remapindex_26 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3164 = remapindex_26 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3165 = remapindex_26 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3166 = remapindex_26 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3167 = remapindex_26 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3168 = remapindex_26 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3169 = remapindex_26 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3170 = remapindex_26 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3171 = remapindex_26 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3172 = remapindex_26 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3173 = remapindex_26 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3174 = remapindex_26 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3175 = remapindex_26 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3176 = remapindex_26 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3177 = remapindex_26 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3178 = remapindex_26 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3179 = remapindex_26 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3180 = remapindex_26 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3181 = remapindex_26 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3182 = remapindex_26 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3183 = remapindex_26 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3184 = remapindex_26 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3185 = remapindex_26 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3186 = remapindex_26 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3187 = remapindex_26 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3188 = remapindex_26 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3189 = remapindex_26 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3190 = remapindex_26 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3191 = remapindex_26 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3192 = remapindex_26 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3193 = remapindex_26 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_26 = _T_3193 ? _Queue64_UInt8_31_io_deq_bits : _T_3192 ? _Queue64_UInt8_30_io_deq_bits : _T_3191 ? _Queue64_UInt8_29_io_deq_bits : _T_3190 ? _Queue64_UInt8_28_io_deq_bits : _T_3189 ? _Queue64_UInt8_27_io_deq_bits : _T_3188 ? _Queue64_UInt8_26_io_deq_bits : _T_3187 ? _Queue64_UInt8_25_io_deq_bits : _T_3186 ? _Queue64_UInt8_24_io_deq_bits : _T_3185 ? _Queue64_UInt8_23_io_deq_bits : _T_3184 ? _Queue64_UInt8_22_io_deq_bits : _T_3183 ? _Queue64_UInt8_21_io_deq_bits : _T_3182 ? _Queue64_UInt8_20_io_deq_bits : _T_3181 ? _Queue64_UInt8_19_io_deq_bits : _T_3180 ? _Queue64_UInt8_18_io_deq_bits : _T_3179 ? _Queue64_UInt8_17_io_deq_bits : _T_3178 ? _Queue64_UInt8_16_io_deq_bits : _T_3177 ? _Queue64_UInt8_15_io_deq_bits : _T_3176 ? _Queue64_UInt8_14_io_deq_bits : _T_3175 ? _Queue64_UInt8_13_io_deq_bits : _T_3174 ? _Queue64_UInt8_12_io_deq_bits : _T_3173 ? _Queue64_UInt8_11_io_deq_bits : _T_3172 ? _Queue64_UInt8_10_io_deq_bits : _T_3171 ? _Queue64_UInt8_9_io_deq_bits : _T_3170 ? _Queue64_UInt8_8_io_deq_bits : _T_3169 ? _Queue64_UInt8_7_io_deq_bits : _T_3168 ? _Queue64_UInt8_6_io_deq_bits : _T_3167 ? _Queue64_UInt8_5_io_deq_bits : _T_3166 ? _Queue64_UInt8_4_io_deq_bits : _T_3165 ? _Queue64_UInt8_3_io_deq_bits : _T_3164 ? _Queue64_UInt8_2_io_deq_bits : _T_3163 ? _Queue64_UInt8_1_io_deq_bits : _T_3162 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_26 = _T_3193 ? _Queue64_UInt8_31_io_deq_valid : _T_3192 ? _Queue64_UInt8_30_io_deq_valid : _T_3191 ? _Queue64_UInt8_29_io_deq_valid : _T_3190 ? _Queue64_UInt8_28_io_deq_valid : _T_3189 ? _Queue64_UInt8_27_io_deq_valid : _T_3188 ? _Queue64_UInt8_26_io_deq_valid : _T_3187 ? _Queue64_UInt8_25_io_deq_valid : _T_3186 ? _Queue64_UInt8_24_io_deq_valid : _T_3185 ? _Queue64_UInt8_23_io_deq_valid : _T_3184 ? _Queue64_UInt8_22_io_deq_valid : _T_3183 ? _Queue64_UInt8_21_io_deq_valid : _T_3182 ? _Queue64_UInt8_20_io_deq_valid : _T_3181 ? _Queue64_UInt8_19_io_deq_valid : _T_3180 ? _Queue64_UInt8_18_io_deq_valid : _T_3179 ? _Queue64_UInt8_17_io_deq_valid : _T_3178 ? _Queue64_UInt8_16_io_deq_valid : _T_3177 ? _Queue64_UInt8_15_io_deq_valid : _T_3176 ? _Queue64_UInt8_14_io_deq_valid : _T_3175 ? _Queue64_UInt8_13_io_deq_valid : _T_3174 ? _Queue64_UInt8_12_io_deq_valid : _T_3173 ? _Queue64_UInt8_11_io_deq_valid : _T_3172 ? _Queue64_UInt8_10_io_deq_valid : _T_3171 ? _Queue64_UInt8_9_io_deq_valid : _T_3170 ? _Queue64_UInt8_8_io_deq_valid : _T_3169 ? _Queue64_UInt8_7_io_deq_valid : _T_3168 ? _Queue64_UInt8_6_io_deq_valid : _T_3167 ? _Queue64_UInt8_5_io_deq_valid : _T_3166 ? _Queue64_UInt8_4_io_deq_valid : _T_3165 ? _Queue64_UInt8_3_io_deq_valid : _T_3164 ? _Queue64_UInt8_2_io_deq_valid : _T_3163 ? _Queue64_UInt8_1_io_deq_valid : _T_3162 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_27 = _remapindex_T + 7'h1B; // @[MemLoader.scala:177:33] wire [6:0] _GEN_118 = _remapindex_T_27 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_27 = _GEN_118[5:0]; // @[MemLoader.scala:177:54] wire _T_3194 = remapindex_27 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3195 = remapindex_27 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3196 = remapindex_27 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3197 = remapindex_27 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3198 = remapindex_27 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3199 = remapindex_27 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3200 = remapindex_27 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3201 = remapindex_27 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3202 = remapindex_27 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3203 = remapindex_27 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3204 = remapindex_27 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3205 = remapindex_27 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3206 = remapindex_27 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3207 = remapindex_27 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3208 = remapindex_27 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3209 = remapindex_27 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3210 = remapindex_27 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3211 = remapindex_27 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3212 = remapindex_27 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3213 = remapindex_27 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3214 = remapindex_27 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3215 = remapindex_27 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3216 = remapindex_27 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3217 = remapindex_27 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3218 = remapindex_27 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3219 = remapindex_27 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3220 = remapindex_27 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3221 = remapindex_27 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3222 = remapindex_27 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3223 = remapindex_27 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3224 = remapindex_27 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3225 = remapindex_27 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_27 = _T_3225 ? _Queue64_UInt8_31_io_deq_bits : _T_3224 ? _Queue64_UInt8_30_io_deq_bits : _T_3223 ? _Queue64_UInt8_29_io_deq_bits : _T_3222 ? _Queue64_UInt8_28_io_deq_bits : _T_3221 ? _Queue64_UInt8_27_io_deq_bits : _T_3220 ? _Queue64_UInt8_26_io_deq_bits : _T_3219 ? _Queue64_UInt8_25_io_deq_bits : _T_3218 ? _Queue64_UInt8_24_io_deq_bits : _T_3217 ? _Queue64_UInt8_23_io_deq_bits : _T_3216 ? _Queue64_UInt8_22_io_deq_bits : _T_3215 ? _Queue64_UInt8_21_io_deq_bits : _T_3214 ? _Queue64_UInt8_20_io_deq_bits : _T_3213 ? _Queue64_UInt8_19_io_deq_bits : _T_3212 ? _Queue64_UInt8_18_io_deq_bits : _T_3211 ? _Queue64_UInt8_17_io_deq_bits : _T_3210 ? _Queue64_UInt8_16_io_deq_bits : _T_3209 ? _Queue64_UInt8_15_io_deq_bits : _T_3208 ? _Queue64_UInt8_14_io_deq_bits : _T_3207 ? _Queue64_UInt8_13_io_deq_bits : _T_3206 ? _Queue64_UInt8_12_io_deq_bits : _T_3205 ? _Queue64_UInt8_11_io_deq_bits : _T_3204 ? _Queue64_UInt8_10_io_deq_bits : _T_3203 ? _Queue64_UInt8_9_io_deq_bits : _T_3202 ? _Queue64_UInt8_8_io_deq_bits : _T_3201 ? _Queue64_UInt8_7_io_deq_bits : _T_3200 ? _Queue64_UInt8_6_io_deq_bits : _T_3199 ? _Queue64_UInt8_5_io_deq_bits : _T_3198 ? _Queue64_UInt8_4_io_deq_bits : _T_3197 ? _Queue64_UInt8_3_io_deq_bits : _T_3196 ? _Queue64_UInt8_2_io_deq_bits : _T_3195 ? _Queue64_UInt8_1_io_deq_bits : _T_3194 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_27 = _T_3225 ? _Queue64_UInt8_31_io_deq_valid : _T_3224 ? _Queue64_UInt8_30_io_deq_valid : _T_3223 ? _Queue64_UInt8_29_io_deq_valid : _T_3222 ? _Queue64_UInt8_28_io_deq_valid : _T_3221 ? _Queue64_UInt8_27_io_deq_valid : _T_3220 ? _Queue64_UInt8_26_io_deq_valid : _T_3219 ? _Queue64_UInt8_25_io_deq_valid : _T_3218 ? _Queue64_UInt8_24_io_deq_valid : _T_3217 ? _Queue64_UInt8_23_io_deq_valid : _T_3216 ? _Queue64_UInt8_22_io_deq_valid : _T_3215 ? _Queue64_UInt8_21_io_deq_valid : _T_3214 ? _Queue64_UInt8_20_io_deq_valid : _T_3213 ? _Queue64_UInt8_19_io_deq_valid : _T_3212 ? _Queue64_UInt8_18_io_deq_valid : _T_3211 ? _Queue64_UInt8_17_io_deq_valid : _T_3210 ? _Queue64_UInt8_16_io_deq_valid : _T_3209 ? _Queue64_UInt8_15_io_deq_valid : _T_3208 ? _Queue64_UInt8_14_io_deq_valid : _T_3207 ? _Queue64_UInt8_13_io_deq_valid : _T_3206 ? _Queue64_UInt8_12_io_deq_valid : _T_3205 ? _Queue64_UInt8_11_io_deq_valid : _T_3204 ? _Queue64_UInt8_10_io_deq_valid : _T_3203 ? _Queue64_UInt8_9_io_deq_valid : _T_3202 ? _Queue64_UInt8_8_io_deq_valid : _T_3201 ? _Queue64_UInt8_7_io_deq_valid : _T_3200 ? _Queue64_UInt8_6_io_deq_valid : _T_3199 ? _Queue64_UInt8_5_io_deq_valid : _T_3198 ? _Queue64_UInt8_4_io_deq_valid : _T_3197 ? _Queue64_UInt8_3_io_deq_valid : _T_3196 ? _Queue64_UInt8_2_io_deq_valid : _T_3195 ? _Queue64_UInt8_1_io_deq_valid : _T_3194 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_28 = _remapindex_T + 7'h1C; // @[MemLoader.scala:177:33] wire [6:0] _GEN_119 = _remapindex_T_28 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_28 = _GEN_119[5:0]; // @[MemLoader.scala:177:54] wire _T_3226 = remapindex_28 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3227 = remapindex_28 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3228 = remapindex_28 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3229 = remapindex_28 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3230 = remapindex_28 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3231 = remapindex_28 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3232 = remapindex_28 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3233 = remapindex_28 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3234 = remapindex_28 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3235 = remapindex_28 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3236 = remapindex_28 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3237 = remapindex_28 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3238 = remapindex_28 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3239 = remapindex_28 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3240 = remapindex_28 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3241 = remapindex_28 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3242 = remapindex_28 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3243 = remapindex_28 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3244 = remapindex_28 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3245 = remapindex_28 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3246 = remapindex_28 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3247 = remapindex_28 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3248 = remapindex_28 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3249 = remapindex_28 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3250 = remapindex_28 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3251 = remapindex_28 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3252 = remapindex_28 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3253 = remapindex_28 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3254 = remapindex_28 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3255 = remapindex_28 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3256 = remapindex_28 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3257 = remapindex_28 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_28 = _T_3257 ? _Queue64_UInt8_31_io_deq_bits : _T_3256 ? _Queue64_UInt8_30_io_deq_bits : _T_3255 ? _Queue64_UInt8_29_io_deq_bits : _T_3254 ? _Queue64_UInt8_28_io_deq_bits : _T_3253 ? _Queue64_UInt8_27_io_deq_bits : _T_3252 ? _Queue64_UInt8_26_io_deq_bits : _T_3251 ? _Queue64_UInt8_25_io_deq_bits : _T_3250 ? _Queue64_UInt8_24_io_deq_bits : _T_3249 ? _Queue64_UInt8_23_io_deq_bits : _T_3248 ? _Queue64_UInt8_22_io_deq_bits : _T_3247 ? _Queue64_UInt8_21_io_deq_bits : _T_3246 ? _Queue64_UInt8_20_io_deq_bits : _T_3245 ? _Queue64_UInt8_19_io_deq_bits : _T_3244 ? _Queue64_UInt8_18_io_deq_bits : _T_3243 ? _Queue64_UInt8_17_io_deq_bits : _T_3242 ? _Queue64_UInt8_16_io_deq_bits : _T_3241 ? _Queue64_UInt8_15_io_deq_bits : _T_3240 ? _Queue64_UInt8_14_io_deq_bits : _T_3239 ? _Queue64_UInt8_13_io_deq_bits : _T_3238 ? _Queue64_UInt8_12_io_deq_bits : _T_3237 ? _Queue64_UInt8_11_io_deq_bits : _T_3236 ? _Queue64_UInt8_10_io_deq_bits : _T_3235 ? _Queue64_UInt8_9_io_deq_bits : _T_3234 ? _Queue64_UInt8_8_io_deq_bits : _T_3233 ? _Queue64_UInt8_7_io_deq_bits : _T_3232 ? _Queue64_UInt8_6_io_deq_bits : _T_3231 ? _Queue64_UInt8_5_io_deq_bits : _T_3230 ? _Queue64_UInt8_4_io_deq_bits : _T_3229 ? _Queue64_UInt8_3_io_deq_bits : _T_3228 ? _Queue64_UInt8_2_io_deq_bits : _T_3227 ? _Queue64_UInt8_1_io_deq_bits : _T_3226 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_28 = _T_3257 ? _Queue64_UInt8_31_io_deq_valid : _T_3256 ? _Queue64_UInt8_30_io_deq_valid : _T_3255 ? _Queue64_UInt8_29_io_deq_valid : _T_3254 ? _Queue64_UInt8_28_io_deq_valid : _T_3253 ? _Queue64_UInt8_27_io_deq_valid : _T_3252 ? _Queue64_UInt8_26_io_deq_valid : _T_3251 ? _Queue64_UInt8_25_io_deq_valid : _T_3250 ? _Queue64_UInt8_24_io_deq_valid : _T_3249 ? _Queue64_UInt8_23_io_deq_valid : _T_3248 ? _Queue64_UInt8_22_io_deq_valid : _T_3247 ? _Queue64_UInt8_21_io_deq_valid : _T_3246 ? _Queue64_UInt8_20_io_deq_valid : _T_3245 ? _Queue64_UInt8_19_io_deq_valid : _T_3244 ? _Queue64_UInt8_18_io_deq_valid : _T_3243 ? _Queue64_UInt8_17_io_deq_valid : _T_3242 ? _Queue64_UInt8_16_io_deq_valid : _T_3241 ? _Queue64_UInt8_15_io_deq_valid : _T_3240 ? _Queue64_UInt8_14_io_deq_valid : _T_3239 ? _Queue64_UInt8_13_io_deq_valid : _T_3238 ? _Queue64_UInt8_12_io_deq_valid : _T_3237 ? _Queue64_UInt8_11_io_deq_valid : _T_3236 ? _Queue64_UInt8_10_io_deq_valid : _T_3235 ? _Queue64_UInt8_9_io_deq_valid : _T_3234 ? _Queue64_UInt8_8_io_deq_valid : _T_3233 ? _Queue64_UInt8_7_io_deq_valid : _T_3232 ? _Queue64_UInt8_6_io_deq_valid : _T_3231 ? _Queue64_UInt8_5_io_deq_valid : _T_3230 ? _Queue64_UInt8_4_io_deq_valid : _T_3229 ? _Queue64_UInt8_3_io_deq_valid : _T_3228 ? _Queue64_UInt8_2_io_deq_valid : _T_3227 ? _Queue64_UInt8_1_io_deq_valid : _T_3226 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_29 = _remapindex_T + 7'h1D; // @[MemLoader.scala:177:33] wire [6:0] _GEN_120 = _remapindex_T_29 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_29 = _GEN_120[5:0]; // @[MemLoader.scala:177:54] wire _T_3258 = remapindex_29 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3259 = remapindex_29 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3260 = remapindex_29 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3261 = remapindex_29 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3262 = remapindex_29 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3263 = remapindex_29 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3264 = remapindex_29 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3265 = remapindex_29 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3266 = remapindex_29 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3267 = remapindex_29 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3268 = remapindex_29 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3269 = remapindex_29 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3270 = remapindex_29 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3271 = remapindex_29 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3272 = remapindex_29 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3273 = remapindex_29 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3274 = remapindex_29 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3275 = remapindex_29 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3276 = remapindex_29 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3277 = remapindex_29 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3278 = remapindex_29 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3279 = remapindex_29 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3280 = remapindex_29 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3281 = remapindex_29 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3282 = remapindex_29 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3283 = remapindex_29 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3284 = remapindex_29 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3285 = remapindex_29 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3286 = remapindex_29 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3287 = remapindex_29 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3288 = remapindex_29 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3289 = remapindex_29 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_29 = _T_3289 ? _Queue64_UInt8_31_io_deq_bits : _T_3288 ? _Queue64_UInt8_30_io_deq_bits : _T_3287 ? _Queue64_UInt8_29_io_deq_bits : _T_3286 ? _Queue64_UInt8_28_io_deq_bits : _T_3285 ? _Queue64_UInt8_27_io_deq_bits : _T_3284 ? _Queue64_UInt8_26_io_deq_bits : _T_3283 ? _Queue64_UInt8_25_io_deq_bits : _T_3282 ? _Queue64_UInt8_24_io_deq_bits : _T_3281 ? _Queue64_UInt8_23_io_deq_bits : _T_3280 ? _Queue64_UInt8_22_io_deq_bits : _T_3279 ? _Queue64_UInt8_21_io_deq_bits : _T_3278 ? _Queue64_UInt8_20_io_deq_bits : _T_3277 ? _Queue64_UInt8_19_io_deq_bits : _T_3276 ? _Queue64_UInt8_18_io_deq_bits : _T_3275 ? _Queue64_UInt8_17_io_deq_bits : _T_3274 ? _Queue64_UInt8_16_io_deq_bits : _T_3273 ? _Queue64_UInt8_15_io_deq_bits : _T_3272 ? _Queue64_UInt8_14_io_deq_bits : _T_3271 ? _Queue64_UInt8_13_io_deq_bits : _T_3270 ? _Queue64_UInt8_12_io_deq_bits : _T_3269 ? _Queue64_UInt8_11_io_deq_bits : _T_3268 ? _Queue64_UInt8_10_io_deq_bits : _T_3267 ? _Queue64_UInt8_9_io_deq_bits : _T_3266 ? _Queue64_UInt8_8_io_deq_bits : _T_3265 ? _Queue64_UInt8_7_io_deq_bits : _T_3264 ? _Queue64_UInt8_6_io_deq_bits : _T_3263 ? _Queue64_UInt8_5_io_deq_bits : _T_3262 ? _Queue64_UInt8_4_io_deq_bits : _T_3261 ? _Queue64_UInt8_3_io_deq_bits : _T_3260 ? _Queue64_UInt8_2_io_deq_bits : _T_3259 ? _Queue64_UInt8_1_io_deq_bits : _T_3258 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_29 = _T_3289 ? _Queue64_UInt8_31_io_deq_valid : _T_3288 ? _Queue64_UInt8_30_io_deq_valid : _T_3287 ? _Queue64_UInt8_29_io_deq_valid : _T_3286 ? _Queue64_UInt8_28_io_deq_valid : _T_3285 ? _Queue64_UInt8_27_io_deq_valid : _T_3284 ? _Queue64_UInt8_26_io_deq_valid : _T_3283 ? _Queue64_UInt8_25_io_deq_valid : _T_3282 ? _Queue64_UInt8_24_io_deq_valid : _T_3281 ? _Queue64_UInt8_23_io_deq_valid : _T_3280 ? _Queue64_UInt8_22_io_deq_valid : _T_3279 ? _Queue64_UInt8_21_io_deq_valid : _T_3278 ? _Queue64_UInt8_20_io_deq_valid : _T_3277 ? _Queue64_UInt8_19_io_deq_valid : _T_3276 ? _Queue64_UInt8_18_io_deq_valid : _T_3275 ? _Queue64_UInt8_17_io_deq_valid : _T_3274 ? _Queue64_UInt8_16_io_deq_valid : _T_3273 ? _Queue64_UInt8_15_io_deq_valid : _T_3272 ? _Queue64_UInt8_14_io_deq_valid : _T_3271 ? _Queue64_UInt8_13_io_deq_valid : _T_3270 ? _Queue64_UInt8_12_io_deq_valid : _T_3269 ? _Queue64_UInt8_11_io_deq_valid : _T_3268 ? _Queue64_UInt8_10_io_deq_valid : _T_3267 ? _Queue64_UInt8_9_io_deq_valid : _T_3266 ? _Queue64_UInt8_8_io_deq_valid : _T_3265 ? _Queue64_UInt8_7_io_deq_valid : _T_3264 ? _Queue64_UInt8_6_io_deq_valid : _T_3263 ? _Queue64_UInt8_5_io_deq_valid : _T_3262 ? _Queue64_UInt8_4_io_deq_valid : _T_3261 ? _Queue64_UInt8_3_io_deq_valid : _T_3260 ? _Queue64_UInt8_2_io_deq_valid : _T_3259 ? _Queue64_UInt8_1_io_deq_valid : _T_3258 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_30 = _remapindex_T + 7'h1E; // @[MemLoader.scala:177:33] wire [6:0] _GEN_121 = _remapindex_T_30 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_30 = _GEN_121[5:0]; // @[MemLoader.scala:177:54] wire _T_3290 = remapindex_30 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3291 = remapindex_30 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3292 = remapindex_30 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3293 = remapindex_30 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3294 = remapindex_30 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3295 = remapindex_30 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3296 = remapindex_30 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3297 = remapindex_30 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3298 = remapindex_30 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3299 = remapindex_30 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3300 = remapindex_30 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3301 = remapindex_30 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3302 = remapindex_30 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3303 = remapindex_30 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3304 = remapindex_30 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3305 = remapindex_30 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3306 = remapindex_30 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3307 = remapindex_30 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3308 = remapindex_30 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3309 = remapindex_30 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3310 = remapindex_30 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3311 = remapindex_30 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3312 = remapindex_30 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3313 = remapindex_30 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3314 = remapindex_30 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3315 = remapindex_30 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3316 = remapindex_30 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3317 = remapindex_30 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3318 = remapindex_30 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3319 = remapindex_30 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3320 = remapindex_30 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3321 = remapindex_30 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_30 = _T_3321 ? _Queue64_UInt8_31_io_deq_bits : _T_3320 ? _Queue64_UInt8_30_io_deq_bits : _T_3319 ? _Queue64_UInt8_29_io_deq_bits : _T_3318 ? _Queue64_UInt8_28_io_deq_bits : _T_3317 ? _Queue64_UInt8_27_io_deq_bits : _T_3316 ? _Queue64_UInt8_26_io_deq_bits : _T_3315 ? _Queue64_UInt8_25_io_deq_bits : _T_3314 ? _Queue64_UInt8_24_io_deq_bits : _T_3313 ? _Queue64_UInt8_23_io_deq_bits : _T_3312 ? _Queue64_UInt8_22_io_deq_bits : _T_3311 ? _Queue64_UInt8_21_io_deq_bits : _T_3310 ? _Queue64_UInt8_20_io_deq_bits : _T_3309 ? _Queue64_UInt8_19_io_deq_bits : _T_3308 ? _Queue64_UInt8_18_io_deq_bits : _T_3307 ? _Queue64_UInt8_17_io_deq_bits : _T_3306 ? _Queue64_UInt8_16_io_deq_bits : _T_3305 ? _Queue64_UInt8_15_io_deq_bits : _T_3304 ? _Queue64_UInt8_14_io_deq_bits : _T_3303 ? _Queue64_UInt8_13_io_deq_bits : _T_3302 ? _Queue64_UInt8_12_io_deq_bits : _T_3301 ? _Queue64_UInt8_11_io_deq_bits : _T_3300 ? _Queue64_UInt8_10_io_deq_bits : _T_3299 ? _Queue64_UInt8_9_io_deq_bits : _T_3298 ? _Queue64_UInt8_8_io_deq_bits : _T_3297 ? _Queue64_UInt8_7_io_deq_bits : _T_3296 ? _Queue64_UInt8_6_io_deq_bits : _T_3295 ? _Queue64_UInt8_5_io_deq_bits : _T_3294 ? _Queue64_UInt8_4_io_deq_bits : _T_3293 ? _Queue64_UInt8_3_io_deq_bits : _T_3292 ? _Queue64_UInt8_2_io_deq_bits : _T_3291 ? _Queue64_UInt8_1_io_deq_bits : _T_3290 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_30 = _T_3321 ? _Queue64_UInt8_31_io_deq_valid : _T_3320 ? _Queue64_UInt8_30_io_deq_valid : _T_3319 ? _Queue64_UInt8_29_io_deq_valid : _T_3318 ? _Queue64_UInt8_28_io_deq_valid : _T_3317 ? _Queue64_UInt8_27_io_deq_valid : _T_3316 ? _Queue64_UInt8_26_io_deq_valid : _T_3315 ? _Queue64_UInt8_25_io_deq_valid : _T_3314 ? _Queue64_UInt8_24_io_deq_valid : _T_3313 ? _Queue64_UInt8_23_io_deq_valid : _T_3312 ? _Queue64_UInt8_22_io_deq_valid : _T_3311 ? _Queue64_UInt8_21_io_deq_valid : _T_3310 ? _Queue64_UInt8_20_io_deq_valid : _T_3309 ? _Queue64_UInt8_19_io_deq_valid : _T_3308 ? _Queue64_UInt8_18_io_deq_valid : _T_3307 ? _Queue64_UInt8_17_io_deq_valid : _T_3306 ? _Queue64_UInt8_16_io_deq_valid : _T_3305 ? _Queue64_UInt8_15_io_deq_valid : _T_3304 ? _Queue64_UInt8_14_io_deq_valid : _T_3303 ? _Queue64_UInt8_13_io_deq_valid : _T_3302 ? _Queue64_UInt8_12_io_deq_valid : _T_3301 ? _Queue64_UInt8_11_io_deq_valid : _T_3300 ? _Queue64_UInt8_10_io_deq_valid : _T_3299 ? _Queue64_UInt8_9_io_deq_valid : _T_3298 ? _Queue64_UInt8_8_io_deq_valid : _T_3297 ? _Queue64_UInt8_7_io_deq_valid : _T_3296 ? _Queue64_UInt8_6_io_deq_valid : _T_3295 ? _Queue64_UInt8_5_io_deq_valid : _T_3294 ? _Queue64_UInt8_4_io_deq_valid : _T_3293 ? _Queue64_UInt8_3_io_deq_valid : _T_3292 ? _Queue64_UInt8_2_io_deq_valid : _T_3291 ? _Queue64_UInt8_1_io_deq_valid : _T_3290 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [6:0] _remapindex_T_31 = _remapindex_T + 7'h1F; // @[MemLoader.scala:177:33] wire [6:0] _GEN_122 = _remapindex_T_31 % 7'h20; // @[MemLoader.scala:177:{33,54}] wire [5:0] remapindex_31 = _GEN_122[5:0]; // @[MemLoader.scala:177:54] wire _T_3322 = remapindex_31 == 6'h0; // @[MemLoader.scala:177:54, :179:17] wire _T_3323 = remapindex_31 == 6'h1; // @[MemLoader.scala:177:54, :179:17] wire _T_3324 = remapindex_31 == 6'h2; // @[MemLoader.scala:177:54, :179:17] wire _T_3325 = remapindex_31 == 6'h3; // @[MemLoader.scala:177:54, :179:17] wire _T_3326 = remapindex_31 == 6'h4; // @[MemLoader.scala:177:54, :179:17] wire _T_3327 = remapindex_31 == 6'h5; // @[MemLoader.scala:177:54, :179:17] wire _T_3328 = remapindex_31 == 6'h6; // @[MemLoader.scala:177:54, :179:17] wire _T_3329 = remapindex_31 == 6'h7; // @[MemLoader.scala:177:54, :179:17] wire _T_3330 = remapindex_31 == 6'h8; // @[MemLoader.scala:177:54, :179:17] wire _T_3331 = remapindex_31 == 6'h9; // @[MemLoader.scala:177:54, :179:17] wire _T_3332 = remapindex_31 == 6'hA; // @[MemLoader.scala:177:54, :179:17] wire _T_3333 = remapindex_31 == 6'hB; // @[MemLoader.scala:177:54, :179:17] wire _T_3334 = remapindex_31 == 6'hC; // @[MemLoader.scala:177:54, :179:17] wire _T_3335 = remapindex_31 == 6'hD; // @[MemLoader.scala:177:54, :179:17] wire _T_3336 = remapindex_31 == 6'hE; // @[MemLoader.scala:177:54, :179:17] wire _T_3337 = remapindex_31 == 6'hF; // @[MemLoader.scala:177:54, :179:17] wire _T_3338 = remapindex_31 == 6'h10; // @[MemLoader.scala:177:54, :179:17] wire _T_3339 = remapindex_31 == 6'h11; // @[MemLoader.scala:177:54, :179:17] wire _T_3340 = remapindex_31 == 6'h12; // @[MemLoader.scala:177:54, :179:17] wire _T_3341 = remapindex_31 == 6'h13; // @[MemLoader.scala:177:54, :179:17] wire _T_3342 = remapindex_31 == 6'h14; // @[MemLoader.scala:177:54, :179:17] wire _T_3343 = remapindex_31 == 6'h15; // @[MemLoader.scala:177:54, :179:17] wire _T_3344 = remapindex_31 == 6'h16; // @[MemLoader.scala:177:54, :179:17] wire _T_3345 = remapindex_31 == 6'h17; // @[MemLoader.scala:177:54, :179:17] wire _T_3346 = remapindex_31 == 6'h18; // @[MemLoader.scala:177:54, :179:17] wire _T_3347 = remapindex_31 == 6'h19; // @[MemLoader.scala:177:54, :179:17] wire _T_3348 = remapindex_31 == 6'h1A; // @[MemLoader.scala:177:54, :179:17] wire _T_3349 = remapindex_31 == 6'h1B; // @[MemLoader.scala:177:54, :179:17] wire _T_3350 = remapindex_31 == 6'h1C; // @[MemLoader.scala:177:54, :179:17] wire _T_3351 = remapindex_31 == 6'h1D; // @[MemLoader.scala:177:54, :179:17] wire _T_3352 = remapindex_31 == 6'h1E; // @[MemLoader.scala:177:54, :179:17] wire _T_3353 = remapindex_31 == 6'h1F; // @[MemLoader.scala:177:54, :179:17] assign remapVecData_31 = _T_3353 ? _Queue64_UInt8_31_io_deq_bits : _T_3352 ? _Queue64_UInt8_30_io_deq_bits : _T_3351 ? _Queue64_UInt8_29_io_deq_bits : _T_3350 ? _Queue64_UInt8_28_io_deq_bits : _T_3349 ? _Queue64_UInt8_27_io_deq_bits : _T_3348 ? _Queue64_UInt8_26_io_deq_bits : _T_3347 ? _Queue64_UInt8_25_io_deq_bits : _T_3346 ? _Queue64_UInt8_24_io_deq_bits : _T_3345 ? _Queue64_UInt8_23_io_deq_bits : _T_3344 ? _Queue64_UInt8_22_io_deq_bits : _T_3343 ? _Queue64_UInt8_21_io_deq_bits : _T_3342 ? _Queue64_UInt8_20_io_deq_bits : _T_3341 ? _Queue64_UInt8_19_io_deq_bits : _T_3340 ? _Queue64_UInt8_18_io_deq_bits : _T_3339 ? _Queue64_UInt8_17_io_deq_bits : _T_3338 ? _Queue64_UInt8_16_io_deq_bits : _T_3337 ? _Queue64_UInt8_15_io_deq_bits : _T_3336 ? _Queue64_UInt8_14_io_deq_bits : _T_3335 ? _Queue64_UInt8_13_io_deq_bits : _T_3334 ? _Queue64_UInt8_12_io_deq_bits : _T_3333 ? _Queue64_UInt8_11_io_deq_bits : _T_3332 ? _Queue64_UInt8_10_io_deq_bits : _T_3331 ? _Queue64_UInt8_9_io_deq_bits : _T_3330 ? _Queue64_UInt8_8_io_deq_bits : _T_3329 ? _Queue64_UInt8_7_io_deq_bits : _T_3328 ? _Queue64_UInt8_6_io_deq_bits : _T_3327 ? _Queue64_UInt8_5_io_deq_bits : _T_3326 ? _Queue64_UInt8_4_io_deq_bits : _T_3325 ? _Queue64_UInt8_3_io_deq_bits : _T_3324 ? _Queue64_UInt8_2_io_deq_bits : _T_3323 ? _Queue64_UInt8_1_io_deq_bits : _T_3322 ? _Queue64_UInt8_io_deq_bits : 8'h0; // @[MemLoader.scala:106:52, :166:26, :171:27, :179:{17,33}, :180:31] assign remapVecValids_31 = _T_3353 ? _Queue64_UInt8_31_io_deq_valid : _T_3352 ? _Queue64_UInt8_30_io_deq_valid : _T_3351 ? _Queue64_UInt8_29_io_deq_valid : _T_3350 ? _Queue64_UInt8_28_io_deq_valid : _T_3349 ? _Queue64_UInt8_27_io_deq_valid : _T_3348 ? _Queue64_UInt8_26_io_deq_valid : _T_3347 ? _Queue64_UInt8_25_io_deq_valid : _T_3346 ? _Queue64_UInt8_24_io_deq_valid : _T_3345 ? _Queue64_UInt8_23_io_deq_valid : _T_3344 ? _Queue64_UInt8_22_io_deq_valid : _T_3343 ? _Queue64_UInt8_21_io_deq_valid : _T_3342 ? _Queue64_UInt8_20_io_deq_valid : _T_3341 ? _Queue64_UInt8_19_io_deq_valid : _T_3340 ? _Queue64_UInt8_18_io_deq_valid : _T_3339 ? _Queue64_UInt8_17_io_deq_valid : _T_3338 ? _Queue64_UInt8_16_io_deq_valid : _T_3337 ? _Queue64_UInt8_15_io_deq_valid : _T_3336 ? _Queue64_UInt8_14_io_deq_valid : _T_3335 ? _Queue64_UInt8_13_io_deq_valid : _T_3334 ? _Queue64_UInt8_12_io_deq_valid : _T_3333 ? _Queue64_UInt8_11_io_deq_valid : _T_3332 ? _Queue64_UInt8_10_io_deq_valid : _T_3331 ? _Queue64_UInt8_9_io_deq_valid : _T_3330 ? _Queue64_UInt8_8_io_deq_valid : _T_3329 ? _Queue64_UInt8_7_io_deq_valid : _T_3328 ? _Queue64_UInt8_6_io_deq_valid : _T_3327 ? _Queue64_UInt8_5_io_deq_valid : _T_3326 ? _Queue64_UInt8_4_io_deq_valid : _T_3325 ? _Queue64_UInt8_3_io_deq_valid : _T_3324 ? _Queue64_UInt8_2_io_deq_valid : _T_3323 ? _Queue64_UInt8_1_io_deq_valid : _T_3322 & _Queue64_UInt8_io_deq_valid; // @[MemLoader.scala:106:52, :167:28, :172:29, :179:{17,33}, :181:33] wire [15:0] io_consumer_output_data_lo_lo_lo_lo = {remapVecData_1, remapVecData_0}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_lo_lo_lo_hi = {remapVecData_3, remapVecData_2}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_lo_lo_lo = {io_consumer_output_data_lo_lo_lo_hi, io_consumer_output_data_lo_lo_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_lo_lo_hi_lo = {remapVecData_5, remapVecData_4}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_lo_lo_hi_hi = {remapVecData_7, remapVecData_6}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_lo_lo_hi = {io_consumer_output_data_lo_lo_hi_hi, io_consumer_output_data_lo_lo_hi_lo}; // @[MemLoader.scala:186:33] wire [63:0] io_consumer_output_data_lo_lo = {io_consumer_output_data_lo_lo_hi, io_consumer_output_data_lo_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_lo_hi_lo_lo = {remapVecData_9, remapVecData_8}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_lo_hi_lo_hi = {remapVecData_11, remapVecData_10}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_lo_hi_lo = {io_consumer_output_data_lo_hi_lo_hi, io_consumer_output_data_lo_hi_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_lo_hi_hi_lo = {remapVecData_13, remapVecData_12}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_lo_hi_hi_hi = {remapVecData_15, remapVecData_14}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_lo_hi_hi = {io_consumer_output_data_lo_hi_hi_hi, io_consumer_output_data_lo_hi_hi_lo}; // @[MemLoader.scala:186:33] wire [63:0] io_consumer_output_data_lo_hi = {io_consumer_output_data_lo_hi_hi, io_consumer_output_data_lo_hi_lo}; // @[MemLoader.scala:186:33] wire [127:0] io_consumer_output_data_lo = {io_consumer_output_data_lo_hi, io_consumer_output_data_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_hi_lo_lo_lo = {remapVecData_17, remapVecData_16}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_hi_lo_lo_hi = {remapVecData_19, remapVecData_18}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_hi_lo_lo = {io_consumer_output_data_hi_lo_lo_hi, io_consumer_output_data_hi_lo_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_hi_lo_hi_lo = {remapVecData_21, remapVecData_20}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_hi_lo_hi_hi = {remapVecData_23, remapVecData_22}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_hi_lo_hi = {io_consumer_output_data_hi_lo_hi_hi, io_consumer_output_data_hi_lo_hi_lo}; // @[MemLoader.scala:186:33] wire [63:0] io_consumer_output_data_hi_lo = {io_consumer_output_data_hi_lo_hi, io_consumer_output_data_hi_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_hi_hi_lo_lo = {remapVecData_25, remapVecData_24}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_hi_hi_lo_hi = {remapVecData_27, remapVecData_26}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_hi_hi_lo = {io_consumer_output_data_hi_hi_lo_hi, io_consumer_output_data_hi_hi_lo_lo}; // @[MemLoader.scala:186:33] wire [15:0] io_consumer_output_data_hi_hi_hi_lo = {remapVecData_29, remapVecData_28}; // @[MemLoader.scala:166:26, :186:33] wire [15:0] io_consumer_output_data_hi_hi_hi_hi = {remapVecData_31, remapVecData_30}; // @[MemLoader.scala:166:26, :186:33] wire [31:0] io_consumer_output_data_hi_hi_hi = {io_consumer_output_data_hi_hi_hi_hi, io_consumer_output_data_hi_hi_hi_lo}; // @[MemLoader.scala:186:33] wire [63:0] io_consumer_output_data_hi_hi = {io_consumer_output_data_hi_hi_hi, io_consumer_output_data_hi_hi_lo}; // @[MemLoader.scala:186:33] wire [127:0] io_consumer_output_data_hi = {io_consumer_output_data_hi_hi, io_consumer_output_data_hi_lo}; // @[MemLoader.scala:186:33] assign _io_consumer_output_data_T = {io_consumer_output_data_hi, io_consumer_output_data_lo}; // @[MemLoader.scala:186:33] assign io_consumer_output_data_0 = _io_consumer_output_data_T; // @[MemLoader.scala:15:7, :186:33] wire [64:0] _GEN_123 = {1'h0, len_already_consumed}; // @[MemLoader.scala:164:37, :189:40] wire [64:0] _GEN_124 = _GEN_123 + {59'h0, io_consumer_user_consumed_bytes_0}; // @[MemLoader.scala:15:7, :189:40] wire [64:0] _buf_last_T; // @[MemLoader.scala:189:40] assign _buf_last_T = _GEN_124; // @[MemLoader.scala:189:40] wire [64:0] _len_already_consumed_T; // @[MemLoader.scala:230:52] assign _len_already_consumed_T = _GEN_124; // @[MemLoader.scala:189:40, :230:52] wire [63:0] _buf_last_T_1 = _buf_last_T[63:0]; // @[MemLoader.scala:189:40] wire buf_last = _buf_last_T_1 == _buf_info_queue_io_deq_bits_len_bytes; // @[MemLoader.scala:26:30, :189:{40,75}] wire [1:0] _count_valids_T = {1'h0, remapVecValids_0} + {1'h0, remapVecValids_1}; // @[MemLoader.scala:167:28, :190:60] wire [2:0] _count_valids_T_1 = {1'h0, _count_valids_T} + {2'h0, remapVecValids_2}; // @[MemLoader.scala:167:28, :190:60] wire [3:0] _count_valids_T_2 = {1'h0, _count_valids_T_1} + {3'h0, remapVecValids_3}; // @[MemLoader.scala:167:28, :190:60] wire [4:0] _count_valids_T_3 = {1'h0, _count_valids_T_2} + {4'h0, remapVecValids_4}; // @[MemLoader.scala:167:28, :190:60] wire [5:0] _count_valids_T_4 = {1'h0, _count_valids_T_3} + {5'h0, remapVecValids_5}; // @[MemLoader.scala:167:28, :190:60] wire [6:0] _count_valids_T_5 = {1'h0, _count_valids_T_4} + {6'h0, remapVecValids_6}; // @[MemLoader.scala:167:28, :190:60] wire [7:0] _count_valids_T_6 = {1'h0, _count_valids_T_5} + {7'h0, remapVecValids_7}; // @[MemLoader.scala:167:28, :190:60] wire [8:0] _count_valids_T_7 = {1'h0, _count_valids_T_6} + {8'h0, remapVecValids_8}; // @[MemLoader.scala:167:28, :190:60] wire [9:0] _count_valids_T_8 = {1'h0, _count_valids_T_7} + {9'h0, remapVecValids_9}; // @[MemLoader.scala:167:28, :190:60] wire [10:0] _count_valids_T_9 = {1'h0, _count_valids_T_8} + {10'h0, remapVecValids_10}; // @[MemLoader.scala:167:28, :190:60] wire [11:0] _count_valids_T_10 = {1'h0, _count_valids_T_9} + {11'h0, remapVecValids_11}; // @[MemLoader.scala:167:28, :190:60] wire [12:0] _count_valids_T_11 = {1'h0, _count_valids_T_10} + {12'h0, remapVecValids_12}; // @[MemLoader.scala:167:28, :190:60] wire [13:0] _count_valids_T_12 = {1'h0, _count_valids_T_11} + {13'h0, remapVecValids_13}; // @[MemLoader.scala:167:28, :190:60] wire [14:0] _count_valids_T_13 = {1'h0, _count_valids_T_12} + {14'h0, remapVecValids_14}; // @[MemLoader.scala:167:28, :190:60] wire [15:0] _count_valids_T_14 = {1'h0, _count_valids_T_13} + {15'h0, remapVecValids_15}; // @[MemLoader.scala:167:28, :190:60] wire [16:0] _count_valids_T_15 = {1'h0, _count_valids_T_14} + {16'h0, remapVecValids_16}; // @[MemLoader.scala:167:28, :190:60] wire [17:0] _count_valids_T_16 = {1'h0, _count_valids_T_15} + {17'h0, remapVecValids_17}; // @[MemLoader.scala:167:28, :190:60] wire [18:0] _count_valids_T_17 = {1'h0, _count_valids_T_16} + {18'h0, remapVecValids_18}; // @[MemLoader.scala:167:28, :190:60] wire [19:0] _count_valids_T_18 = {1'h0, _count_valids_T_17} + {19'h0, remapVecValids_19}; // @[MemLoader.scala:167:28, :190:60] wire [20:0] _count_valids_T_19 = {1'h0, _count_valids_T_18} + {20'h0, remapVecValids_20}; // @[MemLoader.scala:167:28, :190:60] wire [21:0] _count_valids_T_20 = {1'h0, _count_valids_T_19} + {21'h0, remapVecValids_21}; // @[MemLoader.scala:167:28, :190:60] wire [22:0] _count_valids_T_21 = {1'h0, _count_valids_T_20} + {22'h0, remapVecValids_22}; // @[MemLoader.scala:167:28, :190:60] wire [23:0] _count_valids_T_22 = {1'h0, _count_valids_T_21} + {23'h0, remapVecValids_23}; // @[MemLoader.scala:167:28, :190:60] wire [24:0] _count_valids_T_23 = {1'h0, _count_valids_T_22} + {24'h0, remapVecValids_24}; // @[MemLoader.scala:167:28, :190:60] wire [25:0] _count_valids_T_24 = {1'h0, _count_valids_T_23} + {25'h0, remapVecValids_25}; // @[MemLoader.scala:167:28, :190:60] wire [26:0] _count_valids_T_25 = {1'h0, _count_valids_T_24} + {26'h0, remapVecValids_26}; // @[MemLoader.scala:167:28, :190:60] wire [27:0] _count_valids_T_26 = {1'h0, _count_valids_T_25} + {27'h0, remapVecValids_27}; // @[MemLoader.scala:167:28, :190:60] wire [28:0] _count_valids_T_27 = {1'h0, _count_valids_T_26} + {28'h0, remapVecValids_28}; // @[MemLoader.scala:167:28, :190:60] wire [29:0] _count_valids_T_28 = {1'h0, _count_valids_T_27} + {29'h0, remapVecValids_29}; // @[MemLoader.scala:167:28, :190:60] wire [30:0] _count_valids_T_29 = {1'h0, _count_valids_T_28} + {30'h0, remapVecValids_30}; // @[MemLoader.scala:167:28, :190:60] wire [31:0] count_valids = {1'h0, _count_valids_T_29} + {31'h0, remapVecValids_31}; // @[MemLoader.scala:167:28, :190:60] wire [64:0] _unconsumed_bytes_so_far_T = {1'h0, _buf_info_queue_io_deq_bits_len_bytes} - _GEN_123; // @[MemLoader.scala:26:30, :189:40, :191:70] wire [63:0] unconsumed_bytes_so_far = _unconsumed_bytes_so_far_T[63:0]; // @[MemLoader.scala:191:70] wire _enough_data_T = |(unconsumed_bytes_so_far[63:5]); // @[MemLoader.scala:191:70, :193:49] wire _enough_data_T_1 = count_valids == 32'h20; // @[MemLoader.scala:190:60, :194:38] wire _enough_data_T_2 = {32'h0, count_valids} >= unconsumed_bytes_so_far; // @[MemLoader.scala:190:60, :191:70, :195:38] wire enough_data = _enough_data_T ? _enough_data_T_1 : _enough_data_T_2; // @[MemLoader.scala:193:{24,49}, :194:38, :195:38] wire _io_consumer_available_output_bytes_T = |(unconsumed_bytes_so_far[63:5]); // @[MemLoader.scala:191:70, :193:49, :197:69] wire [63:0] _io_consumer_available_output_bytes_T_1 = _io_consumer_available_output_bytes_T ? 64'h20 : unconsumed_bytes_so_far; // @[MemLoader.scala:191:70, :197:{44,69}] assign io_consumer_available_output_bytes_0 = _io_consumer_available_output_bytes_T_1[5:0]; // @[MemLoader.scala:15:7, :197:{38,44}] assign _io_consumer_output_last_chunk_T = unconsumed_bytes_so_far < 64'h21; // @[MemLoader.scala:191:70, :201:61] assign io_consumer_output_last_chunk_0 = _io_consumer_output_last_chunk_T; // @[MemLoader.scala:15:7, :201:61] wire _T_3362 = io_consumer_output_ready_0 & _buf_info_queue_io_deq_valid; // @[Misc.scala:29:18] wire _remapVecReadys_0_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_0_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_1_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_1_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_2_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_2_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_3_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_3_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_4_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_4_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_5_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_5_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_6_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_6_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_7_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_7_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_8_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_8_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_9_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_9_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_10_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_10_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_11_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_11_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_12_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_12_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_13_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_13_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_14_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_14_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_15_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_15_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_16_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_16_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_17_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_17_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_18_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_18_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_19_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_19_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_20_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_20_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_21_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_21_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_22_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_22_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_23_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_23_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_24_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_24_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_25_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_25_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_26_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_26_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_27_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_27_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_28_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_28_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_29_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_29_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_30_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_30_T_1 = _T_3362; // @[Misc.scala:29:18] wire _remapVecReadys_31_T_1; // @[Misc.scala:29:18] assign _remapVecReadys_31_T_1 = _T_3362; // @[Misc.scala:29:18] reg [63:0] loginfo_cycles_44; // @[Util.scala:18:33] wire [64:0] _loginfo_cycles_T_88 = {1'h0, loginfo_cycles_44} + 65'h1; // @[Util.scala:18:33, :19:38] wire [63:0] _loginfo_cycles_T_89 = _loginfo_cycles_T_88[63:0]; // @[Util.scala:19:38]
Generate the Verilog code corresponding to this FIRRTL code module BankedStore : input clock : Clock input reset : Reset output io : { flip sinkC_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip sinkC_dat : { data : UInt<64>}, flip sinkD_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip sinkD_dat : { data : UInt<64>}, flip sourceC_adr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, sourceC_dat : { data : UInt<64>}, flip sourceD_radr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, sourceD_rdat : { data : UInt<64>}, flip sourceD_wadr : { flip ready : UInt<1>, valid : UInt<1>, bits : { noop : UInt<1>, way : UInt<3>, set : UInt<10>, beat : UInt<3>, mask : UInt<1>}}, flip sourceD_wdat : { data : UInt<64>}} smem cc_banks_0 : UInt<64> [16384] smem cc_banks_1 : UInt<64> [16384] smem cc_banks_2 : UInt<64> [16384] smem cc_banks_3 : UInt<64> [16384] node sinkC_req_words_0 = bits(io.sinkC_dat.data, 63, 0) node sinkC_req_a_hi = cat(io.sinkC_adr.bits.way, io.sinkC_adr.bits.set) node sinkC_req_a = cat(sinkC_req_a_hi, io.sinkC_adr.bits.beat) wire sinkC_req : { wen : UInt<1>, index : UInt<14>, bankSel : UInt<4>, bankSum : UInt<4>, bankEn : UInt<4>, data : UInt<64>[4]} node _sinkC_req_select_T = bits(sinkC_req_a, 1, 0) node sinkC_req_select_shiftAmount = bits(_sinkC_req_select_T, 1, 0) node _sinkC_req_select_T_1 = dshl(UInt<1>(0h1), sinkC_req_select_shiftAmount) node sinkC_req_select = bits(_sinkC_req_select_T_1, 3, 0) node _sinkC_req_ready_T = bits(sinkC_req.bankSum, 0, 0) node _sinkC_req_ready_T_1 = and(_sinkC_req_ready_T, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_2 = orr(_sinkC_req_ready_T_1) node _sinkC_req_ready_T_3 = eq(_sinkC_req_ready_T_2, UInt<1>(0h0)) node _sinkC_req_ready_T_4 = bits(sinkC_req.bankSum, 1, 1) node _sinkC_req_ready_T_5 = and(_sinkC_req_ready_T_4, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_6 = orr(_sinkC_req_ready_T_5) node _sinkC_req_ready_T_7 = eq(_sinkC_req_ready_T_6, UInt<1>(0h0)) node _sinkC_req_ready_T_8 = bits(sinkC_req.bankSum, 2, 2) node _sinkC_req_ready_T_9 = and(_sinkC_req_ready_T_8, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_10 = orr(_sinkC_req_ready_T_9) node _sinkC_req_ready_T_11 = eq(_sinkC_req_ready_T_10, UInt<1>(0h0)) node _sinkC_req_ready_T_12 = bits(sinkC_req.bankSum, 3, 3) node _sinkC_req_ready_T_13 = and(_sinkC_req_ready_T_12, io.sinkC_adr.bits.mask) node _sinkC_req_ready_T_14 = orr(_sinkC_req_ready_T_13) node _sinkC_req_ready_T_15 = eq(_sinkC_req_ready_T_14, UInt<1>(0h0)) node sinkC_req_ready_lo = cat(_sinkC_req_ready_T_7, _sinkC_req_ready_T_3) node sinkC_req_ready_hi = cat(_sinkC_req_ready_T_15, _sinkC_req_ready_T_11) node sinkC_req_ready = cat(sinkC_req_ready_hi, sinkC_req_ready_lo) node _sinkC_req_io_sinkC_adr_ready_T = bits(sinkC_req_a, 1, 0) node _sinkC_req_io_sinkC_adr_ready_T_1 = dshr(sinkC_req_ready, _sinkC_req_io_sinkC_adr_ready_T) node _sinkC_req_io_sinkC_adr_ready_T_2 = bits(_sinkC_req_io_sinkC_adr_ready_T_1, 0, 0) connect io.sinkC_adr.ready, _sinkC_req_io_sinkC_adr_ready_T_2 connect sinkC_req.wen, UInt<1>(0h1) node _sinkC_req_out_index_T = shr(sinkC_req_a, 2) connect sinkC_req.index, _sinkC_req_out_index_T node _sinkC_req_out_bankSel_T = bits(sinkC_req_select, 0, 0) node _sinkC_req_out_bankSel_T_1 = bits(sinkC_req_select, 1, 1) node _sinkC_req_out_bankSel_T_2 = bits(sinkC_req_select, 2, 2) node _sinkC_req_out_bankSel_T_3 = bits(sinkC_req_select, 3, 3) node sinkC_req_out_bankSel_lo = cat(_sinkC_req_out_bankSel_T_1, _sinkC_req_out_bankSel_T) node sinkC_req_out_bankSel_hi = cat(_sinkC_req_out_bankSel_T_3, _sinkC_req_out_bankSel_T_2) node _sinkC_req_out_bankSel_T_4 = cat(sinkC_req_out_bankSel_hi, sinkC_req_out_bankSel_lo) node _sinkC_req_out_bankSel_T_5 = bits(io.sinkC_adr.bits.mask, 0, 0) node _sinkC_req_out_bankSel_T_6 = mux(_sinkC_req_out_bankSel_T_5, UInt<4>(0hf), UInt<4>(0h0)) node _sinkC_req_out_bankSel_T_7 = and(_sinkC_req_out_bankSel_T_4, _sinkC_req_out_bankSel_T_6) node _sinkC_req_out_bankSel_T_8 = mux(io.sinkC_adr.valid, _sinkC_req_out_bankSel_T_7, UInt<1>(0h0)) connect sinkC_req.bankSel, _sinkC_req_out_bankSel_T_8 node _sinkC_req_out_bankEn_T = bits(sinkC_req_ready, 0, 0) node _sinkC_req_out_bankEn_T_1 = bits(sinkC_req_ready, 1, 1) node _sinkC_req_out_bankEn_T_2 = bits(sinkC_req_ready, 2, 2) node _sinkC_req_out_bankEn_T_3 = bits(sinkC_req_ready, 3, 3) node sinkC_req_out_bankEn_lo = cat(_sinkC_req_out_bankEn_T_1, _sinkC_req_out_bankEn_T) node sinkC_req_out_bankEn_hi = cat(_sinkC_req_out_bankEn_T_3, _sinkC_req_out_bankEn_T_2) node _sinkC_req_out_bankEn_T_4 = cat(sinkC_req_out_bankEn_hi, sinkC_req_out_bankEn_lo) node _sinkC_req_out_bankEn_T_5 = and(sinkC_req.bankSel, _sinkC_req_out_bankEn_T_4) node _sinkC_req_out_bankEn_T_6 = mux(io.sinkC_adr.bits.noop, UInt<1>(0h0), _sinkC_req_out_bankEn_T_5) connect sinkC_req.bankEn, _sinkC_req_out_bankEn_T_6 connect sinkC_req.data[0], sinkC_req_words_0 connect sinkC_req.data[1], sinkC_req_words_0 connect sinkC_req.data[2], sinkC_req_words_0 connect sinkC_req.data[3], sinkC_req_words_0 node sinkD_req_words_0 = bits(io.sinkD_dat.data, 63, 0) node sinkD_req_a_hi = cat(io.sinkD_adr.bits.way, io.sinkD_adr.bits.set) node sinkD_req_a = cat(sinkD_req_a_hi, io.sinkD_adr.bits.beat) wire sinkD_req : { wen : UInt<1>, index : UInt<14>, bankSel : UInt<4>, bankSum : UInt<4>, bankEn : UInt<4>, data : UInt<64>[4]} node _sinkD_req_select_T = bits(sinkD_req_a, 1, 0) node sinkD_req_select_shiftAmount = bits(_sinkD_req_select_T, 1, 0) node _sinkD_req_select_T_1 = dshl(UInt<1>(0h1), sinkD_req_select_shiftAmount) node sinkD_req_select = bits(_sinkD_req_select_T_1, 3, 0) node _sinkD_req_ready_T = bits(sinkD_req.bankSum, 0, 0) node _sinkD_req_ready_T_1 = and(_sinkD_req_ready_T, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_2 = orr(_sinkD_req_ready_T_1) node _sinkD_req_ready_T_3 = eq(_sinkD_req_ready_T_2, UInt<1>(0h0)) node _sinkD_req_ready_T_4 = bits(sinkD_req.bankSum, 1, 1) node _sinkD_req_ready_T_5 = and(_sinkD_req_ready_T_4, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_6 = orr(_sinkD_req_ready_T_5) node _sinkD_req_ready_T_7 = eq(_sinkD_req_ready_T_6, UInt<1>(0h0)) node _sinkD_req_ready_T_8 = bits(sinkD_req.bankSum, 2, 2) node _sinkD_req_ready_T_9 = and(_sinkD_req_ready_T_8, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_10 = orr(_sinkD_req_ready_T_9) node _sinkD_req_ready_T_11 = eq(_sinkD_req_ready_T_10, UInt<1>(0h0)) node _sinkD_req_ready_T_12 = bits(sinkD_req.bankSum, 3, 3) node _sinkD_req_ready_T_13 = and(_sinkD_req_ready_T_12, io.sinkD_adr.bits.mask) node _sinkD_req_ready_T_14 = orr(_sinkD_req_ready_T_13) node _sinkD_req_ready_T_15 = eq(_sinkD_req_ready_T_14, UInt<1>(0h0)) node sinkD_req_ready_lo = cat(_sinkD_req_ready_T_7, _sinkD_req_ready_T_3) node sinkD_req_ready_hi = cat(_sinkD_req_ready_T_15, _sinkD_req_ready_T_11) node sinkD_req_ready = cat(sinkD_req_ready_hi, sinkD_req_ready_lo) node _sinkD_req_io_sinkD_adr_ready_T = bits(sinkD_req_a, 1, 0) node _sinkD_req_io_sinkD_adr_ready_T_1 = dshr(sinkD_req_ready, _sinkD_req_io_sinkD_adr_ready_T) node _sinkD_req_io_sinkD_adr_ready_T_2 = bits(_sinkD_req_io_sinkD_adr_ready_T_1, 0, 0) connect io.sinkD_adr.ready, _sinkD_req_io_sinkD_adr_ready_T_2 connect sinkD_req.wen, UInt<1>(0h1) node _sinkD_req_out_index_T = shr(sinkD_req_a, 2) connect sinkD_req.index, _sinkD_req_out_index_T node _sinkD_req_out_bankSel_T = bits(sinkD_req_select, 0, 0) node _sinkD_req_out_bankSel_T_1 = bits(sinkD_req_select, 1, 1) node _sinkD_req_out_bankSel_T_2 = bits(sinkD_req_select, 2, 2) node _sinkD_req_out_bankSel_T_3 = bits(sinkD_req_select, 3, 3) node sinkD_req_out_bankSel_lo = cat(_sinkD_req_out_bankSel_T_1, _sinkD_req_out_bankSel_T) node sinkD_req_out_bankSel_hi = cat(_sinkD_req_out_bankSel_T_3, _sinkD_req_out_bankSel_T_2) node _sinkD_req_out_bankSel_T_4 = cat(sinkD_req_out_bankSel_hi, sinkD_req_out_bankSel_lo) node _sinkD_req_out_bankSel_T_5 = bits(io.sinkD_adr.bits.mask, 0, 0) node _sinkD_req_out_bankSel_T_6 = mux(_sinkD_req_out_bankSel_T_5, UInt<4>(0hf), UInt<4>(0h0)) node _sinkD_req_out_bankSel_T_7 = and(_sinkD_req_out_bankSel_T_4, _sinkD_req_out_bankSel_T_6) node _sinkD_req_out_bankSel_T_8 = mux(io.sinkD_adr.valid, _sinkD_req_out_bankSel_T_7, UInt<1>(0h0)) connect sinkD_req.bankSel, _sinkD_req_out_bankSel_T_8 node _sinkD_req_out_bankEn_T = bits(sinkD_req_ready, 0, 0) node _sinkD_req_out_bankEn_T_1 = bits(sinkD_req_ready, 1, 1) node _sinkD_req_out_bankEn_T_2 = bits(sinkD_req_ready, 2, 2) node _sinkD_req_out_bankEn_T_3 = bits(sinkD_req_ready, 3, 3) node sinkD_req_out_bankEn_lo = cat(_sinkD_req_out_bankEn_T_1, _sinkD_req_out_bankEn_T) node sinkD_req_out_bankEn_hi = cat(_sinkD_req_out_bankEn_T_3, _sinkD_req_out_bankEn_T_2) node _sinkD_req_out_bankEn_T_4 = cat(sinkD_req_out_bankEn_hi, sinkD_req_out_bankEn_lo) node _sinkD_req_out_bankEn_T_5 = and(sinkD_req.bankSel, _sinkD_req_out_bankEn_T_4) node _sinkD_req_out_bankEn_T_6 = mux(io.sinkD_adr.bits.noop, UInt<1>(0h0), _sinkD_req_out_bankEn_T_5) connect sinkD_req.bankEn, _sinkD_req_out_bankEn_T_6 connect sinkD_req.data[0], sinkD_req_words_0 connect sinkD_req.data[1], sinkD_req_words_0 connect sinkD_req.data[2], sinkD_req_words_0 connect sinkD_req.data[3], sinkD_req_words_0 node sourceC_req_a_hi = cat(io.sourceC_adr.bits.way, io.sourceC_adr.bits.set) node sourceC_req_a = cat(sourceC_req_a_hi, io.sourceC_adr.bits.beat) wire sourceC_req : { wen : UInt<1>, index : UInt<14>, bankSel : UInt<4>, bankSum : UInt<4>, bankEn : UInt<4>, data : UInt<64>[4]} node _sourceC_req_select_T = bits(sourceC_req_a, 1, 0) node sourceC_req_select_shiftAmount = bits(_sourceC_req_select_T, 1, 0) node _sourceC_req_select_T_1 = dshl(UInt<1>(0h1), sourceC_req_select_shiftAmount) node sourceC_req_select = bits(_sourceC_req_select_T_1, 3, 0) node _sourceC_req_ready_T = bits(sourceC_req.bankSum, 0, 0) node _sourceC_req_ready_T_1 = and(_sourceC_req_ready_T, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_2 = orr(_sourceC_req_ready_T_1) node _sourceC_req_ready_T_3 = eq(_sourceC_req_ready_T_2, UInt<1>(0h0)) node _sourceC_req_ready_T_4 = bits(sourceC_req.bankSum, 1, 1) node _sourceC_req_ready_T_5 = and(_sourceC_req_ready_T_4, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_6 = orr(_sourceC_req_ready_T_5) node _sourceC_req_ready_T_7 = eq(_sourceC_req_ready_T_6, UInt<1>(0h0)) node _sourceC_req_ready_T_8 = bits(sourceC_req.bankSum, 2, 2) node _sourceC_req_ready_T_9 = and(_sourceC_req_ready_T_8, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_10 = orr(_sourceC_req_ready_T_9) node _sourceC_req_ready_T_11 = eq(_sourceC_req_ready_T_10, UInt<1>(0h0)) node _sourceC_req_ready_T_12 = bits(sourceC_req.bankSum, 3, 3) node _sourceC_req_ready_T_13 = and(_sourceC_req_ready_T_12, io.sourceC_adr.bits.mask) node _sourceC_req_ready_T_14 = orr(_sourceC_req_ready_T_13) node _sourceC_req_ready_T_15 = eq(_sourceC_req_ready_T_14, UInt<1>(0h0)) node sourceC_req_ready_lo = cat(_sourceC_req_ready_T_7, _sourceC_req_ready_T_3) node sourceC_req_ready_hi = cat(_sourceC_req_ready_T_15, _sourceC_req_ready_T_11) node sourceC_req_ready = cat(sourceC_req_ready_hi, sourceC_req_ready_lo) node _sourceC_req_io_sourceC_adr_ready_T = bits(sourceC_req_a, 1, 0) node _sourceC_req_io_sourceC_adr_ready_T_1 = dshr(sourceC_req_ready, _sourceC_req_io_sourceC_adr_ready_T) node _sourceC_req_io_sourceC_adr_ready_T_2 = bits(_sourceC_req_io_sourceC_adr_ready_T_1, 0, 0) connect io.sourceC_adr.ready, _sourceC_req_io_sourceC_adr_ready_T_2 connect sourceC_req.wen, UInt<1>(0h0) node _sourceC_req_out_index_T = shr(sourceC_req_a, 2) connect sourceC_req.index, _sourceC_req_out_index_T node _sourceC_req_out_bankSel_T = bits(sourceC_req_select, 0, 0) node _sourceC_req_out_bankSel_T_1 = bits(sourceC_req_select, 1, 1) node _sourceC_req_out_bankSel_T_2 = bits(sourceC_req_select, 2, 2) node _sourceC_req_out_bankSel_T_3 = bits(sourceC_req_select, 3, 3) node sourceC_req_out_bankSel_lo = cat(_sourceC_req_out_bankSel_T_1, _sourceC_req_out_bankSel_T) node sourceC_req_out_bankSel_hi = cat(_sourceC_req_out_bankSel_T_3, _sourceC_req_out_bankSel_T_2) node _sourceC_req_out_bankSel_T_4 = cat(sourceC_req_out_bankSel_hi, sourceC_req_out_bankSel_lo) node _sourceC_req_out_bankSel_T_5 = bits(io.sourceC_adr.bits.mask, 0, 0) node _sourceC_req_out_bankSel_T_6 = mux(_sourceC_req_out_bankSel_T_5, UInt<4>(0hf), UInt<4>(0h0)) node _sourceC_req_out_bankSel_T_7 = and(_sourceC_req_out_bankSel_T_4, _sourceC_req_out_bankSel_T_6) node _sourceC_req_out_bankSel_T_8 = mux(io.sourceC_adr.valid, _sourceC_req_out_bankSel_T_7, UInt<1>(0h0)) connect sourceC_req.bankSel, _sourceC_req_out_bankSel_T_8 node _sourceC_req_out_bankEn_T = bits(sourceC_req_ready, 0, 0) node _sourceC_req_out_bankEn_T_1 = bits(sourceC_req_ready, 1, 1) node _sourceC_req_out_bankEn_T_2 = bits(sourceC_req_ready, 2, 2) node _sourceC_req_out_bankEn_T_3 = bits(sourceC_req_ready, 3, 3) node sourceC_req_out_bankEn_lo = cat(_sourceC_req_out_bankEn_T_1, _sourceC_req_out_bankEn_T) node sourceC_req_out_bankEn_hi = cat(_sourceC_req_out_bankEn_T_3, _sourceC_req_out_bankEn_T_2) node _sourceC_req_out_bankEn_T_4 = cat(sourceC_req_out_bankEn_hi, sourceC_req_out_bankEn_lo) node _sourceC_req_out_bankEn_T_5 = and(sourceC_req.bankSel, _sourceC_req_out_bankEn_T_4) node _sourceC_req_out_bankEn_T_6 = mux(io.sourceC_adr.bits.noop, UInt<1>(0h0), _sourceC_req_out_bankEn_T_5) connect sourceC_req.bankEn, _sourceC_req_out_bankEn_T_6 connect sourceC_req.data[0], UInt<64>(0h0) connect sourceC_req.data[1], UInt<64>(0h0) connect sourceC_req.data[2], UInt<64>(0h0) connect sourceC_req.data[3], UInt<64>(0h0) node sourceD_rreq_a_hi = cat(io.sourceD_radr.bits.way, io.sourceD_radr.bits.set) node sourceD_rreq_a = cat(sourceD_rreq_a_hi, io.sourceD_radr.bits.beat) wire sourceD_rreq : { wen : UInt<1>, index : UInt<14>, bankSel : UInt<4>, bankSum : UInt<4>, bankEn : UInt<4>, data : UInt<64>[4]} node _sourceD_rreq_select_T = bits(sourceD_rreq_a, 1, 0) node sourceD_rreq_select_shiftAmount = bits(_sourceD_rreq_select_T, 1, 0) node _sourceD_rreq_select_T_1 = dshl(UInt<1>(0h1), sourceD_rreq_select_shiftAmount) node sourceD_rreq_select = bits(_sourceD_rreq_select_T_1, 3, 0) node _sourceD_rreq_ready_T = bits(sourceD_rreq.bankSum, 0, 0) node _sourceD_rreq_ready_T_1 = and(_sourceD_rreq_ready_T, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_2 = orr(_sourceD_rreq_ready_T_1) node _sourceD_rreq_ready_T_3 = eq(_sourceD_rreq_ready_T_2, UInt<1>(0h0)) node _sourceD_rreq_ready_T_4 = bits(sourceD_rreq.bankSum, 1, 1) node _sourceD_rreq_ready_T_5 = and(_sourceD_rreq_ready_T_4, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_6 = orr(_sourceD_rreq_ready_T_5) node _sourceD_rreq_ready_T_7 = eq(_sourceD_rreq_ready_T_6, UInt<1>(0h0)) node _sourceD_rreq_ready_T_8 = bits(sourceD_rreq.bankSum, 2, 2) node _sourceD_rreq_ready_T_9 = and(_sourceD_rreq_ready_T_8, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_10 = orr(_sourceD_rreq_ready_T_9) node _sourceD_rreq_ready_T_11 = eq(_sourceD_rreq_ready_T_10, UInt<1>(0h0)) node _sourceD_rreq_ready_T_12 = bits(sourceD_rreq.bankSum, 3, 3) node _sourceD_rreq_ready_T_13 = and(_sourceD_rreq_ready_T_12, io.sourceD_radr.bits.mask) node _sourceD_rreq_ready_T_14 = orr(_sourceD_rreq_ready_T_13) node _sourceD_rreq_ready_T_15 = eq(_sourceD_rreq_ready_T_14, UInt<1>(0h0)) node sourceD_rreq_ready_lo = cat(_sourceD_rreq_ready_T_7, _sourceD_rreq_ready_T_3) node sourceD_rreq_ready_hi = cat(_sourceD_rreq_ready_T_15, _sourceD_rreq_ready_T_11) node sourceD_rreq_ready = cat(sourceD_rreq_ready_hi, sourceD_rreq_ready_lo) node _sourceD_rreq_io_sourceD_radr_ready_T = bits(sourceD_rreq_a, 1, 0) node _sourceD_rreq_io_sourceD_radr_ready_T_1 = dshr(sourceD_rreq_ready, _sourceD_rreq_io_sourceD_radr_ready_T) node _sourceD_rreq_io_sourceD_radr_ready_T_2 = bits(_sourceD_rreq_io_sourceD_radr_ready_T_1, 0, 0) connect io.sourceD_radr.ready, _sourceD_rreq_io_sourceD_radr_ready_T_2 connect sourceD_rreq.wen, UInt<1>(0h0) node _sourceD_rreq_out_index_T = shr(sourceD_rreq_a, 2) connect sourceD_rreq.index, _sourceD_rreq_out_index_T node _sourceD_rreq_out_bankSel_T = bits(sourceD_rreq_select, 0, 0) node _sourceD_rreq_out_bankSel_T_1 = bits(sourceD_rreq_select, 1, 1) node _sourceD_rreq_out_bankSel_T_2 = bits(sourceD_rreq_select, 2, 2) node _sourceD_rreq_out_bankSel_T_3 = bits(sourceD_rreq_select, 3, 3) node sourceD_rreq_out_bankSel_lo = cat(_sourceD_rreq_out_bankSel_T_1, _sourceD_rreq_out_bankSel_T) node sourceD_rreq_out_bankSel_hi = cat(_sourceD_rreq_out_bankSel_T_3, _sourceD_rreq_out_bankSel_T_2) node _sourceD_rreq_out_bankSel_T_4 = cat(sourceD_rreq_out_bankSel_hi, sourceD_rreq_out_bankSel_lo) node _sourceD_rreq_out_bankSel_T_5 = bits(io.sourceD_radr.bits.mask, 0, 0) node _sourceD_rreq_out_bankSel_T_6 = mux(_sourceD_rreq_out_bankSel_T_5, UInt<4>(0hf), UInt<4>(0h0)) node _sourceD_rreq_out_bankSel_T_7 = and(_sourceD_rreq_out_bankSel_T_4, _sourceD_rreq_out_bankSel_T_6) node _sourceD_rreq_out_bankSel_T_8 = mux(io.sourceD_radr.valid, _sourceD_rreq_out_bankSel_T_7, UInt<1>(0h0)) connect sourceD_rreq.bankSel, _sourceD_rreq_out_bankSel_T_8 node _sourceD_rreq_out_bankEn_T = bits(sourceD_rreq_ready, 0, 0) node _sourceD_rreq_out_bankEn_T_1 = bits(sourceD_rreq_ready, 1, 1) node _sourceD_rreq_out_bankEn_T_2 = bits(sourceD_rreq_ready, 2, 2) node _sourceD_rreq_out_bankEn_T_3 = bits(sourceD_rreq_ready, 3, 3) node sourceD_rreq_out_bankEn_lo = cat(_sourceD_rreq_out_bankEn_T_1, _sourceD_rreq_out_bankEn_T) node sourceD_rreq_out_bankEn_hi = cat(_sourceD_rreq_out_bankEn_T_3, _sourceD_rreq_out_bankEn_T_2) node _sourceD_rreq_out_bankEn_T_4 = cat(sourceD_rreq_out_bankEn_hi, sourceD_rreq_out_bankEn_lo) node _sourceD_rreq_out_bankEn_T_5 = and(sourceD_rreq.bankSel, _sourceD_rreq_out_bankEn_T_4) node _sourceD_rreq_out_bankEn_T_6 = mux(io.sourceD_radr.bits.noop, UInt<1>(0h0), _sourceD_rreq_out_bankEn_T_5) connect sourceD_rreq.bankEn, _sourceD_rreq_out_bankEn_T_6 connect sourceD_rreq.data[0], UInt<64>(0h0) connect sourceD_rreq.data[1], UInt<64>(0h0) connect sourceD_rreq.data[2], UInt<64>(0h0) connect sourceD_rreq.data[3], UInt<64>(0h0) node sourceD_wreq_words_0 = bits(io.sourceD_wdat.data, 63, 0) node sourceD_wreq_a_hi = cat(io.sourceD_wadr.bits.way, io.sourceD_wadr.bits.set) node sourceD_wreq_a = cat(sourceD_wreq_a_hi, io.sourceD_wadr.bits.beat) wire sourceD_wreq : { wen : UInt<1>, index : UInt<14>, bankSel : UInt<4>, bankSum : UInt<4>, bankEn : UInt<4>, data : UInt<64>[4]} node _sourceD_wreq_select_T = bits(sourceD_wreq_a, 1, 0) node sourceD_wreq_select_shiftAmount = bits(_sourceD_wreq_select_T, 1, 0) node _sourceD_wreq_select_T_1 = dshl(UInt<1>(0h1), sourceD_wreq_select_shiftAmount) node sourceD_wreq_select = bits(_sourceD_wreq_select_T_1, 3, 0) node _sourceD_wreq_ready_T = bits(sourceD_wreq.bankSum, 0, 0) node _sourceD_wreq_ready_T_1 = and(_sourceD_wreq_ready_T, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_2 = orr(_sourceD_wreq_ready_T_1) node _sourceD_wreq_ready_T_3 = eq(_sourceD_wreq_ready_T_2, UInt<1>(0h0)) node _sourceD_wreq_ready_T_4 = bits(sourceD_wreq.bankSum, 1, 1) node _sourceD_wreq_ready_T_5 = and(_sourceD_wreq_ready_T_4, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_6 = orr(_sourceD_wreq_ready_T_5) node _sourceD_wreq_ready_T_7 = eq(_sourceD_wreq_ready_T_6, UInt<1>(0h0)) node _sourceD_wreq_ready_T_8 = bits(sourceD_wreq.bankSum, 2, 2) node _sourceD_wreq_ready_T_9 = and(_sourceD_wreq_ready_T_8, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_10 = orr(_sourceD_wreq_ready_T_9) node _sourceD_wreq_ready_T_11 = eq(_sourceD_wreq_ready_T_10, UInt<1>(0h0)) node _sourceD_wreq_ready_T_12 = bits(sourceD_wreq.bankSum, 3, 3) node _sourceD_wreq_ready_T_13 = and(_sourceD_wreq_ready_T_12, io.sourceD_wadr.bits.mask) node _sourceD_wreq_ready_T_14 = orr(_sourceD_wreq_ready_T_13) node _sourceD_wreq_ready_T_15 = eq(_sourceD_wreq_ready_T_14, UInt<1>(0h0)) node sourceD_wreq_ready_lo = cat(_sourceD_wreq_ready_T_7, _sourceD_wreq_ready_T_3) node sourceD_wreq_ready_hi = cat(_sourceD_wreq_ready_T_15, _sourceD_wreq_ready_T_11) node sourceD_wreq_ready = cat(sourceD_wreq_ready_hi, sourceD_wreq_ready_lo) node _sourceD_wreq_io_sourceD_wadr_ready_T = bits(sourceD_wreq_a, 1, 0) node _sourceD_wreq_io_sourceD_wadr_ready_T_1 = dshr(sourceD_wreq_ready, _sourceD_wreq_io_sourceD_wadr_ready_T) node _sourceD_wreq_io_sourceD_wadr_ready_T_2 = bits(_sourceD_wreq_io_sourceD_wadr_ready_T_1, 0, 0) connect io.sourceD_wadr.ready, _sourceD_wreq_io_sourceD_wadr_ready_T_2 connect sourceD_wreq.wen, UInt<1>(0h1) node _sourceD_wreq_out_index_T = shr(sourceD_wreq_a, 2) connect sourceD_wreq.index, _sourceD_wreq_out_index_T node _sourceD_wreq_out_bankSel_T = bits(sourceD_wreq_select, 0, 0) node _sourceD_wreq_out_bankSel_T_1 = bits(sourceD_wreq_select, 1, 1) node _sourceD_wreq_out_bankSel_T_2 = bits(sourceD_wreq_select, 2, 2) node _sourceD_wreq_out_bankSel_T_3 = bits(sourceD_wreq_select, 3, 3) node sourceD_wreq_out_bankSel_lo = cat(_sourceD_wreq_out_bankSel_T_1, _sourceD_wreq_out_bankSel_T) node sourceD_wreq_out_bankSel_hi = cat(_sourceD_wreq_out_bankSel_T_3, _sourceD_wreq_out_bankSel_T_2) node _sourceD_wreq_out_bankSel_T_4 = cat(sourceD_wreq_out_bankSel_hi, sourceD_wreq_out_bankSel_lo) node _sourceD_wreq_out_bankSel_T_5 = bits(io.sourceD_wadr.bits.mask, 0, 0) node _sourceD_wreq_out_bankSel_T_6 = mux(_sourceD_wreq_out_bankSel_T_5, UInt<4>(0hf), UInt<4>(0h0)) node _sourceD_wreq_out_bankSel_T_7 = and(_sourceD_wreq_out_bankSel_T_4, _sourceD_wreq_out_bankSel_T_6) node _sourceD_wreq_out_bankSel_T_8 = mux(io.sourceD_wadr.valid, _sourceD_wreq_out_bankSel_T_7, UInt<1>(0h0)) connect sourceD_wreq.bankSel, _sourceD_wreq_out_bankSel_T_8 node _sourceD_wreq_out_bankEn_T = bits(sourceD_wreq_ready, 0, 0) node _sourceD_wreq_out_bankEn_T_1 = bits(sourceD_wreq_ready, 1, 1) node _sourceD_wreq_out_bankEn_T_2 = bits(sourceD_wreq_ready, 2, 2) node _sourceD_wreq_out_bankEn_T_3 = bits(sourceD_wreq_ready, 3, 3) node sourceD_wreq_out_bankEn_lo = cat(_sourceD_wreq_out_bankEn_T_1, _sourceD_wreq_out_bankEn_T) node sourceD_wreq_out_bankEn_hi = cat(_sourceD_wreq_out_bankEn_T_3, _sourceD_wreq_out_bankEn_T_2) node _sourceD_wreq_out_bankEn_T_4 = cat(sourceD_wreq_out_bankEn_hi, sourceD_wreq_out_bankEn_lo) node _sourceD_wreq_out_bankEn_T_5 = and(sourceD_wreq.bankSel, _sourceD_wreq_out_bankEn_T_4) node _sourceD_wreq_out_bankEn_T_6 = mux(io.sourceD_wadr.bits.noop, UInt<1>(0h0), _sourceD_wreq_out_bankEn_T_5) connect sourceD_wreq.bankEn, _sourceD_wreq_out_bankEn_T_6 connect sourceD_wreq.data[0], sourceD_wreq_words_0 connect sourceD_wreq.data[1], sourceD_wreq_words_0 connect sourceD_wreq.data[2], sourceD_wreq_words_0 connect sourceD_wreq.data[3], sourceD_wreq_words_0 connect sinkC_req.bankSum, UInt<1>(0h0) node _T = or(sinkC_req.bankSel, UInt<1>(0h0)) connect sourceC_req.bankSum, _T node _T_1 = or(sourceC_req.bankSel, _T) connect sinkD_req.bankSum, _T_1 node _T_2 = or(sinkD_req.bankSel, _T_1) connect sourceD_wreq.bankSum, _T_2 node _T_3 = or(sourceD_wreq.bankSel, _T_2) connect sourceD_rreq.bankSum, _T_3 node _T_4 = or(sourceD_rreq.bankSel, _T_3) node _regout_en_T = bits(sinkC_req.bankEn, 0, 0) node _regout_en_T_1 = bits(sourceC_req.bankEn, 0, 0) node _regout_en_T_2 = bits(sinkD_req.bankEn, 0, 0) node _regout_en_T_3 = bits(sourceD_wreq.bankEn, 0, 0) node _regout_en_T_4 = bits(sourceD_rreq.bankEn, 0, 0) node _regout_en_T_5 = or(_regout_en_T, _regout_en_T_1) node _regout_en_T_6 = or(_regout_en_T_5, _regout_en_T_2) node _regout_en_T_7 = or(_regout_en_T_6, _regout_en_T_3) node regout_en = or(_regout_en_T_7, _regout_en_T_4) node regout_sel_0 = bits(sinkC_req.bankSel, 0, 0) node regout_sel_1 = bits(sourceC_req.bankSel, 0, 0) node regout_sel_2 = bits(sinkD_req.bankSel, 0, 0) node regout_sel_3 = bits(sourceD_wreq.bankSel, 0, 0) node regout_sel_4 = bits(sourceD_rreq.bankSel, 0, 0) node _regout_wen_T = mux(regout_sel_3, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_1 = mux(regout_sel_2, sinkD_req.wen, _regout_wen_T) node _regout_wen_T_2 = mux(regout_sel_1, sourceC_req.wen, _regout_wen_T_1) node regout_wen = mux(regout_sel_0, sinkC_req.wen, _regout_wen_T_2) node _regout_idx_T = mux(regout_sel_3, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_1 = mux(regout_sel_2, sinkD_req.index, _regout_idx_T) node _regout_idx_T_2 = mux(regout_sel_1, sourceC_req.index, _regout_idx_T_1) node regout_idx = mux(regout_sel_0, sinkC_req.index, _regout_idx_T_2) node _regout_data_T = mux(regout_sel_3, sourceD_wreq.data[0], sourceD_rreq.data[0]) node _regout_data_T_1 = mux(regout_sel_2, sinkD_req.data[0], _regout_data_T) node _regout_data_T_2 = mux(regout_sel_1, sourceC_req.data[0], _regout_data_T_1) node regout_data = mux(regout_sel_0, sinkC_req.data[0], _regout_data_T_2) node _regout_T = and(regout_wen, regout_en) when _regout_T : write mport regout_MPORT = cc_banks_0[regout_idx], clock connect regout_MPORT, regout_data node _regout_T_1 = eq(regout_wen, UInt<1>(0h0)) node _regout_T_2 = and(_regout_T_1, regout_en) wire _regout_WIRE : UInt<14> invalidate _regout_WIRE when _regout_T_2 : connect _regout_WIRE, regout_idx read mport regout_MPORT_1 = cc_banks_0[_regout_WIRE], clock node _regout_T_3 = eq(regout_wen, UInt<1>(0h0)) node _regout_T_4 = and(_regout_T_3, regout_en) reg regout_REG : UInt<1>, clock connect regout_REG, _regout_T_4 reg regout_r : UInt<64>, clock when regout_REG : connect regout_r, regout_MPORT_1 node _regout_en_T_8 = bits(sinkC_req.bankEn, 1, 1) node _regout_en_T_9 = bits(sourceC_req.bankEn, 1, 1) node _regout_en_T_10 = bits(sinkD_req.bankEn, 1, 1) node _regout_en_T_11 = bits(sourceD_wreq.bankEn, 1, 1) node _regout_en_T_12 = bits(sourceD_rreq.bankEn, 1, 1) node _regout_en_T_13 = or(_regout_en_T_8, _regout_en_T_9) node _regout_en_T_14 = or(_regout_en_T_13, _regout_en_T_10) node _regout_en_T_15 = or(_regout_en_T_14, _regout_en_T_11) node regout_en_1 = or(_regout_en_T_15, _regout_en_T_12) node regout_sel_0_1 = bits(sinkC_req.bankSel, 1, 1) node regout_sel_1_1 = bits(sourceC_req.bankSel, 1, 1) node regout_sel_2_1 = bits(sinkD_req.bankSel, 1, 1) node regout_sel_3_1 = bits(sourceD_wreq.bankSel, 1, 1) node regout_sel_4_1 = bits(sourceD_rreq.bankSel, 1, 1) node _regout_wen_T_3 = mux(regout_sel_3_1, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_4 = mux(regout_sel_2_1, sinkD_req.wen, _regout_wen_T_3) node _regout_wen_T_5 = mux(regout_sel_1_1, sourceC_req.wen, _regout_wen_T_4) node regout_wen_1 = mux(regout_sel_0_1, sinkC_req.wen, _regout_wen_T_5) node _regout_idx_T_3 = mux(regout_sel_3_1, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_4 = mux(regout_sel_2_1, sinkD_req.index, _regout_idx_T_3) node _regout_idx_T_5 = mux(regout_sel_1_1, sourceC_req.index, _regout_idx_T_4) node regout_idx_1 = mux(regout_sel_0_1, sinkC_req.index, _regout_idx_T_5) node _regout_data_T_3 = mux(regout_sel_3_1, sourceD_wreq.data[1], sourceD_rreq.data[1]) node _regout_data_T_4 = mux(regout_sel_2_1, sinkD_req.data[1], _regout_data_T_3) node _regout_data_T_5 = mux(regout_sel_1_1, sourceC_req.data[1], _regout_data_T_4) node regout_data_1 = mux(regout_sel_0_1, sinkC_req.data[1], _regout_data_T_5) node _regout_T_5 = and(regout_wen_1, regout_en_1) when _regout_T_5 : write mport regout_MPORT_2 = cc_banks_1[regout_idx_1], clock connect regout_MPORT_2, regout_data_1 node _regout_T_6 = eq(regout_wen_1, UInt<1>(0h0)) node _regout_T_7 = and(_regout_T_6, regout_en_1) wire _regout_WIRE_1 : UInt<14> invalidate _regout_WIRE_1 when _regout_T_7 : connect _regout_WIRE_1, regout_idx_1 read mport regout_MPORT_3 = cc_banks_1[_regout_WIRE_1], clock node _regout_T_8 = eq(regout_wen_1, UInt<1>(0h0)) node _regout_T_9 = and(_regout_T_8, regout_en_1) reg regout_REG_1 : UInt<1>, clock connect regout_REG_1, _regout_T_9 reg regout_r_1 : UInt<64>, clock when regout_REG_1 : connect regout_r_1, regout_MPORT_3 node _regout_en_T_16 = bits(sinkC_req.bankEn, 2, 2) node _regout_en_T_17 = bits(sourceC_req.bankEn, 2, 2) node _regout_en_T_18 = bits(sinkD_req.bankEn, 2, 2) node _regout_en_T_19 = bits(sourceD_wreq.bankEn, 2, 2) node _regout_en_T_20 = bits(sourceD_rreq.bankEn, 2, 2) node _regout_en_T_21 = or(_regout_en_T_16, _regout_en_T_17) node _regout_en_T_22 = or(_regout_en_T_21, _regout_en_T_18) node _regout_en_T_23 = or(_regout_en_T_22, _regout_en_T_19) node regout_en_2 = or(_regout_en_T_23, _regout_en_T_20) node regout_sel_0_2 = bits(sinkC_req.bankSel, 2, 2) node regout_sel_1_2 = bits(sourceC_req.bankSel, 2, 2) node regout_sel_2_2 = bits(sinkD_req.bankSel, 2, 2) node regout_sel_3_2 = bits(sourceD_wreq.bankSel, 2, 2) node regout_sel_4_2 = bits(sourceD_rreq.bankSel, 2, 2) node _regout_wen_T_6 = mux(regout_sel_3_2, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_7 = mux(regout_sel_2_2, sinkD_req.wen, _regout_wen_T_6) node _regout_wen_T_8 = mux(regout_sel_1_2, sourceC_req.wen, _regout_wen_T_7) node regout_wen_2 = mux(regout_sel_0_2, sinkC_req.wen, _regout_wen_T_8) node _regout_idx_T_6 = mux(regout_sel_3_2, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_7 = mux(regout_sel_2_2, sinkD_req.index, _regout_idx_T_6) node _regout_idx_T_8 = mux(regout_sel_1_2, sourceC_req.index, _regout_idx_T_7) node regout_idx_2 = mux(regout_sel_0_2, sinkC_req.index, _regout_idx_T_8) node _regout_data_T_6 = mux(regout_sel_3_2, sourceD_wreq.data[2], sourceD_rreq.data[2]) node _regout_data_T_7 = mux(regout_sel_2_2, sinkD_req.data[2], _regout_data_T_6) node _regout_data_T_8 = mux(regout_sel_1_2, sourceC_req.data[2], _regout_data_T_7) node regout_data_2 = mux(regout_sel_0_2, sinkC_req.data[2], _regout_data_T_8) node _regout_T_10 = and(regout_wen_2, regout_en_2) when _regout_T_10 : write mport regout_MPORT_4 = cc_banks_2[regout_idx_2], clock connect regout_MPORT_4, regout_data_2 node _regout_T_11 = eq(regout_wen_2, UInt<1>(0h0)) node _regout_T_12 = and(_regout_T_11, regout_en_2) wire _regout_WIRE_2 : UInt<14> invalidate _regout_WIRE_2 when _regout_T_12 : connect _regout_WIRE_2, regout_idx_2 read mport regout_MPORT_5 = cc_banks_2[_regout_WIRE_2], clock node _regout_T_13 = eq(regout_wen_2, UInt<1>(0h0)) node _regout_T_14 = and(_regout_T_13, regout_en_2) reg regout_REG_2 : UInt<1>, clock connect regout_REG_2, _regout_T_14 reg regout_r_2 : UInt<64>, clock when regout_REG_2 : connect regout_r_2, regout_MPORT_5 node _regout_en_T_24 = bits(sinkC_req.bankEn, 3, 3) node _regout_en_T_25 = bits(sourceC_req.bankEn, 3, 3) node _regout_en_T_26 = bits(sinkD_req.bankEn, 3, 3) node _regout_en_T_27 = bits(sourceD_wreq.bankEn, 3, 3) node _regout_en_T_28 = bits(sourceD_rreq.bankEn, 3, 3) node _regout_en_T_29 = or(_regout_en_T_24, _regout_en_T_25) node _regout_en_T_30 = or(_regout_en_T_29, _regout_en_T_26) node _regout_en_T_31 = or(_regout_en_T_30, _regout_en_T_27) node regout_en_3 = or(_regout_en_T_31, _regout_en_T_28) node regout_sel_0_3 = bits(sinkC_req.bankSel, 3, 3) node regout_sel_1_3 = bits(sourceC_req.bankSel, 3, 3) node regout_sel_2_3 = bits(sinkD_req.bankSel, 3, 3) node regout_sel_3_3 = bits(sourceD_wreq.bankSel, 3, 3) node regout_sel_4_3 = bits(sourceD_rreq.bankSel, 3, 3) node _regout_wen_T_9 = mux(regout_sel_3_3, sourceD_wreq.wen, sourceD_rreq.wen) node _regout_wen_T_10 = mux(regout_sel_2_3, sinkD_req.wen, _regout_wen_T_9) node _regout_wen_T_11 = mux(regout_sel_1_3, sourceC_req.wen, _regout_wen_T_10) node regout_wen_3 = mux(regout_sel_0_3, sinkC_req.wen, _regout_wen_T_11) node _regout_idx_T_9 = mux(regout_sel_3_3, sourceD_wreq.index, sourceD_rreq.index) node _regout_idx_T_10 = mux(regout_sel_2_3, sinkD_req.index, _regout_idx_T_9) node _regout_idx_T_11 = mux(regout_sel_1_3, sourceC_req.index, _regout_idx_T_10) node regout_idx_3 = mux(regout_sel_0_3, sinkC_req.index, _regout_idx_T_11) node _regout_data_T_9 = mux(regout_sel_3_3, sourceD_wreq.data[3], sourceD_rreq.data[3]) node _regout_data_T_10 = mux(regout_sel_2_3, sinkD_req.data[3], _regout_data_T_9) node _regout_data_T_11 = mux(regout_sel_1_3, sourceC_req.data[3], _regout_data_T_10) node regout_data_3 = mux(regout_sel_0_3, sinkC_req.data[3], _regout_data_T_11) node _regout_T_15 = and(regout_wen_3, regout_en_3) when _regout_T_15 : write mport regout_MPORT_6 = cc_banks_3[regout_idx_3], clock connect regout_MPORT_6, regout_data_3 node _regout_T_16 = eq(regout_wen_3, UInt<1>(0h0)) node _regout_T_17 = and(_regout_T_16, regout_en_3) wire _regout_WIRE_3 : UInt<14> invalidate _regout_WIRE_3 when _regout_T_17 : connect _regout_WIRE_3, regout_idx_3 read mport regout_MPORT_7 = cc_banks_3[_regout_WIRE_3], clock node _regout_T_18 = eq(regout_wen_3, UInt<1>(0h0)) node _regout_T_19 = and(_regout_T_18, regout_en_3) reg regout_REG_3 : UInt<1>, clock connect regout_REG_3, _regout_T_19 reg regout_r_3 : UInt<64>, clock when regout_REG_3 : connect regout_r_3, regout_MPORT_7 wire regout : UInt<64>[4] connect regout[0], regout_r connect regout[1], regout_r_1 connect regout[2], regout_r_2 connect regout[3], regout_r_3 reg regsel_sourceC_REG : UInt, clock connect regsel_sourceC_REG, sourceC_req.bankEn reg regsel_sourceC : UInt, clock connect regsel_sourceC, regsel_sourceC_REG reg regsel_sourceD_REG : UInt, clock connect regsel_sourceD_REG, sourceD_rreq.bankEn reg regsel_sourceD : UInt, clock connect regsel_sourceD, regsel_sourceD_REG node _decodeC_T = bits(regsel_sourceC, 0, 0) node _decodeC_T_1 = mux(_decodeC_T, regout[0], UInt<1>(0h0)) node _decodeC_T_2 = bits(regsel_sourceC, 1, 1) node _decodeC_T_3 = mux(_decodeC_T_2, regout[1], UInt<1>(0h0)) node _decodeC_T_4 = bits(regsel_sourceC, 2, 2) node _decodeC_T_5 = mux(_decodeC_T_4, regout[2], UInt<1>(0h0)) node _decodeC_T_6 = bits(regsel_sourceC, 3, 3) node _decodeC_T_7 = mux(_decodeC_T_6, regout[3], UInt<1>(0h0)) node _decodeC_T_8 = or(_decodeC_T_1, _decodeC_T_3) node _decodeC_T_9 = or(_decodeC_T_8, _decodeC_T_5) node decodeC_0 = or(_decodeC_T_9, _decodeC_T_7) connect io.sourceC_dat.data, decodeC_0 node _decodeD_T = bits(regsel_sourceD, 0, 0) node _decodeD_T_1 = mux(_decodeD_T, regout[0], UInt<1>(0h0)) node _decodeD_T_2 = bits(regsel_sourceD, 1, 1) node _decodeD_T_3 = mux(_decodeD_T_2, regout[1], UInt<1>(0h0)) node _decodeD_T_4 = bits(regsel_sourceD, 2, 2) node _decodeD_T_5 = mux(_decodeD_T_4, regout[2], UInt<1>(0h0)) node _decodeD_T_6 = bits(regsel_sourceD, 3, 3) node _decodeD_T_7 = mux(_decodeD_T_6, regout[3], UInt<1>(0h0)) node _decodeD_T_8 = or(_decodeD_T_1, _decodeD_T_3) node _decodeD_T_9 = or(_decodeD_T_8, _decodeD_T_5) node decodeD_0 = or(_decodeD_T_9, _decodeD_T_7) connect io.sourceD_rdat.data, decodeD_0
module BankedStore( // @[BankedStore.scala:59:7] input clock, // @[BankedStore.scala:59:7] output io_sinkC_adr_ready, // @[BankedStore.scala:61:14] input io_sinkC_adr_valid, // @[BankedStore.scala:61:14] input io_sinkC_adr_bits_noop, // @[BankedStore.scala:61:14] input [2:0] io_sinkC_adr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sinkC_adr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sinkC_adr_bits_beat, // @[BankedStore.scala:61:14] input io_sinkC_adr_bits_mask, // @[BankedStore.scala:61:14] input [63:0] io_sinkC_dat_data, // @[BankedStore.scala:61:14] output io_sinkD_adr_ready, // @[BankedStore.scala:61:14] input io_sinkD_adr_valid, // @[BankedStore.scala:61:14] input io_sinkD_adr_bits_noop, // @[BankedStore.scala:61:14] input [2:0] io_sinkD_adr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sinkD_adr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sinkD_adr_bits_beat, // @[BankedStore.scala:61:14] input [63:0] io_sinkD_dat_data, // @[BankedStore.scala:61:14] output io_sourceC_adr_ready, // @[BankedStore.scala:61:14] input io_sourceC_adr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceC_adr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceC_adr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sourceC_adr_bits_beat, // @[BankedStore.scala:61:14] output [63:0] io_sourceC_dat_data, // @[BankedStore.scala:61:14] output io_sourceD_radr_ready, // @[BankedStore.scala:61:14] input io_sourceD_radr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceD_radr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceD_radr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sourceD_radr_bits_beat, // @[BankedStore.scala:61:14] input io_sourceD_radr_bits_mask, // @[BankedStore.scala:61:14] output [63:0] io_sourceD_rdat_data, // @[BankedStore.scala:61:14] output io_sourceD_wadr_ready, // @[BankedStore.scala:61:14] input io_sourceD_wadr_valid, // @[BankedStore.scala:61:14] input [2:0] io_sourceD_wadr_bits_way, // @[BankedStore.scala:61:14] input [9:0] io_sourceD_wadr_bits_set, // @[BankedStore.scala:61:14] input [2:0] io_sourceD_wadr_bits_beat, // @[BankedStore.scala:61:14] input io_sourceD_wadr_bits_mask, // @[BankedStore.scala:61:14] input [63:0] io_sourceD_wdat_data // @[BankedStore.scala:61:14] ); wire readEnable; // @[BankedStore.scala:172:32] wire writeEnable; // @[BankedStore.scala:171:15] wire readEnable_0; // @[BankedStore.scala:172:32] wire writeEnable_0; // @[BankedStore.scala:171:15] wire readEnable_1; // @[BankedStore.scala:172:32] wire writeEnable_1; // @[BankedStore.scala:171:15] wire readEnable_2; // @[BankedStore.scala:172:32] wire writeEnable_2; // @[BankedStore.scala:171:15] wire [3:0] sourceD_rreq_bankSum; // @[BankedStore.scala:161:17] wire [3:0] sourceD_wreq_bankSum; // @[BankedStore.scala:161:17] wire [3:0] sinkD_req_bankSum; // @[BankedStore.scala:161:17] wire [63:0] _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [63:0] _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] wire [3:0] _GEN = {2'h0, io_sinkC_adr_bits_beat[1:0]}; // @[OneHot.scala:65:12] wire [3:0] _sinkC_req_io_sinkC_adr_ready_T_1 = 4'hF >> _GEN; // @[OneHot.scala:65:12] wire [13:0] sinkC_req_index = {io_sinkC_adr_bits_way, io_sinkC_adr_bits_set, io_sinkC_adr_bits_beat[2]}; // @[BankedStore.scala:135:23] wire [3:0] _sinkC_req_out_bankSel_T_7 = 4'h1 << _GEN & {4{io_sinkC_adr_bits_mask}}; // @[OneHot.scala:65:12] wire [3:0] sinkC_req_bankSel = io_sinkC_adr_valid ? _sinkC_req_out_bankSel_T_7 : 4'h0; // @[BankedStore.scala:59:7, :136:{24,65}] wire [3:0] sinkC_req_bankEn = io_sinkC_adr_bits_noop | ~io_sinkC_adr_valid ? 4'h0 : _sinkC_req_out_bankSel_T_7; // @[BankedStore.scala:59:7, :136:65, :137:24] wire [3:0] _GEN_0 = {2'h0, io_sinkD_adr_bits_beat[1:0]}; // @[OneHot.scala:65:12] wire [3:0] sinkD_req_ready = {~(sinkD_req_bankSum[3]), ~(sinkD_req_bankSum[2]), ~(sinkD_req_bankSum[1]), ~(sinkD_req_bankSum[0])}; // @[BankedStore.scala:131:{21,58,71}, :161:17] wire [3:0] _sinkD_req_io_sinkD_adr_ready_T_1 = sinkD_req_ready >> _GEN_0; // @[OneHot.scala:65:12] wire [13:0] sinkD_req_index = {io_sinkD_adr_bits_way, io_sinkD_adr_bits_set, io_sinkD_adr_bits_beat[2]}; // @[BankedStore.scala:135:23] wire [3:0] sinkD_req_bankSel = io_sinkD_adr_valid ? 4'h1 << _GEN_0 : 4'h0; // @[OneHot.scala:65:12] wire [3:0] sinkD_req_bankEn = io_sinkD_adr_bits_noop ? 4'h0 : sinkD_req_bankSel & sinkD_req_ready; // @[BankedStore.scala:59:7, :131:21, :136:24, :137:{24,55}] wire [3:0] _GEN_1 = {2'h0, io_sourceC_adr_bits_beat[1:0]}; // @[OneHot.scala:65:12] wire [3:0] sourceC_req_ready = {~(sinkC_req_bankSel[3]), ~(sinkC_req_bankSel[2]), ~(sinkC_req_bankSel[1]), ~(sinkC_req_bankSel[0])}; // @[BankedStore.scala:131:{21,58,71}, :136:24] wire [3:0] _sourceC_req_io_sourceC_adr_ready_T_1 = sourceC_req_ready >> _GEN_1; // @[OneHot.scala:65:12] wire [13:0] sourceC_req_index = {io_sourceC_adr_bits_way, io_sourceC_adr_bits_set, io_sourceC_adr_bits_beat[2]}; // @[BankedStore.scala:135:23] wire [3:0] sourceC_req_bankSel = io_sourceC_adr_valid ? 4'h1 << _GEN_1 : 4'h0; // @[OneHot.scala:65:12] wire [3:0] sourceC_req_bankEn = sourceC_req_bankSel & sourceC_req_ready; // @[BankedStore.scala:131:21, :136:24, :137:55] wire [3:0] _GEN_2 = {2'h0, io_sourceD_radr_bits_beat[1:0]}; // @[OneHot.scala:65:12] wire [3:0] sourceD_rreq_ready = {~(sourceD_rreq_bankSum[3] & io_sourceD_radr_bits_mask), ~(sourceD_rreq_bankSum[2] & io_sourceD_radr_bits_mask), ~(sourceD_rreq_bankSum[1] & io_sourceD_radr_bits_mask), ~(sourceD_rreq_bankSum[0] & io_sourceD_radr_bits_mask)}; // @[BankedStore.scala:131:{21,58,71,96}, :161:17] wire [3:0] _sourceD_rreq_io_sourceD_radr_ready_T_1 = sourceD_rreq_ready >> _GEN_2; // @[OneHot.scala:65:12] wire [13:0] sourceD_rreq_index = {io_sourceD_radr_bits_way, io_sourceD_radr_bits_set, io_sourceD_radr_bits_beat[2]}; // @[BankedStore.scala:135:23] wire [3:0] sourceD_rreq_bankEn = (io_sourceD_radr_valid ? 4'h1 << _GEN_2 & {4{io_sourceD_radr_bits_mask}} : 4'h0) & sourceD_rreq_ready; // @[OneHot.scala:65:12] wire [3:0] _GEN_3 = {2'h0, io_sourceD_wadr_bits_beat[1:0]}; // @[OneHot.scala:65:12] wire [3:0] sourceD_wreq_ready = {~(sourceD_wreq_bankSum[3] & io_sourceD_wadr_bits_mask), ~(sourceD_wreq_bankSum[2] & io_sourceD_wadr_bits_mask), ~(sourceD_wreq_bankSum[1] & io_sourceD_wadr_bits_mask), ~(sourceD_wreq_bankSum[0] & io_sourceD_wadr_bits_mask)}; // @[BankedStore.scala:131:{21,58,71,96}, :161:17] wire [3:0] _sourceD_wreq_io_sourceD_wadr_ready_T_1 = sourceD_wreq_ready >> _GEN_3; // @[OneHot.scala:65:12] wire [13:0] sourceD_wreq_index = {io_sourceD_wadr_bits_way, io_sourceD_wadr_bits_set, io_sourceD_wadr_bits_beat[2]}; // @[BankedStore.scala:135:23] wire [3:0] sourceD_wreq_bankSel = io_sourceD_wadr_valid ? 4'h1 << _GEN_3 & {4{io_sourceD_wadr_bits_mask}} : 4'h0; // @[OneHot.scala:65:12] wire [3:0] sourceD_wreq_bankEn = sourceD_wreq_bankSel & sourceD_wreq_ready; // @[BankedStore.scala:131:21, :136:24, :137:55] assign sinkD_req_bankSum = sourceC_req_bankSel | sinkC_req_bankSel; // @[BankedStore.scala:136:24, :161:17] assign sourceD_wreq_bankSum = sinkD_req_bankSel | sinkD_req_bankSum; // @[BankedStore.scala:136:24, :161:17] assign sourceD_rreq_bankSum = sourceD_wreq_bankSel | sourceD_wreq_bankSum; // @[BankedStore.scala:136:24, :161:17] wire regout_en = sinkC_req_bankEn[0] | sourceC_req_bankEn[0] | sinkD_req_bankEn[0] | sourceD_wreq_bankEn[0] | sourceD_rreq_bankEn[0]; // @[BankedStore.scala:137:{24,55}, :165:{32,45}] wire regout_wen = sinkC_req_bankSel[0] | ~(sourceC_req_bankSel[0]) & (sinkD_req_bankSel[0] | sourceD_wreq_bankSel[0]); // @[Mux.scala:50:70] assign writeEnable_2 = regout_wen & regout_en; // @[Mux.scala:50:70] assign readEnable_2 = ~regout_wen & regout_en; // @[Mux.scala:50:70] reg regout_REG; // @[BankedStore.scala:172:47] reg [63:0] regout_r; // @[BankedStore.scala:172:14] wire regout_en_1 = sinkC_req_bankEn[1] | sourceC_req_bankEn[1] | sinkD_req_bankEn[1] | sourceD_wreq_bankEn[1] | sourceD_rreq_bankEn[1]; // @[BankedStore.scala:137:{24,55}, :165:{32,45}] wire regout_wen_1 = sinkC_req_bankSel[1] | ~(sourceC_req_bankSel[1]) & (sinkD_req_bankSel[1] | sourceD_wreq_bankSel[1]); // @[Mux.scala:50:70] assign writeEnable_1 = regout_wen_1 & regout_en_1; // @[Mux.scala:50:70] assign readEnable_1 = ~regout_wen_1 & regout_en_1; // @[Mux.scala:50:70] reg regout_REG_1; // @[BankedStore.scala:172:47] reg [63:0] regout_r_1; // @[BankedStore.scala:172:14] wire regout_en_2 = sinkC_req_bankEn[2] | sourceC_req_bankEn[2] | sinkD_req_bankEn[2] | sourceD_wreq_bankEn[2] | sourceD_rreq_bankEn[2]; // @[BankedStore.scala:137:{24,55}, :165:{32,45}] wire regout_wen_2 = sinkC_req_bankSel[2] | ~(sourceC_req_bankSel[2]) & (sinkD_req_bankSel[2] | sourceD_wreq_bankSel[2]); // @[Mux.scala:50:70] assign writeEnable_0 = regout_wen_2 & regout_en_2; // @[Mux.scala:50:70] assign readEnable_0 = ~regout_wen_2 & regout_en_2; // @[Mux.scala:50:70] reg regout_REG_2; // @[BankedStore.scala:172:47] reg [63:0] regout_r_2; // @[BankedStore.scala:172:14] wire regout_en_3 = sinkC_req_bankEn[3] | sourceC_req_bankEn[3] | sinkD_req_bankEn[3] | sourceD_wreq_bankEn[3] | sourceD_rreq_bankEn[3]; // @[BankedStore.scala:137:{24,55}, :165:{32,45}] wire regout_wen_3 = sinkC_req_bankSel[3] | ~(sourceC_req_bankSel[3]) & (sinkD_req_bankSel[3] | sourceD_wreq_bankSel[3]); // @[Mux.scala:50:70] assign writeEnable = regout_wen_3 & regout_en_3; // @[Mux.scala:50:70] assign readEnable = ~regout_wen_3 & regout_en_3; // @[Mux.scala:50:70] reg regout_REG_3; // @[BankedStore.scala:172:47] reg [63:0] regout_r_3; // @[BankedStore.scala:172:14] reg [3:0] regsel_sourceC_REG; // @[BankedStore.scala:175:39] reg [3:0] regsel_sourceC; // @[BankedStore.scala:175:31] reg [3:0] regsel_sourceD_REG; // @[BankedStore.scala:176:39] reg [3:0] regsel_sourceD; // @[BankedStore.scala:176:31] always @(posedge clock) begin // @[BankedStore.scala:59:7] regout_REG <= ~regout_wen & regout_en; // @[Mux.scala:50:70] if (regout_REG) // @[BankedStore.scala:172:47] regout_r <= _cc_banks_0_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_1 <= ~regout_wen_1 & regout_en_1; // @[Mux.scala:50:70] if (regout_REG_1) // @[BankedStore.scala:172:47] regout_r_1 <= _cc_banks_1_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_2 <= ~regout_wen_2 & regout_en_2; // @[Mux.scala:50:70] if (regout_REG_2) // @[BankedStore.scala:172:47] regout_r_2 <= _cc_banks_2_RW0_rdata; // @[DescribedSRAM.scala:17:26] regout_REG_3 <= ~regout_wen_3 & regout_en_3; // @[Mux.scala:50:70] if (regout_REG_3) // @[BankedStore.scala:172:47] regout_r_3 <= _cc_banks_3_RW0_rdata; // @[DescribedSRAM.scala:17:26] regsel_sourceC_REG <= sourceC_req_bankEn; // @[BankedStore.scala:137:55, :175:39] regsel_sourceC <= regsel_sourceC_REG; // @[BankedStore.scala:175:{31,39}] regsel_sourceD_REG <= sourceD_rreq_bankEn; // @[BankedStore.scala:137:55, :176:39] regsel_sourceD <= regsel_sourceD_REG; // @[BankedStore.scala:176:{31,39}] always @(posedge)
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_43 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_43 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_43( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_43 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InputUnit_29 : input clock : Clock input reset : Reset output io : { router_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { src_virt_id : UInt<2>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}}}, flip router_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, vcalloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}}, flip vcalloc_resp : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}, flip out_credit_available : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, salloc_req : { flip ready : UInt<1>, valid : UInt<1>, bits : { vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, tail : UInt<1>}}[1], out : { valid : UInt<1>, bits : { flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}, out_virt_channel : UInt<2>}}[1], debug : { va_stall : UInt<2>, sa_stall : UInt<2>}, flip block : UInt<1>, flip in : { flit : { valid : UInt<1>, bits : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1], flip credit_return : UInt<3>, flip vc_free : UInt<3>}} inst input_buffer of InputBuffer_29 connect input_buffer.clock, clock connect input_buffer.reset, reset connect input_buffer.io.enq[0].bits.virt_channel_id, io.in.flit[0].bits.virt_channel_id connect input_buffer.io.enq[0].bits.flow.egress_node_id, io.in.flit[0].bits.flow.egress_node_id connect input_buffer.io.enq[0].bits.flow.egress_node, io.in.flit[0].bits.flow.egress_node connect input_buffer.io.enq[0].bits.flow.ingress_node_id, io.in.flit[0].bits.flow.ingress_node_id connect input_buffer.io.enq[0].bits.flow.ingress_node, io.in.flit[0].bits.flow.ingress_node connect input_buffer.io.enq[0].bits.flow.vnet_id, io.in.flit[0].bits.flow.vnet_id connect input_buffer.io.enq[0].bits.payload, io.in.flit[0].bits.payload connect input_buffer.io.enq[0].bits.tail, io.in.flit[0].bits.tail connect input_buffer.io.enq[0].bits.head, io.in.flit[0].bits.head connect input_buffer.io.enq[0].valid, io.in.flit[0].valid connect input_buffer.io.deq[0].ready, UInt<1>(0h0) connect input_buffer.io.deq[1].ready, UInt<1>(0h0) connect input_buffer.io.deq[2].ready, UInt<1>(0h0) inst route_arbiter of Arbiter3_RouteComputerReq_29 connect route_arbiter.clock, clock connect route_arbiter.reset, reset connect io.router_req.bits, route_arbiter.io.out.bits connect io.router_req.valid, route_arbiter.io.out.valid connect route_arbiter.io.out.ready, io.router_req.ready reg states : { g : UInt<3>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, fifo_deps : UInt<3>}[3], clock node _T = and(io.in.flit[0].valid, io.in.flit[0].bits.head) when _T : node _T_1 = lt(io.in.flit[0].bits.virt_channel_id, UInt<2>(0h3)) node _T_2 = asUInt(reset) node _T_3 = eq(_T_2, UInt<1>(0h0)) when _T_3 : node _T_4 = eq(_T_1, UInt<1>(0h0)) when _T_4 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:207 assert(id < nVirtualChannels.U)\n") : printf assert(clock, _T_1, UInt<1>(0h1), "") : assert node _T_5 = eq(states[io.in.flit[0].bits.virt_channel_id].g, UInt<3>(0h0)) node _T_6 = asUInt(reset) node _T_7 = eq(_T_6, UInt<1>(0h0)) when _T_7 : node _T_8 = eq(_T_5, UInt<1>(0h0)) when _T_8 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:208 assert(states(id).g === g_i)\n") : printf_1 assert(clock, _T_5, UInt<1>(0h1), "") : assert_1 node at_dest = eq(io.in.flit[0].bits.flow.egress_node, UInt<4>(0h9)) node _states_g_T = mux(at_dest, UInt<3>(0h2), UInt<3>(0h1)) connect states[io.in.flit[0].bits.virt_channel_id].g, _states_g_T connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`0`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`1`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`2`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[1], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`3`[2], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h0) connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h0) node _T_9 = eq(UInt<1>(0h0), io.in.flit[0].bits.flow.egress_node_id) when _T_9 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`4`[0], UInt<1>(0h1) node _T_10 = eq(UInt<1>(0h1), io.in.flit[0].bits.flow.egress_node_id) when _T_10 : connect states[io.in.flit[0].bits.virt_channel_id].vc_sel.`5`[0], UInt<1>(0h1) connect states[io.in.flit[0].bits.virt_channel_id].flow, io.in.flit[0].bits.flow node _route_arbiter_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h1)) connect route_arbiter.io.in[0].valid, _route_arbiter_io_in_0_valid_T connect route_arbiter.io.in[0].bits.flow.egress_node_id, states[0].flow.egress_node_id connect route_arbiter.io.in[0].bits.flow.egress_node, states[0].flow.egress_node connect route_arbiter.io.in[0].bits.flow.ingress_node_id, states[0].flow.ingress_node_id connect route_arbiter.io.in[0].bits.flow.ingress_node, states[0].flow.ingress_node connect route_arbiter.io.in[0].bits.flow.vnet_id, states[0].flow.vnet_id connect route_arbiter.io.in[0].bits.src_virt_id, UInt<1>(0h0) node _T_11 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_11 : connect states[0].g, UInt<3>(0h2) node _route_arbiter_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h1)) connect route_arbiter.io.in[1].valid, _route_arbiter_io_in_1_valid_T connect route_arbiter.io.in[1].bits.flow.egress_node_id, states[1].flow.egress_node_id connect route_arbiter.io.in[1].bits.flow.egress_node, states[1].flow.egress_node connect route_arbiter.io.in[1].bits.flow.ingress_node_id, states[1].flow.ingress_node_id connect route_arbiter.io.in[1].bits.flow.ingress_node, states[1].flow.ingress_node connect route_arbiter.io.in[1].bits.flow.vnet_id, states[1].flow.vnet_id connect route_arbiter.io.in[1].bits.src_virt_id, UInt<1>(0h1) node _T_12 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_12 : connect states[1].g, UInt<3>(0h2) node _route_arbiter_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h1)) connect route_arbiter.io.in[2].valid, _route_arbiter_io_in_2_valid_T connect route_arbiter.io.in[2].bits.flow.egress_node_id, states[2].flow.egress_node_id connect route_arbiter.io.in[2].bits.flow.egress_node, states[2].flow.egress_node connect route_arbiter.io.in[2].bits.flow.ingress_node_id, states[2].flow.ingress_node_id connect route_arbiter.io.in[2].bits.flow.ingress_node, states[2].flow.ingress_node connect route_arbiter.io.in[2].bits.flow.vnet_id, states[2].flow.vnet_id connect route_arbiter.io.in[2].bits.src_virt_id, UInt<2>(0h2) node _T_13 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_13 : connect states[2].g, UInt<3>(0h2) node _T_14 = and(io.router_req.ready, io.router_req.valid) when _T_14 : node _T_15 = eq(states[io.router_req.bits.src_virt_id].g, UInt<3>(0h1)) node _T_16 = asUInt(reset) node _T_17 = eq(_T_16, UInt<1>(0h0)) when _T_17 : node _T_18 = eq(_T_15, UInt<1>(0h0)) when _T_18 : printf(clock, UInt<1>(0h1), "Assertion failed\n at InputUnit.scala:241 assert(states(id).g === g_r)\n") : printf_2 assert(clock, _T_15, UInt<1>(0h1), "") : assert_2 connect states[io.router_req.bits.src_virt_id].g, UInt<3>(0h2) node _T_19 = eq(UInt<1>(0h0), io.router_req.bits.src_virt_id) when _T_19 : connect states[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_20 = eq(UInt<1>(0h1), io.router_req.bits.src_virt_id) when _T_20 : connect states[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.router_resp.vc_sel.`5` node _T_21 = eq(UInt<2>(0h2), io.router_req.bits.src_virt_id) when _T_21 : connect states[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.router_resp.vc_sel.`5` regreset mask : UInt<3>, clock, reset, UInt<3>(0h0) wire vcalloc_reqs : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}}[3] wire vcalloc_vals : UInt<1>[3] node vcalloc_filter_hi = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T = cat(vcalloc_filter_hi, vcalloc_vals[0]) node vcalloc_filter_hi_1 = cat(vcalloc_vals[2], vcalloc_vals[1]) node _vcalloc_filter_T_1 = cat(vcalloc_filter_hi_1, vcalloc_vals[0]) node _vcalloc_filter_T_2 = not(mask) node _vcalloc_filter_T_3 = and(_vcalloc_filter_T_1, _vcalloc_filter_T_2) node _vcalloc_filter_T_4 = cat(_vcalloc_filter_T, _vcalloc_filter_T_3) node _vcalloc_filter_T_5 = bits(_vcalloc_filter_T_4, 0, 0) node _vcalloc_filter_T_6 = bits(_vcalloc_filter_T_4, 1, 1) node _vcalloc_filter_T_7 = bits(_vcalloc_filter_T_4, 2, 2) node _vcalloc_filter_T_8 = bits(_vcalloc_filter_T_4, 3, 3) node _vcalloc_filter_T_9 = bits(_vcalloc_filter_T_4, 4, 4) node _vcalloc_filter_T_10 = bits(_vcalloc_filter_T_4, 5, 5) node _vcalloc_filter_T_11 = mux(_vcalloc_filter_T_10, UInt<6>(0h20), UInt<6>(0h0)) node _vcalloc_filter_T_12 = mux(_vcalloc_filter_T_9, UInt<6>(0h10), _vcalloc_filter_T_11) node _vcalloc_filter_T_13 = mux(_vcalloc_filter_T_8, UInt<6>(0h8), _vcalloc_filter_T_12) node _vcalloc_filter_T_14 = mux(_vcalloc_filter_T_7, UInt<6>(0h4), _vcalloc_filter_T_13) node _vcalloc_filter_T_15 = mux(_vcalloc_filter_T_6, UInt<6>(0h2), _vcalloc_filter_T_14) node vcalloc_filter = mux(_vcalloc_filter_T_5, UInt<6>(0h1), _vcalloc_filter_T_15) node _vcalloc_sel_T = bits(vcalloc_filter, 2, 0) node _vcalloc_sel_T_1 = shr(vcalloc_filter, 3) node vcalloc_sel = or(_vcalloc_sel_T, _vcalloc_sel_T_1) node _T_22 = and(io.router_req.ready, io.router_req.valid) when _T_22 : node _mask_T = dshl(UInt<1>(0h1), io.router_req.bits.src_virt_id) node _mask_T_1 = sub(_mask_T, UInt<1>(0h1)) node _mask_T_2 = tail(_mask_T_1, 1) connect mask, _mask_T_2 else : node _T_23 = or(vcalloc_vals[0], vcalloc_vals[1]) node _T_24 = or(_T_23, vcalloc_vals[2]) when _T_24 : node _mask_T_3 = not(UInt<1>(0h0)) node _mask_T_4 = not(UInt<2>(0h0)) node _mask_T_5 = not(UInt<3>(0h0)) node _mask_T_6 = bits(vcalloc_sel, 0, 0) node _mask_T_7 = bits(vcalloc_sel, 1, 1) node _mask_T_8 = bits(vcalloc_sel, 2, 2) node _mask_T_9 = mux(_mask_T_6, _mask_T_3, UInt<1>(0h0)) node _mask_T_10 = mux(_mask_T_7, _mask_T_4, UInt<1>(0h0)) node _mask_T_11 = mux(_mask_T_8, _mask_T_5, UInt<1>(0h0)) node _mask_T_12 = or(_mask_T_9, _mask_T_10) node _mask_T_13 = or(_mask_T_12, _mask_T_11) wire _mask_WIRE : UInt<3> connect _mask_WIRE, _mask_T_13 connect mask, _mask_WIRE node _io_vcalloc_req_valid_T = or(vcalloc_vals[0], vcalloc_vals[1]) node _io_vcalloc_req_valid_T_1 = or(_io_vcalloc_req_valid_T, vcalloc_vals[2]) connect io.vcalloc_req.valid, _io_vcalloc_req_valid_T_1 node _io_vcalloc_req_bits_T = bits(vcalloc_sel, 0, 0) node _io_vcalloc_req_bits_T_1 = bits(vcalloc_sel, 1, 1) node _io_vcalloc_req_bits_T_2 = bits(vcalloc_sel, 2, 2) wire _io_vcalloc_req_bits_WIRE : { flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, in_vc : UInt<2>, vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]}} wire _io_vcalloc_req_bits_WIRE_1 : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _io_vcalloc_req_bits_WIRE_2 : UInt<1>[3] node _io_vcalloc_req_bits_T_3 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_4 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_5 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_6 = or(_io_vcalloc_req_bits_T_3, _io_vcalloc_req_bits_T_4) node _io_vcalloc_req_bits_T_7 = or(_io_vcalloc_req_bits_T_6, _io_vcalloc_req_bits_T_5) wire _io_vcalloc_req_bits_WIRE_3 : UInt<1> connect _io_vcalloc_req_bits_WIRE_3, _io_vcalloc_req_bits_T_7 connect _io_vcalloc_req_bits_WIRE_2[0], _io_vcalloc_req_bits_WIRE_3 node _io_vcalloc_req_bits_T_8 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_9 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_10 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_11 = or(_io_vcalloc_req_bits_T_8, _io_vcalloc_req_bits_T_9) node _io_vcalloc_req_bits_T_12 = or(_io_vcalloc_req_bits_T_11, _io_vcalloc_req_bits_T_10) wire _io_vcalloc_req_bits_WIRE_4 : UInt<1> connect _io_vcalloc_req_bits_WIRE_4, _io_vcalloc_req_bits_T_12 connect _io_vcalloc_req_bits_WIRE_2[1], _io_vcalloc_req_bits_WIRE_4 node _io_vcalloc_req_bits_T_13 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_14 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_15 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`0`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_16 = or(_io_vcalloc_req_bits_T_13, _io_vcalloc_req_bits_T_14) node _io_vcalloc_req_bits_T_17 = or(_io_vcalloc_req_bits_T_16, _io_vcalloc_req_bits_T_15) wire _io_vcalloc_req_bits_WIRE_5 : UInt<1> connect _io_vcalloc_req_bits_WIRE_5, _io_vcalloc_req_bits_T_17 connect _io_vcalloc_req_bits_WIRE_2[2], _io_vcalloc_req_bits_WIRE_5 connect _io_vcalloc_req_bits_WIRE_1.`0`, _io_vcalloc_req_bits_WIRE_2 wire _io_vcalloc_req_bits_WIRE_6 : UInt<1>[3] node _io_vcalloc_req_bits_T_18 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_19 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_20 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_21 = or(_io_vcalloc_req_bits_T_18, _io_vcalloc_req_bits_T_19) node _io_vcalloc_req_bits_T_22 = or(_io_vcalloc_req_bits_T_21, _io_vcalloc_req_bits_T_20) wire _io_vcalloc_req_bits_WIRE_7 : UInt<1> connect _io_vcalloc_req_bits_WIRE_7, _io_vcalloc_req_bits_T_22 connect _io_vcalloc_req_bits_WIRE_6[0], _io_vcalloc_req_bits_WIRE_7 node _io_vcalloc_req_bits_T_23 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_24 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_25 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_26 = or(_io_vcalloc_req_bits_T_23, _io_vcalloc_req_bits_T_24) node _io_vcalloc_req_bits_T_27 = or(_io_vcalloc_req_bits_T_26, _io_vcalloc_req_bits_T_25) wire _io_vcalloc_req_bits_WIRE_8 : UInt<1> connect _io_vcalloc_req_bits_WIRE_8, _io_vcalloc_req_bits_T_27 connect _io_vcalloc_req_bits_WIRE_6[1], _io_vcalloc_req_bits_WIRE_8 node _io_vcalloc_req_bits_T_28 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_29 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_30 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`1`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_31 = or(_io_vcalloc_req_bits_T_28, _io_vcalloc_req_bits_T_29) node _io_vcalloc_req_bits_T_32 = or(_io_vcalloc_req_bits_T_31, _io_vcalloc_req_bits_T_30) wire _io_vcalloc_req_bits_WIRE_9 : UInt<1> connect _io_vcalloc_req_bits_WIRE_9, _io_vcalloc_req_bits_T_32 connect _io_vcalloc_req_bits_WIRE_6[2], _io_vcalloc_req_bits_WIRE_9 connect _io_vcalloc_req_bits_WIRE_1.`1`, _io_vcalloc_req_bits_WIRE_6 wire _io_vcalloc_req_bits_WIRE_10 : UInt<1>[3] node _io_vcalloc_req_bits_T_33 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_34 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_35 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_36 = or(_io_vcalloc_req_bits_T_33, _io_vcalloc_req_bits_T_34) node _io_vcalloc_req_bits_T_37 = or(_io_vcalloc_req_bits_T_36, _io_vcalloc_req_bits_T_35) wire _io_vcalloc_req_bits_WIRE_11 : UInt<1> connect _io_vcalloc_req_bits_WIRE_11, _io_vcalloc_req_bits_T_37 connect _io_vcalloc_req_bits_WIRE_10[0], _io_vcalloc_req_bits_WIRE_11 node _io_vcalloc_req_bits_T_38 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_39 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_40 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_41 = or(_io_vcalloc_req_bits_T_38, _io_vcalloc_req_bits_T_39) node _io_vcalloc_req_bits_T_42 = or(_io_vcalloc_req_bits_T_41, _io_vcalloc_req_bits_T_40) wire _io_vcalloc_req_bits_WIRE_12 : UInt<1> connect _io_vcalloc_req_bits_WIRE_12, _io_vcalloc_req_bits_T_42 connect _io_vcalloc_req_bits_WIRE_10[1], _io_vcalloc_req_bits_WIRE_12 node _io_vcalloc_req_bits_T_43 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_44 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_45 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`2`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_46 = or(_io_vcalloc_req_bits_T_43, _io_vcalloc_req_bits_T_44) node _io_vcalloc_req_bits_T_47 = or(_io_vcalloc_req_bits_T_46, _io_vcalloc_req_bits_T_45) wire _io_vcalloc_req_bits_WIRE_13 : UInt<1> connect _io_vcalloc_req_bits_WIRE_13, _io_vcalloc_req_bits_T_47 connect _io_vcalloc_req_bits_WIRE_10[2], _io_vcalloc_req_bits_WIRE_13 connect _io_vcalloc_req_bits_WIRE_1.`2`, _io_vcalloc_req_bits_WIRE_10 wire _io_vcalloc_req_bits_WIRE_14 : UInt<1>[3] node _io_vcalloc_req_bits_T_48 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_49 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_50 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_51 = or(_io_vcalloc_req_bits_T_48, _io_vcalloc_req_bits_T_49) node _io_vcalloc_req_bits_T_52 = or(_io_vcalloc_req_bits_T_51, _io_vcalloc_req_bits_T_50) wire _io_vcalloc_req_bits_WIRE_15 : UInt<1> connect _io_vcalloc_req_bits_WIRE_15, _io_vcalloc_req_bits_T_52 connect _io_vcalloc_req_bits_WIRE_14[0], _io_vcalloc_req_bits_WIRE_15 node _io_vcalloc_req_bits_T_53 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_54 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_55 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[1], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_56 = or(_io_vcalloc_req_bits_T_53, _io_vcalloc_req_bits_T_54) node _io_vcalloc_req_bits_T_57 = or(_io_vcalloc_req_bits_T_56, _io_vcalloc_req_bits_T_55) wire _io_vcalloc_req_bits_WIRE_16 : UInt<1> connect _io_vcalloc_req_bits_WIRE_16, _io_vcalloc_req_bits_T_57 connect _io_vcalloc_req_bits_WIRE_14[1], _io_vcalloc_req_bits_WIRE_16 node _io_vcalloc_req_bits_T_58 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_59 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_60 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`3`[2], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_61 = or(_io_vcalloc_req_bits_T_58, _io_vcalloc_req_bits_T_59) node _io_vcalloc_req_bits_T_62 = or(_io_vcalloc_req_bits_T_61, _io_vcalloc_req_bits_T_60) wire _io_vcalloc_req_bits_WIRE_17 : UInt<1> connect _io_vcalloc_req_bits_WIRE_17, _io_vcalloc_req_bits_T_62 connect _io_vcalloc_req_bits_WIRE_14[2], _io_vcalloc_req_bits_WIRE_17 connect _io_vcalloc_req_bits_WIRE_1.`3`, _io_vcalloc_req_bits_WIRE_14 wire _io_vcalloc_req_bits_WIRE_18 : UInt<1>[1] node _io_vcalloc_req_bits_T_63 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_64 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_65 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`4`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_66 = or(_io_vcalloc_req_bits_T_63, _io_vcalloc_req_bits_T_64) node _io_vcalloc_req_bits_T_67 = or(_io_vcalloc_req_bits_T_66, _io_vcalloc_req_bits_T_65) wire _io_vcalloc_req_bits_WIRE_19 : UInt<1> connect _io_vcalloc_req_bits_WIRE_19, _io_vcalloc_req_bits_T_67 connect _io_vcalloc_req_bits_WIRE_18[0], _io_vcalloc_req_bits_WIRE_19 connect _io_vcalloc_req_bits_WIRE_1.`4`, _io_vcalloc_req_bits_WIRE_18 wire _io_vcalloc_req_bits_WIRE_20 : UInt<1>[1] node _io_vcalloc_req_bits_T_68 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_69 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_70 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].vc_sel.`5`[0], UInt<1>(0h0)) node _io_vcalloc_req_bits_T_71 = or(_io_vcalloc_req_bits_T_68, _io_vcalloc_req_bits_T_69) node _io_vcalloc_req_bits_T_72 = or(_io_vcalloc_req_bits_T_71, _io_vcalloc_req_bits_T_70) wire _io_vcalloc_req_bits_WIRE_21 : UInt<1> connect _io_vcalloc_req_bits_WIRE_21, _io_vcalloc_req_bits_T_72 connect _io_vcalloc_req_bits_WIRE_20[0], _io_vcalloc_req_bits_WIRE_21 connect _io_vcalloc_req_bits_WIRE_1.`5`, _io_vcalloc_req_bits_WIRE_20 connect _io_vcalloc_req_bits_WIRE.vc_sel, _io_vcalloc_req_bits_WIRE_1 node _io_vcalloc_req_bits_T_73 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_74 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_75 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].in_vc, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_76 = or(_io_vcalloc_req_bits_T_73, _io_vcalloc_req_bits_T_74) node _io_vcalloc_req_bits_T_77 = or(_io_vcalloc_req_bits_T_76, _io_vcalloc_req_bits_T_75) wire _io_vcalloc_req_bits_WIRE_22 : UInt<2> connect _io_vcalloc_req_bits_WIRE_22, _io_vcalloc_req_bits_T_77 connect _io_vcalloc_req_bits_WIRE.in_vc, _io_vcalloc_req_bits_WIRE_22 wire _io_vcalloc_req_bits_WIRE_23 : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _io_vcalloc_req_bits_T_78 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_79 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_80 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_81 = or(_io_vcalloc_req_bits_T_78, _io_vcalloc_req_bits_T_79) node _io_vcalloc_req_bits_T_82 = or(_io_vcalloc_req_bits_T_81, _io_vcalloc_req_bits_T_80) wire _io_vcalloc_req_bits_WIRE_24 : UInt<2> connect _io_vcalloc_req_bits_WIRE_24, _io_vcalloc_req_bits_T_82 connect _io_vcalloc_req_bits_WIRE_23.egress_node_id, _io_vcalloc_req_bits_WIRE_24 node _io_vcalloc_req_bits_T_83 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_84 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_85 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.egress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_86 = or(_io_vcalloc_req_bits_T_83, _io_vcalloc_req_bits_T_84) node _io_vcalloc_req_bits_T_87 = or(_io_vcalloc_req_bits_T_86, _io_vcalloc_req_bits_T_85) wire _io_vcalloc_req_bits_WIRE_25 : UInt<4> connect _io_vcalloc_req_bits_WIRE_25, _io_vcalloc_req_bits_T_87 connect _io_vcalloc_req_bits_WIRE_23.egress_node, _io_vcalloc_req_bits_WIRE_25 node _io_vcalloc_req_bits_T_88 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_89 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_90 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_91 = or(_io_vcalloc_req_bits_T_88, _io_vcalloc_req_bits_T_89) node _io_vcalloc_req_bits_T_92 = or(_io_vcalloc_req_bits_T_91, _io_vcalloc_req_bits_T_90) wire _io_vcalloc_req_bits_WIRE_26 : UInt<3> connect _io_vcalloc_req_bits_WIRE_26, _io_vcalloc_req_bits_T_92 connect _io_vcalloc_req_bits_WIRE_23.ingress_node_id, _io_vcalloc_req_bits_WIRE_26 node _io_vcalloc_req_bits_T_93 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_94 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_95 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.ingress_node, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_96 = or(_io_vcalloc_req_bits_T_93, _io_vcalloc_req_bits_T_94) node _io_vcalloc_req_bits_T_97 = or(_io_vcalloc_req_bits_T_96, _io_vcalloc_req_bits_T_95) wire _io_vcalloc_req_bits_WIRE_27 : UInt<4> connect _io_vcalloc_req_bits_WIRE_27, _io_vcalloc_req_bits_T_97 connect _io_vcalloc_req_bits_WIRE_23.ingress_node, _io_vcalloc_req_bits_WIRE_27 node _io_vcalloc_req_bits_T_98 = mux(_io_vcalloc_req_bits_T, vcalloc_reqs[0].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_99 = mux(_io_vcalloc_req_bits_T_1, vcalloc_reqs[1].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_100 = mux(_io_vcalloc_req_bits_T_2, vcalloc_reqs[2].flow.vnet_id, UInt<1>(0h0)) node _io_vcalloc_req_bits_T_101 = or(_io_vcalloc_req_bits_T_98, _io_vcalloc_req_bits_T_99) node _io_vcalloc_req_bits_T_102 = or(_io_vcalloc_req_bits_T_101, _io_vcalloc_req_bits_T_100) wire _io_vcalloc_req_bits_WIRE_28 : UInt<2> connect _io_vcalloc_req_bits_WIRE_28, _io_vcalloc_req_bits_T_102 connect _io_vcalloc_req_bits_WIRE_23.vnet_id, _io_vcalloc_req_bits_WIRE_28 connect _io_vcalloc_req_bits_WIRE.flow, _io_vcalloc_req_bits_WIRE_23 connect io.vcalloc_req.bits, _io_vcalloc_req_bits_WIRE node _vcalloc_vals_0_T = eq(states[0].g, UInt<3>(0h2)) node _vcalloc_vals_0_T_1 = eq(states[0].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_0_T_2 = and(_vcalloc_vals_0_T, _vcalloc_vals_0_T_1) connect vcalloc_vals[0], _vcalloc_vals_0_T_2 connect vcalloc_reqs[0].in_vc, UInt<1>(0h0) connect vcalloc_reqs[0].vc_sel.`0`, states[0].vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, states[0].vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, states[0].vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, states[0].vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, states[0].vc_sel.`4` connect vcalloc_reqs[0].vc_sel.`5`, states[0].vc_sel.`5` connect vcalloc_reqs[0].flow, states[0].flow node _T_25 = bits(vcalloc_sel, 0, 0) node _T_26 = and(vcalloc_vals[0], _T_25) node _T_27 = and(_T_26, io.vcalloc_req.ready) when _T_27 : connect states[0].g, UInt<3>(0h3) node _T_28 = and(route_arbiter.io.in[0].ready, route_arbiter.io.in[0].valid) when _T_28 : connect vcalloc_vals[0], UInt<1>(0h1) connect vcalloc_reqs[0].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[0].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[0].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[0].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[0].vc_sel.`4`, io.router_resp.vc_sel.`4` connect vcalloc_reqs[0].vc_sel.`5`, io.router_resp.vc_sel.`5` node _vcalloc_vals_1_T = eq(states[1].g, UInt<3>(0h2)) node _vcalloc_vals_1_T_1 = eq(states[1].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_1_T_2 = and(_vcalloc_vals_1_T, _vcalloc_vals_1_T_1) connect vcalloc_vals[1], _vcalloc_vals_1_T_2 connect vcalloc_reqs[1].in_vc, UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, states[1].vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, states[1].vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, states[1].vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, states[1].vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, states[1].vc_sel.`4` connect vcalloc_reqs[1].vc_sel.`5`, states[1].vc_sel.`5` connect vcalloc_reqs[1].flow, states[1].flow node _T_29 = bits(vcalloc_sel, 1, 1) node _T_30 = and(vcalloc_vals[1], _T_29) node _T_31 = and(_T_30, io.vcalloc_req.ready) when _T_31 : connect states[1].g, UInt<3>(0h3) node _T_32 = and(route_arbiter.io.in[1].ready, route_arbiter.io.in[1].valid) when _T_32 : connect vcalloc_vals[1], UInt<1>(0h1) connect vcalloc_reqs[1].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[1].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[1].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[1].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[1].vc_sel.`4`, io.router_resp.vc_sel.`4` connect vcalloc_reqs[1].vc_sel.`5`, io.router_resp.vc_sel.`5` node _vcalloc_vals_2_T = eq(states[2].g, UInt<3>(0h2)) node _vcalloc_vals_2_T_1 = eq(states[2].fifo_deps, UInt<1>(0h0)) node _vcalloc_vals_2_T_2 = and(_vcalloc_vals_2_T, _vcalloc_vals_2_T_1) connect vcalloc_vals[2], _vcalloc_vals_2_T_2 connect vcalloc_reqs[2].in_vc, UInt<2>(0h2) connect vcalloc_reqs[2].vc_sel.`0`, states[2].vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, states[2].vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, states[2].vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, states[2].vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, states[2].vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, states[2].vc_sel.`5` connect vcalloc_reqs[2].flow, states[2].flow node _T_33 = bits(vcalloc_sel, 2, 2) node _T_34 = and(vcalloc_vals[2], _T_33) node _T_35 = and(_T_34, io.vcalloc_req.ready) when _T_35 : connect states[2].g, UInt<3>(0h3) node _T_36 = and(route_arbiter.io.in[2].ready, route_arbiter.io.in[2].valid) when _T_36 : connect vcalloc_vals[2], UInt<1>(0h1) connect vcalloc_reqs[2].vc_sel.`0`, io.router_resp.vc_sel.`0` connect vcalloc_reqs[2].vc_sel.`1`, io.router_resp.vc_sel.`1` connect vcalloc_reqs[2].vc_sel.`2`, io.router_resp.vc_sel.`2` connect vcalloc_reqs[2].vc_sel.`3`, io.router_resp.vc_sel.`3` connect vcalloc_reqs[2].vc_sel.`4`, io.router_resp.vc_sel.`4` connect vcalloc_reqs[2].vc_sel.`5`, io.router_resp.vc_sel.`5` node _io_debug_va_stall_T = add(vcalloc_vals[1], vcalloc_vals[2]) node _io_debug_va_stall_T_1 = bits(_io_debug_va_stall_T, 1, 0) node _io_debug_va_stall_T_2 = add(vcalloc_vals[0], _io_debug_va_stall_T_1) node _io_debug_va_stall_T_3 = bits(_io_debug_va_stall_T_2, 1, 0) node _io_debug_va_stall_T_4 = sub(_io_debug_va_stall_T_3, io.vcalloc_req.ready) node _io_debug_va_stall_T_5 = tail(_io_debug_va_stall_T_4, 1) connect io.debug.va_stall, _io_debug_va_stall_T_5 node _T_37 = and(io.vcalloc_req.ready, io.vcalloc_req.valid) when _T_37 : node _T_38 = bits(vcalloc_sel, 0, 0) when _T_38 : connect states[0].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[0].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[0].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[0].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[0].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[0].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[0].g, UInt<3>(0h3) node _T_39 = bits(vcalloc_sel, 1, 1) when _T_39 : connect states[1].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[1].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[1].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[1].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[1].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[1].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[1].g, UInt<3>(0h3) node _T_40 = bits(vcalloc_sel, 2, 2) when _T_40 : connect states[2].vc_sel.`0`, io.vcalloc_resp.vc_sel.`0` connect states[2].vc_sel.`1`, io.vcalloc_resp.vc_sel.`1` connect states[2].vc_sel.`2`, io.vcalloc_resp.vc_sel.`2` connect states[2].vc_sel.`3`, io.vcalloc_resp.vc_sel.`3` connect states[2].vc_sel.`4`, io.vcalloc_resp.vc_sel.`4` connect states[2].vc_sel.`5`, io.vcalloc_resp.vc_sel.`5` connect states[2].g, UInt<3>(0h3) inst salloc_arb of SwitchArbiter_70 connect salloc_arb.clock, clock connect salloc_arb.reset, reset node credit_available_hi = cat(states[0].vc_sel.`0`[2], states[0].vc_sel.`0`[1]) node _credit_available_T = cat(credit_available_hi, states[0].vc_sel.`0`[0]) node credit_available_hi_1 = cat(states[0].vc_sel.`1`[2], states[0].vc_sel.`1`[1]) node _credit_available_T_1 = cat(credit_available_hi_1, states[0].vc_sel.`1`[0]) node credit_available_hi_2 = cat(states[0].vc_sel.`2`[2], states[0].vc_sel.`2`[1]) node _credit_available_T_2 = cat(credit_available_hi_2, states[0].vc_sel.`2`[0]) node credit_available_hi_3 = cat(states[0].vc_sel.`3`[2], states[0].vc_sel.`3`[1]) node _credit_available_T_3 = cat(credit_available_hi_3, states[0].vc_sel.`3`[0]) node credit_available_lo_hi = cat(_credit_available_T_2, _credit_available_T_1) node credit_available_lo = cat(credit_available_lo_hi, _credit_available_T) node credit_available_hi_hi = cat(states[0].vc_sel.`5`[0], states[0].vc_sel.`4`[0]) node credit_available_hi_4 = cat(credit_available_hi_hi, _credit_available_T_3) node _credit_available_T_4 = cat(credit_available_hi_4, credit_available_lo) node credit_available_hi_5 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_5 = cat(credit_available_hi_5, io.out_credit_available.`0`[0]) node credit_available_hi_6 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_6 = cat(credit_available_hi_6, io.out_credit_available.`1`[0]) node credit_available_hi_7 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_7 = cat(credit_available_hi_7, io.out_credit_available.`2`[0]) node credit_available_hi_8 = cat(io.out_credit_available.`3`[2], io.out_credit_available.`3`[1]) node _credit_available_T_8 = cat(credit_available_hi_8, io.out_credit_available.`3`[0]) node credit_available_lo_hi_1 = cat(_credit_available_T_7, _credit_available_T_6) node credit_available_lo_1 = cat(credit_available_lo_hi_1, _credit_available_T_5) node credit_available_hi_hi_1 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_9 = cat(credit_available_hi_hi_1, _credit_available_T_8) node _credit_available_T_9 = cat(credit_available_hi_9, credit_available_lo_1) node _credit_available_T_10 = and(_credit_available_T_4, _credit_available_T_9) node credit_available = neq(_credit_available_T_10, UInt<1>(0h0)) node _salloc_arb_io_in_0_valid_T = eq(states[0].g, UInt<3>(0h3)) node _salloc_arb_io_in_0_valid_T_1 = and(_salloc_arb_io_in_0_valid_T, credit_available) node _salloc_arb_io_in_0_valid_T_2 = and(_salloc_arb_io_in_0_valid_T_1, input_buffer.io.deq[0].valid) connect salloc_arb.io.in[0].valid, _salloc_arb_io_in_0_valid_T_2 connect salloc_arb.io.in[0].bits.vc_sel.`0`[0], states[0].vc_sel.`0`[0] connect salloc_arb.io.in[0].bits.vc_sel.`0`[1], states[0].vc_sel.`0`[1] connect salloc_arb.io.in[0].bits.vc_sel.`0`[2], states[0].vc_sel.`0`[2] connect salloc_arb.io.in[0].bits.vc_sel.`1`[0], states[0].vc_sel.`1`[0] connect salloc_arb.io.in[0].bits.vc_sel.`1`[1], states[0].vc_sel.`1`[1] connect salloc_arb.io.in[0].bits.vc_sel.`1`[2], states[0].vc_sel.`1`[2] connect salloc_arb.io.in[0].bits.vc_sel.`2`[0], states[0].vc_sel.`2`[0] connect salloc_arb.io.in[0].bits.vc_sel.`2`[1], states[0].vc_sel.`2`[1] connect salloc_arb.io.in[0].bits.vc_sel.`2`[2], states[0].vc_sel.`2`[2] connect salloc_arb.io.in[0].bits.vc_sel.`3`[0], states[0].vc_sel.`3`[0] connect salloc_arb.io.in[0].bits.vc_sel.`3`[1], states[0].vc_sel.`3`[1] connect salloc_arb.io.in[0].bits.vc_sel.`3`[2], states[0].vc_sel.`3`[2] connect salloc_arb.io.in[0].bits.vc_sel.`4`[0], states[0].vc_sel.`4`[0] connect salloc_arb.io.in[0].bits.vc_sel.`5`[0], states[0].vc_sel.`5`[0] connect salloc_arb.io.in[0].bits.tail, input_buffer.io.deq[0].bits.tail node _T_41 = and(salloc_arb.io.in[0].ready, salloc_arb.io.in[0].valid) node _T_42 = and(_T_41, input_buffer.io.deq[0].bits.tail) when _T_42 : connect states[0].g, UInt<3>(0h0) connect input_buffer.io.deq[0].ready, salloc_arb.io.in[0].ready node credit_available_hi_10 = cat(states[1].vc_sel.`0`[2], states[1].vc_sel.`0`[1]) node _credit_available_T_11 = cat(credit_available_hi_10, states[1].vc_sel.`0`[0]) node credit_available_hi_11 = cat(states[1].vc_sel.`1`[2], states[1].vc_sel.`1`[1]) node _credit_available_T_12 = cat(credit_available_hi_11, states[1].vc_sel.`1`[0]) node credit_available_hi_12 = cat(states[1].vc_sel.`2`[2], states[1].vc_sel.`2`[1]) node _credit_available_T_13 = cat(credit_available_hi_12, states[1].vc_sel.`2`[0]) node credit_available_hi_13 = cat(states[1].vc_sel.`3`[2], states[1].vc_sel.`3`[1]) node _credit_available_T_14 = cat(credit_available_hi_13, states[1].vc_sel.`3`[0]) node credit_available_lo_hi_2 = cat(_credit_available_T_13, _credit_available_T_12) node credit_available_lo_2 = cat(credit_available_lo_hi_2, _credit_available_T_11) node credit_available_hi_hi_2 = cat(states[1].vc_sel.`5`[0], states[1].vc_sel.`4`[0]) node credit_available_hi_14 = cat(credit_available_hi_hi_2, _credit_available_T_14) node _credit_available_T_15 = cat(credit_available_hi_14, credit_available_lo_2) node credit_available_hi_15 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_16 = cat(credit_available_hi_15, io.out_credit_available.`0`[0]) node credit_available_hi_16 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_17 = cat(credit_available_hi_16, io.out_credit_available.`1`[0]) node credit_available_hi_17 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_18 = cat(credit_available_hi_17, io.out_credit_available.`2`[0]) node credit_available_hi_18 = cat(io.out_credit_available.`3`[2], io.out_credit_available.`3`[1]) node _credit_available_T_19 = cat(credit_available_hi_18, io.out_credit_available.`3`[0]) node credit_available_lo_hi_3 = cat(_credit_available_T_18, _credit_available_T_17) node credit_available_lo_3 = cat(credit_available_lo_hi_3, _credit_available_T_16) node credit_available_hi_hi_3 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_19 = cat(credit_available_hi_hi_3, _credit_available_T_19) node _credit_available_T_20 = cat(credit_available_hi_19, credit_available_lo_3) node _credit_available_T_21 = and(_credit_available_T_15, _credit_available_T_20) node credit_available_1 = neq(_credit_available_T_21, UInt<1>(0h0)) node _salloc_arb_io_in_1_valid_T = eq(states[1].g, UInt<3>(0h3)) node _salloc_arb_io_in_1_valid_T_1 = and(_salloc_arb_io_in_1_valid_T, credit_available_1) node _salloc_arb_io_in_1_valid_T_2 = and(_salloc_arb_io_in_1_valid_T_1, input_buffer.io.deq[1].valid) connect salloc_arb.io.in[1].valid, _salloc_arb_io_in_1_valid_T_2 connect salloc_arb.io.in[1].bits.vc_sel.`0`[0], states[1].vc_sel.`0`[0] connect salloc_arb.io.in[1].bits.vc_sel.`0`[1], states[1].vc_sel.`0`[1] connect salloc_arb.io.in[1].bits.vc_sel.`0`[2], states[1].vc_sel.`0`[2] connect salloc_arb.io.in[1].bits.vc_sel.`1`[0], states[1].vc_sel.`1`[0] connect salloc_arb.io.in[1].bits.vc_sel.`1`[1], states[1].vc_sel.`1`[1] connect salloc_arb.io.in[1].bits.vc_sel.`1`[2], states[1].vc_sel.`1`[2] connect salloc_arb.io.in[1].bits.vc_sel.`2`[0], states[1].vc_sel.`2`[0] connect salloc_arb.io.in[1].bits.vc_sel.`2`[1], states[1].vc_sel.`2`[1] connect salloc_arb.io.in[1].bits.vc_sel.`2`[2], states[1].vc_sel.`2`[2] connect salloc_arb.io.in[1].bits.vc_sel.`3`[0], states[1].vc_sel.`3`[0] connect salloc_arb.io.in[1].bits.vc_sel.`3`[1], states[1].vc_sel.`3`[1] connect salloc_arb.io.in[1].bits.vc_sel.`3`[2], states[1].vc_sel.`3`[2] connect salloc_arb.io.in[1].bits.vc_sel.`4`[0], states[1].vc_sel.`4`[0] connect salloc_arb.io.in[1].bits.vc_sel.`5`[0], states[1].vc_sel.`5`[0] connect salloc_arb.io.in[1].bits.tail, input_buffer.io.deq[1].bits.tail node _T_43 = and(salloc_arb.io.in[1].ready, salloc_arb.io.in[1].valid) node _T_44 = and(_T_43, input_buffer.io.deq[1].bits.tail) when _T_44 : connect states[1].g, UInt<3>(0h0) connect input_buffer.io.deq[1].ready, salloc_arb.io.in[1].ready node credit_available_hi_20 = cat(states[2].vc_sel.`0`[2], states[2].vc_sel.`0`[1]) node _credit_available_T_22 = cat(credit_available_hi_20, states[2].vc_sel.`0`[0]) node credit_available_hi_21 = cat(states[2].vc_sel.`1`[2], states[2].vc_sel.`1`[1]) node _credit_available_T_23 = cat(credit_available_hi_21, states[2].vc_sel.`1`[0]) node credit_available_hi_22 = cat(states[2].vc_sel.`2`[2], states[2].vc_sel.`2`[1]) node _credit_available_T_24 = cat(credit_available_hi_22, states[2].vc_sel.`2`[0]) node credit_available_hi_23 = cat(states[2].vc_sel.`3`[2], states[2].vc_sel.`3`[1]) node _credit_available_T_25 = cat(credit_available_hi_23, states[2].vc_sel.`3`[0]) node credit_available_lo_hi_4 = cat(_credit_available_T_24, _credit_available_T_23) node credit_available_lo_4 = cat(credit_available_lo_hi_4, _credit_available_T_22) node credit_available_hi_hi_4 = cat(states[2].vc_sel.`5`[0], states[2].vc_sel.`4`[0]) node credit_available_hi_24 = cat(credit_available_hi_hi_4, _credit_available_T_25) node _credit_available_T_26 = cat(credit_available_hi_24, credit_available_lo_4) node credit_available_hi_25 = cat(io.out_credit_available.`0`[2], io.out_credit_available.`0`[1]) node _credit_available_T_27 = cat(credit_available_hi_25, io.out_credit_available.`0`[0]) node credit_available_hi_26 = cat(io.out_credit_available.`1`[2], io.out_credit_available.`1`[1]) node _credit_available_T_28 = cat(credit_available_hi_26, io.out_credit_available.`1`[0]) node credit_available_hi_27 = cat(io.out_credit_available.`2`[2], io.out_credit_available.`2`[1]) node _credit_available_T_29 = cat(credit_available_hi_27, io.out_credit_available.`2`[0]) node credit_available_hi_28 = cat(io.out_credit_available.`3`[2], io.out_credit_available.`3`[1]) node _credit_available_T_30 = cat(credit_available_hi_28, io.out_credit_available.`3`[0]) node credit_available_lo_hi_5 = cat(_credit_available_T_29, _credit_available_T_28) node credit_available_lo_5 = cat(credit_available_lo_hi_5, _credit_available_T_27) node credit_available_hi_hi_5 = cat(io.out_credit_available.`5`[0], io.out_credit_available.`4`[0]) node credit_available_hi_29 = cat(credit_available_hi_hi_5, _credit_available_T_30) node _credit_available_T_31 = cat(credit_available_hi_29, credit_available_lo_5) node _credit_available_T_32 = and(_credit_available_T_26, _credit_available_T_31) node credit_available_2 = neq(_credit_available_T_32, UInt<1>(0h0)) node _salloc_arb_io_in_2_valid_T = eq(states[2].g, UInt<3>(0h3)) node _salloc_arb_io_in_2_valid_T_1 = and(_salloc_arb_io_in_2_valid_T, credit_available_2) node _salloc_arb_io_in_2_valid_T_2 = and(_salloc_arb_io_in_2_valid_T_1, input_buffer.io.deq[2].valid) connect salloc_arb.io.in[2].valid, _salloc_arb_io_in_2_valid_T_2 connect salloc_arb.io.in[2].bits.vc_sel.`0`[0], states[2].vc_sel.`0`[0] connect salloc_arb.io.in[2].bits.vc_sel.`0`[1], states[2].vc_sel.`0`[1] connect salloc_arb.io.in[2].bits.vc_sel.`0`[2], states[2].vc_sel.`0`[2] connect salloc_arb.io.in[2].bits.vc_sel.`1`[0], states[2].vc_sel.`1`[0] connect salloc_arb.io.in[2].bits.vc_sel.`1`[1], states[2].vc_sel.`1`[1] connect salloc_arb.io.in[2].bits.vc_sel.`1`[2], states[2].vc_sel.`1`[2] connect salloc_arb.io.in[2].bits.vc_sel.`2`[0], states[2].vc_sel.`2`[0] connect salloc_arb.io.in[2].bits.vc_sel.`2`[1], states[2].vc_sel.`2`[1] connect salloc_arb.io.in[2].bits.vc_sel.`2`[2], states[2].vc_sel.`2`[2] connect salloc_arb.io.in[2].bits.vc_sel.`3`[0], states[2].vc_sel.`3`[0] connect salloc_arb.io.in[2].bits.vc_sel.`3`[1], states[2].vc_sel.`3`[1] connect salloc_arb.io.in[2].bits.vc_sel.`3`[2], states[2].vc_sel.`3`[2] connect salloc_arb.io.in[2].bits.vc_sel.`4`[0], states[2].vc_sel.`4`[0] connect salloc_arb.io.in[2].bits.vc_sel.`5`[0], states[2].vc_sel.`5`[0] connect salloc_arb.io.in[2].bits.tail, input_buffer.io.deq[2].bits.tail node _T_45 = and(salloc_arb.io.in[2].ready, salloc_arb.io.in[2].valid) node _T_46 = and(_T_45, input_buffer.io.deq[2].bits.tail) when _T_46 : connect states[2].g, UInt<3>(0h0) connect input_buffer.io.deq[2].ready, salloc_arb.io.in[2].ready node _io_debug_sa_stall_T = eq(salloc_arb.io.in[0].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_1 = and(salloc_arb.io.in[0].valid, _io_debug_sa_stall_T) node _io_debug_sa_stall_T_2 = eq(salloc_arb.io.in[1].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_3 = and(salloc_arb.io.in[1].valid, _io_debug_sa_stall_T_2) node _io_debug_sa_stall_T_4 = eq(salloc_arb.io.in[2].ready, UInt<1>(0h0)) node _io_debug_sa_stall_T_5 = and(salloc_arb.io.in[2].valid, _io_debug_sa_stall_T_4) node _io_debug_sa_stall_T_6 = add(_io_debug_sa_stall_T_3, _io_debug_sa_stall_T_5) node _io_debug_sa_stall_T_7 = bits(_io_debug_sa_stall_T_6, 1, 0) node _io_debug_sa_stall_T_8 = add(_io_debug_sa_stall_T_1, _io_debug_sa_stall_T_7) node _io_debug_sa_stall_T_9 = bits(_io_debug_sa_stall_T_8, 1, 0) connect io.debug.sa_stall, _io_debug_sa_stall_T_9 connect io.salloc_req[0].bits, salloc_arb.io.out[0].bits connect io.salloc_req[0].valid, salloc_arb.io.out[0].valid connect salloc_arb.io.out[0].ready, io.salloc_req[0].ready when io.block : connect salloc_arb.io.out[0].ready, UInt<1>(0h0) connect io.salloc_req[0].valid, UInt<1>(0h0) wire salloc_outs : { valid : UInt<1>, vid : UInt<2>, out_vid : UInt<2>, flit : { head : UInt<1>, tail : UInt<1>, payload : UInt<145>, flow : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>}, virt_channel_id : UInt<2>}}[1] node _io_in_credit_return_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_credit_return_T_1 = mux(_io_in_credit_return_T, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.credit_return, _io_in_credit_return_T_1 node _io_in_vc_free_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) node _io_in_vc_free_T_1 = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _io_in_vc_free_T_2 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _io_in_vc_free_T_3 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _io_in_vc_free_T_4 = mux(_io_in_vc_free_T_1, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_5 = mux(_io_in_vc_free_T_2, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_6 = mux(_io_in_vc_free_T_3, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _io_in_vc_free_T_7 = or(_io_in_vc_free_T_4, _io_in_vc_free_T_5) node _io_in_vc_free_T_8 = or(_io_in_vc_free_T_7, _io_in_vc_free_T_6) wire _io_in_vc_free_WIRE : UInt<1> connect _io_in_vc_free_WIRE, _io_in_vc_free_T_8 node _io_in_vc_free_T_9 = and(_io_in_vc_free_T, _io_in_vc_free_WIRE) node _io_in_vc_free_T_10 = mux(_io_in_vc_free_T_9, salloc_arb.io.chosen_oh[0], UInt<1>(0h0)) connect io.in.vc_free, _io_in_vc_free_T_10 node _salloc_outs_0_valid_T = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) connect salloc_outs[0].valid, _salloc_outs_0_valid_T node salloc_outs_0_vid_hi = bits(salloc_arb.io.chosen_oh[0], 2, 2) node salloc_outs_0_vid_lo = bits(salloc_arb.io.chosen_oh[0], 1, 0) node _salloc_outs_0_vid_T = orr(salloc_outs_0_vid_hi) node _salloc_outs_0_vid_T_1 = or(salloc_outs_0_vid_hi, salloc_outs_0_vid_lo) node _salloc_outs_0_vid_T_2 = bits(_salloc_outs_0_vid_T_1, 1, 1) node _salloc_outs_0_vid_T_3 = cat(_salloc_outs_0_vid_T, _salloc_outs_0_vid_T_2) connect salloc_outs[0].vid, _salloc_outs_0_vid_T_3 node _vc_sel_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _vc_sel_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _vc_sel_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire vc_sel : { `5` : UInt<1>[1], `4` : UInt<1>[1], `3` : UInt<1>[3], `2` : UInt<1>[3], `1` : UInt<1>[3], `0` : UInt<1>[3]} wire _vc_sel_WIRE : UInt<1>[3] node _vc_sel_T_3 = mux(_vc_sel_T, states[0].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_4 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_5 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[0], UInt<1>(0h0)) node _vc_sel_T_6 = or(_vc_sel_T_3, _vc_sel_T_4) node _vc_sel_T_7 = or(_vc_sel_T_6, _vc_sel_T_5) wire _vc_sel_WIRE_1 : UInt<1> connect _vc_sel_WIRE_1, _vc_sel_T_7 connect _vc_sel_WIRE[0], _vc_sel_WIRE_1 node _vc_sel_T_8 = mux(_vc_sel_T, states[0].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_9 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_10 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[1], UInt<1>(0h0)) node _vc_sel_T_11 = or(_vc_sel_T_8, _vc_sel_T_9) node _vc_sel_T_12 = or(_vc_sel_T_11, _vc_sel_T_10) wire _vc_sel_WIRE_2 : UInt<1> connect _vc_sel_WIRE_2, _vc_sel_T_12 connect _vc_sel_WIRE[1], _vc_sel_WIRE_2 node _vc_sel_T_13 = mux(_vc_sel_T, states[0].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_14 = mux(_vc_sel_T_1, states[1].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_15 = mux(_vc_sel_T_2, states[2].vc_sel.`0`[2], UInt<1>(0h0)) node _vc_sel_T_16 = or(_vc_sel_T_13, _vc_sel_T_14) node _vc_sel_T_17 = or(_vc_sel_T_16, _vc_sel_T_15) wire _vc_sel_WIRE_3 : UInt<1> connect _vc_sel_WIRE_3, _vc_sel_T_17 connect _vc_sel_WIRE[2], _vc_sel_WIRE_3 connect vc_sel.`0`, _vc_sel_WIRE wire _vc_sel_WIRE_4 : UInt<1>[3] node _vc_sel_T_18 = mux(_vc_sel_T, states[0].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_19 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_20 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[0], UInt<1>(0h0)) node _vc_sel_T_21 = or(_vc_sel_T_18, _vc_sel_T_19) node _vc_sel_T_22 = or(_vc_sel_T_21, _vc_sel_T_20) wire _vc_sel_WIRE_5 : UInt<1> connect _vc_sel_WIRE_5, _vc_sel_T_22 connect _vc_sel_WIRE_4[0], _vc_sel_WIRE_5 node _vc_sel_T_23 = mux(_vc_sel_T, states[0].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_24 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_25 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[1], UInt<1>(0h0)) node _vc_sel_T_26 = or(_vc_sel_T_23, _vc_sel_T_24) node _vc_sel_T_27 = or(_vc_sel_T_26, _vc_sel_T_25) wire _vc_sel_WIRE_6 : UInt<1> connect _vc_sel_WIRE_6, _vc_sel_T_27 connect _vc_sel_WIRE_4[1], _vc_sel_WIRE_6 node _vc_sel_T_28 = mux(_vc_sel_T, states[0].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_29 = mux(_vc_sel_T_1, states[1].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_30 = mux(_vc_sel_T_2, states[2].vc_sel.`1`[2], UInt<1>(0h0)) node _vc_sel_T_31 = or(_vc_sel_T_28, _vc_sel_T_29) node _vc_sel_T_32 = or(_vc_sel_T_31, _vc_sel_T_30) wire _vc_sel_WIRE_7 : UInt<1> connect _vc_sel_WIRE_7, _vc_sel_T_32 connect _vc_sel_WIRE_4[2], _vc_sel_WIRE_7 connect vc_sel.`1`, _vc_sel_WIRE_4 wire _vc_sel_WIRE_8 : UInt<1>[3] node _vc_sel_T_33 = mux(_vc_sel_T, states[0].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_34 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_35 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[0], UInt<1>(0h0)) node _vc_sel_T_36 = or(_vc_sel_T_33, _vc_sel_T_34) node _vc_sel_T_37 = or(_vc_sel_T_36, _vc_sel_T_35) wire _vc_sel_WIRE_9 : UInt<1> connect _vc_sel_WIRE_9, _vc_sel_T_37 connect _vc_sel_WIRE_8[0], _vc_sel_WIRE_9 node _vc_sel_T_38 = mux(_vc_sel_T, states[0].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_39 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_40 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[1], UInt<1>(0h0)) node _vc_sel_T_41 = or(_vc_sel_T_38, _vc_sel_T_39) node _vc_sel_T_42 = or(_vc_sel_T_41, _vc_sel_T_40) wire _vc_sel_WIRE_10 : UInt<1> connect _vc_sel_WIRE_10, _vc_sel_T_42 connect _vc_sel_WIRE_8[1], _vc_sel_WIRE_10 node _vc_sel_T_43 = mux(_vc_sel_T, states[0].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_44 = mux(_vc_sel_T_1, states[1].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_45 = mux(_vc_sel_T_2, states[2].vc_sel.`2`[2], UInt<1>(0h0)) node _vc_sel_T_46 = or(_vc_sel_T_43, _vc_sel_T_44) node _vc_sel_T_47 = or(_vc_sel_T_46, _vc_sel_T_45) wire _vc_sel_WIRE_11 : UInt<1> connect _vc_sel_WIRE_11, _vc_sel_T_47 connect _vc_sel_WIRE_8[2], _vc_sel_WIRE_11 connect vc_sel.`2`, _vc_sel_WIRE_8 wire _vc_sel_WIRE_12 : UInt<1>[3] node _vc_sel_T_48 = mux(_vc_sel_T, states[0].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_49 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_50 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[0], UInt<1>(0h0)) node _vc_sel_T_51 = or(_vc_sel_T_48, _vc_sel_T_49) node _vc_sel_T_52 = or(_vc_sel_T_51, _vc_sel_T_50) wire _vc_sel_WIRE_13 : UInt<1> connect _vc_sel_WIRE_13, _vc_sel_T_52 connect _vc_sel_WIRE_12[0], _vc_sel_WIRE_13 node _vc_sel_T_53 = mux(_vc_sel_T, states[0].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_54 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_55 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[1], UInt<1>(0h0)) node _vc_sel_T_56 = or(_vc_sel_T_53, _vc_sel_T_54) node _vc_sel_T_57 = or(_vc_sel_T_56, _vc_sel_T_55) wire _vc_sel_WIRE_14 : UInt<1> connect _vc_sel_WIRE_14, _vc_sel_T_57 connect _vc_sel_WIRE_12[1], _vc_sel_WIRE_14 node _vc_sel_T_58 = mux(_vc_sel_T, states[0].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_59 = mux(_vc_sel_T_1, states[1].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_60 = mux(_vc_sel_T_2, states[2].vc_sel.`3`[2], UInt<1>(0h0)) node _vc_sel_T_61 = or(_vc_sel_T_58, _vc_sel_T_59) node _vc_sel_T_62 = or(_vc_sel_T_61, _vc_sel_T_60) wire _vc_sel_WIRE_15 : UInt<1> connect _vc_sel_WIRE_15, _vc_sel_T_62 connect _vc_sel_WIRE_12[2], _vc_sel_WIRE_15 connect vc_sel.`3`, _vc_sel_WIRE_12 wire _vc_sel_WIRE_16 : UInt<1>[1] node _vc_sel_T_63 = mux(_vc_sel_T, states[0].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_64 = mux(_vc_sel_T_1, states[1].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_65 = mux(_vc_sel_T_2, states[2].vc_sel.`4`[0], UInt<1>(0h0)) node _vc_sel_T_66 = or(_vc_sel_T_63, _vc_sel_T_64) node _vc_sel_T_67 = or(_vc_sel_T_66, _vc_sel_T_65) wire _vc_sel_WIRE_17 : UInt<1> connect _vc_sel_WIRE_17, _vc_sel_T_67 connect _vc_sel_WIRE_16[0], _vc_sel_WIRE_17 connect vc_sel.`4`, _vc_sel_WIRE_16 wire _vc_sel_WIRE_18 : UInt<1>[1] node _vc_sel_T_68 = mux(_vc_sel_T, states[0].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_69 = mux(_vc_sel_T_1, states[1].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_70 = mux(_vc_sel_T_2, states[2].vc_sel.`5`[0], UInt<1>(0h0)) node _vc_sel_T_71 = or(_vc_sel_T_68, _vc_sel_T_69) node _vc_sel_T_72 = or(_vc_sel_T_71, _vc_sel_T_70) wire _vc_sel_WIRE_19 : UInt<1> connect _vc_sel_WIRE_19, _vc_sel_T_72 connect _vc_sel_WIRE_18[0], _vc_sel_WIRE_19 connect vc_sel.`5`, _vc_sel_WIRE_18 node _channel_oh_T = or(vc_sel.`0`[0], vc_sel.`0`[1]) node channel_oh_0 = or(_channel_oh_T, vc_sel.`0`[2]) node _channel_oh_T_1 = or(vc_sel.`1`[0], vc_sel.`1`[1]) node channel_oh_1 = or(_channel_oh_T_1, vc_sel.`1`[2]) node _channel_oh_T_2 = or(vc_sel.`2`[0], vc_sel.`2`[1]) node channel_oh_2 = or(_channel_oh_T_2, vc_sel.`2`[2]) node _channel_oh_T_3 = or(vc_sel.`3`[0], vc_sel.`3`[1]) node channel_oh_3 = or(_channel_oh_T_3, vc_sel.`3`[2]) node virt_channel_hi = cat(vc_sel.`0`[2], vc_sel.`0`[1]) node _virt_channel_T = cat(virt_channel_hi, vc_sel.`0`[0]) node virt_channel_hi_1 = bits(_virt_channel_T, 2, 2) node virt_channel_lo = bits(_virt_channel_T, 1, 0) node _virt_channel_T_1 = orr(virt_channel_hi_1) node _virt_channel_T_2 = or(virt_channel_hi_1, virt_channel_lo) node _virt_channel_T_3 = bits(_virt_channel_T_2, 1, 1) node _virt_channel_T_4 = cat(_virt_channel_T_1, _virt_channel_T_3) node virt_channel_hi_2 = cat(vc_sel.`1`[2], vc_sel.`1`[1]) node _virt_channel_T_5 = cat(virt_channel_hi_2, vc_sel.`1`[0]) node virt_channel_hi_3 = bits(_virt_channel_T_5, 2, 2) node virt_channel_lo_1 = bits(_virt_channel_T_5, 1, 0) node _virt_channel_T_6 = orr(virt_channel_hi_3) node _virt_channel_T_7 = or(virt_channel_hi_3, virt_channel_lo_1) node _virt_channel_T_8 = bits(_virt_channel_T_7, 1, 1) node _virt_channel_T_9 = cat(_virt_channel_T_6, _virt_channel_T_8) node virt_channel_hi_4 = cat(vc_sel.`2`[2], vc_sel.`2`[1]) node _virt_channel_T_10 = cat(virt_channel_hi_4, vc_sel.`2`[0]) node virt_channel_hi_5 = bits(_virt_channel_T_10, 2, 2) node virt_channel_lo_2 = bits(_virt_channel_T_10, 1, 0) node _virt_channel_T_11 = orr(virt_channel_hi_5) node _virt_channel_T_12 = or(virt_channel_hi_5, virt_channel_lo_2) node _virt_channel_T_13 = bits(_virt_channel_T_12, 1, 1) node _virt_channel_T_14 = cat(_virt_channel_T_11, _virt_channel_T_13) node virt_channel_hi_6 = cat(vc_sel.`3`[2], vc_sel.`3`[1]) node _virt_channel_T_15 = cat(virt_channel_hi_6, vc_sel.`3`[0]) node virt_channel_hi_7 = bits(_virt_channel_T_15, 2, 2) node virt_channel_lo_3 = bits(_virt_channel_T_15, 1, 0) node _virt_channel_T_16 = orr(virt_channel_hi_7) node _virt_channel_T_17 = or(virt_channel_hi_7, virt_channel_lo_3) node _virt_channel_T_18 = bits(_virt_channel_T_17, 1, 1) node _virt_channel_T_19 = cat(_virt_channel_T_16, _virt_channel_T_18) node _virt_channel_T_20 = mux(channel_oh_0, _virt_channel_T_4, UInt<1>(0h0)) node _virt_channel_T_21 = mux(channel_oh_1, _virt_channel_T_9, UInt<1>(0h0)) node _virt_channel_T_22 = mux(channel_oh_2, _virt_channel_T_14, UInt<1>(0h0)) node _virt_channel_T_23 = mux(channel_oh_3, _virt_channel_T_19, UInt<1>(0h0)) node _virt_channel_T_24 = mux(vc_sel.`4`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_25 = mux(vc_sel.`5`[0], UInt<1>(0h0), UInt<1>(0h0)) node _virt_channel_T_26 = or(_virt_channel_T_20, _virt_channel_T_21) node _virt_channel_T_27 = or(_virt_channel_T_26, _virt_channel_T_22) node _virt_channel_T_28 = or(_virt_channel_T_27, _virt_channel_T_23) node _virt_channel_T_29 = or(_virt_channel_T_28, _virt_channel_T_24) node _virt_channel_T_30 = or(_virt_channel_T_29, _virt_channel_T_25) wire virt_channel : UInt<2> connect virt_channel, _virt_channel_T_30 node _T_47 = and(salloc_arb.io.out[0].ready, salloc_arb.io.out[0].valid) when _T_47 : connect salloc_outs[0].out_vid, virt_channel node _salloc_outs_0_flit_payload_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_payload_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_payload_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_payload_T_3 = mux(_salloc_outs_0_flit_payload_T, input_buffer.io.deq[0].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_4 = mux(_salloc_outs_0_flit_payload_T_1, input_buffer.io.deq[1].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_5 = mux(_salloc_outs_0_flit_payload_T_2, input_buffer.io.deq[2].bits.payload, UInt<1>(0h0)) node _salloc_outs_0_flit_payload_T_6 = or(_salloc_outs_0_flit_payload_T_3, _salloc_outs_0_flit_payload_T_4) node _salloc_outs_0_flit_payload_T_7 = or(_salloc_outs_0_flit_payload_T_6, _salloc_outs_0_flit_payload_T_5) wire _salloc_outs_0_flit_payload_WIRE : UInt<145> connect _salloc_outs_0_flit_payload_WIRE, _salloc_outs_0_flit_payload_T_7 connect salloc_outs[0].flit.payload, _salloc_outs_0_flit_payload_WIRE node _salloc_outs_0_flit_head_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_head_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_head_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_head_T_3 = mux(_salloc_outs_0_flit_head_T, input_buffer.io.deq[0].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_4 = mux(_salloc_outs_0_flit_head_T_1, input_buffer.io.deq[1].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_5 = mux(_salloc_outs_0_flit_head_T_2, input_buffer.io.deq[2].bits.head, UInt<1>(0h0)) node _salloc_outs_0_flit_head_T_6 = or(_salloc_outs_0_flit_head_T_3, _salloc_outs_0_flit_head_T_4) node _salloc_outs_0_flit_head_T_7 = or(_salloc_outs_0_flit_head_T_6, _salloc_outs_0_flit_head_T_5) wire _salloc_outs_0_flit_head_WIRE : UInt<1> connect _salloc_outs_0_flit_head_WIRE, _salloc_outs_0_flit_head_T_7 connect salloc_outs[0].flit.head, _salloc_outs_0_flit_head_WIRE node _salloc_outs_0_flit_tail_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_tail_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_tail_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) node _salloc_outs_0_flit_tail_T_3 = mux(_salloc_outs_0_flit_tail_T, input_buffer.io.deq[0].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_4 = mux(_salloc_outs_0_flit_tail_T_1, input_buffer.io.deq[1].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_5 = mux(_salloc_outs_0_flit_tail_T_2, input_buffer.io.deq[2].bits.tail, UInt<1>(0h0)) node _salloc_outs_0_flit_tail_T_6 = or(_salloc_outs_0_flit_tail_T_3, _salloc_outs_0_flit_tail_T_4) node _salloc_outs_0_flit_tail_T_7 = or(_salloc_outs_0_flit_tail_T_6, _salloc_outs_0_flit_tail_T_5) wire _salloc_outs_0_flit_tail_WIRE : UInt<1> connect _salloc_outs_0_flit_tail_WIRE, _salloc_outs_0_flit_tail_T_7 connect salloc_outs[0].flit.tail, _salloc_outs_0_flit_tail_WIRE node _salloc_outs_0_flit_flow_T = bits(salloc_arb.io.chosen_oh[0], 0, 0) node _salloc_outs_0_flit_flow_T_1 = bits(salloc_arb.io.chosen_oh[0], 1, 1) node _salloc_outs_0_flit_flow_T_2 = bits(salloc_arb.io.chosen_oh[0], 2, 2) wire _salloc_outs_0_flit_flow_WIRE : { vnet_id : UInt<2>, ingress_node : UInt<4>, ingress_node_id : UInt<3>, egress_node : UInt<4>, egress_node_id : UInt<2>} node _salloc_outs_0_flit_flow_T_3 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_4 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_5 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_6 = or(_salloc_outs_0_flit_flow_T_3, _salloc_outs_0_flit_flow_T_4) node _salloc_outs_0_flit_flow_T_7 = or(_salloc_outs_0_flit_flow_T_6, _salloc_outs_0_flit_flow_T_5) wire _salloc_outs_0_flit_flow_WIRE_1 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_1, _salloc_outs_0_flit_flow_T_7 connect _salloc_outs_0_flit_flow_WIRE.egress_node_id, _salloc_outs_0_flit_flow_WIRE_1 node _salloc_outs_0_flit_flow_T_8 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_9 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_10 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.egress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_11 = or(_salloc_outs_0_flit_flow_T_8, _salloc_outs_0_flit_flow_T_9) node _salloc_outs_0_flit_flow_T_12 = or(_salloc_outs_0_flit_flow_T_11, _salloc_outs_0_flit_flow_T_10) wire _salloc_outs_0_flit_flow_WIRE_2 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_2, _salloc_outs_0_flit_flow_T_12 connect _salloc_outs_0_flit_flow_WIRE.egress_node, _salloc_outs_0_flit_flow_WIRE_2 node _salloc_outs_0_flit_flow_T_13 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_14 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_15 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_16 = or(_salloc_outs_0_flit_flow_T_13, _salloc_outs_0_flit_flow_T_14) node _salloc_outs_0_flit_flow_T_17 = or(_salloc_outs_0_flit_flow_T_16, _salloc_outs_0_flit_flow_T_15) wire _salloc_outs_0_flit_flow_WIRE_3 : UInt<3> connect _salloc_outs_0_flit_flow_WIRE_3, _salloc_outs_0_flit_flow_T_17 connect _salloc_outs_0_flit_flow_WIRE.ingress_node_id, _salloc_outs_0_flit_flow_WIRE_3 node _salloc_outs_0_flit_flow_T_18 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_19 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_20 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.ingress_node, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_21 = or(_salloc_outs_0_flit_flow_T_18, _salloc_outs_0_flit_flow_T_19) node _salloc_outs_0_flit_flow_T_22 = or(_salloc_outs_0_flit_flow_T_21, _salloc_outs_0_flit_flow_T_20) wire _salloc_outs_0_flit_flow_WIRE_4 : UInt<4> connect _salloc_outs_0_flit_flow_WIRE_4, _salloc_outs_0_flit_flow_T_22 connect _salloc_outs_0_flit_flow_WIRE.ingress_node, _salloc_outs_0_flit_flow_WIRE_4 node _salloc_outs_0_flit_flow_T_23 = mux(_salloc_outs_0_flit_flow_T, states[0].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_24 = mux(_salloc_outs_0_flit_flow_T_1, states[1].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_25 = mux(_salloc_outs_0_flit_flow_T_2, states[2].flow.vnet_id, UInt<1>(0h0)) node _salloc_outs_0_flit_flow_T_26 = or(_salloc_outs_0_flit_flow_T_23, _salloc_outs_0_flit_flow_T_24) node _salloc_outs_0_flit_flow_T_27 = or(_salloc_outs_0_flit_flow_T_26, _salloc_outs_0_flit_flow_T_25) wire _salloc_outs_0_flit_flow_WIRE_5 : UInt<2> connect _salloc_outs_0_flit_flow_WIRE_5, _salloc_outs_0_flit_flow_T_27 connect _salloc_outs_0_flit_flow_WIRE.vnet_id, _salloc_outs_0_flit_flow_WIRE_5 connect salloc_outs[0].flit.flow, _salloc_outs_0_flit_flow_WIRE else : invalidate salloc_outs[0].out_vid invalidate salloc_outs[0].flit.virt_channel_id invalidate salloc_outs[0].flit.flow.egress_node_id invalidate salloc_outs[0].flit.flow.egress_node invalidate salloc_outs[0].flit.flow.ingress_node_id invalidate salloc_outs[0].flit.flow.ingress_node invalidate salloc_outs[0].flit.flow.vnet_id invalidate salloc_outs[0].flit.payload invalidate salloc_outs[0].flit.tail invalidate salloc_outs[0].flit.head invalidate salloc_outs[0].flit.virt_channel_id connect io.out[0].valid, salloc_outs[0].valid connect io.out[0].bits.flit, salloc_outs[0].flit connect io.out[0].bits.out_virt_channel, salloc_outs[0].out_vid connect states[0].vc_sel.`0`[1], UInt<1>(0h0) connect states[0].vc_sel.`0`[2], UInt<1>(0h0) connect states[0].vc_sel.`1`[1], UInt<1>(0h0) connect states[0].vc_sel.`1`[2], UInt<1>(0h0) connect states[0].vc_sel.`2`[0], UInt<1>(0h0) connect states[0].vc_sel.`2`[1], UInt<1>(0h0) connect states[0].vc_sel.`2`[2], UInt<1>(0h0) connect states[0].vc_sel.`3`[1], UInt<1>(0h0) connect states[0].vc_sel.`3`[2], UInt<1>(0h0) connect states[1].vc_sel.`0`[0], UInt<1>(0h0) connect states[1].vc_sel.`0`[2], UInt<1>(0h0) connect states[1].vc_sel.`1`[0], UInt<1>(0h0) connect states[1].vc_sel.`1`[1], UInt<1>(0h0) connect states[1].vc_sel.`1`[2], UInt<1>(0h0) connect states[1].vc_sel.`2`[0], UInt<1>(0h0) connect states[1].vc_sel.`2`[1], UInt<1>(0h0) connect states[1].vc_sel.`2`[2], UInt<1>(0h0) connect states[1].vc_sel.`3`[0], UInt<1>(0h0) connect states[1].vc_sel.`3`[1], UInt<1>(0h0) connect states[1].vc_sel.`3`[2], UInt<1>(0h0) connect states[2].vc_sel.`0`[0], UInt<1>(0h0) connect states[2].vc_sel.`0`[1], UInt<1>(0h0) connect states[2].vc_sel.`1`[0], UInt<1>(0h0) connect states[2].vc_sel.`1`[1], UInt<1>(0h0) connect states[2].vc_sel.`2`[0], UInt<1>(0h0) connect states[2].vc_sel.`2`[1], UInt<1>(0h0) connect states[2].vc_sel.`2`[2], UInt<1>(0h0) connect states[2].vc_sel.`3`[0], UInt<1>(0h0) connect states[2].vc_sel.`3`[1], UInt<1>(0h0) connect states[2].vc_sel.`3`[2], UInt<1>(0h0) node _T_48 = asUInt(reset) when _T_48 : connect states[0].g, UInt<3>(0h0) connect states[1].g, UInt<3>(0h0) connect states[2].g, UInt<3>(0h0)
module InputUnit_29( // @[InputUnit.scala:158:7] input clock, // @[InputUnit.scala:158:7] input reset, // @[InputUnit.scala:158:7] output [1:0] io_router_req_bits_src_virt_id, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_router_req_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_router_req_bits_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_router_req_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_3_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_2_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_router_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_req_ready, // @[InputUnit.scala:170:14] output io_vcalloc_req_valid, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_vcalloc_req_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_5_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_4_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_3_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_1_2, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_0, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_1, // @[InputUnit.scala:170:14] input io_vcalloc_resp_vc_sel_0_2, // @[InputUnit.scala:170:14] input io_out_credit_available_5_0, // @[InputUnit.scala:170:14] input io_out_credit_available_4_0, // @[InputUnit.scala:170:14] input io_out_credit_available_3_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_0, // @[InputUnit.scala:170:14] input io_out_credit_available_2_1, // @[InputUnit.scala:170:14] input io_out_credit_available_2_2, // @[InputUnit.scala:170:14] input io_out_credit_available_1_0, // @[InputUnit.scala:170:14] input io_out_credit_available_1_2, // @[InputUnit.scala:170:14] input io_out_credit_available_0_0, // @[InputUnit.scala:170:14] input io_out_credit_available_0_1, // @[InputUnit.scala:170:14] input io_out_credit_available_0_2, // @[InputUnit.scala:170:14] input io_salloc_req_0_ready, // @[InputUnit.scala:170:14] output io_salloc_req_0_valid, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_5_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_4_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_3_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_2_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_1_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_0, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_1, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_vc_sel_0_2, // @[InputUnit.scala:170:14] output io_salloc_req_0_bits_tail, // @[InputUnit.scala:170:14] output io_out_0_valid, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_head, // @[InputUnit.scala:170:14] output io_out_0_bits_flit_tail, // @[InputUnit.scala:170:14] output [144:0] io_out_0_bits_flit_payload, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_vnet_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_ingress_node, // @[InputUnit.scala:170:14] output [2:0] io_out_0_bits_flit_flow_ingress_node_id, // @[InputUnit.scala:170:14] output [3:0] io_out_0_bits_flit_flow_egress_node, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_flit_flow_egress_node_id, // @[InputUnit.scala:170:14] output [1:0] io_out_0_bits_out_virt_channel, // @[InputUnit.scala:170:14] output [1:0] io_debug_va_stall, // @[InputUnit.scala:170:14] output [1:0] io_debug_sa_stall, // @[InputUnit.scala:170:14] input io_in_flit_0_valid, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_head, // @[InputUnit.scala:170:14] input io_in_flit_0_bits_tail, // @[InputUnit.scala:170:14] input [144:0] io_in_flit_0_bits_payload, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_vnet_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_ingress_node, // @[InputUnit.scala:170:14] input [2:0] io_in_flit_0_bits_flow_ingress_node_id, // @[InputUnit.scala:170:14] input [3:0] io_in_flit_0_bits_flow_egress_node, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_flow_egress_node_id, // @[InputUnit.scala:170:14] input [1:0] io_in_flit_0_bits_virt_channel_id, // @[InputUnit.scala:170:14] output [2:0] io_in_credit_return, // @[InputUnit.scala:170:14] output [2:0] io_in_vc_free // @[InputUnit.scala:170:14] ); wire _GEN; // @[MixedVec.scala:116:9] wire _GEN_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_2_vc_sel_1_2; // @[MixedVec.scala:116:9] wire vcalloc_reqs_2_vc_sel_0_2; // @[MixedVec.scala:116:9] wire vcalloc_vals_2; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _GEN_1; // @[MixedVec.scala:116:9] wire _GEN_2; // @[MixedVec.scala:116:9] wire vcalloc_reqs_1_vc_sel_0_1; // @[MixedVec.scala:116:9] wire vcalloc_vals_1; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _GEN_3; // @[MixedVec.scala:116:9] wire _GEN_4; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_3_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_1_0; // @[MixedVec.scala:116:9] wire vcalloc_reqs_0_vc_sel_0_0; // @[MixedVec.scala:116:9] wire vcalloc_vals_0; // @[InputUnit.scala:266:25, :272:46, :273:29] wire _salloc_arb_io_in_0_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_1_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_in_2_ready; // @[InputUnit.scala:296:26] wire _salloc_arb_io_out_0_valid; // @[InputUnit.scala:296:26] wire [2:0] _salloc_arb_io_chosen_oh_0; // @[InputUnit.scala:296:26] wire _route_arbiter_io_in_1_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_in_2_ready; // @[InputUnit.scala:187:29] wire _route_arbiter_io_out_valid; // @[InputUnit.scala:187:29] wire [1:0] _route_arbiter_io_out_bits_src_virt_id; // @[InputUnit.scala:187:29] wire _input_buffer_io_deq_0_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_0_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_0_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_1_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_1_bits_payload; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_valid; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_head; // @[InputUnit.scala:181:28] wire _input_buffer_io_deq_2_bits_tail; // @[InputUnit.scala:181:28] wire [144:0] _input_buffer_io_deq_2_bits_payload; // @[InputUnit.scala:181:28] reg [2:0] states_0_g; // @[InputUnit.scala:192:19] reg states_0_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_3_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_1_0; // @[InputUnit.scala:192:19] reg states_0_vc_sel_0_0; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_0_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_0_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_0_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_1_g; // @[InputUnit.scala:192:19] reg states_1_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_1_vc_sel_0_1; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_1_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_1_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_1_flow_egress_node_id; // @[InputUnit.scala:192:19] reg [2:0] states_2_g; // @[InputUnit.scala:192:19] reg states_2_vc_sel_5_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_4_0; // @[InputUnit.scala:192:19] reg states_2_vc_sel_1_2; // @[InputUnit.scala:192:19] reg states_2_vc_sel_0_2; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_vnet_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_ingress_node; // @[InputUnit.scala:192:19] reg [2:0] states_2_flow_ingress_node_id; // @[InputUnit.scala:192:19] reg [3:0] states_2_flow_egress_node; // @[InputUnit.scala:192:19] reg [1:0] states_2_flow_egress_node_id; // @[InputUnit.scala:192:19] wire _GEN_5 = io_in_flit_0_valid & io_in_flit_0_bits_head; // @[InputUnit.scala:205:30] wire route_arbiter_io_in_0_valid = states_0_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire route_arbiter_io_in_1_valid = states_1_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_6 = _route_arbiter_io_in_1_ready & route_arbiter_io_in_1_valid; // @[Decoupled.scala:51:35] wire route_arbiter_io_in_2_valid = states_2_g == 3'h1; // @[InputUnit.scala:158:7, :192:19, :229:22] wire _GEN_7 = _route_arbiter_io_in_2_ready & route_arbiter_io_in_2_valid; // @[Decoupled.scala:51:35]
Generate the Verilog code corresponding to this FIRRTL code module RecFNToRecFN_38 : output io : { flip in : UInt<33>, flip roundingMode : UInt<3>, flip detectTininess : UInt<1>, out : UInt<33>, exceptionFlags : UInt<5>} node rawIn_exp = bits(io.in, 31, 23) node _rawIn_isZero_T = bits(rawIn_exp, 8, 6) node rawIn_isZero = eq(_rawIn_isZero_T, UInt<1>(0h0)) node _rawIn_isSpecial_T = bits(rawIn_exp, 8, 7) node rawIn_isSpecial = eq(_rawIn_isSpecial_T, UInt<2>(0h3)) wire rawIn : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<10>, sig : UInt<25>} node _rawIn_out_isNaN_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isNaN_T_1 = and(rawIn_isSpecial, _rawIn_out_isNaN_T) connect rawIn.isNaN, _rawIn_out_isNaN_T_1 node _rawIn_out_isInf_T = bits(rawIn_exp, 6, 6) node _rawIn_out_isInf_T_1 = eq(_rawIn_out_isInf_T, UInt<1>(0h0)) node _rawIn_out_isInf_T_2 = and(rawIn_isSpecial, _rawIn_out_isInf_T_1) connect rawIn.isInf, _rawIn_out_isInf_T_2 connect rawIn.isZero, rawIn_isZero node _rawIn_out_sign_T = bits(io.in, 32, 32) connect rawIn.sign, _rawIn_out_sign_T node _rawIn_out_sExp_T = cvt(rawIn_exp) connect rawIn.sExp, _rawIn_out_sExp_T node _rawIn_out_sig_T = eq(rawIn_isZero, UInt<1>(0h0)) node _rawIn_out_sig_T_1 = cat(UInt<1>(0h0), _rawIn_out_sig_T) node _rawIn_out_sig_T_2 = bits(io.in, 22, 0) node _rawIn_out_sig_T_3 = cat(_rawIn_out_sig_T_1, _rawIn_out_sig_T_2) connect rawIn.sig, _rawIn_out_sig_T_3 node _io_out_T = shl(io.in, 0) connect io.out, _io_out_T node _io_exceptionFlags_T = bits(rawIn.sig, 22, 22) node _io_exceptionFlags_T_1 = eq(_io_exceptionFlags_T, UInt<1>(0h0)) node _io_exceptionFlags_T_2 = and(rawIn.isNaN, _io_exceptionFlags_T_1) node _io_exceptionFlags_T_3 = cat(_io_exceptionFlags_T_2, UInt<4>(0h0)) connect io.exceptionFlags, _io_exceptionFlags_T_3
module RecFNToRecFN_38( // @[RecFNToRecFN.scala:44:5] input [32:0] io_in, // @[RecFNToRecFN.scala:48:16] output [32:0] io_out // @[RecFNToRecFN.scala:48:16] ); wire [32:0] io_in_0 = io_in; // @[RecFNToRecFN.scala:44:5] wire io_detectTininess = 1'h1; // @[RecFNToRecFN.scala:44:5, :48:16] wire [2:0] io_roundingMode = 3'h0; // @[RecFNToRecFN.scala:44:5, :48:16] wire [32:0] _io_out_T = io_in_0; // @[RecFNToRecFN.scala:44:5, :64:35] wire [4:0] _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:65:54] wire [32:0] io_out_0; // @[RecFNToRecFN.scala:44:5] wire [4:0] io_exceptionFlags; // @[RecFNToRecFN.scala:44:5] wire [8:0] rawIn_exp = io_in_0[31:23]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawIn_isZero_T = rawIn_exp[8:6]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawIn_isZero = _rawIn_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] wire rawIn_isZero_0 = rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawIn_isSpecial_T = rawIn_exp[8:7]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawIn_isSpecial = &_rawIn_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] wire _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [9:0] _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [24:0] _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawIn_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawIn_sign; // @[rawFloatFromRecFN.scala:55:23] wire [9:0] rawIn_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [24:0] rawIn_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawIn_out_isNaN_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawIn_out_isInf_T = rawIn_exp[6]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawIn_out_isNaN_T_1 = rawIn_isSpecial & _rawIn_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawIn_isNaN = _rawIn_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawIn_out_isInf_T_1 = ~_rawIn_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawIn_out_isInf_T_2 = rawIn_isSpecial & _rawIn_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawIn_isInf = _rawIn_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawIn_out_sign_T = io_in_0[32]; // @[rawFloatFromRecFN.scala:59:25] assign rawIn_sign = _rawIn_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawIn_out_sExp_T = {1'h0, rawIn_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawIn_sExp = _rawIn_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawIn_out_sig_T = ~rawIn_isZero; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawIn_out_sig_T_1 = {1'h0, _rawIn_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [22:0] _rawIn_out_sig_T_2 = io_in_0[22:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawIn_out_sig_T_3 = {_rawIn_out_sig_T_1, _rawIn_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawIn_sig = _rawIn_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] assign io_out_0 = _io_out_T; // @[RecFNToRecFN.scala:44:5, :64:35] wire _io_exceptionFlags_T = rawIn_sig[22]; // @[rawFloatFromRecFN.scala:55:23] wire _io_exceptionFlags_T_1 = ~_io_exceptionFlags_T; // @[common.scala:82:{49,56}] wire _io_exceptionFlags_T_2 = rawIn_isNaN & _io_exceptionFlags_T_1; // @[rawFloatFromRecFN.scala:55:23] assign _io_exceptionFlags_T_3 = {_io_exceptionFlags_T_2, 4'h0}; // @[common.scala:82:46] assign io_exceptionFlags = _io_exceptionFlags_T_3; // @[RecFNToRecFN.scala:44:5, :65:54] assign io_out = io_out_0; // @[RecFNToRecFN.scala:44:5] endmodule
Generate the Verilog code corresponding to this FIRRTL code module MulAddRecFNToRaw_preMul_e11_s53_6 : output io : { flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : { isSigNaNAny : UInt<1>, isNaNAOrB : UInt<1>, isInfA : UInt<1>, isZeroA : UInt<1>, isInfB : UInt<1>, isZeroB : UInt<1>, signProd : UInt<1>, isNaNC : UInt<1>, isInfC : UInt<1>, isZeroC : UInt<1>, sExpSum : SInt<13>, doSubMags : UInt<1>, CIsDominant : UInt<1>, CDom_CAlignDist : UInt<6>, highAlignedSigC : UInt<55>, bit0AlignedSigC : UInt<1>}} node rawA_exp = bits(io.a, 63, 52) node _rawA_isZero_T = bits(rawA_exp, 11, 9) node rawA_isZero = eq(_rawA_isZero_T, UInt<1>(0h0)) node _rawA_isSpecial_T = bits(rawA_exp, 11, 10) node rawA_isSpecial = eq(_rawA_isSpecial_T, UInt<2>(0h3)) wire rawA : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawA_out_isNaN_T = bits(rawA_exp, 9, 9) node _rawA_out_isNaN_T_1 = and(rawA_isSpecial, _rawA_out_isNaN_T) connect rawA.isNaN, _rawA_out_isNaN_T_1 node _rawA_out_isInf_T = bits(rawA_exp, 9, 9) node _rawA_out_isInf_T_1 = eq(_rawA_out_isInf_T, UInt<1>(0h0)) node _rawA_out_isInf_T_2 = and(rawA_isSpecial, _rawA_out_isInf_T_1) connect rawA.isInf, _rawA_out_isInf_T_2 connect rawA.isZero, rawA_isZero node _rawA_out_sign_T = bits(io.a, 64, 64) connect rawA.sign, _rawA_out_sign_T node _rawA_out_sExp_T = cvt(rawA_exp) connect rawA.sExp, _rawA_out_sExp_T node _rawA_out_sig_T = eq(rawA_isZero, UInt<1>(0h0)) node _rawA_out_sig_T_1 = cat(UInt<1>(0h0), _rawA_out_sig_T) node _rawA_out_sig_T_2 = bits(io.a, 51, 0) node _rawA_out_sig_T_3 = cat(_rawA_out_sig_T_1, _rawA_out_sig_T_2) connect rawA.sig, _rawA_out_sig_T_3 node rawB_exp = bits(io.b, 63, 52) node _rawB_isZero_T = bits(rawB_exp, 11, 9) node rawB_isZero = eq(_rawB_isZero_T, UInt<1>(0h0)) node _rawB_isSpecial_T = bits(rawB_exp, 11, 10) node rawB_isSpecial = eq(_rawB_isSpecial_T, UInt<2>(0h3)) wire rawB : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawB_out_isNaN_T = bits(rawB_exp, 9, 9) node _rawB_out_isNaN_T_1 = and(rawB_isSpecial, _rawB_out_isNaN_T) connect rawB.isNaN, _rawB_out_isNaN_T_1 node _rawB_out_isInf_T = bits(rawB_exp, 9, 9) node _rawB_out_isInf_T_1 = eq(_rawB_out_isInf_T, UInt<1>(0h0)) node _rawB_out_isInf_T_2 = and(rawB_isSpecial, _rawB_out_isInf_T_1) connect rawB.isInf, _rawB_out_isInf_T_2 connect rawB.isZero, rawB_isZero node _rawB_out_sign_T = bits(io.b, 64, 64) connect rawB.sign, _rawB_out_sign_T node _rawB_out_sExp_T = cvt(rawB_exp) connect rawB.sExp, _rawB_out_sExp_T node _rawB_out_sig_T = eq(rawB_isZero, UInt<1>(0h0)) node _rawB_out_sig_T_1 = cat(UInt<1>(0h0), _rawB_out_sig_T) node _rawB_out_sig_T_2 = bits(io.b, 51, 0) node _rawB_out_sig_T_3 = cat(_rawB_out_sig_T_1, _rawB_out_sig_T_2) connect rawB.sig, _rawB_out_sig_T_3 node rawC_exp = bits(io.c, 63, 52) node _rawC_isZero_T = bits(rawC_exp, 11, 9) node rawC_isZero = eq(_rawC_isZero_T, UInt<1>(0h0)) node _rawC_isSpecial_T = bits(rawC_exp, 11, 10) node rawC_isSpecial = eq(_rawC_isSpecial_T, UInt<2>(0h3)) wire rawC : { isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sign : UInt<1>, sExp : SInt<13>, sig : UInt<54>} node _rawC_out_isNaN_T = bits(rawC_exp, 9, 9) node _rawC_out_isNaN_T_1 = and(rawC_isSpecial, _rawC_out_isNaN_T) connect rawC.isNaN, _rawC_out_isNaN_T_1 node _rawC_out_isInf_T = bits(rawC_exp, 9, 9) node _rawC_out_isInf_T_1 = eq(_rawC_out_isInf_T, UInt<1>(0h0)) node _rawC_out_isInf_T_2 = and(rawC_isSpecial, _rawC_out_isInf_T_1) connect rawC.isInf, _rawC_out_isInf_T_2 connect rawC.isZero, rawC_isZero node _rawC_out_sign_T = bits(io.c, 64, 64) connect rawC.sign, _rawC_out_sign_T node _rawC_out_sExp_T = cvt(rawC_exp) connect rawC.sExp, _rawC_out_sExp_T node _rawC_out_sig_T = eq(rawC_isZero, UInt<1>(0h0)) node _rawC_out_sig_T_1 = cat(UInt<1>(0h0), _rawC_out_sig_T) node _rawC_out_sig_T_2 = bits(io.c, 51, 0) node _rawC_out_sig_T_3 = cat(_rawC_out_sig_T_1, _rawC_out_sig_T_2) connect rawC.sig, _rawC_out_sig_T_3 node _signProd_T = xor(rawA.sign, rawB.sign) node _signProd_T_1 = bits(io.op, 1, 1) node signProd = xor(_signProd_T, _signProd_T_1) node _sExpAlignedProd_T = add(rawA.sExp, rawB.sExp) node _sExpAlignedProd_T_1 = add(_sExpAlignedProd_T, asSInt(UInt<12>(0h838))) node _sExpAlignedProd_T_2 = tail(_sExpAlignedProd_T_1, 1) node sExpAlignedProd = asSInt(_sExpAlignedProd_T_2) node _doSubMags_T = xor(signProd, rawC.sign) node _doSubMags_T_1 = bits(io.op, 0, 0) node doSubMags = xor(_doSubMags_T, _doSubMags_T_1) node _sNatCAlignDist_T = sub(sExpAlignedProd, rawC.sExp) node _sNatCAlignDist_T_1 = tail(_sNatCAlignDist_T, 1) node sNatCAlignDist = asSInt(_sNatCAlignDist_T_1) node posNatCAlignDist = bits(sNatCAlignDist, 12, 0) node _isMinCAlign_T = or(rawA.isZero, rawB.isZero) node _isMinCAlign_T_1 = lt(sNatCAlignDist, asSInt(UInt<1>(0h0))) node isMinCAlign = or(_isMinCAlign_T, _isMinCAlign_T_1) node _CIsDominant_T = eq(rawC.isZero, UInt<1>(0h0)) node _CIsDominant_T_1 = leq(posNatCAlignDist, UInt<6>(0h35)) node _CIsDominant_T_2 = or(isMinCAlign, _CIsDominant_T_1) node CIsDominant = and(_CIsDominant_T, _CIsDominant_T_2) node _CAlignDist_T = lt(posNatCAlignDist, UInt<8>(0ha1)) node _CAlignDist_T_1 = bits(posNatCAlignDist, 7, 0) node _CAlignDist_T_2 = mux(_CAlignDist_T, _CAlignDist_T_1, UInt<8>(0ha1)) node CAlignDist = mux(isMinCAlign, UInt<1>(0h0), _CAlignDist_T_2) node _mainAlignedSigC_T = not(rawC.sig) node _mainAlignedSigC_T_1 = mux(doSubMags, _mainAlignedSigC_T, rawC.sig) node _mainAlignedSigC_T_2 = mux(doSubMags, UInt<111>(0h7fffffffffffffffffffffffffff), UInt<111>(0h0)) node _mainAlignedSigC_T_3 = cat(_mainAlignedSigC_T_1, _mainAlignedSigC_T_2) node _mainAlignedSigC_T_4 = asSInt(_mainAlignedSigC_T_3) node mainAlignedSigC = dshr(_mainAlignedSigC_T_4, CAlignDist) node _reduced4CExtra_T = shl(rawC.sig, 0) wire reduced4CExtra_reducedVec : UInt<1>[14] node _reduced4CExtra_reducedVec_0_T = bits(_reduced4CExtra_T, 3, 0) node _reduced4CExtra_reducedVec_0_T_1 = orr(_reduced4CExtra_reducedVec_0_T) connect reduced4CExtra_reducedVec[0], _reduced4CExtra_reducedVec_0_T_1 node _reduced4CExtra_reducedVec_1_T = bits(_reduced4CExtra_T, 7, 4) node _reduced4CExtra_reducedVec_1_T_1 = orr(_reduced4CExtra_reducedVec_1_T) connect reduced4CExtra_reducedVec[1], _reduced4CExtra_reducedVec_1_T_1 node _reduced4CExtra_reducedVec_2_T = bits(_reduced4CExtra_T, 11, 8) node _reduced4CExtra_reducedVec_2_T_1 = orr(_reduced4CExtra_reducedVec_2_T) connect reduced4CExtra_reducedVec[2], _reduced4CExtra_reducedVec_2_T_1 node _reduced4CExtra_reducedVec_3_T = bits(_reduced4CExtra_T, 15, 12) node _reduced4CExtra_reducedVec_3_T_1 = orr(_reduced4CExtra_reducedVec_3_T) connect reduced4CExtra_reducedVec[3], _reduced4CExtra_reducedVec_3_T_1 node _reduced4CExtra_reducedVec_4_T = bits(_reduced4CExtra_T, 19, 16) node _reduced4CExtra_reducedVec_4_T_1 = orr(_reduced4CExtra_reducedVec_4_T) connect reduced4CExtra_reducedVec[4], _reduced4CExtra_reducedVec_4_T_1 node _reduced4CExtra_reducedVec_5_T = bits(_reduced4CExtra_T, 23, 20) node _reduced4CExtra_reducedVec_5_T_1 = orr(_reduced4CExtra_reducedVec_5_T) connect reduced4CExtra_reducedVec[5], _reduced4CExtra_reducedVec_5_T_1 node _reduced4CExtra_reducedVec_6_T = bits(_reduced4CExtra_T, 27, 24) node _reduced4CExtra_reducedVec_6_T_1 = orr(_reduced4CExtra_reducedVec_6_T) connect reduced4CExtra_reducedVec[6], _reduced4CExtra_reducedVec_6_T_1 node _reduced4CExtra_reducedVec_7_T = bits(_reduced4CExtra_T, 31, 28) node _reduced4CExtra_reducedVec_7_T_1 = orr(_reduced4CExtra_reducedVec_7_T) connect reduced4CExtra_reducedVec[7], _reduced4CExtra_reducedVec_7_T_1 node _reduced4CExtra_reducedVec_8_T = bits(_reduced4CExtra_T, 35, 32) node _reduced4CExtra_reducedVec_8_T_1 = orr(_reduced4CExtra_reducedVec_8_T) connect reduced4CExtra_reducedVec[8], _reduced4CExtra_reducedVec_8_T_1 node _reduced4CExtra_reducedVec_9_T = bits(_reduced4CExtra_T, 39, 36) node _reduced4CExtra_reducedVec_9_T_1 = orr(_reduced4CExtra_reducedVec_9_T) connect reduced4CExtra_reducedVec[9], _reduced4CExtra_reducedVec_9_T_1 node _reduced4CExtra_reducedVec_10_T = bits(_reduced4CExtra_T, 43, 40) node _reduced4CExtra_reducedVec_10_T_1 = orr(_reduced4CExtra_reducedVec_10_T) connect reduced4CExtra_reducedVec[10], _reduced4CExtra_reducedVec_10_T_1 node _reduced4CExtra_reducedVec_11_T = bits(_reduced4CExtra_T, 47, 44) node _reduced4CExtra_reducedVec_11_T_1 = orr(_reduced4CExtra_reducedVec_11_T) connect reduced4CExtra_reducedVec[11], _reduced4CExtra_reducedVec_11_T_1 node _reduced4CExtra_reducedVec_12_T = bits(_reduced4CExtra_T, 51, 48) node _reduced4CExtra_reducedVec_12_T_1 = orr(_reduced4CExtra_reducedVec_12_T) connect reduced4CExtra_reducedVec[12], _reduced4CExtra_reducedVec_12_T_1 node _reduced4CExtra_reducedVec_13_T = bits(_reduced4CExtra_T, 53, 52) node _reduced4CExtra_reducedVec_13_T_1 = orr(_reduced4CExtra_reducedVec_13_T) connect reduced4CExtra_reducedVec[13], _reduced4CExtra_reducedVec_13_T_1 node reduced4CExtra_lo_lo_hi = cat(reduced4CExtra_reducedVec[2], reduced4CExtra_reducedVec[1]) node reduced4CExtra_lo_lo = cat(reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec[0]) node reduced4CExtra_lo_hi_lo = cat(reduced4CExtra_reducedVec[4], reduced4CExtra_reducedVec[3]) node reduced4CExtra_lo_hi_hi = cat(reduced4CExtra_reducedVec[6], reduced4CExtra_reducedVec[5]) node reduced4CExtra_lo_hi = cat(reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo) node reduced4CExtra_lo = cat(reduced4CExtra_lo_hi, reduced4CExtra_lo_lo) node reduced4CExtra_hi_lo_hi = cat(reduced4CExtra_reducedVec[9], reduced4CExtra_reducedVec[8]) node reduced4CExtra_hi_lo = cat(reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec[7]) node reduced4CExtra_hi_hi_lo = cat(reduced4CExtra_reducedVec[11], reduced4CExtra_reducedVec[10]) node reduced4CExtra_hi_hi_hi = cat(reduced4CExtra_reducedVec[13], reduced4CExtra_reducedVec[12]) node reduced4CExtra_hi_hi = cat(reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo) node reduced4CExtra_hi = cat(reduced4CExtra_hi_hi, reduced4CExtra_hi_lo) node _reduced4CExtra_T_1 = cat(reduced4CExtra_hi, reduced4CExtra_lo) node _reduced4CExtra_T_2 = shr(CAlignDist, 2) node reduced4CExtra_shift = dshr(asSInt(UInt<65>(0h10000000000000000)), _reduced4CExtra_T_2) node _reduced4CExtra_T_3 = bits(reduced4CExtra_shift, 36, 24) node _reduced4CExtra_T_4 = bits(_reduced4CExtra_T_3, 7, 0) node _reduced4CExtra_T_5 = shl(UInt<4>(0hf), 4) node _reduced4CExtra_T_6 = xor(UInt<8>(0hff), _reduced4CExtra_T_5) node _reduced4CExtra_T_7 = shr(_reduced4CExtra_T_4, 4) node _reduced4CExtra_T_8 = and(_reduced4CExtra_T_7, _reduced4CExtra_T_6) node _reduced4CExtra_T_9 = bits(_reduced4CExtra_T_4, 3, 0) node _reduced4CExtra_T_10 = shl(_reduced4CExtra_T_9, 4) node _reduced4CExtra_T_11 = not(_reduced4CExtra_T_6) node _reduced4CExtra_T_12 = and(_reduced4CExtra_T_10, _reduced4CExtra_T_11) node _reduced4CExtra_T_13 = or(_reduced4CExtra_T_8, _reduced4CExtra_T_12) node _reduced4CExtra_T_14 = bits(_reduced4CExtra_T_6, 5, 0) node _reduced4CExtra_T_15 = shl(_reduced4CExtra_T_14, 2) node _reduced4CExtra_T_16 = xor(_reduced4CExtra_T_6, _reduced4CExtra_T_15) node _reduced4CExtra_T_17 = shr(_reduced4CExtra_T_13, 2) node _reduced4CExtra_T_18 = and(_reduced4CExtra_T_17, _reduced4CExtra_T_16) node _reduced4CExtra_T_19 = bits(_reduced4CExtra_T_13, 5, 0) node _reduced4CExtra_T_20 = shl(_reduced4CExtra_T_19, 2) node _reduced4CExtra_T_21 = not(_reduced4CExtra_T_16) node _reduced4CExtra_T_22 = and(_reduced4CExtra_T_20, _reduced4CExtra_T_21) node _reduced4CExtra_T_23 = or(_reduced4CExtra_T_18, _reduced4CExtra_T_22) node _reduced4CExtra_T_24 = bits(_reduced4CExtra_T_16, 6, 0) node _reduced4CExtra_T_25 = shl(_reduced4CExtra_T_24, 1) node _reduced4CExtra_T_26 = xor(_reduced4CExtra_T_16, _reduced4CExtra_T_25) node _reduced4CExtra_T_27 = shr(_reduced4CExtra_T_23, 1) node _reduced4CExtra_T_28 = and(_reduced4CExtra_T_27, _reduced4CExtra_T_26) node _reduced4CExtra_T_29 = bits(_reduced4CExtra_T_23, 6, 0) node _reduced4CExtra_T_30 = shl(_reduced4CExtra_T_29, 1) node _reduced4CExtra_T_31 = not(_reduced4CExtra_T_26) node _reduced4CExtra_T_32 = and(_reduced4CExtra_T_30, _reduced4CExtra_T_31) node _reduced4CExtra_T_33 = or(_reduced4CExtra_T_28, _reduced4CExtra_T_32) node _reduced4CExtra_T_34 = bits(_reduced4CExtra_T_3, 12, 8) node _reduced4CExtra_T_35 = bits(_reduced4CExtra_T_34, 3, 0) node _reduced4CExtra_T_36 = bits(_reduced4CExtra_T_35, 1, 0) node _reduced4CExtra_T_37 = bits(_reduced4CExtra_T_36, 0, 0) node _reduced4CExtra_T_38 = bits(_reduced4CExtra_T_36, 1, 1) node _reduced4CExtra_T_39 = cat(_reduced4CExtra_T_37, _reduced4CExtra_T_38) node _reduced4CExtra_T_40 = bits(_reduced4CExtra_T_35, 3, 2) node _reduced4CExtra_T_41 = bits(_reduced4CExtra_T_40, 0, 0) node _reduced4CExtra_T_42 = bits(_reduced4CExtra_T_40, 1, 1) node _reduced4CExtra_T_43 = cat(_reduced4CExtra_T_41, _reduced4CExtra_T_42) node _reduced4CExtra_T_44 = cat(_reduced4CExtra_T_39, _reduced4CExtra_T_43) node _reduced4CExtra_T_45 = bits(_reduced4CExtra_T_34, 4, 4) node _reduced4CExtra_T_46 = cat(_reduced4CExtra_T_44, _reduced4CExtra_T_45) node _reduced4CExtra_T_47 = cat(_reduced4CExtra_T_33, _reduced4CExtra_T_46) node _reduced4CExtra_T_48 = and(_reduced4CExtra_T_1, _reduced4CExtra_T_47) node reduced4CExtra = orr(_reduced4CExtra_T_48) node _alignedSigC_T = shr(mainAlignedSigC, 3) node _alignedSigC_T_1 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_2 = andr(_alignedSigC_T_1) node _alignedSigC_T_3 = eq(reduced4CExtra, UInt<1>(0h0)) node _alignedSigC_T_4 = and(_alignedSigC_T_2, _alignedSigC_T_3) node _alignedSigC_T_5 = bits(mainAlignedSigC, 2, 0) node _alignedSigC_T_6 = orr(_alignedSigC_T_5) node _alignedSigC_T_7 = or(_alignedSigC_T_6, reduced4CExtra) node _alignedSigC_T_8 = mux(doSubMags, _alignedSigC_T_4, _alignedSigC_T_7) node alignedSigC_hi = asUInt(_alignedSigC_T) node alignedSigC = cat(alignedSigC_hi, _alignedSigC_T_8) connect io.mulAddA, rawA.sig connect io.mulAddB, rawB.sig node _io_mulAddC_T = bits(alignedSigC, 106, 1) connect io.mulAddC, _io_mulAddC_T node _io_toPostMul_isSigNaNAny_T = bits(rawA.sig, 51, 51) node _io_toPostMul_isSigNaNAny_T_1 = eq(_io_toPostMul_isSigNaNAny_T, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_2 = and(rawA.isNaN, _io_toPostMul_isSigNaNAny_T_1) node _io_toPostMul_isSigNaNAny_T_3 = bits(rawB.sig, 51, 51) node _io_toPostMul_isSigNaNAny_T_4 = eq(_io_toPostMul_isSigNaNAny_T_3, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_5 = and(rawB.isNaN, _io_toPostMul_isSigNaNAny_T_4) node _io_toPostMul_isSigNaNAny_T_6 = or(_io_toPostMul_isSigNaNAny_T_2, _io_toPostMul_isSigNaNAny_T_5) node _io_toPostMul_isSigNaNAny_T_7 = bits(rawC.sig, 51, 51) node _io_toPostMul_isSigNaNAny_T_8 = eq(_io_toPostMul_isSigNaNAny_T_7, UInt<1>(0h0)) node _io_toPostMul_isSigNaNAny_T_9 = and(rawC.isNaN, _io_toPostMul_isSigNaNAny_T_8) node _io_toPostMul_isSigNaNAny_T_10 = or(_io_toPostMul_isSigNaNAny_T_6, _io_toPostMul_isSigNaNAny_T_9) connect io.toPostMul.isSigNaNAny, _io_toPostMul_isSigNaNAny_T_10 node _io_toPostMul_isNaNAOrB_T = or(rawA.isNaN, rawB.isNaN) connect io.toPostMul.isNaNAOrB, _io_toPostMul_isNaNAOrB_T connect io.toPostMul.isInfA, rawA.isInf connect io.toPostMul.isZeroA, rawA.isZero connect io.toPostMul.isInfB, rawB.isInf connect io.toPostMul.isZeroB, rawB.isZero connect io.toPostMul.signProd, signProd connect io.toPostMul.isNaNC, rawC.isNaN connect io.toPostMul.isInfC, rawC.isInf connect io.toPostMul.isZeroC, rawC.isZero node _io_toPostMul_sExpSum_T = sub(sExpAlignedProd, asSInt(UInt<7>(0h35))) node _io_toPostMul_sExpSum_T_1 = tail(_io_toPostMul_sExpSum_T, 1) node _io_toPostMul_sExpSum_T_2 = asSInt(_io_toPostMul_sExpSum_T_1) node _io_toPostMul_sExpSum_T_3 = mux(CIsDominant, rawC.sExp, _io_toPostMul_sExpSum_T_2) connect io.toPostMul.sExpSum, _io_toPostMul_sExpSum_T_3 connect io.toPostMul.doSubMags, doSubMags connect io.toPostMul.CIsDominant, CIsDominant node _io_toPostMul_CDom_CAlignDist_T = bits(CAlignDist, 5, 0) connect io.toPostMul.CDom_CAlignDist, _io_toPostMul_CDom_CAlignDist_T node _io_toPostMul_highAlignedSigC_T = bits(alignedSigC, 161, 107) connect io.toPostMul.highAlignedSigC, _io_toPostMul_highAlignedSigC_T node _io_toPostMul_bit0AlignedSigC_T = bits(alignedSigC, 0, 0) connect io.toPostMul.bit0AlignedSigC, _io_toPostMul_bit0AlignedSigC_T
module MulAddRecFNToRaw_preMul_e11_s53_6( // @[MulAddRecFN.scala:71:7] input [1:0] io_op, // @[MulAddRecFN.scala:74:16] input [64:0] io_a, // @[MulAddRecFN.scala:74:16] input [64:0] io_b, // @[MulAddRecFN.scala:74:16] input [64:0] io_c, // @[MulAddRecFN.scala:74:16] output [52:0] io_mulAddA, // @[MulAddRecFN.scala:74:16] output [52:0] io_mulAddB, // @[MulAddRecFN.scala:74:16] output [105:0] io_mulAddC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isSigNaNAny, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNAOrB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroA, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroB, // @[MulAddRecFN.scala:74:16] output io_toPostMul_signProd, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isNaNC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isInfC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_isZeroC, // @[MulAddRecFN.scala:74:16] output [12:0] io_toPostMul_sExpSum, // @[MulAddRecFN.scala:74:16] output io_toPostMul_doSubMags, // @[MulAddRecFN.scala:74:16] output io_toPostMul_CIsDominant, // @[MulAddRecFN.scala:74:16] output [5:0] io_toPostMul_CDom_CAlignDist, // @[MulAddRecFN.scala:74:16] output [54:0] io_toPostMul_highAlignedSigC, // @[MulAddRecFN.scala:74:16] output io_toPostMul_bit0AlignedSigC // @[MulAddRecFN.scala:74:16] ); wire [1:0] io_op_0 = io_op; // @[MulAddRecFN.scala:71:7] wire [64:0] io_a_0 = io_a; // @[MulAddRecFN.scala:71:7] wire [64:0] io_b_0 = io_b; // @[MulAddRecFN.scala:71:7] wire [64:0] io_c_0 = io_c; // @[MulAddRecFN.scala:71:7] wire [7:0] _reduced4CExtra_T_6 = 8'hF; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_5 = 8'hF0; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_11 = 8'hF0; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_14 = 6'hF; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_15 = 8'h3C; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_16 = 8'h33; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_21 = 8'hCC; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_24 = 7'h33; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_25 = 8'h66; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_26 = 8'h55; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_31 = 8'hAA; // @[primitives.scala:77:20] wire [105:0] _io_mulAddC_T; // @[MulAddRecFN.scala:143:30] wire _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:146:58] wire _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:148:42] wire rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire signProd; // @[MulAddRecFN.scala:97:42] wire rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] wire rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire doSubMags; // @[MulAddRecFN.scala:102:42] wire CIsDominant; // @[MulAddRecFN.scala:110:23] wire [5:0] _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:161:47] wire [54:0] _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:163:20] wire _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:164:48] wire io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] wire [12:0] io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] wire [5:0] io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] wire [54:0] io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] wire [52:0] io_mulAddA_0; // @[MulAddRecFN.scala:71:7] wire [52:0] io_mulAddB_0; // @[MulAddRecFN.scala:71:7] wire [105:0] io_mulAddC_0; // @[MulAddRecFN.scala:71:7] wire [11:0] rawA_exp = io_a_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawA_isZero_T = rawA_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawA_isZero_0 = _rawA_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawA_isZero = rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawA_isSpecial_T = rawA_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawA_isSpecial = &_rawA_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfA_0 = rawA_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroA_0 = rawA_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawA_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawA_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawA_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawA_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawA_out_isNaN_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawA_out_isInf_T = rawA_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawA_out_isNaN_T_1 = rawA_isSpecial & _rawA_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawA_isNaN = _rawA_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawA_out_isInf_T_1 = ~_rawA_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawA_out_isInf_T_2 = rawA_isSpecial & _rawA_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawA_isInf = _rawA_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawA_out_sign_T = io_a_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawA_sign = _rawA_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawA_out_sExp_T = {1'h0, rawA_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawA_sExp = _rawA_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawA_out_sig_T = ~rawA_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawA_out_sig_T_1 = {1'h0, _rawA_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawA_out_sig_T_2 = io_a_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawA_out_sig_T_3 = {_rawA_out_sig_T_1, _rawA_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawA_sig = _rawA_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [11:0] rawB_exp = io_b_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawB_isZero_T = rawB_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawB_isZero_0 = _rawB_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawB_isZero = rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawB_isSpecial_T = rawB_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawB_isSpecial = &_rawB_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] wire _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfB_0 = rawB_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroB_0 = rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawB_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawB_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawB_out_isNaN_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawB_out_isInf_T = rawB_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawB_out_isNaN_T_1 = rawB_isSpecial & _rawB_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawB_isNaN = _rawB_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawB_out_isInf_T_1 = ~_rawB_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawB_out_isInf_T_2 = rawB_isSpecial & _rawB_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawB_isInf = _rawB_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawB_out_sign_T = io_b_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawB_sign = _rawB_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawB_out_sExp_T = {1'h0, rawB_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawB_sExp = _rawB_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawB_out_sig_T = ~rawB_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawB_out_sig_T_1 = {1'h0, _rawB_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawB_out_sig_T_2 = io_b_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawB_out_sig_T_3 = {_rawB_out_sig_T_1, _rawB_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawB_sig = _rawB_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire [11:0] rawC_exp = io_c_0[63:52]; // @[rawFloatFromRecFN.scala:51:21] wire [2:0] _rawC_isZero_T = rawC_exp[11:9]; // @[rawFloatFromRecFN.scala:51:21, :52:28] wire rawC_isZero_0 = _rawC_isZero_T == 3'h0; // @[rawFloatFromRecFN.scala:52:{28,53}] assign rawC_isZero = rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :55:23] wire [1:0] _rawC_isSpecial_T = rawC_exp[11:10]; // @[rawFloatFromRecFN.scala:51:21, :53:28] wire rawC_isSpecial = &_rawC_isSpecial_T; // @[rawFloatFromRecFN.scala:53:{28,53}] wire _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:56:33] assign io_toPostMul_isNaNC_0 = rawC_isNaN; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:57:33] assign io_toPostMul_isInfC_0 = rawC_isInf; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isZeroC_0 = rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:59:25] wire [12:0] _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:60:27] wire [53:0] _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:61:44] wire rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire [12:0] rawC_sExp; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] _reduced4CExtra_T = rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire _rawC_out_isNaN_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41] wire _rawC_out_isInf_T = rawC_exp[9]; // @[rawFloatFromRecFN.scala:51:21, :56:41, :57:41] assign _rawC_out_isNaN_T_1 = rawC_isSpecial & _rawC_out_isNaN_T; // @[rawFloatFromRecFN.scala:53:53, :56:{33,41}] assign rawC_isNaN = _rawC_out_isNaN_T_1; // @[rawFloatFromRecFN.scala:55:23, :56:33] wire _rawC_out_isInf_T_1 = ~_rawC_out_isInf_T; // @[rawFloatFromRecFN.scala:57:{36,41}] assign _rawC_out_isInf_T_2 = rawC_isSpecial & _rawC_out_isInf_T_1; // @[rawFloatFromRecFN.scala:53:53, :57:{33,36}] assign rawC_isInf = _rawC_out_isInf_T_2; // @[rawFloatFromRecFN.scala:55:23, :57:33] assign _rawC_out_sign_T = io_c_0[64]; // @[rawFloatFromRecFN.scala:59:25] assign rawC_sign = _rawC_out_sign_T; // @[rawFloatFromRecFN.scala:55:23, :59:25] assign _rawC_out_sExp_T = {1'h0, rawC_exp}; // @[rawFloatFromRecFN.scala:51:21, :60:27] assign rawC_sExp = _rawC_out_sExp_T; // @[rawFloatFromRecFN.scala:55:23, :60:27] wire _rawC_out_sig_T = ~rawC_isZero_0; // @[rawFloatFromRecFN.scala:52:53, :61:35] wire [1:0] _rawC_out_sig_T_1 = {1'h0, _rawC_out_sig_T}; // @[rawFloatFromRecFN.scala:61:{32,35}] wire [51:0] _rawC_out_sig_T_2 = io_c_0[51:0]; // @[rawFloatFromRecFN.scala:61:49] assign _rawC_out_sig_T_3 = {_rawC_out_sig_T_1, _rawC_out_sig_T_2}; // @[rawFloatFromRecFN.scala:61:{32,44,49}] assign rawC_sig = _rawC_out_sig_T_3; // @[rawFloatFromRecFN.scala:55:23, :61:44] wire _signProd_T = rawA_sign ^ rawB_sign; // @[rawFloatFromRecFN.scala:55:23] wire _signProd_T_1 = io_op_0[1]; // @[MulAddRecFN.scala:71:7, :97:49] assign signProd = _signProd_T ^ _signProd_T_1; // @[MulAddRecFN.scala:97:{30,42,49}] assign io_toPostMul_signProd_0 = signProd; // @[MulAddRecFN.scala:71:7, :97:42] wire [13:0] _sExpAlignedProd_T = {rawA_sExp[12], rawA_sExp} + {rawB_sExp[12], rawB_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [14:0] _sExpAlignedProd_T_1 = {_sExpAlignedProd_T[13], _sExpAlignedProd_T} - 15'h7C8; // @[MulAddRecFN.scala:100:{19,32}] wire [13:0] _sExpAlignedProd_T_2 = _sExpAlignedProd_T_1[13:0]; // @[MulAddRecFN.scala:100:32] wire [13:0] sExpAlignedProd = _sExpAlignedProd_T_2; // @[MulAddRecFN.scala:100:32] wire _doSubMags_T = signProd ^ rawC_sign; // @[rawFloatFromRecFN.scala:55:23] wire _doSubMags_T_1 = io_op_0[0]; // @[MulAddRecFN.scala:71:7, :102:49] assign doSubMags = _doSubMags_T ^ _doSubMags_T_1; // @[MulAddRecFN.scala:102:{30,42,49}] assign io_toPostMul_doSubMags_0 = doSubMags; // @[MulAddRecFN.scala:71:7, :102:42] wire [14:0] _GEN = {sExpAlignedProd[13], sExpAlignedProd}; // @[MulAddRecFN.scala:100:32, :106:42] wire [14:0] _sNatCAlignDist_T = _GEN - {{2{rawC_sExp[12]}}, rawC_sExp}; // @[rawFloatFromRecFN.scala:55:23] wire [13:0] _sNatCAlignDist_T_1 = _sNatCAlignDist_T[13:0]; // @[MulAddRecFN.scala:106:42] wire [13:0] sNatCAlignDist = _sNatCAlignDist_T_1; // @[MulAddRecFN.scala:106:42] wire [12:0] posNatCAlignDist = sNatCAlignDist[12:0]; // @[MulAddRecFN.scala:106:42, :107:42] wire _isMinCAlign_T = rawA_isZero | rawB_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _isMinCAlign_T_1 = $signed(sNatCAlignDist) < 14'sh0; // @[MulAddRecFN.scala:106:42, :108:69, :130:11] wire isMinCAlign = _isMinCAlign_T | _isMinCAlign_T_1; // @[MulAddRecFN.scala:108:{35,50,69}] wire _CIsDominant_T = ~rawC_isZero; // @[rawFloatFromRecFN.scala:55:23] wire _CIsDominant_T_1 = posNatCAlignDist < 13'h36; // @[MulAddRecFN.scala:107:42, :110:60] wire _CIsDominant_T_2 = isMinCAlign | _CIsDominant_T_1; // @[MulAddRecFN.scala:108:50, :110:{39,60}] assign CIsDominant = _CIsDominant_T & _CIsDominant_T_2; // @[MulAddRecFN.scala:110:{9,23,39}] assign io_toPostMul_CIsDominant_0 = CIsDominant; // @[MulAddRecFN.scala:71:7, :110:23] wire _CAlignDist_T = posNatCAlignDist < 13'hA1; // @[MulAddRecFN.scala:107:42, :114:34] wire [7:0] _CAlignDist_T_1 = posNatCAlignDist[7:0]; // @[MulAddRecFN.scala:107:42, :115:33] wire [7:0] _CAlignDist_T_2 = _CAlignDist_T ? _CAlignDist_T_1 : 8'hA1; // @[MulAddRecFN.scala:114:{16,34}, :115:33] wire [7:0] CAlignDist = isMinCAlign ? 8'h0 : _CAlignDist_T_2; // @[MulAddRecFN.scala:108:50, :112:12, :114:16] wire [53:0] _mainAlignedSigC_T = ~rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [53:0] _mainAlignedSigC_T_1 = doSubMags ? _mainAlignedSigC_T : rawC_sig; // @[rawFloatFromRecFN.scala:55:23] wire [110:0] _mainAlignedSigC_T_2 = {111{doSubMags}}; // @[MulAddRecFN.scala:102:42, :120:53] wire [164:0] _mainAlignedSigC_T_3 = {_mainAlignedSigC_T_1, _mainAlignedSigC_T_2}; // @[MulAddRecFN.scala:120:{13,46,53}] wire [164:0] _mainAlignedSigC_T_4 = _mainAlignedSigC_T_3; // @[MulAddRecFN.scala:120:{46,94}] wire [164:0] mainAlignedSigC = $signed($signed(_mainAlignedSigC_T_4) >>> CAlignDist); // @[MulAddRecFN.scala:112:12, :120:{94,100}] wire _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:120:54] wire _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:123:57] wire reduced4CExtra_reducedVec_0; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_1; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_2; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_3; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_4; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_5; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_6; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_7; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_8; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_9; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_10; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_11; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_12; // @[primitives.scala:118:30] wire reduced4CExtra_reducedVec_13; // @[primitives.scala:118:30] wire [3:0] _reduced4CExtra_reducedVec_0_T = _reduced4CExtra_T[3:0]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_0_T_1 = |_reduced4CExtra_reducedVec_0_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_0 = _reduced4CExtra_reducedVec_0_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_1_T = _reduced4CExtra_T[7:4]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_1_T_1 = |_reduced4CExtra_reducedVec_1_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_1 = _reduced4CExtra_reducedVec_1_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_2_T = _reduced4CExtra_T[11:8]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_2_T_1 = |_reduced4CExtra_reducedVec_2_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_2 = _reduced4CExtra_reducedVec_2_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_3_T = _reduced4CExtra_T[15:12]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_3_T_1 = |_reduced4CExtra_reducedVec_3_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_3 = _reduced4CExtra_reducedVec_3_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_4_T = _reduced4CExtra_T[19:16]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_4_T_1 = |_reduced4CExtra_reducedVec_4_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_4 = _reduced4CExtra_reducedVec_4_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_5_T = _reduced4CExtra_T[23:20]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_5_T_1 = |_reduced4CExtra_reducedVec_5_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_5 = _reduced4CExtra_reducedVec_5_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_6_T = _reduced4CExtra_T[27:24]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_6_T_1 = |_reduced4CExtra_reducedVec_6_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_6 = _reduced4CExtra_reducedVec_6_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_7_T = _reduced4CExtra_T[31:28]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_7_T_1 = |_reduced4CExtra_reducedVec_7_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_7 = _reduced4CExtra_reducedVec_7_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_8_T = _reduced4CExtra_T[35:32]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_8_T_1 = |_reduced4CExtra_reducedVec_8_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_8 = _reduced4CExtra_reducedVec_8_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_9_T = _reduced4CExtra_T[39:36]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_9_T_1 = |_reduced4CExtra_reducedVec_9_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_9 = _reduced4CExtra_reducedVec_9_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_10_T = _reduced4CExtra_T[43:40]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_10_T_1 = |_reduced4CExtra_reducedVec_10_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_10 = _reduced4CExtra_reducedVec_10_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_11_T = _reduced4CExtra_T[47:44]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_11_T_1 = |_reduced4CExtra_reducedVec_11_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_11 = _reduced4CExtra_reducedVec_11_T_1; // @[primitives.scala:118:30, :120:54] wire [3:0] _reduced4CExtra_reducedVec_12_T = _reduced4CExtra_T[51:48]; // @[primitives.scala:120:33] assign _reduced4CExtra_reducedVec_12_T_1 = |_reduced4CExtra_reducedVec_12_T; // @[primitives.scala:120:{33,54}] assign reduced4CExtra_reducedVec_12 = _reduced4CExtra_reducedVec_12_T_1; // @[primitives.scala:118:30, :120:54] wire [1:0] _reduced4CExtra_reducedVec_13_T = _reduced4CExtra_T[53:52]; // @[primitives.scala:123:15] assign _reduced4CExtra_reducedVec_13_T_1 = |_reduced4CExtra_reducedVec_13_T; // @[primitives.scala:123:{15,57}] assign reduced4CExtra_reducedVec_13 = _reduced4CExtra_reducedVec_13_T_1; // @[primitives.scala:118:30, :123:57] wire [1:0] reduced4CExtra_lo_lo_hi = {reduced4CExtra_reducedVec_2, reduced4CExtra_reducedVec_1}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_lo_lo = {reduced4CExtra_lo_lo_hi, reduced4CExtra_reducedVec_0}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_lo_hi_lo = {reduced4CExtra_reducedVec_4, reduced4CExtra_reducedVec_3}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_lo_hi_hi = {reduced4CExtra_reducedVec_6, reduced4CExtra_reducedVec_5}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_lo_hi = {reduced4CExtra_lo_hi_hi, reduced4CExtra_lo_hi_lo}; // @[primitives.scala:124:20] wire [6:0] reduced4CExtra_lo = {reduced4CExtra_lo_hi, reduced4CExtra_lo_lo}; // @[primitives.scala:124:20] wire [1:0] reduced4CExtra_hi_lo_hi = {reduced4CExtra_reducedVec_9, reduced4CExtra_reducedVec_8}; // @[primitives.scala:118:30, :124:20] wire [2:0] reduced4CExtra_hi_lo = {reduced4CExtra_hi_lo_hi, reduced4CExtra_reducedVec_7}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi_lo = {reduced4CExtra_reducedVec_11, reduced4CExtra_reducedVec_10}; // @[primitives.scala:118:30, :124:20] wire [1:0] reduced4CExtra_hi_hi_hi = {reduced4CExtra_reducedVec_13, reduced4CExtra_reducedVec_12}; // @[primitives.scala:118:30, :124:20] wire [3:0] reduced4CExtra_hi_hi = {reduced4CExtra_hi_hi_hi, reduced4CExtra_hi_hi_lo}; // @[primitives.scala:124:20] wire [6:0] reduced4CExtra_hi = {reduced4CExtra_hi_hi, reduced4CExtra_hi_lo}; // @[primitives.scala:124:20] wire [13:0] _reduced4CExtra_T_1 = {reduced4CExtra_hi, reduced4CExtra_lo}; // @[primitives.scala:124:20] wire [5:0] _reduced4CExtra_T_2 = CAlignDist[7:2]; // @[MulAddRecFN.scala:112:12, :124:28] wire [64:0] reduced4CExtra_shift = $signed(65'sh10000000000000000 >>> _reduced4CExtra_T_2); // @[primitives.scala:76:56] wire [12:0] _reduced4CExtra_T_3 = reduced4CExtra_shift[36:24]; // @[primitives.scala:76:56, :78:22] wire [7:0] _reduced4CExtra_T_4 = _reduced4CExtra_T_3[7:0]; // @[primitives.scala:77:20, :78:22] wire [3:0] _reduced4CExtra_T_7 = _reduced4CExtra_T_4[7:4]; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_8 = {4'h0, _reduced4CExtra_T_7}; // @[primitives.scala:77:20, :120:54] wire [3:0] _reduced4CExtra_T_9 = _reduced4CExtra_T_4[3:0]; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_10 = {_reduced4CExtra_T_9, 4'h0}; // @[primitives.scala:77:20, :120:54] wire [7:0] _reduced4CExtra_T_12 = _reduced4CExtra_T_10 & 8'hF0; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_13 = _reduced4CExtra_T_8 | _reduced4CExtra_T_12; // @[primitives.scala:77:20] wire [5:0] _reduced4CExtra_T_17 = _reduced4CExtra_T_13[7:2]; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_18 = {2'h0, _reduced4CExtra_T_17 & 6'h33}; // @[primitives.scala:77:20, :123:57] wire [5:0] _reduced4CExtra_T_19 = _reduced4CExtra_T_13[5:0]; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_20 = {_reduced4CExtra_T_19, 2'h0}; // @[primitives.scala:77:20, :123:57] wire [7:0] _reduced4CExtra_T_22 = _reduced4CExtra_T_20 & 8'hCC; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_23 = _reduced4CExtra_T_18 | _reduced4CExtra_T_22; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_27 = _reduced4CExtra_T_23[7:1]; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_28 = {1'h0, _reduced4CExtra_T_27 & 7'h55}; // @[primitives.scala:77:20] wire [6:0] _reduced4CExtra_T_29 = _reduced4CExtra_T_23[6:0]; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_30 = {_reduced4CExtra_T_29, 1'h0}; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_32 = _reduced4CExtra_T_30 & 8'hAA; // @[primitives.scala:77:20] wire [7:0] _reduced4CExtra_T_33 = _reduced4CExtra_T_28 | _reduced4CExtra_T_32; // @[primitives.scala:77:20] wire [4:0] _reduced4CExtra_T_34 = _reduced4CExtra_T_3[12:8]; // @[primitives.scala:77:20, :78:22] wire [3:0] _reduced4CExtra_T_35 = _reduced4CExtra_T_34[3:0]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_36 = _reduced4CExtra_T_35[1:0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_37 = _reduced4CExtra_T_36[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_38 = _reduced4CExtra_T_36[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_39 = {_reduced4CExtra_T_37, _reduced4CExtra_T_38}; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_40 = _reduced4CExtra_T_35[3:2]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_41 = _reduced4CExtra_T_40[0]; // @[primitives.scala:77:20] wire _reduced4CExtra_T_42 = _reduced4CExtra_T_40[1]; // @[primitives.scala:77:20] wire [1:0] _reduced4CExtra_T_43 = {_reduced4CExtra_T_41, _reduced4CExtra_T_42}; // @[primitives.scala:77:20] wire [3:0] _reduced4CExtra_T_44 = {_reduced4CExtra_T_39, _reduced4CExtra_T_43}; // @[primitives.scala:77:20] wire _reduced4CExtra_T_45 = _reduced4CExtra_T_34[4]; // @[primitives.scala:77:20] wire [4:0] _reduced4CExtra_T_46 = {_reduced4CExtra_T_44, _reduced4CExtra_T_45}; // @[primitives.scala:77:20] wire [12:0] _reduced4CExtra_T_47 = {_reduced4CExtra_T_33, _reduced4CExtra_T_46}; // @[primitives.scala:77:20] wire [13:0] _reduced4CExtra_T_48 = {1'h0, _reduced4CExtra_T_1[12:0] & _reduced4CExtra_T_47}; // @[primitives.scala:77:20, :124:20] wire reduced4CExtra = |_reduced4CExtra_T_48; // @[MulAddRecFN.scala:122:68, :130:11] wire [161:0] _alignedSigC_T = mainAlignedSigC[164:3]; // @[MulAddRecFN.scala:120:100, :132:28] wire [161:0] alignedSigC_hi = _alignedSigC_T; // @[MulAddRecFN.scala:132:{12,28}] wire [2:0] _alignedSigC_T_1 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32] wire [2:0] _alignedSigC_T_5 = mainAlignedSigC[2:0]; // @[MulAddRecFN.scala:120:100, :134:32, :135:32] wire _alignedSigC_T_2 = &_alignedSigC_T_1; // @[MulAddRecFN.scala:134:{32,39}] wire _alignedSigC_T_3 = ~reduced4CExtra; // @[MulAddRecFN.scala:130:11, :134:47] wire _alignedSigC_T_4 = _alignedSigC_T_2 & _alignedSigC_T_3; // @[MulAddRecFN.scala:134:{39,44,47}] wire _alignedSigC_T_6 = |_alignedSigC_T_5; // @[MulAddRecFN.scala:135:{32,39}] wire _alignedSigC_T_7 = _alignedSigC_T_6 | reduced4CExtra; // @[MulAddRecFN.scala:130:11, :135:{39,44}] wire _alignedSigC_T_8 = doSubMags ? _alignedSigC_T_4 : _alignedSigC_T_7; // @[MulAddRecFN.scala:102:42, :133:16, :134:44, :135:44] wire [162:0] alignedSigC = {alignedSigC_hi, _alignedSigC_T_8}; // @[MulAddRecFN.scala:132:12, :133:16] assign io_mulAddA_0 = rawA_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23] assign io_mulAddB_0 = rawB_sig[52:0]; // @[rawFloatFromRecFN.scala:55:23] assign _io_mulAddC_T = alignedSigC[106:1]; // @[MulAddRecFN.scala:132:12, :143:30] assign io_mulAddC_0 = _io_mulAddC_T; // @[MulAddRecFN.scala:71:7, :143:30] wire _io_toPostMul_isSigNaNAny_T = rawA_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_1 = ~_io_toPostMul_isSigNaNAny_T; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_2 = rawA_isNaN & _io_toPostMul_isSigNaNAny_T_1; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_3 = rawB_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_4 = ~_io_toPostMul_isSigNaNAny_T_3; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_5 = rawB_isNaN & _io_toPostMul_isSigNaNAny_T_4; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_6 = _io_toPostMul_isSigNaNAny_T_2 | _io_toPostMul_isSigNaNAny_T_5; // @[common.scala:82:46] wire _io_toPostMul_isSigNaNAny_T_7 = rawC_sig[51]; // @[rawFloatFromRecFN.scala:55:23] wire _io_toPostMul_isSigNaNAny_T_8 = ~_io_toPostMul_isSigNaNAny_T_7; // @[common.scala:82:{49,56}] wire _io_toPostMul_isSigNaNAny_T_9 = rawC_isNaN & _io_toPostMul_isSigNaNAny_T_8; // @[rawFloatFromRecFN.scala:55:23] assign _io_toPostMul_isSigNaNAny_T_10 = _io_toPostMul_isSigNaNAny_T_6 | _io_toPostMul_isSigNaNAny_T_9; // @[common.scala:82:46] assign io_toPostMul_isSigNaNAny_0 = _io_toPostMul_isSigNaNAny_T_10; // @[MulAddRecFN.scala:71:7, :146:58] assign _io_toPostMul_isNaNAOrB_T = rawA_isNaN | rawB_isNaN; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_isNaNAOrB_0 = _io_toPostMul_isNaNAOrB_T; // @[MulAddRecFN.scala:71:7, :148:42] wire [14:0] _io_toPostMul_sExpSum_T = _GEN - 15'h35; // @[MulAddRecFN.scala:106:42, :158:53] wire [13:0] _io_toPostMul_sExpSum_T_1 = _io_toPostMul_sExpSum_T[13:0]; // @[MulAddRecFN.scala:158:53] wire [13:0] _io_toPostMul_sExpSum_T_2 = _io_toPostMul_sExpSum_T_1; // @[MulAddRecFN.scala:158:53] wire [13:0] _io_toPostMul_sExpSum_T_3 = CIsDominant ? {rawC_sExp[12], rawC_sExp} : _io_toPostMul_sExpSum_T_2; // @[rawFloatFromRecFN.scala:55:23] assign io_toPostMul_sExpSum_0 = _io_toPostMul_sExpSum_T_3[12:0]; // @[MulAddRecFN.scala:71:7, :157:28, :158:12] assign _io_toPostMul_CDom_CAlignDist_T = CAlignDist[5:0]; // @[MulAddRecFN.scala:112:12, :161:47] assign io_toPostMul_CDom_CAlignDist_0 = _io_toPostMul_CDom_CAlignDist_T; // @[MulAddRecFN.scala:71:7, :161:47] assign _io_toPostMul_highAlignedSigC_T = alignedSigC[161:107]; // @[MulAddRecFN.scala:132:12, :163:20] assign io_toPostMul_highAlignedSigC_0 = _io_toPostMul_highAlignedSigC_T; // @[MulAddRecFN.scala:71:7, :163:20] assign _io_toPostMul_bit0AlignedSigC_T = alignedSigC[0]; // @[MulAddRecFN.scala:132:12, :164:48] assign io_toPostMul_bit0AlignedSigC_0 = _io_toPostMul_bit0AlignedSigC_T; // @[MulAddRecFN.scala:71:7, :164:48] assign io_mulAddA = io_mulAddA_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddB = io_mulAddB_0; // @[MulAddRecFN.scala:71:7] assign io_mulAddC = io_mulAddC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isSigNaNAny = io_toPostMul_isSigNaNAny_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNAOrB = io_toPostMul_isNaNAOrB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfA = io_toPostMul_isInfA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroA = io_toPostMul_isZeroA_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfB = io_toPostMul_isInfB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroB = io_toPostMul_isZeroB_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_signProd = io_toPostMul_signProd_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isNaNC = io_toPostMul_isNaNC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isInfC = io_toPostMul_isInfC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_isZeroC = io_toPostMul_isZeroC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_sExpSum = io_toPostMul_sExpSum_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_doSubMags = io_toPostMul_doSubMags_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CIsDominant = io_toPostMul_CIsDominant_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_CDom_CAlignDist = io_toPostMul_CDom_CAlignDist_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_highAlignedSigC = io_toPostMul_highAlignedSigC_0; // @[MulAddRecFN.scala:71:7] assign io_toPostMul_bit0AlignedSigC = io_toPostMul_bit0AlignedSigC_0; // @[MulAddRecFN.scala:71:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module TLMonitor_104 : input clock : Clock input reset : Reset output io : { flip in : { a : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, d : { ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}} when io.in.a.valid : node _T = leq(io.in.a.bits.opcode, UInt<3>(0h7)) node _T_1 = asUInt(reset) node _T_2 = eq(_T_1, UInt<1>(0h0)) when _T_2 : node _T_3 = eq(_T, UInt<1>(0h0)) when _T_3 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf assert(clock, _T, UInt<1>(0h1), "") : assert node _source_ok_T = eq(io.in.a.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits = bits(_source_ok_uncommonBits_T, 1, 0) node _source_ok_T_1 = shr(io.in.a.bits.source, 2) node _source_ok_T_2 = eq(_source_ok_T_1, UInt<1>(0h0)) node _source_ok_T_3 = leq(UInt<1>(0h0), source_ok_uncommonBits) node _source_ok_T_4 = and(_source_ok_T_2, _source_ok_T_3) node _source_ok_T_5 = leq(source_ok_uncommonBits, UInt<2>(0h3)) node _source_ok_T_6 = and(_source_ok_T_4, _source_ok_T_5) node _source_ok_uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_1 = bits(_source_ok_uncommonBits_T_1, 1, 0) node _source_ok_T_7 = shr(io.in.a.bits.source, 2) node _source_ok_T_8 = eq(_source_ok_T_7, UInt<1>(0h1)) node _source_ok_T_9 = leq(UInt<1>(0h0), source_ok_uncommonBits_1) node _source_ok_T_10 = and(_source_ok_T_8, _source_ok_T_9) node _source_ok_T_11 = leq(source_ok_uncommonBits_1, UInt<2>(0h3)) node _source_ok_T_12 = and(_source_ok_T_10, _source_ok_T_11) node _source_ok_uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_2 = bits(_source_ok_uncommonBits_T_2, 1, 0) node _source_ok_T_13 = shr(io.in.a.bits.source, 2) node _source_ok_T_14 = eq(_source_ok_T_13, UInt<2>(0h2)) node _source_ok_T_15 = leq(UInt<1>(0h0), source_ok_uncommonBits_2) node _source_ok_T_16 = and(_source_ok_T_14, _source_ok_T_15) node _source_ok_T_17 = leq(source_ok_uncommonBits_2, UInt<2>(0h3)) node _source_ok_T_18 = and(_source_ok_T_16, _source_ok_T_17) node _source_ok_uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_3 = bits(_source_ok_uncommonBits_T_3, 1, 0) node _source_ok_T_19 = shr(io.in.a.bits.source, 2) node _source_ok_T_20 = eq(_source_ok_T_19, UInt<2>(0h3)) node _source_ok_T_21 = leq(UInt<1>(0h0), source_ok_uncommonBits_3) node _source_ok_T_22 = and(_source_ok_T_20, _source_ok_T_21) node _source_ok_T_23 = leq(source_ok_uncommonBits_3, UInt<2>(0h3)) node _source_ok_T_24 = and(_source_ok_T_22, _source_ok_T_23) node _source_ok_uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_4 = bits(_source_ok_uncommonBits_T_4, 2, 0) node _source_ok_T_25 = shr(io.in.a.bits.source, 3) node _source_ok_T_26 = eq(_source_ok_T_25, UInt<3>(0h4)) node _source_ok_T_27 = leq(UInt<1>(0h0), source_ok_uncommonBits_4) node _source_ok_T_28 = and(_source_ok_T_26, _source_ok_T_27) node _source_ok_T_29 = leq(source_ok_uncommonBits_4, UInt<3>(0h7)) node _source_ok_T_30 = and(_source_ok_T_28, _source_ok_T_29) node _source_ok_T_31 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _source_ok_T_32 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _source_ok_T_33 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _source_ok_T_34 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE : UInt<1>[10] connect _source_ok_WIRE[0], _source_ok_T connect _source_ok_WIRE[1], _source_ok_T_6 connect _source_ok_WIRE[2], _source_ok_T_12 connect _source_ok_WIRE[3], _source_ok_T_18 connect _source_ok_WIRE[4], _source_ok_T_24 connect _source_ok_WIRE[5], _source_ok_T_30 connect _source_ok_WIRE[6], _source_ok_T_31 connect _source_ok_WIRE[7], _source_ok_T_32 connect _source_ok_WIRE[8], _source_ok_T_33 connect _source_ok_WIRE[9], _source_ok_T_34 node _source_ok_T_35 = or(_source_ok_WIRE[0], _source_ok_WIRE[1]) node _source_ok_T_36 = or(_source_ok_T_35, _source_ok_WIRE[2]) node _source_ok_T_37 = or(_source_ok_T_36, _source_ok_WIRE[3]) node _source_ok_T_38 = or(_source_ok_T_37, _source_ok_WIRE[4]) node _source_ok_T_39 = or(_source_ok_T_38, _source_ok_WIRE[5]) node _source_ok_T_40 = or(_source_ok_T_39, _source_ok_WIRE[6]) node _source_ok_T_41 = or(_source_ok_T_40, _source_ok_WIRE[7]) node _source_ok_T_42 = or(_source_ok_T_41, _source_ok_WIRE[8]) node source_ok = or(_source_ok_T_42, _source_ok_WIRE[9]) node _is_aligned_mask_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _is_aligned_mask_T_1 = bits(_is_aligned_mask_T, 5, 0) node is_aligned_mask = not(_is_aligned_mask_T_1) node _is_aligned_T = and(io.in.a.bits.address, is_aligned_mask) node is_aligned = eq(_is_aligned_T, UInt<1>(0h0)) node _mask_sizeOH_T = or(io.in.a.bits.size, UInt<3>(0h0)) node mask_sizeOH_shiftAmount = bits(_mask_sizeOH_T, 1, 0) node _mask_sizeOH_T_1 = dshl(UInt<1>(0h1), mask_sizeOH_shiftAmount) node _mask_sizeOH_T_2 = bits(_mask_sizeOH_T_1, 2, 0) node mask_sizeOH = or(_mask_sizeOH_T_2, UInt<1>(0h1)) node mask_sub_sub_sub_0_1 = geq(io.in.a.bits.size, UInt<2>(0h3)) node mask_sub_sub_size = bits(mask_sizeOH, 2, 2) node mask_sub_sub_bit = bits(io.in.a.bits.address, 2, 2) node mask_sub_sub_nbit = eq(mask_sub_sub_bit, UInt<1>(0h0)) node mask_sub_sub_0_2 = and(UInt<1>(0h1), mask_sub_sub_nbit) node _mask_sub_sub_acc_T = and(mask_sub_sub_size, mask_sub_sub_0_2) node mask_sub_sub_0_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T) node mask_sub_sub_1_2 = and(UInt<1>(0h1), mask_sub_sub_bit) node _mask_sub_sub_acc_T_1 = and(mask_sub_sub_size, mask_sub_sub_1_2) node mask_sub_sub_1_1 = or(mask_sub_sub_sub_0_1, _mask_sub_sub_acc_T_1) node mask_sub_size = bits(mask_sizeOH, 1, 1) node mask_sub_bit = bits(io.in.a.bits.address, 1, 1) node mask_sub_nbit = eq(mask_sub_bit, UInt<1>(0h0)) node mask_sub_0_2 = and(mask_sub_sub_0_2, mask_sub_nbit) node _mask_sub_acc_T = and(mask_sub_size, mask_sub_0_2) node mask_sub_0_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T) node mask_sub_1_2 = and(mask_sub_sub_0_2, mask_sub_bit) node _mask_sub_acc_T_1 = and(mask_sub_size, mask_sub_1_2) node mask_sub_1_1 = or(mask_sub_sub_0_1, _mask_sub_acc_T_1) node mask_sub_2_2 = and(mask_sub_sub_1_2, mask_sub_nbit) node _mask_sub_acc_T_2 = and(mask_sub_size, mask_sub_2_2) node mask_sub_2_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_2) node mask_sub_3_2 = and(mask_sub_sub_1_2, mask_sub_bit) node _mask_sub_acc_T_3 = and(mask_sub_size, mask_sub_3_2) node mask_sub_3_1 = or(mask_sub_sub_1_1, _mask_sub_acc_T_3) node mask_size = bits(mask_sizeOH, 0, 0) node mask_bit = bits(io.in.a.bits.address, 0, 0) node mask_nbit = eq(mask_bit, UInt<1>(0h0)) node mask_eq = and(mask_sub_0_2, mask_nbit) node _mask_acc_T = and(mask_size, mask_eq) node mask_acc = or(mask_sub_0_1, _mask_acc_T) node mask_eq_1 = and(mask_sub_0_2, mask_bit) node _mask_acc_T_1 = and(mask_size, mask_eq_1) node mask_acc_1 = or(mask_sub_0_1, _mask_acc_T_1) node mask_eq_2 = and(mask_sub_1_2, mask_nbit) node _mask_acc_T_2 = and(mask_size, mask_eq_2) node mask_acc_2 = or(mask_sub_1_1, _mask_acc_T_2) node mask_eq_3 = and(mask_sub_1_2, mask_bit) node _mask_acc_T_3 = and(mask_size, mask_eq_3) node mask_acc_3 = or(mask_sub_1_1, _mask_acc_T_3) node mask_eq_4 = and(mask_sub_2_2, mask_nbit) node _mask_acc_T_4 = and(mask_size, mask_eq_4) node mask_acc_4 = or(mask_sub_2_1, _mask_acc_T_4) node mask_eq_5 = and(mask_sub_2_2, mask_bit) node _mask_acc_T_5 = and(mask_size, mask_eq_5) node mask_acc_5 = or(mask_sub_2_1, _mask_acc_T_5) node mask_eq_6 = and(mask_sub_3_2, mask_nbit) node _mask_acc_T_6 = and(mask_size, mask_eq_6) node mask_acc_6 = or(mask_sub_3_1, _mask_acc_T_6) node mask_eq_7 = and(mask_sub_3_2, mask_bit) node _mask_acc_T_7 = and(mask_size, mask_eq_7) node mask_acc_7 = or(mask_sub_3_1, _mask_acc_T_7) node mask_lo_lo = cat(mask_acc_1, mask_acc) node mask_lo_hi = cat(mask_acc_3, mask_acc_2) node mask_lo = cat(mask_lo_hi, mask_lo_lo) node mask_hi_lo = cat(mask_acc_5, mask_acc_4) node mask_hi_hi = cat(mask_acc_7, mask_acc_6) node mask_hi = cat(mask_hi_hi, mask_hi_lo) node mask = cat(mask_hi, mask_lo) node _T_4 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _T_5 = eq(_T_4, UInt<1>(0h0)) node _T_6 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_7 = cvt(_T_6) node _T_8 = and(_T_7, asSInt(UInt<1>(0h0))) node _T_9 = asSInt(_T_8) node _T_10 = eq(_T_9, asSInt(UInt<1>(0h0))) node _T_11 = or(_T_5, _T_10) node _uncommonBits_T = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits = bits(_uncommonBits_T, 1, 0) node _T_12 = shr(io.in.a.bits.source, 2) node _T_13 = eq(_T_12, UInt<1>(0h0)) node _T_14 = leq(UInt<1>(0h0), uncommonBits) node _T_15 = and(_T_13, _T_14) node _T_16 = leq(uncommonBits, UInt<2>(0h3)) node _T_17 = and(_T_15, _T_16) node _T_18 = eq(_T_17, UInt<1>(0h0)) node _T_19 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_20 = cvt(_T_19) node _T_21 = and(_T_20, asSInt(UInt<1>(0h0))) node _T_22 = asSInt(_T_21) node _T_23 = eq(_T_22, asSInt(UInt<1>(0h0))) node _T_24 = or(_T_18, _T_23) node _uncommonBits_T_1 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_1 = bits(_uncommonBits_T_1, 1, 0) node _T_25 = shr(io.in.a.bits.source, 2) node _T_26 = eq(_T_25, UInt<1>(0h1)) node _T_27 = leq(UInt<1>(0h0), uncommonBits_1) node _T_28 = and(_T_26, _T_27) node _T_29 = leq(uncommonBits_1, UInt<2>(0h3)) node _T_30 = and(_T_28, _T_29) node _T_31 = eq(_T_30, UInt<1>(0h0)) node _T_32 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_33 = cvt(_T_32) node _T_34 = and(_T_33, asSInt(UInt<1>(0h0))) node _T_35 = asSInt(_T_34) node _T_36 = eq(_T_35, asSInt(UInt<1>(0h0))) node _T_37 = or(_T_31, _T_36) node _uncommonBits_T_2 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_2 = bits(_uncommonBits_T_2, 1, 0) node _T_38 = shr(io.in.a.bits.source, 2) node _T_39 = eq(_T_38, UInt<2>(0h2)) node _T_40 = leq(UInt<1>(0h0), uncommonBits_2) node _T_41 = and(_T_39, _T_40) node _T_42 = leq(uncommonBits_2, UInt<2>(0h3)) node _T_43 = and(_T_41, _T_42) node _T_44 = eq(_T_43, UInt<1>(0h0)) node _T_45 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_46 = cvt(_T_45) node _T_47 = and(_T_46, asSInt(UInt<1>(0h0))) node _T_48 = asSInt(_T_47) node _T_49 = eq(_T_48, asSInt(UInt<1>(0h0))) node _T_50 = or(_T_44, _T_49) node _uncommonBits_T_3 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_3 = bits(_uncommonBits_T_3, 1, 0) node _T_51 = shr(io.in.a.bits.source, 2) node _T_52 = eq(_T_51, UInt<2>(0h3)) node _T_53 = leq(UInt<1>(0h0), uncommonBits_3) node _T_54 = and(_T_52, _T_53) node _T_55 = leq(uncommonBits_3, UInt<2>(0h3)) node _T_56 = and(_T_54, _T_55) node _T_57 = eq(_T_56, UInt<1>(0h0)) node _T_58 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_59 = cvt(_T_58) node _T_60 = and(_T_59, asSInt(UInt<1>(0h0))) node _T_61 = asSInt(_T_60) node _T_62 = eq(_T_61, asSInt(UInt<1>(0h0))) node _T_63 = or(_T_57, _T_62) node _uncommonBits_T_4 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_4 = bits(_uncommonBits_T_4, 2, 0) node _T_64 = shr(io.in.a.bits.source, 3) node _T_65 = eq(_T_64, UInt<3>(0h4)) node _T_66 = leq(UInt<1>(0h0), uncommonBits_4) node _T_67 = and(_T_65, _T_66) node _T_68 = leq(uncommonBits_4, UInt<3>(0h7)) node _T_69 = and(_T_67, _T_68) node _T_70 = eq(_T_69, UInt<1>(0h0)) node _T_71 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_72 = cvt(_T_71) node _T_73 = and(_T_72, asSInt(UInt<1>(0h0))) node _T_74 = asSInt(_T_73) node _T_75 = eq(_T_74, asSInt(UInt<1>(0h0))) node _T_76 = or(_T_70, _T_75) node _T_77 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_78 = eq(_T_77, UInt<1>(0h0)) node _T_79 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_80 = cvt(_T_79) node _T_81 = and(_T_80, asSInt(UInt<1>(0h0))) node _T_82 = asSInt(_T_81) node _T_83 = eq(_T_82, asSInt(UInt<1>(0h0))) node _T_84 = or(_T_78, _T_83) node _T_85 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_86 = eq(_T_85, UInt<1>(0h0)) node _T_87 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_88 = cvt(_T_87) node _T_89 = and(_T_88, asSInt(UInt<1>(0h0))) node _T_90 = asSInt(_T_89) node _T_91 = eq(_T_90, asSInt(UInt<1>(0h0))) node _T_92 = or(_T_86, _T_91) node _T_93 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_94 = eq(_T_93, UInt<1>(0h0)) node _T_95 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_96 = cvt(_T_95) node _T_97 = and(_T_96, asSInt(UInt<1>(0h0))) node _T_98 = asSInt(_T_97) node _T_99 = eq(_T_98, asSInt(UInt<1>(0h0))) node _T_100 = or(_T_94, _T_99) node _T_101 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_102 = eq(_T_101, UInt<1>(0h0)) node _T_103 = xor(io.in.a.bits.address, UInt<1>(0h0)) node _T_104 = cvt(_T_103) node _T_105 = and(_T_104, asSInt(UInt<1>(0h0))) node _T_106 = asSInt(_T_105) node _T_107 = eq(_T_106, asSInt(UInt<1>(0h0))) node _T_108 = or(_T_102, _T_107) node _T_109 = and(_T_11, _T_24) node _T_110 = and(_T_109, _T_37) node _T_111 = and(_T_110, _T_50) node _T_112 = and(_T_111, _T_63) node _T_113 = and(_T_112, _T_76) node _T_114 = and(_T_113, _T_84) node _T_115 = and(_T_114, _T_92) node _T_116 = and(_T_115, _T_100) node _T_117 = and(_T_116, _T_108) node _T_118 = asUInt(reset) node _T_119 = eq(_T_118, UInt<1>(0h0)) when _T_119 : node _T_120 = eq(_T_117, UInt<1>(0h0)) when _T_120 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries an address illegal for the specified bank visibility\n at Monitor.scala:45 assert(cond, message)\n") : printf_1 assert(clock, _T_117, UInt<1>(0h1), "") : assert_1 node _T_121 = eq(io.in.a.bits.opcode, UInt<3>(0h6)) when _T_121 : node _T_122 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_123 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_124 = and(_T_122, _T_123) node _T_125 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_5 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_5 = bits(_uncommonBits_T_5, 1, 0) node _T_126 = shr(io.in.a.bits.source, 2) node _T_127 = eq(_T_126, UInt<1>(0h0)) node _T_128 = leq(UInt<1>(0h0), uncommonBits_5) node _T_129 = and(_T_127, _T_128) node _T_130 = leq(uncommonBits_5, UInt<2>(0h3)) node _T_131 = and(_T_129, _T_130) node _uncommonBits_T_6 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_6 = bits(_uncommonBits_T_6, 1, 0) node _T_132 = shr(io.in.a.bits.source, 2) node _T_133 = eq(_T_132, UInt<1>(0h1)) node _T_134 = leq(UInt<1>(0h0), uncommonBits_6) node _T_135 = and(_T_133, _T_134) node _T_136 = leq(uncommonBits_6, UInt<2>(0h3)) node _T_137 = and(_T_135, _T_136) node _uncommonBits_T_7 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_7 = bits(_uncommonBits_T_7, 1, 0) node _T_138 = shr(io.in.a.bits.source, 2) node _T_139 = eq(_T_138, UInt<2>(0h2)) node _T_140 = leq(UInt<1>(0h0), uncommonBits_7) node _T_141 = and(_T_139, _T_140) node _T_142 = leq(uncommonBits_7, UInt<2>(0h3)) node _T_143 = and(_T_141, _T_142) node _uncommonBits_T_8 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_8 = bits(_uncommonBits_T_8, 1, 0) node _T_144 = shr(io.in.a.bits.source, 2) node _T_145 = eq(_T_144, UInt<2>(0h3)) node _T_146 = leq(UInt<1>(0h0), uncommonBits_8) node _T_147 = and(_T_145, _T_146) node _T_148 = leq(uncommonBits_8, UInt<2>(0h3)) node _T_149 = and(_T_147, _T_148) node _uncommonBits_T_9 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_9 = bits(_uncommonBits_T_9, 2, 0) node _T_150 = shr(io.in.a.bits.source, 3) node _T_151 = eq(_T_150, UInt<3>(0h4)) node _T_152 = leq(UInt<1>(0h0), uncommonBits_9) node _T_153 = and(_T_151, _T_152) node _T_154 = leq(uncommonBits_9, UInt<3>(0h7)) node _T_155 = and(_T_153, _T_154) node _T_156 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_157 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_158 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_159 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_160 = or(_T_125, _T_131) node _T_161 = or(_T_160, _T_137) node _T_162 = or(_T_161, _T_143) node _T_163 = or(_T_162, _T_149) node _T_164 = or(_T_163, _T_155) node _T_165 = or(_T_164, _T_156) node _T_166 = or(_T_165, _T_157) node _T_167 = or(_T_166, _T_158) node _T_168 = or(_T_167, _T_159) node _T_169 = and(_T_124, _T_168) node _T_170 = or(UInt<1>(0h0), _T_169) node _T_171 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_172 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_173 = cvt(_T_172) node _T_174 = and(_T_173, asSInt(UInt<13>(0h1000))) node _T_175 = asSInt(_T_174) node _T_176 = eq(_T_175, asSInt(UInt<1>(0h0))) node _T_177 = and(_T_171, _T_176) node _T_178 = or(UInt<1>(0h0), _T_177) node _T_179 = and(_T_170, _T_178) node _T_180 = asUInt(reset) node _T_181 = eq(_T_180, UInt<1>(0h0)) when _T_181 : node _T_182 = eq(_T_179, UInt<1>(0h0)) when _T_182 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_2 assert(clock, _T_179, UInt<1>(0h1), "") : assert_2 node _T_183 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_10 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_10 = bits(_uncommonBits_T_10, 1, 0) node _T_184 = shr(io.in.a.bits.source, 2) node _T_185 = eq(_T_184, UInt<1>(0h0)) node _T_186 = leq(UInt<1>(0h0), uncommonBits_10) node _T_187 = and(_T_185, _T_186) node _T_188 = leq(uncommonBits_10, UInt<2>(0h3)) node _T_189 = and(_T_187, _T_188) node _uncommonBits_T_11 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_11 = bits(_uncommonBits_T_11, 1, 0) node _T_190 = shr(io.in.a.bits.source, 2) node _T_191 = eq(_T_190, UInt<1>(0h1)) node _T_192 = leq(UInt<1>(0h0), uncommonBits_11) node _T_193 = and(_T_191, _T_192) node _T_194 = leq(uncommonBits_11, UInt<2>(0h3)) node _T_195 = and(_T_193, _T_194) node _uncommonBits_T_12 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_12 = bits(_uncommonBits_T_12, 1, 0) node _T_196 = shr(io.in.a.bits.source, 2) node _T_197 = eq(_T_196, UInt<2>(0h2)) node _T_198 = leq(UInt<1>(0h0), uncommonBits_12) node _T_199 = and(_T_197, _T_198) node _T_200 = leq(uncommonBits_12, UInt<2>(0h3)) node _T_201 = and(_T_199, _T_200) node _uncommonBits_T_13 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_13 = bits(_uncommonBits_T_13, 1, 0) node _T_202 = shr(io.in.a.bits.source, 2) node _T_203 = eq(_T_202, UInt<2>(0h3)) node _T_204 = leq(UInt<1>(0h0), uncommonBits_13) node _T_205 = and(_T_203, _T_204) node _T_206 = leq(uncommonBits_13, UInt<2>(0h3)) node _T_207 = and(_T_205, _T_206) node _uncommonBits_T_14 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_14 = bits(_uncommonBits_T_14, 2, 0) node _T_208 = shr(io.in.a.bits.source, 3) node _T_209 = eq(_T_208, UInt<3>(0h4)) node _T_210 = leq(UInt<1>(0h0), uncommonBits_14) node _T_211 = and(_T_209, _T_210) node _T_212 = leq(uncommonBits_14, UInt<3>(0h7)) node _T_213 = and(_T_211, _T_212) node _T_214 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_215 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_216 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_217 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE : UInt<1>[10] connect _WIRE[0], _T_183 connect _WIRE[1], _T_189 connect _WIRE[2], _T_195 connect _WIRE[3], _T_201 connect _WIRE[4], _T_207 connect _WIRE[5], _T_213 connect _WIRE[6], _T_214 connect _WIRE[7], _T_215 connect _WIRE[8], _T_216 connect _WIRE[9], _T_217 node _T_218 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_219 = mux(_WIRE[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_220 = mux(_WIRE[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_221 = mux(_WIRE[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_222 = mux(_WIRE[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_223 = mux(_WIRE[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_224 = mux(_WIRE[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_225 = mux(_WIRE[6], _T_218, UInt<1>(0h0)) node _T_226 = mux(_WIRE[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_227 = mux(_WIRE[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_228 = mux(_WIRE[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_229 = or(_T_219, _T_220) node _T_230 = or(_T_229, _T_221) node _T_231 = or(_T_230, _T_222) node _T_232 = or(_T_231, _T_223) node _T_233 = or(_T_232, _T_224) node _T_234 = or(_T_233, _T_225) node _T_235 = or(_T_234, _T_226) node _T_236 = or(_T_235, _T_227) node _T_237 = or(_T_236, _T_228) wire _WIRE_1 : UInt<1> connect _WIRE_1, _T_237 node _T_238 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_239 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_240 = and(_T_238, _T_239) node _T_241 = or(UInt<1>(0h0), _T_240) node _T_242 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_243 = cvt(_T_242) node _T_244 = and(_T_243, asSInt(UInt<13>(0h1000))) node _T_245 = asSInt(_T_244) node _T_246 = eq(_T_245, asSInt(UInt<1>(0h0))) node _T_247 = and(_T_241, _T_246) node _T_248 = or(UInt<1>(0h0), _T_247) node _T_249 = and(_WIRE_1, _T_248) node _T_250 = asUInt(reset) node _T_251 = eq(_T_250, UInt<1>(0h0)) when _T_251 : node _T_252 = eq(_T_249, UInt<1>(0h0)) when _T_252 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquireBlock from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_3 assert(clock, _T_249, UInt<1>(0h1), "") : assert_3 node _T_253 = asUInt(reset) node _T_254 = eq(_T_253, UInt<1>(0h0)) when _T_254 : node _T_255 = eq(source_ok, UInt<1>(0h0)) when _T_255 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_4 assert(clock, source_ok, UInt<1>(0h1), "") : assert_4 node _T_256 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_257 = asUInt(reset) node _T_258 = eq(_T_257, UInt<1>(0h0)) when _T_258 : node _T_259 = eq(_T_256, UInt<1>(0h0)) when _T_259 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_5 assert(clock, _T_256, UInt<1>(0h1), "") : assert_5 node _T_260 = asUInt(reset) node _T_261 = eq(_T_260, UInt<1>(0h0)) when _T_261 : node _T_262 = eq(is_aligned, UInt<1>(0h0)) when _T_262 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_6 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_6 node _T_263 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_264 = asUInt(reset) node _T_265 = eq(_T_264, UInt<1>(0h0)) when _T_265 : node _T_266 = eq(_T_263, UInt<1>(0h0)) when _T_266 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_7 assert(clock, _T_263, UInt<1>(0h1), "") : assert_7 node _T_267 = not(io.in.a.bits.mask) node _T_268 = eq(_T_267, UInt<1>(0h0)) node _T_269 = asUInt(reset) node _T_270 = eq(_T_269, UInt<1>(0h0)) when _T_270 : node _T_271 = eq(_T_268, UInt<1>(0h0)) when _T_271 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_8 assert(clock, _T_268, UInt<1>(0h1), "") : assert_8 node _T_272 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_273 = asUInt(reset) node _T_274 = eq(_T_273, UInt<1>(0h0)) when _T_274 : node _T_275 = eq(_T_272, UInt<1>(0h0)) when _T_275 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquireBlock is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_9 assert(clock, _T_272, UInt<1>(0h1), "") : assert_9 node _T_276 = eq(io.in.a.bits.opcode, UInt<3>(0h7)) when _T_276 : node _T_277 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_278 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_279 = and(_T_277, _T_278) node _T_280 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_15 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_15 = bits(_uncommonBits_T_15, 1, 0) node _T_281 = shr(io.in.a.bits.source, 2) node _T_282 = eq(_T_281, UInt<1>(0h0)) node _T_283 = leq(UInt<1>(0h0), uncommonBits_15) node _T_284 = and(_T_282, _T_283) node _T_285 = leq(uncommonBits_15, UInt<2>(0h3)) node _T_286 = and(_T_284, _T_285) node _uncommonBits_T_16 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_16 = bits(_uncommonBits_T_16, 1, 0) node _T_287 = shr(io.in.a.bits.source, 2) node _T_288 = eq(_T_287, UInt<1>(0h1)) node _T_289 = leq(UInt<1>(0h0), uncommonBits_16) node _T_290 = and(_T_288, _T_289) node _T_291 = leq(uncommonBits_16, UInt<2>(0h3)) node _T_292 = and(_T_290, _T_291) node _uncommonBits_T_17 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_17 = bits(_uncommonBits_T_17, 1, 0) node _T_293 = shr(io.in.a.bits.source, 2) node _T_294 = eq(_T_293, UInt<2>(0h2)) node _T_295 = leq(UInt<1>(0h0), uncommonBits_17) node _T_296 = and(_T_294, _T_295) node _T_297 = leq(uncommonBits_17, UInt<2>(0h3)) node _T_298 = and(_T_296, _T_297) node _uncommonBits_T_18 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_18 = bits(_uncommonBits_T_18, 1, 0) node _T_299 = shr(io.in.a.bits.source, 2) node _T_300 = eq(_T_299, UInt<2>(0h3)) node _T_301 = leq(UInt<1>(0h0), uncommonBits_18) node _T_302 = and(_T_300, _T_301) node _T_303 = leq(uncommonBits_18, UInt<2>(0h3)) node _T_304 = and(_T_302, _T_303) node _uncommonBits_T_19 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_19 = bits(_uncommonBits_T_19, 2, 0) node _T_305 = shr(io.in.a.bits.source, 3) node _T_306 = eq(_T_305, UInt<3>(0h4)) node _T_307 = leq(UInt<1>(0h0), uncommonBits_19) node _T_308 = and(_T_306, _T_307) node _T_309 = leq(uncommonBits_19, UInt<3>(0h7)) node _T_310 = and(_T_308, _T_309) node _T_311 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_312 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_313 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_314 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_315 = or(_T_280, _T_286) node _T_316 = or(_T_315, _T_292) node _T_317 = or(_T_316, _T_298) node _T_318 = or(_T_317, _T_304) node _T_319 = or(_T_318, _T_310) node _T_320 = or(_T_319, _T_311) node _T_321 = or(_T_320, _T_312) node _T_322 = or(_T_321, _T_313) node _T_323 = or(_T_322, _T_314) node _T_324 = and(_T_279, _T_323) node _T_325 = or(UInt<1>(0h0), _T_324) node _T_326 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_327 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_328 = cvt(_T_327) node _T_329 = and(_T_328, asSInt(UInt<13>(0h1000))) node _T_330 = asSInt(_T_329) node _T_331 = eq(_T_330, asSInt(UInt<1>(0h0))) node _T_332 = and(_T_326, _T_331) node _T_333 = or(UInt<1>(0h0), _T_332) node _T_334 = and(_T_325, _T_333) node _T_335 = asUInt(reset) node _T_336 = eq(_T_335, UInt<1>(0h0)) when _T_336 : node _T_337 = eq(_T_334, UInt<1>(0h0)) when _T_337 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_10 assert(clock, _T_334, UInt<1>(0h1), "") : assert_10 node _T_338 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_20 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_20 = bits(_uncommonBits_T_20, 1, 0) node _T_339 = shr(io.in.a.bits.source, 2) node _T_340 = eq(_T_339, UInt<1>(0h0)) node _T_341 = leq(UInt<1>(0h0), uncommonBits_20) node _T_342 = and(_T_340, _T_341) node _T_343 = leq(uncommonBits_20, UInt<2>(0h3)) node _T_344 = and(_T_342, _T_343) node _uncommonBits_T_21 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_21 = bits(_uncommonBits_T_21, 1, 0) node _T_345 = shr(io.in.a.bits.source, 2) node _T_346 = eq(_T_345, UInt<1>(0h1)) node _T_347 = leq(UInt<1>(0h0), uncommonBits_21) node _T_348 = and(_T_346, _T_347) node _T_349 = leq(uncommonBits_21, UInt<2>(0h3)) node _T_350 = and(_T_348, _T_349) node _uncommonBits_T_22 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_22 = bits(_uncommonBits_T_22, 1, 0) node _T_351 = shr(io.in.a.bits.source, 2) node _T_352 = eq(_T_351, UInt<2>(0h2)) node _T_353 = leq(UInt<1>(0h0), uncommonBits_22) node _T_354 = and(_T_352, _T_353) node _T_355 = leq(uncommonBits_22, UInt<2>(0h3)) node _T_356 = and(_T_354, _T_355) node _uncommonBits_T_23 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_23 = bits(_uncommonBits_T_23, 1, 0) node _T_357 = shr(io.in.a.bits.source, 2) node _T_358 = eq(_T_357, UInt<2>(0h3)) node _T_359 = leq(UInt<1>(0h0), uncommonBits_23) node _T_360 = and(_T_358, _T_359) node _T_361 = leq(uncommonBits_23, UInt<2>(0h3)) node _T_362 = and(_T_360, _T_361) node _uncommonBits_T_24 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_24 = bits(_uncommonBits_T_24, 2, 0) node _T_363 = shr(io.in.a.bits.source, 3) node _T_364 = eq(_T_363, UInt<3>(0h4)) node _T_365 = leq(UInt<1>(0h0), uncommonBits_24) node _T_366 = and(_T_364, _T_365) node _T_367 = leq(uncommonBits_24, UInt<3>(0h7)) node _T_368 = and(_T_366, _T_367) node _T_369 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_370 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_371 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_372 = eq(io.in.a.bits.source, UInt<7>(0h40)) wire _WIRE_2 : UInt<1>[10] connect _WIRE_2[0], _T_338 connect _WIRE_2[1], _T_344 connect _WIRE_2[2], _T_350 connect _WIRE_2[3], _T_356 connect _WIRE_2[4], _T_362 connect _WIRE_2[5], _T_368 connect _WIRE_2[6], _T_369 connect _WIRE_2[7], _T_370 connect _WIRE_2[8], _T_371 connect _WIRE_2[9], _T_372 node _T_373 = eq(UInt<3>(0h6), io.in.a.bits.size) node _T_374 = mux(_WIRE_2[0], UInt<1>(0h0), UInt<1>(0h0)) node _T_375 = mux(_WIRE_2[1], UInt<1>(0h0), UInt<1>(0h0)) node _T_376 = mux(_WIRE_2[2], UInt<1>(0h0), UInt<1>(0h0)) node _T_377 = mux(_WIRE_2[3], UInt<1>(0h0), UInt<1>(0h0)) node _T_378 = mux(_WIRE_2[4], UInt<1>(0h0), UInt<1>(0h0)) node _T_379 = mux(_WIRE_2[5], UInt<1>(0h0), UInt<1>(0h0)) node _T_380 = mux(_WIRE_2[6], _T_373, UInt<1>(0h0)) node _T_381 = mux(_WIRE_2[7], UInt<1>(0h0), UInt<1>(0h0)) node _T_382 = mux(_WIRE_2[8], UInt<1>(0h0), UInt<1>(0h0)) node _T_383 = mux(_WIRE_2[9], UInt<1>(0h0), UInt<1>(0h0)) node _T_384 = or(_T_374, _T_375) node _T_385 = or(_T_384, _T_376) node _T_386 = or(_T_385, _T_377) node _T_387 = or(_T_386, _T_378) node _T_388 = or(_T_387, _T_379) node _T_389 = or(_T_388, _T_380) node _T_390 = or(_T_389, _T_381) node _T_391 = or(_T_390, _T_382) node _T_392 = or(_T_391, _T_383) wire _WIRE_3 : UInt<1> connect _WIRE_3, _T_392 node _T_393 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_394 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_395 = and(_T_393, _T_394) node _T_396 = or(UInt<1>(0h0), _T_395) node _T_397 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_398 = cvt(_T_397) node _T_399 = and(_T_398, asSInt(UInt<13>(0h1000))) node _T_400 = asSInt(_T_399) node _T_401 = eq(_T_400, asSInt(UInt<1>(0h0))) node _T_402 = and(_T_396, _T_401) node _T_403 = or(UInt<1>(0h0), _T_402) node _T_404 = and(_WIRE_3, _T_403) node _T_405 = asUInt(reset) node _T_406 = eq(_T_405, UInt<1>(0h0)) when _T_406 : node _T_407 = eq(_T_404, UInt<1>(0h0)) when _T_407 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries AcquirePerm from a client which does not support Probe (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_11 assert(clock, _T_404, UInt<1>(0h1), "") : assert_11 node _T_408 = asUInt(reset) node _T_409 = eq(_T_408, UInt<1>(0h0)) when _T_409 : node _T_410 = eq(source_ok, UInt<1>(0h0)) when _T_410 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_12 assert(clock, source_ok, UInt<1>(0h1), "") : assert_12 node _T_411 = geq(io.in.a.bits.size, UInt<2>(0h3)) node _T_412 = asUInt(reset) node _T_413 = eq(_T_412, UInt<1>(0h0)) when _T_413 : node _T_414 = eq(_T_411, UInt<1>(0h0)) when _T_414 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_13 assert(clock, _T_411, UInt<1>(0h1), "") : assert_13 node _T_415 = asUInt(reset) node _T_416 = eq(_T_415, UInt<1>(0h0)) when _T_416 : node _T_417 = eq(is_aligned, UInt<1>(0h0)) when _T_417 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_14 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_14 node _T_418 = leq(io.in.a.bits.param, UInt<2>(0h2)) node _T_419 = asUInt(reset) node _T_420 = eq(_T_419, UInt<1>(0h0)) when _T_420 : node _T_421 = eq(_T_418, UInt<1>(0h0)) when _T_421 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm carries invalid grow param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_15 assert(clock, _T_418, UInt<1>(0h1), "") : assert_15 node _T_422 = neq(io.in.a.bits.param, UInt<2>(0h0)) node _T_423 = asUInt(reset) node _T_424 = eq(_T_423, UInt<1>(0h0)) when _T_424 : node _T_425 = eq(_T_422, UInt<1>(0h0)) when _T_425 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm requests NtoB (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_16 assert(clock, _T_422, UInt<1>(0h1), "") : assert_16 node _T_426 = not(io.in.a.bits.mask) node _T_427 = eq(_T_426, UInt<1>(0h0)) node _T_428 = asUInt(reset) node _T_429 = eq(_T_428, UInt<1>(0h0)) when _T_429 : node _T_430 = eq(_T_427, UInt<1>(0h0)) when _T_430 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_17 assert(clock, _T_427, UInt<1>(0h1), "") : assert_17 node _T_431 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_432 = asUInt(reset) node _T_433 = eq(_T_432, UInt<1>(0h0)) when _T_433 : node _T_434 = eq(_T_431, UInt<1>(0h0)) when _T_434 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel AcquirePerm is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_18 assert(clock, _T_431, UInt<1>(0h1), "") : assert_18 node _T_435 = eq(io.in.a.bits.opcode, UInt<3>(0h4)) when _T_435 : node _T_436 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_437 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_438 = and(_T_436, _T_437) node _T_439 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_25 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_25 = bits(_uncommonBits_T_25, 1, 0) node _T_440 = shr(io.in.a.bits.source, 2) node _T_441 = eq(_T_440, UInt<1>(0h0)) node _T_442 = leq(UInt<1>(0h0), uncommonBits_25) node _T_443 = and(_T_441, _T_442) node _T_444 = leq(uncommonBits_25, UInt<2>(0h3)) node _T_445 = and(_T_443, _T_444) node _uncommonBits_T_26 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_26 = bits(_uncommonBits_T_26, 1, 0) node _T_446 = shr(io.in.a.bits.source, 2) node _T_447 = eq(_T_446, UInt<1>(0h1)) node _T_448 = leq(UInt<1>(0h0), uncommonBits_26) node _T_449 = and(_T_447, _T_448) node _T_450 = leq(uncommonBits_26, UInt<2>(0h3)) node _T_451 = and(_T_449, _T_450) node _uncommonBits_T_27 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_27 = bits(_uncommonBits_T_27, 1, 0) node _T_452 = shr(io.in.a.bits.source, 2) node _T_453 = eq(_T_452, UInt<2>(0h2)) node _T_454 = leq(UInt<1>(0h0), uncommonBits_27) node _T_455 = and(_T_453, _T_454) node _T_456 = leq(uncommonBits_27, UInt<2>(0h3)) node _T_457 = and(_T_455, _T_456) node _uncommonBits_T_28 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_28 = bits(_uncommonBits_T_28, 1, 0) node _T_458 = shr(io.in.a.bits.source, 2) node _T_459 = eq(_T_458, UInt<2>(0h3)) node _T_460 = leq(UInt<1>(0h0), uncommonBits_28) node _T_461 = and(_T_459, _T_460) node _T_462 = leq(uncommonBits_28, UInt<2>(0h3)) node _T_463 = and(_T_461, _T_462) node _uncommonBits_T_29 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_29 = bits(_uncommonBits_T_29, 2, 0) node _T_464 = shr(io.in.a.bits.source, 3) node _T_465 = eq(_T_464, UInt<3>(0h4)) node _T_466 = leq(UInt<1>(0h0), uncommonBits_29) node _T_467 = and(_T_465, _T_466) node _T_468 = leq(uncommonBits_29, UInt<3>(0h7)) node _T_469 = and(_T_467, _T_468) node _T_470 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_471 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_472 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_473 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_474 = or(_T_439, _T_445) node _T_475 = or(_T_474, _T_451) node _T_476 = or(_T_475, _T_457) node _T_477 = or(_T_476, _T_463) node _T_478 = or(_T_477, _T_469) node _T_479 = or(_T_478, _T_470) node _T_480 = or(_T_479, _T_471) node _T_481 = or(_T_480, _T_472) node _T_482 = or(_T_481, _T_473) node _T_483 = and(_T_438, _T_482) node _T_484 = or(UInt<1>(0h0), _T_483) node _T_485 = asUInt(reset) node _T_486 = eq(_T_485, UInt<1>(0h0)) when _T_486 : node _T_487 = eq(_T_484, UInt<1>(0h0)) when _T_487 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which master claims it can't emit (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_19 assert(clock, _T_484, UInt<1>(0h1), "") : assert_19 node _T_488 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_489 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_490 = and(_T_488, _T_489) node _T_491 = or(UInt<1>(0h0), _T_490) node _T_492 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_493 = cvt(_T_492) node _T_494 = and(_T_493, asSInt(UInt<13>(0h1000))) node _T_495 = asSInt(_T_494) node _T_496 = eq(_T_495, asSInt(UInt<1>(0h0))) node _T_497 = and(_T_491, _T_496) node _T_498 = or(UInt<1>(0h0), _T_497) node _T_499 = asUInt(reset) node _T_500 = eq(_T_499, UInt<1>(0h0)) when _T_500 : node _T_501 = eq(_T_498, UInt<1>(0h0)) when _T_501 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Get type which slave claims it can't support (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_20 assert(clock, _T_498, UInt<1>(0h1), "") : assert_20 node _T_502 = asUInt(reset) node _T_503 = eq(_T_502, UInt<1>(0h0)) when _T_503 : node _T_504 = eq(source_ok, UInt<1>(0h0)) when _T_504 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_21 assert(clock, source_ok, UInt<1>(0h1), "") : assert_21 node _T_505 = asUInt(reset) node _T_506 = eq(_T_505, UInt<1>(0h0)) when _T_506 : node _T_507 = eq(is_aligned, UInt<1>(0h0)) when _T_507 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_22 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_22 node _T_508 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_509 = asUInt(reset) node _T_510 = eq(_T_509, UInt<1>(0h0)) when _T_510 : node _T_511 = eq(_T_508, UInt<1>(0h0)) when _T_511 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_23 assert(clock, _T_508, UInt<1>(0h1), "") : assert_23 node _T_512 = eq(io.in.a.bits.mask, mask) node _T_513 = asUInt(reset) node _T_514 = eq(_T_513, UInt<1>(0h0)) when _T_514 : node _T_515 = eq(_T_512, UInt<1>(0h0)) when _T_515 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_24 assert(clock, _T_512, UInt<1>(0h1), "") : assert_24 node _T_516 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_517 = asUInt(reset) node _T_518 = eq(_T_517, UInt<1>(0h0)) when _T_518 : node _T_519 = eq(_T_516, UInt<1>(0h0)) when _T_519 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Get is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_25 assert(clock, _T_516, UInt<1>(0h1), "") : assert_25 node _T_520 = eq(io.in.a.bits.opcode, UInt<1>(0h0)) when _T_520 : node _T_521 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_522 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_523 = and(_T_521, _T_522) node _T_524 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_30 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_30 = bits(_uncommonBits_T_30, 1, 0) node _T_525 = shr(io.in.a.bits.source, 2) node _T_526 = eq(_T_525, UInt<1>(0h0)) node _T_527 = leq(UInt<1>(0h0), uncommonBits_30) node _T_528 = and(_T_526, _T_527) node _T_529 = leq(uncommonBits_30, UInt<2>(0h3)) node _T_530 = and(_T_528, _T_529) node _uncommonBits_T_31 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_31 = bits(_uncommonBits_T_31, 1, 0) node _T_531 = shr(io.in.a.bits.source, 2) node _T_532 = eq(_T_531, UInt<1>(0h1)) node _T_533 = leq(UInt<1>(0h0), uncommonBits_31) node _T_534 = and(_T_532, _T_533) node _T_535 = leq(uncommonBits_31, UInt<2>(0h3)) node _T_536 = and(_T_534, _T_535) node _uncommonBits_T_32 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_32 = bits(_uncommonBits_T_32, 1, 0) node _T_537 = shr(io.in.a.bits.source, 2) node _T_538 = eq(_T_537, UInt<2>(0h2)) node _T_539 = leq(UInt<1>(0h0), uncommonBits_32) node _T_540 = and(_T_538, _T_539) node _T_541 = leq(uncommonBits_32, UInt<2>(0h3)) node _T_542 = and(_T_540, _T_541) node _uncommonBits_T_33 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_33 = bits(_uncommonBits_T_33, 1, 0) node _T_543 = shr(io.in.a.bits.source, 2) node _T_544 = eq(_T_543, UInt<2>(0h3)) node _T_545 = leq(UInt<1>(0h0), uncommonBits_33) node _T_546 = and(_T_544, _T_545) node _T_547 = leq(uncommonBits_33, UInt<2>(0h3)) node _T_548 = and(_T_546, _T_547) node _uncommonBits_T_34 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_34 = bits(_uncommonBits_T_34, 2, 0) node _T_549 = shr(io.in.a.bits.source, 3) node _T_550 = eq(_T_549, UInt<3>(0h4)) node _T_551 = leq(UInt<1>(0h0), uncommonBits_34) node _T_552 = and(_T_550, _T_551) node _T_553 = leq(uncommonBits_34, UInt<3>(0h7)) node _T_554 = and(_T_552, _T_553) node _T_555 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_556 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_557 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_558 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_559 = or(_T_524, _T_530) node _T_560 = or(_T_559, _T_536) node _T_561 = or(_T_560, _T_542) node _T_562 = or(_T_561, _T_548) node _T_563 = or(_T_562, _T_554) node _T_564 = or(_T_563, _T_555) node _T_565 = or(_T_564, _T_556) node _T_566 = or(_T_565, _T_557) node _T_567 = or(_T_566, _T_558) node _T_568 = and(_T_523, _T_567) node _T_569 = or(UInt<1>(0h0), _T_568) node _T_570 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_571 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_572 = and(_T_570, _T_571) node _T_573 = or(UInt<1>(0h0), _T_572) node _T_574 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_575 = cvt(_T_574) node _T_576 = and(_T_575, asSInt(UInt<13>(0h1000))) node _T_577 = asSInt(_T_576) node _T_578 = eq(_T_577, asSInt(UInt<1>(0h0))) node _T_579 = and(_T_573, _T_578) node _T_580 = or(UInt<1>(0h0), _T_579) node _T_581 = and(_T_569, _T_580) node _T_582 = asUInt(reset) node _T_583 = eq(_T_582, UInt<1>(0h0)) when _T_583 : node _T_584 = eq(_T_581, UInt<1>(0h0)) when _T_584 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutFull type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_26 assert(clock, _T_581, UInt<1>(0h1), "") : assert_26 node _T_585 = asUInt(reset) node _T_586 = eq(_T_585, UInt<1>(0h0)) when _T_586 : node _T_587 = eq(source_ok, UInt<1>(0h0)) when _T_587 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_27 assert(clock, source_ok, UInt<1>(0h1), "") : assert_27 node _T_588 = asUInt(reset) node _T_589 = eq(_T_588, UInt<1>(0h0)) when _T_589 : node _T_590 = eq(is_aligned, UInt<1>(0h0)) when _T_590 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_28 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_28 node _T_591 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_592 = asUInt(reset) node _T_593 = eq(_T_592, UInt<1>(0h0)) when _T_593 : node _T_594 = eq(_T_591, UInt<1>(0h0)) when _T_594 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_29 assert(clock, _T_591, UInt<1>(0h1), "") : assert_29 node _T_595 = eq(io.in.a.bits.mask, mask) node _T_596 = asUInt(reset) node _T_597 = eq(_T_596, UInt<1>(0h0)) when _T_597 : node _T_598 = eq(_T_595, UInt<1>(0h0)) when _T_598 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutFull contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_30 assert(clock, _T_595, UInt<1>(0h1), "") : assert_30 node _T_599 = eq(io.in.a.bits.opcode, UInt<1>(0h1)) when _T_599 : node _T_600 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_601 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_602 = and(_T_600, _T_601) node _T_603 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_35 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_35 = bits(_uncommonBits_T_35, 1, 0) node _T_604 = shr(io.in.a.bits.source, 2) node _T_605 = eq(_T_604, UInt<1>(0h0)) node _T_606 = leq(UInt<1>(0h0), uncommonBits_35) node _T_607 = and(_T_605, _T_606) node _T_608 = leq(uncommonBits_35, UInt<2>(0h3)) node _T_609 = and(_T_607, _T_608) node _uncommonBits_T_36 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_36 = bits(_uncommonBits_T_36, 1, 0) node _T_610 = shr(io.in.a.bits.source, 2) node _T_611 = eq(_T_610, UInt<1>(0h1)) node _T_612 = leq(UInt<1>(0h0), uncommonBits_36) node _T_613 = and(_T_611, _T_612) node _T_614 = leq(uncommonBits_36, UInt<2>(0h3)) node _T_615 = and(_T_613, _T_614) node _uncommonBits_T_37 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_37 = bits(_uncommonBits_T_37, 1, 0) node _T_616 = shr(io.in.a.bits.source, 2) node _T_617 = eq(_T_616, UInt<2>(0h2)) node _T_618 = leq(UInt<1>(0h0), uncommonBits_37) node _T_619 = and(_T_617, _T_618) node _T_620 = leq(uncommonBits_37, UInt<2>(0h3)) node _T_621 = and(_T_619, _T_620) node _uncommonBits_T_38 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_38 = bits(_uncommonBits_T_38, 1, 0) node _T_622 = shr(io.in.a.bits.source, 2) node _T_623 = eq(_T_622, UInt<2>(0h3)) node _T_624 = leq(UInt<1>(0h0), uncommonBits_38) node _T_625 = and(_T_623, _T_624) node _T_626 = leq(uncommonBits_38, UInt<2>(0h3)) node _T_627 = and(_T_625, _T_626) node _uncommonBits_T_39 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_39 = bits(_uncommonBits_T_39, 2, 0) node _T_628 = shr(io.in.a.bits.source, 3) node _T_629 = eq(_T_628, UInt<3>(0h4)) node _T_630 = leq(UInt<1>(0h0), uncommonBits_39) node _T_631 = and(_T_629, _T_630) node _T_632 = leq(uncommonBits_39, UInt<3>(0h7)) node _T_633 = and(_T_631, _T_632) node _T_634 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_635 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_636 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_637 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_638 = or(_T_603, _T_609) node _T_639 = or(_T_638, _T_615) node _T_640 = or(_T_639, _T_621) node _T_641 = or(_T_640, _T_627) node _T_642 = or(_T_641, _T_633) node _T_643 = or(_T_642, _T_634) node _T_644 = or(_T_643, _T_635) node _T_645 = or(_T_644, _T_636) node _T_646 = or(_T_645, _T_637) node _T_647 = and(_T_602, _T_646) node _T_648 = or(UInt<1>(0h0), _T_647) node _T_649 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_650 = leq(io.in.a.bits.size, UInt<3>(0h6)) node _T_651 = and(_T_649, _T_650) node _T_652 = or(UInt<1>(0h0), _T_651) node _T_653 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_654 = cvt(_T_653) node _T_655 = and(_T_654, asSInt(UInt<13>(0h1000))) node _T_656 = asSInt(_T_655) node _T_657 = eq(_T_656, asSInt(UInt<1>(0h0))) node _T_658 = and(_T_652, _T_657) node _T_659 = or(UInt<1>(0h0), _T_658) node _T_660 = and(_T_648, _T_659) node _T_661 = asUInt(reset) node _T_662 = eq(_T_661, UInt<1>(0h0)) when _T_662 : node _T_663 = eq(_T_660, UInt<1>(0h0)) when _T_663 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries PutPartial type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_31 assert(clock, _T_660, UInt<1>(0h1), "") : assert_31 node _T_664 = asUInt(reset) node _T_665 = eq(_T_664, UInt<1>(0h0)) when _T_665 : node _T_666 = eq(source_ok, UInt<1>(0h0)) when _T_666 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_32 assert(clock, source_ok, UInt<1>(0h1), "") : assert_32 node _T_667 = asUInt(reset) node _T_668 = eq(_T_667, UInt<1>(0h0)) when _T_668 : node _T_669 = eq(is_aligned, UInt<1>(0h0)) when _T_669 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_33 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_33 node _T_670 = eq(io.in.a.bits.param, UInt<1>(0h0)) node _T_671 = asUInt(reset) node _T_672 = eq(_T_671, UInt<1>(0h0)) when _T_672 : node _T_673 = eq(_T_670, UInt<1>(0h0)) when _T_673 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_34 assert(clock, _T_670, UInt<1>(0h1), "") : assert_34 node _T_674 = not(mask) node _T_675 = and(io.in.a.bits.mask, _T_674) node _T_676 = eq(_T_675, UInt<1>(0h0)) node _T_677 = asUInt(reset) node _T_678 = eq(_T_677, UInt<1>(0h0)) when _T_678 : node _T_679 = eq(_T_676, UInt<1>(0h0)) when _T_679 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel PutPartial contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_35 assert(clock, _T_676, UInt<1>(0h1), "") : assert_35 node _T_680 = eq(io.in.a.bits.opcode, UInt<2>(0h2)) when _T_680 : node _T_681 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_682 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_683 = and(_T_681, _T_682) node _T_684 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_40 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_40 = bits(_uncommonBits_T_40, 1, 0) node _T_685 = shr(io.in.a.bits.source, 2) node _T_686 = eq(_T_685, UInt<1>(0h0)) node _T_687 = leq(UInt<1>(0h0), uncommonBits_40) node _T_688 = and(_T_686, _T_687) node _T_689 = leq(uncommonBits_40, UInt<2>(0h3)) node _T_690 = and(_T_688, _T_689) node _uncommonBits_T_41 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_41 = bits(_uncommonBits_T_41, 1, 0) node _T_691 = shr(io.in.a.bits.source, 2) node _T_692 = eq(_T_691, UInt<1>(0h1)) node _T_693 = leq(UInt<1>(0h0), uncommonBits_41) node _T_694 = and(_T_692, _T_693) node _T_695 = leq(uncommonBits_41, UInt<2>(0h3)) node _T_696 = and(_T_694, _T_695) node _uncommonBits_T_42 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_42 = bits(_uncommonBits_T_42, 1, 0) node _T_697 = shr(io.in.a.bits.source, 2) node _T_698 = eq(_T_697, UInt<2>(0h2)) node _T_699 = leq(UInt<1>(0h0), uncommonBits_42) node _T_700 = and(_T_698, _T_699) node _T_701 = leq(uncommonBits_42, UInt<2>(0h3)) node _T_702 = and(_T_700, _T_701) node _uncommonBits_T_43 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_43 = bits(_uncommonBits_T_43, 1, 0) node _T_703 = shr(io.in.a.bits.source, 2) node _T_704 = eq(_T_703, UInt<2>(0h3)) node _T_705 = leq(UInt<1>(0h0), uncommonBits_43) node _T_706 = and(_T_704, _T_705) node _T_707 = leq(uncommonBits_43, UInt<2>(0h3)) node _T_708 = and(_T_706, _T_707) node _uncommonBits_T_44 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_44 = bits(_uncommonBits_T_44, 2, 0) node _T_709 = shr(io.in.a.bits.source, 3) node _T_710 = eq(_T_709, UInt<3>(0h4)) node _T_711 = leq(UInt<1>(0h0), uncommonBits_44) node _T_712 = and(_T_710, _T_711) node _T_713 = leq(uncommonBits_44, UInt<3>(0h7)) node _T_714 = and(_T_712, _T_713) node _T_715 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_716 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_717 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_718 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_719 = or(_T_684, _T_690) node _T_720 = or(_T_719, _T_696) node _T_721 = or(_T_720, _T_702) node _T_722 = or(_T_721, _T_708) node _T_723 = or(_T_722, _T_714) node _T_724 = or(_T_723, _T_715) node _T_725 = or(_T_724, _T_716) node _T_726 = or(_T_725, _T_717) node _T_727 = or(_T_726, _T_718) node _T_728 = and(_T_683, _T_727) node _T_729 = or(UInt<1>(0h0), _T_728) node _T_730 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_731 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_732 = cvt(_T_731) node _T_733 = and(_T_732, asSInt(UInt<13>(0h1000))) node _T_734 = asSInt(_T_733) node _T_735 = eq(_T_734, asSInt(UInt<1>(0h0))) node _T_736 = and(_T_730, _T_735) node _T_737 = or(UInt<1>(0h0), _T_736) node _T_738 = and(_T_729, _T_737) node _T_739 = asUInt(reset) node _T_740 = eq(_T_739, UInt<1>(0h0)) when _T_740 : node _T_741 = eq(_T_738, UInt<1>(0h0)) when _T_741 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Arithmetic type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_36 assert(clock, _T_738, UInt<1>(0h1), "") : assert_36 node _T_742 = asUInt(reset) node _T_743 = eq(_T_742, UInt<1>(0h0)) when _T_743 : node _T_744 = eq(source_ok, UInt<1>(0h0)) when _T_744 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_37 assert(clock, source_ok, UInt<1>(0h1), "") : assert_37 node _T_745 = asUInt(reset) node _T_746 = eq(_T_745, UInt<1>(0h0)) when _T_746 : node _T_747 = eq(is_aligned, UInt<1>(0h0)) when _T_747 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_38 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_38 node _T_748 = leq(io.in.a.bits.param, UInt<3>(0h4)) node _T_749 = asUInt(reset) node _T_750 = eq(_T_749, UInt<1>(0h0)) when _T_750 : node _T_751 = eq(_T_748, UInt<1>(0h0)) when _T_751 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_39 assert(clock, _T_748, UInt<1>(0h1), "") : assert_39 node _T_752 = eq(io.in.a.bits.mask, mask) node _T_753 = asUInt(reset) node _T_754 = eq(_T_753, UInt<1>(0h0)) when _T_754 : node _T_755 = eq(_T_752, UInt<1>(0h0)) when _T_755 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Arithmetic contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_40 assert(clock, _T_752, UInt<1>(0h1), "") : assert_40 node _T_756 = eq(io.in.a.bits.opcode, UInt<2>(0h3)) when _T_756 : node _T_757 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_758 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_759 = and(_T_757, _T_758) node _T_760 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_45 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_45 = bits(_uncommonBits_T_45, 1, 0) node _T_761 = shr(io.in.a.bits.source, 2) node _T_762 = eq(_T_761, UInt<1>(0h0)) node _T_763 = leq(UInt<1>(0h0), uncommonBits_45) node _T_764 = and(_T_762, _T_763) node _T_765 = leq(uncommonBits_45, UInt<2>(0h3)) node _T_766 = and(_T_764, _T_765) node _uncommonBits_T_46 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_46 = bits(_uncommonBits_T_46, 1, 0) node _T_767 = shr(io.in.a.bits.source, 2) node _T_768 = eq(_T_767, UInt<1>(0h1)) node _T_769 = leq(UInt<1>(0h0), uncommonBits_46) node _T_770 = and(_T_768, _T_769) node _T_771 = leq(uncommonBits_46, UInt<2>(0h3)) node _T_772 = and(_T_770, _T_771) node _uncommonBits_T_47 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_47 = bits(_uncommonBits_T_47, 1, 0) node _T_773 = shr(io.in.a.bits.source, 2) node _T_774 = eq(_T_773, UInt<2>(0h2)) node _T_775 = leq(UInt<1>(0h0), uncommonBits_47) node _T_776 = and(_T_774, _T_775) node _T_777 = leq(uncommonBits_47, UInt<2>(0h3)) node _T_778 = and(_T_776, _T_777) node _uncommonBits_T_48 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_48 = bits(_uncommonBits_T_48, 1, 0) node _T_779 = shr(io.in.a.bits.source, 2) node _T_780 = eq(_T_779, UInt<2>(0h3)) node _T_781 = leq(UInt<1>(0h0), uncommonBits_48) node _T_782 = and(_T_780, _T_781) node _T_783 = leq(uncommonBits_48, UInt<2>(0h3)) node _T_784 = and(_T_782, _T_783) node _uncommonBits_T_49 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_49 = bits(_uncommonBits_T_49, 2, 0) node _T_785 = shr(io.in.a.bits.source, 3) node _T_786 = eq(_T_785, UInt<3>(0h4)) node _T_787 = leq(UInt<1>(0h0), uncommonBits_49) node _T_788 = and(_T_786, _T_787) node _T_789 = leq(uncommonBits_49, UInt<3>(0h7)) node _T_790 = and(_T_788, _T_789) node _T_791 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_792 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_793 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_794 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_795 = or(_T_760, _T_766) node _T_796 = or(_T_795, _T_772) node _T_797 = or(_T_796, _T_778) node _T_798 = or(_T_797, _T_784) node _T_799 = or(_T_798, _T_790) node _T_800 = or(_T_799, _T_791) node _T_801 = or(_T_800, _T_792) node _T_802 = or(_T_801, _T_793) node _T_803 = or(_T_802, _T_794) node _T_804 = and(_T_759, _T_803) node _T_805 = or(UInt<1>(0h0), _T_804) node _T_806 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_807 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_808 = cvt(_T_807) node _T_809 = and(_T_808, asSInt(UInt<13>(0h1000))) node _T_810 = asSInt(_T_809) node _T_811 = eq(_T_810, asSInt(UInt<1>(0h0))) node _T_812 = and(_T_806, _T_811) node _T_813 = or(UInt<1>(0h0), _T_812) node _T_814 = and(_T_805, _T_813) node _T_815 = asUInt(reset) node _T_816 = eq(_T_815, UInt<1>(0h0)) when _T_816 : node _T_817 = eq(_T_814, UInt<1>(0h0)) when _T_817 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Logical type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_41 assert(clock, _T_814, UInt<1>(0h1), "") : assert_41 node _T_818 = asUInt(reset) node _T_819 = eq(_T_818, UInt<1>(0h0)) when _T_819 : node _T_820 = eq(source_ok, UInt<1>(0h0)) when _T_820 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_42 assert(clock, source_ok, UInt<1>(0h1), "") : assert_42 node _T_821 = asUInt(reset) node _T_822 = eq(_T_821, UInt<1>(0h0)) when _T_822 : node _T_823 = eq(is_aligned, UInt<1>(0h0)) when _T_823 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_43 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_43 node _T_824 = leq(io.in.a.bits.param, UInt<3>(0h3)) node _T_825 = asUInt(reset) node _T_826 = eq(_T_825, UInt<1>(0h0)) when _T_826 : node _T_827 = eq(_T_824, UInt<1>(0h0)) when _T_827 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_44 assert(clock, _T_824, UInt<1>(0h1), "") : assert_44 node _T_828 = eq(io.in.a.bits.mask, mask) node _T_829 = asUInt(reset) node _T_830 = eq(_T_829, UInt<1>(0h0)) when _T_830 : node _T_831 = eq(_T_828, UInt<1>(0h0)) when _T_831 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Logical contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_45 assert(clock, _T_828, UInt<1>(0h1), "") : assert_45 node _T_832 = eq(io.in.a.bits.opcode, UInt<3>(0h5)) when _T_832 : node _T_833 = leq(UInt<1>(0h0), io.in.a.bits.size) node _T_834 = leq(io.in.a.bits.size, UInt<4>(0hc)) node _T_835 = and(_T_833, _T_834) node _T_836 = eq(io.in.a.bits.source, UInt<5>(0h10)) node _uncommonBits_T_50 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_50 = bits(_uncommonBits_T_50, 1, 0) node _T_837 = shr(io.in.a.bits.source, 2) node _T_838 = eq(_T_837, UInt<1>(0h0)) node _T_839 = leq(UInt<1>(0h0), uncommonBits_50) node _T_840 = and(_T_838, _T_839) node _T_841 = leq(uncommonBits_50, UInt<2>(0h3)) node _T_842 = and(_T_840, _T_841) node _uncommonBits_T_51 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_51 = bits(_uncommonBits_T_51, 1, 0) node _T_843 = shr(io.in.a.bits.source, 2) node _T_844 = eq(_T_843, UInt<1>(0h1)) node _T_845 = leq(UInt<1>(0h0), uncommonBits_51) node _T_846 = and(_T_844, _T_845) node _T_847 = leq(uncommonBits_51, UInt<2>(0h3)) node _T_848 = and(_T_846, _T_847) node _uncommonBits_T_52 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_52 = bits(_uncommonBits_T_52, 1, 0) node _T_849 = shr(io.in.a.bits.source, 2) node _T_850 = eq(_T_849, UInt<2>(0h2)) node _T_851 = leq(UInt<1>(0h0), uncommonBits_52) node _T_852 = and(_T_850, _T_851) node _T_853 = leq(uncommonBits_52, UInt<2>(0h3)) node _T_854 = and(_T_852, _T_853) node _uncommonBits_T_53 = or(io.in.a.bits.source, UInt<2>(0h0)) node uncommonBits_53 = bits(_uncommonBits_T_53, 1, 0) node _T_855 = shr(io.in.a.bits.source, 2) node _T_856 = eq(_T_855, UInt<2>(0h3)) node _T_857 = leq(UInt<1>(0h0), uncommonBits_53) node _T_858 = and(_T_856, _T_857) node _T_859 = leq(uncommonBits_53, UInt<2>(0h3)) node _T_860 = and(_T_858, _T_859) node _uncommonBits_T_54 = or(io.in.a.bits.source, UInt<3>(0h0)) node uncommonBits_54 = bits(_uncommonBits_T_54, 2, 0) node _T_861 = shr(io.in.a.bits.source, 3) node _T_862 = eq(_T_861, UInt<3>(0h4)) node _T_863 = leq(UInt<1>(0h0), uncommonBits_54) node _T_864 = and(_T_862, _T_863) node _T_865 = leq(uncommonBits_54, UInt<3>(0h7)) node _T_866 = and(_T_864, _T_865) node _T_867 = eq(io.in.a.bits.source, UInt<6>(0h28)) node _T_868 = eq(io.in.a.bits.source, UInt<6>(0h29)) node _T_869 = eq(io.in.a.bits.source, UInt<6>(0h2a)) node _T_870 = eq(io.in.a.bits.source, UInt<7>(0h40)) node _T_871 = or(_T_836, _T_842) node _T_872 = or(_T_871, _T_848) node _T_873 = or(_T_872, _T_854) node _T_874 = or(_T_873, _T_860) node _T_875 = or(_T_874, _T_866) node _T_876 = or(_T_875, _T_867) node _T_877 = or(_T_876, _T_868) node _T_878 = or(_T_877, _T_869) node _T_879 = or(_T_878, _T_870) node _T_880 = and(_T_835, _T_879) node _T_881 = or(UInt<1>(0h0), _T_880) node _T_882 = or(UInt<1>(0h0), UInt<1>(0h0)) node _T_883 = xor(io.in.a.bits.address, UInt<21>(0h110000)) node _T_884 = cvt(_T_883) node _T_885 = and(_T_884, asSInt(UInt<13>(0h1000))) node _T_886 = asSInt(_T_885) node _T_887 = eq(_T_886, asSInt(UInt<1>(0h0))) node _T_888 = and(_T_882, _T_887) node _T_889 = or(UInt<1>(0h0), _T_888) node _T_890 = and(_T_881, _T_889) node _T_891 = asUInt(reset) node _T_892 = eq(_T_891, UInt<1>(0h0)) when _T_892 : node _T_893 = eq(_T_890, UInt<1>(0h0)) when _T_893 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel carries Hint type which is unexpected using diplomatic parameters (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_46 assert(clock, _T_890, UInt<1>(0h1), "") : assert_46 node _T_894 = asUInt(reset) node _T_895 = eq(_T_894, UInt<1>(0h0)) when _T_895 : node _T_896 = eq(source_ok, UInt<1>(0h0)) when _T_896 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_47 assert(clock, source_ok, UInt<1>(0h1), "") : assert_47 node _T_897 = asUInt(reset) node _T_898 = eq(_T_897, UInt<1>(0h0)) when _T_898 : node _T_899 = eq(is_aligned, UInt<1>(0h0)) when _T_899 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint address not aligned to size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_48 assert(clock, is_aligned, UInt<1>(0h1), "") : assert_48 node _T_900 = leq(io.in.a.bits.param, UInt<1>(0h1)) node _T_901 = asUInt(reset) node _T_902 = eq(_T_901, UInt<1>(0h0)) when _T_902 : node _T_903 = eq(_T_900, UInt<1>(0h0)) when _T_903 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint carries invalid opcode param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_49 assert(clock, _T_900, UInt<1>(0h1), "") : assert_49 node _T_904 = eq(io.in.a.bits.mask, mask) node _T_905 = asUInt(reset) node _T_906 = eq(_T_905, UInt<1>(0h0)) when _T_906 : node _T_907 = eq(_T_904, UInt<1>(0h0)) when _T_907 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint contains invalid mask (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_50 assert(clock, _T_904, UInt<1>(0h1), "") : assert_50 node _T_908 = eq(io.in.a.bits.corrupt, UInt<1>(0h0)) node _T_909 = asUInt(reset) node _T_910 = eq(_T_909, UInt<1>(0h0)) when _T_910 : node _T_911 = eq(_T_908, UInt<1>(0h0)) when _T_911 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel Hint is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_51 assert(clock, _T_908, UInt<1>(0h1), "") : assert_51 when io.in.d.valid : node _T_912 = leq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_913 = asUInt(reset) node _T_914 = eq(_T_913, UInt<1>(0h0)) when _T_914 : node _T_915 = eq(_T_912, UInt<1>(0h0)) when _T_915 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel has invalid opcode (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_52 assert(clock, _T_912, UInt<1>(0h1), "") : assert_52 node _source_ok_T_43 = eq(io.in.d.bits.source, UInt<5>(0h10)) node _source_ok_uncommonBits_T_5 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_5 = bits(_source_ok_uncommonBits_T_5, 1, 0) node _source_ok_T_44 = shr(io.in.d.bits.source, 2) node _source_ok_T_45 = eq(_source_ok_T_44, UInt<1>(0h0)) node _source_ok_T_46 = leq(UInt<1>(0h0), source_ok_uncommonBits_5) node _source_ok_T_47 = and(_source_ok_T_45, _source_ok_T_46) node _source_ok_T_48 = leq(source_ok_uncommonBits_5, UInt<2>(0h3)) node _source_ok_T_49 = and(_source_ok_T_47, _source_ok_T_48) node _source_ok_uncommonBits_T_6 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_6 = bits(_source_ok_uncommonBits_T_6, 1, 0) node _source_ok_T_50 = shr(io.in.d.bits.source, 2) node _source_ok_T_51 = eq(_source_ok_T_50, UInt<1>(0h1)) node _source_ok_T_52 = leq(UInt<1>(0h0), source_ok_uncommonBits_6) node _source_ok_T_53 = and(_source_ok_T_51, _source_ok_T_52) node _source_ok_T_54 = leq(source_ok_uncommonBits_6, UInt<2>(0h3)) node _source_ok_T_55 = and(_source_ok_T_53, _source_ok_T_54) node _source_ok_uncommonBits_T_7 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_7 = bits(_source_ok_uncommonBits_T_7, 1, 0) node _source_ok_T_56 = shr(io.in.d.bits.source, 2) node _source_ok_T_57 = eq(_source_ok_T_56, UInt<2>(0h2)) node _source_ok_T_58 = leq(UInt<1>(0h0), source_ok_uncommonBits_7) node _source_ok_T_59 = and(_source_ok_T_57, _source_ok_T_58) node _source_ok_T_60 = leq(source_ok_uncommonBits_7, UInt<2>(0h3)) node _source_ok_T_61 = and(_source_ok_T_59, _source_ok_T_60) node _source_ok_uncommonBits_T_8 = or(io.in.d.bits.source, UInt<2>(0h0)) node source_ok_uncommonBits_8 = bits(_source_ok_uncommonBits_T_8, 1, 0) node _source_ok_T_62 = shr(io.in.d.bits.source, 2) node _source_ok_T_63 = eq(_source_ok_T_62, UInt<2>(0h3)) node _source_ok_T_64 = leq(UInt<1>(0h0), source_ok_uncommonBits_8) node _source_ok_T_65 = and(_source_ok_T_63, _source_ok_T_64) node _source_ok_T_66 = leq(source_ok_uncommonBits_8, UInt<2>(0h3)) node _source_ok_T_67 = and(_source_ok_T_65, _source_ok_T_66) node _source_ok_uncommonBits_T_9 = or(io.in.d.bits.source, UInt<3>(0h0)) node source_ok_uncommonBits_9 = bits(_source_ok_uncommonBits_T_9, 2, 0) node _source_ok_T_68 = shr(io.in.d.bits.source, 3) node _source_ok_T_69 = eq(_source_ok_T_68, UInt<3>(0h4)) node _source_ok_T_70 = leq(UInt<1>(0h0), source_ok_uncommonBits_9) node _source_ok_T_71 = and(_source_ok_T_69, _source_ok_T_70) node _source_ok_T_72 = leq(source_ok_uncommonBits_9, UInt<3>(0h7)) node _source_ok_T_73 = and(_source_ok_T_71, _source_ok_T_72) node _source_ok_T_74 = eq(io.in.d.bits.source, UInt<6>(0h28)) node _source_ok_T_75 = eq(io.in.d.bits.source, UInt<6>(0h29)) node _source_ok_T_76 = eq(io.in.d.bits.source, UInt<6>(0h2a)) node _source_ok_T_77 = eq(io.in.d.bits.source, UInt<7>(0h40)) wire _source_ok_WIRE_1 : UInt<1>[10] connect _source_ok_WIRE_1[0], _source_ok_T_43 connect _source_ok_WIRE_1[1], _source_ok_T_49 connect _source_ok_WIRE_1[2], _source_ok_T_55 connect _source_ok_WIRE_1[3], _source_ok_T_61 connect _source_ok_WIRE_1[4], _source_ok_T_67 connect _source_ok_WIRE_1[5], _source_ok_T_73 connect _source_ok_WIRE_1[6], _source_ok_T_74 connect _source_ok_WIRE_1[7], _source_ok_T_75 connect _source_ok_WIRE_1[8], _source_ok_T_76 connect _source_ok_WIRE_1[9], _source_ok_T_77 node _source_ok_T_78 = or(_source_ok_WIRE_1[0], _source_ok_WIRE_1[1]) node _source_ok_T_79 = or(_source_ok_T_78, _source_ok_WIRE_1[2]) node _source_ok_T_80 = or(_source_ok_T_79, _source_ok_WIRE_1[3]) node _source_ok_T_81 = or(_source_ok_T_80, _source_ok_WIRE_1[4]) node _source_ok_T_82 = or(_source_ok_T_81, _source_ok_WIRE_1[5]) node _source_ok_T_83 = or(_source_ok_T_82, _source_ok_WIRE_1[6]) node _source_ok_T_84 = or(_source_ok_T_83, _source_ok_WIRE_1[7]) node _source_ok_T_85 = or(_source_ok_T_84, _source_ok_WIRE_1[8]) node source_ok_1 = or(_source_ok_T_85, _source_ok_WIRE_1[9]) node sink_ok = lt(io.in.d.bits.sink, UInt<1>(0h0)) node _T_916 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) when _T_916 : node _T_917 = asUInt(reset) node _T_918 = eq(_T_917, UInt<1>(0h0)) when _T_918 : node _T_919 = eq(source_ok_1, UInt<1>(0h0)) when _T_919 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_53 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_53 node _T_920 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_921 = asUInt(reset) node _T_922 = eq(_T_921, UInt<1>(0h0)) when _T_922 : node _T_923 = eq(_T_920, UInt<1>(0h0)) when _T_923 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_54 assert(clock, _T_920, UInt<1>(0h1), "") : assert_54 node _T_924 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_925 = asUInt(reset) node _T_926 = eq(_T_925, UInt<1>(0h0)) when _T_926 : node _T_927 = eq(_T_924, UInt<1>(0h0)) when _T_927 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseeAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_55 assert(clock, _T_924, UInt<1>(0h1), "") : assert_55 node _T_928 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_929 = asUInt(reset) node _T_930 = eq(_T_929, UInt<1>(0h0)) when _T_930 : node _T_931 = eq(_T_928, UInt<1>(0h0)) when _T_931 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_56 assert(clock, _T_928, UInt<1>(0h1), "") : assert_56 node _T_932 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_933 = asUInt(reset) node _T_934 = eq(_T_933, UInt<1>(0h0)) when _T_934 : node _T_935 = eq(_T_932, UInt<1>(0h0)) when _T_935 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel ReleaseAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_57 assert(clock, _T_932, UInt<1>(0h1), "") : assert_57 node _T_936 = eq(io.in.d.bits.opcode, UInt<3>(0h4)) when _T_936 : node _T_937 = asUInt(reset) node _T_938 = eq(_T_937, UInt<1>(0h0)) when _T_938 : node _T_939 = eq(source_ok_1, UInt<1>(0h0)) when _T_939 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_58 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_58 node _T_940 = asUInt(reset) node _T_941 = eq(_T_940, UInt<1>(0h0)) when _T_941 : node _T_942 = eq(sink_ok, UInt<1>(0h0)) when _T_942 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_59 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_59 node _T_943 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_944 = asUInt(reset) node _T_945 = eq(_T_944, UInt<1>(0h0)) when _T_945 : node _T_946 = eq(_T_943, UInt<1>(0h0)) when _T_946 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_60 assert(clock, _T_943, UInt<1>(0h1), "") : assert_60 node _T_947 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_948 = asUInt(reset) node _T_949 = eq(_T_948, UInt<1>(0h0)) when _T_949 : node _T_950 = eq(_T_947, UInt<1>(0h0)) when _T_950 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_61 assert(clock, _T_947, UInt<1>(0h1), "") : assert_61 node _T_951 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_952 = asUInt(reset) node _T_953 = eq(_T_952, UInt<1>(0h0)) when _T_953 : node _T_954 = eq(_T_951, UInt<1>(0h0)) when _T_954 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_62 assert(clock, _T_951, UInt<1>(0h1), "") : assert_62 node _T_955 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_956 = asUInt(reset) node _T_957 = eq(_T_956, UInt<1>(0h0)) when _T_957 : node _T_958 = eq(_T_955, UInt<1>(0h0)) when _T_958 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_63 assert(clock, _T_955, UInt<1>(0h1), "") : assert_63 node _T_959 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_960 = or(UInt<1>(0h0), _T_959) node _T_961 = asUInt(reset) node _T_962 = eq(_T_961, UInt<1>(0h0)) when _T_962 : node _T_963 = eq(_T_960, UInt<1>(0h0)) when _T_963 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel Grant is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_64 assert(clock, _T_960, UInt<1>(0h1), "") : assert_64 node _T_964 = eq(io.in.d.bits.opcode, UInt<3>(0h5)) when _T_964 : node _T_965 = asUInt(reset) node _T_966 = eq(_T_965, UInt<1>(0h0)) when _T_966 : node _T_967 = eq(source_ok_1, UInt<1>(0h0)) when _T_967 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_65 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_65 node _T_968 = asUInt(reset) node _T_969 = eq(_T_968, UInt<1>(0h0)) when _T_969 : node _T_970 = eq(sink_ok, UInt<1>(0h0)) when _T_970 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid sink ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_66 assert(clock, sink_ok, UInt<1>(0h1), "") : assert_66 node _T_971 = geq(io.in.d.bits.size, UInt<2>(0h3)) node _T_972 = asUInt(reset) node _T_973 = eq(_T_972, UInt<1>(0h0)) when _T_973 : node _T_974 = eq(_T_971, UInt<1>(0h0)) when _T_974 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData smaller than a beat (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_67 assert(clock, _T_971, UInt<1>(0h1), "") : assert_67 node _T_975 = leq(io.in.d.bits.param, UInt<2>(0h2)) node _T_976 = asUInt(reset) node _T_977 = eq(_T_976, UInt<1>(0h0)) when _T_977 : node _T_978 = eq(_T_975, UInt<1>(0h0)) when _T_978 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries invalid cap param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_68 assert(clock, _T_975, UInt<1>(0h1), "") : assert_68 node _T_979 = neq(io.in.d.bits.param, UInt<2>(0h2)) node _T_980 = asUInt(reset) node _T_981 = eq(_T_980, UInt<1>(0h0)) when _T_981 : node _T_982 = eq(_T_979, UInt<1>(0h0)) when _T_982 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData carries toN param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_69 assert(clock, _T_979, UInt<1>(0h1), "") : assert_69 node _T_983 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_984 = or(_T_983, io.in.d.bits.corrupt) node _T_985 = asUInt(reset) node _T_986 = eq(_T_985, UInt<1>(0h0)) when _T_986 : node _T_987 = eq(_T_984, UInt<1>(0h0)) when _T_987 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_70 assert(clock, _T_984, UInt<1>(0h1), "") : assert_70 node _T_988 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_989 = or(UInt<1>(0h0), _T_988) node _T_990 = asUInt(reset) node _T_991 = eq(_T_990, UInt<1>(0h0)) when _T_991 : node _T_992 = eq(_T_989, UInt<1>(0h0)) when _T_992 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel GrantData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_71 assert(clock, _T_989, UInt<1>(0h1), "") : assert_71 node _T_993 = eq(io.in.d.bits.opcode, UInt<1>(0h0)) when _T_993 : node _T_994 = asUInt(reset) node _T_995 = eq(_T_994, UInt<1>(0h0)) when _T_995 : node _T_996 = eq(source_ok_1, UInt<1>(0h0)) when _T_996 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_72 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_72 node _T_997 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_998 = asUInt(reset) node _T_999 = eq(_T_998, UInt<1>(0h0)) when _T_999 : node _T_1000 = eq(_T_997, UInt<1>(0h0)) when _T_1000 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_73 assert(clock, _T_997, UInt<1>(0h1), "") : assert_73 node _T_1001 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1002 = asUInt(reset) node _T_1003 = eq(_T_1002, UInt<1>(0h0)) when _T_1003 : node _T_1004 = eq(_T_1001, UInt<1>(0h0)) when _T_1004 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_74 assert(clock, _T_1001, UInt<1>(0h1), "") : assert_74 node _T_1005 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1006 = or(UInt<1>(0h0), _T_1005) node _T_1007 = asUInt(reset) node _T_1008 = eq(_T_1007, UInt<1>(0h0)) when _T_1008 : node _T_1009 = eq(_T_1006, UInt<1>(0h0)) when _T_1009 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_75 assert(clock, _T_1006, UInt<1>(0h1), "") : assert_75 node _T_1010 = eq(io.in.d.bits.opcode, UInt<1>(0h1)) when _T_1010 : node _T_1011 = asUInt(reset) node _T_1012 = eq(_T_1011, UInt<1>(0h0)) when _T_1012 : node _T_1013 = eq(source_ok_1, UInt<1>(0h0)) when _T_1013 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_76 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_76 node _T_1014 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1015 = asUInt(reset) node _T_1016 = eq(_T_1015, UInt<1>(0h0)) when _T_1016 : node _T_1017 = eq(_T_1014, UInt<1>(0h0)) when _T_1017 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_77 assert(clock, _T_1014, UInt<1>(0h1), "") : assert_77 node _T_1018 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1019 = or(_T_1018, io.in.d.bits.corrupt) node _T_1020 = asUInt(reset) node _T_1021 = eq(_T_1020, UInt<1>(0h0)) when _T_1021 : node _T_1022 = eq(_T_1019, UInt<1>(0h0)) when _T_1022 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied but not corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_78 assert(clock, _T_1019, UInt<1>(0h1), "") : assert_78 node _T_1023 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1024 = or(UInt<1>(0h0), _T_1023) node _T_1025 = asUInt(reset) node _T_1026 = eq(_T_1025, UInt<1>(0h0)) when _T_1026 : node _T_1027 = eq(_T_1024, UInt<1>(0h0)) when _T_1027 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel AccessAckData is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_79 assert(clock, _T_1024, UInt<1>(0h1), "") : assert_79 node _T_1028 = eq(io.in.d.bits.opcode, UInt<2>(0h2)) when _T_1028 : node _T_1029 = asUInt(reset) node _T_1030 = eq(_T_1029, UInt<1>(0h0)) when _T_1030 : node _T_1031 = eq(source_ok_1, UInt<1>(0h0)) when _T_1031 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_80 assert(clock, source_ok_1, UInt<1>(0h1), "") : assert_80 node _T_1032 = eq(io.in.d.bits.param, UInt<1>(0h0)) node _T_1033 = asUInt(reset) node _T_1034 = eq(_T_1033, UInt<1>(0h0)) when _T_1034 : node _T_1035 = eq(_T_1032, UInt<1>(0h0)) when _T_1035 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck carries invalid param (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_81 assert(clock, _T_1032, UInt<1>(0h1), "") : assert_81 node _T_1036 = eq(io.in.d.bits.corrupt, UInt<1>(0h0)) node _T_1037 = asUInt(reset) node _T_1038 = eq(_T_1037, UInt<1>(0h0)) when _T_1038 : node _T_1039 = eq(_T_1036, UInt<1>(0h0)) when _T_1039 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is corrupt (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_82 assert(clock, _T_1036, UInt<1>(0h1), "") : assert_82 node _T_1040 = eq(io.in.d.bits.denied, UInt<1>(0h0)) node _T_1041 = or(UInt<1>(0h0), _T_1040) node _T_1042 = asUInt(reset) node _T_1043 = eq(_T_1042, UInt<1>(0h0)) when _T_1043 : node _T_1044 = eq(_T_1041, UInt<1>(0h0)) when _T_1044 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel HintAck is denied (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_83 assert(clock, _T_1041, UInt<1>(0h1), "") : assert_83 wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_4.bits.corrupt, UInt<1>(0h0) connect _WIRE_4.bits.data, UInt<64>(0h0) connect _WIRE_4.bits.mask, UInt<8>(0h0) connect _WIRE_4.bits.address, UInt<21>(0h0) connect _WIRE_4.bits.source, UInt<7>(0h0) connect _WIRE_4.bits.size, UInt<3>(0h0) connect _WIRE_4.bits.param, UInt<2>(0h0) connect _WIRE_4.bits.opcode, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<7>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready node _T_1045 = eq(_WIRE_5.valid, UInt<1>(0h0)) node _T_1046 = asUInt(reset) node _T_1047 = eq(_T_1046, UInt<1>(0h0)) when _T_1047 : node _T_1048 = eq(_T_1045, UInt<1>(0h0)) when _T_1048 : printf(clock, UInt<1>(0h1), "Assertion failed: 'B' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_84 assert(clock, _T_1045, UInt<1>(0h1), "") : assert_84 wire _WIRE_6 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_6.bits.corrupt, UInt<1>(0h0) connect _WIRE_6.bits.data, UInt<64>(0h0) connect _WIRE_6.bits.address, UInt<21>(0h0) connect _WIRE_6.bits.source, UInt<7>(0h0) connect _WIRE_6.bits.size, UInt<3>(0h0) connect _WIRE_6.bits.param, UInt<3>(0h0) connect _WIRE_6.bits.opcode, UInt<3>(0h0) connect _WIRE_6.valid, UInt<1>(0h0) connect _WIRE_6.ready, UInt<1>(0h0) wire _WIRE_7 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_7.bits, _WIRE_6.bits connect _WIRE_7.valid, _WIRE_6.valid connect _WIRE_7.ready, _WIRE_6.ready node _T_1049 = eq(_WIRE_7.valid, UInt<1>(0h0)) node _T_1050 = asUInt(reset) node _T_1051 = eq(_T_1050, UInt<1>(0h0)) when _T_1051 : node _T_1052 = eq(_T_1049, UInt<1>(0h0)) when _T_1052 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_85 assert(clock, _T_1049, UInt<1>(0h1), "") : assert_85 wire _WIRE_8 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_8.bits.sink, UInt<1>(0h0) connect _WIRE_8.valid, UInt<1>(0h0) connect _WIRE_8.ready, UInt<1>(0h0) wire _WIRE_9 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_9.bits, _WIRE_8.bits connect _WIRE_9.valid, _WIRE_8.valid connect _WIRE_9.ready, _WIRE_8.ready node _T_1053 = eq(_WIRE_9.valid, UInt<1>(0h0)) node _T_1054 = asUInt(reset) node _T_1055 = eq(_T_1054, UInt<1>(0h0)) when _T_1055 : node _T_1056 = eq(_T_1053, UInt<1>(0h0)) when _T_1056 : printf(clock, UInt<1>(0h1), "Assertion failed: 'E' channel valid and not TL-C (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_86 assert(clock, _T_1053, UInt<1>(0h1), "") : assert_86 node _a_first_T = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_1 = bits(_a_first_beats1_decode_T, 5, 0) node _a_first_beats1_decode_T_2 = not(_a_first_beats1_decode_T_1) node a_first_beats1_decode = shr(_a_first_beats1_decode_T_2, 3) node _a_first_beats1_opdata_T = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata = eq(_a_first_beats1_opdata_T, UInt<1>(0h0)) node a_first_beats1 = mux(a_first_beats1_opdata, a_first_beats1_decode, UInt<1>(0h0)) regreset a_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T = sub(a_first_counter, UInt<1>(0h1)) node a_first_counter1 = tail(_a_first_counter1_T, 1) node a_first = eq(a_first_counter, UInt<1>(0h0)) node _a_first_last_T = eq(a_first_counter, UInt<1>(0h1)) node _a_first_last_T_1 = eq(a_first_beats1, UInt<1>(0h0)) node a_first_last = or(_a_first_last_T, _a_first_last_T_1) node a_first_done = and(a_first_last, _a_first_T) node _a_first_count_T = not(a_first_counter1) node a_first_count = and(a_first_beats1, _a_first_count_T) when _a_first_T : node _a_first_counter_T = mux(a_first, a_first_beats1, a_first_counter1) connect a_first_counter, _a_first_counter_T reg opcode : UInt, clock reg param : UInt, clock reg size : UInt, clock reg source : UInt, clock reg address : UInt, clock node _T_1057 = eq(a_first, UInt<1>(0h0)) node _T_1058 = and(io.in.a.valid, _T_1057) when _T_1058 : node _T_1059 = eq(io.in.a.bits.opcode, opcode) node _T_1060 = asUInt(reset) node _T_1061 = eq(_T_1060, UInt<1>(0h0)) when _T_1061 : node _T_1062 = eq(_T_1059, UInt<1>(0h0)) when _T_1062 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_87 assert(clock, _T_1059, UInt<1>(0h1), "") : assert_87 node _T_1063 = eq(io.in.a.bits.param, param) node _T_1064 = asUInt(reset) node _T_1065 = eq(_T_1064, UInt<1>(0h0)) when _T_1065 : node _T_1066 = eq(_T_1063, UInt<1>(0h0)) when _T_1066 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_88 assert(clock, _T_1063, UInt<1>(0h1), "") : assert_88 node _T_1067 = eq(io.in.a.bits.size, size) node _T_1068 = asUInt(reset) node _T_1069 = eq(_T_1068, UInt<1>(0h0)) when _T_1069 : node _T_1070 = eq(_T_1067, UInt<1>(0h0)) when _T_1070 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_89 assert(clock, _T_1067, UInt<1>(0h1), "") : assert_89 node _T_1071 = eq(io.in.a.bits.source, source) node _T_1072 = asUInt(reset) node _T_1073 = eq(_T_1072, UInt<1>(0h0)) when _T_1073 : node _T_1074 = eq(_T_1071, UInt<1>(0h0)) when _T_1074 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_90 assert(clock, _T_1071, UInt<1>(0h1), "") : assert_90 node _T_1075 = eq(io.in.a.bits.address, address) node _T_1076 = asUInt(reset) node _T_1077 = eq(_T_1076, UInt<1>(0h0)) when _T_1077 : node _T_1078 = eq(_T_1075, UInt<1>(0h0)) when _T_1078 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel address changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_91 assert(clock, _T_1075, UInt<1>(0h1), "") : assert_91 node _T_1079 = and(io.in.a.ready, io.in.a.valid) node _T_1080 = and(_T_1079, a_first) when _T_1080 : connect opcode, io.in.a.bits.opcode connect param, io.in.a.bits.param connect size, io.in.a.bits.size connect source, io.in.a.bits.source connect address, io.in.a.bits.address node _d_first_T = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_1 = bits(_d_first_beats1_decode_T, 5, 0) node _d_first_beats1_decode_T_2 = not(_d_first_beats1_decode_T_1) node d_first_beats1_decode = shr(_d_first_beats1_decode_T_2, 3) node d_first_beats1_opdata = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1 = mux(d_first_beats1_opdata, d_first_beats1_decode, UInt<1>(0h0)) regreset d_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T = sub(d_first_counter, UInt<1>(0h1)) node d_first_counter1 = tail(_d_first_counter1_T, 1) node d_first = eq(d_first_counter, UInt<1>(0h0)) node _d_first_last_T = eq(d_first_counter, UInt<1>(0h1)) node _d_first_last_T_1 = eq(d_first_beats1, UInt<1>(0h0)) node d_first_last = or(_d_first_last_T, _d_first_last_T_1) node d_first_done = and(d_first_last, _d_first_T) node _d_first_count_T = not(d_first_counter1) node d_first_count = and(d_first_beats1, _d_first_count_T) when _d_first_T : node _d_first_counter_T = mux(d_first, d_first_beats1, d_first_counter1) connect d_first_counter, _d_first_counter_T reg opcode_1 : UInt, clock reg param_1 : UInt, clock reg size_1 : UInt, clock reg source_1 : UInt, clock reg sink : UInt, clock reg denied : UInt<1>, clock node _T_1081 = eq(d_first, UInt<1>(0h0)) node _T_1082 = and(io.in.d.valid, _T_1081) when _T_1082 : node _T_1083 = eq(io.in.d.bits.opcode, opcode_1) node _T_1084 = asUInt(reset) node _T_1085 = eq(_T_1084, UInt<1>(0h0)) when _T_1085 : node _T_1086 = eq(_T_1083, UInt<1>(0h0)) when _T_1086 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel opcode changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_92 assert(clock, _T_1083, UInt<1>(0h1), "") : assert_92 node _T_1087 = eq(io.in.d.bits.param, param_1) node _T_1088 = asUInt(reset) node _T_1089 = eq(_T_1088, UInt<1>(0h0)) when _T_1089 : node _T_1090 = eq(_T_1087, UInt<1>(0h0)) when _T_1090 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel param changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_93 assert(clock, _T_1087, UInt<1>(0h1), "") : assert_93 node _T_1091 = eq(io.in.d.bits.size, size_1) node _T_1092 = asUInt(reset) node _T_1093 = eq(_T_1092, UInt<1>(0h0)) when _T_1093 : node _T_1094 = eq(_T_1091, UInt<1>(0h0)) when _T_1094 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel size changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_94 assert(clock, _T_1091, UInt<1>(0h1), "") : assert_94 node _T_1095 = eq(io.in.d.bits.source, source_1) node _T_1096 = asUInt(reset) node _T_1097 = eq(_T_1096, UInt<1>(0h0)) when _T_1097 : node _T_1098 = eq(_T_1095, UInt<1>(0h0)) when _T_1098 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel source changed within multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_95 assert(clock, _T_1095, UInt<1>(0h1), "") : assert_95 node _T_1099 = eq(io.in.d.bits.sink, sink) node _T_1100 = asUInt(reset) node _T_1101 = eq(_T_1100, UInt<1>(0h0)) when _T_1101 : node _T_1102 = eq(_T_1099, UInt<1>(0h0)) when _T_1102 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel sink changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_96 assert(clock, _T_1099, UInt<1>(0h1), "") : assert_96 node _T_1103 = eq(io.in.d.bits.denied, denied) node _T_1104 = asUInt(reset) node _T_1105 = eq(_T_1104, UInt<1>(0h0)) when _T_1105 : node _T_1106 = eq(_T_1103, UInt<1>(0h0)) when _T_1106 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel denied changed with multibeat operation (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_97 assert(clock, _T_1103, UInt<1>(0h1), "") : assert_97 node _T_1107 = and(io.in.d.ready, io.in.d.valid) node _T_1108 = and(_T_1107, d_first) when _T_1108 : connect opcode_1, io.in.d.bits.opcode connect param_1, io.in.d.bits.param connect size_1, io.in.d.bits.size connect source_1, io.in.d.bits.source connect sink, io.in.d.bits.sink connect denied, io.in.d.bits.denied regreset inflight : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes : UInt<260>, clock, reset, UInt<260>(0h0) node _a_first_T_1 = and(io.in.a.ready, io.in.a.valid) node _a_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.a.bits.size) node _a_first_beats1_decode_T_4 = bits(_a_first_beats1_decode_T_3, 5, 0) node _a_first_beats1_decode_T_5 = not(_a_first_beats1_decode_T_4) node a_first_beats1_decode_1 = shr(_a_first_beats1_decode_T_5, 3) node _a_first_beats1_opdata_T_1 = bits(io.in.a.bits.opcode, 2, 2) node a_first_beats1_opdata_1 = eq(_a_first_beats1_opdata_T_1, UInt<1>(0h0)) node a_first_beats1_1 = mux(a_first_beats1_opdata_1, a_first_beats1_decode_1, UInt<1>(0h0)) regreset a_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _a_first_counter1_T_1 = sub(a_first_counter_1, UInt<1>(0h1)) node a_first_counter1_1 = tail(_a_first_counter1_T_1, 1) node a_first_1 = eq(a_first_counter_1, UInt<1>(0h0)) node _a_first_last_T_2 = eq(a_first_counter_1, UInt<1>(0h1)) node _a_first_last_T_3 = eq(a_first_beats1_1, UInt<1>(0h0)) node a_first_last_1 = or(_a_first_last_T_2, _a_first_last_T_3) node a_first_done_1 = and(a_first_last_1, _a_first_T_1) node _a_first_count_T_1 = not(a_first_counter1_1) node a_first_count_1 = and(a_first_beats1_1, _a_first_count_T_1) when _a_first_T_1 : node _a_first_counter_T_1 = mux(a_first_1, a_first_beats1_1, a_first_counter1_1) connect a_first_counter_1, _a_first_counter_T_1 node _d_first_T_1 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_3 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_4 = bits(_d_first_beats1_decode_T_3, 5, 0) node _d_first_beats1_decode_T_5 = not(_d_first_beats1_decode_T_4) node d_first_beats1_decode_1 = shr(_d_first_beats1_decode_T_5, 3) node d_first_beats1_opdata_1 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_1 = mux(d_first_beats1_opdata_1, d_first_beats1_decode_1, UInt<1>(0h0)) regreset d_first_counter_1 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_1 = sub(d_first_counter_1, UInt<1>(0h1)) node d_first_counter1_1 = tail(_d_first_counter1_T_1, 1) node d_first_1 = eq(d_first_counter_1, UInt<1>(0h0)) node _d_first_last_T_2 = eq(d_first_counter_1, UInt<1>(0h1)) node _d_first_last_T_3 = eq(d_first_beats1_1, UInt<1>(0h0)) node d_first_last_1 = or(_d_first_last_T_2, _d_first_last_T_3) node d_first_done_1 = and(d_first_last_1, _d_first_T_1) node _d_first_count_T_1 = not(d_first_counter1_1) node d_first_count_1 = and(d_first_beats1_1, _d_first_count_T_1) when _d_first_T_1 : node _d_first_counter_T_1 = mux(d_first_1, d_first_beats1_1, d_first_counter1_1) connect d_first_counter_1, _d_first_counter_T_1 wire a_set : UInt<65> connect a_set, UInt<65>(0h0) wire a_set_wo_ready : UInt<65> connect a_set_wo_ready, UInt<65>(0h0) wire a_opcodes_set : UInt<260> connect a_opcodes_set, UInt<260>(0h0) wire a_sizes_set : UInt<260> connect a_sizes_set, UInt<260>(0h0) wire a_opcode_lookup : UInt<3> connect a_opcode_lookup, UInt<3>(0h0) node _a_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_opcode_lookup_T_1 = dshr(inflight_opcodes, _a_opcode_lookup_T) node _a_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _a_opcode_lookup_T_2) node _a_opcode_lookup_T_4 = sub(_a_opcode_lookup_T_3, UInt<1>(0h1)) node _a_opcode_lookup_T_5 = tail(_a_opcode_lookup_T_4, 1) node _a_opcode_lookup_T_6 = and(_a_opcode_lookup_T_1, _a_opcode_lookup_T_5) node _a_opcode_lookup_T_7 = dshr(_a_opcode_lookup_T_6, UInt<1>(0h1)) connect a_opcode_lookup, _a_opcode_lookup_T_7 wire a_size_lookup : UInt<4> connect a_size_lookup, UInt<4>(0h0) node _a_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _a_size_lookup_T_1 = dshr(inflight_sizes, _a_size_lookup_T) node _a_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _a_size_lookup_T_3 = dshl(UInt<1>(0h1), _a_size_lookup_T_2) node _a_size_lookup_T_4 = sub(_a_size_lookup_T_3, UInt<1>(0h1)) node _a_size_lookup_T_5 = tail(_a_size_lookup_T_4, 1) node _a_size_lookup_T_6 = and(_a_size_lookup_T_1, _a_size_lookup_T_5) node _a_size_lookup_T_7 = dshr(_a_size_lookup_T_6, UInt<1>(0h1)) connect a_size_lookup, _a_size_lookup_T_7 wire responseMap : UInt<3>[8] connect responseMap[0], UInt<1>(0h0) connect responseMap[1], UInt<1>(0h0) connect responseMap[2], UInt<1>(0h1) connect responseMap[3], UInt<1>(0h1) connect responseMap[4], UInt<1>(0h1) connect responseMap[5], UInt<2>(0h2) connect responseMap[6], UInt<3>(0h4) connect responseMap[7], UInt<3>(0h4) wire responseMapSecondOption : UInt<3>[8] connect responseMapSecondOption[0], UInt<1>(0h0) connect responseMapSecondOption[1], UInt<1>(0h0) connect responseMapSecondOption[2], UInt<1>(0h1) connect responseMapSecondOption[3], UInt<1>(0h1) connect responseMapSecondOption[4], UInt<1>(0h1) connect responseMapSecondOption[5], UInt<2>(0h2) connect responseMapSecondOption[6], UInt<3>(0h5) connect responseMapSecondOption[7], UInt<3>(0h4) wire a_opcodes_set_interm : UInt<4> connect a_opcodes_set_interm, UInt<4>(0h0) wire a_sizes_set_interm : UInt<4> connect a_sizes_set_interm, UInt<4>(0h0) node _T_1109 = and(io.in.a.valid, a_first_1) node _T_1110 = and(_T_1109, UInt<1>(0h1)) when _T_1110 : node _a_set_wo_ready_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set_wo_ready, _a_set_wo_ready_T node _T_1111 = and(io.in.a.ready, io.in.a.valid) node _T_1112 = and(_T_1111, a_first_1) node _T_1113 = and(_T_1112, UInt<1>(0h1)) when _T_1113 : node _a_set_T = dshl(UInt<1>(0h1), io.in.a.bits.source) connect a_set, _a_set_T node _a_opcodes_set_interm_T = dshl(io.in.a.bits.opcode, UInt<1>(0h1)) node _a_opcodes_set_interm_T_1 = or(_a_opcodes_set_interm_T, UInt<1>(0h1)) connect a_opcodes_set_interm, _a_opcodes_set_interm_T_1 node _a_sizes_set_interm_T = dshl(io.in.a.bits.size, UInt<1>(0h1)) node _a_sizes_set_interm_T_1 = or(_a_sizes_set_interm_T, UInt<1>(0h1)) connect a_sizes_set_interm, _a_sizes_set_interm_T_1 node _a_opcodes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_opcodes_set_T_1 = dshl(a_opcodes_set_interm, _a_opcodes_set_T) connect a_opcodes_set, _a_opcodes_set_T_1 node _a_sizes_set_T = dshl(io.in.a.bits.source, UInt<2>(0h2)) node _a_sizes_set_T_1 = dshl(a_sizes_set_interm, _a_sizes_set_T) connect a_sizes_set, _a_sizes_set_T_1 node _T_1114 = dshr(inflight, io.in.a.bits.source) node _T_1115 = bits(_T_1114, 0, 0) node _T_1116 = eq(_T_1115, UInt<1>(0h0)) node _T_1117 = asUInt(reset) node _T_1118 = eq(_T_1117, UInt<1>(0h0)) when _T_1118 : node _T_1119 = eq(_T_1116, UInt<1>(0h0)) when _T_1119 : printf(clock, UInt<1>(0h1), "Assertion failed: 'A' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_98 assert(clock, _T_1116, UInt<1>(0h1), "") : assert_98 wire d_clr : UInt<65> connect d_clr, UInt<65>(0h0) wire d_clr_wo_ready : UInt<65> connect d_clr_wo_ready, UInt<65>(0h0) wire d_opcodes_clr : UInt<260> connect d_opcodes_clr, UInt<260>(0h0) wire d_sizes_clr : UInt<260> connect d_sizes_clr, UInt<260>(0h0) node d_release_ack = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1120 = and(io.in.d.valid, d_first_1) node _T_1121 = and(_T_1120, UInt<1>(0h1)) node _T_1122 = eq(d_release_ack, UInt<1>(0h0)) node _T_1123 = and(_T_1121, _T_1122) when _T_1123 : node _d_clr_wo_ready_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready, _d_clr_wo_ready_T node _T_1124 = and(io.in.d.ready, io.in.d.valid) node _T_1125 = and(_T_1124, d_first_1) node _T_1126 = and(_T_1125, UInt<1>(0h1)) node _T_1127 = eq(d_release_ack, UInt<1>(0h0)) node _T_1128 = and(_T_1126, _T_1127) when _T_1128 : node _d_clr_T = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr, _d_clr_T node _d_opcodes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_1 = dshl(UInt<1>(0h1), _d_opcodes_clr_T) node _d_opcodes_clr_T_2 = sub(_d_opcodes_clr_T_1, UInt<1>(0h1)) node _d_opcodes_clr_T_3 = tail(_d_opcodes_clr_T_2, 1) node _d_opcodes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_5 = dshl(_d_opcodes_clr_T_3, _d_opcodes_clr_T_4) connect d_opcodes_clr, _d_opcodes_clr_T_5 node _d_sizes_clr_T = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_1 = dshl(UInt<1>(0h1), _d_sizes_clr_T) node _d_sizes_clr_T_2 = sub(_d_sizes_clr_T_1, UInt<1>(0h1)) node _d_sizes_clr_T_3 = tail(_d_sizes_clr_T_2, 1) node _d_sizes_clr_T_4 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_5 = dshl(_d_sizes_clr_T_3, _d_sizes_clr_T_4) connect d_sizes_clr, _d_sizes_clr_T_5 node _T_1129 = and(io.in.d.valid, d_first_1) node _T_1130 = and(_T_1129, UInt<1>(0h1)) node _T_1131 = eq(d_release_ack, UInt<1>(0h0)) node _T_1132 = and(_T_1130, _T_1131) when _T_1132 : node _same_cycle_resp_T = and(io.in.a.valid, a_first_1) node _same_cycle_resp_T_1 = and(_same_cycle_resp_T, UInt<1>(0h1)) node _same_cycle_resp_T_2 = eq(io.in.a.bits.source, io.in.d.bits.source) node same_cycle_resp = and(_same_cycle_resp_T_1, _same_cycle_resp_T_2) node _T_1133 = dshr(inflight, io.in.d.bits.source) node _T_1134 = bits(_T_1133, 0, 0) node _T_1135 = or(_T_1134, same_cycle_resp) node _T_1136 = asUInt(reset) node _T_1137 = eq(_T_1136, UInt<1>(0h0)) when _T_1137 : node _T_1138 = eq(_T_1135, UInt<1>(0h0)) when _T_1138 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_99 assert(clock, _T_1135, UInt<1>(0h1), "") : assert_99 when same_cycle_resp : node _T_1139 = eq(io.in.d.bits.opcode, responseMap[io.in.a.bits.opcode]) node _T_1140 = eq(io.in.d.bits.opcode, responseMapSecondOption[io.in.a.bits.opcode]) node _T_1141 = or(_T_1139, _T_1140) node _T_1142 = asUInt(reset) node _T_1143 = eq(_T_1142, UInt<1>(0h0)) when _T_1143 : node _T_1144 = eq(_T_1141, UInt<1>(0h0)) when _T_1144 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_100 assert(clock, _T_1141, UInt<1>(0h1), "") : assert_100 node _T_1145 = eq(io.in.a.bits.size, io.in.d.bits.size) node _T_1146 = asUInt(reset) node _T_1147 = eq(_T_1146, UInt<1>(0h0)) when _T_1147 : node _T_1148 = eq(_T_1145, UInt<1>(0h0)) when _T_1148 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_101 assert(clock, _T_1145, UInt<1>(0h1), "") : assert_101 else : node _T_1149 = eq(io.in.d.bits.opcode, responseMap[a_opcode_lookup]) node _T_1150 = eq(io.in.d.bits.opcode, responseMapSecondOption[a_opcode_lookup]) node _T_1151 = or(_T_1149, _T_1150) node _T_1152 = asUInt(reset) node _T_1153 = eq(_T_1152, UInt<1>(0h0)) when _T_1153 : node _T_1154 = eq(_T_1151, UInt<1>(0h0)) when _T_1154 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper opcode response (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_102 assert(clock, _T_1151, UInt<1>(0h1), "") : assert_102 node _T_1155 = eq(io.in.d.bits.size, a_size_lookup) node _T_1156 = asUInt(reset) node _T_1157 = eq(_T_1156, UInt<1>(0h0)) when _T_1157 : node _T_1158 = eq(_T_1155, UInt<1>(0h0)) when _T_1158 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_103 assert(clock, _T_1155, UInt<1>(0h1), "") : assert_103 node _T_1159 = and(io.in.d.valid, d_first_1) node _T_1160 = and(_T_1159, a_first_1) node _T_1161 = and(_T_1160, io.in.a.valid) node _T_1162 = eq(io.in.a.bits.source, io.in.d.bits.source) node _T_1163 = and(_T_1161, _T_1162) node _T_1164 = eq(d_release_ack, UInt<1>(0h0)) node _T_1165 = and(_T_1163, _T_1164) when _T_1165 : node _T_1166 = eq(io.in.d.ready, UInt<1>(0h0)) node _T_1167 = or(_T_1166, io.in.a.ready) node _T_1168 = asUInt(reset) node _T_1169 = eq(_T_1168, UInt<1>(0h0)) when _T_1169 : node _T_1170 = eq(_T_1167, UInt<1>(0h0)) when _T_1170 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_104 assert(clock, _T_1167, UInt<1>(0h1), "") : assert_104 node _inflight_T = or(inflight, a_set) node _inflight_T_1 = not(d_clr) node _inflight_T_2 = and(_inflight_T, _inflight_T_1) connect inflight, _inflight_T_2 node _inflight_opcodes_T = or(inflight_opcodes, a_opcodes_set) node _inflight_opcodes_T_1 = not(d_opcodes_clr) node _inflight_opcodes_T_2 = and(_inflight_opcodes_T, _inflight_opcodes_T_1) connect inflight_opcodes, _inflight_opcodes_T_2 node _inflight_sizes_T = or(inflight_sizes, a_sizes_set) node _inflight_sizes_T_1 = not(d_sizes_clr) node _inflight_sizes_T_2 = and(_inflight_sizes_T, _inflight_sizes_T_1) connect inflight_sizes, _inflight_sizes_T_2 regreset watchdog : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader of plusarg_reader_211 node _T_1171 = orr(inflight) node _T_1172 = eq(_T_1171, UInt<1>(0h0)) node _T_1173 = eq(plusarg_reader.out, UInt<1>(0h0)) node _T_1174 = or(_T_1172, _T_1173) node _T_1175 = lt(watchdog, plusarg_reader.out) node _T_1176 = or(_T_1174, _T_1175) node _T_1177 = asUInt(reset) node _T_1178 = eq(_T_1177, UInt<1>(0h0)) when _T_1178 : node _T_1179 = eq(_T_1176, UInt<1>(0h0)) when _T_1179 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_105 assert(clock, _T_1176, UInt<1>(0h1), "") : assert_105 node _watchdog_T = add(watchdog, UInt<1>(0h1)) node _watchdog_T_1 = tail(_watchdog_T, 1) connect watchdog, _watchdog_T_1 node _T_1180 = and(io.in.a.ready, io.in.a.valid) node _T_1181 = and(io.in.d.ready, io.in.d.valid) node _T_1182 = or(_T_1180, _T_1181) when _T_1182 : connect watchdog, UInt<1>(0h0) regreset inflight_1 : UInt<65>, clock, reset, UInt<65>(0h0) regreset inflight_opcodes_1 : UInt<260>, clock, reset, UInt<260>(0h0) regreset inflight_sizes_1 : UInt<260>, clock, reset, UInt<260>(0h0) wire _c_first_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE.bits.data, UInt<64>(0h0) connect _c_first_WIRE.bits.address, UInt<21>(0h0) connect _c_first_WIRE.bits.source, UInt<7>(0h0) connect _c_first_WIRE.bits.size, UInt<3>(0h0) connect _c_first_WIRE.bits.param, UInt<3>(0h0) connect _c_first_WIRE.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE.valid, UInt<1>(0h0) connect _c_first_WIRE.ready, UInt<1>(0h0) wire _c_first_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_1.bits, _c_first_WIRE.bits connect _c_first_WIRE_1.valid, _c_first_WIRE.valid connect _c_first_WIRE_1.ready, _c_first_WIRE.ready wire _c_first_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_first_WIRE_2.bits.data, UInt<64>(0h0) connect _c_first_WIRE_2.bits.address, UInt<21>(0h0) connect _c_first_WIRE_2.bits.source, UInt<7>(0h0) connect _c_first_WIRE_2.bits.size, UInt<3>(0h0) connect _c_first_WIRE_2.bits.param, UInt<3>(0h0) connect _c_first_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_first_WIRE_2.valid, UInt<1>(0h0) connect _c_first_WIRE_2.ready, UInt<1>(0h0) wire _c_first_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_first_WIRE_3.bits, _c_first_WIRE_2.bits connect _c_first_WIRE_3.valid, _c_first_WIRE_2.valid connect _c_first_WIRE_3.ready, _c_first_WIRE_2.ready node _c_first_T = and(_c_first_WIRE_3.ready, _c_first_WIRE_3.valid) node _c_first_beats1_decode_T = dshl(UInt<6>(0h3f), _c_first_WIRE_1.bits.size) node _c_first_beats1_decode_T_1 = bits(_c_first_beats1_decode_T, 5, 0) node _c_first_beats1_decode_T_2 = not(_c_first_beats1_decode_T_1) node c_first_beats1_decode = shr(_c_first_beats1_decode_T_2, 3) node c_first_beats1_opdata = bits(_c_first_WIRE_1.bits.opcode, 0, 0) node c_first_beats1 = mux(c_first_beats1_opdata, c_first_beats1_decode, UInt<1>(0h0)) regreset c_first_counter : UInt<3>, clock, reset, UInt<3>(0h0) node _c_first_counter1_T = sub(c_first_counter, UInt<1>(0h1)) node c_first_counter1 = tail(_c_first_counter1_T, 1) node c_first = eq(c_first_counter, UInt<1>(0h0)) node _c_first_last_T = eq(c_first_counter, UInt<1>(0h1)) node _c_first_last_T_1 = eq(c_first_beats1, UInt<1>(0h0)) node c_first_last = or(_c_first_last_T, _c_first_last_T_1) node c_first_done = and(c_first_last, _c_first_T) node _c_first_count_T = not(c_first_counter1) node c_first_count = and(c_first_beats1, _c_first_count_T) when _c_first_T : node _c_first_counter_T = mux(c_first, c_first_beats1, c_first_counter1) connect c_first_counter, _c_first_counter_T node _d_first_T_2 = and(io.in.d.ready, io.in.d.valid) node _d_first_beats1_decode_T_6 = dshl(UInt<6>(0h3f), io.in.d.bits.size) node _d_first_beats1_decode_T_7 = bits(_d_first_beats1_decode_T_6, 5, 0) node _d_first_beats1_decode_T_8 = not(_d_first_beats1_decode_T_7) node d_first_beats1_decode_2 = shr(_d_first_beats1_decode_T_8, 3) node d_first_beats1_opdata_2 = bits(io.in.d.bits.opcode, 0, 0) node d_first_beats1_2 = mux(d_first_beats1_opdata_2, d_first_beats1_decode_2, UInt<1>(0h0)) regreset d_first_counter_2 : UInt<3>, clock, reset, UInt<3>(0h0) node _d_first_counter1_T_2 = sub(d_first_counter_2, UInt<1>(0h1)) node d_first_counter1_2 = tail(_d_first_counter1_T_2, 1) node d_first_2 = eq(d_first_counter_2, UInt<1>(0h0)) node _d_first_last_T_4 = eq(d_first_counter_2, UInt<1>(0h1)) node _d_first_last_T_5 = eq(d_first_beats1_2, UInt<1>(0h0)) node d_first_last_2 = or(_d_first_last_T_4, _d_first_last_T_5) node d_first_done_2 = and(d_first_last_2, _d_first_T_2) node _d_first_count_T_2 = not(d_first_counter1_2) node d_first_count_2 = and(d_first_beats1_2, _d_first_count_T_2) when _d_first_T_2 : node _d_first_counter_T_2 = mux(d_first_2, d_first_beats1_2, d_first_counter1_2) connect d_first_counter_2, _d_first_counter_T_2 wire c_set : UInt<65> connect c_set, UInt<65>(0h0) wire c_set_wo_ready : UInt<65> connect c_set_wo_ready, UInt<65>(0h0) wire c_opcodes_set : UInt<260> connect c_opcodes_set, UInt<260>(0h0) wire c_sizes_set : UInt<260> connect c_sizes_set, UInt<260>(0h0) wire c_opcode_lookup : UInt<4> connect c_opcode_lookup, UInt<4>(0h0) wire c_size_lookup : UInt<4> connect c_size_lookup, UInt<4>(0h0) node _c_opcode_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_opcode_lookup_T_1 = dshr(inflight_opcodes_1, _c_opcode_lookup_T) node _c_opcode_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_opcode_lookup_T_3 = dshl(UInt<1>(0h1), _c_opcode_lookup_T_2) node _c_opcode_lookup_T_4 = sub(_c_opcode_lookup_T_3, UInt<1>(0h1)) node _c_opcode_lookup_T_5 = tail(_c_opcode_lookup_T_4, 1) node _c_opcode_lookup_T_6 = and(_c_opcode_lookup_T_1, _c_opcode_lookup_T_5) node _c_opcode_lookup_T_7 = dshr(_c_opcode_lookup_T_6, UInt<1>(0h1)) connect c_opcode_lookup, _c_opcode_lookup_T_7 node _c_size_lookup_T = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _c_size_lookup_T_1 = dshr(inflight_sizes_1, _c_size_lookup_T) node _c_size_lookup_T_2 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _c_size_lookup_T_3 = dshl(UInt<1>(0h1), _c_size_lookup_T_2) node _c_size_lookup_T_4 = sub(_c_size_lookup_T_3, UInt<1>(0h1)) node _c_size_lookup_T_5 = tail(_c_size_lookup_T_4, 1) node _c_size_lookup_T_6 = and(_c_size_lookup_T_1, _c_size_lookup_T_5) node _c_size_lookup_T_7 = dshr(_c_size_lookup_T_6, UInt<1>(0h1)) connect c_size_lookup, _c_size_lookup_T_7 wire c_opcodes_set_interm : UInt<4> connect c_opcodes_set_interm, UInt<4>(0h0) wire c_sizes_set_interm : UInt<4> connect c_sizes_set_interm, UInt<4>(0h0) wire _WIRE_10 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_10.bits.corrupt, UInt<1>(0h0) connect _WIRE_10.bits.data, UInt<64>(0h0) connect _WIRE_10.bits.address, UInt<21>(0h0) connect _WIRE_10.bits.source, UInt<7>(0h0) connect _WIRE_10.bits.size, UInt<3>(0h0) connect _WIRE_10.bits.param, UInt<3>(0h0) connect _WIRE_10.bits.opcode, UInt<3>(0h0) connect _WIRE_10.valid, UInt<1>(0h0) connect _WIRE_10.ready, UInt<1>(0h0) wire _WIRE_11 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_11.bits, _WIRE_10.bits connect _WIRE_11.valid, _WIRE_10.valid connect _WIRE_11.ready, _WIRE_10.ready node _T_1183 = and(_WIRE_11.valid, c_first) wire _WIRE_12 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_12.bits.corrupt, UInt<1>(0h0) connect _WIRE_12.bits.data, UInt<64>(0h0) connect _WIRE_12.bits.address, UInt<21>(0h0) connect _WIRE_12.bits.source, UInt<7>(0h0) connect _WIRE_12.bits.size, UInt<3>(0h0) connect _WIRE_12.bits.param, UInt<3>(0h0) connect _WIRE_12.bits.opcode, UInt<3>(0h0) connect _WIRE_12.valid, UInt<1>(0h0) connect _WIRE_12.ready, UInt<1>(0h0) wire _WIRE_13 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_13.bits, _WIRE_12.bits connect _WIRE_13.valid, _WIRE_12.valid connect _WIRE_13.ready, _WIRE_12.ready node _T_1184 = bits(_WIRE_13.bits.opcode, 2, 2) node _T_1185 = bits(_WIRE_13.bits.opcode, 1, 1) node _T_1186 = and(_T_1184, _T_1185) node _T_1187 = and(_T_1183, _T_1186) when _T_1187 : wire _c_set_wo_ready_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.bits.data, UInt<64>(0h0) connect _c_set_wo_ready_WIRE.bits.address, UInt<21>(0h0) connect _c_set_wo_ready_WIRE.bits.source, UInt<7>(0h0) connect _c_set_wo_ready_WIRE.bits.size, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.param, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_wo_ready_WIRE.valid, UInt<1>(0h0) connect _c_set_wo_ready_WIRE.ready, UInt<1>(0h0) wire _c_set_wo_ready_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_wo_ready_WIRE_1.bits, _c_set_wo_ready_WIRE.bits connect _c_set_wo_ready_WIRE_1.valid, _c_set_wo_ready_WIRE.valid connect _c_set_wo_ready_WIRE_1.ready, _c_set_wo_ready_WIRE.ready node _c_set_wo_ready_T = dshl(UInt<1>(0h1), _c_set_wo_ready_WIRE_1.bits.source) connect c_set_wo_ready, _c_set_wo_ready_T wire _WIRE_14 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_14.bits.corrupt, UInt<1>(0h0) connect _WIRE_14.bits.data, UInt<64>(0h0) connect _WIRE_14.bits.address, UInt<21>(0h0) connect _WIRE_14.bits.source, UInt<7>(0h0) connect _WIRE_14.bits.size, UInt<3>(0h0) connect _WIRE_14.bits.param, UInt<3>(0h0) connect _WIRE_14.bits.opcode, UInt<3>(0h0) connect _WIRE_14.valid, UInt<1>(0h0) connect _WIRE_14.ready, UInt<1>(0h0) wire _WIRE_15 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_15.bits, _WIRE_14.bits connect _WIRE_15.valid, _WIRE_14.valid connect _WIRE_15.ready, _WIRE_14.ready node _T_1188 = and(_WIRE_15.ready, _WIRE_15.valid) node _T_1189 = and(_T_1188, c_first) wire _WIRE_16 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_16.bits.corrupt, UInt<1>(0h0) connect _WIRE_16.bits.data, UInt<64>(0h0) connect _WIRE_16.bits.address, UInt<21>(0h0) connect _WIRE_16.bits.source, UInt<7>(0h0) connect _WIRE_16.bits.size, UInt<3>(0h0) connect _WIRE_16.bits.param, UInt<3>(0h0) connect _WIRE_16.bits.opcode, UInt<3>(0h0) connect _WIRE_16.valid, UInt<1>(0h0) connect _WIRE_16.ready, UInt<1>(0h0) wire _WIRE_17 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_17.bits, _WIRE_16.bits connect _WIRE_17.valid, _WIRE_16.valid connect _WIRE_17.ready, _WIRE_16.ready node _T_1190 = bits(_WIRE_17.bits.opcode, 2, 2) node _T_1191 = bits(_WIRE_17.bits.opcode, 1, 1) node _T_1192 = and(_T_1190, _T_1191) node _T_1193 = and(_T_1189, _T_1192) when _T_1193 : wire _c_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_set_WIRE.bits.data, UInt<64>(0h0) connect _c_set_WIRE.bits.address, UInt<21>(0h0) connect _c_set_WIRE.bits.source, UInt<7>(0h0) connect _c_set_WIRE.bits.size, UInt<3>(0h0) connect _c_set_WIRE.bits.param, UInt<3>(0h0) connect _c_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_set_WIRE.valid, UInt<1>(0h0) connect _c_set_WIRE.ready, UInt<1>(0h0) wire _c_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_set_WIRE_1.bits, _c_set_WIRE.bits connect _c_set_WIRE_1.valid, _c_set_WIRE.valid connect _c_set_WIRE_1.ready, _c_set_WIRE.ready node _c_set_T = dshl(UInt<1>(0h1), _c_set_WIRE_1.bits.source) connect c_set, _c_set_T wire _c_opcodes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_interm_WIRE_1.bits, _c_opcodes_set_interm_WIRE.bits connect _c_opcodes_set_interm_WIRE_1.valid, _c_opcodes_set_interm_WIRE.valid connect _c_opcodes_set_interm_WIRE_1.ready, _c_opcodes_set_interm_WIRE.ready node _c_opcodes_set_interm_T = dshl(_c_opcodes_set_interm_WIRE_1.bits.opcode, UInt<1>(0h1)) node _c_opcodes_set_interm_T_1 = or(_c_opcodes_set_interm_T, UInt<1>(0h1)) connect c_opcodes_set_interm, _c_opcodes_set_interm_T_1 wire _c_sizes_set_interm_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_interm_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_interm_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_interm_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_interm_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_interm_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_interm_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_interm_WIRE_1.bits, _c_sizes_set_interm_WIRE.bits connect _c_sizes_set_interm_WIRE_1.valid, _c_sizes_set_interm_WIRE.valid connect _c_sizes_set_interm_WIRE_1.ready, _c_sizes_set_interm_WIRE.ready node _c_sizes_set_interm_T = dshl(_c_sizes_set_interm_WIRE_1.bits.size, UInt<1>(0h1)) node _c_sizes_set_interm_T_1 = or(_c_sizes_set_interm_T, UInt<1>(0h1)) connect c_sizes_set_interm, _c_sizes_set_interm_T_1 wire _c_opcodes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_opcodes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_opcodes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_opcodes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_opcodes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_opcodes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_opcodes_set_WIRE.valid, UInt<1>(0h0) connect _c_opcodes_set_WIRE.ready, UInt<1>(0h0) wire _c_opcodes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_opcodes_set_WIRE_1.bits, _c_opcodes_set_WIRE.bits connect _c_opcodes_set_WIRE_1.valid, _c_opcodes_set_WIRE.valid connect _c_opcodes_set_WIRE_1.ready, _c_opcodes_set_WIRE.ready node _c_opcodes_set_T = dshl(_c_opcodes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_opcodes_set_T_1 = dshl(c_opcodes_set_interm, _c_opcodes_set_T) connect c_opcodes_set, _c_opcodes_set_T_1 wire _c_sizes_set_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_sizes_set_WIRE.bits.data, UInt<64>(0h0) connect _c_sizes_set_WIRE.bits.address, UInt<21>(0h0) connect _c_sizes_set_WIRE.bits.source, UInt<7>(0h0) connect _c_sizes_set_WIRE.bits.size, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.param, UInt<3>(0h0) connect _c_sizes_set_WIRE.bits.opcode, UInt<3>(0h0) connect _c_sizes_set_WIRE.valid, UInt<1>(0h0) connect _c_sizes_set_WIRE.ready, UInt<1>(0h0) wire _c_sizes_set_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_sizes_set_WIRE_1.bits, _c_sizes_set_WIRE.bits connect _c_sizes_set_WIRE_1.valid, _c_sizes_set_WIRE.valid connect _c_sizes_set_WIRE_1.ready, _c_sizes_set_WIRE.ready node _c_sizes_set_T = dshl(_c_sizes_set_WIRE_1.bits.source, UInt<2>(0h2)) node _c_sizes_set_T_1 = dshl(c_sizes_set_interm, _c_sizes_set_T) connect c_sizes_set, _c_sizes_set_T_1 wire _WIRE_18 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_18.bits.corrupt, UInt<1>(0h0) connect _WIRE_18.bits.data, UInt<64>(0h0) connect _WIRE_18.bits.address, UInt<21>(0h0) connect _WIRE_18.bits.source, UInt<7>(0h0) connect _WIRE_18.bits.size, UInt<3>(0h0) connect _WIRE_18.bits.param, UInt<3>(0h0) connect _WIRE_18.bits.opcode, UInt<3>(0h0) connect _WIRE_18.valid, UInt<1>(0h0) connect _WIRE_18.ready, UInt<1>(0h0) wire _WIRE_19 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_19.bits, _WIRE_18.bits connect _WIRE_19.valid, _WIRE_18.valid connect _WIRE_19.ready, _WIRE_18.ready node _T_1194 = dshr(inflight_1, _WIRE_19.bits.source) node _T_1195 = bits(_T_1194, 0, 0) node _T_1196 = eq(_T_1195, UInt<1>(0h0)) node _T_1197 = asUInt(reset) node _T_1198 = eq(_T_1197, UInt<1>(0h0)) when _T_1198 : node _T_1199 = eq(_T_1196, UInt<1>(0h0)) when _T_1199 : printf(clock, UInt<1>(0h1), "Assertion failed: 'C' channel re-used a source ID (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_106 assert(clock, _T_1196, UInt<1>(0h1), "") : assert_106 wire _c_probe_ack_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_1.bits, _c_probe_ack_WIRE.bits connect _c_probe_ack_WIRE_1.valid, _c_probe_ack_WIRE.valid connect _c_probe_ack_WIRE_1.ready, _c_probe_ack_WIRE.ready node _c_probe_ack_T = eq(_c_probe_ack_WIRE_1.bits.opcode, UInt<3>(0h4)) wire _c_probe_ack_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.bits.data, UInt<64>(0h0) connect _c_probe_ack_WIRE_2.bits.address, UInt<21>(0h0) connect _c_probe_ack_WIRE_2.bits.source, UInt<7>(0h0) connect _c_probe_ack_WIRE_2.bits.size, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.param, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.bits.opcode, UInt<3>(0h0) connect _c_probe_ack_WIRE_2.valid, UInt<1>(0h0) connect _c_probe_ack_WIRE_2.ready, UInt<1>(0h0) wire _c_probe_ack_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _c_probe_ack_WIRE_3.bits, _c_probe_ack_WIRE_2.bits connect _c_probe_ack_WIRE_3.valid, _c_probe_ack_WIRE_2.valid connect _c_probe_ack_WIRE_3.ready, _c_probe_ack_WIRE_2.ready node _c_probe_ack_T_1 = eq(_c_probe_ack_WIRE_3.bits.opcode, UInt<3>(0h5)) node c_probe_ack = or(_c_probe_ack_T, _c_probe_ack_T_1) wire d_clr_1 : UInt<65> connect d_clr_1, UInt<65>(0h0) wire d_clr_wo_ready_1 : UInt<65> connect d_clr_wo_ready_1, UInt<65>(0h0) wire d_opcodes_clr_1 : UInt<260> connect d_opcodes_clr_1, UInt<260>(0h0) wire d_sizes_clr_1 : UInt<260> connect d_sizes_clr_1, UInt<260>(0h0) node d_release_ack_1 = eq(io.in.d.bits.opcode, UInt<3>(0h6)) node _T_1200 = and(io.in.d.valid, d_first_2) node _T_1201 = and(_T_1200, UInt<1>(0h1)) node _T_1202 = and(_T_1201, d_release_ack_1) when _T_1202 : node _d_clr_wo_ready_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_wo_ready_1, _d_clr_wo_ready_T_1 node _T_1203 = and(io.in.d.ready, io.in.d.valid) node _T_1204 = and(_T_1203, d_first_2) node _T_1205 = and(_T_1204, UInt<1>(0h1)) node _T_1206 = and(_T_1205, d_release_ack_1) when _T_1206 : node _d_clr_T_1 = dshl(UInt<1>(0h1), io.in.d.bits.source) connect d_clr_1, _d_clr_T_1 node _d_opcodes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_opcodes_clr_T_7 = dshl(UInt<1>(0h1), _d_opcodes_clr_T_6) node _d_opcodes_clr_T_8 = sub(_d_opcodes_clr_T_7, UInt<1>(0h1)) node _d_opcodes_clr_T_9 = tail(_d_opcodes_clr_T_8, 1) node _d_opcodes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_opcodes_clr_T_11 = dshl(_d_opcodes_clr_T_9, _d_opcodes_clr_T_10) connect d_opcodes_clr_1, _d_opcodes_clr_T_11 node _d_sizes_clr_T_6 = dshl(UInt<1>(0h1), UInt<2>(0h2)) node _d_sizes_clr_T_7 = dshl(UInt<1>(0h1), _d_sizes_clr_T_6) node _d_sizes_clr_T_8 = sub(_d_sizes_clr_T_7, UInt<1>(0h1)) node _d_sizes_clr_T_9 = tail(_d_sizes_clr_T_8, 1) node _d_sizes_clr_T_10 = dshl(io.in.d.bits.source, UInt<2>(0h2)) node _d_sizes_clr_T_11 = dshl(_d_sizes_clr_T_9, _d_sizes_clr_T_10) connect d_sizes_clr_1, _d_sizes_clr_T_11 node _T_1207 = and(io.in.d.valid, d_first_2) node _T_1208 = and(_T_1207, UInt<1>(0h1)) node _T_1209 = and(_T_1208, d_release_ack_1) when _T_1209 : wire _same_cycle_resp_WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_1.bits, _same_cycle_resp_WIRE.bits connect _same_cycle_resp_WIRE_1.valid, _same_cycle_resp_WIRE.valid connect _same_cycle_resp_WIRE_1.ready, _same_cycle_resp_WIRE.ready node _same_cycle_resp_T_3 = and(_same_cycle_resp_WIRE_1.valid, c_first) wire _same_cycle_resp_WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_2.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_2.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_2.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_2.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_2.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_2.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_3.bits, _same_cycle_resp_WIRE_2.bits connect _same_cycle_resp_WIRE_3.valid, _same_cycle_resp_WIRE_2.valid connect _same_cycle_resp_WIRE_3.ready, _same_cycle_resp_WIRE_2.ready node _same_cycle_resp_T_4 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 2, 2) node _same_cycle_resp_T_5 = bits(_same_cycle_resp_WIRE_3.bits.opcode, 1, 1) node _same_cycle_resp_T_6 = and(_same_cycle_resp_T_4, _same_cycle_resp_T_5) node _same_cycle_resp_T_7 = and(_same_cycle_resp_T_3, _same_cycle_resp_T_6) wire _same_cycle_resp_WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_4.bits.corrupt, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.bits.data, UInt<64>(0h0) connect _same_cycle_resp_WIRE_4.bits.address, UInt<21>(0h0) connect _same_cycle_resp_WIRE_4.bits.source, UInt<7>(0h0) connect _same_cycle_resp_WIRE_4.bits.size, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.param, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.bits.opcode, UInt<3>(0h0) connect _same_cycle_resp_WIRE_4.valid, UInt<1>(0h0) connect _same_cycle_resp_WIRE_4.ready, UInt<1>(0h0) wire _same_cycle_resp_WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _same_cycle_resp_WIRE_5.bits, _same_cycle_resp_WIRE_4.bits connect _same_cycle_resp_WIRE_5.valid, _same_cycle_resp_WIRE_4.valid connect _same_cycle_resp_WIRE_5.ready, _same_cycle_resp_WIRE_4.ready node _same_cycle_resp_T_8 = eq(_same_cycle_resp_WIRE_5.bits.source, io.in.d.bits.source) node same_cycle_resp_1 = and(_same_cycle_resp_T_7, _same_cycle_resp_T_8) node _T_1210 = dshr(inflight_1, io.in.d.bits.source) node _T_1211 = bits(_T_1210, 0, 0) node _T_1212 = or(_T_1211, same_cycle_resp_1) node _T_1213 = asUInt(reset) node _T_1214 = eq(_T_1213, UInt<1>(0h0)) when _T_1214 : node _T_1215 = eq(_T_1212, UInt<1>(0h0)) when _T_1215 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel acknowledged for nothing inflight (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_107 assert(clock, _T_1212, UInt<1>(0h1), "") : assert_107 when same_cycle_resp_1 : wire _WIRE_20 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_20.bits.corrupt, UInt<1>(0h0) connect _WIRE_20.bits.data, UInt<64>(0h0) connect _WIRE_20.bits.address, UInt<21>(0h0) connect _WIRE_20.bits.source, UInt<7>(0h0) connect _WIRE_20.bits.size, UInt<3>(0h0) connect _WIRE_20.bits.param, UInt<3>(0h0) connect _WIRE_20.bits.opcode, UInt<3>(0h0) connect _WIRE_20.valid, UInt<1>(0h0) connect _WIRE_20.ready, UInt<1>(0h0) wire _WIRE_21 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_21.bits, _WIRE_20.bits connect _WIRE_21.valid, _WIRE_20.valid connect _WIRE_21.ready, _WIRE_20.ready node _T_1216 = eq(io.in.d.bits.size, _WIRE_21.bits.size) node _T_1217 = asUInt(reset) node _T_1218 = eq(_T_1217, UInt<1>(0h0)) when _T_1218 : node _T_1219 = eq(_T_1216, UInt<1>(0h0)) when _T_1219 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_108 assert(clock, _T_1216, UInt<1>(0h1), "") : assert_108 else : node _T_1220 = eq(io.in.d.bits.size, c_size_lookup) node _T_1221 = asUInt(reset) node _T_1222 = eq(_T_1221, UInt<1>(0h0)) when _T_1222 : node _T_1223 = eq(_T_1220, UInt<1>(0h0)) when _T_1223 : printf(clock, UInt<1>(0h1), "Assertion failed: 'D' channel contains improper response size (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:52 assert(cond, message)\n") : printf_109 assert(clock, _T_1220, UInt<1>(0h1), "") : assert_109 node _T_1224 = and(io.in.d.valid, d_first_2) node _T_1225 = and(_T_1224, c_first) wire _WIRE_22 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_22.bits.corrupt, UInt<1>(0h0) connect _WIRE_22.bits.data, UInt<64>(0h0) connect _WIRE_22.bits.address, UInt<21>(0h0) connect _WIRE_22.bits.source, UInt<7>(0h0) connect _WIRE_22.bits.size, UInt<3>(0h0) connect _WIRE_22.bits.param, UInt<3>(0h0) connect _WIRE_22.bits.opcode, UInt<3>(0h0) connect _WIRE_22.valid, UInt<1>(0h0) connect _WIRE_22.ready, UInt<1>(0h0) wire _WIRE_23 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_23.bits, _WIRE_22.bits connect _WIRE_23.valid, _WIRE_22.valid connect _WIRE_23.ready, _WIRE_22.ready node _T_1226 = and(_T_1225, _WIRE_23.valid) wire _WIRE_24 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_24.bits.corrupt, UInt<1>(0h0) connect _WIRE_24.bits.data, UInt<64>(0h0) connect _WIRE_24.bits.address, UInt<21>(0h0) connect _WIRE_24.bits.source, UInt<7>(0h0) connect _WIRE_24.bits.size, UInt<3>(0h0) connect _WIRE_24.bits.param, UInt<3>(0h0) connect _WIRE_24.bits.opcode, UInt<3>(0h0) connect _WIRE_24.valid, UInt<1>(0h0) connect _WIRE_24.ready, UInt<1>(0h0) wire _WIRE_25 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_25.bits, _WIRE_24.bits connect _WIRE_25.valid, _WIRE_24.valid connect _WIRE_25.ready, _WIRE_24.ready node _T_1227 = eq(_WIRE_25.bits.source, io.in.d.bits.source) node _T_1228 = and(_T_1226, _T_1227) node _T_1229 = and(_T_1228, d_release_ack_1) node _T_1230 = eq(c_probe_ack, UInt<1>(0h0)) node _T_1231 = and(_T_1229, _T_1230) when _T_1231 : node _T_1232 = eq(io.in.d.ready, UInt<1>(0h0)) wire _WIRE_26 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_26.bits.corrupt, UInt<1>(0h0) connect _WIRE_26.bits.data, UInt<64>(0h0) connect _WIRE_26.bits.address, UInt<21>(0h0) connect _WIRE_26.bits.source, UInt<7>(0h0) connect _WIRE_26.bits.size, UInt<3>(0h0) connect _WIRE_26.bits.param, UInt<3>(0h0) connect _WIRE_26.bits.opcode, UInt<3>(0h0) connect _WIRE_26.valid, UInt<1>(0h0) connect _WIRE_26.ready, UInt<1>(0h0) wire _WIRE_27 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_27.bits, _WIRE_26.bits connect _WIRE_27.valid, _WIRE_26.valid connect _WIRE_27.ready, _WIRE_26.ready node _T_1233 = or(_T_1232, _WIRE_27.ready) node _T_1234 = asUInt(reset) node _T_1235 = eq(_T_1234, UInt<1>(0h0)) when _T_1235 : node _T_1236 = eq(_T_1233, UInt<1>(0h0)) when _T_1236 : printf(clock, UInt<1>(0h1), "Assertion failed: ready check\n at Monitor.scala:52 assert(cond, message)\n") : printf_110 assert(clock, _T_1233, UInt<1>(0h1), "") : assert_110 node _inflight_T_3 = or(inflight_1, c_set) node _inflight_T_4 = not(d_clr_1) node _inflight_T_5 = and(_inflight_T_3, _inflight_T_4) connect inflight_1, _inflight_T_5 node _inflight_opcodes_T_3 = or(inflight_opcodes_1, c_opcodes_set) node _inflight_opcodes_T_4 = not(d_opcodes_clr_1) node _inflight_opcodes_T_5 = and(_inflight_opcodes_T_3, _inflight_opcodes_T_4) connect inflight_opcodes_1, _inflight_opcodes_T_5 node _inflight_sizes_T_3 = or(inflight_sizes_1, c_sizes_set) node _inflight_sizes_T_4 = not(d_sizes_clr_1) node _inflight_sizes_T_5 = and(_inflight_sizes_T_3, _inflight_sizes_T_4) connect inflight_sizes_1, _inflight_sizes_T_5 regreset watchdog_1 : UInt<32>, clock, reset, UInt<32>(0h0) inst plusarg_reader_1 of plusarg_reader_212 node _T_1237 = orr(inflight_1) node _T_1238 = eq(_T_1237, UInt<1>(0h0)) node _T_1239 = eq(plusarg_reader_1.out, UInt<1>(0h0)) node _T_1240 = or(_T_1238, _T_1239) node _T_1241 = lt(watchdog_1, plusarg_reader_1.out) node _T_1242 = or(_T_1240, _T_1241) node _T_1243 = asUInt(reset) node _T_1244 = eq(_T_1243, UInt<1>(0h0)) when _T_1244 : node _T_1245 = eq(_T_1242, UInt<1>(0h0)) when _T_1245 : printf(clock, UInt<1>(0h1), "Assertion failed: TileLink timeout expired (connected at generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala:80:114)\n at Monitor.scala:45 assert(cond, message)\n") : printf_111 assert(clock, _T_1242, UInt<1>(0h1), "") : assert_111 node _watchdog_T_2 = add(watchdog_1, UInt<1>(0h1)) node _watchdog_T_3 = tail(_watchdog_T_2, 1) connect watchdog_1, _watchdog_T_3 wire _WIRE_28 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_28.bits.corrupt, UInt<1>(0h0) connect _WIRE_28.bits.data, UInt<64>(0h0) connect _WIRE_28.bits.address, UInt<21>(0h0) connect _WIRE_28.bits.source, UInt<7>(0h0) connect _WIRE_28.bits.size, UInt<3>(0h0) connect _WIRE_28.bits.param, UInt<3>(0h0) connect _WIRE_28.bits.opcode, UInt<3>(0h0) connect _WIRE_28.valid, UInt<1>(0h0) connect _WIRE_28.ready, UInt<1>(0h0) wire _WIRE_29 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<7>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_29.bits, _WIRE_28.bits connect _WIRE_29.valid, _WIRE_28.valid connect _WIRE_29.ready, _WIRE_28.ready node _T_1246 = and(_WIRE_29.ready, _WIRE_29.valid) node _T_1247 = and(io.in.d.ready, io.in.d.valid) node _T_1248 = or(_T_1246, _T_1247) when _T_1248 : connect watchdog_1, UInt<1>(0h0)
module TLMonitor_104( // @[Monitor.scala:36:7] input clock, // @[Monitor.scala:36:7] input reset, // @[Monitor.scala:36:7] input io_in_a_ready, // @[Monitor.scala:20:14] input io_in_a_valid, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_param, // @[Monitor.scala:20:14] input [2:0] io_in_a_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_a_bits_source, // @[Monitor.scala:20:14] input [20:0] io_in_a_bits_address, // @[Monitor.scala:20:14] input [7:0] io_in_a_bits_mask, // @[Monitor.scala:20:14] input [63:0] io_in_a_bits_data, // @[Monitor.scala:20:14] input io_in_a_bits_corrupt, // @[Monitor.scala:20:14] input io_in_d_ready, // @[Monitor.scala:20:14] input io_in_d_valid, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_opcode, // @[Monitor.scala:20:14] input [2:0] io_in_d_bits_size, // @[Monitor.scala:20:14] input [6:0] io_in_d_bits_source // @[Monitor.scala:20:14] ); wire [31:0] _plusarg_reader_1_out; // @[PlusArg.scala:80:11] wire [31:0] _plusarg_reader_out; // @[PlusArg.scala:80:11] wire io_in_a_ready_0 = io_in_a_ready; // @[Monitor.scala:36:7] wire io_in_a_valid_0 = io_in_a_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Monitor.scala:36:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Monitor.scala:36:7] wire [20:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Monitor.scala:36:7] wire [7:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Monitor.scala:36:7] wire [63:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Monitor.scala:36:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Monitor.scala:36:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Monitor.scala:36:7] wire io_in_d_valid_0 = io_in_d_valid; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_opcode_0 = io_in_d_bits_opcode; // @[Monitor.scala:36:7] wire [2:0] io_in_d_bits_size_0 = io_in_d_bits_size; // @[Monitor.scala:36:7] wire [6:0] io_in_d_bits_source_0 = io_in_d_bits_source; // @[Monitor.scala:36:7] wire [63:0] io_in_d_bits_data = 64'h0; // @[Monitor.scala:36:7] wire [63:0] _c_first_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_first_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_first_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_wo_ready_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_wo_ready_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_interm_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_interm_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_opcodes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_opcodes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_sizes_set_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_sizes_set_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _c_probe_ack_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _c_probe_ack_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_1_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_2_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_3_bits_data = 64'h0; // @[Bundles.scala:265:61] wire [63:0] _same_cycle_resp_WIRE_4_bits_data = 64'h0; // @[Bundles.scala:265:74] wire [63:0] _same_cycle_resp_WIRE_5_bits_data = 64'h0; // @[Bundles.scala:265:61] wire io_in_d_bits_sink = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_denied = 1'h0; // @[Monitor.scala:36:7] wire io_in_d_bits_corrupt = 1'h0; // @[Monitor.scala:36:7] wire sink_ok = 1'h0; // @[Monitor.scala:309:31] wire _c_first_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_first_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_first_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_first_T = 1'h0; // @[Decoupled.scala:51:35] wire c_first_beats1_opdata = 1'h0; // @[Edges.scala:102:36] wire _c_first_last_T = 1'h0; // @[Edges.scala:232:25] wire c_first_done = 1'h0; // @[Edges.scala:233:22] wire _c_set_wo_ready_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_wo_ready_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_wo_ready_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_interm_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_interm_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_opcodes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_opcodes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_sizes_set_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_sizes_set_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T = 1'h0; // @[Monitor.scala:772:47] wire _c_probe_ack_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _c_probe_ack_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _c_probe_ack_T_1 = 1'h0; // @[Monitor.scala:772:95] wire c_probe_ack = 1'h0; // @[Monitor.scala:772:71] wire _same_cycle_resp_WIRE_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_1_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_1_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_3 = 1'h0; // @[Monitor.scala:795:44] wire _same_cycle_resp_WIRE_2_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_2_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_3_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_3_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_T_4 = 1'h0; // @[Edges.scala:68:36] wire _same_cycle_resp_T_5 = 1'h0; // @[Edges.scala:68:51] wire _same_cycle_resp_T_6 = 1'h0; // @[Edges.scala:68:40] wire _same_cycle_resp_T_7 = 1'h0; // @[Monitor.scala:795:55] wire _same_cycle_resp_WIRE_4_ready = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_valid = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_4_bits_corrupt = 1'h0; // @[Bundles.scala:265:74] wire _same_cycle_resp_WIRE_5_ready = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_valid = 1'h0; // @[Bundles.scala:265:61] wire _same_cycle_resp_WIRE_5_bits_corrupt = 1'h0; // @[Bundles.scala:265:61] wire same_cycle_resp_1 = 1'h0; // @[Monitor.scala:795:88] wire [2:0] responseMap_0 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMap_1 = 3'h0; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_0 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_1 = 3'h0; // @[Monitor.scala:644:42] wire [2:0] _c_first_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_first_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_first_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] c_first_beats1_decode = 3'h0; // @[Edges.scala:220:59] wire [2:0] c_first_beats1 = 3'h0; // @[Edges.scala:221:14] wire [2:0] _c_first_count_T = 3'h0; // @[Edges.scala:234:27] wire [2:0] c_first_count = 3'h0; // @[Edges.scala:234:25] wire [2:0] _c_first_counter_T = 3'h0; // @[Edges.scala:236:21] wire [2:0] _c_set_wo_ready_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_wo_ready_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_wo_ready_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_interm_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_opcodes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_opcodes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_sizes_set_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_sizes_set_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _c_probe_ack_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _c_probe_ack_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_1_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_1_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_2_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_2_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_3_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_3_bits_size = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_4_bits_opcode = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_param = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_4_bits_size = 3'h0; // @[Bundles.scala:265:74] wire [2:0] _same_cycle_resp_WIRE_5_bits_opcode = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_param = 3'h0; // @[Bundles.scala:265:61] wire [2:0] _same_cycle_resp_WIRE_5_bits_size = 3'h0; // @[Bundles.scala:265:61] wire _source_ok_T_3 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_5 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_9 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_11 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_15 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_17 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_21 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_23 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_27 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_29 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_46 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_48 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_52 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_54 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_58 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_60 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_64 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_66 = 1'h1; // @[Parameters.scala:57:20] wire _source_ok_T_70 = 1'h1; // @[Parameters.scala:56:32] wire _source_ok_T_72 = 1'h1; // @[Parameters.scala:57:20] wire c_first = 1'h1; // @[Edges.scala:231:25] wire _c_first_last_T_1 = 1'h1; // @[Edges.scala:232:43] wire c_first_last = 1'h1; // @[Edges.scala:232:33] wire [2:0] c_first_counter1 = 3'h7; // @[Edges.scala:230:28] wire [3:0] _c_first_counter1_T = 4'hF; // @[Edges.scala:230:28] wire [1:0] io_in_d_bits_param = 2'h0; // @[Monitor.scala:36:7] wire [20:0] _c_first_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_first_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_first_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_wo_ready_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_wo_ready_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_interm_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_interm_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_opcodes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_opcodes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_sizes_set_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_sizes_set_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _c_probe_ack_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _c_probe_ack_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_1_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_2_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_3_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [20:0] _same_cycle_resp_WIRE_4_bits_address = 21'h0; // @[Bundles.scala:265:74] wire [20:0] _same_cycle_resp_WIRE_5_bits_address = 21'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_first_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_first_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_wo_ready_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_wo_ready_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_interm_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_interm_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_opcodes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_opcodes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_sizes_set_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_sizes_set_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _c_probe_ack_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _c_probe_ack_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_1_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_2_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_3_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [6:0] _same_cycle_resp_WIRE_4_bits_source = 7'h0; // @[Bundles.scala:265:74] wire [6:0] _same_cycle_resp_WIRE_5_bits_source = 7'h0; // @[Bundles.scala:265:61] wire [15:0] _a_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _a_size_lookup_T_5 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_opcodes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _d_sizes_clr_T_3 = 16'hF; // @[Monitor.scala:612:57] wire [15:0] _c_opcode_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _c_size_lookup_T_5 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_opcodes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [15:0] _d_sizes_clr_T_9 = 16'hF; // @[Monitor.scala:724:57] wire [16:0] _a_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _a_size_lookup_T_4 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_opcodes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _d_sizes_clr_T_2 = 17'hF; // @[Monitor.scala:612:57] wire [16:0] _c_opcode_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _c_size_lookup_T_4 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_opcodes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [16:0] _d_sizes_clr_T_8 = 17'hF; // @[Monitor.scala:724:57] wire [15:0] _a_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _a_size_lookup_T_3 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_opcodes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _d_sizes_clr_T_1 = 16'h10; // @[Monitor.scala:612:51] wire [15:0] _c_opcode_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _c_size_lookup_T_3 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_opcodes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [15:0] _d_sizes_clr_T_7 = 16'h10; // @[Monitor.scala:724:51] wire [1026:0] _c_opcodes_set_T_1 = 1027'h0; // @[Monitor.scala:767:54] wire [1026:0] _c_sizes_set_T_1 = 1027'h0; // @[Monitor.scala:768:52] wire [9:0] _c_opcodes_set_T = 10'h0; // @[Monitor.scala:767:79] wire [9:0] _c_sizes_set_T = 10'h0; // @[Monitor.scala:768:77] wire [3:0] _c_opcodes_set_interm_T_1 = 4'h1; // @[Monitor.scala:765:61] wire [3:0] _c_sizes_set_interm_T_1 = 4'h1; // @[Monitor.scala:766:59] wire [3:0] c_opcodes_set_interm = 4'h0; // @[Monitor.scala:754:40] wire [3:0] c_sizes_set_interm = 4'h0; // @[Monitor.scala:755:40] wire [3:0] _c_opcodes_set_interm_T = 4'h0; // @[Monitor.scala:765:53] wire [3:0] _c_sizes_set_interm_T = 4'h0; // @[Monitor.scala:766:51] wire [127:0] _c_set_wo_ready_T = 128'h1; // @[OneHot.scala:58:35] wire [127:0] _c_set_T = 128'h1; // @[OneHot.scala:58:35] wire [259:0] c_opcodes_set = 260'h0; // @[Monitor.scala:740:34] wire [259:0] c_sizes_set = 260'h0; // @[Monitor.scala:741:34] wire [64:0] c_set = 65'h0; // @[Monitor.scala:738:34] wire [64:0] c_set_wo_ready = 65'h0; // @[Monitor.scala:739:34] wire [5:0] _c_first_beats1_decode_T_2 = 6'h0; // @[package.scala:243:46] wire [5:0] _c_first_beats1_decode_T_1 = 6'h3F; // @[package.scala:243:76] wire [12:0] _c_first_beats1_decode_T = 13'h3F; // @[package.scala:243:71] wire [2:0] responseMap_6 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMap_7 = 3'h4; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_7 = 3'h4; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_6 = 3'h5; // @[Monitor.scala:644:42] wire [2:0] responseMap_5 = 3'h2; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_5 = 3'h2; // @[Monitor.scala:644:42] wire [2:0] responseMap_2 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_3 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMap_4 = 3'h1; // @[Monitor.scala:643:42] wire [2:0] responseMapSecondOption_2 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_3 = 3'h1; // @[Monitor.scala:644:42] wire [2:0] responseMapSecondOption_4 = 3'h1; // @[Monitor.scala:644:42] wire [3:0] _a_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:637:123] wire [3:0] _a_size_lookup_T_2 = 4'h4; // @[Monitor.scala:641:117] wire [3:0] _d_opcodes_clr_T = 4'h4; // @[Monitor.scala:680:48] wire [3:0] _d_sizes_clr_T = 4'h4; // @[Monitor.scala:681:48] wire [3:0] _c_opcode_lookup_T_2 = 4'h4; // @[Monitor.scala:749:123] wire [3:0] _c_size_lookup_T_2 = 4'h4; // @[Monitor.scala:750:119] wire [3:0] _d_opcodes_clr_T_6 = 4'h4; // @[Monitor.scala:790:48] wire [3:0] _d_sizes_clr_T_6 = 4'h4; // @[Monitor.scala:791:48] wire [2:0] _mask_sizeOH_T = io_in_a_bits_size_0; // @[Misc.scala:202:34] wire [6:0] _source_ok_uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_1 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_2 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_3 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_4 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_5 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_6 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_7 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_8 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_9 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_10 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_11 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_12 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_13 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_14 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_15 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_16 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_17 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_18 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_19 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_20 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_21 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_22 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_23 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_24 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_25 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_26 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_27 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_28 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_29 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_30 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_31 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_32 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_33 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_34 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_35 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_36 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_37 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_38 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_39 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_40 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_41 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_42 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_43 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_44 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_45 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_46 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_47 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_48 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_49 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_50 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_51 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_52 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_53 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _uncommonBits_T_54 = io_in_a_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_5 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_6 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_7 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_8 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire [6:0] _source_ok_uncommonBits_T_9 = io_in_d_bits_source_0; // @[Monitor.scala:36:7] wire _source_ok_T = io_in_a_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_0 = _source_ok_T; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits = _source_ok_uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_1 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_7 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_13 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_19 = io_in_a_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_2 = _source_ok_T_1 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_4 = _source_ok_T_2; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_6 = _source_ok_T_4; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1 = _source_ok_T_6; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_1 = _source_ok_uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_8 = _source_ok_T_7 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_10 = _source_ok_T_8; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_12 = _source_ok_T_10; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_2 = _source_ok_T_12; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_2 = _source_ok_uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_14 = _source_ok_T_13 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_16 = _source_ok_T_14; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_18 = _source_ok_T_16; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_3 = _source_ok_T_18; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_3 = _source_ok_uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_20 = _source_ok_T_19 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_22 = _source_ok_T_20; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_24 = _source_ok_T_22; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_4 = _source_ok_T_24; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_4 = _source_ok_uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_25 = io_in_a_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_26 = _source_ok_T_25 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_28 = _source_ok_T_26; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_30 = _source_ok_T_28; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_5 = _source_ok_T_30; // @[Parameters.scala:1138:31] wire _source_ok_T_31 = io_in_a_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_6 = _source_ok_T_31; // @[Parameters.scala:1138:31] wire _source_ok_T_32 = io_in_a_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_7 = _source_ok_T_32; // @[Parameters.scala:1138:31] wire _source_ok_T_33 = io_in_a_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_8 = _source_ok_T_33; // @[Parameters.scala:1138:31] wire _source_ok_T_34 = io_in_a_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_9 = _source_ok_T_34; // @[Parameters.scala:1138:31] wire _source_ok_T_35 = _source_ok_WIRE_0 | _source_ok_WIRE_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_36 = _source_ok_T_35 | _source_ok_WIRE_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_37 = _source_ok_T_36 | _source_ok_WIRE_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_38 = _source_ok_T_37 | _source_ok_WIRE_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_39 = _source_ok_T_38 | _source_ok_WIRE_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_40 = _source_ok_T_39 | _source_ok_WIRE_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_41 = _source_ok_T_40 | _source_ok_WIRE_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_42 = _source_ok_T_41 | _source_ok_WIRE_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok = _source_ok_T_42 | _source_ok_WIRE_9; // @[Parameters.scala:1138:31, :1139:46] wire [12:0] _GEN = 13'h3F << io_in_a_bits_size_0; // @[package.scala:243:71] wire [12:0] _is_aligned_mask_T; // @[package.scala:243:71] assign _is_aligned_mask_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T; // @[package.scala:243:71] assign _a_first_beats1_decode_T = _GEN; // @[package.scala:243:71] wire [12:0] _a_first_beats1_decode_T_3; // @[package.scala:243:71] assign _a_first_beats1_decode_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _is_aligned_mask_T_1 = _is_aligned_mask_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] is_aligned_mask = ~_is_aligned_mask_T_1; // @[package.scala:243:{46,76}] wire [20:0] _is_aligned_T = {15'h0, io_in_a_bits_address_0[5:0] & is_aligned_mask}; // @[package.scala:243:46] wire is_aligned = _is_aligned_T == 21'h0; // @[Edges.scala:21:{16,24}] wire [1:0] mask_sizeOH_shiftAmount = _mask_sizeOH_T[1:0]; // @[OneHot.scala:64:49] wire [3:0] _mask_sizeOH_T_1 = 4'h1 << mask_sizeOH_shiftAmount; // @[OneHot.scala:64:49, :65:12] wire [2:0] _mask_sizeOH_T_2 = _mask_sizeOH_T_1[2:0]; // @[OneHot.scala:65:{12,27}] wire [2:0] mask_sizeOH = {_mask_sizeOH_T_2[2:1], 1'h1}; // @[OneHot.scala:65:27] wire mask_sub_sub_sub_0_1 = io_in_a_bits_size_0 > 3'h2; // @[Misc.scala:206:21] wire mask_sub_sub_size = mask_sizeOH[2]; // @[Misc.scala:202:81, :209:26] wire mask_sub_sub_bit = io_in_a_bits_address_0[2]; // @[Misc.scala:210:26] wire mask_sub_sub_1_2 = mask_sub_sub_bit; // @[Misc.scala:210:26, :214:27] wire mask_sub_sub_nbit = ~mask_sub_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_sub_0_2 = mask_sub_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_sub_acc_T = mask_sub_sub_size & mask_sub_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_0_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T; // @[Misc.scala:206:21, :215:{29,38}] wire _mask_sub_sub_acc_T_1 = mask_sub_sub_size & mask_sub_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_sub_1_1 = mask_sub_sub_sub_0_1 | _mask_sub_sub_acc_T_1; // @[Misc.scala:206:21, :215:{29,38}] wire mask_sub_size = mask_sizeOH[1]; // @[Misc.scala:202:81, :209:26] wire mask_sub_bit = io_in_a_bits_address_0[1]; // @[Misc.scala:210:26] wire mask_sub_nbit = ~mask_sub_bit; // @[Misc.scala:210:26, :211:20] wire mask_sub_0_2 = mask_sub_sub_0_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T = mask_sub_size & mask_sub_0_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_0_1 = mask_sub_sub_0_1 | _mask_sub_acc_T; // @[Misc.scala:215:{29,38}] wire mask_sub_1_2 = mask_sub_sub_0_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_1 = mask_sub_size & mask_sub_1_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_1_1 = mask_sub_sub_0_1 | _mask_sub_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_sub_2_2 = mask_sub_sub_1_2 & mask_sub_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_sub_acc_T_2 = mask_sub_size & mask_sub_2_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_2_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_sub_3_2 = mask_sub_sub_1_2 & mask_sub_bit; // @[Misc.scala:210:26, :214:27] wire _mask_sub_acc_T_3 = mask_sub_size & mask_sub_3_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_sub_3_1 = mask_sub_sub_1_1 | _mask_sub_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_size = mask_sizeOH[0]; // @[Misc.scala:202:81, :209:26] wire mask_bit = io_in_a_bits_address_0[0]; // @[Misc.scala:210:26] wire mask_nbit = ~mask_bit; // @[Misc.scala:210:26, :211:20] wire mask_eq = mask_sub_0_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T = mask_size & mask_eq; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc = mask_sub_0_1 | _mask_acc_T; // @[Misc.scala:215:{29,38}] wire mask_eq_1 = mask_sub_0_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_1 = mask_size & mask_eq_1; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_1 = mask_sub_0_1 | _mask_acc_T_1; // @[Misc.scala:215:{29,38}] wire mask_eq_2 = mask_sub_1_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_2 = mask_size & mask_eq_2; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_2 = mask_sub_1_1 | _mask_acc_T_2; // @[Misc.scala:215:{29,38}] wire mask_eq_3 = mask_sub_1_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_3 = mask_size & mask_eq_3; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_3 = mask_sub_1_1 | _mask_acc_T_3; // @[Misc.scala:215:{29,38}] wire mask_eq_4 = mask_sub_2_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_4 = mask_size & mask_eq_4; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_4 = mask_sub_2_1 | _mask_acc_T_4; // @[Misc.scala:215:{29,38}] wire mask_eq_5 = mask_sub_2_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_5 = mask_size & mask_eq_5; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_5 = mask_sub_2_1 | _mask_acc_T_5; // @[Misc.scala:215:{29,38}] wire mask_eq_6 = mask_sub_3_2 & mask_nbit; // @[Misc.scala:211:20, :214:27] wire _mask_acc_T_6 = mask_size & mask_eq_6; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_6 = mask_sub_3_1 | _mask_acc_T_6; // @[Misc.scala:215:{29,38}] wire mask_eq_7 = mask_sub_3_2 & mask_bit; // @[Misc.scala:210:26, :214:27] wire _mask_acc_T_7 = mask_size & mask_eq_7; // @[Misc.scala:209:26, :214:27, :215:38] wire mask_acc_7 = mask_sub_3_1 | _mask_acc_T_7; // @[Misc.scala:215:{29,38}] wire [1:0] mask_lo_lo = {mask_acc_1, mask_acc}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_lo_hi = {mask_acc_3, mask_acc_2}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_lo = {mask_lo_hi, mask_lo_lo}; // @[Misc.scala:222:10] wire [1:0] mask_hi_lo = {mask_acc_5, mask_acc_4}; // @[Misc.scala:215:29, :222:10] wire [1:0] mask_hi_hi = {mask_acc_7, mask_acc_6}; // @[Misc.scala:215:29, :222:10] wire [3:0] mask_hi = {mask_hi_hi, mask_hi_lo}; // @[Misc.scala:222:10] wire [7:0] mask = {mask_hi, mask_lo}; // @[Misc.scala:222:10] wire [1:0] uncommonBits = _uncommonBits_T[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_1 = _uncommonBits_T_1[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_2 = _uncommonBits_T_2[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_3 = _uncommonBits_T_3[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_4 = _uncommonBits_T_4[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_5 = _uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_6 = _uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_7 = _uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_8 = _uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_9 = _uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_10 = _uncommonBits_T_10[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_11 = _uncommonBits_T_11[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_12 = _uncommonBits_T_12[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_13 = _uncommonBits_T_13[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_14 = _uncommonBits_T_14[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_15 = _uncommonBits_T_15[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_16 = _uncommonBits_T_16[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_17 = _uncommonBits_T_17[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_18 = _uncommonBits_T_18[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_19 = _uncommonBits_T_19[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_20 = _uncommonBits_T_20[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_21 = _uncommonBits_T_21[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_22 = _uncommonBits_T_22[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_23 = _uncommonBits_T_23[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_24 = _uncommonBits_T_24[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_25 = _uncommonBits_T_25[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_26 = _uncommonBits_T_26[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_27 = _uncommonBits_T_27[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_28 = _uncommonBits_T_28[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_29 = _uncommonBits_T_29[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_30 = _uncommonBits_T_30[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_31 = _uncommonBits_T_31[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_32 = _uncommonBits_T_32[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_33 = _uncommonBits_T_33[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_34 = _uncommonBits_T_34[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_35 = _uncommonBits_T_35[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_36 = _uncommonBits_T_36[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_37 = _uncommonBits_T_37[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_38 = _uncommonBits_T_38[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_39 = _uncommonBits_T_39[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_40 = _uncommonBits_T_40[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_41 = _uncommonBits_T_41[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_42 = _uncommonBits_T_42[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_43 = _uncommonBits_T_43[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_44 = _uncommonBits_T_44[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_45 = _uncommonBits_T_45[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_46 = _uncommonBits_T_46[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_47 = _uncommonBits_T_47[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_48 = _uncommonBits_T_48[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_49 = _uncommonBits_T_49[2:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_50 = _uncommonBits_T_50[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_51 = _uncommonBits_T_51[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_52 = _uncommonBits_T_52[1:0]; // @[Parameters.scala:52:{29,56}] wire [1:0] uncommonBits_53 = _uncommonBits_T_53[1:0]; // @[Parameters.scala:52:{29,56}] wire [2:0] uncommonBits_54 = _uncommonBits_T_54[2:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_43 = io_in_d_bits_source_0 == 7'h10; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_0 = _source_ok_T_43; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_5 = _source_ok_uncommonBits_T_5[1:0]; // @[Parameters.scala:52:{29,56}] wire [4:0] _source_ok_T_44 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_50 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_56 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire [4:0] _source_ok_T_62 = io_in_d_bits_source_0[6:2]; // @[Monitor.scala:36:7] wire _source_ok_T_45 = _source_ok_T_44 == 5'h0; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_47 = _source_ok_T_45; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_49 = _source_ok_T_47; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_1 = _source_ok_T_49; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_6 = _source_ok_uncommonBits_T_6[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_51 = _source_ok_T_50 == 5'h1; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_53 = _source_ok_T_51; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_55 = _source_ok_T_53; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_2 = _source_ok_T_55; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_7 = _source_ok_uncommonBits_T_7[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_57 = _source_ok_T_56 == 5'h2; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_59 = _source_ok_T_57; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_61 = _source_ok_T_59; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_3 = _source_ok_T_61; // @[Parameters.scala:1138:31] wire [1:0] source_ok_uncommonBits_8 = _source_ok_uncommonBits_T_8[1:0]; // @[Parameters.scala:52:{29,56}] wire _source_ok_T_63 = _source_ok_T_62 == 5'h3; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_65 = _source_ok_T_63; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_67 = _source_ok_T_65; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_4 = _source_ok_T_67; // @[Parameters.scala:1138:31] wire [2:0] source_ok_uncommonBits_9 = _source_ok_uncommonBits_T_9[2:0]; // @[Parameters.scala:52:{29,56}] wire [3:0] _source_ok_T_68 = io_in_d_bits_source_0[6:3]; // @[Monitor.scala:36:7] wire _source_ok_T_69 = _source_ok_T_68 == 4'h4; // @[Parameters.scala:54:{10,32}] wire _source_ok_T_71 = _source_ok_T_69; // @[Parameters.scala:54:{32,67}] wire _source_ok_T_73 = _source_ok_T_71; // @[Parameters.scala:54:67, :56:48] wire _source_ok_WIRE_1_5 = _source_ok_T_73; // @[Parameters.scala:1138:31] wire _source_ok_T_74 = io_in_d_bits_source_0 == 7'h28; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_6 = _source_ok_T_74; // @[Parameters.scala:1138:31] wire _source_ok_T_75 = io_in_d_bits_source_0 == 7'h29; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_7 = _source_ok_T_75; // @[Parameters.scala:1138:31] wire _source_ok_T_76 = io_in_d_bits_source_0 == 7'h2A; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_8 = _source_ok_T_76; // @[Parameters.scala:1138:31] wire _source_ok_T_77 = io_in_d_bits_source_0 == 7'h40; // @[Monitor.scala:36:7] wire _source_ok_WIRE_1_9 = _source_ok_T_77; // @[Parameters.scala:1138:31] wire _source_ok_T_78 = _source_ok_WIRE_1_0 | _source_ok_WIRE_1_1; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_79 = _source_ok_T_78 | _source_ok_WIRE_1_2; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_80 = _source_ok_T_79 | _source_ok_WIRE_1_3; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_81 = _source_ok_T_80 | _source_ok_WIRE_1_4; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_82 = _source_ok_T_81 | _source_ok_WIRE_1_5; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_83 = _source_ok_T_82 | _source_ok_WIRE_1_6; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_84 = _source_ok_T_83 | _source_ok_WIRE_1_7; // @[Parameters.scala:1138:31, :1139:46] wire _source_ok_T_85 = _source_ok_T_84 | _source_ok_WIRE_1_8; // @[Parameters.scala:1138:31, :1139:46] wire source_ok_1 = _source_ok_T_85 | _source_ok_WIRE_1_9; // @[Parameters.scala:1138:31, :1139:46] wire _T_1180 = io_in_a_ready_0 & io_in_a_valid_0; // @[Decoupled.scala:51:35] wire _a_first_T; // @[Decoupled.scala:51:35] assign _a_first_T = _T_1180; // @[Decoupled.scala:51:35] wire _a_first_T_1; // @[Decoupled.scala:51:35] assign _a_first_T_1 = _T_1180; // @[Decoupled.scala:51:35] wire [5:0] _a_first_beats1_decode_T_1 = _a_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_2 = ~_a_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode = _a_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire _a_first_beats1_opdata_T = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire _a_first_beats1_opdata_T_1 = io_in_a_bits_opcode_0[2]; // @[Monitor.scala:36:7] wire a_first_beats1_opdata = ~_a_first_beats1_opdata_T; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1 = a_first_beats1_opdata ? a_first_beats1_decode : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T = {1'h0, a_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1 = _a_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire a_first = a_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T = a_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_1 = a_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last = _a_first_last_T | _a_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire a_first_done = a_first_last & _a_first_T; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T = ~a_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count = a_first_beats1 & _a_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T = a_first ? a_first_beats1 : a_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode; // @[Monitor.scala:387:22] reg [2:0] param; // @[Monitor.scala:388:22] reg [2:0] size; // @[Monitor.scala:389:22] reg [6:0] source; // @[Monitor.scala:390:22] reg [20:0] address; // @[Monitor.scala:391:22] wire _T_1248 = io_in_d_ready_0 & io_in_d_valid_0; // @[Decoupled.scala:51:35] wire _d_first_T; // @[Decoupled.scala:51:35] assign _d_first_T = _T_1248; // @[Decoupled.scala:51:35] wire _d_first_T_1; // @[Decoupled.scala:51:35] assign _d_first_T_1 = _T_1248; // @[Decoupled.scala:51:35] wire _d_first_T_2; // @[Decoupled.scala:51:35] assign _d_first_T_2 = _T_1248; // @[Decoupled.scala:51:35] wire [12:0] _GEN_0 = 13'h3F << io_in_d_bits_size_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T; // @[package.scala:243:71] assign _d_first_beats1_decode_T = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_3; // @[package.scala:243:71] assign _d_first_beats1_decode_T_3 = _GEN_0; // @[package.scala:243:71] wire [12:0] _d_first_beats1_decode_T_6; // @[package.scala:243:71] assign _d_first_beats1_decode_T_6 = _GEN_0; // @[package.scala:243:71] wire [5:0] _d_first_beats1_decode_T_1 = _d_first_beats1_decode_T[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_2 = ~_d_first_beats1_decode_T_1; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode = _d_first_beats1_decode_T_2[5:3]; // @[package.scala:243:46] wire d_first_beats1_opdata = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_1 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire d_first_beats1_opdata_2 = io_in_d_bits_opcode_0[0]; // @[Monitor.scala:36:7] wire [2:0] d_first_beats1 = d_first_beats1_opdata ? d_first_beats1_decode : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T = {1'h0, d_first_counter} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1 = _d_first_counter1_T[2:0]; // @[Edges.scala:230:28] wire d_first = d_first_counter == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T = d_first_counter == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_1 = d_first_beats1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last = _d_first_last_T | _d_first_last_T_1; // @[Edges.scala:232:{25,33,43}] wire d_first_done = d_first_last & _d_first_T; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T = ~d_first_counter1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count = d_first_beats1 & _d_first_count_T; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T = d_first ? d_first_beats1 : d_first_counter1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] reg [2:0] opcode_1; // @[Monitor.scala:538:22] reg [2:0] size_1; // @[Monitor.scala:540:22] reg [6:0] source_1; // @[Monitor.scala:541:22] reg [64:0] inflight; // @[Monitor.scala:614:27] reg [259:0] inflight_opcodes; // @[Monitor.scala:616:35] reg [259:0] inflight_sizes; // @[Monitor.scala:618:33] wire [5:0] _a_first_beats1_decode_T_4 = _a_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _a_first_beats1_decode_T_5 = ~_a_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] a_first_beats1_decode_1 = _a_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire a_first_beats1_opdata_1 = ~_a_first_beats1_opdata_T_1; // @[Edges.scala:92:{28,37}] wire [2:0] a_first_beats1_1 = a_first_beats1_opdata_1 ? a_first_beats1_decode_1 : 3'h0; // @[Edges.scala:92:28, :220:59, :221:14] reg [2:0] a_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _a_first_counter1_T_1 = {1'h0, a_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] a_first_counter1_1 = _a_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire a_first_1 = a_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _a_first_last_T_2 = a_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _a_first_last_T_3 = a_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire a_first_last_1 = _a_first_last_T_2 | _a_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire a_first_done_1 = a_first_last_1 & _a_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _a_first_count_T_1 = ~a_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] a_first_count_1 = a_first_beats1_1 & _a_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _a_first_counter_T_1 = a_first_1 ? a_first_beats1_1 : a_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [5:0] _d_first_beats1_decode_T_4 = _d_first_beats1_decode_T_3[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_5 = ~_d_first_beats1_decode_T_4; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_1 = _d_first_beats1_decode_T_5[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_1 = d_first_beats1_opdata_1 ? d_first_beats1_decode_1 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_1; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_1 = {1'h0, d_first_counter_1} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_1 = _d_first_counter1_T_1[2:0]; // @[Edges.scala:230:28] wire d_first_1 = d_first_counter_1 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_2 = d_first_counter_1 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_3 = d_first_beats1_1 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_1 = _d_first_last_T_2 | _d_first_last_T_3; // @[Edges.scala:232:{25,33,43}] wire d_first_done_1 = d_first_last_1 & _d_first_T_1; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_1 = ~d_first_counter1_1; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_1 = d_first_beats1_1 & _d_first_count_T_1; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_1 = d_first_1 ? d_first_beats1_1 : d_first_counter1_1; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [64:0] a_set; // @[Monitor.scala:626:34] wire [64:0] a_set_wo_ready; // @[Monitor.scala:627:34] wire [259:0] a_opcodes_set; // @[Monitor.scala:630:33] wire [259:0] a_sizes_set; // @[Monitor.scala:632:31] wire [2:0] a_opcode_lookup; // @[Monitor.scala:635:35] wire [9:0] _GEN_1 = {1'h0, io_in_d_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :637:69] wire [9:0] _a_opcode_lookup_T; // @[Monitor.scala:637:69] assign _a_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69] wire [9:0] _a_size_lookup_T; // @[Monitor.scala:641:65] assign _a_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :641:65] wire [9:0] _d_opcodes_clr_T_4; // @[Monitor.scala:680:101] assign _d_opcodes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :680:101] wire [9:0] _d_sizes_clr_T_4; // @[Monitor.scala:681:99] assign _d_sizes_clr_T_4 = _GEN_1; // @[Monitor.scala:637:69, :681:99] wire [9:0] _c_opcode_lookup_T; // @[Monitor.scala:749:69] assign _c_opcode_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :749:69] wire [9:0] _c_size_lookup_T; // @[Monitor.scala:750:67] assign _c_size_lookup_T = _GEN_1; // @[Monitor.scala:637:69, :750:67] wire [9:0] _d_opcodes_clr_T_10; // @[Monitor.scala:790:101] assign _d_opcodes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :790:101] wire [9:0] _d_sizes_clr_T_10; // @[Monitor.scala:791:99] assign _d_sizes_clr_T_10 = _GEN_1; // @[Monitor.scala:637:69, :791:99] wire [259:0] _a_opcode_lookup_T_1 = inflight_opcodes >> _a_opcode_lookup_T; // @[Monitor.scala:616:35, :637:{44,69}] wire [259:0] _a_opcode_lookup_T_6 = {256'h0, _a_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:637:{44,97}] wire [259:0] _a_opcode_lookup_T_7 = {1'h0, _a_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:637:{97,152}] assign a_opcode_lookup = _a_opcode_lookup_T_7[2:0]; // @[Monitor.scala:635:35, :637:{21,152}] wire [3:0] a_size_lookup; // @[Monitor.scala:639:33] wire [259:0] _a_size_lookup_T_1 = inflight_sizes >> _a_size_lookup_T; // @[Monitor.scala:618:33, :641:{40,65}] wire [259:0] _a_size_lookup_T_6 = {256'h0, _a_size_lookup_T_1[3:0]}; // @[Monitor.scala:641:{40,91}] wire [259:0] _a_size_lookup_T_7 = {1'h0, _a_size_lookup_T_6[259:1]}; // @[Monitor.scala:641:{91,144}] assign a_size_lookup = _a_size_lookup_T_7[3:0]; // @[Monitor.scala:639:33, :641:{19,144}] wire [3:0] a_opcodes_set_interm; // @[Monitor.scala:646:40] wire [3:0] a_sizes_set_interm; // @[Monitor.scala:648:38] wire _same_cycle_resp_T = io_in_a_valid_0 & a_first_1; // @[Monitor.scala:36:7, :651:26, :684:44] wire [127:0] _GEN_2 = 128'h1 << io_in_a_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _a_set_wo_ready_T; // @[OneHot.scala:58:35] assign _a_set_wo_ready_T = _GEN_2; // @[OneHot.scala:58:35] wire [127:0] _a_set_T; // @[OneHot.scala:58:35] assign _a_set_T = _GEN_2; // @[OneHot.scala:58:35] assign a_set_wo_ready = _same_cycle_resp_T ? _a_set_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1113 = _T_1180 & a_first_1; // @[Decoupled.scala:51:35] assign a_set = _T_1113 ? _a_set_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [3:0] _a_opcodes_set_interm_T = {io_in_a_bits_opcode_0, 1'h0}; // @[Monitor.scala:36:7, :657:53] wire [3:0] _a_opcodes_set_interm_T_1 = {_a_opcodes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:657:{53,61}] assign a_opcodes_set_interm = _T_1113 ? _a_opcodes_set_interm_T_1 : 4'h0; // @[Monitor.scala:646:40, :655:{25,70}, :657:{28,61}] wire [3:0] _a_sizes_set_interm_T = {io_in_a_bits_size_0, 1'h0}; // @[Monitor.scala:36:7, :658:51] wire [3:0] _a_sizes_set_interm_T_1 = {_a_sizes_set_interm_T[3:1], 1'h1}; // @[Monitor.scala:658:{51,59}] assign a_sizes_set_interm = _T_1113 ? _a_sizes_set_interm_T_1 : 4'h0; // @[Monitor.scala:648:38, :655:{25,70}, :658:{28,59}] wire [9:0] _GEN_3 = {1'h0, io_in_a_bits_source_0, 2'h0}; // @[Monitor.scala:36:7, :659:79] wire [9:0] _a_opcodes_set_T; // @[Monitor.scala:659:79] assign _a_opcodes_set_T = _GEN_3; // @[Monitor.scala:659:79] wire [9:0] _a_sizes_set_T; // @[Monitor.scala:660:77] assign _a_sizes_set_T = _GEN_3; // @[Monitor.scala:659:79, :660:77] wire [1026:0] _a_opcodes_set_T_1 = {1023'h0, a_opcodes_set_interm} << _a_opcodes_set_T; // @[Monitor.scala:646:40, :659:{54,79}] assign a_opcodes_set = _T_1113 ? _a_opcodes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:630:33, :655:{25,70}, :659:{28,54}] wire [1026:0] _a_sizes_set_T_1 = {1023'h0, a_sizes_set_interm} << _a_sizes_set_T; // @[Monitor.scala:648:38, :659:54, :660:{52,77}] assign a_sizes_set = _T_1113 ? _a_sizes_set_T_1[259:0] : 260'h0; // @[Monitor.scala:632:31, :655:{25,70}, :660:{28,52}] wire [64:0] d_clr; // @[Monitor.scala:664:34] wire [64:0] d_clr_wo_ready; // @[Monitor.scala:665:34] wire [259:0] d_opcodes_clr; // @[Monitor.scala:668:33] wire [259:0] d_sizes_clr; // @[Monitor.scala:670:31] wire _GEN_4 = io_in_d_bits_opcode_0 == 3'h6; // @[Monitor.scala:36:7, :673:46] wire d_release_ack; // @[Monitor.scala:673:46] assign d_release_ack = _GEN_4; // @[Monitor.scala:673:46] wire d_release_ack_1; // @[Monitor.scala:783:46] assign d_release_ack_1 = _GEN_4; // @[Monitor.scala:673:46, :783:46] wire _T_1159 = io_in_d_valid_0 & d_first_1; // @[Monitor.scala:36:7, :674:26] wire [127:0] _GEN_5 = 128'h1 << io_in_d_bits_source_0; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T; // @[OneHot.scala:58:35] assign _d_clr_T = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_wo_ready_T_1; // @[OneHot.scala:58:35] assign _d_clr_wo_ready_T_1 = _GEN_5; // @[OneHot.scala:58:35] wire [127:0] _d_clr_T_1; // @[OneHot.scala:58:35] assign _d_clr_T_1 = _GEN_5; // @[OneHot.scala:58:35] assign d_clr_wo_ready = _T_1159 & ~d_release_ack ? _d_clr_wo_ready_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1128 = _T_1248 & d_first_1 & ~d_release_ack; // @[Decoupled.scala:51:35] assign d_clr = _T_1128 ? _d_clr_T[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_5 = 1039'hF << _d_opcodes_clr_T_4; // @[Monitor.scala:680:{76,101}] assign d_opcodes_clr = _T_1128 ? _d_opcodes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:668:33, :678:{25,70,89}, :680:{21,76}] wire [1038:0] _d_sizes_clr_T_5 = 1039'hF << _d_sizes_clr_T_4; // @[Monitor.scala:681:{74,99}] assign d_sizes_clr = _T_1128 ? _d_sizes_clr_T_5[259:0] : 260'h0; // @[Monitor.scala:670:31, :678:{25,70,89}, :681:{21,74}] wire _same_cycle_resp_T_1 = _same_cycle_resp_T; // @[Monitor.scala:684:{44,55}] wire _same_cycle_resp_T_2 = io_in_a_bits_source_0 == io_in_d_bits_source_0; // @[Monitor.scala:36:7, :684:113] wire same_cycle_resp = _same_cycle_resp_T_1 & _same_cycle_resp_T_2; // @[Monitor.scala:684:{55,88,113}] wire [64:0] _inflight_T = inflight | a_set; // @[Monitor.scala:614:27, :626:34, :705:27] wire [64:0] _inflight_T_1 = ~d_clr; // @[Monitor.scala:664:34, :705:38] wire [64:0] _inflight_T_2 = _inflight_T & _inflight_T_1; // @[Monitor.scala:705:{27,36,38}] wire [259:0] _inflight_opcodes_T = inflight_opcodes | a_opcodes_set; // @[Monitor.scala:616:35, :630:33, :706:43] wire [259:0] _inflight_opcodes_T_1 = ~d_opcodes_clr; // @[Monitor.scala:668:33, :706:62] wire [259:0] _inflight_opcodes_T_2 = _inflight_opcodes_T & _inflight_opcodes_T_1; // @[Monitor.scala:706:{43,60,62}] wire [259:0] _inflight_sizes_T = inflight_sizes | a_sizes_set; // @[Monitor.scala:618:33, :632:31, :707:39] wire [259:0] _inflight_sizes_T_1 = ~d_sizes_clr; // @[Monitor.scala:670:31, :707:56] wire [259:0] _inflight_sizes_T_2 = _inflight_sizes_T & _inflight_sizes_T_1; // @[Monitor.scala:707:{39,54,56}] reg [31:0] watchdog; // @[Monitor.scala:709:27] wire [32:0] _watchdog_T = {1'h0, watchdog} + 33'h1; // @[Monitor.scala:709:27, :714:26] wire [31:0] _watchdog_T_1 = _watchdog_T[31:0]; // @[Monitor.scala:714:26] reg [64:0] inflight_1; // @[Monitor.scala:726:35] wire [64:0] _inflight_T_3 = inflight_1; // @[Monitor.scala:726:35, :814:35] reg [259:0] inflight_opcodes_1; // @[Monitor.scala:727:35] wire [259:0] _inflight_opcodes_T_3 = inflight_opcodes_1; // @[Monitor.scala:727:35, :815:43] reg [259:0] inflight_sizes_1; // @[Monitor.scala:728:35] wire [259:0] _inflight_sizes_T_3 = inflight_sizes_1; // @[Monitor.scala:728:35, :816:41] wire [5:0] _d_first_beats1_decode_T_7 = _d_first_beats1_decode_T_6[5:0]; // @[package.scala:243:{71,76}] wire [5:0] _d_first_beats1_decode_T_8 = ~_d_first_beats1_decode_T_7; // @[package.scala:243:{46,76}] wire [2:0] d_first_beats1_decode_2 = _d_first_beats1_decode_T_8[5:3]; // @[package.scala:243:46] wire [2:0] d_first_beats1_2 = d_first_beats1_opdata_2 ? d_first_beats1_decode_2 : 3'h0; // @[Edges.scala:106:36, :220:59, :221:14] reg [2:0] d_first_counter_2; // @[Edges.scala:229:27] wire [3:0] _d_first_counter1_T_2 = {1'h0, d_first_counter_2} - 4'h1; // @[Edges.scala:229:27, :230:28] wire [2:0] d_first_counter1_2 = _d_first_counter1_T_2[2:0]; // @[Edges.scala:230:28] wire d_first_2 = d_first_counter_2 == 3'h0; // @[Edges.scala:229:27, :231:25] wire _d_first_last_T_4 = d_first_counter_2 == 3'h1; // @[Edges.scala:229:27, :232:25] wire _d_first_last_T_5 = d_first_beats1_2 == 3'h0; // @[Edges.scala:221:14, :232:43] wire d_first_last_2 = _d_first_last_T_4 | _d_first_last_T_5; // @[Edges.scala:232:{25,33,43}] wire d_first_done_2 = d_first_last_2 & _d_first_T_2; // @[Decoupled.scala:51:35] wire [2:0] _d_first_count_T_2 = ~d_first_counter1_2; // @[Edges.scala:230:28, :234:27] wire [2:0] d_first_count_2 = d_first_beats1_2 & _d_first_count_T_2; // @[Edges.scala:221:14, :234:{25,27}] wire [2:0] _d_first_counter_T_2 = d_first_2 ? d_first_beats1_2 : d_first_counter1_2; // @[Edges.scala:221:14, :230:28, :231:25, :236:21] wire [3:0] c_opcode_lookup; // @[Monitor.scala:747:35] wire [3:0] c_size_lookup; // @[Monitor.scala:748:35] wire [259:0] _c_opcode_lookup_T_1 = inflight_opcodes_1 >> _c_opcode_lookup_T; // @[Monitor.scala:727:35, :749:{44,69}] wire [259:0] _c_opcode_lookup_T_6 = {256'h0, _c_opcode_lookup_T_1[3:0]}; // @[Monitor.scala:749:{44,97}] wire [259:0] _c_opcode_lookup_T_7 = {1'h0, _c_opcode_lookup_T_6[259:1]}; // @[Monitor.scala:749:{97,152}] assign c_opcode_lookup = _c_opcode_lookup_T_7[3:0]; // @[Monitor.scala:747:35, :749:{21,152}] wire [259:0] _c_size_lookup_T_1 = inflight_sizes_1 >> _c_size_lookup_T; // @[Monitor.scala:728:35, :750:{42,67}] wire [259:0] _c_size_lookup_T_6 = {256'h0, _c_size_lookup_T_1[3:0]}; // @[Monitor.scala:750:{42,93}] wire [259:0] _c_size_lookup_T_7 = {1'h0, _c_size_lookup_T_6[259:1]}; // @[Monitor.scala:750:{93,146}] assign c_size_lookup = _c_size_lookup_T_7[3:0]; // @[Monitor.scala:748:35, :750:{21,146}] wire [64:0] d_clr_1; // @[Monitor.scala:774:34] wire [64:0] d_clr_wo_ready_1; // @[Monitor.scala:775:34] wire [259:0] d_opcodes_clr_1; // @[Monitor.scala:776:34] wire [259:0] d_sizes_clr_1; // @[Monitor.scala:777:34] wire _T_1224 = io_in_d_valid_0 & d_first_2; // @[Monitor.scala:36:7, :784:26] assign d_clr_wo_ready_1 = _T_1224 & d_release_ack_1 ? _d_clr_wo_ready_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire _T_1206 = _T_1248 & d_first_2 & d_release_ack_1; // @[Decoupled.scala:51:35] assign d_clr_1 = _T_1206 ? _d_clr_T_1[64:0] : 65'h0; // @[OneHot.scala:58:35] wire [1038:0] _d_opcodes_clr_T_11 = 1039'hF << _d_opcodes_clr_T_10; // @[Monitor.scala:790:{76,101}] assign d_opcodes_clr_1 = _T_1206 ? _d_opcodes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:776:34, :788:{25,70,88}, :790:{21,76}] wire [1038:0] _d_sizes_clr_T_11 = 1039'hF << _d_sizes_clr_T_10; // @[Monitor.scala:791:{74,99}] assign d_sizes_clr_1 = _T_1206 ? _d_sizes_clr_T_11[259:0] : 260'h0; // @[Monitor.scala:777:34, :788:{25,70,88}, :791:{21,74}] wire _same_cycle_resp_T_8 = io_in_d_bits_source_0 == 7'h0; // @[Monitor.scala:36:7, :795:113] wire [64:0] _inflight_T_4 = ~d_clr_1; // @[Monitor.scala:774:34, :814:46] wire [64:0] _inflight_T_5 = _inflight_T_3 & _inflight_T_4; // @[Monitor.scala:814:{35,44,46}] wire [259:0] _inflight_opcodes_T_4 = ~d_opcodes_clr_1; // @[Monitor.scala:776:34, :815:62] wire [259:0] _inflight_opcodes_T_5 = _inflight_opcodes_T_3 & _inflight_opcodes_T_4; // @[Monitor.scala:815:{43,60,62}] wire [259:0] _inflight_sizes_T_4 = ~d_sizes_clr_1; // @[Monitor.scala:777:34, :816:58] wire [259:0] _inflight_sizes_T_5 = _inflight_sizes_T_3 & _inflight_sizes_T_4; // @[Monitor.scala:816:{41,56,58}] reg [31:0] watchdog_1; // @[Monitor.scala:818:27]
Generate the Verilog code corresponding to this FIRRTL code module SBToTL : input clock : Clock input reset : Reset output auto : { out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}}} output io : { flip rdEn : UInt<1>, flip wrEn : UInt<1>, flip addrIn : UInt<128>, flip dataIn : UInt<128>, flip sizeIn : UInt<3>, rdLegal : UInt<1>, wrLegal : UInt<1>, rdDone : UInt<1>, wrDone : UInt<1>, respError : UInt<1>, dataOut : UInt<8>, rdLoad : UInt<1>[8], sbStateOut : UInt<3>} input rf_reset : Reset wire nodeOut : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<8>, corrupt : UInt<1>}}} invalidate nodeOut.d.bits.corrupt invalidate nodeOut.d.bits.data invalidate nodeOut.d.bits.denied invalidate nodeOut.d.bits.sink invalidate nodeOut.d.bits.source invalidate nodeOut.d.bits.size invalidate nodeOut.d.bits.param invalidate nodeOut.d.bits.opcode invalidate nodeOut.d.valid invalidate nodeOut.d.ready invalidate nodeOut.a.bits.corrupt invalidate nodeOut.a.bits.data invalidate nodeOut.a.bits.mask invalidate nodeOut.a.bits.user.amba_prot.fetch invalidate nodeOut.a.bits.user.amba_prot.secure invalidate nodeOut.a.bits.user.amba_prot.privileged invalidate nodeOut.a.bits.user.amba_prot.writealloc invalidate nodeOut.a.bits.user.amba_prot.readalloc invalidate nodeOut.a.bits.user.amba_prot.modifiable invalidate nodeOut.a.bits.user.amba_prot.bufferable invalidate nodeOut.a.bits.address invalidate nodeOut.a.bits.source invalidate nodeOut.a.bits.size invalidate nodeOut.a.bits.param invalidate nodeOut.a.bits.opcode invalidate nodeOut.a.valid invalidate nodeOut.a.ready connect auto.out, nodeOut regreset sbState : UInt, clock, reset, UInt<1>(0h0) inst d_q of Queue2_TLBundleD_a32d8s1k3z4u connect d_q.clock, clock connect d_q.reset, reset connect d_q.io.enq.valid, nodeOut.d.valid connect d_q.io.enq.bits.corrupt, nodeOut.d.bits.corrupt connect d_q.io.enq.bits.data, nodeOut.d.bits.data connect d_q.io.enq.bits.denied, nodeOut.d.bits.denied connect d_q.io.enq.bits.sink, nodeOut.d.bits.sink connect d_q.io.enq.bits.source, nodeOut.d.bits.source connect d_q.io.enq.bits.size, nodeOut.d.bits.size connect d_q.io.enq.bits.param, nodeOut.d.bits.param connect d_q.io.enq.bits.opcode, nodeOut.d.bits.opcode connect nodeOut.d.ready, d_q.io.enq.ready node _q_io_deq_ready_T = eq(sbState, UInt<2>(0h3)) node _q_io_deq_ready_T_1 = eq(sbState, UInt<3>(0h4)) node _q_io_deq_ready_T_2 = or(_q_io_deq_ready_T, _q_io_deq_ready_T_1) connect d_q.io.deq.ready, _q_io_deq_ready_T_2 wire muxedData : UInt<8> connect muxedData, UInt<8>(0h0) regreset counter : UInt<4>, clock, reset, UInt<4>(0h0) wire vecData : UInt<8>[8] node _vecData_0_T = bits(io.dataIn, 7, 0) connect vecData[0], _vecData_0_T node _vecData_1_T = bits(io.dataIn, 15, 8) connect vecData[1], _vecData_1_T node _vecData_2_T = bits(io.dataIn, 23, 16) connect vecData[2], _vecData_2_T node _vecData_3_T = bits(io.dataIn, 31, 24) connect vecData[3], _vecData_3_T node _vecData_4_T = bits(io.dataIn, 39, 32) connect vecData[4], _vecData_4_T node _vecData_5_T = bits(io.dataIn, 47, 40) connect vecData[5], _vecData_5_T node _vecData_6_T = bits(io.dataIn, 55, 48) connect vecData[6], _vecData_6_T node _vecData_7_T = bits(io.dataIn, 63, 56) connect vecData[7], _vecData_7_T node _muxedData_T = bits(counter, 2, 0) connect muxedData, vecData[_muxedData_T] node _rdLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _rdLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _rdLegal_addr_T_2 = and(_rdLegal_addr_T, _rdLegal_addr_T_1) node _rdLegal_addr_T_3 = or(UInt<1>(0h1), _rdLegal_addr_T_2) node _rdLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _rdLegal_addr_T_5 = cvt(_rdLegal_addr_T_4) node _rdLegal_addr_T_6 = and(_rdLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _rdLegal_addr_T_7 = asSInt(_rdLegal_addr_T_6) node _rdLegal_addr_T_8 = eq(_rdLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000)) node _rdLegal_addr_T_10 = cvt(_rdLegal_addr_T_9) node _rdLegal_addr_T_11 = and(_rdLegal_addr_T_10, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_12 = asSInt(_rdLegal_addr_T_11) node _rdLegal_addr_T_13 = eq(_rdLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_14 = xor(io.addrIn, UInt<15>(0h4000)) node _rdLegal_addr_T_15 = cvt(_rdLegal_addr_T_14) node _rdLegal_addr_T_16 = and(_rdLegal_addr_T_15, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_17 = asSInt(_rdLegal_addr_T_16) node _rdLegal_addr_T_18 = eq(_rdLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_19 = xor(io.addrIn, UInt<17>(0h10000)) node _rdLegal_addr_T_20 = cvt(_rdLegal_addr_T_19) node _rdLegal_addr_T_21 = and(_rdLegal_addr_T_20, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_22 = asSInt(_rdLegal_addr_T_21) node _rdLegal_addr_T_23 = eq(_rdLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_24 = xor(io.addrIn, UInt<21>(0h100000)) node _rdLegal_addr_T_25 = cvt(_rdLegal_addr_T_24) node _rdLegal_addr_T_26 = and(_rdLegal_addr_T_25, asSInt(UInt<18>(0h2f000))) node _rdLegal_addr_T_27 = asSInt(_rdLegal_addr_T_26) node _rdLegal_addr_T_28 = eq(_rdLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _rdLegal_addr_T_30 = cvt(_rdLegal_addr_T_29) node _rdLegal_addr_T_31 = and(_rdLegal_addr_T_30, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_32 = asSInt(_rdLegal_addr_T_31) node _rdLegal_addr_T_33 = eq(_rdLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_34 = xor(io.addrIn, UInt<26>(0h2010000)) node _rdLegal_addr_T_35 = cvt(_rdLegal_addr_T_34) node _rdLegal_addr_T_36 = and(_rdLegal_addr_T_35, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_37 = asSInt(_rdLegal_addr_T_36) node _rdLegal_addr_T_38 = eq(_rdLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _rdLegal_addr_T_40 = cvt(_rdLegal_addr_T_39) node _rdLegal_addr_T_41 = and(_rdLegal_addr_T_40, asSInt(UInt<17>(0h10000))) node _rdLegal_addr_T_42 = asSInt(_rdLegal_addr_T_41) node _rdLegal_addr_T_43 = eq(_rdLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_44 = xor(io.addrIn, UInt<28>(0hc000000)) node _rdLegal_addr_T_45 = cvt(_rdLegal_addr_T_44) node _rdLegal_addr_T_46 = and(_rdLegal_addr_T_45, asSInt(UInt<27>(0h4000000))) node _rdLegal_addr_T_47 = asSInt(_rdLegal_addr_T_46) node _rdLegal_addr_T_48 = eq(_rdLegal_addr_T_47, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_49 = xor(io.addrIn, UInt<29>(0h10020000)) node _rdLegal_addr_T_50 = cvt(_rdLegal_addr_T_49) node _rdLegal_addr_T_51 = and(_rdLegal_addr_T_50, asSInt(UInt<13>(0h1000))) node _rdLegal_addr_T_52 = asSInt(_rdLegal_addr_T_51) node _rdLegal_addr_T_53 = eq(_rdLegal_addr_T_52, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_54 = xor(io.addrIn, UInt<32>(0h80000000)) node _rdLegal_addr_T_55 = cvt(_rdLegal_addr_T_54) node _rdLegal_addr_T_56 = and(_rdLegal_addr_T_55, asSInt(UInt<29>(0h10000000))) node _rdLegal_addr_T_57 = asSInt(_rdLegal_addr_T_56) node _rdLegal_addr_T_58 = eq(_rdLegal_addr_T_57, asSInt(UInt<1>(0h0))) node _rdLegal_addr_T_59 = or(_rdLegal_addr_T_8, _rdLegal_addr_T_13) node _rdLegal_addr_T_60 = or(_rdLegal_addr_T_59, _rdLegal_addr_T_18) node _rdLegal_addr_T_61 = or(_rdLegal_addr_T_60, _rdLegal_addr_T_23) node _rdLegal_addr_T_62 = or(_rdLegal_addr_T_61, _rdLegal_addr_T_28) node _rdLegal_addr_T_63 = or(_rdLegal_addr_T_62, _rdLegal_addr_T_33) node _rdLegal_addr_T_64 = or(_rdLegal_addr_T_63, _rdLegal_addr_T_38) node _rdLegal_addr_T_65 = or(_rdLegal_addr_T_64, _rdLegal_addr_T_43) node _rdLegal_addr_T_66 = or(_rdLegal_addr_T_65, _rdLegal_addr_T_48) node _rdLegal_addr_T_67 = or(_rdLegal_addr_T_66, _rdLegal_addr_T_53) node _rdLegal_addr_T_68 = or(_rdLegal_addr_T_67, _rdLegal_addr_T_58) node _rdLegal_addr_T_69 = and(_rdLegal_addr_T_3, _rdLegal_addr_T_68) node rdLegal_addr = or(UInt<1>(0h0), _rdLegal_addr_T_69) node _wrLegal_addr_T = leq(UInt<1>(0h0), io.sizeIn) node _wrLegal_addr_T_1 = leq(io.sizeIn, UInt<2>(0h3)) node _wrLegal_addr_T_2 = and(_wrLegal_addr_T, _wrLegal_addr_T_1) node _wrLegal_addr_T_3 = or(UInt<1>(0h1), _wrLegal_addr_T_2) node _wrLegal_addr_T_4 = xor(io.addrIn, UInt<1>(0h0)) node _wrLegal_addr_T_5 = cvt(_wrLegal_addr_T_4) node _wrLegal_addr_T_6 = and(_wrLegal_addr_T_5, asSInt(UInt<14>(0h2000))) node _wrLegal_addr_T_7 = asSInt(_wrLegal_addr_T_6) node _wrLegal_addr_T_8 = eq(_wrLegal_addr_T_7, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_9 = xor(io.addrIn, UInt<14>(0h3000)) node _wrLegal_addr_T_10 = cvt(_wrLegal_addr_T_9) node _wrLegal_addr_T_11 = and(_wrLegal_addr_T_10, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_12 = asSInt(_wrLegal_addr_T_11) node _wrLegal_addr_T_13 = eq(_wrLegal_addr_T_12, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_14 = xor(io.addrIn, UInt<15>(0h4000)) node _wrLegal_addr_T_15 = cvt(_wrLegal_addr_T_14) node _wrLegal_addr_T_16 = and(_wrLegal_addr_T_15, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_17 = asSInt(_wrLegal_addr_T_16) node _wrLegal_addr_T_18 = eq(_wrLegal_addr_T_17, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_19 = xor(io.addrIn, UInt<21>(0h100000)) node _wrLegal_addr_T_20 = cvt(_wrLegal_addr_T_19) node _wrLegal_addr_T_21 = and(_wrLegal_addr_T_20, asSInt(UInt<18>(0h2f000))) node _wrLegal_addr_T_22 = asSInt(_wrLegal_addr_T_21) node _wrLegal_addr_T_23 = eq(_wrLegal_addr_T_22, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_24 = xor(io.addrIn, UInt<26>(0h2000000)) node _wrLegal_addr_T_25 = cvt(_wrLegal_addr_T_24) node _wrLegal_addr_T_26 = and(_wrLegal_addr_T_25, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_27 = asSInt(_wrLegal_addr_T_26) node _wrLegal_addr_T_28 = eq(_wrLegal_addr_T_27, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_29 = xor(io.addrIn, UInt<26>(0h2010000)) node _wrLegal_addr_T_30 = cvt(_wrLegal_addr_T_29) node _wrLegal_addr_T_31 = and(_wrLegal_addr_T_30, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_32 = asSInt(_wrLegal_addr_T_31) node _wrLegal_addr_T_33 = eq(_wrLegal_addr_T_32, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_34 = xor(io.addrIn, UInt<28>(0h8000000)) node _wrLegal_addr_T_35 = cvt(_wrLegal_addr_T_34) node _wrLegal_addr_T_36 = and(_wrLegal_addr_T_35, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_37 = asSInt(_wrLegal_addr_T_36) node _wrLegal_addr_T_38 = eq(_wrLegal_addr_T_37, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_39 = xor(io.addrIn, UInt<28>(0hc000000)) node _wrLegal_addr_T_40 = cvt(_wrLegal_addr_T_39) node _wrLegal_addr_T_41 = and(_wrLegal_addr_T_40, asSInt(UInt<27>(0h4000000))) node _wrLegal_addr_T_42 = asSInt(_wrLegal_addr_T_41) node _wrLegal_addr_T_43 = eq(_wrLegal_addr_T_42, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_44 = xor(io.addrIn, UInt<29>(0h10020000)) node _wrLegal_addr_T_45 = cvt(_wrLegal_addr_T_44) node _wrLegal_addr_T_46 = and(_wrLegal_addr_T_45, asSInt(UInt<13>(0h1000))) node _wrLegal_addr_T_47 = asSInt(_wrLegal_addr_T_46) node _wrLegal_addr_T_48 = eq(_wrLegal_addr_T_47, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_49 = xor(io.addrIn, UInt<32>(0h80000000)) node _wrLegal_addr_T_50 = cvt(_wrLegal_addr_T_49) node _wrLegal_addr_T_51 = and(_wrLegal_addr_T_50, asSInt(UInt<29>(0h10000000))) node _wrLegal_addr_T_52 = asSInt(_wrLegal_addr_T_51) node _wrLegal_addr_T_53 = eq(_wrLegal_addr_T_52, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_54 = or(_wrLegal_addr_T_8, _wrLegal_addr_T_13) node _wrLegal_addr_T_55 = or(_wrLegal_addr_T_54, _wrLegal_addr_T_18) node _wrLegal_addr_T_56 = or(_wrLegal_addr_T_55, _wrLegal_addr_T_23) node _wrLegal_addr_T_57 = or(_wrLegal_addr_T_56, _wrLegal_addr_T_28) node _wrLegal_addr_T_58 = or(_wrLegal_addr_T_57, _wrLegal_addr_T_33) node _wrLegal_addr_T_59 = or(_wrLegal_addr_T_58, _wrLegal_addr_T_38) node _wrLegal_addr_T_60 = or(_wrLegal_addr_T_59, _wrLegal_addr_T_43) node _wrLegal_addr_T_61 = or(_wrLegal_addr_T_60, _wrLegal_addr_T_48) node _wrLegal_addr_T_62 = or(_wrLegal_addr_T_61, _wrLegal_addr_T_53) node _wrLegal_addr_T_63 = and(_wrLegal_addr_T_3, _wrLegal_addr_T_62) node _wrLegal_addr_T_64 = or(UInt<1>(0h0), UInt<1>(0h0)) node _wrLegal_addr_T_65 = xor(io.addrIn, UInt<17>(0h10000)) node _wrLegal_addr_T_66 = cvt(_wrLegal_addr_T_65) node _wrLegal_addr_T_67 = and(_wrLegal_addr_T_66, asSInt(UInt<17>(0h10000))) node _wrLegal_addr_T_68 = asSInt(_wrLegal_addr_T_67) node _wrLegal_addr_T_69 = eq(_wrLegal_addr_T_68, asSInt(UInt<1>(0h0))) node _wrLegal_addr_T_70 = and(_wrLegal_addr_T_64, _wrLegal_addr_T_69) node _wrLegal_addr_T_71 = or(UInt<1>(0h0), _wrLegal_addr_T_63) node wrLegal_addr = or(_wrLegal_addr_T_71, _wrLegal_addr_T_70) node _gbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _gbits_legal_T_2 = and(_gbits_legal_T, _gbits_legal_T_1) node _gbits_legal_T_3 = or(UInt<1>(0h0), _gbits_legal_T_2) node _gbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _gbits_legal_T_5 = cvt(_gbits_legal_T_4) node _gbits_legal_T_6 = and(_gbits_legal_T_5, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_7 = asSInt(_gbits_legal_T_6) node _gbits_legal_T_8 = eq(_gbits_legal_T_7, asSInt(UInt<1>(0h0))) node _gbits_legal_T_9 = and(_gbits_legal_T_3, _gbits_legal_T_8) node _gbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _gbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _gbits_legal_T_12 = and(_gbits_legal_T_10, _gbits_legal_T_11) node _gbits_legal_T_13 = or(UInt<1>(0h0), _gbits_legal_T_12) node _gbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _gbits_legal_T_15 = cvt(_gbits_legal_T_14) node _gbits_legal_T_16 = and(_gbits_legal_T_15, asSInt(UInt<33>(0h9a012000))) node _gbits_legal_T_17 = asSInt(_gbits_legal_T_16) node _gbits_legal_T_18 = eq(_gbits_legal_T_17, asSInt(UInt<1>(0h0))) node _gbits_legal_T_19 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_20 = cvt(_gbits_legal_T_19) node _gbits_legal_T_21 = and(_gbits_legal_T_20, asSInt(UInt<33>(0h98013000))) node _gbits_legal_T_22 = asSInt(_gbits_legal_T_21) node _gbits_legal_T_23 = eq(_gbits_legal_T_22, asSInt(UInt<1>(0h0))) node _gbits_legal_T_24 = xor(io.addrIn, UInt<17>(0h10000)) node _gbits_legal_T_25 = cvt(_gbits_legal_T_24) node _gbits_legal_T_26 = and(_gbits_legal_T_25, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_27 = asSInt(_gbits_legal_T_26) node _gbits_legal_T_28 = eq(_gbits_legal_T_27, asSInt(UInt<1>(0h0))) node _gbits_legal_T_29 = xor(io.addrIn, UInt<26>(0h2000000)) node _gbits_legal_T_30 = cvt(_gbits_legal_T_29) node _gbits_legal_T_31 = and(_gbits_legal_T_30, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_32 = asSInt(_gbits_legal_T_31) node _gbits_legal_T_33 = eq(_gbits_legal_T_32, asSInt(UInt<1>(0h0))) node _gbits_legal_T_34 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_35 = cvt(_gbits_legal_T_34) node _gbits_legal_T_36 = and(_gbits_legal_T_35, asSInt(UInt<33>(0h98000000))) node _gbits_legal_T_37 = asSInt(_gbits_legal_T_36) node _gbits_legal_T_38 = eq(_gbits_legal_T_37, asSInt(UInt<1>(0h0))) node _gbits_legal_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _gbits_legal_T_40 = cvt(_gbits_legal_T_39) node _gbits_legal_T_41 = and(_gbits_legal_T_40, asSInt(UInt<33>(0h9a010000))) node _gbits_legal_T_42 = asSInt(_gbits_legal_T_41) node _gbits_legal_T_43 = eq(_gbits_legal_T_42, asSInt(UInt<1>(0h0))) node _gbits_legal_T_44 = xor(io.addrIn, UInt<29>(0h10000000)) node _gbits_legal_T_45 = cvt(_gbits_legal_T_44) node _gbits_legal_T_46 = and(_gbits_legal_T_45, asSInt(UInt<33>(0h9a013000))) node _gbits_legal_T_47 = asSInt(_gbits_legal_T_46) node _gbits_legal_T_48 = eq(_gbits_legal_T_47, asSInt(UInt<1>(0h0))) node _gbits_legal_T_49 = xor(io.addrIn, UInt<32>(0h80000000)) node _gbits_legal_T_50 = cvt(_gbits_legal_T_49) node _gbits_legal_T_51 = and(_gbits_legal_T_50, asSInt(UInt<33>(0h90000000))) node _gbits_legal_T_52 = asSInt(_gbits_legal_T_51) node _gbits_legal_T_53 = eq(_gbits_legal_T_52, asSInt(UInt<1>(0h0))) node _gbits_legal_T_54 = or(_gbits_legal_T_18, _gbits_legal_T_23) node _gbits_legal_T_55 = or(_gbits_legal_T_54, _gbits_legal_T_28) node _gbits_legal_T_56 = or(_gbits_legal_T_55, _gbits_legal_T_33) node _gbits_legal_T_57 = or(_gbits_legal_T_56, _gbits_legal_T_38) node _gbits_legal_T_58 = or(_gbits_legal_T_57, _gbits_legal_T_43) node _gbits_legal_T_59 = or(_gbits_legal_T_58, _gbits_legal_T_48) node _gbits_legal_T_60 = or(_gbits_legal_T_59, _gbits_legal_T_53) node _gbits_legal_T_61 = and(_gbits_legal_T_13, _gbits_legal_T_60) node _gbits_legal_T_62 = or(UInt<1>(0h0), _gbits_legal_T_9) node gbits_legal = or(_gbits_legal_T_62, _gbits_legal_T_61) wire gbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect gbits.opcode, UInt<3>(0h4) connect gbits.param, UInt<1>(0h0) connect gbits.size, io.sizeIn connect gbits.source, UInt<1>(0h0) connect gbits.address, io.addrIn invalidate gbits.user.amba_prot.fetch invalidate gbits.user.amba_prot.secure invalidate gbits.user.amba_prot.privileged invalidate gbits.user.amba_prot.writealloc invalidate gbits.user.amba_prot.readalloc invalidate gbits.user.amba_prot.modifiable invalidate gbits.user.amba_prot.bufferable node _gbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node gbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect gbits.mask, UInt<1>(0h1) invalidate gbits.data connect gbits.corrupt, UInt<1>(0h0) node _pfbits_legal_T = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_1 = leq(io.sizeIn, UInt<4>(0hc)) node _pfbits_legal_T_2 = and(_pfbits_legal_T, _pfbits_legal_T_1) node _pfbits_legal_T_3 = or(UInt<1>(0h0), _pfbits_legal_T_2) node _pfbits_legal_T_4 = xor(io.addrIn, UInt<14>(0h3000)) node _pfbits_legal_T_5 = cvt(_pfbits_legal_T_4) node _pfbits_legal_T_6 = and(_pfbits_legal_T_5, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_7 = asSInt(_pfbits_legal_T_6) node _pfbits_legal_T_8 = eq(_pfbits_legal_T_7, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_9 = and(_pfbits_legal_T_3, _pfbits_legal_T_8) node _pfbits_legal_T_10 = leq(UInt<1>(0h0), io.sizeIn) node _pfbits_legal_T_11 = leq(io.sizeIn, UInt<3>(0h6)) node _pfbits_legal_T_12 = and(_pfbits_legal_T_10, _pfbits_legal_T_11) node _pfbits_legal_T_13 = or(UInt<1>(0h0), _pfbits_legal_T_12) node _pfbits_legal_T_14 = xor(io.addrIn, UInt<1>(0h0)) node _pfbits_legal_T_15 = cvt(_pfbits_legal_T_14) node _pfbits_legal_T_16 = and(_pfbits_legal_T_15, asSInt(UInt<33>(0h9a112000))) node _pfbits_legal_T_17 = asSInt(_pfbits_legal_T_16) node _pfbits_legal_T_18 = eq(_pfbits_legal_T_17, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_19 = xor(io.addrIn, UInt<21>(0h100000)) node _pfbits_legal_T_20 = cvt(_pfbits_legal_T_19) node _pfbits_legal_T_21 = and(_pfbits_legal_T_20, asSInt(UInt<33>(0h9a103000))) node _pfbits_legal_T_22 = asSInt(_pfbits_legal_T_21) node _pfbits_legal_T_23 = eq(_pfbits_legal_T_22, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_24 = xor(io.addrIn, UInt<26>(0h2000000)) node _pfbits_legal_T_25 = cvt(_pfbits_legal_T_24) node _pfbits_legal_T_26 = and(_pfbits_legal_T_25, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_27 = asSInt(_pfbits_legal_T_26) node _pfbits_legal_T_28 = eq(_pfbits_legal_T_27, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_29 = xor(io.addrIn, UInt<26>(0h2010000)) node _pfbits_legal_T_30 = cvt(_pfbits_legal_T_29) node _pfbits_legal_T_31 = and(_pfbits_legal_T_30, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_32 = asSInt(_pfbits_legal_T_31) node _pfbits_legal_T_33 = eq(_pfbits_legal_T_32, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_34 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_35 = cvt(_pfbits_legal_T_34) node _pfbits_legal_T_36 = and(_pfbits_legal_T_35, asSInt(UInt<33>(0h98000000))) node _pfbits_legal_T_37 = asSInt(_pfbits_legal_T_36) node _pfbits_legal_T_38 = eq(_pfbits_legal_T_37, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_39 = xor(io.addrIn, UInt<28>(0h8000000)) node _pfbits_legal_T_40 = cvt(_pfbits_legal_T_39) node _pfbits_legal_T_41 = and(_pfbits_legal_T_40, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_42 = asSInt(_pfbits_legal_T_41) node _pfbits_legal_T_43 = eq(_pfbits_legal_T_42, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_44 = xor(io.addrIn, UInt<29>(0h10000000)) node _pfbits_legal_T_45 = cvt(_pfbits_legal_T_44) node _pfbits_legal_T_46 = and(_pfbits_legal_T_45, asSInt(UInt<33>(0h9a113000))) node _pfbits_legal_T_47 = asSInt(_pfbits_legal_T_46) node _pfbits_legal_T_48 = eq(_pfbits_legal_T_47, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_49 = xor(io.addrIn, UInt<32>(0h80000000)) node _pfbits_legal_T_50 = cvt(_pfbits_legal_T_49) node _pfbits_legal_T_51 = and(_pfbits_legal_T_50, asSInt(UInt<33>(0h90000000))) node _pfbits_legal_T_52 = asSInt(_pfbits_legal_T_51) node _pfbits_legal_T_53 = eq(_pfbits_legal_T_52, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_54 = or(_pfbits_legal_T_18, _pfbits_legal_T_23) node _pfbits_legal_T_55 = or(_pfbits_legal_T_54, _pfbits_legal_T_28) node _pfbits_legal_T_56 = or(_pfbits_legal_T_55, _pfbits_legal_T_33) node _pfbits_legal_T_57 = or(_pfbits_legal_T_56, _pfbits_legal_T_38) node _pfbits_legal_T_58 = or(_pfbits_legal_T_57, _pfbits_legal_T_43) node _pfbits_legal_T_59 = or(_pfbits_legal_T_58, _pfbits_legal_T_48) node _pfbits_legal_T_60 = or(_pfbits_legal_T_59, _pfbits_legal_T_53) node _pfbits_legal_T_61 = and(_pfbits_legal_T_13, _pfbits_legal_T_60) node _pfbits_legal_T_62 = or(UInt<1>(0h0), UInt<1>(0h0)) node _pfbits_legal_T_63 = xor(io.addrIn, UInt<17>(0h10000)) node _pfbits_legal_T_64 = cvt(_pfbits_legal_T_63) node _pfbits_legal_T_65 = and(_pfbits_legal_T_64, asSInt(UInt<33>(0h9a110000))) node _pfbits_legal_T_66 = asSInt(_pfbits_legal_T_65) node _pfbits_legal_T_67 = eq(_pfbits_legal_T_66, asSInt(UInt<1>(0h0))) node _pfbits_legal_T_68 = and(_pfbits_legal_T_62, _pfbits_legal_T_67) node _pfbits_legal_T_69 = or(UInt<1>(0h0), _pfbits_legal_T_9) node _pfbits_legal_T_70 = or(_pfbits_legal_T_69, _pfbits_legal_T_61) node pfbits_legal = or(_pfbits_legal_T_70, _pfbits_legal_T_68) wire pfbits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>} connect pfbits.opcode, UInt<1>(0h0) connect pfbits.param, UInt<1>(0h0) connect pfbits.size, io.sizeIn connect pfbits.source, UInt<1>(0h0) connect pfbits.address, io.addrIn invalidate pfbits.user.amba_prot.fetch invalidate pfbits.user.amba_prot.secure invalidate pfbits.user.amba_prot.privileged invalidate pfbits.user.amba_prot.writealloc invalidate pfbits.user.amba_prot.readalloc invalidate pfbits.user.amba_prot.modifiable invalidate pfbits.user.amba_prot.bufferable node _pfbits_a_mask_sizeOH_T = or(io.sizeIn, UInt<1>(0h0)) node pfbits_a_mask_sizeOH = or(UInt<1>(0h1), UInt<1>(0h1)) connect pfbits.mask, UInt<1>(0h1) connect pfbits.data, muxedData connect pfbits.corrupt, UInt<1>(0h0) connect io.rdLegal, rdLegal_addr connect io.wrLegal, wrLegal_addr connect io.sbStateOut, sbState node _T = eq(sbState, UInt<1>(0h1)) when _T : connect nodeOut.a.bits, gbits else : connect nodeOut.a.bits, pfbits connect nodeOut.a.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect nodeOut.a.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect nodeOut.a.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect nodeOut.a.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect nodeOut.a.bits.user.amba_prot.privileged, UInt<1>(0h1) connect nodeOut.a.bits.user.amba_prot.secure, UInt<1>(0h1) connect nodeOut.a.bits.user.amba_prot.fetch, UInt<1>(0h0) node respError = or(d_q.io.deq.bits.denied, d_q.io.deq.bits.corrupt) connect io.respError, respError node _wrTxValid_T = eq(sbState, UInt<2>(0h2)) node _wrTxValid_T_1 = and(_wrTxValid_T, nodeOut.a.valid) node wrTxValid = and(_wrTxValid_T_1, nodeOut.a.ready) node _rdTxValid_T = eq(sbState, UInt<2>(0h3)) node _rdTxValid_T_1 = and(_rdTxValid_T, d_q.io.deq.valid) node rdTxValid = and(_rdTxValid_T_1, d_q.io.deq.ready) node _txLast_T = dshl(UInt<1>(0h1), io.sizeIn) node _txLast_T_1 = sub(_txLast_T, UInt<1>(0h1)) node _txLast_T_2 = tail(_txLast_T_1, 1) node txLast = eq(counter, _txLast_T_2) node _counter_T = or(wrTxValid, rdTxValid) node _counter_T_1 = and(_counter_T, txLast) node _counter_T_2 = or(wrTxValid, rdTxValid) node _counter_T_3 = add(counter, UInt<1>(0h1)) node _counter_T_4 = tail(_counter_T_3, 1) node _counter_T_5 = mux(_counter_T_2, _counter_T_4, counter) node _counter_T_6 = mux(_counter_T_1, UInt<1>(0h0), _counter_T_5) connect counter, _counter_T_6 node _io_rdLoad_0_T = eq(counter, UInt<1>(0h0)) node _io_rdLoad_0_T_1 = and(rdTxValid, _io_rdLoad_0_T) connect io.rdLoad[0], _io_rdLoad_0_T_1 node _io_rdLoad_1_T = eq(counter, UInt<1>(0h1)) node _io_rdLoad_1_T_1 = and(rdTxValid, _io_rdLoad_1_T) connect io.rdLoad[1], _io_rdLoad_1_T_1 node _io_rdLoad_2_T = eq(counter, UInt<2>(0h2)) node _io_rdLoad_2_T_1 = and(rdTxValid, _io_rdLoad_2_T) connect io.rdLoad[2], _io_rdLoad_2_T_1 node _io_rdLoad_3_T = eq(counter, UInt<2>(0h3)) node _io_rdLoad_3_T_1 = and(rdTxValid, _io_rdLoad_3_T) connect io.rdLoad[3], _io_rdLoad_3_T_1 node _io_rdLoad_4_T = eq(counter, UInt<3>(0h4)) node _io_rdLoad_4_T_1 = and(rdTxValid, _io_rdLoad_4_T) connect io.rdLoad[4], _io_rdLoad_4_T_1 node _io_rdLoad_5_T = eq(counter, UInt<3>(0h5)) node _io_rdLoad_5_T_1 = and(rdTxValid, _io_rdLoad_5_T) connect io.rdLoad[5], _io_rdLoad_5_T_1 node _io_rdLoad_6_T = eq(counter, UInt<3>(0h6)) node _io_rdLoad_6_T_1 = and(rdTxValid, _io_rdLoad_6_T) connect io.rdLoad[6], _io_rdLoad_6_T_1 node _io_rdLoad_7_T = eq(counter, UInt<3>(0h7)) node _io_rdLoad_7_T_1 = and(rdTxValid, _io_rdLoad_7_T) connect io.rdLoad[7], _io_rdLoad_7_T_1 node _T_1 = eq(sbState, UInt<1>(0h0)) when _T_1 : node _sbState_T = and(io.rdEn, io.rdLegal) node _sbState_T_1 = and(io.wrEn, io.wrLegal) node _sbState_T_2 = mux(_sbState_T_1, UInt<2>(0h2), sbState) node _sbState_T_3 = mux(_sbState_T, UInt<1>(0h1), _sbState_T_2) connect sbState, _sbState_T_3 else : node _T_2 = eq(sbState, UInt<1>(0h1)) when _T_2 : node _sbState_T_4 = and(nodeOut.a.valid, nodeOut.a.ready) node _sbState_T_5 = mux(_sbState_T_4, UInt<2>(0h3), sbState) connect sbState, _sbState_T_5 else : node _T_3 = eq(sbState, UInt<2>(0h2)) when _T_3 : node _sbState_T_6 = and(wrTxValid, txLast) node _sbState_T_7 = mux(_sbState_T_6, UInt<3>(0h4), sbState) connect sbState, _sbState_T_7 else : node _T_4 = eq(sbState, UInt<2>(0h3)) when _T_4 : node _sbState_T_8 = and(rdTxValid, txLast) node _sbState_T_9 = mux(_sbState_T_8, UInt<1>(0h0), sbState) connect sbState, _sbState_T_9 else : node _T_5 = eq(sbState, UInt<3>(0h4)) when _T_5 : node _sbState_T_10 = and(d_q.io.deq.valid, d_q.io.deq.ready) node _sbState_T_11 = mux(_sbState_T_10, UInt<1>(0h0), sbState) connect sbState, _sbState_T_11 node _io_rdDone_T = and(rdTxValid, txLast) connect io.rdDone, _io_rdDone_T node _io_wrDone_T = eq(sbState, UInt<3>(0h4)) node _io_wrDone_T_1 = and(_io_wrDone_T, d_q.io.deq.valid) node _io_wrDone_T_2 = and(_io_wrDone_T_1, d_q.io.deq.ready) connect io.wrDone, _io_wrDone_T_2 connect io.dataOut, d_q.io.deq.bits.data node _nodeOut_a_valid_T = eq(sbState, UInt<1>(0h1)) node _nodeOut_a_valid_T_1 = eq(sbState, UInt<2>(0h2)) node _nodeOut_a_valid_T_2 = or(_nodeOut_a_valid_T, _nodeOut_a_valid_T_1) connect nodeOut.a.valid, _nodeOut_a_valid_T_2 wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<8>(0h0) connect _WIRE.bits.mask, UInt<1>(0h0) connect _WIRE.bits.address, UInt<32>(0h0) connect _WIRE.bits.source, UInt<1>(0h0) connect _WIRE.bits.size, UInt<4>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<4>, source : UInt<1>, address : UInt<32>, mask : UInt<1>, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.ready, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<8>(0h0) connect _WIRE_2.bits.user.amba_prot.fetch, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.secure, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.privileged, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.writealloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.readalloc, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.modifiable, UInt<1>(0h0) connect _WIRE_2.bits.user.amba_prot.bufferable, UInt<1>(0h0) connect _WIRE_2.bits.address, UInt<32>(0h0) connect _WIRE_2.bits.source, UInt<1>(0h0) connect _WIRE_2.bits.size, UInt<4>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<4>, source : UInt<1>, address : UInt<32>, user : { amba_prot : { bufferable : UInt<1>, modifiable : UInt<1>, readalloc : UInt<1>, writealloc : UInt<1>, privileged : UInt<1>, secure : UInt<1>, fetch : UInt<1>}}, echo : { }, data : UInt<8>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.valid, UInt<1>(0h0) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_4.bits.sink, UInt<3>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.valid, UInt<1>(0h0) node _T_6 = eq(sbState, UInt<1>(0h0)) node _T_7 = eq(sbState, UInt<1>(0h1)) node _T_8 = or(_T_6, _T_7) node _T_9 = eq(sbState, UInt<2>(0h2)) node _T_10 = or(_T_8, _T_9) node _T_11 = eq(sbState, UInt<2>(0h3)) node _T_12 = or(_T_10, _T_11) node _T_13 = eq(sbState, UInt<3>(0h4)) node _T_14 = or(_T_12, _T_13) node _T_15 = asUInt(reset) node _T_16 = eq(_T_15, UInt<1>(0h0)) when _T_16 : node _T_17 = eq(_T_14, UInt<1>(0h0)) when _T_17 : printf(clock, UInt<1>(0h1), "Assertion failed: SBA state machine in undefined state\n at SBA.scala:373 assert (sbState === Idle.id.U ||\n") : printf assert(clock, _T_14, UInt<1>(0h1), "") : assert node _T_18 = eq(sbState, UInt<1>(0h0)) node _T_19 = eq(sbState, UInt<1>(0h1)) node _T_20 = eq(sbState, UInt<2>(0h2)) node _T_21 = eq(sbState, UInt<2>(0h3)) node _T_22 = eq(sbState, UInt<3>(0h4)) node _T_23 = eq(io.rdLegal, UInt<1>(0h0)) node _T_24 = and(io.rdEn, _T_23) node _T_25 = eq(io.wrLegal, UInt<1>(0h0)) node _T_26 = and(io.wrEn, _T_25) extmodule plusarg_reader_101 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_102 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module SBToTL( // @[SBA.scala:273:9] input clock, // @[SBA.scala:273:9] input reset, // @[SBA.scala:273:9] input auto_out_a_ready, // @[LazyModuleImp.scala:107:25] output auto_out_a_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_out_a_bits_opcode, // @[LazyModuleImp.scala:107:25] output [3:0] auto_out_a_bits_size, // @[LazyModuleImp.scala:107:25] output [31:0] auto_out_a_bits_address, // @[LazyModuleImp.scala:107:25] output [7:0] auto_out_a_bits_data, // @[LazyModuleImp.scala:107:25] output auto_out_d_ready, // @[LazyModuleImp.scala:107:25] input auto_out_d_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_opcode, // @[LazyModuleImp.scala:107:25] input [1:0] auto_out_d_bits_param, // @[LazyModuleImp.scala:107:25] input [3:0] auto_out_d_bits_size, // @[LazyModuleImp.scala:107:25] input [2:0] auto_out_d_bits_sink, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_denied, // @[LazyModuleImp.scala:107:25] input [7:0] auto_out_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_out_d_bits_corrupt, // @[LazyModuleImp.scala:107:25] input io_rdEn, // @[SBA.scala:274:16] input io_wrEn, // @[SBA.scala:274:16] input [127:0] io_addrIn, // @[SBA.scala:274:16] input [127:0] io_dataIn, // @[SBA.scala:274:16] input [2:0] io_sizeIn, // @[SBA.scala:274:16] output io_rdLegal, // @[SBA.scala:274:16] output io_wrLegal, // @[SBA.scala:274:16] output io_rdDone, // @[SBA.scala:274:16] output io_wrDone, // @[SBA.scala:274:16] output io_respError, // @[SBA.scala:274:16] output [7:0] io_dataOut, // @[SBA.scala:274:16] output io_rdLoad_0, // @[SBA.scala:274:16] output io_rdLoad_1, // @[SBA.scala:274:16] output io_rdLoad_2, // @[SBA.scala:274:16] output io_rdLoad_3, // @[SBA.scala:274:16] output io_rdLoad_4, // @[SBA.scala:274:16] output io_rdLoad_5, // @[SBA.scala:274:16] output io_rdLoad_6, // @[SBA.scala:274:16] output io_rdLoad_7, // @[SBA.scala:274:16] output [2:0] io_sbStateOut // @[SBA.scala:274:16] ); wire _d_q_io_deq_valid; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_denied; // @[Decoupled.scala:362:21] wire _d_q_io_deq_bits_corrupt; // @[Decoupled.scala:362:21] reg [2:0] sbState; // @[SBA.scala:295:26] wire _rdTxValid_T = sbState == 3'h3; // @[SBA.scala:295:26, :299:25] wire _io_wrDone_T = sbState == 3'h4; // @[SBA.scala:295:26, :299:62] wire d_q_io_deq_ready = _rdTxValid_T | _io_wrDone_T; // @[SBA.scala:299:{25,50,62}] reg [3:0] counter; // @[SBA.scala:307:26] wire [7:0][7:0] _GEN = {{io_dataIn[63:56]}, {io_dataIn[55:48]}, {io_dataIn[47:40]}, {io_dataIn[39:32]}, {io_dataIn[31:24]}, {io_dataIn[23:16]}, {io_dataIn[15:8]}, {io_dataIn[7:0]}}; // @[SBA.scala:309:63, :310:15] wire [115:0] _GEN_0 = {io_addrIn[127:14], ~(io_addrIn[13:12])}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_1 = {io_addrIn[127:15], io_addrIn[14:12] ^ 3'h4}; // @[Parameters.scala:137:{31,41,46}] wire [114:0] _GEN_2 = {io_addrIn[127:21], io_addrIn[20:17] ^ 4'h8, io_addrIn[15:12]}; // @[Parameters.scala:137:{31,41,46}] wire [111:0] _GEN_3 = {io_addrIn[127:26], io_addrIn[25:16] ^ 10'h200}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_4 = {io_addrIn[127:26], io_addrIn[25:12] ^ 14'h2010}; // @[Parameters.scala:137:{31,41,46}] wire [111:0] _GEN_5 = {io_addrIn[127:28], io_addrIn[27:16] ^ 12'h800}; // @[Parameters.scala:137:{31,41,46}] wire [101:0] _GEN_6 = {io_addrIn[127:28], ~(io_addrIn[27:26])}; // @[Parameters.scala:137:{31,41,46}] wire [115:0] _GEN_7 = {io_addrIn[127:29], io_addrIn[28:12] ^ 17'h10020}; // @[Parameters.scala:137:{31,41,46}] wire [99:0] _GEN_8 = {io_addrIn[127:32], io_addrIn[31:28] ^ 4'h8}; // @[Parameters.scala:137:{31,41,46}] wire io_rdLegal_0 = ~(|(io_addrIn[127:13])) | ~(|_GEN_0) | ~(|_GEN_1) | {io_addrIn[127:17], ~(io_addrIn[16])} == 112'h0 | ~(|_GEN_2) | ~(|_GEN_3) | ~(|_GEN_4) | ~(|_GEN_5) | ~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8); // @[Parameters.scala:685:42] wire io_wrLegal_0 = ~(|(io_addrIn[127:13])) | ~(|_GEN_0) | ~(|_GEN_1) | ~(|_GEN_2) | ~(|_GEN_3) | ~(|_GEN_4) | ~(|_GEN_5) | ~(|_GEN_6) | ~(|_GEN_7) | ~(|_GEN_8); // @[Parameters.scala:685:42] wire _nodeOut_a_valid_T = sbState == 3'h1; // @[SBA.scala:295:26, :322:18] wire _nodeOut_a_valid_T_1 = sbState == 3'h2; // @[SBA.scala:295:26, :338:29] wire rdTxValid = _rdTxValid_T & _d_q_io_deq_valid & d_q_io_deq_ready; // @[Decoupled.scala:362:21] wire txLast = {4'h0, counter} == (8'h1 << io_sizeIn) - 8'h1; // @[SBA.scala:307:26, :340:{29,39,53}] wire _GEN_9 = sbState == 3'h0; // @[SBA.scala:295:26, :349:19] wire nodeOut_a_valid = _nodeOut_a_valid_T | _nodeOut_a_valid_T_1; // @[SBA.scala:322:18, :338:29, :366:52]
Generate the Verilog code corresponding to this FIRRTL code module PMPChecker_s3_1 : input clock : Clock input reset : Reset output io : { flip prv : UInt<2>, flip pmp : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>}[8], flip addr : UInt<32>, flip size : UInt<2>, r : UInt<1>, w : UInt<1>, x : UInt<1>} node default = gt(io.prv, UInt<1>(0h1)) wire _pmp0_WIRE : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect _pmp0_WIRE.mask, UInt<32>(0h0) connect _pmp0_WIRE.addr, UInt<30>(0h0) connect _pmp0_WIRE.cfg.r, UInt<1>(0h0) connect _pmp0_WIRE.cfg.w, UInt<1>(0h0) connect _pmp0_WIRE.cfg.x, UInt<1>(0h0) connect _pmp0_WIRE.cfg.a, UInt<2>(0h0) connect _pmp0_WIRE.cfg.res, UInt<2>(0h0) connect _pmp0_WIRE.cfg.l, UInt<1>(0h0) wire pmp0 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect pmp0, _pmp0_WIRE connect pmp0.cfg.r, default connect pmp0.cfg.w, default connect pmp0.cfg.x, default node _res_hit_T = bits(io.pmp[7].cfg.a, 1, 1) node _res_hit_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_1 = bits(_res_hit_lsbMask_T, 2, 0) node _res_hit_lsbMask_T_2 = not(_res_hit_lsbMask_T_1) node res_hit_lsbMask = or(io.pmp[7].mask, _res_hit_lsbMask_T_2) node _res_hit_msbMatch_T = shr(io.addr, 3) node _res_hit_msbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_msbMatch_T_2 = not(_res_hit_msbMatch_T_1) node _res_hit_msbMatch_T_3 = or(_res_hit_msbMatch_T_2, UInt<2>(0h3)) node _res_hit_msbMatch_T_4 = not(_res_hit_msbMatch_T_3) node _res_hit_msbMatch_T_5 = shr(_res_hit_msbMatch_T_4, 3) node _res_hit_msbMatch_T_6 = shr(io.pmp[7].mask, 3) node _res_hit_msbMatch_T_7 = xor(_res_hit_msbMatch_T, _res_hit_msbMatch_T_5) node _res_hit_msbMatch_T_8 = not(_res_hit_msbMatch_T_6) node _res_hit_msbMatch_T_9 = and(_res_hit_msbMatch_T_7, _res_hit_msbMatch_T_8) node res_hit_msbMatch = eq(_res_hit_msbMatch_T_9, UInt<1>(0h0)) node _res_hit_lsbMatch_T = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_1 = shl(io.pmp[7].addr, 2) node _res_hit_lsbMatch_T_2 = not(_res_hit_lsbMatch_T_1) node _res_hit_lsbMatch_T_3 = or(_res_hit_lsbMatch_T_2, UInt<2>(0h3)) node _res_hit_lsbMatch_T_4 = not(_res_hit_lsbMatch_T_3) node _res_hit_lsbMatch_T_5 = bits(_res_hit_lsbMatch_T_4, 2, 0) node _res_hit_lsbMatch_T_6 = bits(res_hit_lsbMask, 2, 0) node _res_hit_lsbMatch_T_7 = xor(_res_hit_lsbMatch_T, _res_hit_lsbMatch_T_5) node _res_hit_lsbMatch_T_8 = not(_res_hit_lsbMatch_T_6) node _res_hit_lsbMatch_T_9 = and(_res_hit_lsbMatch_T_7, _res_hit_lsbMatch_T_8) node res_hit_lsbMatch = eq(_res_hit_lsbMatch_T_9, UInt<1>(0h0)) node _res_hit_T_1 = and(res_hit_msbMatch, res_hit_lsbMatch) node _res_hit_T_2 = bits(io.pmp[7].cfg.a, 0, 0) node _res_hit_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_4 = bits(_res_hit_T_3, 2, 0) node _res_hit_T_5 = not(_res_hit_T_4) node _res_hit_msbsLess_T = shr(io.addr, 3) node _res_hit_msbsLess_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_2 = not(_res_hit_msbsLess_T_1) node _res_hit_msbsLess_T_3 = or(_res_hit_msbsLess_T_2, UInt<2>(0h3)) node _res_hit_msbsLess_T_4 = not(_res_hit_msbsLess_T_3) node _res_hit_msbsLess_T_5 = shr(_res_hit_msbsLess_T_4, 3) node res_hit_msbsLess = lt(_res_hit_msbsLess_T, _res_hit_msbsLess_T_5) node _res_hit_msbsEqual_T = shr(io.addr, 3) node _res_hit_msbsEqual_T_1 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_2 = not(_res_hit_msbsEqual_T_1) node _res_hit_msbsEqual_T_3 = or(_res_hit_msbsEqual_T_2, UInt<2>(0h3)) node _res_hit_msbsEqual_T_4 = not(_res_hit_msbsEqual_T_3) node _res_hit_msbsEqual_T_5 = shr(_res_hit_msbsEqual_T_4, 3) node _res_hit_msbsEqual_T_6 = xor(_res_hit_msbsEqual_T, _res_hit_msbsEqual_T_5) node res_hit_msbsEqual = eq(_res_hit_msbsEqual_T_6, UInt<1>(0h0)) node _res_hit_lsbsLess_T = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_1 = or(_res_hit_lsbsLess_T, _res_hit_T_5) node _res_hit_lsbsLess_T_2 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_3 = not(_res_hit_lsbsLess_T_2) node _res_hit_lsbsLess_T_4 = or(_res_hit_lsbsLess_T_3, UInt<2>(0h3)) node _res_hit_lsbsLess_T_5 = not(_res_hit_lsbsLess_T_4) node _res_hit_lsbsLess_T_6 = bits(_res_hit_lsbsLess_T_5, 2, 0) node res_hit_lsbsLess = lt(_res_hit_lsbsLess_T_1, _res_hit_lsbsLess_T_6) node _res_hit_T_6 = and(res_hit_msbsEqual, res_hit_lsbsLess) node _res_hit_T_7 = or(res_hit_msbsLess, _res_hit_T_6) node _res_hit_T_8 = eq(_res_hit_T_7, UInt<1>(0h0)) node _res_hit_msbsLess_T_6 = shr(io.addr, 3) node _res_hit_msbsLess_T_7 = shl(io.pmp[7].addr, 2) node _res_hit_msbsLess_T_8 = not(_res_hit_msbsLess_T_7) node _res_hit_msbsLess_T_9 = or(_res_hit_msbsLess_T_8, UInt<2>(0h3)) node _res_hit_msbsLess_T_10 = not(_res_hit_msbsLess_T_9) node _res_hit_msbsLess_T_11 = shr(_res_hit_msbsLess_T_10, 3) node res_hit_msbsLess_1 = lt(_res_hit_msbsLess_T_6, _res_hit_msbsLess_T_11) node _res_hit_msbsEqual_T_7 = shr(io.addr, 3) node _res_hit_msbsEqual_T_8 = shl(io.pmp[7].addr, 2) node _res_hit_msbsEqual_T_9 = not(_res_hit_msbsEqual_T_8) node _res_hit_msbsEqual_T_10 = or(_res_hit_msbsEqual_T_9, UInt<2>(0h3)) node _res_hit_msbsEqual_T_11 = not(_res_hit_msbsEqual_T_10) node _res_hit_msbsEqual_T_12 = shr(_res_hit_msbsEqual_T_11, 3) node _res_hit_msbsEqual_T_13 = xor(_res_hit_msbsEqual_T_7, _res_hit_msbsEqual_T_12) node res_hit_msbsEqual_1 = eq(_res_hit_msbsEqual_T_13, UInt<1>(0h0)) node _res_hit_lsbsLess_T_7 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_8 = or(_res_hit_lsbsLess_T_7, UInt<1>(0h0)) node _res_hit_lsbsLess_T_9 = shl(io.pmp[7].addr, 2) node _res_hit_lsbsLess_T_10 = not(_res_hit_lsbsLess_T_9) node _res_hit_lsbsLess_T_11 = or(_res_hit_lsbsLess_T_10, UInt<2>(0h3)) node _res_hit_lsbsLess_T_12 = not(_res_hit_lsbsLess_T_11) node _res_hit_lsbsLess_T_13 = bits(_res_hit_lsbsLess_T_12, 2, 0) node res_hit_lsbsLess_1 = lt(_res_hit_lsbsLess_T_8, _res_hit_lsbsLess_T_13) node _res_hit_T_9 = and(res_hit_msbsEqual_1, res_hit_lsbsLess_1) node _res_hit_T_10 = or(res_hit_msbsLess_1, _res_hit_T_9) node _res_hit_T_11 = and(_res_hit_T_8, _res_hit_T_10) node _res_hit_T_12 = and(_res_hit_T_2, _res_hit_T_11) node res_hit = mux(_res_hit_T, _res_hit_T_1, _res_hit_T_12) node _res_ignore_T = eq(io.pmp[7].cfg.l, UInt<1>(0h0)) node res_ignore = and(default, _res_ignore_T) node _res_aligned_lsbMask_T = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_1 = bits(_res_aligned_lsbMask_T, 2, 0) node res_aligned_lsbMask = not(_res_aligned_lsbMask_T_1) node _res_aligned_straddlesLowerBound_T = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_1 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_2 = not(_res_aligned_straddlesLowerBound_T_1) node _res_aligned_straddlesLowerBound_T_3 = or(_res_aligned_straddlesLowerBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_4 = not(_res_aligned_straddlesLowerBound_T_3) node _res_aligned_straddlesLowerBound_T_5 = shr(_res_aligned_straddlesLowerBound_T_4, 3) node _res_aligned_straddlesLowerBound_T_6 = xor(_res_aligned_straddlesLowerBound_T, _res_aligned_straddlesLowerBound_T_5) node _res_aligned_straddlesLowerBound_T_7 = eq(_res_aligned_straddlesLowerBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_8 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesLowerBound_T_9 = not(_res_aligned_straddlesLowerBound_T_8) node _res_aligned_straddlesLowerBound_T_10 = or(_res_aligned_straddlesLowerBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_11 = not(_res_aligned_straddlesLowerBound_T_10) node _res_aligned_straddlesLowerBound_T_12 = bits(_res_aligned_straddlesLowerBound_T_11, 2, 0) node _res_aligned_straddlesLowerBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_14 = not(_res_aligned_straddlesLowerBound_T_13) node _res_aligned_straddlesLowerBound_T_15 = and(_res_aligned_straddlesLowerBound_T_12, _res_aligned_straddlesLowerBound_T_14) node _res_aligned_straddlesLowerBound_T_16 = neq(_res_aligned_straddlesLowerBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesLowerBound = and(_res_aligned_straddlesLowerBound_T_7, _res_aligned_straddlesLowerBound_T_16) node _res_aligned_straddlesUpperBound_T = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_1 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_2 = not(_res_aligned_straddlesUpperBound_T_1) node _res_aligned_straddlesUpperBound_T_3 = or(_res_aligned_straddlesUpperBound_T_2, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_4 = not(_res_aligned_straddlesUpperBound_T_3) node _res_aligned_straddlesUpperBound_T_5 = shr(_res_aligned_straddlesUpperBound_T_4, 3) node _res_aligned_straddlesUpperBound_T_6 = xor(_res_aligned_straddlesUpperBound_T, _res_aligned_straddlesUpperBound_T_5) node _res_aligned_straddlesUpperBound_T_7 = eq(_res_aligned_straddlesUpperBound_T_6, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_8 = shl(io.pmp[7].addr, 2) node _res_aligned_straddlesUpperBound_T_9 = not(_res_aligned_straddlesUpperBound_T_8) node _res_aligned_straddlesUpperBound_T_10 = or(_res_aligned_straddlesUpperBound_T_9, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_11 = not(_res_aligned_straddlesUpperBound_T_10) node _res_aligned_straddlesUpperBound_T_12 = bits(_res_aligned_straddlesUpperBound_T_11, 2, 0) node _res_aligned_straddlesUpperBound_T_13 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_14 = or(_res_aligned_straddlesUpperBound_T_13, res_aligned_lsbMask) node _res_aligned_straddlesUpperBound_T_15 = and(_res_aligned_straddlesUpperBound_T_12, _res_aligned_straddlesUpperBound_T_14) node _res_aligned_straddlesUpperBound_T_16 = neq(_res_aligned_straddlesUpperBound_T_15, UInt<1>(0h0)) node res_aligned_straddlesUpperBound = and(_res_aligned_straddlesUpperBound_T_7, _res_aligned_straddlesUpperBound_T_16) node _res_aligned_rangeAligned_T = or(res_aligned_straddlesLowerBound, res_aligned_straddlesUpperBound) node res_aligned_rangeAligned = eq(_res_aligned_rangeAligned_T, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T = bits(io.pmp[7].mask, 2, 0) node _res_aligned_pow2Aligned_T_1 = not(_res_aligned_pow2Aligned_T) node _res_aligned_pow2Aligned_T_2 = and(res_aligned_lsbMask, _res_aligned_pow2Aligned_T_1) node res_aligned_pow2Aligned = eq(_res_aligned_pow2Aligned_T_2, UInt<1>(0h0)) node _res_aligned_T = bits(io.pmp[7].cfg.a, 1, 1) node res_aligned = mux(_res_aligned_T, res_aligned_pow2Aligned, res_aligned_rangeAligned) node _res_T = eq(io.pmp[7].cfg.a, UInt<1>(0h0)) node _res_T_1 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_2 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_3 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_4 = eq(io.pmp[7].cfg.l, UInt<1>(0h1)) node res_hi = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_5 = cat(res_hi, io.pmp[7].cfg.r) node _res_T_6 = eq(_res_T_5, UInt<1>(0h0)) node res_hi_1 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_7 = cat(res_hi_1, io.pmp[7].cfg.r) node _res_T_8 = eq(_res_T_7, UInt<1>(0h1)) node res_hi_2 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_9 = cat(res_hi_2, io.pmp[7].cfg.r) node _res_T_10 = eq(_res_T_9, UInt<2>(0h3)) node res_hi_3 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_11 = cat(res_hi_3, io.pmp[7].cfg.r) node _res_T_12 = eq(_res_T_11, UInt<3>(0h4)) node res_hi_4 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_13 = cat(res_hi_4, io.pmp[7].cfg.r) node _res_T_14 = eq(_res_T_13, UInt<3>(0h5)) node res_hi_5 = cat(io.pmp[7].cfg.x, io.pmp[7].cfg.w) node _res_T_15 = cat(res_hi_5, io.pmp[7].cfg.r) node _res_T_16 = eq(_res_T_15, UInt<3>(0h7)) node _res_T_17 = eq(res_ignore, UInt<1>(0h0)) node _res_T_18 = and(_res_T_17, res_hit) node _res_T_19 = and(_res_T_18, res_aligned) node _res_T_20 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_21 = and(_res_T_19, _res_T_20) node _res_T_22 = and(io.pmp[7].cfg.l, res_hit) node _res_T_23 = and(_res_T_22, res_aligned) node _res_T_24 = eq(io.pmp[7].cfg.a, UInt<1>(0h1)) node _res_T_25 = and(_res_T_23, _res_T_24) node _res_T_26 = eq(res_ignore, UInt<1>(0h0)) node _res_T_27 = and(_res_T_26, res_hit) node _res_T_28 = and(_res_T_27, res_aligned) node _res_T_29 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_30 = and(_res_T_28, _res_T_29) node _res_T_31 = and(io.pmp[7].cfg.l, res_hit) node _res_T_32 = and(_res_T_31, res_aligned) node _res_T_33 = eq(io.pmp[7].cfg.a, UInt<2>(0h2)) node _res_T_34 = and(_res_T_32, _res_T_33) node _res_T_35 = eq(res_ignore, UInt<1>(0h0)) node _res_T_36 = and(_res_T_35, res_hit) node _res_T_37 = and(_res_T_36, res_aligned) node _res_T_38 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_39 = and(_res_T_37, _res_T_38) node _res_T_40 = and(io.pmp[7].cfg.l, res_hit) node _res_T_41 = and(_res_T_40, res_aligned) node _res_T_42 = eq(io.pmp[7].cfg.a, UInt<2>(0h3)) node _res_T_43 = and(_res_T_41, _res_T_42) wire res_cur : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur, io.pmp[7] node _res_cur_cfg_r_T = or(io.pmp[7].cfg.r, res_ignore) node _res_cur_cfg_r_T_1 = and(res_aligned, _res_cur_cfg_r_T) connect res_cur.cfg.r, _res_cur_cfg_r_T_1 node _res_cur_cfg_w_T = or(io.pmp[7].cfg.w, res_ignore) node _res_cur_cfg_w_T_1 = and(res_aligned, _res_cur_cfg_w_T) connect res_cur.cfg.w, _res_cur_cfg_w_T_1 node _res_cur_cfg_x_T = or(io.pmp[7].cfg.x, res_ignore) node _res_cur_cfg_x_T_1 = and(res_aligned, _res_cur_cfg_x_T) connect res_cur.cfg.x, _res_cur_cfg_x_T_1 node _res_T_44 = mux(res_hit, res_cur, pmp0) node _res_hit_T_13 = bits(io.pmp[6].cfg.a, 1, 1) node _res_hit_lsbMask_T_3 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_4 = bits(_res_hit_lsbMask_T_3, 2, 0) node _res_hit_lsbMask_T_5 = not(_res_hit_lsbMask_T_4) node res_hit_lsbMask_1 = or(io.pmp[6].mask, _res_hit_lsbMask_T_5) node _res_hit_msbMatch_T_10 = shr(io.addr, 3) node _res_hit_msbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_msbMatch_T_12 = not(_res_hit_msbMatch_T_11) node _res_hit_msbMatch_T_13 = or(_res_hit_msbMatch_T_12, UInt<2>(0h3)) node _res_hit_msbMatch_T_14 = not(_res_hit_msbMatch_T_13) node _res_hit_msbMatch_T_15 = shr(_res_hit_msbMatch_T_14, 3) node _res_hit_msbMatch_T_16 = shr(io.pmp[6].mask, 3) node _res_hit_msbMatch_T_17 = xor(_res_hit_msbMatch_T_10, _res_hit_msbMatch_T_15) node _res_hit_msbMatch_T_18 = not(_res_hit_msbMatch_T_16) node _res_hit_msbMatch_T_19 = and(_res_hit_msbMatch_T_17, _res_hit_msbMatch_T_18) node res_hit_msbMatch_1 = eq(_res_hit_msbMatch_T_19, UInt<1>(0h0)) node _res_hit_lsbMatch_T_10 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_11 = shl(io.pmp[6].addr, 2) node _res_hit_lsbMatch_T_12 = not(_res_hit_lsbMatch_T_11) node _res_hit_lsbMatch_T_13 = or(_res_hit_lsbMatch_T_12, UInt<2>(0h3)) node _res_hit_lsbMatch_T_14 = not(_res_hit_lsbMatch_T_13) node _res_hit_lsbMatch_T_15 = bits(_res_hit_lsbMatch_T_14, 2, 0) node _res_hit_lsbMatch_T_16 = bits(res_hit_lsbMask_1, 2, 0) node _res_hit_lsbMatch_T_17 = xor(_res_hit_lsbMatch_T_10, _res_hit_lsbMatch_T_15) node _res_hit_lsbMatch_T_18 = not(_res_hit_lsbMatch_T_16) node _res_hit_lsbMatch_T_19 = and(_res_hit_lsbMatch_T_17, _res_hit_lsbMatch_T_18) node res_hit_lsbMatch_1 = eq(_res_hit_lsbMatch_T_19, UInt<1>(0h0)) node _res_hit_T_14 = and(res_hit_msbMatch_1, res_hit_lsbMatch_1) node _res_hit_T_15 = bits(io.pmp[6].cfg.a, 0, 0) node _res_hit_T_16 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_17 = bits(_res_hit_T_16, 2, 0) node _res_hit_T_18 = not(_res_hit_T_17) node _res_hit_msbsLess_T_12 = shr(io.addr, 3) node _res_hit_msbsLess_T_13 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_14 = not(_res_hit_msbsLess_T_13) node _res_hit_msbsLess_T_15 = or(_res_hit_msbsLess_T_14, UInt<2>(0h3)) node _res_hit_msbsLess_T_16 = not(_res_hit_msbsLess_T_15) node _res_hit_msbsLess_T_17 = shr(_res_hit_msbsLess_T_16, 3) node res_hit_msbsLess_2 = lt(_res_hit_msbsLess_T_12, _res_hit_msbsLess_T_17) node _res_hit_msbsEqual_T_14 = shr(io.addr, 3) node _res_hit_msbsEqual_T_15 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_16 = not(_res_hit_msbsEqual_T_15) node _res_hit_msbsEqual_T_17 = or(_res_hit_msbsEqual_T_16, UInt<2>(0h3)) node _res_hit_msbsEqual_T_18 = not(_res_hit_msbsEqual_T_17) node _res_hit_msbsEqual_T_19 = shr(_res_hit_msbsEqual_T_18, 3) node _res_hit_msbsEqual_T_20 = xor(_res_hit_msbsEqual_T_14, _res_hit_msbsEqual_T_19) node res_hit_msbsEqual_2 = eq(_res_hit_msbsEqual_T_20, UInt<1>(0h0)) node _res_hit_lsbsLess_T_14 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_15 = or(_res_hit_lsbsLess_T_14, _res_hit_T_18) node _res_hit_lsbsLess_T_16 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_17 = not(_res_hit_lsbsLess_T_16) node _res_hit_lsbsLess_T_18 = or(_res_hit_lsbsLess_T_17, UInt<2>(0h3)) node _res_hit_lsbsLess_T_19 = not(_res_hit_lsbsLess_T_18) node _res_hit_lsbsLess_T_20 = bits(_res_hit_lsbsLess_T_19, 2, 0) node res_hit_lsbsLess_2 = lt(_res_hit_lsbsLess_T_15, _res_hit_lsbsLess_T_20) node _res_hit_T_19 = and(res_hit_msbsEqual_2, res_hit_lsbsLess_2) node _res_hit_T_20 = or(res_hit_msbsLess_2, _res_hit_T_19) node _res_hit_T_21 = eq(_res_hit_T_20, UInt<1>(0h0)) node _res_hit_msbsLess_T_18 = shr(io.addr, 3) node _res_hit_msbsLess_T_19 = shl(io.pmp[6].addr, 2) node _res_hit_msbsLess_T_20 = not(_res_hit_msbsLess_T_19) node _res_hit_msbsLess_T_21 = or(_res_hit_msbsLess_T_20, UInt<2>(0h3)) node _res_hit_msbsLess_T_22 = not(_res_hit_msbsLess_T_21) node _res_hit_msbsLess_T_23 = shr(_res_hit_msbsLess_T_22, 3) node res_hit_msbsLess_3 = lt(_res_hit_msbsLess_T_18, _res_hit_msbsLess_T_23) node _res_hit_msbsEqual_T_21 = shr(io.addr, 3) node _res_hit_msbsEqual_T_22 = shl(io.pmp[6].addr, 2) node _res_hit_msbsEqual_T_23 = not(_res_hit_msbsEqual_T_22) node _res_hit_msbsEqual_T_24 = or(_res_hit_msbsEqual_T_23, UInt<2>(0h3)) node _res_hit_msbsEqual_T_25 = not(_res_hit_msbsEqual_T_24) node _res_hit_msbsEqual_T_26 = shr(_res_hit_msbsEqual_T_25, 3) node _res_hit_msbsEqual_T_27 = xor(_res_hit_msbsEqual_T_21, _res_hit_msbsEqual_T_26) node res_hit_msbsEqual_3 = eq(_res_hit_msbsEqual_T_27, UInt<1>(0h0)) node _res_hit_lsbsLess_T_21 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_22 = or(_res_hit_lsbsLess_T_21, UInt<1>(0h0)) node _res_hit_lsbsLess_T_23 = shl(io.pmp[6].addr, 2) node _res_hit_lsbsLess_T_24 = not(_res_hit_lsbsLess_T_23) node _res_hit_lsbsLess_T_25 = or(_res_hit_lsbsLess_T_24, UInt<2>(0h3)) node _res_hit_lsbsLess_T_26 = not(_res_hit_lsbsLess_T_25) node _res_hit_lsbsLess_T_27 = bits(_res_hit_lsbsLess_T_26, 2, 0) node res_hit_lsbsLess_3 = lt(_res_hit_lsbsLess_T_22, _res_hit_lsbsLess_T_27) node _res_hit_T_22 = and(res_hit_msbsEqual_3, res_hit_lsbsLess_3) node _res_hit_T_23 = or(res_hit_msbsLess_3, _res_hit_T_22) node _res_hit_T_24 = and(_res_hit_T_21, _res_hit_T_23) node _res_hit_T_25 = and(_res_hit_T_15, _res_hit_T_24) node res_hit_1 = mux(_res_hit_T_13, _res_hit_T_14, _res_hit_T_25) node _res_ignore_T_1 = eq(io.pmp[6].cfg.l, UInt<1>(0h0)) node res_ignore_1 = and(default, _res_ignore_T_1) node _res_aligned_lsbMask_T_2 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_3 = bits(_res_aligned_lsbMask_T_2, 2, 0) node res_aligned_lsbMask_1 = not(_res_aligned_lsbMask_T_3) node _res_aligned_straddlesLowerBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_18 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_19 = not(_res_aligned_straddlesLowerBound_T_18) node _res_aligned_straddlesLowerBound_T_20 = or(_res_aligned_straddlesLowerBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_21 = not(_res_aligned_straddlesLowerBound_T_20) node _res_aligned_straddlesLowerBound_T_22 = shr(_res_aligned_straddlesLowerBound_T_21, 3) node _res_aligned_straddlesLowerBound_T_23 = xor(_res_aligned_straddlesLowerBound_T_17, _res_aligned_straddlesLowerBound_T_22) node _res_aligned_straddlesLowerBound_T_24 = eq(_res_aligned_straddlesLowerBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_25 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesLowerBound_T_26 = not(_res_aligned_straddlesLowerBound_T_25) node _res_aligned_straddlesLowerBound_T_27 = or(_res_aligned_straddlesLowerBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_28 = not(_res_aligned_straddlesLowerBound_T_27) node _res_aligned_straddlesLowerBound_T_29 = bits(_res_aligned_straddlesLowerBound_T_28, 2, 0) node _res_aligned_straddlesLowerBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_31 = not(_res_aligned_straddlesLowerBound_T_30) node _res_aligned_straddlesLowerBound_T_32 = and(_res_aligned_straddlesLowerBound_T_29, _res_aligned_straddlesLowerBound_T_31) node _res_aligned_straddlesLowerBound_T_33 = neq(_res_aligned_straddlesLowerBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_1 = and(_res_aligned_straddlesLowerBound_T_24, _res_aligned_straddlesLowerBound_T_33) node _res_aligned_straddlesUpperBound_T_17 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_18 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_19 = not(_res_aligned_straddlesUpperBound_T_18) node _res_aligned_straddlesUpperBound_T_20 = or(_res_aligned_straddlesUpperBound_T_19, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_21 = not(_res_aligned_straddlesUpperBound_T_20) node _res_aligned_straddlesUpperBound_T_22 = shr(_res_aligned_straddlesUpperBound_T_21, 3) node _res_aligned_straddlesUpperBound_T_23 = xor(_res_aligned_straddlesUpperBound_T_17, _res_aligned_straddlesUpperBound_T_22) node _res_aligned_straddlesUpperBound_T_24 = eq(_res_aligned_straddlesUpperBound_T_23, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_25 = shl(io.pmp[6].addr, 2) node _res_aligned_straddlesUpperBound_T_26 = not(_res_aligned_straddlesUpperBound_T_25) node _res_aligned_straddlesUpperBound_T_27 = or(_res_aligned_straddlesUpperBound_T_26, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_28 = not(_res_aligned_straddlesUpperBound_T_27) node _res_aligned_straddlesUpperBound_T_29 = bits(_res_aligned_straddlesUpperBound_T_28, 2, 0) node _res_aligned_straddlesUpperBound_T_30 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_31 = or(_res_aligned_straddlesUpperBound_T_30, res_aligned_lsbMask_1) node _res_aligned_straddlesUpperBound_T_32 = and(_res_aligned_straddlesUpperBound_T_29, _res_aligned_straddlesUpperBound_T_31) node _res_aligned_straddlesUpperBound_T_33 = neq(_res_aligned_straddlesUpperBound_T_32, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_1 = and(_res_aligned_straddlesUpperBound_T_24, _res_aligned_straddlesUpperBound_T_33) node _res_aligned_rangeAligned_T_1 = or(res_aligned_straddlesLowerBound_1, res_aligned_straddlesUpperBound_1) node res_aligned_rangeAligned_1 = eq(_res_aligned_rangeAligned_T_1, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_3 = bits(io.pmp[6].mask, 2, 0) node _res_aligned_pow2Aligned_T_4 = not(_res_aligned_pow2Aligned_T_3) node _res_aligned_pow2Aligned_T_5 = and(res_aligned_lsbMask_1, _res_aligned_pow2Aligned_T_4) node res_aligned_pow2Aligned_1 = eq(_res_aligned_pow2Aligned_T_5, UInt<1>(0h0)) node _res_aligned_T_1 = bits(io.pmp[6].cfg.a, 1, 1) node res_aligned_1 = mux(_res_aligned_T_1, res_aligned_pow2Aligned_1, res_aligned_rangeAligned_1) node _res_T_45 = eq(io.pmp[6].cfg.a, UInt<1>(0h0)) node _res_T_46 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_47 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_48 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_49 = eq(io.pmp[6].cfg.l, UInt<1>(0h1)) node res_hi_6 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_50 = cat(res_hi_6, io.pmp[6].cfg.r) node _res_T_51 = eq(_res_T_50, UInt<1>(0h0)) node res_hi_7 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_52 = cat(res_hi_7, io.pmp[6].cfg.r) node _res_T_53 = eq(_res_T_52, UInt<1>(0h1)) node res_hi_8 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_54 = cat(res_hi_8, io.pmp[6].cfg.r) node _res_T_55 = eq(_res_T_54, UInt<2>(0h3)) node res_hi_9 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_56 = cat(res_hi_9, io.pmp[6].cfg.r) node _res_T_57 = eq(_res_T_56, UInt<3>(0h4)) node res_hi_10 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_58 = cat(res_hi_10, io.pmp[6].cfg.r) node _res_T_59 = eq(_res_T_58, UInt<3>(0h5)) node res_hi_11 = cat(io.pmp[6].cfg.x, io.pmp[6].cfg.w) node _res_T_60 = cat(res_hi_11, io.pmp[6].cfg.r) node _res_T_61 = eq(_res_T_60, UInt<3>(0h7)) node _res_T_62 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_63 = and(_res_T_62, res_hit_1) node _res_T_64 = and(_res_T_63, res_aligned_1) node _res_T_65 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_66 = and(_res_T_64, _res_T_65) node _res_T_67 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_68 = and(_res_T_67, res_aligned_1) node _res_T_69 = eq(io.pmp[6].cfg.a, UInt<1>(0h1)) node _res_T_70 = and(_res_T_68, _res_T_69) node _res_T_71 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_72 = and(_res_T_71, res_hit_1) node _res_T_73 = and(_res_T_72, res_aligned_1) node _res_T_74 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_75 = and(_res_T_73, _res_T_74) node _res_T_76 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_77 = and(_res_T_76, res_aligned_1) node _res_T_78 = eq(io.pmp[6].cfg.a, UInt<2>(0h2)) node _res_T_79 = and(_res_T_77, _res_T_78) node _res_T_80 = eq(res_ignore_1, UInt<1>(0h0)) node _res_T_81 = and(_res_T_80, res_hit_1) node _res_T_82 = and(_res_T_81, res_aligned_1) node _res_T_83 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_84 = and(_res_T_82, _res_T_83) node _res_T_85 = and(io.pmp[6].cfg.l, res_hit_1) node _res_T_86 = and(_res_T_85, res_aligned_1) node _res_T_87 = eq(io.pmp[6].cfg.a, UInt<2>(0h3)) node _res_T_88 = and(_res_T_86, _res_T_87) wire res_cur_1 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_1, io.pmp[6] node _res_cur_cfg_r_T_2 = or(io.pmp[6].cfg.r, res_ignore_1) node _res_cur_cfg_r_T_3 = and(res_aligned_1, _res_cur_cfg_r_T_2) connect res_cur_1.cfg.r, _res_cur_cfg_r_T_3 node _res_cur_cfg_w_T_2 = or(io.pmp[6].cfg.w, res_ignore_1) node _res_cur_cfg_w_T_3 = and(res_aligned_1, _res_cur_cfg_w_T_2) connect res_cur_1.cfg.w, _res_cur_cfg_w_T_3 node _res_cur_cfg_x_T_2 = or(io.pmp[6].cfg.x, res_ignore_1) node _res_cur_cfg_x_T_3 = and(res_aligned_1, _res_cur_cfg_x_T_2) connect res_cur_1.cfg.x, _res_cur_cfg_x_T_3 node _res_T_89 = mux(res_hit_1, res_cur_1, _res_T_44) node _res_hit_T_26 = bits(io.pmp[5].cfg.a, 1, 1) node _res_hit_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_7 = bits(_res_hit_lsbMask_T_6, 2, 0) node _res_hit_lsbMask_T_8 = not(_res_hit_lsbMask_T_7) node res_hit_lsbMask_2 = or(io.pmp[5].mask, _res_hit_lsbMask_T_8) node _res_hit_msbMatch_T_20 = shr(io.addr, 3) node _res_hit_msbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_msbMatch_T_22 = not(_res_hit_msbMatch_T_21) node _res_hit_msbMatch_T_23 = or(_res_hit_msbMatch_T_22, UInt<2>(0h3)) node _res_hit_msbMatch_T_24 = not(_res_hit_msbMatch_T_23) node _res_hit_msbMatch_T_25 = shr(_res_hit_msbMatch_T_24, 3) node _res_hit_msbMatch_T_26 = shr(io.pmp[5].mask, 3) node _res_hit_msbMatch_T_27 = xor(_res_hit_msbMatch_T_20, _res_hit_msbMatch_T_25) node _res_hit_msbMatch_T_28 = not(_res_hit_msbMatch_T_26) node _res_hit_msbMatch_T_29 = and(_res_hit_msbMatch_T_27, _res_hit_msbMatch_T_28) node res_hit_msbMatch_2 = eq(_res_hit_msbMatch_T_29, UInt<1>(0h0)) node _res_hit_lsbMatch_T_20 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_21 = shl(io.pmp[5].addr, 2) node _res_hit_lsbMatch_T_22 = not(_res_hit_lsbMatch_T_21) node _res_hit_lsbMatch_T_23 = or(_res_hit_lsbMatch_T_22, UInt<2>(0h3)) node _res_hit_lsbMatch_T_24 = not(_res_hit_lsbMatch_T_23) node _res_hit_lsbMatch_T_25 = bits(_res_hit_lsbMatch_T_24, 2, 0) node _res_hit_lsbMatch_T_26 = bits(res_hit_lsbMask_2, 2, 0) node _res_hit_lsbMatch_T_27 = xor(_res_hit_lsbMatch_T_20, _res_hit_lsbMatch_T_25) node _res_hit_lsbMatch_T_28 = not(_res_hit_lsbMatch_T_26) node _res_hit_lsbMatch_T_29 = and(_res_hit_lsbMatch_T_27, _res_hit_lsbMatch_T_28) node res_hit_lsbMatch_2 = eq(_res_hit_lsbMatch_T_29, UInt<1>(0h0)) node _res_hit_T_27 = and(res_hit_msbMatch_2, res_hit_lsbMatch_2) node _res_hit_T_28 = bits(io.pmp[5].cfg.a, 0, 0) node _res_hit_T_29 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_30 = bits(_res_hit_T_29, 2, 0) node _res_hit_T_31 = not(_res_hit_T_30) node _res_hit_msbsLess_T_24 = shr(io.addr, 3) node _res_hit_msbsLess_T_25 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_26 = not(_res_hit_msbsLess_T_25) node _res_hit_msbsLess_T_27 = or(_res_hit_msbsLess_T_26, UInt<2>(0h3)) node _res_hit_msbsLess_T_28 = not(_res_hit_msbsLess_T_27) node _res_hit_msbsLess_T_29 = shr(_res_hit_msbsLess_T_28, 3) node res_hit_msbsLess_4 = lt(_res_hit_msbsLess_T_24, _res_hit_msbsLess_T_29) node _res_hit_msbsEqual_T_28 = shr(io.addr, 3) node _res_hit_msbsEqual_T_29 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_30 = not(_res_hit_msbsEqual_T_29) node _res_hit_msbsEqual_T_31 = or(_res_hit_msbsEqual_T_30, UInt<2>(0h3)) node _res_hit_msbsEqual_T_32 = not(_res_hit_msbsEqual_T_31) node _res_hit_msbsEqual_T_33 = shr(_res_hit_msbsEqual_T_32, 3) node _res_hit_msbsEqual_T_34 = xor(_res_hit_msbsEqual_T_28, _res_hit_msbsEqual_T_33) node res_hit_msbsEqual_4 = eq(_res_hit_msbsEqual_T_34, UInt<1>(0h0)) node _res_hit_lsbsLess_T_28 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_29 = or(_res_hit_lsbsLess_T_28, _res_hit_T_31) node _res_hit_lsbsLess_T_30 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_31 = not(_res_hit_lsbsLess_T_30) node _res_hit_lsbsLess_T_32 = or(_res_hit_lsbsLess_T_31, UInt<2>(0h3)) node _res_hit_lsbsLess_T_33 = not(_res_hit_lsbsLess_T_32) node _res_hit_lsbsLess_T_34 = bits(_res_hit_lsbsLess_T_33, 2, 0) node res_hit_lsbsLess_4 = lt(_res_hit_lsbsLess_T_29, _res_hit_lsbsLess_T_34) node _res_hit_T_32 = and(res_hit_msbsEqual_4, res_hit_lsbsLess_4) node _res_hit_T_33 = or(res_hit_msbsLess_4, _res_hit_T_32) node _res_hit_T_34 = eq(_res_hit_T_33, UInt<1>(0h0)) node _res_hit_msbsLess_T_30 = shr(io.addr, 3) node _res_hit_msbsLess_T_31 = shl(io.pmp[5].addr, 2) node _res_hit_msbsLess_T_32 = not(_res_hit_msbsLess_T_31) node _res_hit_msbsLess_T_33 = or(_res_hit_msbsLess_T_32, UInt<2>(0h3)) node _res_hit_msbsLess_T_34 = not(_res_hit_msbsLess_T_33) node _res_hit_msbsLess_T_35 = shr(_res_hit_msbsLess_T_34, 3) node res_hit_msbsLess_5 = lt(_res_hit_msbsLess_T_30, _res_hit_msbsLess_T_35) node _res_hit_msbsEqual_T_35 = shr(io.addr, 3) node _res_hit_msbsEqual_T_36 = shl(io.pmp[5].addr, 2) node _res_hit_msbsEqual_T_37 = not(_res_hit_msbsEqual_T_36) node _res_hit_msbsEqual_T_38 = or(_res_hit_msbsEqual_T_37, UInt<2>(0h3)) node _res_hit_msbsEqual_T_39 = not(_res_hit_msbsEqual_T_38) node _res_hit_msbsEqual_T_40 = shr(_res_hit_msbsEqual_T_39, 3) node _res_hit_msbsEqual_T_41 = xor(_res_hit_msbsEqual_T_35, _res_hit_msbsEqual_T_40) node res_hit_msbsEqual_5 = eq(_res_hit_msbsEqual_T_41, UInt<1>(0h0)) node _res_hit_lsbsLess_T_35 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_36 = or(_res_hit_lsbsLess_T_35, UInt<1>(0h0)) node _res_hit_lsbsLess_T_37 = shl(io.pmp[5].addr, 2) node _res_hit_lsbsLess_T_38 = not(_res_hit_lsbsLess_T_37) node _res_hit_lsbsLess_T_39 = or(_res_hit_lsbsLess_T_38, UInt<2>(0h3)) node _res_hit_lsbsLess_T_40 = not(_res_hit_lsbsLess_T_39) node _res_hit_lsbsLess_T_41 = bits(_res_hit_lsbsLess_T_40, 2, 0) node res_hit_lsbsLess_5 = lt(_res_hit_lsbsLess_T_36, _res_hit_lsbsLess_T_41) node _res_hit_T_35 = and(res_hit_msbsEqual_5, res_hit_lsbsLess_5) node _res_hit_T_36 = or(res_hit_msbsLess_5, _res_hit_T_35) node _res_hit_T_37 = and(_res_hit_T_34, _res_hit_T_36) node _res_hit_T_38 = and(_res_hit_T_28, _res_hit_T_37) node res_hit_2 = mux(_res_hit_T_26, _res_hit_T_27, _res_hit_T_38) node _res_ignore_T_2 = eq(io.pmp[5].cfg.l, UInt<1>(0h0)) node res_ignore_2 = and(default, _res_ignore_T_2) node _res_aligned_lsbMask_T_4 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_5 = bits(_res_aligned_lsbMask_T_4, 2, 0) node res_aligned_lsbMask_2 = not(_res_aligned_lsbMask_T_5) node _res_aligned_straddlesLowerBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_35 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_36 = not(_res_aligned_straddlesLowerBound_T_35) node _res_aligned_straddlesLowerBound_T_37 = or(_res_aligned_straddlesLowerBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_38 = not(_res_aligned_straddlesLowerBound_T_37) node _res_aligned_straddlesLowerBound_T_39 = shr(_res_aligned_straddlesLowerBound_T_38, 3) node _res_aligned_straddlesLowerBound_T_40 = xor(_res_aligned_straddlesLowerBound_T_34, _res_aligned_straddlesLowerBound_T_39) node _res_aligned_straddlesLowerBound_T_41 = eq(_res_aligned_straddlesLowerBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_42 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesLowerBound_T_43 = not(_res_aligned_straddlesLowerBound_T_42) node _res_aligned_straddlesLowerBound_T_44 = or(_res_aligned_straddlesLowerBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_45 = not(_res_aligned_straddlesLowerBound_T_44) node _res_aligned_straddlesLowerBound_T_46 = bits(_res_aligned_straddlesLowerBound_T_45, 2, 0) node _res_aligned_straddlesLowerBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_48 = not(_res_aligned_straddlesLowerBound_T_47) node _res_aligned_straddlesLowerBound_T_49 = and(_res_aligned_straddlesLowerBound_T_46, _res_aligned_straddlesLowerBound_T_48) node _res_aligned_straddlesLowerBound_T_50 = neq(_res_aligned_straddlesLowerBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_2 = and(_res_aligned_straddlesLowerBound_T_41, _res_aligned_straddlesLowerBound_T_50) node _res_aligned_straddlesUpperBound_T_34 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_35 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_36 = not(_res_aligned_straddlesUpperBound_T_35) node _res_aligned_straddlesUpperBound_T_37 = or(_res_aligned_straddlesUpperBound_T_36, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_38 = not(_res_aligned_straddlesUpperBound_T_37) node _res_aligned_straddlesUpperBound_T_39 = shr(_res_aligned_straddlesUpperBound_T_38, 3) node _res_aligned_straddlesUpperBound_T_40 = xor(_res_aligned_straddlesUpperBound_T_34, _res_aligned_straddlesUpperBound_T_39) node _res_aligned_straddlesUpperBound_T_41 = eq(_res_aligned_straddlesUpperBound_T_40, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_42 = shl(io.pmp[5].addr, 2) node _res_aligned_straddlesUpperBound_T_43 = not(_res_aligned_straddlesUpperBound_T_42) node _res_aligned_straddlesUpperBound_T_44 = or(_res_aligned_straddlesUpperBound_T_43, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_45 = not(_res_aligned_straddlesUpperBound_T_44) node _res_aligned_straddlesUpperBound_T_46 = bits(_res_aligned_straddlesUpperBound_T_45, 2, 0) node _res_aligned_straddlesUpperBound_T_47 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_48 = or(_res_aligned_straddlesUpperBound_T_47, res_aligned_lsbMask_2) node _res_aligned_straddlesUpperBound_T_49 = and(_res_aligned_straddlesUpperBound_T_46, _res_aligned_straddlesUpperBound_T_48) node _res_aligned_straddlesUpperBound_T_50 = neq(_res_aligned_straddlesUpperBound_T_49, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_2 = and(_res_aligned_straddlesUpperBound_T_41, _res_aligned_straddlesUpperBound_T_50) node _res_aligned_rangeAligned_T_2 = or(res_aligned_straddlesLowerBound_2, res_aligned_straddlesUpperBound_2) node res_aligned_rangeAligned_2 = eq(_res_aligned_rangeAligned_T_2, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_6 = bits(io.pmp[5].mask, 2, 0) node _res_aligned_pow2Aligned_T_7 = not(_res_aligned_pow2Aligned_T_6) node _res_aligned_pow2Aligned_T_8 = and(res_aligned_lsbMask_2, _res_aligned_pow2Aligned_T_7) node res_aligned_pow2Aligned_2 = eq(_res_aligned_pow2Aligned_T_8, UInt<1>(0h0)) node _res_aligned_T_2 = bits(io.pmp[5].cfg.a, 1, 1) node res_aligned_2 = mux(_res_aligned_T_2, res_aligned_pow2Aligned_2, res_aligned_rangeAligned_2) node _res_T_90 = eq(io.pmp[5].cfg.a, UInt<1>(0h0)) node _res_T_91 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_92 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_93 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_94 = eq(io.pmp[5].cfg.l, UInt<1>(0h1)) node res_hi_12 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_95 = cat(res_hi_12, io.pmp[5].cfg.r) node _res_T_96 = eq(_res_T_95, UInt<1>(0h0)) node res_hi_13 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_97 = cat(res_hi_13, io.pmp[5].cfg.r) node _res_T_98 = eq(_res_T_97, UInt<1>(0h1)) node res_hi_14 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_99 = cat(res_hi_14, io.pmp[5].cfg.r) node _res_T_100 = eq(_res_T_99, UInt<2>(0h3)) node res_hi_15 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_101 = cat(res_hi_15, io.pmp[5].cfg.r) node _res_T_102 = eq(_res_T_101, UInt<3>(0h4)) node res_hi_16 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_103 = cat(res_hi_16, io.pmp[5].cfg.r) node _res_T_104 = eq(_res_T_103, UInt<3>(0h5)) node res_hi_17 = cat(io.pmp[5].cfg.x, io.pmp[5].cfg.w) node _res_T_105 = cat(res_hi_17, io.pmp[5].cfg.r) node _res_T_106 = eq(_res_T_105, UInt<3>(0h7)) node _res_T_107 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_108 = and(_res_T_107, res_hit_2) node _res_T_109 = and(_res_T_108, res_aligned_2) node _res_T_110 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_111 = and(_res_T_109, _res_T_110) node _res_T_112 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_113 = and(_res_T_112, res_aligned_2) node _res_T_114 = eq(io.pmp[5].cfg.a, UInt<1>(0h1)) node _res_T_115 = and(_res_T_113, _res_T_114) node _res_T_116 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_117 = and(_res_T_116, res_hit_2) node _res_T_118 = and(_res_T_117, res_aligned_2) node _res_T_119 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_120 = and(_res_T_118, _res_T_119) node _res_T_121 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_122 = and(_res_T_121, res_aligned_2) node _res_T_123 = eq(io.pmp[5].cfg.a, UInt<2>(0h2)) node _res_T_124 = and(_res_T_122, _res_T_123) node _res_T_125 = eq(res_ignore_2, UInt<1>(0h0)) node _res_T_126 = and(_res_T_125, res_hit_2) node _res_T_127 = and(_res_T_126, res_aligned_2) node _res_T_128 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_129 = and(_res_T_127, _res_T_128) node _res_T_130 = and(io.pmp[5].cfg.l, res_hit_2) node _res_T_131 = and(_res_T_130, res_aligned_2) node _res_T_132 = eq(io.pmp[5].cfg.a, UInt<2>(0h3)) node _res_T_133 = and(_res_T_131, _res_T_132) wire res_cur_2 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_2, io.pmp[5] node _res_cur_cfg_r_T_4 = or(io.pmp[5].cfg.r, res_ignore_2) node _res_cur_cfg_r_T_5 = and(res_aligned_2, _res_cur_cfg_r_T_4) connect res_cur_2.cfg.r, _res_cur_cfg_r_T_5 node _res_cur_cfg_w_T_4 = or(io.pmp[5].cfg.w, res_ignore_2) node _res_cur_cfg_w_T_5 = and(res_aligned_2, _res_cur_cfg_w_T_4) connect res_cur_2.cfg.w, _res_cur_cfg_w_T_5 node _res_cur_cfg_x_T_4 = or(io.pmp[5].cfg.x, res_ignore_2) node _res_cur_cfg_x_T_5 = and(res_aligned_2, _res_cur_cfg_x_T_4) connect res_cur_2.cfg.x, _res_cur_cfg_x_T_5 node _res_T_134 = mux(res_hit_2, res_cur_2, _res_T_89) node _res_hit_T_39 = bits(io.pmp[4].cfg.a, 1, 1) node _res_hit_lsbMask_T_9 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_10 = bits(_res_hit_lsbMask_T_9, 2, 0) node _res_hit_lsbMask_T_11 = not(_res_hit_lsbMask_T_10) node res_hit_lsbMask_3 = or(io.pmp[4].mask, _res_hit_lsbMask_T_11) node _res_hit_msbMatch_T_30 = shr(io.addr, 3) node _res_hit_msbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_msbMatch_T_32 = not(_res_hit_msbMatch_T_31) node _res_hit_msbMatch_T_33 = or(_res_hit_msbMatch_T_32, UInt<2>(0h3)) node _res_hit_msbMatch_T_34 = not(_res_hit_msbMatch_T_33) node _res_hit_msbMatch_T_35 = shr(_res_hit_msbMatch_T_34, 3) node _res_hit_msbMatch_T_36 = shr(io.pmp[4].mask, 3) node _res_hit_msbMatch_T_37 = xor(_res_hit_msbMatch_T_30, _res_hit_msbMatch_T_35) node _res_hit_msbMatch_T_38 = not(_res_hit_msbMatch_T_36) node _res_hit_msbMatch_T_39 = and(_res_hit_msbMatch_T_37, _res_hit_msbMatch_T_38) node res_hit_msbMatch_3 = eq(_res_hit_msbMatch_T_39, UInt<1>(0h0)) node _res_hit_lsbMatch_T_30 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_31 = shl(io.pmp[4].addr, 2) node _res_hit_lsbMatch_T_32 = not(_res_hit_lsbMatch_T_31) node _res_hit_lsbMatch_T_33 = or(_res_hit_lsbMatch_T_32, UInt<2>(0h3)) node _res_hit_lsbMatch_T_34 = not(_res_hit_lsbMatch_T_33) node _res_hit_lsbMatch_T_35 = bits(_res_hit_lsbMatch_T_34, 2, 0) node _res_hit_lsbMatch_T_36 = bits(res_hit_lsbMask_3, 2, 0) node _res_hit_lsbMatch_T_37 = xor(_res_hit_lsbMatch_T_30, _res_hit_lsbMatch_T_35) node _res_hit_lsbMatch_T_38 = not(_res_hit_lsbMatch_T_36) node _res_hit_lsbMatch_T_39 = and(_res_hit_lsbMatch_T_37, _res_hit_lsbMatch_T_38) node res_hit_lsbMatch_3 = eq(_res_hit_lsbMatch_T_39, UInt<1>(0h0)) node _res_hit_T_40 = and(res_hit_msbMatch_3, res_hit_lsbMatch_3) node _res_hit_T_41 = bits(io.pmp[4].cfg.a, 0, 0) node _res_hit_T_42 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_43 = bits(_res_hit_T_42, 2, 0) node _res_hit_T_44 = not(_res_hit_T_43) node _res_hit_msbsLess_T_36 = shr(io.addr, 3) node _res_hit_msbsLess_T_37 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_38 = not(_res_hit_msbsLess_T_37) node _res_hit_msbsLess_T_39 = or(_res_hit_msbsLess_T_38, UInt<2>(0h3)) node _res_hit_msbsLess_T_40 = not(_res_hit_msbsLess_T_39) node _res_hit_msbsLess_T_41 = shr(_res_hit_msbsLess_T_40, 3) node res_hit_msbsLess_6 = lt(_res_hit_msbsLess_T_36, _res_hit_msbsLess_T_41) node _res_hit_msbsEqual_T_42 = shr(io.addr, 3) node _res_hit_msbsEqual_T_43 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_44 = not(_res_hit_msbsEqual_T_43) node _res_hit_msbsEqual_T_45 = or(_res_hit_msbsEqual_T_44, UInt<2>(0h3)) node _res_hit_msbsEqual_T_46 = not(_res_hit_msbsEqual_T_45) node _res_hit_msbsEqual_T_47 = shr(_res_hit_msbsEqual_T_46, 3) node _res_hit_msbsEqual_T_48 = xor(_res_hit_msbsEqual_T_42, _res_hit_msbsEqual_T_47) node res_hit_msbsEqual_6 = eq(_res_hit_msbsEqual_T_48, UInt<1>(0h0)) node _res_hit_lsbsLess_T_42 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_43 = or(_res_hit_lsbsLess_T_42, _res_hit_T_44) node _res_hit_lsbsLess_T_44 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_45 = not(_res_hit_lsbsLess_T_44) node _res_hit_lsbsLess_T_46 = or(_res_hit_lsbsLess_T_45, UInt<2>(0h3)) node _res_hit_lsbsLess_T_47 = not(_res_hit_lsbsLess_T_46) node _res_hit_lsbsLess_T_48 = bits(_res_hit_lsbsLess_T_47, 2, 0) node res_hit_lsbsLess_6 = lt(_res_hit_lsbsLess_T_43, _res_hit_lsbsLess_T_48) node _res_hit_T_45 = and(res_hit_msbsEqual_6, res_hit_lsbsLess_6) node _res_hit_T_46 = or(res_hit_msbsLess_6, _res_hit_T_45) node _res_hit_T_47 = eq(_res_hit_T_46, UInt<1>(0h0)) node _res_hit_msbsLess_T_42 = shr(io.addr, 3) node _res_hit_msbsLess_T_43 = shl(io.pmp[4].addr, 2) node _res_hit_msbsLess_T_44 = not(_res_hit_msbsLess_T_43) node _res_hit_msbsLess_T_45 = or(_res_hit_msbsLess_T_44, UInt<2>(0h3)) node _res_hit_msbsLess_T_46 = not(_res_hit_msbsLess_T_45) node _res_hit_msbsLess_T_47 = shr(_res_hit_msbsLess_T_46, 3) node res_hit_msbsLess_7 = lt(_res_hit_msbsLess_T_42, _res_hit_msbsLess_T_47) node _res_hit_msbsEqual_T_49 = shr(io.addr, 3) node _res_hit_msbsEqual_T_50 = shl(io.pmp[4].addr, 2) node _res_hit_msbsEqual_T_51 = not(_res_hit_msbsEqual_T_50) node _res_hit_msbsEqual_T_52 = or(_res_hit_msbsEqual_T_51, UInt<2>(0h3)) node _res_hit_msbsEqual_T_53 = not(_res_hit_msbsEqual_T_52) node _res_hit_msbsEqual_T_54 = shr(_res_hit_msbsEqual_T_53, 3) node _res_hit_msbsEqual_T_55 = xor(_res_hit_msbsEqual_T_49, _res_hit_msbsEqual_T_54) node res_hit_msbsEqual_7 = eq(_res_hit_msbsEqual_T_55, UInt<1>(0h0)) node _res_hit_lsbsLess_T_49 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_50 = or(_res_hit_lsbsLess_T_49, UInt<1>(0h0)) node _res_hit_lsbsLess_T_51 = shl(io.pmp[4].addr, 2) node _res_hit_lsbsLess_T_52 = not(_res_hit_lsbsLess_T_51) node _res_hit_lsbsLess_T_53 = or(_res_hit_lsbsLess_T_52, UInt<2>(0h3)) node _res_hit_lsbsLess_T_54 = not(_res_hit_lsbsLess_T_53) node _res_hit_lsbsLess_T_55 = bits(_res_hit_lsbsLess_T_54, 2, 0) node res_hit_lsbsLess_7 = lt(_res_hit_lsbsLess_T_50, _res_hit_lsbsLess_T_55) node _res_hit_T_48 = and(res_hit_msbsEqual_7, res_hit_lsbsLess_7) node _res_hit_T_49 = or(res_hit_msbsLess_7, _res_hit_T_48) node _res_hit_T_50 = and(_res_hit_T_47, _res_hit_T_49) node _res_hit_T_51 = and(_res_hit_T_41, _res_hit_T_50) node res_hit_3 = mux(_res_hit_T_39, _res_hit_T_40, _res_hit_T_51) node _res_ignore_T_3 = eq(io.pmp[4].cfg.l, UInt<1>(0h0)) node res_ignore_3 = and(default, _res_ignore_T_3) node _res_aligned_lsbMask_T_6 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_7 = bits(_res_aligned_lsbMask_T_6, 2, 0) node res_aligned_lsbMask_3 = not(_res_aligned_lsbMask_T_7) node _res_aligned_straddlesLowerBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_52 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_53 = not(_res_aligned_straddlesLowerBound_T_52) node _res_aligned_straddlesLowerBound_T_54 = or(_res_aligned_straddlesLowerBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_55 = not(_res_aligned_straddlesLowerBound_T_54) node _res_aligned_straddlesLowerBound_T_56 = shr(_res_aligned_straddlesLowerBound_T_55, 3) node _res_aligned_straddlesLowerBound_T_57 = xor(_res_aligned_straddlesLowerBound_T_51, _res_aligned_straddlesLowerBound_T_56) node _res_aligned_straddlesLowerBound_T_58 = eq(_res_aligned_straddlesLowerBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_59 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesLowerBound_T_60 = not(_res_aligned_straddlesLowerBound_T_59) node _res_aligned_straddlesLowerBound_T_61 = or(_res_aligned_straddlesLowerBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_62 = not(_res_aligned_straddlesLowerBound_T_61) node _res_aligned_straddlesLowerBound_T_63 = bits(_res_aligned_straddlesLowerBound_T_62, 2, 0) node _res_aligned_straddlesLowerBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_65 = not(_res_aligned_straddlesLowerBound_T_64) node _res_aligned_straddlesLowerBound_T_66 = and(_res_aligned_straddlesLowerBound_T_63, _res_aligned_straddlesLowerBound_T_65) node _res_aligned_straddlesLowerBound_T_67 = neq(_res_aligned_straddlesLowerBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_3 = and(_res_aligned_straddlesLowerBound_T_58, _res_aligned_straddlesLowerBound_T_67) node _res_aligned_straddlesUpperBound_T_51 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_52 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_53 = not(_res_aligned_straddlesUpperBound_T_52) node _res_aligned_straddlesUpperBound_T_54 = or(_res_aligned_straddlesUpperBound_T_53, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_55 = not(_res_aligned_straddlesUpperBound_T_54) node _res_aligned_straddlesUpperBound_T_56 = shr(_res_aligned_straddlesUpperBound_T_55, 3) node _res_aligned_straddlesUpperBound_T_57 = xor(_res_aligned_straddlesUpperBound_T_51, _res_aligned_straddlesUpperBound_T_56) node _res_aligned_straddlesUpperBound_T_58 = eq(_res_aligned_straddlesUpperBound_T_57, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_59 = shl(io.pmp[4].addr, 2) node _res_aligned_straddlesUpperBound_T_60 = not(_res_aligned_straddlesUpperBound_T_59) node _res_aligned_straddlesUpperBound_T_61 = or(_res_aligned_straddlesUpperBound_T_60, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_62 = not(_res_aligned_straddlesUpperBound_T_61) node _res_aligned_straddlesUpperBound_T_63 = bits(_res_aligned_straddlesUpperBound_T_62, 2, 0) node _res_aligned_straddlesUpperBound_T_64 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_65 = or(_res_aligned_straddlesUpperBound_T_64, res_aligned_lsbMask_3) node _res_aligned_straddlesUpperBound_T_66 = and(_res_aligned_straddlesUpperBound_T_63, _res_aligned_straddlesUpperBound_T_65) node _res_aligned_straddlesUpperBound_T_67 = neq(_res_aligned_straddlesUpperBound_T_66, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_3 = and(_res_aligned_straddlesUpperBound_T_58, _res_aligned_straddlesUpperBound_T_67) node _res_aligned_rangeAligned_T_3 = or(res_aligned_straddlesLowerBound_3, res_aligned_straddlesUpperBound_3) node res_aligned_rangeAligned_3 = eq(_res_aligned_rangeAligned_T_3, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_9 = bits(io.pmp[4].mask, 2, 0) node _res_aligned_pow2Aligned_T_10 = not(_res_aligned_pow2Aligned_T_9) node _res_aligned_pow2Aligned_T_11 = and(res_aligned_lsbMask_3, _res_aligned_pow2Aligned_T_10) node res_aligned_pow2Aligned_3 = eq(_res_aligned_pow2Aligned_T_11, UInt<1>(0h0)) node _res_aligned_T_3 = bits(io.pmp[4].cfg.a, 1, 1) node res_aligned_3 = mux(_res_aligned_T_3, res_aligned_pow2Aligned_3, res_aligned_rangeAligned_3) node _res_T_135 = eq(io.pmp[4].cfg.a, UInt<1>(0h0)) node _res_T_136 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_137 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_138 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_139 = eq(io.pmp[4].cfg.l, UInt<1>(0h1)) node res_hi_18 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_140 = cat(res_hi_18, io.pmp[4].cfg.r) node _res_T_141 = eq(_res_T_140, UInt<1>(0h0)) node res_hi_19 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_142 = cat(res_hi_19, io.pmp[4].cfg.r) node _res_T_143 = eq(_res_T_142, UInt<1>(0h1)) node res_hi_20 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_144 = cat(res_hi_20, io.pmp[4].cfg.r) node _res_T_145 = eq(_res_T_144, UInt<2>(0h3)) node res_hi_21 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_146 = cat(res_hi_21, io.pmp[4].cfg.r) node _res_T_147 = eq(_res_T_146, UInt<3>(0h4)) node res_hi_22 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_148 = cat(res_hi_22, io.pmp[4].cfg.r) node _res_T_149 = eq(_res_T_148, UInt<3>(0h5)) node res_hi_23 = cat(io.pmp[4].cfg.x, io.pmp[4].cfg.w) node _res_T_150 = cat(res_hi_23, io.pmp[4].cfg.r) node _res_T_151 = eq(_res_T_150, UInt<3>(0h7)) node _res_T_152 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_153 = and(_res_T_152, res_hit_3) node _res_T_154 = and(_res_T_153, res_aligned_3) node _res_T_155 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_156 = and(_res_T_154, _res_T_155) node _res_T_157 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_158 = and(_res_T_157, res_aligned_3) node _res_T_159 = eq(io.pmp[4].cfg.a, UInt<1>(0h1)) node _res_T_160 = and(_res_T_158, _res_T_159) node _res_T_161 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_162 = and(_res_T_161, res_hit_3) node _res_T_163 = and(_res_T_162, res_aligned_3) node _res_T_164 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_165 = and(_res_T_163, _res_T_164) node _res_T_166 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_167 = and(_res_T_166, res_aligned_3) node _res_T_168 = eq(io.pmp[4].cfg.a, UInt<2>(0h2)) node _res_T_169 = and(_res_T_167, _res_T_168) node _res_T_170 = eq(res_ignore_3, UInt<1>(0h0)) node _res_T_171 = and(_res_T_170, res_hit_3) node _res_T_172 = and(_res_T_171, res_aligned_3) node _res_T_173 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_174 = and(_res_T_172, _res_T_173) node _res_T_175 = and(io.pmp[4].cfg.l, res_hit_3) node _res_T_176 = and(_res_T_175, res_aligned_3) node _res_T_177 = eq(io.pmp[4].cfg.a, UInt<2>(0h3)) node _res_T_178 = and(_res_T_176, _res_T_177) wire res_cur_3 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_3, io.pmp[4] node _res_cur_cfg_r_T_6 = or(io.pmp[4].cfg.r, res_ignore_3) node _res_cur_cfg_r_T_7 = and(res_aligned_3, _res_cur_cfg_r_T_6) connect res_cur_3.cfg.r, _res_cur_cfg_r_T_7 node _res_cur_cfg_w_T_6 = or(io.pmp[4].cfg.w, res_ignore_3) node _res_cur_cfg_w_T_7 = and(res_aligned_3, _res_cur_cfg_w_T_6) connect res_cur_3.cfg.w, _res_cur_cfg_w_T_7 node _res_cur_cfg_x_T_6 = or(io.pmp[4].cfg.x, res_ignore_3) node _res_cur_cfg_x_T_7 = and(res_aligned_3, _res_cur_cfg_x_T_6) connect res_cur_3.cfg.x, _res_cur_cfg_x_T_7 node _res_T_179 = mux(res_hit_3, res_cur_3, _res_T_134) node _res_hit_T_52 = bits(io.pmp[3].cfg.a, 1, 1) node _res_hit_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_13 = bits(_res_hit_lsbMask_T_12, 2, 0) node _res_hit_lsbMask_T_14 = not(_res_hit_lsbMask_T_13) node res_hit_lsbMask_4 = or(io.pmp[3].mask, _res_hit_lsbMask_T_14) node _res_hit_msbMatch_T_40 = shr(io.addr, 3) node _res_hit_msbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_msbMatch_T_42 = not(_res_hit_msbMatch_T_41) node _res_hit_msbMatch_T_43 = or(_res_hit_msbMatch_T_42, UInt<2>(0h3)) node _res_hit_msbMatch_T_44 = not(_res_hit_msbMatch_T_43) node _res_hit_msbMatch_T_45 = shr(_res_hit_msbMatch_T_44, 3) node _res_hit_msbMatch_T_46 = shr(io.pmp[3].mask, 3) node _res_hit_msbMatch_T_47 = xor(_res_hit_msbMatch_T_40, _res_hit_msbMatch_T_45) node _res_hit_msbMatch_T_48 = not(_res_hit_msbMatch_T_46) node _res_hit_msbMatch_T_49 = and(_res_hit_msbMatch_T_47, _res_hit_msbMatch_T_48) node res_hit_msbMatch_4 = eq(_res_hit_msbMatch_T_49, UInt<1>(0h0)) node _res_hit_lsbMatch_T_40 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_41 = shl(io.pmp[3].addr, 2) node _res_hit_lsbMatch_T_42 = not(_res_hit_lsbMatch_T_41) node _res_hit_lsbMatch_T_43 = or(_res_hit_lsbMatch_T_42, UInt<2>(0h3)) node _res_hit_lsbMatch_T_44 = not(_res_hit_lsbMatch_T_43) node _res_hit_lsbMatch_T_45 = bits(_res_hit_lsbMatch_T_44, 2, 0) node _res_hit_lsbMatch_T_46 = bits(res_hit_lsbMask_4, 2, 0) node _res_hit_lsbMatch_T_47 = xor(_res_hit_lsbMatch_T_40, _res_hit_lsbMatch_T_45) node _res_hit_lsbMatch_T_48 = not(_res_hit_lsbMatch_T_46) node _res_hit_lsbMatch_T_49 = and(_res_hit_lsbMatch_T_47, _res_hit_lsbMatch_T_48) node res_hit_lsbMatch_4 = eq(_res_hit_lsbMatch_T_49, UInt<1>(0h0)) node _res_hit_T_53 = and(res_hit_msbMatch_4, res_hit_lsbMatch_4) node _res_hit_T_54 = bits(io.pmp[3].cfg.a, 0, 0) node _res_hit_T_55 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_56 = bits(_res_hit_T_55, 2, 0) node _res_hit_T_57 = not(_res_hit_T_56) node _res_hit_msbsLess_T_48 = shr(io.addr, 3) node _res_hit_msbsLess_T_49 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_50 = not(_res_hit_msbsLess_T_49) node _res_hit_msbsLess_T_51 = or(_res_hit_msbsLess_T_50, UInt<2>(0h3)) node _res_hit_msbsLess_T_52 = not(_res_hit_msbsLess_T_51) node _res_hit_msbsLess_T_53 = shr(_res_hit_msbsLess_T_52, 3) node res_hit_msbsLess_8 = lt(_res_hit_msbsLess_T_48, _res_hit_msbsLess_T_53) node _res_hit_msbsEqual_T_56 = shr(io.addr, 3) node _res_hit_msbsEqual_T_57 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_58 = not(_res_hit_msbsEqual_T_57) node _res_hit_msbsEqual_T_59 = or(_res_hit_msbsEqual_T_58, UInt<2>(0h3)) node _res_hit_msbsEqual_T_60 = not(_res_hit_msbsEqual_T_59) node _res_hit_msbsEqual_T_61 = shr(_res_hit_msbsEqual_T_60, 3) node _res_hit_msbsEqual_T_62 = xor(_res_hit_msbsEqual_T_56, _res_hit_msbsEqual_T_61) node res_hit_msbsEqual_8 = eq(_res_hit_msbsEqual_T_62, UInt<1>(0h0)) node _res_hit_lsbsLess_T_56 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_57 = or(_res_hit_lsbsLess_T_56, _res_hit_T_57) node _res_hit_lsbsLess_T_58 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_59 = not(_res_hit_lsbsLess_T_58) node _res_hit_lsbsLess_T_60 = or(_res_hit_lsbsLess_T_59, UInt<2>(0h3)) node _res_hit_lsbsLess_T_61 = not(_res_hit_lsbsLess_T_60) node _res_hit_lsbsLess_T_62 = bits(_res_hit_lsbsLess_T_61, 2, 0) node res_hit_lsbsLess_8 = lt(_res_hit_lsbsLess_T_57, _res_hit_lsbsLess_T_62) node _res_hit_T_58 = and(res_hit_msbsEqual_8, res_hit_lsbsLess_8) node _res_hit_T_59 = or(res_hit_msbsLess_8, _res_hit_T_58) node _res_hit_T_60 = eq(_res_hit_T_59, UInt<1>(0h0)) node _res_hit_msbsLess_T_54 = shr(io.addr, 3) node _res_hit_msbsLess_T_55 = shl(io.pmp[3].addr, 2) node _res_hit_msbsLess_T_56 = not(_res_hit_msbsLess_T_55) node _res_hit_msbsLess_T_57 = or(_res_hit_msbsLess_T_56, UInt<2>(0h3)) node _res_hit_msbsLess_T_58 = not(_res_hit_msbsLess_T_57) node _res_hit_msbsLess_T_59 = shr(_res_hit_msbsLess_T_58, 3) node res_hit_msbsLess_9 = lt(_res_hit_msbsLess_T_54, _res_hit_msbsLess_T_59) node _res_hit_msbsEqual_T_63 = shr(io.addr, 3) node _res_hit_msbsEqual_T_64 = shl(io.pmp[3].addr, 2) node _res_hit_msbsEqual_T_65 = not(_res_hit_msbsEqual_T_64) node _res_hit_msbsEqual_T_66 = or(_res_hit_msbsEqual_T_65, UInt<2>(0h3)) node _res_hit_msbsEqual_T_67 = not(_res_hit_msbsEqual_T_66) node _res_hit_msbsEqual_T_68 = shr(_res_hit_msbsEqual_T_67, 3) node _res_hit_msbsEqual_T_69 = xor(_res_hit_msbsEqual_T_63, _res_hit_msbsEqual_T_68) node res_hit_msbsEqual_9 = eq(_res_hit_msbsEqual_T_69, UInt<1>(0h0)) node _res_hit_lsbsLess_T_63 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_64 = or(_res_hit_lsbsLess_T_63, UInt<1>(0h0)) node _res_hit_lsbsLess_T_65 = shl(io.pmp[3].addr, 2) node _res_hit_lsbsLess_T_66 = not(_res_hit_lsbsLess_T_65) node _res_hit_lsbsLess_T_67 = or(_res_hit_lsbsLess_T_66, UInt<2>(0h3)) node _res_hit_lsbsLess_T_68 = not(_res_hit_lsbsLess_T_67) node _res_hit_lsbsLess_T_69 = bits(_res_hit_lsbsLess_T_68, 2, 0) node res_hit_lsbsLess_9 = lt(_res_hit_lsbsLess_T_64, _res_hit_lsbsLess_T_69) node _res_hit_T_61 = and(res_hit_msbsEqual_9, res_hit_lsbsLess_9) node _res_hit_T_62 = or(res_hit_msbsLess_9, _res_hit_T_61) node _res_hit_T_63 = and(_res_hit_T_60, _res_hit_T_62) node _res_hit_T_64 = and(_res_hit_T_54, _res_hit_T_63) node res_hit_4 = mux(_res_hit_T_52, _res_hit_T_53, _res_hit_T_64) node _res_ignore_T_4 = eq(io.pmp[3].cfg.l, UInt<1>(0h0)) node res_ignore_4 = and(default, _res_ignore_T_4) node _res_aligned_lsbMask_T_8 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_9 = bits(_res_aligned_lsbMask_T_8, 2, 0) node res_aligned_lsbMask_4 = not(_res_aligned_lsbMask_T_9) node _res_aligned_straddlesLowerBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_69 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_70 = not(_res_aligned_straddlesLowerBound_T_69) node _res_aligned_straddlesLowerBound_T_71 = or(_res_aligned_straddlesLowerBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_72 = not(_res_aligned_straddlesLowerBound_T_71) node _res_aligned_straddlesLowerBound_T_73 = shr(_res_aligned_straddlesLowerBound_T_72, 3) node _res_aligned_straddlesLowerBound_T_74 = xor(_res_aligned_straddlesLowerBound_T_68, _res_aligned_straddlesLowerBound_T_73) node _res_aligned_straddlesLowerBound_T_75 = eq(_res_aligned_straddlesLowerBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_76 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesLowerBound_T_77 = not(_res_aligned_straddlesLowerBound_T_76) node _res_aligned_straddlesLowerBound_T_78 = or(_res_aligned_straddlesLowerBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_79 = not(_res_aligned_straddlesLowerBound_T_78) node _res_aligned_straddlesLowerBound_T_80 = bits(_res_aligned_straddlesLowerBound_T_79, 2, 0) node _res_aligned_straddlesLowerBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_82 = not(_res_aligned_straddlesLowerBound_T_81) node _res_aligned_straddlesLowerBound_T_83 = and(_res_aligned_straddlesLowerBound_T_80, _res_aligned_straddlesLowerBound_T_82) node _res_aligned_straddlesLowerBound_T_84 = neq(_res_aligned_straddlesLowerBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_4 = and(_res_aligned_straddlesLowerBound_T_75, _res_aligned_straddlesLowerBound_T_84) node _res_aligned_straddlesUpperBound_T_68 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_69 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_70 = not(_res_aligned_straddlesUpperBound_T_69) node _res_aligned_straddlesUpperBound_T_71 = or(_res_aligned_straddlesUpperBound_T_70, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_72 = not(_res_aligned_straddlesUpperBound_T_71) node _res_aligned_straddlesUpperBound_T_73 = shr(_res_aligned_straddlesUpperBound_T_72, 3) node _res_aligned_straddlesUpperBound_T_74 = xor(_res_aligned_straddlesUpperBound_T_68, _res_aligned_straddlesUpperBound_T_73) node _res_aligned_straddlesUpperBound_T_75 = eq(_res_aligned_straddlesUpperBound_T_74, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_76 = shl(io.pmp[3].addr, 2) node _res_aligned_straddlesUpperBound_T_77 = not(_res_aligned_straddlesUpperBound_T_76) node _res_aligned_straddlesUpperBound_T_78 = or(_res_aligned_straddlesUpperBound_T_77, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_79 = not(_res_aligned_straddlesUpperBound_T_78) node _res_aligned_straddlesUpperBound_T_80 = bits(_res_aligned_straddlesUpperBound_T_79, 2, 0) node _res_aligned_straddlesUpperBound_T_81 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_82 = or(_res_aligned_straddlesUpperBound_T_81, res_aligned_lsbMask_4) node _res_aligned_straddlesUpperBound_T_83 = and(_res_aligned_straddlesUpperBound_T_80, _res_aligned_straddlesUpperBound_T_82) node _res_aligned_straddlesUpperBound_T_84 = neq(_res_aligned_straddlesUpperBound_T_83, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_4 = and(_res_aligned_straddlesUpperBound_T_75, _res_aligned_straddlesUpperBound_T_84) node _res_aligned_rangeAligned_T_4 = or(res_aligned_straddlesLowerBound_4, res_aligned_straddlesUpperBound_4) node res_aligned_rangeAligned_4 = eq(_res_aligned_rangeAligned_T_4, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_12 = bits(io.pmp[3].mask, 2, 0) node _res_aligned_pow2Aligned_T_13 = not(_res_aligned_pow2Aligned_T_12) node _res_aligned_pow2Aligned_T_14 = and(res_aligned_lsbMask_4, _res_aligned_pow2Aligned_T_13) node res_aligned_pow2Aligned_4 = eq(_res_aligned_pow2Aligned_T_14, UInt<1>(0h0)) node _res_aligned_T_4 = bits(io.pmp[3].cfg.a, 1, 1) node res_aligned_4 = mux(_res_aligned_T_4, res_aligned_pow2Aligned_4, res_aligned_rangeAligned_4) node _res_T_180 = eq(io.pmp[3].cfg.a, UInt<1>(0h0)) node _res_T_181 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_182 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_183 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_184 = eq(io.pmp[3].cfg.l, UInt<1>(0h1)) node res_hi_24 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_185 = cat(res_hi_24, io.pmp[3].cfg.r) node _res_T_186 = eq(_res_T_185, UInt<1>(0h0)) node res_hi_25 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_187 = cat(res_hi_25, io.pmp[3].cfg.r) node _res_T_188 = eq(_res_T_187, UInt<1>(0h1)) node res_hi_26 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_189 = cat(res_hi_26, io.pmp[3].cfg.r) node _res_T_190 = eq(_res_T_189, UInt<2>(0h3)) node res_hi_27 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_191 = cat(res_hi_27, io.pmp[3].cfg.r) node _res_T_192 = eq(_res_T_191, UInt<3>(0h4)) node res_hi_28 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_193 = cat(res_hi_28, io.pmp[3].cfg.r) node _res_T_194 = eq(_res_T_193, UInt<3>(0h5)) node res_hi_29 = cat(io.pmp[3].cfg.x, io.pmp[3].cfg.w) node _res_T_195 = cat(res_hi_29, io.pmp[3].cfg.r) node _res_T_196 = eq(_res_T_195, UInt<3>(0h7)) node _res_T_197 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_198 = and(_res_T_197, res_hit_4) node _res_T_199 = and(_res_T_198, res_aligned_4) node _res_T_200 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_201 = and(_res_T_199, _res_T_200) node _res_T_202 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_203 = and(_res_T_202, res_aligned_4) node _res_T_204 = eq(io.pmp[3].cfg.a, UInt<1>(0h1)) node _res_T_205 = and(_res_T_203, _res_T_204) node _res_T_206 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_207 = and(_res_T_206, res_hit_4) node _res_T_208 = and(_res_T_207, res_aligned_4) node _res_T_209 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_210 = and(_res_T_208, _res_T_209) node _res_T_211 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_212 = and(_res_T_211, res_aligned_4) node _res_T_213 = eq(io.pmp[3].cfg.a, UInt<2>(0h2)) node _res_T_214 = and(_res_T_212, _res_T_213) node _res_T_215 = eq(res_ignore_4, UInt<1>(0h0)) node _res_T_216 = and(_res_T_215, res_hit_4) node _res_T_217 = and(_res_T_216, res_aligned_4) node _res_T_218 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_219 = and(_res_T_217, _res_T_218) node _res_T_220 = and(io.pmp[3].cfg.l, res_hit_4) node _res_T_221 = and(_res_T_220, res_aligned_4) node _res_T_222 = eq(io.pmp[3].cfg.a, UInt<2>(0h3)) node _res_T_223 = and(_res_T_221, _res_T_222) wire res_cur_4 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_4, io.pmp[3] node _res_cur_cfg_r_T_8 = or(io.pmp[3].cfg.r, res_ignore_4) node _res_cur_cfg_r_T_9 = and(res_aligned_4, _res_cur_cfg_r_T_8) connect res_cur_4.cfg.r, _res_cur_cfg_r_T_9 node _res_cur_cfg_w_T_8 = or(io.pmp[3].cfg.w, res_ignore_4) node _res_cur_cfg_w_T_9 = and(res_aligned_4, _res_cur_cfg_w_T_8) connect res_cur_4.cfg.w, _res_cur_cfg_w_T_9 node _res_cur_cfg_x_T_8 = or(io.pmp[3].cfg.x, res_ignore_4) node _res_cur_cfg_x_T_9 = and(res_aligned_4, _res_cur_cfg_x_T_8) connect res_cur_4.cfg.x, _res_cur_cfg_x_T_9 node _res_T_224 = mux(res_hit_4, res_cur_4, _res_T_179) node _res_hit_T_65 = bits(io.pmp[2].cfg.a, 1, 1) node _res_hit_lsbMask_T_15 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_16 = bits(_res_hit_lsbMask_T_15, 2, 0) node _res_hit_lsbMask_T_17 = not(_res_hit_lsbMask_T_16) node res_hit_lsbMask_5 = or(io.pmp[2].mask, _res_hit_lsbMask_T_17) node _res_hit_msbMatch_T_50 = shr(io.addr, 3) node _res_hit_msbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_msbMatch_T_52 = not(_res_hit_msbMatch_T_51) node _res_hit_msbMatch_T_53 = or(_res_hit_msbMatch_T_52, UInt<2>(0h3)) node _res_hit_msbMatch_T_54 = not(_res_hit_msbMatch_T_53) node _res_hit_msbMatch_T_55 = shr(_res_hit_msbMatch_T_54, 3) node _res_hit_msbMatch_T_56 = shr(io.pmp[2].mask, 3) node _res_hit_msbMatch_T_57 = xor(_res_hit_msbMatch_T_50, _res_hit_msbMatch_T_55) node _res_hit_msbMatch_T_58 = not(_res_hit_msbMatch_T_56) node _res_hit_msbMatch_T_59 = and(_res_hit_msbMatch_T_57, _res_hit_msbMatch_T_58) node res_hit_msbMatch_5 = eq(_res_hit_msbMatch_T_59, UInt<1>(0h0)) node _res_hit_lsbMatch_T_50 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_51 = shl(io.pmp[2].addr, 2) node _res_hit_lsbMatch_T_52 = not(_res_hit_lsbMatch_T_51) node _res_hit_lsbMatch_T_53 = or(_res_hit_lsbMatch_T_52, UInt<2>(0h3)) node _res_hit_lsbMatch_T_54 = not(_res_hit_lsbMatch_T_53) node _res_hit_lsbMatch_T_55 = bits(_res_hit_lsbMatch_T_54, 2, 0) node _res_hit_lsbMatch_T_56 = bits(res_hit_lsbMask_5, 2, 0) node _res_hit_lsbMatch_T_57 = xor(_res_hit_lsbMatch_T_50, _res_hit_lsbMatch_T_55) node _res_hit_lsbMatch_T_58 = not(_res_hit_lsbMatch_T_56) node _res_hit_lsbMatch_T_59 = and(_res_hit_lsbMatch_T_57, _res_hit_lsbMatch_T_58) node res_hit_lsbMatch_5 = eq(_res_hit_lsbMatch_T_59, UInt<1>(0h0)) node _res_hit_T_66 = and(res_hit_msbMatch_5, res_hit_lsbMatch_5) node _res_hit_T_67 = bits(io.pmp[2].cfg.a, 0, 0) node _res_hit_T_68 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_69 = bits(_res_hit_T_68, 2, 0) node _res_hit_T_70 = not(_res_hit_T_69) node _res_hit_msbsLess_T_60 = shr(io.addr, 3) node _res_hit_msbsLess_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_62 = not(_res_hit_msbsLess_T_61) node _res_hit_msbsLess_T_63 = or(_res_hit_msbsLess_T_62, UInt<2>(0h3)) node _res_hit_msbsLess_T_64 = not(_res_hit_msbsLess_T_63) node _res_hit_msbsLess_T_65 = shr(_res_hit_msbsLess_T_64, 3) node res_hit_msbsLess_10 = lt(_res_hit_msbsLess_T_60, _res_hit_msbsLess_T_65) node _res_hit_msbsEqual_T_70 = shr(io.addr, 3) node _res_hit_msbsEqual_T_71 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_72 = not(_res_hit_msbsEqual_T_71) node _res_hit_msbsEqual_T_73 = or(_res_hit_msbsEqual_T_72, UInt<2>(0h3)) node _res_hit_msbsEqual_T_74 = not(_res_hit_msbsEqual_T_73) node _res_hit_msbsEqual_T_75 = shr(_res_hit_msbsEqual_T_74, 3) node _res_hit_msbsEqual_T_76 = xor(_res_hit_msbsEqual_T_70, _res_hit_msbsEqual_T_75) node res_hit_msbsEqual_10 = eq(_res_hit_msbsEqual_T_76, UInt<1>(0h0)) node _res_hit_lsbsLess_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_71 = or(_res_hit_lsbsLess_T_70, _res_hit_T_70) node _res_hit_lsbsLess_T_72 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_73 = not(_res_hit_lsbsLess_T_72) node _res_hit_lsbsLess_T_74 = or(_res_hit_lsbsLess_T_73, UInt<2>(0h3)) node _res_hit_lsbsLess_T_75 = not(_res_hit_lsbsLess_T_74) node _res_hit_lsbsLess_T_76 = bits(_res_hit_lsbsLess_T_75, 2, 0) node res_hit_lsbsLess_10 = lt(_res_hit_lsbsLess_T_71, _res_hit_lsbsLess_T_76) node _res_hit_T_71 = and(res_hit_msbsEqual_10, res_hit_lsbsLess_10) node _res_hit_T_72 = or(res_hit_msbsLess_10, _res_hit_T_71) node _res_hit_T_73 = eq(_res_hit_T_72, UInt<1>(0h0)) node _res_hit_msbsLess_T_66 = shr(io.addr, 3) node _res_hit_msbsLess_T_67 = shl(io.pmp[2].addr, 2) node _res_hit_msbsLess_T_68 = not(_res_hit_msbsLess_T_67) node _res_hit_msbsLess_T_69 = or(_res_hit_msbsLess_T_68, UInt<2>(0h3)) node _res_hit_msbsLess_T_70 = not(_res_hit_msbsLess_T_69) node _res_hit_msbsLess_T_71 = shr(_res_hit_msbsLess_T_70, 3) node res_hit_msbsLess_11 = lt(_res_hit_msbsLess_T_66, _res_hit_msbsLess_T_71) node _res_hit_msbsEqual_T_77 = shr(io.addr, 3) node _res_hit_msbsEqual_T_78 = shl(io.pmp[2].addr, 2) node _res_hit_msbsEqual_T_79 = not(_res_hit_msbsEqual_T_78) node _res_hit_msbsEqual_T_80 = or(_res_hit_msbsEqual_T_79, UInt<2>(0h3)) node _res_hit_msbsEqual_T_81 = not(_res_hit_msbsEqual_T_80) node _res_hit_msbsEqual_T_82 = shr(_res_hit_msbsEqual_T_81, 3) node _res_hit_msbsEqual_T_83 = xor(_res_hit_msbsEqual_T_77, _res_hit_msbsEqual_T_82) node res_hit_msbsEqual_11 = eq(_res_hit_msbsEqual_T_83, UInt<1>(0h0)) node _res_hit_lsbsLess_T_77 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_78 = or(_res_hit_lsbsLess_T_77, UInt<1>(0h0)) node _res_hit_lsbsLess_T_79 = shl(io.pmp[2].addr, 2) node _res_hit_lsbsLess_T_80 = not(_res_hit_lsbsLess_T_79) node _res_hit_lsbsLess_T_81 = or(_res_hit_lsbsLess_T_80, UInt<2>(0h3)) node _res_hit_lsbsLess_T_82 = not(_res_hit_lsbsLess_T_81) node _res_hit_lsbsLess_T_83 = bits(_res_hit_lsbsLess_T_82, 2, 0) node res_hit_lsbsLess_11 = lt(_res_hit_lsbsLess_T_78, _res_hit_lsbsLess_T_83) node _res_hit_T_74 = and(res_hit_msbsEqual_11, res_hit_lsbsLess_11) node _res_hit_T_75 = or(res_hit_msbsLess_11, _res_hit_T_74) node _res_hit_T_76 = and(_res_hit_T_73, _res_hit_T_75) node _res_hit_T_77 = and(_res_hit_T_67, _res_hit_T_76) node res_hit_5 = mux(_res_hit_T_65, _res_hit_T_66, _res_hit_T_77) node _res_ignore_T_5 = eq(io.pmp[2].cfg.l, UInt<1>(0h0)) node res_ignore_5 = and(default, _res_ignore_T_5) node _res_aligned_lsbMask_T_10 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_11 = bits(_res_aligned_lsbMask_T_10, 2, 0) node res_aligned_lsbMask_5 = not(_res_aligned_lsbMask_T_11) node _res_aligned_straddlesLowerBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_86 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_87 = not(_res_aligned_straddlesLowerBound_T_86) node _res_aligned_straddlesLowerBound_T_88 = or(_res_aligned_straddlesLowerBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_89 = not(_res_aligned_straddlesLowerBound_T_88) node _res_aligned_straddlesLowerBound_T_90 = shr(_res_aligned_straddlesLowerBound_T_89, 3) node _res_aligned_straddlesLowerBound_T_91 = xor(_res_aligned_straddlesLowerBound_T_85, _res_aligned_straddlesLowerBound_T_90) node _res_aligned_straddlesLowerBound_T_92 = eq(_res_aligned_straddlesLowerBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_93 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesLowerBound_T_94 = not(_res_aligned_straddlesLowerBound_T_93) node _res_aligned_straddlesLowerBound_T_95 = or(_res_aligned_straddlesLowerBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_96 = not(_res_aligned_straddlesLowerBound_T_95) node _res_aligned_straddlesLowerBound_T_97 = bits(_res_aligned_straddlesLowerBound_T_96, 2, 0) node _res_aligned_straddlesLowerBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_99 = not(_res_aligned_straddlesLowerBound_T_98) node _res_aligned_straddlesLowerBound_T_100 = and(_res_aligned_straddlesLowerBound_T_97, _res_aligned_straddlesLowerBound_T_99) node _res_aligned_straddlesLowerBound_T_101 = neq(_res_aligned_straddlesLowerBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_5 = and(_res_aligned_straddlesLowerBound_T_92, _res_aligned_straddlesLowerBound_T_101) node _res_aligned_straddlesUpperBound_T_85 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_86 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_87 = not(_res_aligned_straddlesUpperBound_T_86) node _res_aligned_straddlesUpperBound_T_88 = or(_res_aligned_straddlesUpperBound_T_87, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_89 = not(_res_aligned_straddlesUpperBound_T_88) node _res_aligned_straddlesUpperBound_T_90 = shr(_res_aligned_straddlesUpperBound_T_89, 3) node _res_aligned_straddlesUpperBound_T_91 = xor(_res_aligned_straddlesUpperBound_T_85, _res_aligned_straddlesUpperBound_T_90) node _res_aligned_straddlesUpperBound_T_92 = eq(_res_aligned_straddlesUpperBound_T_91, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_93 = shl(io.pmp[2].addr, 2) node _res_aligned_straddlesUpperBound_T_94 = not(_res_aligned_straddlesUpperBound_T_93) node _res_aligned_straddlesUpperBound_T_95 = or(_res_aligned_straddlesUpperBound_T_94, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_96 = not(_res_aligned_straddlesUpperBound_T_95) node _res_aligned_straddlesUpperBound_T_97 = bits(_res_aligned_straddlesUpperBound_T_96, 2, 0) node _res_aligned_straddlesUpperBound_T_98 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_99 = or(_res_aligned_straddlesUpperBound_T_98, res_aligned_lsbMask_5) node _res_aligned_straddlesUpperBound_T_100 = and(_res_aligned_straddlesUpperBound_T_97, _res_aligned_straddlesUpperBound_T_99) node _res_aligned_straddlesUpperBound_T_101 = neq(_res_aligned_straddlesUpperBound_T_100, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_5 = and(_res_aligned_straddlesUpperBound_T_92, _res_aligned_straddlesUpperBound_T_101) node _res_aligned_rangeAligned_T_5 = or(res_aligned_straddlesLowerBound_5, res_aligned_straddlesUpperBound_5) node res_aligned_rangeAligned_5 = eq(_res_aligned_rangeAligned_T_5, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_15 = bits(io.pmp[2].mask, 2, 0) node _res_aligned_pow2Aligned_T_16 = not(_res_aligned_pow2Aligned_T_15) node _res_aligned_pow2Aligned_T_17 = and(res_aligned_lsbMask_5, _res_aligned_pow2Aligned_T_16) node res_aligned_pow2Aligned_5 = eq(_res_aligned_pow2Aligned_T_17, UInt<1>(0h0)) node _res_aligned_T_5 = bits(io.pmp[2].cfg.a, 1, 1) node res_aligned_5 = mux(_res_aligned_T_5, res_aligned_pow2Aligned_5, res_aligned_rangeAligned_5) node _res_T_225 = eq(io.pmp[2].cfg.a, UInt<1>(0h0)) node _res_T_226 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_227 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_228 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_229 = eq(io.pmp[2].cfg.l, UInt<1>(0h1)) node res_hi_30 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_230 = cat(res_hi_30, io.pmp[2].cfg.r) node _res_T_231 = eq(_res_T_230, UInt<1>(0h0)) node res_hi_31 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_232 = cat(res_hi_31, io.pmp[2].cfg.r) node _res_T_233 = eq(_res_T_232, UInt<1>(0h1)) node res_hi_32 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_234 = cat(res_hi_32, io.pmp[2].cfg.r) node _res_T_235 = eq(_res_T_234, UInt<2>(0h3)) node res_hi_33 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_236 = cat(res_hi_33, io.pmp[2].cfg.r) node _res_T_237 = eq(_res_T_236, UInt<3>(0h4)) node res_hi_34 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_238 = cat(res_hi_34, io.pmp[2].cfg.r) node _res_T_239 = eq(_res_T_238, UInt<3>(0h5)) node res_hi_35 = cat(io.pmp[2].cfg.x, io.pmp[2].cfg.w) node _res_T_240 = cat(res_hi_35, io.pmp[2].cfg.r) node _res_T_241 = eq(_res_T_240, UInt<3>(0h7)) node _res_T_242 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_243 = and(_res_T_242, res_hit_5) node _res_T_244 = and(_res_T_243, res_aligned_5) node _res_T_245 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_246 = and(_res_T_244, _res_T_245) node _res_T_247 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_248 = and(_res_T_247, res_aligned_5) node _res_T_249 = eq(io.pmp[2].cfg.a, UInt<1>(0h1)) node _res_T_250 = and(_res_T_248, _res_T_249) node _res_T_251 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_252 = and(_res_T_251, res_hit_5) node _res_T_253 = and(_res_T_252, res_aligned_5) node _res_T_254 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_255 = and(_res_T_253, _res_T_254) node _res_T_256 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_257 = and(_res_T_256, res_aligned_5) node _res_T_258 = eq(io.pmp[2].cfg.a, UInt<2>(0h2)) node _res_T_259 = and(_res_T_257, _res_T_258) node _res_T_260 = eq(res_ignore_5, UInt<1>(0h0)) node _res_T_261 = and(_res_T_260, res_hit_5) node _res_T_262 = and(_res_T_261, res_aligned_5) node _res_T_263 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_264 = and(_res_T_262, _res_T_263) node _res_T_265 = and(io.pmp[2].cfg.l, res_hit_5) node _res_T_266 = and(_res_T_265, res_aligned_5) node _res_T_267 = eq(io.pmp[2].cfg.a, UInt<2>(0h3)) node _res_T_268 = and(_res_T_266, _res_T_267) wire res_cur_5 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_5, io.pmp[2] node _res_cur_cfg_r_T_10 = or(io.pmp[2].cfg.r, res_ignore_5) node _res_cur_cfg_r_T_11 = and(res_aligned_5, _res_cur_cfg_r_T_10) connect res_cur_5.cfg.r, _res_cur_cfg_r_T_11 node _res_cur_cfg_w_T_10 = or(io.pmp[2].cfg.w, res_ignore_5) node _res_cur_cfg_w_T_11 = and(res_aligned_5, _res_cur_cfg_w_T_10) connect res_cur_5.cfg.w, _res_cur_cfg_w_T_11 node _res_cur_cfg_x_T_10 = or(io.pmp[2].cfg.x, res_ignore_5) node _res_cur_cfg_x_T_11 = and(res_aligned_5, _res_cur_cfg_x_T_10) connect res_cur_5.cfg.x, _res_cur_cfg_x_T_11 node _res_T_269 = mux(res_hit_5, res_cur_5, _res_T_224) node _res_hit_T_78 = bits(io.pmp[1].cfg.a, 1, 1) node _res_hit_lsbMask_T_18 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_19 = bits(_res_hit_lsbMask_T_18, 2, 0) node _res_hit_lsbMask_T_20 = not(_res_hit_lsbMask_T_19) node res_hit_lsbMask_6 = or(io.pmp[1].mask, _res_hit_lsbMask_T_20) node _res_hit_msbMatch_T_60 = shr(io.addr, 3) node _res_hit_msbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_msbMatch_T_62 = not(_res_hit_msbMatch_T_61) node _res_hit_msbMatch_T_63 = or(_res_hit_msbMatch_T_62, UInt<2>(0h3)) node _res_hit_msbMatch_T_64 = not(_res_hit_msbMatch_T_63) node _res_hit_msbMatch_T_65 = shr(_res_hit_msbMatch_T_64, 3) node _res_hit_msbMatch_T_66 = shr(io.pmp[1].mask, 3) node _res_hit_msbMatch_T_67 = xor(_res_hit_msbMatch_T_60, _res_hit_msbMatch_T_65) node _res_hit_msbMatch_T_68 = not(_res_hit_msbMatch_T_66) node _res_hit_msbMatch_T_69 = and(_res_hit_msbMatch_T_67, _res_hit_msbMatch_T_68) node res_hit_msbMatch_6 = eq(_res_hit_msbMatch_T_69, UInt<1>(0h0)) node _res_hit_lsbMatch_T_60 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_61 = shl(io.pmp[1].addr, 2) node _res_hit_lsbMatch_T_62 = not(_res_hit_lsbMatch_T_61) node _res_hit_lsbMatch_T_63 = or(_res_hit_lsbMatch_T_62, UInt<2>(0h3)) node _res_hit_lsbMatch_T_64 = not(_res_hit_lsbMatch_T_63) node _res_hit_lsbMatch_T_65 = bits(_res_hit_lsbMatch_T_64, 2, 0) node _res_hit_lsbMatch_T_66 = bits(res_hit_lsbMask_6, 2, 0) node _res_hit_lsbMatch_T_67 = xor(_res_hit_lsbMatch_T_60, _res_hit_lsbMatch_T_65) node _res_hit_lsbMatch_T_68 = not(_res_hit_lsbMatch_T_66) node _res_hit_lsbMatch_T_69 = and(_res_hit_lsbMatch_T_67, _res_hit_lsbMatch_T_68) node res_hit_lsbMatch_6 = eq(_res_hit_lsbMatch_T_69, UInt<1>(0h0)) node _res_hit_T_79 = and(res_hit_msbMatch_6, res_hit_lsbMatch_6) node _res_hit_T_80 = bits(io.pmp[1].cfg.a, 0, 0) node _res_hit_T_81 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_82 = bits(_res_hit_T_81, 2, 0) node _res_hit_T_83 = not(_res_hit_T_82) node _res_hit_msbsLess_T_72 = shr(io.addr, 3) node _res_hit_msbsLess_T_73 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_74 = not(_res_hit_msbsLess_T_73) node _res_hit_msbsLess_T_75 = or(_res_hit_msbsLess_T_74, UInt<2>(0h3)) node _res_hit_msbsLess_T_76 = not(_res_hit_msbsLess_T_75) node _res_hit_msbsLess_T_77 = shr(_res_hit_msbsLess_T_76, 3) node res_hit_msbsLess_12 = lt(_res_hit_msbsLess_T_72, _res_hit_msbsLess_T_77) node _res_hit_msbsEqual_T_84 = shr(io.addr, 3) node _res_hit_msbsEqual_T_85 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_86 = not(_res_hit_msbsEqual_T_85) node _res_hit_msbsEqual_T_87 = or(_res_hit_msbsEqual_T_86, UInt<2>(0h3)) node _res_hit_msbsEqual_T_88 = not(_res_hit_msbsEqual_T_87) node _res_hit_msbsEqual_T_89 = shr(_res_hit_msbsEqual_T_88, 3) node _res_hit_msbsEqual_T_90 = xor(_res_hit_msbsEqual_T_84, _res_hit_msbsEqual_T_89) node res_hit_msbsEqual_12 = eq(_res_hit_msbsEqual_T_90, UInt<1>(0h0)) node _res_hit_lsbsLess_T_84 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_85 = or(_res_hit_lsbsLess_T_84, _res_hit_T_83) node _res_hit_lsbsLess_T_86 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_87 = not(_res_hit_lsbsLess_T_86) node _res_hit_lsbsLess_T_88 = or(_res_hit_lsbsLess_T_87, UInt<2>(0h3)) node _res_hit_lsbsLess_T_89 = not(_res_hit_lsbsLess_T_88) node _res_hit_lsbsLess_T_90 = bits(_res_hit_lsbsLess_T_89, 2, 0) node res_hit_lsbsLess_12 = lt(_res_hit_lsbsLess_T_85, _res_hit_lsbsLess_T_90) node _res_hit_T_84 = and(res_hit_msbsEqual_12, res_hit_lsbsLess_12) node _res_hit_T_85 = or(res_hit_msbsLess_12, _res_hit_T_84) node _res_hit_T_86 = eq(_res_hit_T_85, UInt<1>(0h0)) node _res_hit_msbsLess_T_78 = shr(io.addr, 3) node _res_hit_msbsLess_T_79 = shl(io.pmp[1].addr, 2) node _res_hit_msbsLess_T_80 = not(_res_hit_msbsLess_T_79) node _res_hit_msbsLess_T_81 = or(_res_hit_msbsLess_T_80, UInt<2>(0h3)) node _res_hit_msbsLess_T_82 = not(_res_hit_msbsLess_T_81) node _res_hit_msbsLess_T_83 = shr(_res_hit_msbsLess_T_82, 3) node res_hit_msbsLess_13 = lt(_res_hit_msbsLess_T_78, _res_hit_msbsLess_T_83) node _res_hit_msbsEqual_T_91 = shr(io.addr, 3) node _res_hit_msbsEqual_T_92 = shl(io.pmp[1].addr, 2) node _res_hit_msbsEqual_T_93 = not(_res_hit_msbsEqual_T_92) node _res_hit_msbsEqual_T_94 = or(_res_hit_msbsEqual_T_93, UInt<2>(0h3)) node _res_hit_msbsEqual_T_95 = not(_res_hit_msbsEqual_T_94) node _res_hit_msbsEqual_T_96 = shr(_res_hit_msbsEqual_T_95, 3) node _res_hit_msbsEqual_T_97 = xor(_res_hit_msbsEqual_T_91, _res_hit_msbsEqual_T_96) node res_hit_msbsEqual_13 = eq(_res_hit_msbsEqual_T_97, UInt<1>(0h0)) node _res_hit_lsbsLess_T_91 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_92 = or(_res_hit_lsbsLess_T_91, UInt<1>(0h0)) node _res_hit_lsbsLess_T_93 = shl(io.pmp[1].addr, 2) node _res_hit_lsbsLess_T_94 = not(_res_hit_lsbsLess_T_93) node _res_hit_lsbsLess_T_95 = or(_res_hit_lsbsLess_T_94, UInt<2>(0h3)) node _res_hit_lsbsLess_T_96 = not(_res_hit_lsbsLess_T_95) node _res_hit_lsbsLess_T_97 = bits(_res_hit_lsbsLess_T_96, 2, 0) node res_hit_lsbsLess_13 = lt(_res_hit_lsbsLess_T_92, _res_hit_lsbsLess_T_97) node _res_hit_T_87 = and(res_hit_msbsEqual_13, res_hit_lsbsLess_13) node _res_hit_T_88 = or(res_hit_msbsLess_13, _res_hit_T_87) node _res_hit_T_89 = and(_res_hit_T_86, _res_hit_T_88) node _res_hit_T_90 = and(_res_hit_T_80, _res_hit_T_89) node res_hit_6 = mux(_res_hit_T_78, _res_hit_T_79, _res_hit_T_90) node _res_ignore_T_6 = eq(io.pmp[1].cfg.l, UInt<1>(0h0)) node res_ignore_6 = and(default, _res_ignore_T_6) node _res_aligned_lsbMask_T_12 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_13 = bits(_res_aligned_lsbMask_T_12, 2, 0) node res_aligned_lsbMask_6 = not(_res_aligned_lsbMask_T_13) node _res_aligned_straddlesLowerBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_103 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_104 = not(_res_aligned_straddlesLowerBound_T_103) node _res_aligned_straddlesLowerBound_T_105 = or(_res_aligned_straddlesLowerBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_106 = not(_res_aligned_straddlesLowerBound_T_105) node _res_aligned_straddlesLowerBound_T_107 = shr(_res_aligned_straddlesLowerBound_T_106, 3) node _res_aligned_straddlesLowerBound_T_108 = xor(_res_aligned_straddlesLowerBound_T_102, _res_aligned_straddlesLowerBound_T_107) node _res_aligned_straddlesLowerBound_T_109 = eq(_res_aligned_straddlesLowerBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_110 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesLowerBound_T_111 = not(_res_aligned_straddlesLowerBound_T_110) node _res_aligned_straddlesLowerBound_T_112 = or(_res_aligned_straddlesLowerBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_113 = not(_res_aligned_straddlesLowerBound_T_112) node _res_aligned_straddlesLowerBound_T_114 = bits(_res_aligned_straddlesLowerBound_T_113, 2, 0) node _res_aligned_straddlesLowerBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_116 = not(_res_aligned_straddlesLowerBound_T_115) node _res_aligned_straddlesLowerBound_T_117 = and(_res_aligned_straddlesLowerBound_T_114, _res_aligned_straddlesLowerBound_T_116) node _res_aligned_straddlesLowerBound_T_118 = neq(_res_aligned_straddlesLowerBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_6 = and(_res_aligned_straddlesLowerBound_T_109, _res_aligned_straddlesLowerBound_T_118) node _res_aligned_straddlesUpperBound_T_102 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_103 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_104 = not(_res_aligned_straddlesUpperBound_T_103) node _res_aligned_straddlesUpperBound_T_105 = or(_res_aligned_straddlesUpperBound_T_104, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_106 = not(_res_aligned_straddlesUpperBound_T_105) node _res_aligned_straddlesUpperBound_T_107 = shr(_res_aligned_straddlesUpperBound_T_106, 3) node _res_aligned_straddlesUpperBound_T_108 = xor(_res_aligned_straddlesUpperBound_T_102, _res_aligned_straddlesUpperBound_T_107) node _res_aligned_straddlesUpperBound_T_109 = eq(_res_aligned_straddlesUpperBound_T_108, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_110 = shl(io.pmp[1].addr, 2) node _res_aligned_straddlesUpperBound_T_111 = not(_res_aligned_straddlesUpperBound_T_110) node _res_aligned_straddlesUpperBound_T_112 = or(_res_aligned_straddlesUpperBound_T_111, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_113 = not(_res_aligned_straddlesUpperBound_T_112) node _res_aligned_straddlesUpperBound_T_114 = bits(_res_aligned_straddlesUpperBound_T_113, 2, 0) node _res_aligned_straddlesUpperBound_T_115 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_116 = or(_res_aligned_straddlesUpperBound_T_115, res_aligned_lsbMask_6) node _res_aligned_straddlesUpperBound_T_117 = and(_res_aligned_straddlesUpperBound_T_114, _res_aligned_straddlesUpperBound_T_116) node _res_aligned_straddlesUpperBound_T_118 = neq(_res_aligned_straddlesUpperBound_T_117, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_6 = and(_res_aligned_straddlesUpperBound_T_109, _res_aligned_straddlesUpperBound_T_118) node _res_aligned_rangeAligned_T_6 = or(res_aligned_straddlesLowerBound_6, res_aligned_straddlesUpperBound_6) node res_aligned_rangeAligned_6 = eq(_res_aligned_rangeAligned_T_6, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_18 = bits(io.pmp[1].mask, 2, 0) node _res_aligned_pow2Aligned_T_19 = not(_res_aligned_pow2Aligned_T_18) node _res_aligned_pow2Aligned_T_20 = and(res_aligned_lsbMask_6, _res_aligned_pow2Aligned_T_19) node res_aligned_pow2Aligned_6 = eq(_res_aligned_pow2Aligned_T_20, UInt<1>(0h0)) node _res_aligned_T_6 = bits(io.pmp[1].cfg.a, 1, 1) node res_aligned_6 = mux(_res_aligned_T_6, res_aligned_pow2Aligned_6, res_aligned_rangeAligned_6) node _res_T_270 = eq(io.pmp[1].cfg.a, UInt<1>(0h0)) node _res_T_271 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_272 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_273 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_274 = eq(io.pmp[1].cfg.l, UInt<1>(0h1)) node res_hi_36 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_275 = cat(res_hi_36, io.pmp[1].cfg.r) node _res_T_276 = eq(_res_T_275, UInt<1>(0h0)) node res_hi_37 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_277 = cat(res_hi_37, io.pmp[1].cfg.r) node _res_T_278 = eq(_res_T_277, UInt<1>(0h1)) node res_hi_38 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_279 = cat(res_hi_38, io.pmp[1].cfg.r) node _res_T_280 = eq(_res_T_279, UInt<2>(0h3)) node res_hi_39 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_281 = cat(res_hi_39, io.pmp[1].cfg.r) node _res_T_282 = eq(_res_T_281, UInt<3>(0h4)) node res_hi_40 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_283 = cat(res_hi_40, io.pmp[1].cfg.r) node _res_T_284 = eq(_res_T_283, UInt<3>(0h5)) node res_hi_41 = cat(io.pmp[1].cfg.x, io.pmp[1].cfg.w) node _res_T_285 = cat(res_hi_41, io.pmp[1].cfg.r) node _res_T_286 = eq(_res_T_285, UInt<3>(0h7)) node _res_T_287 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_288 = and(_res_T_287, res_hit_6) node _res_T_289 = and(_res_T_288, res_aligned_6) node _res_T_290 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_291 = and(_res_T_289, _res_T_290) node _res_T_292 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_293 = and(_res_T_292, res_aligned_6) node _res_T_294 = eq(io.pmp[1].cfg.a, UInt<1>(0h1)) node _res_T_295 = and(_res_T_293, _res_T_294) node _res_T_296 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_297 = and(_res_T_296, res_hit_6) node _res_T_298 = and(_res_T_297, res_aligned_6) node _res_T_299 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_300 = and(_res_T_298, _res_T_299) node _res_T_301 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_302 = and(_res_T_301, res_aligned_6) node _res_T_303 = eq(io.pmp[1].cfg.a, UInt<2>(0h2)) node _res_T_304 = and(_res_T_302, _res_T_303) node _res_T_305 = eq(res_ignore_6, UInt<1>(0h0)) node _res_T_306 = and(_res_T_305, res_hit_6) node _res_T_307 = and(_res_T_306, res_aligned_6) node _res_T_308 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_309 = and(_res_T_307, _res_T_308) node _res_T_310 = and(io.pmp[1].cfg.l, res_hit_6) node _res_T_311 = and(_res_T_310, res_aligned_6) node _res_T_312 = eq(io.pmp[1].cfg.a, UInt<2>(0h3)) node _res_T_313 = and(_res_T_311, _res_T_312) wire res_cur_6 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_6, io.pmp[1] node _res_cur_cfg_r_T_12 = or(io.pmp[1].cfg.r, res_ignore_6) node _res_cur_cfg_r_T_13 = and(res_aligned_6, _res_cur_cfg_r_T_12) connect res_cur_6.cfg.r, _res_cur_cfg_r_T_13 node _res_cur_cfg_w_T_12 = or(io.pmp[1].cfg.w, res_ignore_6) node _res_cur_cfg_w_T_13 = and(res_aligned_6, _res_cur_cfg_w_T_12) connect res_cur_6.cfg.w, _res_cur_cfg_w_T_13 node _res_cur_cfg_x_T_12 = or(io.pmp[1].cfg.x, res_ignore_6) node _res_cur_cfg_x_T_13 = and(res_aligned_6, _res_cur_cfg_x_T_12) connect res_cur_6.cfg.x, _res_cur_cfg_x_T_13 node _res_T_314 = mux(res_hit_6, res_cur_6, _res_T_269) node _res_hit_T_91 = bits(io.pmp[0].cfg.a, 1, 1) node _res_hit_lsbMask_T_21 = dshl(UInt<3>(0h7), io.size) node _res_hit_lsbMask_T_22 = bits(_res_hit_lsbMask_T_21, 2, 0) node _res_hit_lsbMask_T_23 = not(_res_hit_lsbMask_T_22) node res_hit_lsbMask_7 = or(io.pmp[0].mask, _res_hit_lsbMask_T_23) node _res_hit_msbMatch_T_70 = shr(io.addr, 3) node _res_hit_msbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_msbMatch_T_72 = not(_res_hit_msbMatch_T_71) node _res_hit_msbMatch_T_73 = or(_res_hit_msbMatch_T_72, UInt<2>(0h3)) node _res_hit_msbMatch_T_74 = not(_res_hit_msbMatch_T_73) node _res_hit_msbMatch_T_75 = shr(_res_hit_msbMatch_T_74, 3) node _res_hit_msbMatch_T_76 = shr(io.pmp[0].mask, 3) node _res_hit_msbMatch_T_77 = xor(_res_hit_msbMatch_T_70, _res_hit_msbMatch_T_75) node _res_hit_msbMatch_T_78 = not(_res_hit_msbMatch_T_76) node _res_hit_msbMatch_T_79 = and(_res_hit_msbMatch_T_77, _res_hit_msbMatch_T_78) node res_hit_msbMatch_7 = eq(_res_hit_msbMatch_T_79, UInt<1>(0h0)) node _res_hit_lsbMatch_T_70 = bits(io.addr, 2, 0) node _res_hit_lsbMatch_T_71 = shl(io.pmp[0].addr, 2) node _res_hit_lsbMatch_T_72 = not(_res_hit_lsbMatch_T_71) node _res_hit_lsbMatch_T_73 = or(_res_hit_lsbMatch_T_72, UInt<2>(0h3)) node _res_hit_lsbMatch_T_74 = not(_res_hit_lsbMatch_T_73) node _res_hit_lsbMatch_T_75 = bits(_res_hit_lsbMatch_T_74, 2, 0) node _res_hit_lsbMatch_T_76 = bits(res_hit_lsbMask_7, 2, 0) node _res_hit_lsbMatch_T_77 = xor(_res_hit_lsbMatch_T_70, _res_hit_lsbMatch_T_75) node _res_hit_lsbMatch_T_78 = not(_res_hit_lsbMatch_T_76) node _res_hit_lsbMatch_T_79 = and(_res_hit_lsbMatch_T_77, _res_hit_lsbMatch_T_78) node res_hit_lsbMatch_7 = eq(_res_hit_lsbMatch_T_79, UInt<1>(0h0)) node _res_hit_T_92 = and(res_hit_msbMatch_7, res_hit_lsbMatch_7) node _res_hit_T_93 = bits(io.pmp[0].cfg.a, 0, 0) node _res_hit_T_94 = dshl(UInt<3>(0h7), io.size) node _res_hit_T_95 = bits(_res_hit_T_94, 2, 0) node _res_hit_T_96 = not(_res_hit_T_95) node _res_hit_msbsLess_T_84 = shr(io.addr, 3) node _res_hit_msbsLess_T_85 = shl(pmp0.addr, 2) node _res_hit_msbsLess_T_86 = not(_res_hit_msbsLess_T_85) node _res_hit_msbsLess_T_87 = or(_res_hit_msbsLess_T_86, UInt<2>(0h3)) node _res_hit_msbsLess_T_88 = not(_res_hit_msbsLess_T_87) node _res_hit_msbsLess_T_89 = shr(_res_hit_msbsLess_T_88, 3) node res_hit_msbsLess_14 = lt(_res_hit_msbsLess_T_84, _res_hit_msbsLess_T_89) node _res_hit_msbsEqual_T_98 = shr(io.addr, 3) node _res_hit_msbsEqual_T_99 = shl(pmp0.addr, 2) node _res_hit_msbsEqual_T_100 = not(_res_hit_msbsEqual_T_99) node _res_hit_msbsEqual_T_101 = or(_res_hit_msbsEqual_T_100, UInt<2>(0h3)) node _res_hit_msbsEqual_T_102 = not(_res_hit_msbsEqual_T_101) node _res_hit_msbsEqual_T_103 = shr(_res_hit_msbsEqual_T_102, 3) node _res_hit_msbsEqual_T_104 = xor(_res_hit_msbsEqual_T_98, _res_hit_msbsEqual_T_103) node res_hit_msbsEqual_14 = eq(_res_hit_msbsEqual_T_104, UInt<1>(0h0)) node _res_hit_lsbsLess_T_98 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_99 = or(_res_hit_lsbsLess_T_98, _res_hit_T_96) node _res_hit_lsbsLess_T_100 = shl(pmp0.addr, 2) node _res_hit_lsbsLess_T_101 = not(_res_hit_lsbsLess_T_100) node _res_hit_lsbsLess_T_102 = or(_res_hit_lsbsLess_T_101, UInt<2>(0h3)) node _res_hit_lsbsLess_T_103 = not(_res_hit_lsbsLess_T_102) node _res_hit_lsbsLess_T_104 = bits(_res_hit_lsbsLess_T_103, 2, 0) node res_hit_lsbsLess_14 = lt(_res_hit_lsbsLess_T_99, _res_hit_lsbsLess_T_104) node _res_hit_T_97 = and(res_hit_msbsEqual_14, res_hit_lsbsLess_14) node _res_hit_T_98 = or(res_hit_msbsLess_14, _res_hit_T_97) node _res_hit_T_99 = eq(_res_hit_T_98, UInt<1>(0h0)) node _res_hit_msbsLess_T_90 = shr(io.addr, 3) node _res_hit_msbsLess_T_91 = shl(io.pmp[0].addr, 2) node _res_hit_msbsLess_T_92 = not(_res_hit_msbsLess_T_91) node _res_hit_msbsLess_T_93 = or(_res_hit_msbsLess_T_92, UInt<2>(0h3)) node _res_hit_msbsLess_T_94 = not(_res_hit_msbsLess_T_93) node _res_hit_msbsLess_T_95 = shr(_res_hit_msbsLess_T_94, 3) node res_hit_msbsLess_15 = lt(_res_hit_msbsLess_T_90, _res_hit_msbsLess_T_95) node _res_hit_msbsEqual_T_105 = shr(io.addr, 3) node _res_hit_msbsEqual_T_106 = shl(io.pmp[0].addr, 2) node _res_hit_msbsEqual_T_107 = not(_res_hit_msbsEqual_T_106) node _res_hit_msbsEqual_T_108 = or(_res_hit_msbsEqual_T_107, UInt<2>(0h3)) node _res_hit_msbsEqual_T_109 = not(_res_hit_msbsEqual_T_108) node _res_hit_msbsEqual_T_110 = shr(_res_hit_msbsEqual_T_109, 3) node _res_hit_msbsEqual_T_111 = xor(_res_hit_msbsEqual_T_105, _res_hit_msbsEqual_T_110) node res_hit_msbsEqual_15 = eq(_res_hit_msbsEqual_T_111, UInt<1>(0h0)) node _res_hit_lsbsLess_T_105 = bits(io.addr, 2, 0) node _res_hit_lsbsLess_T_106 = or(_res_hit_lsbsLess_T_105, UInt<1>(0h0)) node _res_hit_lsbsLess_T_107 = shl(io.pmp[0].addr, 2) node _res_hit_lsbsLess_T_108 = not(_res_hit_lsbsLess_T_107) node _res_hit_lsbsLess_T_109 = or(_res_hit_lsbsLess_T_108, UInt<2>(0h3)) node _res_hit_lsbsLess_T_110 = not(_res_hit_lsbsLess_T_109) node _res_hit_lsbsLess_T_111 = bits(_res_hit_lsbsLess_T_110, 2, 0) node res_hit_lsbsLess_15 = lt(_res_hit_lsbsLess_T_106, _res_hit_lsbsLess_T_111) node _res_hit_T_100 = and(res_hit_msbsEqual_15, res_hit_lsbsLess_15) node _res_hit_T_101 = or(res_hit_msbsLess_15, _res_hit_T_100) node _res_hit_T_102 = and(_res_hit_T_99, _res_hit_T_101) node _res_hit_T_103 = and(_res_hit_T_93, _res_hit_T_102) node res_hit_7 = mux(_res_hit_T_91, _res_hit_T_92, _res_hit_T_103) node _res_ignore_T_7 = eq(io.pmp[0].cfg.l, UInt<1>(0h0)) node res_ignore_7 = and(default, _res_ignore_T_7) node _res_aligned_lsbMask_T_14 = dshl(UInt<3>(0h7), io.size) node _res_aligned_lsbMask_T_15 = bits(_res_aligned_lsbMask_T_14, 2, 0) node res_aligned_lsbMask_7 = not(_res_aligned_lsbMask_T_15) node _res_aligned_straddlesLowerBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesLowerBound_T_120 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_121 = not(_res_aligned_straddlesLowerBound_T_120) node _res_aligned_straddlesLowerBound_T_122 = or(_res_aligned_straddlesLowerBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_123 = not(_res_aligned_straddlesLowerBound_T_122) node _res_aligned_straddlesLowerBound_T_124 = shr(_res_aligned_straddlesLowerBound_T_123, 3) node _res_aligned_straddlesLowerBound_T_125 = xor(_res_aligned_straddlesLowerBound_T_119, _res_aligned_straddlesLowerBound_T_124) node _res_aligned_straddlesLowerBound_T_126 = eq(_res_aligned_straddlesLowerBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesLowerBound_T_127 = shl(pmp0.addr, 2) node _res_aligned_straddlesLowerBound_T_128 = not(_res_aligned_straddlesLowerBound_T_127) node _res_aligned_straddlesLowerBound_T_129 = or(_res_aligned_straddlesLowerBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesLowerBound_T_130 = not(_res_aligned_straddlesLowerBound_T_129) node _res_aligned_straddlesLowerBound_T_131 = bits(_res_aligned_straddlesLowerBound_T_130, 2, 0) node _res_aligned_straddlesLowerBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesLowerBound_T_133 = not(_res_aligned_straddlesLowerBound_T_132) node _res_aligned_straddlesLowerBound_T_134 = and(_res_aligned_straddlesLowerBound_T_131, _res_aligned_straddlesLowerBound_T_133) node _res_aligned_straddlesLowerBound_T_135 = neq(_res_aligned_straddlesLowerBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesLowerBound_7 = and(_res_aligned_straddlesLowerBound_T_126, _res_aligned_straddlesLowerBound_T_135) node _res_aligned_straddlesUpperBound_T_119 = shr(io.addr, 3) node _res_aligned_straddlesUpperBound_T_120 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_121 = not(_res_aligned_straddlesUpperBound_T_120) node _res_aligned_straddlesUpperBound_T_122 = or(_res_aligned_straddlesUpperBound_T_121, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_123 = not(_res_aligned_straddlesUpperBound_T_122) node _res_aligned_straddlesUpperBound_T_124 = shr(_res_aligned_straddlesUpperBound_T_123, 3) node _res_aligned_straddlesUpperBound_T_125 = xor(_res_aligned_straddlesUpperBound_T_119, _res_aligned_straddlesUpperBound_T_124) node _res_aligned_straddlesUpperBound_T_126 = eq(_res_aligned_straddlesUpperBound_T_125, UInt<1>(0h0)) node _res_aligned_straddlesUpperBound_T_127 = shl(io.pmp[0].addr, 2) node _res_aligned_straddlesUpperBound_T_128 = not(_res_aligned_straddlesUpperBound_T_127) node _res_aligned_straddlesUpperBound_T_129 = or(_res_aligned_straddlesUpperBound_T_128, UInt<2>(0h3)) node _res_aligned_straddlesUpperBound_T_130 = not(_res_aligned_straddlesUpperBound_T_129) node _res_aligned_straddlesUpperBound_T_131 = bits(_res_aligned_straddlesUpperBound_T_130, 2, 0) node _res_aligned_straddlesUpperBound_T_132 = bits(io.addr, 2, 0) node _res_aligned_straddlesUpperBound_T_133 = or(_res_aligned_straddlesUpperBound_T_132, res_aligned_lsbMask_7) node _res_aligned_straddlesUpperBound_T_134 = and(_res_aligned_straddlesUpperBound_T_131, _res_aligned_straddlesUpperBound_T_133) node _res_aligned_straddlesUpperBound_T_135 = neq(_res_aligned_straddlesUpperBound_T_134, UInt<1>(0h0)) node res_aligned_straddlesUpperBound_7 = and(_res_aligned_straddlesUpperBound_T_126, _res_aligned_straddlesUpperBound_T_135) node _res_aligned_rangeAligned_T_7 = or(res_aligned_straddlesLowerBound_7, res_aligned_straddlesUpperBound_7) node res_aligned_rangeAligned_7 = eq(_res_aligned_rangeAligned_T_7, UInt<1>(0h0)) node _res_aligned_pow2Aligned_T_21 = bits(io.pmp[0].mask, 2, 0) node _res_aligned_pow2Aligned_T_22 = not(_res_aligned_pow2Aligned_T_21) node _res_aligned_pow2Aligned_T_23 = and(res_aligned_lsbMask_7, _res_aligned_pow2Aligned_T_22) node res_aligned_pow2Aligned_7 = eq(_res_aligned_pow2Aligned_T_23, UInt<1>(0h0)) node _res_aligned_T_7 = bits(io.pmp[0].cfg.a, 1, 1) node res_aligned_7 = mux(_res_aligned_T_7, res_aligned_pow2Aligned_7, res_aligned_rangeAligned_7) node _res_T_315 = eq(io.pmp[0].cfg.a, UInt<1>(0h0)) node _res_T_316 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_317 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_318 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_319 = eq(io.pmp[0].cfg.l, UInt<1>(0h1)) node res_hi_42 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_320 = cat(res_hi_42, io.pmp[0].cfg.r) node _res_T_321 = eq(_res_T_320, UInt<1>(0h0)) node res_hi_43 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_322 = cat(res_hi_43, io.pmp[0].cfg.r) node _res_T_323 = eq(_res_T_322, UInt<1>(0h1)) node res_hi_44 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_324 = cat(res_hi_44, io.pmp[0].cfg.r) node _res_T_325 = eq(_res_T_324, UInt<2>(0h3)) node res_hi_45 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_326 = cat(res_hi_45, io.pmp[0].cfg.r) node _res_T_327 = eq(_res_T_326, UInt<3>(0h4)) node res_hi_46 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_328 = cat(res_hi_46, io.pmp[0].cfg.r) node _res_T_329 = eq(_res_T_328, UInt<3>(0h5)) node res_hi_47 = cat(io.pmp[0].cfg.x, io.pmp[0].cfg.w) node _res_T_330 = cat(res_hi_47, io.pmp[0].cfg.r) node _res_T_331 = eq(_res_T_330, UInt<3>(0h7)) node _res_T_332 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_333 = and(_res_T_332, res_hit_7) node _res_T_334 = and(_res_T_333, res_aligned_7) node _res_T_335 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_336 = and(_res_T_334, _res_T_335) node _res_T_337 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_338 = and(_res_T_337, res_aligned_7) node _res_T_339 = eq(io.pmp[0].cfg.a, UInt<1>(0h1)) node _res_T_340 = and(_res_T_338, _res_T_339) node _res_T_341 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_342 = and(_res_T_341, res_hit_7) node _res_T_343 = and(_res_T_342, res_aligned_7) node _res_T_344 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_345 = and(_res_T_343, _res_T_344) node _res_T_346 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_347 = and(_res_T_346, res_aligned_7) node _res_T_348 = eq(io.pmp[0].cfg.a, UInt<2>(0h2)) node _res_T_349 = and(_res_T_347, _res_T_348) node _res_T_350 = eq(res_ignore_7, UInt<1>(0h0)) node _res_T_351 = and(_res_T_350, res_hit_7) node _res_T_352 = and(_res_T_351, res_aligned_7) node _res_T_353 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_354 = and(_res_T_352, _res_T_353) node _res_T_355 = and(io.pmp[0].cfg.l, res_hit_7) node _res_T_356 = and(_res_T_355, res_aligned_7) node _res_T_357 = eq(io.pmp[0].cfg.a, UInt<2>(0h3)) node _res_T_358 = and(_res_T_356, _res_T_357) wire res_cur_7 : { cfg : { l : UInt<1>, res : UInt<2>, a : UInt<2>, x : UInt<1>, w : UInt<1>, r : UInt<1>}, addr : UInt<30>, mask : UInt<32>} connect res_cur_7, io.pmp[0] node _res_cur_cfg_r_T_14 = or(io.pmp[0].cfg.r, res_ignore_7) node _res_cur_cfg_r_T_15 = and(res_aligned_7, _res_cur_cfg_r_T_14) connect res_cur_7.cfg.r, _res_cur_cfg_r_T_15 node _res_cur_cfg_w_T_14 = or(io.pmp[0].cfg.w, res_ignore_7) node _res_cur_cfg_w_T_15 = and(res_aligned_7, _res_cur_cfg_w_T_14) connect res_cur_7.cfg.w, _res_cur_cfg_w_T_15 node _res_cur_cfg_x_T_14 = or(io.pmp[0].cfg.x, res_ignore_7) node _res_cur_cfg_x_T_15 = and(res_aligned_7, _res_cur_cfg_x_T_14) connect res_cur_7.cfg.x, _res_cur_cfg_x_T_15 node res = mux(res_hit_7, res_cur_7, _res_T_314) connect io.r, res.cfg.r connect io.w, res.cfg.w connect io.x, res.cfg.x
module PMPChecker_s3_1( // @[PMP.scala:143:7] input clock, // @[PMP.scala:143:7] input reset, // @[PMP.scala:143:7] input [31:0] io_addr, // @[PMP.scala:146:14] input [1:0] io_size // @[PMP.scala:146:14] ); wire [31:0] io_addr_0 = io_addr; // @[PMP.scala:143:7] wire [1:0] io_size_0 = io_size; // @[PMP.scala:143:7] wire [28:0] _res_hit_msbMatch_T_8 = 29'h1FFFFFFF; // @[PMP.scala:63:54] wire [28:0] _res_hit_msbMatch_T_18 = 29'h1FFFFFFF; // @[PMP.scala:63:54] wire [28:0] _res_hit_msbMatch_T_28 = 29'h1FFFFFFF; // @[PMP.scala:63:54] wire [28:0] _res_hit_msbMatch_T_38 = 29'h1FFFFFFF; // @[PMP.scala:63:54] wire [28:0] _res_hit_msbMatch_T_48 = 29'h1FFFFFFF; // @[PMP.scala:63:54] wire [28:0] _res_hit_msbMatch_T_58 = 29'h1FFFFFFF; // @[PMP.scala:63:54] wire [28:0] _res_hit_msbMatch_T_68 = 29'h1FFFFFFF; // @[PMP.scala:63:54] wire [28:0] _res_hit_msbMatch_T_78 = 29'h1FFFFFFF; // @[PMP.scala:63:54] wire [28:0] _res_hit_msbMatch_T_5 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_6 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_5 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_5 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_11 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_12 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesLowerBound_T_5 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_5 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_15 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_16 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_17 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_19 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_23 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_26 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesLowerBound_T_22 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_22 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_25 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_26 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_29 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_33 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_35 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_40 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesLowerBound_T_39 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_39 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_35 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_36 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_41 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_47 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_47 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_54 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesLowerBound_T_56 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_56 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_45 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_46 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_53 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_61 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_59 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_68 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesLowerBound_T_73 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_73 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_55 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_56 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_65 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_75 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_71 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_82 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesLowerBound_T_90 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_90 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_65 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_66 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_77 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_89 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_83 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_96 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesLowerBound_T_107 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_107 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_75 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbMatch_T_76 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_89 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_103 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsLess_T_95 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_hit_msbsEqual_T_110 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesLowerBound_T_124 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [28:0] _res_aligned_straddlesUpperBound_T_124 = 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [31:0] _res_hit_msbMatch_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_4 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_8 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_9 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_9 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_10 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_10 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_11 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_9 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_10 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_2 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_3 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_9 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_10 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_12 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_13 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_12 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_13 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_14 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_15 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_16 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_17 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_17 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_18 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_20 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_21 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_23 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_24 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_24 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_25 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_19 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_20 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_26 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_27 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_19 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_20 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_26 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_27 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_22 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_23 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_22 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_23 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_26 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_27 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_30 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_31 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_31 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_32 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_32 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_33 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_37 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_38 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_38 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_39 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_36 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_37 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_43 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_44 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_36 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_37 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_43 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_44 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_32 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_33 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_32 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_33 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_38 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_39 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_44 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_45 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_45 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_46 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_44 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_45 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_51 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_52 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_52 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_53 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_53 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_54 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_60 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_61 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_53 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_54 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_60 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_61 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_42 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_43 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_42 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_43 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_50 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_51 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_58 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_59 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_59 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_60 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_56 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_57 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_65 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_66 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_66 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_67 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_70 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_71 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_77 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_78 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_70 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_71 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_77 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_78 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_52 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_53 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_52 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_53 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_62 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_63 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_72 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_73 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_73 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_74 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_68 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_69 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_79 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_80 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_80 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_81 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_88 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_94 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_95 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_88 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_94 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_95 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_62 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_63 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_62 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_63 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_74 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_75 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_88 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_80 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_81 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_93 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_94 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_94 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_95 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_104 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_105 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_111 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_112 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_104 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_105 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_111 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_112 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_72 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbMatch_T_73 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_72 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbMatch_T_73 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_86 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_87 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_100 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_101 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_102 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_92 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsLess_T_93 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_107 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_msbsEqual_T_108 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_108 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_hit_lsbsLess_T_109 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesLowerBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_121 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_122 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_128 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [31:0] _res_aligned_straddlesUpperBound_T_129 = 32'hFFFFFFFF; // @[PMP.scala:60:{29,48}] wire [2:0] _res_aligned_pow2Aligned_T_1 = 3'h7; // @[PMP.scala:126:34] wire [2:0] _res_aligned_pow2Aligned_T_4 = 3'h7; // @[PMP.scala:126:34] wire [2:0] _res_aligned_pow2Aligned_T_7 = 3'h7; // @[PMP.scala:126:34] wire [2:0] _res_aligned_pow2Aligned_T_10 = 3'h7; // @[PMP.scala:126:34] wire [2:0] _res_aligned_pow2Aligned_T_13 = 3'h7; // @[PMP.scala:126:34] wire [2:0] _res_aligned_pow2Aligned_T_16 = 3'h7; // @[PMP.scala:126:34] wire [2:0] _res_aligned_pow2Aligned_T_19 = 3'h7; // @[PMP.scala:126:34] wire [2:0] _res_aligned_pow2Aligned_T_22 = 3'h7; // @[PMP.scala:126:34] wire [2:0] _res_hit_lsbMatch_T_5 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_6 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_13 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_12 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_15 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_12 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_15 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_pow2Aligned_T = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_5 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_7 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_9 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_11 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_13 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_15 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbMatch_T_15 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_20 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_27 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_29 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_32 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_29 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_32 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_pow2Aligned_T_3 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_50 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_52 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_54 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_56 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_58 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_60 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbMatch_T_25 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_34 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_41 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_46 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_49 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_46 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_49 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_pow2Aligned_T_6 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_95 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_97 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_99 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_101 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_103 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_105 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbMatch_T_35 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_48 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_55 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_63 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_66 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_63 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_66 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_pow2Aligned_T_9 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_140 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_142 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_144 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_146 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_148 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_150 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbMatch_T_45 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_62 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_69 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_80 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_83 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_80 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_83 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_pow2Aligned_T_12 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_185 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_187 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_189 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_191 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_193 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_195 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbMatch_T_55 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_76 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_83 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_97 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_100 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_97 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_100 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_pow2Aligned_T_15 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_230 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_232 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_234 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_236 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_238 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_240 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbMatch_T_65 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_90 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_97 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_114 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_117 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_114 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_117 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_pow2Aligned_T_18 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_275 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_277 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_279 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_281 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_283 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_285 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbMatch_T_75 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_104 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_hit_lsbsLess_T_111 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_131 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesLowerBound_T_134 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_131 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_straddlesUpperBound_T_134 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_aligned_pow2Aligned_T_21 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_320 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_322 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_324 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_326 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_328 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire [2:0] _res_T_330 = 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire _res_hit_T_8 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_ignore_T = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_rangeAligned = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_6 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_17 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_26 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_35 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_hit_T_21 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_ignore_T_1 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_rangeAligned_1 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_1 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_45 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_51 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_62 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_71 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_80 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_hit_T_34 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_ignore_T_2 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_rangeAligned_2 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_2 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_90 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_96 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_107 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_116 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_125 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_hit_T_47 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_ignore_T_3 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_rangeAligned_3 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_3 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_135 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_141 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_152 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_161 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_170 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_hit_T_60 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_ignore_T_4 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_rangeAligned_4 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_4 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_180 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_186 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_197 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_206 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_215 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_hit_T_73 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_ignore_T_5 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_rangeAligned_5 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_5 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_225 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_231 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_242 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_251 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_260 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_hit_T_86 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_ignore_T_6 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_rangeAligned_6 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_6 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_270 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_276 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_287 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_296 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_305 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_hit_T_99 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_ignore_T_7 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_rangeAligned_7 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire res_aligned_7 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_315 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_321 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_332 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_341 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire _res_T_350 = 1'h1; // @[PMP.scala:88:5, :125:24, :127:8, :164:29, :168:32, :174:60, :177:22] wire [31:0] io_pmp_0_mask = 32'h0; // @[PMP.scala:143:7] wire [31:0] io_pmp_1_mask = 32'h0; // @[PMP.scala:143:7] wire [31:0] io_pmp_2_mask = 32'h0; // @[PMP.scala:143:7] wire [31:0] io_pmp_3_mask = 32'h0; // @[PMP.scala:143:7] wire [31:0] io_pmp_4_mask = 32'h0; // @[PMP.scala:143:7] wire [31:0] io_pmp_5_mask = 32'h0; // @[PMP.scala:143:7] wire [31:0] io_pmp_6_mask = 32'h0; // @[PMP.scala:143:7] wire [31:0] io_pmp_7_mask = 32'h0; // @[PMP.scala:143:7] wire [31:0] _pmp0_WIRE_mask = 32'h0; // @[PMP.scala:157:35] wire [31:0] pmp0_mask = 32'h0; // @[PMP.scala:157:22] wire [31:0] _res_hit_msbMatch_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbMatch_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_2 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_5 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_7 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_10 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_8 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_11 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_9 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_12 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_8 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_11 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_1 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_4 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_8 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_11 = 32'h0; // @[PMP.scala:60:27] wire [31:0] res_cur_mask = 32'h0; // @[PMP.scala:181:23] wire [31:0] _res_T_44_mask = 32'h0; // @[PMP.scala:185:8] wire [31:0] _res_hit_msbMatch_T_11 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_14 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbMatch_T_11 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_14 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_13 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_16 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_15 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_18 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_16 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_19 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_19 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_22 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_22 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_25 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_23 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_26 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_18 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_21 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_25 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_28 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_18 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_21 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_25 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_28 = 32'h0; // @[PMP.scala:60:27] wire [31:0] res_cur_1_mask = 32'h0; // @[PMP.scala:181:23] wire [31:0] _res_T_89_mask = 32'h0; // @[PMP.scala:185:8] wire [31:0] _res_hit_msbMatch_T_21 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_24 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbMatch_T_21 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_24 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_25 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_28 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_29 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_32 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_30 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_33 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_31 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_34 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_36 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_39 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_37 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_40 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_35 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_38 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_42 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_45 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_35 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_38 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_42 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_45 = 32'h0; // @[PMP.scala:60:27] wire [31:0] res_cur_2_mask = 32'h0; // @[PMP.scala:181:23] wire [31:0] _res_T_134_mask = 32'h0; // @[PMP.scala:185:8] wire [31:0] _res_hit_msbMatch_T_31 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_34 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbMatch_T_31 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_34 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_37 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_40 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_43 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_46 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_44 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_47 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_43 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_46 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_50 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_53 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_51 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_54 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_52 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_55 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_59 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_62 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_52 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_55 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_59 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_62 = 32'h0; // @[PMP.scala:60:27] wire [31:0] res_cur_3_mask = 32'h0; // @[PMP.scala:181:23] wire [31:0] _res_T_179_mask = 32'h0; // @[PMP.scala:185:8] wire [31:0] _res_hit_msbMatch_T_41 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_44 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbMatch_T_41 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_44 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_49 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_52 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_57 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_60 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_58 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_61 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_55 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_58 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_64 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_67 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_65 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_68 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_69 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_72 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_76 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_79 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_69 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_72 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_76 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_79 = 32'h0; // @[PMP.scala:60:27] wire [31:0] res_cur_4_mask = 32'h0; // @[PMP.scala:181:23] wire [31:0] _res_T_224_mask = 32'h0; // @[PMP.scala:185:8] wire [31:0] _res_hit_msbMatch_T_51 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_54 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbMatch_T_51 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_54 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_61 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_64 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_71 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_74 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_72 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_75 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_67 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_70 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_78 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_81 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_79 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_82 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_86 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_89 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_93 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_96 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_86 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_89 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_93 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_96 = 32'h0; // @[PMP.scala:60:27] wire [31:0] res_cur_5_mask = 32'h0; // @[PMP.scala:181:23] wire [31:0] _res_T_269_mask = 32'h0; // @[PMP.scala:185:8] wire [31:0] _res_hit_msbMatch_T_61 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_64 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbMatch_T_61 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_64 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_73 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_76 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_86 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_89 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_79 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_82 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_92 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_95 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_93 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_96 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_103 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_106 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_110 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_113 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_103 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_106 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_110 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_113 = 32'h0; // @[PMP.scala:60:27] wire [31:0] res_cur_6_mask = 32'h0; // @[PMP.scala:181:23] wire [31:0] _res_T_314_mask = 32'h0; // @[PMP.scala:185:8] wire [31:0] _res_hit_msbMatch_T_71 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbMatch_T_74 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbMatch_T_71 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbMatch_T_74 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_85 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_88 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_99 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_102 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_100 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_103 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsLess_T_91 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsLess_T_94 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_msbsEqual_T_106 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_msbsEqual_T_109 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_hit_lsbsLess_T_107 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_hit_lsbsLess_T_110 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesLowerBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesLowerBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_120 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_123 = 32'h0; // @[PMP.scala:60:27] wire [31:0] _res_aligned_straddlesUpperBound_T_127 = 32'h0; // @[PMP.scala:60:36] wire [31:0] _res_aligned_straddlesUpperBound_T_130 = 32'h0; // @[PMP.scala:60:27] wire [31:0] res_cur_7_mask = 32'h0; // @[PMP.scala:181:23] wire [31:0] res_mask = 32'h0; // @[PMP.scala:185:8] wire [29:0] io_pmp_0_addr = 30'h0; // @[PMP.scala:143:7] wire [29:0] io_pmp_1_addr = 30'h0; // @[PMP.scala:143:7] wire [29:0] io_pmp_2_addr = 30'h0; // @[PMP.scala:143:7] wire [29:0] io_pmp_3_addr = 30'h0; // @[PMP.scala:143:7] wire [29:0] io_pmp_4_addr = 30'h0; // @[PMP.scala:143:7] wire [29:0] io_pmp_5_addr = 30'h0; // @[PMP.scala:143:7] wire [29:0] io_pmp_6_addr = 30'h0; // @[PMP.scala:143:7] wire [29:0] io_pmp_7_addr = 30'h0; // @[PMP.scala:143:7] wire [29:0] _pmp0_WIRE_addr = 30'h0; // @[PMP.scala:157:35] wire [29:0] pmp0_addr = 30'h0; // @[PMP.scala:157:22] wire [29:0] res_cur_addr = 30'h0; // @[PMP.scala:181:23] wire [29:0] _res_T_44_addr = 30'h0; // @[PMP.scala:185:8] wire [29:0] res_cur_1_addr = 30'h0; // @[PMP.scala:181:23] wire [29:0] _res_T_89_addr = 30'h0; // @[PMP.scala:185:8] wire [29:0] res_cur_2_addr = 30'h0; // @[PMP.scala:181:23] wire [29:0] _res_T_134_addr = 30'h0; // @[PMP.scala:185:8] wire [29:0] res_cur_3_addr = 30'h0; // @[PMP.scala:181:23] wire [29:0] _res_T_179_addr = 30'h0; // @[PMP.scala:185:8] wire [29:0] res_cur_4_addr = 30'h0; // @[PMP.scala:181:23] wire [29:0] _res_T_224_addr = 30'h0; // @[PMP.scala:185:8] wire [29:0] res_cur_5_addr = 30'h0; // @[PMP.scala:181:23] wire [29:0] _res_T_269_addr = 30'h0; // @[PMP.scala:185:8] wire [29:0] res_cur_6_addr = 30'h0; // @[PMP.scala:181:23] wire [29:0] _res_T_314_addr = 30'h0; // @[PMP.scala:185:8] wire [29:0] res_cur_7_addr = 30'h0; // @[PMP.scala:181:23] wire [29:0] res_addr = 30'h0; // @[PMP.scala:185:8] wire [1:0] io_pmp_0_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_0_cfg_a = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_1_cfg_a = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_2_cfg_a = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_3_cfg_a = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_4_cfg_a = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_5_cfg_a = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_6_cfg_a = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_res = 2'h0; // @[PMP.scala:143:7] wire [1:0] io_pmp_7_cfg_a = 2'h0; // @[PMP.scala:143:7] wire [1:0] _pmp0_WIRE_cfg_res = 2'h0; // @[PMP.scala:157:35] wire [1:0] _pmp0_WIRE_cfg_a = 2'h0; // @[PMP.scala:157:35] wire [1:0] pmp0_cfg_res = 2'h0; // @[PMP.scala:157:22] wire [1:0] pmp0_cfg_a = 2'h0; // @[PMP.scala:157:22] wire [1:0] res_hi = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_1 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_2 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_3 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_4 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_5 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_cur_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cur_cfg_a = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_44_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_T_44_cfg_a = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_hi_6 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_7 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_8 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_9 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_10 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_11 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_cur_1_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cur_1_cfg_a = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_89_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_T_89_cfg_a = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_hi_12 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_13 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_14 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_15 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_16 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_17 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_cur_2_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cur_2_cfg_a = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_134_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_T_134_cfg_a = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_hi_18 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_19 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_20 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_21 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_22 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_23 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_cur_3_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cur_3_cfg_a = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_179_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_T_179_cfg_a = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_hi_24 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_25 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_26 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_27 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_28 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_29 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_cur_4_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cur_4_cfg_a = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_224_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_T_224_cfg_a = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_hi_30 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_31 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_32 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_33 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_34 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_35 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_cur_5_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cur_5_cfg_a = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_269_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_T_269_cfg_a = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_hi_36 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_37 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_38 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_39 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_40 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_41 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_cur_6_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cur_6_cfg_a = 2'h0; // @[PMP.scala:181:23] wire [1:0] _res_T_314_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] _res_T_314_cfg_a = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_hi_42 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_43 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_44 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_45 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_46 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_hi_47 = 2'h0; // @[PMP.scala:174:26] wire [1:0] res_cur_7_cfg_res = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cur_7_cfg_a = 2'h0; // @[PMP.scala:181:23] wire [1:0] res_cfg_res = 2'h0; // @[PMP.scala:185:8] wire [1:0] res_cfg_a = 2'h0; // @[PMP.scala:185:8] wire io_pmp_0_cfg_l = 1'h0; // @[PMP.scala:143:7] wire io_pmp_0_cfg_x = 1'h0; // @[PMP.scala:143:7] wire io_pmp_0_cfg_w = 1'h0; // @[PMP.scala:143:7] wire io_pmp_0_cfg_r = 1'h0; // @[PMP.scala:143:7] wire io_pmp_1_cfg_l = 1'h0; // @[PMP.scala:143:7] wire io_pmp_1_cfg_x = 1'h0; // @[PMP.scala:143:7] wire io_pmp_1_cfg_w = 1'h0; // @[PMP.scala:143:7] wire io_pmp_1_cfg_r = 1'h0; // @[PMP.scala:143:7] wire io_pmp_2_cfg_l = 1'h0; // @[PMP.scala:143:7] wire io_pmp_2_cfg_x = 1'h0; // @[PMP.scala:143:7] wire io_pmp_2_cfg_w = 1'h0; // @[PMP.scala:143:7] wire io_pmp_2_cfg_r = 1'h0; // @[PMP.scala:143:7] wire io_pmp_3_cfg_l = 1'h0; // @[PMP.scala:143:7] wire io_pmp_3_cfg_x = 1'h0; // @[PMP.scala:143:7] wire io_pmp_3_cfg_w = 1'h0; // @[PMP.scala:143:7] wire io_pmp_3_cfg_r = 1'h0; // @[PMP.scala:143:7] wire io_pmp_4_cfg_l = 1'h0; // @[PMP.scala:143:7] wire io_pmp_4_cfg_x = 1'h0; // @[PMP.scala:143:7] wire io_pmp_4_cfg_w = 1'h0; // @[PMP.scala:143:7] wire io_pmp_4_cfg_r = 1'h0; // @[PMP.scala:143:7] wire io_pmp_5_cfg_l = 1'h0; // @[PMP.scala:143:7] wire io_pmp_5_cfg_x = 1'h0; // @[PMP.scala:143:7] wire io_pmp_5_cfg_w = 1'h0; // @[PMP.scala:143:7] wire io_pmp_5_cfg_r = 1'h0; // @[PMP.scala:143:7] wire io_pmp_6_cfg_l = 1'h0; // @[PMP.scala:143:7] wire io_pmp_6_cfg_x = 1'h0; // @[PMP.scala:143:7] wire io_pmp_6_cfg_w = 1'h0; // @[PMP.scala:143:7] wire io_pmp_6_cfg_r = 1'h0; // @[PMP.scala:143:7] wire io_pmp_7_cfg_l = 1'h0; // @[PMP.scala:143:7] wire io_pmp_7_cfg_x = 1'h0; // @[PMP.scala:143:7] wire io_pmp_7_cfg_w = 1'h0; // @[PMP.scala:143:7] wire io_pmp_7_cfg_r = 1'h0; // @[PMP.scala:143:7] wire io_r = 1'h0; // @[PMP.scala:143:7] wire io_w = 1'h0; // @[PMP.scala:143:7] wire io_x = 1'h0; // @[PMP.scala:143:7] wire default_0 = 1'h0; // @[PMP.scala:156:56] wire _pmp0_WIRE_cfg_l = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_x = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_w = 1'h0; // @[PMP.scala:157:35] wire _pmp0_WIRE_cfg_r = 1'h0; // @[PMP.scala:157:35] wire pmp0_cfg_l = 1'h0; // @[PMP.scala:157:22] wire pmp0_cfg_x = 1'h0; // @[PMP.scala:157:22] wire pmp0_cfg_w = 1'h0; // @[PMP.scala:157:22] wire pmp0_cfg_r = 1'h0; // @[PMP.scala:157:22] wire _res_hit_T = 1'h0; // @[PMP.scala:45:20] wire _res_hit_T_2 = 1'h0; // @[PMP.scala:46:26] wire res_hit_msbsLess = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_6 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_7 = 1'h0; // @[PMP.scala:83:16] wire res_hit_msbsLess_1 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_1 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_9 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_10 = 1'h0; // @[PMP.scala:83:16] wire _res_hit_T_11 = 1'h0; // @[PMP.scala:94:48] wire _res_hit_T_12 = 1'h0; // @[PMP.scala:132:61] wire res_hit = 1'h0; // @[PMP.scala:132:8] wire res_ignore = 1'h0; // @[PMP.scala:164:26] wire _res_aligned_straddlesLowerBound_T_16 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound = 1'h0; // @[PMP.scala:123:90] wire _res_aligned_straddlesUpperBound_T_16 = 1'h0; // @[PMP.scala:124:148] wire res_aligned_straddlesUpperBound = 1'h0; // @[PMP.scala:124:85] wire _res_aligned_rangeAligned_T = 1'h0; // @[PMP.scala:125:46] wire _res_aligned_T = 1'h0; // @[PMP.scala:45:20] wire _res_T_1 = 1'h0; // @[PMP.scala:168:32] wire _res_T_2 = 1'h0; // @[PMP.scala:168:32] wire _res_T_3 = 1'h0; // @[PMP.scala:168:32] wire _res_T_4 = 1'h0; // @[PMP.scala:170:30] wire _res_T_8 = 1'h0; // @[PMP.scala:174:60] wire _res_T_10 = 1'h0; // @[PMP.scala:174:60] wire _res_T_12 = 1'h0; // @[PMP.scala:174:60] wire _res_T_14 = 1'h0; // @[PMP.scala:174:60] wire _res_T_16 = 1'h0; // @[PMP.scala:174:60] wire _res_T_18 = 1'h0; // @[PMP.scala:177:30] wire _res_T_19 = 1'h0; // @[PMP.scala:177:37] wire _res_T_20 = 1'h0; // @[PMP.scala:177:61] wire _res_T_21 = 1'h0; // @[PMP.scala:177:48] wire _res_T_22 = 1'h0; // @[PMP.scala:178:32] wire _res_T_23 = 1'h0; // @[PMP.scala:178:39] wire _res_T_24 = 1'h0; // @[PMP.scala:178:63] wire _res_T_25 = 1'h0; // @[PMP.scala:178:50] wire _res_T_27 = 1'h0; // @[PMP.scala:177:30] wire _res_T_28 = 1'h0; // @[PMP.scala:177:37] wire _res_T_29 = 1'h0; // @[PMP.scala:177:61] wire _res_T_30 = 1'h0; // @[PMP.scala:177:48] wire _res_T_31 = 1'h0; // @[PMP.scala:178:32] wire _res_T_32 = 1'h0; // @[PMP.scala:178:39] wire _res_T_33 = 1'h0; // @[PMP.scala:178:63] wire _res_T_34 = 1'h0; // @[PMP.scala:178:50] wire _res_T_36 = 1'h0; // @[PMP.scala:177:30] wire _res_T_37 = 1'h0; // @[PMP.scala:177:37] wire _res_T_38 = 1'h0; // @[PMP.scala:177:61] wire _res_T_39 = 1'h0; // @[PMP.scala:177:48] wire _res_T_40 = 1'h0; // @[PMP.scala:178:32] wire _res_T_41 = 1'h0; // @[PMP.scala:178:39] wire _res_T_42 = 1'h0; // @[PMP.scala:178:63] wire _res_T_43 = 1'h0; // @[PMP.scala:178:50] wire res_cur_cfg_l = 1'h0; // @[PMP.scala:181:23] wire res_cur_cfg_x = 1'h0; // @[PMP.scala:181:23] wire res_cur_cfg_w = 1'h0; // @[PMP.scala:181:23] wire res_cur_cfg_r = 1'h0; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T = 1'h0; // @[PMP.scala:182:40] wire _res_cur_cfg_r_T_1 = 1'h0; // @[PMP.scala:182:26] wire _res_cur_cfg_w_T = 1'h0; // @[PMP.scala:183:40] wire _res_cur_cfg_w_T_1 = 1'h0; // @[PMP.scala:183:26] wire _res_cur_cfg_x_T = 1'h0; // @[PMP.scala:184:40] wire _res_cur_cfg_x_T_1 = 1'h0; // @[PMP.scala:184:26] wire _res_T_44_cfg_l = 1'h0; // @[PMP.scala:185:8] wire _res_T_44_cfg_x = 1'h0; // @[PMP.scala:185:8] wire _res_T_44_cfg_w = 1'h0; // @[PMP.scala:185:8] wire _res_T_44_cfg_r = 1'h0; // @[PMP.scala:185:8] wire _res_hit_T_13 = 1'h0; // @[PMP.scala:45:20] wire _res_hit_T_15 = 1'h0; // @[PMP.scala:46:26] wire res_hit_msbsLess_2 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_2 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_19 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_20 = 1'h0; // @[PMP.scala:83:16] wire res_hit_msbsLess_3 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_3 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_22 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_23 = 1'h0; // @[PMP.scala:83:16] wire _res_hit_T_24 = 1'h0; // @[PMP.scala:94:48] wire _res_hit_T_25 = 1'h0; // @[PMP.scala:132:61] wire res_hit_1 = 1'h0; // @[PMP.scala:132:8] wire res_ignore_1 = 1'h0; // @[PMP.scala:164:26] wire _res_aligned_straddlesLowerBound_T_33 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_1 = 1'h0; // @[PMP.scala:123:90] wire _res_aligned_straddlesUpperBound_T_33 = 1'h0; // @[PMP.scala:124:148] wire res_aligned_straddlesUpperBound_1 = 1'h0; // @[PMP.scala:124:85] wire _res_aligned_rangeAligned_T_1 = 1'h0; // @[PMP.scala:125:46] wire _res_aligned_T_1 = 1'h0; // @[PMP.scala:45:20] wire _res_T_46 = 1'h0; // @[PMP.scala:168:32] wire _res_T_47 = 1'h0; // @[PMP.scala:168:32] wire _res_T_48 = 1'h0; // @[PMP.scala:168:32] wire _res_T_49 = 1'h0; // @[PMP.scala:170:30] wire _res_T_53 = 1'h0; // @[PMP.scala:174:60] wire _res_T_55 = 1'h0; // @[PMP.scala:174:60] wire _res_T_57 = 1'h0; // @[PMP.scala:174:60] wire _res_T_59 = 1'h0; // @[PMP.scala:174:60] wire _res_T_61 = 1'h0; // @[PMP.scala:174:60] wire _res_T_63 = 1'h0; // @[PMP.scala:177:30] wire _res_T_64 = 1'h0; // @[PMP.scala:177:37] wire _res_T_65 = 1'h0; // @[PMP.scala:177:61] wire _res_T_66 = 1'h0; // @[PMP.scala:177:48] wire _res_T_67 = 1'h0; // @[PMP.scala:178:32] wire _res_T_68 = 1'h0; // @[PMP.scala:178:39] wire _res_T_69 = 1'h0; // @[PMP.scala:178:63] wire _res_T_70 = 1'h0; // @[PMP.scala:178:50] wire _res_T_72 = 1'h0; // @[PMP.scala:177:30] wire _res_T_73 = 1'h0; // @[PMP.scala:177:37] wire _res_T_74 = 1'h0; // @[PMP.scala:177:61] wire _res_T_75 = 1'h0; // @[PMP.scala:177:48] wire _res_T_76 = 1'h0; // @[PMP.scala:178:32] wire _res_T_77 = 1'h0; // @[PMP.scala:178:39] wire _res_T_78 = 1'h0; // @[PMP.scala:178:63] wire _res_T_79 = 1'h0; // @[PMP.scala:178:50] wire _res_T_81 = 1'h0; // @[PMP.scala:177:30] wire _res_T_82 = 1'h0; // @[PMP.scala:177:37] wire _res_T_83 = 1'h0; // @[PMP.scala:177:61] wire _res_T_84 = 1'h0; // @[PMP.scala:177:48] wire _res_T_85 = 1'h0; // @[PMP.scala:178:32] wire _res_T_86 = 1'h0; // @[PMP.scala:178:39] wire _res_T_87 = 1'h0; // @[PMP.scala:178:63] wire _res_T_88 = 1'h0; // @[PMP.scala:178:50] wire res_cur_1_cfg_l = 1'h0; // @[PMP.scala:181:23] wire res_cur_1_cfg_x = 1'h0; // @[PMP.scala:181:23] wire res_cur_1_cfg_w = 1'h0; // @[PMP.scala:181:23] wire res_cur_1_cfg_r = 1'h0; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_2 = 1'h0; // @[PMP.scala:182:40] wire _res_cur_cfg_r_T_3 = 1'h0; // @[PMP.scala:182:26] wire _res_cur_cfg_w_T_2 = 1'h0; // @[PMP.scala:183:40] wire _res_cur_cfg_w_T_3 = 1'h0; // @[PMP.scala:183:26] wire _res_cur_cfg_x_T_2 = 1'h0; // @[PMP.scala:184:40] wire _res_cur_cfg_x_T_3 = 1'h0; // @[PMP.scala:184:26] wire _res_T_89_cfg_l = 1'h0; // @[PMP.scala:185:8] wire _res_T_89_cfg_x = 1'h0; // @[PMP.scala:185:8] wire _res_T_89_cfg_w = 1'h0; // @[PMP.scala:185:8] wire _res_T_89_cfg_r = 1'h0; // @[PMP.scala:185:8] wire _res_hit_T_26 = 1'h0; // @[PMP.scala:45:20] wire _res_hit_T_28 = 1'h0; // @[PMP.scala:46:26] wire res_hit_msbsLess_4 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_4 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_32 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_33 = 1'h0; // @[PMP.scala:83:16] wire res_hit_msbsLess_5 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_5 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_35 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_36 = 1'h0; // @[PMP.scala:83:16] wire _res_hit_T_37 = 1'h0; // @[PMP.scala:94:48] wire _res_hit_T_38 = 1'h0; // @[PMP.scala:132:61] wire res_hit_2 = 1'h0; // @[PMP.scala:132:8] wire res_ignore_2 = 1'h0; // @[PMP.scala:164:26] wire _res_aligned_straddlesLowerBound_T_50 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_2 = 1'h0; // @[PMP.scala:123:90] wire _res_aligned_straddlesUpperBound_T_50 = 1'h0; // @[PMP.scala:124:148] wire res_aligned_straddlesUpperBound_2 = 1'h0; // @[PMP.scala:124:85] wire _res_aligned_rangeAligned_T_2 = 1'h0; // @[PMP.scala:125:46] wire _res_aligned_T_2 = 1'h0; // @[PMP.scala:45:20] wire _res_T_91 = 1'h0; // @[PMP.scala:168:32] wire _res_T_92 = 1'h0; // @[PMP.scala:168:32] wire _res_T_93 = 1'h0; // @[PMP.scala:168:32] wire _res_T_94 = 1'h0; // @[PMP.scala:170:30] wire _res_T_98 = 1'h0; // @[PMP.scala:174:60] wire _res_T_100 = 1'h0; // @[PMP.scala:174:60] wire _res_T_102 = 1'h0; // @[PMP.scala:174:60] wire _res_T_104 = 1'h0; // @[PMP.scala:174:60] wire _res_T_106 = 1'h0; // @[PMP.scala:174:60] wire _res_T_108 = 1'h0; // @[PMP.scala:177:30] wire _res_T_109 = 1'h0; // @[PMP.scala:177:37] wire _res_T_110 = 1'h0; // @[PMP.scala:177:61] wire _res_T_111 = 1'h0; // @[PMP.scala:177:48] wire _res_T_112 = 1'h0; // @[PMP.scala:178:32] wire _res_T_113 = 1'h0; // @[PMP.scala:178:39] wire _res_T_114 = 1'h0; // @[PMP.scala:178:63] wire _res_T_115 = 1'h0; // @[PMP.scala:178:50] wire _res_T_117 = 1'h0; // @[PMP.scala:177:30] wire _res_T_118 = 1'h0; // @[PMP.scala:177:37] wire _res_T_119 = 1'h0; // @[PMP.scala:177:61] wire _res_T_120 = 1'h0; // @[PMP.scala:177:48] wire _res_T_121 = 1'h0; // @[PMP.scala:178:32] wire _res_T_122 = 1'h0; // @[PMP.scala:178:39] wire _res_T_123 = 1'h0; // @[PMP.scala:178:63] wire _res_T_124 = 1'h0; // @[PMP.scala:178:50] wire _res_T_126 = 1'h0; // @[PMP.scala:177:30] wire _res_T_127 = 1'h0; // @[PMP.scala:177:37] wire _res_T_128 = 1'h0; // @[PMP.scala:177:61] wire _res_T_129 = 1'h0; // @[PMP.scala:177:48] wire _res_T_130 = 1'h0; // @[PMP.scala:178:32] wire _res_T_131 = 1'h0; // @[PMP.scala:178:39] wire _res_T_132 = 1'h0; // @[PMP.scala:178:63] wire _res_T_133 = 1'h0; // @[PMP.scala:178:50] wire res_cur_2_cfg_l = 1'h0; // @[PMP.scala:181:23] wire res_cur_2_cfg_x = 1'h0; // @[PMP.scala:181:23] wire res_cur_2_cfg_w = 1'h0; // @[PMP.scala:181:23] wire res_cur_2_cfg_r = 1'h0; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_4 = 1'h0; // @[PMP.scala:182:40] wire _res_cur_cfg_r_T_5 = 1'h0; // @[PMP.scala:182:26] wire _res_cur_cfg_w_T_4 = 1'h0; // @[PMP.scala:183:40] wire _res_cur_cfg_w_T_5 = 1'h0; // @[PMP.scala:183:26] wire _res_cur_cfg_x_T_4 = 1'h0; // @[PMP.scala:184:40] wire _res_cur_cfg_x_T_5 = 1'h0; // @[PMP.scala:184:26] wire _res_T_134_cfg_l = 1'h0; // @[PMP.scala:185:8] wire _res_T_134_cfg_x = 1'h0; // @[PMP.scala:185:8] wire _res_T_134_cfg_w = 1'h0; // @[PMP.scala:185:8] wire _res_T_134_cfg_r = 1'h0; // @[PMP.scala:185:8] wire _res_hit_T_39 = 1'h0; // @[PMP.scala:45:20] wire _res_hit_T_41 = 1'h0; // @[PMP.scala:46:26] wire res_hit_msbsLess_6 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_6 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_45 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_46 = 1'h0; // @[PMP.scala:83:16] wire res_hit_msbsLess_7 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_7 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_48 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_49 = 1'h0; // @[PMP.scala:83:16] wire _res_hit_T_50 = 1'h0; // @[PMP.scala:94:48] wire _res_hit_T_51 = 1'h0; // @[PMP.scala:132:61] wire res_hit_3 = 1'h0; // @[PMP.scala:132:8] wire res_ignore_3 = 1'h0; // @[PMP.scala:164:26] wire _res_aligned_straddlesLowerBound_T_67 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_3 = 1'h0; // @[PMP.scala:123:90] wire _res_aligned_straddlesUpperBound_T_67 = 1'h0; // @[PMP.scala:124:148] wire res_aligned_straddlesUpperBound_3 = 1'h0; // @[PMP.scala:124:85] wire _res_aligned_rangeAligned_T_3 = 1'h0; // @[PMP.scala:125:46] wire _res_aligned_T_3 = 1'h0; // @[PMP.scala:45:20] wire _res_T_136 = 1'h0; // @[PMP.scala:168:32] wire _res_T_137 = 1'h0; // @[PMP.scala:168:32] wire _res_T_138 = 1'h0; // @[PMP.scala:168:32] wire _res_T_139 = 1'h0; // @[PMP.scala:170:30] wire _res_T_143 = 1'h0; // @[PMP.scala:174:60] wire _res_T_145 = 1'h0; // @[PMP.scala:174:60] wire _res_T_147 = 1'h0; // @[PMP.scala:174:60] wire _res_T_149 = 1'h0; // @[PMP.scala:174:60] wire _res_T_151 = 1'h0; // @[PMP.scala:174:60] wire _res_T_153 = 1'h0; // @[PMP.scala:177:30] wire _res_T_154 = 1'h0; // @[PMP.scala:177:37] wire _res_T_155 = 1'h0; // @[PMP.scala:177:61] wire _res_T_156 = 1'h0; // @[PMP.scala:177:48] wire _res_T_157 = 1'h0; // @[PMP.scala:178:32] wire _res_T_158 = 1'h0; // @[PMP.scala:178:39] wire _res_T_159 = 1'h0; // @[PMP.scala:178:63] wire _res_T_160 = 1'h0; // @[PMP.scala:178:50] wire _res_T_162 = 1'h0; // @[PMP.scala:177:30] wire _res_T_163 = 1'h0; // @[PMP.scala:177:37] wire _res_T_164 = 1'h0; // @[PMP.scala:177:61] wire _res_T_165 = 1'h0; // @[PMP.scala:177:48] wire _res_T_166 = 1'h0; // @[PMP.scala:178:32] wire _res_T_167 = 1'h0; // @[PMP.scala:178:39] wire _res_T_168 = 1'h0; // @[PMP.scala:178:63] wire _res_T_169 = 1'h0; // @[PMP.scala:178:50] wire _res_T_171 = 1'h0; // @[PMP.scala:177:30] wire _res_T_172 = 1'h0; // @[PMP.scala:177:37] wire _res_T_173 = 1'h0; // @[PMP.scala:177:61] wire _res_T_174 = 1'h0; // @[PMP.scala:177:48] wire _res_T_175 = 1'h0; // @[PMP.scala:178:32] wire _res_T_176 = 1'h0; // @[PMP.scala:178:39] wire _res_T_177 = 1'h0; // @[PMP.scala:178:63] wire _res_T_178 = 1'h0; // @[PMP.scala:178:50] wire res_cur_3_cfg_l = 1'h0; // @[PMP.scala:181:23] wire res_cur_3_cfg_x = 1'h0; // @[PMP.scala:181:23] wire res_cur_3_cfg_w = 1'h0; // @[PMP.scala:181:23] wire res_cur_3_cfg_r = 1'h0; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_6 = 1'h0; // @[PMP.scala:182:40] wire _res_cur_cfg_r_T_7 = 1'h0; // @[PMP.scala:182:26] wire _res_cur_cfg_w_T_6 = 1'h0; // @[PMP.scala:183:40] wire _res_cur_cfg_w_T_7 = 1'h0; // @[PMP.scala:183:26] wire _res_cur_cfg_x_T_6 = 1'h0; // @[PMP.scala:184:40] wire _res_cur_cfg_x_T_7 = 1'h0; // @[PMP.scala:184:26] wire _res_T_179_cfg_l = 1'h0; // @[PMP.scala:185:8] wire _res_T_179_cfg_x = 1'h0; // @[PMP.scala:185:8] wire _res_T_179_cfg_w = 1'h0; // @[PMP.scala:185:8] wire _res_T_179_cfg_r = 1'h0; // @[PMP.scala:185:8] wire _res_hit_T_52 = 1'h0; // @[PMP.scala:45:20] wire _res_hit_T_54 = 1'h0; // @[PMP.scala:46:26] wire res_hit_msbsLess_8 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_8 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_58 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_59 = 1'h0; // @[PMP.scala:83:16] wire res_hit_msbsLess_9 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_9 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_61 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_62 = 1'h0; // @[PMP.scala:83:16] wire _res_hit_T_63 = 1'h0; // @[PMP.scala:94:48] wire _res_hit_T_64 = 1'h0; // @[PMP.scala:132:61] wire res_hit_4 = 1'h0; // @[PMP.scala:132:8] wire res_ignore_4 = 1'h0; // @[PMP.scala:164:26] wire _res_aligned_straddlesLowerBound_T_84 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_4 = 1'h0; // @[PMP.scala:123:90] wire _res_aligned_straddlesUpperBound_T_84 = 1'h0; // @[PMP.scala:124:148] wire res_aligned_straddlesUpperBound_4 = 1'h0; // @[PMP.scala:124:85] wire _res_aligned_rangeAligned_T_4 = 1'h0; // @[PMP.scala:125:46] wire _res_aligned_T_4 = 1'h0; // @[PMP.scala:45:20] wire _res_T_181 = 1'h0; // @[PMP.scala:168:32] wire _res_T_182 = 1'h0; // @[PMP.scala:168:32] wire _res_T_183 = 1'h0; // @[PMP.scala:168:32] wire _res_T_184 = 1'h0; // @[PMP.scala:170:30] wire _res_T_188 = 1'h0; // @[PMP.scala:174:60] wire _res_T_190 = 1'h0; // @[PMP.scala:174:60] wire _res_T_192 = 1'h0; // @[PMP.scala:174:60] wire _res_T_194 = 1'h0; // @[PMP.scala:174:60] wire _res_T_196 = 1'h0; // @[PMP.scala:174:60] wire _res_T_198 = 1'h0; // @[PMP.scala:177:30] wire _res_T_199 = 1'h0; // @[PMP.scala:177:37] wire _res_T_200 = 1'h0; // @[PMP.scala:177:61] wire _res_T_201 = 1'h0; // @[PMP.scala:177:48] wire _res_T_202 = 1'h0; // @[PMP.scala:178:32] wire _res_T_203 = 1'h0; // @[PMP.scala:178:39] wire _res_T_204 = 1'h0; // @[PMP.scala:178:63] wire _res_T_205 = 1'h0; // @[PMP.scala:178:50] wire _res_T_207 = 1'h0; // @[PMP.scala:177:30] wire _res_T_208 = 1'h0; // @[PMP.scala:177:37] wire _res_T_209 = 1'h0; // @[PMP.scala:177:61] wire _res_T_210 = 1'h0; // @[PMP.scala:177:48] wire _res_T_211 = 1'h0; // @[PMP.scala:178:32] wire _res_T_212 = 1'h0; // @[PMP.scala:178:39] wire _res_T_213 = 1'h0; // @[PMP.scala:178:63] wire _res_T_214 = 1'h0; // @[PMP.scala:178:50] wire _res_T_216 = 1'h0; // @[PMP.scala:177:30] wire _res_T_217 = 1'h0; // @[PMP.scala:177:37] wire _res_T_218 = 1'h0; // @[PMP.scala:177:61] wire _res_T_219 = 1'h0; // @[PMP.scala:177:48] wire _res_T_220 = 1'h0; // @[PMP.scala:178:32] wire _res_T_221 = 1'h0; // @[PMP.scala:178:39] wire _res_T_222 = 1'h0; // @[PMP.scala:178:63] wire _res_T_223 = 1'h0; // @[PMP.scala:178:50] wire res_cur_4_cfg_l = 1'h0; // @[PMP.scala:181:23] wire res_cur_4_cfg_x = 1'h0; // @[PMP.scala:181:23] wire res_cur_4_cfg_w = 1'h0; // @[PMP.scala:181:23] wire res_cur_4_cfg_r = 1'h0; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_8 = 1'h0; // @[PMP.scala:182:40] wire _res_cur_cfg_r_T_9 = 1'h0; // @[PMP.scala:182:26] wire _res_cur_cfg_w_T_8 = 1'h0; // @[PMP.scala:183:40] wire _res_cur_cfg_w_T_9 = 1'h0; // @[PMP.scala:183:26] wire _res_cur_cfg_x_T_8 = 1'h0; // @[PMP.scala:184:40] wire _res_cur_cfg_x_T_9 = 1'h0; // @[PMP.scala:184:26] wire _res_T_224_cfg_l = 1'h0; // @[PMP.scala:185:8] wire _res_T_224_cfg_x = 1'h0; // @[PMP.scala:185:8] wire _res_T_224_cfg_w = 1'h0; // @[PMP.scala:185:8] wire _res_T_224_cfg_r = 1'h0; // @[PMP.scala:185:8] wire _res_hit_T_65 = 1'h0; // @[PMP.scala:45:20] wire _res_hit_T_67 = 1'h0; // @[PMP.scala:46:26] wire res_hit_msbsLess_10 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_10 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_71 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_72 = 1'h0; // @[PMP.scala:83:16] wire res_hit_msbsLess_11 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_11 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_74 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_75 = 1'h0; // @[PMP.scala:83:16] wire _res_hit_T_76 = 1'h0; // @[PMP.scala:94:48] wire _res_hit_T_77 = 1'h0; // @[PMP.scala:132:61] wire res_hit_5 = 1'h0; // @[PMP.scala:132:8] wire res_ignore_5 = 1'h0; // @[PMP.scala:164:26] wire _res_aligned_straddlesLowerBound_T_101 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_5 = 1'h0; // @[PMP.scala:123:90] wire _res_aligned_straddlesUpperBound_T_101 = 1'h0; // @[PMP.scala:124:148] wire res_aligned_straddlesUpperBound_5 = 1'h0; // @[PMP.scala:124:85] wire _res_aligned_rangeAligned_T_5 = 1'h0; // @[PMP.scala:125:46] wire _res_aligned_T_5 = 1'h0; // @[PMP.scala:45:20] wire _res_T_226 = 1'h0; // @[PMP.scala:168:32] wire _res_T_227 = 1'h0; // @[PMP.scala:168:32] wire _res_T_228 = 1'h0; // @[PMP.scala:168:32] wire _res_T_229 = 1'h0; // @[PMP.scala:170:30] wire _res_T_233 = 1'h0; // @[PMP.scala:174:60] wire _res_T_235 = 1'h0; // @[PMP.scala:174:60] wire _res_T_237 = 1'h0; // @[PMP.scala:174:60] wire _res_T_239 = 1'h0; // @[PMP.scala:174:60] wire _res_T_241 = 1'h0; // @[PMP.scala:174:60] wire _res_T_243 = 1'h0; // @[PMP.scala:177:30] wire _res_T_244 = 1'h0; // @[PMP.scala:177:37] wire _res_T_245 = 1'h0; // @[PMP.scala:177:61] wire _res_T_246 = 1'h0; // @[PMP.scala:177:48] wire _res_T_247 = 1'h0; // @[PMP.scala:178:32] wire _res_T_248 = 1'h0; // @[PMP.scala:178:39] wire _res_T_249 = 1'h0; // @[PMP.scala:178:63] wire _res_T_250 = 1'h0; // @[PMP.scala:178:50] wire _res_T_252 = 1'h0; // @[PMP.scala:177:30] wire _res_T_253 = 1'h0; // @[PMP.scala:177:37] wire _res_T_254 = 1'h0; // @[PMP.scala:177:61] wire _res_T_255 = 1'h0; // @[PMP.scala:177:48] wire _res_T_256 = 1'h0; // @[PMP.scala:178:32] wire _res_T_257 = 1'h0; // @[PMP.scala:178:39] wire _res_T_258 = 1'h0; // @[PMP.scala:178:63] wire _res_T_259 = 1'h0; // @[PMP.scala:178:50] wire _res_T_261 = 1'h0; // @[PMP.scala:177:30] wire _res_T_262 = 1'h0; // @[PMP.scala:177:37] wire _res_T_263 = 1'h0; // @[PMP.scala:177:61] wire _res_T_264 = 1'h0; // @[PMP.scala:177:48] wire _res_T_265 = 1'h0; // @[PMP.scala:178:32] wire _res_T_266 = 1'h0; // @[PMP.scala:178:39] wire _res_T_267 = 1'h0; // @[PMP.scala:178:63] wire _res_T_268 = 1'h0; // @[PMP.scala:178:50] wire res_cur_5_cfg_l = 1'h0; // @[PMP.scala:181:23] wire res_cur_5_cfg_x = 1'h0; // @[PMP.scala:181:23] wire res_cur_5_cfg_w = 1'h0; // @[PMP.scala:181:23] wire res_cur_5_cfg_r = 1'h0; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_10 = 1'h0; // @[PMP.scala:182:40] wire _res_cur_cfg_r_T_11 = 1'h0; // @[PMP.scala:182:26] wire _res_cur_cfg_w_T_10 = 1'h0; // @[PMP.scala:183:40] wire _res_cur_cfg_w_T_11 = 1'h0; // @[PMP.scala:183:26] wire _res_cur_cfg_x_T_10 = 1'h0; // @[PMP.scala:184:40] wire _res_cur_cfg_x_T_11 = 1'h0; // @[PMP.scala:184:26] wire _res_T_269_cfg_l = 1'h0; // @[PMP.scala:185:8] wire _res_T_269_cfg_x = 1'h0; // @[PMP.scala:185:8] wire _res_T_269_cfg_w = 1'h0; // @[PMP.scala:185:8] wire _res_T_269_cfg_r = 1'h0; // @[PMP.scala:185:8] wire _res_hit_T_78 = 1'h0; // @[PMP.scala:45:20] wire _res_hit_T_80 = 1'h0; // @[PMP.scala:46:26] wire res_hit_msbsLess_12 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_12 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_84 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_85 = 1'h0; // @[PMP.scala:83:16] wire res_hit_msbsLess_13 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_13 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_87 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_88 = 1'h0; // @[PMP.scala:83:16] wire _res_hit_T_89 = 1'h0; // @[PMP.scala:94:48] wire _res_hit_T_90 = 1'h0; // @[PMP.scala:132:61] wire res_hit_6 = 1'h0; // @[PMP.scala:132:8] wire res_ignore_6 = 1'h0; // @[PMP.scala:164:26] wire _res_aligned_straddlesLowerBound_T_118 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_6 = 1'h0; // @[PMP.scala:123:90] wire _res_aligned_straddlesUpperBound_T_118 = 1'h0; // @[PMP.scala:124:148] wire res_aligned_straddlesUpperBound_6 = 1'h0; // @[PMP.scala:124:85] wire _res_aligned_rangeAligned_T_6 = 1'h0; // @[PMP.scala:125:46] wire _res_aligned_T_6 = 1'h0; // @[PMP.scala:45:20] wire _res_T_271 = 1'h0; // @[PMP.scala:168:32] wire _res_T_272 = 1'h0; // @[PMP.scala:168:32] wire _res_T_273 = 1'h0; // @[PMP.scala:168:32] wire _res_T_274 = 1'h0; // @[PMP.scala:170:30] wire _res_T_278 = 1'h0; // @[PMP.scala:174:60] wire _res_T_280 = 1'h0; // @[PMP.scala:174:60] wire _res_T_282 = 1'h0; // @[PMP.scala:174:60] wire _res_T_284 = 1'h0; // @[PMP.scala:174:60] wire _res_T_286 = 1'h0; // @[PMP.scala:174:60] wire _res_T_288 = 1'h0; // @[PMP.scala:177:30] wire _res_T_289 = 1'h0; // @[PMP.scala:177:37] wire _res_T_290 = 1'h0; // @[PMP.scala:177:61] wire _res_T_291 = 1'h0; // @[PMP.scala:177:48] wire _res_T_292 = 1'h0; // @[PMP.scala:178:32] wire _res_T_293 = 1'h0; // @[PMP.scala:178:39] wire _res_T_294 = 1'h0; // @[PMP.scala:178:63] wire _res_T_295 = 1'h0; // @[PMP.scala:178:50] wire _res_T_297 = 1'h0; // @[PMP.scala:177:30] wire _res_T_298 = 1'h0; // @[PMP.scala:177:37] wire _res_T_299 = 1'h0; // @[PMP.scala:177:61] wire _res_T_300 = 1'h0; // @[PMP.scala:177:48] wire _res_T_301 = 1'h0; // @[PMP.scala:178:32] wire _res_T_302 = 1'h0; // @[PMP.scala:178:39] wire _res_T_303 = 1'h0; // @[PMP.scala:178:63] wire _res_T_304 = 1'h0; // @[PMP.scala:178:50] wire _res_T_306 = 1'h0; // @[PMP.scala:177:30] wire _res_T_307 = 1'h0; // @[PMP.scala:177:37] wire _res_T_308 = 1'h0; // @[PMP.scala:177:61] wire _res_T_309 = 1'h0; // @[PMP.scala:177:48] wire _res_T_310 = 1'h0; // @[PMP.scala:178:32] wire _res_T_311 = 1'h0; // @[PMP.scala:178:39] wire _res_T_312 = 1'h0; // @[PMP.scala:178:63] wire _res_T_313 = 1'h0; // @[PMP.scala:178:50] wire res_cur_6_cfg_l = 1'h0; // @[PMP.scala:181:23] wire res_cur_6_cfg_x = 1'h0; // @[PMP.scala:181:23] wire res_cur_6_cfg_w = 1'h0; // @[PMP.scala:181:23] wire res_cur_6_cfg_r = 1'h0; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_12 = 1'h0; // @[PMP.scala:182:40] wire _res_cur_cfg_r_T_13 = 1'h0; // @[PMP.scala:182:26] wire _res_cur_cfg_w_T_12 = 1'h0; // @[PMP.scala:183:40] wire _res_cur_cfg_w_T_13 = 1'h0; // @[PMP.scala:183:26] wire _res_cur_cfg_x_T_12 = 1'h0; // @[PMP.scala:184:40] wire _res_cur_cfg_x_T_13 = 1'h0; // @[PMP.scala:184:26] wire _res_T_314_cfg_l = 1'h0; // @[PMP.scala:185:8] wire _res_T_314_cfg_x = 1'h0; // @[PMP.scala:185:8] wire _res_T_314_cfg_w = 1'h0; // @[PMP.scala:185:8] wire _res_T_314_cfg_r = 1'h0; // @[PMP.scala:185:8] wire _res_hit_T_91 = 1'h0; // @[PMP.scala:45:20] wire _res_hit_T_93 = 1'h0; // @[PMP.scala:46:26] wire res_hit_msbsLess_14 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_14 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_97 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_98 = 1'h0; // @[PMP.scala:83:16] wire res_hit_msbsLess_15 = 1'h0; // @[PMP.scala:80:39] wire res_hit_lsbsLess_15 = 1'h0; // @[PMP.scala:82:53] wire _res_hit_T_100 = 1'h0; // @[PMP.scala:83:30] wire _res_hit_T_101 = 1'h0; // @[PMP.scala:83:16] wire _res_hit_T_102 = 1'h0; // @[PMP.scala:94:48] wire _res_hit_T_103 = 1'h0; // @[PMP.scala:132:61] wire res_hit_7 = 1'h0; // @[PMP.scala:132:8] wire res_ignore_7 = 1'h0; // @[PMP.scala:164:26] wire _res_aligned_straddlesLowerBound_T_135 = 1'h0; // @[PMP.scala:123:147] wire res_aligned_straddlesLowerBound_7 = 1'h0; // @[PMP.scala:123:90] wire _res_aligned_straddlesUpperBound_T_135 = 1'h0; // @[PMP.scala:124:148] wire res_aligned_straddlesUpperBound_7 = 1'h0; // @[PMP.scala:124:85] wire _res_aligned_rangeAligned_T_7 = 1'h0; // @[PMP.scala:125:46] wire _res_aligned_T_7 = 1'h0; // @[PMP.scala:45:20] wire _res_T_316 = 1'h0; // @[PMP.scala:168:32] wire _res_T_317 = 1'h0; // @[PMP.scala:168:32] wire _res_T_318 = 1'h0; // @[PMP.scala:168:32] wire _res_T_319 = 1'h0; // @[PMP.scala:170:30] wire _res_T_323 = 1'h0; // @[PMP.scala:174:60] wire _res_T_325 = 1'h0; // @[PMP.scala:174:60] wire _res_T_327 = 1'h0; // @[PMP.scala:174:60] wire _res_T_329 = 1'h0; // @[PMP.scala:174:60] wire _res_T_331 = 1'h0; // @[PMP.scala:174:60] wire _res_T_333 = 1'h0; // @[PMP.scala:177:30] wire _res_T_334 = 1'h0; // @[PMP.scala:177:37] wire _res_T_335 = 1'h0; // @[PMP.scala:177:61] wire _res_T_336 = 1'h0; // @[PMP.scala:177:48] wire _res_T_337 = 1'h0; // @[PMP.scala:178:32] wire _res_T_338 = 1'h0; // @[PMP.scala:178:39] wire _res_T_339 = 1'h0; // @[PMP.scala:178:63] wire _res_T_340 = 1'h0; // @[PMP.scala:178:50] wire _res_T_342 = 1'h0; // @[PMP.scala:177:30] wire _res_T_343 = 1'h0; // @[PMP.scala:177:37] wire _res_T_344 = 1'h0; // @[PMP.scala:177:61] wire _res_T_345 = 1'h0; // @[PMP.scala:177:48] wire _res_T_346 = 1'h0; // @[PMP.scala:178:32] wire _res_T_347 = 1'h0; // @[PMP.scala:178:39] wire _res_T_348 = 1'h0; // @[PMP.scala:178:63] wire _res_T_349 = 1'h0; // @[PMP.scala:178:50] wire _res_T_351 = 1'h0; // @[PMP.scala:177:30] wire _res_T_352 = 1'h0; // @[PMP.scala:177:37] wire _res_T_353 = 1'h0; // @[PMP.scala:177:61] wire _res_T_354 = 1'h0; // @[PMP.scala:177:48] wire _res_T_355 = 1'h0; // @[PMP.scala:178:32] wire _res_T_356 = 1'h0; // @[PMP.scala:178:39] wire _res_T_357 = 1'h0; // @[PMP.scala:178:63] wire _res_T_358 = 1'h0; // @[PMP.scala:178:50] wire res_cur_7_cfg_l = 1'h0; // @[PMP.scala:181:23] wire res_cur_7_cfg_x = 1'h0; // @[PMP.scala:181:23] wire res_cur_7_cfg_w = 1'h0; // @[PMP.scala:181:23] wire res_cur_7_cfg_r = 1'h0; // @[PMP.scala:181:23] wire _res_cur_cfg_r_T_14 = 1'h0; // @[PMP.scala:182:40] wire _res_cur_cfg_r_T_15 = 1'h0; // @[PMP.scala:182:26] wire _res_cur_cfg_w_T_14 = 1'h0; // @[PMP.scala:183:40] wire _res_cur_cfg_w_T_15 = 1'h0; // @[PMP.scala:183:26] wire _res_cur_cfg_x_T_14 = 1'h0; // @[PMP.scala:184:40] wire _res_cur_cfg_x_T_15 = 1'h0; // @[PMP.scala:184:26] wire res_cfg_l = 1'h0; // @[PMP.scala:185:8] wire res_cfg_x = 1'h0; // @[PMP.scala:185:8] wire res_cfg_w = 1'h0; // @[PMP.scala:185:8] wire res_cfg_r = 1'h0; // @[PMP.scala:185:8] wire [1:0] io_prv = 2'h1; // @[PMP.scala:143:7, :146:14] wire [5:0] _GEN = 6'h7 << io_size_0; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T; // @[package.scala:243:71] assign _res_hit_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_3; // @[package.scala:243:71] assign _res_hit_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T; // @[package.scala:243:71] assign _res_aligned_lsbMask_T = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_3; // @[package.scala:243:71] assign _res_hit_lsbMask_T_3 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_16; // @[package.scala:243:71] assign _res_hit_T_16 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_2; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_2 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_6; // @[package.scala:243:71] assign _res_hit_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_29; // @[package.scala:243:71] assign _res_hit_T_29 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_4; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_4 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_9; // @[package.scala:243:71] assign _res_hit_lsbMask_T_9 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_42; // @[package.scala:243:71] assign _res_hit_T_42 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_6; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_6 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_12; // @[package.scala:243:71] assign _res_hit_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_55; // @[package.scala:243:71] assign _res_hit_T_55 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_8; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_8 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_15; // @[package.scala:243:71] assign _res_hit_lsbMask_T_15 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_68; // @[package.scala:243:71] assign _res_hit_T_68 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_10; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_10 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_18; // @[package.scala:243:71] assign _res_hit_lsbMask_T_18 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_81; // @[package.scala:243:71] assign _res_hit_T_81 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_12; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_12 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_lsbMask_T_21; // @[package.scala:243:71] assign _res_hit_lsbMask_T_21 = _GEN; // @[package.scala:243:71] wire [5:0] _res_hit_T_94; // @[package.scala:243:71] assign _res_hit_T_94 = _GEN; // @[package.scala:243:71] wire [5:0] _res_aligned_lsbMask_T_14; // @[package.scala:243:71] assign _res_aligned_lsbMask_T_14 = _GEN; // @[package.scala:243:71] wire [2:0] _res_hit_lsbMask_T_1 = _res_hit_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_2 = ~_res_hit_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [31:0] res_hit_lsbMask = {29'h0, _res_hit_lsbMask_T_2}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_6 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_7 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_10 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_12 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_14 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_18 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_21 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_17 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_20 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_24 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_28 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_35 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_34 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_30 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_36 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_42 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_49 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_51 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_40 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_48 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_56 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_54 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_63 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_68 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_50 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_66 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_77 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_85 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_60 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_72 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_78 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_91 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_102 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_70 = io_addr_0[31:3]; // @[PMP.scala:69:29, :143:7] wire [28:0] _res_hit_msbsLess_T_84 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_98 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_hit_msbsLess_T_90 = io_addr_0[31:3]; // @[PMP.scala:69:29, :80:25, :143:7] wire [28:0] _res_hit_msbsEqual_T_105 = io_addr_0[31:3]; // @[PMP.scala:69:29, :81:27, :143:7] wire [28:0] _res_aligned_straddlesLowerBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :123:35, :143:7] wire [28:0] _res_aligned_straddlesUpperBound_T_119 = io_addr_0[31:3]; // @[PMP.scala:69:29, :124:35, :143:7] wire [28:0] _res_hit_msbMatch_T_7 = _res_hit_msbMatch_T; // @[PMP.scala:63:47, :69:29] wire [28:0] _res_hit_msbMatch_T_9 = _res_hit_msbMatch_T_7; // @[PMP.scala:63:{47,52}] wire res_hit_msbMatch = _res_hit_msbMatch_T_9 == 29'h0; // @[PMP.scala:63:{52,58}, :68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [2:0] _res_hit_lsbMatch_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_7 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_13 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_10 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_14 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_21 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_20 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_28 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_35 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_47 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_30 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_42 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_49 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_64 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_40 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_56 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_63 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_81 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_50 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_77 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_60 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_84 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_91 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_115 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_70 = io_addr_0[2:0]; // @[PMP.scala:70:28, :143:7] wire [2:0] _res_hit_lsbsLess_T_98 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_hit_lsbsLess_T_105 = io_addr_0[2:0]; // @[PMP.scala:70:28, :82:25, :143:7] wire [2:0] _res_aligned_straddlesLowerBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :123:129, :143:7] wire [2:0] _res_aligned_straddlesUpperBound_T_132 = io_addr_0[2:0]; // @[PMP.scala:70:28, :124:119, :143:7] wire [2:0] _res_hit_lsbMatch_T_7 = _res_hit_lsbMatch_T; // @[PMP.scala:63:47, :70:28] wire [2:0] _res_hit_lsbMatch_T_6 = res_hit_lsbMask[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_8 = ~_res_hit_lsbMatch_T_6; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_9 = _res_hit_lsbMatch_T_7 & _res_hit_lsbMatch_T_8; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch = _res_hit_lsbMatch_T_9 == 3'h0; // @[PMP.scala:63:{52,58}, :68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire _res_hit_T_1 = res_hit_msbMatch & res_hit_lsbMatch; // @[PMP.scala:63:58, :71:16] wire [2:0] _res_hit_T_4 = _res_hit_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_5 = ~_res_hit_T_4; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_6 = _res_hit_msbsEqual_T; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual = _res_hit_msbsEqual_T_6 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_1 = _res_hit_lsbsLess_T | _res_hit_T_5; // @[package.scala:243:46] wire [28:0] _res_hit_msbsEqual_T_13 = _res_hit_msbsEqual_T_7; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_1 = _res_hit_msbsEqual_T_13 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_8 = _res_hit_lsbsLess_T_7; // @[PMP.scala:82:{25,42}] wire [2:0] _res_aligned_lsbMask_T_1 = _res_aligned_lsbMask_T[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask = ~_res_aligned_lsbMask_T_1; // @[package.scala:243:{46,76}] wire [2:0] _res_aligned_pow2Aligned_T_2 = res_aligned_lsbMask; // @[package.scala:243:46] wire [28:0] _res_aligned_straddlesLowerBound_T_6 = _res_aligned_straddlesLowerBound_T; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_7 = _res_aligned_straddlesLowerBound_T_6 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:{49,67,82}, :124:62] wire [2:0] _res_aligned_straddlesLowerBound_T_14 = ~_res_aligned_straddlesLowerBound_T_13; // @[PMP.scala:123:{127,129}] wire [28:0] _res_aligned_straddlesUpperBound_T_6 = _res_aligned_straddlesUpperBound_T; // @[PMP.scala:124:{35,49}] wire _res_aligned_straddlesUpperBound_T_7 = _res_aligned_straddlesUpperBound_T_6 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:{49,62,77}] wire [2:0] _res_aligned_straddlesUpperBound_T_14 = _res_aligned_straddlesUpperBound_T_13 | res_aligned_lsbMask; // @[package.scala:243:46] wire res_aligned_pow2Aligned = _res_aligned_pow2Aligned_T_2 == 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:{32,39,57}, :174:26] wire [2:0] _res_hit_lsbMask_T_4 = _res_hit_lsbMask_T_3[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_5 = ~_res_hit_lsbMask_T_4; // @[package.scala:243:{46,76}] wire [31:0] res_hit_lsbMask_1 = {29'h0, _res_hit_lsbMask_T_5}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T_17 = _res_hit_msbMatch_T_10; // @[PMP.scala:63:47, :69:29] wire [28:0] _res_hit_msbMatch_T_19 = _res_hit_msbMatch_T_17; // @[PMP.scala:63:{47,52}] wire res_hit_msbMatch_1 = _res_hit_msbMatch_T_19 == 29'h0; // @[PMP.scala:63:{52,58}, :68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [2:0] _res_hit_lsbMatch_T_17 = _res_hit_lsbMatch_T_10; // @[PMP.scala:63:47, :70:28] wire [2:0] _res_hit_lsbMatch_T_16 = res_hit_lsbMask_1[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_18 = ~_res_hit_lsbMatch_T_16; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_19 = _res_hit_lsbMatch_T_17 & _res_hit_lsbMatch_T_18; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_1 = _res_hit_lsbMatch_T_19 == 3'h0; // @[PMP.scala:63:{52,58}, :68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire _res_hit_T_14 = res_hit_msbMatch_1 & res_hit_lsbMatch_1; // @[PMP.scala:63:58, :71:16] wire [2:0] _res_hit_T_17 = _res_hit_T_16[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_18 = ~_res_hit_T_17; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_20 = _res_hit_msbsEqual_T_14; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_2 = _res_hit_msbsEqual_T_20 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_15 = _res_hit_lsbsLess_T_14 | _res_hit_T_18; // @[package.scala:243:46] wire [28:0] _res_hit_msbsEqual_T_27 = _res_hit_msbsEqual_T_21; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_3 = _res_hit_msbsEqual_T_27 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_22 = _res_hit_lsbsLess_T_21; // @[PMP.scala:82:{25,42}] wire [2:0] _res_aligned_lsbMask_T_3 = _res_aligned_lsbMask_T_2[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_1 = ~_res_aligned_lsbMask_T_3; // @[package.scala:243:{46,76}] wire [2:0] _res_aligned_pow2Aligned_T_5 = res_aligned_lsbMask_1; // @[package.scala:243:46] wire [28:0] _res_aligned_straddlesLowerBound_T_23 = _res_aligned_straddlesLowerBound_T_17; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_24 = _res_aligned_straddlesLowerBound_T_23 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:{49,67,82}, :124:62] wire [2:0] _res_aligned_straddlesLowerBound_T_31 = ~_res_aligned_straddlesLowerBound_T_30; // @[PMP.scala:123:{127,129}] wire [28:0] _res_aligned_straddlesUpperBound_T_23 = _res_aligned_straddlesUpperBound_T_17; // @[PMP.scala:124:{35,49}] wire _res_aligned_straddlesUpperBound_T_24 = _res_aligned_straddlesUpperBound_T_23 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:{49,62,77}] wire [2:0] _res_aligned_straddlesUpperBound_T_31 = _res_aligned_straddlesUpperBound_T_30 | res_aligned_lsbMask_1; // @[package.scala:243:46] wire res_aligned_pow2Aligned_1 = _res_aligned_pow2Aligned_T_5 == 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:{32,39,57}, :174:26] wire [2:0] _res_hit_lsbMask_T_7 = _res_hit_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_8 = ~_res_hit_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [31:0] res_hit_lsbMask_2 = {29'h0, _res_hit_lsbMask_T_8}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T_27 = _res_hit_msbMatch_T_20; // @[PMP.scala:63:47, :69:29] wire [28:0] _res_hit_msbMatch_T_29 = _res_hit_msbMatch_T_27; // @[PMP.scala:63:{47,52}] wire res_hit_msbMatch_2 = _res_hit_msbMatch_T_29 == 29'h0; // @[PMP.scala:63:{52,58}, :68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [2:0] _res_hit_lsbMatch_T_27 = _res_hit_lsbMatch_T_20; // @[PMP.scala:63:47, :70:28] wire [2:0] _res_hit_lsbMatch_T_26 = res_hit_lsbMask_2[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_28 = ~_res_hit_lsbMatch_T_26; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_29 = _res_hit_lsbMatch_T_27 & _res_hit_lsbMatch_T_28; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_2 = _res_hit_lsbMatch_T_29 == 3'h0; // @[PMP.scala:63:{52,58}, :68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire _res_hit_T_27 = res_hit_msbMatch_2 & res_hit_lsbMatch_2; // @[PMP.scala:63:58, :71:16] wire [2:0] _res_hit_T_30 = _res_hit_T_29[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_31 = ~_res_hit_T_30; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_34 = _res_hit_msbsEqual_T_28; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_4 = _res_hit_msbsEqual_T_34 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_29 = _res_hit_lsbsLess_T_28 | _res_hit_T_31; // @[package.scala:243:46] wire [28:0] _res_hit_msbsEqual_T_41 = _res_hit_msbsEqual_T_35; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_5 = _res_hit_msbsEqual_T_41 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_36 = _res_hit_lsbsLess_T_35; // @[PMP.scala:82:{25,42}] wire [2:0] _res_aligned_lsbMask_T_5 = _res_aligned_lsbMask_T_4[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_2 = ~_res_aligned_lsbMask_T_5; // @[package.scala:243:{46,76}] wire [2:0] _res_aligned_pow2Aligned_T_8 = res_aligned_lsbMask_2; // @[package.scala:243:46] wire [28:0] _res_aligned_straddlesLowerBound_T_40 = _res_aligned_straddlesLowerBound_T_34; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_41 = _res_aligned_straddlesLowerBound_T_40 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:{49,67,82}, :124:62] wire [2:0] _res_aligned_straddlesLowerBound_T_48 = ~_res_aligned_straddlesLowerBound_T_47; // @[PMP.scala:123:{127,129}] wire [28:0] _res_aligned_straddlesUpperBound_T_40 = _res_aligned_straddlesUpperBound_T_34; // @[PMP.scala:124:{35,49}] wire _res_aligned_straddlesUpperBound_T_41 = _res_aligned_straddlesUpperBound_T_40 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:{49,62,77}] wire [2:0] _res_aligned_straddlesUpperBound_T_48 = _res_aligned_straddlesUpperBound_T_47 | res_aligned_lsbMask_2; // @[package.scala:243:46] wire res_aligned_pow2Aligned_2 = _res_aligned_pow2Aligned_T_8 == 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:{32,39,57}, :174:26] wire [2:0] _res_hit_lsbMask_T_10 = _res_hit_lsbMask_T_9[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_11 = ~_res_hit_lsbMask_T_10; // @[package.scala:243:{46,76}] wire [31:0] res_hit_lsbMask_3 = {29'h0, _res_hit_lsbMask_T_11}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T_37 = _res_hit_msbMatch_T_30; // @[PMP.scala:63:47, :69:29] wire [28:0] _res_hit_msbMatch_T_39 = _res_hit_msbMatch_T_37; // @[PMP.scala:63:{47,52}] wire res_hit_msbMatch_3 = _res_hit_msbMatch_T_39 == 29'h0; // @[PMP.scala:63:{52,58}, :68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [2:0] _res_hit_lsbMatch_T_37 = _res_hit_lsbMatch_T_30; // @[PMP.scala:63:47, :70:28] wire [2:0] _res_hit_lsbMatch_T_36 = res_hit_lsbMask_3[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_38 = ~_res_hit_lsbMatch_T_36; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_39 = _res_hit_lsbMatch_T_37 & _res_hit_lsbMatch_T_38; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_3 = _res_hit_lsbMatch_T_39 == 3'h0; // @[PMP.scala:63:{52,58}, :68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire _res_hit_T_40 = res_hit_msbMatch_3 & res_hit_lsbMatch_3; // @[PMP.scala:63:58, :71:16] wire [2:0] _res_hit_T_43 = _res_hit_T_42[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_44 = ~_res_hit_T_43; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_48 = _res_hit_msbsEqual_T_42; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_6 = _res_hit_msbsEqual_T_48 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_43 = _res_hit_lsbsLess_T_42 | _res_hit_T_44; // @[package.scala:243:46] wire [28:0] _res_hit_msbsEqual_T_55 = _res_hit_msbsEqual_T_49; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_7 = _res_hit_msbsEqual_T_55 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_50 = _res_hit_lsbsLess_T_49; // @[PMP.scala:82:{25,42}] wire [2:0] _res_aligned_lsbMask_T_7 = _res_aligned_lsbMask_T_6[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_3 = ~_res_aligned_lsbMask_T_7; // @[package.scala:243:{46,76}] wire [2:0] _res_aligned_pow2Aligned_T_11 = res_aligned_lsbMask_3; // @[package.scala:243:46] wire [28:0] _res_aligned_straddlesLowerBound_T_57 = _res_aligned_straddlesLowerBound_T_51; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_58 = _res_aligned_straddlesLowerBound_T_57 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:{49,67,82}, :124:62] wire [2:0] _res_aligned_straddlesLowerBound_T_65 = ~_res_aligned_straddlesLowerBound_T_64; // @[PMP.scala:123:{127,129}] wire [28:0] _res_aligned_straddlesUpperBound_T_57 = _res_aligned_straddlesUpperBound_T_51; // @[PMP.scala:124:{35,49}] wire _res_aligned_straddlesUpperBound_T_58 = _res_aligned_straddlesUpperBound_T_57 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:{49,62,77}] wire [2:0] _res_aligned_straddlesUpperBound_T_65 = _res_aligned_straddlesUpperBound_T_64 | res_aligned_lsbMask_3; // @[package.scala:243:46] wire res_aligned_pow2Aligned_3 = _res_aligned_pow2Aligned_T_11 == 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:{32,39,57}, :174:26] wire [2:0] _res_hit_lsbMask_T_13 = _res_hit_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_14 = ~_res_hit_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [31:0] res_hit_lsbMask_4 = {29'h0, _res_hit_lsbMask_T_14}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T_47 = _res_hit_msbMatch_T_40; // @[PMP.scala:63:47, :69:29] wire [28:0] _res_hit_msbMatch_T_49 = _res_hit_msbMatch_T_47; // @[PMP.scala:63:{47,52}] wire res_hit_msbMatch_4 = _res_hit_msbMatch_T_49 == 29'h0; // @[PMP.scala:63:{52,58}, :68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [2:0] _res_hit_lsbMatch_T_47 = _res_hit_lsbMatch_T_40; // @[PMP.scala:63:47, :70:28] wire [2:0] _res_hit_lsbMatch_T_46 = res_hit_lsbMask_4[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_48 = ~_res_hit_lsbMatch_T_46; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_49 = _res_hit_lsbMatch_T_47 & _res_hit_lsbMatch_T_48; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_4 = _res_hit_lsbMatch_T_49 == 3'h0; // @[PMP.scala:63:{52,58}, :68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire _res_hit_T_53 = res_hit_msbMatch_4 & res_hit_lsbMatch_4; // @[PMP.scala:63:58, :71:16] wire [2:0] _res_hit_T_56 = _res_hit_T_55[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_57 = ~_res_hit_T_56; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_62 = _res_hit_msbsEqual_T_56; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_8 = _res_hit_msbsEqual_T_62 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_57 = _res_hit_lsbsLess_T_56 | _res_hit_T_57; // @[package.scala:243:46] wire [28:0] _res_hit_msbsEqual_T_69 = _res_hit_msbsEqual_T_63; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_9 = _res_hit_msbsEqual_T_69 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_64 = _res_hit_lsbsLess_T_63; // @[PMP.scala:82:{25,42}] wire [2:0] _res_aligned_lsbMask_T_9 = _res_aligned_lsbMask_T_8[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_4 = ~_res_aligned_lsbMask_T_9; // @[package.scala:243:{46,76}] wire [2:0] _res_aligned_pow2Aligned_T_14 = res_aligned_lsbMask_4; // @[package.scala:243:46] wire [28:0] _res_aligned_straddlesLowerBound_T_74 = _res_aligned_straddlesLowerBound_T_68; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_75 = _res_aligned_straddlesLowerBound_T_74 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:{49,67,82}, :124:62] wire [2:0] _res_aligned_straddlesLowerBound_T_82 = ~_res_aligned_straddlesLowerBound_T_81; // @[PMP.scala:123:{127,129}] wire [28:0] _res_aligned_straddlesUpperBound_T_74 = _res_aligned_straddlesUpperBound_T_68; // @[PMP.scala:124:{35,49}] wire _res_aligned_straddlesUpperBound_T_75 = _res_aligned_straddlesUpperBound_T_74 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:{49,62,77}] wire [2:0] _res_aligned_straddlesUpperBound_T_82 = _res_aligned_straddlesUpperBound_T_81 | res_aligned_lsbMask_4; // @[package.scala:243:46] wire res_aligned_pow2Aligned_4 = _res_aligned_pow2Aligned_T_14 == 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:{32,39,57}, :174:26] wire [2:0] _res_hit_lsbMask_T_16 = _res_hit_lsbMask_T_15[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_17 = ~_res_hit_lsbMask_T_16; // @[package.scala:243:{46,76}] wire [31:0] res_hit_lsbMask_5 = {29'h0, _res_hit_lsbMask_T_17}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T_57 = _res_hit_msbMatch_T_50; // @[PMP.scala:63:47, :69:29] wire [28:0] _res_hit_msbMatch_T_59 = _res_hit_msbMatch_T_57; // @[PMP.scala:63:{47,52}] wire res_hit_msbMatch_5 = _res_hit_msbMatch_T_59 == 29'h0; // @[PMP.scala:63:{52,58}, :68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [2:0] _res_hit_lsbMatch_T_57 = _res_hit_lsbMatch_T_50; // @[PMP.scala:63:47, :70:28] wire [2:0] _res_hit_lsbMatch_T_56 = res_hit_lsbMask_5[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_58 = ~_res_hit_lsbMatch_T_56; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_59 = _res_hit_lsbMatch_T_57 & _res_hit_lsbMatch_T_58; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_5 = _res_hit_lsbMatch_T_59 == 3'h0; // @[PMP.scala:63:{52,58}, :68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire _res_hit_T_66 = res_hit_msbMatch_5 & res_hit_lsbMatch_5; // @[PMP.scala:63:58, :71:16] wire [2:0] _res_hit_T_69 = _res_hit_T_68[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_70 = ~_res_hit_T_69; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_76 = _res_hit_msbsEqual_T_70; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_10 = _res_hit_msbsEqual_T_76 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_71 = _res_hit_lsbsLess_T_70 | _res_hit_T_70; // @[package.scala:243:46] wire [28:0] _res_hit_msbsEqual_T_83 = _res_hit_msbsEqual_T_77; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_11 = _res_hit_msbsEqual_T_83 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_78 = _res_hit_lsbsLess_T_77; // @[PMP.scala:82:{25,42}] wire [2:0] _res_aligned_lsbMask_T_11 = _res_aligned_lsbMask_T_10[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_5 = ~_res_aligned_lsbMask_T_11; // @[package.scala:243:{46,76}] wire [2:0] _res_aligned_pow2Aligned_T_17 = res_aligned_lsbMask_5; // @[package.scala:243:46] wire [28:0] _res_aligned_straddlesLowerBound_T_91 = _res_aligned_straddlesLowerBound_T_85; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_92 = _res_aligned_straddlesLowerBound_T_91 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:{49,67,82}, :124:62] wire [2:0] _res_aligned_straddlesLowerBound_T_99 = ~_res_aligned_straddlesLowerBound_T_98; // @[PMP.scala:123:{127,129}] wire [28:0] _res_aligned_straddlesUpperBound_T_91 = _res_aligned_straddlesUpperBound_T_85; // @[PMP.scala:124:{35,49}] wire _res_aligned_straddlesUpperBound_T_92 = _res_aligned_straddlesUpperBound_T_91 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:{49,62,77}] wire [2:0] _res_aligned_straddlesUpperBound_T_99 = _res_aligned_straddlesUpperBound_T_98 | res_aligned_lsbMask_5; // @[package.scala:243:46] wire res_aligned_pow2Aligned_5 = _res_aligned_pow2Aligned_T_17 == 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:{32,39,57}, :174:26] wire [2:0] _res_hit_lsbMask_T_19 = _res_hit_lsbMask_T_18[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_20 = ~_res_hit_lsbMask_T_19; // @[package.scala:243:{46,76}] wire [31:0] res_hit_lsbMask_6 = {29'h0, _res_hit_lsbMask_T_20}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T_67 = _res_hit_msbMatch_T_60; // @[PMP.scala:63:47, :69:29] wire [28:0] _res_hit_msbMatch_T_69 = _res_hit_msbMatch_T_67; // @[PMP.scala:63:{47,52}] wire res_hit_msbMatch_6 = _res_hit_msbMatch_T_69 == 29'h0; // @[PMP.scala:63:{52,58}, :68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [2:0] _res_hit_lsbMatch_T_67 = _res_hit_lsbMatch_T_60; // @[PMP.scala:63:47, :70:28] wire [2:0] _res_hit_lsbMatch_T_66 = res_hit_lsbMask_6[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_68 = ~_res_hit_lsbMatch_T_66; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_69 = _res_hit_lsbMatch_T_67 & _res_hit_lsbMatch_T_68; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_6 = _res_hit_lsbMatch_T_69 == 3'h0; // @[PMP.scala:63:{52,58}, :68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire _res_hit_T_79 = res_hit_msbMatch_6 & res_hit_lsbMatch_6; // @[PMP.scala:63:58, :71:16] wire [2:0] _res_hit_T_82 = _res_hit_T_81[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_83 = ~_res_hit_T_82; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_90 = _res_hit_msbsEqual_T_84; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_12 = _res_hit_msbsEqual_T_90 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_85 = _res_hit_lsbsLess_T_84 | _res_hit_T_83; // @[package.scala:243:46] wire [28:0] _res_hit_msbsEqual_T_97 = _res_hit_msbsEqual_T_91; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_13 = _res_hit_msbsEqual_T_97 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_92 = _res_hit_lsbsLess_T_91; // @[PMP.scala:82:{25,42}] wire [2:0] _res_aligned_lsbMask_T_13 = _res_aligned_lsbMask_T_12[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_6 = ~_res_aligned_lsbMask_T_13; // @[package.scala:243:{46,76}] wire [2:0] _res_aligned_pow2Aligned_T_20 = res_aligned_lsbMask_6; // @[package.scala:243:46] wire [28:0] _res_aligned_straddlesLowerBound_T_108 = _res_aligned_straddlesLowerBound_T_102; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_109 = _res_aligned_straddlesLowerBound_T_108 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:{49,67,82}, :124:62] wire [2:0] _res_aligned_straddlesLowerBound_T_116 = ~_res_aligned_straddlesLowerBound_T_115; // @[PMP.scala:123:{127,129}] wire [28:0] _res_aligned_straddlesUpperBound_T_108 = _res_aligned_straddlesUpperBound_T_102; // @[PMP.scala:124:{35,49}] wire _res_aligned_straddlesUpperBound_T_109 = _res_aligned_straddlesUpperBound_T_108 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:{49,62,77}] wire [2:0] _res_aligned_straddlesUpperBound_T_116 = _res_aligned_straddlesUpperBound_T_115 | res_aligned_lsbMask_6; // @[package.scala:243:46] wire res_aligned_pow2Aligned_6 = _res_aligned_pow2Aligned_T_20 == 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:{32,39,57}, :174:26] wire [2:0] _res_hit_lsbMask_T_22 = _res_hit_lsbMask_T_21[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_lsbMask_T_23 = ~_res_hit_lsbMask_T_22; // @[package.scala:243:{46,76}] wire [31:0] res_hit_lsbMask_7 = {29'h0, _res_hit_lsbMask_T_23}; // @[package.scala:243:46] wire [28:0] _res_hit_msbMatch_T_77 = _res_hit_msbMatch_T_70; // @[PMP.scala:63:47, :69:29] wire [28:0] _res_hit_msbMatch_T_79 = _res_hit_msbMatch_T_77; // @[PMP.scala:63:{47,52}] wire res_hit_msbMatch_7 = _res_hit_msbMatch_T_79 == 29'h0; // @[PMP.scala:63:{52,58}, :68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:62] wire [2:0] _res_hit_lsbMatch_T_77 = _res_hit_lsbMatch_T_70; // @[PMP.scala:63:47, :70:28] wire [2:0] _res_hit_lsbMatch_T_76 = res_hit_lsbMask_7[2:0]; // @[PMP.scala:68:26, :70:80] wire [2:0] _res_hit_lsbMatch_T_78 = ~_res_hit_lsbMatch_T_76; // @[PMP.scala:63:54, :70:80] wire [2:0] _res_hit_lsbMatch_T_79 = _res_hit_lsbMatch_T_77 & _res_hit_lsbMatch_T_78; // @[PMP.scala:63:{47,52,54}] wire res_hit_lsbMatch_7 = _res_hit_lsbMatch_T_79 == 3'h0; // @[PMP.scala:63:{52,58}, :68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:39, :174:26] wire _res_hit_T_92 = res_hit_msbMatch_7 & res_hit_lsbMatch_7; // @[PMP.scala:63:58, :71:16] wire [2:0] _res_hit_T_95 = _res_hit_T_94[2:0]; // @[package.scala:243:{71,76}] wire [2:0] _res_hit_T_96 = ~_res_hit_T_95; // @[package.scala:243:{46,76}] wire [28:0] _res_hit_msbsEqual_T_104 = _res_hit_msbsEqual_T_98; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_14 = _res_hit_msbsEqual_T_104 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_99 = _res_hit_lsbsLess_T_98 | _res_hit_T_96; // @[package.scala:243:46] wire [28:0] _res_hit_msbsEqual_T_111 = _res_hit_msbsEqual_T_105; // @[PMP.scala:81:{27,41}] wire res_hit_msbsEqual_15 = _res_hit_msbsEqual_T_111 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:{41,54,69}, :123:67, :124:62] wire [2:0] _res_hit_lsbsLess_T_106 = _res_hit_lsbsLess_T_105; // @[PMP.scala:82:{25,42}] wire [2:0] _res_aligned_lsbMask_T_15 = _res_aligned_lsbMask_T_14[2:0]; // @[package.scala:243:{71,76}] wire [2:0] res_aligned_lsbMask_7 = ~_res_aligned_lsbMask_T_15; // @[package.scala:243:{46,76}] wire [2:0] _res_aligned_pow2Aligned_T_23 = res_aligned_lsbMask_7; // @[package.scala:243:46] wire [28:0] _res_aligned_straddlesLowerBound_T_125 = _res_aligned_straddlesLowerBound_T_119; // @[PMP.scala:123:{35,49}] wire _res_aligned_straddlesLowerBound_T_126 = _res_aligned_straddlesLowerBound_T_125 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:{49,67,82}, :124:62] wire [2:0] _res_aligned_straddlesLowerBound_T_133 = ~_res_aligned_straddlesLowerBound_T_132; // @[PMP.scala:123:{127,129}] wire [28:0] _res_aligned_straddlesUpperBound_T_125 = _res_aligned_straddlesUpperBound_T_119; // @[PMP.scala:124:{35,49}] wire _res_aligned_straddlesUpperBound_T_126 = _res_aligned_straddlesUpperBound_T_125 == 29'h0; // @[PMP.scala:68:26, :69:{53,72}, :80:52, :81:54, :123:67, :124:{49,62,77}] wire [2:0] _res_aligned_straddlesUpperBound_T_133 = _res_aligned_straddlesUpperBound_T_132 | res_aligned_lsbMask_7; // @[package.scala:243:46] wire res_aligned_pow2Aligned_7 = _res_aligned_pow2Aligned_T_23 == 3'h0; // @[PMP.scala:68:26, :70:55, :82:64, :123:{108,125}, :124:{98,115}, :126:{32,39,57}, :174:26] endmodule
Generate the Verilog code corresponding to this FIRRTL code module InclusiveCacheBankScheduler_2 : input clock : Clock input reset : Reset output io : { flip in : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, address : UInt<32>, mask : UInt<16>, data : UInt<128>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, address : UInt<32>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<6>, sink : UInt<4>, denied : UInt<1>, user : { }, echo : { }, data : UInt<128>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<4>}}}, out : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip b : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, address : UInt<32>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, c : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<4>, address : UInt<32>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<3>, source : UInt<4>, sink : UInt<3>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}, e : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<3>}}}, flip ways : UInt<16>[8], flip divs : UInt<11>[8], flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { address : UInt<32>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { fail : UInt<1>}}} inst sourceA of SourceA_2 connect sourceA.clock, clock connect sourceA.reset, reset inst sourceB of SourceB_2 connect sourceB.clock, clock connect sourceB.reset, reset inst sourceC of SourceC_2 connect sourceC.clock, clock connect sourceC.reset, reset inst sourceD of SourceD_2 connect sourceD.clock, clock connect sourceD.reset, reset inst sourceE of SourceE_2 connect sourceE.clock, clock connect sourceE.reset, reset inst sourceX of SourceX_2 connect sourceX.clock, clock connect sourceX.reset, reset connect io.out.a.bits, sourceA.io.a.bits connect io.out.a.valid, sourceA.io.a.valid connect sourceA.io.a.ready, io.out.a.ready connect io.out.c.bits, sourceC.io.c.bits connect io.out.c.valid, sourceC.io.c.valid connect sourceC.io.c.ready, io.out.c.ready connect io.out.e.bits, sourceE.io.e.bits connect io.out.e.valid, sourceE.io.e.valid connect sourceE.io.e.ready, io.out.e.ready connect io.in.b.bits, sourceB.io.b.bits connect io.in.b.valid, sourceB.io.b.valid connect sourceB.io.b.ready, io.in.b.ready connect io.in.d.bits, sourceD.io.d.bits connect io.in.d.valid, sourceD.io.d.valid connect sourceD.io.d.ready, io.in.d.ready connect io.resp.bits, sourceX.io.x.bits connect io.resp.valid, sourceX.io.x.valid connect sourceX.io.x.ready, io.resp.ready inst sinkA of SinkA_2 connect sinkA.clock, clock connect sinkA.reset, reset inst sinkC of SinkC_2 connect sinkC.clock, clock connect sinkC.reset, reset inst sinkD of SinkD_2 connect sinkD.clock, clock connect sinkD.reset, reset inst sinkE of SinkE_2 connect sinkE.clock, clock connect sinkE.reset, reset inst sinkX of SinkX_2 connect sinkX.clock, clock connect sinkX.reset, reset connect sinkA.io.a, io.in.a connect sinkC.io.c, io.in.c connect sinkE.io.e, io.in.e connect sinkD.io.d, io.out.d connect sinkX.io.x, io.req connect io.out.b.ready, UInt<1>(0h1) inst directory of Directory_2 connect directory.clock, clock connect directory.reset, reset inst bankedStore of BankedStore_2 connect bankedStore.clock, clock connect bankedStore.reset, reset inst requests of ListBuffer_QueuedRequest_q36_e28_2 connect requests.clock, clock connect requests.reset, reset inst mshrs_0 of MSHR_24 connect mshrs_0.clock, clock connect mshrs_0.reset, reset inst mshrs_1 of MSHR_25 connect mshrs_1.clock, clock connect mshrs_1.reset, reset inst mshrs_2 of MSHR_26 connect mshrs_2.clock, clock connect mshrs_2.reset, reset inst mshrs_3 of MSHR_27 connect mshrs_3.clock, clock connect mshrs_3.reset, reset inst mshrs_4 of MSHR_28 connect mshrs_4.clock, clock connect mshrs_4.reset, reset inst mshrs_5 of MSHR_29 connect mshrs_5.clock, clock connect mshrs_5.reset, reset inst mshrs_6 of MSHR_30 connect mshrs_6.clock, clock connect mshrs_6.reset, reset inst mshrs_7 of MSHR_31 connect mshrs_7.clock, clock connect mshrs_7.reset, reset inst mshrs_8 of MSHR_32 connect mshrs_8.clock, clock connect mshrs_8.reset, reset inst mshrs_9 of MSHR_33 connect mshrs_9.clock, clock connect mshrs_9.reset, reset inst mshrs_10 of MSHR_34 connect mshrs_10.clock, clock connect mshrs_10.reset, reset inst mshrs_11 of MSHR_35 connect mshrs_11.clock, clock connect mshrs_11.reset, reset wire nestedwb : { set : UInt<11>, tag : UInt<9>, b_toN : UInt<1>, b_toB : UInt<1>, b_clr_dirty : UInt<1>, c_set_dirty : UInt<1>} node _mshrs_0_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_0.io.status.bits.set) node _mshrs_0_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_0_io_sinkc_valid_T) connect mshrs_0.io.sinkc.valid, _mshrs_0_io_sinkc_valid_T_1 node _mshrs_0_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h0)) node _mshrs_0_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_0_io_sinkd_valid_T) connect mshrs_0.io.sinkd.valid, _mshrs_0_io_sinkd_valid_T_1 node _mshrs_0_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h0)) node _mshrs_0_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_0_io_sinke_valid_T) connect mshrs_0.io.sinke.valid, _mshrs_0_io_sinke_valid_T_1 connect mshrs_0.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_0.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_0.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_0.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_0.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_0.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_0.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_0.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_0.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_0.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_0.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_0.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_0.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_0.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_0.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_0.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_0.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_0.io.nestedwb.tag, nestedwb.tag connect mshrs_0.io.nestedwb.set, nestedwb.set node _mshrs_1_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_1.io.status.bits.set) node _mshrs_1_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_1_io_sinkc_valid_T) connect mshrs_1.io.sinkc.valid, _mshrs_1_io_sinkc_valid_T_1 node _mshrs_1_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<1>(0h1)) node _mshrs_1_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_1_io_sinkd_valid_T) connect mshrs_1.io.sinkd.valid, _mshrs_1_io_sinkd_valid_T_1 node _mshrs_1_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<1>(0h1)) node _mshrs_1_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_1_io_sinke_valid_T) connect mshrs_1.io.sinke.valid, _mshrs_1_io_sinke_valid_T_1 connect mshrs_1.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_1.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_1.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_1.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_1.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_1.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_1.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_1.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_1.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_1.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_1.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_1.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_1.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_1.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_1.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_1.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_1.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_1.io.nestedwb.tag, nestedwb.tag connect mshrs_1.io.nestedwb.set, nestedwb.set node _mshrs_2_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_2.io.status.bits.set) node _mshrs_2_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_2_io_sinkc_valid_T) connect mshrs_2.io.sinkc.valid, _mshrs_2_io_sinkc_valid_T_1 node _mshrs_2_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h2)) node _mshrs_2_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_2_io_sinkd_valid_T) connect mshrs_2.io.sinkd.valid, _mshrs_2_io_sinkd_valid_T_1 node _mshrs_2_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h2)) node _mshrs_2_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_2_io_sinke_valid_T) connect mshrs_2.io.sinke.valid, _mshrs_2_io_sinke_valid_T_1 connect mshrs_2.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_2.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_2.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_2.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_2.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_2.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_2.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_2.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_2.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_2.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_2.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_2.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_2.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_2.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_2.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_2.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_2.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_2.io.nestedwb.tag, nestedwb.tag connect mshrs_2.io.nestedwb.set, nestedwb.set node _mshrs_3_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_3.io.status.bits.set) node _mshrs_3_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_3_io_sinkc_valid_T) connect mshrs_3.io.sinkc.valid, _mshrs_3_io_sinkc_valid_T_1 node _mshrs_3_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<2>(0h3)) node _mshrs_3_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_3_io_sinkd_valid_T) connect mshrs_3.io.sinkd.valid, _mshrs_3_io_sinkd_valid_T_1 node _mshrs_3_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<2>(0h3)) node _mshrs_3_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_3_io_sinke_valid_T) connect mshrs_3.io.sinke.valid, _mshrs_3_io_sinke_valid_T_1 connect mshrs_3.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_3.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_3.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_3.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_3.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_3.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_3.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_3.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_3.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_3.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_3.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_3.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_3.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_3.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_3.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_3.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_3.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_3.io.nestedwb.tag, nestedwb.tag connect mshrs_3.io.nestedwb.set, nestedwb.set node _mshrs_4_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_4.io.status.bits.set) node _mshrs_4_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_4_io_sinkc_valid_T) connect mshrs_4.io.sinkc.valid, _mshrs_4_io_sinkc_valid_T_1 node _mshrs_4_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h4)) node _mshrs_4_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_4_io_sinkd_valid_T) connect mshrs_4.io.sinkd.valid, _mshrs_4_io_sinkd_valid_T_1 node _mshrs_4_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h4)) node _mshrs_4_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_4_io_sinke_valid_T) connect mshrs_4.io.sinke.valid, _mshrs_4_io_sinke_valid_T_1 connect mshrs_4.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_4.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_4.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_4.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_4.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_4.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_4.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_4.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_4.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_4.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_4.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_4.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_4.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_4.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_4.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_4.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_4.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_4.io.nestedwb.tag, nestedwb.tag connect mshrs_4.io.nestedwb.set, nestedwb.set node _mshrs_5_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_5.io.status.bits.set) node _mshrs_5_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_5_io_sinkc_valid_T) connect mshrs_5.io.sinkc.valid, _mshrs_5_io_sinkc_valid_T_1 node _mshrs_5_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h5)) node _mshrs_5_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_5_io_sinkd_valid_T) connect mshrs_5.io.sinkd.valid, _mshrs_5_io_sinkd_valid_T_1 node _mshrs_5_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h5)) node _mshrs_5_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_5_io_sinke_valid_T) connect mshrs_5.io.sinke.valid, _mshrs_5_io_sinke_valid_T_1 connect mshrs_5.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_5.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_5.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_5.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_5.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_5.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_5.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_5.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_5.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_5.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_5.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_5.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_5.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_5.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_5.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_5.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_5.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_5.io.nestedwb.tag, nestedwb.tag connect mshrs_5.io.nestedwb.set, nestedwb.set node _mshrs_6_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_6.io.status.bits.set) node _mshrs_6_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_6_io_sinkc_valid_T) connect mshrs_6.io.sinkc.valid, _mshrs_6_io_sinkc_valid_T_1 node _mshrs_6_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h6)) node _mshrs_6_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_6_io_sinkd_valid_T) connect mshrs_6.io.sinkd.valid, _mshrs_6_io_sinkd_valid_T_1 node _mshrs_6_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h6)) node _mshrs_6_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_6_io_sinke_valid_T) connect mshrs_6.io.sinke.valid, _mshrs_6_io_sinke_valid_T_1 connect mshrs_6.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_6.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_6.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_6.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_6.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_6.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_6.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_6.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_6.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_6.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_6.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_6.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_6.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_6.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_6.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_6.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_6.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_6.io.nestedwb.tag, nestedwb.tag connect mshrs_6.io.nestedwb.set, nestedwb.set node _mshrs_7_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_7.io.status.bits.set) node _mshrs_7_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_7_io_sinkc_valid_T) connect mshrs_7.io.sinkc.valid, _mshrs_7_io_sinkc_valid_T_1 node _mshrs_7_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<3>(0h7)) node _mshrs_7_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_7_io_sinkd_valid_T) connect mshrs_7.io.sinkd.valid, _mshrs_7_io_sinkd_valid_T_1 node _mshrs_7_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<3>(0h7)) node _mshrs_7_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_7_io_sinke_valid_T) connect mshrs_7.io.sinke.valid, _mshrs_7_io_sinke_valid_T_1 connect mshrs_7.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_7.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_7.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_7.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_7.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_7.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_7.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_7.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_7.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_7.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_7.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_7.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_7.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_7.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_7.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_7.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_7.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_7.io.nestedwb.tag, nestedwb.tag connect mshrs_7.io.nestedwb.set, nestedwb.set node _mshrs_8_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_8.io.status.bits.set) node _mshrs_8_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_8_io_sinkc_valid_T) connect mshrs_8.io.sinkc.valid, _mshrs_8_io_sinkc_valid_T_1 node _mshrs_8_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h8)) node _mshrs_8_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_8_io_sinkd_valid_T) connect mshrs_8.io.sinkd.valid, _mshrs_8_io_sinkd_valid_T_1 node _mshrs_8_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h8)) node _mshrs_8_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_8_io_sinke_valid_T) connect mshrs_8.io.sinke.valid, _mshrs_8_io_sinke_valid_T_1 connect mshrs_8.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_8.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_8.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_8.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_8.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_8.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_8.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_8.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_8.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_8.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_8.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_8.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_8.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_8.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_8.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_8.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_8.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_8.io.nestedwb.tag, nestedwb.tag connect mshrs_8.io.nestedwb.set, nestedwb.set node _mshrs_9_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_9.io.status.bits.set) node _mshrs_9_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_9_io_sinkc_valid_T) connect mshrs_9.io.sinkc.valid, _mshrs_9_io_sinkc_valid_T_1 node _mshrs_9_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0h9)) node _mshrs_9_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_9_io_sinkd_valid_T) connect mshrs_9.io.sinkd.valid, _mshrs_9_io_sinkd_valid_T_1 node _mshrs_9_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0h9)) node _mshrs_9_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_9_io_sinke_valid_T) connect mshrs_9.io.sinke.valid, _mshrs_9_io_sinke_valid_T_1 connect mshrs_9.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_9.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_9.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_9.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_9.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_9.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_9.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_9.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_9.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_9.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_9.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_9.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_9.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_9.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_9.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_9.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_9.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_9.io.nestedwb.tag, nestedwb.tag connect mshrs_9.io.nestedwb.set, nestedwb.set node _mshrs_10_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_10.io.status.bits.set) node _mshrs_10_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_10_io_sinkc_valid_T) connect mshrs_10.io.sinkc.valid, _mshrs_10_io_sinkc_valid_T_1 node _mshrs_10_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0ha)) node _mshrs_10_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_10_io_sinkd_valid_T) connect mshrs_10.io.sinkd.valid, _mshrs_10_io_sinkd_valid_T_1 node _mshrs_10_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0ha)) node _mshrs_10_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_10_io_sinke_valid_T) connect mshrs_10.io.sinke.valid, _mshrs_10_io_sinke_valid_T_1 connect mshrs_10.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_10.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_10.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_10.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_10.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_10.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_10.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_10.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_10.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_10.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_10.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_10.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_10.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_10.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_10.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_10.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_10.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_10.io.nestedwb.tag, nestedwb.tag connect mshrs_10.io.nestedwb.set, nestedwb.set node _mshrs_11_io_sinkc_valid_T = eq(sinkC.io.resp.bits.set, mshrs_11.io.status.bits.set) node _mshrs_11_io_sinkc_valid_T_1 = and(sinkC.io.resp.valid, _mshrs_11_io_sinkc_valid_T) connect mshrs_11.io.sinkc.valid, _mshrs_11_io_sinkc_valid_T_1 node _mshrs_11_io_sinkd_valid_T = eq(sinkD.io.resp.bits.source, UInt<4>(0hb)) node _mshrs_11_io_sinkd_valid_T_1 = and(sinkD.io.resp.valid, _mshrs_11_io_sinkd_valid_T) connect mshrs_11.io.sinkd.valid, _mshrs_11_io_sinkd_valid_T_1 node _mshrs_11_io_sinke_valid_T = eq(sinkE.io.resp.bits.sink, UInt<4>(0hb)) node _mshrs_11_io_sinke_valid_T_1 = and(sinkE.io.resp.valid, _mshrs_11_io_sinke_valid_T) connect mshrs_11.io.sinke.valid, _mshrs_11_io_sinke_valid_T_1 connect mshrs_11.io.sinkc.bits.data, sinkC.io.resp.bits.data connect mshrs_11.io.sinkc.bits.param, sinkC.io.resp.bits.param connect mshrs_11.io.sinkc.bits.source, sinkC.io.resp.bits.source connect mshrs_11.io.sinkc.bits.tag, sinkC.io.resp.bits.tag connect mshrs_11.io.sinkc.bits.set, sinkC.io.resp.bits.set connect mshrs_11.io.sinkc.bits.last, sinkC.io.resp.bits.last connect mshrs_11.io.sinkd.bits.denied, sinkD.io.resp.bits.denied connect mshrs_11.io.sinkd.bits.sink, sinkD.io.resp.bits.sink connect mshrs_11.io.sinkd.bits.source, sinkD.io.resp.bits.source connect mshrs_11.io.sinkd.bits.param, sinkD.io.resp.bits.param connect mshrs_11.io.sinkd.bits.opcode, sinkD.io.resp.bits.opcode connect mshrs_11.io.sinkd.bits.last, sinkD.io.resp.bits.last connect mshrs_11.io.sinke.bits.sink, sinkE.io.resp.bits.sink connect mshrs_11.io.nestedwb.c_set_dirty, nestedwb.c_set_dirty connect mshrs_11.io.nestedwb.b_clr_dirty, nestedwb.b_clr_dirty connect mshrs_11.io.nestedwb.b_toB, nestedwb.b_toB connect mshrs_11.io.nestedwb.b_toN, nestedwb.b_toN connect mshrs_11.io.nestedwb.tag, nestedwb.tag connect mshrs_11.io.nestedwb.set, nestedwb.set node _mshr_stall_abc_T = eq(mshrs_0.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_1 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T) node _mshr_stall_abc_T_2 = eq(mshrs_0.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_3 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_2) node mshr_stall_abc_0 = or(_mshr_stall_abc_T_1, _mshr_stall_abc_T_3) node _mshr_stall_abc_T_4 = eq(mshrs_1.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_5 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_4) node _mshr_stall_abc_T_6 = eq(mshrs_1.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_7 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_6) node mshr_stall_abc_1 = or(_mshr_stall_abc_T_5, _mshr_stall_abc_T_7) node _mshr_stall_abc_T_8 = eq(mshrs_2.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_9 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_8) node _mshr_stall_abc_T_10 = eq(mshrs_2.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_11 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_10) node mshr_stall_abc_2 = or(_mshr_stall_abc_T_9, _mshr_stall_abc_T_11) node _mshr_stall_abc_T_12 = eq(mshrs_3.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_13 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_12) node _mshr_stall_abc_T_14 = eq(mshrs_3.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_15 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_14) node mshr_stall_abc_3 = or(_mshr_stall_abc_T_13, _mshr_stall_abc_T_15) node _mshr_stall_abc_T_16 = eq(mshrs_4.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_17 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_16) node _mshr_stall_abc_T_18 = eq(mshrs_4.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_19 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_18) node mshr_stall_abc_4 = or(_mshr_stall_abc_T_17, _mshr_stall_abc_T_19) node _mshr_stall_abc_T_20 = eq(mshrs_5.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_21 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_20) node _mshr_stall_abc_T_22 = eq(mshrs_5.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_23 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_22) node mshr_stall_abc_5 = or(_mshr_stall_abc_T_21, _mshr_stall_abc_T_23) node _mshr_stall_abc_T_24 = eq(mshrs_6.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_25 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_24) node _mshr_stall_abc_T_26 = eq(mshrs_6.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_27 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_26) node mshr_stall_abc_6 = or(_mshr_stall_abc_T_25, _mshr_stall_abc_T_27) node _mshr_stall_abc_T_28 = eq(mshrs_7.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_29 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_28) node _mshr_stall_abc_T_30 = eq(mshrs_7.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_31 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_30) node mshr_stall_abc_7 = or(_mshr_stall_abc_T_29, _mshr_stall_abc_T_31) node _mshr_stall_abc_T_32 = eq(mshrs_8.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_33 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_32) node _mshr_stall_abc_T_34 = eq(mshrs_8.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_35 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_34) node mshr_stall_abc_8 = or(_mshr_stall_abc_T_33, _mshr_stall_abc_T_35) node _mshr_stall_abc_T_36 = eq(mshrs_9.io.status.bits.set, mshrs_10.io.status.bits.set) node _mshr_stall_abc_T_37 = and(mshrs_10.io.status.valid, _mshr_stall_abc_T_36) node _mshr_stall_abc_T_38 = eq(mshrs_9.io.status.bits.set, mshrs_11.io.status.bits.set) node _mshr_stall_abc_T_39 = and(mshrs_11.io.status.valid, _mshr_stall_abc_T_38) node mshr_stall_abc_9 = or(_mshr_stall_abc_T_37, _mshr_stall_abc_T_39) node _mshr_stall_bc_T = eq(mshrs_10.io.status.bits.set, mshrs_11.io.status.bits.set) node mshr_stall_bc = and(mshrs_11.io.status.valid, _mshr_stall_bc_T) node stall_abc_0 = and(mshr_stall_abc_0, mshrs_0.io.status.valid) node stall_abc_1 = and(mshr_stall_abc_1, mshrs_1.io.status.valid) node stall_abc_2 = and(mshr_stall_abc_2, mshrs_2.io.status.valid) node stall_abc_3 = and(mshr_stall_abc_3, mshrs_3.io.status.valid) node stall_abc_4 = and(mshr_stall_abc_4, mshrs_4.io.status.valid) node stall_abc_5 = and(mshr_stall_abc_5, mshrs_5.io.status.valid) node stall_abc_6 = and(mshr_stall_abc_6, mshrs_6.io.status.valid) node stall_abc_7 = and(mshr_stall_abc_7, mshrs_7.io.status.valid) node stall_abc_8 = and(mshr_stall_abc_8, mshrs_8.io.status.valid) node stall_abc_9 = and(mshr_stall_abc_9, mshrs_9.io.status.valid) node _T = or(stall_abc_0, stall_abc_1) node _T_1 = or(_T, stall_abc_2) node _T_2 = or(_T_1, stall_abc_3) node _T_3 = or(_T_2, stall_abc_4) node _T_4 = or(_T_3, stall_abc_5) node _T_5 = or(_T_4, stall_abc_6) node _T_6 = or(_T_5, stall_abc_7) node _T_7 = or(_T_6, stall_abc_8) node _T_8 = or(_T_7, stall_abc_9) node _mshr_request_T = eq(mshr_stall_abc_0, UInt<1>(0h0)) node _mshr_request_T_1 = and(mshrs_0.io.schedule.valid, _mshr_request_T) node _mshr_request_T_2 = eq(mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_3 = or(sourceA.io.req.ready, _mshr_request_T_2) node _mshr_request_T_4 = and(_mshr_request_T_1, _mshr_request_T_3) node _mshr_request_T_5 = eq(mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_6 = or(sourceB.io.req.ready, _mshr_request_T_5) node _mshr_request_T_7 = and(_mshr_request_T_4, _mshr_request_T_6) node _mshr_request_T_8 = eq(mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_9 = or(sourceC.io.req.ready, _mshr_request_T_8) node _mshr_request_T_10 = and(_mshr_request_T_7, _mshr_request_T_9) node _mshr_request_T_11 = eq(mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_12 = or(sourceD.io.req.ready, _mshr_request_T_11) node _mshr_request_T_13 = and(_mshr_request_T_10, _mshr_request_T_12) node _mshr_request_T_14 = eq(mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_15 = or(sourceE.io.req.ready, _mshr_request_T_14) node _mshr_request_T_16 = and(_mshr_request_T_13, _mshr_request_T_15) node _mshr_request_T_17 = eq(mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_18 = or(sourceX.io.req.ready, _mshr_request_T_17) node _mshr_request_T_19 = and(_mshr_request_T_16, _mshr_request_T_18) node _mshr_request_T_20 = eq(mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_21 = or(directory.io.write.ready, _mshr_request_T_20) node _mshr_request_T_22 = and(_mshr_request_T_19, _mshr_request_T_21) node _mshr_request_T_23 = eq(mshr_stall_abc_1, UInt<1>(0h0)) node _mshr_request_T_24 = and(mshrs_1.io.schedule.valid, _mshr_request_T_23) node _mshr_request_T_25 = eq(mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_26 = or(sourceA.io.req.ready, _mshr_request_T_25) node _mshr_request_T_27 = and(_mshr_request_T_24, _mshr_request_T_26) node _mshr_request_T_28 = eq(mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_29 = or(sourceB.io.req.ready, _mshr_request_T_28) node _mshr_request_T_30 = and(_mshr_request_T_27, _mshr_request_T_29) node _mshr_request_T_31 = eq(mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_32 = or(sourceC.io.req.ready, _mshr_request_T_31) node _mshr_request_T_33 = and(_mshr_request_T_30, _mshr_request_T_32) node _mshr_request_T_34 = eq(mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_35 = or(sourceD.io.req.ready, _mshr_request_T_34) node _mshr_request_T_36 = and(_mshr_request_T_33, _mshr_request_T_35) node _mshr_request_T_37 = eq(mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_38 = or(sourceE.io.req.ready, _mshr_request_T_37) node _mshr_request_T_39 = and(_mshr_request_T_36, _mshr_request_T_38) node _mshr_request_T_40 = eq(mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_41 = or(sourceX.io.req.ready, _mshr_request_T_40) node _mshr_request_T_42 = and(_mshr_request_T_39, _mshr_request_T_41) node _mshr_request_T_43 = eq(mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_44 = or(directory.io.write.ready, _mshr_request_T_43) node _mshr_request_T_45 = and(_mshr_request_T_42, _mshr_request_T_44) node _mshr_request_T_46 = eq(mshr_stall_abc_2, UInt<1>(0h0)) node _mshr_request_T_47 = and(mshrs_2.io.schedule.valid, _mshr_request_T_46) node _mshr_request_T_48 = eq(mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_49 = or(sourceA.io.req.ready, _mshr_request_T_48) node _mshr_request_T_50 = and(_mshr_request_T_47, _mshr_request_T_49) node _mshr_request_T_51 = eq(mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_52 = or(sourceB.io.req.ready, _mshr_request_T_51) node _mshr_request_T_53 = and(_mshr_request_T_50, _mshr_request_T_52) node _mshr_request_T_54 = eq(mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_55 = or(sourceC.io.req.ready, _mshr_request_T_54) node _mshr_request_T_56 = and(_mshr_request_T_53, _mshr_request_T_55) node _mshr_request_T_57 = eq(mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_58 = or(sourceD.io.req.ready, _mshr_request_T_57) node _mshr_request_T_59 = and(_mshr_request_T_56, _mshr_request_T_58) node _mshr_request_T_60 = eq(mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_61 = or(sourceE.io.req.ready, _mshr_request_T_60) node _mshr_request_T_62 = and(_mshr_request_T_59, _mshr_request_T_61) node _mshr_request_T_63 = eq(mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_64 = or(sourceX.io.req.ready, _mshr_request_T_63) node _mshr_request_T_65 = and(_mshr_request_T_62, _mshr_request_T_64) node _mshr_request_T_66 = eq(mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_67 = or(directory.io.write.ready, _mshr_request_T_66) node _mshr_request_T_68 = and(_mshr_request_T_65, _mshr_request_T_67) node _mshr_request_T_69 = eq(mshr_stall_abc_3, UInt<1>(0h0)) node _mshr_request_T_70 = and(mshrs_3.io.schedule.valid, _mshr_request_T_69) node _mshr_request_T_71 = eq(mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_72 = or(sourceA.io.req.ready, _mshr_request_T_71) node _mshr_request_T_73 = and(_mshr_request_T_70, _mshr_request_T_72) node _mshr_request_T_74 = eq(mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_75 = or(sourceB.io.req.ready, _mshr_request_T_74) node _mshr_request_T_76 = and(_mshr_request_T_73, _mshr_request_T_75) node _mshr_request_T_77 = eq(mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_78 = or(sourceC.io.req.ready, _mshr_request_T_77) node _mshr_request_T_79 = and(_mshr_request_T_76, _mshr_request_T_78) node _mshr_request_T_80 = eq(mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_81 = or(sourceD.io.req.ready, _mshr_request_T_80) node _mshr_request_T_82 = and(_mshr_request_T_79, _mshr_request_T_81) node _mshr_request_T_83 = eq(mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_84 = or(sourceE.io.req.ready, _mshr_request_T_83) node _mshr_request_T_85 = and(_mshr_request_T_82, _mshr_request_T_84) node _mshr_request_T_86 = eq(mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_87 = or(sourceX.io.req.ready, _mshr_request_T_86) node _mshr_request_T_88 = and(_mshr_request_T_85, _mshr_request_T_87) node _mshr_request_T_89 = eq(mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_90 = or(directory.io.write.ready, _mshr_request_T_89) node _mshr_request_T_91 = and(_mshr_request_T_88, _mshr_request_T_90) node _mshr_request_T_92 = eq(mshr_stall_abc_4, UInt<1>(0h0)) node _mshr_request_T_93 = and(mshrs_4.io.schedule.valid, _mshr_request_T_92) node _mshr_request_T_94 = eq(mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_95 = or(sourceA.io.req.ready, _mshr_request_T_94) node _mshr_request_T_96 = and(_mshr_request_T_93, _mshr_request_T_95) node _mshr_request_T_97 = eq(mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_98 = or(sourceB.io.req.ready, _mshr_request_T_97) node _mshr_request_T_99 = and(_mshr_request_T_96, _mshr_request_T_98) node _mshr_request_T_100 = eq(mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_101 = or(sourceC.io.req.ready, _mshr_request_T_100) node _mshr_request_T_102 = and(_mshr_request_T_99, _mshr_request_T_101) node _mshr_request_T_103 = eq(mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_104 = or(sourceD.io.req.ready, _mshr_request_T_103) node _mshr_request_T_105 = and(_mshr_request_T_102, _mshr_request_T_104) node _mshr_request_T_106 = eq(mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_107 = or(sourceE.io.req.ready, _mshr_request_T_106) node _mshr_request_T_108 = and(_mshr_request_T_105, _mshr_request_T_107) node _mshr_request_T_109 = eq(mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_110 = or(sourceX.io.req.ready, _mshr_request_T_109) node _mshr_request_T_111 = and(_mshr_request_T_108, _mshr_request_T_110) node _mshr_request_T_112 = eq(mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_113 = or(directory.io.write.ready, _mshr_request_T_112) node _mshr_request_T_114 = and(_mshr_request_T_111, _mshr_request_T_113) node _mshr_request_T_115 = eq(mshr_stall_abc_5, UInt<1>(0h0)) node _mshr_request_T_116 = and(mshrs_5.io.schedule.valid, _mshr_request_T_115) node _mshr_request_T_117 = eq(mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_118 = or(sourceA.io.req.ready, _mshr_request_T_117) node _mshr_request_T_119 = and(_mshr_request_T_116, _mshr_request_T_118) node _mshr_request_T_120 = eq(mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_121 = or(sourceB.io.req.ready, _mshr_request_T_120) node _mshr_request_T_122 = and(_mshr_request_T_119, _mshr_request_T_121) node _mshr_request_T_123 = eq(mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_124 = or(sourceC.io.req.ready, _mshr_request_T_123) node _mshr_request_T_125 = and(_mshr_request_T_122, _mshr_request_T_124) node _mshr_request_T_126 = eq(mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_127 = or(sourceD.io.req.ready, _mshr_request_T_126) node _mshr_request_T_128 = and(_mshr_request_T_125, _mshr_request_T_127) node _mshr_request_T_129 = eq(mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_130 = or(sourceE.io.req.ready, _mshr_request_T_129) node _mshr_request_T_131 = and(_mshr_request_T_128, _mshr_request_T_130) node _mshr_request_T_132 = eq(mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_133 = or(sourceX.io.req.ready, _mshr_request_T_132) node _mshr_request_T_134 = and(_mshr_request_T_131, _mshr_request_T_133) node _mshr_request_T_135 = eq(mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_136 = or(directory.io.write.ready, _mshr_request_T_135) node _mshr_request_T_137 = and(_mshr_request_T_134, _mshr_request_T_136) node _mshr_request_T_138 = eq(mshr_stall_abc_6, UInt<1>(0h0)) node _mshr_request_T_139 = and(mshrs_6.io.schedule.valid, _mshr_request_T_138) node _mshr_request_T_140 = eq(mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_141 = or(sourceA.io.req.ready, _mshr_request_T_140) node _mshr_request_T_142 = and(_mshr_request_T_139, _mshr_request_T_141) node _mshr_request_T_143 = eq(mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_144 = or(sourceB.io.req.ready, _mshr_request_T_143) node _mshr_request_T_145 = and(_mshr_request_T_142, _mshr_request_T_144) node _mshr_request_T_146 = eq(mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_147 = or(sourceC.io.req.ready, _mshr_request_T_146) node _mshr_request_T_148 = and(_mshr_request_T_145, _mshr_request_T_147) node _mshr_request_T_149 = eq(mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_150 = or(sourceD.io.req.ready, _mshr_request_T_149) node _mshr_request_T_151 = and(_mshr_request_T_148, _mshr_request_T_150) node _mshr_request_T_152 = eq(mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_153 = or(sourceE.io.req.ready, _mshr_request_T_152) node _mshr_request_T_154 = and(_mshr_request_T_151, _mshr_request_T_153) node _mshr_request_T_155 = eq(mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_156 = or(sourceX.io.req.ready, _mshr_request_T_155) node _mshr_request_T_157 = and(_mshr_request_T_154, _mshr_request_T_156) node _mshr_request_T_158 = eq(mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_159 = or(directory.io.write.ready, _mshr_request_T_158) node _mshr_request_T_160 = and(_mshr_request_T_157, _mshr_request_T_159) node _mshr_request_T_161 = eq(mshr_stall_abc_7, UInt<1>(0h0)) node _mshr_request_T_162 = and(mshrs_7.io.schedule.valid, _mshr_request_T_161) node _mshr_request_T_163 = eq(mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_164 = or(sourceA.io.req.ready, _mshr_request_T_163) node _mshr_request_T_165 = and(_mshr_request_T_162, _mshr_request_T_164) node _mshr_request_T_166 = eq(mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_167 = or(sourceB.io.req.ready, _mshr_request_T_166) node _mshr_request_T_168 = and(_mshr_request_T_165, _mshr_request_T_167) node _mshr_request_T_169 = eq(mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_170 = or(sourceC.io.req.ready, _mshr_request_T_169) node _mshr_request_T_171 = and(_mshr_request_T_168, _mshr_request_T_170) node _mshr_request_T_172 = eq(mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_173 = or(sourceD.io.req.ready, _mshr_request_T_172) node _mshr_request_T_174 = and(_mshr_request_T_171, _mshr_request_T_173) node _mshr_request_T_175 = eq(mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_176 = or(sourceE.io.req.ready, _mshr_request_T_175) node _mshr_request_T_177 = and(_mshr_request_T_174, _mshr_request_T_176) node _mshr_request_T_178 = eq(mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_179 = or(sourceX.io.req.ready, _mshr_request_T_178) node _mshr_request_T_180 = and(_mshr_request_T_177, _mshr_request_T_179) node _mshr_request_T_181 = eq(mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_182 = or(directory.io.write.ready, _mshr_request_T_181) node _mshr_request_T_183 = and(_mshr_request_T_180, _mshr_request_T_182) node _mshr_request_T_184 = eq(mshr_stall_abc_8, UInt<1>(0h0)) node _mshr_request_T_185 = and(mshrs_8.io.schedule.valid, _mshr_request_T_184) node _mshr_request_T_186 = eq(mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_187 = or(sourceA.io.req.ready, _mshr_request_T_186) node _mshr_request_T_188 = and(_mshr_request_T_185, _mshr_request_T_187) node _mshr_request_T_189 = eq(mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_190 = or(sourceB.io.req.ready, _mshr_request_T_189) node _mshr_request_T_191 = and(_mshr_request_T_188, _mshr_request_T_190) node _mshr_request_T_192 = eq(mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_193 = or(sourceC.io.req.ready, _mshr_request_T_192) node _mshr_request_T_194 = and(_mshr_request_T_191, _mshr_request_T_193) node _mshr_request_T_195 = eq(mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_196 = or(sourceD.io.req.ready, _mshr_request_T_195) node _mshr_request_T_197 = and(_mshr_request_T_194, _mshr_request_T_196) node _mshr_request_T_198 = eq(mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_199 = or(sourceE.io.req.ready, _mshr_request_T_198) node _mshr_request_T_200 = and(_mshr_request_T_197, _mshr_request_T_199) node _mshr_request_T_201 = eq(mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_202 = or(sourceX.io.req.ready, _mshr_request_T_201) node _mshr_request_T_203 = and(_mshr_request_T_200, _mshr_request_T_202) node _mshr_request_T_204 = eq(mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_205 = or(directory.io.write.ready, _mshr_request_T_204) node _mshr_request_T_206 = and(_mshr_request_T_203, _mshr_request_T_205) node _mshr_request_T_207 = eq(mshr_stall_abc_9, UInt<1>(0h0)) node _mshr_request_T_208 = and(mshrs_9.io.schedule.valid, _mshr_request_T_207) node _mshr_request_T_209 = eq(mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_210 = or(sourceA.io.req.ready, _mshr_request_T_209) node _mshr_request_T_211 = and(_mshr_request_T_208, _mshr_request_T_210) node _mshr_request_T_212 = eq(mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_213 = or(sourceB.io.req.ready, _mshr_request_T_212) node _mshr_request_T_214 = and(_mshr_request_T_211, _mshr_request_T_213) node _mshr_request_T_215 = eq(mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_216 = or(sourceC.io.req.ready, _mshr_request_T_215) node _mshr_request_T_217 = and(_mshr_request_T_214, _mshr_request_T_216) node _mshr_request_T_218 = eq(mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_219 = or(sourceD.io.req.ready, _mshr_request_T_218) node _mshr_request_T_220 = and(_mshr_request_T_217, _mshr_request_T_219) node _mshr_request_T_221 = eq(mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_222 = or(sourceE.io.req.ready, _mshr_request_T_221) node _mshr_request_T_223 = and(_mshr_request_T_220, _mshr_request_T_222) node _mshr_request_T_224 = eq(mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_225 = or(sourceX.io.req.ready, _mshr_request_T_224) node _mshr_request_T_226 = and(_mshr_request_T_223, _mshr_request_T_225) node _mshr_request_T_227 = eq(mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_228 = or(directory.io.write.ready, _mshr_request_T_227) node _mshr_request_T_229 = and(_mshr_request_T_226, _mshr_request_T_228) node _mshr_request_T_230 = eq(mshr_stall_bc, UInt<1>(0h0)) node _mshr_request_T_231 = and(mshrs_10.io.schedule.valid, _mshr_request_T_230) node _mshr_request_T_232 = eq(mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_233 = or(sourceA.io.req.ready, _mshr_request_T_232) node _mshr_request_T_234 = and(_mshr_request_T_231, _mshr_request_T_233) node _mshr_request_T_235 = eq(mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_236 = or(sourceB.io.req.ready, _mshr_request_T_235) node _mshr_request_T_237 = and(_mshr_request_T_234, _mshr_request_T_236) node _mshr_request_T_238 = eq(mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_239 = or(sourceC.io.req.ready, _mshr_request_T_238) node _mshr_request_T_240 = and(_mshr_request_T_237, _mshr_request_T_239) node _mshr_request_T_241 = eq(mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_242 = or(sourceD.io.req.ready, _mshr_request_T_241) node _mshr_request_T_243 = and(_mshr_request_T_240, _mshr_request_T_242) node _mshr_request_T_244 = eq(mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_245 = or(sourceE.io.req.ready, _mshr_request_T_244) node _mshr_request_T_246 = and(_mshr_request_T_243, _mshr_request_T_245) node _mshr_request_T_247 = eq(mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_248 = or(sourceX.io.req.ready, _mshr_request_T_247) node _mshr_request_T_249 = and(_mshr_request_T_246, _mshr_request_T_248) node _mshr_request_T_250 = eq(mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_251 = or(directory.io.write.ready, _mshr_request_T_250) node _mshr_request_T_252 = and(_mshr_request_T_249, _mshr_request_T_251) node _mshr_request_T_253 = eq(UInt<1>(0h0), UInt<1>(0h0)) node _mshr_request_T_254 = and(mshrs_11.io.schedule.valid, _mshr_request_T_253) node _mshr_request_T_255 = eq(mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0)) node _mshr_request_T_256 = or(sourceA.io.req.ready, _mshr_request_T_255) node _mshr_request_T_257 = and(_mshr_request_T_254, _mshr_request_T_256) node _mshr_request_T_258 = eq(mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0)) node _mshr_request_T_259 = or(sourceB.io.req.ready, _mshr_request_T_258) node _mshr_request_T_260 = and(_mshr_request_T_257, _mshr_request_T_259) node _mshr_request_T_261 = eq(mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0)) node _mshr_request_T_262 = or(sourceC.io.req.ready, _mshr_request_T_261) node _mshr_request_T_263 = and(_mshr_request_T_260, _mshr_request_T_262) node _mshr_request_T_264 = eq(mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0)) node _mshr_request_T_265 = or(sourceD.io.req.ready, _mshr_request_T_264) node _mshr_request_T_266 = and(_mshr_request_T_263, _mshr_request_T_265) node _mshr_request_T_267 = eq(mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0)) node _mshr_request_T_268 = or(sourceE.io.req.ready, _mshr_request_T_267) node _mshr_request_T_269 = and(_mshr_request_T_266, _mshr_request_T_268) node _mshr_request_T_270 = eq(mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0)) node _mshr_request_T_271 = or(sourceX.io.req.ready, _mshr_request_T_270) node _mshr_request_T_272 = and(_mshr_request_T_269, _mshr_request_T_271) node _mshr_request_T_273 = eq(mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _mshr_request_T_274 = or(directory.io.write.ready, _mshr_request_T_273) node _mshr_request_T_275 = and(_mshr_request_T_272, _mshr_request_T_274) node mshr_request_lo_lo_hi = cat(_mshr_request_T_68, _mshr_request_T_45) node mshr_request_lo_lo = cat(mshr_request_lo_lo_hi, _mshr_request_T_22) node mshr_request_lo_hi_hi = cat(_mshr_request_T_137, _mshr_request_T_114) node mshr_request_lo_hi = cat(mshr_request_lo_hi_hi, _mshr_request_T_91) node mshr_request_lo = cat(mshr_request_lo_hi, mshr_request_lo_lo) node mshr_request_hi_lo_hi = cat(_mshr_request_T_206, _mshr_request_T_183) node mshr_request_hi_lo = cat(mshr_request_hi_lo_hi, _mshr_request_T_160) node mshr_request_hi_hi_hi = cat(_mshr_request_T_275, _mshr_request_T_252) node mshr_request_hi_hi = cat(mshr_request_hi_hi_hi, _mshr_request_T_229) node mshr_request_hi = cat(mshr_request_hi_hi, mshr_request_hi_lo) node mshr_request = cat(mshr_request_hi, mshr_request_lo) regreset robin_filter : UInt<12>, clock, reset, UInt<12>(0h0) node _robin_request_T = and(mshr_request, robin_filter) node robin_request = cat(mshr_request, _robin_request_T) node _mshr_selectOH2_T = shl(robin_request, 1) node _mshr_selectOH2_T_1 = bits(_mshr_selectOH2_T, 23, 0) node _mshr_selectOH2_T_2 = or(robin_request, _mshr_selectOH2_T_1) node _mshr_selectOH2_T_3 = shl(_mshr_selectOH2_T_2, 2) node _mshr_selectOH2_T_4 = bits(_mshr_selectOH2_T_3, 23, 0) node _mshr_selectOH2_T_5 = or(_mshr_selectOH2_T_2, _mshr_selectOH2_T_4) node _mshr_selectOH2_T_6 = shl(_mshr_selectOH2_T_5, 4) node _mshr_selectOH2_T_7 = bits(_mshr_selectOH2_T_6, 23, 0) node _mshr_selectOH2_T_8 = or(_mshr_selectOH2_T_5, _mshr_selectOH2_T_7) node _mshr_selectOH2_T_9 = shl(_mshr_selectOH2_T_8, 8) node _mshr_selectOH2_T_10 = bits(_mshr_selectOH2_T_9, 23, 0) node _mshr_selectOH2_T_11 = or(_mshr_selectOH2_T_8, _mshr_selectOH2_T_10) node _mshr_selectOH2_T_12 = shl(_mshr_selectOH2_T_11, 16) node _mshr_selectOH2_T_13 = bits(_mshr_selectOH2_T_12, 23, 0) node _mshr_selectOH2_T_14 = or(_mshr_selectOH2_T_11, _mshr_selectOH2_T_13) node _mshr_selectOH2_T_15 = bits(_mshr_selectOH2_T_14, 23, 0) node _mshr_selectOH2_T_16 = shl(_mshr_selectOH2_T_15, 1) node _mshr_selectOH2_T_17 = not(_mshr_selectOH2_T_16) node mshr_selectOH2 = and(_mshr_selectOH2_T_17, robin_request) node _mshr_selectOH_T = bits(mshr_selectOH2, 23, 12) node _mshr_selectOH_T_1 = bits(mshr_selectOH2, 11, 0) node mshr_selectOH = or(_mshr_selectOH_T, _mshr_selectOH_T_1) node mshr_select_hi = bits(mshr_selectOH, 11, 8) node mshr_select_lo = bits(mshr_selectOH, 7, 0) node _mshr_select_T = orr(mshr_select_hi) node _mshr_select_T_1 = or(mshr_select_hi, mshr_select_lo) node mshr_select_hi_1 = bits(_mshr_select_T_1, 7, 4) node mshr_select_lo_1 = bits(_mshr_select_T_1, 3, 0) node _mshr_select_T_2 = orr(mshr_select_hi_1) node _mshr_select_T_3 = or(mshr_select_hi_1, mshr_select_lo_1) node mshr_select_hi_2 = bits(_mshr_select_T_3, 3, 2) node mshr_select_lo_2 = bits(_mshr_select_T_3, 1, 0) node _mshr_select_T_4 = orr(mshr_select_hi_2) node _mshr_select_T_5 = or(mshr_select_hi_2, mshr_select_lo_2) node _mshr_select_T_6 = bits(_mshr_select_T_5, 1, 1) node _mshr_select_T_7 = cat(_mshr_select_T_4, _mshr_select_T_6) node _mshr_select_T_8 = cat(_mshr_select_T_2, _mshr_select_T_7) node mshr_select = cat(_mshr_select_T, _mshr_select_T_8) node _schedule_T = bits(mshr_selectOH, 0, 0) node _schedule_T_1 = bits(mshr_selectOH, 1, 1) node _schedule_T_2 = bits(mshr_selectOH, 2, 2) node _schedule_T_3 = bits(mshr_selectOH, 3, 3) node _schedule_T_4 = bits(mshr_selectOH, 4, 4) node _schedule_T_5 = bits(mshr_selectOH, 5, 5) node _schedule_T_6 = bits(mshr_selectOH, 6, 6) node _schedule_T_7 = bits(mshr_selectOH, 7, 7) node _schedule_T_8 = bits(mshr_selectOH, 8, 8) node _schedule_T_9 = bits(mshr_selectOH, 9, 9) node _schedule_T_10 = bits(mshr_selectOH, 10, 10) node _schedule_T_11 = bits(mshr_selectOH, 11, 11) wire schedule : { a : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}}, b : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}}, c : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}}, d : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}}, e : { valid : UInt<1>, bits : { sink : UInt<3>}}, x : { valid : UInt<1>, bits : { fail : UInt<1>}}, dir : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}}, reload : UInt<1>} node _schedule_T_12 = mux(_schedule_T, mshrs_0.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_13 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_14 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_15 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_16 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_17 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_18 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_19 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_20 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_21 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_22 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_23 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.reload, UInt<1>(0h0)) node _schedule_T_24 = or(_schedule_T_12, _schedule_T_13) node _schedule_T_25 = or(_schedule_T_24, _schedule_T_14) node _schedule_T_26 = or(_schedule_T_25, _schedule_T_15) node _schedule_T_27 = or(_schedule_T_26, _schedule_T_16) node _schedule_T_28 = or(_schedule_T_27, _schedule_T_17) node _schedule_T_29 = or(_schedule_T_28, _schedule_T_18) node _schedule_T_30 = or(_schedule_T_29, _schedule_T_19) node _schedule_T_31 = or(_schedule_T_30, _schedule_T_20) node _schedule_T_32 = or(_schedule_T_31, _schedule_T_21) node _schedule_T_33 = or(_schedule_T_32, _schedule_T_22) node _schedule_T_34 = or(_schedule_T_33, _schedule_T_23) wire _schedule_WIRE : UInt<1> connect _schedule_WIRE, _schedule_T_34 connect schedule.reload, _schedule_WIRE wire _schedule_WIRE_1 : { valid : UInt<1>, bits : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}}} wire _schedule_WIRE_2 : { set : UInt<11>, way : UInt<4>, data : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>}} wire _schedule_WIRE_3 : { dirty : UInt<1>, state : UInt<2>, clients : UInt<1>, tag : UInt<9>} node _schedule_T_35 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_36 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_37 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_38 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_39 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_40 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_41 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_42 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_43 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_44 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_45 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_46 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.tag, UInt<1>(0h0)) node _schedule_T_47 = or(_schedule_T_35, _schedule_T_36) node _schedule_T_48 = or(_schedule_T_47, _schedule_T_37) node _schedule_T_49 = or(_schedule_T_48, _schedule_T_38) node _schedule_T_50 = or(_schedule_T_49, _schedule_T_39) node _schedule_T_51 = or(_schedule_T_50, _schedule_T_40) node _schedule_T_52 = or(_schedule_T_51, _schedule_T_41) node _schedule_T_53 = or(_schedule_T_52, _schedule_T_42) node _schedule_T_54 = or(_schedule_T_53, _schedule_T_43) node _schedule_T_55 = or(_schedule_T_54, _schedule_T_44) node _schedule_T_56 = or(_schedule_T_55, _schedule_T_45) node _schedule_T_57 = or(_schedule_T_56, _schedule_T_46) wire _schedule_WIRE_4 : UInt<9> connect _schedule_WIRE_4, _schedule_T_57 connect _schedule_WIRE_3.tag, _schedule_WIRE_4 node _schedule_T_58 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_59 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_60 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_61 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_62 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_63 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_64 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_65 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_66 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_67 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_68 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_69 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.clients, UInt<1>(0h0)) node _schedule_T_70 = or(_schedule_T_58, _schedule_T_59) node _schedule_T_71 = or(_schedule_T_70, _schedule_T_60) node _schedule_T_72 = or(_schedule_T_71, _schedule_T_61) node _schedule_T_73 = or(_schedule_T_72, _schedule_T_62) node _schedule_T_74 = or(_schedule_T_73, _schedule_T_63) node _schedule_T_75 = or(_schedule_T_74, _schedule_T_64) node _schedule_T_76 = or(_schedule_T_75, _schedule_T_65) node _schedule_T_77 = or(_schedule_T_76, _schedule_T_66) node _schedule_T_78 = or(_schedule_T_77, _schedule_T_67) node _schedule_T_79 = or(_schedule_T_78, _schedule_T_68) node _schedule_T_80 = or(_schedule_T_79, _schedule_T_69) wire _schedule_WIRE_5 : UInt<1> connect _schedule_WIRE_5, _schedule_T_80 connect _schedule_WIRE_3.clients, _schedule_WIRE_5 node _schedule_T_81 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_82 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_83 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_84 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_85 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_86 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_87 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_88 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_89 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_90 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_91 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_92 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.state, UInt<1>(0h0)) node _schedule_T_93 = or(_schedule_T_81, _schedule_T_82) node _schedule_T_94 = or(_schedule_T_93, _schedule_T_83) node _schedule_T_95 = or(_schedule_T_94, _schedule_T_84) node _schedule_T_96 = or(_schedule_T_95, _schedule_T_85) node _schedule_T_97 = or(_schedule_T_96, _schedule_T_86) node _schedule_T_98 = or(_schedule_T_97, _schedule_T_87) node _schedule_T_99 = or(_schedule_T_98, _schedule_T_88) node _schedule_T_100 = or(_schedule_T_99, _schedule_T_89) node _schedule_T_101 = or(_schedule_T_100, _schedule_T_90) node _schedule_T_102 = or(_schedule_T_101, _schedule_T_91) node _schedule_T_103 = or(_schedule_T_102, _schedule_T_92) wire _schedule_WIRE_6 : UInt<2> connect _schedule_WIRE_6, _schedule_T_103 connect _schedule_WIRE_3.state, _schedule_WIRE_6 node _schedule_T_104 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_105 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_106 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_107 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_108 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_109 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_110 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_111 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_112 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_113 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_114 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_115 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.data.dirty, UInt<1>(0h0)) node _schedule_T_116 = or(_schedule_T_104, _schedule_T_105) node _schedule_T_117 = or(_schedule_T_116, _schedule_T_106) node _schedule_T_118 = or(_schedule_T_117, _schedule_T_107) node _schedule_T_119 = or(_schedule_T_118, _schedule_T_108) node _schedule_T_120 = or(_schedule_T_119, _schedule_T_109) node _schedule_T_121 = or(_schedule_T_120, _schedule_T_110) node _schedule_T_122 = or(_schedule_T_121, _schedule_T_111) node _schedule_T_123 = or(_schedule_T_122, _schedule_T_112) node _schedule_T_124 = or(_schedule_T_123, _schedule_T_113) node _schedule_T_125 = or(_schedule_T_124, _schedule_T_114) node _schedule_T_126 = or(_schedule_T_125, _schedule_T_115) wire _schedule_WIRE_7 : UInt<1> connect _schedule_WIRE_7, _schedule_T_126 connect _schedule_WIRE_3.dirty, _schedule_WIRE_7 connect _schedule_WIRE_2.data, _schedule_WIRE_3 node _schedule_T_127 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_128 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_129 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_130 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_131 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_132 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_133 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_134 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_135 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_136 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_137 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_138 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.way, UInt<1>(0h0)) node _schedule_T_139 = or(_schedule_T_127, _schedule_T_128) node _schedule_T_140 = or(_schedule_T_139, _schedule_T_129) node _schedule_T_141 = or(_schedule_T_140, _schedule_T_130) node _schedule_T_142 = or(_schedule_T_141, _schedule_T_131) node _schedule_T_143 = or(_schedule_T_142, _schedule_T_132) node _schedule_T_144 = or(_schedule_T_143, _schedule_T_133) node _schedule_T_145 = or(_schedule_T_144, _schedule_T_134) node _schedule_T_146 = or(_schedule_T_145, _schedule_T_135) node _schedule_T_147 = or(_schedule_T_146, _schedule_T_136) node _schedule_T_148 = or(_schedule_T_147, _schedule_T_137) node _schedule_T_149 = or(_schedule_T_148, _schedule_T_138) wire _schedule_WIRE_8 : UInt<4> connect _schedule_WIRE_8, _schedule_T_149 connect _schedule_WIRE_2.way, _schedule_WIRE_8 node _schedule_T_150 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_151 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_152 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_153 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_154 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_155 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_156 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_157 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_158 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_159 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_160 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_161 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.bits.set, UInt<1>(0h0)) node _schedule_T_162 = or(_schedule_T_150, _schedule_T_151) node _schedule_T_163 = or(_schedule_T_162, _schedule_T_152) node _schedule_T_164 = or(_schedule_T_163, _schedule_T_153) node _schedule_T_165 = or(_schedule_T_164, _schedule_T_154) node _schedule_T_166 = or(_schedule_T_165, _schedule_T_155) node _schedule_T_167 = or(_schedule_T_166, _schedule_T_156) node _schedule_T_168 = or(_schedule_T_167, _schedule_T_157) node _schedule_T_169 = or(_schedule_T_168, _schedule_T_158) node _schedule_T_170 = or(_schedule_T_169, _schedule_T_159) node _schedule_T_171 = or(_schedule_T_170, _schedule_T_160) node _schedule_T_172 = or(_schedule_T_171, _schedule_T_161) wire _schedule_WIRE_9 : UInt<11> connect _schedule_WIRE_9, _schedule_T_172 connect _schedule_WIRE_2.set, _schedule_WIRE_9 connect _schedule_WIRE_1.bits, _schedule_WIRE_2 node _schedule_T_173 = mux(_schedule_T, mshrs_0.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_174 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_175 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_176 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_177 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_178 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_179 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_180 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_181 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_182 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_183 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_184 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.dir.valid, UInt<1>(0h0)) node _schedule_T_185 = or(_schedule_T_173, _schedule_T_174) node _schedule_T_186 = or(_schedule_T_185, _schedule_T_175) node _schedule_T_187 = or(_schedule_T_186, _schedule_T_176) node _schedule_T_188 = or(_schedule_T_187, _schedule_T_177) node _schedule_T_189 = or(_schedule_T_188, _schedule_T_178) node _schedule_T_190 = or(_schedule_T_189, _schedule_T_179) node _schedule_T_191 = or(_schedule_T_190, _schedule_T_180) node _schedule_T_192 = or(_schedule_T_191, _schedule_T_181) node _schedule_T_193 = or(_schedule_T_192, _schedule_T_182) node _schedule_T_194 = or(_schedule_T_193, _schedule_T_183) node _schedule_T_195 = or(_schedule_T_194, _schedule_T_184) wire _schedule_WIRE_10 : UInt<1> connect _schedule_WIRE_10, _schedule_T_195 connect _schedule_WIRE_1.valid, _schedule_WIRE_10 connect schedule.dir, _schedule_WIRE_1 wire _schedule_WIRE_11 : { valid : UInt<1>, bits : { fail : UInt<1>}} wire _schedule_WIRE_12 : { fail : UInt<1>} node _schedule_T_196 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_197 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_198 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_199 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_200 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_201 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_202 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_203 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_204 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_205 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_206 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_207 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.bits.fail, UInt<1>(0h0)) node _schedule_T_208 = or(_schedule_T_196, _schedule_T_197) node _schedule_T_209 = or(_schedule_T_208, _schedule_T_198) node _schedule_T_210 = or(_schedule_T_209, _schedule_T_199) node _schedule_T_211 = or(_schedule_T_210, _schedule_T_200) node _schedule_T_212 = or(_schedule_T_211, _schedule_T_201) node _schedule_T_213 = or(_schedule_T_212, _schedule_T_202) node _schedule_T_214 = or(_schedule_T_213, _schedule_T_203) node _schedule_T_215 = or(_schedule_T_214, _schedule_T_204) node _schedule_T_216 = or(_schedule_T_215, _schedule_T_205) node _schedule_T_217 = or(_schedule_T_216, _schedule_T_206) node _schedule_T_218 = or(_schedule_T_217, _schedule_T_207) wire _schedule_WIRE_13 : UInt<1> connect _schedule_WIRE_13, _schedule_T_218 connect _schedule_WIRE_12.fail, _schedule_WIRE_13 connect _schedule_WIRE_11.bits, _schedule_WIRE_12 node _schedule_T_219 = mux(_schedule_T, mshrs_0.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_220 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_221 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_222 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_223 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_224 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_225 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_226 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_227 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_228 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_229 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_230 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.x.valid, UInt<1>(0h0)) node _schedule_T_231 = or(_schedule_T_219, _schedule_T_220) node _schedule_T_232 = or(_schedule_T_231, _schedule_T_221) node _schedule_T_233 = or(_schedule_T_232, _schedule_T_222) node _schedule_T_234 = or(_schedule_T_233, _schedule_T_223) node _schedule_T_235 = or(_schedule_T_234, _schedule_T_224) node _schedule_T_236 = or(_schedule_T_235, _schedule_T_225) node _schedule_T_237 = or(_schedule_T_236, _schedule_T_226) node _schedule_T_238 = or(_schedule_T_237, _schedule_T_227) node _schedule_T_239 = or(_schedule_T_238, _schedule_T_228) node _schedule_T_240 = or(_schedule_T_239, _schedule_T_229) node _schedule_T_241 = or(_schedule_T_240, _schedule_T_230) wire _schedule_WIRE_14 : UInt<1> connect _schedule_WIRE_14, _schedule_T_241 connect _schedule_WIRE_11.valid, _schedule_WIRE_14 connect schedule.x, _schedule_WIRE_11 wire _schedule_WIRE_15 : { valid : UInt<1>, bits : { sink : UInt<3>}} wire _schedule_WIRE_16 : { sink : UInt<3>} node _schedule_T_242 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_243 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_244 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_245 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_246 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_247 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_248 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_249 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_250 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_251 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_252 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_253 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.bits.sink, UInt<1>(0h0)) node _schedule_T_254 = or(_schedule_T_242, _schedule_T_243) node _schedule_T_255 = or(_schedule_T_254, _schedule_T_244) node _schedule_T_256 = or(_schedule_T_255, _schedule_T_245) node _schedule_T_257 = or(_schedule_T_256, _schedule_T_246) node _schedule_T_258 = or(_schedule_T_257, _schedule_T_247) node _schedule_T_259 = or(_schedule_T_258, _schedule_T_248) node _schedule_T_260 = or(_schedule_T_259, _schedule_T_249) node _schedule_T_261 = or(_schedule_T_260, _schedule_T_250) node _schedule_T_262 = or(_schedule_T_261, _schedule_T_251) node _schedule_T_263 = or(_schedule_T_262, _schedule_T_252) node _schedule_T_264 = or(_schedule_T_263, _schedule_T_253) wire _schedule_WIRE_17 : UInt<3> connect _schedule_WIRE_17, _schedule_T_264 connect _schedule_WIRE_16.sink, _schedule_WIRE_17 connect _schedule_WIRE_15.bits, _schedule_WIRE_16 node _schedule_T_265 = mux(_schedule_T, mshrs_0.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_266 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_267 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_268 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_269 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_270 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_271 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_272 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_273 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_274 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_275 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_276 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.e.valid, UInt<1>(0h0)) node _schedule_T_277 = or(_schedule_T_265, _schedule_T_266) node _schedule_T_278 = or(_schedule_T_277, _schedule_T_267) node _schedule_T_279 = or(_schedule_T_278, _schedule_T_268) node _schedule_T_280 = or(_schedule_T_279, _schedule_T_269) node _schedule_T_281 = or(_schedule_T_280, _schedule_T_270) node _schedule_T_282 = or(_schedule_T_281, _schedule_T_271) node _schedule_T_283 = or(_schedule_T_282, _schedule_T_272) node _schedule_T_284 = or(_schedule_T_283, _schedule_T_273) node _schedule_T_285 = or(_schedule_T_284, _schedule_T_274) node _schedule_T_286 = or(_schedule_T_285, _schedule_T_275) node _schedule_T_287 = or(_schedule_T_286, _schedule_T_276) wire _schedule_WIRE_18 : UInt<1> connect _schedule_WIRE_18, _schedule_T_287 connect _schedule_WIRE_15.valid, _schedule_WIRE_18 connect schedule.e, _schedule_WIRE_15 wire _schedule_WIRE_19 : { valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>}} wire _schedule_WIRE_20 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>, sink : UInt<4>, way : UInt<4>, bad : UInt<1>} node _schedule_T_288 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_289 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_290 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_291 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_292 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_293 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_294 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_295 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_296 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_297 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_298 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_299 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.bad, UInt<1>(0h0)) node _schedule_T_300 = or(_schedule_T_288, _schedule_T_289) node _schedule_T_301 = or(_schedule_T_300, _schedule_T_290) node _schedule_T_302 = or(_schedule_T_301, _schedule_T_291) node _schedule_T_303 = or(_schedule_T_302, _schedule_T_292) node _schedule_T_304 = or(_schedule_T_303, _schedule_T_293) node _schedule_T_305 = or(_schedule_T_304, _schedule_T_294) node _schedule_T_306 = or(_schedule_T_305, _schedule_T_295) node _schedule_T_307 = or(_schedule_T_306, _schedule_T_296) node _schedule_T_308 = or(_schedule_T_307, _schedule_T_297) node _schedule_T_309 = or(_schedule_T_308, _schedule_T_298) node _schedule_T_310 = or(_schedule_T_309, _schedule_T_299) wire _schedule_WIRE_21 : UInt<1> connect _schedule_WIRE_21, _schedule_T_310 connect _schedule_WIRE_20.bad, _schedule_WIRE_21 node _schedule_T_311 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_312 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_313 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_314 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_315 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_316 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_317 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_318 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_319 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_320 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_321 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_322 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.way, UInt<1>(0h0)) node _schedule_T_323 = or(_schedule_T_311, _schedule_T_312) node _schedule_T_324 = or(_schedule_T_323, _schedule_T_313) node _schedule_T_325 = or(_schedule_T_324, _schedule_T_314) node _schedule_T_326 = or(_schedule_T_325, _schedule_T_315) node _schedule_T_327 = or(_schedule_T_326, _schedule_T_316) node _schedule_T_328 = or(_schedule_T_327, _schedule_T_317) node _schedule_T_329 = or(_schedule_T_328, _schedule_T_318) node _schedule_T_330 = or(_schedule_T_329, _schedule_T_319) node _schedule_T_331 = or(_schedule_T_330, _schedule_T_320) node _schedule_T_332 = or(_schedule_T_331, _schedule_T_321) node _schedule_T_333 = or(_schedule_T_332, _schedule_T_322) wire _schedule_WIRE_22 : UInt<4> connect _schedule_WIRE_22, _schedule_T_333 connect _schedule_WIRE_20.way, _schedule_WIRE_22 node _schedule_T_334 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_335 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_336 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_337 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_338 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_339 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_340 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_341 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_342 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_343 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_344 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_345 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.sink, UInt<1>(0h0)) node _schedule_T_346 = or(_schedule_T_334, _schedule_T_335) node _schedule_T_347 = or(_schedule_T_346, _schedule_T_336) node _schedule_T_348 = or(_schedule_T_347, _schedule_T_337) node _schedule_T_349 = or(_schedule_T_348, _schedule_T_338) node _schedule_T_350 = or(_schedule_T_349, _schedule_T_339) node _schedule_T_351 = or(_schedule_T_350, _schedule_T_340) node _schedule_T_352 = or(_schedule_T_351, _schedule_T_341) node _schedule_T_353 = or(_schedule_T_352, _schedule_T_342) node _schedule_T_354 = or(_schedule_T_353, _schedule_T_343) node _schedule_T_355 = or(_schedule_T_354, _schedule_T_344) node _schedule_T_356 = or(_schedule_T_355, _schedule_T_345) wire _schedule_WIRE_23 : UInt<4> connect _schedule_WIRE_23, _schedule_T_356 connect _schedule_WIRE_20.sink, _schedule_WIRE_23 node _schedule_T_357 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_358 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_359 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_360 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_361 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_362 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_363 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_364 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_365 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_366 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_367 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_368 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.set, UInt<1>(0h0)) node _schedule_T_369 = or(_schedule_T_357, _schedule_T_358) node _schedule_T_370 = or(_schedule_T_369, _schedule_T_359) node _schedule_T_371 = or(_schedule_T_370, _schedule_T_360) node _schedule_T_372 = or(_schedule_T_371, _schedule_T_361) node _schedule_T_373 = or(_schedule_T_372, _schedule_T_362) node _schedule_T_374 = or(_schedule_T_373, _schedule_T_363) node _schedule_T_375 = or(_schedule_T_374, _schedule_T_364) node _schedule_T_376 = or(_schedule_T_375, _schedule_T_365) node _schedule_T_377 = or(_schedule_T_376, _schedule_T_366) node _schedule_T_378 = or(_schedule_T_377, _schedule_T_367) node _schedule_T_379 = or(_schedule_T_378, _schedule_T_368) wire _schedule_WIRE_24 : UInt<11> connect _schedule_WIRE_24, _schedule_T_379 connect _schedule_WIRE_20.set, _schedule_WIRE_24 node _schedule_T_380 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_381 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_382 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_383 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_384 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_385 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_386 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_387 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_388 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_389 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_390 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_391 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.put, UInt<1>(0h0)) node _schedule_T_392 = or(_schedule_T_380, _schedule_T_381) node _schedule_T_393 = or(_schedule_T_392, _schedule_T_382) node _schedule_T_394 = or(_schedule_T_393, _schedule_T_383) node _schedule_T_395 = or(_schedule_T_394, _schedule_T_384) node _schedule_T_396 = or(_schedule_T_395, _schedule_T_385) node _schedule_T_397 = or(_schedule_T_396, _schedule_T_386) node _schedule_T_398 = or(_schedule_T_397, _schedule_T_387) node _schedule_T_399 = or(_schedule_T_398, _schedule_T_388) node _schedule_T_400 = or(_schedule_T_399, _schedule_T_389) node _schedule_T_401 = or(_schedule_T_400, _schedule_T_390) node _schedule_T_402 = or(_schedule_T_401, _schedule_T_391) wire _schedule_WIRE_25 : UInt<6> connect _schedule_WIRE_25, _schedule_T_402 connect _schedule_WIRE_20.put, _schedule_WIRE_25 node _schedule_T_403 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_404 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_405 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_406 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_407 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_408 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_409 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_410 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_411 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_412 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_413 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_414 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.offset, UInt<1>(0h0)) node _schedule_T_415 = or(_schedule_T_403, _schedule_T_404) node _schedule_T_416 = or(_schedule_T_415, _schedule_T_405) node _schedule_T_417 = or(_schedule_T_416, _schedule_T_406) node _schedule_T_418 = or(_schedule_T_417, _schedule_T_407) node _schedule_T_419 = or(_schedule_T_418, _schedule_T_408) node _schedule_T_420 = or(_schedule_T_419, _schedule_T_409) node _schedule_T_421 = or(_schedule_T_420, _schedule_T_410) node _schedule_T_422 = or(_schedule_T_421, _schedule_T_411) node _schedule_T_423 = or(_schedule_T_422, _schedule_T_412) node _schedule_T_424 = or(_schedule_T_423, _schedule_T_413) node _schedule_T_425 = or(_schedule_T_424, _schedule_T_414) wire _schedule_WIRE_26 : UInt<6> connect _schedule_WIRE_26, _schedule_T_425 connect _schedule_WIRE_20.offset, _schedule_WIRE_26 node _schedule_T_426 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_427 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_428 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_429 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_430 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_431 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_432 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_433 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_434 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_435 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_436 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_437 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.tag, UInt<1>(0h0)) node _schedule_T_438 = or(_schedule_T_426, _schedule_T_427) node _schedule_T_439 = or(_schedule_T_438, _schedule_T_428) node _schedule_T_440 = or(_schedule_T_439, _schedule_T_429) node _schedule_T_441 = or(_schedule_T_440, _schedule_T_430) node _schedule_T_442 = or(_schedule_T_441, _schedule_T_431) node _schedule_T_443 = or(_schedule_T_442, _schedule_T_432) node _schedule_T_444 = or(_schedule_T_443, _schedule_T_433) node _schedule_T_445 = or(_schedule_T_444, _schedule_T_434) node _schedule_T_446 = or(_schedule_T_445, _schedule_T_435) node _schedule_T_447 = or(_schedule_T_446, _schedule_T_436) node _schedule_T_448 = or(_schedule_T_447, _schedule_T_437) wire _schedule_WIRE_27 : UInt<9> connect _schedule_WIRE_27, _schedule_T_448 connect _schedule_WIRE_20.tag, _schedule_WIRE_27 node _schedule_T_449 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_450 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_451 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_452 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_453 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_454 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_455 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_456 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_457 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_458 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_459 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_460 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.source, UInt<1>(0h0)) node _schedule_T_461 = or(_schedule_T_449, _schedule_T_450) node _schedule_T_462 = or(_schedule_T_461, _schedule_T_451) node _schedule_T_463 = or(_schedule_T_462, _schedule_T_452) node _schedule_T_464 = or(_schedule_T_463, _schedule_T_453) node _schedule_T_465 = or(_schedule_T_464, _schedule_T_454) node _schedule_T_466 = or(_schedule_T_465, _schedule_T_455) node _schedule_T_467 = or(_schedule_T_466, _schedule_T_456) node _schedule_T_468 = or(_schedule_T_467, _schedule_T_457) node _schedule_T_469 = or(_schedule_T_468, _schedule_T_458) node _schedule_T_470 = or(_schedule_T_469, _schedule_T_459) node _schedule_T_471 = or(_schedule_T_470, _schedule_T_460) wire _schedule_WIRE_28 : UInt<6> connect _schedule_WIRE_28, _schedule_T_471 connect _schedule_WIRE_20.source, _schedule_WIRE_28 node _schedule_T_472 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_473 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_474 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_475 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_476 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_477 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_478 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_479 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_480 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_481 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_482 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_483 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.size, UInt<1>(0h0)) node _schedule_T_484 = or(_schedule_T_472, _schedule_T_473) node _schedule_T_485 = or(_schedule_T_484, _schedule_T_474) node _schedule_T_486 = or(_schedule_T_485, _schedule_T_475) node _schedule_T_487 = or(_schedule_T_486, _schedule_T_476) node _schedule_T_488 = or(_schedule_T_487, _schedule_T_477) node _schedule_T_489 = or(_schedule_T_488, _schedule_T_478) node _schedule_T_490 = or(_schedule_T_489, _schedule_T_479) node _schedule_T_491 = or(_schedule_T_490, _schedule_T_480) node _schedule_T_492 = or(_schedule_T_491, _schedule_T_481) node _schedule_T_493 = or(_schedule_T_492, _schedule_T_482) node _schedule_T_494 = or(_schedule_T_493, _schedule_T_483) wire _schedule_WIRE_29 : UInt<3> connect _schedule_WIRE_29, _schedule_T_494 connect _schedule_WIRE_20.size, _schedule_WIRE_29 node _schedule_T_495 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_496 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_497 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_498 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_499 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_500 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_501 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_502 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_503 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_504 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_505 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_506 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.param, UInt<1>(0h0)) node _schedule_T_507 = or(_schedule_T_495, _schedule_T_496) node _schedule_T_508 = or(_schedule_T_507, _schedule_T_497) node _schedule_T_509 = or(_schedule_T_508, _schedule_T_498) node _schedule_T_510 = or(_schedule_T_509, _schedule_T_499) node _schedule_T_511 = or(_schedule_T_510, _schedule_T_500) node _schedule_T_512 = or(_schedule_T_511, _schedule_T_501) node _schedule_T_513 = or(_schedule_T_512, _schedule_T_502) node _schedule_T_514 = or(_schedule_T_513, _schedule_T_503) node _schedule_T_515 = or(_schedule_T_514, _schedule_T_504) node _schedule_T_516 = or(_schedule_T_515, _schedule_T_505) node _schedule_T_517 = or(_schedule_T_516, _schedule_T_506) wire _schedule_WIRE_30 : UInt<3> connect _schedule_WIRE_30, _schedule_T_517 connect _schedule_WIRE_20.param, _schedule_WIRE_30 node _schedule_T_518 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_519 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_520 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_521 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_522 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_523 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_524 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_525 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_526 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_527 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_528 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_529 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.opcode, UInt<1>(0h0)) node _schedule_T_530 = or(_schedule_T_518, _schedule_T_519) node _schedule_T_531 = or(_schedule_T_530, _schedule_T_520) node _schedule_T_532 = or(_schedule_T_531, _schedule_T_521) node _schedule_T_533 = or(_schedule_T_532, _schedule_T_522) node _schedule_T_534 = or(_schedule_T_533, _schedule_T_523) node _schedule_T_535 = or(_schedule_T_534, _schedule_T_524) node _schedule_T_536 = or(_schedule_T_535, _schedule_T_525) node _schedule_T_537 = or(_schedule_T_536, _schedule_T_526) node _schedule_T_538 = or(_schedule_T_537, _schedule_T_527) node _schedule_T_539 = or(_schedule_T_538, _schedule_T_528) node _schedule_T_540 = or(_schedule_T_539, _schedule_T_529) wire _schedule_WIRE_31 : UInt<3> connect _schedule_WIRE_31, _schedule_T_540 connect _schedule_WIRE_20.opcode, _schedule_WIRE_31 node _schedule_T_541 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_542 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_543 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_544 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_545 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_546 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_547 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_548 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_549 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_550 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_551 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_552 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.control, UInt<1>(0h0)) node _schedule_T_553 = or(_schedule_T_541, _schedule_T_542) node _schedule_T_554 = or(_schedule_T_553, _schedule_T_543) node _schedule_T_555 = or(_schedule_T_554, _schedule_T_544) node _schedule_T_556 = or(_schedule_T_555, _schedule_T_545) node _schedule_T_557 = or(_schedule_T_556, _schedule_T_546) node _schedule_T_558 = or(_schedule_T_557, _schedule_T_547) node _schedule_T_559 = or(_schedule_T_558, _schedule_T_548) node _schedule_T_560 = or(_schedule_T_559, _schedule_T_549) node _schedule_T_561 = or(_schedule_T_560, _schedule_T_550) node _schedule_T_562 = or(_schedule_T_561, _schedule_T_551) node _schedule_T_563 = or(_schedule_T_562, _schedule_T_552) wire _schedule_WIRE_32 : UInt<1> connect _schedule_WIRE_32, _schedule_T_563 connect _schedule_WIRE_20.control, _schedule_WIRE_32 wire _schedule_WIRE_33 : UInt<1>[3] node _schedule_T_564 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_565 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_566 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_567 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_568 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_569 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_570 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_571 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_572 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_573 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_574 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_575 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[0], UInt<1>(0h0)) node _schedule_T_576 = or(_schedule_T_564, _schedule_T_565) node _schedule_T_577 = or(_schedule_T_576, _schedule_T_566) node _schedule_T_578 = or(_schedule_T_577, _schedule_T_567) node _schedule_T_579 = or(_schedule_T_578, _schedule_T_568) node _schedule_T_580 = or(_schedule_T_579, _schedule_T_569) node _schedule_T_581 = or(_schedule_T_580, _schedule_T_570) node _schedule_T_582 = or(_schedule_T_581, _schedule_T_571) node _schedule_T_583 = or(_schedule_T_582, _schedule_T_572) node _schedule_T_584 = or(_schedule_T_583, _schedule_T_573) node _schedule_T_585 = or(_schedule_T_584, _schedule_T_574) node _schedule_T_586 = or(_schedule_T_585, _schedule_T_575) wire _schedule_WIRE_34 : UInt<1> connect _schedule_WIRE_34, _schedule_T_586 connect _schedule_WIRE_33[0], _schedule_WIRE_34 node _schedule_T_587 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_588 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_589 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_590 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_591 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_592 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_593 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_594 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_595 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_596 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_597 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_598 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[1], UInt<1>(0h0)) node _schedule_T_599 = or(_schedule_T_587, _schedule_T_588) node _schedule_T_600 = or(_schedule_T_599, _schedule_T_589) node _schedule_T_601 = or(_schedule_T_600, _schedule_T_590) node _schedule_T_602 = or(_schedule_T_601, _schedule_T_591) node _schedule_T_603 = or(_schedule_T_602, _schedule_T_592) node _schedule_T_604 = or(_schedule_T_603, _schedule_T_593) node _schedule_T_605 = or(_schedule_T_604, _schedule_T_594) node _schedule_T_606 = or(_schedule_T_605, _schedule_T_595) node _schedule_T_607 = or(_schedule_T_606, _schedule_T_596) node _schedule_T_608 = or(_schedule_T_607, _schedule_T_597) node _schedule_T_609 = or(_schedule_T_608, _schedule_T_598) wire _schedule_WIRE_35 : UInt<1> connect _schedule_WIRE_35, _schedule_T_609 connect _schedule_WIRE_33[1], _schedule_WIRE_35 node _schedule_T_610 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_611 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_612 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_613 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_614 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_615 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_616 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_617 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_618 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_619 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_620 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_621 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.bits.prio[2], UInt<1>(0h0)) node _schedule_T_622 = or(_schedule_T_610, _schedule_T_611) node _schedule_T_623 = or(_schedule_T_622, _schedule_T_612) node _schedule_T_624 = or(_schedule_T_623, _schedule_T_613) node _schedule_T_625 = or(_schedule_T_624, _schedule_T_614) node _schedule_T_626 = or(_schedule_T_625, _schedule_T_615) node _schedule_T_627 = or(_schedule_T_626, _schedule_T_616) node _schedule_T_628 = or(_schedule_T_627, _schedule_T_617) node _schedule_T_629 = or(_schedule_T_628, _schedule_T_618) node _schedule_T_630 = or(_schedule_T_629, _schedule_T_619) node _schedule_T_631 = or(_schedule_T_630, _schedule_T_620) node _schedule_T_632 = or(_schedule_T_631, _schedule_T_621) wire _schedule_WIRE_36 : UInt<1> connect _schedule_WIRE_36, _schedule_T_632 connect _schedule_WIRE_33[2], _schedule_WIRE_36 connect _schedule_WIRE_20.prio, _schedule_WIRE_33 connect _schedule_WIRE_19.bits, _schedule_WIRE_20 node _schedule_T_633 = mux(_schedule_T, mshrs_0.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_634 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_635 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_636 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_637 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_638 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_639 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_640 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_641 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_642 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_643 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_644 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.d.valid, UInt<1>(0h0)) node _schedule_T_645 = or(_schedule_T_633, _schedule_T_634) node _schedule_T_646 = or(_schedule_T_645, _schedule_T_635) node _schedule_T_647 = or(_schedule_T_646, _schedule_T_636) node _schedule_T_648 = or(_schedule_T_647, _schedule_T_637) node _schedule_T_649 = or(_schedule_T_648, _schedule_T_638) node _schedule_T_650 = or(_schedule_T_649, _schedule_T_639) node _schedule_T_651 = or(_schedule_T_650, _schedule_T_640) node _schedule_T_652 = or(_schedule_T_651, _schedule_T_641) node _schedule_T_653 = or(_schedule_T_652, _schedule_T_642) node _schedule_T_654 = or(_schedule_T_653, _schedule_T_643) node _schedule_T_655 = or(_schedule_T_654, _schedule_T_644) wire _schedule_WIRE_37 : UInt<1> connect _schedule_WIRE_37, _schedule_T_655 connect _schedule_WIRE_19.valid, _schedule_WIRE_37 connect schedule.d, _schedule_WIRE_19 wire _schedule_WIRE_38 : { valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>}} wire _schedule_WIRE_39 : { opcode : UInt<3>, param : UInt<3>, source : UInt<4>, tag : UInt<9>, set : UInt<11>, way : UInt<4>, dirty : UInt<1>} node _schedule_T_656 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_657 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_658 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_659 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_660 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_661 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_662 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_663 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_664 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_665 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_666 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_667 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.dirty, UInt<1>(0h0)) node _schedule_T_668 = or(_schedule_T_656, _schedule_T_657) node _schedule_T_669 = or(_schedule_T_668, _schedule_T_658) node _schedule_T_670 = or(_schedule_T_669, _schedule_T_659) node _schedule_T_671 = or(_schedule_T_670, _schedule_T_660) node _schedule_T_672 = or(_schedule_T_671, _schedule_T_661) node _schedule_T_673 = or(_schedule_T_672, _schedule_T_662) node _schedule_T_674 = or(_schedule_T_673, _schedule_T_663) node _schedule_T_675 = or(_schedule_T_674, _schedule_T_664) node _schedule_T_676 = or(_schedule_T_675, _schedule_T_665) node _schedule_T_677 = or(_schedule_T_676, _schedule_T_666) node _schedule_T_678 = or(_schedule_T_677, _schedule_T_667) wire _schedule_WIRE_40 : UInt<1> connect _schedule_WIRE_40, _schedule_T_678 connect _schedule_WIRE_39.dirty, _schedule_WIRE_40 node _schedule_T_679 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_680 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_681 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_682 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_683 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_684 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_685 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_686 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_687 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_688 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_689 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_690 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.way, UInt<1>(0h0)) node _schedule_T_691 = or(_schedule_T_679, _schedule_T_680) node _schedule_T_692 = or(_schedule_T_691, _schedule_T_681) node _schedule_T_693 = or(_schedule_T_692, _schedule_T_682) node _schedule_T_694 = or(_schedule_T_693, _schedule_T_683) node _schedule_T_695 = or(_schedule_T_694, _schedule_T_684) node _schedule_T_696 = or(_schedule_T_695, _schedule_T_685) node _schedule_T_697 = or(_schedule_T_696, _schedule_T_686) node _schedule_T_698 = or(_schedule_T_697, _schedule_T_687) node _schedule_T_699 = or(_schedule_T_698, _schedule_T_688) node _schedule_T_700 = or(_schedule_T_699, _schedule_T_689) node _schedule_T_701 = or(_schedule_T_700, _schedule_T_690) wire _schedule_WIRE_41 : UInt<4> connect _schedule_WIRE_41, _schedule_T_701 connect _schedule_WIRE_39.way, _schedule_WIRE_41 node _schedule_T_702 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_703 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_704 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_705 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_706 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_707 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_708 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_709 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_710 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_711 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_712 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_713 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.set, UInt<1>(0h0)) node _schedule_T_714 = or(_schedule_T_702, _schedule_T_703) node _schedule_T_715 = or(_schedule_T_714, _schedule_T_704) node _schedule_T_716 = or(_schedule_T_715, _schedule_T_705) node _schedule_T_717 = or(_schedule_T_716, _schedule_T_706) node _schedule_T_718 = or(_schedule_T_717, _schedule_T_707) node _schedule_T_719 = or(_schedule_T_718, _schedule_T_708) node _schedule_T_720 = or(_schedule_T_719, _schedule_T_709) node _schedule_T_721 = or(_schedule_T_720, _schedule_T_710) node _schedule_T_722 = or(_schedule_T_721, _schedule_T_711) node _schedule_T_723 = or(_schedule_T_722, _schedule_T_712) node _schedule_T_724 = or(_schedule_T_723, _schedule_T_713) wire _schedule_WIRE_42 : UInt<11> connect _schedule_WIRE_42, _schedule_T_724 connect _schedule_WIRE_39.set, _schedule_WIRE_42 node _schedule_T_725 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_726 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_727 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_728 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_729 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_730 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_731 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_732 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_733 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_734 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_735 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_736 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.tag, UInt<1>(0h0)) node _schedule_T_737 = or(_schedule_T_725, _schedule_T_726) node _schedule_T_738 = or(_schedule_T_737, _schedule_T_727) node _schedule_T_739 = or(_schedule_T_738, _schedule_T_728) node _schedule_T_740 = or(_schedule_T_739, _schedule_T_729) node _schedule_T_741 = or(_schedule_T_740, _schedule_T_730) node _schedule_T_742 = or(_schedule_T_741, _schedule_T_731) node _schedule_T_743 = or(_schedule_T_742, _schedule_T_732) node _schedule_T_744 = or(_schedule_T_743, _schedule_T_733) node _schedule_T_745 = or(_schedule_T_744, _schedule_T_734) node _schedule_T_746 = or(_schedule_T_745, _schedule_T_735) node _schedule_T_747 = or(_schedule_T_746, _schedule_T_736) wire _schedule_WIRE_43 : UInt<9> connect _schedule_WIRE_43, _schedule_T_747 connect _schedule_WIRE_39.tag, _schedule_WIRE_43 node _schedule_T_748 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_749 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_750 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_751 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_752 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_753 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_754 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_755 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_756 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_757 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_758 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_759 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.source, UInt<1>(0h0)) node _schedule_T_760 = or(_schedule_T_748, _schedule_T_749) node _schedule_T_761 = or(_schedule_T_760, _schedule_T_750) node _schedule_T_762 = or(_schedule_T_761, _schedule_T_751) node _schedule_T_763 = or(_schedule_T_762, _schedule_T_752) node _schedule_T_764 = or(_schedule_T_763, _schedule_T_753) node _schedule_T_765 = or(_schedule_T_764, _schedule_T_754) node _schedule_T_766 = or(_schedule_T_765, _schedule_T_755) node _schedule_T_767 = or(_schedule_T_766, _schedule_T_756) node _schedule_T_768 = or(_schedule_T_767, _schedule_T_757) node _schedule_T_769 = or(_schedule_T_768, _schedule_T_758) node _schedule_T_770 = or(_schedule_T_769, _schedule_T_759) wire _schedule_WIRE_44 : UInt<4> connect _schedule_WIRE_44, _schedule_T_770 connect _schedule_WIRE_39.source, _schedule_WIRE_44 node _schedule_T_771 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_772 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_773 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_774 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_775 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_776 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_777 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_778 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_779 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_780 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_781 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_782 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.param, UInt<1>(0h0)) node _schedule_T_783 = or(_schedule_T_771, _schedule_T_772) node _schedule_T_784 = or(_schedule_T_783, _schedule_T_773) node _schedule_T_785 = or(_schedule_T_784, _schedule_T_774) node _schedule_T_786 = or(_schedule_T_785, _schedule_T_775) node _schedule_T_787 = or(_schedule_T_786, _schedule_T_776) node _schedule_T_788 = or(_schedule_T_787, _schedule_T_777) node _schedule_T_789 = or(_schedule_T_788, _schedule_T_778) node _schedule_T_790 = or(_schedule_T_789, _schedule_T_779) node _schedule_T_791 = or(_schedule_T_790, _schedule_T_780) node _schedule_T_792 = or(_schedule_T_791, _schedule_T_781) node _schedule_T_793 = or(_schedule_T_792, _schedule_T_782) wire _schedule_WIRE_45 : UInt<3> connect _schedule_WIRE_45, _schedule_T_793 connect _schedule_WIRE_39.param, _schedule_WIRE_45 node _schedule_T_794 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_795 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_796 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_797 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_798 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_799 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_800 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_801 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_802 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_803 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_804 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_805 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.bits.opcode, UInt<1>(0h0)) node _schedule_T_806 = or(_schedule_T_794, _schedule_T_795) node _schedule_T_807 = or(_schedule_T_806, _schedule_T_796) node _schedule_T_808 = or(_schedule_T_807, _schedule_T_797) node _schedule_T_809 = or(_schedule_T_808, _schedule_T_798) node _schedule_T_810 = or(_schedule_T_809, _schedule_T_799) node _schedule_T_811 = or(_schedule_T_810, _schedule_T_800) node _schedule_T_812 = or(_schedule_T_811, _schedule_T_801) node _schedule_T_813 = or(_schedule_T_812, _schedule_T_802) node _schedule_T_814 = or(_schedule_T_813, _schedule_T_803) node _schedule_T_815 = or(_schedule_T_814, _schedule_T_804) node _schedule_T_816 = or(_schedule_T_815, _schedule_T_805) wire _schedule_WIRE_46 : UInt<3> connect _schedule_WIRE_46, _schedule_T_816 connect _schedule_WIRE_39.opcode, _schedule_WIRE_46 connect _schedule_WIRE_38.bits, _schedule_WIRE_39 node _schedule_T_817 = mux(_schedule_T, mshrs_0.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_818 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_819 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_820 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_821 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_822 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_823 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_824 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_825 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_826 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_827 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_828 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.c.valid, UInt<1>(0h0)) node _schedule_T_829 = or(_schedule_T_817, _schedule_T_818) node _schedule_T_830 = or(_schedule_T_829, _schedule_T_819) node _schedule_T_831 = or(_schedule_T_830, _schedule_T_820) node _schedule_T_832 = or(_schedule_T_831, _schedule_T_821) node _schedule_T_833 = or(_schedule_T_832, _schedule_T_822) node _schedule_T_834 = or(_schedule_T_833, _schedule_T_823) node _schedule_T_835 = or(_schedule_T_834, _schedule_T_824) node _schedule_T_836 = or(_schedule_T_835, _schedule_T_825) node _schedule_T_837 = or(_schedule_T_836, _schedule_T_826) node _schedule_T_838 = or(_schedule_T_837, _schedule_T_827) node _schedule_T_839 = or(_schedule_T_838, _schedule_T_828) wire _schedule_WIRE_47 : UInt<1> connect _schedule_WIRE_47, _schedule_T_839 connect _schedule_WIRE_38.valid, _schedule_WIRE_47 connect schedule.c, _schedule_WIRE_38 wire _schedule_WIRE_48 : { valid : UInt<1>, bits : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>}} wire _schedule_WIRE_49 : { param : UInt<3>, tag : UInt<9>, set : UInt<11>, clients : UInt<1>} node _schedule_T_840 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_841 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_842 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_843 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_844 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_845 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_846 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_847 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_848 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_849 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_850 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_851 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.clients, UInt<1>(0h0)) node _schedule_T_852 = or(_schedule_T_840, _schedule_T_841) node _schedule_T_853 = or(_schedule_T_852, _schedule_T_842) node _schedule_T_854 = or(_schedule_T_853, _schedule_T_843) node _schedule_T_855 = or(_schedule_T_854, _schedule_T_844) node _schedule_T_856 = or(_schedule_T_855, _schedule_T_845) node _schedule_T_857 = or(_schedule_T_856, _schedule_T_846) node _schedule_T_858 = or(_schedule_T_857, _schedule_T_847) node _schedule_T_859 = or(_schedule_T_858, _schedule_T_848) node _schedule_T_860 = or(_schedule_T_859, _schedule_T_849) node _schedule_T_861 = or(_schedule_T_860, _schedule_T_850) node _schedule_T_862 = or(_schedule_T_861, _schedule_T_851) wire _schedule_WIRE_50 : UInt<1> connect _schedule_WIRE_50, _schedule_T_862 connect _schedule_WIRE_49.clients, _schedule_WIRE_50 node _schedule_T_863 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_864 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_865 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_866 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_867 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_868 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_869 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_870 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_871 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_872 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_873 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_874 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.set, UInt<1>(0h0)) node _schedule_T_875 = or(_schedule_T_863, _schedule_T_864) node _schedule_T_876 = or(_schedule_T_875, _schedule_T_865) node _schedule_T_877 = or(_schedule_T_876, _schedule_T_866) node _schedule_T_878 = or(_schedule_T_877, _schedule_T_867) node _schedule_T_879 = or(_schedule_T_878, _schedule_T_868) node _schedule_T_880 = or(_schedule_T_879, _schedule_T_869) node _schedule_T_881 = or(_schedule_T_880, _schedule_T_870) node _schedule_T_882 = or(_schedule_T_881, _schedule_T_871) node _schedule_T_883 = or(_schedule_T_882, _schedule_T_872) node _schedule_T_884 = or(_schedule_T_883, _schedule_T_873) node _schedule_T_885 = or(_schedule_T_884, _schedule_T_874) wire _schedule_WIRE_51 : UInt<11> connect _schedule_WIRE_51, _schedule_T_885 connect _schedule_WIRE_49.set, _schedule_WIRE_51 node _schedule_T_886 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_887 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_888 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_889 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_890 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_891 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_892 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_893 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_894 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_895 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_896 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_897 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.tag, UInt<1>(0h0)) node _schedule_T_898 = or(_schedule_T_886, _schedule_T_887) node _schedule_T_899 = or(_schedule_T_898, _schedule_T_888) node _schedule_T_900 = or(_schedule_T_899, _schedule_T_889) node _schedule_T_901 = or(_schedule_T_900, _schedule_T_890) node _schedule_T_902 = or(_schedule_T_901, _schedule_T_891) node _schedule_T_903 = or(_schedule_T_902, _schedule_T_892) node _schedule_T_904 = or(_schedule_T_903, _schedule_T_893) node _schedule_T_905 = or(_schedule_T_904, _schedule_T_894) node _schedule_T_906 = or(_schedule_T_905, _schedule_T_895) node _schedule_T_907 = or(_schedule_T_906, _schedule_T_896) node _schedule_T_908 = or(_schedule_T_907, _schedule_T_897) wire _schedule_WIRE_52 : UInt<9> connect _schedule_WIRE_52, _schedule_T_908 connect _schedule_WIRE_49.tag, _schedule_WIRE_52 node _schedule_T_909 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_910 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_911 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_912 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_913 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_914 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_915 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_916 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_917 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_918 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_919 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_920 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.bits.param, UInt<1>(0h0)) node _schedule_T_921 = or(_schedule_T_909, _schedule_T_910) node _schedule_T_922 = or(_schedule_T_921, _schedule_T_911) node _schedule_T_923 = or(_schedule_T_922, _schedule_T_912) node _schedule_T_924 = or(_schedule_T_923, _schedule_T_913) node _schedule_T_925 = or(_schedule_T_924, _schedule_T_914) node _schedule_T_926 = or(_schedule_T_925, _schedule_T_915) node _schedule_T_927 = or(_schedule_T_926, _schedule_T_916) node _schedule_T_928 = or(_schedule_T_927, _schedule_T_917) node _schedule_T_929 = or(_schedule_T_928, _schedule_T_918) node _schedule_T_930 = or(_schedule_T_929, _schedule_T_919) node _schedule_T_931 = or(_schedule_T_930, _schedule_T_920) wire _schedule_WIRE_53 : UInt<3> connect _schedule_WIRE_53, _schedule_T_931 connect _schedule_WIRE_49.param, _schedule_WIRE_53 connect _schedule_WIRE_48.bits, _schedule_WIRE_49 node _schedule_T_932 = mux(_schedule_T, mshrs_0.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_933 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_934 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_935 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_936 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_937 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_938 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_939 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_940 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_941 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_942 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_943 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.b.valid, UInt<1>(0h0)) node _schedule_T_944 = or(_schedule_T_932, _schedule_T_933) node _schedule_T_945 = or(_schedule_T_944, _schedule_T_934) node _schedule_T_946 = or(_schedule_T_945, _schedule_T_935) node _schedule_T_947 = or(_schedule_T_946, _schedule_T_936) node _schedule_T_948 = or(_schedule_T_947, _schedule_T_937) node _schedule_T_949 = or(_schedule_T_948, _schedule_T_938) node _schedule_T_950 = or(_schedule_T_949, _schedule_T_939) node _schedule_T_951 = or(_schedule_T_950, _schedule_T_940) node _schedule_T_952 = or(_schedule_T_951, _schedule_T_941) node _schedule_T_953 = or(_schedule_T_952, _schedule_T_942) node _schedule_T_954 = or(_schedule_T_953, _schedule_T_943) wire _schedule_WIRE_54 : UInt<1> connect _schedule_WIRE_54, _schedule_T_954 connect _schedule_WIRE_48.valid, _schedule_WIRE_54 connect schedule.b, _schedule_WIRE_48 wire _schedule_WIRE_55 : { valid : UInt<1>, bits : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>}} wire _schedule_WIRE_56 : { tag : UInt<9>, set : UInt<11>, param : UInt<3>, source : UInt<4>, block : UInt<1>} node _schedule_T_955 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_956 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_957 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_958 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_959 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_960 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_961 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_962 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_963 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_964 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_965 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_966 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.block, UInt<1>(0h0)) node _schedule_T_967 = or(_schedule_T_955, _schedule_T_956) node _schedule_T_968 = or(_schedule_T_967, _schedule_T_957) node _schedule_T_969 = or(_schedule_T_968, _schedule_T_958) node _schedule_T_970 = or(_schedule_T_969, _schedule_T_959) node _schedule_T_971 = or(_schedule_T_970, _schedule_T_960) node _schedule_T_972 = or(_schedule_T_971, _schedule_T_961) node _schedule_T_973 = or(_schedule_T_972, _schedule_T_962) node _schedule_T_974 = or(_schedule_T_973, _schedule_T_963) node _schedule_T_975 = or(_schedule_T_974, _schedule_T_964) node _schedule_T_976 = or(_schedule_T_975, _schedule_T_965) node _schedule_T_977 = or(_schedule_T_976, _schedule_T_966) wire _schedule_WIRE_57 : UInt<1> connect _schedule_WIRE_57, _schedule_T_977 connect _schedule_WIRE_56.block, _schedule_WIRE_57 node _schedule_T_978 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_979 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_980 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_981 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_982 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_983 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_984 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_985 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_986 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_987 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_988 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_989 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.source, UInt<1>(0h0)) node _schedule_T_990 = or(_schedule_T_978, _schedule_T_979) node _schedule_T_991 = or(_schedule_T_990, _schedule_T_980) node _schedule_T_992 = or(_schedule_T_991, _schedule_T_981) node _schedule_T_993 = or(_schedule_T_992, _schedule_T_982) node _schedule_T_994 = or(_schedule_T_993, _schedule_T_983) node _schedule_T_995 = or(_schedule_T_994, _schedule_T_984) node _schedule_T_996 = or(_schedule_T_995, _schedule_T_985) node _schedule_T_997 = or(_schedule_T_996, _schedule_T_986) node _schedule_T_998 = or(_schedule_T_997, _schedule_T_987) node _schedule_T_999 = or(_schedule_T_998, _schedule_T_988) node _schedule_T_1000 = or(_schedule_T_999, _schedule_T_989) wire _schedule_WIRE_58 : UInt<4> connect _schedule_WIRE_58, _schedule_T_1000 connect _schedule_WIRE_56.source, _schedule_WIRE_58 node _schedule_T_1001 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1002 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1003 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1004 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1005 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1006 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1007 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1008 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1009 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1010 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1011 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1012 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.param, UInt<1>(0h0)) node _schedule_T_1013 = or(_schedule_T_1001, _schedule_T_1002) node _schedule_T_1014 = or(_schedule_T_1013, _schedule_T_1003) node _schedule_T_1015 = or(_schedule_T_1014, _schedule_T_1004) node _schedule_T_1016 = or(_schedule_T_1015, _schedule_T_1005) node _schedule_T_1017 = or(_schedule_T_1016, _schedule_T_1006) node _schedule_T_1018 = or(_schedule_T_1017, _schedule_T_1007) node _schedule_T_1019 = or(_schedule_T_1018, _schedule_T_1008) node _schedule_T_1020 = or(_schedule_T_1019, _schedule_T_1009) node _schedule_T_1021 = or(_schedule_T_1020, _schedule_T_1010) node _schedule_T_1022 = or(_schedule_T_1021, _schedule_T_1011) node _schedule_T_1023 = or(_schedule_T_1022, _schedule_T_1012) wire _schedule_WIRE_59 : UInt<3> connect _schedule_WIRE_59, _schedule_T_1023 connect _schedule_WIRE_56.param, _schedule_WIRE_59 node _schedule_T_1024 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1025 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1026 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1027 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1028 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1029 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1030 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1031 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1032 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1033 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1034 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1035 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.set, UInt<1>(0h0)) node _schedule_T_1036 = or(_schedule_T_1024, _schedule_T_1025) node _schedule_T_1037 = or(_schedule_T_1036, _schedule_T_1026) node _schedule_T_1038 = or(_schedule_T_1037, _schedule_T_1027) node _schedule_T_1039 = or(_schedule_T_1038, _schedule_T_1028) node _schedule_T_1040 = or(_schedule_T_1039, _schedule_T_1029) node _schedule_T_1041 = or(_schedule_T_1040, _schedule_T_1030) node _schedule_T_1042 = or(_schedule_T_1041, _schedule_T_1031) node _schedule_T_1043 = or(_schedule_T_1042, _schedule_T_1032) node _schedule_T_1044 = or(_schedule_T_1043, _schedule_T_1033) node _schedule_T_1045 = or(_schedule_T_1044, _schedule_T_1034) node _schedule_T_1046 = or(_schedule_T_1045, _schedule_T_1035) wire _schedule_WIRE_60 : UInt<11> connect _schedule_WIRE_60, _schedule_T_1046 connect _schedule_WIRE_56.set, _schedule_WIRE_60 node _schedule_T_1047 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1048 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1049 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1050 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1051 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1052 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1053 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1054 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1055 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1056 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1057 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1058 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.bits.tag, UInt<1>(0h0)) node _schedule_T_1059 = or(_schedule_T_1047, _schedule_T_1048) node _schedule_T_1060 = or(_schedule_T_1059, _schedule_T_1049) node _schedule_T_1061 = or(_schedule_T_1060, _schedule_T_1050) node _schedule_T_1062 = or(_schedule_T_1061, _schedule_T_1051) node _schedule_T_1063 = or(_schedule_T_1062, _schedule_T_1052) node _schedule_T_1064 = or(_schedule_T_1063, _schedule_T_1053) node _schedule_T_1065 = or(_schedule_T_1064, _schedule_T_1054) node _schedule_T_1066 = or(_schedule_T_1065, _schedule_T_1055) node _schedule_T_1067 = or(_schedule_T_1066, _schedule_T_1056) node _schedule_T_1068 = or(_schedule_T_1067, _schedule_T_1057) node _schedule_T_1069 = or(_schedule_T_1068, _schedule_T_1058) wire _schedule_WIRE_61 : UInt<9> connect _schedule_WIRE_61, _schedule_T_1069 connect _schedule_WIRE_56.tag, _schedule_WIRE_61 connect _schedule_WIRE_55.bits, _schedule_WIRE_56 node _schedule_T_1070 = mux(_schedule_T, mshrs_0.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1071 = mux(_schedule_T_1, mshrs_1.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1072 = mux(_schedule_T_2, mshrs_2.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1073 = mux(_schedule_T_3, mshrs_3.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1074 = mux(_schedule_T_4, mshrs_4.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1075 = mux(_schedule_T_5, mshrs_5.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1076 = mux(_schedule_T_6, mshrs_6.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1077 = mux(_schedule_T_7, mshrs_7.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1078 = mux(_schedule_T_8, mshrs_8.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1079 = mux(_schedule_T_9, mshrs_9.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1080 = mux(_schedule_T_10, mshrs_10.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1081 = mux(_schedule_T_11, mshrs_11.io.schedule.bits.a.valid, UInt<1>(0h0)) node _schedule_T_1082 = or(_schedule_T_1070, _schedule_T_1071) node _schedule_T_1083 = or(_schedule_T_1082, _schedule_T_1072) node _schedule_T_1084 = or(_schedule_T_1083, _schedule_T_1073) node _schedule_T_1085 = or(_schedule_T_1084, _schedule_T_1074) node _schedule_T_1086 = or(_schedule_T_1085, _schedule_T_1075) node _schedule_T_1087 = or(_schedule_T_1086, _schedule_T_1076) node _schedule_T_1088 = or(_schedule_T_1087, _schedule_T_1077) node _schedule_T_1089 = or(_schedule_T_1088, _schedule_T_1078) node _schedule_T_1090 = or(_schedule_T_1089, _schedule_T_1079) node _schedule_T_1091 = or(_schedule_T_1090, _schedule_T_1080) node _schedule_T_1092 = or(_schedule_T_1091, _schedule_T_1081) wire _schedule_WIRE_62 : UInt<1> connect _schedule_WIRE_62, _schedule_T_1092 connect _schedule_WIRE_55.valid, _schedule_WIRE_62 connect schedule.a, _schedule_WIRE_55 node _scheduleTag_T = bits(mshr_selectOH, 0, 0) node _scheduleTag_T_1 = bits(mshr_selectOH, 1, 1) node _scheduleTag_T_2 = bits(mshr_selectOH, 2, 2) node _scheduleTag_T_3 = bits(mshr_selectOH, 3, 3) node _scheduleTag_T_4 = bits(mshr_selectOH, 4, 4) node _scheduleTag_T_5 = bits(mshr_selectOH, 5, 5) node _scheduleTag_T_6 = bits(mshr_selectOH, 6, 6) node _scheduleTag_T_7 = bits(mshr_selectOH, 7, 7) node _scheduleTag_T_8 = bits(mshr_selectOH, 8, 8) node _scheduleTag_T_9 = bits(mshr_selectOH, 9, 9) node _scheduleTag_T_10 = bits(mshr_selectOH, 10, 10) node _scheduleTag_T_11 = bits(mshr_selectOH, 11, 11) node _scheduleTag_T_12 = mux(_scheduleTag_T, mshrs_0.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_13 = mux(_scheduleTag_T_1, mshrs_1.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_14 = mux(_scheduleTag_T_2, mshrs_2.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_15 = mux(_scheduleTag_T_3, mshrs_3.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_16 = mux(_scheduleTag_T_4, mshrs_4.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_17 = mux(_scheduleTag_T_5, mshrs_5.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_18 = mux(_scheduleTag_T_6, mshrs_6.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_19 = mux(_scheduleTag_T_7, mshrs_7.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_20 = mux(_scheduleTag_T_8, mshrs_8.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_21 = mux(_scheduleTag_T_9, mshrs_9.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_22 = mux(_scheduleTag_T_10, mshrs_10.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_23 = mux(_scheduleTag_T_11, mshrs_11.io.status.bits.tag, UInt<1>(0h0)) node _scheduleTag_T_24 = or(_scheduleTag_T_12, _scheduleTag_T_13) node _scheduleTag_T_25 = or(_scheduleTag_T_24, _scheduleTag_T_14) node _scheduleTag_T_26 = or(_scheduleTag_T_25, _scheduleTag_T_15) node _scheduleTag_T_27 = or(_scheduleTag_T_26, _scheduleTag_T_16) node _scheduleTag_T_28 = or(_scheduleTag_T_27, _scheduleTag_T_17) node _scheduleTag_T_29 = or(_scheduleTag_T_28, _scheduleTag_T_18) node _scheduleTag_T_30 = or(_scheduleTag_T_29, _scheduleTag_T_19) node _scheduleTag_T_31 = or(_scheduleTag_T_30, _scheduleTag_T_20) node _scheduleTag_T_32 = or(_scheduleTag_T_31, _scheduleTag_T_21) node _scheduleTag_T_33 = or(_scheduleTag_T_32, _scheduleTag_T_22) node _scheduleTag_T_34 = or(_scheduleTag_T_33, _scheduleTag_T_23) wire scheduleTag : UInt<9> connect scheduleTag, _scheduleTag_T_34 node _scheduleSet_T = bits(mshr_selectOH, 0, 0) node _scheduleSet_T_1 = bits(mshr_selectOH, 1, 1) node _scheduleSet_T_2 = bits(mshr_selectOH, 2, 2) node _scheduleSet_T_3 = bits(mshr_selectOH, 3, 3) node _scheduleSet_T_4 = bits(mshr_selectOH, 4, 4) node _scheduleSet_T_5 = bits(mshr_selectOH, 5, 5) node _scheduleSet_T_6 = bits(mshr_selectOH, 6, 6) node _scheduleSet_T_7 = bits(mshr_selectOH, 7, 7) node _scheduleSet_T_8 = bits(mshr_selectOH, 8, 8) node _scheduleSet_T_9 = bits(mshr_selectOH, 9, 9) node _scheduleSet_T_10 = bits(mshr_selectOH, 10, 10) node _scheduleSet_T_11 = bits(mshr_selectOH, 11, 11) node _scheduleSet_T_12 = mux(_scheduleSet_T, mshrs_0.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_13 = mux(_scheduleSet_T_1, mshrs_1.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_14 = mux(_scheduleSet_T_2, mshrs_2.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_15 = mux(_scheduleSet_T_3, mshrs_3.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_16 = mux(_scheduleSet_T_4, mshrs_4.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_17 = mux(_scheduleSet_T_5, mshrs_5.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_18 = mux(_scheduleSet_T_6, mshrs_6.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_19 = mux(_scheduleSet_T_7, mshrs_7.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_20 = mux(_scheduleSet_T_8, mshrs_8.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_21 = mux(_scheduleSet_T_9, mshrs_9.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_22 = mux(_scheduleSet_T_10, mshrs_10.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_23 = mux(_scheduleSet_T_11, mshrs_11.io.status.bits.set, UInt<1>(0h0)) node _scheduleSet_T_24 = or(_scheduleSet_T_12, _scheduleSet_T_13) node _scheduleSet_T_25 = or(_scheduleSet_T_24, _scheduleSet_T_14) node _scheduleSet_T_26 = or(_scheduleSet_T_25, _scheduleSet_T_15) node _scheduleSet_T_27 = or(_scheduleSet_T_26, _scheduleSet_T_16) node _scheduleSet_T_28 = or(_scheduleSet_T_27, _scheduleSet_T_17) node _scheduleSet_T_29 = or(_scheduleSet_T_28, _scheduleSet_T_18) node _scheduleSet_T_30 = or(_scheduleSet_T_29, _scheduleSet_T_19) node _scheduleSet_T_31 = or(_scheduleSet_T_30, _scheduleSet_T_20) node _scheduleSet_T_32 = or(_scheduleSet_T_31, _scheduleSet_T_21) node _scheduleSet_T_33 = or(_scheduleSet_T_32, _scheduleSet_T_22) node _scheduleSet_T_34 = or(_scheduleSet_T_33, _scheduleSet_T_23) wire scheduleSet : UInt<11> connect scheduleSet, _scheduleSet_T_34 node _T_9 = orr(mshr_request) when _T_9 : node _robin_filter_T = shr(mshr_selectOH, 1) node _robin_filter_T_1 = or(mshr_selectOH, _robin_filter_T) node _robin_filter_T_2 = shr(_robin_filter_T_1, 2) node _robin_filter_T_3 = or(_robin_filter_T_1, _robin_filter_T_2) node _robin_filter_T_4 = shr(_robin_filter_T_3, 4) node _robin_filter_T_5 = or(_robin_filter_T_3, _robin_filter_T_4) node _robin_filter_T_6 = shr(_robin_filter_T_5, 8) node _robin_filter_T_7 = or(_robin_filter_T_5, _robin_filter_T_6) node _robin_filter_T_8 = bits(_robin_filter_T_7, 11, 0) node _robin_filter_T_9 = not(_robin_filter_T_8) connect robin_filter, _robin_filter_T_9 connect schedule.a.bits.source, mshr_select node _schedule_c_bits_source_T = bits(schedule.c.bits.opcode, 1, 1) node _schedule_c_bits_source_T_1 = mux(_schedule_c_bits_source_T, mshr_select, UInt<1>(0h0)) connect schedule.c.bits.source, _schedule_c_bits_source_T_1 connect schedule.d.bits.sink, mshr_select connect sourceA.io.req.valid, schedule.a.valid connect sourceB.io.req.valid, schedule.b.valid connect sourceC.io.req.valid, schedule.c.valid connect sourceD.io.req.valid, schedule.d.valid connect sourceE.io.req.valid, schedule.e.valid connect sourceX.io.req.valid, schedule.x.valid connect sourceA.io.req.bits.block, schedule.a.bits.block connect sourceA.io.req.bits.source, schedule.a.bits.source connect sourceA.io.req.bits.param, schedule.a.bits.param connect sourceA.io.req.bits.set, schedule.a.bits.set connect sourceA.io.req.bits.tag, schedule.a.bits.tag connect sourceB.io.req.bits.clients, schedule.b.bits.clients connect sourceB.io.req.bits.set, schedule.b.bits.set connect sourceB.io.req.bits.tag, schedule.b.bits.tag connect sourceB.io.req.bits.param, schedule.b.bits.param connect sourceC.io.req.bits.dirty, schedule.c.bits.dirty connect sourceC.io.req.bits.way, schedule.c.bits.way connect sourceC.io.req.bits.set, schedule.c.bits.set connect sourceC.io.req.bits.tag, schedule.c.bits.tag connect sourceC.io.req.bits.source, schedule.c.bits.source connect sourceC.io.req.bits.param, schedule.c.bits.param connect sourceC.io.req.bits.opcode, schedule.c.bits.opcode connect sourceD.io.req.bits.bad, schedule.d.bits.bad connect sourceD.io.req.bits.way, schedule.d.bits.way connect sourceD.io.req.bits.sink, schedule.d.bits.sink connect sourceD.io.req.bits.set, schedule.d.bits.set connect sourceD.io.req.bits.put, schedule.d.bits.put connect sourceD.io.req.bits.offset, schedule.d.bits.offset connect sourceD.io.req.bits.tag, schedule.d.bits.tag connect sourceD.io.req.bits.source, schedule.d.bits.source connect sourceD.io.req.bits.size, schedule.d.bits.size connect sourceD.io.req.bits.param, schedule.d.bits.param connect sourceD.io.req.bits.opcode, schedule.d.bits.opcode connect sourceD.io.req.bits.control, schedule.d.bits.control connect sourceD.io.req.bits.prio[0], schedule.d.bits.prio[0] connect sourceD.io.req.bits.prio[1], schedule.d.bits.prio[1] connect sourceD.io.req.bits.prio[2], schedule.d.bits.prio[2] connect sourceE.io.req.bits.sink, schedule.e.bits.sink connect sourceX.io.req.bits.fail, schedule.x.bits.fail connect directory.io.write.valid, schedule.dir.valid connect directory.io.write.bits.data.tag, schedule.dir.bits.data.tag connect directory.io.write.bits.data.clients, schedule.dir.bits.data.clients connect directory.io.write.bits.data.state, schedule.dir.bits.data.state connect directory.io.write.bits.data.dirty, schedule.dir.bits.data.dirty connect directory.io.write.bits.way, schedule.dir.bits.way connect directory.io.write.bits.set, schedule.dir.bits.set node select_c = bits(mshr_selectOH, 11, 11) node select_bc = bits(mshr_selectOH, 10, 10) node _nestedwb_set_T = mux(select_c, mshrs_11.io.status.bits.set, mshrs_10.io.status.bits.set) connect nestedwb.set, _nestedwb_set_T node _nestedwb_tag_T = mux(select_c, mshrs_11.io.status.bits.tag, mshrs_10.io.status.bits.tag) connect nestedwb.tag, _nestedwb_tag_T node _nestedwb_b_toN_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid) node _nestedwb_b_toN_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h0)) node _nestedwb_b_toN_T_2 = and(_nestedwb_b_toN_T, _nestedwb_b_toN_T_1) connect nestedwb.b_toN, _nestedwb_b_toN_T_2 node _nestedwb_b_toB_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid) node _nestedwb_b_toB_T_1 = eq(mshrs_10.io.schedule.bits.dir.bits.data.state, UInt<2>(0h1)) node _nestedwb_b_toB_T_2 = and(_nestedwb_b_toB_T, _nestedwb_b_toB_T_1) connect nestedwb.b_toB, _nestedwb_b_toB_T_2 node _nestedwb_b_clr_dirty_T = and(select_bc, mshrs_10.io.schedule.bits.dir.valid) connect nestedwb.b_clr_dirty, _nestedwb_b_clr_dirty_T node _nestedwb_c_set_dirty_T = and(select_c, mshrs_11.io.schedule.bits.dir.valid) node _nestedwb_c_set_dirty_T_1 = and(_nestedwb_c_set_dirty_T, mshrs_11.io.schedule.bits.dir.bits.data.dirty) connect nestedwb.c_set_dirty, _nestedwb_c_set_dirty_T_1 wire request : { flip ready : UInt<1>, valid : UInt<1>, bits : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>, set : UInt<11>}} node _request_valid_T = or(sinkA.io.req.valid, sinkX.io.req.valid) node _request_valid_T_1 = or(_request_valid_T, sinkC.io.req.valid) node _request_valid_T_2 = and(directory.io.ready, _request_valid_T_1) connect request.valid, _request_valid_T_2 node _request_bits_T = mux(sinkX.io.req.valid, sinkX.io.req.bits, sinkA.io.req.bits) node _request_bits_T_1 = mux(sinkC.io.req.valid, sinkC.io.req.bits, _request_bits_T) connect request.bits, _request_bits_T_1 node _sinkC_io_req_ready_T = and(directory.io.ready, request.ready) connect sinkC.io.req.ready, _sinkC_io_req_ready_T node _sinkX_io_req_ready_T = and(directory.io.ready, request.ready) node _sinkX_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0)) node _sinkX_io_req_ready_T_2 = and(_sinkX_io_req_ready_T, _sinkX_io_req_ready_T_1) connect sinkX.io.req.ready, _sinkX_io_req_ready_T_2 node _sinkA_io_req_ready_T = and(directory.io.ready, request.ready) node _sinkA_io_req_ready_T_1 = eq(sinkC.io.req.valid, UInt<1>(0h0)) node _sinkA_io_req_ready_T_2 = and(_sinkA_io_req_ready_T, _sinkA_io_req_ready_T_1) node _sinkA_io_req_ready_T_3 = eq(sinkX.io.req.valid, UInt<1>(0h0)) node _sinkA_io_req_ready_T_4 = and(_sinkA_io_req_ready_T_2, _sinkA_io_req_ready_T_3) connect sinkA.io.req.ready, _sinkA_io_req_ready_T_4 node _setMatches_T = eq(mshrs_0.io.status.bits.set, request.bits.set) node _setMatches_T_1 = and(mshrs_0.io.status.valid, _setMatches_T) node _setMatches_T_2 = eq(mshrs_1.io.status.bits.set, request.bits.set) node _setMatches_T_3 = and(mshrs_1.io.status.valid, _setMatches_T_2) node _setMatches_T_4 = eq(mshrs_2.io.status.bits.set, request.bits.set) node _setMatches_T_5 = and(mshrs_2.io.status.valid, _setMatches_T_4) node _setMatches_T_6 = eq(mshrs_3.io.status.bits.set, request.bits.set) node _setMatches_T_7 = and(mshrs_3.io.status.valid, _setMatches_T_6) node _setMatches_T_8 = eq(mshrs_4.io.status.bits.set, request.bits.set) node _setMatches_T_9 = and(mshrs_4.io.status.valid, _setMatches_T_8) node _setMatches_T_10 = eq(mshrs_5.io.status.bits.set, request.bits.set) node _setMatches_T_11 = and(mshrs_5.io.status.valid, _setMatches_T_10) node _setMatches_T_12 = eq(mshrs_6.io.status.bits.set, request.bits.set) node _setMatches_T_13 = and(mshrs_6.io.status.valid, _setMatches_T_12) node _setMatches_T_14 = eq(mshrs_7.io.status.bits.set, request.bits.set) node _setMatches_T_15 = and(mshrs_7.io.status.valid, _setMatches_T_14) node _setMatches_T_16 = eq(mshrs_8.io.status.bits.set, request.bits.set) node _setMatches_T_17 = and(mshrs_8.io.status.valid, _setMatches_T_16) node _setMatches_T_18 = eq(mshrs_9.io.status.bits.set, request.bits.set) node _setMatches_T_19 = and(mshrs_9.io.status.valid, _setMatches_T_18) node _setMatches_T_20 = eq(mshrs_10.io.status.bits.set, request.bits.set) node _setMatches_T_21 = and(mshrs_10.io.status.valid, _setMatches_T_20) node _setMatches_T_22 = eq(mshrs_11.io.status.bits.set, request.bits.set) node _setMatches_T_23 = and(mshrs_11.io.status.valid, _setMatches_T_22) node setMatches_lo_lo_hi = cat(_setMatches_T_5, _setMatches_T_3) node setMatches_lo_lo = cat(setMatches_lo_lo_hi, _setMatches_T_1) node setMatches_lo_hi_hi = cat(_setMatches_T_11, _setMatches_T_9) node setMatches_lo_hi = cat(setMatches_lo_hi_hi, _setMatches_T_7) node setMatches_lo = cat(setMatches_lo_hi, setMatches_lo_lo) node setMatches_hi_lo_hi = cat(_setMatches_T_17, _setMatches_T_15) node setMatches_hi_lo = cat(setMatches_hi_lo_hi, _setMatches_T_13) node setMatches_hi_hi_hi = cat(_setMatches_T_23, _setMatches_T_21) node setMatches_hi_hi = cat(setMatches_hi_hi_hi, _setMatches_T_19) node setMatches_hi = cat(setMatches_hi_hi, setMatches_hi_lo) node setMatches = cat(setMatches_hi, setMatches_lo) node _alloc_T = orr(setMatches) node alloc = eq(_alloc_T, UInt<1>(0h0)) node _blockB_T = bits(setMatches, 0, 0) node _blockB_T_1 = bits(setMatches, 1, 1) node _blockB_T_2 = bits(setMatches, 2, 2) node _blockB_T_3 = bits(setMatches, 3, 3) node _blockB_T_4 = bits(setMatches, 4, 4) node _blockB_T_5 = bits(setMatches, 5, 5) node _blockB_T_6 = bits(setMatches, 6, 6) node _blockB_T_7 = bits(setMatches, 7, 7) node _blockB_T_8 = bits(setMatches, 8, 8) node _blockB_T_9 = bits(setMatches, 9, 9) node _blockB_T_10 = bits(setMatches, 10, 10) node _blockB_T_11 = bits(setMatches, 11, 11) node _blockB_T_12 = mux(_blockB_T, mshrs_0.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_13 = mux(_blockB_T_1, mshrs_1.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_14 = mux(_blockB_T_2, mshrs_2.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_15 = mux(_blockB_T_3, mshrs_3.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_16 = mux(_blockB_T_4, mshrs_4.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_17 = mux(_blockB_T_5, mshrs_5.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_18 = mux(_blockB_T_6, mshrs_6.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_19 = mux(_blockB_T_7, mshrs_7.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_20 = mux(_blockB_T_8, mshrs_8.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_21 = mux(_blockB_T_9, mshrs_9.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_22 = mux(_blockB_T_10, mshrs_10.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_23 = mux(_blockB_T_11, mshrs_11.io.status.bits.blockB, UInt<1>(0h0)) node _blockB_T_24 = or(_blockB_T_12, _blockB_T_13) node _blockB_T_25 = or(_blockB_T_24, _blockB_T_14) node _blockB_T_26 = or(_blockB_T_25, _blockB_T_15) node _blockB_T_27 = or(_blockB_T_26, _blockB_T_16) node _blockB_T_28 = or(_blockB_T_27, _blockB_T_17) node _blockB_T_29 = or(_blockB_T_28, _blockB_T_18) node _blockB_T_30 = or(_blockB_T_29, _blockB_T_19) node _blockB_T_31 = or(_blockB_T_30, _blockB_T_20) node _blockB_T_32 = or(_blockB_T_31, _blockB_T_21) node _blockB_T_33 = or(_blockB_T_32, _blockB_T_22) node _blockB_T_34 = or(_blockB_T_33, _blockB_T_23) wire _blockB_WIRE : UInt<1> connect _blockB_WIRE, _blockB_T_34 node blockB = and(_blockB_WIRE, request.bits.prio[1]) node _blockC_T = bits(setMatches, 0, 0) node _blockC_T_1 = bits(setMatches, 1, 1) node _blockC_T_2 = bits(setMatches, 2, 2) node _blockC_T_3 = bits(setMatches, 3, 3) node _blockC_T_4 = bits(setMatches, 4, 4) node _blockC_T_5 = bits(setMatches, 5, 5) node _blockC_T_6 = bits(setMatches, 6, 6) node _blockC_T_7 = bits(setMatches, 7, 7) node _blockC_T_8 = bits(setMatches, 8, 8) node _blockC_T_9 = bits(setMatches, 9, 9) node _blockC_T_10 = bits(setMatches, 10, 10) node _blockC_T_11 = bits(setMatches, 11, 11) node _blockC_T_12 = mux(_blockC_T, mshrs_0.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_13 = mux(_blockC_T_1, mshrs_1.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_14 = mux(_blockC_T_2, mshrs_2.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_15 = mux(_blockC_T_3, mshrs_3.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_16 = mux(_blockC_T_4, mshrs_4.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_17 = mux(_blockC_T_5, mshrs_5.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_18 = mux(_blockC_T_6, mshrs_6.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_19 = mux(_blockC_T_7, mshrs_7.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_20 = mux(_blockC_T_8, mshrs_8.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_21 = mux(_blockC_T_9, mshrs_9.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_22 = mux(_blockC_T_10, mshrs_10.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_23 = mux(_blockC_T_11, mshrs_11.io.status.bits.blockC, UInt<1>(0h0)) node _blockC_T_24 = or(_blockC_T_12, _blockC_T_13) node _blockC_T_25 = or(_blockC_T_24, _blockC_T_14) node _blockC_T_26 = or(_blockC_T_25, _blockC_T_15) node _blockC_T_27 = or(_blockC_T_26, _blockC_T_16) node _blockC_T_28 = or(_blockC_T_27, _blockC_T_17) node _blockC_T_29 = or(_blockC_T_28, _blockC_T_18) node _blockC_T_30 = or(_blockC_T_29, _blockC_T_19) node _blockC_T_31 = or(_blockC_T_30, _blockC_T_20) node _blockC_T_32 = or(_blockC_T_31, _blockC_T_21) node _blockC_T_33 = or(_blockC_T_32, _blockC_T_22) node _blockC_T_34 = or(_blockC_T_33, _blockC_T_23) wire _blockC_WIRE : UInt<1> connect _blockC_WIRE, _blockC_T_34 node blockC = and(_blockC_WIRE, request.bits.prio[2]) node _nestB_T = bits(setMatches, 0, 0) node _nestB_T_1 = bits(setMatches, 1, 1) node _nestB_T_2 = bits(setMatches, 2, 2) node _nestB_T_3 = bits(setMatches, 3, 3) node _nestB_T_4 = bits(setMatches, 4, 4) node _nestB_T_5 = bits(setMatches, 5, 5) node _nestB_T_6 = bits(setMatches, 6, 6) node _nestB_T_7 = bits(setMatches, 7, 7) node _nestB_T_8 = bits(setMatches, 8, 8) node _nestB_T_9 = bits(setMatches, 9, 9) node _nestB_T_10 = bits(setMatches, 10, 10) node _nestB_T_11 = bits(setMatches, 11, 11) node _nestB_T_12 = mux(_nestB_T, mshrs_0.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_13 = mux(_nestB_T_1, mshrs_1.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_14 = mux(_nestB_T_2, mshrs_2.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_15 = mux(_nestB_T_3, mshrs_3.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_16 = mux(_nestB_T_4, mshrs_4.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_17 = mux(_nestB_T_5, mshrs_5.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_18 = mux(_nestB_T_6, mshrs_6.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_19 = mux(_nestB_T_7, mshrs_7.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_20 = mux(_nestB_T_8, mshrs_8.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_21 = mux(_nestB_T_9, mshrs_9.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_22 = mux(_nestB_T_10, mshrs_10.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_23 = mux(_nestB_T_11, mshrs_11.io.status.bits.nestB, UInt<1>(0h0)) node _nestB_T_24 = or(_nestB_T_12, _nestB_T_13) node _nestB_T_25 = or(_nestB_T_24, _nestB_T_14) node _nestB_T_26 = or(_nestB_T_25, _nestB_T_15) node _nestB_T_27 = or(_nestB_T_26, _nestB_T_16) node _nestB_T_28 = or(_nestB_T_27, _nestB_T_17) node _nestB_T_29 = or(_nestB_T_28, _nestB_T_18) node _nestB_T_30 = or(_nestB_T_29, _nestB_T_19) node _nestB_T_31 = or(_nestB_T_30, _nestB_T_20) node _nestB_T_32 = or(_nestB_T_31, _nestB_T_21) node _nestB_T_33 = or(_nestB_T_32, _nestB_T_22) node _nestB_T_34 = or(_nestB_T_33, _nestB_T_23) wire _nestB_WIRE : UInt<1> connect _nestB_WIRE, _nestB_T_34 node nestB = and(_nestB_WIRE, request.bits.prio[1]) node _nestC_T = bits(setMatches, 0, 0) node _nestC_T_1 = bits(setMatches, 1, 1) node _nestC_T_2 = bits(setMatches, 2, 2) node _nestC_T_3 = bits(setMatches, 3, 3) node _nestC_T_4 = bits(setMatches, 4, 4) node _nestC_T_5 = bits(setMatches, 5, 5) node _nestC_T_6 = bits(setMatches, 6, 6) node _nestC_T_7 = bits(setMatches, 7, 7) node _nestC_T_8 = bits(setMatches, 8, 8) node _nestC_T_9 = bits(setMatches, 9, 9) node _nestC_T_10 = bits(setMatches, 10, 10) node _nestC_T_11 = bits(setMatches, 11, 11) node _nestC_T_12 = mux(_nestC_T, mshrs_0.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_13 = mux(_nestC_T_1, mshrs_1.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_14 = mux(_nestC_T_2, mshrs_2.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_15 = mux(_nestC_T_3, mshrs_3.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_16 = mux(_nestC_T_4, mshrs_4.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_17 = mux(_nestC_T_5, mshrs_5.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_18 = mux(_nestC_T_6, mshrs_6.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_19 = mux(_nestC_T_7, mshrs_7.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_20 = mux(_nestC_T_8, mshrs_8.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_21 = mux(_nestC_T_9, mshrs_9.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_22 = mux(_nestC_T_10, mshrs_10.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_23 = mux(_nestC_T_11, mshrs_11.io.status.bits.nestC, UInt<1>(0h0)) node _nestC_T_24 = or(_nestC_T_12, _nestC_T_13) node _nestC_T_25 = or(_nestC_T_24, _nestC_T_14) node _nestC_T_26 = or(_nestC_T_25, _nestC_T_15) node _nestC_T_27 = or(_nestC_T_26, _nestC_T_16) node _nestC_T_28 = or(_nestC_T_27, _nestC_T_17) node _nestC_T_29 = or(_nestC_T_28, _nestC_T_18) node _nestC_T_30 = or(_nestC_T_29, _nestC_T_19) node _nestC_T_31 = or(_nestC_T_30, _nestC_T_20) node _nestC_T_32 = or(_nestC_T_31, _nestC_T_21) node _nestC_T_33 = or(_nestC_T_32, _nestC_T_22) node _nestC_T_34 = or(_nestC_T_33, _nestC_T_23) wire _nestC_WIRE : UInt<1> connect _nestC_WIRE, _nestC_T_34 node nestC = and(_nestC_WIRE, request.bits.prio[2]) node _prioFilter_T = eq(request.bits.prio[0], UInt<1>(0h0)) node _prioFilter_T_1 = not(UInt<10>(0h0)) node prioFilter_hi = cat(request.bits.prio[2], _prioFilter_T) node prioFilter = cat(prioFilter_hi, _prioFilter_T_1) node lowerMatches = and(setMatches, prioFilter) node _queue_T = orr(lowerMatches) node _queue_T_1 = eq(nestB, UInt<1>(0h0)) node _queue_T_2 = and(_queue_T, _queue_T_1) node _queue_T_3 = eq(nestC, UInt<1>(0h0)) node _queue_T_4 = and(_queue_T_2, _queue_T_3) node _queue_T_5 = eq(blockB, UInt<1>(0h0)) node _queue_T_6 = and(_queue_T_4, _queue_T_5) node _queue_T_7 = eq(blockC, UInt<1>(0h0)) node queue = and(_queue_T_6, _queue_T_7) node _T_10 = and(request.valid, blockC) node _T_11 = and(request.valid, nestC) node _T_12 = and(request.valid, queue) node _lowerMatches1_T = bits(lowerMatches, 11, 11) node _lowerMatches1_T_1 = shl(UInt<1>(0h1), 11) node _lowerMatches1_T_2 = bits(lowerMatches, 10, 10) node _lowerMatches1_T_3 = shl(UInt<1>(0h1), 10) node _lowerMatches1_T_4 = mux(_lowerMatches1_T_2, _lowerMatches1_T_3, lowerMatches) node lowerMatches1 = mux(_lowerMatches1_T, _lowerMatches1_T_1, _lowerMatches1_T_4) node selected_requests_hi = cat(mshr_selectOH, mshr_selectOH) node _selected_requests_T = cat(selected_requests_hi, mshr_selectOH) node selected_requests = and(_selected_requests_T, requests.io.valid) node _a_pop_T = bits(selected_requests, 11, 0) node a_pop = orr(_a_pop_T) node _b_pop_T = bits(selected_requests, 23, 12) node b_pop = orr(_b_pop_T) node _c_pop_T = bits(selected_requests, 35, 24) node c_pop = orr(_c_pop_T) node _bypassMatches_T = and(mshr_selectOH, lowerMatches1) node _bypassMatches_T_1 = orr(_bypassMatches_T) node _bypassMatches_T_2 = or(c_pop, request.bits.prio[2]) node _bypassMatches_T_3 = eq(c_pop, UInt<1>(0h0)) node _bypassMatches_T_4 = or(b_pop, request.bits.prio[1]) node _bypassMatches_T_5 = eq(b_pop, UInt<1>(0h0)) node _bypassMatches_T_6 = eq(a_pop, UInt<1>(0h0)) node _bypassMatches_T_7 = mux(_bypassMatches_T_4, _bypassMatches_T_5, _bypassMatches_T_6) node _bypassMatches_T_8 = mux(_bypassMatches_T_2, _bypassMatches_T_3, _bypassMatches_T_7) node bypassMatches = and(_bypassMatches_T_1, _bypassMatches_T_8) node _may_pop_T = or(a_pop, b_pop) node may_pop = or(_may_pop_T, c_pop) node _bypass_T = and(request.valid, queue) node bypass = and(_bypass_T, bypassMatches) node _will_reload_T = or(may_pop, bypass) node will_reload = and(schedule.reload, _will_reload_T) node _will_pop_T = and(schedule.reload, may_pop) node _will_pop_T_1 = eq(bypass, UInt<1>(0h0)) node will_pop = and(_will_pop_T, _will_pop_T_1) node _T_13 = orr(mshr_selectOH) node _T_14 = and(_T_13, bypass) node _T_15 = orr(mshr_selectOH) node _T_16 = and(_T_15, will_reload) node _T_17 = orr(mshr_selectOH) node _T_18 = and(_T_17, will_pop) node sel = bits(mshr_selectOH, 0, 0) connect mshrs_0.io.schedule.ready, sel node a_pop_1 = bits(requests.io.valid, 0, 0) node b_pop_1 = bits(requests.io.valid, 12, 12) node c_pop_1 = bits(requests.io.valid, 24, 24) node _bypassMatches_T_9 = bits(lowerMatches1, 0, 0) node _bypassMatches_T_10 = or(c_pop_1, request.bits.prio[2]) node _bypassMatches_T_11 = eq(c_pop_1, UInt<1>(0h0)) node _bypassMatches_T_12 = or(b_pop_1, request.bits.prio[1]) node _bypassMatches_T_13 = eq(b_pop_1, UInt<1>(0h0)) node _bypassMatches_T_14 = eq(a_pop_1, UInt<1>(0h0)) node _bypassMatches_T_15 = mux(_bypassMatches_T_12, _bypassMatches_T_13, _bypassMatches_T_14) node _bypassMatches_T_16 = mux(_bypassMatches_T_10, _bypassMatches_T_11, _bypassMatches_T_15) node bypassMatches_1 = and(_bypassMatches_T_9, _bypassMatches_T_16) node _may_pop_T_1 = or(a_pop_1, b_pop_1) node may_pop_1 = or(_may_pop_T_1, c_pop_1) node _bypass_T_1 = and(request.valid, queue) node bypass_1 = and(_bypass_T_1, bypassMatches_1) node _will_reload_T_1 = or(may_pop_1, bypass_1) node will_reload_1 = and(mshrs_0.io.schedule.bits.reload, _will_reload_T_1) wire _view__WIRE : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE.put, request.bits.put connect _view__WIRE.offset, request.bits.offset connect _view__WIRE.tag, request.bits.tag connect _view__WIRE.source, request.bits.source connect _view__WIRE.size, request.bits.size connect _view__WIRE.param, request.bits.param connect _view__WIRE.opcode, request.bits.opcode connect _view__WIRE.control, request.bits.control connect _view__WIRE.prio, request.bits.prio node _view__T = mux(bypass_1, _view__WIRE, requests.io.data) connect mshrs_0.io.allocate.bits.put, _view__T.put connect mshrs_0.io.allocate.bits.offset, _view__T.offset connect mshrs_0.io.allocate.bits.tag, _view__T.tag connect mshrs_0.io.allocate.bits.source, _view__T.source connect mshrs_0.io.allocate.bits.size, _view__T.size connect mshrs_0.io.allocate.bits.param, _view__T.param connect mshrs_0.io.allocate.bits.opcode, _view__T.opcode connect mshrs_0.io.allocate.bits.control, _view__T.control connect mshrs_0.io.allocate.bits.prio[0], _view__T.prio[0] connect mshrs_0.io.allocate.bits.prio[1], _view__T.prio[1] connect mshrs_0.io.allocate.bits.prio[2], _view__T.prio[2] connect mshrs_0.io.allocate.bits.set, mshrs_0.io.status.bits.set node _mshrs_0_io_allocate_bits_repeat_T = eq(mshrs_0.io.allocate.bits.tag, mshrs_0.io.status.bits.tag) connect mshrs_0.io.allocate.bits.repeat, _mshrs_0_io_allocate_bits_repeat_T node _mshrs_0_io_allocate_valid_T = and(sel, will_reload_1) connect mshrs_0.io.allocate.valid, _mshrs_0_io_allocate_valid_T node sel_1 = bits(mshr_selectOH, 1, 1) connect mshrs_1.io.schedule.ready, sel_1 node a_pop_2 = bits(requests.io.valid, 1, 1) node b_pop_2 = bits(requests.io.valid, 13, 13) node c_pop_2 = bits(requests.io.valid, 25, 25) node _bypassMatches_T_17 = bits(lowerMatches1, 1, 1) node _bypassMatches_T_18 = or(c_pop_2, request.bits.prio[2]) node _bypassMatches_T_19 = eq(c_pop_2, UInt<1>(0h0)) node _bypassMatches_T_20 = or(b_pop_2, request.bits.prio[1]) node _bypassMatches_T_21 = eq(b_pop_2, UInt<1>(0h0)) node _bypassMatches_T_22 = eq(a_pop_2, UInt<1>(0h0)) node _bypassMatches_T_23 = mux(_bypassMatches_T_20, _bypassMatches_T_21, _bypassMatches_T_22) node _bypassMatches_T_24 = mux(_bypassMatches_T_18, _bypassMatches_T_19, _bypassMatches_T_23) node bypassMatches_2 = and(_bypassMatches_T_17, _bypassMatches_T_24) node _may_pop_T_2 = or(a_pop_2, b_pop_2) node may_pop_2 = or(_may_pop_T_2, c_pop_2) node _bypass_T_2 = and(request.valid, queue) node bypass_2 = and(_bypass_T_2, bypassMatches_2) node _will_reload_T_2 = or(may_pop_2, bypass_2) node will_reload_2 = and(mshrs_1.io.schedule.bits.reload, _will_reload_T_2) wire _view__WIRE_1 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_1.put, request.bits.put connect _view__WIRE_1.offset, request.bits.offset connect _view__WIRE_1.tag, request.bits.tag connect _view__WIRE_1.source, request.bits.source connect _view__WIRE_1.size, request.bits.size connect _view__WIRE_1.param, request.bits.param connect _view__WIRE_1.opcode, request.bits.opcode connect _view__WIRE_1.control, request.bits.control connect _view__WIRE_1.prio, request.bits.prio node _view__T_1 = mux(bypass_2, _view__WIRE_1, requests.io.data) connect mshrs_1.io.allocate.bits.put, _view__T_1.put connect mshrs_1.io.allocate.bits.offset, _view__T_1.offset connect mshrs_1.io.allocate.bits.tag, _view__T_1.tag connect mshrs_1.io.allocate.bits.source, _view__T_1.source connect mshrs_1.io.allocate.bits.size, _view__T_1.size connect mshrs_1.io.allocate.bits.param, _view__T_1.param connect mshrs_1.io.allocate.bits.opcode, _view__T_1.opcode connect mshrs_1.io.allocate.bits.control, _view__T_1.control connect mshrs_1.io.allocate.bits.prio[0], _view__T_1.prio[0] connect mshrs_1.io.allocate.bits.prio[1], _view__T_1.prio[1] connect mshrs_1.io.allocate.bits.prio[2], _view__T_1.prio[2] connect mshrs_1.io.allocate.bits.set, mshrs_1.io.status.bits.set node _mshrs_1_io_allocate_bits_repeat_T = eq(mshrs_1.io.allocate.bits.tag, mshrs_1.io.status.bits.tag) connect mshrs_1.io.allocate.bits.repeat, _mshrs_1_io_allocate_bits_repeat_T node _mshrs_1_io_allocate_valid_T = and(sel_1, will_reload_2) connect mshrs_1.io.allocate.valid, _mshrs_1_io_allocate_valid_T node sel_2 = bits(mshr_selectOH, 2, 2) connect mshrs_2.io.schedule.ready, sel_2 node a_pop_3 = bits(requests.io.valid, 2, 2) node b_pop_3 = bits(requests.io.valid, 14, 14) node c_pop_3 = bits(requests.io.valid, 26, 26) node _bypassMatches_T_25 = bits(lowerMatches1, 2, 2) node _bypassMatches_T_26 = or(c_pop_3, request.bits.prio[2]) node _bypassMatches_T_27 = eq(c_pop_3, UInt<1>(0h0)) node _bypassMatches_T_28 = or(b_pop_3, request.bits.prio[1]) node _bypassMatches_T_29 = eq(b_pop_3, UInt<1>(0h0)) node _bypassMatches_T_30 = eq(a_pop_3, UInt<1>(0h0)) node _bypassMatches_T_31 = mux(_bypassMatches_T_28, _bypassMatches_T_29, _bypassMatches_T_30) node _bypassMatches_T_32 = mux(_bypassMatches_T_26, _bypassMatches_T_27, _bypassMatches_T_31) node bypassMatches_3 = and(_bypassMatches_T_25, _bypassMatches_T_32) node _may_pop_T_3 = or(a_pop_3, b_pop_3) node may_pop_3 = or(_may_pop_T_3, c_pop_3) node _bypass_T_3 = and(request.valid, queue) node bypass_3 = and(_bypass_T_3, bypassMatches_3) node _will_reload_T_3 = or(may_pop_3, bypass_3) node will_reload_3 = and(mshrs_2.io.schedule.bits.reload, _will_reload_T_3) wire _view__WIRE_2 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_2.put, request.bits.put connect _view__WIRE_2.offset, request.bits.offset connect _view__WIRE_2.tag, request.bits.tag connect _view__WIRE_2.source, request.bits.source connect _view__WIRE_2.size, request.bits.size connect _view__WIRE_2.param, request.bits.param connect _view__WIRE_2.opcode, request.bits.opcode connect _view__WIRE_2.control, request.bits.control connect _view__WIRE_2.prio, request.bits.prio node _view__T_2 = mux(bypass_3, _view__WIRE_2, requests.io.data) connect mshrs_2.io.allocate.bits.put, _view__T_2.put connect mshrs_2.io.allocate.bits.offset, _view__T_2.offset connect mshrs_2.io.allocate.bits.tag, _view__T_2.tag connect mshrs_2.io.allocate.bits.source, _view__T_2.source connect mshrs_2.io.allocate.bits.size, _view__T_2.size connect mshrs_2.io.allocate.bits.param, _view__T_2.param connect mshrs_2.io.allocate.bits.opcode, _view__T_2.opcode connect mshrs_2.io.allocate.bits.control, _view__T_2.control connect mshrs_2.io.allocate.bits.prio[0], _view__T_2.prio[0] connect mshrs_2.io.allocate.bits.prio[1], _view__T_2.prio[1] connect mshrs_2.io.allocate.bits.prio[2], _view__T_2.prio[2] connect mshrs_2.io.allocate.bits.set, mshrs_2.io.status.bits.set node _mshrs_2_io_allocate_bits_repeat_T = eq(mshrs_2.io.allocate.bits.tag, mshrs_2.io.status.bits.tag) connect mshrs_2.io.allocate.bits.repeat, _mshrs_2_io_allocate_bits_repeat_T node _mshrs_2_io_allocate_valid_T = and(sel_2, will_reload_3) connect mshrs_2.io.allocate.valid, _mshrs_2_io_allocate_valid_T node sel_3 = bits(mshr_selectOH, 3, 3) connect mshrs_3.io.schedule.ready, sel_3 node a_pop_4 = bits(requests.io.valid, 3, 3) node b_pop_4 = bits(requests.io.valid, 15, 15) node c_pop_4 = bits(requests.io.valid, 27, 27) node _bypassMatches_T_33 = bits(lowerMatches1, 3, 3) node _bypassMatches_T_34 = or(c_pop_4, request.bits.prio[2]) node _bypassMatches_T_35 = eq(c_pop_4, UInt<1>(0h0)) node _bypassMatches_T_36 = or(b_pop_4, request.bits.prio[1]) node _bypassMatches_T_37 = eq(b_pop_4, UInt<1>(0h0)) node _bypassMatches_T_38 = eq(a_pop_4, UInt<1>(0h0)) node _bypassMatches_T_39 = mux(_bypassMatches_T_36, _bypassMatches_T_37, _bypassMatches_T_38) node _bypassMatches_T_40 = mux(_bypassMatches_T_34, _bypassMatches_T_35, _bypassMatches_T_39) node bypassMatches_4 = and(_bypassMatches_T_33, _bypassMatches_T_40) node _may_pop_T_4 = or(a_pop_4, b_pop_4) node may_pop_4 = or(_may_pop_T_4, c_pop_4) node _bypass_T_4 = and(request.valid, queue) node bypass_4 = and(_bypass_T_4, bypassMatches_4) node _will_reload_T_4 = or(may_pop_4, bypass_4) node will_reload_4 = and(mshrs_3.io.schedule.bits.reload, _will_reload_T_4) wire _view__WIRE_3 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_3.put, request.bits.put connect _view__WIRE_3.offset, request.bits.offset connect _view__WIRE_3.tag, request.bits.tag connect _view__WIRE_3.source, request.bits.source connect _view__WIRE_3.size, request.bits.size connect _view__WIRE_3.param, request.bits.param connect _view__WIRE_3.opcode, request.bits.opcode connect _view__WIRE_3.control, request.bits.control connect _view__WIRE_3.prio, request.bits.prio node _view__T_3 = mux(bypass_4, _view__WIRE_3, requests.io.data) connect mshrs_3.io.allocate.bits.put, _view__T_3.put connect mshrs_3.io.allocate.bits.offset, _view__T_3.offset connect mshrs_3.io.allocate.bits.tag, _view__T_3.tag connect mshrs_3.io.allocate.bits.source, _view__T_3.source connect mshrs_3.io.allocate.bits.size, _view__T_3.size connect mshrs_3.io.allocate.bits.param, _view__T_3.param connect mshrs_3.io.allocate.bits.opcode, _view__T_3.opcode connect mshrs_3.io.allocate.bits.control, _view__T_3.control connect mshrs_3.io.allocate.bits.prio[0], _view__T_3.prio[0] connect mshrs_3.io.allocate.bits.prio[1], _view__T_3.prio[1] connect mshrs_3.io.allocate.bits.prio[2], _view__T_3.prio[2] connect mshrs_3.io.allocate.bits.set, mshrs_3.io.status.bits.set node _mshrs_3_io_allocate_bits_repeat_T = eq(mshrs_3.io.allocate.bits.tag, mshrs_3.io.status.bits.tag) connect mshrs_3.io.allocate.bits.repeat, _mshrs_3_io_allocate_bits_repeat_T node _mshrs_3_io_allocate_valid_T = and(sel_3, will_reload_4) connect mshrs_3.io.allocate.valid, _mshrs_3_io_allocate_valid_T node sel_4 = bits(mshr_selectOH, 4, 4) connect mshrs_4.io.schedule.ready, sel_4 node a_pop_5 = bits(requests.io.valid, 4, 4) node b_pop_5 = bits(requests.io.valid, 16, 16) node c_pop_5 = bits(requests.io.valid, 28, 28) node _bypassMatches_T_41 = bits(lowerMatches1, 4, 4) node _bypassMatches_T_42 = or(c_pop_5, request.bits.prio[2]) node _bypassMatches_T_43 = eq(c_pop_5, UInt<1>(0h0)) node _bypassMatches_T_44 = or(b_pop_5, request.bits.prio[1]) node _bypassMatches_T_45 = eq(b_pop_5, UInt<1>(0h0)) node _bypassMatches_T_46 = eq(a_pop_5, UInt<1>(0h0)) node _bypassMatches_T_47 = mux(_bypassMatches_T_44, _bypassMatches_T_45, _bypassMatches_T_46) node _bypassMatches_T_48 = mux(_bypassMatches_T_42, _bypassMatches_T_43, _bypassMatches_T_47) node bypassMatches_5 = and(_bypassMatches_T_41, _bypassMatches_T_48) node _may_pop_T_5 = or(a_pop_5, b_pop_5) node may_pop_5 = or(_may_pop_T_5, c_pop_5) node _bypass_T_5 = and(request.valid, queue) node bypass_5 = and(_bypass_T_5, bypassMatches_5) node _will_reload_T_5 = or(may_pop_5, bypass_5) node will_reload_5 = and(mshrs_4.io.schedule.bits.reload, _will_reload_T_5) wire _view__WIRE_4 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_4.put, request.bits.put connect _view__WIRE_4.offset, request.bits.offset connect _view__WIRE_4.tag, request.bits.tag connect _view__WIRE_4.source, request.bits.source connect _view__WIRE_4.size, request.bits.size connect _view__WIRE_4.param, request.bits.param connect _view__WIRE_4.opcode, request.bits.opcode connect _view__WIRE_4.control, request.bits.control connect _view__WIRE_4.prio, request.bits.prio node _view__T_4 = mux(bypass_5, _view__WIRE_4, requests.io.data) connect mshrs_4.io.allocate.bits.put, _view__T_4.put connect mshrs_4.io.allocate.bits.offset, _view__T_4.offset connect mshrs_4.io.allocate.bits.tag, _view__T_4.tag connect mshrs_4.io.allocate.bits.source, _view__T_4.source connect mshrs_4.io.allocate.bits.size, _view__T_4.size connect mshrs_4.io.allocate.bits.param, _view__T_4.param connect mshrs_4.io.allocate.bits.opcode, _view__T_4.opcode connect mshrs_4.io.allocate.bits.control, _view__T_4.control connect mshrs_4.io.allocate.bits.prio[0], _view__T_4.prio[0] connect mshrs_4.io.allocate.bits.prio[1], _view__T_4.prio[1] connect mshrs_4.io.allocate.bits.prio[2], _view__T_4.prio[2] connect mshrs_4.io.allocate.bits.set, mshrs_4.io.status.bits.set node _mshrs_4_io_allocate_bits_repeat_T = eq(mshrs_4.io.allocate.bits.tag, mshrs_4.io.status.bits.tag) connect mshrs_4.io.allocate.bits.repeat, _mshrs_4_io_allocate_bits_repeat_T node _mshrs_4_io_allocate_valid_T = and(sel_4, will_reload_5) connect mshrs_4.io.allocate.valid, _mshrs_4_io_allocate_valid_T node sel_5 = bits(mshr_selectOH, 5, 5) connect mshrs_5.io.schedule.ready, sel_5 node a_pop_6 = bits(requests.io.valid, 5, 5) node b_pop_6 = bits(requests.io.valid, 17, 17) node c_pop_6 = bits(requests.io.valid, 29, 29) node _bypassMatches_T_49 = bits(lowerMatches1, 5, 5) node _bypassMatches_T_50 = or(c_pop_6, request.bits.prio[2]) node _bypassMatches_T_51 = eq(c_pop_6, UInt<1>(0h0)) node _bypassMatches_T_52 = or(b_pop_6, request.bits.prio[1]) node _bypassMatches_T_53 = eq(b_pop_6, UInt<1>(0h0)) node _bypassMatches_T_54 = eq(a_pop_6, UInt<1>(0h0)) node _bypassMatches_T_55 = mux(_bypassMatches_T_52, _bypassMatches_T_53, _bypassMatches_T_54) node _bypassMatches_T_56 = mux(_bypassMatches_T_50, _bypassMatches_T_51, _bypassMatches_T_55) node bypassMatches_6 = and(_bypassMatches_T_49, _bypassMatches_T_56) node _may_pop_T_6 = or(a_pop_6, b_pop_6) node may_pop_6 = or(_may_pop_T_6, c_pop_6) node _bypass_T_6 = and(request.valid, queue) node bypass_6 = and(_bypass_T_6, bypassMatches_6) node _will_reload_T_6 = or(may_pop_6, bypass_6) node will_reload_6 = and(mshrs_5.io.schedule.bits.reload, _will_reload_T_6) wire _view__WIRE_5 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_5.put, request.bits.put connect _view__WIRE_5.offset, request.bits.offset connect _view__WIRE_5.tag, request.bits.tag connect _view__WIRE_5.source, request.bits.source connect _view__WIRE_5.size, request.bits.size connect _view__WIRE_5.param, request.bits.param connect _view__WIRE_5.opcode, request.bits.opcode connect _view__WIRE_5.control, request.bits.control connect _view__WIRE_5.prio, request.bits.prio node _view__T_5 = mux(bypass_6, _view__WIRE_5, requests.io.data) connect mshrs_5.io.allocate.bits.put, _view__T_5.put connect mshrs_5.io.allocate.bits.offset, _view__T_5.offset connect mshrs_5.io.allocate.bits.tag, _view__T_5.tag connect mshrs_5.io.allocate.bits.source, _view__T_5.source connect mshrs_5.io.allocate.bits.size, _view__T_5.size connect mshrs_5.io.allocate.bits.param, _view__T_5.param connect mshrs_5.io.allocate.bits.opcode, _view__T_5.opcode connect mshrs_5.io.allocate.bits.control, _view__T_5.control connect mshrs_5.io.allocate.bits.prio[0], _view__T_5.prio[0] connect mshrs_5.io.allocate.bits.prio[1], _view__T_5.prio[1] connect mshrs_5.io.allocate.bits.prio[2], _view__T_5.prio[2] connect mshrs_5.io.allocate.bits.set, mshrs_5.io.status.bits.set node _mshrs_5_io_allocate_bits_repeat_T = eq(mshrs_5.io.allocate.bits.tag, mshrs_5.io.status.bits.tag) connect mshrs_5.io.allocate.bits.repeat, _mshrs_5_io_allocate_bits_repeat_T node _mshrs_5_io_allocate_valid_T = and(sel_5, will_reload_6) connect mshrs_5.io.allocate.valid, _mshrs_5_io_allocate_valid_T node sel_6 = bits(mshr_selectOH, 6, 6) connect mshrs_6.io.schedule.ready, sel_6 node a_pop_7 = bits(requests.io.valid, 6, 6) node b_pop_7 = bits(requests.io.valid, 18, 18) node c_pop_7 = bits(requests.io.valid, 30, 30) node _bypassMatches_T_57 = bits(lowerMatches1, 6, 6) node _bypassMatches_T_58 = or(c_pop_7, request.bits.prio[2]) node _bypassMatches_T_59 = eq(c_pop_7, UInt<1>(0h0)) node _bypassMatches_T_60 = or(b_pop_7, request.bits.prio[1]) node _bypassMatches_T_61 = eq(b_pop_7, UInt<1>(0h0)) node _bypassMatches_T_62 = eq(a_pop_7, UInt<1>(0h0)) node _bypassMatches_T_63 = mux(_bypassMatches_T_60, _bypassMatches_T_61, _bypassMatches_T_62) node _bypassMatches_T_64 = mux(_bypassMatches_T_58, _bypassMatches_T_59, _bypassMatches_T_63) node bypassMatches_7 = and(_bypassMatches_T_57, _bypassMatches_T_64) node _may_pop_T_7 = or(a_pop_7, b_pop_7) node may_pop_7 = or(_may_pop_T_7, c_pop_7) node _bypass_T_7 = and(request.valid, queue) node bypass_7 = and(_bypass_T_7, bypassMatches_7) node _will_reload_T_7 = or(may_pop_7, bypass_7) node will_reload_7 = and(mshrs_6.io.schedule.bits.reload, _will_reload_T_7) wire _view__WIRE_6 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_6.put, request.bits.put connect _view__WIRE_6.offset, request.bits.offset connect _view__WIRE_6.tag, request.bits.tag connect _view__WIRE_6.source, request.bits.source connect _view__WIRE_6.size, request.bits.size connect _view__WIRE_6.param, request.bits.param connect _view__WIRE_6.opcode, request.bits.opcode connect _view__WIRE_6.control, request.bits.control connect _view__WIRE_6.prio, request.bits.prio node _view__T_6 = mux(bypass_7, _view__WIRE_6, requests.io.data) connect mshrs_6.io.allocate.bits.put, _view__T_6.put connect mshrs_6.io.allocate.bits.offset, _view__T_6.offset connect mshrs_6.io.allocate.bits.tag, _view__T_6.tag connect mshrs_6.io.allocate.bits.source, _view__T_6.source connect mshrs_6.io.allocate.bits.size, _view__T_6.size connect mshrs_6.io.allocate.bits.param, _view__T_6.param connect mshrs_6.io.allocate.bits.opcode, _view__T_6.opcode connect mshrs_6.io.allocate.bits.control, _view__T_6.control connect mshrs_6.io.allocate.bits.prio[0], _view__T_6.prio[0] connect mshrs_6.io.allocate.bits.prio[1], _view__T_6.prio[1] connect mshrs_6.io.allocate.bits.prio[2], _view__T_6.prio[2] connect mshrs_6.io.allocate.bits.set, mshrs_6.io.status.bits.set node _mshrs_6_io_allocate_bits_repeat_T = eq(mshrs_6.io.allocate.bits.tag, mshrs_6.io.status.bits.tag) connect mshrs_6.io.allocate.bits.repeat, _mshrs_6_io_allocate_bits_repeat_T node _mshrs_6_io_allocate_valid_T = and(sel_6, will_reload_7) connect mshrs_6.io.allocate.valid, _mshrs_6_io_allocate_valid_T node sel_7 = bits(mshr_selectOH, 7, 7) connect mshrs_7.io.schedule.ready, sel_7 node a_pop_8 = bits(requests.io.valid, 7, 7) node b_pop_8 = bits(requests.io.valid, 19, 19) node c_pop_8 = bits(requests.io.valid, 31, 31) node _bypassMatches_T_65 = bits(lowerMatches1, 7, 7) node _bypassMatches_T_66 = or(c_pop_8, request.bits.prio[2]) node _bypassMatches_T_67 = eq(c_pop_8, UInt<1>(0h0)) node _bypassMatches_T_68 = or(b_pop_8, request.bits.prio[1]) node _bypassMatches_T_69 = eq(b_pop_8, UInt<1>(0h0)) node _bypassMatches_T_70 = eq(a_pop_8, UInt<1>(0h0)) node _bypassMatches_T_71 = mux(_bypassMatches_T_68, _bypassMatches_T_69, _bypassMatches_T_70) node _bypassMatches_T_72 = mux(_bypassMatches_T_66, _bypassMatches_T_67, _bypassMatches_T_71) node bypassMatches_8 = and(_bypassMatches_T_65, _bypassMatches_T_72) node _may_pop_T_8 = or(a_pop_8, b_pop_8) node may_pop_8 = or(_may_pop_T_8, c_pop_8) node _bypass_T_8 = and(request.valid, queue) node bypass_8 = and(_bypass_T_8, bypassMatches_8) node _will_reload_T_8 = or(may_pop_8, bypass_8) node will_reload_8 = and(mshrs_7.io.schedule.bits.reload, _will_reload_T_8) wire _view__WIRE_7 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_7.put, request.bits.put connect _view__WIRE_7.offset, request.bits.offset connect _view__WIRE_7.tag, request.bits.tag connect _view__WIRE_7.source, request.bits.source connect _view__WIRE_7.size, request.bits.size connect _view__WIRE_7.param, request.bits.param connect _view__WIRE_7.opcode, request.bits.opcode connect _view__WIRE_7.control, request.bits.control connect _view__WIRE_7.prio, request.bits.prio node _view__T_7 = mux(bypass_8, _view__WIRE_7, requests.io.data) connect mshrs_7.io.allocate.bits.put, _view__T_7.put connect mshrs_7.io.allocate.bits.offset, _view__T_7.offset connect mshrs_7.io.allocate.bits.tag, _view__T_7.tag connect mshrs_7.io.allocate.bits.source, _view__T_7.source connect mshrs_7.io.allocate.bits.size, _view__T_7.size connect mshrs_7.io.allocate.bits.param, _view__T_7.param connect mshrs_7.io.allocate.bits.opcode, _view__T_7.opcode connect mshrs_7.io.allocate.bits.control, _view__T_7.control connect mshrs_7.io.allocate.bits.prio[0], _view__T_7.prio[0] connect mshrs_7.io.allocate.bits.prio[1], _view__T_7.prio[1] connect mshrs_7.io.allocate.bits.prio[2], _view__T_7.prio[2] connect mshrs_7.io.allocate.bits.set, mshrs_7.io.status.bits.set node _mshrs_7_io_allocate_bits_repeat_T = eq(mshrs_7.io.allocate.bits.tag, mshrs_7.io.status.bits.tag) connect mshrs_7.io.allocate.bits.repeat, _mshrs_7_io_allocate_bits_repeat_T node _mshrs_7_io_allocate_valid_T = and(sel_7, will_reload_8) connect mshrs_7.io.allocate.valid, _mshrs_7_io_allocate_valid_T node sel_8 = bits(mshr_selectOH, 8, 8) connect mshrs_8.io.schedule.ready, sel_8 node a_pop_9 = bits(requests.io.valid, 8, 8) node b_pop_9 = bits(requests.io.valid, 20, 20) node c_pop_9 = bits(requests.io.valid, 32, 32) node _bypassMatches_T_73 = bits(lowerMatches1, 8, 8) node _bypassMatches_T_74 = or(c_pop_9, request.bits.prio[2]) node _bypassMatches_T_75 = eq(c_pop_9, UInt<1>(0h0)) node _bypassMatches_T_76 = or(b_pop_9, request.bits.prio[1]) node _bypassMatches_T_77 = eq(b_pop_9, UInt<1>(0h0)) node _bypassMatches_T_78 = eq(a_pop_9, UInt<1>(0h0)) node _bypassMatches_T_79 = mux(_bypassMatches_T_76, _bypassMatches_T_77, _bypassMatches_T_78) node _bypassMatches_T_80 = mux(_bypassMatches_T_74, _bypassMatches_T_75, _bypassMatches_T_79) node bypassMatches_9 = and(_bypassMatches_T_73, _bypassMatches_T_80) node _may_pop_T_9 = or(a_pop_9, b_pop_9) node may_pop_9 = or(_may_pop_T_9, c_pop_9) node _bypass_T_9 = and(request.valid, queue) node bypass_9 = and(_bypass_T_9, bypassMatches_9) node _will_reload_T_9 = or(may_pop_9, bypass_9) node will_reload_9 = and(mshrs_8.io.schedule.bits.reload, _will_reload_T_9) wire _view__WIRE_8 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_8.put, request.bits.put connect _view__WIRE_8.offset, request.bits.offset connect _view__WIRE_8.tag, request.bits.tag connect _view__WIRE_8.source, request.bits.source connect _view__WIRE_8.size, request.bits.size connect _view__WIRE_8.param, request.bits.param connect _view__WIRE_8.opcode, request.bits.opcode connect _view__WIRE_8.control, request.bits.control connect _view__WIRE_8.prio, request.bits.prio node _view__T_8 = mux(bypass_9, _view__WIRE_8, requests.io.data) connect mshrs_8.io.allocate.bits.put, _view__T_8.put connect mshrs_8.io.allocate.bits.offset, _view__T_8.offset connect mshrs_8.io.allocate.bits.tag, _view__T_8.tag connect mshrs_8.io.allocate.bits.source, _view__T_8.source connect mshrs_8.io.allocate.bits.size, _view__T_8.size connect mshrs_8.io.allocate.bits.param, _view__T_8.param connect mshrs_8.io.allocate.bits.opcode, _view__T_8.opcode connect mshrs_8.io.allocate.bits.control, _view__T_8.control connect mshrs_8.io.allocate.bits.prio[0], _view__T_8.prio[0] connect mshrs_8.io.allocate.bits.prio[1], _view__T_8.prio[1] connect mshrs_8.io.allocate.bits.prio[2], _view__T_8.prio[2] connect mshrs_8.io.allocate.bits.set, mshrs_8.io.status.bits.set node _mshrs_8_io_allocate_bits_repeat_T = eq(mshrs_8.io.allocate.bits.tag, mshrs_8.io.status.bits.tag) connect mshrs_8.io.allocate.bits.repeat, _mshrs_8_io_allocate_bits_repeat_T node _mshrs_8_io_allocate_valid_T = and(sel_8, will_reload_9) connect mshrs_8.io.allocate.valid, _mshrs_8_io_allocate_valid_T node sel_9 = bits(mshr_selectOH, 9, 9) connect mshrs_9.io.schedule.ready, sel_9 node a_pop_10 = bits(requests.io.valid, 9, 9) node b_pop_10 = bits(requests.io.valid, 21, 21) node c_pop_10 = bits(requests.io.valid, 33, 33) node _bypassMatches_T_81 = bits(lowerMatches1, 9, 9) node _bypassMatches_T_82 = or(c_pop_10, request.bits.prio[2]) node _bypassMatches_T_83 = eq(c_pop_10, UInt<1>(0h0)) node _bypassMatches_T_84 = or(b_pop_10, request.bits.prio[1]) node _bypassMatches_T_85 = eq(b_pop_10, UInt<1>(0h0)) node _bypassMatches_T_86 = eq(a_pop_10, UInt<1>(0h0)) node _bypassMatches_T_87 = mux(_bypassMatches_T_84, _bypassMatches_T_85, _bypassMatches_T_86) node _bypassMatches_T_88 = mux(_bypassMatches_T_82, _bypassMatches_T_83, _bypassMatches_T_87) node bypassMatches_10 = and(_bypassMatches_T_81, _bypassMatches_T_88) node _may_pop_T_10 = or(a_pop_10, b_pop_10) node may_pop_10 = or(_may_pop_T_10, c_pop_10) node _bypass_T_10 = and(request.valid, queue) node bypass_10 = and(_bypass_T_10, bypassMatches_10) node _will_reload_T_10 = or(may_pop_10, bypass_10) node will_reload_10 = and(mshrs_9.io.schedule.bits.reload, _will_reload_T_10) wire _view__WIRE_9 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_9.put, request.bits.put connect _view__WIRE_9.offset, request.bits.offset connect _view__WIRE_9.tag, request.bits.tag connect _view__WIRE_9.source, request.bits.source connect _view__WIRE_9.size, request.bits.size connect _view__WIRE_9.param, request.bits.param connect _view__WIRE_9.opcode, request.bits.opcode connect _view__WIRE_9.control, request.bits.control connect _view__WIRE_9.prio, request.bits.prio node _view__T_9 = mux(bypass_10, _view__WIRE_9, requests.io.data) connect mshrs_9.io.allocate.bits.put, _view__T_9.put connect mshrs_9.io.allocate.bits.offset, _view__T_9.offset connect mshrs_9.io.allocate.bits.tag, _view__T_9.tag connect mshrs_9.io.allocate.bits.source, _view__T_9.source connect mshrs_9.io.allocate.bits.size, _view__T_9.size connect mshrs_9.io.allocate.bits.param, _view__T_9.param connect mshrs_9.io.allocate.bits.opcode, _view__T_9.opcode connect mshrs_9.io.allocate.bits.control, _view__T_9.control connect mshrs_9.io.allocate.bits.prio[0], _view__T_9.prio[0] connect mshrs_9.io.allocate.bits.prio[1], _view__T_9.prio[1] connect mshrs_9.io.allocate.bits.prio[2], _view__T_9.prio[2] connect mshrs_9.io.allocate.bits.set, mshrs_9.io.status.bits.set node _mshrs_9_io_allocate_bits_repeat_T = eq(mshrs_9.io.allocate.bits.tag, mshrs_9.io.status.bits.tag) connect mshrs_9.io.allocate.bits.repeat, _mshrs_9_io_allocate_bits_repeat_T node _mshrs_9_io_allocate_valid_T = and(sel_9, will_reload_10) connect mshrs_9.io.allocate.valid, _mshrs_9_io_allocate_valid_T node sel_10 = bits(mshr_selectOH, 10, 10) connect mshrs_10.io.schedule.ready, sel_10 node a_pop_11 = bits(requests.io.valid, 10, 10) node b_pop_11 = bits(requests.io.valid, 22, 22) node c_pop_11 = bits(requests.io.valid, 34, 34) node _bypassMatches_T_89 = bits(lowerMatches1, 10, 10) node _bypassMatches_T_90 = or(c_pop_11, request.bits.prio[2]) node _bypassMatches_T_91 = eq(c_pop_11, UInt<1>(0h0)) node _bypassMatches_T_92 = or(b_pop_11, request.bits.prio[1]) node _bypassMatches_T_93 = eq(b_pop_11, UInt<1>(0h0)) node _bypassMatches_T_94 = eq(a_pop_11, UInt<1>(0h0)) node _bypassMatches_T_95 = mux(_bypassMatches_T_92, _bypassMatches_T_93, _bypassMatches_T_94) node _bypassMatches_T_96 = mux(_bypassMatches_T_90, _bypassMatches_T_91, _bypassMatches_T_95) node bypassMatches_11 = and(_bypassMatches_T_89, _bypassMatches_T_96) node _may_pop_T_11 = or(a_pop_11, b_pop_11) node may_pop_11 = or(_may_pop_T_11, c_pop_11) node _bypass_T_11 = and(request.valid, queue) node bypass_11 = and(_bypass_T_11, bypassMatches_11) node _will_reload_T_11 = or(may_pop_11, bypass_11) node will_reload_11 = and(mshrs_10.io.schedule.bits.reload, _will_reload_T_11) wire _view__WIRE_10 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_10.put, request.bits.put connect _view__WIRE_10.offset, request.bits.offset connect _view__WIRE_10.tag, request.bits.tag connect _view__WIRE_10.source, request.bits.source connect _view__WIRE_10.size, request.bits.size connect _view__WIRE_10.param, request.bits.param connect _view__WIRE_10.opcode, request.bits.opcode connect _view__WIRE_10.control, request.bits.control connect _view__WIRE_10.prio, request.bits.prio node _view__T_10 = mux(bypass_11, _view__WIRE_10, requests.io.data) connect mshrs_10.io.allocate.bits.put, _view__T_10.put connect mshrs_10.io.allocate.bits.offset, _view__T_10.offset connect mshrs_10.io.allocate.bits.tag, _view__T_10.tag connect mshrs_10.io.allocate.bits.source, _view__T_10.source connect mshrs_10.io.allocate.bits.size, _view__T_10.size connect mshrs_10.io.allocate.bits.param, _view__T_10.param connect mshrs_10.io.allocate.bits.opcode, _view__T_10.opcode connect mshrs_10.io.allocate.bits.control, _view__T_10.control connect mshrs_10.io.allocate.bits.prio[0], _view__T_10.prio[0] connect mshrs_10.io.allocate.bits.prio[1], _view__T_10.prio[1] connect mshrs_10.io.allocate.bits.prio[2], _view__T_10.prio[2] connect mshrs_10.io.allocate.bits.set, mshrs_10.io.status.bits.set node _mshrs_10_io_allocate_bits_repeat_T = eq(mshrs_10.io.allocate.bits.tag, mshrs_10.io.status.bits.tag) connect mshrs_10.io.allocate.bits.repeat, _mshrs_10_io_allocate_bits_repeat_T node _mshrs_10_io_allocate_valid_T = and(sel_10, will_reload_11) connect mshrs_10.io.allocate.valid, _mshrs_10_io_allocate_valid_T node sel_11 = bits(mshr_selectOH, 11, 11) connect mshrs_11.io.schedule.ready, sel_11 node a_pop_12 = bits(requests.io.valid, 11, 11) node b_pop_12 = bits(requests.io.valid, 23, 23) node c_pop_12 = bits(requests.io.valid, 35, 35) node _bypassMatches_T_97 = bits(lowerMatches1, 11, 11) node _bypassMatches_T_98 = or(c_pop_12, request.bits.prio[2]) node _bypassMatches_T_99 = eq(c_pop_12, UInt<1>(0h0)) node _bypassMatches_T_100 = or(b_pop_12, request.bits.prio[1]) node _bypassMatches_T_101 = eq(b_pop_12, UInt<1>(0h0)) node _bypassMatches_T_102 = eq(a_pop_12, UInt<1>(0h0)) node _bypassMatches_T_103 = mux(_bypassMatches_T_100, _bypassMatches_T_101, _bypassMatches_T_102) node _bypassMatches_T_104 = mux(_bypassMatches_T_98, _bypassMatches_T_99, _bypassMatches_T_103) node bypassMatches_12 = and(_bypassMatches_T_97, _bypassMatches_T_104) node _may_pop_T_12 = or(a_pop_12, b_pop_12) node may_pop_12 = or(_may_pop_T_12, c_pop_12) node _bypass_T_12 = and(request.valid, queue) node bypass_12 = and(_bypass_T_12, bypassMatches_12) node _will_reload_T_12 = or(may_pop_12, bypass_12) node will_reload_12 = and(mshrs_11.io.schedule.bits.reload, _will_reload_T_12) wire _view__WIRE_11 : { prio : UInt<1>[3], control : UInt<1>, opcode : UInt<3>, param : UInt<3>, size : UInt<3>, source : UInt<6>, tag : UInt<9>, offset : UInt<6>, put : UInt<6>} connect _view__WIRE_11.put, request.bits.put connect _view__WIRE_11.offset, request.bits.offset connect _view__WIRE_11.tag, request.bits.tag connect _view__WIRE_11.source, request.bits.source connect _view__WIRE_11.size, request.bits.size connect _view__WIRE_11.param, request.bits.param connect _view__WIRE_11.opcode, request.bits.opcode connect _view__WIRE_11.control, request.bits.control connect _view__WIRE_11.prio, request.bits.prio node _view__T_11 = mux(bypass_12, _view__WIRE_11, requests.io.data) connect mshrs_11.io.allocate.bits.put, _view__T_11.put connect mshrs_11.io.allocate.bits.offset, _view__T_11.offset connect mshrs_11.io.allocate.bits.tag, _view__T_11.tag connect mshrs_11.io.allocate.bits.source, _view__T_11.source connect mshrs_11.io.allocate.bits.size, _view__T_11.size connect mshrs_11.io.allocate.bits.param, _view__T_11.param connect mshrs_11.io.allocate.bits.opcode, _view__T_11.opcode connect mshrs_11.io.allocate.bits.control, _view__T_11.control connect mshrs_11.io.allocate.bits.prio[0], _view__T_11.prio[0] connect mshrs_11.io.allocate.bits.prio[1], _view__T_11.prio[1] connect mshrs_11.io.allocate.bits.prio[2], _view__T_11.prio[2] connect mshrs_11.io.allocate.bits.set, mshrs_11.io.status.bits.set node _mshrs_11_io_allocate_bits_repeat_T = eq(mshrs_11.io.allocate.bits.tag, mshrs_11.io.status.bits.tag) connect mshrs_11.io.allocate.bits.repeat, _mshrs_11_io_allocate_bits_repeat_T node _mshrs_11_io_allocate_valid_T = and(sel_11, will_reload_12) connect mshrs_11.io.allocate.valid, _mshrs_11_io_allocate_valid_T node _prio_requests_T = not(requests.io.valid) node _prio_requests_T_1 = shr(requests.io.valid, 12) node _prio_requests_T_2 = or(_prio_requests_T, _prio_requests_T_1) node _prio_requests_T_3 = shr(requests.io.valid, 24) node _prio_requests_T_4 = or(_prio_requests_T_2, _prio_requests_T_3) node prio_requests = not(_prio_requests_T_4) node pop_index_hi = cat(mshr_selectOH, mshr_selectOH) node _pop_index_T = cat(pop_index_hi, mshr_selectOH) node _pop_index_T_1 = and(_pop_index_T, prio_requests) node pop_index_hi_1 = bits(_pop_index_T_1, 35, 32) node pop_index_lo = bits(_pop_index_T_1, 31, 0) node _pop_index_T_2 = orr(pop_index_hi_1) node _pop_index_T_3 = or(pop_index_hi_1, pop_index_lo) node pop_index_hi_2 = bits(_pop_index_T_3, 31, 16) node pop_index_lo_1 = bits(_pop_index_T_3, 15, 0) node _pop_index_T_4 = orr(pop_index_hi_2) node _pop_index_T_5 = or(pop_index_hi_2, pop_index_lo_1) node pop_index_hi_3 = bits(_pop_index_T_5, 15, 8) node pop_index_lo_2 = bits(_pop_index_T_5, 7, 0) node _pop_index_T_6 = orr(pop_index_hi_3) node _pop_index_T_7 = or(pop_index_hi_3, pop_index_lo_2) node pop_index_hi_4 = bits(_pop_index_T_7, 7, 4) node pop_index_lo_3 = bits(_pop_index_T_7, 3, 0) node _pop_index_T_8 = orr(pop_index_hi_4) node _pop_index_T_9 = or(pop_index_hi_4, pop_index_lo_3) node pop_index_hi_5 = bits(_pop_index_T_9, 3, 2) node pop_index_lo_4 = bits(_pop_index_T_9, 1, 0) node _pop_index_T_10 = orr(pop_index_hi_5) node _pop_index_T_11 = or(pop_index_hi_5, pop_index_lo_4) node _pop_index_T_12 = bits(_pop_index_T_11, 1, 1) node _pop_index_T_13 = cat(_pop_index_T_10, _pop_index_T_12) node _pop_index_T_14 = cat(_pop_index_T_8, _pop_index_T_13) node _pop_index_T_15 = cat(_pop_index_T_6, _pop_index_T_14) node _pop_index_T_16 = cat(_pop_index_T_4, _pop_index_T_15) node pop_index = cat(_pop_index_T_2, _pop_index_T_16) connect requests.io.pop.valid, will_pop connect requests.io.pop.bits, pop_index node lb_tag_mismatch = neq(scheduleTag, requests.io.data.tag) node _mshr_uses_directory_assuming_no_bypass_T = and(schedule.reload, may_pop) node mshr_uses_directory_assuming_no_bypass = and(_mshr_uses_directory_assuming_no_bypass_T, lb_tag_mismatch) node mshr_uses_directory_for_lb = and(will_pop, lb_tag_mismatch) node _mshr_uses_directory_T = mux(bypass, request.bits.tag, requests.io.data.tag) node _mshr_uses_directory_T_1 = neq(scheduleTag, _mshr_uses_directory_T) node mshr_uses_directory = and(will_reload, _mshr_uses_directory_T_1) node mshr_validOH_lo_lo_hi = cat(mshrs_2.io.status.valid, mshrs_1.io.status.valid) node mshr_validOH_lo_lo = cat(mshr_validOH_lo_lo_hi, mshrs_0.io.status.valid) node mshr_validOH_lo_hi_hi = cat(mshrs_5.io.status.valid, mshrs_4.io.status.valid) node mshr_validOH_lo_hi = cat(mshr_validOH_lo_hi_hi, mshrs_3.io.status.valid) node mshr_validOH_lo = cat(mshr_validOH_lo_hi, mshr_validOH_lo_lo) node mshr_validOH_hi_lo_hi = cat(mshrs_8.io.status.valid, mshrs_7.io.status.valid) node mshr_validOH_hi_lo = cat(mshr_validOH_hi_lo_hi, mshrs_6.io.status.valid) node mshr_validOH_hi_hi_hi = cat(mshrs_11.io.status.valid, mshrs_10.io.status.valid) node mshr_validOH_hi_hi = cat(mshr_validOH_hi_hi_hi, mshrs_9.io.status.valid) node mshr_validOH_hi = cat(mshr_validOH_hi_hi, mshr_validOH_hi_lo) node mshr_validOH = cat(mshr_validOH_hi, mshr_validOH_lo) node _mshr_free_T = not(mshr_validOH) node _mshr_free_T_1 = and(_mshr_free_T, prioFilter) node mshr_free = orr(_mshr_free_T_1) node bypassQueue = and(schedule.reload, bypassMatches) node _request_alloc_cases_T = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_1 = and(alloc, _request_alloc_cases_T) node _request_alloc_cases_T_2 = and(_request_alloc_cases_T_1, mshr_free) node _request_alloc_cases_T_3 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_4 = and(nestB, _request_alloc_cases_T_3) node _request_alloc_cases_T_5 = eq(mshrs_10.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_6 = and(_request_alloc_cases_T_4, _request_alloc_cases_T_5) node _request_alloc_cases_T_7 = eq(mshrs_11.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_8 = and(_request_alloc_cases_T_6, _request_alloc_cases_T_7) node _request_alloc_cases_T_9 = or(_request_alloc_cases_T_2, _request_alloc_cases_T_8) node _request_alloc_cases_T_10 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _request_alloc_cases_T_11 = and(nestC, _request_alloc_cases_T_10) node _request_alloc_cases_T_12 = eq(mshrs_11.io.status.valid, UInt<1>(0h0)) node _request_alloc_cases_T_13 = and(_request_alloc_cases_T_11, _request_alloc_cases_T_12) node request_alloc_cases = or(_request_alloc_cases_T_9, _request_alloc_cases_T_13) node _request_ready_T = or(bypassQueue, requests.io.push.ready) node _request_ready_T_1 = and(queue, _request_ready_T) node _request_ready_T_2 = or(request_alloc_cases, _request_ready_T_1) connect request.ready, _request_ready_T_2 node alloc_uses_directory = and(request.valid, request_alloc_cases) node _directory_io_read_valid_T = or(mshr_uses_directory, alloc_uses_directory) connect directory.io.read.valid, _directory_io_read_valid_T node _directory_io_read_bits_set_T = mux(mshr_uses_directory_for_lb, scheduleSet, request.bits.set) connect directory.io.read.bits.set, _directory_io_read_bits_set_T node _directory_io_read_bits_tag_T = mux(mshr_uses_directory_for_lb, requests.io.data.tag, request.bits.tag) connect directory.io.read.bits.tag, _directory_io_read_bits_tag_T node _requests_io_push_valid_T = and(request.valid, queue) node _requests_io_push_valid_T_1 = eq(bypassQueue, UInt<1>(0h0)) node _requests_io_push_valid_T_2 = and(_requests_io_push_valid_T, _requests_io_push_valid_T_1) connect requests.io.push.valid, _requests_io_push_valid_T_2 connect requests.io.push.bits.data.put, request.bits.put connect requests.io.push.bits.data.offset, request.bits.offset connect requests.io.push.bits.data.tag, request.bits.tag connect requests.io.push.bits.data.source, request.bits.source connect requests.io.push.bits.data.size, request.bits.size connect requests.io.push.bits.data.param, request.bits.param connect requests.io.push.bits.data.opcode, request.bits.opcode connect requests.io.push.bits.data.control, request.bits.control connect requests.io.push.bits.data.prio[0], request.bits.prio[0] connect requests.io.push.bits.data.prio[1], request.bits.prio[1] connect requests.io.push.bits.data.prio[2], request.bits.prio[2] node _requests_io_push_bits_index_T = shl(lowerMatches1, 0) node requests_io_push_bits_index_hi = bits(_requests_io_push_bits_index_T, 11, 8) node requests_io_push_bits_index_lo = bits(_requests_io_push_bits_index_T, 7, 0) node _requests_io_push_bits_index_T_1 = orr(requests_io_push_bits_index_hi) node _requests_io_push_bits_index_T_2 = or(requests_io_push_bits_index_hi, requests_io_push_bits_index_lo) node requests_io_push_bits_index_hi_1 = bits(_requests_io_push_bits_index_T_2, 7, 4) node requests_io_push_bits_index_lo_1 = bits(_requests_io_push_bits_index_T_2, 3, 0) node _requests_io_push_bits_index_T_3 = orr(requests_io_push_bits_index_hi_1) node _requests_io_push_bits_index_T_4 = or(requests_io_push_bits_index_hi_1, requests_io_push_bits_index_lo_1) node requests_io_push_bits_index_hi_2 = bits(_requests_io_push_bits_index_T_4, 3, 2) node requests_io_push_bits_index_lo_2 = bits(_requests_io_push_bits_index_T_4, 1, 0) node _requests_io_push_bits_index_T_5 = orr(requests_io_push_bits_index_hi_2) node _requests_io_push_bits_index_T_6 = or(requests_io_push_bits_index_hi_2, requests_io_push_bits_index_lo_2) node _requests_io_push_bits_index_T_7 = bits(_requests_io_push_bits_index_T_6, 1, 1) node _requests_io_push_bits_index_T_8 = cat(_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7) node _requests_io_push_bits_index_T_9 = cat(_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8) node _requests_io_push_bits_index_T_10 = cat(_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9) node _requests_io_push_bits_index_T_11 = shl(lowerMatches1, 12) node requests_io_push_bits_index_hi_3 = bits(_requests_io_push_bits_index_T_11, 23, 16) node requests_io_push_bits_index_lo_3 = bits(_requests_io_push_bits_index_T_11, 15, 0) node _requests_io_push_bits_index_T_12 = orr(requests_io_push_bits_index_hi_3) node _requests_io_push_bits_index_T_13 = or(requests_io_push_bits_index_hi_3, requests_io_push_bits_index_lo_3) node requests_io_push_bits_index_hi_4 = bits(_requests_io_push_bits_index_T_13, 15, 8) node requests_io_push_bits_index_lo_4 = bits(_requests_io_push_bits_index_T_13, 7, 0) node _requests_io_push_bits_index_T_14 = orr(requests_io_push_bits_index_hi_4) node _requests_io_push_bits_index_T_15 = or(requests_io_push_bits_index_hi_4, requests_io_push_bits_index_lo_4) node requests_io_push_bits_index_hi_5 = bits(_requests_io_push_bits_index_T_15, 7, 4) node requests_io_push_bits_index_lo_5 = bits(_requests_io_push_bits_index_T_15, 3, 0) node _requests_io_push_bits_index_T_16 = orr(requests_io_push_bits_index_hi_5) node _requests_io_push_bits_index_T_17 = or(requests_io_push_bits_index_hi_5, requests_io_push_bits_index_lo_5) node requests_io_push_bits_index_hi_6 = bits(_requests_io_push_bits_index_T_17, 3, 2) node requests_io_push_bits_index_lo_6 = bits(_requests_io_push_bits_index_T_17, 1, 0) node _requests_io_push_bits_index_T_18 = orr(requests_io_push_bits_index_hi_6) node _requests_io_push_bits_index_T_19 = or(requests_io_push_bits_index_hi_6, requests_io_push_bits_index_lo_6) node _requests_io_push_bits_index_T_20 = bits(_requests_io_push_bits_index_T_19, 1, 1) node _requests_io_push_bits_index_T_21 = cat(_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20) node _requests_io_push_bits_index_T_22 = cat(_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21) node _requests_io_push_bits_index_T_23 = cat(_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22) node _requests_io_push_bits_index_T_24 = cat(_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23) node _requests_io_push_bits_index_T_25 = shl(lowerMatches1, 24) node requests_io_push_bits_index_hi_7 = bits(_requests_io_push_bits_index_T_25, 35, 32) node requests_io_push_bits_index_lo_7 = bits(_requests_io_push_bits_index_T_25, 31, 0) node _requests_io_push_bits_index_T_26 = orr(requests_io_push_bits_index_hi_7) node _requests_io_push_bits_index_T_27 = or(requests_io_push_bits_index_hi_7, requests_io_push_bits_index_lo_7) node requests_io_push_bits_index_hi_8 = bits(_requests_io_push_bits_index_T_27, 31, 16) node requests_io_push_bits_index_lo_8 = bits(_requests_io_push_bits_index_T_27, 15, 0) node _requests_io_push_bits_index_T_28 = orr(requests_io_push_bits_index_hi_8) node _requests_io_push_bits_index_T_29 = or(requests_io_push_bits_index_hi_8, requests_io_push_bits_index_lo_8) node requests_io_push_bits_index_hi_9 = bits(_requests_io_push_bits_index_T_29, 15, 8) node requests_io_push_bits_index_lo_9 = bits(_requests_io_push_bits_index_T_29, 7, 0) node _requests_io_push_bits_index_T_30 = orr(requests_io_push_bits_index_hi_9) node _requests_io_push_bits_index_T_31 = or(requests_io_push_bits_index_hi_9, requests_io_push_bits_index_lo_9) node requests_io_push_bits_index_hi_10 = bits(_requests_io_push_bits_index_T_31, 7, 4) node requests_io_push_bits_index_lo_10 = bits(_requests_io_push_bits_index_T_31, 3, 0) node _requests_io_push_bits_index_T_32 = orr(requests_io_push_bits_index_hi_10) node _requests_io_push_bits_index_T_33 = or(requests_io_push_bits_index_hi_10, requests_io_push_bits_index_lo_10) node requests_io_push_bits_index_hi_11 = bits(_requests_io_push_bits_index_T_33, 3, 2) node requests_io_push_bits_index_lo_11 = bits(_requests_io_push_bits_index_T_33, 1, 0) node _requests_io_push_bits_index_T_34 = orr(requests_io_push_bits_index_hi_11) node _requests_io_push_bits_index_T_35 = or(requests_io_push_bits_index_hi_11, requests_io_push_bits_index_lo_11) node _requests_io_push_bits_index_T_36 = bits(_requests_io_push_bits_index_T_35, 1, 1) node _requests_io_push_bits_index_T_37 = cat(_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36) node _requests_io_push_bits_index_T_38 = cat(_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37) node _requests_io_push_bits_index_T_39 = cat(_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38) node _requests_io_push_bits_index_T_40 = cat(_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39) node _requests_io_push_bits_index_T_41 = cat(_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40) node _requests_io_push_bits_index_T_42 = mux(request.bits.prio[0], _requests_io_push_bits_index_T_10, UInt<1>(0h0)) node _requests_io_push_bits_index_T_43 = mux(request.bits.prio[1], _requests_io_push_bits_index_T_24, UInt<1>(0h0)) node _requests_io_push_bits_index_T_44 = mux(request.bits.prio[2], _requests_io_push_bits_index_T_41, UInt<1>(0h0)) node _requests_io_push_bits_index_T_45 = or(_requests_io_push_bits_index_T_42, _requests_io_push_bits_index_T_43) node _requests_io_push_bits_index_T_46 = or(_requests_io_push_bits_index_T_45, _requests_io_push_bits_index_T_44) wire _requests_io_push_bits_index_WIRE : UInt<6> connect _requests_io_push_bits_index_WIRE, _requests_io_push_bits_index_T_46 connect requests.io.push.bits.index, _requests_io_push_bits_index_WIRE node _mshr_insertOH_T = not(mshr_validOH) node _mshr_insertOH_T_1 = shl(_mshr_insertOH_T, 1) node _mshr_insertOH_T_2 = bits(_mshr_insertOH_T_1, 11, 0) node _mshr_insertOH_T_3 = or(_mshr_insertOH_T, _mshr_insertOH_T_2) node _mshr_insertOH_T_4 = shl(_mshr_insertOH_T_3, 2) node _mshr_insertOH_T_5 = bits(_mshr_insertOH_T_4, 11, 0) node _mshr_insertOH_T_6 = or(_mshr_insertOH_T_3, _mshr_insertOH_T_5) node _mshr_insertOH_T_7 = shl(_mshr_insertOH_T_6, 4) node _mshr_insertOH_T_8 = bits(_mshr_insertOH_T_7, 11, 0) node _mshr_insertOH_T_9 = or(_mshr_insertOH_T_6, _mshr_insertOH_T_8) node _mshr_insertOH_T_10 = shl(_mshr_insertOH_T_9, 8) node _mshr_insertOH_T_11 = bits(_mshr_insertOH_T_10, 11, 0) node _mshr_insertOH_T_12 = or(_mshr_insertOH_T_9, _mshr_insertOH_T_11) node _mshr_insertOH_T_13 = bits(_mshr_insertOH_T_12, 11, 0) node _mshr_insertOH_T_14 = shl(_mshr_insertOH_T_13, 1) node _mshr_insertOH_T_15 = not(_mshr_insertOH_T_14) node _mshr_insertOH_T_16 = not(mshr_validOH) node _mshr_insertOH_T_17 = and(_mshr_insertOH_T_15, _mshr_insertOH_T_16) node mshr_insertOH = and(_mshr_insertOH_T_17, prioFilter) node _T_19 = bits(mshr_insertOH, 0, 0) node _T_20 = bits(mshr_insertOH, 1, 1) node _T_21 = bits(mshr_insertOH, 2, 2) node _T_22 = bits(mshr_insertOH, 3, 3) node _T_23 = bits(mshr_insertOH, 4, 4) node _T_24 = bits(mshr_insertOH, 5, 5) node _T_25 = bits(mshr_insertOH, 6, 6) node _T_26 = bits(mshr_insertOH, 7, 7) node _T_27 = bits(mshr_insertOH, 8, 8) node _T_28 = bits(mshr_insertOH, 9, 9) node _T_29 = bits(mshr_insertOH, 10, 10) node _T_30 = bits(mshr_insertOH, 11, 11) node _T_31 = bits(mshr_insertOH, 12, 12) node _T_32 = and(request.valid, alloc) node _T_33 = and(_T_32, _T_19) node _T_34 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_35 = and(_T_33, _T_34) when _T_35 : connect mshrs_0.io.allocate.valid, UInt<1>(0h1) connect mshrs_0.io.allocate.bits.set, request.bits.set connect mshrs_0.io.allocate.bits.put, request.bits.put connect mshrs_0.io.allocate.bits.offset, request.bits.offset connect mshrs_0.io.allocate.bits.tag, request.bits.tag connect mshrs_0.io.allocate.bits.source, request.bits.source connect mshrs_0.io.allocate.bits.size, request.bits.size connect mshrs_0.io.allocate.bits.param, request.bits.param connect mshrs_0.io.allocate.bits.opcode, request.bits.opcode connect mshrs_0.io.allocate.bits.control, request.bits.control connect mshrs_0.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_0.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_0.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_0.io.allocate.bits.repeat, UInt<1>(0h0) node _T_36 = and(request.valid, alloc) node _T_37 = and(_T_36, _T_20) node _T_38 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_39 = and(_T_37, _T_38) when _T_39 : connect mshrs_1.io.allocate.valid, UInt<1>(0h1) connect mshrs_1.io.allocate.bits.set, request.bits.set connect mshrs_1.io.allocate.bits.put, request.bits.put connect mshrs_1.io.allocate.bits.offset, request.bits.offset connect mshrs_1.io.allocate.bits.tag, request.bits.tag connect mshrs_1.io.allocate.bits.source, request.bits.source connect mshrs_1.io.allocate.bits.size, request.bits.size connect mshrs_1.io.allocate.bits.param, request.bits.param connect mshrs_1.io.allocate.bits.opcode, request.bits.opcode connect mshrs_1.io.allocate.bits.control, request.bits.control connect mshrs_1.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_1.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_1.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_1.io.allocate.bits.repeat, UInt<1>(0h0) node _T_40 = and(request.valid, alloc) node _T_41 = and(_T_40, _T_21) node _T_42 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_43 = and(_T_41, _T_42) when _T_43 : connect mshrs_2.io.allocate.valid, UInt<1>(0h1) connect mshrs_2.io.allocate.bits.set, request.bits.set connect mshrs_2.io.allocate.bits.put, request.bits.put connect mshrs_2.io.allocate.bits.offset, request.bits.offset connect mshrs_2.io.allocate.bits.tag, request.bits.tag connect mshrs_2.io.allocate.bits.source, request.bits.source connect mshrs_2.io.allocate.bits.size, request.bits.size connect mshrs_2.io.allocate.bits.param, request.bits.param connect mshrs_2.io.allocate.bits.opcode, request.bits.opcode connect mshrs_2.io.allocate.bits.control, request.bits.control connect mshrs_2.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_2.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_2.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_2.io.allocate.bits.repeat, UInt<1>(0h0) node _T_44 = and(request.valid, alloc) node _T_45 = and(_T_44, _T_22) node _T_46 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_47 = and(_T_45, _T_46) when _T_47 : connect mshrs_3.io.allocate.valid, UInt<1>(0h1) connect mshrs_3.io.allocate.bits.set, request.bits.set connect mshrs_3.io.allocate.bits.put, request.bits.put connect mshrs_3.io.allocate.bits.offset, request.bits.offset connect mshrs_3.io.allocate.bits.tag, request.bits.tag connect mshrs_3.io.allocate.bits.source, request.bits.source connect mshrs_3.io.allocate.bits.size, request.bits.size connect mshrs_3.io.allocate.bits.param, request.bits.param connect mshrs_3.io.allocate.bits.opcode, request.bits.opcode connect mshrs_3.io.allocate.bits.control, request.bits.control connect mshrs_3.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_3.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_3.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_3.io.allocate.bits.repeat, UInt<1>(0h0) node _T_48 = and(request.valid, alloc) node _T_49 = and(_T_48, _T_23) node _T_50 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_51 = and(_T_49, _T_50) when _T_51 : connect mshrs_4.io.allocate.valid, UInt<1>(0h1) connect mshrs_4.io.allocate.bits.set, request.bits.set connect mshrs_4.io.allocate.bits.put, request.bits.put connect mshrs_4.io.allocate.bits.offset, request.bits.offset connect mshrs_4.io.allocate.bits.tag, request.bits.tag connect mshrs_4.io.allocate.bits.source, request.bits.source connect mshrs_4.io.allocate.bits.size, request.bits.size connect mshrs_4.io.allocate.bits.param, request.bits.param connect mshrs_4.io.allocate.bits.opcode, request.bits.opcode connect mshrs_4.io.allocate.bits.control, request.bits.control connect mshrs_4.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_4.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_4.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_4.io.allocate.bits.repeat, UInt<1>(0h0) node _T_52 = and(request.valid, alloc) node _T_53 = and(_T_52, _T_24) node _T_54 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_55 = and(_T_53, _T_54) when _T_55 : connect mshrs_5.io.allocate.valid, UInt<1>(0h1) connect mshrs_5.io.allocate.bits.set, request.bits.set connect mshrs_5.io.allocate.bits.put, request.bits.put connect mshrs_5.io.allocate.bits.offset, request.bits.offset connect mshrs_5.io.allocate.bits.tag, request.bits.tag connect mshrs_5.io.allocate.bits.source, request.bits.source connect mshrs_5.io.allocate.bits.size, request.bits.size connect mshrs_5.io.allocate.bits.param, request.bits.param connect mshrs_5.io.allocate.bits.opcode, request.bits.opcode connect mshrs_5.io.allocate.bits.control, request.bits.control connect mshrs_5.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_5.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_5.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_5.io.allocate.bits.repeat, UInt<1>(0h0) node _T_56 = and(request.valid, alloc) node _T_57 = and(_T_56, _T_25) node _T_58 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_59 = and(_T_57, _T_58) when _T_59 : connect mshrs_6.io.allocate.valid, UInt<1>(0h1) connect mshrs_6.io.allocate.bits.set, request.bits.set connect mshrs_6.io.allocate.bits.put, request.bits.put connect mshrs_6.io.allocate.bits.offset, request.bits.offset connect mshrs_6.io.allocate.bits.tag, request.bits.tag connect mshrs_6.io.allocate.bits.source, request.bits.source connect mshrs_6.io.allocate.bits.size, request.bits.size connect mshrs_6.io.allocate.bits.param, request.bits.param connect mshrs_6.io.allocate.bits.opcode, request.bits.opcode connect mshrs_6.io.allocate.bits.control, request.bits.control connect mshrs_6.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_6.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_6.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_6.io.allocate.bits.repeat, UInt<1>(0h0) node _T_60 = and(request.valid, alloc) node _T_61 = and(_T_60, _T_26) node _T_62 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_63 = and(_T_61, _T_62) when _T_63 : connect mshrs_7.io.allocate.valid, UInt<1>(0h1) connect mshrs_7.io.allocate.bits.set, request.bits.set connect mshrs_7.io.allocate.bits.put, request.bits.put connect mshrs_7.io.allocate.bits.offset, request.bits.offset connect mshrs_7.io.allocate.bits.tag, request.bits.tag connect mshrs_7.io.allocate.bits.source, request.bits.source connect mshrs_7.io.allocate.bits.size, request.bits.size connect mshrs_7.io.allocate.bits.param, request.bits.param connect mshrs_7.io.allocate.bits.opcode, request.bits.opcode connect mshrs_7.io.allocate.bits.control, request.bits.control connect mshrs_7.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_7.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_7.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_7.io.allocate.bits.repeat, UInt<1>(0h0) node _T_64 = and(request.valid, alloc) node _T_65 = and(_T_64, _T_27) node _T_66 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_67 = and(_T_65, _T_66) when _T_67 : connect mshrs_8.io.allocate.valid, UInt<1>(0h1) connect mshrs_8.io.allocate.bits.set, request.bits.set connect mshrs_8.io.allocate.bits.put, request.bits.put connect mshrs_8.io.allocate.bits.offset, request.bits.offset connect mshrs_8.io.allocate.bits.tag, request.bits.tag connect mshrs_8.io.allocate.bits.source, request.bits.source connect mshrs_8.io.allocate.bits.size, request.bits.size connect mshrs_8.io.allocate.bits.param, request.bits.param connect mshrs_8.io.allocate.bits.opcode, request.bits.opcode connect mshrs_8.io.allocate.bits.control, request.bits.control connect mshrs_8.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_8.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_8.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_8.io.allocate.bits.repeat, UInt<1>(0h0) node _T_68 = and(request.valid, alloc) node _T_69 = and(_T_68, _T_28) node _T_70 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_71 = and(_T_69, _T_70) when _T_71 : connect mshrs_9.io.allocate.valid, UInt<1>(0h1) connect mshrs_9.io.allocate.bits.set, request.bits.set connect mshrs_9.io.allocate.bits.put, request.bits.put connect mshrs_9.io.allocate.bits.offset, request.bits.offset connect mshrs_9.io.allocate.bits.tag, request.bits.tag connect mshrs_9.io.allocate.bits.source, request.bits.source connect mshrs_9.io.allocate.bits.size, request.bits.size connect mshrs_9.io.allocate.bits.param, request.bits.param connect mshrs_9.io.allocate.bits.opcode, request.bits.opcode connect mshrs_9.io.allocate.bits.control, request.bits.control connect mshrs_9.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_9.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_9.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_9.io.allocate.bits.repeat, UInt<1>(0h0) node _T_72 = and(request.valid, alloc) node _T_73 = and(_T_72, _T_29) node _T_74 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_75 = and(_T_73, _T_74) when _T_75 : connect mshrs_10.io.allocate.valid, UInt<1>(0h1) connect mshrs_10.io.allocate.bits.set, request.bits.set connect mshrs_10.io.allocate.bits.put, request.bits.put connect mshrs_10.io.allocate.bits.offset, request.bits.offset connect mshrs_10.io.allocate.bits.tag, request.bits.tag connect mshrs_10.io.allocate.bits.source, request.bits.source connect mshrs_10.io.allocate.bits.size, request.bits.size connect mshrs_10.io.allocate.bits.param, request.bits.param connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode connect mshrs_10.io.allocate.bits.control, request.bits.control connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0) node _T_76 = and(request.valid, alloc) node _T_77 = and(_T_76, _T_30) node _T_78 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_79 = and(_T_77, _T_78) when _T_79 : connect mshrs_11.io.allocate.valid, UInt<1>(0h1) connect mshrs_11.io.allocate.bits.set, request.bits.set connect mshrs_11.io.allocate.bits.put, request.bits.put connect mshrs_11.io.allocate.bits.offset, request.bits.offset connect mshrs_11.io.allocate.bits.tag, request.bits.tag connect mshrs_11.io.allocate.bits.source, request.bits.source connect mshrs_11.io.allocate.bits.size, request.bits.size connect mshrs_11.io.allocate.bits.param, request.bits.param connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode connect mshrs_11.io.allocate.bits.control, request.bits.control connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0) node _T_80 = and(request.valid, nestB) node _T_81 = eq(mshrs_10.io.status.valid, UInt<1>(0h0)) node _T_82 = and(_T_80, _T_81) node _T_83 = eq(mshrs_11.io.status.valid, UInt<1>(0h0)) node _T_84 = and(_T_82, _T_83) node _T_85 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_86 = and(_T_84, _T_85) when _T_86 : connect mshrs_10.io.allocate.valid, UInt<1>(0h1) connect mshrs_10.io.allocate.bits.set, request.bits.set connect mshrs_10.io.allocate.bits.put, request.bits.put connect mshrs_10.io.allocate.bits.offset, request.bits.offset connect mshrs_10.io.allocate.bits.tag, request.bits.tag connect mshrs_10.io.allocate.bits.source, request.bits.source connect mshrs_10.io.allocate.bits.size, request.bits.size connect mshrs_10.io.allocate.bits.param, request.bits.param connect mshrs_10.io.allocate.bits.opcode, request.bits.opcode connect mshrs_10.io.allocate.bits.control, request.bits.control connect mshrs_10.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_10.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_10.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_10.io.allocate.bits.repeat, UInt<1>(0h0) node _T_87 = eq(request.bits.prio[0], UInt<1>(0h0)) node _T_88 = asUInt(reset) node _T_89 = eq(_T_88, UInt<1>(0h0)) when _T_89 : node _T_90 = eq(_T_87, UInt<1>(0h0)) when _T_90 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:291 assert (!request.bits.prio(0))\n") : printf assert(clock, _T_87, UInt<1>(0h1), "") : assert connect mshrs_10.io.allocate.bits.prio[0], UInt<1>(0h0) node _T_91 = and(request.valid, nestC) node _T_92 = eq(mshrs_11.io.status.valid, UInt<1>(0h0)) node _T_93 = and(_T_91, _T_92) node _T_94 = eq(mshr_uses_directory_assuming_no_bypass, UInt<1>(0h0)) node _T_95 = and(_T_93, _T_94) when _T_95 : connect mshrs_11.io.allocate.valid, UInt<1>(0h1) connect mshrs_11.io.allocate.bits.set, request.bits.set connect mshrs_11.io.allocate.bits.put, request.bits.put connect mshrs_11.io.allocate.bits.offset, request.bits.offset connect mshrs_11.io.allocate.bits.tag, request.bits.tag connect mshrs_11.io.allocate.bits.source, request.bits.source connect mshrs_11.io.allocate.bits.size, request.bits.size connect mshrs_11.io.allocate.bits.param, request.bits.param connect mshrs_11.io.allocate.bits.opcode, request.bits.opcode connect mshrs_11.io.allocate.bits.control, request.bits.control connect mshrs_11.io.allocate.bits.prio[0], request.bits.prio[0] connect mshrs_11.io.allocate.bits.prio[1], request.bits.prio[1] connect mshrs_11.io.allocate.bits.prio[2], request.bits.prio[2] connect mshrs_11.io.allocate.bits.repeat, UInt<1>(0h0) node _T_96 = eq(request.bits.prio[0], UInt<1>(0h0)) node _T_97 = asUInt(reset) node _T_98 = eq(_T_97, UInt<1>(0h0)) when _T_98 : node _T_99 = eq(_T_96, UInt<1>(0h0)) when _T_99 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:299 assert (!request.bits.prio(0))\n") : printf_1 assert(clock, _T_96, UInt<1>(0h1), "") : assert_1 node _T_100 = eq(request.bits.prio[1], UInt<1>(0h0)) node _T_101 = asUInt(reset) node _T_102 = eq(_T_101, UInt<1>(0h0)) when _T_102 : node _T_103 = eq(_T_100, UInt<1>(0h0)) when _T_103 : printf(clock, UInt<1>(0h1), "Assertion failed\n at Scheduler.scala:300 assert (!request.bits.prio(1))\n") : printf_2 assert(clock, _T_100, UInt<1>(0h1), "") : assert_2 connect mshrs_11.io.allocate.bits.prio[0], UInt<1>(0h0) connect mshrs_11.io.allocate.bits.prio[1], UInt<1>(0h0) node _dirTarget_T = mux(nestB, UInt<11>(0h400), UInt<12>(0h800)) node dirTarget = mux(alloc, mshr_insertOH, _dirTarget_T) node _directoryFanout_T = mux(alloc_uses_directory, dirTarget, UInt<1>(0h0)) node _directoryFanout_T_1 = mux(mshr_uses_directory, mshr_selectOH, _directoryFanout_T) reg directoryFanout : UInt, clock connect directoryFanout, _directoryFanout_T_1 node _mshrs_0_io_directory_valid_T = bits(directoryFanout, 0, 0) connect mshrs_0.io.directory.valid, _mshrs_0_io_directory_valid_T connect mshrs_0.io.directory.bits.way, directory.io.result.bits.way connect mshrs_0.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_0.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_0.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_0.io.directory.bits.state, directory.io.result.bits.state connect mshrs_0.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_1_io_directory_valid_T = bits(directoryFanout, 1, 1) connect mshrs_1.io.directory.valid, _mshrs_1_io_directory_valid_T connect mshrs_1.io.directory.bits.way, directory.io.result.bits.way connect mshrs_1.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_1.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_1.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_1.io.directory.bits.state, directory.io.result.bits.state connect mshrs_1.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_2_io_directory_valid_T = bits(directoryFanout, 2, 2) connect mshrs_2.io.directory.valid, _mshrs_2_io_directory_valid_T connect mshrs_2.io.directory.bits.way, directory.io.result.bits.way connect mshrs_2.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_2.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_2.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_2.io.directory.bits.state, directory.io.result.bits.state connect mshrs_2.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_3_io_directory_valid_T = bits(directoryFanout, 3, 3) connect mshrs_3.io.directory.valid, _mshrs_3_io_directory_valid_T connect mshrs_3.io.directory.bits.way, directory.io.result.bits.way connect mshrs_3.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_3.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_3.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_3.io.directory.bits.state, directory.io.result.bits.state connect mshrs_3.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_4_io_directory_valid_T = bits(directoryFanout, 4, 4) connect mshrs_4.io.directory.valid, _mshrs_4_io_directory_valid_T connect mshrs_4.io.directory.bits.way, directory.io.result.bits.way connect mshrs_4.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_4.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_4.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_4.io.directory.bits.state, directory.io.result.bits.state connect mshrs_4.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_5_io_directory_valid_T = bits(directoryFanout, 5, 5) connect mshrs_5.io.directory.valid, _mshrs_5_io_directory_valid_T connect mshrs_5.io.directory.bits.way, directory.io.result.bits.way connect mshrs_5.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_5.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_5.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_5.io.directory.bits.state, directory.io.result.bits.state connect mshrs_5.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_6_io_directory_valid_T = bits(directoryFanout, 6, 6) connect mshrs_6.io.directory.valid, _mshrs_6_io_directory_valid_T connect mshrs_6.io.directory.bits.way, directory.io.result.bits.way connect mshrs_6.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_6.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_6.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_6.io.directory.bits.state, directory.io.result.bits.state connect mshrs_6.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_7_io_directory_valid_T = bits(directoryFanout, 7, 7) connect mshrs_7.io.directory.valid, _mshrs_7_io_directory_valid_T connect mshrs_7.io.directory.bits.way, directory.io.result.bits.way connect mshrs_7.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_7.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_7.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_7.io.directory.bits.state, directory.io.result.bits.state connect mshrs_7.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_8_io_directory_valid_T = bits(directoryFanout, 8, 8) connect mshrs_8.io.directory.valid, _mshrs_8_io_directory_valid_T connect mshrs_8.io.directory.bits.way, directory.io.result.bits.way connect mshrs_8.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_8.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_8.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_8.io.directory.bits.state, directory.io.result.bits.state connect mshrs_8.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_9_io_directory_valid_T = bits(directoryFanout, 9, 9) connect mshrs_9.io.directory.valid, _mshrs_9_io_directory_valid_T connect mshrs_9.io.directory.bits.way, directory.io.result.bits.way connect mshrs_9.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_9.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_9.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_9.io.directory.bits.state, directory.io.result.bits.state connect mshrs_9.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_10_io_directory_valid_T = bits(directoryFanout, 10, 10) connect mshrs_10.io.directory.valid, _mshrs_10_io_directory_valid_T connect mshrs_10.io.directory.bits.way, directory.io.result.bits.way connect mshrs_10.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_10.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_10.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_10.io.directory.bits.state, directory.io.result.bits.state connect mshrs_10.io.directory.bits.dirty, directory.io.result.bits.dirty node _mshrs_11_io_directory_valid_T = bits(directoryFanout, 11, 11) connect mshrs_11.io.directory.valid, _mshrs_11_io_directory_valid_T connect mshrs_11.io.directory.bits.way, directory.io.result.bits.way connect mshrs_11.io.directory.bits.hit, directory.io.result.bits.hit connect mshrs_11.io.directory.bits.tag, directory.io.result.bits.tag connect mshrs_11.io.directory.bits.clients, directory.io.result.bits.clients connect mshrs_11.io.directory.bits.state, directory.io.result.bits.state connect mshrs_11.io.directory.bits.dirty, directory.io.result.bits.dirty node _sinkC_io_way_T = eq(mshrs_10.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_1 = and(mshrs_10.io.status.valid, _sinkC_io_way_T) node _sinkC_io_way_T_2 = eq(mshrs_0.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_3 = and(mshrs_0.io.status.valid, _sinkC_io_way_T_2) node _sinkC_io_way_T_4 = eq(mshrs_1.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_5 = and(mshrs_1.io.status.valid, _sinkC_io_way_T_4) node _sinkC_io_way_T_6 = eq(mshrs_2.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_7 = and(mshrs_2.io.status.valid, _sinkC_io_way_T_6) node _sinkC_io_way_T_8 = eq(mshrs_3.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_9 = and(mshrs_3.io.status.valid, _sinkC_io_way_T_8) node _sinkC_io_way_T_10 = eq(mshrs_4.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_11 = and(mshrs_4.io.status.valid, _sinkC_io_way_T_10) node _sinkC_io_way_T_12 = eq(mshrs_5.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_13 = and(mshrs_5.io.status.valid, _sinkC_io_way_T_12) node _sinkC_io_way_T_14 = eq(mshrs_6.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_15 = and(mshrs_6.io.status.valid, _sinkC_io_way_T_14) node _sinkC_io_way_T_16 = eq(mshrs_7.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_17 = and(mshrs_7.io.status.valid, _sinkC_io_way_T_16) node _sinkC_io_way_T_18 = eq(mshrs_8.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_19 = and(mshrs_8.io.status.valid, _sinkC_io_way_T_18) node _sinkC_io_way_T_20 = eq(mshrs_9.io.status.bits.set, sinkC.io.set) node _sinkC_io_way_T_21 = and(mshrs_9.io.status.valid, _sinkC_io_way_T_20) node _sinkC_io_way_T_22 = mux(_sinkC_io_way_T_3, mshrs_0.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_23 = mux(_sinkC_io_way_T_5, mshrs_1.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_24 = mux(_sinkC_io_way_T_7, mshrs_2.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_25 = mux(_sinkC_io_way_T_9, mshrs_3.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_26 = mux(_sinkC_io_way_T_11, mshrs_4.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_27 = mux(_sinkC_io_way_T_13, mshrs_5.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_28 = mux(_sinkC_io_way_T_15, mshrs_6.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_29 = mux(_sinkC_io_way_T_17, mshrs_7.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_30 = mux(_sinkC_io_way_T_19, mshrs_8.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_31 = mux(_sinkC_io_way_T_21, mshrs_9.io.status.bits.way, UInt<1>(0h0)) node _sinkC_io_way_T_32 = or(_sinkC_io_way_T_22, _sinkC_io_way_T_23) node _sinkC_io_way_T_33 = or(_sinkC_io_way_T_32, _sinkC_io_way_T_24) node _sinkC_io_way_T_34 = or(_sinkC_io_way_T_33, _sinkC_io_way_T_25) node _sinkC_io_way_T_35 = or(_sinkC_io_way_T_34, _sinkC_io_way_T_26) node _sinkC_io_way_T_36 = or(_sinkC_io_way_T_35, _sinkC_io_way_T_27) node _sinkC_io_way_T_37 = or(_sinkC_io_way_T_36, _sinkC_io_way_T_28) node _sinkC_io_way_T_38 = or(_sinkC_io_way_T_37, _sinkC_io_way_T_29) node _sinkC_io_way_T_39 = or(_sinkC_io_way_T_38, _sinkC_io_way_T_30) node _sinkC_io_way_T_40 = or(_sinkC_io_way_T_39, _sinkC_io_way_T_31) wire _sinkC_io_way_WIRE : UInt<4> connect _sinkC_io_way_WIRE, _sinkC_io_way_T_40 node _sinkC_io_way_T_41 = mux(_sinkC_io_way_T_1, mshrs_10.io.status.bits.way, _sinkC_io_way_WIRE) connect sinkC.io.way, _sinkC_io_way_T_41 wire _sinkD_io_way_WIRE : UInt<4>[12] connect _sinkD_io_way_WIRE[0], mshrs_0.io.status.bits.way connect _sinkD_io_way_WIRE[1], mshrs_1.io.status.bits.way connect _sinkD_io_way_WIRE[2], mshrs_2.io.status.bits.way connect _sinkD_io_way_WIRE[3], mshrs_3.io.status.bits.way connect _sinkD_io_way_WIRE[4], mshrs_4.io.status.bits.way connect _sinkD_io_way_WIRE[5], mshrs_5.io.status.bits.way connect _sinkD_io_way_WIRE[6], mshrs_6.io.status.bits.way connect _sinkD_io_way_WIRE[7], mshrs_7.io.status.bits.way connect _sinkD_io_way_WIRE[8], mshrs_8.io.status.bits.way connect _sinkD_io_way_WIRE[9], mshrs_9.io.status.bits.way connect _sinkD_io_way_WIRE[10], mshrs_10.io.status.bits.way connect _sinkD_io_way_WIRE[11], mshrs_11.io.status.bits.way connect sinkD.io.way, _sinkD_io_way_WIRE[sinkD.io.source] wire _sinkD_io_set_WIRE : UInt<11>[12] connect _sinkD_io_set_WIRE[0], mshrs_0.io.status.bits.set connect _sinkD_io_set_WIRE[1], mshrs_1.io.status.bits.set connect _sinkD_io_set_WIRE[2], mshrs_2.io.status.bits.set connect _sinkD_io_set_WIRE[3], mshrs_3.io.status.bits.set connect _sinkD_io_set_WIRE[4], mshrs_4.io.status.bits.set connect _sinkD_io_set_WIRE[5], mshrs_5.io.status.bits.set connect _sinkD_io_set_WIRE[6], mshrs_6.io.status.bits.set connect _sinkD_io_set_WIRE[7], mshrs_7.io.status.bits.set connect _sinkD_io_set_WIRE[8], mshrs_8.io.status.bits.set connect _sinkD_io_set_WIRE[9], mshrs_9.io.status.bits.set connect _sinkD_io_set_WIRE[10], mshrs_10.io.status.bits.set connect _sinkD_io_set_WIRE[11], mshrs_11.io.status.bits.set connect sinkD.io.set, _sinkD_io_set_WIRE[sinkD.io.source] connect sinkA.io.pb_pop, sourceD.io.pb_pop connect sourceD.io.pb_beat.corrupt, sinkA.io.pb_beat.corrupt connect sourceD.io.pb_beat.mask, sinkA.io.pb_beat.mask connect sourceD.io.pb_beat.data, sinkA.io.pb_beat.data connect sinkC.io.rel_pop, sourceD.io.rel_pop connect sourceD.io.rel_beat.corrupt, sinkC.io.rel_beat.corrupt connect sourceD.io.rel_beat.data, sinkC.io.rel_beat.data connect bankedStore.io.sinkC_adr, sinkC.io.bs_adr connect bankedStore.io.sinkC_dat.data, sinkC.io.bs_dat.data connect bankedStore.io.sinkD_adr, sinkD.io.bs_adr connect bankedStore.io.sinkD_dat.data, sinkD.io.bs_dat.data connect bankedStore.io.sourceC_adr, sourceC.io.bs_adr connect bankedStore.io.sourceD_radr, sourceD.io.bs_radr connect bankedStore.io.sourceD_wadr, sourceD.io.bs_wadr connect bankedStore.io.sourceD_wdat.data, sourceD.io.bs_wdat.data connect sourceC.io.bs_dat.data, bankedStore.io.sourceC_dat.data connect sourceD.io.bs_rdat.data, bankedStore.io.sourceD_rdat.data connect sourceD.io.evict_req.way, sourceC.io.evict_req.way connect sourceD.io.evict_req.set, sourceC.io.evict_req.set connect sourceD.io.grant_req.way, sinkD.io.grant_req.way connect sourceD.io.grant_req.set, sinkD.io.grant_req.set connect sourceC.io.evict_safe, sourceD.io.evict_safe connect sinkD.io.grant_safe, sourceD.io.grant_safe
module InclusiveCacheBankScheduler_2( // @[Scheduler.scala:27:7] input clock, // @[Scheduler.scala:27:7] input reset, // @[Scheduler.scala:27:7] output io_in_a_ready, // @[Scheduler.scala:29:14] input io_in_a_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_a_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_a_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_a_bits_address, // @[Scheduler.scala:29:14] input [15:0] io_in_a_bits_mask, // @[Scheduler.scala:29:14] input [127:0] io_in_a_bits_data, // @[Scheduler.scala:29:14] input io_in_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_b_ready, // @[Scheduler.scala:29:14] output io_in_b_valid, // @[Scheduler.scala:29:14] output [1:0] io_in_b_bits_param, // @[Scheduler.scala:29:14] output [31:0] io_in_b_bits_address, // @[Scheduler.scala:29:14] output io_in_c_ready, // @[Scheduler.scala:29:14] input io_in_c_valid, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_opcode, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_in_c_bits_size, // @[Scheduler.scala:29:14] input [5:0] io_in_c_bits_source, // @[Scheduler.scala:29:14] input [31:0] io_in_c_bits_address, // @[Scheduler.scala:29:14] input [127:0] io_in_c_bits_data, // @[Scheduler.scala:29:14] input io_in_c_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_d_ready, // @[Scheduler.scala:29:14] output io_in_d_valid, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_opcode, // @[Scheduler.scala:29:14] output [1:0] io_in_d_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_in_d_bits_size, // @[Scheduler.scala:29:14] output [5:0] io_in_d_bits_source, // @[Scheduler.scala:29:14] output [3:0] io_in_d_bits_sink, // @[Scheduler.scala:29:14] output io_in_d_bits_denied, // @[Scheduler.scala:29:14] output [127:0] io_in_d_bits_data, // @[Scheduler.scala:29:14] output io_in_d_bits_corrupt, // @[Scheduler.scala:29:14] input io_in_e_valid, // @[Scheduler.scala:29:14] input [3:0] io_in_e_bits_sink, // @[Scheduler.scala:29:14] input io_out_a_ready, // @[Scheduler.scala:29:14] output io_out_a_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_a_bits_size, // @[Scheduler.scala:29:14] output [3:0] io_out_a_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_a_bits_address, // @[Scheduler.scala:29:14] output [7:0] io_out_a_bits_mask, // @[Scheduler.scala:29:14] output [63:0] io_out_a_bits_data, // @[Scheduler.scala:29:14] output io_out_a_bits_corrupt, // @[Scheduler.scala:29:14] input io_out_c_ready, // @[Scheduler.scala:29:14] output io_out_c_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_opcode, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_param, // @[Scheduler.scala:29:14] output [2:0] io_out_c_bits_size, // @[Scheduler.scala:29:14] output [3:0] io_out_c_bits_source, // @[Scheduler.scala:29:14] output [31:0] io_out_c_bits_address, // @[Scheduler.scala:29:14] output [63:0] io_out_c_bits_data, // @[Scheduler.scala:29:14] output io_out_c_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_d_ready, // @[Scheduler.scala:29:14] input io_out_d_valid, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_opcode, // @[Scheduler.scala:29:14] input [1:0] io_out_d_bits_param, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_size, // @[Scheduler.scala:29:14] input [3:0] io_out_d_bits_source, // @[Scheduler.scala:29:14] input [2:0] io_out_d_bits_sink, // @[Scheduler.scala:29:14] input io_out_d_bits_denied, // @[Scheduler.scala:29:14] input [63:0] io_out_d_bits_data, // @[Scheduler.scala:29:14] input io_out_d_bits_corrupt, // @[Scheduler.scala:29:14] output io_out_e_valid, // @[Scheduler.scala:29:14] output [2:0] io_out_e_bits_sink, // @[Scheduler.scala:29:14] output io_req_ready, // @[Scheduler.scala:29:14] input io_req_valid, // @[Scheduler.scala:29:14] input [31:0] io_req_bits_address, // @[Scheduler.scala:29:14] output io_resp_valid // @[Scheduler.scala:29:14] ); wire [8:0] mshrs_11_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :295:103, :297:73] wire [8:0] mshrs_10_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70, :287:131, :289:74] wire [8:0] mshrs_9_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_8_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_7_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_6_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_5_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_4_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_3_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_2_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_1_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [8:0] mshrs_0_io_allocate_bits_tag; // @[Scheduler.scala:233:72, :280:83, :282:70] wire [5:0] request_bits_put; // @[Scheduler.scala:163:21] wire [5:0] request_bits_offset; // @[Scheduler.scala:163:21] wire [8:0] request_bits_tag; // @[Scheduler.scala:163:21] wire [5:0] request_bits_source; // @[Scheduler.scala:163:21] wire [2:0] request_bits_size; // @[Scheduler.scala:163:21] wire [2:0] request_bits_param; // @[Scheduler.scala:163:21] wire [2:0] request_bits_opcode; // @[Scheduler.scala:163:21] wire request_bits_control; // @[Scheduler.scala:163:21] wire request_bits_prio_2; // @[Scheduler.scala:163:21] wire request_bits_prio_0; // @[Scheduler.scala:163:21] wire _mshrs_11_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46] wire _mshrs_11_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_11_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_11_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_11_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_11_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_11_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_11_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_11_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_11_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_11_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_11_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_11_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_11_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_11_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_11_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_10_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_10_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_10_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_10_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_10_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_10_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_10_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_10_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_10_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_10_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_10_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_10_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_10_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_10_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_10_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_10_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_10_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_9_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_9_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_9_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_9_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_9_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_9_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_9_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_9_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_9_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_9_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_9_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_9_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_9_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_9_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_9_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_9_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_8_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_8_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_8_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_8_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_8_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_8_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_8_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_8_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_8_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_8_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_8_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_8_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_8_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_8_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_8_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_8_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_7_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_7_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_7_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_7_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_7_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_7_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_7_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_7_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_7_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_7_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_7_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_7_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_7_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_7_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_7_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_7_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_6_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_6_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_6_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_6_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_6_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_6_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_6_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_6_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_6_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_6_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_5_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_5_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_5_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_5_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_5_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_5_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_5_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_5_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_5_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_5_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_4_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_4_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_4_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_4_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_4_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_4_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_4_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_4_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_4_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_4_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_3_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_3_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_3_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_3_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_3_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_3_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_3_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_3_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_3_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_3_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_2_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_2_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_2_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_2_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_2_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_2_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_2_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_2_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_2_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_2_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_1_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_1_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_1_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_1_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_1_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_1_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_1_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_1_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_1_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_1_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_status_bits_set; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_0_io_status_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestB; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_blockC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_status_bits_nestC; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_schedule_bits_a_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_a_bits_set; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_a_bits_param; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_a_bits_block; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_b_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_schedule_bits_b_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_b_bits_set; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_b_bits_clients; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_c_bits_param; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_schedule_bits_c_bits_tag; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_c_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_0_io_schedule_bits_c_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_control; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_opcode; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_param; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_d_bits_size; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_source; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_schedule_bits_d_bits_tag; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_offset; // @[Scheduler.scala:71:46] wire [5:0] _mshrs_0_io_schedule_bits_d_bits_put; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_d_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_0_io_schedule_bits_d_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_d_bits_bad; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46] wire [2:0] _mshrs_0_io_schedule_bits_e_bits_sink; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46] wire [10:0] _mshrs_0_io_schedule_bits_dir_bits_set; // @[Scheduler.scala:71:46] wire [3:0] _mshrs_0_io_schedule_bits_dir_bits_way; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46] wire [1:0] _mshrs_0_io_schedule_bits_dir_bits_data_state; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Scheduler.scala:71:46] wire [8:0] _mshrs_0_io_schedule_bits_dir_bits_data_tag; // @[Scheduler.scala:71:46] wire _mshrs_0_io_schedule_bits_reload; // @[Scheduler.scala:71:46] wire _requests_io_push_ready; // @[Scheduler.scala:70:24] wire [35:0] _requests_io_valid; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_0; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_1; // @[Scheduler.scala:70:24] wire _requests_io_data_prio_2; // @[Scheduler.scala:70:24] wire _requests_io_data_control; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_opcode; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_param; // @[Scheduler.scala:70:24] wire [2:0] _requests_io_data_size; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_source; // @[Scheduler.scala:70:24] wire [8:0] _requests_io_data_tag; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_offset; // @[Scheduler.scala:70:24] wire [5:0] _requests_io_data_put; // @[Scheduler.scala:70:24] wire _bankedStore_io_sinkC_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sinkD_adr_ready; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceC_adr_ready; // @[Scheduler.scala:69:27] wire [63:0] _bankedStore_io_sourceC_dat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_radr_ready; // @[Scheduler.scala:69:27] wire [127:0] _bankedStore_io_sourceD_rdat_data; // @[Scheduler.scala:69:27] wire _bankedStore_io_sourceD_wadr_ready; // @[Scheduler.scala:69:27] wire _directory_io_write_ready; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_dirty; // @[Scheduler.scala:68:25] wire [1:0] _directory_io_result_bits_state; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_clients; // @[Scheduler.scala:68:25] wire [8:0] _directory_io_result_bits_tag; // @[Scheduler.scala:68:25] wire _directory_io_result_bits_hit; // @[Scheduler.scala:68:25] wire [3:0] _directory_io_result_bits_way; // @[Scheduler.scala:68:25] wire _directory_io_ready; // @[Scheduler.scala:68:25] wire _sinkX_io_req_valid; // @[Scheduler.scala:58:21] wire [8:0] _sinkX_io_req_bits_tag; // @[Scheduler.scala:58:21] wire [10:0] _sinkX_io_req_bits_set; // @[Scheduler.scala:58:21] wire _sinkE_io_resp_valid; // @[Scheduler.scala:57:21] wire [3:0] _sinkE_io_resp_bits_sink; // @[Scheduler.scala:57:21] wire _sinkD_io_resp_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_last; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_opcode; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_param; // @[Scheduler.scala:56:21] wire [3:0] _sinkD_io_resp_bits_source; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_resp_bits_sink; // @[Scheduler.scala:56:21] wire _sinkD_io_resp_bits_denied; // @[Scheduler.scala:56:21] wire [3:0] _sinkD_io_source; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_valid; // @[Scheduler.scala:56:21] wire _sinkD_io_bs_adr_bits_noop; // @[Scheduler.scala:56:21] wire [3:0] _sinkD_io_bs_adr_bits_way; // @[Scheduler.scala:56:21] wire [10:0] _sinkD_io_bs_adr_bits_set; // @[Scheduler.scala:56:21] wire [2:0] _sinkD_io_bs_adr_bits_beat; // @[Scheduler.scala:56:21] wire [63:0] _sinkD_io_bs_dat_data; // @[Scheduler.scala:56:21] wire [10:0] _sinkD_io_grant_req_set; // @[Scheduler.scala:56:21] wire [3:0] _sinkD_io_grant_req_way; // @[Scheduler.scala:56:21] wire _sinkC_io_req_valid; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_opcode; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_param; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_req_bits_size; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_source; // @[Scheduler.scala:55:21] wire [8:0] _sinkC_io_req_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_offset; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_req_bits_put; // @[Scheduler.scala:55:21] wire [10:0] _sinkC_io_req_bits_set; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_last; // @[Scheduler.scala:55:21] wire [10:0] _sinkC_io_resp_bits_set; // @[Scheduler.scala:55:21] wire [8:0] _sinkC_io_resp_bits_tag; // @[Scheduler.scala:55:21] wire [5:0] _sinkC_io_resp_bits_source; // @[Scheduler.scala:55:21] wire [2:0] _sinkC_io_resp_bits_param; // @[Scheduler.scala:55:21] wire _sinkC_io_resp_bits_data; // @[Scheduler.scala:55:21] wire [10:0] _sinkC_io_set; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_valid; // @[Scheduler.scala:55:21] wire _sinkC_io_bs_adr_bits_noop; // @[Scheduler.scala:55:21] wire [3:0] _sinkC_io_bs_adr_bits_way; // @[Scheduler.scala:55:21] wire [10:0] _sinkC_io_bs_adr_bits_set; // @[Scheduler.scala:55:21] wire [1:0] _sinkC_io_bs_adr_bits_beat; // @[Scheduler.scala:55:21] wire [1:0] _sinkC_io_bs_adr_bits_mask; // @[Scheduler.scala:55:21] wire [127:0] _sinkC_io_bs_dat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_pop_ready; // @[Scheduler.scala:55:21] wire [127:0] _sinkC_io_rel_beat_data; // @[Scheduler.scala:55:21] wire _sinkC_io_rel_beat_corrupt; // @[Scheduler.scala:55:21] wire _sinkA_io_req_valid; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21] wire [2:0] _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21] wire [8:0] _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21] wire [5:0] _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21] wire [10:0] _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_pop_ready; // @[Scheduler.scala:54:21] wire [127:0] _sinkA_io_pb_beat_data; // @[Scheduler.scala:54:21] wire [15:0] _sinkA_io_pb_beat_mask; // @[Scheduler.scala:54:21] wire _sinkA_io_pb_beat_corrupt; // @[Scheduler.scala:54:21] wire _sourceX_io_req_ready; // @[Scheduler.scala:45:23] wire _sourceE_io_req_ready; // @[Scheduler.scala:44:23] wire _sourceD_io_req_ready; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_pb_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_pb_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_valid; // @[Scheduler.scala:43:23] wire [5:0] _sourceD_io_rel_pop_bits_index; // @[Scheduler.scala:43:23] wire _sourceD_io_rel_pop_bits_last; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_radr_valid; // @[Scheduler.scala:43:23] wire [3:0] _sourceD_io_bs_radr_bits_way; // @[Scheduler.scala:43:23] wire [10:0] _sourceD_io_bs_radr_bits_set; // @[Scheduler.scala:43:23] wire [1:0] _sourceD_io_bs_radr_bits_beat; // @[Scheduler.scala:43:23] wire [1:0] _sourceD_io_bs_radr_bits_mask; // @[Scheduler.scala:43:23] wire _sourceD_io_bs_wadr_valid; // @[Scheduler.scala:43:23] wire [3:0] _sourceD_io_bs_wadr_bits_way; // @[Scheduler.scala:43:23] wire [10:0] _sourceD_io_bs_wadr_bits_set; // @[Scheduler.scala:43:23] wire [1:0] _sourceD_io_bs_wadr_bits_beat; // @[Scheduler.scala:43:23] wire [1:0] _sourceD_io_bs_wadr_bits_mask; // @[Scheduler.scala:43:23] wire [127:0] _sourceD_io_bs_wdat_data; // @[Scheduler.scala:43:23] wire _sourceD_io_evict_safe; // @[Scheduler.scala:43:23] wire _sourceD_io_grant_safe; // @[Scheduler.scala:43:23] wire _sourceC_io_req_ready; // @[Scheduler.scala:42:23] wire _sourceC_io_bs_adr_valid; // @[Scheduler.scala:42:23] wire [3:0] _sourceC_io_bs_adr_bits_way; // @[Scheduler.scala:42:23] wire [10:0] _sourceC_io_bs_adr_bits_set; // @[Scheduler.scala:42:23] wire [2:0] _sourceC_io_bs_adr_bits_beat; // @[Scheduler.scala:42:23] wire [10:0] _sourceC_io_evict_req_set; // @[Scheduler.scala:42:23] wire [3:0] _sourceC_io_evict_req_way; // @[Scheduler.scala:42:23] wire _sourceB_io_req_ready; // @[Scheduler.scala:41:23] wire _sourceA_io_req_ready; // @[Scheduler.scala:40:23] wire io_in_a_valid_0 = io_in_a_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_opcode_0 = io_in_a_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_param_0 = io_in_a_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_a_bits_size_0 = io_in_a_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_a_bits_source_0 = io_in_a_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_a_bits_address_0 = io_in_a_bits_address; // @[Scheduler.scala:27:7] wire [15:0] io_in_a_bits_mask_0 = io_in_a_bits_mask; // @[Scheduler.scala:27:7] wire [127:0] io_in_a_bits_data_0 = io_in_a_bits_data; // @[Scheduler.scala:27:7] wire io_in_a_bits_corrupt_0 = io_in_a_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_b_ready_0 = io_in_b_ready; // @[Scheduler.scala:27:7] wire io_in_c_valid_0 = io_in_c_valid; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_opcode_0 = io_in_c_bits_opcode; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_param_0 = io_in_c_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_in_c_bits_size_0 = io_in_c_bits_size; // @[Scheduler.scala:27:7] wire [5:0] io_in_c_bits_source_0 = io_in_c_bits_source; // @[Scheduler.scala:27:7] wire [31:0] io_in_c_bits_address_0 = io_in_c_bits_address; // @[Scheduler.scala:27:7] wire [127:0] io_in_c_bits_data_0 = io_in_c_bits_data; // @[Scheduler.scala:27:7] wire io_in_c_bits_corrupt_0 = io_in_c_bits_corrupt; // @[Scheduler.scala:27:7] wire io_in_d_ready_0 = io_in_d_ready; // @[Scheduler.scala:27:7] wire io_in_e_valid_0 = io_in_e_valid; // @[Scheduler.scala:27:7] wire [3:0] io_in_e_bits_sink_0 = io_in_e_bits_sink; // @[Scheduler.scala:27:7] wire io_out_a_ready_0 = io_out_a_ready; // @[Scheduler.scala:27:7] wire io_out_c_ready_0 = io_out_c_ready; // @[Scheduler.scala:27:7] wire io_out_d_valid_0 = io_out_d_valid; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_opcode_0 = io_out_d_bits_opcode; // @[Scheduler.scala:27:7] wire [1:0] io_out_d_bits_param_0 = io_out_d_bits_param; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_size_0 = io_out_d_bits_size; // @[Scheduler.scala:27:7] wire [3:0] io_out_d_bits_source_0 = io_out_d_bits_source; // @[Scheduler.scala:27:7] wire [2:0] io_out_d_bits_sink_0 = io_out_d_bits_sink; // @[Scheduler.scala:27:7] wire io_out_d_bits_denied_0 = io_out_d_bits_denied; // @[Scheduler.scala:27:7] wire [63:0] io_out_d_bits_data_0 = io_out_d_bits_data; // @[Scheduler.scala:27:7] wire io_out_d_bits_corrupt_0 = io_out_d_bits_corrupt; // @[Scheduler.scala:27:7] wire io_req_valid_0 = io_req_valid; // @[Scheduler.scala:27:7] wire [31:0] io_req_bits_address_0 = io_req_bits_address; // @[Scheduler.scala:27:7] wire io_in_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_valid = 1'h0; // @[Scheduler.scala:27:7] wire io_out_b_bits_corrupt = 1'h0; // @[Scheduler.scala:27:7] wire io_resp_bits_fail = 1'h0; // @[Scheduler.scala:27:7] wire schedule_x_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_11_bits_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_12_fail = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_196 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_197 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_198 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_199 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_200 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_201 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_202 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_203 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_204 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_205 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_206 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_207 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_208 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_209 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_210 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_211 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_212 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_213 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_214 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_215 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_216 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_217 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_218 = 1'h0; // @[Mux.scala:30:73] wire _schedule_WIRE_13 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_574 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_575 = 1'h0; // @[Mux.scala:30:73] wire _schedule_T_598 = 1'h0; // @[Mux.scala:30:73] wire request_bits_prio_1 = 1'h0; // @[Scheduler.scala:163:21] wire _request_bits_T_prio_1 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_prio_2 = 1'h0; // @[Scheduler.scala:166:22] wire _request_bits_T_1_prio_1 = 1'h0; // @[Scheduler.scala:165:22] wire blockB = 1'h0; // @[Scheduler.scala:175:70] wire nestB = 1'h0; // @[Scheduler.scala:179:70] wire _view__WIRE_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_1_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_2_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_3_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_4_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_5_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_6_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_7_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_8_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_9_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_10_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _view__WIRE_11_prio_1 = 1'h0; // @[Scheduler.scala:233:95] wire _request_alloc_cases_T_4 = 1'h0; // @[Scheduler.scala:259:13] wire _request_alloc_cases_T_6 = 1'h0; // @[Scheduler.scala:259:56] wire _request_alloc_cases_T_8 = 1'h0; // @[Scheduler.scala:259:84] wire [2:0] io_in_b_bits_opcode = 3'h6; // @[Scheduler.scala:27:7] wire [2:0] io_in_b_bits_size = 3'h6; // @[Scheduler.scala:27:7] wire [5:0] io_in_b_bits_source = 6'h28; // @[Scheduler.scala:27:7] wire [15:0] io_in_b_bits_mask = 16'hFFFF; // @[Scheduler.scala:27:7] wire [127:0] io_in_b_bits_data = 128'h0; // @[Scheduler.scala:27:7] wire io_in_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_b_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_out_e_ready = 1'h1; // @[Scheduler.scala:27:7] wire io_resp_ready = 1'h1; // @[Scheduler.scala:27:7] wire _mshr_request_T_253 = 1'h1; // @[Scheduler.scala:107:28] wire _request_bits_T_prio_0 = 1'h1; // @[Scheduler.scala:166:22] wire _queue_T_1 = 1'h1; // @[Scheduler.scala:185:35] wire _queue_T_5 = 1'h1; // @[Scheduler.scala:185:55] wire [2:0] io_out_b_bits_opcode = 3'h0; // @[Scheduler.scala:27:7] wire [2:0] io_out_b_bits_size = 3'h0; // @[Scheduler.scala:27:7] wire [1:0] io_out_b_bits_param = 2'h0; // @[Scheduler.scala:27:7] wire [3:0] io_out_b_bits_source = 4'h0; // @[Scheduler.scala:27:7] wire [3:0] _schedule_WIRE_19_bits_sink = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_20_sink = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_334 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_335 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_336 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_337 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_338 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_339 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_340 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_341 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_342 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_343 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_344 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_345 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_346 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_347 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_348 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_349 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_350 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_351 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_352 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_353 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_354 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_355 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_356 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_23 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_38_bits_source = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_39_source = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_748 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_749 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_750 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_751 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_752 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_753 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_754 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_755 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_756 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_757 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_758 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_759 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_760 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_761 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_762 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_763 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_764 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_765 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_766 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_767 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_768 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_769 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_770 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_44 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_55_bits_source = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_56_source = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_978 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_979 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_980 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_981 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_982 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_983 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_984 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_985 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_986 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_987 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_988 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_989 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_990 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_991 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_992 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_993 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_994 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_995 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_996 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_997 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_998 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_999 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_T_1000 = 4'h0; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_58 = 4'h0; // @[Mux.scala:30:73] wire [31:0] io_out_b_bits_address = 32'h0; // @[Scheduler.scala:27:7] wire [7:0] io_out_b_bits_mask = 8'h0; // @[Scheduler.scala:27:7] wire [63:0] io_out_b_bits_data = 64'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_0 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_1 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_2 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_3 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_4 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_5 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_6 = 16'h0; // @[Scheduler.scala:27:7] wire [15:0] io_ways_7 = 16'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_0 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_1 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_2 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_3 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_4 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_5 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_6 = 11'h0; // @[Scheduler.scala:27:7] wire [10:0] io_divs_7 = 11'h0; // @[Scheduler.scala:27:7] wire [11:0] _lowerMatches1_T_1 = 12'h800; // @[Scheduler.scala:200:43] wire [11:0] _dirTarget_T = 12'h800; // @[Scheduler.scala:306:48] wire [4:0] _requests_io_push_bits_index_T_43 = 5'h0; // @[Mux.scala:30:73] wire [9:0] _prioFilter_T_1 = 10'h3FF; // @[Scheduler.scala:182:69] wire [10:0] _lowerMatches1_T_3 = 11'h400; // @[Scheduler.scala:201:43] wire io_in_a_ready_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_b_bits_param_0; // @[Scheduler.scala:27:7] wire [31:0] io_in_b_bits_address_0; // @[Scheduler.scala:27:7] wire io_in_b_valid_0; // @[Scheduler.scala:27:7] wire io_in_c_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_opcode_0; // @[Scheduler.scala:27:7] wire [1:0] io_in_d_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_in_d_bits_size_0; // @[Scheduler.scala:27:7] wire [5:0] io_in_d_bits_source_0; // @[Scheduler.scala:27:7] wire [3:0] io_in_d_bits_sink_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_denied_0; // @[Scheduler.scala:27:7] wire [127:0] io_in_d_bits_data_0; // @[Scheduler.scala:27:7] wire io_in_d_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_in_d_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_a_bits_size_0; // @[Scheduler.scala:27:7] wire [3:0] io_out_a_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_a_bits_address_0; // @[Scheduler.scala:27:7] wire [7:0] io_out_a_bits_mask_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_a_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_a_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_a_valid_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_opcode_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_param_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_c_bits_size_0; // @[Scheduler.scala:27:7] wire [3:0] io_out_c_bits_source_0; // @[Scheduler.scala:27:7] wire [31:0] io_out_c_bits_address_0; // @[Scheduler.scala:27:7] wire [63:0] io_out_c_bits_data_0; // @[Scheduler.scala:27:7] wire io_out_c_bits_corrupt_0; // @[Scheduler.scala:27:7] wire io_out_c_valid_0; // @[Scheduler.scala:27:7] wire io_out_d_ready_0; // @[Scheduler.scala:27:7] wire [2:0] io_out_e_bits_sink_0; // @[Scheduler.scala:27:7] wire io_out_e_valid_0; // @[Scheduler.scala:27:7] wire io_req_ready_0; // @[Scheduler.scala:27:7] wire io_resp_valid_0; // @[Scheduler.scala:27:7] wire [10:0] _nestedwb_set_T; // @[Scheduler.scala:155:24] wire [8:0] _nestedwb_tag_T; // @[Scheduler.scala:156:24] wire _nestedwb_b_toN_T_2; // @[Scheduler.scala:157:75] wire _nestedwb_b_toB_T_2; // @[Scheduler.scala:158:75] wire _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:159:37] wire _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:160:75] wire [10:0] nestedwb_set; // @[Scheduler.scala:75:22] wire [8:0] nestedwb_tag; // @[Scheduler.scala:75:22] wire nestedwb_b_toN; // @[Scheduler.scala:75:22] wire nestedwb_b_toB; // @[Scheduler.scala:75:22] wire nestedwb_b_clr_dirty; // @[Scheduler.scala:75:22] wire nestedwb_c_set_dirty; // @[Scheduler.scala:75:22] wire _mshrs_0_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_0_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_0_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_0_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_0_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h0; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_0_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_0_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_0_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h0; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_0_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_0_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_1_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_1_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_1_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_1_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_1_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h1; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_1_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_1_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_1_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h1; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_1_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_1_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_2_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_2_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_2_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_2_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_2_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h2; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_2_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_2_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_2_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h2; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_2_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_2_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_3_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_3_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_3_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_3_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_3_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h3; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_3_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_3_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_3_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h3; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_3_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_3_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_4_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_4_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_4_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_4_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_4_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h4; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_4_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_4_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_4_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h4; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_4_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_4_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_5_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_5_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_5_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_5_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_5_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h5; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_5_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_5_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_5_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h5; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_5_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_5_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_6_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_6_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_6_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_6_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_6_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h6; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_6_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_6_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_6_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h6; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_6_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_6_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_7_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_7_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_7_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_7_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_7_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h7; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_7_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_7_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_7_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h7; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_7_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_7_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_8_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_8_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_8_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_8_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_8_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h8; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_8_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_8_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_8_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h8; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_8_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_8_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_9_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_9_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_9_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_9_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_9_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'h9; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_9_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_9_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_9_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'h9; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_9_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_9_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_10_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_10_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_10_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_10_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hA; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_10_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_10_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_10_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hA; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_10_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_10_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshrs_11_io_sinkc_valid_T = _sinkC_io_resp_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:55:21, :71:46, :79:71] wire _mshrs_11_io_sinkc_valid_T_1 = _sinkC_io_resp_valid & _mshrs_11_io_sinkc_valid_T; // @[Scheduler.scala:55:21, :79:{45,71}] wire _mshrs_11_io_sinkd_valid_T = _sinkD_io_resp_bits_source == 4'hB; // @[Scheduler.scala:56:21, :80:74] wire _mshrs_11_io_sinkd_valid_T_1 = _sinkD_io_resp_valid & _mshrs_11_io_sinkd_valid_T; // @[Scheduler.scala:56:21, :80:{45,74}] wire _mshrs_11_io_sinke_valid_T = _sinkE_io_resp_bits_sink == 4'hB; // @[Scheduler.scala:57:21, :81:74] wire _mshrs_11_io_sinke_valid_T_1 = _sinkE_io_resp_valid & _mshrs_11_io_sinke_valid_T; // @[Scheduler.scala:57:21, :81:{45,74}] wire _mshr_stall_abc_T = _mshrs_0_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_1 = _mshrs_10_io_status_valid & _mshr_stall_abc_T; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_2 = _mshrs_0_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_3 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_2; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_0 = _mshr_stall_abc_T_1 | _mshr_stall_abc_T_3; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_4 = _mshrs_1_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_5 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_4; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_6 = _mshrs_1_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_7 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_6; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_1 = _mshr_stall_abc_T_5 | _mshr_stall_abc_T_7; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_8 = _mshrs_2_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_9 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_8; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_10 = _mshrs_2_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_11 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_10; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_2 = _mshr_stall_abc_T_9 | _mshr_stall_abc_T_11; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_12 = _mshrs_3_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_13 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_12; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_14 = _mshrs_3_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_15 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_14; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_3 = _mshr_stall_abc_T_13 | _mshr_stall_abc_T_15; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_16 = _mshrs_4_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_17 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_16; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_18 = _mshrs_4_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_19 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_18; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_4 = _mshr_stall_abc_T_17 | _mshr_stall_abc_T_19; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_20 = _mshrs_5_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_21 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_20; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_22 = _mshrs_5_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_23 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_22; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_5 = _mshr_stall_abc_T_21 | _mshr_stall_abc_T_23; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_24 = _mshrs_6_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_25 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_24; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_26 = _mshrs_6_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_27 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_26; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_6 = _mshr_stall_abc_T_25 | _mshr_stall_abc_T_27; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_28 = _mshrs_7_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_29 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_28; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_30 = _mshrs_7_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_31 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_30; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_7 = _mshr_stall_abc_T_29 | _mshr_stall_abc_T_31; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_32 = _mshrs_8_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_33 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_32; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_34 = _mshrs_8_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_35 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_34; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_8 = _mshr_stall_abc_T_33 | _mshr_stall_abc_T_35; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_abc_T_36 = _mshrs_9_io_status_bits_set == _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :90:54] wire _mshr_stall_abc_T_37 = _mshrs_10_io_status_valid & _mshr_stall_abc_T_36; // @[Scheduler.scala:71:46, :90:{30,54}] wire _mshr_stall_abc_T_38 = _mshrs_9_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :91:54] wire _mshr_stall_abc_T_39 = _mshrs_11_io_status_valid & _mshr_stall_abc_T_38; // @[Scheduler.scala:71:46, :91:{30,54}] wire mshr_stall_abc_9 = _mshr_stall_abc_T_37 | _mshr_stall_abc_T_39; // @[Scheduler.scala:90:{30,86}, :91:30] wire _mshr_stall_bc_T = _mshrs_10_io_status_bits_set == _mshrs_11_io_status_bits_set; // @[Scheduler.scala:71:46, :94:58] wire mshr_stall_bc = _mshrs_11_io_status_valid & _mshr_stall_bc_T; // @[Scheduler.scala:71:46, :94:{28,58}] wire stall_abc_0 = mshr_stall_abc_0 & _mshrs_0_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_1 = mshr_stall_abc_1 & _mshrs_1_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_2 = mshr_stall_abc_2 & _mshrs_2_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_3 = mshr_stall_abc_3 & _mshrs_3_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_4 = mshr_stall_abc_4 & _mshrs_4_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_5 = mshr_stall_abc_5 & _mshrs_5_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_6 = mshr_stall_abc_6 & _mshrs_6_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_7 = mshr_stall_abc_7 & _mshrs_7_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_8 = mshr_stall_abc_8 & _mshrs_8_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire stall_abc_9 = mshr_stall_abc_9 & _mshrs_9_io_status_valid; // @[Scheduler.scala:71:46, :90:86, :99:73] wire _mshr_request_T = ~mshr_stall_abc_0; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_1 = _mshrs_0_io_schedule_valid & _mshr_request_T; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_2 = ~_mshrs_0_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_3 = _sourceA_io_req_ready | _mshr_request_T_2; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_4 = _mshr_request_T_1 & _mshr_request_T_3; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_5 = ~_mshrs_0_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_6 = _sourceB_io_req_ready | _mshr_request_T_5; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_7 = _mshr_request_T_4 & _mshr_request_T_6; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_8 = ~_mshrs_0_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_9 = _sourceC_io_req_ready | _mshr_request_T_8; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_10 = _mshr_request_T_7 & _mshr_request_T_9; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_11 = ~_mshrs_0_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_12 = _sourceD_io_req_ready | _mshr_request_T_11; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_13 = _mshr_request_T_10 & _mshr_request_T_12; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_14 = ~_mshrs_0_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_15 = _sourceE_io_req_ready | _mshr_request_T_14; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_16 = _mshr_request_T_13 & _mshr_request_T_15; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_17 = ~_mshrs_0_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_18 = _sourceX_io_req_ready | _mshr_request_T_17; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_19 = _mshr_request_T_16 & _mshr_request_T_18; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_20 = ~_mshrs_0_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_21 = _directory_io_write_ready | _mshr_request_T_20; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_22 = _mshr_request_T_19 & _mshr_request_T_21; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_23 = ~mshr_stall_abc_1; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_24 = _mshrs_1_io_schedule_valid & _mshr_request_T_23; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_25 = ~_mshrs_1_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_26 = _sourceA_io_req_ready | _mshr_request_T_25; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_27 = _mshr_request_T_24 & _mshr_request_T_26; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_28 = ~_mshrs_1_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_29 = _sourceB_io_req_ready | _mshr_request_T_28; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_30 = _mshr_request_T_27 & _mshr_request_T_29; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_31 = ~_mshrs_1_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_32 = _sourceC_io_req_ready | _mshr_request_T_31; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_33 = _mshr_request_T_30 & _mshr_request_T_32; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_34 = ~_mshrs_1_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_35 = _sourceD_io_req_ready | _mshr_request_T_34; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_36 = _mshr_request_T_33 & _mshr_request_T_35; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_37 = ~_mshrs_1_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_38 = _sourceE_io_req_ready | _mshr_request_T_37; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_39 = _mshr_request_T_36 & _mshr_request_T_38; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_40 = ~_mshrs_1_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_41 = _sourceX_io_req_ready | _mshr_request_T_40; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_42 = _mshr_request_T_39 & _mshr_request_T_41; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_43 = ~_mshrs_1_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_44 = _directory_io_write_ready | _mshr_request_T_43; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_45 = _mshr_request_T_42 & _mshr_request_T_44; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_46 = ~mshr_stall_abc_2; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_47 = _mshrs_2_io_schedule_valid & _mshr_request_T_46; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_48 = ~_mshrs_2_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_49 = _sourceA_io_req_ready | _mshr_request_T_48; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_50 = _mshr_request_T_47 & _mshr_request_T_49; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_51 = ~_mshrs_2_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_52 = _sourceB_io_req_ready | _mshr_request_T_51; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_53 = _mshr_request_T_50 & _mshr_request_T_52; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_54 = ~_mshrs_2_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_55 = _sourceC_io_req_ready | _mshr_request_T_54; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_56 = _mshr_request_T_53 & _mshr_request_T_55; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_57 = ~_mshrs_2_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_58 = _sourceD_io_req_ready | _mshr_request_T_57; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_59 = _mshr_request_T_56 & _mshr_request_T_58; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_60 = ~_mshrs_2_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_61 = _sourceE_io_req_ready | _mshr_request_T_60; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_62 = _mshr_request_T_59 & _mshr_request_T_61; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_63 = ~_mshrs_2_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_64 = _sourceX_io_req_ready | _mshr_request_T_63; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_65 = _mshr_request_T_62 & _mshr_request_T_64; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_66 = ~_mshrs_2_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_67 = _directory_io_write_ready | _mshr_request_T_66; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_68 = _mshr_request_T_65 & _mshr_request_T_67; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_69 = ~mshr_stall_abc_3; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_70 = _mshrs_3_io_schedule_valid & _mshr_request_T_69; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_71 = ~_mshrs_3_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_72 = _sourceA_io_req_ready | _mshr_request_T_71; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_73 = _mshr_request_T_70 & _mshr_request_T_72; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_74 = ~_mshrs_3_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_75 = _sourceB_io_req_ready | _mshr_request_T_74; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_76 = _mshr_request_T_73 & _mshr_request_T_75; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_77 = ~_mshrs_3_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_78 = _sourceC_io_req_ready | _mshr_request_T_77; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_79 = _mshr_request_T_76 & _mshr_request_T_78; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_80 = ~_mshrs_3_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_81 = _sourceD_io_req_ready | _mshr_request_T_80; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_82 = _mshr_request_T_79 & _mshr_request_T_81; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_83 = ~_mshrs_3_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_84 = _sourceE_io_req_ready | _mshr_request_T_83; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_85 = _mshr_request_T_82 & _mshr_request_T_84; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_86 = ~_mshrs_3_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_87 = _sourceX_io_req_ready | _mshr_request_T_86; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_88 = _mshr_request_T_85 & _mshr_request_T_87; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_89 = ~_mshrs_3_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_90 = _directory_io_write_ready | _mshr_request_T_89; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_91 = _mshr_request_T_88 & _mshr_request_T_90; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_92 = ~mshr_stall_abc_4; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_93 = _mshrs_4_io_schedule_valid & _mshr_request_T_92; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_94 = ~_mshrs_4_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_95 = _sourceA_io_req_ready | _mshr_request_T_94; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_96 = _mshr_request_T_93 & _mshr_request_T_95; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_97 = ~_mshrs_4_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_98 = _sourceB_io_req_ready | _mshr_request_T_97; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_99 = _mshr_request_T_96 & _mshr_request_T_98; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_100 = ~_mshrs_4_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_101 = _sourceC_io_req_ready | _mshr_request_T_100; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_102 = _mshr_request_T_99 & _mshr_request_T_101; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_103 = ~_mshrs_4_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_104 = _sourceD_io_req_ready | _mshr_request_T_103; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_105 = _mshr_request_T_102 & _mshr_request_T_104; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_106 = ~_mshrs_4_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_107 = _sourceE_io_req_ready | _mshr_request_T_106; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_108 = _mshr_request_T_105 & _mshr_request_T_107; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_109 = ~_mshrs_4_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_110 = _sourceX_io_req_ready | _mshr_request_T_109; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_111 = _mshr_request_T_108 & _mshr_request_T_110; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_112 = ~_mshrs_4_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_113 = _directory_io_write_ready | _mshr_request_T_112; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_114 = _mshr_request_T_111 & _mshr_request_T_113; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_115 = ~mshr_stall_abc_5; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_116 = _mshrs_5_io_schedule_valid & _mshr_request_T_115; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_117 = ~_mshrs_5_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_118 = _sourceA_io_req_ready | _mshr_request_T_117; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_119 = _mshr_request_T_116 & _mshr_request_T_118; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_120 = ~_mshrs_5_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_121 = _sourceB_io_req_ready | _mshr_request_T_120; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_122 = _mshr_request_T_119 & _mshr_request_T_121; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_123 = ~_mshrs_5_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_124 = _sourceC_io_req_ready | _mshr_request_T_123; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_125 = _mshr_request_T_122 & _mshr_request_T_124; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_126 = ~_mshrs_5_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_127 = _sourceD_io_req_ready | _mshr_request_T_126; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_128 = _mshr_request_T_125 & _mshr_request_T_127; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_129 = ~_mshrs_5_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_130 = _sourceE_io_req_ready | _mshr_request_T_129; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_131 = _mshr_request_T_128 & _mshr_request_T_130; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_132 = ~_mshrs_5_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_133 = _sourceX_io_req_ready | _mshr_request_T_132; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_134 = _mshr_request_T_131 & _mshr_request_T_133; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_135 = ~_mshrs_5_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_136 = _directory_io_write_ready | _mshr_request_T_135; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_137 = _mshr_request_T_134 & _mshr_request_T_136; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_138 = ~mshr_stall_abc_6; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_139 = _mshrs_6_io_schedule_valid & _mshr_request_T_138; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_140 = ~_mshrs_6_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_141 = _sourceA_io_req_ready | _mshr_request_T_140; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_142 = _mshr_request_T_139 & _mshr_request_T_141; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_143 = ~_mshrs_6_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_144 = _sourceB_io_req_ready | _mshr_request_T_143; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_145 = _mshr_request_T_142 & _mshr_request_T_144; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_146 = ~_mshrs_6_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_147 = _sourceC_io_req_ready | _mshr_request_T_146; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_148 = _mshr_request_T_145 & _mshr_request_T_147; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_149 = ~_mshrs_6_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_150 = _sourceD_io_req_ready | _mshr_request_T_149; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_151 = _mshr_request_T_148 & _mshr_request_T_150; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_152 = ~_mshrs_6_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_153 = _sourceE_io_req_ready | _mshr_request_T_152; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_154 = _mshr_request_T_151 & _mshr_request_T_153; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_155 = ~_mshrs_6_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_156 = _sourceX_io_req_ready | _mshr_request_T_155; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_157 = _mshr_request_T_154 & _mshr_request_T_156; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_158 = ~_mshrs_6_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_159 = _directory_io_write_ready | _mshr_request_T_158; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_160 = _mshr_request_T_157 & _mshr_request_T_159; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_161 = ~mshr_stall_abc_7; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_162 = _mshrs_7_io_schedule_valid & _mshr_request_T_161; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_163 = ~_mshrs_7_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_164 = _sourceA_io_req_ready | _mshr_request_T_163; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_165 = _mshr_request_T_162 & _mshr_request_T_164; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_166 = ~_mshrs_7_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_167 = _sourceB_io_req_ready | _mshr_request_T_166; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_168 = _mshr_request_T_165 & _mshr_request_T_167; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_169 = ~_mshrs_7_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_170 = _sourceC_io_req_ready | _mshr_request_T_169; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_171 = _mshr_request_T_168 & _mshr_request_T_170; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_172 = ~_mshrs_7_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_173 = _sourceD_io_req_ready | _mshr_request_T_172; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_174 = _mshr_request_T_171 & _mshr_request_T_173; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_175 = ~_mshrs_7_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_176 = _sourceE_io_req_ready | _mshr_request_T_175; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_177 = _mshr_request_T_174 & _mshr_request_T_176; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_178 = ~_mshrs_7_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_179 = _sourceX_io_req_ready | _mshr_request_T_178; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_180 = _mshr_request_T_177 & _mshr_request_T_179; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_181 = ~_mshrs_7_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_182 = _directory_io_write_ready | _mshr_request_T_181; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_183 = _mshr_request_T_180 & _mshr_request_T_182; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_184 = ~mshr_stall_abc_8; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_185 = _mshrs_8_io_schedule_valid & _mshr_request_T_184; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_186 = ~_mshrs_8_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_187 = _sourceA_io_req_ready | _mshr_request_T_186; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_188 = _mshr_request_T_185 & _mshr_request_T_187; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_189 = ~_mshrs_8_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_190 = _sourceB_io_req_ready | _mshr_request_T_189; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_191 = _mshr_request_T_188 & _mshr_request_T_190; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_192 = ~_mshrs_8_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_193 = _sourceC_io_req_ready | _mshr_request_T_192; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_194 = _mshr_request_T_191 & _mshr_request_T_193; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_195 = ~_mshrs_8_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_196 = _sourceD_io_req_ready | _mshr_request_T_195; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_197 = _mshr_request_T_194 & _mshr_request_T_196; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_198 = ~_mshrs_8_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_199 = _sourceE_io_req_ready | _mshr_request_T_198; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_200 = _mshr_request_T_197 & _mshr_request_T_199; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_201 = ~_mshrs_8_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_202 = _sourceX_io_req_ready | _mshr_request_T_201; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_203 = _mshr_request_T_200 & _mshr_request_T_202; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_204 = ~_mshrs_8_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_205 = _directory_io_write_ready | _mshr_request_T_204; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_206 = _mshr_request_T_203 & _mshr_request_T_205; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_207 = ~mshr_stall_abc_9; // @[Scheduler.scala:90:86, :107:28] wire _mshr_request_T_208 = _mshrs_9_io_schedule_valid & _mshr_request_T_207; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_209 = ~_mshrs_9_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_210 = _sourceA_io_req_ready | _mshr_request_T_209; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_211 = _mshr_request_T_208 & _mshr_request_T_210; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_212 = ~_mshrs_9_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_213 = _sourceB_io_req_ready | _mshr_request_T_212; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_214 = _mshr_request_T_211 & _mshr_request_T_213; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_215 = ~_mshrs_9_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_216 = _sourceC_io_req_ready | _mshr_request_T_215; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_217 = _mshr_request_T_214 & _mshr_request_T_216; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_218 = ~_mshrs_9_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_219 = _sourceD_io_req_ready | _mshr_request_T_218; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_220 = _mshr_request_T_217 & _mshr_request_T_219; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_221 = ~_mshrs_9_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_222 = _sourceE_io_req_ready | _mshr_request_T_221; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_223 = _mshr_request_T_220 & _mshr_request_T_222; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_224 = ~_mshrs_9_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_225 = _sourceX_io_req_ready | _mshr_request_T_224; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_226 = _mshr_request_T_223 & _mshr_request_T_225; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_227 = ~_mshrs_9_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_228 = _directory_io_write_ready | _mshr_request_T_227; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_229 = _mshr_request_T_226 & _mshr_request_T_228; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_230 = ~mshr_stall_bc; // @[Scheduler.scala:94:28, :107:28] wire _mshr_request_T_231 = _mshrs_10_io_schedule_valid & _mshr_request_T_230; // @[Scheduler.scala:71:46, :107:{25,28}] wire _mshr_request_T_232 = ~_mshrs_10_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_233 = _sourceA_io_req_ready | _mshr_request_T_232; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_234 = _mshr_request_T_231 & _mshr_request_T_233; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_235 = ~_mshrs_10_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_236 = _sourceB_io_req_ready | _mshr_request_T_235; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_237 = _mshr_request_T_234 & _mshr_request_T_236; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_238 = ~_mshrs_10_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_239 = _sourceC_io_req_ready | _mshr_request_T_238; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_240 = _mshr_request_T_237 & _mshr_request_T_239; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_241 = ~_mshrs_10_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_242 = _sourceD_io_req_ready | _mshr_request_T_241; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_243 = _mshr_request_T_240 & _mshr_request_T_242; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_244 = ~_mshrs_10_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_245 = _sourceE_io_req_ready | _mshr_request_T_244; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_246 = _mshr_request_T_243 & _mshr_request_T_245; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_247 = ~_mshrs_10_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_248 = _sourceX_io_req_ready | _mshr_request_T_247; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_249 = _mshr_request_T_246 & _mshr_request_T_248; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_250 = ~_mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_251 = _directory_io_write_ready | _mshr_request_T_250; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_252 = _mshr_request_T_249 & _mshr_request_T_251; // @[Scheduler.scala:112:61, :113:61, :114:33] wire _mshr_request_T_255 = ~_mshrs_11_io_schedule_bits_a_valid; // @[Scheduler.scala:71:46, :108:32] wire _mshr_request_T_256 = _sourceA_io_req_ready | _mshr_request_T_255; // @[Scheduler.scala:40:23, :108:{29,32}] wire _mshr_request_T_254; // @[Scheduler.scala:107:25] wire _mshr_request_T_257 = _mshr_request_T_254 & _mshr_request_T_256; // @[Scheduler.scala:107:{25,31}, :108:29] wire _mshr_request_T_258 = ~_mshrs_11_io_schedule_bits_b_valid; // @[Scheduler.scala:71:46, :109:32] wire _mshr_request_T_259 = _sourceB_io_req_ready | _mshr_request_T_258; // @[Scheduler.scala:41:23, :109:{29,32}] wire _mshr_request_T_260 = _mshr_request_T_257 & _mshr_request_T_259; // @[Scheduler.scala:107:31, :108:61, :109:29] wire _mshr_request_T_261 = ~_mshrs_11_io_schedule_bits_c_valid; // @[Scheduler.scala:71:46, :110:32] wire _mshr_request_T_262 = _sourceC_io_req_ready | _mshr_request_T_261; // @[Scheduler.scala:42:23, :110:{29,32}] wire _mshr_request_T_263 = _mshr_request_T_260 & _mshr_request_T_262; // @[Scheduler.scala:108:61, :109:61, :110:29] wire _mshr_request_T_264 = ~_mshrs_11_io_schedule_bits_d_valid; // @[Scheduler.scala:71:46, :111:32] wire _mshr_request_T_265 = _sourceD_io_req_ready | _mshr_request_T_264; // @[Scheduler.scala:43:23, :111:{29,32}] wire _mshr_request_T_266 = _mshr_request_T_263 & _mshr_request_T_265; // @[Scheduler.scala:109:61, :110:61, :111:29] wire _mshr_request_T_267 = ~_mshrs_11_io_schedule_bits_e_valid; // @[Scheduler.scala:71:46, :112:32] wire _mshr_request_T_268 = _sourceE_io_req_ready | _mshr_request_T_267; // @[Scheduler.scala:44:23, :112:{29,32}] wire _mshr_request_T_269 = _mshr_request_T_266 & _mshr_request_T_268; // @[Scheduler.scala:110:61, :111:61, :112:29] wire _mshr_request_T_270 = ~_mshrs_11_io_schedule_bits_x_valid; // @[Scheduler.scala:71:46, :113:32] wire _mshr_request_T_271 = _sourceX_io_req_ready | _mshr_request_T_270; // @[Scheduler.scala:45:23, :113:{29,32}] wire _mshr_request_T_272 = _mshr_request_T_269 & _mshr_request_T_271; // @[Scheduler.scala:111:61, :112:61, :113:29] wire _mshr_request_T_273 = ~_mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :114:36] wire _mshr_request_T_274 = _directory_io_write_ready | _mshr_request_T_273; // @[Scheduler.scala:68:25, :114:{33,36}] wire _mshr_request_T_275 = _mshr_request_T_272 & _mshr_request_T_274; // @[Scheduler.scala:112:61, :113:61, :114:33] wire [1:0] mshr_request_lo_lo_hi = {_mshr_request_T_68, _mshr_request_T_45}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_lo_lo = {mshr_request_lo_lo_hi, _mshr_request_T_22}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_lo_hi_hi = {_mshr_request_T_137, _mshr_request_T_114}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_lo_hi = {mshr_request_lo_hi_hi, _mshr_request_T_91}; // @[Scheduler.scala:106:25, :113:61] wire [5:0] mshr_request_lo = {mshr_request_lo_hi, mshr_request_lo_lo}; // @[Scheduler.scala:106:25] wire [1:0] mshr_request_hi_lo_hi = {_mshr_request_T_206, _mshr_request_T_183}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_hi_lo = {mshr_request_hi_lo_hi, _mshr_request_T_160}; // @[Scheduler.scala:106:25, :113:61] wire [1:0] mshr_request_hi_hi_hi = {_mshr_request_T_275, _mshr_request_T_252}; // @[Scheduler.scala:106:25, :113:61] wire [2:0] mshr_request_hi_hi = {mshr_request_hi_hi_hi, _mshr_request_T_229}; // @[Scheduler.scala:106:25, :113:61] wire [5:0] mshr_request_hi = {mshr_request_hi_hi, mshr_request_hi_lo}; // @[Scheduler.scala:106:25] wire [11:0] mshr_request = {mshr_request_hi, mshr_request_lo}; // @[Scheduler.scala:106:25] reg [11:0] robin_filter; // @[Scheduler.scala:118:29] wire [11:0] _robin_request_T = mshr_request & robin_filter; // @[Scheduler.scala:106:25, :118:29, :119:54] wire [23:0] robin_request = {mshr_request, _robin_request_T}; // @[Scheduler.scala:106:25, :119:{26,54}] wire [24:0] _mshr_selectOH2_T = {robin_request, 1'h0}; // @[package.scala:253:48] wire [23:0] _mshr_selectOH2_T_1 = _mshr_selectOH2_T[23:0]; // @[package.scala:253:{48,53}] wire [23:0] _mshr_selectOH2_T_2 = robin_request | _mshr_selectOH2_T_1; // @[package.scala:253:{43,53}] wire [25:0] _mshr_selectOH2_T_3 = {_mshr_selectOH2_T_2, 2'h0}; // @[package.scala:253:{43,48}] wire [23:0] _mshr_selectOH2_T_4 = _mshr_selectOH2_T_3[23:0]; // @[package.scala:253:{48,53}] wire [23:0] _mshr_selectOH2_T_5 = _mshr_selectOH2_T_2 | _mshr_selectOH2_T_4; // @[package.scala:253:{43,53}] wire [27:0] _mshr_selectOH2_T_6 = {_mshr_selectOH2_T_5, 4'h0}; // @[package.scala:253:{43,48}] wire [23:0] _mshr_selectOH2_T_7 = _mshr_selectOH2_T_6[23:0]; // @[package.scala:253:{48,53}] wire [23:0] _mshr_selectOH2_T_8 = _mshr_selectOH2_T_5 | _mshr_selectOH2_T_7; // @[package.scala:253:{43,53}] wire [31:0] _mshr_selectOH2_T_9 = {_mshr_selectOH2_T_8, 8'h0}; // @[package.scala:253:{43,48}] wire [23:0] _mshr_selectOH2_T_10 = _mshr_selectOH2_T_9[23:0]; // @[package.scala:253:{48,53}] wire [23:0] _mshr_selectOH2_T_11 = _mshr_selectOH2_T_8 | _mshr_selectOH2_T_10; // @[package.scala:253:{43,53}] wire [39:0] _mshr_selectOH2_T_12 = {_mshr_selectOH2_T_11, 16'h0}; // @[package.scala:253:{43,48}] wire [23:0] _mshr_selectOH2_T_13 = _mshr_selectOH2_T_12[23:0]; // @[package.scala:253:{48,53}] wire [23:0] _mshr_selectOH2_T_14 = _mshr_selectOH2_T_11 | _mshr_selectOH2_T_13; // @[package.scala:253:{43,53}] wire [23:0] _mshr_selectOH2_T_15 = _mshr_selectOH2_T_14; // @[package.scala:253:43, :254:17] wire [24:0] _mshr_selectOH2_T_16 = {_mshr_selectOH2_T_15, 1'h0}; // @[package.scala:254:17] wire [24:0] _mshr_selectOH2_T_17 = ~_mshr_selectOH2_T_16; // @[Scheduler.scala:120:{24,48}] wire [24:0] mshr_selectOH2 = {1'h0, _mshr_selectOH2_T_17[23:0] & robin_request}; // @[Scheduler.scala:119:26, :120:{24,54}] wire [11:0] _mshr_selectOH_T = mshr_selectOH2[23:12]; // @[Scheduler.scala:120:54, :121:37] wire [11:0] _mshr_selectOH_T_1 = mshr_selectOH2[11:0]; // @[Scheduler.scala:120:54, :121:86] wire [11:0] mshr_selectOH = _mshr_selectOH_T | _mshr_selectOH_T_1; // @[Scheduler.scala:121:{37,70,86}] wire [3:0] mshr_select_hi = mshr_selectOH[11:8]; // @[OneHot.scala:30:18] wire [7:0] mshr_select_lo = mshr_selectOH[7:0]; // @[OneHot.scala:31:18] wire _mshr_select_T = |mshr_select_hi; // @[OneHot.scala:30:18, :32:14] wire [7:0] _mshr_select_T_1 = {4'h0, mshr_select_hi} | mshr_select_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] mshr_select_hi_1 = _mshr_select_T_1[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] mshr_select_lo_1 = _mshr_select_T_1[3:0]; // @[OneHot.scala:31:18, :32:28] wire _mshr_select_T_2 = |mshr_select_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _mshr_select_T_3 = mshr_select_hi_1 | mshr_select_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] mshr_select_hi_2 = _mshr_select_T_3[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] mshr_select_lo_2 = _mshr_select_T_3[1:0]; // @[OneHot.scala:31:18, :32:28] wire _mshr_select_T_4 = |mshr_select_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _mshr_select_T_5 = mshr_select_hi_2 | mshr_select_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _mshr_select_T_6 = _mshr_select_T_5[1]; // @[OneHot.scala:32:28] wire [1:0] _mshr_select_T_7 = {_mshr_select_T_4, _mshr_select_T_6}; // @[OneHot.scala:32:{10,14}] wire [2:0] _mshr_select_T_8 = {_mshr_select_T_2, _mshr_select_T_7}; // @[OneHot.scala:32:{10,14}] wire [3:0] mshr_select = {_mshr_select_T, _mshr_select_T_8}; // @[OneHot.scala:32:{10,14}] wire [3:0] schedule_a_bits_source = mshr_select; // @[OneHot.scala:32:10] wire [3:0] schedule_d_bits_sink = mshr_select; // @[OneHot.scala:32:10] wire _schedule_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleTag_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _scheduleSet_T = mshr_selectOH[0]; // @[Mux.scala:32:36] wire sel = mshr_selectOH[0]; // @[Mux.scala:32:36] wire _schedule_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleTag_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _scheduleSet_T_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire sel_1 = mshr_selectOH[1]; // @[Mux.scala:32:36] wire _schedule_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleTag_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _scheduleSet_T_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire sel_2 = mshr_selectOH[2]; // @[Mux.scala:32:36] wire _schedule_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleTag_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _scheduleSet_T_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire sel_3 = mshr_selectOH[3]; // @[Mux.scala:32:36] wire _schedule_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleTag_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _scheduleSet_T_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire sel_4 = mshr_selectOH[4]; // @[Mux.scala:32:36] wire _schedule_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleTag_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _scheduleSet_T_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire sel_5 = mshr_selectOH[5]; // @[Mux.scala:32:36] wire _schedule_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleTag_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _scheduleSet_T_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire sel_6 = mshr_selectOH[6]; // @[Mux.scala:32:36] wire _schedule_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36] wire _scheduleTag_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36] wire _scheduleSet_T_7 = mshr_selectOH[7]; // @[Mux.scala:32:36] wire sel_7 = mshr_selectOH[7]; // @[Mux.scala:32:36] wire _schedule_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36] wire _scheduleTag_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36] wire _scheduleSet_T_8 = mshr_selectOH[8]; // @[Mux.scala:32:36] wire sel_8 = mshr_selectOH[8]; // @[Mux.scala:32:36] wire _schedule_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36] wire _scheduleTag_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36] wire _scheduleSet_T_9 = mshr_selectOH[9]; // @[Mux.scala:32:36] wire sel_9 = mshr_selectOH[9]; // @[Mux.scala:32:36] wire _schedule_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36] wire _scheduleTag_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36] wire _scheduleSet_T_10 = mshr_selectOH[10]; // @[Mux.scala:32:36] wire select_bc = mshr_selectOH[10]; // @[Mux.scala:32:36] wire sel_10 = mshr_selectOH[10]; // @[Mux.scala:32:36] wire _schedule_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36] wire _scheduleTag_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36] wire _scheduleSet_T_11 = mshr_selectOH[11]; // @[Mux.scala:32:36] wire select_c = mshr_selectOH[11]; // @[Mux.scala:32:36] wire sel_11 = mshr_selectOH[11]; // @[Mux.scala:32:36] wire _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [3:0] _schedule_c_bits_source_T_1; // @[Scheduler.scala:132:32] wire [8:0] _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE; // @[Mux.scala:30:73] wire [8:0] schedule_a_bits_tag; // @[Mux.scala:30:73] wire [10:0] schedule_a_bits_set; // @[Mux.scala:30:73] wire [2:0] schedule_a_bits_param; // @[Mux.scala:30:73] wire schedule_a_bits_block; // @[Mux.scala:30:73] wire schedule_a_valid; // @[Mux.scala:30:73] wire [2:0] schedule_b_bits_param; // @[Mux.scala:30:73] wire [8:0] schedule_b_bits_tag; // @[Mux.scala:30:73] wire [10:0] schedule_b_bits_set; // @[Mux.scala:30:73] wire schedule_b_bits_clients; // @[Mux.scala:30:73] wire schedule_b_valid; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_c_bits_param; // @[Mux.scala:30:73] wire [3:0] schedule_c_bits_source; // @[Mux.scala:30:73] wire [8:0] schedule_c_bits_tag; // @[Mux.scala:30:73] wire [10:0] schedule_c_bits_set; // @[Mux.scala:30:73] wire [3:0] schedule_c_bits_way; // @[Mux.scala:30:73] wire schedule_c_bits_dirty; // @[Mux.scala:30:73] wire schedule_c_valid; // @[Mux.scala:30:73] wire schedule_d_bits_prio_0; // @[Mux.scala:30:73] wire schedule_d_bits_prio_1; // @[Mux.scala:30:73] wire schedule_d_bits_prio_2; // @[Mux.scala:30:73] wire schedule_d_bits_control; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_opcode; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_param; // @[Mux.scala:30:73] wire [2:0] schedule_d_bits_size; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_source; // @[Mux.scala:30:73] wire [8:0] schedule_d_bits_tag; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_offset; // @[Mux.scala:30:73] wire [5:0] schedule_d_bits_put; // @[Mux.scala:30:73] wire [10:0] schedule_d_bits_set; // @[Mux.scala:30:73] wire [3:0] schedule_d_bits_way; // @[Mux.scala:30:73] wire schedule_d_bits_bad; // @[Mux.scala:30:73] wire schedule_d_valid; // @[Mux.scala:30:73] wire [2:0] schedule_e_bits_sink; // @[Mux.scala:30:73] wire schedule_e_valid; // @[Mux.scala:30:73] wire schedule_x_valid; // @[Mux.scala:30:73] wire schedule_dir_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] schedule_dir_bits_data_state; // @[Mux.scala:30:73] wire schedule_dir_bits_data_clients; // @[Mux.scala:30:73] wire [8:0] schedule_dir_bits_data_tag; // @[Mux.scala:30:73] wire [10:0] schedule_dir_bits_set; // @[Mux.scala:30:73] wire [3:0] schedule_dir_bits_way; // @[Mux.scala:30:73] wire schedule_dir_valid; // @[Mux.scala:30:73] wire schedule_reload; // @[Mux.scala:30:73] wire _schedule_T_12 = _schedule_T & _mshrs_0_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_13 = _schedule_T_1 & _mshrs_1_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_14 = _schedule_T_2 & _mshrs_2_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_15 = _schedule_T_3 & _mshrs_3_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_16 = _schedule_T_4 & _mshrs_4_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_17 = _schedule_T_5 & _mshrs_5_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_18 = _schedule_T_6 & _mshrs_6_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_19 = _schedule_T_7 & _mshrs_7_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_20 = _schedule_T_8 & _mshrs_8_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_21 = _schedule_T_9 & _mshrs_9_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_22 = _schedule_T_10 & _mshrs_10_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_23 = _schedule_T_11 & _mshrs_11_io_schedule_bits_reload; // @[Mux.scala:30:73, :32:36] wire _schedule_T_24 = _schedule_T_12 | _schedule_T_13; // @[Mux.scala:30:73] wire _schedule_T_25 = _schedule_T_24 | _schedule_T_14; // @[Mux.scala:30:73] wire _schedule_T_26 = _schedule_T_25 | _schedule_T_15; // @[Mux.scala:30:73] wire _schedule_T_27 = _schedule_T_26 | _schedule_T_16; // @[Mux.scala:30:73] wire _schedule_T_28 = _schedule_T_27 | _schedule_T_17; // @[Mux.scala:30:73] wire _schedule_T_29 = _schedule_T_28 | _schedule_T_18; // @[Mux.scala:30:73] wire _schedule_T_30 = _schedule_T_29 | _schedule_T_19; // @[Mux.scala:30:73] wire _schedule_T_31 = _schedule_T_30 | _schedule_T_20; // @[Mux.scala:30:73] wire _schedule_T_32 = _schedule_T_31 | _schedule_T_21; // @[Mux.scala:30:73] wire _schedule_T_33 = _schedule_T_32 | _schedule_T_22; // @[Mux.scala:30:73] wire _schedule_T_34 = _schedule_T_33 | _schedule_T_23; // @[Mux.scala:30:73] assign _schedule_WIRE = _schedule_T_34; // @[Mux.scala:30:73] assign schedule_reload = _schedule_WIRE; // @[Mux.scala:30:73] wire _schedule_WIRE_10; // @[Mux.scala:30:73] assign schedule_dir_valid = _schedule_WIRE_1_valid; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_2_set; // @[Mux.scala:30:73] assign schedule_dir_bits_set = _schedule_WIRE_1_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_2_way; // @[Mux.scala:30:73] assign schedule_dir_bits_way = _schedule_WIRE_1_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] assign schedule_dir_bits_data_dirty = _schedule_WIRE_1_bits_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] assign schedule_dir_bits_data_state = _schedule_WIRE_1_bits_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] assign schedule_dir_bits_data_clients = _schedule_WIRE_1_bits_data_clients; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] assign schedule_dir_bits_data_tag = _schedule_WIRE_1_bits_data_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_9; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_set = _schedule_WIRE_2_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_8; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_way = _schedule_WIRE_2_way; // @[Mux.scala:30:73] wire _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_dirty = _schedule_WIRE_2_data_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_3_state; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_state = _schedule_WIRE_2_data_state; // @[Mux.scala:30:73] wire _schedule_WIRE_3_clients; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_clients = _schedule_WIRE_2_data_clients; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_3_tag; // @[Mux.scala:30:73] assign _schedule_WIRE_1_bits_data_tag = _schedule_WIRE_2_data_tag; // @[Mux.scala:30:73] wire _schedule_WIRE_7; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_dirty = _schedule_WIRE_3_dirty; // @[Mux.scala:30:73] wire [1:0] _schedule_WIRE_6; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_state = _schedule_WIRE_3_state; // @[Mux.scala:30:73] wire _schedule_WIRE_5; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_clients = _schedule_WIRE_3_clients; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_4; // @[Mux.scala:30:73] assign _schedule_WIRE_2_data_tag = _schedule_WIRE_3_tag; // @[Mux.scala:30:73] wire [8:0] _schedule_T_35 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_36 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_37 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_38 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_39 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_40 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_41 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_42 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_43 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_44 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_45 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_46 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_47 = _schedule_T_35 | _schedule_T_36; // @[Mux.scala:30:73] wire [8:0] _schedule_T_48 = _schedule_T_47 | _schedule_T_37; // @[Mux.scala:30:73] wire [8:0] _schedule_T_49 = _schedule_T_48 | _schedule_T_38; // @[Mux.scala:30:73] wire [8:0] _schedule_T_50 = _schedule_T_49 | _schedule_T_39; // @[Mux.scala:30:73] wire [8:0] _schedule_T_51 = _schedule_T_50 | _schedule_T_40; // @[Mux.scala:30:73] wire [8:0] _schedule_T_52 = _schedule_T_51 | _schedule_T_41; // @[Mux.scala:30:73] wire [8:0] _schedule_T_53 = _schedule_T_52 | _schedule_T_42; // @[Mux.scala:30:73] wire [8:0] _schedule_T_54 = _schedule_T_53 | _schedule_T_43; // @[Mux.scala:30:73] wire [8:0] _schedule_T_55 = _schedule_T_54 | _schedule_T_44; // @[Mux.scala:30:73] wire [8:0] _schedule_T_56 = _schedule_T_55 | _schedule_T_45; // @[Mux.scala:30:73] wire [8:0] _schedule_T_57 = _schedule_T_56 | _schedule_T_46; // @[Mux.scala:30:73] assign _schedule_WIRE_4 = _schedule_T_57; // @[Mux.scala:30:73] assign _schedule_WIRE_3_tag = _schedule_WIRE_4; // @[Mux.scala:30:73] wire _schedule_T_58 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_59 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_60 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_61 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_62 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_63 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_64 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_65 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_66 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_67 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_68 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_69 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_70 = _schedule_T_58 | _schedule_T_59; // @[Mux.scala:30:73] wire _schedule_T_71 = _schedule_T_70 | _schedule_T_60; // @[Mux.scala:30:73] wire _schedule_T_72 = _schedule_T_71 | _schedule_T_61; // @[Mux.scala:30:73] wire _schedule_T_73 = _schedule_T_72 | _schedule_T_62; // @[Mux.scala:30:73] wire _schedule_T_74 = _schedule_T_73 | _schedule_T_63; // @[Mux.scala:30:73] wire _schedule_T_75 = _schedule_T_74 | _schedule_T_64; // @[Mux.scala:30:73] wire _schedule_T_76 = _schedule_T_75 | _schedule_T_65; // @[Mux.scala:30:73] wire _schedule_T_77 = _schedule_T_76 | _schedule_T_66; // @[Mux.scala:30:73] wire _schedule_T_78 = _schedule_T_77 | _schedule_T_67; // @[Mux.scala:30:73] wire _schedule_T_79 = _schedule_T_78 | _schedule_T_68; // @[Mux.scala:30:73] wire _schedule_T_80 = _schedule_T_79 | _schedule_T_69; // @[Mux.scala:30:73] assign _schedule_WIRE_5 = _schedule_T_80; // @[Mux.scala:30:73] assign _schedule_WIRE_3_clients = _schedule_WIRE_5; // @[Mux.scala:30:73] wire [1:0] _schedule_T_81 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_82 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_83 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_84 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_85 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_86 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_87 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_88 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_89 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_90 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_91 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_92 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_data_state : 2'h0; // @[Mux.scala:30:73, :32:36] wire [1:0] _schedule_T_93 = _schedule_T_81 | _schedule_T_82; // @[Mux.scala:30:73] wire [1:0] _schedule_T_94 = _schedule_T_93 | _schedule_T_83; // @[Mux.scala:30:73] wire [1:0] _schedule_T_95 = _schedule_T_94 | _schedule_T_84; // @[Mux.scala:30:73] wire [1:0] _schedule_T_96 = _schedule_T_95 | _schedule_T_85; // @[Mux.scala:30:73] wire [1:0] _schedule_T_97 = _schedule_T_96 | _schedule_T_86; // @[Mux.scala:30:73] wire [1:0] _schedule_T_98 = _schedule_T_97 | _schedule_T_87; // @[Mux.scala:30:73] wire [1:0] _schedule_T_99 = _schedule_T_98 | _schedule_T_88; // @[Mux.scala:30:73] wire [1:0] _schedule_T_100 = _schedule_T_99 | _schedule_T_89; // @[Mux.scala:30:73] wire [1:0] _schedule_T_101 = _schedule_T_100 | _schedule_T_90; // @[Mux.scala:30:73] wire [1:0] _schedule_T_102 = _schedule_T_101 | _schedule_T_91; // @[Mux.scala:30:73] wire [1:0] _schedule_T_103 = _schedule_T_102 | _schedule_T_92; // @[Mux.scala:30:73] assign _schedule_WIRE_6 = _schedule_T_103; // @[Mux.scala:30:73] assign _schedule_WIRE_3_state = _schedule_WIRE_6; // @[Mux.scala:30:73] wire _schedule_T_104 = _schedule_T & _mshrs_0_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_105 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_106 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_107 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_108 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_109 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_110 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_111 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_112 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_113 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_114 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_115 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_116 = _schedule_T_104 | _schedule_T_105; // @[Mux.scala:30:73] wire _schedule_T_117 = _schedule_T_116 | _schedule_T_106; // @[Mux.scala:30:73] wire _schedule_T_118 = _schedule_T_117 | _schedule_T_107; // @[Mux.scala:30:73] wire _schedule_T_119 = _schedule_T_118 | _schedule_T_108; // @[Mux.scala:30:73] wire _schedule_T_120 = _schedule_T_119 | _schedule_T_109; // @[Mux.scala:30:73] wire _schedule_T_121 = _schedule_T_120 | _schedule_T_110; // @[Mux.scala:30:73] wire _schedule_T_122 = _schedule_T_121 | _schedule_T_111; // @[Mux.scala:30:73] wire _schedule_T_123 = _schedule_T_122 | _schedule_T_112; // @[Mux.scala:30:73] wire _schedule_T_124 = _schedule_T_123 | _schedule_T_113; // @[Mux.scala:30:73] wire _schedule_T_125 = _schedule_T_124 | _schedule_T_114; // @[Mux.scala:30:73] wire _schedule_T_126 = _schedule_T_125 | _schedule_T_115; // @[Mux.scala:30:73] assign _schedule_WIRE_7 = _schedule_T_126; // @[Mux.scala:30:73] assign _schedule_WIRE_3_dirty = _schedule_WIRE_7; // @[Mux.scala:30:73] wire [3:0] _schedule_T_127 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_128 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_129 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_130 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_131 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_132 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_133 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_134 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_135 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_136 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_137 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_138 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_139 = _schedule_T_127 | _schedule_T_128; // @[Mux.scala:30:73] wire [3:0] _schedule_T_140 = _schedule_T_139 | _schedule_T_129; // @[Mux.scala:30:73] wire [3:0] _schedule_T_141 = _schedule_T_140 | _schedule_T_130; // @[Mux.scala:30:73] wire [3:0] _schedule_T_142 = _schedule_T_141 | _schedule_T_131; // @[Mux.scala:30:73] wire [3:0] _schedule_T_143 = _schedule_T_142 | _schedule_T_132; // @[Mux.scala:30:73] wire [3:0] _schedule_T_144 = _schedule_T_143 | _schedule_T_133; // @[Mux.scala:30:73] wire [3:0] _schedule_T_145 = _schedule_T_144 | _schedule_T_134; // @[Mux.scala:30:73] wire [3:0] _schedule_T_146 = _schedule_T_145 | _schedule_T_135; // @[Mux.scala:30:73] wire [3:0] _schedule_T_147 = _schedule_T_146 | _schedule_T_136; // @[Mux.scala:30:73] wire [3:0] _schedule_T_148 = _schedule_T_147 | _schedule_T_137; // @[Mux.scala:30:73] wire [3:0] _schedule_T_149 = _schedule_T_148 | _schedule_T_138; // @[Mux.scala:30:73] assign _schedule_WIRE_8 = _schedule_T_149; // @[Mux.scala:30:73] assign _schedule_WIRE_2_way = _schedule_WIRE_8; // @[Mux.scala:30:73] wire [10:0] _schedule_T_150 = _schedule_T ? _mshrs_0_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_151 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_152 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_153 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_154 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_155 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_156 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_157 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_158 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_159 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_160 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_161 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_dir_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_162 = _schedule_T_150 | _schedule_T_151; // @[Mux.scala:30:73] wire [10:0] _schedule_T_163 = _schedule_T_162 | _schedule_T_152; // @[Mux.scala:30:73] wire [10:0] _schedule_T_164 = _schedule_T_163 | _schedule_T_153; // @[Mux.scala:30:73] wire [10:0] _schedule_T_165 = _schedule_T_164 | _schedule_T_154; // @[Mux.scala:30:73] wire [10:0] _schedule_T_166 = _schedule_T_165 | _schedule_T_155; // @[Mux.scala:30:73] wire [10:0] _schedule_T_167 = _schedule_T_166 | _schedule_T_156; // @[Mux.scala:30:73] wire [10:0] _schedule_T_168 = _schedule_T_167 | _schedule_T_157; // @[Mux.scala:30:73] wire [10:0] _schedule_T_169 = _schedule_T_168 | _schedule_T_158; // @[Mux.scala:30:73] wire [10:0] _schedule_T_170 = _schedule_T_169 | _schedule_T_159; // @[Mux.scala:30:73] wire [10:0] _schedule_T_171 = _schedule_T_170 | _schedule_T_160; // @[Mux.scala:30:73] wire [10:0] _schedule_T_172 = _schedule_T_171 | _schedule_T_161; // @[Mux.scala:30:73] assign _schedule_WIRE_9 = _schedule_T_172; // @[Mux.scala:30:73] assign _schedule_WIRE_2_set = _schedule_WIRE_9; // @[Mux.scala:30:73] wire _schedule_T_173 = _schedule_T & _mshrs_0_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_174 = _schedule_T_1 & _mshrs_1_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_175 = _schedule_T_2 & _mshrs_2_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_176 = _schedule_T_3 & _mshrs_3_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_177 = _schedule_T_4 & _mshrs_4_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_178 = _schedule_T_5 & _mshrs_5_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_179 = _schedule_T_6 & _mshrs_6_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_180 = _schedule_T_7 & _mshrs_7_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_181 = _schedule_T_8 & _mshrs_8_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_182 = _schedule_T_9 & _mshrs_9_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_183 = _schedule_T_10 & _mshrs_10_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_184 = _schedule_T_11 & _mshrs_11_io_schedule_bits_dir_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_185 = _schedule_T_173 | _schedule_T_174; // @[Mux.scala:30:73] wire _schedule_T_186 = _schedule_T_185 | _schedule_T_175; // @[Mux.scala:30:73] wire _schedule_T_187 = _schedule_T_186 | _schedule_T_176; // @[Mux.scala:30:73] wire _schedule_T_188 = _schedule_T_187 | _schedule_T_177; // @[Mux.scala:30:73] wire _schedule_T_189 = _schedule_T_188 | _schedule_T_178; // @[Mux.scala:30:73] wire _schedule_T_190 = _schedule_T_189 | _schedule_T_179; // @[Mux.scala:30:73] wire _schedule_T_191 = _schedule_T_190 | _schedule_T_180; // @[Mux.scala:30:73] wire _schedule_T_192 = _schedule_T_191 | _schedule_T_181; // @[Mux.scala:30:73] wire _schedule_T_193 = _schedule_T_192 | _schedule_T_182; // @[Mux.scala:30:73] wire _schedule_T_194 = _schedule_T_193 | _schedule_T_183; // @[Mux.scala:30:73] wire _schedule_T_195 = _schedule_T_194 | _schedule_T_184; // @[Mux.scala:30:73] assign _schedule_WIRE_10 = _schedule_T_195; // @[Mux.scala:30:73] assign _schedule_WIRE_1_valid = _schedule_WIRE_10; // @[Mux.scala:30:73] wire _schedule_WIRE_14; // @[Mux.scala:30:73] assign schedule_x_valid = _schedule_WIRE_11_valid; // @[Mux.scala:30:73] wire _schedule_T_219 = _schedule_T & _mshrs_0_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_220 = _schedule_T_1 & _mshrs_1_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_221 = _schedule_T_2 & _mshrs_2_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_222 = _schedule_T_3 & _mshrs_3_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_223 = _schedule_T_4 & _mshrs_4_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_224 = _schedule_T_5 & _mshrs_5_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_225 = _schedule_T_6 & _mshrs_6_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_226 = _schedule_T_7 & _mshrs_7_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_227 = _schedule_T_8 & _mshrs_8_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_228 = _schedule_T_9 & _mshrs_9_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_229 = _schedule_T_10 & _mshrs_10_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_230 = _schedule_T_11 & _mshrs_11_io_schedule_bits_x_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_231 = _schedule_T_219 | _schedule_T_220; // @[Mux.scala:30:73] wire _schedule_T_232 = _schedule_T_231 | _schedule_T_221; // @[Mux.scala:30:73] wire _schedule_T_233 = _schedule_T_232 | _schedule_T_222; // @[Mux.scala:30:73] wire _schedule_T_234 = _schedule_T_233 | _schedule_T_223; // @[Mux.scala:30:73] wire _schedule_T_235 = _schedule_T_234 | _schedule_T_224; // @[Mux.scala:30:73] wire _schedule_T_236 = _schedule_T_235 | _schedule_T_225; // @[Mux.scala:30:73] wire _schedule_T_237 = _schedule_T_236 | _schedule_T_226; // @[Mux.scala:30:73] wire _schedule_T_238 = _schedule_T_237 | _schedule_T_227; // @[Mux.scala:30:73] wire _schedule_T_239 = _schedule_T_238 | _schedule_T_228; // @[Mux.scala:30:73] wire _schedule_T_240 = _schedule_T_239 | _schedule_T_229; // @[Mux.scala:30:73] wire _schedule_T_241 = _schedule_T_240 | _schedule_T_230; // @[Mux.scala:30:73] assign _schedule_WIRE_14 = _schedule_T_241; // @[Mux.scala:30:73] assign _schedule_WIRE_11_valid = _schedule_WIRE_14; // @[Mux.scala:30:73] wire _schedule_WIRE_18; // @[Mux.scala:30:73] assign schedule_e_valid = _schedule_WIRE_15_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_16_sink; // @[Mux.scala:30:73] assign schedule_e_bits_sink = _schedule_WIRE_15_bits_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_17; // @[Mux.scala:30:73] assign _schedule_WIRE_15_bits_sink = _schedule_WIRE_16_sink; // @[Mux.scala:30:73] wire [2:0] _schedule_T_242 = _schedule_T ? _mshrs_0_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_243 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_244 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_245 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_246 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_247 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_248 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_249 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_250 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_251 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_252 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_253 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_e_bits_sink : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_254 = _schedule_T_242 | _schedule_T_243; // @[Mux.scala:30:73] wire [2:0] _schedule_T_255 = _schedule_T_254 | _schedule_T_244; // @[Mux.scala:30:73] wire [2:0] _schedule_T_256 = _schedule_T_255 | _schedule_T_245; // @[Mux.scala:30:73] wire [2:0] _schedule_T_257 = _schedule_T_256 | _schedule_T_246; // @[Mux.scala:30:73] wire [2:0] _schedule_T_258 = _schedule_T_257 | _schedule_T_247; // @[Mux.scala:30:73] wire [2:0] _schedule_T_259 = _schedule_T_258 | _schedule_T_248; // @[Mux.scala:30:73] wire [2:0] _schedule_T_260 = _schedule_T_259 | _schedule_T_249; // @[Mux.scala:30:73] wire [2:0] _schedule_T_261 = _schedule_T_260 | _schedule_T_250; // @[Mux.scala:30:73] wire [2:0] _schedule_T_262 = _schedule_T_261 | _schedule_T_251; // @[Mux.scala:30:73] wire [2:0] _schedule_T_263 = _schedule_T_262 | _schedule_T_252; // @[Mux.scala:30:73] wire [2:0] _schedule_T_264 = _schedule_T_263 | _schedule_T_253; // @[Mux.scala:30:73] assign _schedule_WIRE_17 = _schedule_T_264; // @[Mux.scala:30:73] assign _schedule_WIRE_16_sink = _schedule_WIRE_17; // @[Mux.scala:30:73] wire _schedule_T_265 = _schedule_T & _mshrs_0_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_266 = _schedule_T_1 & _mshrs_1_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_267 = _schedule_T_2 & _mshrs_2_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_268 = _schedule_T_3 & _mshrs_3_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_269 = _schedule_T_4 & _mshrs_4_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_270 = _schedule_T_5 & _mshrs_5_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_271 = _schedule_T_6 & _mshrs_6_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_272 = _schedule_T_7 & _mshrs_7_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_273 = _schedule_T_8 & _mshrs_8_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_274 = _schedule_T_9 & _mshrs_9_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_275 = _schedule_T_10 & _mshrs_10_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_276 = _schedule_T_11 & _mshrs_11_io_schedule_bits_e_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_277 = _schedule_T_265 | _schedule_T_266; // @[Mux.scala:30:73] wire _schedule_T_278 = _schedule_T_277 | _schedule_T_267; // @[Mux.scala:30:73] wire _schedule_T_279 = _schedule_T_278 | _schedule_T_268; // @[Mux.scala:30:73] wire _schedule_T_280 = _schedule_T_279 | _schedule_T_269; // @[Mux.scala:30:73] wire _schedule_T_281 = _schedule_T_280 | _schedule_T_270; // @[Mux.scala:30:73] wire _schedule_T_282 = _schedule_T_281 | _schedule_T_271; // @[Mux.scala:30:73] wire _schedule_T_283 = _schedule_T_282 | _schedule_T_272; // @[Mux.scala:30:73] wire _schedule_T_284 = _schedule_T_283 | _schedule_T_273; // @[Mux.scala:30:73] wire _schedule_T_285 = _schedule_T_284 | _schedule_T_274; // @[Mux.scala:30:73] wire _schedule_T_286 = _schedule_T_285 | _schedule_T_275; // @[Mux.scala:30:73] wire _schedule_T_287 = _schedule_T_286 | _schedule_T_276; // @[Mux.scala:30:73] assign _schedule_WIRE_18 = _schedule_T_287; // @[Mux.scala:30:73] assign _schedule_WIRE_15_valid = _schedule_WIRE_18; // @[Mux.scala:30:73] wire _schedule_WIRE_37; // @[Mux.scala:30:73] assign schedule_d_valid = _schedule_WIRE_19_valid; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] assign schedule_d_bits_prio_0 = _schedule_WIRE_19_bits_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] assign schedule_d_bits_prio_1 = _schedule_WIRE_19_bits_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] assign schedule_d_bits_prio_2 = _schedule_WIRE_19_bits_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_20_control; // @[Mux.scala:30:73] assign schedule_d_bits_control = _schedule_WIRE_19_bits_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] assign schedule_d_bits_opcode = _schedule_WIRE_19_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_param; // @[Mux.scala:30:73] assign schedule_d_bits_param = _schedule_WIRE_19_bits_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_20_size; // @[Mux.scala:30:73] assign schedule_d_bits_size = _schedule_WIRE_19_bits_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_source; // @[Mux.scala:30:73] assign schedule_d_bits_source = _schedule_WIRE_19_bits_source; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_20_tag; // @[Mux.scala:30:73] assign schedule_d_bits_tag = _schedule_WIRE_19_bits_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_offset; // @[Mux.scala:30:73] assign schedule_d_bits_offset = _schedule_WIRE_19_bits_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_20_put; // @[Mux.scala:30:73] assign schedule_d_bits_put = _schedule_WIRE_19_bits_put; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_20_set; // @[Mux.scala:30:73] assign schedule_d_bits_set = _schedule_WIRE_19_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_20_way; // @[Mux.scala:30:73] assign schedule_d_bits_way = _schedule_WIRE_19_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_20_bad; // @[Mux.scala:30:73] assign schedule_d_bits_bad = _schedule_WIRE_19_bits_bad; // @[Mux.scala:30:73] wire _schedule_WIRE_33_0; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_0 = _schedule_WIRE_20_prio_0; // @[Mux.scala:30:73] wire _schedule_WIRE_33_1; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_1 = _schedule_WIRE_20_prio_1; // @[Mux.scala:30:73] wire _schedule_WIRE_33_2; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_prio_2 = _schedule_WIRE_20_prio_2; // @[Mux.scala:30:73] wire _schedule_WIRE_32; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_control = _schedule_WIRE_20_control; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_31; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_opcode = _schedule_WIRE_20_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_30; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_param = _schedule_WIRE_20_param; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_29; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_size = _schedule_WIRE_20_size; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_28; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_source = _schedule_WIRE_20_source; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_27; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_tag = _schedule_WIRE_20_tag; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_26; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_offset = _schedule_WIRE_20_offset; // @[Mux.scala:30:73] wire [5:0] _schedule_WIRE_25; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_put = _schedule_WIRE_20_put; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_24; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_set = _schedule_WIRE_20_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_22; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_way = _schedule_WIRE_20_way; // @[Mux.scala:30:73] wire _schedule_WIRE_21; // @[Mux.scala:30:73] assign _schedule_WIRE_19_bits_bad = _schedule_WIRE_20_bad; // @[Mux.scala:30:73] wire _schedule_T_288 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_289 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_290 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_291 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_292 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_293 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_294 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_295 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_296 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_297 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_298 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_299 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_bad; // @[Mux.scala:30:73, :32:36] wire _schedule_T_300 = _schedule_T_288 | _schedule_T_289; // @[Mux.scala:30:73] wire _schedule_T_301 = _schedule_T_300 | _schedule_T_290; // @[Mux.scala:30:73] wire _schedule_T_302 = _schedule_T_301 | _schedule_T_291; // @[Mux.scala:30:73] wire _schedule_T_303 = _schedule_T_302 | _schedule_T_292; // @[Mux.scala:30:73] wire _schedule_T_304 = _schedule_T_303 | _schedule_T_293; // @[Mux.scala:30:73] wire _schedule_T_305 = _schedule_T_304 | _schedule_T_294; // @[Mux.scala:30:73] wire _schedule_T_306 = _schedule_T_305 | _schedule_T_295; // @[Mux.scala:30:73] wire _schedule_T_307 = _schedule_T_306 | _schedule_T_296; // @[Mux.scala:30:73] wire _schedule_T_308 = _schedule_T_307 | _schedule_T_297; // @[Mux.scala:30:73] wire _schedule_T_309 = _schedule_T_308 | _schedule_T_298; // @[Mux.scala:30:73] wire _schedule_T_310 = _schedule_T_309 | _schedule_T_299; // @[Mux.scala:30:73] assign _schedule_WIRE_21 = _schedule_T_310; // @[Mux.scala:30:73] assign _schedule_WIRE_20_bad = _schedule_WIRE_21; // @[Mux.scala:30:73] wire [3:0] _schedule_T_311 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_312 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_313 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_314 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_315 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_316 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_317 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_318 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_319 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_320 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_321 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_322 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_323 = _schedule_T_311 | _schedule_T_312; // @[Mux.scala:30:73] wire [3:0] _schedule_T_324 = _schedule_T_323 | _schedule_T_313; // @[Mux.scala:30:73] wire [3:0] _schedule_T_325 = _schedule_T_324 | _schedule_T_314; // @[Mux.scala:30:73] wire [3:0] _schedule_T_326 = _schedule_T_325 | _schedule_T_315; // @[Mux.scala:30:73] wire [3:0] _schedule_T_327 = _schedule_T_326 | _schedule_T_316; // @[Mux.scala:30:73] wire [3:0] _schedule_T_328 = _schedule_T_327 | _schedule_T_317; // @[Mux.scala:30:73] wire [3:0] _schedule_T_329 = _schedule_T_328 | _schedule_T_318; // @[Mux.scala:30:73] wire [3:0] _schedule_T_330 = _schedule_T_329 | _schedule_T_319; // @[Mux.scala:30:73] wire [3:0] _schedule_T_331 = _schedule_T_330 | _schedule_T_320; // @[Mux.scala:30:73] wire [3:0] _schedule_T_332 = _schedule_T_331 | _schedule_T_321; // @[Mux.scala:30:73] wire [3:0] _schedule_T_333 = _schedule_T_332 | _schedule_T_322; // @[Mux.scala:30:73] assign _schedule_WIRE_22 = _schedule_T_333; // @[Mux.scala:30:73] assign _schedule_WIRE_20_way = _schedule_WIRE_22; // @[Mux.scala:30:73] wire [10:0] _schedule_T_357 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_358 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_359 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_360 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_361 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_362 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_363 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_364 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_365 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_366 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_367 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_368 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_369 = _schedule_T_357 | _schedule_T_358; // @[Mux.scala:30:73] wire [10:0] _schedule_T_370 = _schedule_T_369 | _schedule_T_359; // @[Mux.scala:30:73] wire [10:0] _schedule_T_371 = _schedule_T_370 | _schedule_T_360; // @[Mux.scala:30:73] wire [10:0] _schedule_T_372 = _schedule_T_371 | _schedule_T_361; // @[Mux.scala:30:73] wire [10:0] _schedule_T_373 = _schedule_T_372 | _schedule_T_362; // @[Mux.scala:30:73] wire [10:0] _schedule_T_374 = _schedule_T_373 | _schedule_T_363; // @[Mux.scala:30:73] wire [10:0] _schedule_T_375 = _schedule_T_374 | _schedule_T_364; // @[Mux.scala:30:73] wire [10:0] _schedule_T_376 = _schedule_T_375 | _schedule_T_365; // @[Mux.scala:30:73] wire [10:0] _schedule_T_377 = _schedule_T_376 | _schedule_T_366; // @[Mux.scala:30:73] wire [10:0] _schedule_T_378 = _schedule_T_377 | _schedule_T_367; // @[Mux.scala:30:73] wire [10:0] _schedule_T_379 = _schedule_T_378 | _schedule_T_368; // @[Mux.scala:30:73] assign _schedule_WIRE_24 = _schedule_T_379; // @[Mux.scala:30:73] assign _schedule_WIRE_20_set = _schedule_WIRE_24; // @[Mux.scala:30:73] wire [5:0] _schedule_T_380 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_381 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_382 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_383 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_384 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_385 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_386 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_387 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_388 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_389 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_390 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_391 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_put : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_392 = _schedule_T_380 | _schedule_T_381; // @[Mux.scala:30:73] wire [5:0] _schedule_T_393 = _schedule_T_392 | _schedule_T_382; // @[Mux.scala:30:73] wire [5:0] _schedule_T_394 = _schedule_T_393 | _schedule_T_383; // @[Mux.scala:30:73] wire [5:0] _schedule_T_395 = _schedule_T_394 | _schedule_T_384; // @[Mux.scala:30:73] wire [5:0] _schedule_T_396 = _schedule_T_395 | _schedule_T_385; // @[Mux.scala:30:73] wire [5:0] _schedule_T_397 = _schedule_T_396 | _schedule_T_386; // @[Mux.scala:30:73] wire [5:0] _schedule_T_398 = _schedule_T_397 | _schedule_T_387; // @[Mux.scala:30:73] wire [5:0] _schedule_T_399 = _schedule_T_398 | _schedule_T_388; // @[Mux.scala:30:73] wire [5:0] _schedule_T_400 = _schedule_T_399 | _schedule_T_389; // @[Mux.scala:30:73] wire [5:0] _schedule_T_401 = _schedule_T_400 | _schedule_T_390; // @[Mux.scala:30:73] wire [5:0] _schedule_T_402 = _schedule_T_401 | _schedule_T_391; // @[Mux.scala:30:73] assign _schedule_WIRE_25 = _schedule_T_402; // @[Mux.scala:30:73] assign _schedule_WIRE_20_put = _schedule_WIRE_25; // @[Mux.scala:30:73] wire [5:0] _schedule_T_403 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_404 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_405 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_406 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_407 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_408 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_409 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_410 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_411 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_412 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_413 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_414 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_offset : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_415 = _schedule_T_403 | _schedule_T_404; // @[Mux.scala:30:73] wire [5:0] _schedule_T_416 = _schedule_T_415 | _schedule_T_405; // @[Mux.scala:30:73] wire [5:0] _schedule_T_417 = _schedule_T_416 | _schedule_T_406; // @[Mux.scala:30:73] wire [5:0] _schedule_T_418 = _schedule_T_417 | _schedule_T_407; // @[Mux.scala:30:73] wire [5:0] _schedule_T_419 = _schedule_T_418 | _schedule_T_408; // @[Mux.scala:30:73] wire [5:0] _schedule_T_420 = _schedule_T_419 | _schedule_T_409; // @[Mux.scala:30:73] wire [5:0] _schedule_T_421 = _schedule_T_420 | _schedule_T_410; // @[Mux.scala:30:73] wire [5:0] _schedule_T_422 = _schedule_T_421 | _schedule_T_411; // @[Mux.scala:30:73] wire [5:0] _schedule_T_423 = _schedule_T_422 | _schedule_T_412; // @[Mux.scala:30:73] wire [5:0] _schedule_T_424 = _schedule_T_423 | _schedule_T_413; // @[Mux.scala:30:73] wire [5:0] _schedule_T_425 = _schedule_T_424 | _schedule_T_414; // @[Mux.scala:30:73] assign _schedule_WIRE_26 = _schedule_T_425; // @[Mux.scala:30:73] assign _schedule_WIRE_20_offset = _schedule_WIRE_26; // @[Mux.scala:30:73] wire [8:0] _schedule_T_426 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_427 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_428 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_429 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_430 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_431 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_432 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_433 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_434 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_435 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_436 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_437 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_438 = _schedule_T_426 | _schedule_T_427; // @[Mux.scala:30:73] wire [8:0] _schedule_T_439 = _schedule_T_438 | _schedule_T_428; // @[Mux.scala:30:73] wire [8:0] _schedule_T_440 = _schedule_T_439 | _schedule_T_429; // @[Mux.scala:30:73] wire [8:0] _schedule_T_441 = _schedule_T_440 | _schedule_T_430; // @[Mux.scala:30:73] wire [8:0] _schedule_T_442 = _schedule_T_441 | _schedule_T_431; // @[Mux.scala:30:73] wire [8:0] _schedule_T_443 = _schedule_T_442 | _schedule_T_432; // @[Mux.scala:30:73] wire [8:0] _schedule_T_444 = _schedule_T_443 | _schedule_T_433; // @[Mux.scala:30:73] wire [8:0] _schedule_T_445 = _schedule_T_444 | _schedule_T_434; // @[Mux.scala:30:73] wire [8:0] _schedule_T_446 = _schedule_T_445 | _schedule_T_435; // @[Mux.scala:30:73] wire [8:0] _schedule_T_447 = _schedule_T_446 | _schedule_T_436; // @[Mux.scala:30:73] wire [8:0] _schedule_T_448 = _schedule_T_447 | _schedule_T_437; // @[Mux.scala:30:73] assign _schedule_WIRE_27 = _schedule_T_448; // @[Mux.scala:30:73] assign _schedule_WIRE_20_tag = _schedule_WIRE_27; // @[Mux.scala:30:73] wire [5:0] _schedule_T_449 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_450 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_451 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_452 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_453 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_454 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_455 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_456 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_457 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_458 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_459 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_460 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_source : 6'h0; // @[Mux.scala:30:73, :32:36] wire [5:0] _schedule_T_461 = _schedule_T_449 | _schedule_T_450; // @[Mux.scala:30:73] wire [5:0] _schedule_T_462 = _schedule_T_461 | _schedule_T_451; // @[Mux.scala:30:73] wire [5:0] _schedule_T_463 = _schedule_T_462 | _schedule_T_452; // @[Mux.scala:30:73] wire [5:0] _schedule_T_464 = _schedule_T_463 | _schedule_T_453; // @[Mux.scala:30:73] wire [5:0] _schedule_T_465 = _schedule_T_464 | _schedule_T_454; // @[Mux.scala:30:73] wire [5:0] _schedule_T_466 = _schedule_T_465 | _schedule_T_455; // @[Mux.scala:30:73] wire [5:0] _schedule_T_467 = _schedule_T_466 | _schedule_T_456; // @[Mux.scala:30:73] wire [5:0] _schedule_T_468 = _schedule_T_467 | _schedule_T_457; // @[Mux.scala:30:73] wire [5:0] _schedule_T_469 = _schedule_T_468 | _schedule_T_458; // @[Mux.scala:30:73] wire [5:0] _schedule_T_470 = _schedule_T_469 | _schedule_T_459; // @[Mux.scala:30:73] wire [5:0] _schedule_T_471 = _schedule_T_470 | _schedule_T_460; // @[Mux.scala:30:73] assign _schedule_WIRE_28 = _schedule_T_471; // @[Mux.scala:30:73] assign _schedule_WIRE_20_source = _schedule_WIRE_28; // @[Mux.scala:30:73] wire [2:0] _schedule_T_472 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_473 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_474 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_475 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_476 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_477 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_478 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_479 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_480 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_481 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_482 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_483 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_size : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_484 = _schedule_T_472 | _schedule_T_473; // @[Mux.scala:30:73] wire [2:0] _schedule_T_485 = _schedule_T_484 | _schedule_T_474; // @[Mux.scala:30:73] wire [2:0] _schedule_T_486 = _schedule_T_485 | _schedule_T_475; // @[Mux.scala:30:73] wire [2:0] _schedule_T_487 = _schedule_T_486 | _schedule_T_476; // @[Mux.scala:30:73] wire [2:0] _schedule_T_488 = _schedule_T_487 | _schedule_T_477; // @[Mux.scala:30:73] wire [2:0] _schedule_T_489 = _schedule_T_488 | _schedule_T_478; // @[Mux.scala:30:73] wire [2:0] _schedule_T_490 = _schedule_T_489 | _schedule_T_479; // @[Mux.scala:30:73] wire [2:0] _schedule_T_491 = _schedule_T_490 | _schedule_T_480; // @[Mux.scala:30:73] wire [2:0] _schedule_T_492 = _schedule_T_491 | _schedule_T_481; // @[Mux.scala:30:73] wire [2:0] _schedule_T_493 = _schedule_T_492 | _schedule_T_482; // @[Mux.scala:30:73] wire [2:0] _schedule_T_494 = _schedule_T_493 | _schedule_T_483; // @[Mux.scala:30:73] assign _schedule_WIRE_29 = _schedule_T_494; // @[Mux.scala:30:73] assign _schedule_WIRE_20_size = _schedule_WIRE_29; // @[Mux.scala:30:73] wire [2:0] _schedule_T_495 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_496 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_497 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_498 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_499 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_500 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_501 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_502 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_503 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_504 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_505 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_506 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_507 = _schedule_T_495 | _schedule_T_496; // @[Mux.scala:30:73] wire [2:0] _schedule_T_508 = _schedule_T_507 | _schedule_T_497; // @[Mux.scala:30:73] wire [2:0] _schedule_T_509 = _schedule_T_508 | _schedule_T_498; // @[Mux.scala:30:73] wire [2:0] _schedule_T_510 = _schedule_T_509 | _schedule_T_499; // @[Mux.scala:30:73] wire [2:0] _schedule_T_511 = _schedule_T_510 | _schedule_T_500; // @[Mux.scala:30:73] wire [2:0] _schedule_T_512 = _schedule_T_511 | _schedule_T_501; // @[Mux.scala:30:73] wire [2:0] _schedule_T_513 = _schedule_T_512 | _schedule_T_502; // @[Mux.scala:30:73] wire [2:0] _schedule_T_514 = _schedule_T_513 | _schedule_T_503; // @[Mux.scala:30:73] wire [2:0] _schedule_T_515 = _schedule_T_514 | _schedule_T_504; // @[Mux.scala:30:73] wire [2:0] _schedule_T_516 = _schedule_T_515 | _schedule_T_505; // @[Mux.scala:30:73] wire [2:0] _schedule_T_517 = _schedule_T_516 | _schedule_T_506; // @[Mux.scala:30:73] assign _schedule_WIRE_30 = _schedule_T_517; // @[Mux.scala:30:73] assign _schedule_WIRE_20_param = _schedule_WIRE_30; // @[Mux.scala:30:73] wire [2:0] _schedule_T_518 = _schedule_T ? _mshrs_0_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_519 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_520 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_521 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_522 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_523 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_524 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_525 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_526 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_527 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_528 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_529 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_d_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_530 = _schedule_T_518 | _schedule_T_519; // @[Mux.scala:30:73] wire [2:0] _schedule_T_531 = _schedule_T_530 | _schedule_T_520; // @[Mux.scala:30:73] wire [2:0] _schedule_T_532 = _schedule_T_531 | _schedule_T_521; // @[Mux.scala:30:73] wire [2:0] _schedule_T_533 = _schedule_T_532 | _schedule_T_522; // @[Mux.scala:30:73] wire [2:0] _schedule_T_534 = _schedule_T_533 | _schedule_T_523; // @[Mux.scala:30:73] wire [2:0] _schedule_T_535 = _schedule_T_534 | _schedule_T_524; // @[Mux.scala:30:73] wire [2:0] _schedule_T_536 = _schedule_T_535 | _schedule_T_525; // @[Mux.scala:30:73] wire [2:0] _schedule_T_537 = _schedule_T_536 | _schedule_T_526; // @[Mux.scala:30:73] wire [2:0] _schedule_T_538 = _schedule_T_537 | _schedule_T_527; // @[Mux.scala:30:73] wire [2:0] _schedule_T_539 = _schedule_T_538 | _schedule_T_528; // @[Mux.scala:30:73] wire [2:0] _schedule_T_540 = _schedule_T_539 | _schedule_T_529; // @[Mux.scala:30:73] assign _schedule_WIRE_31 = _schedule_T_540; // @[Mux.scala:30:73] assign _schedule_WIRE_20_opcode = _schedule_WIRE_31; // @[Mux.scala:30:73] wire _schedule_T_541 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_542 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_543 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_544 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_545 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_546 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_547 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_548 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_549 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_550 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_551 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_552 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_control; // @[Mux.scala:30:73, :32:36] wire _schedule_T_553 = _schedule_T_541 | _schedule_T_542; // @[Mux.scala:30:73] wire _schedule_T_554 = _schedule_T_553 | _schedule_T_543; // @[Mux.scala:30:73] wire _schedule_T_555 = _schedule_T_554 | _schedule_T_544; // @[Mux.scala:30:73] wire _schedule_T_556 = _schedule_T_555 | _schedule_T_545; // @[Mux.scala:30:73] wire _schedule_T_557 = _schedule_T_556 | _schedule_T_546; // @[Mux.scala:30:73] wire _schedule_T_558 = _schedule_T_557 | _schedule_T_547; // @[Mux.scala:30:73] wire _schedule_T_559 = _schedule_T_558 | _schedule_T_548; // @[Mux.scala:30:73] wire _schedule_T_560 = _schedule_T_559 | _schedule_T_549; // @[Mux.scala:30:73] wire _schedule_T_561 = _schedule_T_560 | _schedule_T_550; // @[Mux.scala:30:73] wire _schedule_T_562 = _schedule_T_561 | _schedule_T_551; // @[Mux.scala:30:73] wire _schedule_T_563 = _schedule_T_562 | _schedule_T_552; // @[Mux.scala:30:73] assign _schedule_WIRE_32 = _schedule_T_563; // @[Mux.scala:30:73] assign _schedule_WIRE_20_control = _schedule_WIRE_32; // @[Mux.scala:30:73] wire _schedule_WIRE_34; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_0 = _schedule_WIRE_33_0; // @[Mux.scala:30:73] wire _schedule_WIRE_35; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_1 = _schedule_WIRE_33_1; // @[Mux.scala:30:73] wire _schedule_WIRE_36; // @[Mux.scala:30:73] assign _schedule_WIRE_20_prio_2 = _schedule_WIRE_33_2; // @[Mux.scala:30:73] wire _schedule_T_564 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_565 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_566 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_567 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_568 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_569 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_570 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_571 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_572 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_573 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_0; // @[Mux.scala:30:73, :32:36] wire _schedule_T_576 = _schedule_T_564 | _schedule_T_565; // @[Mux.scala:30:73] wire _schedule_T_577 = _schedule_T_576 | _schedule_T_566; // @[Mux.scala:30:73] wire _schedule_T_578 = _schedule_T_577 | _schedule_T_567; // @[Mux.scala:30:73] wire _schedule_T_579 = _schedule_T_578 | _schedule_T_568; // @[Mux.scala:30:73] wire _schedule_T_580 = _schedule_T_579 | _schedule_T_569; // @[Mux.scala:30:73] wire _schedule_T_581 = _schedule_T_580 | _schedule_T_570; // @[Mux.scala:30:73] wire _schedule_T_582 = _schedule_T_581 | _schedule_T_571; // @[Mux.scala:30:73] wire _schedule_T_583 = _schedule_T_582 | _schedule_T_572; // @[Mux.scala:30:73] wire _schedule_T_584 = _schedule_T_583 | _schedule_T_573; // @[Mux.scala:30:73] wire _schedule_T_585 = _schedule_T_584; // @[Mux.scala:30:73] wire _schedule_T_586 = _schedule_T_585; // @[Mux.scala:30:73] assign _schedule_WIRE_34 = _schedule_T_586; // @[Mux.scala:30:73] assign _schedule_WIRE_33_0 = _schedule_WIRE_34; // @[Mux.scala:30:73] wire _schedule_T_587 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_588 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_589 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_590 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_591 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_592 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_593 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_594 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_595 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_596 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_597 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_1; // @[Mux.scala:30:73, :32:36] wire _schedule_T_599 = _schedule_T_587 | _schedule_T_588; // @[Mux.scala:30:73] wire _schedule_T_600 = _schedule_T_599 | _schedule_T_589; // @[Mux.scala:30:73] wire _schedule_T_601 = _schedule_T_600 | _schedule_T_590; // @[Mux.scala:30:73] wire _schedule_T_602 = _schedule_T_601 | _schedule_T_591; // @[Mux.scala:30:73] wire _schedule_T_603 = _schedule_T_602 | _schedule_T_592; // @[Mux.scala:30:73] wire _schedule_T_604 = _schedule_T_603 | _schedule_T_593; // @[Mux.scala:30:73] wire _schedule_T_605 = _schedule_T_604 | _schedule_T_594; // @[Mux.scala:30:73] wire _schedule_T_606 = _schedule_T_605 | _schedule_T_595; // @[Mux.scala:30:73] wire _schedule_T_607 = _schedule_T_606 | _schedule_T_596; // @[Mux.scala:30:73] wire _schedule_T_608 = _schedule_T_607 | _schedule_T_597; // @[Mux.scala:30:73] wire _schedule_T_609 = _schedule_T_608; // @[Mux.scala:30:73] assign _schedule_WIRE_35 = _schedule_T_609; // @[Mux.scala:30:73] assign _schedule_WIRE_33_1 = _schedule_WIRE_35; // @[Mux.scala:30:73] wire _schedule_T_610 = _schedule_T & _mshrs_0_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_611 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_612 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_613 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_614 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_615 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_616 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_617 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_618 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_619 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_620 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_621 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_bits_prio_2; // @[Mux.scala:30:73, :32:36] wire _schedule_T_622 = _schedule_T_610 | _schedule_T_611; // @[Mux.scala:30:73] wire _schedule_T_623 = _schedule_T_622 | _schedule_T_612; // @[Mux.scala:30:73] wire _schedule_T_624 = _schedule_T_623 | _schedule_T_613; // @[Mux.scala:30:73] wire _schedule_T_625 = _schedule_T_624 | _schedule_T_614; // @[Mux.scala:30:73] wire _schedule_T_626 = _schedule_T_625 | _schedule_T_615; // @[Mux.scala:30:73] wire _schedule_T_627 = _schedule_T_626 | _schedule_T_616; // @[Mux.scala:30:73] wire _schedule_T_628 = _schedule_T_627 | _schedule_T_617; // @[Mux.scala:30:73] wire _schedule_T_629 = _schedule_T_628 | _schedule_T_618; // @[Mux.scala:30:73] wire _schedule_T_630 = _schedule_T_629 | _schedule_T_619; // @[Mux.scala:30:73] wire _schedule_T_631 = _schedule_T_630 | _schedule_T_620; // @[Mux.scala:30:73] wire _schedule_T_632 = _schedule_T_631 | _schedule_T_621; // @[Mux.scala:30:73] assign _schedule_WIRE_36 = _schedule_T_632; // @[Mux.scala:30:73] assign _schedule_WIRE_33_2 = _schedule_WIRE_36; // @[Mux.scala:30:73] wire _schedule_T_633 = _schedule_T & _mshrs_0_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_634 = _schedule_T_1 & _mshrs_1_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_635 = _schedule_T_2 & _mshrs_2_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_636 = _schedule_T_3 & _mshrs_3_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_637 = _schedule_T_4 & _mshrs_4_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_638 = _schedule_T_5 & _mshrs_5_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_639 = _schedule_T_6 & _mshrs_6_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_640 = _schedule_T_7 & _mshrs_7_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_641 = _schedule_T_8 & _mshrs_8_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_642 = _schedule_T_9 & _mshrs_9_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_643 = _schedule_T_10 & _mshrs_10_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_644 = _schedule_T_11 & _mshrs_11_io_schedule_bits_d_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_645 = _schedule_T_633 | _schedule_T_634; // @[Mux.scala:30:73] wire _schedule_T_646 = _schedule_T_645 | _schedule_T_635; // @[Mux.scala:30:73] wire _schedule_T_647 = _schedule_T_646 | _schedule_T_636; // @[Mux.scala:30:73] wire _schedule_T_648 = _schedule_T_647 | _schedule_T_637; // @[Mux.scala:30:73] wire _schedule_T_649 = _schedule_T_648 | _schedule_T_638; // @[Mux.scala:30:73] wire _schedule_T_650 = _schedule_T_649 | _schedule_T_639; // @[Mux.scala:30:73] wire _schedule_T_651 = _schedule_T_650 | _schedule_T_640; // @[Mux.scala:30:73] wire _schedule_T_652 = _schedule_T_651 | _schedule_T_641; // @[Mux.scala:30:73] wire _schedule_T_653 = _schedule_T_652 | _schedule_T_642; // @[Mux.scala:30:73] wire _schedule_T_654 = _schedule_T_653 | _schedule_T_643; // @[Mux.scala:30:73] wire _schedule_T_655 = _schedule_T_654 | _schedule_T_644; // @[Mux.scala:30:73] assign _schedule_WIRE_37 = _schedule_T_655; // @[Mux.scala:30:73] assign _schedule_WIRE_19_valid = _schedule_WIRE_37; // @[Mux.scala:30:73] wire _schedule_WIRE_47; // @[Mux.scala:30:73] assign schedule_c_valid = _schedule_WIRE_38_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] assign schedule_c_bits_opcode = _schedule_WIRE_38_bits_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_39_param; // @[Mux.scala:30:73] assign schedule_c_bits_param = _schedule_WIRE_38_bits_param; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_39_tag; // @[Mux.scala:30:73] assign schedule_c_bits_tag = _schedule_WIRE_38_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_39_set; // @[Mux.scala:30:73] assign schedule_c_bits_set = _schedule_WIRE_38_bits_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_39_way; // @[Mux.scala:30:73] assign schedule_c_bits_way = _schedule_WIRE_38_bits_way; // @[Mux.scala:30:73] wire _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] assign schedule_c_bits_dirty = _schedule_WIRE_38_bits_dirty; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_46; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_opcode = _schedule_WIRE_39_opcode; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_45; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_param = _schedule_WIRE_39_param; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_43; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_tag = _schedule_WIRE_39_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_42; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_set = _schedule_WIRE_39_set; // @[Mux.scala:30:73] wire [3:0] _schedule_WIRE_41; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_way = _schedule_WIRE_39_way; // @[Mux.scala:30:73] wire _schedule_WIRE_40; // @[Mux.scala:30:73] assign _schedule_WIRE_38_bits_dirty = _schedule_WIRE_39_dirty; // @[Mux.scala:30:73] wire _schedule_T_656 = _schedule_T & _mshrs_0_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_657 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_658 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_659 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_660 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_661 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_662 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_663 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_664 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_665 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_666 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_667 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_bits_dirty; // @[Mux.scala:30:73, :32:36] wire _schedule_T_668 = _schedule_T_656 | _schedule_T_657; // @[Mux.scala:30:73] wire _schedule_T_669 = _schedule_T_668 | _schedule_T_658; // @[Mux.scala:30:73] wire _schedule_T_670 = _schedule_T_669 | _schedule_T_659; // @[Mux.scala:30:73] wire _schedule_T_671 = _schedule_T_670 | _schedule_T_660; // @[Mux.scala:30:73] wire _schedule_T_672 = _schedule_T_671 | _schedule_T_661; // @[Mux.scala:30:73] wire _schedule_T_673 = _schedule_T_672 | _schedule_T_662; // @[Mux.scala:30:73] wire _schedule_T_674 = _schedule_T_673 | _schedule_T_663; // @[Mux.scala:30:73] wire _schedule_T_675 = _schedule_T_674 | _schedule_T_664; // @[Mux.scala:30:73] wire _schedule_T_676 = _schedule_T_675 | _schedule_T_665; // @[Mux.scala:30:73] wire _schedule_T_677 = _schedule_T_676 | _schedule_T_666; // @[Mux.scala:30:73] wire _schedule_T_678 = _schedule_T_677 | _schedule_T_667; // @[Mux.scala:30:73] assign _schedule_WIRE_40 = _schedule_T_678; // @[Mux.scala:30:73] assign _schedule_WIRE_39_dirty = _schedule_WIRE_40; // @[Mux.scala:30:73] wire [3:0] _schedule_T_679 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_680 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_681 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_682 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_683 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_684 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_685 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_686 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_687 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_688 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_689 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_690 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_way : 4'h0; // @[Mux.scala:30:73, :32:36] wire [3:0] _schedule_T_691 = _schedule_T_679 | _schedule_T_680; // @[Mux.scala:30:73] wire [3:0] _schedule_T_692 = _schedule_T_691 | _schedule_T_681; // @[Mux.scala:30:73] wire [3:0] _schedule_T_693 = _schedule_T_692 | _schedule_T_682; // @[Mux.scala:30:73] wire [3:0] _schedule_T_694 = _schedule_T_693 | _schedule_T_683; // @[Mux.scala:30:73] wire [3:0] _schedule_T_695 = _schedule_T_694 | _schedule_T_684; // @[Mux.scala:30:73] wire [3:0] _schedule_T_696 = _schedule_T_695 | _schedule_T_685; // @[Mux.scala:30:73] wire [3:0] _schedule_T_697 = _schedule_T_696 | _schedule_T_686; // @[Mux.scala:30:73] wire [3:0] _schedule_T_698 = _schedule_T_697 | _schedule_T_687; // @[Mux.scala:30:73] wire [3:0] _schedule_T_699 = _schedule_T_698 | _schedule_T_688; // @[Mux.scala:30:73] wire [3:0] _schedule_T_700 = _schedule_T_699 | _schedule_T_689; // @[Mux.scala:30:73] wire [3:0] _schedule_T_701 = _schedule_T_700 | _schedule_T_690; // @[Mux.scala:30:73] assign _schedule_WIRE_41 = _schedule_T_701; // @[Mux.scala:30:73] assign _schedule_WIRE_39_way = _schedule_WIRE_41; // @[Mux.scala:30:73] wire [10:0] _schedule_T_702 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_703 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_704 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_705 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_706 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_707 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_708 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_709 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_710 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_711 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_712 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_713 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_714 = _schedule_T_702 | _schedule_T_703; // @[Mux.scala:30:73] wire [10:0] _schedule_T_715 = _schedule_T_714 | _schedule_T_704; // @[Mux.scala:30:73] wire [10:0] _schedule_T_716 = _schedule_T_715 | _schedule_T_705; // @[Mux.scala:30:73] wire [10:0] _schedule_T_717 = _schedule_T_716 | _schedule_T_706; // @[Mux.scala:30:73] wire [10:0] _schedule_T_718 = _schedule_T_717 | _schedule_T_707; // @[Mux.scala:30:73] wire [10:0] _schedule_T_719 = _schedule_T_718 | _schedule_T_708; // @[Mux.scala:30:73] wire [10:0] _schedule_T_720 = _schedule_T_719 | _schedule_T_709; // @[Mux.scala:30:73] wire [10:0] _schedule_T_721 = _schedule_T_720 | _schedule_T_710; // @[Mux.scala:30:73] wire [10:0] _schedule_T_722 = _schedule_T_721 | _schedule_T_711; // @[Mux.scala:30:73] wire [10:0] _schedule_T_723 = _schedule_T_722 | _schedule_T_712; // @[Mux.scala:30:73] wire [10:0] _schedule_T_724 = _schedule_T_723 | _schedule_T_713; // @[Mux.scala:30:73] assign _schedule_WIRE_42 = _schedule_T_724; // @[Mux.scala:30:73] assign _schedule_WIRE_39_set = _schedule_WIRE_42; // @[Mux.scala:30:73] wire [8:0] _schedule_T_725 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_726 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_727 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_728 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_729 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_730 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_731 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_732 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_733 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_734 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_735 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_736 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_737 = _schedule_T_725 | _schedule_T_726; // @[Mux.scala:30:73] wire [8:0] _schedule_T_738 = _schedule_T_737 | _schedule_T_727; // @[Mux.scala:30:73] wire [8:0] _schedule_T_739 = _schedule_T_738 | _schedule_T_728; // @[Mux.scala:30:73] wire [8:0] _schedule_T_740 = _schedule_T_739 | _schedule_T_729; // @[Mux.scala:30:73] wire [8:0] _schedule_T_741 = _schedule_T_740 | _schedule_T_730; // @[Mux.scala:30:73] wire [8:0] _schedule_T_742 = _schedule_T_741 | _schedule_T_731; // @[Mux.scala:30:73] wire [8:0] _schedule_T_743 = _schedule_T_742 | _schedule_T_732; // @[Mux.scala:30:73] wire [8:0] _schedule_T_744 = _schedule_T_743 | _schedule_T_733; // @[Mux.scala:30:73] wire [8:0] _schedule_T_745 = _schedule_T_744 | _schedule_T_734; // @[Mux.scala:30:73] wire [8:0] _schedule_T_746 = _schedule_T_745 | _schedule_T_735; // @[Mux.scala:30:73] wire [8:0] _schedule_T_747 = _schedule_T_746 | _schedule_T_736; // @[Mux.scala:30:73] assign _schedule_WIRE_43 = _schedule_T_747; // @[Mux.scala:30:73] assign _schedule_WIRE_39_tag = _schedule_WIRE_43; // @[Mux.scala:30:73] wire [2:0] _schedule_T_771 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_772 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_773 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_774 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_775 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_776 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_777 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_778 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_779 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_780 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_781 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_782 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_783 = _schedule_T_771 | _schedule_T_772; // @[Mux.scala:30:73] wire [2:0] _schedule_T_784 = _schedule_T_783 | _schedule_T_773; // @[Mux.scala:30:73] wire [2:0] _schedule_T_785 = _schedule_T_784 | _schedule_T_774; // @[Mux.scala:30:73] wire [2:0] _schedule_T_786 = _schedule_T_785 | _schedule_T_775; // @[Mux.scala:30:73] wire [2:0] _schedule_T_787 = _schedule_T_786 | _schedule_T_776; // @[Mux.scala:30:73] wire [2:0] _schedule_T_788 = _schedule_T_787 | _schedule_T_777; // @[Mux.scala:30:73] wire [2:0] _schedule_T_789 = _schedule_T_788 | _schedule_T_778; // @[Mux.scala:30:73] wire [2:0] _schedule_T_790 = _schedule_T_789 | _schedule_T_779; // @[Mux.scala:30:73] wire [2:0] _schedule_T_791 = _schedule_T_790 | _schedule_T_780; // @[Mux.scala:30:73] wire [2:0] _schedule_T_792 = _schedule_T_791 | _schedule_T_781; // @[Mux.scala:30:73] wire [2:0] _schedule_T_793 = _schedule_T_792 | _schedule_T_782; // @[Mux.scala:30:73] assign _schedule_WIRE_45 = _schedule_T_793; // @[Mux.scala:30:73] assign _schedule_WIRE_39_param = _schedule_WIRE_45; // @[Mux.scala:30:73] wire [2:0] _schedule_T_794 = _schedule_T ? _mshrs_0_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_795 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_796 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_797 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_798 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_799 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_800 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_801 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_802 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_803 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_804 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_805 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_c_bits_opcode : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_806 = _schedule_T_794 | _schedule_T_795; // @[Mux.scala:30:73] wire [2:0] _schedule_T_807 = _schedule_T_806 | _schedule_T_796; // @[Mux.scala:30:73] wire [2:0] _schedule_T_808 = _schedule_T_807 | _schedule_T_797; // @[Mux.scala:30:73] wire [2:0] _schedule_T_809 = _schedule_T_808 | _schedule_T_798; // @[Mux.scala:30:73] wire [2:0] _schedule_T_810 = _schedule_T_809 | _schedule_T_799; // @[Mux.scala:30:73] wire [2:0] _schedule_T_811 = _schedule_T_810 | _schedule_T_800; // @[Mux.scala:30:73] wire [2:0] _schedule_T_812 = _schedule_T_811 | _schedule_T_801; // @[Mux.scala:30:73] wire [2:0] _schedule_T_813 = _schedule_T_812 | _schedule_T_802; // @[Mux.scala:30:73] wire [2:0] _schedule_T_814 = _schedule_T_813 | _schedule_T_803; // @[Mux.scala:30:73] wire [2:0] _schedule_T_815 = _schedule_T_814 | _schedule_T_804; // @[Mux.scala:30:73] wire [2:0] _schedule_T_816 = _schedule_T_815 | _schedule_T_805; // @[Mux.scala:30:73] assign _schedule_WIRE_46 = _schedule_T_816; // @[Mux.scala:30:73] assign _schedule_WIRE_39_opcode = _schedule_WIRE_46; // @[Mux.scala:30:73] wire _schedule_T_817 = _schedule_T & _mshrs_0_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_818 = _schedule_T_1 & _mshrs_1_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_819 = _schedule_T_2 & _mshrs_2_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_820 = _schedule_T_3 & _mshrs_3_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_821 = _schedule_T_4 & _mshrs_4_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_822 = _schedule_T_5 & _mshrs_5_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_823 = _schedule_T_6 & _mshrs_6_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_824 = _schedule_T_7 & _mshrs_7_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_825 = _schedule_T_8 & _mshrs_8_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_826 = _schedule_T_9 & _mshrs_9_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_827 = _schedule_T_10 & _mshrs_10_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_828 = _schedule_T_11 & _mshrs_11_io_schedule_bits_c_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_829 = _schedule_T_817 | _schedule_T_818; // @[Mux.scala:30:73] wire _schedule_T_830 = _schedule_T_829 | _schedule_T_819; // @[Mux.scala:30:73] wire _schedule_T_831 = _schedule_T_830 | _schedule_T_820; // @[Mux.scala:30:73] wire _schedule_T_832 = _schedule_T_831 | _schedule_T_821; // @[Mux.scala:30:73] wire _schedule_T_833 = _schedule_T_832 | _schedule_T_822; // @[Mux.scala:30:73] wire _schedule_T_834 = _schedule_T_833 | _schedule_T_823; // @[Mux.scala:30:73] wire _schedule_T_835 = _schedule_T_834 | _schedule_T_824; // @[Mux.scala:30:73] wire _schedule_T_836 = _schedule_T_835 | _schedule_T_825; // @[Mux.scala:30:73] wire _schedule_T_837 = _schedule_T_836 | _schedule_T_826; // @[Mux.scala:30:73] wire _schedule_T_838 = _schedule_T_837 | _schedule_T_827; // @[Mux.scala:30:73] wire _schedule_T_839 = _schedule_T_838 | _schedule_T_828; // @[Mux.scala:30:73] assign _schedule_WIRE_47 = _schedule_T_839; // @[Mux.scala:30:73] assign _schedule_WIRE_38_valid = _schedule_WIRE_47; // @[Mux.scala:30:73] wire _schedule_WIRE_54; // @[Mux.scala:30:73] assign schedule_b_valid = _schedule_WIRE_48_valid; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_49_param; // @[Mux.scala:30:73] assign schedule_b_bits_param = _schedule_WIRE_48_bits_param; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_49_tag; // @[Mux.scala:30:73] assign schedule_b_bits_tag = _schedule_WIRE_48_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_49_set; // @[Mux.scala:30:73] assign schedule_b_bits_set = _schedule_WIRE_48_bits_set; // @[Mux.scala:30:73] wire _schedule_WIRE_49_clients; // @[Mux.scala:30:73] assign schedule_b_bits_clients = _schedule_WIRE_48_bits_clients; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_53; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_param = _schedule_WIRE_49_param; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_52; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_tag = _schedule_WIRE_49_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_51; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_set = _schedule_WIRE_49_set; // @[Mux.scala:30:73] wire _schedule_WIRE_50; // @[Mux.scala:30:73] assign _schedule_WIRE_48_bits_clients = _schedule_WIRE_49_clients; // @[Mux.scala:30:73] wire _schedule_T_840 = _schedule_T & _mshrs_0_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_841 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_842 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_843 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_844 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_845 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_846 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_847 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_848 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_849 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_850 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_851 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_bits_clients; // @[Mux.scala:30:73, :32:36] wire _schedule_T_852 = _schedule_T_840 | _schedule_T_841; // @[Mux.scala:30:73] wire _schedule_T_853 = _schedule_T_852 | _schedule_T_842; // @[Mux.scala:30:73] wire _schedule_T_854 = _schedule_T_853 | _schedule_T_843; // @[Mux.scala:30:73] wire _schedule_T_855 = _schedule_T_854 | _schedule_T_844; // @[Mux.scala:30:73] wire _schedule_T_856 = _schedule_T_855 | _schedule_T_845; // @[Mux.scala:30:73] wire _schedule_T_857 = _schedule_T_856 | _schedule_T_846; // @[Mux.scala:30:73] wire _schedule_T_858 = _schedule_T_857 | _schedule_T_847; // @[Mux.scala:30:73] wire _schedule_T_859 = _schedule_T_858 | _schedule_T_848; // @[Mux.scala:30:73] wire _schedule_T_860 = _schedule_T_859 | _schedule_T_849; // @[Mux.scala:30:73] wire _schedule_T_861 = _schedule_T_860 | _schedule_T_850; // @[Mux.scala:30:73] wire _schedule_T_862 = _schedule_T_861 | _schedule_T_851; // @[Mux.scala:30:73] assign _schedule_WIRE_50 = _schedule_T_862; // @[Mux.scala:30:73] assign _schedule_WIRE_49_clients = _schedule_WIRE_50; // @[Mux.scala:30:73] wire [10:0] _schedule_T_863 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_864 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_865 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_866 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_867 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_868 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_869 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_870 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_871 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_872 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_873 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_874 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_875 = _schedule_T_863 | _schedule_T_864; // @[Mux.scala:30:73] wire [10:0] _schedule_T_876 = _schedule_T_875 | _schedule_T_865; // @[Mux.scala:30:73] wire [10:0] _schedule_T_877 = _schedule_T_876 | _schedule_T_866; // @[Mux.scala:30:73] wire [10:0] _schedule_T_878 = _schedule_T_877 | _schedule_T_867; // @[Mux.scala:30:73] wire [10:0] _schedule_T_879 = _schedule_T_878 | _schedule_T_868; // @[Mux.scala:30:73] wire [10:0] _schedule_T_880 = _schedule_T_879 | _schedule_T_869; // @[Mux.scala:30:73] wire [10:0] _schedule_T_881 = _schedule_T_880 | _schedule_T_870; // @[Mux.scala:30:73] wire [10:0] _schedule_T_882 = _schedule_T_881 | _schedule_T_871; // @[Mux.scala:30:73] wire [10:0] _schedule_T_883 = _schedule_T_882 | _schedule_T_872; // @[Mux.scala:30:73] wire [10:0] _schedule_T_884 = _schedule_T_883 | _schedule_T_873; // @[Mux.scala:30:73] wire [10:0] _schedule_T_885 = _schedule_T_884 | _schedule_T_874; // @[Mux.scala:30:73] assign _schedule_WIRE_51 = _schedule_T_885; // @[Mux.scala:30:73] assign _schedule_WIRE_49_set = _schedule_WIRE_51; // @[Mux.scala:30:73] wire [8:0] _schedule_T_886 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_887 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_888 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_889 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_890 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_891 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_892 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_893 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_894 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_895 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_896 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_897 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_898 = _schedule_T_886 | _schedule_T_887; // @[Mux.scala:30:73] wire [8:0] _schedule_T_899 = _schedule_T_898 | _schedule_T_888; // @[Mux.scala:30:73] wire [8:0] _schedule_T_900 = _schedule_T_899 | _schedule_T_889; // @[Mux.scala:30:73] wire [8:0] _schedule_T_901 = _schedule_T_900 | _schedule_T_890; // @[Mux.scala:30:73] wire [8:0] _schedule_T_902 = _schedule_T_901 | _schedule_T_891; // @[Mux.scala:30:73] wire [8:0] _schedule_T_903 = _schedule_T_902 | _schedule_T_892; // @[Mux.scala:30:73] wire [8:0] _schedule_T_904 = _schedule_T_903 | _schedule_T_893; // @[Mux.scala:30:73] wire [8:0] _schedule_T_905 = _schedule_T_904 | _schedule_T_894; // @[Mux.scala:30:73] wire [8:0] _schedule_T_906 = _schedule_T_905 | _schedule_T_895; // @[Mux.scala:30:73] wire [8:0] _schedule_T_907 = _schedule_T_906 | _schedule_T_896; // @[Mux.scala:30:73] wire [8:0] _schedule_T_908 = _schedule_T_907 | _schedule_T_897; // @[Mux.scala:30:73] assign _schedule_WIRE_52 = _schedule_T_908; // @[Mux.scala:30:73] assign _schedule_WIRE_49_tag = _schedule_WIRE_52; // @[Mux.scala:30:73] wire [2:0] _schedule_T_909 = _schedule_T ? _mshrs_0_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_910 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_911 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_912 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_913 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_914 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_915 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_916 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_917 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_918 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_919 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_920 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_b_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_921 = _schedule_T_909 | _schedule_T_910; // @[Mux.scala:30:73] wire [2:0] _schedule_T_922 = _schedule_T_921 | _schedule_T_911; // @[Mux.scala:30:73] wire [2:0] _schedule_T_923 = _schedule_T_922 | _schedule_T_912; // @[Mux.scala:30:73] wire [2:0] _schedule_T_924 = _schedule_T_923 | _schedule_T_913; // @[Mux.scala:30:73] wire [2:0] _schedule_T_925 = _schedule_T_924 | _schedule_T_914; // @[Mux.scala:30:73] wire [2:0] _schedule_T_926 = _schedule_T_925 | _schedule_T_915; // @[Mux.scala:30:73] wire [2:0] _schedule_T_927 = _schedule_T_926 | _schedule_T_916; // @[Mux.scala:30:73] wire [2:0] _schedule_T_928 = _schedule_T_927 | _schedule_T_917; // @[Mux.scala:30:73] wire [2:0] _schedule_T_929 = _schedule_T_928 | _schedule_T_918; // @[Mux.scala:30:73] wire [2:0] _schedule_T_930 = _schedule_T_929 | _schedule_T_919; // @[Mux.scala:30:73] wire [2:0] _schedule_T_931 = _schedule_T_930 | _schedule_T_920; // @[Mux.scala:30:73] assign _schedule_WIRE_53 = _schedule_T_931; // @[Mux.scala:30:73] assign _schedule_WIRE_49_param = _schedule_WIRE_53; // @[Mux.scala:30:73] wire _schedule_T_932 = _schedule_T & _mshrs_0_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_933 = _schedule_T_1 & _mshrs_1_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_934 = _schedule_T_2 & _mshrs_2_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_935 = _schedule_T_3 & _mshrs_3_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_936 = _schedule_T_4 & _mshrs_4_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_937 = _schedule_T_5 & _mshrs_5_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_938 = _schedule_T_6 & _mshrs_6_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_939 = _schedule_T_7 & _mshrs_7_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_940 = _schedule_T_8 & _mshrs_8_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_941 = _schedule_T_9 & _mshrs_9_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_942 = _schedule_T_10 & _mshrs_10_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_943 = _schedule_T_11 & _mshrs_11_io_schedule_bits_b_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_944 = _schedule_T_932 | _schedule_T_933; // @[Mux.scala:30:73] wire _schedule_T_945 = _schedule_T_944 | _schedule_T_934; // @[Mux.scala:30:73] wire _schedule_T_946 = _schedule_T_945 | _schedule_T_935; // @[Mux.scala:30:73] wire _schedule_T_947 = _schedule_T_946 | _schedule_T_936; // @[Mux.scala:30:73] wire _schedule_T_948 = _schedule_T_947 | _schedule_T_937; // @[Mux.scala:30:73] wire _schedule_T_949 = _schedule_T_948 | _schedule_T_938; // @[Mux.scala:30:73] wire _schedule_T_950 = _schedule_T_949 | _schedule_T_939; // @[Mux.scala:30:73] wire _schedule_T_951 = _schedule_T_950 | _schedule_T_940; // @[Mux.scala:30:73] wire _schedule_T_952 = _schedule_T_951 | _schedule_T_941; // @[Mux.scala:30:73] wire _schedule_T_953 = _schedule_T_952 | _schedule_T_942; // @[Mux.scala:30:73] wire _schedule_T_954 = _schedule_T_953 | _schedule_T_943; // @[Mux.scala:30:73] assign _schedule_WIRE_54 = _schedule_T_954; // @[Mux.scala:30:73] assign _schedule_WIRE_48_valid = _schedule_WIRE_54; // @[Mux.scala:30:73] wire _schedule_WIRE_62; // @[Mux.scala:30:73] assign schedule_a_valid = _schedule_WIRE_55_valid; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_56_tag; // @[Mux.scala:30:73] assign schedule_a_bits_tag = _schedule_WIRE_55_bits_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_56_set; // @[Mux.scala:30:73] assign schedule_a_bits_set = _schedule_WIRE_55_bits_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_56_param; // @[Mux.scala:30:73] assign schedule_a_bits_param = _schedule_WIRE_55_bits_param; // @[Mux.scala:30:73] wire _schedule_WIRE_56_block; // @[Mux.scala:30:73] assign schedule_a_bits_block = _schedule_WIRE_55_bits_block; // @[Mux.scala:30:73] wire [8:0] _schedule_WIRE_61; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_tag = _schedule_WIRE_56_tag; // @[Mux.scala:30:73] wire [10:0] _schedule_WIRE_60; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_set = _schedule_WIRE_56_set; // @[Mux.scala:30:73] wire [2:0] _schedule_WIRE_59; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_param = _schedule_WIRE_56_param; // @[Mux.scala:30:73] wire _schedule_WIRE_57; // @[Mux.scala:30:73] assign _schedule_WIRE_55_bits_block = _schedule_WIRE_56_block; // @[Mux.scala:30:73] wire _schedule_T_955 = _schedule_T & _mshrs_0_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_956 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_957 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_958 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_959 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_960 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_961 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_962 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_963 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_964 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_965 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_966 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_bits_block; // @[Mux.scala:30:73, :32:36] wire _schedule_T_967 = _schedule_T_955 | _schedule_T_956; // @[Mux.scala:30:73] wire _schedule_T_968 = _schedule_T_967 | _schedule_T_957; // @[Mux.scala:30:73] wire _schedule_T_969 = _schedule_T_968 | _schedule_T_958; // @[Mux.scala:30:73] wire _schedule_T_970 = _schedule_T_969 | _schedule_T_959; // @[Mux.scala:30:73] wire _schedule_T_971 = _schedule_T_970 | _schedule_T_960; // @[Mux.scala:30:73] wire _schedule_T_972 = _schedule_T_971 | _schedule_T_961; // @[Mux.scala:30:73] wire _schedule_T_973 = _schedule_T_972 | _schedule_T_962; // @[Mux.scala:30:73] wire _schedule_T_974 = _schedule_T_973 | _schedule_T_963; // @[Mux.scala:30:73] wire _schedule_T_975 = _schedule_T_974 | _schedule_T_964; // @[Mux.scala:30:73] wire _schedule_T_976 = _schedule_T_975 | _schedule_T_965; // @[Mux.scala:30:73] wire _schedule_T_977 = _schedule_T_976 | _schedule_T_966; // @[Mux.scala:30:73] assign _schedule_WIRE_57 = _schedule_T_977; // @[Mux.scala:30:73] assign _schedule_WIRE_56_block = _schedule_WIRE_57; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1001 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1002 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1003 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1004 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1005 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1006 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1007 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1008 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1009 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1010 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1011 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1012 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_param : 3'h0; // @[Mux.scala:30:73, :32:36] wire [2:0] _schedule_T_1013 = _schedule_T_1001 | _schedule_T_1002; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1014 = _schedule_T_1013 | _schedule_T_1003; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1015 = _schedule_T_1014 | _schedule_T_1004; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1016 = _schedule_T_1015 | _schedule_T_1005; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1017 = _schedule_T_1016 | _schedule_T_1006; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1018 = _schedule_T_1017 | _schedule_T_1007; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1019 = _schedule_T_1018 | _schedule_T_1008; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1020 = _schedule_T_1019 | _schedule_T_1009; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1021 = _schedule_T_1020 | _schedule_T_1010; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1022 = _schedule_T_1021 | _schedule_T_1011; // @[Mux.scala:30:73] wire [2:0] _schedule_T_1023 = _schedule_T_1022 | _schedule_T_1012; // @[Mux.scala:30:73] assign _schedule_WIRE_59 = _schedule_T_1023; // @[Mux.scala:30:73] assign _schedule_WIRE_56_param = _schedule_WIRE_59; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1024 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1025 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1026 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1027 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1028 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1029 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1030 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1031 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1032 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1033 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1034 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1035 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _schedule_T_1036 = _schedule_T_1024 | _schedule_T_1025; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1037 = _schedule_T_1036 | _schedule_T_1026; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1038 = _schedule_T_1037 | _schedule_T_1027; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1039 = _schedule_T_1038 | _schedule_T_1028; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1040 = _schedule_T_1039 | _schedule_T_1029; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1041 = _schedule_T_1040 | _schedule_T_1030; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1042 = _schedule_T_1041 | _schedule_T_1031; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1043 = _schedule_T_1042 | _schedule_T_1032; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1044 = _schedule_T_1043 | _schedule_T_1033; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1045 = _schedule_T_1044 | _schedule_T_1034; // @[Mux.scala:30:73] wire [10:0] _schedule_T_1046 = _schedule_T_1045 | _schedule_T_1035; // @[Mux.scala:30:73] assign _schedule_WIRE_60 = _schedule_T_1046; // @[Mux.scala:30:73] assign _schedule_WIRE_56_set = _schedule_WIRE_60; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1047 = _schedule_T ? _mshrs_0_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1048 = _schedule_T_1 ? _mshrs_1_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1049 = _schedule_T_2 ? _mshrs_2_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1050 = _schedule_T_3 ? _mshrs_3_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1051 = _schedule_T_4 ? _mshrs_4_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1052 = _schedule_T_5 ? _mshrs_5_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1053 = _schedule_T_6 ? _mshrs_6_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1054 = _schedule_T_7 ? _mshrs_7_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1055 = _schedule_T_8 ? _mshrs_8_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1056 = _schedule_T_9 ? _mshrs_9_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1057 = _schedule_T_10 ? _mshrs_10_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1058 = _schedule_T_11 ? _mshrs_11_io_schedule_bits_a_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _schedule_T_1059 = _schedule_T_1047 | _schedule_T_1048; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1060 = _schedule_T_1059 | _schedule_T_1049; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1061 = _schedule_T_1060 | _schedule_T_1050; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1062 = _schedule_T_1061 | _schedule_T_1051; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1063 = _schedule_T_1062 | _schedule_T_1052; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1064 = _schedule_T_1063 | _schedule_T_1053; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1065 = _schedule_T_1064 | _schedule_T_1054; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1066 = _schedule_T_1065 | _schedule_T_1055; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1067 = _schedule_T_1066 | _schedule_T_1056; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1068 = _schedule_T_1067 | _schedule_T_1057; // @[Mux.scala:30:73] wire [8:0] _schedule_T_1069 = _schedule_T_1068 | _schedule_T_1058; // @[Mux.scala:30:73] assign _schedule_WIRE_61 = _schedule_T_1069; // @[Mux.scala:30:73] assign _schedule_WIRE_56_tag = _schedule_WIRE_61; // @[Mux.scala:30:73] wire _schedule_T_1070 = _schedule_T & _mshrs_0_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1071 = _schedule_T_1 & _mshrs_1_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1072 = _schedule_T_2 & _mshrs_2_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1073 = _schedule_T_3 & _mshrs_3_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1074 = _schedule_T_4 & _mshrs_4_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1075 = _schedule_T_5 & _mshrs_5_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1076 = _schedule_T_6 & _mshrs_6_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1077 = _schedule_T_7 & _mshrs_7_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1078 = _schedule_T_8 & _mshrs_8_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1079 = _schedule_T_9 & _mshrs_9_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1080 = _schedule_T_10 & _mshrs_10_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1081 = _schedule_T_11 & _mshrs_11_io_schedule_bits_a_valid; // @[Mux.scala:30:73, :32:36] wire _schedule_T_1082 = _schedule_T_1070 | _schedule_T_1071; // @[Mux.scala:30:73] wire _schedule_T_1083 = _schedule_T_1082 | _schedule_T_1072; // @[Mux.scala:30:73] wire _schedule_T_1084 = _schedule_T_1083 | _schedule_T_1073; // @[Mux.scala:30:73] wire _schedule_T_1085 = _schedule_T_1084 | _schedule_T_1074; // @[Mux.scala:30:73] wire _schedule_T_1086 = _schedule_T_1085 | _schedule_T_1075; // @[Mux.scala:30:73] wire _schedule_T_1087 = _schedule_T_1086 | _schedule_T_1076; // @[Mux.scala:30:73] wire _schedule_T_1088 = _schedule_T_1087 | _schedule_T_1077; // @[Mux.scala:30:73] wire _schedule_T_1089 = _schedule_T_1088 | _schedule_T_1078; // @[Mux.scala:30:73] wire _schedule_T_1090 = _schedule_T_1089 | _schedule_T_1079; // @[Mux.scala:30:73] wire _schedule_T_1091 = _schedule_T_1090 | _schedule_T_1080; // @[Mux.scala:30:73] wire _schedule_T_1092 = _schedule_T_1091 | _schedule_T_1081; // @[Mux.scala:30:73] assign _schedule_WIRE_62 = _schedule_T_1092; // @[Mux.scala:30:73] assign _schedule_WIRE_55_valid = _schedule_WIRE_62; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_12 = _scheduleTag_T ? _mshrs_0_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_13 = _scheduleTag_T_1 ? _mshrs_1_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_14 = _scheduleTag_T_2 ? _mshrs_2_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_15 = _scheduleTag_T_3 ? _mshrs_3_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_16 = _scheduleTag_T_4 ? _mshrs_4_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_17 = _scheduleTag_T_5 ? _mshrs_5_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_18 = _scheduleTag_T_6 ? _mshrs_6_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_19 = _scheduleTag_T_7 ? _mshrs_7_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_20 = _scheduleTag_T_8 ? _mshrs_8_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_21 = _scheduleTag_T_9 ? _mshrs_9_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_22 = _scheduleTag_T_10 ? _mshrs_10_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_23 = _scheduleTag_T_11 ? _mshrs_11_io_status_bits_tag : 9'h0; // @[Mux.scala:30:73, :32:36] wire [8:0] _scheduleTag_T_24 = _scheduleTag_T_12 | _scheduleTag_T_13; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_25 = _scheduleTag_T_24 | _scheduleTag_T_14; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_26 = _scheduleTag_T_25 | _scheduleTag_T_15; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_27 = _scheduleTag_T_26 | _scheduleTag_T_16; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_28 = _scheduleTag_T_27 | _scheduleTag_T_17; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_29 = _scheduleTag_T_28 | _scheduleTag_T_18; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_30 = _scheduleTag_T_29 | _scheduleTag_T_19; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_31 = _scheduleTag_T_30 | _scheduleTag_T_20; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_32 = _scheduleTag_T_31 | _scheduleTag_T_21; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_33 = _scheduleTag_T_32 | _scheduleTag_T_22; // @[Mux.scala:30:73] wire [8:0] _scheduleTag_T_34 = _scheduleTag_T_33 | _scheduleTag_T_23; // @[Mux.scala:30:73] wire [8:0] scheduleTag = _scheduleTag_T_34; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_12 = _scheduleSet_T ? _mshrs_0_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_13 = _scheduleSet_T_1 ? _mshrs_1_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_14 = _scheduleSet_T_2 ? _mshrs_2_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_15 = _scheduleSet_T_3 ? _mshrs_3_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_16 = _scheduleSet_T_4 ? _mshrs_4_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_17 = _scheduleSet_T_5 ? _mshrs_5_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_18 = _scheduleSet_T_6 ? _mshrs_6_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_19 = _scheduleSet_T_7 ? _mshrs_7_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_20 = _scheduleSet_T_8 ? _mshrs_8_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_21 = _scheduleSet_T_9 ? _mshrs_9_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_22 = _scheduleSet_T_10 ? _mshrs_10_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_23 = _scheduleSet_T_11 ? _mshrs_11_io_status_bits_set : 11'h0; // @[Mux.scala:30:73, :32:36] wire [10:0] _scheduleSet_T_24 = _scheduleSet_T_12 | _scheduleSet_T_13; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_25 = _scheduleSet_T_24 | _scheduleSet_T_14; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_26 = _scheduleSet_T_25 | _scheduleSet_T_15; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_27 = _scheduleSet_T_26 | _scheduleSet_T_16; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_28 = _scheduleSet_T_27 | _scheduleSet_T_17; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_29 = _scheduleSet_T_28 | _scheduleSet_T_18; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_30 = _scheduleSet_T_29 | _scheduleSet_T_19; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_31 = _scheduleSet_T_30 | _scheduleSet_T_20; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_32 = _scheduleSet_T_31 | _scheduleSet_T_21; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_33 = _scheduleSet_T_32 | _scheduleSet_T_22; // @[Mux.scala:30:73] wire [10:0] _scheduleSet_T_34 = _scheduleSet_T_33 | _scheduleSet_T_23; // @[Mux.scala:30:73] wire [10:0] scheduleSet = _scheduleSet_T_34; // @[Mux.scala:30:73] wire [10:0] _robin_filter_T = mshr_selectOH[11:1]; // @[package.scala:262:48] wire [11:0] _robin_filter_T_1 = {mshr_selectOH[11], mshr_selectOH[10:0] | _robin_filter_T}; // @[Mux.scala:32:36] wire [9:0] _robin_filter_T_2 = _robin_filter_T_1[11:2]; // @[package.scala:262:{43,48}] wire [11:0] _robin_filter_T_3 = {_robin_filter_T_1[11:10], _robin_filter_T_1[9:0] | _robin_filter_T_2}; // @[package.scala:262:{43,48}] wire [7:0] _robin_filter_T_4 = _robin_filter_T_3[11:4]; // @[package.scala:262:{43,48}] wire [11:0] _robin_filter_T_5 = {_robin_filter_T_3[11:8], _robin_filter_T_3[7:0] | _robin_filter_T_4}; // @[package.scala:262:{43,48}] wire [3:0] _robin_filter_T_6 = _robin_filter_T_5[11:8]; // @[package.scala:262:{43,48}] wire [11:0] _robin_filter_T_7 = {_robin_filter_T_5[11:4], _robin_filter_T_5[3:0] | _robin_filter_T_6}; // @[package.scala:262:{43,48}] wire [11:0] _robin_filter_T_8 = _robin_filter_T_7; // @[package.scala:262:43, :263:17] wire [11:0] _robin_filter_T_9 = ~_robin_filter_T_8; // @[package.scala:263:17] wire _schedule_c_bits_source_T = schedule_c_bits_opcode[1]; // @[Mux.scala:30:73] assign _schedule_c_bits_source_T_1 = _schedule_c_bits_source_T ? mshr_select : 4'h0; // @[OneHot.scala:32:10] assign schedule_c_bits_source = _schedule_c_bits_source_T_1; // @[Mux.scala:30:73] assign _nestedwb_set_T = select_c ? _mshrs_11_io_status_bits_set : _mshrs_10_io_status_bits_set; // @[Scheduler.scala:71:46, :153:32, :155:24] assign nestedwb_set = _nestedwb_set_T; // @[Scheduler.scala:75:22, :155:24] assign _nestedwb_tag_T = select_c ? _mshrs_11_io_status_bits_tag : _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :153:32, :156:24] assign nestedwb_tag = _nestedwb_tag_T; // @[Scheduler.scala:75:22, :156:24] wire _GEN = select_bc & _mshrs_10_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :154:32, :157:37] wire _nestedwb_b_toN_T; // @[Scheduler.scala:157:37] assign _nestedwb_b_toN_T = _GEN; // @[Scheduler.scala:157:37] wire _nestedwb_b_toB_T; // @[Scheduler.scala:158:37] assign _nestedwb_b_toB_T = _GEN; // @[Scheduler.scala:157:37, :158:37] assign _nestedwb_b_clr_dirty_T = _GEN; // @[Scheduler.scala:157:37, :159:37] wire _nestedwb_b_toN_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h0; // @[Scheduler.scala:71:46, :157:123] assign _nestedwb_b_toN_T_2 = _nestedwb_b_toN_T & _nestedwb_b_toN_T_1; // @[Scheduler.scala:157:{37,75,123}] assign nestedwb_b_toN = _nestedwb_b_toN_T_2; // @[Scheduler.scala:75:22, :157:75] wire _nestedwb_b_toB_T_1 = _mshrs_10_io_schedule_bits_dir_bits_data_state == 2'h1; // @[Scheduler.scala:71:46, :158:123] assign _nestedwb_b_toB_T_2 = _nestedwb_b_toB_T & _nestedwb_b_toB_T_1; // @[Scheduler.scala:158:{37,75,123}] assign nestedwb_b_toB = _nestedwb_b_toB_T_2; // @[Scheduler.scala:75:22, :158:75] assign nestedwb_b_clr_dirty = _nestedwb_b_clr_dirty_T; // @[Scheduler.scala:75:22, :159:37] wire _nestedwb_c_set_dirty_T = select_c & _mshrs_11_io_schedule_bits_dir_valid; // @[Scheduler.scala:71:46, :153:32, :160:37] assign _nestedwb_c_set_dirty_T_1 = _nestedwb_c_set_dirty_T & _mshrs_11_io_schedule_bits_dir_bits_data_dirty; // @[Scheduler.scala:71:46, :160:{37,75}] assign nestedwb_c_set_dirty = _nestedwb_c_set_dirty_T_1; // @[Scheduler.scala:75:22, :160:75] wire _request_ready_T_2; // @[Scheduler.scala:261:40] wire _request_valid_T_2; // @[Scheduler.scala:164:39] wire _request_bits_T_1_prio_0; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_7_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_8_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_9_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_10_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_11_prio_0 = request_bits_prio_0; // @[Scheduler.scala:163:21, :233:95] wire _request_bits_T_1_prio_2; // @[Scheduler.scala:165:22] wire _request_bits_T_1_control; // @[Scheduler.scala:165:22] wire _view__WIRE_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_7_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_8_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_9_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_10_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_11_prio_2 = request_bits_prio_2; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_opcode; // @[Scheduler.scala:165:22] wire _view__WIRE_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_1_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_2_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_3_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_4_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_5_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_6_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_7_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_8_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_9_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_10_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire _view__WIRE_11_control = request_bits_control; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_param; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_7_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_8_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_9_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_10_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_11_opcode = request_bits_opcode; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _request_bits_T_1_size; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_7_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_8_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_9_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_10_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_11_param = request_bits_param; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_source; // @[Scheduler.scala:165:22] wire [2:0] _view__WIRE_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_1_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_2_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_3_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_4_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_5_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_6_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_7_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_8_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_9_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_10_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [2:0] _view__WIRE_11_size = request_bits_size; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _request_bits_T_1_tag; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_7_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_8_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_9_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_10_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_11_source = request_bits_source; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_offset; // @[Scheduler.scala:165:22] wire [8:0] _view__WIRE_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_1_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_2_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_3_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_4_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_5_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_6_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_7_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_8_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_9_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_10_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [8:0] _view__WIRE_11_tag = request_bits_tag; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _request_bits_T_1_put; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_7_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_8_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_9_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_10_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_11_offset = request_bits_offset; // @[Scheduler.scala:163:21, :233:95] wire [10:0] _request_bits_T_1_set; // @[Scheduler.scala:165:22] wire [5:0] _view__WIRE_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_1_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_2_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_3_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_4_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_5_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_6_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_7_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_8_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_9_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_10_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [5:0] _view__WIRE_11_put = request_bits_put; // @[Scheduler.scala:163:21, :233:95] wire [10:0] request_bits_set; // @[Scheduler.scala:163:21] wire request_ready; // @[Scheduler.scala:163:21] wire request_valid; // @[Scheduler.scala:163:21] wire _request_valid_T = _sinkA_io_req_valid | _sinkX_io_req_valid; // @[Scheduler.scala:54:21, :58:21, :164:62] wire _request_valid_T_1 = _request_valid_T | _sinkC_io_req_valid; // @[Scheduler.scala:55:21, :164:{62,84}] assign _request_valid_T_2 = _directory_io_ready & _request_valid_T_1; // @[Scheduler.scala:68:25, :164:{39,84}] assign request_valid = _request_valid_T_2; // @[Scheduler.scala:163:21, :164:39] wire [2:0] _request_bits_T_opcode = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_opcode; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_param = _sinkX_io_req_valid ? 3'h0 : _sinkA_io_req_bits_param; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [2:0] _request_bits_T_size = _sinkX_io_req_valid ? 3'h6 : _sinkA_io_req_bits_size; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_source = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_source; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [8:0] _request_bits_T_tag = _sinkX_io_req_valid ? _sinkX_io_req_bits_tag : _sinkA_io_req_bits_tag; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_offset = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_offset; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [5:0] _request_bits_T_put = _sinkX_io_req_valid ? 6'h0 : _sinkA_io_req_bits_put; // @[Scheduler.scala:54:21, :58:21, :166:22] wire [10:0] _request_bits_T_set = _sinkX_io_req_valid ? _sinkX_io_req_bits_set : _sinkA_io_req_bits_set; // @[Scheduler.scala:54:21, :58:21, :166:22] wire _request_bits_T_control; // @[Scheduler.scala:166:22] assign _request_bits_T_1_control = ~_sinkC_io_req_valid & _request_bits_T_control; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_opcode = _sinkC_io_req_valid ? _sinkC_io_req_bits_opcode : _request_bits_T_opcode; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_param = _sinkC_io_req_valid ? _sinkC_io_req_bits_param : _request_bits_T_param; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_size = _sinkC_io_req_valid ? _sinkC_io_req_bits_size : _request_bits_T_size; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_source = _sinkC_io_req_valid ? _sinkC_io_req_bits_source : _request_bits_T_source; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_tag = _sinkC_io_req_valid ? _sinkC_io_req_bits_tag : _request_bits_T_tag; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_offset = _sinkC_io_req_valid ? _sinkC_io_req_bits_offset : _request_bits_T_offset; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_put = _sinkC_io_req_valid ? _sinkC_io_req_bits_put : _request_bits_T_put; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_set = _sinkC_io_req_valid ? _sinkC_io_req_bits_set : _request_bits_T_set; // @[Scheduler.scala:55:21, :165:22, :166:22] assign _request_bits_T_1_prio_0 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22] assign request_bits_prio_0 = _request_bits_T_1_prio_0; // @[Scheduler.scala:163:21, :165:22] assign request_bits_prio_2 = _request_bits_T_1_prio_2; // @[Scheduler.scala:163:21, :165:22] assign request_bits_control = _request_bits_T_1_control; // @[Scheduler.scala:163:21, :165:22] assign request_bits_opcode = _request_bits_T_1_opcode; // @[Scheduler.scala:163:21, :165:22] assign request_bits_param = _request_bits_T_1_param; // @[Scheduler.scala:163:21, :165:22] assign request_bits_size = _request_bits_T_1_size; // @[Scheduler.scala:163:21, :165:22] assign request_bits_source = _request_bits_T_1_source; // @[Scheduler.scala:163:21, :165:22] assign request_bits_tag = _request_bits_T_1_tag; // @[Scheduler.scala:163:21, :165:22] assign request_bits_offset = _request_bits_T_1_offset; // @[Scheduler.scala:163:21, :165:22] assign request_bits_put = _request_bits_T_1_put; // @[Scheduler.scala:163:21, :165:22] assign request_bits_set = _request_bits_T_1_set; // @[Scheduler.scala:163:21, :165:22] wire _GEN_0 = _directory_io_ready & request_ready; // @[Scheduler.scala:68:25, :163:21, :167:44] wire _sinkC_io_req_ready_T; // @[Scheduler.scala:167:44] assign _sinkC_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44] wire _sinkX_io_req_ready_T; // @[Scheduler.scala:168:44] assign _sinkX_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :168:44] wire _sinkA_io_req_ready_T; // @[Scheduler.scala:169:44] assign _sinkA_io_req_ready_T = _GEN_0; // @[Scheduler.scala:167:44, :169:44] wire _sinkX_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :168:64] wire _sinkX_io_req_ready_T_2 = _sinkX_io_req_ready_T & _sinkX_io_req_ready_T_1; // @[Scheduler.scala:168:{44,61,64}] wire _sinkA_io_req_ready_T_1 = ~_sinkC_io_req_valid; // @[Scheduler.scala:55:21, :165:22, :169:64] wire _sinkA_io_req_ready_T_2 = _sinkA_io_req_ready_T & _sinkA_io_req_ready_T_1; // @[Scheduler.scala:169:{44,61,64}] wire _sinkA_io_req_ready_T_3 = ~_sinkX_io_req_valid; // @[Scheduler.scala:58:21, :169:87] wire _sinkA_io_req_ready_T_4 = _sinkA_io_req_ready_T_2 & _sinkA_io_req_ready_T_3; // @[Scheduler.scala:169:{61,84,87}] wire _setMatches_T = _mshrs_0_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_1 = _mshrs_0_io_status_valid & _setMatches_T; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_2 = _mshrs_1_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_3 = _mshrs_1_io_status_valid & _setMatches_T_2; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_4 = _mshrs_2_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_5 = _mshrs_2_io_status_valid & _setMatches_T_4; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_6 = _mshrs_3_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_7 = _mshrs_3_io_status_valid & _setMatches_T_6; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_8 = _mshrs_4_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_9 = _mshrs_4_io_status_valid & _setMatches_T_8; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_10 = _mshrs_5_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_11 = _mshrs_5_io_status_valid & _setMatches_T_10; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_12 = _mshrs_6_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_13 = _mshrs_6_io_status_valid & _setMatches_T_12; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_14 = _mshrs_7_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_15 = _mshrs_7_io_status_valid & _setMatches_T_14; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_16 = _mshrs_8_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_17 = _mshrs_8_io_status_valid & _setMatches_T_16; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_18 = _mshrs_9_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_19 = _mshrs_9_io_status_valid & _setMatches_T_18; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_20 = _mshrs_10_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_21 = _mshrs_10_io_status_valid & _setMatches_T_20; // @[Scheduler.scala:71:46, :172:{59,83}] wire _setMatches_T_22 = _mshrs_11_io_status_bits_set == request_bits_set; // @[Scheduler.scala:71:46, :163:21, :172:83] wire _setMatches_T_23 = _mshrs_11_io_status_valid & _setMatches_T_22; // @[Scheduler.scala:71:46, :172:{59,83}] wire [1:0] setMatches_lo_lo_hi = {_setMatches_T_5, _setMatches_T_3}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_lo_lo = {setMatches_lo_lo_hi, _setMatches_T_1}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_lo_hi_hi = {_setMatches_T_11, _setMatches_T_9}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_lo_hi = {setMatches_lo_hi_hi, _setMatches_T_7}; // @[Scheduler.scala:172:{23,59}] wire [5:0] setMatches_lo = {setMatches_lo_hi, setMatches_lo_lo}; // @[Scheduler.scala:172:23] wire [1:0] setMatches_hi_lo_hi = {_setMatches_T_17, _setMatches_T_15}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_hi_lo = {setMatches_hi_lo_hi, _setMatches_T_13}; // @[Scheduler.scala:172:{23,59}] wire [1:0] setMatches_hi_hi_hi = {_setMatches_T_23, _setMatches_T_21}; // @[Scheduler.scala:172:{23,59}] wire [2:0] setMatches_hi_hi = {setMatches_hi_hi_hi, _setMatches_T_19}; // @[Scheduler.scala:172:{23,59}] wire [5:0] setMatches_hi = {setMatches_hi_hi, setMatches_hi_lo}; // @[Scheduler.scala:172:23] wire [11:0] setMatches = {setMatches_hi, setMatches_lo}; // @[Scheduler.scala:172:23] wire _alloc_T = |setMatches; // @[Scheduler.scala:172:23, :173:27] wire alloc = ~_alloc_T; // @[Scheduler.scala:173:{15,27}] wire _blockB_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockC_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestB_T = setMatches[0]; // @[Mux.scala:32:36] wire _nestC_T = setMatches[0]; // @[Mux.scala:32:36] wire _blockB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestB_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _nestC_T_1 = setMatches[1]; // @[Mux.scala:32:36] wire _blockB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestB_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _nestC_T_2 = setMatches[2]; // @[Mux.scala:32:36] wire _blockB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestB_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _nestC_T_3 = setMatches[3]; // @[Mux.scala:32:36] wire _blockB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestB_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _nestC_T_4 = setMatches[4]; // @[Mux.scala:32:36] wire _blockB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestB_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _nestC_T_5 = setMatches[5]; // @[Mux.scala:32:36] wire _blockB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestB_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _nestC_T_6 = setMatches[6]; // @[Mux.scala:32:36] wire _blockB_T_7 = setMatches[7]; // @[Mux.scala:32:36] wire _blockC_T_7 = setMatches[7]; // @[Mux.scala:32:36] wire _nestB_T_7 = setMatches[7]; // @[Mux.scala:32:36] wire _nestC_T_7 = setMatches[7]; // @[Mux.scala:32:36] wire _blockB_T_8 = setMatches[8]; // @[Mux.scala:32:36] wire _blockC_T_8 = setMatches[8]; // @[Mux.scala:32:36] wire _nestB_T_8 = setMatches[8]; // @[Mux.scala:32:36] wire _nestC_T_8 = setMatches[8]; // @[Mux.scala:32:36] wire _blockB_T_9 = setMatches[9]; // @[Mux.scala:32:36] wire _blockC_T_9 = setMatches[9]; // @[Mux.scala:32:36] wire _nestB_T_9 = setMatches[9]; // @[Mux.scala:32:36] wire _nestC_T_9 = setMatches[9]; // @[Mux.scala:32:36] wire _blockB_T_10 = setMatches[10]; // @[Mux.scala:32:36] wire _blockC_T_10 = setMatches[10]; // @[Mux.scala:32:36] wire _nestB_T_10 = setMatches[10]; // @[Mux.scala:32:36] wire _nestC_T_10 = setMatches[10]; // @[Mux.scala:32:36] wire _blockB_T_11 = setMatches[11]; // @[Mux.scala:32:36] wire _blockC_T_11 = setMatches[11]; // @[Mux.scala:32:36] wire _nestB_T_11 = setMatches[11]; // @[Mux.scala:32:36] wire _nestC_T_11 = setMatches[11]; // @[Mux.scala:32:36] wire _blockB_T_12 = _blockB_T & _mshrs_0_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_13 = _blockB_T_1 & _mshrs_1_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_14 = _blockB_T_2 & _mshrs_2_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_15 = _blockB_T_3 & _mshrs_3_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_16 = _blockB_T_4 & _mshrs_4_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_17 = _blockB_T_5 & _mshrs_5_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_18 = _blockB_T_6 & _mshrs_6_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_19 = _blockB_T_7 & _mshrs_7_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_20 = _blockB_T_8 & _mshrs_8_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_21 = _blockB_T_9 & _mshrs_9_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_22 = _blockB_T_10 & _mshrs_10_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_23 = _blockB_T_11 & _mshrs_11_io_status_bits_blockB; // @[Mux.scala:30:73, :32:36] wire _blockB_T_24 = _blockB_T_12 | _blockB_T_13; // @[Mux.scala:30:73] wire _blockB_T_25 = _blockB_T_24 | _blockB_T_14; // @[Mux.scala:30:73] wire _blockB_T_26 = _blockB_T_25 | _blockB_T_15; // @[Mux.scala:30:73] wire _blockB_T_27 = _blockB_T_26 | _blockB_T_16; // @[Mux.scala:30:73] wire _blockB_T_28 = _blockB_T_27 | _blockB_T_17; // @[Mux.scala:30:73] wire _blockB_T_29 = _blockB_T_28 | _blockB_T_18; // @[Mux.scala:30:73] wire _blockB_T_30 = _blockB_T_29 | _blockB_T_19; // @[Mux.scala:30:73] wire _blockB_T_31 = _blockB_T_30 | _blockB_T_20; // @[Mux.scala:30:73] wire _blockB_T_32 = _blockB_T_31 | _blockB_T_21; // @[Mux.scala:30:73] wire _blockB_T_33 = _blockB_T_32 | _blockB_T_22; // @[Mux.scala:30:73] wire _blockB_T_34 = _blockB_T_33 | _blockB_T_23; // @[Mux.scala:30:73] wire _blockB_WIRE = _blockB_T_34; // @[Mux.scala:30:73] wire _blockC_T_12 = _blockC_T & _mshrs_0_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_13 = _blockC_T_1 & _mshrs_1_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_14 = _blockC_T_2 & _mshrs_2_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_15 = _blockC_T_3 & _mshrs_3_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_16 = _blockC_T_4 & _mshrs_4_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_17 = _blockC_T_5 & _mshrs_5_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_18 = _blockC_T_6 & _mshrs_6_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_19 = _blockC_T_7 & _mshrs_7_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_20 = _blockC_T_8 & _mshrs_8_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_21 = _blockC_T_9 & _mshrs_9_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_22 = _blockC_T_10 & _mshrs_10_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_23 = _blockC_T_11 & _mshrs_11_io_status_bits_blockC; // @[Mux.scala:30:73, :32:36] wire _blockC_T_24 = _blockC_T_12 | _blockC_T_13; // @[Mux.scala:30:73] wire _blockC_T_25 = _blockC_T_24 | _blockC_T_14; // @[Mux.scala:30:73] wire _blockC_T_26 = _blockC_T_25 | _blockC_T_15; // @[Mux.scala:30:73] wire _blockC_T_27 = _blockC_T_26 | _blockC_T_16; // @[Mux.scala:30:73] wire _blockC_T_28 = _blockC_T_27 | _blockC_T_17; // @[Mux.scala:30:73] wire _blockC_T_29 = _blockC_T_28 | _blockC_T_18; // @[Mux.scala:30:73] wire _blockC_T_30 = _blockC_T_29 | _blockC_T_19; // @[Mux.scala:30:73] wire _blockC_T_31 = _blockC_T_30 | _blockC_T_20; // @[Mux.scala:30:73] wire _blockC_T_32 = _blockC_T_31 | _blockC_T_21; // @[Mux.scala:30:73] wire _blockC_T_33 = _blockC_T_32 | _blockC_T_22; // @[Mux.scala:30:73] wire _blockC_T_34 = _blockC_T_33 | _blockC_T_23; // @[Mux.scala:30:73] wire _blockC_WIRE = _blockC_T_34; // @[Mux.scala:30:73] wire blockC = _blockC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _nestB_T_12 = _nestB_T & _mshrs_0_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_13 = _nestB_T_1 & _mshrs_1_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_14 = _nestB_T_2 & _mshrs_2_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_15 = _nestB_T_3 & _mshrs_3_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_16 = _nestB_T_4 & _mshrs_4_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_17 = _nestB_T_5 & _mshrs_5_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_18 = _nestB_T_6 & _mshrs_6_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_19 = _nestB_T_7 & _mshrs_7_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_20 = _nestB_T_8 & _mshrs_8_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_21 = _nestB_T_9 & _mshrs_9_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_22 = _nestB_T_10 & _mshrs_10_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_23 = _nestB_T_11 & _mshrs_11_io_status_bits_nestB; // @[Mux.scala:30:73, :32:36] wire _nestB_T_24 = _nestB_T_12 | _nestB_T_13; // @[Mux.scala:30:73] wire _nestB_T_25 = _nestB_T_24 | _nestB_T_14; // @[Mux.scala:30:73] wire _nestB_T_26 = _nestB_T_25 | _nestB_T_15; // @[Mux.scala:30:73] wire _nestB_T_27 = _nestB_T_26 | _nestB_T_16; // @[Mux.scala:30:73] wire _nestB_T_28 = _nestB_T_27 | _nestB_T_17; // @[Mux.scala:30:73] wire _nestB_T_29 = _nestB_T_28 | _nestB_T_18; // @[Mux.scala:30:73] wire _nestB_T_30 = _nestB_T_29 | _nestB_T_19; // @[Mux.scala:30:73] wire _nestB_T_31 = _nestB_T_30 | _nestB_T_20; // @[Mux.scala:30:73] wire _nestB_T_32 = _nestB_T_31 | _nestB_T_21; // @[Mux.scala:30:73] wire _nestB_T_33 = _nestB_T_32 | _nestB_T_22; // @[Mux.scala:30:73] wire _nestB_T_34 = _nestB_T_33 | _nestB_T_23; // @[Mux.scala:30:73] wire _nestB_WIRE = _nestB_T_34; // @[Mux.scala:30:73] wire _nestC_T_12 = _nestC_T & _mshrs_0_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_13 = _nestC_T_1 & _mshrs_1_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_14 = _nestC_T_2 & _mshrs_2_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_15 = _nestC_T_3 & _mshrs_3_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_16 = _nestC_T_4 & _mshrs_4_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_17 = _nestC_T_5 & _mshrs_5_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_18 = _nestC_T_6 & _mshrs_6_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_19 = _nestC_T_7 & _mshrs_7_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_20 = _nestC_T_8 & _mshrs_8_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_21 = _nestC_T_9 & _mshrs_9_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_22 = _nestC_T_10 & _mshrs_10_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_23 = _nestC_T_11 & _mshrs_11_io_status_bits_nestC; // @[Mux.scala:30:73, :32:36] wire _nestC_T_24 = _nestC_T_12 | _nestC_T_13; // @[Mux.scala:30:73] wire _nestC_T_25 = _nestC_T_24 | _nestC_T_14; // @[Mux.scala:30:73] wire _nestC_T_26 = _nestC_T_25 | _nestC_T_15; // @[Mux.scala:30:73] wire _nestC_T_27 = _nestC_T_26 | _nestC_T_16; // @[Mux.scala:30:73] wire _nestC_T_28 = _nestC_T_27 | _nestC_T_17; // @[Mux.scala:30:73] wire _nestC_T_29 = _nestC_T_28 | _nestC_T_18; // @[Mux.scala:30:73] wire _nestC_T_30 = _nestC_T_29 | _nestC_T_19; // @[Mux.scala:30:73] wire _nestC_T_31 = _nestC_T_30 | _nestC_T_20; // @[Mux.scala:30:73] wire _nestC_T_32 = _nestC_T_31 | _nestC_T_21; // @[Mux.scala:30:73] wire _nestC_T_33 = _nestC_T_32 | _nestC_T_22; // @[Mux.scala:30:73] wire _nestC_T_34 = _nestC_T_33 | _nestC_T_23; // @[Mux.scala:30:73] wire _nestC_WIRE = _nestC_T_34; // @[Mux.scala:30:73] wire nestC = _nestC_WIRE & request_bits_prio_2; // @[Mux.scala:30:73] wire _prioFilter_T = ~request_bits_prio_0; // @[Scheduler.scala:163:21, :182:46] wire [1:0] prioFilter_hi = {request_bits_prio_2, _prioFilter_T}; // @[Scheduler.scala:163:21, :182:{23,46}] wire [11:0] prioFilter = {prioFilter_hi, 10'h3FF}; // @[Scheduler.scala:182:23] wire [11:0] lowerMatches = setMatches & prioFilter; // @[Scheduler.scala:172:23, :182:23, :183:33] wire _queue_T = |lowerMatches; // @[Scheduler.scala:183:33, :185:28] wire _queue_T_2 = _queue_T; // @[Scheduler.scala:185:{28,32}] wire _queue_T_3 = ~nestC; // @[Scheduler.scala:180:70, :185:45] wire _queue_T_4 = _queue_T_2 & _queue_T_3; // @[Scheduler.scala:185:{32,42,45}] wire _queue_T_6 = _queue_T_4; // @[Scheduler.scala:185:{42,52}] wire _queue_T_7 = ~blockC; // @[Scheduler.scala:176:70, :185:66] wire queue = _queue_T_6 & _queue_T_7; // @[Scheduler.scala:185:{52,63,66}] wire _T_12 = request_valid & queue; // @[Scheduler.scala:163:21, :185:63, :195:31] wire _bypass_T; // @[Scheduler.scala:213:30] assign _bypass_T = _T_12; // @[Scheduler.scala:195:31, :213:30] wire _bypass_T_1; // @[Scheduler.scala:231:32] assign _bypass_T_1 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_2; // @[Scheduler.scala:231:32] assign _bypass_T_2 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_3; // @[Scheduler.scala:231:32] assign _bypass_T_3 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_4; // @[Scheduler.scala:231:32] assign _bypass_T_4 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_5; // @[Scheduler.scala:231:32] assign _bypass_T_5 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_6; // @[Scheduler.scala:231:32] assign _bypass_T_6 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_7; // @[Scheduler.scala:231:32] assign _bypass_T_7 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_8; // @[Scheduler.scala:231:32] assign _bypass_T_8 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_9; // @[Scheduler.scala:231:32] assign _bypass_T_9 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_10; // @[Scheduler.scala:231:32] assign _bypass_T_10 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_11; // @[Scheduler.scala:231:32] assign _bypass_T_11 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _bypass_T_12; // @[Scheduler.scala:231:32] assign _bypass_T_12 = _T_12; // @[Scheduler.scala:195:31, :231:32] wire _requests_io_push_valid_T; // @[Scheduler.scala:270:43] assign _requests_io_push_valid_T = _T_12; // @[Scheduler.scala:195:31, :270:43] wire _lowerMatches1_T = lowerMatches[11]; // @[Scheduler.scala:183:33, :200:21] wire _lowerMatches1_T_2 = lowerMatches[10]; // @[Scheduler.scala:183:33, :201:21] wire [11:0] _lowerMatches1_T_4 = _lowerMatches1_T_2 ? 12'h400 : lowerMatches; // @[Scheduler.scala:183:33, :201:{8,21}] wire [11:0] lowerMatches1 = _lowerMatches1_T ? 12'h800 : _lowerMatches1_T_4; // @[Scheduler.scala:200:{8,21}, :201:8] wire [11:0] _requests_io_push_bits_index_T = lowerMatches1; // @[Scheduler.scala:200:8, :274:30] wire [23:0] _GEN_1 = {2{mshr_selectOH}}; // @[Scheduler.scala:121:70, :206:30] wire [23:0] selected_requests_hi; // @[Scheduler.scala:206:30] assign selected_requests_hi = _GEN_1; // @[Scheduler.scala:206:30] wire [23:0] pop_index_hi; // @[Scheduler.scala:241:31] assign pop_index_hi = _GEN_1; // @[Scheduler.scala:206:30, :241:31] wire [35:0] _selected_requests_T = {selected_requests_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :206:30] wire [35:0] selected_requests = _selected_requests_T & _requests_io_valid; // @[Scheduler.scala:70:24, :206:{30,76}] wire [11:0] _a_pop_T = selected_requests[11:0]; // @[Scheduler.scala:206:76, :207:32] wire a_pop = |_a_pop_T; // @[Scheduler.scala:207:{32,79}] wire [11:0] _b_pop_T = selected_requests[23:12]; // @[Scheduler.scala:206:76, :208:32] wire b_pop = |_b_pop_T; // @[Scheduler.scala:208:{32,79}] wire _bypassMatches_T_4 = b_pop; // @[Scheduler.scala:208:79, :211:76] wire [11:0] _c_pop_T = selected_requests[35:24]; // @[Scheduler.scala:206:76, :209:32] wire c_pop = |_c_pop_T; // @[Scheduler.scala:209:{32,79}] wire [11:0] _bypassMatches_T = mshr_selectOH & lowerMatches1; // @[Scheduler.scala:121:70, :200:8, :210:38] wire _bypassMatches_T_1 = |_bypassMatches_T; // @[Scheduler.scala:210:{38,55}] wire _bypassMatches_T_2 = c_pop | request_bits_prio_2; // @[Scheduler.scala:163:21, :209:79, :211:33] wire _bypassMatches_T_3 = ~c_pop; // @[Scheduler.scala:209:79, :211:58] wire _bypassMatches_T_5 = ~b_pop; // @[Scheduler.scala:208:79, :211:101] wire _bypassMatches_T_6 = ~a_pop; // @[Scheduler.scala:207:79, :211:109] wire _bypassMatches_T_7 = _bypassMatches_T_4 ? _bypassMatches_T_5 : _bypassMatches_T_6; // @[Scheduler.scala:211:{69,76,101,109}] wire _bypassMatches_T_8 = _bypassMatches_T_2 ? _bypassMatches_T_3 : _bypassMatches_T_7; // @[Scheduler.scala:211:{26,33,58,69}] wire bypassMatches = _bypassMatches_T_1 & _bypassMatches_T_8; // @[Scheduler.scala:210:{55,59}, :211:26] wire _may_pop_T = a_pop | b_pop; // @[Scheduler.scala:207:79, :208:79, :212:23] wire may_pop = _may_pop_T | c_pop; // @[Scheduler.scala:209:79, :212:{23,32}] wire bypass = _bypass_T & bypassMatches; // @[Scheduler.scala:210:59, :213:{30,39}] wire _will_reload_T = may_pop | bypass; // @[Scheduler.scala:212:32, :213:39, :214:49] wire will_reload = schedule_reload & _will_reload_T; // @[Mux.scala:30:73] wire _GEN_2 = schedule_reload & may_pop; // @[Mux.scala:30:73] wire _will_pop_T; // @[Scheduler.scala:215:34] assign _will_pop_T = _GEN_2; // @[Scheduler.scala:215:34] wire _mshr_uses_directory_assuming_no_bypass_T; // @[Scheduler.scala:247:64] assign _mshr_uses_directory_assuming_no_bypass_T = _GEN_2; // @[Scheduler.scala:215:34, :247:64] wire _will_pop_T_1 = ~bypass; // @[Scheduler.scala:213:39, :215:48] wire will_pop = _will_pop_T & _will_pop_T_1; // @[Scheduler.scala:215:{34,45,48}] wire a_pop_1 = _requests_io_valid[0]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_1 = _requests_io_valid[12]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_12 = b_pop_1; // @[Scheduler.scala:226:34, :229:78] wire c_pop_1 = _requests_io_valid[24]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_9 = lowerMatches1[0]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_10 = c_pop_1 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_11 = ~c_pop_1; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_13 = ~b_pop_1; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_14 = ~a_pop_1; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_15 = _bypassMatches_T_12 ? _bypassMatches_T_13 : _bypassMatches_T_14; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_16 = _bypassMatches_T_10 ? _bypassMatches_T_11 : _bypassMatches_T_15; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_1 = _bypassMatches_T_9 & _bypassMatches_T_16; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_1 = a_pop_1 | b_pop_1; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_1 = _may_pop_T_1 | c_pop_1; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_1 = _bypass_T_1 & bypassMatches_1; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_1 = may_pop_1 | bypass_1; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_1 = _mshrs_0_io_schedule_bits_reload & _will_reload_T_1; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_prio_0 = bypass_1 ? _view__WIRE_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_prio_1 = ~bypass_1 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_prio_2 = bypass_1 ? _view__WIRE_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_control = bypass_1 ? _view__WIRE_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_opcode = bypass_1 ? _view__WIRE_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_param = bypass_1 ? _view__WIRE_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_size = bypass_1 ? _view__WIRE_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_source = bypass_1 ? _view__WIRE_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_tag = bypass_1 ? _view__WIRE_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_offset = bypass_1 ? _view__WIRE_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_put = bypass_1 ? _view__WIRE_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_0_io_allocate_bits_repeat_T = mshrs_0_io_allocate_bits_tag == _mshrs_0_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_0_io_allocate_valid_T = sel & will_reload_1; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_2 = _requests_io_valid[1]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_2 = _requests_io_valid[13]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_20 = b_pop_2; // @[Scheduler.scala:226:34, :229:78] wire c_pop_2 = _requests_io_valid[25]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_17 = lowerMatches1[1]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_18 = c_pop_2 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_19 = ~c_pop_2; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_21 = ~b_pop_2; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_22 = ~a_pop_2; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_23 = _bypassMatches_T_20 ? _bypassMatches_T_21 : _bypassMatches_T_22; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_24 = _bypassMatches_T_18 ? _bypassMatches_T_19 : _bypassMatches_T_23; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_2 = _bypassMatches_T_17 & _bypassMatches_T_24; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_2 = a_pop_2 | b_pop_2; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_2 = _may_pop_T_2 | c_pop_2; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_2 = _bypass_T_2 & bypassMatches_2; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_2 = may_pop_2 | bypass_2; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_2 = _mshrs_1_io_schedule_bits_reload & _will_reload_T_2; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_1_prio_0 = bypass_2 ? _view__WIRE_1_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_prio_1 = ~bypass_2 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_1_prio_2 = bypass_2 ? _view__WIRE_1_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_1_control = bypass_2 ? _view__WIRE_1_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_opcode = bypass_2 ? _view__WIRE_1_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_param = bypass_2 ? _view__WIRE_1_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_1_size = bypass_2 ? _view__WIRE_1_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_source = bypass_2 ? _view__WIRE_1_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_1_tag = bypass_2 ? _view__WIRE_1_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_offset = bypass_2 ? _view__WIRE_1_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_1_put = bypass_2 ? _view__WIRE_1_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_1_io_allocate_bits_repeat_T = mshrs_1_io_allocate_bits_tag == _mshrs_1_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_1_io_allocate_valid_T = sel_1 & will_reload_2; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_3 = _requests_io_valid[2]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_3 = _requests_io_valid[14]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_28 = b_pop_3; // @[Scheduler.scala:226:34, :229:78] wire c_pop_3 = _requests_io_valid[26]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_25 = lowerMatches1[2]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_26 = c_pop_3 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_27 = ~c_pop_3; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_29 = ~b_pop_3; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_30 = ~a_pop_3; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_31 = _bypassMatches_T_28 ? _bypassMatches_T_29 : _bypassMatches_T_30; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_32 = _bypassMatches_T_26 ? _bypassMatches_T_27 : _bypassMatches_T_31; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_3 = _bypassMatches_T_25 & _bypassMatches_T_32; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_3 = a_pop_3 | b_pop_3; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_3 = _may_pop_T_3 | c_pop_3; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_3 = _bypass_T_3 & bypassMatches_3; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_3 = may_pop_3 | bypass_3; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_3 = _mshrs_2_io_schedule_bits_reload & _will_reload_T_3; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_2_prio_0 = bypass_3 ? _view__WIRE_2_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_prio_1 = ~bypass_3 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_2_prio_2 = bypass_3 ? _view__WIRE_2_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_2_control = bypass_3 ? _view__WIRE_2_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_opcode = bypass_3 ? _view__WIRE_2_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_param = bypass_3 ? _view__WIRE_2_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_2_size = bypass_3 ? _view__WIRE_2_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_source = bypass_3 ? _view__WIRE_2_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_2_tag = bypass_3 ? _view__WIRE_2_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_offset = bypass_3 ? _view__WIRE_2_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_2_put = bypass_3 ? _view__WIRE_2_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_2_io_allocate_bits_repeat_T = mshrs_2_io_allocate_bits_tag == _mshrs_2_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_2_io_allocate_valid_T = sel_2 & will_reload_3; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_4 = _requests_io_valid[3]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_4 = _requests_io_valid[15]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_36 = b_pop_4; // @[Scheduler.scala:226:34, :229:78] wire c_pop_4 = _requests_io_valid[27]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_33 = lowerMatches1[3]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_34 = c_pop_4 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_35 = ~c_pop_4; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_37 = ~b_pop_4; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_38 = ~a_pop_4; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_39 = _bypassMatches_T_36 ? _bypassMatches_T_37 : _bypassMatches_T_38; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_40 = _bypassMatches_T_34 ? _bypassMatches_T_35 : _bypassMatches_T_39; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_4 = _bypassMatches_T_33 & _bypassMatches_T_40; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_4 = a_pop_4 | b_pop_4; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_4 = _may_pop_T_4 | c_pop_4; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_4 = _bypass_T_4 & bypassMatches_4; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_4 = may_pop_4 | bypass_4; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_4 = _mshrs_3_io_schedule_bits_reload & _will_reload_T_4; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_3_prio_0 = bypass_4 ? _view__WIRE_3_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_prio_1 = ~bypass_4 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_3_prio_2 = bypass_4 ? _view__WIRE_3_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_3_control = bypass_4 ? _view__WIRE_3_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_opcode = bypass_4 ? _view__WIRE_3_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_param = bypass_4 ? _view__WIRE_3_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_3_size = bypass_4 ? _view__WIRE_3_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_source = bypass_4 ? _view__WIRE_3_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_3_tag = bypass_4 ? _view__WIRE_3_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_offset = bypass_4 ? _view__WIRE_3_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_3_put = bypass_4 ? _view__WIRE_3_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_3_io_allocate_bits_repeat_T = mshrs_3_io_allocate_bits_tag == _mshrs_3_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_3_io_allocate_valid_T = sel_3 & will_reload_4; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_5 = _requests_io_valid[4]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_5 = _requests_io_valid[16]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_44 = b_pop_5; // @[Scheduler.scala:226:34, :229:78] wire c_pop_5 = _requests_io_valid[28]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_41 = lowerMatches1[4]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_42 = c_pop_5 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_43 = ~c_pop_5; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_45 = ~b_pop_5; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_46 = ~a_pop_5; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_47 = _bypassMatches_T_44 ? _bypassMatches_T_45 : _bypassMatches_T_46; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_48 = _bypassMatches_T_42 ? _bypassMatches_T_43 : _bypassMatches_T_47; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_5 = _bypassMatches_T_41 & _bypassMatches_T_48; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_5 = a_pop_5 | b_pop_5; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_5 = _may_pop_T_5 | c_pop_5; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_5 = _bypass_T_5 & bypassMatches_5; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_5 = may_pop_5 | bypass_5; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_5 = _mshrs_4_io_schedule_bits_reload & _will_reload_T_5; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_4_prio_0 = bypass_5 ? _view__WIRE_4_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_prio_1 = ~bypass_5 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_4_prio_2 = bypass_5 ? _view__WIRE_4_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_4_control = bypass_5 ? _view__WIRE_4_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_opcode = bypass_5 ? _view__WIRE_4_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_param = bypass_5 ? _view__WIRE_4_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_4_size = bypass_5 ? _view__WIRE_4_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_source = bypass_5 ? _view__WIRE_4_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_4_tag = bypass_5 ? _view__WIRE_4_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_offset = bypass_5 ? _view__WIRE_4_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_4_put = bypass_5 ? _view__WIRE_4_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_4_io_allocate_bits_repeat_T = mshrs_4_io_allocate_bits_tag == _mshrs_4_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_4_io_allocate_valid_T = sel_4 & will_reload_5; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_6 = _requests_io_valid[5]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_6 = _requests_io_valid[17]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_52 = b_pop_6; // @[Scheduler.scala:226:34, :229:78] wire c_pop_6 = _requests_io_valid[29]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_49 = lowerMatches1[5]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_50 = c_pop_6 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_51 = ~c_pop_6; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_53 = ~b_pop_6; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_54 = ~a_pop_6; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_55 = _bypassMatches_T_52 ? _bypassMatches_T_53 : _bypassMatches_T_54; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_56 = _bypassMatches_T_50 ? _bypassMatches_T_51 : _bypassMatches_T_55; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_6 = _bypassMatches_T_49 & _bypassMatches_T_56; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_6 = a_pop_6 | b_pop_6; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_6 = _may_pop_T_6 | c_pop_6; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_6 = _bypass_T_6 & bypassMatches_6; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_6 = may_pop_6 | bypass_6; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_6 = _mshrs_5_io_schedule_bits_reload & _will_reload_T_6; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_5_prio_0 = bypass_6 ? _view__WIRE_5_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_prio_1 = ~bypass_6 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_5_prio_2 = bypass_6 ? _view__WIRE_5_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_5_control = bypass_6 ? _view__WIRE_5_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_opcode = bypass_6 ? _view__WIRE_5_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_param = bypass_6 ? _view__WIRE_5_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_5_size = bypass_6 ? _view__WIRE_5_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_source = bypass_6 ? _view__WIRE_5_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_5_tag = bypass_6 ? _view__WIRE_5_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_offset = bypass_6 ? _view__WIRE_5_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_5_put = bypass_6 ? _view__WIRE_5_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_5_io_allocate_bits_repeat_T = mshrs_5_io_allocate_bits_tag == _mshrs_5_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_5_io_allocate_valid_T = sel_5 & will_reload_6; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_7 = _requests_io_valid[6]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_7 = _requests_io_valid[18]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_60 = b_pop_7; // @[Scheduler.scala:226:34, :229:78] wire c_pop_7 = _requests_io_valid[30]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_57 = lowerMatches1[6]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_58 = c_pop_7 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_59 = ~c_pop_7; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_61 = ~b_pop_7; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_62 = ~a_pop_7; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_63 = _bypassMatches_T_60 ? _bypassMatches_T_61 : _bypassMatches_T_62; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_64 = _bypassMatches_T_58 ? _bypassMatches_T_59 : _bypassMatches_T_63; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_7 = _bypassMatches_T_57 & _bypassMatches_T_64; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_7 = a_pop_7 | b_pop_7; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_7 = _may_pop_T_7 | c_pop_7; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_7 = _bypass_T_7 & bypassMatches_7; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_7 = may_pop_7 | bypass_7; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_7 = _mshrs_6_io_schedule_bits_reload & _will_reload_T_7; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_6_prio_0 = bypass_7 ? _view__WIRE_6_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_prio_1 = ~bypass_7 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_6_prio_2 = bypass_7 ? _view__WIRE_6_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_6_control = bypass_7 ? _view__WIRE_6_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_opcode = bypass_7 ? _view__WIRE_6_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_param = bypass_7 ? _view__WIRE_6_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_6_size = bypass_7 ? _view__WIRE_6_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_source = bypass_7 ? _view__WIRE_6_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_6_tag = bypass_7 ? _view__WIRE_6_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_offset = bypass_7 ? _view__WIRE_6_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_6_put = bypass_7 ? _view__WIRE_6_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_6_io_allocate_bits_repeat_T = mshrs_6_io_allocate_bits_tag == _mshrs_6_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_6_io_allocate_valid_T = sel_6 & will_reload_7; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_8 = _requests_io_valid[7]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_8 = _requests_io_valid[19]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_68 = b_pop_8; // @[Scheduler.scala:226:34, :229:78] wire c_pop_8 = _requests_io_valid[31]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_65 = lowerMatches1[7]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_66 = c_pop_8 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_67 = ~c_pop_8; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_69 = ~b_pop_8; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_70 = ~a_pop_8; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_71 = _bypassMatches_T_68 ? _bypassMatches_T_69 : _bypassMatches_T_70; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_72 = _bypassMatches_T_66 ? _bypassMatches_T_67 : _bypassMatches_T_71; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_8 = _bypassMatches_T_65 & _bypassMatches_T_72; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_8 = a_pop_8 | b_pop_8; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_8 = _may_pop_T_8 | c_pop_8; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_8 = _bypass_T_8 & bypassMatches_8; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_8 = may_pop_8 | bypass_8; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_8 = _mshrs_7_io_schedule_bits_reload & _will_reload_T_8; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_7_prio_0 = bypass_8 ? _view__WIRE_7_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_7_prio_1 = ~bypass_8 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_7_prio_2 = bypass_8 ? _view__WIRE_7_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_7_control = bypass_8 ? _view__WIRE_7_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_7_opcode = bypass_8 ? _view__WIRE_7_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_7_param = bypass_8 ? _view__WIRE_7_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_7_size = bypass_8 ? _view__WIRE_7_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_7_source = bypass_8 ? _view__WIRE_7_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_7_tag = bypass_8 ? _view__WIRE_7_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_7_offset = bypass_8 ? _view__WIRE_7_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_7_put = bypass_8 ? _view__WIRE_7_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_7_io_allocate_bits_repeat_T = mshrs_7_io_allocate_bits_tag == _mshrs_7_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_7_io_allocate_valid_T = sel_7 & will_reload_8; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_9 = _requests_io_valid[8]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_9 = _requests_io_valid[20]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_76 = b_pop_9; // @[Scheduler.scala:226:34, :229:78] wire c_pop_9 = _requests_io_valid[32]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_73 = lowerMatches1[8]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_74 = c_pop_9 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_75 = ~c_pop_9; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_77 = ~b_pop_9; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_78 = ~a_pop_9; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_79 = _bypassMatches_T_76 ? _bypassMatches_T_77 : _bypassMatches_T_78; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_80 = _bypassMatches_T_74 ? _bypassMatches_T_75 : _bypassMatches_T_79; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_9 = _bypassMatches_T_73 & _bypassMatches_T_80; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_9 = a_pop_9 | b_pop_9; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_9 = _may_pop_T_9 | c_pop_9; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_9 = _bypass_T_9 & bypassMatches_9; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_9 = may_pop_9 | bypass_9; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_9 = _mshrs_8_io_schedule_bits_reload & _will_reload_T_9; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_8_prio_0 = bypass_9 ? _view__WIRE_8_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_8_prio_1 = ~bypass_9 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_8_prio_2 = bypass_9 ? _view__WIRE_8_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_8_control = bypass_9 ? _view__WIRE_8_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_8_opcode = bypass_9 ? _view__WIRE_8_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_8_param = bypass_9 ? _view__WIRE_8_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_8_size = bypass_9 ? _view__WIRE_8_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_8_source = bypass_9 ? _view__WIRE_8_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_8_tag = bypass_9 ? _view__WIRE_8_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_8_offset = bypass_9 ? _view__WIRE_8_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_8_put = bypass_9 ? _view__WIRE_8_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_8_io_allocate_bits_repeat_T = mshrs_8_io_allocate_bits_tag == _mshrs_8_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_8_io_allocate_valid_T = sel_8 & will_reload_9; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_10 = _requests_io_valid[9]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_10 = _requests_io_valid[21]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_84 = b_pop_10; // @[Scheduler.scala:226:34, :229:78] wire c_pop_10 = _requests_io_valid[33]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_81 = lowerMatches1[9]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_82 = c_pop_10 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_83 = ~c_pop_10; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_85 = ~b_pop_10; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_86 = ~a_pop_10; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_87 = _bypassMatches_T_84 ? _bypassMatches_T_85 : _bypassMatches_T_86; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_88 = _bypassMatches_T_82 ? _bypassMatches_T_83 : _bypassMatches_T_87; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_10 = _bypassMatches_T_81 & _bypassMatches_T_88; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_10 = a_pop_10 | b_pop_10; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_10 = _may_pop_T_10 | c_pop_10; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_10 = _bypass_T_10 & bypassMatches_10; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_10 = may_pop_10 | bypass_10; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_10 = _mshrs_9_io_schedule_bits_reload & _will_reload_T_10; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_9_prio_0 = bypass_10 ? _view__WIRE_9_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_9_prio_1 = ~bypass_10 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_9_prio_2 = bypass_10 ? _view__WIRE_9_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_9_control = bypass_10 ? _view__WIRE_9_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_9_opcode = bypass_10 ? _view__WIRE_9_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_9_param = bypass_10 ? _view__WIRE_9_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_9_size = bypass_10 ? _view__WIRE_9_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_9_source = bypass_10 ? _view__WIRE_9_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_9_tag = bypass_10 ? _view__WIRE_9_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_9_offset = bypass_10 ? _view__WIRE_9_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_9_put = bypass_10 ? _view__WIRE_9_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_9_io_allocate_bits_repeat_T = mshrs_9_io_allocate_bits_tag == _mshrs_9_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70] wire _mshrs_9_io_allocate_valid_T = sel_9 & will_reload_10; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_11 = _requests_io_valid[10]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_11 = _requests_io_valid[22]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_92 = b_pop_11; // @[Scheduler.scala:226:34, :229:78] wire c_pop_11 = _requests_io_valid[34]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_89 = lowerMatches1[10]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_90 = c_pop_11 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_91 = ~c_pop_11; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_93 = ~b_pop_11; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_94 = ~a_pop_11; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_95 = _bypassMatches_T_92 ? _bypassMatches_T_93 : _bypassMatches_T_94; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_96 = _bypassMatches_T_90 ? _bypassMatches_T_91 : _bypassMatches_T_95; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_11 = _bypassMatches_T_89 & _bypassMatches_T_96; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_11 = a_pop_11 | b_pop_11; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_11 = _may_pop_T_11 | c_pop_11; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_11 = _bypass_T_11 & bypassMatches_11; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_11 = may_pop_11 | bypass_11; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_11 = _mshrs_10_io_schedule_bits_reload & _will_reload_T_11; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_10_prio_0 = bypass_11 ? _view__WIRE_10_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_10_prio_1 = ~bypass_11 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_10_prio_2 = bypass_11 ? _view__WIRE_10_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_10_control = bypass_11 ? _view__WIRE_10_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_10_opcode = bypass_11 ? _view__WIRE_10_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_10_param = bypass_11 ? _view__WIRE_10_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_10_size = bypass_11 ? _view__WIRE_10_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_10_source = bypass_11 ? _view__WIRE_10_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_10_tag = bypass_11 ? _view__WIRE_10_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_10_offset = bypass_11 ? _view__WIRE_10_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_10_put = bypass_11 ? _view__WIRE_10_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_10_io_allocate_bits_repeat_T = mshrs_10_io_allocate_bits_tag == _mshrs_10_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :287:131, :289:74] wire _mshrs_10_io_allocate_valid_T = sel_10 & will_reload_11; // @[Scheduler.scala:223:28, :232:49, :236:32] wire a_pop_12 = _requests_io_valid[11]; // @[Scheduler.scala:70:24, :225:34] wire b_pop_12 = _requests_io_valid[23]; // @[Scheduler.scala:70:24, :226:34] wire _bypassMatches_T_100 = b_pop_12; // @[Scheduler.scala:226:34, :229:78] wire c_pop_12 = _requests_io_valid[35]; // @[Scheduler.scala:70:24, :227:34] wire _bypassMatches_T_97 = lowerMatches1[11]; // @[Scheduler.scala:200:8, :228:38] wire _bypassMatches_T_98 = c_pop_12 | request_bits_prio_2; // @[Scheduler.scala:163:21, :227:34, :229:35] wire _bypassMatches_T_99 = ~c_pop_12; // @[Scheduler.scala:227:34, :229:60] wire _bypassMatches_T_101 = ~b_pop_12; // @[Scheduler.scala:226:34, :229:103] wire _bypassMatches_T_102 = ~a_pop_12; // @[Scheduler.scala:225:34, :229:111] wire _bypassMatches_T_103 = _bypassMatches_T_100 ? _bypassMatches_T_101 : _bypassMatches_T_102; // @[Scheduler.scala:229:{71,78,103,111}] wire _bypassMatches_T_104 = _bypassMatches_T_98 ? _bypassMatches_T_99 : _bypassMatches_T_103; // @[Scheduler.scala:229:{28,35,60,71}] wire bypassMatches_12 = _bypassMatches_T_97 & _bypassMatches_T_104; // @[Scheduler.scala:228:{38,42}, :229:28] wire _may_pop_T_12 = a_pop_12 | b_pop_12; // @[Scheduler.scala:225:34, :226:34, :230:25] wire may_pop_12 = _may_pop_T_12 | c_pop_12; // @[Scheduler.scala:227:34, :230:{25,34}] wire bypass_12 = _bypass_T_12 & bypassMatches_12; // @[Scheduler.scala:228:42, :231:{32,41}] wire _will_reload_T_12 = may_pop_12 | bypass_12; // @[Scheduler.scala:230:34, :231:41, :232:61] wire will_reload_12 = _mshrs_11_io_schedule_bits_reload & _will_reload_T_12; // @[Scheduler.scala:71:46, :232:{49,61}] wire _view__T_11_prio_0 = bypass_12 ? _view__WIRE_11_prio_0 : _requests_io_data_prio_0; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_11_prio_1 = ~bypass_12 & _requests_io_data_prio_1; // @[Scheduler.scala:70:24, :231:41, :233:78] wire _view__T_11_prio_2 = bypass_12 ? _view__WIRE_11_prio_2 : _requests_io_data_prio_2; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _view__T_11_control = bypass_12 ? _view__WIRE_11_control : _requests_io_data_control; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_11_opcode = bypass_12 ? _view__WIRE_11_opcode : _requests_io_data_opcode; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_11_param = bypass_12 ? _view__WIRE_11_param : _requests_io_data_param; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [2:0] _view__T_11_size = bypass_12 ? _view__WIRE_11_size : _requests_io_data_size; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_11_source = bypass_12 ? _view__WIRE_11_source : _requests_io_data_source; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [8:0] _view__T_11_tag = bypass_12 ? _view__WIRE_11_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_11_offset = bypass_12 ? _view__WIRE_11_offset : _requests_io_data_offset; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire [5:0] _view__T_11_put = bypass_12 ? _view__WIRE_11_put : _requests_io_data_put; // @[Scheduler.scala:70:24, :231:41, :233:{78,95}] wire _mshrs_11_io_allocate_bits_repeat_T = mshrs_11_io_allocate_bits_tag == _mshrs_11_io_status_bits_tag; // @[Scheduler.scala:71:46, :233:72, :235:57, :280:83, :282:70, :295:103, :297:73] wire _mshrs_11_io_allocate_valid_T = sel_11 & will_reload_12; // @[Scheduler.scala:223:28, :232:49, :236:32] wire [35:0] _prio_requests_T = ~_requests_io_valid; // @[Scheduler.scala:70:24, :240:25] wire [23:0] _prio_requests_T_1 = _requests_io_valid[35:12]; // @[Scheduler.scala:70:24, :240:65] wire [35:0] _prio_requests_T_2 = {_prio_requests_T[35:24], _prio_requests_T[23:0] | _prio_requests_T_1}; // @[Scheduler.scala:240:{25,44,65}] wire [11:0] _prio_requests_T_3 = _requests_io_valid[35:24]; // @[Scheduler.scala:70:24, :240:103] wire [35:0] _prio_requests_T_4 = {_prio_requests_T_2[35:12], _prio_requests_T_2[11:0] | _prio_requests_T_3}; // @[Scheduler.scala:240:{44,82,103}] wire [35:0] prio_requests = ~_prio_requests_T_4; // @[Scheduler.scala:240:{23,82}] wire [35:0] _pop_index_T = {pop_index_hi, mshr_selectOH}; // @[Scheduler.scala:121:70, :241:31] wire [35:0] _pop_index_T_1 = _pop_index_T & prio_requests; // @[Scheduler.scala:240:23, :241:{31,77}] wire [3:0] pop_index_hi_1 = _pop_index_T_1[35:32]; // @[OneHot.scala:30:18] wire [31:0] pop_index_lo = _pop_index_T_1[31:0]; // @[OneHot.scala:31:18] wire _pop_index_T_2 = |pop_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [31:0] _pop_index_T_3 = {28'h0, pop_index_hi_1} | pop_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] pop_index_hi_2 = _pop_index_T_3[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] pop_index_lo_1 = _pop_index_T_3[15:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_4 = |pop_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [15:0] _pop_index_T_5 = pop_index_hi_2 | pop_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] pop_index_hi_3 = _pop_index_T_5[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] pop_index_lo_2 = _pop_index_T_5[7:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_6 = |pop_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [7:0] _pop_index_T_7 = pop_index_hi_3 | pop_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] pop_index_hi_4 = _pop_index_T_7[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] pop_index_lo_3 = _pop_index_T_7[3:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_8 = |pop_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [3:0] _pop_index_T_9 = pop_index_hi_4 | pop_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] pop_index_hi_5 = _pop_index_T_9[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] pop_index_lo_4 = _pop_index_T_9[1:0]; // @[OneHot.scala:31:18, :32:28] wire _pop_index_T_10 = |pop_index_hi_5; // @[OneHot.scala:30:18, :32:14] wire [1:0] _pop_index_T_11 = pop_index_hi_5 | pop_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire _pop_index_T_12 = _pop_index_T_11[1]; // @[OneHot.scala:32:28] wire [1:0] _pop_index_T_13 = {_pop_index_T_10, _pop_index_T_12}; // @[OneHot.scala:32:{10,14}] wire [2:0] _pop_index_T_14 = {_pop_index_T_8, _pop_index_T_13}; // @[OneHot.scala:32:{10,14}] wire [3:0] _pop_index_T_15 = {_pop_index_T_6, _pop_index_T_14}; // @[OneHot.scala:32:{10,14}] wire [4:0] _pop_index_T_16 = {_pop_index_T_4, _pop_index_T_15}; // @[OneHot.scala:32:{10,14}] wire [5:0] pop_index = {_pop_index_T_2, _pop_index_T_16}; // @[OneHot.scala:32:{10,14}] wire lb_tag_mismatch = scheduleTag != _requests_io_data_tag; // @[Mux.scala:30:73] wire mshr_uses_directory_assuming_no_bypass = _mshr_uses_directory_assuming_no_bypass_T & lb_tag_mismatch; // @[Scheduler.scala:246:37, :247:{64,75}] wire mshr_uses_directory_for_lb = will_pop & lb_tag_mismatch; // @[Scheduler.scala:215:45, :246:37, :248:45] wire [8:0] _mshr_uses_directory_T = bypass ? request_bits_tag : _requests_io_data_tag; // @[Scheduler.scala:70:24, :163:21, :213:39, :249:63] wire _mshr_uses_directory_T_1 = scheduleTag != _mshr_uses_directory_T; // @[Mux.scala:30:73] wire mshr_uses_directory = will_reload & _mshr_uses_directory_T_1; // @[Scheduler.scala:214:37, :249:{41,56}] wire [1:0] mshr_validOH_lo_lo_hi = {_mshrs_2_io_status_valid, _mshrs_1_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_lo_lo = {mshr_validOH_lo_lo_hi, _mshrs_0_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_lo_hi_hi = {_mshrs_5_io_status_valid, _mshrs_4_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_lo_hi = {mshr_validOH_lo_hi_hi, _mshrs_3_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [5:0] mshr_validOH_lo = {mshr_validOH_lo_hi, mshr_validOH_lo_lo}; // @[Scheduler.scala:252:25] wire [1:0] mshr_validOH_hi_lo_hi = {_mshrs_8_io_status_valid, _mshrs_7_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_hi_lo = {mshr_validOH_hi_lo_hi, _mshrs_6_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [1:0] mshr_validOH_hi_hi_hi = {_mshrs_11_io_status_valid, _mshrs_10_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [2:0] mshr_validOH_hi_hi = {mshr_validOH_hi_hi_hi, _mshrs_9_io_status_valid}; // @[Scheduler.scala:71:46, :252:25] wire [5:0] mshr_validOH_hi = {mshr_validOH_hi_hi, mshr_validOH_hi_lo}; // @[Scheduler.scala:252:25] wire [11:0] mshr_validOH = {mshr_validOH_hi, mshr_validOH_lo}; // @[Scheduler.scala:252:25] wire [11:0] _mshr_free_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20] wire [11:0] _mshr_free_T_1 = _mshr_free_T & prioFilter; // @[Scheduler.scala:182:23, :253:{20,34}] wire mshr_free = |_mshr_free_T_1; // @[Scheduler.scala:253:{34,48}] wire bypassQueue = schedule_reload & bypassMatches; // @[Mux.scala:30:73] wire _request_alloc_cases_T = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16] wire _request_alloc_cases_T_1 = alloc & _request_alloc_cases_T; // @[Scheduler.scala:173:15, :258:{13,16}] wire _request_alloc_cases_T_2 = _request_alloc_cases_T_1 & mshr_free; // @[Scheduler.scala:253:48, :258:{13,56}] wire _request_alloc_cases_T_9 = _request_alloc_cases_T_2; // @[Scheduler.scala:258:{56,70}] wire _request_alloc_cases_T_3 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :259:16] wire _request_alloc_cases_T_5 = ~_mshrs_10_io_status_valid; // @[Scheduler.scala:71:46, :259:59] wire _request_alloc_cases_T_7 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87] wire _request_alloc_cases_T_10 = ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :260:16] wire _request_alloc_cases_T_11 = nestC & _request_alloc_cases_T_10; // @[Scheduler.scala:180:70, :260:{13,16}] wire _request_alloc_cases_T_12 = ~_mshrs_11_io_status_valid; // @[Scheduler.scala:71:46, :259:87, :260:59] wire _request_alloc_cases_T_13 = _request_alloc_cases_T_11 & _request_alloc_cases_T_12; // @[Scheduler.scala:260:{13,56,59}] wire request_alloc_cases = _request_alloc_cases_T_9 | _request_alloc_cases_T_13; // @[Scheduler.scala:258:70, :259:112, :260:56] wire _request_ready_T = bypassQueue | _requests_io_push_ready; // @[Scheduler.scala:70:24, :256:37, :261:66] wire _request_ready_T_1 = queue & _request_ready_T; // @[Scheduler.scala:185:63, :261:{50,66}] assign _request_ready_T_2 = request_alloc_cases | _request_ready_T_1; // @[Scheduler.scala:259:112, :261:{40,50}] assign request_ready = _request_ready_T_2; // @[Scheduler.scala:163:21, :261:40] wire alloc_uses_directory = request_valid & request_alloc_cases; // @[Scheduler.scala:163:21, :259:112, :262:44] wire _directory_io_read_valid_T = mshr_uses_directory | alloc_uses_directory; // @[Scheduler.scala:249:41, :262:44, :265:50] wire [10:0] _directory_io_read_bits_set_T = mshr_uses_directory_for_lb ? scheduleSet : request_bits_set; // @[Mux.scala:30:73] wire [8:0] _directory_io_read_bits_tag_T = mshr_uses_directory_for_lb ? _requests_io_data_tag : request_bits_tag; // @[Scheduler.scala:70:24, :163:21, :248:45, :267:36] wire _requests_io_push_valid_T_1 = ~bypassQueue; // @[Scheduler.scala:256:37, :270:55] wire _requests_io_push_valid_T_2 = _requests_io_push_valid_T & _requests_io_push_valid_T_1; // @[Scheduler.scala:270:{43,52,55}] wire [3:0] requests_io_push_bits_index_hi = _requests_io_push_bits_index_T[11:8]; // @[OneHot.scala:30:18] wire [7:0] requests_io_push_bits_index_lo = _requests_io_push_bits_index_T[7:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_1 = |requests_io_push_bits_index_hi; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_2 = {4'h0, requests_io_push_bits_index_hi} | requests_io_push_bits_index_lo; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_1 = _requests_io_push_bits_index_T_2[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_1 = _requests_io_push_bits_index_T_2[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_3 = |requests_io_push_bits_index_hi_1; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_4 = requests_io_push_bits_index_hi_1 | requests_io_push_bits_index_lo_1; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_2 = _requests_io_push_bits_index_T_4[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_2 = _requests_io_push_bits_index_T_4[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_5 = |requests_io_push_bits_index_hi_2; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_6 = requests_io_push_bits_index_hi_2 | requests_io_push_bits_index_lo_2; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_7 = _requests_io_push_bits_index_T_6[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_8 = {_requests_io_push_bits_index_T_5, _requests_io_push_bits_index_T_7}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_9 = {_requests_io_push_bits_index_T_3, _requests_io_push_bits_index_T_8}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_10 = {_requests_io_push_bits_index_T_1, _requests_io_push_bits_index_T_9}; // @[OneHot.scala:32:{10,14}] wire [23:0] _requests_io_push_bits_index_T_11 = {lowerMatches1, 12'h0}; // @[Scheduler.scala:200:8, :275:30] wire [7:0] requests_io_push_bits_index_hi_3 = _requests_io_push_bits_index_T_11[23:16]; // @[OneHot.scala:30:18] wire [15:0] requests_io_push_bits_index_lo_3 = _requests_io_push_bits_index_T_11[15:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_12 = |requests_io_push_bits_index_hi_3; // @[OneHot.scala:30:18, :32:14] wire [15:0] _requests_io_push_bits_index_T_13 = {8'h0, requests_io_push_bits_index_hi_3} | requests_io_push_bits_index_lo_3; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] requests_io_push_bits_index_hi_4 = _requests_io_push_bits_index_T_13[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] requests_io_push_bits_index_lo_4 = _requests_io_push_bits_index_T_13[7:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_14 = |requests_io_push_bits_index_hi_4; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_15 = requests_io_push_bits_index_hi_4 | requests_io_push_bits_index_lo_4; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_5 = _requests_io_push_bits_index_T_15[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_5 = _requests_io_push_bits_index_T_15[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_16 = |requests_io_push_bits_index_hi_5; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_17 = requests_io_push_bits_index_hi_5 | requests_io_push_bits_index_lo_5; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_6 = _requests_io_push_bits_index_T_17[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_6 = _requests_io_push_bits_index_T_17[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_18 = |requests_io_push_bits_index_hi_6; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_19 = requests_io_push_bits_index_hi_6 | requests_io_push_bits_index_lo_6; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_20 = _requests_io_push_bits_index_T_19[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_21 = {_requests_io_push_bits_index_T_18, _requests_io_push_bits_index_T_20}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_22 = {_requests_io_push_bits_index_T_16, _requests_io_push_bits_index_T_21}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_23 = {_requests_io_push_bits_index_T_14, _requests_io_push_bits_index_T_22}; // @[OneHot.scala:32:{10,14}] wire [4:0] _requests_io_push_bits_index_T_24 = {_requests_io_push_bits_index_T_12, _requests_io_push_bits_index_T_23}; // @[OneHot.scala:32:{10,14}] wire [35:0] _requests_io_push_bits_index_T_25 = {lowerMatches1, 24'h0}; // @[Scheduler.scala:200:8, :276:30] wire [3:0] requests_io_push_bits_index_hi_7 = _requests_io_push_bits_index_T_25[35:32]; // @[OneHot.scala:30:18] wire [31:0] requests_io_push_bits_index_lo_7 = _requests_io_push_bits_index_T_25[31:0]; // @[OneHot.scala:31:18] wire _requests_io_push_bits_index_T_26 = |requests_io_push_bits_index_hi_7; // @[OneHot.scala:30:18, :32:14] wire [31:0] _requests_io_push_bits_index_T_27 = {28'h0, requests_io_push_bits_index_hi_7} | requests_io_push_bits_index_lo_7; // @[OneHot.scala:30:18, :31:18, :32:28] wire [15:0] requests_io_push_bits_index_hi_8 = _requests_io_push_bits_index_T_27[31:16]; // @[OneHot.scala:30:18, :32:28] wire [15:0] requests_io_push_bits_index_lo_8 = _requests_io_push_bits_index_T_27[15:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_28 = |requests_io_push_bits_index_hi_8; // @[OneHot.scala:30:18, :32:14] wire [15:0] _requests_io_push_bits_index_T_29 = requests_io_push_bits_index_hi_8 | requests_io_push_bits_index_lo_8; // @[OneHot.scala:30:18, :31:18, :32:28] wire [7:0] requests_io_push_bits_index_hi_9 = _requests_io_push_bits_index_T_29[15:8]; // @[OneHot.scala:30:18, :32:28] wire [7:0] requests_io_push_bits_index_lo_9 = _requests_io_push_bits_index_T_29[7:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_30 = |requests_io_push_bits_index_hi_9; // @[OneHot.scala:30:18, :32:14] wire [7:0] _requests_io_push_bits_index_T_31 = requests_io_push_bits_index_hi_9 | requests_io_push_bits_index_lo_9; // @[OneHot.scala:30:18, :31:18, :32:28] wire [3:0] requests_io_push_bits_index_hi_10 = _requests_io_push_bits_index_T_31[7:4]; // @[OneHot.scala:30:18, :32:28] wire [3:0] requests_io_push_bits_index_lo_10 = _requests_io_push_bits_index_T_31[3:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_32 = |requests_io_push_bits_index_hi_10; // @[OneHot.scala:30:18, :32:14] wire [3:0] _requests_io_push_bits_index_T_33 = requests_io_push_bits_index_hi_10 | requests_io_push_bits_index_lo_10; // @[OneHot.scala:30:18, :31:18, :32:28] wire [1:0] requests_io_push_bits_index_hi_11 = _requests_io_push_bits_index_T_33[3:2]; // @[OneHot.scala:30:18, :32:28] wire [1:0] requests_io_push_bits_index_lo_11 = _requests_io_push_bits_index_T_33[1:0]; // @[OneHot.scala:31:18, :32:28] wire _requests_io_push_bits_index_T_34 = |requests_io_push_bits_index_hi_11; // @[OneHot.scala:30:18, :32:14] wire [1:0] _requests_io_push_bits_index_T_35 = requests_io_push_bits_index_hi_11 | requests_io_push_bits_index_lo_11; // @[OneHot.scala:30:18, :31:18, :32:28] wire _requests_io_push_bits_index_T_36 = _requests_io_push_bits_index_T_35[1]; // @[OneHot.scala:32:28] wire [1:0] _requests_io_push_bits_index_T_37 = {_requests_io_push_bits_index_T_34, _requests_io_push_bits_index_T_36}; // @[OneHot.scala:32:{10,14}] wire [2:0] _requests_io_push_bits_index_T_38 = {_requests_io_push_bits_index_T_32, _requests_io_push_bits_index_T_37}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_39 = {_requests_io_push_bits_index_T_30, _requests_io_push_bits_index_T_38}; // @[OneHot.scala:32:{10,14}] wire [4:0] _requests_io_push_bits_index_T_40 = {_requests_io_push_bits_index_T_28, _requests_io_push_bits_index_T_39}; // @[OneHot.scala:32:{10,14}] wire [5:0] _requests_io_push_bits_index_T_41 = {_requests_io_push_bits_index_T_26, _requests_io_push_bits_index_T_40}; // @[OneHot.scala:32:{10,14}] wire [3:0] _requests_io_push_bits_index_T_42 = request_bits_prio_0 ? _requests_io_push_bits_index_T_10 : 4'h0; // @[OneHot.scala:32:10] wire [5:0] _requests_io_push_bits_index_T_44 = request_bits_prio_2 ? _requests_io_push_bits_index_T_41 : 6'h0; // @[OneHot.scala:32:10] wire [4:0] _requests_io_push_bits_index_T_45 = {1'h0, _requests_io_push_bits_index_T_42}; // @[Mux.scala:30:73] wire [5:0] _requests_io_push_bits_index_T_46 = {1'h0, _requests_io_push_bits_index_T_45} | _requests_io_push_bits_index_T_44; // @[Mux.scala:30:73] wire [5:0] _requests_io_push_bits_index_WIRE = _requests_io_push_bits_index_T_46; // @[Mux.scala:30:73] wire [11:0] _mshr_insertOH_T = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:32] wire [12:0] _mshr_insertOH_T_1 = {_mshr_insertOH_T, 1'h0}; // @[package.scala:253:48] wire [11:0] _mshr_insertOH_T_2 = _mshr_insertOH_T_1[11:0]; // @[package.scala:253:{48,53}] wire [11:0] _mshr_insertOH_T_3 = _mshr_insertOH_T | _mshr_insertOH_T_2; // @[package.scala:253:{43,53}] wire [13:0] _mshr_insertOH_T_4 = {_mshr_insertOH_T_3, 2'h0}; // @[package.scala:253:{43,48}] wire [11:0] _mshr_insertOH_T_5 = _mshr_insertOH_T_4[11:0]; // @[package.scala:253:{48,53}] wire [11:0] _mshr_insertOH_T_6 = _mshr_insertOH_T_3 | _mshr_insertOH_T_5; // @[package.scala:253:{43,53}] wire [15:0] _mshr_insertOH_T_7 = {_mshr_insertOH_T_6, 4'h0}; // @[package.scala:253:{43,48}] wire [11:0] _mshr_insertOH_T_8 = _mshr_insertOH_T_7[11:0]; // @[package.scala:253:{48,53}] wire [11:0] _mshr_insertOH_T_9 = _mshr_insertOH_T_6 | _mshr_insertOH_T_8; // @[package.scala:253:{43,53}] wire [19:0] _mshr_insertOH_T_10 = {_mshr_insertOH_T_9, 8'h0}; // @[package.scala:253:{43,48}] wire [11:0] _mshr_insertOH_T_11 = _mshr_insertOH_T_10[11:0]; // @[package.scala:253:{48,53}] wire [11:0] _mshr_insertOH_T_12 = _mshr_insertOH_T_9 | _mshr_insertOH_T_11; // @[package.scala:253:{43,53}] wire [11:0] _mshr_insertOH_T_13 = _mshr_insertOH_T_12; // @[package.scala:253:43, :254:17] wire [12:0] _mshr_insertOH_T_14 = {_mshr_insertOH_T_13, 1'h0}; // @[package.scala:254:17] wire [12:0] _mshr_insertOH_T_15 = ~_mshr_insertOH_T_14; // @[Scheduler.scala:278:{23,47}] wire [11:0] _mshr_insertOH_T_16 = ~mshr_validOH; // @[Scheduler.scala:252:25, :253:20, :278:55] wire [12:0] _mshr_insertOH_T_17 = {1'h0, _mshr_insertOH_T_15[11:0] & _mshr_insertOH_T_16}; // @[Scheduler.scala:278:{23,53,55}] wire [12:0] mshr_insertOH = {1'h0, _mshr_insertOH_T_17[11:0] & prioFilter}; // @[Scheduler.scala:182:23, :278:{53,69}] wire _T_76 = request_valid & alloc; // @[Scheduler.scala:163:21, :173:15, :280:25] wire _T_35 = _T_76 & mshr_insertOH[0] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_0_io_allocate_bits_tag = _T_35 ? request_bits_tag : _view__T_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_39 = _T_76 & mshr_insertOH[1] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_1_io_allocate_bits_tag = _T_39 ? request_bits_tag : _view__T_1_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_43 = _T_76 & mshr_insertOH[2] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_2_io_allocate_bits_tag = _T_43 ? request_bits_tag : _view__T_2_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_47 = _T_76 & mshr_insertOH[3] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_3_io_allocate_bits_tag = _T_47 ? request_bits_tag : _view__T_3_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_51 = _T_76 & mshr_insertOH[4] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_4_io_allocate_bits_tag = _T_51 ? request_bits_tag : _view__T_4_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_55 = _T_76 & mshr_insertOH[5] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_5_io_allocate_bits_tag = _T_55 ? request_bits_tag : _view__T_5_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_59 = _T_76 & mshr_insertOH[6] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_6_io_allocate_bits_tag = _T_59 ? request_bits_tag : _view__T_6_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_63 = _T_76 & mshr_insertOH[7] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_7_io_allocate_bits_tag = _T_63 ? request_bits_tag : _view__T_7_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_67 = _T_76 & mshr_insertOH[8] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_8_io_allocate_bits_tag = _T_67 ? request_bits_tag : _view__T_8_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_71 = _T_76 & mshr_insertOH[9] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_9_io_allocate_bits_tag = _T_71 ? request_bits_tag : _view__T_9_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70] wire _T_75 = _T_76 & mshr_insertOH[10] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:247:75, :258:16, :278:69, :279:18, :280:{25,34,39}] assign mshrs_10_io_allocate_bits_tag = _T_75 ? request_bits_tag : _view__T_10_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :280:{34,39,83}, :282:70, :287:131, :289:74] wire _T_95 = request_valid & nestC & ~_mshrs_11_io_status_valid & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:71:46, :163:21, :180:70, :193:33, :247:75, :258:16, :259:87, :295:{32,59}] wire _GEN_3 = _T_95 | _T_76 & mshr_insertOH[11] & ~mshr_uses_directory_assuming_no_bypass; // @[Scheduler.scala:193:33, :236:25, :247:75, :258:16, :278:69, :279:18, :280:{25,34,39,83}, :281:27, :295:{32,59,103}, :296:30] assign mshrs_11_io_allocate_bits_tag = _GEN_3 ? request_bits_tag : _view__T_11_tag; // @[Scheduler.scala:163:21, :233:{72,78}, :236:25, :280:83, :281:27, :282:70, :295:103, :296:30, :297:73]
Generate the Verilog code corresponding to this FIRRTL code module TileClockGater : input clock : Clock input reset : Reset output auto : { flip clock_gater_in_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}}, flip clock_gater_in_0 : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}, clock_gater_out : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}}} wire clock_gaterOut : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterOut.member.allClocks_uncore.reset invalidate clock_gaterOut.member.allClocks_uncore.clock wire clock_gaterIn : { member : { allClocks_uncore : { clock : Clock, reset : Reset}}} invalidate clock_gaterIn.member.allClocks_uncore.reset invalidate clock_gaterIn.member.allClocks_uncore.clock connect clock_gaterOut, clock_gaterIn wire clock_gaterIn_1 : { a : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}}, flip d : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}}} invalidate clock_gaterIn_1.d.bits.corrupt invalidate clock_gaterIn_1.d.bits.data invalidate clock_gaterIn_1.d.bits.denied invalidate clock_gaterIn_1.d.bits.sink invalidate clock_gaterIn_1.d.bits.source invalidate clock_gaterIn_1.d.bits.size invalidate clock_gaterIn_1.d.bits.param invalidate clock_gaterIn_1.d.bits.opcode invalidate clock_gaterIn_1.d.valid invalidate clock_gaterIn_1.d.ready invalidate clock_gaterIn_1.a.bits.corrupt invalidate clock_gaterIn_1.a.bits.data invalidate clock_gaterIn_1.a.bits.mask invalidate clock_gaterIn_1.a.bits.address invalidate clock_gaterIn_1.a.bits.source invalidate clock_gaterIn_1.a.bits.size invalidate clock_gaterIn_1.a.bits.param invalidate clock_gaterIn_1.a.bits.opcode invalidate clock_gaterIn_1.a.valid invalidate clock_gaterIn_1.a.ready inst monitor of TLMonitor_57 connect monitor.clock, clock connect monitor.reset, reset connect monitor.io.in.d.bits.corrupt, clock_gaterIn_1.d.bits.corrupt connect monitor.io.in.d.bits.data, clock_gaterIn_1.d.bits.data connect monitor.io.in.d.bits.denied, clock_gaterIn_1.d.bits.denied connect monitor.io.in.d.bits.sink, clock_gaterIn_1.d.bits.sink connect monitor.io.in.d.bits.source, clock_gaterIn_1.d.bits.source connect monitor.io.in.d.bits.size, clock_gaterIn_1.d.bits.size connect monitor.io.in.d.bits.param, clock_gaterIn_1.d.bits.param connect monitor.io.in.d.bits.opcode, clock_gaterIn_1.d.bits.opcode connect monitor.io.in.d.valid, clock_gaterIn_1.d.valid connect monitor.io.in.d.ready, clock_gaterIn_1.d.ready connect monitor.io.in.a.bits.corrupt, clock_gaterIn_1.a.bits.corrupt connect monitor.io.in.a.bits.data, clock_gaterIn_1.a.bits.data connect monitor.io.in.a.bits.mask, clock_gaterIn_1.a.bits.mask connect monitor.io.in.a.bits.address, clock_gaterIn_1.a.bits.address connect monitor.io.in.a.bits.source, clock_gaterIn_1.a.bits.source connect monitor.io.in.a.bits.size, clock_gaterIn_1.a.bits.size connect monitor.io.in.a.bits.param, clock_gaterIn_1.a.bits.param connect monitor.io.in.a.bits.opcode, clock_gaterIn_1.a.bits.opcode connect monitor.io.in.a.valid, clock_gaterIn_1.a.valid connect monitor.io.in.a.ready, clock_gaterIn_1.a.ready connect auto.clock_gater_out, clock_gaterOut connect clock_gaterIn, auto.clock_gater_in_0 connect clock_gaterIn_1, auto.clock_gater_in_1 inst regs_0 of AsyncResetRegVec_w1_i1 connect regs_0.clock, clock connect regs_0.reset, clock_gaterIn.member.allClocks_uncore.reset connect clock_gaterOut.member.allClocks_uncore, clock_gaterIn.member.allClocks_uncore wire in : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} node _in_bits_read_T = eq(clock_gaterIn_1.a.bits.opcode, UInt<3>(0h4)) connect in.bits.read, _in_bits_read_T node _in_bits_index_T = shr(clock_gaterIn_1.a.bits.address, 3) connect in.bits.index, _in_bits_index_T connect in.bits.data, clock_gaterIn_1.a.bits.data connect in.bits.mask, clock_gaterIn_1.a.bits.mask connect in.bits.extra.tlrr_extra.source, clock_gaterIn_1.a.bits.source connect in.bits.extra.tlrr_extra.size, clock_gaterIn_1.a.bits.size wire out : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, data : UInt<64>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} wire out_front : { flip ready : UInt<1>, valid : UInt<1>, bits : { read : UInt<1>, index : UInt<9>, data : UInt<64>, mask : UInt<8>, extra : { tlrr_extra : { source : UInt<11>, size : UInt<2>}}}} connect out_front.bits, in.bits node out_maskMatch = not(UInt<9>(0h0)) node out_findex = and(out_front.bits.index, out_maskMatch) node out_bindex = and(out_front.bits.index, out_maskMatch) node _out_T = eq(out_findex, UInt<9>(0h0)) node _out_T_1 = eq(out_bindex, UInt<9>(0h0)) wire out_rivalid : UInt<1>[1] wire out_wivalid : UInt<1>[1] wire out_roready : UInt<1>[1] wire out_woready : UInt<1>[1] node _out_frontMask_T = bits(out_front.bits.mask, 0, 0) node _out_frontMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_frontMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_frontMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_frontMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_frontMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_frontMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_frontMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_frontMask_T_8 = mux(_out_frontMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_9 = mux(_out_frontMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_10 = mux(_out_frontMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_11 = mux(_out_frontMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_12 = mux(_out_frontMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_13 = mux(_out_frontMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_14 = mux(_out_frontMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_frontMask_T_15 = mux(_out_frontMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_frontMask_lo_lo = cat(_out_frontMask_T_9, _out_frontMask_T_8) node out_frontMask_lo_hi = cat(_out_frontMask_T_11, _out_frontMask_T_10) node out_frontMask_lo = cat(out_frontMask_lo_hi, out_frontMask_lo_lo) node out_frontMask_hi_lo = cat(_out_frontMask_T_13, _out_frontMask_T_12) node out_frontMask_hi_hi = cat(_out_frontMask_T_15, _out_frontMask_T_14) node out_frontMask_hi = cat(out_frontMask_hi_hi, out_frontMask_hi_lo) node out_frontMask = cat(out_frontMask_hi, out_frontMask_lo) node _out_backMask_T = bits(out_front.bits.mask, 0, 0) node _out_backMask_T_1 = bits(out_front.bits.mask, 1, 1) node _out_backMask_T_2 = bits(out_front.bits.mask, 2, 2) node _out_backMask_T_3 = bits(out_front.bits.mask, 3, 3) node _out_backMask_T_4 = bits(out_front.bits.mask, 4, 4) node _out_backMask_T_5 = bits(out_front.bits.mask, 5, 5) node _out_backMask_T_6 = bits(out_front.bits.mask, 6, 6) node _out_backMask_T_7 = bits(out_front.bits.mask, 7, 7) node _out_backMask_T_8 = mux(_out_backMask_T, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_9 = mux(_out_backMask_T_1, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_10 = mux(_out_backMask_T_2, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_11 = mux(_out_backMask_T_3, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_12 = mux(_out_backMask_T_4, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_13 = mux(_out_backMask_T_5, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_14 = mux(_out_backMask_T_6, UInt<8>(0hff), UInt<8>(0h0)) node _out_backMask_T_15 = mux(_out_backMask_T_7, UInt<8>(0hff), UInt<8>(0h0)) node out_backMask_lo_lo = cat(_out_backMask_T_9, _out_backMask_T_8) node out_backMask_lo_hi = cat(_out_backMask_T_11, _out_backMask_T_10) node out_backMask_lo = cat(out_backMask_lo_hi, out_backMask_lo_lo) node out_backMask_hi_lo = cat(_out_backMask_T_13, _out_backMask_T_12) node out_backMask_hi_hi = cat(_out_backMask_T_15, _out_backMask_T_14) node out_backMask_hi = cat(out_backMask_hi_hi, out_backMask_hi_lo) node out_backMask = cat(out_backMask_hi, out_backMask_lo) node _out_rimask_T = bits(out_frontMask, 0, 0) node out_rimask = orr(_out_rimask_T) node _out_wimask_T = bits(out_frontMask, 0, 0) node out_wimask = andr(_out_wimask_T) node _out_romask_T = bits(out_backMask, 0, 0) node out_romask = orr(_out_romask_T) node _out_womask_T = bits(out_backMask, 0, 0) node out_womask = andr(_out_womask_T) node out_f_rivalid = and(out_rivalid[0], out_rimask) node out_f_roready = and(out_roready[0], out_romask) node out_f_wivalid = and(out_wivalid[0], out_wimask) node out_f_woready = and(out_woready[0], out_womask) node _out_T_2 = bits(out_front.bits.data, 0, 0) connect regs_0.io.en, out_f_woready connect regs_0.io.d, _out_T_2 node _out_T_3 = eq(out_rimask, UInt<1>(0h0)) node _out_T_4 = eq(out_wimask, UInt<1>(0h0)) node _out_T_5 = eq(out_romask, UInt<1>(0h0)) node _out_T_6 = eq(out_womask, UInt<1>(0h0)) node _out_T_7 = or(regs_0.io.q, UInt<1>(0h0)) node _out_T_8 = bits(_out_T_7, 0, 0) node _out_frontSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_frontSel_0 = bits(_out_frontSel_T, 0, 0) node out_frontSel_1 = bits(_out_frontSel_T, 1, 1) node _out_backSel_T = dshl(UInt<1>(0h1), UInt<1>(0h0)) node out_backSel_0 = bits(_out_backSel_T, 0, 0) node out_backSel_1 = bits(_out_backSel_T, 1, 1) node _out_rifireMux_T = and(in.valid, out_front.ready) node _out_rifireMux_T_1 = and(_out_rifireMux_T, out_front.bits.read) wire out_rifireMux_out : UInt<1> node _out_rifireMux_T_2 = and(_out_rifireMux_T_1, out_frontSel_0) node _out_rifireMux_T_3 = and(_out_rifireMux_T_2, _out_T) connect out_rifireMux_out, UInt<1>(0h1) connect out_rivalid[0], _out_rifireMux_T_3 node _out_rifireMux_T_4 = eq(_out_T, UInt<1>(0h0)) node _out_rifireMux_T_5 = or(out_rifireMux_out, _out_rifireMux_T_4) node _out_rifireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rifireMux_WIRE : UInt<1>[1] connect _out_rifireMux_WIRE[0], _out_rifireMux_T_5 node out_rifireMux = mux(_out_rifireMux_T_6, UInt<1>(0h1), _out_rifireMux_WIRE[0]) node _out_wifireMux_T = and(in.valid, out_front.ready) node _out_wifireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wifireMux_T_2 = and(_out_wifireMux_T, _out_wifireMux_T_1) wire out_wifireMux_out : UInt<1> node _out_wifireMux_T_3 = and(_out_wifireMux_T_2, out_frontSel_0) node _out_wifireMux_T_4 = and(_out_wifireMux_T_3, _out_T) connect out_wifireMux_out, UInt<1>(0h1) connect out_wivalid[0], _out_wifireMux_T_4 node _out_wifireMux_T_5 = eq(_out_T, UInt<1>(0h0)) node _out_wifireMux_T_6 = or(out_wifireMux_out, _out_wifireMux_T_5) node _out_wifireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wifireMux_WIRE : UInt<1>[1] connect _out_wifireMux_WIRE[0], _out_wifireMux_T_6 node out_wifireMux = mux(_out_wifireMux_T_7, UInt<1>(0h1), _out_wifireMux_WIRE[0]) node _out_rofireMux_T = and(out_front.valid, out.ready) node _out_rofireMux_T_1 = and(_out_rofireMux_T, out_front.bits.read) wire out_rofireMux_out : UInt<1> node _out_rofireMux_T_2 = and(_out_rofireMux_T_1, out_backSel_0) node _out_rofireMux_T_3 = and(_out_rofireMux_T_2, _out_T_1) connect out_rofireMux_out, UInt<1>(0h1) connect out_roready[0], _out_rofireMux_T_3 node _out_rofireMux_T_4 = eq(_out_T_1, UInt<1>(0h0)) node _out_rofireMux_T_5 = or(out_rofireMux_out, _out_rofireMux_T_4) node _out_rofireMux_T_6 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_rofireMux_WIRE : UInt<1>[1] connect _out_rofireMux_WIRE[0], _out_rofireMux_T_5 node out_rofireMux = mux(_out_rofireMux_T_6, UInt<1>(0h1), _out_rofireMux_WIRE[0]) node _out_wofireMux_T = and(out_front.valid, out.ready) node _out_wofireMux_T_1 = eq(out_front.bits.read, UInt<1>(0h0)) node _out_wofireMux_T_2 = and(_out_wofireMux_T, _out_wofireMux_T_1) wire out_wofireMux_out : UInt<1> node _out_wofireMux_T_3 = and(_out_wofireMux_T_2, out_backSel_0) node _out_wofireMux_T_4 = and(_out_wofireMux_T_3, _out_T_1) connect out_wofireMux_out, UInt<1>(0h1) connect out_woready[0], _out_wofireMux_T_4 node _out_wofireMux_T_5 = eq(_out_T_1, UInt<1>(0h0)) node _out_wofireMux_T_6 = or(out_wofireMux_out, _out_wofireMux_T_5) node _out_wofireMux_T_7 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_wofireMux_WIRE : UInt<1>[1] connect _out_wofireMux_WIRE[0], _out_wofireMux_T_6 node out_wofireMux = mux(_out_wofireMux_T_7, UInt<1>(0h1), _out_wofireMux_WIRE[0]) node out_iready = mux(out_front.bits.read, out_rifireMux, out_wifireMux) node out_oready = mux(out_front.bits.read, out_rofireMux, out_wofireMux) node _out_in_ready_T = and(out_front.ready, out_iready) connect in.ready, _out_in_ready_T node _out_front_valid_T = and(in.valid, out_iready) connect out_front.valid, _out_front_valid_T node _out_front_ready_T = and(out.ready, out_oready) connect out_front.ready, _out_front_ready_T node _out_out_valid_T = and(out_front.valid, out_oready) connect out.valid, _out_out_valid_T connect out.bits.read, out_front.bits.read node _out_out_bits_data_T = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE : UInt<1>[1] connect _out_out_bits_data_WIRE[0], _out_T_1 node _out_out_bits_data_T_1 = mux(_out_out_bits_data_T, UInt<1>(0h1), _out_out_bits_data_WIRE[0]) node _out_out_bits_data_T_2 = geq(UInt<1>(0h0), UInt<1>(0h1)) wire _out_out_bits_data_WIRE_1 : UInt<1>[1] connect _out_out_bits_data_WIRE_1[0], _out_T_8 node _out_out_bits_data_T_3 = mux(_out_out_bits_data_T_2, UInt<1>(0h0), _out_out_bits_data_WIRE_1[0]) node _out_out_bits_data_T_4 = mux(_out_out_bits_data_T_1, _out_out_bits_data_T_3, UInt<1>(0h0)) connect out.bits.data, _out_out_bits_data_T_4 connect out.bits.extra, out_front.bits.extra connect in.valid, clock_gaterIn_1.a.valid connect clock_gaterIn_1.a.ready, in.ready connect clock_gaterIn_1.d.valid, out.valid connect out.ready, clock_gaterIn_1.d.ready wire clock_gaterIn_d_bits_d : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, sink : UInt<1>, denied : UInt<1>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>} connect clock_gaterIn_d_bits_d.opcode, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.param, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.size, out.bits.extra.tlrr_extra.size connect clock_gaterIn_d_bits_d.source, out.bits.extra.tlrr_extra.source connect clock_gaterIn_d_bits_d.sink, UInt<1>(0h0) connect clock_gaterIn_d_bits_d.denied, UInt<1>(0h0) invalidate clock_gaterIn_d_bits_d.data connect clock_gaterIn_d_bits_d.corrupt, UInt<1>(0h0) connect clock_gaterIn_1.d.bits.corrupt, clock_gaterIn_d_bits_d.corrupt connect clock_gaterIn_1.d.bits.data, clock_gaterIn_d_bits_d.data connect clock_gaterIn_1.d.bits.denied, clock_gaterIn_d_bits_d.denied connect clock_gaterIn_1.d.bits.sink, clock_gaterIn_d_bits_d.sink connect clock_gaterIn_1.d.bits.source, clock_gaterIn_d_bits_d.source connect clock_gaterIn_1.d.bits.size, clock_gaterIn_d_bits_d.size connect clock_gaterIn_1.d.bits.param, clock_gaterIn_d_bits_d.param connect clock_gaterIn_1.d.bits.opcode, clock_gaterIn_d_bits_d.opcode connect clock_gaterIn_1.d.bits.data, out.bits.data node _clock_gaterIn_d_bits_opcode_T = mux(out.bits.read, UInt<1>(0h1), UInt<1>(0h0)) connect clock_gaterIn_1.d.bits.opcode, _clock_gaterIn_d_bits_opcode_T wire _WIRE : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE.bits.corrupt, UInt<1>(0h0) connect _WIRE.bits.data, UInt<64>(0h0) connect _WIRE.bits.mask, UInt<8>(0h0) connect _WIRE.bits.address, UInt<21>(0h0) connect _WIRE.bits.source, UInt<11>(0h0) connect _WIRE.bits.size, UInt<2>(0h0) connect _WIRE.bits.param, UInt<2>(0h0) connect _WIRE.bits.opcode, UInt<3>(0h0) connect _WIRE.valid, UInt<1>(0h0) connect _WIRE.ready, UInt<1>(0h0) wire _WIRE_1 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<2>, size : UInt<2>, source : UInt<11>, address : UInt<21>, mask : UInt<8>, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_1.bits, _WIRE.bits connect _WIRE_1.valid, _WIRE.valid connect _WIRE_1.ready, _WIRE.ready connect _WIRE_1.valid, UInt<1>(0h0) wire _WIRE_2 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_2.bits.corrupt, UInt<1>(0h0) connect _WIRE_2.bits.data, UInt<64>(0h0) connect _WIRE_2.bits.address, UInt<21>(0h0) connect _WIRE_2.bits.source, UInt<11>(0h0) connect _WIRE_2.bits.size, UInt<2>(0h0) connect _WIRE_2.bits.param, UInt<3>(0h0) connect _WIRE_2.bits.opcode, UInt<3>(0h0) connect _WIRE_2.valid, UInt<1>(0h0) connect _WIRE_2.ready, UInt<1>(0h0) wire _WIRE_3 : { flip ready : UInt<1>, valid : UInt<1>, bits : { opcode : UInt<3>, param : UInt<3>, size : UInt<2>, source : UInt<11>, address : UInt<21>, user : { }, echo : { }, data : UInt<64>, corrupt : UInt<1>}} connect _WIRE_3.bits, _WIRE_2.bits connect _WIRE_3.valid, _WIRE_2.valid connect _WIRE_3.ready, _WIRE_2.ready connect _WIRE_3.ready, UInt<1>(0h1) wire _WIRE_4 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_4.bits.sink, UInt<1>(0h0) connect _WIRE_4.valid, UInt<1>(0h0) connect _WIRE_4.ready, UInt<1>(0h0) wire _WIRE_5 : { flip ready : UInt<1>, valid : UInt<1>, bits : { sink : UInt<1>}} connect _WIRE_5.bits, _WIRE_4.bits connect _WIRE_5.valid, _WIRE_4.valid connect _WIRE_5.ready, _WIRE_4.ready connect _WIRE_5.ready, UInt<1>(0h1) extmodule plusarg_reader_119 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32 extmodule plusarg_reader_120 : output out : UInt<32> defname = plusarg_reader parameter DEFAULT = 0 parameter FORMAT = "tilelink_timeout=%d" parameter WIDTH = 32
module TileClockGater( // @[TileClockGater.scala:27:25] input clock, // @[TileClockGater.scala:27:25] input reset, // @[TileClockGater.scala:27:25] output auto_clock_gater_in_1_a_ready, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_valid, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_opcode, // @[LazyModuleImp.scala:107:25] input [2:0] auto_clock_gater_in_1_a_bits_param, // @[LazyModuleImp.scala:107:25] input [1:0] auto_clock_gater_in_1_a_bits_size, // @[LazyModuleImp.scala:107:25] input [10:0] auto_clock_gater_in_1_a_bits_source, // @[LazyModuleImp.scala:107:25] input [20:0] auto_clock_gater_in_1_a_bits_address, // @[LazyModuleImp.scala:107:25] input [7:0] auto_clock_gater_in_1_a_bits_mask, // @[LazyModuleImp.scala:107:25] input [63:0] auto_clock_gater_in_1_a_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_a_bits_corrupt, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_1_d_ready, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_in_1_d_valid, // @[LazyModuleImp.scala:107:25] output [2:0] auto_clock_gater_in_1_d_bits_opcode, // @[LazyModuleImp.scala:107:25] output [1:0] auto_clock_gater_in_1_d_bits_size, // @[LazyModuleImp.scala:107:25] output [10:0] auto_clock_gater_in_1_d_bits_source, // @[LazyModuleImp.scala:107:25] output [63:0] auto_clock_gater_in_1_d_bits_data, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] input auto_clock_gater_in_0_member_allClocks_uncore_reset, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_clock, // @[LazyModuleImp.scala:107:25] output auto_clock_gater_out_member_allClocks_uncore_reset // @[LazyModuleImp.scala:107:25] ); wire _out_wofireMux_T_1; // @[RegisterRouter.scala:87:24] wire _regs_0_io_q; // @[TileClockGater.scala:33:53] wire in_bits_read = auto_clock_gater_in_1_a_bits_opcode == 3'h4; // @[RegisterRouter.scala:74:36] wire _out_T_1 = auto_clock_gater_in_1_a_bits_address[11:3] == 9'h0; // @[RegisterRouter.scala:75:19, :87:24] assign _out_wofireMux_T_1 = ~in_bits_read; // @[RegisterRouter.scala:74:36, :87:24] wire [2:0] monitor_io_in_d_bits_opcode = {2'h0, in_bits_read}; // @[RegisterRouter.scala:74:36, :105:19] TLMonitor_57 monitor ( // @[Nodes.scala:27:25] .clock (clock), .reset (reset), .io_in_a_ready (auto_clock_gater_in_1_d_ready), .io_in_a_valid (auto_clock_gater_in_1_a_valid), .io_in_a_bits_opcode (auto_clock_gater_in_1_a_bits_opcode), .io_in_a_bits_param (auto_clock_gater_in_1_a_bits_param), .io_in_a_bits_size (auto_clock_gater_in_1_a_bits_size), .io_in_a_bits_source (auto_clock_gater_in_1_a_bits_source), .io_in_a_bits_address (auto_clock_gater_in_1_a_bits_address), .io_in_a_bits_mask (auto_clock_gater_in_1_a_bits_mask), .io_in_a_bits_corrupt (auto_clock_gater_in_1_a_bits_corrupt), .io_in_d_ready (auto_clock_gater_in_1_d_ready), .io_in_d_valid (auto_clock_gater_in_1_a_valid), .io_in_d_bits_opcode (monitor_io_in_d_bits_opcode), // @[RegisterRouter.scala:105:19] .io_in_d_bits_size (auto_clock_gater_in_1_a_bits_size), .io_in_d_bits_source (auto_clock_gater_in_1_a_bits_source) ); // @[Nodes.scala:27:25] AsyncResetRegVec_w1_i1 regs_0 ( // @[TileClockGater.scala:33:53] .clock (clock), .reset (auto_clock_gater_in_0_member_allClocks_uncore_reset), .io_d (auto_clock_gater_in_1_a_bits_data[0]), // @[RegisterRouter.scala:87:24] .io_q (_regs_0_io_q), .io_en (auto_clock_gater_in_1_a_valid & auto_clock_gater_in_1_d_ready & _out_wofireMux_T_1 & _out_T_1 & auto_clock_gater_in_1_a_bits_mask[0]) // @[RegisterRouter.scala:87:24] ); // @[TileClockGater.scala:33:53] assign auto_clock_gater_in_1_a_ready = auto_clock_gater_in_1_d_ready; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_valid = auto_clock_gater_in_1_a_valid; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_opcode = monitor_io_in_d_bits_opcode; // @[RegisterRouter.scala:105:19] assign auto_clock_gater_in_1_d_bits_size = auto_clock_gater_in_1_a_bits_size; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_source = auto_clock_gater_in_1_a_bits_source; // @[TileClockGater.scala:27:25] assign auto_clock_gater_in_1_d_bits_data = {63'h0, _out_T_1 & _regs_0_io_q}; // @[RegisterRouter.scala:87:24] assign auto_clock_gater_out_member_allClocks_uncore_clock = auto_clock_gater_in_0_member_allClocks_uncore_clock; // @[TileClockGater.scala:27:25] assign auto_clock_gater_out_member_allClocks_uncore_reset = auto_clock_gater_in_0_member_allClocks_uncore_reset; // @[TileClockGater.scala:27:25] endmodule
Generate the Verilog code corresponding to this FIRRTL code module Core : input clock : Clock input reset : Reset output io : { flip ddpath : { addr : UInt<5>, wdata : UInt<32>, validreq : UInt<1>, flip rdata : UInt<32>, resetpc : UInt<1>}, flip dcpath : { halt : UInt<1>}, mem : { req : { flip ready : UInt<1>, valid : UInt<1>, bits : { addr : UInt<32>, data : UInt<32>, fcn : UInt<1>, typ : UInt<3>}}, flip resp : { valid : UInt<1>, bits : { data : UInt<32>}}}, flip interrupt : { debug : UInt<1>, mtip : UInt<1>, msip : UInt<1>, meip : UInt<1>, lip : UInt<1>[0]}, flip hartid : UInt, flip reset_vector : UInt} inst c of CtlPath connect c.clock, clock connect c.reset, reset inst d of DatPath connect d.clock, clock connect d.reset, reset connect d.io.ctl, c.io.ctl connect c.io.dat, d.io.dat connect c.io.mem.resp, io.mem.resp connect io.mem.req.bits, c.io.mem.req.bits connect io.mem.req.valid, c.io.mem.req.valid connect c.io.mem.req.ready, io.mem.req.ready connect d.io.mem.resp, io.mem.resp connect io.mem.req.bits, d.io.mem.req.bits connect io.mem.req.valid, d.io.mem.req.valid connect d.io.mem.req.ready, io.mem.req.ready connect io.mem.req.valid, c.io.mem.req.valid connect io.mem.req.bits.fcn, c.io.mem.req.bits.fcn connect io.mem.req.bits.typ, c.io.mem.req.bits.typ connect d.io.ddpath, io.ddpath connect c.io.dcpath, io.dcpath connect d.io.interrupt.meip, io.interrupt.meip connect d.io.interrupt.msip, io.interrupt.msip connect d.io.interrupt.mtip, io.interrupt.mtip connect d.io.interrupt.debug, io.interrupt.debug connect d.io.hartid, io.hartid connect d.io.reset_vector, io.reset_vector
module Core( // @[core.scala:32:7] input clock, // @[core.scala:32:7] input reset, // @[core.scala:32:7] input io_mem_req_ready, // @[core.scala:34:14] output io_mem_req_valid, // @[core.scala:34:14] output [31:0] io_mem_req_bits_addr, // @[core.scala:34:14] output [31:0] io_mem_req_bits_data, // @[core.scala:34:14] output io_mem_req_bits_fcn, // @[core.scala:34:14] output [2:0] io_mem_req_bits_typ, // @[core.scala:34:14] input io_mem_resp_valid, // @[core.scala:34:14] input [31:0] io_mem_resp_bits_data, // @[core.scala:34:14] input io_interrupt_debug, // @[core.scala:34:14] input io_interrupt_mtip, // @[core.scala:34:14] input io_interrupt_msip, // @[core.scala:34:14] input io_interrupt_meip, // @[core.scala:34:14] input io_hartid // @[core.scala:34:14] ); wire [31:0] _d_io_dat_inst; // @[core.scala:36:18] wire _d_io_dat_alu_zero; // @[core.scala:36:18] wire _d_io_dat_csr_eret; // @[core.scala:36:18] wire _d_io_dat_interrupt; // @[core.scala:36:18] wire _d_io_dat_addr_exception; // @[core.scala:36:18] wire [2:0] _c_io_ctl_csr_cmd; // @[core.scala:35:18] wire _c_io_ctl_ld_ir; // @[core.scala:35:18] wire [2:0] _c_io_ctl_reg_sel; // @[core.scala:35:18] wire _c_io_ctl_reg_wr; // @[core.scala:35:18] wire _c_io_ctl_en_reg; // @[core.scala:35:18] wire _c_io_ctl_ld_a; // @[core.scala:35:18] wire _c_io_ctl_ld_b; // @[core.scala:35:18] wire [4:0] _c_io_ctl_alu_op; // @[core.scala:35:18] wire _c_io_ctl_en_alu; // @[core.scala:35:18] wire _c_io_ctl_ld_ma; // @[core.scala:35:18] wire _c_io_ctl_mem_wr; // @[core.scala:35:18] wire _c_io_ctl_en_mem; // @[core.scala:35:18] wire [2:0] _c_io_ctl_msk_sel; // @[core.scala:35:18] wire [2:0] _c_io_ctl_is_sel; // @[core.scala:35:18] wire _c_io_ctl_en_imm; // @[core.scala:35:18] wire [7:0] _c_io_ctl_upc; // @[core.scala:35:18] wire _c_io_ctl_upc_is_fetch; // @[core.scala:35:18] wire _c_io_ctl_illegal_exception; // @[core.scala:35:18] wire _c_io_ctl_exception; // @[core.scala:35:18] wire _c_io_ctl_retire; // @[core.scala:35:18] wire io_mem_req_ready_0 = io_mem_req_ready; // @[core.scala:32:7] wire io_mem_resp_valid_0 = io_mem_resp_valid; // @[core.scala:32:7] wire [31:0] io_mem_resp_bits_data_0 = io_mem_resp_bits_data; // @[core.scala:32:7] wire io_interrupt_debug_0 = io_interrupt_debug; // @[core.scala:32:7] wire io_interrupt_mtip_0 = io_interrupt_mtip; // @[core.scala:32:7] wire io_interrupt_msip_0 = io_interrupt_msip; // @[core.scala:32:7] wire io_interrupt_meip_0 = io_interrupt_meip; // @[core.scala:32:7] wire io_hartid_0 = io_hartid; // @[core.scala:32:7] wire [31:0] io_reset_vector = 32'h10000; // @[core.scala:32:7, :34:14, :36:18] wire io_ddpath_validreq = 1'h0; // @[core.scala:32:7, :34:14, :35:18, :36:18] wire io_ddpath_resetpc = 1'h0; // @[core.scala:32:7, :34:14, :35:18, :36:18] wire io_dcpath_halt = 1'h0; // @[core.scala:32:7, :34:14, :35:18, :36:18] wire [31:0] io_ddpath_wdata = 32'h0; // @[core.scala:32:7, :34:14, :35:18, :36:18] wire [31:0] io_ddpath_rdata = 32'h0; // @[core.scala:32:7, :34:14, :35:18, :36:18] wire [4:0] io_ddpath_addr = 5'h0; // @[core.scala:32:7, :34:14, :36:18] wire [31:0] io_mem_req_bits_addr_0; // @[core.scala:32:7] wire [31:0] io_mem_req_bits_data_0; // @[core.scala:32:7] wire io_mem_req_bits_fcn_0; // @[core.scala:32:7] wire [2:0] io_mem_req_bits_typ_0; // @[core.scala:32:7] wire io_mem_req_valid_0; // @[core.scala:32:7] CtlPath c ( // @[core.scala:35:18] .clock (clock), .reset (reset), .io_mem_req_ready (io_mem_req_ready_0), // @[core.scala:32:7] .io_mem_req_valid (io_mem_req_valid_0), .io_mem_req_bits_fcn (io_mem_req_bits_fcn_0), .io_mem_req_bits_typ (io_mem_req_bits_typ_0), .io_mem_resp_valid (io_mem_resp_valid_0), // @[core.scala:32:7] .io_mem_resp_bits_data (io_mem_resp_bits_data_0), // @[core.scala:32:7] .io_dat_inst (_d_io_dat_inst), // @[core.scala:36:18] .io_dat_alu_zero (_d_io_dat_alu_zero), // @[core.scala:36:18] .io_dat_csr_eret (_d_io_dat_csr_eret), // @[core.scala:36:18] .io_dat_interrupt (_d_io_dat_interrupt), // @[core.scala:36:18] .io_dat_addr_exception (_d_io_dat_addr_exception), // @[core.scala:36:18] .io_ctl_csr_cmd (_c_io_ctl_csr_cmd), .io_ctl_ld_ir (_c_io_ctl_ld_ir), .io_ctl_reg_sel (_c_io_ctl_reg_sel), .io_ctl_reg_wr (_c_io_ctl_reg_wr), .io_ctl_en_reg (_c_io_ctl_en_reg), .io_ctl_ld_a (_c_io_ctl_ld_a), .io_ctl_ld_b (_c_io_ctl_ld_b), .io_ctl_alu_op (_c_io_ctl_alu_op), .io_ctl_en_alu (_c_io_ctl_en_alu), .io_ctl_ld_ma (_c_io_ctl_ld_ma), .io_ctl_mem_wr (_c_io_ctl_mem_wr), .io_ctl_en_mem (_c_io_ctl_en_mem), .io_ctl_msk_sel (_c_io_ctl_msk_sel), .io_ctl_is_sel (_c_io_ctl_is_sel), .io_ctl_en_imm (_c_io_ctl_en_imm), .io_ctl_upc (_c_io_ctl_upc), .io_ctl_upc_is_fetch (_c_io_ctl_upc_is_fetch), .io_ctl_illegal_exception (_c_io_ctl_illegal_exception), .io_ctl_exception (_c_io_ctl_exception), .io_ctl_retire (_c_io_ctl_retire) ); // @[core.scala:35:18] DatPath d ( // @[core.scala:36:18] .clock (clock), .reset (reset), .io_mem_req_ready (io_mem_req_ready_0), // @[core.scala:32:7] .io_mem_req_bits_addr (io_mem_req_bits_addr_0), .io_mem_req_bits_data (io_mem_req_bits_data_0), .io_mem_resp_valid (io_mem_resp_valid_0), // @[core.scala:32:7] .io_mem_resp_bits_data (io_mem_resp_bits_data_0), // @[core.scala:32:7] .io_ctl_csr_cmd (_c_io_ctl_csr_cmd), // @[core.scala:35:18] .io_ctl_ld_ir (_c_io_ctl_ld_ir), // @[core.scala:35:18] .io_ctl_reg_sel (_c_io_ctl_reg_sel), // @[core.scala:35:18] .io_ctl_reg_wr (_c_io_ctl_reg_wr), // @[core.scala:35:18] .io_ctl_en_reg (_c_io_ctl_en_reg), // @[core.scala:35:18] .io_ctl_ld_a (_c_io_ctl_ld_a), // @[core.scala:35:18] .io_ctl_ld_b (_c_io_ctl_ld_b), // @[core.scala:35:18] .io_ctl_alu_op (_c_io_ctl_alu_op), // @[core.scala:35:18] .io_ctl_en_alu (_c_io_ctl_en_alu), // @[core.scala:35:18] .io_ctl_ld_ma (_c_io_ctl_ld_ma), // @[core.scala:35:18] .io_ctl_mem_wr (_c_io_ctl_mem_wr), // @[core.scala:35:18] .io_ctl_en_mem (_c_io_ctl_en_mem), // @[core.scala:35:18] .io_ctl_msk_sel (_c_io_ctl_msk_sel), // @[core.scala:35:18] .io_ctl_is_sel (_c_io_ctl_is_sel), // @[core.scala:35:18] .io_ctl_en_imm (_c_io_ctl_en_imm), // @[core.scala:35:18] .io_ctl_upc (_c_io_ctl_upc), // @[core.scala:35:18] .io_ctl_upc_is_fetch (_c_io_ctl_upc_is_fetch), // @[core.scala:35:18] .io_ctl_illegal_exception (_c_io_ctl_illegal_exception), // @[core.scala:35:18] .io_ctl_exception (_c_io_ctl_exception), // @[core.scala:35:18] .io_ctl_retire (_c_io_ctl_retire), // @[core.scala:35:18] .io_dat_inst (_d_io_dat_inst), .io_dat_alu_zero (_d_io_dat_alu_zero), .io_dat_csr_eret (_d_io_dat_csr_eret), .io_dat_interrupt (_d_io_dat_interrupt), .io_dat_addr_exception (_d_io_dat_addr_exception), .io_interrupt_debug (io_interrupt_debug_0), // @[core.scala:32:7] .io_interrupt_mtip (io_interrupt_mtip_0), // @[core.scala:32:7] .io_interrupt_msip (io_interrupt_msip_0), // @[core.scala:32:7] .io_interrupt_meip (io_interrupt_meip_0), // @[core.scala:32:7] .io_hartid (io_hartid_0) // @[core.scala:32:7] ); // @[core.scala:36:18] assign io_mem_req_valid = io_mem_req_valid_0; // @[core.scala:32:7] assign io_mem_req_bits_addr = io_mem_req_bits_addr_0; // @[core.scala:32:7] assign io_mem_req_bits_data = io_mem_req_bits_data_0; // @[core.scala:32:7] assign io_mem_req_bits_fcn = io_mem_req_bits_fcn_0; // @[core.scala:32:7] assign io_mem_req_bits_typ = io_mem_req_bits_typ_0; // @[core.scala:32:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module PE_164 : input clock : Clock input reset : Reset output io : { flip inR : SInt<8>, flip inD : SInt<8>, outL : SInt<8>, outU : SInt<8>, flip dir : UInt<1>, flip en : UInt<1>} node _reg_T = eq(io.dir, UInt<1>(0h0)) node _reg_T_1 = mux(_reg_T, io.inR, io.inD) reg reg : SInt<8>, clock when io.en : connect reg, _reg_T_1 connect io.outU, reg connect io.outL, reg
module PE_164( // @[Transposer.scala:100:9] input clock, // @[Transposer.scala:100:9] input reset, // @[Transposer.scala:100:9] input [7:0] io_inR, // @[Transposer.scala:101:16] input [7:0] io_inD, // @[Transposer.scala:101:16] output [7:0] io_outL, // @[Transposer.scala:101:16] output [7:0] io_outU, // @[Transposer.scala:101:16] input io_dir, // @[Transposer.scala:101:16] input io_en // @[Transposer.scala:101:16] ); wire [7:0] io_inR_0 = io_inR; // @[Transposer.scala:100:9] wire [7:0] io_inD_0 = io_inD; // @[Transposer.scala:100:9] wire io_dir_0 = io_dir; // @[Transposer.scala:100:9] wire io_en_0 = io_en; // @[Transposer.scala:100:9] wire [7:0] io_outL_0; // @[Transposer.scala:100:9] wire [7:0] io_outU_0; // @[Transposer.scala:100:9] wire _reg_T = ~io_dir_0; // @[Transposer.scala:100:9, :110:36] wire [7:0] _reg_T_1 = _reg_T ? io_inR_0 : io_inD_0; // @[Transposer.scala:100:9, :110:{28,36}] reg [7:0] reg_0; // @[Transposer.scala:110:24] assign io_outL_0 = reg_0; // @[Transposer.scala:100:9, :110:24] assign io_outU_0 = reg_0; // @[Transposer.scala:100:9, :110:24] always @(posedge clock) begin // @[Transposer.scala:100:9] if (io_en_0) // @[Transposer.scala:100:9] reg_0 <= _reg_T_1; // @[Transposer.scala:110:{24,28}] always @(posedge) assign io_outL = io_outL_0; // @[Transposer.scala:100:9] assign io_outU = io_outU_0; // @[Transposer.scala:100:9] endmodule
Generate the Verilog code corresponding to this FIRRTL code module AsyncValidSync_27 : output io : { flip in : UInt<1>, out : UInt<1>} input clock : Clock input reset : AsyncReset inst io_out_source_valid of AsyncResetSynchronizerShiftReg_w1_d3_i0_27 connect io_out_source_valid.clock, clock connect io_out_source_valid.reset, reset connect io_out_source_valid.io.d, io.in wire _io_out_WIRE : UInt<1> connect _io_out_WIRE, io_out_source_valid.io.q connect io.out, _io_out_WIRE
module AsyncValidSync_27( // @[AsyncQueue.scala:58:7] input io_in, // @[AsyncQueue.scala:59:14] output io_out, // @[AsyncQueue.scala:59:14] input clock, // @[AsyncQueue.scala:63:17] input reset // @[AsyncQueue.scala:64:17] ); wire io_in_0 = io_in; // @[AsyncQueue.scala:58:7] wire _io_out_WIRE; // @[ShiftReg.scala:48:24] wire io_out_0; // @[AsyncQueue.scala:58:7] assign io_out_0 = _io_out_WIRE; // @[ShiftReg.scala:48:24] AsyncResetSynchronizerShiftReg_w1_d3_i0_27 io_out_source_valid ( // @[ShiftReg.scala:45:23] .clock (clock), .reset (reset), .io_d (io_in_0), // @[AsyncQueue.scala:58:7] .io_q (_io_out_WIRE) ); // @[ShiftReg.scala:45:23] assign io_out = io_out_0; // @[AsyncQueue.scala:58:7] endmodule
Generate the Verilog code corresponding to this FIRRTL code module DivUnit : input clock : Clock input reset : Reset output io : { flip kill : UInt<1>, flip req : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, rs1_data : UInt<64>, rs2_data : UInt<64>, rs3_data : UInt<64>, ftq_info : { valid : UInt<1>, entry : { cfi_idx : { valid : UInt<1>, bits : UInt<2>}, cfi_taken : UInt<1>, cfi_mispredicted : UInt<1>, cfi_type : UInt<3>, br_mask : UInt<4>, cfi_is_call : UInt<1>, cfi_is_ret : UInt<1>, cfi_npc_plus4 : UInt<1>, ras_top : UInt<40>, ras_idx : UInt<5>, start_bank : UInt<1>}, ghist : { old_history : UInt<64>, current_saw_branch_not_taken : UInt<1>, new_saw_branch_not_taken : UInt<1>, new_saw_branch_taken : UInt<1>, ras_idx : UInt<5>}, pc : UInt<40>}[2], pred_data : UInt<1>, imm_data : UInt<64>}}, resp : { flip ready : UInt<1>, valid : UInt<1>, bits : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, data : UInt<64>, predicated : UInt<1>, fflags : { valid : UInt<1>, bits : UInt<5>}}}, flip brupdate : { b1 : { resolve_mask : UInt<12>, mispredict_mask : UInt<12>}, b2 : { uop : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}, mispredict : UInt<1>, taken : UInt<1>, cfi_type : UInt<3>, pc_sel : UInt<2>, jalr_target : UInt<40>, target_offset : SInt<21>}}} connect io.resp.bits.fflags.valid, UInt<1>(0h0) invalidate io.resp.bits.fflags.bits connect io.resp.bits.predicated, UInt<1>(0h0) inst div of MulDiv connect div.clock, clock connect div.reset, reset reg req : { valid : UInt<1>, bits : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>}}, clock node _T = and(io.req.ready, io.req.valid) when _T : node _req_valid_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask) node _req_valid_T_1 = neq(_req_valid_T, UInt<1>(0h0)) node _req_valid_T_2 = or(_req_valid_T_1, io.kill) node _req_valid_T_3 = eq(_req_valid_T_2, UInt<1>(0h0)) connect req.valid, _req_valid_T_3 wire req_bits_out : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect req_bits_out, io.req.bits.uop node _req_bits_out_br_mask_T = not(io.brupdate.b1.resolve_mask) node _req_bits_out_br_mask_T_1 = and(io.req.bits.uop.br_mask, _req_bits_out_br_mask_T) connect req_bits_out.br_mask, _req_bits_out_br_mask_T_1 connect req.bits, req_bits_out else : node _req_valid_T_4 = and(io.brupdate.b1.mispredict_mask, req.bits.br_mask) node _req_valid_T_5 = neq(_req_valid_T_4, UInt<1>(0h0)) node _req_valid_T_6 = or(_req_valid_T_5, io.kill) node _req_valid_T_7 = eq(_req_valid_T_6, UInt<1>(0h0)) node _req_valid_T_8 = and(_req_valid_T_7, req.valid) connect req.valid, _req_valid_T_8 wire req_bits_out_1 : { inst : UInt<32>, debug_inst : UInt<32>, is_rvc : UInt<1>, debug_pc : UInt<40>, iq_type : UInt<1>[4], fu_code : UInt<1>[10], iw_issued : UInt<1>, iw_issued_partial_agen : UInt<1>, iw_issued_partial_dgen : UInt<1>, iw_p1_speculative_child : UInt<2>, iw_p2_speculative_child : UInt<2>, iw_p1_bypass_hint : UInt<1>, iw_p2_bypass_hint : UInt<1>, iw_p3_bypass_hint : UInt<1>, dis_col_sel : UInt<2>, br_mask : UInt<12>, br_tag : UInt<4>, br_type : UInt<4>, is_sfb : UInt<1>, is_fence : UInt<1>, is_fencei : UInt<1>, is_sfence : UInt<1>, is_amo : UInt<1>, is_eret : UInt<1>, is_sys_pc2epc : UInt<1>, is_rocc : UInt<1>, is_mov : UInt<1>, ftq_idx : UInt<5>, edge_inst : UInt<1>, pc_lob : UInt<6>, taken : UInt<1>, imm_rename : UInt<1>, imm_sel : UInt<3>, pimm : UInt<5>, imm_packed : UInt<20>, op1_sel : UInt<2>, op2_sel : UInt<3>, fp_ctrl : { ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, typeTagIn : UInt<2>, typeTagOut : UInt<2>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, wflags : UInt<1>, vec : UInt<1>}, rob_idx : UInt<6>, ldq_idx : UInt<4>, stq_idx : UInt<4>, rxq_idx : UInt<2>, pdst : UInt<7>, prs1 : UInt<7>, prs2 : UInt<7>, prs3 : UInt<7>, ppred : UInt<5>, prs1_busy : UInt<1>, prs2_busy : UInt<1>, prs3_busy : UInt<1>, ppred_busy : UInt<1>, stale_pdst : UInt<7>, exception : UInt<1>, exc_cause : UInt<64>, mem_cmd : UInt<5>, mem_size : UInt<2>, mem_signed : UInt<1>, uses_ldq : UInt<1>, uses_stq : UInt<1>, is_unique : UInt<1>, flush_on_commit : UInt<1>, csr_cmd : UInt<3>, ldst_is_rs1 : UInt<1>, ldst : UInt<6>, lrs1 : UInt<6>, lrs2 : UInt<6>, lrs3 : UInt<6>, dst_rtype : UInt<2>, lrs1_rtype : UInt<2>, lrs2_rtype : UInt<2>, frs3_en : UInt<1>, fcn_dw : UInt<1>, fcn_op : UInt<5>, fp_val : UInt<1>, fp_rm : UInt<3>, fp_typ : UInt<2>, xcpt_pf_if : UInt<1>, xcpt_ae_if : UInt<1>, xcpt_ma_if : UInt<1>, bp_debug_if : UInt<1>, bp_xcpt_if : UInt<1>, debug_fsrc : UInt<3>, debug_tsrc : UInt<3>} connect req_bits_out_1, req.bits node _req_bits_out_br_mask_T_2 = not(io.brupdate.b1.resolve_mask) node _req_bits_out_br_mask_T_3 = and(req.bits.br_mask, _req_bits_out_br_mask_T_2) connect req_bits_out_1.br_mask, _req_bits_out_br_mask_T_3 connect req.bits, req_bits_out_1 node _T_1 = asUInt(reset) when _T_1 : connect req.valid, UInt<1>(0h0) node _div_io_req_valid_T = and(io.brupdate.b1.mispredict_mask, io.req.bits.uop.br_mask) node _div_io_req_valid_T_1 = neq(_div_io_req_valid_T, UInt<1>(0h0)) node _div_io_req_valid_T_2 = or(_div_io_req_valid_T_1, io.kill) node _div_io_req_valid_T_3 = eq(_div_io_req_valid_T_2, UInt<1>(0h0)) node _div_io_req_valid_T_4 = and(io.req.valid, _div_io_req_valid_T_3) connect div.io.req.valid, _div_io_req_valid_T_4 connect div.io.req.bits.dw, io.req.bits.uop.fcn_dw connect div.io.req.bits.fn, io.req.bits.uop.fcn_op connect div.io.req.bits.in1, io.req.bits.rs1_data connect div.io.req.bits.in2, io.req.bits.rs2_data invalidate div.io.req.bits.tag node _io_req_ready_T = eq(req.valid, UInt<1>(0h0)) node _io_req_ready_T_1 = and(div.io.req.ready, _io_req_ready_T) connect io.req.ready, _io_req_ready_T_1 node _div_io_kill_T = and(io.brupdate.b1.mispredict_mask, req.bits.br_mask) node _div_io_kill_T_1 = neq(_div_io_kill_T, UInt<1>(0h0)) node _div_io_kill_T_2 = or(_div_io_kill_T_1, io.kill) node _div_io_kill_T_3 = and(req.valid, _div_io_kill_T_2) connect div.io.kill, _div_io_kill_T_3 node _io_resp_valid_T = and(div.io.resp.valid, req.valid) connect io.resp.valid, _io_resp_valid_T connect div.io.resp.ready, io.resp.ready node _io_resp_valid_T_1 = and(div.io.resp.valid, req.valid) connect io.resp.valid, _io_resp_valid_T_1 connect io.resp.bits.data, div.io.resp.bits.data connect io.resp.bits.uop, req.bits node _T_2 = and(io.resp.ready, io.resp.valid) when _T_2 : connect req.valid, UInt<1>(0h0)
module DivUnit( // @[functional-unit.scala:393:7] input clock, // @[functional-unit.scala:393:7] input reset, // @[functional-unit.scala:393:7] input io_kill, // @[functional-unit.scala:105:14] output io_req_ready, // @[functional-unit.scala:105:14] input io_req_valid, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_req_bits_uop_debug_inst, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_req_bits_uop_debug_pc, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_req_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_req_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [11:0] io_req_bits_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_br_type, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfb, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_fencei, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sfence, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_amo, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_eret, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_rocc, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_req_bits_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_pc_lob, // @[functional-unit.scala:105:14] input io_req_bits_uop_taken, // @[functional-unit.scala:105:14] input io_req_bits_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_req_bits_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_op2_sel, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_rob_idx, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] input [3:0] io_req_bits_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_ppred, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_req_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_req_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_req_bits_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_mem_size, // @[functional-unit.scala:105:14] input io_req_bits_uop_mem_signed, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_req_bits_uop_uses_stq, // @[functional-unit.scala:105:14] input io_req_bits_uop_is_unique, // @[functional-unit.scala:105:14] input io_req_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_req_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_req_bits_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_req_bits_uop_frs3_en, // @[functional-unit.scala:105:14] input io_req_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_req_bits_uop_fcn_op, // @[functional-unit.scala:105:14] input io_req_bits_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_req_bits_uop_fp_typ, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_req_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_req_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs1_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_rs2_data, // @[functional-unit.scala:105:14] input [63:0] io_req_bits_imm_data, // @[functional-unit.scala:105:14] input io_resp_ready, // @[functional-unit.scala:105:14] output io_resp_valid, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_inst, // @[functional-unit.scala:105:14] output [31:0] io_resp_bits_uop_debug_inst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rvc, // @[functional-unit.scala:105:14] output [39:0] io_resp_bits_uop_debug_pc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iq_type_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_0, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_4, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_5, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_6, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_7, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_8, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fu_code_9, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_dis_col_sel, // @[functional-unit.scala:105:14] output [11:0] io_resp_bits_uop_br_mask, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_tag, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_br_type, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfb, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_fencei, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sfence, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_amo, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_eret, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_rocc, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_mov, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ftq_idx, // @[functional-unit.scala:105:14] output io_resp_bits_uop_edge_inst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_pc_lob, // @[functional-unit.scala:105:14] output io_resp_bits_uop_taken, // @[functional-unit.scala:105:14] output io_resp_bits_uop_imm_rename, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_imm_sel, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_pimm, // @[functional-unit.scala:105:14] output [19:0] io_resp_bits_uop_imm_packed, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_op1_sel, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_op2_sel, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_rob_idx, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_ldq_idx, // @[functional-unit.scala:105:14] output [3:0] io_resp_bits_uop_stq_idx, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_rxq_idx, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_pdst, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs1, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs2, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_prs3, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_ppred, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs1_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs2_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_prs3_busy, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ppred_busy, // @[functional-unit.scala:105:14] output [6:0] io_resp_bits_uop_stale_pdst, // @[functional-unit.scala:105:14] output io_resp_bits_uop_exception, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_uop_exc_cause, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_mem_cmd, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_mem_size, // @[functional-unit.scala:105:14] output io_resp_bits_uop_mem_signed, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_ldq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_uses_stq, // @[functional-unit.scala:105:14] output io_resp_bits_uop_is_unique, // @[functional-unit.scala:105:14] output io_resp_bits_uop_flush_on_commit, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_csr_cmd, // @[functional-unit.scala:105:14] output io_resp_bits_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_ldst, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs1, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs2, // @[functional-unit.scala:105:14] output [5:0] io_resp_bits_uop_lrs3, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_dst_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs1_rtype, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_lrs2_rtype, // @[functional-unit.scala:105:14] output io_resp_bits_uop_frs3_en, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fcn_dw, // @[functional-unit.scala:105:14] output [4:0] io_resp_bits_uop_fcn_op, // @[functional-unit.scala:105:14] output io_resp_bits_uop_fp_val, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_fp_rm, // @[functional-unit.scala:105:14] output [1:0] io_resp_bits_uop_fp_typ, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_debug_if, // @[functional-unit.scala:105:14] output io_resp_bits_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_fsrc, // @[functional-unit.scala:105:14] output [2:0] io_resp_bits_uop_debug_tsrc, // @[functional-unit.scala:105:14] output [63:0] io_resp_bits_data, // @[functional-unit.scala:105:14] input [11:0] io_brupdate_b1_resolve_mask, // @[functional-unit.scala:105:14] input [11:0] io_brupdate_b1_mispredict_mask, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_inst, // @[functional-unit.scala:105:14] input [31:0] io_brupdate_b2_uop_debug_inst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rvc, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_uop_debug_pc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iq_type_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_0, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_4, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_5, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_6, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_7, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_8, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fu_code_9, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_agen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_issued_partial_dgen, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_iw_p1_speculative_child, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_iw_p2_speculative_child, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p1_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p2_bypass_hint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_iw_p3_bypass_hint, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_dis_col_sel, // @[functional-unit.scala:105:14] input [11:0] io_brupdate_b2_uop_br_mask, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_tag, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_br_type, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfb, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_fencei, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sfence, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_amo, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_eret, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_sys_pc2epc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_rocc, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_mov, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ftq_idx, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_edge_inst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_pc_lob, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_taken, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_imm_rename, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_imm_sel, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_pimm, // @[functional-unit.scala:105:14] input [19:0] io_brupdate_b2_uop_imm_packed, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_op1_sel, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_op2_sel, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ldst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wen, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren1, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren2, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_ren3, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap12, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_swap23, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fromint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_toint, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fastpipe, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_fma, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_div, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_sqrt, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_wflags, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_ctrl_vec, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_rob_idx, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_ldq_idx, // @[functional-unit.scala:105:14] input [3:0] io_brupdate_b2_uop_stq_idx, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_rxq_idx, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_pdst, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs1, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs2, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_prs3, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_ppred, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs1_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs2_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_prs3_busy, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ppred_busy, // @[functional-unit.scala:105:14] input [6:0] io_brupdate_b2_uop_stale_pdst, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_exception, // @[functional-unit.scala:105:14] input [63:0] io_brupdate_b2_uop_exc_cause, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_mem_cmd, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_mem_size, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_mem_signed, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_ldq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_uses_stq, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_is_unique, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_flush_on_commit, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_csr_cmd, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_ldst_is_rs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_ldst, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs1, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs2, // @[functional-unit.scala:105:14] input [5:0] io_brupdate_b2_uop_lrs3, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_dst_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs1_rtype, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_lrs2_rtype, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_frs3_en, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fcn_dw, // @[functional-unit.scala:105:14] input [4:0] io_brupdate_b2_uop_fcn_op, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_fp_val, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_fp_rm, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_uop_fp_typ, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_pf_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ae_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_xcpt_ma_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_debug_if, // @[functional-unit.scala:105:14] input io_brupdate_b2_uop_bp_xcpt_if, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_fsrc, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_uop_debug_tsrc, // @[functional-unit.scala:105:14] input io_brupdate_b2_mispredict, // @[functional-unit.scala:105:14] input io_brupdate_b2_taken, // @[functional-unit.scala:105:14] input [2:0] io_brupdate_b2_cfi_type, // @[functional-unit.scala:105:14] input [1:0] io_brupdate_b2_pc_sel, // @[functional-unit.scala:105:14] input [39:0] io_brupdate_b2_jalr_target, // @[functional-unit.scala:105:14] input [20:0] io_brupdate_b2_target_offset // @[functional-unit.scala:105:14] ); wire _div_io_req_ready; // @[functional-unit.scala:399:19] wire _div_io_resp_valid; // @[functional-unit.scala:399:19] wire io_kill_0 = io_kill; // @[functional-unit.scala:393:7] wire io_req_valid_0 = io_req_valid; // @[functional-unit.scala:393:7] wire [31:0] io_req_bits_uop_inst_0 = io_req_bits_uop_inst; // @[functional-unit.scala:393:7] wire [31:0] io_req_bits_uop_debug_inst_0 = io_req_bits_uop_debug_inst; // @[functional-unit.scala:393:7] wire io_req_bits_uop_is_rvc_0 = io_req_bits_uop_is_rvc; // @[functional-unit.scala:393:7] wire [39:0] io_req_bits_uop_debug_pc_0 = io_req_bits_uop_debug_pc; // @[functional-unit.scala:393:7] wire io_req_bits_uop_iq_type_0_0 = io_req_bits_uop_iq_type_0; // @[functional-unit.scala:393:7] wire io_req_bits_uop_iq_type_1_0 = io_req_bits_uop_iq_type_1; // @[functional-unit.scala:393:7] wire io_req_bits_uop_iq_type_2_0 = io_req_bits_uop_iq_type_2; // @[functional-unit.scala:393:7] wire io_req_bits_uop_iq_type_3_0 = io_req_bits_uop_iq_type_3; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fu_code_0_0 = io_req_bits_uop_fu_code_0; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fu_code_1_0 = io_req_bits_uop_fu_code_1; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fu_code_2_0 = io_req_bits_uop_fu_code_2; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fu_code_3_0 = io_req_bits_uop_fu_code_3; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fu_code_4_0 = io_req_bits_uop_fu_code_4; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fu_code_5_0 = io_req_bits_uop_fu_code_5; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fu_code_6_0 = io_req_bits_uop_fu_code_6; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fu_code_7_0 = io_req_bits_uop_fu_code_7; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fu_code_8_0 = io_req_bits_uop_fu_code_8; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fu_code_9_0 = io_req_bits_uop_fu_code_9; // @[functional-unit.scala:393:7] wire io_req_bits_uop_iw_issued_0 = io_req_bits_uop_iw_issued; // @[functional-unit.scala:393:7] wire io_req_bits_uop_iw_issued_partial_agen_0 = io_req_bits_uop_iw_issued_partial_agen; // @[functional-unit.scala:393:7] wire io_req_bits_uop_iw_issued_partial_dgen_0 = io_req_bits_uop_iw_issued_partial_dgen; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_iw_p1_speculative_child_0 = io_req_bits_uop_iw_p1_speculative_child; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_iw_p2_speculative_child_0 = io_req_bits_uop_iw_p2_speculative_child; // @[functional-unit.scala:393:7] wire io_req_bits_uop_iw_p1_bypass_hint_0 = io_req_bits_uop_iw_p1_bypass_hint; // @[functional-unit.scala:393:7] wire io_req_bits_uop_iw_p2_bypass_hint_0 = io_req_bits_uop_iw_p2_bypass_hint; // @[functional-unit.scala:393:7] wire io_req_bits_uop_iw_p3_bypass_hint_0 = io_req_bits_uop_iw_p3_bypass_hint; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_dis_col_sel_0 = io_req_bits_uop_dis_col_sel; // @[functional-unit.scala:393:7] wire [11:0] io_req_bits_uop_br_mask_0 = io_req_bits_uop_br_mask; // @[functional-unit.scala:393:7] wire [3:0] io_req_bits_uop_br_tag_0 = io_req_bits_uop_br_tag; // @[functional-unit.scala:393:7] wire [3:0] io_req_bits_uop_br_type_0 = io_req_bits_uop_br_type; // @[functional-unit.scala:393:7] wire io_req_bits_uop_is_sfb_0 = io_req_bits_uop_is_sfb; // @[functional-unit.scala:393:7] wire io_req_bits_uop_is_fence_0 = io_req_bits_uop_is_fence; // @[functional-unit.scala:393:7] wire io_req_bits_uop_is_fencei_0 = io_req_bits_uop_is_fencei; // @[functional-unit.scala:393:7] wire io_req_bits_uop_is_sfence_0 = io_req_bits_uop_is_sfence; // @[functional-unit.scala:393:7] wire io_req_bits_uop_is_amo_0 = io_req_bits_uop_is_amo; // @[functional-unit.scala:393:7] wire io_req_bits_uop_is_eret_0 = io_req_bits_uop_is_eret; // @[functional-unit.scala:393:7] wire io_req_bits_uop_is_sys_pc2epc_0 = io_req_bits_uop_is_sys_pc2epc; // @[functional-unit.scala:393:7] wire io_req_bits_uop_is_rocc_0 = io_req_bits_uop_is_rocc; // @[functional-unit.scala:393:7] wire io_req_bits_uop_is_mov_0 = io_req_bits_uop_is_mov; // @[functional-unit.scala:393:7] wire [4:0] io_req_bits_uop_ftq_idx_0 = io_req_bits_uop_ftq_idx; // @[functional-unit.scala:393:7] wire io_req_bits_uop_edge_inst_0 = io_req_bits_uop_edge_inst; // @[functional-unit.scala:393:7] wire [5:0] io_req_bits_uop_pc_lob_0 = io_req_bits_uop_pc_lob; // @[functional-unit.scala:393:7] wire io_req_bits_uop_taken_0 = io_req_bits_uop_taken; // @[functional-unit.scala:393:7] wire io_req_bits_uop_imm_rename_0 = io_req_bits_uop_imm_rename; // @[functional-unit.scala:393:7] wire [2:0] io_req_bits_uop_imm_sel_0 = io_req_bits_uop_imm_sel; // @[functional-unit.scala:393:7] wire [4:0] io_req_bits_uop_pimm_0 = io_req_bits_uop_pimm; // @[functional-unit.scala:393:7] wire [19:0] io_req_bits_uop_imm_packed_0 = io_req_bits_uop_imm_packed; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_op1_sel_0 = io_req_bits_uop_op1_sel; // @[functional-unit.scala:393:7] wire [2:0] io_req_bits_uop_op2_sel_0 = io_req_bits_uop_op2_sel; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_ldst_0 = io_req_bits_uop_fp_ctrl_ldst; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_wen_0 = io_req_bits_uop_fp_ctrl_wen; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_ren1_0 = io_req_bits_uop_fp_ctrl_ren1; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_ren2_0 = io_req_bits_uop_fp_ctrl_ren2; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_ren3_0 = io_req_bits_uop_fp_ctrl_ren3; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_swap12_0 = io_req_bits_uop_fp_ctrl_swap12; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_swap23_0 = io_req_bits_uop_fp_ctrl_swap23; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagIn_0 = io_req_bits_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_fp_ctrl_typeTagOut_0 = io_req_bits_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_fromint_0 = io_req_bits_uop_fp_ctrl_fromint; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_toint_0 = io_req_bits_uop_fp_ctrl_toint; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_fastpipe_0 = io_req_bits_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_fma_0 = io_req_bits_uop_fp_ctrl_fma; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_div_0 = io_req_bits_uop_fp_ctrl_div; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_sqrt_0 = io_req_bits_uop_fp_ctrl_sqrt; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_wflags_0 = io_req_bits_uop_fp_ctrl_wflags; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_ctrl_vec_0 = io_req_bits_uop_fp_ctrl_vec; // @[functional-unit.scala:393:7] wire [5:0] io_req_bits_uop_rob_idx_0 = io_req_bits_uop_rob_idx; // @[functional-unit.scala:393:7] wire [3:0] io_req_bits_uop_ldq_idx_0 = io_req_bits_uop_ldq_idx; // @[functional-unit.scala:393:7] wire [3:0] io_req_bits_uop_stq_idx_0 = io_req_bits_uop_stq_idx; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_rxq_idx_0 = io_req_bits_uop_rxq_idx; // @[functional-unit.scala:393:7] wire [6:0] io_req_bits_uop_pdst_0 = io_req_bits_uop_pdst; // @[functional-unit.scala:393:7] wire [6:0] io_req_bits_uop_prs1_0 = io_req_bits_uop_prs1; // @[functional-unit.scala:393:7] wire [6:0] io_req_bits_uop_prs2_0 = io_req_bits_uop_prs2; // @[functional-unit.scala:393:7] wire [6:0] io_req_bits_uop_prs3_0 = io_req_bits_uop_prs3; // @[functional-unit.scala:393:7] wire [4:0] io_req_bits_uop_ppred_0 = io_req_bits_uop_ppred; // @[functional-unit.scala:393:7] wire io_req_bits_uop_prs1_busy_0 = io_req_bits_uop_prs1_busy; // @[functional-unit.scala:393:7] wire io_req_bits_uop_prs2_busy_0 = io_req_bits_uop_prs2_busy; // @[functional-unit.scala:393:7] wire io_req_bits_uop_prs3_busy_0 = io_req_bits_uop_prs3_busy; // @[functional-unit.scala:393:7] wire io_req_bits_uop_ppred_busy_0 = io_req_bits_uop_ppred_busy; // @[functional-unit.scala:393:7] wire [6:0] io_req_bits_uop_stale_pdst_0 = io_req_bits_uop_stale_pdst; // @[functional-unit.scala:393:7] wire io_req_bits_uop_exception_0 = io_req_bits_uop_exception; // @[functional-unit.scala:393:7] wire [63:0] io_req_bits_uop_exc_cause_0 = io_req_bits_uop_exc_cause; // @[functional-unit.scala:393:7] wire [4:0] io_req_bits_uop_mem_cmd_0 = io_req_bits_uop_mem_cmd; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_mem_size_0 = io_req_bits_uop_mem_size; // @[functional-unit.scala:393:7] wire io_req_bits_uop_mem_signed_0 = io_req_bits_uop_mem_signed; // @[functional-unit.scala:393:7] wire io_req_bits_uop_uses_ldq_0 = io_req_bits_uop_uses_ldq; // @[functional-unit.scala:393:7] wire io_req_bits_uop_uses_stq_0 = io_req_bits_uop_uses_stq; // @[functional-unit.scala:393:7] wire io_req_bits_uop_is_unique_0 = io_req_bits_uop_is_unique; // @[functional-unit.scala:393:7] wire io_req_bits_uop_flush_on_commit_0 = io_req_bits_uop_flush_on_commit; // @[functional-unit.scala:393:7] wire [2:0] io_req_bits_uop_csr_cmd_0 = io_req_bits_uop_csr_cmd; // @[functional-unit.scala:393:7] wire io_req_bits_uop_ldst_is_rs1_0 = io_req_bits_uop_ldst_is_rs1; // @[functional-unit.scala:393:7] wire [5:0] io_req_bits_uop_ldst_0 = io_req_bits_uop_ldst; // @[functional-unit.scala:393:7] wire [5:0] io_req_bits_uop_lrs1_0 = io_req_bits_uop_lrs1; // @[functional-unit.scala:393:7] wire [5:0] io_req_bits_uop_lrs2_0 = io_req_bits_uop_lrs2; // @[functional-unit.scala:393:7] wire [5:0] io_req_bits_uop_lrs3_0 = io_req_bits_uop_lrs3; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_dst_rtype_0 = io_req_bits_uop_dst_rtype; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_lrs1_rtype_0 = io_req_bits_uop_lrs1_rtype; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_lrs2_rtype_0 = io_req_bits_uop_lrs2_rtype; // @[functional-unit.scala:393:7] wire io_req_bits_uop_frs3_en_0 = io_req_bits_uop_frs3_en; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fcn_dw_0 = io_req_bits_uop_fcn_dw; // @[functional-unit.scala:393:7] wire [4:0] io_req_bits_uop_fcn_op_0 = io_req_bits_uop_fcn_op; // @[functional-unit.scala:393:7] wire io_req_bits_uop_fp_val_0 = io_req_bits_uop_fp_val; // @[functional-unit.scala:393:7] wire [2:0] io_req_bits_uop_fp_rm_0 = io_req_bits_uop_fp_rm; // @[functional-unit.scala:393:7] wire [1:0] io_req_bits_uop_fp_typ_0 = io_req_bits_uop_fp_typ; // @[functional-unit.scala:393:7] wire io_req_bits_uop_xcpt_pf_if_0 = io_req_bits_uop_xcpt_pf_if; // @[functional-unit.scala:393:7] wire io_req_bits_uop_xcpt_ae_if_0 = io_req_bits_uop_xcpt_ae_if; // @[functional-unit.scala:393:7] wire io_req_bits_uop_xcpt_ma_if_0 = io_req_bits_uop_xcpt_ma_if; // @[functional-unit.scala:393:7] wire io_req_bits_uop_bp_debug_if_0 = io_req_bits_uop_bp_debug_if; // @[functional-unit.scala:393:7] wire io_req_bits_uop_bp_xcpt_if_0 = io_req_bits_uop_bp_xcpt_if; // @[functional-unit.scala:393:7] wire [2:0] io_req_bits_uop_debug_fsrc_0 = io_req_bits_uop_debug_fsrc; // @[functional-unit.scala:393:7] wire [2:0] io_req_bits_uop_debug_tsrc_0 = io_req_bits_uop_debug_tsrc; // @[functional-unit.scala:393:7] wire [63:0] io_req_bits_rs1_data_0 = io_req_bits_rs1_data; // @[functional-unit.scala:393:7] wire [63:0] io_req_bits_rs2_data_0 = io_req_bits_rs2_data; // @[functional-unit.scala:393:7] wire [63:0] io_req_bits_imm_data_0 = io_req_bits_imm_data; // @[functional-unit.scala:393:7] wire io_resp_ready_0 = io_resp_ready; // @[functional-unit.scala:393:7] wire [11:0] io_brupdate_b1_resolve_mask_0 = io_brupdate_b1_resolve_mask; // @[functional-unit.scala:393:7] wire [11:0] io_brupdate_b1_mispredict_mask_0 = io_brupdate_b1_mispredict_mask; // @[functional-unit.scala:393:7] wire [31:0] io_brupdate_b2_uop_inst_0 = io_brupdate_b2_uop_inst; // @[functional-unit.scala:393:7] wire [31:0] io_brupdate_b2_uop_debug_inst_0 = io_brupdate_b2_uop_debug_inst; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_is_rvc_0 = io_brupdate_b2_uop_is_rvc; // @[functional-unit.scala:393:7] wire [39:0] io_brupdate_b2_uop_debug_pc_0 = io_brupdate_b2_uop_debug_pc; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_iq_type_0_0 = io_brupdate_b2_uop_iq_type_0; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_iq_type_1_0 = io_brupdate_b2_uop_iq_type_1; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_iq_type_2_0 = io_brupdate_b2_uop_iq_type_2; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_iq_type_3_0 = io_brupdate_b2_uop_iq_type_3; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fu_code_0_0 = io_brupdate_b2_uop_fu_code_0; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fu_code_1_0 = io_brupdate_b2_uop_fu_code_1; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fu_code_2_0 = io_brupdate_b2_uop_fu_code_2; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fu_code_3_0 = io_brupdate_b2_uop_fu_code_3; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fu_code_4_0 = io_brupdate_b2_uop_fu_code_4; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fu_code_5_0 = io_brupdate_b2_uop_fu_code_5; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fu_code_6_0 = io_brupdate_b2_uop_fu_code_6; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fu_code_7_0 = io_brupdate_b2_uop_fu_code_7; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fu_code_8_0 = io_brupdate_b2_uop_fu_code_8; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fu_code_9_0 = io_brupdate_b2_uop_fu_code_9; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_iw_issued_0 = io_brupdate_b2_uop_iw_issued; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_iw_issued_partial_agen_0 = io_brupdate_b2_uop_iw_issued_partial_agen; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_iw_issued_partial_dgen_0 = io_brupdate_b2_uop_iw_issued_partial_dgen; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_iw_p1_speculative_child_0 = io_brupdate_b2_uop_iw_p1_speculative_child; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_iw_p2_speculative_child_0 = io_brupdate_b2_uop_iw_p2_speculative_child; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_iw_p1_bypass_hint_0 = io_brupdate_b2_uop_iw_p1_bypass_hint; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_iw_p2_bypass_hint_0 = io_brupdate_b2_uop_iw_p2_bypass_hint; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_iw_p3_bypass_hint_0 = io_brupdate_b2_uop_iw_p3_bypass_hint; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_dis_col_sel_0 = io_brupdate_b2_uop_dis_col_sel; // @[functional-unit.scala:393:7] wire [11:0] io_brupdate_b2_uop_br_mask_0 = io_brupdate_b2_uop_br_mask; // @[functional-unit.scala:393:7] wire [3:0] io_brupdate_b2_uop_br_tag_0 = io_brupdate_b2_uop_br_tag; // @[functional-unit.scala:393:7] wire [3:0] io_brupdate_b2_uop_br_type_0 = io_brupdate_b2_uop_br_type; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_is_sfb_0 = io_brupdate_b2_uop_is_sfb; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_is_fence_0 = io_brupdate_b2_uop_is_fence; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_is_fencei_0 = io_brupdate_b2_uop_is_fencei; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_is_sfence_0 = io_brupdate_b2_uop_is_sfence; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_is_amo_0 = io_brupdate_b2_uop_is_amo; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_is_eret_0 = io_brupdate_b2_uop_is_eret; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_is_sys_pc2epc_0 = io_brupdate_b2_uop_is_sys_pc2epc; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_is_rocc_0 = io_brupdate_b2_uop_is_rocc; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_is_mov_0 = io_brupdate_b2_uop_is_mov; // @[functional-unit.scala:393:7] wire [4:0] io_brupdate_b2_uop_ftq_idx_0 = io_brupdate_b2_uop_ftq_idx; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_edge_inst_0 = io_brupdate_b2_uop_edge_inst; // @[functional-unit.scala:393:7] wire [5:0] io_brupdate_b2_uop_pc_lob_0 = io_brupdate_b2_uop_pc_lob; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_taken_0 = io_brupdate_b2_uop_taken; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_imm_rename_0 = io_brupdate_b2_uop_imm_rename; // @[functional-unit.scala:393:7] wire [2:0] io_brupdate_b2_uop_imm_sel_0 = io_brupdate_b2_uop_imm_sel; // @[functional-unit.scala:393:7] wire [4:0] io_brupdate_b2_uop_pimm_0 = io_brupdate_b2_uop_pimm; // @[functional-unit.scala:393:7] wire [19:0] io_brupdate_b2_uop_imm_packed_0 = io_brupdate_b2_uop_imm_packed; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_op1_sel_0 = io_brupdate_b2_uop_op1_sel; // @[functional-unit.scala:393:7] wire [2:0] io_brupdate_b2_uop_op2_sel_0 = io_brupdate_b2_uop_op2_sel; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_ldst_0 = io_brupdate_b2_uop_fp_ctrl_ldst; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_wen_0 = io_brupdate_b2_uop_fp_ctrl_wen; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_ren1_0 = io_brupdate_b2_uop_fp_ctrl_ren1; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_ren2_0 = io_brupdate_b2_uop_fp_ctrl_ren2; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_ren3_0 = io_brupdate_b2_uop_fp_ctrl_ren3; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_swap12_0 = io_brupdate_b2_uop_fp_ctrl_swap12; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_swap23_0 = io_brupdate_b2_uop_fp_ctrl_swap23; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagIn_0 = io_brupdate_b2_uop_fp_ctrl_typeTagIn; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_fp_ctrl_typeTagOut_0 = io_brupdate_b2_uop_fp_ctrl_typeTagOut; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_fromint_0 = io_brupdate_b2_uop_fp_ctrl_fromint; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_toint_0 = io_brupdate_b2_uop_fp_ctrl_toint; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_fastpipe_0 = io_brupdate_b2_uop_fp_ctrl_fastpipe; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_fma_0 = io_brupdate_b2_uop_fp_ctrl_fma; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_div_0 = io_brupdate_b2_uop_fp_ctrl_div; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_sqrt_0 = io_brupdate_b2_uop_fp_ctrl_sqrt; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_wflags_0 = io_brupdate_b2_uop_fp_ctrl_wflags; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_ctrl_vec_0 = io_brupdate_b2_uop_fp_ctrl_vec; // @[functional-unit.scala:393:7] wire [5:0] io_brupdate_b2_uop_rob_idx_0 = io_brupdate_b2_uop_rob_idx; // @[functional-unit.scala:393:7] wire [3:0] io_brupdate_b2_uop_ldq_idx_0 = io_brupdate_b2_uop_ldq_idx; // @[functional-unit.scala:393:7] wire [3:0] io_brupdate_b2_uop_stq_idx_0 = io_brupdate_b2_uop_stq_idx; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_rxq_idx_0 = io_brupdate_b2_uop_rxq_idx; // @[functional-unit.scala:393:7] wire [6:0] io_brupdate_b2_uop_pdst_0 = io_brupdate_b2_uop_pdst; // @[functional-unit.scala:393:7] wire [6:0] io_brupdate_b2_uop_prs1_0 = io_brupdate_b2_uop_prs1; // @[functional-unit.scala:393:7] wire [6:0] io_brupdate_b2_uop_prs2_0 = io_brupdate_b2_uop_prs2; // @[functional-unit.scala:393:7] wire [6:0] io_brupdate_b2_uop_prs3_0 = io_brupdate_b2_uop_prs3; // @[functional-unit.scala:393:7] wire [4:0] io_brupdate_b2_uop_ppred_0 = io_brupdate_b2_uop_ppred; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_prs1_busy_0 = io_brupdate_b2_uop_prs1_busy; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_prs2_busy_0 = io_brupdate_b2_uop_prs2_busy; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_prs3_busy_0 = io_brupdate_b2_uop_prs3_busy; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_ppred_busy_0 = io_brupdate_b2_uop_ppred_busy; // @[functional-unit.scala:393:7] wire [6:0] io_brupdate_b2_uop_stale_pdst_0 = io_brupdate_b2_uop_stale_pdst; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_exception_0 = io_brupdate_b2_uop_exception; // @[functional-unit.scala:393:7] wire [63:0] io_brupdate_b2_uop_exc_cause_0 = io_brupdate_b2_uop_exc_cause; // @[functional-unit.scala:393:7] wire [4:0] io_brupdate_b2_uop_mem_cmd_0 = io_brupdate_b2_uop_mem_cmd; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_mem_size_0 = io_brupdate_b2_uop_mem_size; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_mem_signed_0 = io_brupdate_b2_uop_mem_signed; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_uses_ldq_0 = io_brupdate_b2_uop_uses_ldq; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_uses_stq_0 = io_brupdate_b2_uop_uses_stq; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_is_unique_0 = io_brupdate_b2_uop_is_unique; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_flush_on_commit_0 = io_brupdate_b2_uop_flush_on_commit; // @[functional-unit.scala:393:7] wire [2:0] io_brupdate_b2_uop_csr_cmd_0 = io_brupdate_b2_uop_csr_cmd; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_ldst_is_rs1_0 = io_brupdate_b2_uop_ldst_is_rs1; // @[functional-unit.scala:393:7] wire [5:0] io_brupdate_b2_uop_ldst_0 = io_brupdate_b2_uop_ldst; // @[functional-unit.scala:393:7] wire [5:0] io_brupdate_b2_uop_lrs1_0 = io_brupdate_b2_uop_lrs1; // @[functional-unit.scala:393:7] wire [5:0] io_brupdate_b2_uop_lrs2_0 = io_brupdate_b2_uop_lrs2; // @[functional-unit.scala:393:7] wire [5:0] io_brupdate_b2_uop_lrs3_0 = io_brupdate_b2_uop_lrs3; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_dst_rtype_0 = io_brupdate_b2_uop_dst_rtype; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_lrs1_rtype_0 = io_brupdate_b2_uop_lrs1_rtype; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_lrs2_rtype_0 = io_brupdate_b2_uop_lrs2_rtype; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_frs3_en_0 = io_brupdate_b2_uop_frs3_en; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fcn_dw_0 = io_brupdate_b2_uop_fcn_dw; // @[functional-unit.scala:393:7] wire [4:0] io_brupdate_b2_uop_fcn_op_0 = io_brupdate_b2_uop_fcn_op; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_fp_val_0 = io_brupdate_b2_uop_fp_val; // @[functional-unit.scala:393:7] wire [2:0] io_brupdate_b2_uop_fp_rm_0 = io_brupdate_b2_uop_fp_rm; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_uop_fp_typ_0 = io_brupdate_b2_uop_fp_typ; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_xcpt_pf_if_0 = io_brupdate_b2_uop_xcpt_pf_if; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_xcpt_ae_if_0 = io_brupdate_b2_uop_xcpt_ae_if; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_xcpt_ma_if_0 = io_brupdate_b2_uop_xcpt_ma_if; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_bp_debug_if_0 = io_brupdate_b2_uop_bp_debug_if; // @[functional-unit.scala:393:7] wire io_brupdate_b2_uop_bp_xcpt_if_0 = io_brupdate_b2_uop_bp_xcpt_if; // @[functional-unit.scala:393:7] wire [2:0] io_brupdate_b2_uop_debug_fsrc_0 = io_brupdate_b2_uop_debug_fsrc; // @[functional-unit.scala:393:7] wire [2:0] io_brupdate_b2_uop_debug_tsrc_0 = io_brupdate_b2_uop_debug_tsrc; // @[functional-unit.scala:393:7] wire io_brupdate_b2_mispredict_0 = io_brupdate_b2_mispredict; // @[functional-unit.scala:393:7] wire io_brupdate_b2_taken_0 = io_brupdate_b2_taken; // @[functional-unit.scala:393:7] wire [2:0] io_brupdate_b2_cfi_type_0 = io_brupdate_b2_cfi_type; // @[functional-unit.scala:393:7] wire [1:0] io_brupdate_b2_pc_sel_0 = io_brupdate_b2_pc_sel; // @[functional-unit.scala:393:7] wire [39:0] io_brupdate_b2_jalr_target_0 = io_brupdate_b2_jalr_target; // @[functional-unit.scala:393:7] wire [20:0] io_brupdate_b2_target_offset_0 = io_brupdate_b2_target_offset; // @[functional-unit.scala:393:7] wire [4:0] io_req_bits_ftq_info_0_entry_ras_idx = 5'h0; // @[functional-unit.scala:393:7] wire [4:0] io_req_bits_ftq_info_0_ghist_ras_idx = 5'h0; // @[functional-unit.scala:393:7] wire [4:0] io_req_bits_ftq_info_1_entry_ras_idx = 5'h0; // @[functional-unit.scala:393:7] wire [4:0] io_req_bits_ftq_info_1_ghist_ras_idx = 5'h0; // @[functional-unit.scala:393:7] wire [4:0] io_resp_bits_fflags_bits = 5'h0; // @[functional-unit.scala:393:7] wire [39:0] io_req_bits_ftq_info_0_entry_ras_top = 40'h0; // @[functional-unit.scala:105:14, :393:7] wire [39:0] io_req_bits_ftq_info_0_pc = 40'h0; // @[functional-unit.scala:105:14, :393:7] wire [39:0] io_req_bits_ftq_info_1_entry_ras_top = 40'h0; // @[functional-unit.scala:105:14, :393:7] wire [39:0] io_req_bits_ftq_info_1_pc = 40'h0; // @[functional-unit.scala:105:14, :393:7] wire [3:0] io_req_bits_ftq_info_0_entry_br_mask = 4'h0; // @[functional-unit.scala:105:14, :393:7] wire [3:0] io_req_bits_ftq_info_1_entry_br_mask = 4'h0; // @[functional-unit.scala:105:14, :393:7] wire [2:0] io_req_bits_ftq_info_0_entry_cfi_type = 3'h0; // @[functional-unit.scala:105:14, :393:7] wire [2:0] io_req_bits_ftq_info_1_entry_cfi_type = 3'h0; // @[functional-unit.scala:105:14, :393:7] wire [1:0] io_req_bits_ftq_info_0_entry_cfi_idx_bits = 2'h0; // @[functional-unit.scala:105:14, :393:7] wire [1:0] io_req_bits_ftq_info_1_entry_cfi_idx_bits = 2'h0; // @[functional-unit.scala:105:14, :393:7] wire io_req_bits_ftq_info_0_valid = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_0_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_0_entry_cfi_taken = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_0_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_0_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_0_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_0_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_0_entry_start_bank = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_0_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_0_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_1_valid = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_1_entry_cfi_idx_valid = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_1_entry_cfi_taken = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_1_entry_cfi_mispredicted = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_1_entry_cfi_is_call = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_1_entry_cfi_is_ret = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_1_entry_cfi_npc_plus4 = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_1_entry_start_bank = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_1_ghist_current_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_not_taken = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_ftq_info_1_ghist_new_saw_branch_taken = 1'h0; // @[functional-unit.scala:393:7] wire io_req_bits_pred_data = 1'h0; // @[functional-unit.scala:393:7] wire io_resp_bits_predicated = 1'h0; // @[functional-unit.scala:393:7] wire io_resp_bits_fflags_valid = 1'h0; // @[functional-unit.scala:393:7] wire [63:0] io_req_bits_rs3_data = 64'h0; // @[functional-unit.scala:105:14, :393:7] wire [63:0] io_req_bits_ftq_info_0_ghist_old_history = 64'h0; // @[functional-unit.scala:105:14, :393:7] wire [63:0] io_req_bits_ftq_info_1_ghist_old_history = 64'h0; // @[functional-unit.scala:105:14, :393:7] wire _io_req_ready_T_1; // @[functional-unit.scala:421:43] wire [31:0] req_bits_out_inst = io_req_bits_uop_inst_0; // @[util.scala:104:23] wire [31:0] req_bits_out_debug_inst = io_req_bits_uop_debug_inst_0; // @[util.scala:104:23] wire req_bits_out_is_rvc = io_req_bits_uop_is_rvc_0; // @[util.scala:104:23] wire [39:0] req_bits_out_debug_pc = io_req_bits_uop_debug_pc_0; // @[util.scala:104:23] wire req_bits_out_iq_type_0 = io_req_bits_uop_iq_type_0_0; // @[util.scala:104:23] wire req_bits_out_iq_type_1 = io_req_bits_uop_iq_type_1_0; // @[util.scala:104:23] wire req_bits_out_iq_type_2 = io_req_bits_uop_iq_type_2_0; // @[util.scala:104:23] wire req_bits_out_iq_type_3 = io_req_bits_uop_iq_type_3_0; // @[util.scala:104:23] wire req_bits_out_fu_code_0 = io_req_bits_uop_fu_code_0_0; // @[util.scala:104:23] wire req_bits_out_fu_code_1 = io_req_bits_uop_fu_code_1_0; // @[util.scala:104:23] wire req_bits_out_fu_code_2 = io_req_bits_uop_fu_code_2_0; // @[util.scala:104:23] wire req_bits_out_fu_code_3 = io_req_bits_uop_fu_code_3_0; // @[util.scala:104:23] wire req_bits_out_fu_code_4 = io_req_bits_uop_fu_code_4_0; // @[util.scala:104:23] wire req_bits_out_fu_code_5 = io_req_bits_uop_fu_code_5_0; // @[util.scala:104:23] wire req_bits_out_fu_code_6 = io_req_bits_uop_fu_code_6_0; // @[util.scala:104:23] wire req_bits_out_fu_code_7 = io_req_bits_uop_fu_code_7_0; // @[util.scala:104:23] wire req_bits_out_fu_code_8 = io_req_bits_uop_fu_code_8_0; // @[util.scala:104:23] wire req_bits_out_fu_code_9 = io_req_bits_uop_fu_code_9_0; // @[util.scala:104:23] wire req_bits_out_iw_issued = io_req_bits_uop_iw_issued_0; // @[util.scala:104:23] wire req_bits_out_iw_issued_partial_agen = io_req_bits_uop_iw_issued_partial_agen_0; // @[util.scala:104:23] wire req_bits_out_iw_issued_partial_dgen = io_req_bits_uop_iw_issued_partial_dgen_0; // @[util.scala:104:23] wire [1:0] req_bits_out_iw_p1_speculative_child = io_req_bits_uop_iw_p1_speculative_child_0; // @[util.scala:104:23] wire [1:0] req_bits_out_iw_p2_speculative_child = io_req_bits_uop_iw_p2_speculative_child_0; // @[util.scala:104:23] wire req_bits_out_iw_p1_bypass_hint = io_req_bits_uop_iw_p1_bypass_hint_0; // @[util.scala:104:23] wire req_bits_out_iw_p2_bypass_hint = io_req_bits_uop_iw_p2_bypass_hint_0; // @[util.scala:104:23] wire req_bits_out_iw_p3_bypass_hint = io_req_bits_uop_iw_p3_bypass_hint_0; // @[util.scala:104:23] wire [1:0] req_bits_out_dis_col_sel = io_req_bits_uop_dis_col_sel_0; // @[util.scala:104:23] wire [3:0] req_bits_out_br_tag = io_req_bits_uop_br_tag_0; // @[util.scala:104:23] wire [3:0] req_bits_out_br_type = io_req_bits_uop_br_type_0; // @[util.scala:104:23] wire req_bits_out_is_sfb = io_req_bits_uop_is_sfb_0; // @[util.scala:104:23] wire req_bits_out_is_fence = io_req_bits_uop_is_fence_0; // @[util.scala:104:23] wire req_bits_out_is_fencei = io_req_bits_uop_is_fencei_0; // @[util.scala:104:23] wire req_bits_out_is_sfence = io_req_bits_uop_is_sfence_0; // @[util.scala:104:23] wire req_bits_out_is_amo = io_req_bits_uop_is_amo_0; // @[util.scala:104:23] wire req_bits_out_is_eret = io_req_bits_uop_is_eret_0; // @[util.scala:104:23] wire req_bits_out_is_sys_pc2epc = io_req_bits_uop_is_sys_pc2epc_0; // @[util.scala:104:23] wire req_bits_out_is_rocc = io_req_bits_uop_is_rocc_0; // @[util.scala:104:23] wire req_bits_out_is_mov = io_req_bits_uop_is_mov_0; // @[util.scala:104:23] wire [4:0] req_bits_out_ftq_idx = io_req_bits_uop_ftq_idx_0; // @[util.scala:104:23] wire req_bits_out_edge_inst = io_req_bits_uop_edge_inst_0; // @[util.scala:104:23] wire [5:0] req_bits_out_pc_lob = io_req_bits_uop_pc_lob_0; // @[util.scala:104:23] wire req_bits_out_taken = io_req_bits_uop_taken_0; // @[util.scala:104:23] wire req_bits_out_imm_rename = io_req_bits_uop_imm_rename_0; // @[util.scala:104:23] wire [2:0] req_bits_out_imm_sel = io_req_bits_uop_imm_sel_0; // @[util.scala:104:23] wire [4:0] req_bits_out_pimm = io_req_bits_uop_pimm_0; // @[util.scala:104:23] wire [19:0] req_bits_out_imm_packed = io_req_bits_uop_imm_packed_0; // @[util.scala:104:23] wire [1:0] req_bits_out_op1_sel = io_req_bits_uop_op1_sel_0; // @[util.scala:104:23] wire [2:0] req_bits_out_op2_sel = io_req_bits_uop_op2_sel_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_ldst = io_req_bits_uop_fp_ctrl_ldst_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_wen = io_req_bits_uop_fp_ctrl_wen_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_ren1 = io_req_bits_uop_fp_ctrl_ren1_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_ren2 = io_req_bits_uop_fp_ctrl_ren2_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_ren3 = io_req_bits_uop_fp_ctrl_ren3_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_swap12 = io_req_bits_uop_fp_ctrl_swap12_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_swap23 = io_req_bits_uop_fp_ctrl_swap23_0; // @[util.scala:104:23] wire [1:0] req_bits_out_fp_ctrl_typeTagIn = io_req_bits_uop_fp_ctrl_typeTagIn_0; // @[util.scala:104:23] wire [1:0] req_bits_out_fp_ctrl_typeTagOut = io_req_bits_uop_fp_ctrl_typeTagOut_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_fromint = io_req_bits_uop_fp_ctrl_fromint_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_toint = io_req_bits_uop_fp_ctrl_toint_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_fastpipe = io_req_bits_uop_fp_ctrl_fastpipe_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_fma = io_req_bits_uop_fp_ctrl_fma_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_div = io_req_bits_uop_fp_ctrl_div_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_sqrt = io_req_bits_uop_fp_ctrl_sqrt_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_wflags = io_req_bits_uop_fp_ctrl_wflags_0; // @[util.scala:104:23] wire req_bits_out_fp_ctrl_vec = io_req_bits_uop_fp_ctrl_vec_0; // @[util.scala:104:23] wire [5:0] req_bits_out_rob_idx = io_req_bits_uop_rob_idx_0; // @[util.scala:104:23] wire [3:0] req_bits_out_ldq_idx = io_req_bits_uop_ldq_idx_0; // @[util.scala:104:23] wire [3:0] req_bits_out_stq_idx = io_req_bits_uop_stq_idx_0; // @[util.scala:104:23] wire [1:0] req_bits_out_rxq_idx = io_req_bits_uop_rxq_idx_0; // @[util.scala:104:23] wire [6:0] req_bits_out_pdst = io_req_bits_uop_pdst_0; // @[util.scala:104:23] wire [6:0] req_bits_out_prs1 = io_req_bits_uop_prs1_0; // @[util.scala:104:23] wire [6:0] req_bits_out_prs2 = io_req_bits_uop_prs2_0; // @[util.scala:104:23] wire [6:0] req_bits_out_prs3 = io_req_bits_uop_prs3_0; // @[util.scala:104:23] wire [4:0] req_bits_out_ppred = io_req_bits_uop_ppred_0; // @[util.scala:104:23] wire req_bits_out_prs1_busy = io_req_bits_uop_prs1_busy_0; // @[util.scala:104:23] wire req_bits_out_prs2_busy = io_req_bits_uop_prs2_busy_0; // @[util.scala:104:23] wire req_bits_out_prs3_busy = io_req_bits_uop_prs3_busy_0; // @[util.scala:104:23] wire req_bits_out_ppred_busy = io_req_bits_uop_ppred_busy_0; // @[util.scala:104:23] wire [6:0] req_bits_out_stale_pdst = io_req_bits_uop_stale_pdst_0; // @[util.scala:104:23] wire req_bits_out_exception = io_req_bits_uop_exception_0; // @[util.scala:104:23] wire [63:0] req_bits_out_exc_cause = io_req_bits_uop_exc_cause_0; // @[util.scala:104:23] wire [4:0] req_bits_out_mem_cmd = io_req_bits_uop_mem_cmd_0; // @[util.scala:104:23] wire [1:0] req_bits_out_mem_size = io_req_bits_uop_mem_size_0; // @[util.scala:104:23] wire req_bits_out_mem_signed = io_req_bits_uop_mem_signed_0; // @[util.scala:104:23] wire req_bits_out_uses_ldq = io_req_bits_uop_uses_ldq_0; // @[util.scala:104:23] wire req_bits_out_uses_stq = io_req_bits_uop_uses_stq_0; // @[util.scala:104:23] wire req_bits_out_is_unique = io_req_bits_uop_is_unique_0; // @[util.scala:104:23] wire req_bits_out_flush_on_commit = io_req_bits_uop_flush_on_commit_0; // @[util.scala:104:23] wire [2:0] req_bits_out_csr_cmd = io_req_bits_uop_csr_cmd_0; // @[util.scala:104:23] wire req_bits_out_ldst_is_rs1 = io_req_bits_uop_ldst_is_rs1_0; // @[util.scala:104:23] wire [5:0] req_bits_out_ldst = io_req_bits_uop_ldst_0; // @[util.scala:104:23] wire [5:0] req_bits_out_lrs1 = io_req_bits_uop_lrs1_0; // @[util.scala:104:23] wire [5:0] req_bits_out_lrs2 = io_req_bits_uop_lrs2_0; // @[util.scala:104:23] wire [5:0] req_bits_out_lrs3 = io_req_bits_uop_lrs3_0; // @[util.scala:104:23] wire [1:0] req_bits_out_dst_rtype = io_req_bits_uop_dst_rtype_0; // @[util.scala:104:23] wire [1:0] req_bits_out_lrs1_rtype = io_req_bits_uop_lrs1_rtype_0; // @[util.scala:104:23] wire [1:0] req_bits_out_lrs2_rtype = io_req_bits_uop_lrs2_rtype_0; // @[util.scala:104:23] wire req_bits_out_frs3_en = io_req_bits_uop_frs3_en_0; // @[util.scala:104:23] wire req_bits_out_fcn_dw = io_req_bits_uop_fcn_dw_0; // @[util.scala:104:23] wire [4:0] req_bits_out_fcn_op = io_req_bits_uop_fcn_op_0; // @[util.scala:104:23] wire req_bits_out_fp_val = io_req_bits_uop_fp_val_0; // @[util.scala:104:23] wire [2:0] req_bits_out_fp_rm = io_req_bits_uop_fp_rm_0; // @[util.scala:104:23] wire [1:0] req_bits_out_fp_typ = io_req_bits_uop_fp_typ_0; // @[util.scala:104:23] wire req_bits_out_xcpt_pf_if = io_req_bits_uop_xcpt_pf_if_0; // @[util.scala:104:23] wire req_bits_out_xcpt_ae_if = io_req_bits_uop_xcpt_ae_if_0; // @[util.scala:104:23] wire req_bits_out_xcpt_ma_if = io_req_bits_uop_xcpt_ma_if_0; // @[util.scala:104:23] wire req_bits_out_bp_debug_if = io_req_bits_uop_bp_debug_if_0; // @[util.scala:104:23] wire req_bits_out_bp_xcpt_if = io_req_bits_uop_bp_xcpt_if_0; // @[util.scala:104:23] wire [2:0] req_bits_out_debug_fsrc = io_req_bits_uop_debug_fsrc_0; // @[util.scala:104:23] wire [2:0] req_bits_out_debug_tsrc = io_req_bits_uop_debug_tsrc_0; // @[util.scala:104:23] wire _io_resp_valid_T_1; // @[functional-unit.scala:429:44] wire io_req_ready_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_iq_type_0_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_iq_type_1_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_iq_type_2_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_iq_type_3_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fu_code_0_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fu_code_1_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fu_code_2_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fu_code_3_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fu_code_4_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fu_code_5_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fu_code_6_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fu_code_7_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fu_code_8_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fu_code_9_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:393:7] wire [31:0] io_resp_bits_uop_inst_0; // @[functional-unit.scala:393:7] wire [31:0] io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:393:7] wire [39:0] io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_iw_issued_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_dis_col_sel_0; // @[functional-unit.scala:393:7] wire [11:0] io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:393:7] wire [3:0] io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:393:7] wire [3:0] io_resp_bits_uop_br_type_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_is_sfence_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_is_eret_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_is_rocc_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_is_mov_0; // @[functional-unit.scala:393:7] wire [4:0] io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:393:7] wire [5:0] io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_taken_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_imm_rename_0; // @[functional-unit.scala:393:7] wire [2:0] io_resp_bits_uop_imm_sel_0; // @[functional-unit.scala:393:7] wire [4:0] io_resp_bits_uop_pimm_0; // @[functional-unit.scala:393:7] wire [19:0] io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_op1_sel_0; // @[functional-unit.scala:393:7] wire [2:0] io_resp_bits_uop_op2_sel_0; // @[functional-unit.scala:393:7] wire [5:0] io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:393:7] wire [3:0] io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:393:7] wire [3:0] io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:393:7] wire [6:0] io_resp_bits_uop_pdst_0; // @[functional-unit.scala:393:7] wire [6:0] io_resp_bits_uop_prs1_0; // @[functional-unit.scala:393:7] wire [6:0] io_resp_bits_uop_prs2_0; // @[functional-unit.scala:393:7] wire [6:0] io_resp_bits_uop_prs3_0; // @[functional-unit.scala:393:7] wire [4:0] io_resp_bits_uop_ppred_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:393:7] wire [6:0] io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_exception_0; // @[functional-unit.scala:393:7] wire [63:0] io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:393:7] wire [4:0] io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:393:7] wire [2:0] io_resp_bits_uop_csr_cmd_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:393:7] wire [5:0] io_resp_bits_uop_ldst_0; // @[functional-unit.scala:393:7] wire [5:0] io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:393:7] wire [5:0] io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:393:7] wire [5:0] io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fcn_dw_0; // @[functional-unit.scala:393:7] wire [4:0] io_resp_bits_uop_fcn_op_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:393:7] wire [2:0] io_resp_bits_uop_fp_rm_0; // @[functional-unit.scala:393:7] wire [1:0] io_resp_bits_uop_fp_typ_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:393:7] wire io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:393:7] wire [2:0] io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:393:7] wire [2:0] io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:393:7] wire [63:0] io_resp_bits_data_0; // @[functional-unit.scala:393:7] wire io_resp_valid_0; // @[functional-unit.scala:393:7] reg req_valid; // @[functional-unit.scala:401:16] reg [31:0] req_bits_inst; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_inst_0 = req_bits_inst; // @[functional-unit.scala:393:7, :401:16] wire [31:0] req_bits_out_1_inst = req_bits_inst; // @[util.scala:104:23] reg [31:0] req_bits_debug_inst; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_debug_inst_0 = req_bits_debug_inst; // @[functional-unit.scala:393:7, :401:16] wire [31:0] req_bits_out_1_debug_inst = req_bits_debug_inst; // @[util.scala:104:23] reg req_bits_is_rvc; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_is_rvc_0 = req_bits_is_rvc; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_is_rvc = req_bits_is_rvc; // @[util.scala:104:23] reg [39:0] req_bits_debug_pc; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_debug_pc_0 = req_bits_debug_pc; // @[functional-unit.scala:393:7, :401:16] wire [39:0] req_bits_out_1_debug_pc = req_bits_debug_pc; // @[util.scala:104:23] reg req_bits_iq_type_0; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iq_type_0_0 = req_bits_iq_type_0; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_iq_type_0 = req_bits_iq_type_0; // @[util.scala:104:23] reg req_bits_iq_type_1; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iq_type_1_0 = req_bits_iq_type_1; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_iq_type_1 = req_bits_iq_type_1; // @[util.scala:104:23] reg req_bits_iq_type_2; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iq_type_2_0 = req_bits_iq_type_2; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_iq_type_2 = req_bits_iq_type_2; // @[util.scala:104:23] reg req_bits_iq_type_3; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iq_type_3_0 = req_bits_iq_type_3; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_iq_type_3 = req_bits_iq_type_3; // @[util.scala:104:23] reg req_bits_fu_code_0; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fu_code_0_0 = req_bits_fu_code_0; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fu_code_0 = req_bits_fu_code_0; // @[util.scala:104:23] reg req_bits_fu_code_1; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fu_code_1_0 = req_bits_fu_code_1; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fu_code_1 = req_bits_fu_code_1; // @[util.scala:104:23] reg req_bits_fu_code_2; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fu_code_2_0 = req_bits_fu_code_2; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fu_code_2 = req_bits_fu_code_2; // @[util.scala:104:23] reg req_bits_fu_code_3; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fu_code_3_0 = req_bits_fu_code_3; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fu_code_3 = req_bits_fu_code_3; // @[util.scala:104:23] reg req_bits_fu_code_4; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fu_code_4_0 = req_bits_fu_code_4; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fu_code_4 = req_bits_fu_code_4; // @[util.scala:104:23] reg req_bits_fu_code_5; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fu_code_5_0 = req_bits_fu_code_5; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fu_code_5 = req_bits_fu_code_5; // @[util.scala:104:23] reg req_bits_fu_code_6; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fu_code_6_0 = req_bits_fu_code_6; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fu_code_6 = req_bits_fu_code_6; // @[util.scala:104:23] reg req_bits_fu_code_7; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fu_code_7_0 = req_bits_fu_code_7; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fu_code_7 = req_bits_fu_code_7; // @[util.scala:104:23] reg req_bits_fu_code_8; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fu_code_8_0 = req_bits_fu_code_8; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fu_code_8 = req_bits_fu_code_8; // @[util.scala:104:23] reg req_bits_fu_code_9; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fu_code_9_0 = req_bits_fu_code_9; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fu_code_9 = req_bits_fu_code_9; // @[util.scala:104:23] reg req_bits_iw_issued; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iw_issued_0 = req_bits_iw_issued; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_iw_issued = req_bits_iw_issued; // @[util.scala:104:23] reg req_bits_iw_issued_partial_agen; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iw_issued_partial_agen_0 = req_bits_iw_issued_partial_agen; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_iw_issued_partial_agen = req_bits_iw_issued_partial_agen; // @[util.scala:104:23] reg req_bits_iw_issued_partial_dgen; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iw_issued_partial_dgen_0 = req_bits_iw_issued_partial_dgen; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_iw_issued_partial_dgen = req_bits_iw_issued_partial_dgen; // @[util.scala:104:23] reg [1:0] req_bits_iw_p1_speculative_child; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iw_p1_speculative_child_0 = req_bits_iw_p1_speculative_child; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_iw_p1_speculative_child = req_bits_iw_p1_speculative_child; // @[util.scala:104:23] reg [1:0] req_bits_iw_p2_speculative_child; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iw_p2_speculative_child_0 = req_bits_iw_p2_speculative_child; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_iw_p2_speculative_child = req_bits_iw_p2_speculative_child; // @[util.scala:104:23] reg req_bits_iw_p1_bypass_hint; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iw_p1_bypass_hint_0 = req_bits_iw_p1_bypass_hint; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_iw_p1_bypass_hint = req_bits_iw_p1_bypass_hint; // @[util.scala:104:23] reg req_bits_iw_p2_bypass_hint; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iw_p2_bypass_hint_0 = req_bits_iw_p2_bypass_hint; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_iw_p2_bypass_hint = req_bits_iw_p2_bypass_hint; // @[util.scala:104:23] reg req_bits_iw_p3_bypass_hint; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_iw_p3_bypass_hint_0 = req_bits_iw_p3_bypass_hint; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_iw_p3_bypass_hint = req_bits_iw_p3_bypass_hint; // @[util.scala:104:23] reg [1:0] req_bits_dis_col_sel; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_dis_col_sel_0 = req_bits_dis_col_sel; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_dis_col_sel = req_bits_dis_col_sel; // @[util.scala:104:23] reg [11:0] req_bits_br_mask; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_br_mask_0 = req_bits_br_mask; // @[functional-unit.scala:393:7, :401:16] reg [3:0] req_bits_br_tag; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_br_tag_0 = req_bits_br_tag; // @[functional-unit.scala:393:7, :401:16] wire [3:0] req_bits_out_1_br_tag = req_bits_br_tag; // @[util.scala:104:23] reg [3:0] req_bits_br_type; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_br_type_0 = req_bits_br_type; // @[functional-unit.scala:393:7, :401:16] wire [3:0] req_bits_out_1_br_type = req_bits_br_type; // @[util.scala:104:23] reg req_bits_is_sfb; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_is_sfb_0 = req_bits_is_sfb; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_is_sfb = req_bits_is_sfb; // @[util.scala:104:23] reg req_bits_is_fence; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_is_fence_0 = req_bits_is_fence; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_is_fence = req_bits_is_fence; // @[util.scala:104:23] reg req_bits_is_fencei; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_is_fencei_0 = req_bits_is_fencei; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_is_fencei = req_bits_is_fencei; // @[util.scala:104:23] reg req_bits_is_sfence; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_is_sfence_0 = req_bits_is_sfence; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_is_sfence = req_bits_is_sfence; // @[util.scala:104:23] reg req_bits_is_amo; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_is_amo_0 = req_bits_is_amo; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_is_amo = req_bits_is_amo; // @[util.scala:104:23] reg req_bits_is_eret; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_is_eret_0 = req_bits_is_eret; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_is_eret = req_bits_is_eret; // @[util.scala:104:23] reg req_bits_is_sys_pc2epc; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_is_sys_pc2epc_0 = req_bits_is_sys_pc2epc; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_is_sys_pc2epc = req_bits_is_sys_pc2epc; // @[util.scala:104:23] reg req_bits_is_rocc; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_is_rocc_0 = req_bits_is_rocc; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_is_rocc = req_bits_is_rocc; // @[util.scala:104:23] reg req_bits_is_mov; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_is_mov_0 = req_bits_is_mov; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_is_mov = req_bits_is_mov; // @[util.scala:104:23] reg [4:0] req_bits_ftq_idx; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_ftq_idx_0 = req_bits_ftq_idx; // @[functional-unit.scala:393:7, :401:16] wire [4:0] req_bits_out_1_ftq_idx = req_bits_ftq_idx; // @[util.scala:104:23] reg req_bits_edge_inst; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_edge_inst_0 = req_bits_edge_inst; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_edge_inst = req_bits_edge_inst; // @[util.scala:104:23] reg [5:0] req_bits_pc_lob; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_pc_lob_0 = req_bits_pc_lob; // @[functional-unit.scala:393:7, :401:16] wire [5:0] req_bits_out_1_pc_lob = req_bits_pc_lob; // @[util.scala:104:23] reg req_bits_taken; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_taken_0 = req_bits_taken; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_taken = req_bits_taken; // @[util.scala:104:23] reg req_bits_imm_rename; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_imm_rename_0 = req_bits_imm_rename; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_imm_rename = req_bits_imm_rename; // @[util.scala:104:23] reg [2:0] req_bits_imm_sel; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_imm_sel_0 = req_bits_imm_sel; // @[functional-unit.scala:393:7, :401:16] wire [2:0] req_bits_out_1_imm_sel = req_bits_imm_sel; // @[util.scala:104:23] reg [4:0] req_bits_pimm; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_pimm_0 = req_bits_pimm; // @[functional-unit.scala:393:7, :401:16] wire [4:0] req_bits_out_1_pimm = req_bits_pimm; // @[util.scala:104:23] reg [19:0] req_bits_imm_packed; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_imm_packed_0 = req_bits_imm_packed; // @[functional-unit.scala:393:7, :401:16] wire [19:0] req_bits_out_1_imm_packed = req_bits_imm_packed; // @[util.scala:104:23] reg [1:0] req_bits_op1_sel; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_op1_sel_0 = req_bits_op1_sel; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_op1_sel = req_bits_op1_sel; // @[util.scala:104:23] reg [2:0] req_bits_op2_sel; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_op2_sel_0 = req_bits_op2_sel; // @[functional-unit.scala:393:7, :401:16] wire [2:0] req_bits_out_1_op2_sel = req_bits_op2_sel; // @[util.scala:104:23] reg req_bits_fp_ctrl_ldst; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_ldst_0 = req_bits_fp_ctrl_ldst; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_ldst = req_bits_fp_ctrl_ldst; // @[util.scala:104:23] reg req_bits_fp_ctrl_wen; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_wen_0 = req_bits_fp_ctrl_wen; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_wen = req_bits_fp_ctrl_wen; // @[util.scala:104:23] reg req_bits_fp_ctrl_ren1; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_ren1_0 = req_bits_fp_ctrl_ren1; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_ren1 = req_bits_fp_ctrl_ren1; // @[util.scala:104:23] reg req_bits_fp_ctrl_ren2; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_ren2_0 = req_bits_fp_ctrl_ren2; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_ren2 = req_bits_fp_ctrl_ren2; // @[util.scala:104:23] reg req_bits_fp_ctrl_ren3; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_ren3_0 = req_bits_fp_ctrl_ren3; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_ren3 = req_bits_fp_ctrl_ren3; // @[util.scala:104:23] reg req_bits_fp_ctrl_swap12; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_swap12_0 = req_bits_fp_ctrl_swap12; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_swap12 = req_bits_fp_ctrl_swap12; // @[util.scala:104:23] reg req_bits_fp_ctrl_swap23; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_swap23_0 = req_bits_fp_ctrl_swap23; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_swap23 = req_bits_fp_ctrl_swap23; // @[util.scala:104:23] reg [1:0] req_bits_fp_ctrl_typeTagIn; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_typeTagIn_0 = req_bits_fp_ctrl_typeTagIn; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_fp_ctrl_typeTagIn = req_bits_fp_ctrl_typeTagIn; // @[util.scala:104:23] reg [1:0] req_bits_fp_ctrl_typeTagOut; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_typeTagOut_0 = req_bits_fp_ctrl_typeTagOut; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_fp_ctrl_typeTagOut = req_bits_fp_ctrl_typeTagOut; // @[util.scala:104:23] reg req_bits_fp_ctrl_fromint; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_fromint_0 = req_bits_fp_ctrl_fromint; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_fromint = req_bits_fp_ctrl_fromint; // @[util.scala:104:23] reg req_bits_fp_ctrl_toint; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_toint_0 = req_bits_fp_ctrl_toint; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_toint = req_bits_fp_ctrl_toint; // @[util.scala:104:23] reg req_bits_fp_ctrl_fastpipe; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_fastpipe_0 = req_bits_fp_ctrl_fastpipe; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_fastpipe = req_bits_fp_ctrl_fastpipe; // @[util.scala:104:23] reg req_bits_fp_ctrl_fma; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_fma_0 = req_bits_fp_ctrl_fma; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_fma = req_bits_fp_ctrl_fma; // @[util.scala:104:23] reg req_bits_fp_ctrl_div; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_div_0 = req_bits_fp_ctrl_div; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_div = req_bits_fp_ctrl_div; // @[util.scala:104:23] reg req_bits_fp_ctrl_sqrt; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_sqrt_0 = req_bits_fp_ctrl_sqrt; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_sqrt = req_bits_fp_ctrl_sqrt; // @[util.scala:104:23] reg req_bits_fp_ctrl_wflags; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_wflags_0 = req_bits_fp_ctrl_wflags; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_wflags = req_bits_fp_ctrl_wflags; // @[util.scala:104:23] reg req_bits_fp_ctrl_vec; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_ctrl_vec_0 = req_bits_fp_ctrl_vec; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_ctrl_vec = req_bits_fp_ctrl_vec; // @[util.scala:104:23] reg [5:0] req_bits_rob_idx; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_rob_idx_0 = req_bits_rob_idx; // @[functional-unit.scala:393:7, :401:16] wire [5:0] req_bits_out_1_rob_idx = req_bits_rob_idx; // @[util.scala:104:23] reg [3:0] req_bits_ldq_idx; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_ldq_idx_0 = req_bits_ldq_idx; // @[functional-unit.scala:393:7, :401:16] wire [3:0] req_bits_out_1_ldq_idx = req_bits_ldq_idx; // @[util.scala:104:23] reg [3:0] req_bits_stq_idx; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_stq_idx_0 = req_bits_stq_idx; // @[functional-unit.scala:393:7, :401:16] wire [3:0] req_bits_out_1_stq_idx = req_bits_stq_idx; // @[util.scala:104:23] reg [1:0] req_bits_rxq_idx; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_rxq_idx_0 = req_bits_rxq_idx; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_rxq_idx = req_bits_rxq_idx; // @[util.scala:104:23] reg [6:0] req_bits_pdst; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_pdst_0 = req_bits_pdst; // @[functional-unit.scala:393:7, :401:16] wire [6:0] req_bits_out_1_pdst = req_bits_pdst; // @[util.scala:104:23] reg [6:0] req_bits_prs1; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_prs1_0 = req_bits_prs1; // @[functional-unit.scala:393:7, :401:16] wire [6:0] req_bits_out_1_prs1 = req_bits_prs1; // @[util.scala:104:23] reg [6:0] req_bits_prs2; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_prs2_0 = req_bits_prs2; // @[functional-unit.scala:393:7, :401:16] wire [6:0] req_bits_out_1_prs2 = req_bits_prs2; // @[util.scala:104:23] reg [6:0] req_bits_prs3; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_prs3_0 = req_bits_prs3; // @[functional-unit.scala:393:7, :401:16] wire [6:0] req_bits_out_1_prs3 = req_bits_prs3; // @[util.scala:104:23] reg [4:0] req_bits_ppred; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_ppred_0 = req_bits_ppred; // @[functional-unit.scala:393:7, :401:16] wire [4:0] req_bits_out_1_ppred = req_bits_ppred; // @[util.scala:104:23] reg req_bits_prs1_busy; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_prs1_busy_0 = req_bits_prs1_busy; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_prs1_busy = req_bits_prs1_busy; // @[util.scala:104:23] reg req_bits_prs2_busy; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_prs2_busy_0 = req_bits_prs2_busy; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_prs2_busy = req_bits_prs2_busy; // @[util.scala:104:23] reg req_bits_prs3_busy; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_prs3_busy_0 = req_bits_prs3_busy; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_prs3_busy = req_bits_prs3_busy; // @[util.scala:104:23] reg req_bits_ppred_busy; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_ppred_busy_0 = req_bits_ppred_busy; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_ppred_busy = req_bits_ppred_busy; // @[util.scala:104:23] reg [6:0] req_bits_stale_pdst; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_stale_pdst_0 = req_bits_stale_pdst; // @[functional-unit.scala:393:7, :401:16] wire [6:0] req_bits_out_1_stale_pdst = req_bits_stale_pdst; // @[util.scala:104:23] reg req_bits_exception; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_exception_0 = req_bits_exception; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_exception = req_bits_exception; // @[util.scala:104:23] reg [63:0] req_bits_exc_cause; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_exc_cause_0 = req_bits_exc_cause; // @[functional-unit.scala:393:7, :401:16] wire [63:0] req_bits_out_1_exc_cause = req_bits_exc_cause; // @[util.scala:104:23] reg [4:0] req_bits_mem_cmd; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_mem_cmd_0 = req_bits_mem_cmd; // @[functional-unit.scala:393:7, :401:16] wire [4:0] req_bits_out_1_mem_cmd = req_bits_mem_cmd; // @[util.scala:104:23] reg [1:0] req_bits_mem_size; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_mem_size_0 = req_bits_mem_size; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_mem_size = req_bits_mem_size; // @[util.scala:104:23] reg req_bits_mem_signed; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_mem_signed_0 = req_bits_mem_signed; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_mem_signed = req_bits_mem_signed; // @[util.scala:104:23] reg req_bits_uses_ldq; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_uses_ldq_0 = req_bits_uses_ldq; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_uses_ldq = req_bits_uses_ldq; // @[util.scala:104:23] reg req_bits_uses_stq; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_uses_stq_0 = req_bits_uses_stq; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_uses_stq = req_bits_uses_stq; // @[util.scala:104:23] reg req_bits_is_unique; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_is_unique_0 = req_bits_is_unique; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_is_unique = req_bits_is_unique; // @[util.scala:104:23] reg req_bits_flush_on_commit; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_flush_on_commit_0 = req_bits_flush_on_commit; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_flush_on_commit = req_bits_flush_on_commit; // @[util.scala:104:23] reg [2:0] req_bits_csr_cmd; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_csr_cmd_0 = req_bits_csr_cmd; // @[functional-unit.scala:393:7, :401:16] wire [2:0] req_bits_out_1_csr_cmd = req_bits_csr_cmd; // @[util.scala:104:23] reg req_bits_ldst_is_rs1; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_ldst_is_rs1_0 = req_bits_ldst_is_rs1; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_ldst_is_rs1 = req_bits_ldst_is_rs1; // @[util.scala:104:23] reg [5:0] req_bits_ldst; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_ldst_0 = req_bits_ldst; // @[functional-unit.scala:393:7, :401:16] wire [5:0] req_bits_out_1_ldst = req_bits_ldst; // @[util.scala:104:23] reg [5:0] req_bits_lrs1; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_lrs1_0 = req_bits_lrs1; // @[functional-unit.scala:393:7, :401:16] wire [5:0] req_bits_out_1_lrs1 = req_bits_lrs1; // @[util.scala:104:23] reg [5:0] req_bits_lrs2; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_lrs2_0 = req_bits_lrs2; // @[functional-unit.scala:393:7, :401:16] wire [5:0] req_bits_out_1_lrs2 = req_bits_lrs2; // @[util.scala:104:23] reg [5:0] req_bits_lrs3; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_lrs3_0 = req_bits_lrs3; // @[functional-unit.scala:393:7, :401:16] wire [5:0] req_bits_out_1_lrs3 = req_bits_lrs3; // @[util.scala:104:23] reg [1:0] req_bits_dst_rtype; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_dst_rtype_0 = req_bits_dst_rtype; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_dst_rtype = req_bits_dst_rtype; // @[util.scala:104:23] reg [1:0] req_bits_lrs1_rtype; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_lrs1_rtype_0 = req_bits_lrs1_rtype; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_lrs1_rtype = req_bits_lrs1_rtype; // @[util.scala:104:23] reg [1:0] req_bits_lrs2_rtype; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_lrs2_rtype_0 = req_bits_lrs2_rtype; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_lrs2_rtype = req_bits_lrs2_rtype; // @[util.scala:104:23] reg req_bits_frs3_en; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_frs3_en_0 = req_bits_frs3_en; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_frs3_en = req_bits_frs3_en; // @[util.scala:104:23] reg req_bits_fcn_dw; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fcn_dw_0 = req_bits_fcn_dw; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fcn_dw = req_bits_fcn_dw; // @[util.scala:104:23] reg [4:0] req_bits_fcn_op; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fcn_op_0 = req_bits_fcn_op; // @[functional-unit.scala:393:7, :401:16] wire [4:0] req_bits_out_1_fcn_op = req_bits_fcn_op; // @[util.scala:104:23] reg req_bits_fp_val; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_val_0 = req_bits_fp_val; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_fp_val = req_bits_fp_val; // @[util.scala:104:23] reg [2:0] req_bits_fp_rm; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_rm_0 = req_bits_fp_rm; // @[functional-unit.scala:393:7, :401:16] wire [2:0] req_bits_out_1_fp_rm = req_bits_fp_rm; // @[util.scala:104:23] reg [1:0] req_bits_fp_typ; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_fp_typ_0 = req_bits_fp_typ; // @[functional-unit.scala:393:7, :401:16] wire [1:0] req_bits_out_1_fp_typ = req_bits_fp_typ; // @[util.scala:104:23] reg req_bits_xcpt_pf_if; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_xcpt_pf_if_0 = req_bits_xcpt_pf_if; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_xcpt_pf_if = req_bits_xcpt_pf_if; // @[util.scala:104:23] reg req_bits_xcpt_ae_if; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_xcpt_ae_if_0 = req_bits_xcpt_ae_if; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_xcpt_ae_if = req_bits_xcpt_ae_if; // @[util.scala:104:23] reg req_bits_xcpt_ma_if; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_xcpt_ma_if_0 = req_bits_xcpt_ma_if; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_xcpt_ma_if = req_bits_xcpt_ma_if; // @[util.scala:104:23] reg req_bits_bp_debug_if; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_bp_debug_if_0 = req_bits_bp_debug_if; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_bp_debug_if = req_bits_bp_debug_if; // @[util.scala:104:23] reg req_bits_bp_xcpt_if; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_bp_xcpt_if_0 = req_bits_bp_xcpt_if; // @[functional-unit.scala:393:7, :401:16] wire req_bits_out_1_bp_xcpt_if = req_bits_bp_xcpt_if; // @[util.scala:104:23] reg [2:0] req_bits_debug_fsrc; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_debug_fsrc_0 = req_bits_debug_fsrc; // @[functional-unit.scala:393:7, :401:16] wire [2:0] req_bits_out_1_debug_fsrc = req_bits_debug_fsrc; // @[util.scala:104:23] reg [2:0] req_bits_debug_tsrc; // @[functional-unit.scala:401:16] assign io_resp_bits_uop_debug_tsrc_0 = req_bits_debug_tsrc; // @[functional-unit.scala:393:7, :401:16] wire [2:0] req_bits_out_1_debug_tsrc = req_bits_debug_tsrc; // @[util.scala:104:23] wire [11:0] _GEN = io_brupdate_b1_mispredict_mask_0 & io_req_bits_uop_br_mask_0; // @[util.scala:126:51] wire [11:0] _req_valid_T; // @[util.scala:126:51] assign _req_valid_T = _GEN; // @[util.scala:126:51] wire [11:0] _div_io_req_valid_T; // @[util.scala:126:51] assign _div_io_req_valid_T = _GEN; // @[util.scala:126:51] wire _req_valid_T_1 = |_req_valid_T; // @[util.scala:126:{51,59}] wire _req_valid_T_2 = _req_valid_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _req_valid_T_3 = ~_req_valid_T_2; // @[util.scala:61:61] wire [11:0] _req_bits_out_br_mask_T_1; // @[util.scala:93:25] wire [11:0] req_bits_out_br_mask; // @[util.scala:104:23] wire [11:0] _req_bits_out_br_mask_T = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _req_bits_out_br_mask_T_1 = io_req_bits_uop_br_mask_0 & _req_bits_out_br_mask_T; // @[util.scala:93:{25,27}] assign req_bits_out_br_mask = _req_bits_out_br_mask_T_1; // @[util.scala:93:25, :104:23] wire [11:0] _GEN_0 = io_brupdate_b1_mispredict_mask_0 & req_bits_br_mask; // @[util.scala:126:51] wire [11:0] _req_valid_T_4; // @[util.scala:126:51] assign _req_valid_T_4 = _GEN_0; // @[util.scala:126:51] wire [11:0] _div_io_kill_T; // @[util.scala:126:51] assign _div_io_kill_T = _GEN_0; // @[util.scala:126:51] wire _req_valid_T_5 = |_req_valid_T_4; // @[util.scala:126:{51,59}] wire _req_valid_T_6 = _req_valid_T_5 | io_kill_0; // @[util.scala:61:61, :126:59] wire _req_valid_T_7 = ~_req_valid_T_6; // @[util.scala:61:61] wire _req_valid_T_8 = _req_valid_T_7 & req_valid; // @[functional-unit.scala:401:16, :407:{18,68}] wire [11:0] _req_bits_out_br_mask_T_3; // @[util.scala:93:25] wire [11:0] req_bits_out_1_br_mask; // @[util.scala:104:23] wire [11:0] _req_bits_out_br_mask_T_2 = ~io_brupdate_b1_resolve_mask_0; // @[util.scala:93:27] assign _req_bits_out_br_mask_T_3 = req_bits_br_mask & _req_bits_out_br_mask_T_2; // @[util.scala:93:{25,27}] assign req_bits_out_1_br_mask = _req_bits_out_br_mask_T_3; // @[util.scala:93:25, :104:23] wire _div_io_req_valid_T_1 = |_div_io_req_valid_T; // @[util.scala:126:{51,59}] wire _div_io_req_valid_T_2 = _div_io_req_valid_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _div_io_req_valid_T_3 = ~_div_io_req_valid_T_2; // @[util.scala:61:61] wire _div_io_req_valid_T_4 = io_req_valid_0 & _div_io_req_valid_T_3; // @[functional-unit.scala:393:7, :415:{39,42}] wire _io_req_ready_T = ~req_valid; // @[functional-unit.scala:401:16, :421:46] assign _io_req_ready_T_1 = _div_io_req_ready & _io_req_ready_T; // @[functional-unit.scala:399:19, :421:{43,46}] assign io_req_ready_0 = _io_req_ready_T_1; // @[functional-unit.scala:393:7, :421:43] wire _div_io_kill_T_1 = |_div_io_kill_T; // @[util.scala:126:{51,59}] wire _div_io_kill_T_2 = _div_io_kill_T_1 | io_kill_0; // @[util.scala:61:61, :126:59] wire _div_io_kill_T_3 = req_valid & _div_io_kill_T_2; // @[util.scala:61:61] wire _GEN_1 = _div_io_resp_valid & req_valid; // @[functional-unit.scala:399:19, :401:16, :427:44] wire _io_resp_valid_T; // @[functional-unit.scala:427:44] assign _io_resp_valid_T = _GEN_1; // @[functional-unit.scala:427:44] assign _io_resp_valid_T_1 = _GEN_1; // @[functional-unit.scala:427:44, :429:44] assign io_resp_valid_0 = _io_resp_valid_T_1; // @[functional-unit.scala:393:7, :429:44] wire _T = io_req_ready_0 & io_req_valid_0; // @[Decoupled.scala:51:35] always @(posedge clock) begin // @[functional-unit.scala:393:7] req_valid <= ~(io_resp_ready_0 & io_resp_valid_0 | reset) & (_T ? _req_valid_T_3 : _req_valid_T_8); // @[Decoupled.scala:51:35] req_bits_inst <= _T ? req_bits_out_inst : req_bits_out_1_inst; // @[Decoupled.scala:51:35] req_bits_debug_inst <= _T ? req_bits_out_debug_inst : req_bits_out_1_debug_inst; // @[Decoupled.scala:51:35] req_bits_is_rvc <= _T ? req_bits_out_is_rvc : req_bits_out_1_is_rvc; // @[Decoupled.scala:51:35] req_bits_debug_pc <= _T ? req_bits_out_debug_pc : req_bits_out_1_debug_pc; // @[Decoupled.scala:51:35] req_bits_iq_type_0 <= _T ? req_bits_out_iq_type_0 : req_bits_out_1_iq_type_0; // @[Decoupled.scala:51:35] req_bits_iq_type_1 <= _T ? req_bits_out_iq_type_1 : req_bits_out_1_iq_type_1; // @[Decoupled.scala:51:35] req_bits_iq_type_2 <= _T ? req_bits_out_iq_type_2 : req_bits_out_1_iq_type_2; // @[Decoupled.scala:51:35] req_bits_iq_type_3 <= _T ? req_bits_out_iq_type_3 : req_bits_out_1_iq_type_3; // @[Decoupled.scala:51:35] req_bits_fu_code_0 <= _T ? req_bits_out_fu_code_0 : req_bits_out_1_fu_code_0; // @[Decoupled.scala:51:35] req_bits_fu_code_1 <= _T ? req_bits_out_fu_code_1 : req_bits_out_1_fu_code_1; // @[Decoupled.scala:51:35] req_bits_fu_code_2 <= _T ? req_bits_out_fu_code_2 : req_bits_out_1_fu_code_2; // @[Decoupled.scala:51:35] req_bits_fu_code_3 <= _T ? req_bits_out_fu_code_3 : req_bits_out_1_fu_code_3; // @[Decoupled.scala:51:35] req_bits_fu_code_4 <= _T ? req_bits_out_fu_code_4 : req_bits_out_1_fu_code_4; // @[Decoupled.scala:51:35] req_bits_fu_code_5 <= _T ? req_bits_out_fu_code_5 : req_bits_out_1_fu_code_5; // @[Decoupled.scala:51:35] req_bits_fu_code_6 <= _T ? req_bits_out_fu_code_6 : req_bits_out_1_fu_code_6; // @[Decoupled.scala:51:35] req_bits_fu_code_7 <= _T ? req_bits_out_fu_code_7 : req_bits_out_1_fu_code_7; // @[Decoupled.scala:51:35] req_bits_fu_code_8 <= _T ? req_bits_out_fu_code_8 : req_bits_out_1_fu_code_8; // @[Decoupled.scala:51:35] req_bits_fu_code_9 <= _T ? req_bits_out_fu_code_9 : req_bits_out_1_fu_code_9; // @[Decoupled.scala:51:35] req_bits_iw_issued <= _T ? req_bits_out_iw_issued : req_bits_out_1_iw_issued; // @[Decoupled.scala:51:35] req_bits_iw_issued_partial_agen <= _T ? req_bits_out_iw_issued_partial_agen : req_bits_out_1_iw_issued_partial_agen; // @[Decoupled.scala:51:35] req_bits_iw_issued_partial_dgen <= _T ? req_bits_out_iw_issued_partial_dgen : req_bits_out_1_iw_issued_partial_dgen; // @[Decoupled.scala:51:35] req_bits_iw_p1_speculative_child <= _T ? req_bits_out_iw_p1_speculative_child : req_bits_out_1_iw_p1_speculative_child; // @[Decoupled.scala:51:35] req_bits_iw_p2_speculative_child <= _T ? req_bits_out_iw_p2_speculative_child : req_bits_out_1_iw_p2_speculative_child; // @[Decoupled.scala:51:35] req_bits_iw_p1_bypass_hint <= _T ? req_bits_out_iw_p1_bypass_hint : req_bits_out_1_iw_p1_bypass_hint; // @[Decoupled.scala:51:35] req_bits_iw_p2_bypass_hint <= _T ? req_bits_out_iw_p2_bypass_hint : req_bits_out_1_iw_p2_bypass_hint; // @[Decoupled.scala:51:35] req_bits_iw_p3_bypass_hint <= _T ? req_bits_out_iw_p3_bypass_hint : req_bits_out_1_iw_p3_bypass_hint; // @[Decoupled.scala:51:35] req_bits_dis_col_sel <= _T ? req_bits_out_dis_col_sel : req_bits_out_1_dis_col_sel; // @[Decoupled.scala:51:35] req_bits_br_mask <= _T ? req_bits_out_br_mask : req_bits_out_1_br_mask; // @[Decoupled.scala:51:35] req_bits_br_tag <= _T ? req_bits_out_br_tag : req_bits_out_1_br_tag; // @[Decoupled.scala:51:35] req_bits_br_type <= _T ? req_bits_out_br_type : req_bits_out_1_br_type; // @[Decoupled.scala:51:35] req_bits_is_sfb <= _T ? req_bits_out_is_sfb : req_bits_out_1_is_sfb; // @[Decoupled.scala:51:35] req_bits_is_fence <= _T ? req_bits_out_is_fence : req_bits_out_1_is_fence; // @[Decoupled.scala:51:35] req_bits_is_fencei <= _T ? req_bits_out_is_fencei : req_bits_out_1_is_fencei; // @[Decoupled.scala:51:35] req_bits_is_sfence <= _T ? req_bits_out_is_sfence : req_bits_out_1_is_sfence; // @[Decoupled.scala:51:35] req_bits_is_amo <= _T ? req_bits_out_is_amo : req_bits_out_1_is_amo; // @[Decoupled.scala:51:35] req_bits_is_eret <= _T ? req_bits_out_is_eret : req_bits_out_1_is_eret; // @[Decoupled.scala:51:35] req_bits_is_sys_pc2epc <= _T ? req_bits_out_is_sys_pc2epc : req_bits_out_1_is_sys_pc2epc; // @[Decoupled.scala:51:35] req_bits_is_rocc <= _T ? req_bits_out_is_rocc : req_bits_out_1_is_rocc; // @[Decoupled.scala:51:35] req_bits_is_mov <= _T ? req_bits_out_is_mov : req_bits_out_1_is_mov; // @[Decoupled.scala:51:35] req_bits_ftq_idx <= _T ? req_bits_out_ftq_idx : req_bits_out_1_ftq_idx; // @[Decoupled.scala:51:35] req_bits_edge_inst <= _T ? req_bits_out_edge_inst : req_bits_out_1_edge_inst; // @[Decoupled.scala:51:35] req_bits_pc_lob <= _T ? req_bits_out_pc_lob : req_bits_out_1_pc_lob; // @[Decoupled.scala:51:35] req_bits_taken <= _T ? req_bits_out_taken : req_bits_out_1_taken; // @[Decoupled.scala:51:35] req_bits_imm_rename <= _T ? req_bits_out_imm_rename : req_bits_out_1_imm_rename; // @[Decoupled.scala:51:35] req_bits_imm_sel <= _T ? req_bits_out_imm_sel : req_bits_out_1_imm_sel; // @[Decoupled.scala:51:35] req_bits_pimm <= _T ? req_bits_out_pimm : req_bits_out_1_pimm; // @[Decoupled.scala:51:35] req_bits_imm_packed <= _T ? req_bits_out_imm_packed : req_bits_out_1_imm_packed; // @[Decoupled.scala:51:35] req_bits_op1_sel <= _T ? req_bits_out_op1_sel : req_bits_out_1_op1_sel; // @[Decoupled.scala:51:35] req_bits_op2_sel <= _T ? req_bits_out_op2_sel : req_bits_out_1_op2_sel; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_ldst <= _T ? req_bits_out_fp_ctrl_ldst : req_bits_out_1_fp_ctrl_ldst; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_wen <= _T ? req_bits_out_fp_ctrl_wen : req_bits_out_1_fp_ctrl_wen; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_ren1 <= _T ? req_bits_out_fp_ctrl_ren1 : req_bits_out_1_fp_ctrl_ren1; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_ren2 <= _T ? req_bits_out_fp_ctrl_ren2 : req_bits_out_1_fp_ctrl_ren2; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_ren3 <= _T ? req_bits_out_fp_ctrl_ren3 : req_bits_out_1_fp_ctrl_ren3; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_swap12 <= _T ? req_bits_out_fp_ctrl_swap12 : req_bits_out_1_fp_ctrl_swap12; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_swap23 <= _T ? req_bits_out_fp_ctrl_swap23 : req_bits_out_1_fp_ctrl_swap23; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_typeTagIn <= _T ? req_bits_out_fp_ctrl_typeTagIn : req_bits_out_1_fp_ctrl_typeTagIn; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_typeTagOut <= _T ? req_bits_out_fp_ctrl_typeTagOut : req_bits_out_1_fp_ctrl_typeTagOut; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_fromint <= _T ? req_bits_out_fp_ctrl_fromint : req_bits_out_1_fp_ctrl_fromint; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_toint <= _T ? req_bits_out_fp_ctrl_toint : req_bits_out_1_fp_ctrl_toint; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_fastpipe <= _T ? req_bits_out_fp_ctrl_fastpipe : req_bits_out_1_fp_ctrl_fastpipe; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_fma <= _T ? req_bits_out_fp_ctrl_fma : req_bits_out_1_fp_ctrl_fma; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_div <= _T ? req_bits_out_fp_ctrl_div : req_bits_out_1_fp_ctrl_div; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_sqrt <= _T ? req_bits_out_fp_ctrl_sqrt : req_bits_out_1_fp_ctrl_sqrt; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_wflags <= _T ? req_bits_out_fp_ctrl_wflags : req_bits_out_1_fp_ctrl_wflags; // @[Decoupled.scala:51:35] req_bits_fp_ctrl_vec <= _T ? req_bits_out_fp_ctrl_vec : req_bits_out_1_fp_ctrl_vec; // @[Decoupled.scala:51:35] req_bits_rob_idx <= _T ? req_bits_out_rob_idx : req_bits_out_1_rob_idx; // @[Decoupled.scala:51:35] req_bits_ldq_idx <= _T ? req_bits_out_ldq_idx : req_bits_out_1_ldq_idx; // @[Decoupled.scala:51:35] req_bits_stq_idx <= _T ? req_bits_out_stq_idx : req_bits_out_1_stq_idx; // @[Decoupled.scala:51:35] req_bits_rxq_idx <= _T ? req_bits_out_rxq_idx : req_bits_out_1_rxq_idx; // @[Decoupled.scala:51:35] req_bits_pdst <= _T ? req_bits_out_pdst : req_bits_out_1_pdst; // @[Decoupled.scala:51:35] req_bits_prs1 <= _T ? req_bits_out_prs1 : req_bits_out_1_prs1; // @[Decoupled.scala:51:35] req_bits_prs2 <= _T ? req_bits_out_prs2 : req_bits_out_1_prs2; // @[Decoupled.scala:51:35] req_bits_prs3 <= _T ? req_bits_out_prs3 : req_bits_out_1_prs3; // @[Decoupled.scala:51:35] req_bits_ppred <= _T ? req_bits_out_ppred : req_bits_out_1_ppred; // @[Decoupled.scala:51:35] req_bits_prs1_busy <= _T ? req_bits_out_prs1_busy : req_bits_out_1_prs1_busy; // @[Decoupled.scala:51:35] req_bits_prs2_busy <= _T ? req_bits_out_prs2_busy : req_bits_out_1_prs2_busy; // @[Decoupled.scala:51:35] req_bits_prs3_busy <= _T ? req_bits_out_prs3_busy : req_bits_out_1_prs3_busy; // @[Decoupled.scala:51:35] req_bits_ppred_busy <= _T ? req_bits_out_ppred_busy : req_bits_out_1_ppred_busy; // @[Decoupled.scala:51:35] req_bits_stale_pdst <= _T ? req_bits_out_stale_pdst : req_bits_out_1_stale_pdst; // @[Decoupled.scala:51:35] req_bits_exception <= _T ? req_bits_out_exception : req_bits_out_1_exception; // @[Decoupled.scala:51:35] req_bits_exc_cause <= _T ? req_bits_out_exc_cause : req_bits_out_1_exc_cause; // @[Decoupled.scala:51:35] req_bits_mem_cmd <= _T ? req_bits_out_mem_cmd : req_bits_out_1_mem_cmd; // @[Decoupled.scala:51:35] req_bits_mem_size <= _T ? req_bits_out_mem_size : req_bits_out_1_mem_size; // @[Decoupled.scala:51:35] req_bits_mem_signed <= _T ? req_bits_out_mem_signed : req_bits_out_1_mem_signed; // @[Decoupled.scala:51:35] req_bits_uses_ldq <= _T ? req_bits_out_uses_ldq : req_bits_out_1_uses_ldq; // @[Decoupled.scala:51:35] req_bits_uses_stq <= _T ? req_bits_out_uses_stq : req_bits_out_1_uses_stq; // @[Decoupled.scala:51:35] req_bits_is_unique <= _T ? req_bits_out_is_unique : req_bits_out_1_is_unique; // @[Decoupled.scala:51:35] req_bits_flush_on_commit <= _T ? req_bits_out_flush_on_commit : req_bits_out_1_flush_on_commit; // @[Decoupled.scala:51:35] req_bits_csr_cmd <= _T ? req_bits_out_csr_cmd : req_bits_out_1_csr_cmd; // @[Decoupled.scala:51:35] req_bits_ldst_is_rs1 <= _T ? req_bits_out_ldst_is_rs1 : req_bits_out_1_ldst_is_rs1; // @[Decoupled.scala:51:35] req_bits_ldst <= _T ? req_bits_out_ldst : req_bits_out_1_ldst; // @[Decoupled.scala:51:35] req_bits_lrs1 <= _T ? req_bits_out_lrs1 : req_bits_out_1_lrs1; // @[Decoupled.scala:51:35] req_bits_lrs2 <= _T ? req_bits_out_lrs2 : req_bits_out_1_lrs2; // @[Decoupled.scala:51:35] req_bits_lrs3 <= _T ? req_bits_out_lrs3 : req_bits_out_1_lrs3; // @[Decoupled.scala:51:35] req_bits_dst_rtype <= _T ? req_bits_out_dst_rtype : req_bits_out_1_dst_rtype; // @[Decoupled.scala:51:35] req_bits_lrs1_rtype <= _T ? req_bits_out_lrs1_rtype : req_bits_out_1_lrs1_rtype; // @[Decoupled.scala:51:35] req_bits_lrs2_rtype <= _T ? req_bits_out_lrs2_rtype : req_bits_out_1_lrs2_rtype; // @[Decoupled.scala:51:35] req_bits_frs3_en <= _T ? req_bits_out_frs3_en : req_bits_out_1_frs3_en; // @[Decoupled.scala:51:35] req_bits_fcn_dw <= _T ? req_bits_out_fcn_dw : req_bits_out_1_fcn_dw; // @[Decoupled.scala:51:35] req_bits_fcn_op <= _T ? req_bits_out_fcn_op : req_bits_out_1_fcn_op; // @[Decoupled.scala:51:35] req_bits_fp_val <= _T ? req_bits_out_fp_val : req_bits_out_1_fp_val; // @[Decoupled.scala:51:35] req_bits_fp_rm <= _T ? req_bits_out_fp_rm : req_bits_out_1_fp_rm; // @[Decoupled.scala:51:35] req_bits_fp_typ <= _T ? req_bits_out_fp_typ : req_bits_out_1_fp_typ; // @[Decoupled.scala:51:35] req_bits_xcpt_pf_if <= _T ? req_bits_out_xcpt_pf_if : req_bits_out_1_xcpt_pf_if; // @[Decoupled.scala:51:35] req_bits_xcpt_ae_if <= _T ? req_bits_out_xcpt_ae_if : req_bits_out_1_xcpt_ae_if; // @[Decoupled.scala:51:35] req_bits_xcpt_ma_if <= _T ? req_bits_out_xcpt_ma_if : req_bits_out_1_xcpt_ma_if; // @[Decoupled.scala:51:35] req_bits_bp_debug_if <= _T ? req_bits_out_bp_debug_if : req_bits_out_1_bp_debug_if; // @[Decoupled.scala:51:35] req_bits_bp_xcpt_if <= _T ? req_bits_out_bp_xcpt_if : req_bits_out_1_bp_xcpt_if; // @[Decoupled.scala:51:35] req_bits_debug_fsrc <= _T ? req_bits_out_debug_fsrc : req_bits_out_1_debug_fsrc; // @[Decoupled.scala:51:35] req_bits_debug_tsrc <= _T ? req_bits_out_debug_tsrc : req_bits_out_1_debug_tsrc; // @[Decoupled.scala:51:35] always @(posedge) MulDiv div ( // @[functional-unit.scala:399:19] .clock (clock), .reset (reset), .io_req_ready (_div_io_req_ready), .io_req_valid (_div_io_req_valid_T_4), // @[functional-unit.scala:415:39] .io_req_bits_fn (io_req_bits_uop_fcn_op_0), // @[functional-unit.scala:393:7] .io_req_bits_dw (io_req_bits_uop_fcn_dw_0), // @[functional-unit.scala:393:7] .io_req_bits_in1 (io_req_bits_rs1_data_0), // @[functional-unit.scala:393:7] .io_req_bits_in2 (io_req_bits_rs2_data_0), // @[functional-unit.scala:393:7] .io_kill (_div_io_kill_T_3), // @[functional-unit.scala:424:37] .io_resp_ready (io_resp_ready_0), // @[functional-unit.scala:393:7] .io_resp_valid (_div_io_resp_valid), .io_resp_bits_data (io_resp_bits_data_0) ); // @[functional-unit.scala:399:19] assign io_req_ready = io_req_ready_0; // @[functional-unit.scala:393:7] assign io_resp_valid = io_resp_valid_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_inst = io_resp_bits_uop_inst_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_debug_inst = io_resp_bits_uop_debug_inst_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_is_rvc = io_resp_bits_uop_is_rvc_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_debug_pc = io_resp_bits_uop_debug_pc_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iq_type_0 = io_resp_bits_uop_iq_type_0_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iq_type_1 = io_resp_bits_uop_iq_type_1_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iq_type_2 = io_resp_bits_uop_iq_type_2_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iq_type_3 = io_resp_bits_uop_iq_type_3_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fu_code_0 = io_resp_bits_uop_fu_code_0_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fu_code_1 = io_resp_bits_uop_fu_code_1_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fu_code_2 = io_resp_bits_uop_fu_code_2_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fu_code_3 = io_resp_bits_uop_fu_code_3_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fu_code_4 = io_resp_bits_uop_fu_code_4_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fu_code_5 = io_resp_bits_uop_fu_code_5_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fu_code_6 = io_resp_bits_uop_fu_code_6_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fu_code_7 = io_resp_bits_uop_fu_code_7_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fu_code_8 = io_resp_bits_uop_fu_code_8_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fu_code_9 = io_resp_bits_uop_fu_code_9_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iw_issued = io_resp_bits_uop_iw_issued_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iw_issued_partial_agen = io_resp_bits_uop_iw_issued_partial_agen_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iw_issued_partial_dgen = io_resp_bits_uop_iw_issued_partial_dgen_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iw_p1_speculative_child = io_resp_bits_uop_iw_p1_speculative_child_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iw_p2_speculative_child = io_resp_bits_uop_iw_p2_speculative_child_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iw_p1_bypass_hint = io_resp_bits_uop_iw_p1_bypass_hint_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iw_p2_bypass_hint = io_resp_bits_uop_iw_p2_bypass_hint_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_iw_p3_bypass_hint = io_resp_bits_uop_iw_p3_bypass_hint_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_dis_col_sel = io_resp_bits_uop_dis_col_sel_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_br_mask = io_resp_bits_uop_br_mask_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_br_tag = io_resp_bits_uop_br_tag_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_br_type = io_resp_bits_uop_br_type_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_is_sfb = io_resp_bits_uop_is_sfb_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_is_fence = io_resp_bits_uop_is_fence_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_is_fencei = io_resp_bits_uop_is_fencei_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_is_sfence = io_resp_bits_uop_is_sfence_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_is_amo = io_resp_bits_uop_is_amo_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_is_eret = io_resp_bits_uop_is_eret_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_is_sys_pc2epc = io_resp_bits_uop_is_sys_pc2epc_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_is_rocc = io_resp_bits_uop_is_rocc_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_is_mov = io_resp_bits_uop_is_mov_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_ftq_idx = io_resp_bits_uop_ftq_idx_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_edge_inst = io_resp_bits_uop_edge_inst_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_pc_lob = io_resp_bits_uop_pc_lob_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_taken = io_resp_bits_uop_taken_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_imm_rename = io_resp_bits_uop_imm_rename_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_imm_sel = io_resp_bits_uop_imm_sel_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_pimm = io_resp_bits_uop_pimm_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_imm_packed = io_resp_bits_uop_imm_packed_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_op1_sel = io_resp_bits_uop_op1_sel_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_op2_sel = io_resp_bits_uop_op2_sel_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_ldst = io_resp_bits_uop_fp_ctrl_ldst_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_wen = io_resp_bits_uop_fp_ctrl_wen_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_ren1 = io_resp_bits_uop_fp_ctrl_ren1_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_ren2 = io_resp_bits_uop_fp_ctrl_ren2_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_ren3 = io_resp_bits_uop_fp_ctrl_ren3_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_swap12 = io_resp_bits_uop_fp_ctrl_swap12_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_swap23 = io_resp_bits_uop_fp_ctrl_swap23_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_typeTagIn = io_resp_bits_uop_fp_ctrl_typeTagIn_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_typeTagOut = io_resp_bits_uop_fp_ctrl_typeTagOut_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_fromint = io_resp_bits_uop_fp_ctrl_fromint_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_toint = io_resp_bits_uop_fp_ctrl_toint_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_fastpipe = io_resp_bits_uop_fp_ctrl_fastpipe_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_fma = io_resp_bits_uop_fp_ctrl_fma_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_div = io_resp_bits_uop_fp_ctrl_div_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_sqrt = io_resp_bits_uop_fp_ctrl_sqrt_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_wflags = io_resp_bits_uop_fp_ctrl_wflags_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_ctrl_vec = io_resp_bits_uop_fp_ctrl_vec_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_rob_idx = io_resp_bits_uop_rob_idx_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_ldq_idx = io_resp_bits_uop_ldq_idx_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_stq_idx = io_resp_bits_uop_stq_idx_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_rxq_idx = io_resp_bits_uop_rxq_idx_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_pdst = io_resp_bits_uop_pdst_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_prs1 = io_resp_bits_uop_prs1_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_prs2 = io_resp_bits_uop_prs2_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_prs3 = io_resp_bits_uop_prs3_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_ppred = io_resp_bits_uop_ppred_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_prs1_busy = io_resp_bits_uop_prs1_busy_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_prs2_busy = io_resp_bits_uop_prs2_busy_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_prs3_busy = io_resp_bits_uop_prs3_busy_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_ppred_busy = io_resp_bits_uop_ppred_busy_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_stale_pdst = io_resp_bits_uop_stale_pdst_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_exception = io_resp_bits_uop_exception_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_exc_cause = io_resp_bits_uop_exc_cause_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_mem_cmd = io_resp_bits_uop_mem_cmd_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_mem_size = io_resp_bits_uop_mem_size_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_mem_signed = io_resp_bits_uop_mem_signed_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_uses_ldq = io_resp_bits_uop_uses_ldq_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_uses_stq = io_resp_bits_uop_uses_stq_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_is_unique = io_resp_bits_uop_is_unique_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_flush_on_commit = io_resp_bits_uop_flush_on_commit_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_csr_cmd = io_resp_bits_uop_csr_cmd_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_ldst_is_rs1 = io_resp_bits_uop_ldst_is_rs1_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_ldst = io_resp_bits_uop_ldst_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_lrs1 = io_resp_bits_uop_lrs1_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_lrs2 = io_resp_bits_uop_lrs2_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_lrs3 = io_resp_bits_uop_lrs3_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_dst_rtype = io_resp_bits_uop_dst_rtype_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_lrs1_rtype = io_resp_bits_uop_lrs1_rtype_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_lrs2_rtype = io_resp_bits_uop_lrs2_rtype_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_frs3_en = io_resp_bits_uop_frs3_en_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fcn_dw = io_resp_bits_uop_fcn_dw_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fcn_op = io_resp_bits_uop_fcn_op_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_val = io_resp_bits_uop_fp_val_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_rm = io_resp_bits_uop_fp_rm_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_fp_typ = io_resp_bits_uop_fp_typ_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_xcpt_pf_if = io_resp_bits_uop_xcpt_pf_if_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_xcpt_ae_if = io_resp_bits_uop_xcpt_ae_if_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_xcpt_ma_if = io_resp_bits_uop_xcpt_ma_if_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_bp_debug_if = io_resp_bits_uop_bp_debug_if_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_bp_xcpt_if = io_resp_bits_uop_bp_xcpt_if_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_debug_fsrc = io_resp_bits_uop_debug_fsrc_0; // @[functional-unit.scala:393:7] assign io_resp_bits_uop_debug_tsrc = io_resp_bits_uop_debug_tsrc_0; // @[functional-unit.scala:393:7] assign io_resp_bits_data = io_resp_bits_data_0; // @[functional-unit.scala:393:7] endmodule